A global positioning system receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the products therefrom for generating the total summation value. Therefore, the correlating circuit having portable process is formed. Moreover, an external memory is used to store the sample digital data for reducing costs.

1. Field of the Invention
The present invention relates to a communication apparatus, and more particularly to a Global Positioning System (GPS) receiver and a correlating circuit thereof.
2. Description of the Related Art
Because of advance of technology, electronic devices have been widely used in the daily life of human. As to a global positioning system (GPS) receiver, it becomes more and more available and is used. For example, the navigation system installed in cars can help the drivers identify the location and direction thereof and avoid the lost.
FIG. 1 is a schematic drawing of a signal frame transmitted from a satellite. The A serial represents that the satellite transmits a frame for each 30 seconds which includes 5 sub-frames and each sub-frame with 6 seconds. The B serial represents that the frame data includes the 50 bits/sec navigation data. It means that the transmission time for each bit of the navigation data is 20 ms. Prior to transmission the navigation data and the C/A code for identifying the satellite of the C serial are performed exclusive or logic operation for generating the D serial data. The frequency of the C/A code is 1.023 MHz which transmits 1023 bits C/A code by per ms. The length of the C/A code is 1023 bits. During the transmission the data are carried by a 1575.42 MHz carrying wave for performing bi-phase shift key (BPSK) by the output from the operation of the navigation data and the C/A code as shown E serial. The modulated signals are then transmitted.
For a GPS receiver, a RF front end serves receiving the modulated signals for the sampled digital data, and a correlating circuit serves searching the C/A code for identifying the satellite whose data can be received. To date, 24 satellites are evenly distributed on six orbits. Generally, three or four satellites are sufficient to identify the location. The more the satellites are, the more precise the location is. In addition, because of the Doppler effect, the correlating circuit refers to a corrected frequency code when searching the C/A code. If the sampled digital data received by the correlating circuit is IF data (Please provide the full spelling for IF), and the C/A code for searching the satellite is Code, and the corrected frequency code is Doppler, the correlating circuit can find out the maximum for identifying the C/A code offset and Doppler corrected frequency of the satellite whose data can be received by the following formula:
                              ∑          0          Nms                                                                    IF          *          Doppler          *          Code                                    (        1        )
The "*" represents a multiplication operation, such as exclusive or logic operation, or a multiplication of a single bit. "N ms" means the period of time of receiving the data, which is adjustable. When the period of time increases, the S/N ratio also increases which means search result is slightly affected by the noise. Following is a C/A code searching example, wherein the length of the C/A code is 10237 bits. (Generally, the length of the C/A code is 1023 bits.)
Referring to FIG. 2, it is a schematic drawing of a circuit generating the 7-bit C/A code. The circuit comprises a 3-bit shift register 210 and a multiplier 220. The input of the multiplier 220 is a two-bit output of the shift register 210; the output of the multiplier 220 is inputted into the shift register 210 responding to the output of the two bits. Therefore, the circuit, therefore, generates a 7-bit cycle C/A code, i.e. 1110010.
In order to search the 7-bit C/A code and determine the offset of the IF data, the correlating circuit of the GPS receiver uses the 7-bit C/A code, i.e., 1110010, and the other codes with different offset, such as 0111001, 1011100, 0101110, 0010111, 1001011, 1100101, etc, to perform multiplication and summation with the IF data. The multiplication is, for example, the exclusive or logic operation shown in formula (1). If the C/A code has two-bit offset, the codes with different offset are, for example, 1110010, 0101110, 1011100, 0101110, 1001011, 1100101, etc. After the exclusive or logic operation and the summation operation, only "1011100" has a value "0"; the others have a value "4". If "4" is deemed as the zero point of the coordinate, "0" becomes "−4" in the coordinate. After the square and radical operation, it generates the maximum "4" which can be detected by a peak detector.
Referring to FIG. 3, it is a waveform illustrating a searching result of a correlating circuit. In addition to the offset of the C/A code, the correlating circuit also searches the corresponding Doppler corrected frequency. A corresponding C/A code offset with peak value and Doppler corrected frequency are acquired for tracking satellite in order to obtain navigation data with correct offset of the C/A code and the Doppler corrected frequency.
FIG. 4 is a schematic block diagram of a prior art correlating circuit. The correlating circuit includes a C/A code register 405, a Doppler corrected frequency code register 410, an I memory 415, a Q memory 420, a Doppler multiplier 425, a C/A code multiplier 430, an I analog adder 435, a Q analog adder 440, an I A/D converter 445, a Q A/D converter 450, a square and radical calculator 455, an integrator 460 and a peak detector 465.
The C/A code register 405 serves storing the C/A codes to be searched. The Doppler corrected frequency code register 410 serves storing the Doppler corrected frequency code to be searched. The I memory 415 stores the IF data received by the RF front end. The Q memory 420 stores the IF data with 90° phase shift. The I memory 415 and the Q memory 420 can store the IF data for about 20 ms for the multiplication of formula (1). The data are going to be processed by the Doppler multiplier 425 and the C/A code multiplier 430 for generating the product of each bit. After the process of the I analog adder 435 and the Q analog adder 440, the summation of the product of each bit is acquired. After the process of the I A/D converter 445 and the Q A/D converter 450, the digital data are acquired.
Then, after the process of the square and radical calculator 445, the absolute values of the digital data are generated. By the integration of the integrator 460, the value is then stored in the non-coherent memory 470. It can reduce the noise influence. The longer the integration time is, the higher the S/N ratio is. It means the noise influence is reduced. The integrated value can be detected by the peak detector 465 for acquiring correct offset of the C/A code and the Doppler corrected frequency.
The prior art correlating circuits are disclosed in U.S. Pat. Nos. 5,896,304 and 6,009,118, which have following disadvantages:                1. The correlating circuit uses analog adders for generating the summation of the product of each bit and the total summation of the product of the 1023-bit C/A code. When the process is changed, the A/D converters should be redesigned. Therefore, the process portability is degraded.        2. A large internal memory for storing the 20-ms IF memory is required. It will cause the rise of cost.
Additionally, although the correlating circuit disclosed in U.S. Pat. No. 6,383,046 improved process portability, C/A code bits are still serially converted followed by processed in parallel, and there is not a buffer working as a sampled data register, thus the operation is not substantially parallel.

Global positioning system receiver and correlating circuit thereof


A multi-master node model database management technology involves notifying a higher-level master node of a transaction minimum value as a minimum value of an implementation-underway transaction in a snapshot from a lower-level master node, comparing the transaction minimum value with minimum values retained by the respective master nodes and thus updating a node minimum value and a cluster minimum value. Then, the lower-level master node transmits a write set containing a shadow copy of its own database, a heap tuple map deployed on its own memory and the transaction minimum value to the higher-level master node, and the higher-level master node receiving the write set updates the database by use of the write set if the transaction minimum value is equal to or larger than the cluster minimum value, and aborts the write set if the transaction minimum value is smaller than the cluster minimum value.

In even a recordable database such as PostgreSQL, it is desirable to completely erase (VACUUM) a tuple (row) with an elapse of a predetermined period of time after deleting the tuple in order to effectively utilize resources.
A transaction is, however, managed with a single snapshot from a start (BEGIN) to an end (COMMIT or ROLLBACK) of implementation, and hence, even when a specified tuple is deleted during a certain transaction, this does not necessarily mean that none of the reference to this tuple is promptly made from within all the transactions. Therefore, a principle is that the tuple is not completely erased unless a series of transactions during which to make reference to the tuple are all committed (COMMIT). Even if the tuple is deleted, it is to be contrived that the reference to this tuple can be made on other implementation-underway snapshots at that point of time.
PostgreSQL therefore adopts a mechanism for determining where is delimited for the complete deletion (VACUUM) while referring to transaction IDs of the transactions that have already been committed as viewed from the snapshots of the respective transactions by use of the transaction ID attached to each transaction. Namely, it is because of an operation of calculating respective minimum values in the transaction IDs of the transactions deemed to be the implementation-underway transactions in the snapshots of the respective transactions and performing the complete deletion in accordance with the transaction ID having the smallest of the minimum values.
[Patent document 1] Japanese Patent Application Laid-Open Publication No. 2006-293910


A process for preparing high purity indane bisphenols in high yield is disclosed. The method comprises heating a bisphenol in the presence of Montmorillonite K10 clay, which catalyzes the synthesis reaction more rapidly and effectively than other clays previously disclosed. The high purity (.gtoreq.97%) of the synthesized indane bisphenol is obtained by two successive selective recrystallizations, the first from an organic solvent, and the second from an acetic acid solution. The high purity indane bisphenols produced may be made substantially pure (>99%) by employing a purification process which includes at least one selective recrystallization from a 45%-80% by volume aqueous acetic acid solution. Alternatively, substantially pure indane bisphenol may be obtained by recrystallization from a solution of 89-93% by volume toluene and 7-11% by volume n-propanol, or by a combination of recrystallizations from toluene/n-propanol and from aqueous acetic acid. Substantially pure indane bisphenols, such as 5-hydroxy-3-(4-hydroxyphenyl)-1,1,3-trimethylindane, are suitable for conversion to high molecular weight polymers.

Indane bisphenols of formula (I) below and methods for their preparation have been known for some time. Such compounds are useful in the synthesis of many polymers. For example, high molecular weight homo- and copolycarbonates comprising substituted and unsubstituted indane bisphenol monomers are disclosed and claimed in commonly owned U.S. Pat. No. 5,703,197 and copending and commonly owned application Ser. No. 08/947,980 filed Oct. 9, 1997. Such indane polycarbonates are shown to possess unique and advantageous properties. In addition, U.S. Pat. No. 3,634,089 to Hamb discloses the preparation of high molecular weight indane polyesters. Patel et al. describe poly(arylindane)ethers in U.S. Pat. No. 5,145,926, and Paul et al. disclose in U.S. Pat. No. 4,988.785 bismaleimide resins based on indane bisphenols.
Indane bisphenols, as described herein, are represented by the structural formula ##STR1## wherein each R.sup.1 is independently hydrogen, deuterium, halogen, alkyl having 1 to 4 carbons, alkoxy having 1 to 4 carbons, or a deuterated equivalent thereof; each R.sup.2 is an alkyl group having 1 to 4 carbons or a deuterated equivalent thereof; R.sup.3 is hydrogen or deuterium when R.sup.2 is methyl or its deuterated equivalent; otherwise R.sup.3 is an alkyl group or a deuterated equivalent thereof having one less carbon than that of R.sup.2. As used herein, "alkyl" refers to linear or branched saturated hydrocarbon residues containing 1 to 4 carbons. "Alkoxy" refers to the same residues containing, in addition, an oxygen atom at the point of attachment. "Deuterated equivalents thereof", as used herein, refers to the hydrocarbon moieties listed above for R.sup.1, R.sup.2, and R.sup.3 in which at least one hydrogen is replaced with the deuterium isotope. For example, a deuterated methyl group may be CDH.sub.2, CD.sub.2 H, or CD.sub.3, and a deuterated ethyl may be CH.sub.3 CD.sub.2.
The preparation of indane bisphenols of formula (I), also known as hydroxyphenyl indanols, is disclosed in U.S. Pat. No. 2,754,285 to Petropoulos and U.S. Pat. No. 2,819,249 to Petropoulos et al. via an acid-catalyzed dimerization of a-methyl styrene to form indanes, followed by sulfonation of the indanes, and heating the sulfonated product with potassium hydroxide to yield 5-hydroxy-3-(4-hydroxyphenyl)-1,1,3-trimethylindane, wherein each R.sup.1 and R.sup.3 is hydrogen, and R.sup.2 is methyl in structure (I) above. 5-Hydroxy-3-(4-hydroxyphenyl)-1,1,3-trimethylindane is also referred to herein as "IBP".
U.S. Pat. No. 3,288,864 to Farnham discloses a method of IBP production which comprises treating iso-propenylphenol (IPP) with a Friedel-Crafts catalyst at elevated temperatures. U.S. Pat. No. 4,334,106 to Dai discloses somewhat milder reaction conditions in treating IPP or a mixture of its linear oligomers with a stoichiometric excess of organic acid. U.S. Pat. No. 4,791,234 to Faler et al. describes that a decrease in the amount of organic acid used to catalyze the rearrangement of bisphenol A (also referred to herein as "BPA") to form 6,6'-dihydroxy-3,3,3',3'-tetramethyl-1,1'-spirobiindane (hereinafter, "SBI") leads to the formation of IBP in concentrations of up to 50% in the reaction mixture.
The reaction conditions were further simplified in Japanese Application No. 05294879 which describes a method of producing IBP by treating BPA with an activated clay prepared by Nippon Kassei Hakudo Co. (K-500) at temperatures between 100.degree.-180.degree. C. However, this method requires a lengthy 3-5 hour reaction time. At the completion of the reaction, IBP is precipitated from toluene yielding crystals having a purity between 57% and 78%. Further purification is possible via recrystallization from an aromatic solvent such as toluene, to obtain IBP having a maximum purity of 96% in a 28% yield.
The present invention provides a method for increasing indane bisphenol purity and yield. High purity indane bisphenols (at least 97% pure) previously unreported and in higher yields (34% theoretical) may now be prepared using the present method. In addition, under certain experimental conditions, the present invention allows the reaction time to be significantly cut to as low as 15 minutes. Using a novel set of mild isolation and purification procedures disclosed herein, substantially pure indane bisphenols having a purity of >99% may also be prepared with the present method. These substantially pure materials can then be converted to high molecular weight indane polymers as set forth in the references above.

Method for preparing high purity indane bisphenols


A method for representing arithmetic values on which arithmetic operations can be performed uses operands having a fixed number of bits. In a first step, a plurality of operands are stored in a memory, wherein each operand has a bit pattern representing a particular value. In a second step, a tag associated with each of the operands is also stored in the same or a different memory. Each of the tags has a tag value that indicates whether or not its associated operand represents an ordinary operand value or a special operand value. If the operand represents a special operand value, the tag value also indicates which of a predefined set of special operand values is represented by the associated operand. A result of an arithmetic operation can be generated by, in a first step, inputting at least a first operand and a first tag to an arithmetic section. In a second step, the arithmetic section determines a value of the result of the arithmetic operation based on the special operand indicated by the first tag and independently of a value of the first operand. A tag associated with a result of an arithmetic calculation can be generated by, in a first step, generating in an arithmetic section a result of an arithmetic operation on at least one operand. If the generation of the result produces one of a predetermined set of special operands, a tag generator generates a tag having a predetermined tag value corresponding to the produced special operand. Illustratively the tag generator alternatively generates a predetermined tag value indicating that the result is not a special operand if the result is not a special operand.

FIG. 1 shows a conventional circuit 10 for performing arithmetic operations on one or more floating point operands. Illustratively, each operand has a fixed number of bits i.e., 32, 64, etc. According to standard IEEE format, a 32 bit floating point number has one sign bit, eight exponent bits and twenty three magnitude bits with an implicit bit. If the sign is s, the exponent is e and the magnitude is m, the value of the floating point operand is (-1).sup.s .cndot.m.cndot.2.sup.e-127. The magnitude m is a fractional value with its first non-zero digit aligned with the most significant bit position of the magnitude (unless, as described below, the value of the floating point operand is a special operand value). This property of the magnitude is referred to as normalization. Often, as a result of a calculation, or for purposes of performing a calculation, the first non-zero digit of the value of the magnitude is not aligned with the most significant bit of the magnitude portion of the floating point number. In such a case, the magnitude or floating point number is said to be denormalized. Such a magnitude can be normalized by shifting the decimal place of the value of the magnitude until the first non-zero bit is aligned with the most significant bit position of the magnitude portion of the floating point number and by increasing or decreasing the exponent to indicate the number of bit positions by which the magnitude value has been shifted. IEEE format also provides similar formats for higher precision floating point numbers. Other similar floating point number formats also exist. However, this invention is illustrated herein using the above 32 bit IEEE standard, without loss of generality.
One or more operands x and y are supplied from a memory device, such as a register file 12. The operands x and y are inputted to an arithmetic section 14, which includes a denormalizer and normalizer. The denormalizer equalizes the exponents of the two operands by shifting the decimal point of one operand relative to the other for an addition or subtraction arithmetic operation. The normalizer normalizes the result of the arithmetic operation, which, for example, may have been an addition, a subtraction, a multiplication, or division operation.
Certain mathematical values are not easily represented in the above-described sign, exponent, magnitude format or present difficulty in performing calculations. These mathematical values are zero, infinity and "not a number." For instance, due to constraints on fixed word-sized floating point numbers, it is impossible to represent the value infinity so that it satisfies (-1).sup.s .cndot.m.cndot.2.sup.e-127. On the other hand, although the value zero can be represented so that it satisfies (-1).sup.s .cndot.m.cndot.2.sup.e-127, the number zero can neither be normalized nor denormalized. The IEEE standard provides a single precision format as the following representations for such mathematical values:
(1) sign=`0` or `1` bit, exponent=a sequence of eight `0` bits, magnitude=a sequence of twenty-three `0` bits to indicate that the result is a zero value, PA1 (2) sign=`0` or `1` bit, exponent=a sequence of eight `0` bits, magnitude=a `0` bit followed by a sequence of twenty-two bits, including at least one non-zero bit, to indicate that the result is not a number with signalling (i.e., generation of an error exception), PA1 (3) sign=`0` or `1` bit, exponent=a sequence of eight `0` bits, magnitude=a `1` bit followed by sequence of twenty-two bits to indicate that the result is not a number with no signalling, PA1 (4) sign=`1` bit, exponent=a sequence of eight `1` bits, magnitude=a sequence of twenty-three `0` bits to indicate that the result is negative infinity, and PA1 (5) sign=`0` bit, exponent=a sequence of eight `1` bits, magnitude=a sequence of twenty-three `0` bits to indicate that the result is positive infinity. PA1 (a) The result is the zero valued special operand if: PA1 (b) The result is the infinity valued special operand if: PA1 (c) The result is not a number if:
Operands that have one of the above-noted bit patterns for representing a respective mathematical value are referred to as "special operands." A denormalized number can also be referred to as a special operand in certain ALU models. For instance, in a "fast" ALU model, a denormalized number can be treated as zero in certain operations. In addition, certain user defined values can be treated as special operands. For example, if the ALU must calculate sin n.pi. (n is an integer) frequently, the bit pattern for n.pi. can be treated as a special operand. Lastly, specific predefined constants, e.g., such as Euler's number can be provided predefined bit patterns. Such bit patterns are also special operands. All other operands are referred to as "ordinary operands."
A special operand generator circuit 22 is provided at the output of the arithmetic section 14 for determining whether or not the result of the arithmetic operation performed in the arithmetic section 14 is a special operand value, and which operand value the result equals.
These are summarized as follows:
(i) the magnitude of the result is zero, or PA2 (ii) a division operation is performed wherein the divisor is infinity and the dividend is zero or a finite number. PA2 (i) a division operation is performed wherein the dividend is infinity but the divisor is not zero, PA2 (ii) a multiplication, addition or subtraction arithmetic operation is performed wherein one operand is infinity, or a division operation is performed wherein the dividend is infinity and the divisor is an ordinary operand, or PA2 (iii) if the result is overflow. PA2 (i) any operation is performed on an operand that is not a number, or PA2 (ii) any invalid operation is performed such as the square root of a negative number, a division operation is performed wherein both the dividend and divisor are zero or the dividend is infinity and the divisor is zero, etc.
When the arithmetic section 14 performs one of the operations listed above that results in a value other than an ordinary operand value, the arithmetic unit outputs a signal indicating that the result is zero, infinity or not a number to the generator circuit 22. In response, the circuit 22 generates the appropriate output floating point number as per the above noted IEEE standard of special operands set.
Note that often the result of the arithmetic calculation can be determined without actually performing all of the ordinary steps of the arithmetic calculation when one or more of the operands is a special operand. See, e.g., MANO, COMPUTER ARCHITECTURE sec. 10-4, p. 377-387 (1982). Many of these results are noted above. In addition to these, suppose a first operand is to be added to a second operand or the first operand is to be subtracted from the second operand. If the first operand is the zero valued special operand, then the result must be equal to the second operand. Likewise, if the first operand is to be subtracted from the second operand and the second operand is the zero valued special operand, the result must have a magnitude and exponent that equal the magnitude and exponent of the first operand and a sign of opposite polarity as the second operand.
Interposed between the register file and the arithmetic section 14 are detectors 24 and 26. One detector 24 or 26 is provided for each operand input path. The detectors 24 and 26 each receive a respective operand x or y and determines whether or not the received operand represents a special operand. If not, the detector 24 or 26 simply outputs the operand x or y to the arithmetic section 14. However, if the detector 24 or 26 detects that the operand x or y represents a special operand, the detector 24 or 26 identifies the type of the operand--the detector determines which of the special operands the received operand x or y represents. The detector 24 or 26 then outputs an indication of the type of the operand to the arithmetic section 14. As a result, the arithmetic section 14 generates the appropriate result using fewer steps as would normally be necessary. For instance, two ordinary operands are added (subtracted) by normalizing the operand with the smaller exponent relative to the operand with the larger exponent, adding (subtracting) the magnitudes of the two operands, e.g., using a carry look-ahead or carry save adder, and then normalizing the result. See U.S. Pat. No. 4,758,974. Likewise, two ordinary operands are multiplied (divided) by multiplying (dividing) the magnitudes of the two ordinary operands, e.g., using a Booth multiplier, adding (subtracting) the exponents of the two operands and then normalizing the result. The detectors 24, 26 cause the arithmetic section 14 to avoid performing such steps (which would either be impossible, erroneous or simply time consuming) and instead to generate control signals (exp.sub.-- sel, mag.sub.-- sel) and/or result sign (result.sub.-- sgn), magnitude (result.sub.-- mag) and exponent (result.sub.-- exp) as per the predetermined rules set forth above.
FIG. 2 shows an exemplary special operand generator circuit 22 in greater detail. As shown, the special operand generator circuit 22 includes first and second multiplexers 222 and 224. The first multiplexer 222 has a first input receiving a sequence of eight `0` bits, a second input receiving a sequence of eight `1` bits and a third input receiving an exponent that is outputted from the arithmetic section 14. The first multiplexer 222 also receives selector control signals exp.sub.-- sel from the arithmetic section 14. The second multiplexer 224 has a first input receiving a sequence of twenty-three `0` bits, a second input receiving a sequence including a first `0` bit followed by a sequence of twenty-two bits that have at least one non-zero bit, a third input receiving a sequence including a `1` bit followed by sequence of twenty-two bits and a fourth input receiving the magnitude outputted from the arithmetic section 14. The second multiplexer 22 also receives selector control signals mag.sub.-- sel from the arithmetic section 14.
The arithmetic section 14 outputs appropriate selector control signals exp.sub.-- sel, mag.sub.-- sel to the multiplexer 222 to output a resulting exponent, and to the multiplexer 224 to output a resulting magnitude of an arithmetic operation. The sign bit result.sub.-- sgn is separately outputted from the arithmetic section 14 and appended to the exponent and magnitude outputted from the multiplexers 222 and 224. When the result of an arithmetic operation is zero, the arithmetic section outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the eight `0` bits for the exponent and twenty-three `0` bits for the magnitude. When the result of an arithmetic operation is infinity, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the eight `1` bits for the exponent and the twenty-three `0` bits for the magnitude. When the result of an arithmetic operation is not a number with signalling, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting eight `1` bits for the exponent and the `0` bit followed by twenty two bits including at least one `1` bit as the magnitude. Likewise, when the result of an arithmetic operation is not a number without signalling, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the eight `1` bits as the exponent and the `1` bit followed by twenty-two bits as the magnitude. In all other cases, the arithmetic section 14 outputs selector control signals exp.sub.-- sel and mag.sub.-- sel to the multiplexers 222 and 224 for selecting the exponent and magnitude generated in the arithmetic section 14 as the result exponent and magnitude.
FIG. 3 shows a conventional detector 24 or 26. As shown, the detector 24 or 26 includes two comparator circuits 252 and 254. The comparator 252 receives the exponent (x.sub.-- exp or y.sub.-- exp) of the inputted operand x or y and compares it to a sequence of eight `0` bits and a sequence of eight `1` bits. If the exponent is the same as the sequence of eight `0` bits, the comparator 252 outputs a logic `1` bit on the line 255. If the exponent is the same as the sequence of eight `1` bits, the comparator 252 outputs a logic `1` bit on the line 256. In all other circumstances, the comparator 252 outputs logic `0` bits on the lines 255 and 256. The comparator 254 receives the magnitude (x.sub.-- mag or y.sub.-- mag) of the inputted operand x or y and compares it to the sequence of twenty-three `0` bits. If the magnitude is the same as the sequence of twenty-three `0` bits, the comparator 254 outputs a logic `1` bit on the line 257. If not, the comparator 254 outputs a logic `1` bit on the line 258.
Three AND gates 261, 262 and 263 are also provided. The AND gate 261 receives as inputs the logic bits outputted on the lines 255 and 257. The AND gate 261 therefore outputs a signal indicating whether or not the operand represents a zero valued special operand (a logic `1` indicating that the operand represents the zero valued special operand). The AND gate 262 receives as inputs, the logic bits outputted on the lines 256 and 257. The AND gate 262 therefore outputs a signal indicating whether or not the operand represents infinity (either negative or positive) (a logic `1` indicating that the operand represents the infinity valued operand). The AND gate 263 receives as inputs the logic bits outputted on the lines 256 and 258. The AND gate 263 therefore outputs a signal indicating whether or not the operand represents a non-number special operand (with or without signalling) (a logic `1` indicating that the operand is a non-number special operand). Each of the signals outputted by the AND gates 261-263 of the detectors 24 and 26 are inputted to the arithmetic section 14. Illustratively, the arithmetic section 14 has combinatorial logic for translating these signals, and possibly the values of the operands, to the outputted exponent and magnitudes and control signals exp.sub.-- sel and mag.sub.-- sel provided to the generator circuit 22 of FIGS. 1 and 2. See, e.g., Joseph J. F. Cavanagh, Digital Computer Arithmetic Design and Implementation, p.384.
A disadvantage of the architecture shown in FIGS. 1-3 is that detectors 24 and 26 must be provided in the input path of each operand to determine whether or not the operand represents a special operand, and if so, which special operand value is represented. A detector is necessary because nearly all of the bits of the operand must be examined to determine if the operand represents a special operand value. This introduces a latency into the arithmetic processing of the calculation circuit 10.
It is an object of the invention to overcome the disadvantages of the prior art.

Floating point architecture with tagged operands

Industrial Technology Research Institute


A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.

1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) panel, and more particularly, the present invention relates to a LCD panel having improved image quality.
2. Description of the Related Art
A liquid crystal display (LCD) panel comprises a pair of opposing substrates with a liquid crystal layer therebetween. One of the substrate is a common electrode substrate having a common electrode while the other substrate is a thin film transistor (TFT) substrate having a plurality of TFTs. The common electrode substrate and the TFT substrate are assembled by a seal line disposed at the edge of both the common electrode substrate and the TFT substrate. The liquid crystal layer is disposed between the common electrode substrate and the TFT substrate.
Liquid crystal molecules of the liquid crystal layer are arranged in accordance with the electricity given to the common electrode substrate and TFT substrate respectively.
The TFT substrate has a plurality of gate lines, a plurality of data lines and a plurality of pixels. Each of the gate lines extends horizontally and transmits gate signals. On the other hand, each of the data lines extends vertically and transmits data signals. Each of the pixels may be defined by one gate line and one data line and has a switching element and a storage capacitor.
A switching element may be formed near the cross point of one gate line and one data line. The switching element is a thin film transistor (TFT) with a gate electrode connected to the gate line, source electrode connected to the data line and drain electrode connected to a pixel electrode. The drain electrode may be electrically connected to a liquid crystal capacitor and to a storage capacitor.
Not being a self-emitting display device, an LCD module has a backlight unit behind the LCD panel that provides light to the LCD panel. With light provided from the backlight unit, transmittance of the LCD panel is controlled by arrangement of the liquid crystal molecules of each pixel by selectively passing light to a display image.
With the conventional LCD module of the above structure, light is apt to leak in the gap between the data line and pixel electrode to make poor image quality. Thus, to lessen the light leakage, a black matrix is generally adapted on the common electrode substrate. Specifically, the black matrix is located where the leaked light passes. However, the black matrix may result in a smaller aperture ratio of the overall LCD module to decrease the luminance of the display resulting in poor image quality.
Also, with the conventional LCD module, data signals and pixel electrodes may influence each other. Namely, charge coupling between the data line and pixel electrode can occur causing irregular vertical crosstalk along the data line.

This patent is subject to a terminal disclaimer.

Liquid crystal display panel having a light blocking electrode


A device for regulating fluid flow in an intravenous line comprises a housing and a flow path system in the housing for defining a plurality of separate flow paths having respective predetermined characteristic flow rates. The housing has an input port connectable to an intravenous line segment extending from an intravenous fluid supply and also has an output port connectable to an intravenous line segment extending to a catheter. The device additionally comprises a selector mounted to the housing and in contact with the flow path system for selectively opening the flow paths to connect the output port to the input port, thereby controlling the amount of fluid or solution flowing through the output intravenous line to a patient.

This invention relates to an intravenous fluid supply system. More particularly, this invention relates to a device for regulating the rate of fluid flow through an intravenous line into a patient. This invention also relates to an associated method for controlling the rate of intravenous feeding.
It is important that intravenous solutions are fed to patients at prescribed rates. A rate that is too high or too low can mean disaster to many patients, delicate conditions.
Generally, the rate of intravenous fluid flow is set by constricting a flexible tube extending from an elevated intravenous solution bag to a catheter in the patient. More specifically, the constriction is accomplished by pushing a valve member to pinch the flexible intravenous tube between the valve member and a tapered ramp extending through a housing. To set a desired rate, one views a drip chamber upstream of the valve member. The valve is adjusted until a prescribed number of drips per time unit is counted at the drip chamber.
This conventional rate setting method is inaccurate and prone to error. Nurses frequently do not have the opportunity to accurately monitor the flow rate prior to a final selection.

Intravenous flow regulator device and associated method


A formulation for stabilizing enzymatic activity and immunoreactivity of creatine kinase and creatine kinase isoenzymes comprising animal serum, creatine kinase and/or creatine kinase isoenzymes, an effective amount of a buffer having a pKa in the range of 6.2-7.6 to maintain pH of the formulation at 6.7.+-.0.1, an effective amount of a non-thiol antioxidant to prevent oxidation of creatine kinase or creatine kinase isoenzyme thiol groups, an effective amount of a non-reducing polyol to stabilize immunoreactivity of creatine kinase or creatine kinase isoenzymes, and an effective amount of an antimicrobial to prevent microbial growth is provided.

The determination of creatine kinase (CK) or CK isoenzyme levels in human serum is important in diagnosing a number of physiological conditions. An increased level of CK can be indicative of myocardial infarction, myocardial ischemia, stenocardia, tachycardia, myocarditis, subarachnoid hemorrage, stroke, brain tumor, meningitis and encephalitis, among other conditions.
Three predominant isoenzymes of CK are recognized; these are dimers consisting of the M and B sub-units. The predominant dimer present in the blood, serum or plasma of normal individuals is CK-MM isoenzyme, with variable but usually trace quantities of CK-MB that indicate the normal degradation of skeletal muscle. The CK-BB isoenzyme is not usually present in detectable amounts in serum of normal individuals but is present in significant quantities in brain tissue and smooth muscle tissue.
Elevations of the CK-BB isoenzyme can occur in physiological conditions such as metastatic carcinoma or severe burns. Elevated levels of CK-MB isoenzyme have been used as an indicator of myocardial infarction where possible sources of significant skeletal muscle damage can be eliminated. More particularly, repetitive determinations of CK-MB levels in serum can indicate the time course and severity of infarctions.
More recently, the isoforms of CK isoenzymes have received attention as potential markers for early diagnosis of myocardial infarction. There are three isoforms of CK-MM isoenzyme; CK-MM1, CK-MM2 and CK-MM3; and two isoforms of CK-MB isoenzyme; CK-MB1 and CK-MB2. Shortly after myocardial infarction, the ratio of CK-MM and CK-MB isoforms contained in tissue to that contained in plasma increases. Such increase occurs several hours before either total CK or CK-MB activity exceeds normal reference values.
A number of diagnostic assays have been developed for the determination of the presence or the concentration of CK or CK isoenzymes in human serum. Many such assays are based on measurement of the enzymatic activity of the CK enzyme or isoenzyme. Difficulties in measuring the enzymatic activity of the CK-MB isoenzyme and the need for greater sensitivity have led to the development of immunochemical mass determinations for CK-MB. Such assays are highly dependent on the immunoreactivity of the CK-MB isoenzyme.
It has been observed that CK and CK isoenzymes are highly unstable. CK and CK isoenzymes are sulfhydryl-requiring, that is, they need to maintain their --SH groups in their free, unoxidized form. Atmospheric oxygen causes the oxidation of the --SH groups to the disulfide linkage, thereby diminishing enzyme stability and catalytic activity. Additionally, changes to the CK and CK isoenzyme molecules caused by increased temperatures and the presence of proteases and reducing agents can change the immunoreactivity of the molecules.
Storage stability of patient serum samples containing CK and CK isoenzymes is important, especially when further analysis on a sample is requested retrospectively following an equivocal ECG or when the cause of a raised total CK level is being sought. Such a request may be made the same day or days after the initial ECG or CK assay was performed. Buttery et al. [Clinical Biochemistry, 25: 11-13 (1992)] report that samples stored at -20.degree. C. overnight show, on average, a decrease in CK-MB isoenzyme values of 13.5%. Such a decrease could result in a misdiagnosis. Prolonged storage of samples at room temperature for 4-6 days showed a 50% deterioration of CK-MB when measured electrophoretically and 20% deterioration when measured by an immunochemical mass assay. Therefore, a need exists for a means for stabilizing CK and CK isoenzyme activity in patient serum samples.
CK and CK isoenzyme assay control products containing CK or CK isoenzyme also suffer from instability problems. In order to facilitate storage of such control products, they are typically lyophilized. A useful lyophilized CK or CK isoenzyme control product must have two characteristics which are often very difficult to achieve simultaneously. First, there must be substantially no or only very small temperature of hydration effect and, second, there must only be very slight changes in enzyme activity or immunoreactivity upon standing after reconstitution (rehydration) of the lyophilized control product. The temperature of hydration effect is the phenomenon of variability of recovered enzyme activity and immunoreactivity from a lyophilized control product upon rehydration caused by the differences in the temperature of water used. For practical purposes, for use in diagnostic assays, lyophilized control products must have a small temperature of hydration effect to permit reproducible analytical results.
Thiols, such as N-acetyl cysteine, glutathione and monothioglycerol, have been used as additives to lyophilized CK and CK isoenzyme control products as thiol protectors. (See U.S. Pat. No. 4,442,212, issued Apr. 10, 1984 to Briggs.) While use of such thiols in lyophilized CK and CK isoenzyme control products has been found to control the stability of CK and CK isoenzyme enzymatic activity after reconstitution, use of thiols has little effect on stability of CK and CK isoenzyme immunoreactivity.
U.S. Pat. No. 4,994,375, issued Feb. 19, 1991 to Posner et al., discloses a stable reconstituted human serum-based control for the assay of total lactate dehydrogenase (LDH) and CK and their isoenzymes which is comprised of human serum, LDH and LDH isoenzymes, CK and CK isoenzymes and sodium citrate. The pH of the control product is adjusted to 6.7 before lyophilization. In this control product formulation, there is no means disclosed for maintaining the pH of the control product at 6.7 after rehydration. Variability in pH of the control product after reformulation can lead to inconsistent results. Additionally, there is no suggestion that the disclosed control product formulation would stabilize immunoreactivity of CK or CK isoenzymes.
There is a need for a formulation for stabilizing enzymatic activity and immunoreactivity of CK and CK isoenzymes which can be used to stabilize human serum samples containing CK and CK isoenzymes and as a reconstitutable lyophilized CK and CK isoenzyme control product which exhibits little temperature of hydration effect and which is stable after reconstitution.

Formulation for stabilizing enzymatic activity and immunoreactivity of creatine kinase and creatine kinase isoenzymes


A method and corresponding device for joint signal detection and direction of arrival estimation, based on the ability to identify both the existence and direction of arrival of a required signal featuring known characteristics, before it is forwarded to a modem. Optionally, after identifying the existence and direction of arrival of a required signal, the direction of arrival is entered into a beamformer featuring high resolution, for obtaining the signal coming from the required direction of arrival. The calculated signal is then entered into a modem.

The present invention relates to signals detection used in receivers and, more particularly, to methods and corresponding devices for joint signal detection and direction of arrival estimation, based on the ability to identify both the existence and direction of arrival of a required signal featuring known characteristics, before it is forwarded to a modem. Optionally, after identifying the existence and the direction of arrival of a required signal, the direction of arrival is entered into a beamformer to obtain the signal coming from the required direction of arrival. The calculated signal is then entered into a modem.
Basic principles and details relating to joint signal detection and direction of arrival estimation needed for properly understanding the present invention are provided herein. Complete theoretical descriptions, details, explanations, examples, and applications of these and related subjects and implementations are readily available in standard references from the fields of telecommunication, signals detection and, spatial scanning.
Prior art includes various teachings of signal characteristics detection. In U.S. Pat. No. 6,347,234, issued to Scherzer, there is disclosed a method of enhancing signal quality (carrier to interference) in both up and downlink of wireless point to multi-point CDMA service implements basic radio direction finding techniques to allow for optimal diversity combining in an antenna array employing large number of elements. This prior art is implemented through the use of very small bit counts arithmetic and capitalizing on finite alphabet signal structure or a known training sequence. Alternate implementations can use floating point data representations. The method facilitates ASIC implementation, thereby enabling distributed processing to achieve the required computation practicality. The method utilizes the uplink channel data to determine the downlink spatial structure (array beams) to enhance downlink carrier to interference and hence, increase downlink capacity.
However, Scherzer is notably limited because it describes a specific CDMA implementation that can not be used for other types of signals. Additionally, the disclosed method is particularly described with respect to channel estimation featuring channel estimators, and is not obviously extendable to estimating the characteristics of the received signals.
In U.S. Pat. No. 6,489,923, issued to Bevan et al. there is disclosed a mechanical system for position location for a mobile telecommunications system by estimating its bearing and range from a cell site. A multi-element direction finding antenna at the cell site receives signals from the mobile station and a receiver circuit estimates the bearing using the relative phase of signals received at different antenna elements and estimates the range by measuring round trip delay of signals to and from the mobile station. Motion of the mobile station can introduce errors into the bearing estimate due to frequency offset and frequency spread when element sampling is non-simultaneous. Compensation for these errors is introduced by using signal samples successively received at the same antenna element to estimate Doppler frequency offset and spread. It is necessary to ensure accurate calibration of the direction finding antenna and the receiver circuit. This is done by injecting calibration signals into the circuit near the antenna or into the antenna itself from a near field probe. Other aspects of calibration, such as antenna position, are calibrated using a remote beacon. A beacon emulating a mobile station but at a fixed, known location, or a beacon at an adjacent cell site may be used.
However, Benav et al. disclose a mechanical system and cells fragmentation. There is no description or suggestion for antenna array with no moving parts. Moreover, Bevan et al. provide no description or suggestion relating to joint signal detection and direction of arrival estimation.
Other prior art solutions are analog solutions in RF. Implementation of analog systems requires putting a modem on each beam. However, this solution is highly expensive, which is why current analog solutions do not provide the novel functionality of the present invention.
To date, the inventor is unaware of prior art teaching of a digital solution for joint signal detection and direction of arrival estimation, before the signal is forwarded to a modem.
There is thus a need for, and it would be highly advantageous and useful to have a method and corresponding device for joint signal detection and direction of arrival estimation, based on the ability to identify both the existence and direction of arrival of a required signal featuring known characteristics, before it is forwarded to a modem. Moreover, there is a need for such a method, which is significantly simpler, more rapid, and therefore, more cost effective, than currently used techniques for signal detection and direction of arrival estimation.
To one of ordinary skill in the art, there is thus a need for identifying required signals using inexpensive hardware. As a result, there is a need to identify required signals without using a huge number of calculations. Using a correlator in the time domain to identify required signals requires a huge number of calculations, and therefore is expensive.
Furthermore, most communication standards contain a transmission power limit. Increasing the gain of a transmitting antenna decreases the transmission power. Therefore, there is thus a need for, and it would be highly advantageous to have a method and corresponding device that increase transmission and reception ranges without increasing the antenna's gain.
One of the possible solutions for increasing the transmission and reception ranges without increasing the antenna's gain is to use the spatial scanning method, as known in the radar art. However, the spatial scanning method is notably limited because it is time-consuming.
It is also desirable to have a method and device for sniffing the medium in order to filter out interfering signals. In an exemplary embodiment of the present invention, an IEEE 802.11 type of wireless network is implemented. In this exemplary embodiment, interfering signals that should be filtered out are, for example, Bluetooth signals, Cordless phones signals, etc.

Method and corresponding device for joint signal detection and direction of arrival estimation


A lithography exposure device is provided which includes a mounting device for the layer sensitive to light, an exposure unit with several laser radiation sources, an optical focusing means associated with the laser radiation sources, a movement unit for generating a relative movement between the optical focusing means and the mounting device, and a control for controlling intensity and position of exposure spots so that exposed structures which are as precisely structured as possible can be produced. A laser radiation field propagating in the direction of the light-sensitive layer generates each of the exposure spots from respective focal points and has a power density which leads in the conversion area in the light-sensitive layer to formation of a channel penetrating the light-sensitive layer with an index of refraction increased in relation to its surroundings by the Kerr effect and which guides the laser radiation field in a spatially limited manner.

The invention relates to a lithography exposure device for producing exposed structures extending in a surface area in a layer sensitive to light, comprising a mounting device for the light-sensitive layer, an exposure unit comprising several laser radiation sources, an optical focusing means associated with the laser radiation sources for the laser radiation exiting from the respective laser radiation sources, the optical focusing means generating from the laser radiation of each of the laser radiation sources an exposure spot effective in the light-sensitive layer with a predetermined extension transverse to a direction of exposure movement, a movement unit for generating a relative movement between the optical focusing means and the mounting device in the direction of exposure movement and a control for controlling intensity and position of the exposure spots relative to the light-sensitive layer in such a manner that a plurality of conversion areas penetrating the light-sensitive area can be generated by means of the exposure spots, the material of the light-sensitive layer being converted in these conversion areas from an initial state into an exposed state and the conversion areas together resulting in the exposed structure.
A lithography exposure device of this type is known from EP 1 319 984.
The object of lithography exposure devices is, however, always to configure the extension of the exposure spot as precisely as possible in order to be able to produce exposed structures which are structured as precisely as possible.

Lithography exposure device having a plurality of radiation sources


The present invention is an enclosure with a cooling scheme for cooling heat producing devices, such as electronic components, contained within the enclosure. Specifically, the cooling scheme of the present invention shelters the enclosure from solar heat without significantly decreasing the efficiency of the convection process associated with heat sinks. In an embodiment of the present invention, the enclosure comprises a housing and a solar shield. The housing includes a plurality of heat sinks for absorbing and dissipating heat generated by the devices. Each heat sink has an interior side to which the devices are mounted and an exterior side with a plurality of fins that form first and second channels. The first channels are aligned longitudinally with the prevalent direction of airflow, and the second channels are aligned in a contrasting manner to the first channels to allow fresh air to be drawn into the first channels (through the second channels) during the convection process. Positioned over the heat sinks is the solar shield for sheltering the housing from solar heat. The solar shield includes ventilators which align with the first and second channels for allowing the passage of air into the heat sinks and heat absorbed by the heat sinks to be dissipated. To prevent overcooling, the solar shield may include regulating devices positioned over the ventilators to constrict airflow through the ventilators when the enclosure is below a particular temperature.

In the development of wireless communication networks, it is desirable to provide a number of small base stations, called microcells, which would provide coverage to limited geographical areas. One implementation of such microcells involves the packaging of electronic components associated with the base stations into small outdoor enclosures. However, most enclosures tend to trap heat which may be detrimental to the electronic components, particularly to integrated circuits and microprocessor chips.
Generally, outdoor enclosures containing any electronic components are subject to two forms of heat: heat generated by the electronic components and solar heat. To alleviate the enclosures from the former form of heat, a prior art cooling scheme includes heat sinks to which the electronic components are mounted. In this prior art cooling scheme, the heat generated by the electronic components is absorbed by the heat sinks and dissipated by a process known as convection, i.e., the heat absorbed by the heat sinks is carried away by air flowing through the heat sink.
To alleviate the enclosures from solar heat, a prior are cooling scheme includes covering the enclosures with solar shields that will shelter the enclosures (and electronic components contained within) from the solar heat. However, using the solar shields in combination with the heat sinks, in most cases, can significantly decrease the overall efficiency of the convection process. Specifically, when positioned over the heat sinks, the solar shields tend to disrupt or impede the flow of air into the heat sinks, thereby obstructing the convection process. Accordingly, there exist a need for an enclosure with a cooling scheme for heat producing devices that shelters the enclosures from solar heat without significantly decreasing the efficiency of the convection process associated with heat sinks.


A novel achiral biaryl-type compound and a circular dichroism(CD) color fixing agent are provided. Furthermore, a method for determining an absolute configuration of a chiral compound is carried out by introducing the above achiral biaryl-type compound into the chiral compound.

1. Field of the Invention
This invention relates to a biaryl-type compound, a circular dichroism (CD) color fixing-agent for introducing a CD chromophore into a chiral compound and a method for determination of absolute configuration of a chiral compound.
2. Description of Related Art
In compounds having a single functional group such as alcohols, thiols, amines and the like is included a compound having an optical activity referred to as a chiral compound. There are known various methods in order to determine an absolute configuration of such a chiral compound.
Among them, a modified Mosher method using NMR is used most practically and frequently at the present time.
And also, a method using CD is known in the determination of the absolute configuration. As to such a method for the determination of the absolute configuration, there are several reports. For example, Harada et al. of Tohoku University of Japan reports that by condensing a chiral alcohol with di(1-naphthyl) acetic acid as a CD auxiliary group is observed a good correlation between the absolute configuration and sign of exciton chirality (40th natural organic compounds symposia).
Furthermore, Adam W. et al. reports that in case of a chiral benzyl alcohol, by newly introducing a benzoyl group is observed a good correlation between sign of Cotton effect indicated by the obtained benzoate body and the absolute configuration [Journal of Organic Chemistry, 65, pp 186–190 (2000)].
However, the modified Mosher method becomes complicated in the operation of determining the absolute configuration and requires at least a few milligram of a sample.
The method of Harada et al. is insufficient in the yield of the derivative and further requires the calculation of a stable conformation through a molecular force-field calculation, so that it has a problem that multistage operations are required in the determination of the absolute configuration.
Furthermore, the method of Adam et al. requires the calculation of the stable conformation likewise the above method, and has a problem that an application range of the chiral compound is restricted.
Since the CD exciton chirality method is based on the interaction of two chromophoric excitons, an application to a compound having two or more functional groups such as diol or the like is restricted.

Biaryl-type compounds, CD color fixing agent and method for determination of absolute configuration


Receiver having an RF input for applying an RF input carrier-modulated modulation signal thereto, which receiver is coupled to a multiplier circuit and to a phase-locked loop (PLL) with a signal path incorporating a phase detector, a loop filter, a first dc decoupling circuit and a controlled oscillator having an in-phase and a quadrature output via which local in-phase and quadrature carriers are applied to the multiplier circuit and the phase detector, respectively, and a signal generator for generating a local auxiliary pilot and a pilot detector for detecting the local auxiliary pilot, an output of which is coupled to the controlled oscillator via a low-pass filter. In order to reduce the influence of oscillator radiation and other parasitic crosstalk effects on the dc reduction, an output of the signal generator is coupled to the signal path of the phase-locked loop between an output of the phase detector and a control input of the controlled oscillator, an output of the multiplier circuit is coupled to a first input and the output of the signal generator is coupled to a second input of the pilot detector.

1. Field of the Invention
The invention relates to a receiver having an RF input section for receiving for applying an RF input carrier-modulated modulation signal. The RF input section is coupled to a multiplier circuit and to a phase-locked loop (PLL) with a signal path incorporating a phase detector, a loop filter, a first dc decoupling circuit and a controlled oscillator having an in-phase and a quadrature output via which local in-phase and quadrature carriers are applied to the multiplier circuit and the phase detector, respectively, and a signal generator for generating a local auxiliary pilot and a pilot detector for detecting the local auxiliary pilot, an output of which is coupled to the controlled oscillator via a low-pass filter.
2. Description of the Related Art
A receiver of this type is known per se, for example from European Patent Specification no. 184873 (corresponding to U.S. Pat. No. 4,631,499.
The known receiver is a directly mixing AM PLL synchronous receiver whose multiplier circuit is used for synchronous detection of a modulation signal which is amplitude-modulated on the RF input carrier. The local mixing carrier required for the synchronous detection is obtained by means of the controlled oscillator incorporated in the phase-locked loop and should be phase-synchronous with the RF input carrier for a correct synchronous detection. The local mixing carrier is therefore also referred to as local in-phase carrier.
As is known, the loop signal, i.e. the signal in the phase-locked loop, undergoes an unwanted dc offset which is substantially caused by circuit and/or bias voltage asymmetries and cannot be completely avoided in practice. To prevent this unwanted dc offset from disturbing a correct phase control of the controlled oscillator, particularly at comparatively small amplitudes of the RF input carrier, said RF input carrier and the local quadrature carrier of the controlled oscillator modulated in amplitude by means of the auxiliary pilot are applied to the phase detector of the known directly mixing AM synchronous receiver. Consequently, the phase detector supplies a desired mixing product at a frequency which is equal to the auxiliary pilot frequency and which varies in amplitude with the phase difference deviating from 90.degree. between the RF input carrier and the local quadrature carrier. DC components are removed from this desired mixing product in said first dc decoupling circuit and subsequently applied to the pilot detector for synchronous amplitude detection. A dc signal whose amplitude varies with the last-mentioned phase difference is obtained at the output of the pilot detector. This dc phase difference signal is applied as an oscillator control signal to the controlled oscillator. Due to the dc offset suppression in the first dc decoupling circuit, this oscillator control circuit and hence the phase lock between the local carriers and the RF input carrier is comparatively insensitive to said unwanted dc offsets.
However, due to oscillator radiation and other effects of parasitic crosstalk, the unmodulated oscillator signal occurs with a crosstalk-dependent amplitude at the RF input of the receiver. This parasitic oscillator signal is multiplied in the phase detector by the oscillator signal which is amplitude-modulated by means of the auxiliary pilot, which results in an unwanted mixing product at a frequency which is the same as that of the auxiliary pilot. This unwanted mixing product is inseparably superimposed on said desired mixing product and disturbs the phase difference information in the desired mixing product. Both mixing products jointly pass the first dc decoupling circuit, with the unwanted mixing product at the output of the pilot detector resulting in a parasitic dc offset disturbing the desired dc phase difference signal. Since this parasitic dc offset increases with the frequency of the oscillator signal, a phase error, increasing with the frequency, between the local carrier and the RF input carrier occurs in the known directly AM synchronous receiver.
The dc offset reduction mode used in the known AM PLL synchronous receiver is therefore unsuitable for use in receivers for the reception of signals which are modulated on a much higher carrier frequency than that of the conventional RF AM radio signals which are of the order of at most 1 MHz. Examples are FM PLL synchronous receivers for receiving the now conventional FM radio signals at an RF carrier of the order of 100 MHz, and FM receivers including a PLL FM demodulator tuned to a comparatively high intermediate frequency such as, for example TV satellite receivers.
Moreover, the 3 dB loop passbandwidth of the phase-locked loop of the known AM PLL synchronous receiver is considerably smaller than that of FM receivers and therefore presents fewer problems as regards noise behavior, stability and selectivity.


The device for blood flow property measurement in the body and the method of its connection to the subject enables to measure electrical impedance in the main parts of body simultaneously. The impedance is spatially localized in the particular scanning channels (5) both by the placement of the current electrodes (9) of the alternating current source (2) and by setting their frequencies, and by proper spatial placement of the voltage electrodes (6). For the purpose of the whole body measurement at least three current generators (1) and twelve scanning channels (5) are used. The number of scanning channels (5) can be adjusted as necessary. By means of this device it is possible to monitor blood pulse waves or blood flow in the particular parts of human body.

Nowadays one of the methods used for measuring the cardiac output is based on measuring the thorax impedance. Commercial devices are equipped with one or two scanning channels, not enabling to assess more parameters on more body parts simultaneously. Therefore it is not possible to monitor the pressure waves of the blood or the blood flow in various parts of human body simultaneously.

Device for blood flow property measurement and method of its connection

INSTITUTE OF SCIENTIFIC INSTRUMENTS AS CR, V. V. I.


A screwdriver comprises a torque setting mechanism including a torque adjustment ring, an actuation rod threadedly secured to the upper torque adjustment ring and a lower torque adjustment nut, a spring biased sleeve with the actuation rod passed, and a clutch ring snugly put on two opposing intermediate flats of the actuation rod and having an upper surface engaged the torque adjustment ring and a lower surface formed with recesses engaged with steel balls on an upper surface of a support ring in the sleeve. Turning a rotatable handle will turn the sleeve. The clutch ring will disengage with the steel balls if the torque exceeds a set value. Thus, the torque exerted on the handle will not transmit to a shank secured to the actuation rod so as to prevent a screw from being over-driven by the shank.

1. Field of Invention
The present invention relates to screwdrivers and more particularly to a screwdriver having a torque setting mechanism such that torque exerted on a handle will not transmit to a shank if the torque exceeds a set value so as to prevent a screw from being over-driven by the shank.
2. Related Art
Screwdrivers are well known. It is typical that tightness of a driven screw is determined based on experience of a person working on it. It is understood that in one case the screw may be damaged if force (i.e., torque) exerted thereon exceeds a set value thereof. Thus, it is highly desirable to provide a screwdriver with a torque setting mechanism. However, how to design a torque setting mechanism in a limited internal space of a screwdriver while operation convenience and other advantageous features are still provided is a task to be accomplished. Thus, continuing improvements in the exploitation of such screwdriver are constantly being sought.

Screwdriver with torque setting mechanism


A tire mounting/dismounting machine (1), comprising a base (2), rotating means (3) for supporting and blocking a wheel (100) and a column (4) associated to the base (2), a first arm (7) and a second arm (8) being slidably mounted on the column (4), an upper first debeader tool (13) and a lower second debeader tool (9) being mounted respective at free ends of each arm (7, 8). Mounted at the free end of the first arm (7) is a head (10) which is rotatable with respect to an axis (Y), from which head a mounting tool (11), a dismounting tool (12) and the first debeader tool (13) project, the tools (11, 12, 13) being mounted in reciprocal positions such that the tools (11, 12, 13) do not interfere with one another and such that by rotating the head (10) with respect to the first arm (7) a same work position can be reached for each of the tools (11, 12, 13). Means for blocking (14, 15, 16, 17) are associated to the head (10) in three different positions, a same work position for each of the tools (11, 12, 13) corresponding to each of the three different positions.

The present invention relates to a machine for mounting and dismounting tyres.
In order to perform a tyre dismounting and a following mounting operation off and on a wheel, the prior art comprises machines which include a self-centring device which enables the wheel to be blocked and to set it in rotation with respect to an axis, which in the majority of cases is a vertical axis, in proximity of which device there is a pair of debeader tools, an upper tool and a lower tool, arranged symmetrically with respect to the horizontal plane of symmetry of the wheel, and a second vertical column along which a dismounting tool can slide, as well as a mounting tool, both being associated to a relative work arm.
In the prior art, in order to perform the dismounting of the tyre from the wheel, the wheel is fixed on a self-centring device and blocked thereto. At this point debeader tools are first applied, by translating the first column; the debeaders are positioned in contact with a point of the two opposite circular edges of the tyres (beads) in order to push them internally of the rim, from which the beads then detach. Once the debeading operation is done, the debeaded tyre is removed from the rim (to which it is still associated). This operation is performed by using the dismounting tool located on the second column, which column is neared by translating to the wheel on the self-centring device. In this case too, the dismounting tool, which bears a hook at an end thereof, is brought close to the wheel into a position such that it can be inserted between the edge of the rim and the bead of the tyre up until it hooks the tyre, which is then extracted by completely detaching the tyre from the rim of the wheel itself.
In order to perform a mounting operation of a new tyre on the same rim, a mounting tool is used, also located on the second column, which consists in a bar which is brought into proximity of the bead of the new tyre, previously placed around the rim, to push it internally of the rim to which it must attach. All of these operations are performed while the wheel rotates on the self-centring device.
In order to operate correctly, in each of the above-described operations, i.e. the debeading, dismounting and mounting, the wheel and the tool to be used must time by time be in a reciprocal position such as to enable contact in a point located in proximity of the bead and thus the circular edge of the rim. The described known machines exhibit some drawbacks and disadvantages. Each time the three described operations are performed on a same wheel, the wheel and the tool under use have to be located in a reciprocal position such as to guarantee a correct performing of the work and since the tools are borne on two columns, both columns have to be moved so that the reciprocal position between the wheel and the tool used is the same each time.
Further, the presence of two columns limits the movement and vision of the operator in proximity of the zone in which the machine operates on the wheel, creating relative awkwardness and obstacles in relation to the freedom of movement of the operator himself.

Societa Italiana Costruzioni Elettromeccaniche S.I.C.E. S.p.A.


A semiconductor integrated circuit having an ESD protection circuit enhancing a durability against thermal destruction is provided. The semiconductor integrated circuit configured by a plurality of MOSFETs each having an SOI structure formed on a silicon substrate includes a functional circuit having an external connection signal terminal, a pair of power terminals and at least one of the MOSFETs. The semiconductor integrated circuit also includes at least one ESD protection circuit having a first terminal and a second terminal connected to the signal terminal and the power terminals, respectively. The ESD protection circuit includes at least one first MOSFET of the MOSFETs formed on the silicon substrate. The first MOSFET has a drain connected to the first terminal, a gate connected to the second terminal, and a source connected to the second terminal. The at least one ESD protection circuit also includes at least one second MOSFET of the MOSFETs formed adjacent to the first MOSFET on the silicon substrate. The second MOSFET has a gate connected to the first terminal and the same conductivity type as the first MOSFET.

1. Field of the Invention
The present invention relates to a large-scale integrated (LSI) circuit utilizing an SOI (Silicon on Insulator) substrate, and in particular relates to an LSI circuit having an ESD (Electro-Static Discharge) protection device.
2. Description of the Related Art
In a typical semiconductor integrated circuit, an ESD protection circuit is provided across an internal circuit and an input terminal (PAD) of the semiconductor integrated circuit, thus preventing an excess electric current flow to the internal terminal when an ESD surge is applied from the input terminal. When a voltage applied to the internal circuit or an electric current flowing to the internal circuit is larger than a predetermined value, an excess electric current instantaneously flows to the ESD protection circuit. Thus, the ESD protection circuit is designed so as to prevent a breakdown of the internal circuit. There have been proposed several ESD protection circuits each having a metal oxide semiconductor FET (MOSFET) formed on an SOI substrate.
Japanese Patent Kokai No. 2002-76131 (document D1) discloses a technology of forming an R-C circuit utilized for triggering an electrostatic discharge protection. The R-C circuit includes a trench capacitor and a resistive element which are formed in an SOI substrate. The R-C circuit in document D1 is utilized to provide a time constant of the trigger operation.
Japanese Patent Kokai No. 2002-324842 (document D2) discloses a semiconductor protection circuit having an NMOS as a protection device for protecting an SOI semiconductor circuit from ESD. In document D2, a PMOS is conductive at a time when a stress of the ESD is applied, and thus a positive voltage is applied onto a semiconductor substrate. Owing to a substrate bias effect, a threshold voltage of the NMOS is decreased and a trigger voltage having a snapback characteristic is decreased. In document D2, it is suggested that the PMOS may be replaced by a capacitor.
Japanese Patent Kokai No. 2006-86239 (document 3) discloses a semiconductor device including a layered substrate, a removed part, a cavity part, an ESD protection circuit and a semiconductor element. The layered substrate has a plurality of regions which are overlaid with each other. Upper parts of a semiconductor layer, an insulating layer, and a bulk layer, formed in a first region of the layered substrate are removed so as to form the removed part. An upper part of a bulk layer of a second region adjacent to the removed part is removed so as to form the cavity part. The ESD protection circuit is formed on the bulk layer of the removed part. The semiconductor element is formed in at least one part of the second region of the semiconductor layer. The document D3 states to form an ESD protection circuit which effectively functions for a semiconductor device having an SOI structure having a silicon layer with a thin thickness.
Japanese Patent Kokai No. 2005-93802 (document D4) discloses a method of modeling electric characteristics of an ESD protection device, which method is utilized for simulating a circuit including an ESD protection device. The method includes a parameter configuration step and a modeling step. In the parameter configuration step, at least one specific parameter, which will influence the electric characteristics of the ESD protection device, is configured. In the modeling step, the electric characteristics of the ESD protection device are modeled on the basis of the specific parameter. Accordingly, a change in characteristics of the ESD protection device can be easily expected or evaluated.
A document entitled "ESD protection for SOI technology using under-the-BOX (substrate) diode structure", A. Salman et al., AMD, EOS/ESD symp., 4B.2, 2004 (document 5) suggests that an ESD protection circuit formed on an SOI substrate is thermally damaged by an increased temperature due to a self-heating because the ESD is surrounded by an insulating film of low thermal conductivity. Document 5 also suggests that a breakdown voltage and electric consumption (I: surge electric current×surge voltage) contributing the heat generation should be decreased. In order to lower the breakdown voltage, a method of increasing a substrate electric potential Vsub during an operation of an ESD protection circuit is described to be effective in document D2.
However, for the purpose of preventing destruction of an ESD protection circuit, it is desirable not only to lower the breakdown voltage but also to enhance a durability against thermal destruction that is caused by a higher electric consumption.


A facility for managing a synchronization mechanism that supports initialization, acquisition, release, and deletion operations is described. When a thread seeks to perform the acquisition operation, the facility permits performance of the acquisition operation only if the initialization operation has been performed more recently than the deletion operation. When a thread seeks to perform the deletion operation, the facility waits until any threads that are seeking to perform the acquisition operation or have performed the acquisition operation more recently than the release operation have performed the release operation before deleting the synchronization mechanism.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
A software facility that establishes a wrapper around a native synchronization mechanism provided by an operating system and native functions called to interact with the native synchronization mechanism in order to preclude undesirable behavior of the native synchronization mechanism ("the facility") is described. As part of the wrapper, the facility provides an analog for each of the native synchronization object functions as follows:                safeInitialize: analog of Initialize        safeAcquire: analog of Acquire        safeRelease: analog of Release        safeDelete: analog of Delete

Providing a wrapper around native synchronization objects


The dry coupling includes a typical shaft to shaft coupling, conformed to body the invention by inclusion of two hub parts (4) with hub flanges (5,5') bonded thereunto and also an intermediate tube (6) interconnecting the flanges with respective flanges (7), each forming a membrane. For transmitting a torque the flanges are coupled to adjacent hub flanges (5). It is important that all parts (4,5;6,7) possibly except connecting elements (8) consist of a high modulus fiber reinforced material (FVW). Preferably the hubs consist of a carbon fiber reinforced material (CFK) and the intermediate tube of a more flexible GFK.

Couplings of the kind mentioned above are known especially in high speed machines. They serve, thereby, for the transmitting of the torque and of possible additional forces from a steel shaft by means of a known pressurised-oil connection onto a steel hub and from this steel hub via shrunk on plastic hubs and so called membranes of an intermediate tube (torsion tube). In these known designs parts of steel and such of plastic material are used.

Dr. Ing. Geislinger &C., Schwingungstechnik Gesellschaft mbH


A navigation system comprises an image sensor operable to obtain a first image at a first moment in time and a second image at a second moment in time; an inertial measurement unit (IMU) operable to obtain measurement data corresponding to the first and second moments in time; and a processing unit coupled to the image sensor and the IMU. The processing unit is operable to estimate motion between the first and second moments in time based on the measurement data from the IMU; calculate a plurality of transformations based on the estimated motion; apply each of the plurality of transformations to the first image to produce a plurality of predicted images; compare the second image to each of the plurality of predicted images; select the predicted image from the plurality of predicted images which most closely matches the second image; and compensate for error in the IMU measurement data based on the transformation corresponding to the selected predicted image.

Navigation systems often include an inertial measurement unit (IMU). Typical IMUs include a plurality of gyroscopes and a plurality of accelerometers. The gyroscopes and accelerometers measure a vehicle's velocity, orientation and gravitational forces. However, typical IMUs suffer from various sources of error in the measurements. For example, source of error can include gyroscope scale factor error, bias, and drift. These errors may be time-varying and can accumulate in the IMU measurements. In particular, a small error in an initial measurement may be propagated in subsequent measurements and combined with additional error or magnified by the navigation calculations. For example, a small error in attitude, such as a 10th of a degree, can push the vehicle hundreds of meters away from its target destination.

Method and apparatus for vision aided navigation using image registration


The invention pertains cushioned vinyl floor coverings. For the production of cushioned vinyl floor coverings non-woven carriers made from glass fibers are currently used. However, handling of floor coverings with glass fiber carriers is quite difficult especially when the covering is laid on stairs or sharp edges. According to the present invention a solution to overcome the disadvantages of the prior art is a cushioned vinyl floor covering comprising a nonwoven carrier that is made from different polymers. The different polymers exist either in separate filaments or together in one filament.

The present disclosure pertains to cushioned vinyl floor coverings.
Cushioned vinyl is made by applying several PVC based layers on a carrier, each layer with its own function, for example, impregnation, surface foaming, printing, wear protection and carrier. An important step in the cushioned vinyl process is the foaming step, where the top layer and back layer are being foamed at elevated temperatures and by which the cushioned product is acquired.
Currently wet laid nonwoven glass fleeces are used as carriers in the cushioned vinyl process. They fulfil the requirements to obtain a stable process and a dimensionally stable end product. Moreover, glass fleeces are cheap and can be applied in low weights of about 50 g/m2.
Application of glass fleeces also has disadvantages. Handling of glass fleece may be hazardous to the health of the people concerned. Glass makes the cushioned vinyl product brittle. The product loses its stability already at low elongation levels because of the breaking of the carrier. During installation these elongation levels are often exceeded, especially in corners, on stairs or other places where the product is being folded. The surface becomes uneven at these places. The glass carrier also leads to low tear strength of the product and installers have to be careful not to tear the product, especially on places where cuts have to be made. Transport of cushioned vinyl should not happen without precaution. When a roll is bent too much, the brittle structure causes the roll to break.
For these reasons, the market demands glass free carriers for cushioned vinyl. To overcome the disadvantages that are described, the use of thermoplastic nonwoven carriers can be considered. Application of thermoplastic nonwoven carriers results in much easier and less sensitive installation of the cushioned vinyl product by having higher elongation capacity than glass fleeces. Also thermoplastic nonwoven carriers do not have any negative influence on the health of operators working with these products. Moreover, non woven glass fiber carriers are currently only available in a 4 m width or less. Since producers of cushioned vinyl floor coverings try to satisfy the need for 5 m wide cushioned vinyl floor coverings, there is also a demand for 5 m wide carriers that meet the requirements for cushioned vinyl floor coverings.
Thermoplastic nonwovens are not widely used for cushioned vinyl because of their lower mechanical and thermal stability as compared to glass. Low stability may cause thermal shrinkage, formation of creases and too much loss of product width.
A general demand of carriers for cushioned vinyl is surface regularity, which is necessary to apply the impregnation layer regularly over the full width (4 m-5 m). Furthermore structure openness is needed for penetration of the PVC gel through the carrier in order to have sufficient delamination strength between the top layers and the back cushioned layer. Finally good bonding of the gel to the carrier is needed to have good process speed.
Solutions have been presented for making stable thermoplastic nonwoven carriers for cushioned vinyl but these solutions did not meet with all requirements, either missing an open structure or enough surface regularity or economical attractiveness compared to glass fleece. A possible option to improve the stability by increasing the weight can only be done to a limited extend in order to keep the structure open enough.
Document FR 2,013,722 discloses a nonwoven mat made from nylon (polyamide) filaments with a vinyl chloride coating usable as floor covering. The nonwoven mat is bonded by hydrogen bonds at the points of intersection of the filaments. In this way it seems hardly possible to obtain a carrier with an acceptable stability.
U.S. Pat. No. 4,234,651 discloses a process for the manufacture of a nonwoven product having high shear strength and dimensional stability. This product may be used for cushioned vinyls. The product comprises polyethylene terephthalate (PET) filaments and it exhibits a unit area weight of 150-400 g/m2. Such high unit area weight will make the necessary impregnation quite difficult.
U.S. Pat. No. 4,363,845 discloses a nonwoven fabric made from thermoplastic filaments having a PVC coating that may be used as cushioned vinyl floor covering. Although this nonwoven fabric has high dimensional stability, production is quite laborious as a multiplicity of filament groups and individual filaments must be intermixed and subsequently bonded with a secondary binder. In order to achieve the necessary stability an unit area weight of about 200 g/m2 is required.
It is an object of this disclosure to overcome the disadvantages of the prior art.