A source driver includes a hold memory circuit and a switch circuit. The hold memory circuit includes (i) delay circuits for delaying an inputted horizontal synchronization signal, (ii) hold latch cells each for latching display data in accordance with the horizontal synchronization signal that has been delayed by the delay circuit, and (iii) a control circuit for outputting a display start signal to the switch circuit upon receipt of the horizontal synchronization signal that has been delayed by the delay circuit. The switch circuit outputs a plurality of driving signals in accordance with the display start signal. This allows the peak value of the power source current to be reduced, and enables to avoid the malfunction of the source driver due to the misidentification of the horizontal synchronization signal and to avoid that the output timing becomes nonuniform.

A liquid crystal panel (a liquid crystal display panel) has been in heavy usage in a display (a display module such as a liquid crystal display apparatus) such as a PC (personal computer) or a TV (television).
The following description deals with one example of driving circuits that drive a liquid crystal panel.
FIG. 13 is a block diagram showing a configuration of an X driver (a source driver) for supplying source lines with signals. The X-driver is one of the driving circuits. The technique relating to this kind of circuit is disclosed in Japanese examined patent publication No. 2747583 (publication date: Dec. 12, 1998), for example.
FIG. 14 is a time chart showing how main signals such as input signals, internal signals, and output signals behave during driving of the X-driver shown in FIG. 13.
As shown in FIG. 13, the X-driver includes a shift register 101, a latch A-circuit 102, a latch B-circuit 103, a decoder 104, a level shifter 105, and an analog switch group 106.
The shift register 101 receives a clock signal XCL and a start pulse (an input signal) XSP (see FIG. 14). The shift register 101 supplies internal output signals Q1 through QM to corresponding stages of the latch A-circuit 102, respectively. In FIG. 14, an internal output signal Qa indicates a signal which is outputted from the a-th stage of the shift register 101.
Symbols PD1 through PD4 indicate an input signal to be supplied to the first stage of the latch A-circuit 102. The input signal is a 4-bit digital signal.
The latch A-circuit 102 latches K-bit (here, K=4) signal PD1 through PD4 in parallel, and then outputs signals QA1 through QAM. Note that the signal QAa indicates a signal outputted from the a-th (1≦a≦M) stage of the latch A-circuit 102.
Namely, the latch A-circuit 102 sweeps the 4-bit data PD1 through PD4 in response to each rising edge of the output signals from the shift register 101 so as to output the signals QA1 through QAM.
The latch B-circuit 103 receives a latch clock input signal LCL. The latch B-circuit 103 sweeps the output signal QAa (1≦a≦M) of the latch A-circuit 102 in response to each falling edge of the latch clock input signal LCL so as to output a signal QB (4-bit signal DI1 through DI4).
The decoder 104 receives and decodes the 4-bit signal DI1 through DI4 so as to generate 16 data DO0 through DO15.
The level shifter 105 boosts the output signals of the decoder 104 up to a level of a liquid crystal driving voltage.
The analog switch group 106 supplies the output signals of the level shifter 105 to control terminals of respective analog switches so as to select one of 16(=24)-level gradation signals.
Note that each stage of the latch A-circuit 102 includes four (4) half-latch circuits 107, and that each stage of the latch B-circuit 103 includes four (4) half-latch circuits 108.
Each stage of the latch A-circuit 102 latches a 4-bit PD1 through PD4 in sync with an output Qn (n is an integer, and satisfies 1≦n≦M) from a corresponding stage of the shift register 101. All stages of the latch B-circuit 103 latch, in block, the signals QA1 through QAM in response to the latch clock input signal LCL. The decoder 104 decodes the 4-bit signal DI1 through DI4 for each stage.
One of the data DO0 through DO15 is selected in accordance with each result of the decoded 4-bit signal DI1 through DI4. This allows one of 16 analog switches in the analog switch group 106 to be selected via the level shifter 105.
This selection allows a target one of 16 gradation levels of the liquid crystal driving voltage that is externally supplied to be outputted to a source line as a final analog driver output O. Note that the symbol "i" indicates the data of i-row.
Pursuant to the demand that a large-sized screen be produced, conventional liquid crystal display apparatuses, having the above configuration, have been developed so as to be exploited in screens for TVs or PCs. Meanwhile, small and medium liquid crystal panel and liquid crystal driving circuit (liquid crystal driving apparatuses) suitable for a portable terminal such as a mobile phone have recently been developed such that the liquid crystal display apparatus is exploited in the portable terminal that has gained market share rapidly. With regard to the liquid crystal panel and liquid crystal driving circuit, strongly desired are downsizing, weight saving, low power consumption including battery-driving, multiple-output, speeding up, improvement in display quality, and low cost.
It is the tendency for the amount of data signal outputted at a same timing in block from a latch circuit to increase. The data signal is outputted from the latch circuit in sync with rising or falling edge of a latch signal LS. In the case of the configuration shown in FIG. 13, the data signal is outputted in sync with a falling edge of the latch clock input signal LCL. This tendency is derived from the affect by the large-sized liquid crystal panel and the multiple-output of the liquid crystal driving circuit.
On this occasion, as shown in FIG. 17, the power source current, which is supplied to the liquid crystal driving circuit, has a great peak value, thereby resulting in that the electric current consumption becomes great. FIG. 17 shows the measurement results of peak values of the power source current flowing in GND line (logical GND) in a logical circuit and a level shifter (a level shifter circuit), respectively.
Thus, according to the conventional technique, the current intensively flows in the logical GND, thereby giving rise to the occurrence of a great noise. This causes the problem that the data in a hold circuit section is changed.
In view of the circumstance, a liquid crystal display apparatus, which can reduce a peak value of the power source current in a driving circuit, has been developed. This kind of liquid crystal display apparatus is disclosed in Japanese unexamined patent publication No. 8-22267 published on Jan. 23, 1996, for example. FIG. 15 shows the configuration of such a conventional liquid crystal display apparatus.
A liquid crystal panel control apparatus 205 shown in FIG. 15 controls a liquid crystal panel 201. The liquid crystal panel control apparatus 205 receives a display data from a CPU 204, and generates clock pulses CL1 and CL2, a display data Din, and a frame signal FLM, respectively, which are required for the operation of the liquid crystal panel 201.
An alternating signal generation circuit 206 counts the clock pulse CL1 that corresponds to selection timing, and changes the polarity of an alternating signal M for every plurality of scanning lines during one frame (a display period during which one screen is displayed). This allows a frequency for the alternation to become high up to around hundreds of Hz, so as to avoid the flickering of the screen due to the alternation. Note that the flickering of the screen due to the alternation comes to an issue that the screen flickers, if the polarity of the alternating signal is changed for each frame, for example. This is because the frequency of the polarity inversion becomes relatively low.
A voltage generation circuit 207 generates driving voltages V1 through V6 that are supplied to a scanning driver 203 and a data driver 202. The voltage generation circuit 207 includes resistors that are connected in a series manner and operational amplifiers
The liquid crystal panel 201 includes m×n pixels. Namely, the liquid crystal display apparatus includes m scanning lines X1 through Xm and n signal lines Y1 through Yn.
The scanning driver 203 includes a shift register that carries out a shift operation in accordance with the clock pulse CL1. The scanning driver 203 allows a scanning line electrode to output the driving voltage generated by the voltage generation circuit 207 in accordance with an output signal of the shift register. The scanning driver 203 allows a corresponding scanning line electrode to have a selection level or a non-selection level.
More specifically, when the output signal of the shift register has a selection level, the scanning driver 203 outputs the driving voltage V1 to a corresponding scanning line electrode. Meanwhile, other scanning line driving voltages are the driving voltage V5 that corresponds to the non-selection level of the output signal of the shift register. The shift register sequentially shifts the selection level in sync with the clock pulse CL1. Because of this, a neighboring scanning line electrode has the selection level at the next timing. Thus, the scanning line electrodes are sequentially selected.
The scanning driver 203 switches the driving voltages V1 and V5 to the driving voltages V2 and V6, respectively, in accordance with the alternating signal M. More specifically, when the polarity of the alternating signal M is changed for every plurality of scanning lines during one frame, (i) the selection level is switched from the driving voltage V1 to V2 and vise versa, and (ii) the non-selection level is switched from the driving voltage V5 to V6 and vice versa.
The pixel data Din is serially supplied to a serial/parallel conversion circuit SPC in sync with the clock pulse CL2. A pixel signal corresponding to one scanning line is supplied to a signal line electrode in sync with a clock pulse CL2 during 1H period (within one cycle of the clock pulse CL1).
The pixel signal corresponding to one scanning line thus serially supplied is sent in parallel to a line data latch circuit C shown in FIG. 16. FIG. 16 shows how a driving circuit (the data driver 202), for use in a liquid crystal display apparatus shown in FIG. 15, is configured.
In the data driver 202, the image data is supplied to a level shifter circuit B from a line data latch circuit C that carries out the above described serial to parallel conversion. This allows the image data to be subject to a level shift processing. The line data latch circuit C is configured by a circuit to which a 5-volt power source is supplied. The line data latch circuit C outputs a signal having a high level of 5-volt or a signal having a low level of 0-volt.
In contrast, a driver A, for generating a display output signal that is supplied to a signal line, is configured by a switch MOSFET. The level shifter circuit B allows the output signal of the line data latch circuit C to be subject to the level shift processing. This is made for the purpose of outputting, without any level loss, a voltage, which falls within a relatively great range, such as the driving voltage V1, V3, V4, or V2 generated by the voltage generation circuit 207.
In the liquid crystal display apparatus, as shown in FIG. 16, a delay circuit D is provided between neighboring circuit groups CG. Accordingly, the display output signals outputted from the neighboring circuit groups CG have a phase lag, corresponding to the delay time of the delay circuit D, one another.
This allows the display output signals (display driving currents) to be dispersed and outputted for each circuit group CG. Because of this, the peak current is dispersed and flowed in the power source line, even if the number of the signal lines increases due to the large-sized screen or the high definition. Thus, it is possible to drastically reduce the peak current (the peak value of the power source current) flowing in the power source line (the logical GND line).
As described above, the liquid crystal panel includes many signal line electrodes (n signal line electrodes). The large-sized screen or the high definition causes the number n of the signal line electrodes to astronomically increase. Because of this, the liquid crystal panel includes a plurality of driving circuits having the configuration shown in FIG. 16. This gives rise to the configuration in which a plurality of semiconductor integration circuit apparatuses for driving the signal lines is mounted on a substrate (a mounting substrate).
Even in this case, it is possible in a driving circuit shown in FIG. 16 to disperse the driving current flowing in the power source line in each of the semiconductor integration circuit apparatuses, because the timing for the data latch signal has a phase lag one after another. Accordingly, it is also possible to reduce the peak value of the driving current even in the power source line on the mounting substrate.
Thus, according to the conventional driving circuit, the latch signal LS is delayed so as to reduce the peak value of the power source current.
However, this causes a setup time, provided between the latch signal LS and the start pulse signal in the next horizontal period, to be reduced as shown in FIG. 18.
This gives rise to the problem that the driving circuit erroneously operates for the reason that the latch signal LS cannot be appropriately recognized during one horizontal period.
This driving circuit is configured such that the latch signal LS simply has a phase lag by being sequentially subject to the delay circuits. Although the peak value of the power source current which is supplied to the data driver 202 (signal line driving circuit) can be reduced, the output signals of the data driver 202 also have a phase lag. In other words, the data driver 202 is not configured so as to output the analog signals at a time in block.
This results in that the charging time of the output signals is not uniform in the liquid crystal display apparatus, thereby causing nonuniform display to occur.


A rod guide including an elongated strip base for connection with a vehicle door panel and to encircle an elongated control rod mounted adjacent the door panel, the strip base being spaced away from the rod; at least one mesh wing with a base end connected with the strip base, the mesh wing angularly extending from the strip base and the wing having a contact end for encircling contact with the control rod and dampening any transverse movement of the control rod while freely allowing generally linear movement of the control rod.

Many vehicle doors have an interior door handle at the front end of the vehicle door. The vehicle door handle controls a door latch which is placed in the door towards a rear end of the door.
A control rod guide is typically provided to transfer movement from the door handle to the rear latch. A rod guide typically provides alignment for the control rod. The rod guide also prevents the control rod from rattling within the vehicle door. In U.S. Pat. No. 5,251,403 issued Oct. 12, 1993, to Compeau et al. and assigned to the assignee of the present invention, a rod guide is formed integrally with a plastic mounting panel which is provided inside a vehicle door. The plastic mounting panel mounts the vehicle door regulating hardware.
The rod guide of Compeau et al. provides a cradle having a recess which receives the control rod. A first pair of flex arms are positioned on one side of the cradle and a second pair of flex arms are positioned on the other side of the cradle. The first pair of flex arms reach over the top of the recess and are bent inwardly so that the control rod may be thrust into the recess by deflecting the first pair of flex arms outwardly. The first set of flex arms restore themselves and lock the control rod against removal. The second set of flex arms are similar in construction and operation.
To reduce noise within the vehicle, and also to lower ergonomic efforts associated with opening and closing a vehicle, some of the newly developed automotive door latches have lower release effort requirements. This allows the door to open with a lower force pull being exerted on the interior release handle. However, the rod guide of Compeau et al. places linear friction forces upon the control rod which place a limit on the minimum force requirements for pulling on the door release handle.
It is desirable to provide a rod guide which can laterally secure the control rod yet impose very low frictional loads upon the control rod during linear movement of the control rod.


A method includes: a supervisor writes a digital certificate and a corresponding first public key into an intelligent contract of a blockchain corresponding to an asset type to be supervised, so that all institutions with asset accounts under the asset type can obtain the first public key of the supervisor through the digital certificate, so as to generate an additive homomorphic key for homomorphic encryption of the balance of an asset account; when checking the balance of a new account of a transactor, the supervisor obtains a public key in a public-private key pair corresponding to the new account, generates an additive homomorphic key based on a supervision private key corresponding to the supervisor and a predetermined key exchange protocol and the public key in the public-private key pair according to the key exchange protocol, and decrypts the encrypted balance of the new account, using the generated additive homomorphic key.

Blockchain technology has the characteristics of decentralization and non-tampering of information. By using the blockchain technology, multi-party transaction events (e.g., transfer transactions and payment transactions) can be realized. For example, if bank A and bank B conduct a transaction on a blockchain, then all other nodes on the blockchain will know about the transaction, and other participants can confirm the accuracy of the transaction together and prevent information tampering. However, since there is no absolute authoritative institution node in this transaction method, it is necessary to carry out collective verification on each transaction, leading to the disadvantage that the transaction of transaction participants has no privacy, and the account of one institution may be tracked by institutions on other nodes, thus causing the risk of information disclosure.
In order to solve the above problem, a scheme of additive homomorphic encryption protection is adopted in the industry to solve the problem of information disclosure in blockchain transactions. However, there are still shortcomings: for example, when the account balance of an account is protected by additive homomorphic encryption, only the owner of a homomorphic encryption key can know the actual balance of the account, which makes it difficult for the supervision department to supervise the liquidity of financial assets. If the owner of the assets is required to pass the key for homomorphic encryption to the supervisor in some form, errors and/or potential security risks are likely to occur due to the complicated processing steps of a system, and the efficiency is low.
To sum up, it has become an urgent technical problem to apply the blockchain technology to the trading scene and effectively ensure the security of trading information, the high efficiency of transaction processing and the supervision of accounts by supervisors.

Blockchain-based secure transaction method, electronic device, system and storage medium

One Connect Smart Technology Co., Ltd. (Shenzhen)


A charging system may include a switching device to receive an output voltage from an alternative power source and to provide an output voltage of the charging system, and an algorithm device to provide a control signal to the switching device based on a sensed power from the power source and a sensed output voltage from the charging system.

1. Field
Embodiments may relate to a charging system for alternative energy sources (or alternative power sources).
2. Background
There may be a desire to boost performance and utility of mobile devices (or electronic devices) by extending their battery life. A charging system may be used to provide power to the mobile device.


A method of non-linear display of routes of a machine-tool or another mechanism and including determining a set path based on stored commands and determining an actual path based on actual displacements during operation of the machine-tool or another mechanism resulting from execution of the stored commands, graphically displaying the set path and components of the actual path, which extend parallel to the set path, at a first scale, graphically displaying components of the actual path, which extend perpendicular to the set path, at a second scale, and graphically displaying at a selected points of the set path, the set path and the components of the actual path, which extend parallel to the set path, at a third scale and the components of the actual path, which extend perpendicular to the set path, at a fourth scale.

1. Field of the Invention
The present invention relates to a method of non-linear display of routes of at least one of a machine-tool and another mechanism and which includes determining a set path based on stored commands and determining an actual path based on actual displacements during operation of the at least one of a machine-tool and another mechanism resulting from execution of the stored commands, graphically displaying the set path and components of the actual path, which extend parallel to the set path, at a first scale, and graphically displaying components of the actual path, which extend perpendicular to the set path, at a second scale.
2. Description of the Prior Art
Japanese Publication JP-A-07072914 discloses a method of displaying a return route of a tool with which a workpiece is machined. In order for the operator to be able to simultaneously recognize the displacement speed, the type, color and width of the line, which represents the route, change dependent on the displacement speed. At the points of the route, at which the tool speed is above or below a predetermined value, an attention mark is displayed.
The method of the Japanese Publication JP-A-07072914 does not provide for display of deviations of the actual path from the set path.
Japanese Publication JP-A-58-158713 discloses a method of automatic calculation of a scale and of a position of a tool and a workpiece profile and displaying the information on a display device associated with a numerically controlled machining equipment. The processing information, which is displayed by the display device, occupies the entire available display surface of the display device. The processing information can include a tool route and the machined profile of a workpiece.
However, the display does not permit the operator to compare the tool route with the machined profile of the workpiece. Therefore, the deviations of one line from another are not readily recognizable.
U.S. Pat. No. 5,315,523 discloses a display device of a numerical control unit which displays both the workpiece and the tool. In order to insure an optimal use of the display surface of the display device at all times, a new scale is calculated each time the distance between the tool and the workpiece changes. Thereby, it is insured that both the tool and the workpiece are always shown at a scale which permits to recognize the most possible number of different details.
However, the display of set and actual paths is not contemplated. A further drawback of this display device consists in that at a large distance between the tool and the workpiece, the workpiece in particular is displayed as a very small element. Therefore, an immediate recognition of an erroneous route is not possible.
European Publication EP 510 204 A1 discloses a method of determining the accuracy of a numerically controlled machining equipment. First, a numerical control command is fed to a control of a machine-tool. After execution of the command, the tool route is fed from the machine-tool to the control unit, and the deviation of the actual tool route from that prescribed by the control command is determined. In this way, the accuracy of the machining equipment is determined. Both the set path, which is determined by the control command, and the actual path, which is fed to the control unit, are graphically displayed on the display device. The operator has a possibility to determine the display scales in the X- and Y-direction dependent on the displayed deviations of one path from another.
The drawback of the method, which is disclosed in this European Publication, consists in that the scale can only be changed for the entire display device and not for selected regions of the graphical display. Thus, a selection of an enlargement, which permits to recognize the deviations between the set and actual paths, would not permit a complete display of the entire workpiece.
International Application W094/07187 discloses a method of testing the machining accuracy of a numerically controlled (NC) machine. The NC-machine has at least two axes each having its own drive which is controlled by a servo control loop. The NC-machine further includes a linear encoder for each axis. In accordance with the method, a circular set path is produced by the NC-machine, and a circular actual path, which is obtained based on the NC-machine movement, is compared with the circular set path. For comparison by the operator, both the set path and the actual path are graphically displayed.
One of the drawbacks of this method consists in that, the deviations of the circular actual path from the circular set path are so small at the contemporary NC-machines that the deviations cannot be recognized when the entire circles are displayed by the display device. With an enlarged display of only one section of the circle, the operator cannot see at which point of the circular path the largest error is observed. Further, with a complicated route, a circle does not permit the operator to clearly recognize which portion of the route is straight.
International application WO 97/27521 discloses a method of determining and optimizing the machining accuracy of a machine-tool or a robot. A course of a set path, which is determined by a sub-program available in the numerical control, is compared with an actual path. For determining the actual path, position measuring systems, which are available in a machine-tool for at least two axes, are used. for displaying the profile deviation, the geometrical relationship between the set and actual path is evaluated. The difference between the set point vector and the associated actual point vector is displayed in a direction perpendicular to the course of the set path.
The drawback of the method disclosed in this international application consists in that the entire route cannot be shown when the sectional enlargement takes place in order to make the deviations of the actual path from the set path more recognizable. The display of the entire workpiece is, thus, not possible.
Accordingly, an object of the present invention is to provide a method with which both the entire route display on the available display surface is possible, and the deviations of the actual path from the set path can be qualitatively assessed by the operator.
This and other objects of the present invention, which will become apparent hereinafter, are achieved by providing a method in which at a selected points of the set path, the set path and the components of the actual path, which extend parallel to the set path, are displayed at a third scale, and at the selected points of the set path, the components of the actual path, which extend perpendicular to the set path, are graphically displayed at a fourth scale.
The advantage of the method according to the present invention consists in that the sections of the route, in which no large deviation of the actual path from the set path is expected or takes place, are shown at a reduced scale, and the sections of the route, in which large deviations of the actual path from the set path are expected or take place, are shown at an increased scale. By selecting different scales for a single display, the sections of the route, which are of most interest to the operator, are displayed in detail, without a loss of the possibility of displaying the entire route.
The present invention, thus, provides for a user-friendly display of the set and actual paths. Because the operator can rapidly recognize the deviations, a possibility is created for displaying the entire route in a window of the display device, in addition to the enlarged display of the important sections of the route. Despite the display of the entire route, even small deviations of the actual path from the set path can be shown in detail. This is achieved by changing the scale at critical points such as, e.g., at corners of the set path or at points where a large deviation of the actual path from the set path takes place. Changing of the scale, as discussed above, permits to show the relevant sections of the set and actual path at an increased scale.
In addition, the displacement speed can be displayed in such a manner that the line representing the set displacement speed coincides with the set path, and the actual displacement speed is either determined in absolute terms and is superimposed onto the set displacement speed or is determined as a percentage of the set displacement speed likewise superimposed onto the set displacement speed. This makes immediately clear at which point of the set path the deviation of the speed from the set value takes place.


An information processing apparatus that is capable of accessing to a destination file even when a file including effective entity data and link information to the destination file is transmitted to an external apparatus. An obtaining unit obtains a destination file when a designated file to be transmitted contains link information to the destination file that is different from the designated file. An edition unit edits the link information contained in the designated file so as to become valid link information to the destination file even when the destination file obtained by the obtaining unit and the designated file will be transmitted to an external apparatus. A transmission unit transmits the designated file containing the link information edited by the edition unit and the destination file to the external apparatus.

1. Field of the Invention
The present invention relates to an information processing apparatus that enables transmission of a file including link information, a control method therefor, and a storage medium storing a control program therefor.
2. Description of the Related Art
In recent years, a file (referred to as a "source file", hereafter) that contains link information to a destination file, which is different from the source file, and supports a mechanism by which the destination file is easily opened by clicking the contained link information is provided.
In such a mechanism, the relation between a source file and a destination file always has to hold a relationship shown by link information.
However, if the source file is transmitted, is copied, or is moved, the relation between the source file and the destination file may not hold the relationship shown by the link information.
In order to deal with such a case, Japanese Laid-Open Patent Publication (Kokai) No. 2010-176634 (JP 2010-176634A) discloses a solution in a case where a source file is a file (shortcut key) in which only link information to a destination file is described.
In the disclosed solution, when an operation to copy or move a shortcut key, which is a source file, to a designated location is requested, a destination file linked with the shortcut key is obtained, and the destination file is copied or moved to the designated location instead of copying or moving the shortcut key.
However, the technique disclosed in the above-mentioned publication is effective only when a source file is a file (shortcut key) in which only link information to a destination file is described.
Accordingly, the technique disclosed in the above-mentioned publication cannot be applied to a case where effective entity data and link information to a destination file are described in a source file.
Accordingly, there is a problem in that the destination file cannot be easily accessed from the link information of the source file after moving or copying.

Information processing apparatus enabling transmission of file containing link information, control method therefor, and storage medium storing control program therefor


In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.

1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to SOI semiconductor devices comprising semiconductor elements, such as substrate diodes, that are formed in the crystalline material of the substrate.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes and, in particular, the gate length of the field effect transistors has been an important design criterion.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor- or silicon-on-insulator) architecture has been continuously gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues.
For example, semiconductor elements, such as diodes and the like, may have to be implemented in the substrate material due to certain device requirements, thereby necessitating the formation of appropriate areas in which the substrate material has to be exposed. Any such area may be referred to as a substrate window and may affect the further processing due to a pronounced surface topography. For example, one important issue in high performance devices, such as microprocessors and the like, is an efficient device internal temperature management due to the significant heat generation of the transistors. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance. Typically, for thermal sensing applications, an appropriate diode structure may be used wherein the characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially "ideal" diode characteristic in order to allow a precise estimation of the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is frequently formed in a substrate window area, i.e., in the substrate material located below the buried insulating layer, above which is formed the "active" semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures.
Although providing substrate diodes in sophisticated SOI semiconductor devices is a promising approach for obtaining reliable temperature data during the operation of the semiconductor device, conventional approaches for forming substrate diodes may result in significant yield losses and, thus, loss of performance in the corresponding substrate window due to the continuous shrinkage of device features, such as transistors, lines and the like. For example, in sophisticated semiconductor devices comprising field effect transistors, the gate length has reached values of approximately 40 nm and less, thereby increasing packing density and also providing superior performance of the individual transistors. Similarly, the wiring network, i.e., the metallization system in combination with an appropriate contact level, has to be appropriately adapted to the increased packing density in the device level of sophisticated semiconductor devices, thereby also requiring contact elements and metal features of reduced lateral dimensions. At the same time, the thickness or height of the various metallization levels may have to be reduced so as to correspond to the reduced lateral dimensions. During the fabrication of contact levels, i.e., the dielectric material and the corresponding contact elements formed therein that connect to the contact areas of the semiconductor-based circuit elements, and during the fabrication of the metallization layers of the complex metallization system, a plurality of very complex processes, such as lithography processes, deposition and patterning processes, have to be applied, which may be very sensitive to the overall surface topography of the semiconductor device at a specific manufacturing stage under consideration. In particular, any material removal processes based on a polishing process have been identified to cause significant irregularities when forming contact elements and metallization layers, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100, which represents an SOI device, since the device 100 comprises a substrate 101, a buried insulating layer 103 and a silicon-based semiconductor layer 104. The substrate 101 may represent a silicon substrate and, thus, comprises a crystalline substrate material 102, above which is formed the buried insulating layer 103, which is typically comprised of silicon dioxide. As illustrated, in a certain device area 110A the buried insulating material 103 and the semiconductor layer 104 are at least partially removed in order to provide any circuit elements in the device area 110A within the crystalline substrate material 102. As previously indicated, the device area 110A may also be referred to as a substrate window and is frequently used for implementing a plurality of substrate diodes 150 in and above the crystalline substrate material 202 within the device area 110A. On the other hand, a device area 110B comprises the semiconductor layer 104, in and above which circuit elements are formed, such as sophisticated transistors and the like, wherein, for convenience, a single transistor element 160 is illustrated in FIG. 1.
As discussed above, in sophisticated applications, the transistor 160 may comprise a gate electrode structure 161 having a gate length of approximately 40 nm and less. Furthermore, the transistor 160 comprises drain and source regions 162, wherein at least deeper areas thereof have substantially the same configuration, i.e., dopant concentration, as highly doped regions 152 of the substrate diode 150, wherein, however, the doped regions 152 are formed within an appropriately doped well region 102W provided in the crystalline substrate material 102 within the device area 110A. Similarly, the substrate diodes 150 may further comprise highly doped areas 153, which have a similar configuration as any drain and source regions of transistor elements of inverse conductivity type compared to the transistor 160. For convenience, any such transistors are not illustrated in FIG. 1. In the example shown, the transistor 160 may represent an N-channel transistor and, thus, the drain and source regions 162 and the highly doped regions 152 represent N-doped regions. In combination with an N-type doping in the well region 102W, the regions 152 may represent the cathode of the substrate diodes 150. On the other hand, the P-doped regions 153 may form a PN junction 102P with the N-type well region 102W and may, thus, act as anodes of the substrate diodes 150. Moreover, as illustrated, in view of reducing contact resistivity of the circuit elements 160 and 150, metal silicide regions 164 and 151, respectively, may be provided in the highly doped regions 162, 152, 153, for instance in the form of nickel silicide and the like. The cathode side, i.e., the region 152, and the anode side, i.e., the region 153, in each substrate diode 150 are separated by a portion of the well region 102W above which portions of the buried insulating layer 103 and the semiconductor layer 104 are provided, as indicated as 103D, 104D. Depending on the overall process strategy, additional materials, such as a gate dielectric material, an electrode material, such as polysilicon, and the like, may be formed above the portions 104D. It should further be appreciated that, in other cases, the portions 104D may represent an insulating material, i.e., the residues of isolation structures that are typically formed in the semiconductor layer 104 in order to laterally delineate corresponding active regions or semiconductor regions, in and above which are formed circuit elements, such as the transistor 160 and the like. For convenience, any such isolation structures are not shown in FIG. 1. Above the device level, i.e., the semiconductor layer 104 and any circuit elements formed therein and thereabove, such as the transistor 160, and above the substrate diodes 150 within the device area 110A, a contact level 120 is provided, which may be considered as an interface for connecting the circuit elements 160, 150 with a metallization system, of which a very first metallization layer 130 is illustrated, for convenience. The contact level 120 comprises one or more appropriate dielectric materials, such as a layer 121 in combination with a layer 122 provided, for instance, in the form of silicon nitride and silicon dioxide, respectively. Additionally, the contact level 120 comprises contact elements 123A, 123B that connect to the doped semiconductor regions 152, 153 on the one hand and to doped semiconductor regions in the layer 104, such as the drain and source regions 162, on the other hand. The contact elements 123A, 123B are provided in the form of any appropriate conductive material, such as tungsten, aluminum and the like, possibly in combination with appropriate conductive barrier materials, such as titanium nitride, titanium and the like.
The metallization layer 130 comprises any appropriate dielectric material or materials, such as low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of 3.0 and less, in combination with any other materials, such as etch stop layers (not shown) and the like. Furthermore, metal lines 133A are provided in the dielectric material 131 so as to connect to the contact elements 123A within the device area 110A, while metal lines 133B connect to the contact elements 123B in the device area 110B. The metal lines 133A, 133B are typically comprised of copper in combination with appropriate conductive barrier materials, such as tantalum, tantalum nitride and the like.
The semiconductor device 100 as illustrate in FIG. 1 may be formed on the basis of the following process strategy. The well region 102W of the crystalline substrate material 102 within the device area 110A may be formed at any appropriate manufacturing stage, i.e., upon forming corresponding active regions in the semiconductor layer 104 by performing masked implantation processes. To this end, a high energy implantation process is performed to implant the well dopant species of the region 102W through the layers 104 and 103 and into the crystalline substrate material 102. In other cases, the substrate window 110A may be formed first by providing an appropriate etch mask so as to etch through the layers 104, 103, thereby exposing portions of the substrate material 102 within the device area 110A, while preserving the portions 104D, 103D. In other cases, a corresponding etch process for exposing portions of the material 102 within the area 110A may be performed after forming corresponding gate electrode structures, such as the gate electrode structure 161 of the transistor 160. Thereafter, any appropriate processes are performed so as to complete the transistor 160, thereby performing appropriate implantation processes for forming the drain and source regions 162 of N-type and P-type transistors, thereby also applying an appropriate masking regime for forming the highly doped regions 152 and 153 of the substrate diodes 150. After any anneal processes for activating dopants and re-crystallizing implantation-induced damage, while also initiating a dopant diffusion, if desired, the metal silicide regions 164, 151 may be commonly formed in the transistor 160 and the substrate diodes 150. Consequently, the circuit elements 160 and 150 may be formed on the basis of substantially the same process sequence, thereby providing a very efficient overall manufacturing flow, while, however, a significant difference in height level between the device area 110A and 110B is generated. The pronounced surface topography caused by this difference in height levels, in turn, may result in significant irregularities in the further processing of the device 100. That is, upon depositing the dielectric material or materials of the contact level, a certain degree of height difference may still exist between the device areas 110A, 110B. That is, typically, the material 121, such as a silicon nitride material, is deposited on the basis of plasma enhanced chemical vapor deposition (CVD) techniques having a more or less conformal deposition behavior. Thereafter, the material 122, for instance in the form of silicon dioxide, is deposited, for instance, by a deposition technique of superior gap filling capability, for instance high density plasma CVD, sub-atmospheric CVD, thereby providing a certain degree of leveling between the areas 110A, 110B, wherein, however, a certain global difference in height level may still exist, even if performing any additional polishing processes for improving the overall surface topography. After providing the dielectric material 122, sophisticated lithography processes are applied in order to form an appropriate etch mask, for instance in the form of a hard mask, a resist mask and the like, which may be used during the subsequent anisotropic etch sequence for etching through the material 122 and finally through the material 121 and into the metal silicide regions 164, 151. Thereafter, the contact openings are filled with the desired conductive material, possibly in combination with a conductive barrier material, and any excess material thereof is removed by chemical mechanical polishing (CMP), wherein process parameters have to be adapted so as to also reliably remove any metal residues in the device area 110A having the reduced global height level. In device generations including transistor elements of approximately 60 nm gate length, a corresponding difference in height level, as indicated by 110H, has been taken into consideration by providing the dielectric material 122 with increased thickness so as to generally take advantage of the non-conformal deposition behavior, possibly in combination with the leveling effect of a CMP process, while the removal of any excess material of the contact elements 123A, 123B has been performed on the basis of process parameters in which a high degree of "dishing" is achieved, i.e., a superior removal of metal compared to the dielectric material 122. In this manner, the excess metal of the contact level may be removed efficiently from within the device area 110A, which, however, may result in a height level difference 110H of approximately 60 nm and even more. Thereafter, the metallization layer 130 is formed by depositing the dielectric material 131 based on any appropriate process strategy, followed by the patterning of the material 131 based on sophisticated lithography techniques. Next, any appropriate conductive barrier material (not shown) is deposited, followed by the deposition of the actual fill material, such as copper and the like. Thereafter, any excess material is removed by appropriate planarization techniques, such as CMP, thereby also requiring the removal of the conductive materials within the device area 110A, which may have a different height level (110D). Consequently, upon reliably removing any metal residues from within the device area 110A, a significant reduction in thickness of the metallization layer 130 in the device area 110B may result, which may, thus, reduce performance of any metal lines 133B provided therein.
Upon further scaling the size of the individual circuit elements, lateral feature sizes and generally the thickness of the metallization layer 130 also has to be adapted. For example, in technologies using a gate length of 40 nm and less, a thickness of the metallization layer 130 may be of a similar order of magnitude as the height differences 110H or 110D, which would, thus, lead to a non-acceptable reduced thickness of the metallization layer 130 in the device area 110B after having reliably removed the excess material in the device area 110A. On the other hand, further increasing the thickness of the dielectric material 122 of the contact level 120 so as to further reduce the height difference 110H may not be a promising option, since significant variations may occur during the complex patterning process for forming the contact elements 123A, 123B due to, for instance, the significant height differences at a generally increased etch depth in the contact level, thereby contributing to significant substrate-to-substrate variations. Consequently, in the conventional approach, typically, a compromise of CMP parameters and thickness of the levels 120 and 130 may be applied, while, however, a significant probability exists that any metal residues may remain in the device area 110A after completing the corresponding polishing process. In this case, leakage paths or short circuits between metal lines 133A may be created, thereby at least reducing performance of the substrate diodes 150 or causing a complete failure of one of these devices. Since reliable temperature data may strongly depend on the diode characteristics, a reduction in the reliability or a degradation of performance of the substrate diodes may contribute to significant yield losses and/or reduced functionality of the semiconductor device 100.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.

SOI semiconductor device with reduced topography above a substrate window area


A printer includes a print document receiving unit that receives document data, a document analysis unit that generates output document data from the document data, a print mode determination unit that selects a print mode to be executed by the document analysis unit, a layout processing unit that processes the output document data, and a print execution unit that executes printing. The document analysis unit has a serial print mode, a batch print mode, and a partial serial print mode. The print mode determination unit switches the print modes according to a streamable attribute value or a memory usage.

1. Technical Field
The present invention relates to a document processing of a structured document (XML) in an embedded apparatus, such as a printer or the like.
2. Related Art
As one of markup languages for describing meanings and structures of documents and data, XML (Extensible Markup Language) is known. In addition, there is known SVG (Scalable Vector Graphics) that is an XML-based language for describing 2D vector images and the like. The SVG is released as W3C (World Wide Web Consortium) recommendation. The SVG specifications include the SVG Print specification that defines processing rules in an environment, such as a printer, in which documents described with SVG are printed (Non-Patent Document 1).    [Non-Patent Document 1] SVG Print(http://www.w3.org/TR/SVGPrint/)
In the SVG Print document, a page element is used to define the range of a page in a print medium output from an apparatus, such a printer or the like. In addition, the content of the document (hereinafter, referred to as document fragment) can be structured so as to be shared with a plurality of pages. Accordingly, for example, a use element can be used to assign such that a document fragment of another page is referred to. During rendering, a document fragment of a reference destination is used as data of a page of a reference source and then processed.
A streamable attribute can be defined in an outermost SVG element in the SVG Print document. The streamable attribute is behind an element assigning a reference to indicate whether or not a document fragment (resource) to be referred to exists.
Specifically, when the streamable attribute value is true, it means that, even if an element assigning a reference exists, no document fragment to be referred exists behind the element. That is, even if an element assigning a reference appears, the reference can be resolved without referring to an element behind the corresponding element. Accordingly, it is not necessary to buffer the entire document in order to resolve the reference.
Meanwhile, when the streamable attribute value is false, it means that, according to an element assigning a reference, a document fragment to be referred to exists behind the corresponding element. That is, when an element assigning a reference appears, the reference may not be resolved. Accordingly, it is necessary to buffer the entire document in order to resolve the reference.
However, among the embedded apparatuses, such as printers and the like, for example, there may be an apparatus that has insufficient memory resources, memory space, or print processing performance. In such an apparatus, when a large volume of an SVG Print document, in which a streamable attribute value is set to false, is printed, buffering of the entire document becomes load, and the memory resources may be depleted or throughput may be markedly deteriorated. In addition, when such an apparatus cannot buffer the entire document, printing of the entire document may not be executed.
An advantage of some aspects of the invention is that it provides a technology capable of, in an apparatus, such as a printer or the like, which prints a SVG Print document, reducing the usage of memory resources of a print processing by switching print modes, improving throughput of the print processing according to the utilization of memory resources or the number of pages of the document, and even if the entire document cannot be buffered, allowing the print processing to be continued.


A high pressure hydraulic fitting (300) includes a body (302) having a central passage (322), a channel (304), a threaded section (314), and an extension section (310), wherein the threaded section (314) is disposed between the channel (304) and the extension section (314), and wherein the central passage (322) fluidly connects a first distal end (303) with a second distal end (316) of the body (302). A first o-ring (306) is in the channel (304). A locking nut (324) is engaged to the body (302). The locking nut (324) has an internal threaded section (326) that is arranged to mate with the threaded section (314) on the body (302).

High pressure fittings for hydraulic applications are known. In some applications having vibratory operational environments, for example, fittings used on internal combustion engines, the known fittings are prone to failure due to fractures and sealing issues. Standard hydraulic fitting designs for hydraulic systems are often not adequate for use on diesel engines due to special high loading conditions encountered only on diesel engines. Examples of known fittings can be found in standards maintained by the Society of Automotive Engineers (SAE). For example, fittings conforming to the SAE J-2244 standard may fail due to exposure of the threads to high pressure oil. Fittings conforming to the SAE J-2337 standard may fail due to high loads imparted to the fitting from engine vibrations, hose connections, hose loads, and hydraulic pressures.
Methods used in the past to improve performance of fittings include use of high strength materials and/or design features such as fillets intended to reduce or eliminate stress risers. One example of a high pressure fitting may also be found in U.S. Pat. No. 5,110,160 by Brozovic, published on May 5, 1992, the contents of which are incorporated herein in their entirety by reference. Another example is a fitting design that conforms to the SAE J-2337 standard. Such fittings are partially effective in withstanding operation on a diesel engine environment, but are complex and costly.
Accordingly, there is a need for a design for a high pressure hydraulic fitting that is not prone to the failures experienced by the known designs, and is simple and cost effective.

International Engine Intellectual Property Company, LLC


In a machine for feeding a partially formed carton in a conveying direction and reorienting the carton for completion, a turn-assist mechanism and related methods help to ensure that proper turning of a skewed carton is achieved in a reliable and highly efficient manner. The mechanism comprises a bed for supporting the carton, which may be skewed from a first orientation in which one of the side flaps could be folded and sealed in an upstream procedure. A conveyor includes at least one lug with a portion generally elongated in a direction transverse to the conveying and vertical directions for engaging a trailing end of the carton. This engagement helps to turn the carton to a second, squared orientation approximately 90° rotated from the first orientation so that the forming operation may be completed, such as by folding and sealing any other side flaps.

Machines for feeding and closing partially formed and filled cartons are well-known in the art. For many years, the most successful approach for feeding cartons along an entire carton forming line, including for closing and sealing the lid and flaps, was performed by conveyors in-line with fixed lugs or flights mounted on chains, as shown in U.S. Pat. No. 3,267,637 to Baker, which is incorporated herein by reference. These chains moved the cartons forward by pushing along the rear or trailing end. At various transition locations along the carton forming line, it was necessary to turn the carton about its vertical axis while continuing to feed the carton forward. Usually, this turning motion was through 90 degrees and was performed in one fashion or another, such as by using a plurality of spaced belts running at different speeds, a kick-out mechanism, or the like.
A modern and commercially successful approach to continuous carton forming is found in commonly assigned U.S. Pat. No. 5,660,262 to Landrum et al., the disclosure of which is also incorporated herein by reference. In this arrangement, infeed belts frictionally engage the top and bottom surfaces of the carton for conveying while the front flap is sealed. This eliminates the need for pre-folding the trailing end flap to avoid damaging it, as is required when using upstanding lugs. After the front flap is sealed, the carton enters a zone with a kick-out lug to engage a leading side of the carton, retard its motion and cause it to start to turn. A plurality of spaced parallel belts running at different speeds then continue to reorient the carton, such as with turning through 90° in the same plane. The turned carton is then received and conveyed by spaced belts while the opposite side flaps are folded and sealed. The carton is thus formed in a continuous fashion without stopping or changing the conveying direction.
While this type of approach has enjoyed considerable commercial success, the use of belts running at differential speeds to turn the carton during feeding increases the complexity of the machine, as well as the resulting footprint. Maintenance costs are also increased in view of the need for ensuring that the speed of the belts is proper for turning the carton in the desired fashion. Modern times also demand faster throughput than can be afforded using frictional engagement alone to accomplish turning.
Accordingly, a need exists for an improved carton feeding and forming machine that overcomes the foregoing limitations and others.

In-line carton feeding and forming machine with carton lug conveyor and related methods


A memory device comprises a memory array having corresponding first access control bits to control access thereto. A second set of access control bits is provided to control write access to the first access control bits. The memory array is divided into memory blocks, each block having a corresponding access control bit. At least one such block is further subdivided into pages, each page having a corresponding control bit.

Electrically erasable and programmable read-only memories (EEPROM) are used wherever reprogrammable nonvolatile memory is required. Typically, writing to such devices requires asserting a write enable signal to the chip at the same time the write operation takes place. This prevents inadvertent writing of the memory.
Data contained in an EEPROM, however, is susceptible to various sources of corruption. For example, transients due to powering up and powering down an EEPROM present an opportunity for data corruption. EEPROMs typically find application in harsh industrial environments, thus exposing the devices to noise spikes on the control lines. It is therefore desirable to provide enhanced protection against inadvertent writes, in addition to the simple write enable signaling presently used.
EEPROMs also find use in situations where controlled read access is desirable. For example, smart cards incorporate EEPROM-type memory which require some form of protection against unauthorized access. Such cards are used in personal banking applications, health delivery services, and so on where privacy of the information contained in the card is fundamental.
EEPROMs can be found in radio frequency identification devices (RFIDs), where the memory device is used to store information identifying the object to which an RFID tag is attached. Typically, RFID tags can be written in order to store information in addition to an identifier. RFID tags usually have some sort of write protection capability and read access control. Such read access control is currently implemented by providing password mechanisms which gate access to the memory incorporated in the tag, resulting in a bulky device.
What is needed is a strategy which prohibits reading some or all of the information contained in a memory device, as well as write access to the memory. It is desirable to avoid having additional circuitry to implement such capability, thus permitting smaller and more compact applications which require read access protection.

Memory device having programmable access protection and method of operating the same


A read/write head for a disk drive having a magnetoresistive (MR) read element and an inductive write element suitable for perpendicular recording of data onto a disk having a media layer in which the data is stored perpendicularly to the planar surface of the disk and a soft underlayer (SUL) underneath the media layer to provide a low reluctance return path for the magnetic recording field. The write element is formed on top of a substrate, with the read element on top of the write element on the other side of the write element from the substrate. A pancake write coil coils around a magnetic via that either connects to a write shield adjacent to the read element in one embodiment or directly to one of the read shields in a second embodiment.

In hard disk drives, data is written to and read from magnetic recording media, herein called disks. Typically, one or more disks having a thin film of magnetic material coated thereon are rotatably mounted on a spindle. A read/write head mounted on an actuator arm is positioned in close proximity to the disk surface to write data to and read data from the disk surface.
During operation of the disk drive, the actuator arm moves the read/write head to the desired radial position on the surface of the rotating disk where the read/write head electromagnetically writes data to the disk and senses magnetic field signal changes to read data from the disk. Usually, the read/write head is integrally mounted in a carrier or support referred to as a slider. The slider generally serves to mechanically support the read/write head and any electrical connections between the read/write head and the disk drive. The slider is aerodynamically shaped, which allows it to fly over and maintain a uniform distance from the surface of the rotating disk.
Typically, the read/write head includes a magnetoresistive read element to read recorded data from the disk and an inductive write element to write the data to the disk. The read element includes a thin layer of a magnetoresistive sensor stripe sandwiched between two magnetic shields that may be electrically connected together but are otherwise isolated. A current is passed through the sensor stripe, and the resistance of the magnetoresistive stripe varies in response to a previously recorded magnetic pattern on the disk. In this way, a corresponding varying voltage is detected across the sensor stripe. The magnetic shields help the sensor stripe to focus on a narrow region of the magnetic medium, hence improving the spatial resolution of the read head.
The write element typically includes a coil of wire through which current is passed to create a magnetic field that can be directed toward an adjacent portion of the disk by a ferromagnetic member known as a write pole. While it is known that the write element can be arranged to either store data longitudinally or perpendicularly on the disk, most, if not all, commercial disk drives to date have utilized longitudinal recording arrangements. Although perpendicular recording techniques have the potential to allow for higher densities of recorded information, longitudinal recording is used in all current products for historical reasons. An early perpendicular recording technique is disclosed in U.S. Pat. No. RE 33,949, the contents of which are incorporated herein by reference.
The '949 patent discloses a perpendicular or vertical write head with a write pole section, a downstream shield section, and a pancake coil surrounding the write pole section to generate magnetic flux therein. The shield section is disclosed to have a surface facing toward the media that is many times larger than a similarly-oriented face of the write pole. The media is disclosed to include two layers, an upper layer closer to the head having perpendicular uniaxial anisotropy and a lower layer having low magnetic reluctance (now known as the Soft Under Layer (SUL)). A high write field can then be produced between the write pole and the SUL to record information in the upper layer of the media. The write flux returns through the SUL to the downstream write shield. The return field for this design was predicted to be much lower than the write field because of the larger area of the face of the write shield as compared to the face of the write pole. It was recognized that the return field needed to be sufficiently low so as not to erase the downstream information/data under the write shield.
It is believed that to date all read/write heads in disk drives have featured sliders with a substrate with the read element built on top thereof, and then a write element produced on top of the read element. While this geometric arrangement is completely standard in the industry, it does have certain disadvantages. One class of disadvantages relates to manufacturing processes. It turns out that the read element has the potential to be more adversely affected by subsequent manufacturing processes than does the write element. For example, in producing the read and write elements it is commonly necessary to anneal magnetic materials therein by subjecting them to high temperatures and high magnetic fields for an extended period of time. Modern read elements are limited in the extent to which they can withstand typical annealing temperatures and magnetic fields. Because of this, there are significant constraints that are placed on the manufacturing processes that are subsequent to the read element being deposited onto the substrate. These significant constraints can impact the ability to manufacture the write element in the desired manner.
Another class of disadvantages of placing the read element under the write element relates to heat distribution. It turns out that the write element is the greatest source of heat in the read/write head. The two routes most commonly used for dissipating heat from the head are either through the slider or through the media (the disk surface). While design efforts continue to be made to conduct as much of the heat as possible through the media, the primary source of heat dissipation is through the slider. Unfortunately, as the heat is conducted through the slider, a portion of it passes through the read element and causes the read element to increase in temperature by 20°-30° C. or more. This elevation of the read element temperature ends up reducing the lifetime mean time to failure of the read element, since the mean time to failure falls exponentially with increasing temperature.
Some designs for read/write heads include internal diffusers to directly conduct heat along a particular path from the write element to the substrate, such as via a flat metal plate. While this has somewhat reduced the elevation in read element temperature, this approach has other disadvantages. First of all, due to the extra metal materials in the read/write head, the expansion of the various portions of the read/write head with temperature is more significant and this can result in pole tip protrusion, which is undesirable. Furthermore, having the large metal plate in the read/write head can degrade the write element performance due to eddy currents that are formed.
Another class of disadvantages resulting from the read element being located under the write element relates to electrical coupling, also known as read-write coupling. This is the capacitive coupling that occurs between the writer and the reader due to the electrical fields produced by the write element. In turn, this induces capacitive coupling across the read element. Since reading and writing do not occur simultaneously, the induced voltage across the read element tends to dissipate with time and does not appear to significantly affect performance during read operations. It does appear, however, that prolonged exposure of the read element to this electrical field can degrade the read element in terms of decreasing its lifetime or causing damage thereto.
Another class of disadvantages relating to the conventional reader under writer design relates to magnetic issues. With the commonly-used unshielded monopole write structure, placing the writer on top of the reader does not cause significant magnetic difficulties. However, the unshielded pole writer of the previously-discussed '949 patent has significant performance advantages due to higher field gradient which allows for higher linear bit density and it has a larger longitudinal field component which improves the effective write field strength which allows for the use of higher coercivity media with finer grains. Simply placing such a writer on top of a shielded GMR reader, however, results in the generation of excessive field under the writer shield because of flux coupling between the writer structure and the reader shields. This coupling can be reduced to an optimum level by placing a bucking coil between the writer structure and the reader structure as is taught in a commonly-owned U.S. patent application filed on the same day herewith and given U.S. patent application Ser. No. 10/701,909, entitled "Shielded Pole Writer", the contents of which are incorporated herein by reference. This bucking coil is in series with the write coil and adds extra resistance and therefore power dissipation, thus contributing to heating and pole tip protrusion.
It is desirable to design/provide a read/write head which does not suffer from the above drawbacks. It is against this background and a desire to improve on the prior art that the present invention has been developed.


An antifuse (40, 80, 90′) comprises, first (22′, 24′) and second (26′) conductive regions having spaced-apart curved portions (55, 56), with a first dielectric region (44) therebetween, forming in combination with the curved portions (55, 56) a curved breakdown region (47) adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region (42) is desirably provided adjacent the breakdown region (47) to inhibit heat loss from the breakdown region (47) during programming. Lower programming voltages and currents are observed compared to antifuses (30) using substantially planar dielectric regions (32). In a further embodiment, a resistive region (922) is inserted in one lead (92, 92′) of the antifuses (90, 90′) with either planar (37) or curved (47) breakdown regions to improve post-programming sense reliability.

The term "fuse" is used in the art to identify a device that initially (before) has low impedance and, when exposed to a current above a predetermined threshold, switches to a high impedance final (after) state. In its simplest embodiment, a small section of conductor melts when exposed to excess current, thereby interrupting the circuit of which it is a part. The term "antifuse" is used in the art to describe a device whose behavior is substantially the opposite of a fuse, that is, it initially (before) has high impedance and, when exposed to a voltage above a predetermined threshold, switches to a low impedance final (after) state. In its simplest embodiment, a thin insulating dielectric sandwiched between two conductors breaks down when exposed to a "programming" voltage above a predetermined threshold, thereby forming a conductive path through the dielectric so that the device thereafter exhibits much lower final impedance. With an antifuse, it is not necessary that the initial and final impedances be infinity and zero, respectively, only that they are substantially different. Accordingly, as used herein with respect to antifuses, the terms "open" or "OFF" and "closed" or "ON" are intended to refer, respectively, to the initial high impedance state and the final lower impedance state and not to imply that these states have infinite and zero impedance.
Antifuses are much used in modern electronics, especially in connection with integrated circuits (ICs), to provide substantially non-volatile memory. For example, an array of antifuses may be programmed during or after manufacture of an electronic circuit to store certain information or commands within the electronic circuit or the memory portion thereof. The stored information may be an identifying serial number or other unique label, or may be the binary code for a software routine, or may determine which parts of a particular circuit are active, or what conversion factor should be used in a calculation or any number of other functions where non-volatile memory or state information is needed.
It is important that the antifuse be easy to manufacture, be reliable in operation, be easily and reliably programmed and consistently sensed, and at the same time be compatible with the other elements that may be part of the same circuit or device, especially when they are manufactured together as for example in an integrated circuit (IC) or other common electronic assembly. It is known to use planar metal-oxide-semiconductor (MOS) structures to form antifuses. These are attractive because they can be formed by the same manufacturing technology used for forming associated metal-oxide-semiconductor-field-effect-transistors (MOSFETs) in complex ICs. However, difficulties still remain in obtaining antifuses of optimum properties using manufacturing technologies compatible with the active devices needed for the IC of which both are a part. Accordingly, there is an ongoing need for improved antifuse structures and manufacturing methods compatible with advanced integrated circuit (IC) technology.


An impact detecting device includes a first impact detecting portion, a determining portion and an informing portion. The first impact detecting portion detects an impact applied to an object equipped to a vehicle. The determining portion determines that the object has received the impact when a detection result of the first impact detecting portion is greater than a first impact determination threshold. The informing portion informs that the object has received the impact, when the determining portion determines that the object has received the impact.

As an example of an impact detecting device for detecting an impact applied to an object equipped to a vehicle, a publication of Japanese Patent No. 4962863 (JP 4962862 B2) discloses an impact recording body for a fuel tank.
The impact recording body is made of austenite steel that creates phase transformation upon reception of an impact. The impact recording body covers a fuel tank. When an impact is applied to the fuel tank, the phase transformation of the austenite steel occurs in the impact recording body, and martensite is generated by the phase transformation of the austenite steel. The magnitude of the impact is detected by measuring the quantity of the martensite using a permeameter. Therefore, it is possible to determine whether the fuel tank has received an impact which causes damage to the fuel tank, based on the quantity of the martensite.
In the method where the impact applied to the fuel tank is detected using the impact recording body, it is necessary to measure the quantity of martensite using the permeameter. Therefore, it is difficult to immediately know whether the fuel tank has received the impact. Further, even if the fuel tank has received an impact that causes damage to the fuel tank, a user will not know such damage until a periodic inspection.


A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

Radio receivers are used to receive an incoming radio frequency (RF) signal, process, and downconvert the signal to a lower frequency, e.g., an intermediate frequency (IF) or a baseband frequency, where the signal can be further processed to thus output an audio signal. In typical receivers, a signal path includes multiple components, both in an RF portion of the signal path as well as lower frequency portions of the signal path such as an IF and/or baseband portions. Because an incoming signal may be of relatively low power, some of these components may provide gain to the signal. Many receivers include gain elements both at RF as well as at lower frequencies.
To control these gain elements, many receivers include some type of automatic gain control (AGC) circuitry. AGC circuitry is often used in receivers for maximizing the usable range of input signal levels to a receiver signal path. Such gain control circuitry typically analyzes the level of an incoming signal such as via a peak detection and acts to automatically adjust the gain based on the detection. Other systems use analog circuitry that estimates the root mean square (RMS, also referred to as average) value of the incoming signal. However, both peak detectors and RMS detectors are relatively complicated devices and have high levels of tolerance requirements.
Typically the gain control in such AGC circuits occurs on a schedule determined by analog averaging of the detector signals, or on a relatively simple set of fixed rules applied to the detector signals. While such AGC schemes can work well in many situations, they suffer from drawbacks, including excessive power consumption, possible signal degradation due to unnecessary updates to the gain control elements, poor use of the dynamic range of the signal path circuits, and so forth. An additional complication is that different circuit elements respond differently to overload conditions, with open-loop circuits such as low noise amplifiers (LNAs) and mixers typically showing more gradual degradation as overload level increases, while closed-loop circuits such as programmable gain amplifiers (PGAs) typically show very abrupt and rapid degradation as overload level increases. Getting the best performance from a signal chain therefore requires an AGC scheme that is aware of these characteristics and can adjust gains appropriately. Furthermore, for multi-band receivers, because of the different types of encodings and modulation schemes for different bands, a single type of detector may not be applicable to multiple bands.
For example, for an FM band a constant envelope signal is received and thus has a relatively low (or zero) peak-to-average ratio (PAR). Therefore for receiving an FM signal an AGC scheme based on peak level will perform relatively similarly to an AGC scheme based on RMS level. However, certain digital bands such as digital audio broadcast (DAB) radio have an almost Gaussian distribution with a high PAR value. In this case an AGC scheme based on peak level will perform very differently from an AGC scheme based on RMS level. Accordingly, a single gain control hardware and algorithm for multiple bands can leave headroom or suffer overloading of a receiver.
For example, if a gain control system designed for an FM signal based on peak level is used for DAB reception, a very low range RMS signal will occur, losing dynamic range of the signal chain open-loop circuits. If the FM gain control is based on RMS signal level, then in DAB reception, very high range peak signals will occur, causing severe overload of the signal chain closed-loop circuits.
In contrast, if a gain control system designed for DAB signals based on peak level is used for FM reception, a very high range RMS signal will occur, causing severe overload of the signal chain open-loop circuits. If the DAB gain control is based on RMS signal level, then in FM reception very low range peak signals will occur, losing dynamic range of the signal chain closed-loop circuits.


An organic electroluminescence device includes: an emitting region provided between a cathode and an anode; and a hole transporting zone provided between the anode and the emitting region, in which the hole transporting zone includes at least a first anode side organic layer and a second anode side organic layer, the first anode side organic layer is in direct contact with the second anode side organic layer, a total film thickness of the hole transporting zone is in a range from 20 nm to 80 nm, the first anode side organic layer contains no compound contained in the second anode side organic layer, the first anode side organic layer contains a first organic material and a second organic material, the first organic material is different from the second organic material, and a content of the first organic material in the first anode side organic layer is less than 50 mass %.

An organic electroluminescence device (hereinafter, occasionally referred to as "organic EL device") has found its application in a full-color display for mobile phones, televisions and the like. When a voltage is applied to the organic EL device, holes are injected from an anode and electrons are injected from a cathode into an emitting layer. The injected electrons and holes are recombined in the emitting layer to form excitons. Specifically, according to the electron spin statistics theory, singlet excitons and triplet excitons are generated at a ratio of 25%:75%.
Studies for improving performance of an organic EL device has been made, for instance, in Literature 1 (International Publication No. WO2020/189316), Literature 2 (JP 2019-161218 A), and Literature 3 (International Publication No. WO2011/093056). The performance of the organic EL device is evaluable in terms of, for instance, luminance, emission wavelength, chromaticity, luminous efficiency, drive voltage, and lifetime. One of the problems with the organic EL device is low light-extraction efficiency. Especially, decay due to the reflection caused by the difference between refractive indices of adjacent layers is a major factor in reducing the light-extraction efficiency of the organic EL device. An arrangement of the organic EL device provided with a layer formed from a low refractive index material has been proposed in order to reduce the above effect.

Organic electroluminescence device, light emitting device, organic electroluminescence display device and electronic device


Provided is a mobile communication terminal comprising: a display unit including a touch screen capable of receiving user's input through the touch screen for controlling the mobile communication terminal; a memory unit; a communication unit; and an activation sensing unit, wherein the activation sensing unit detects a change from an inactive state of the mobile communication terminal to an active state of the mobile communication terminal, wherein the inactive state is defined that the display unit being turned off while the mobile communication terminal being communicable and the active state is defined that the display unit being turned on while the mobile communication terminal being communicable, wherein the mobile communication terminal performs a predetermined operation by an application of the mobile communication terminal when the activation sensing unit detects the change from the inactive state to the active state.

1. Field
The disclosure relates to a method and mobile communication terminal for performing a specific function when a mobile communication terminal is activated, and more particularly to a method and mobile communication terminal for performing various functions according to the number of presses or a press time of a button for switching from an inactive state to an active state.
2. Description of the Related Art
Recently, various terminals, for example, such as smart phones, mobile phones, personal digital assistants (PDAs), and web pads, having not only communication functions but also various other functions have come into wide use. These terminals have rapidly been generalized because not only can an environment identical or similar to a desktop computer be implemented anytime and anywhere on the above-described terminals, but they also include a telephone function.
At present, in order to operate a corresponding function among various functions included in a terminal such as those described above, a certain operation should be performed in a state in which the terminal is in an active state, that is, in a state in which a display is turned on. In addition, in order to add a certain function, an interface or button for performing the function should be added to the terminal. For example, it is possible to transmit a rescue signal indicating an emergency or urgent situation by pressing an emergency button only when the emergency button for the urgent situation is separately added.
On the other hand, users of the terminals described above perform operations of habitually taking out and activating the terminals on the move or in a standby state while carrying the terminals.

This patent is subject to a terminal disclaimer.

Method, mobile communication terminal and computer-readable recording medium for performing specific function when mobile recording medium for performing specific function when mobile communication terminal is activated


A hay rake tooth assembly for use with a mounting clip on a hay rake wheel. The hay rake tooth assembly has a tine with a ball-shaped retaining member that is configured to permit a shaft of the tine to move along the length of the difference in diameter between the shaft and a tine opening of the mounting clip in which is the tine is assembled.

This invention is directed towards a hay rake tooth assembly. More specifically, and without limitation, this invention relates to an improved tine for a hay rake tooth assembly.
Both hay rake tooth assemblies and mounting clips for hay rake teeth assemblies are well known in the art. A conventional mounting clip has an elongated member with a central portion and two widened sections on each end of the elongated member. The central portion has legs or flanges that engage the sides of a wheel rim to prevent the clip from turning with respect to the rim of a hay rake wheel.
To provide sufficient strength to prevent turning during raking operations, conventional mounting clips are 6.5 inches long. This length provides a spacing between hay rake teeth assemblies of 5.25 inches where a wheel having a diameter of 60.59 inches has approximately 19 clips and 38 hay rake teeth assemblies. Under normal raking conditions, this design is acceptable. However, when used in short hay or shredded crops, an unacceptable amount of crop passes between the wider teeth and is left in the field. In heavy, wet crops, conventional rakes jump over the crop leaving hay because they lack sufficient raking power.
One advancement that has occurred is disclosed in U.S. Ser. No. 14/254,281 from which the present application claims priority. The inventive mounting clip disclosed therein allows for a greater number of mounting clips to be attached around the diameter of the rim of the hay rake wheel with greater strength due to the presence of flanges of the clips.
Despite this advancement, other deficiencies exist. In conventional assemblies, the tine extends through the central portion of the mounting clip and is held in place by a rubber molding and the hole in the mounting clip in which the tine passes through. In this arrangement, the hole weakens the structural integrity of rubber molding. Since the position of the tine is retained only by the molding, when the molding fatigues, or is stressed beyond its limitations, the molding breaks and the tine is released into the field where the tine can puncture an implement tire, be run through a field chopper, or interfere with production in some other way.
One advancement in the art is disclosed in U.S. Pat. No. 10,412,892, which is incorporated by reference herein in its entirety. The mounting clip is improved by having swedged or cupped portions positioned above the openings for the tine, which extend upwardly from the mounting clip. The tine in the advancement have an enlarged portion that is received within the swedged portions, whereas the smaller portion of the tine passes through the openings. In this way, the enlarged portions are retained in the mounting clip when assembled.
Despite these advances and others, problems still remain. More particularly, conventional hay rake tooth assemblies and their advancements use a tine that has a flat, triangular, or conical retaining member that is retained between the rim of the hay rake wheel and the mounting clip. In these arrangements, the shape of the tine results in the tine being rigidly held in place due to the inability of the tine to change positions as the shape inhibits movement leading to substantial wear and eventual breakage of tines. Therefore, it is a primary objective of the present invention to provide a hay rake tooth assembly that improves upon the art.
Another objective of the present invention is to provide a hay rake tooth assembly that is stronger and more resilient.
Another objective of the present invention is to provide a hay rake tooth assembly that better retains a tine under stress or fatigue.
These and other objectives, features, and advantages of the invention will become apparent from the specification and claims.


This invention relates to improved wound dressings that are adapted to being readily sized to fit the shape of the wound so that healing is promoted. In particular, the present invention is directed to a scored spiral wound dressing. More particularly, this invention relates to a spiral wound dressing having superior absorption properties and which is capable of swelling in the presence of wound fluid to closely fit the wound.

It is recognized that providing a dressing that promotes healing without scab formation is desirable in wound treatment. In addition, the removal of excess wound exudates is important to promote wound healing and to prevent the breakdown of skin surrounding the wound due to maceration.
Many different types of dressings are commercially available. These commonly include dressings containing gauze, foams, sponges, cotton, wools or other fibrous materials. Gauze and other fibrous materials, while capable of absorbing wound exudate can create problems in wound care because of the tendency of these fibrous materials to be engulfed or entrapped by the newly formed tissue that grows into the dressing. As a result, when these fibrous wound dressings are removed newly formed tissues can be damaged and torn. The other commonly used materials for removing exudates in wound dressings include granules and pastes. Similarly, these are frequently difficult to remove from the wound after hydration by the exudate and typically require flushing with a liquid. Further, these materials are limited in the amount of exudate they can absorb.
U.S. Pat. No. 4,551,490 describes an adhesive composition useful with ostomy and incontinent appliances and which has also been used in adhesive bandages. The composition consists of a homogeneous mixture of polyisobutylene, styrene random or block-type copolymer, mineral oil, soluble hydrocolloid gum, water swellable cohesive strengthening agent and a tackifier. This composition has limited exudate absorption capacity and requires a tackifier for its intended use as an adhesive composition.
U.S. Ser. No. 990,719 filed Dec. 15, 1992 which is commonly owned by the assignee of the present invention teaches improved wound fillers having high absorption capabilities. The wound filler is preferably comprised of from about 25% to 75% by weight of a polymer matrix and 25% to 75% by weight absorbing powers. The disclosures of this application are incorporated herein by reference.