A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

1. Field of the Invention
The present invention relates to a timing signal generating circuit, a semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied and a signal transmission system and, more particularly, to a timing signal generating circuit aimed at increasing the speed of signal transmission between LSI (Large Scale Integration Circuit) chips or between a plurality of devices or circuit blocks within one chip.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has improved rapidly; in particular, the performance of dynamic random access memories (DRAMs) and processors has improved dramatically year by year.
Namely, processor performance has increased dramatically in terms of speed, whereas DRAM performance improvements have been dramatic primarily in terms of storage capacity. However, the improvement in DRAM speed has not been so dramatic as the increase in storage capacity, as a result of which a gap between the speed of DRAMs and that of processors has widened and, in recent years, this speed gap has been becoming a bottleneck in boosting computer performance.
Further, with increasing chip size, not only signal transmission between the chips but also the speed of signal transmission between devices and between constituent circuits (circuit blocks) within one LSI chip (semiconductor integrated circuit device) is becoming a major limiting factor in chip performance.
On the other hand, if the speed of signal transmission between LSI chips is to be extremely increased, for example, it is required that signal receiving circuits be made to operate with correct timing to the signals, and techniques such as DLL (Delay Locked Loop) and PLL (Phase Locked Loop) have been known for addressing this requirement.
In addition, the need has arisen for high-speed signal transmission between LSI chips, for example, between a DRAM and a processor (logic circuit), or between a plurality of devices or circuit blocks within one LSI chip. There is, therefore, a need for a timing signal generating circuit that can generate with simple circuitry and with high accuracy a plurality of timing signals, having prescribed phase differences, synchronous with a reference clock.
Furthermore, with increasing operating speeds of LSIs, there is also a need for a signal transmission system that can perform large-capacity signal transmission at high speed between LSIs and between apparatuses constructed with a plurality of LSIs.
The prior art and the problems associated with the prior art will be described in detail later with reference to drawings.
An object of a first aspect of the present invention is to provide a semiconductor integrated circuit device that permits timing design with relatively high adjustment accuracy to be done in a short period. An object of a second aspect of the present invention is to provide a signal transmission system capable of high-speed, error-free signal transmission without being affected by skew on each signal line. An object of a third aspect of the present invention is to provide a timing signal generating circuit that can generate with simple circuitry and with high accuracy a plurality of timing signals, having prescribed phase differences, synchronous with a reference clock.
According to the present invention, there is provided a semiconductor integrated circuit device having a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core, wherein the timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle only for a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks.
The timing adjusting circuit may include a logic gate for enabling the generated DRAM control signal for output only for a period during which the control command is issued. The semiconductor integrated circuit device may include an MPU that accesses the DRAM. The timing adjusting circuit may include a first counter for counting the first clock; a second counter for counting the second clock; and a timing buffer circuit for generating the DRAM control signal by setting the control command active for a period starting from the time that the count value of the first counter reaches a first value and lasting until the time that the count value of the second counter reaches a second value.
The first counter and the second counter may be loop counters. At least, either one of the first and second counters may include a selection circuit for accepting multiple bit outputs from the counter, and for selecting one bit output out of the multiple bit outputs for output in accordance with a selection control input value; and a timing setting section for storing and outputting the selection control input value.
The timing setting section may be a register. The output of the timing setting section may be set before shipment in accordance with production process conditions. The output of the timing setting section may be set before shipment in accordance with required operating speed.
The timing adjusting circuit may include a common counter for counting one of the n clocks, or the reference clock, as a common clock; a first logic gate for enabling one of the n clocks for output only for a period during which the count value of the common counter shows a first value; a second logic gate for enabling one of the n clocks for output only for a period during which the count value of the common counter shows a second value; and a timing buffer circuit for generating the DRAM control signal by setting the control command active for a period starting from the time that the output of the first logic gate becomes active and lasting until the time that the output of the second logic gate becomes active.
The common counter may be a loop counter. The common counter may include a selection circuit for accepting multiple bit outputs from the counter, and for selecting one bit output out of the multiple bit outputs for output in accordance with a selection control input value; and a timing setting section for storing and outputting the selection control input value.
The semiconductor integrated circuit device may include a logic gate for supplying the common clock to the first counter only for a period during which the control command is issued. The command decoder may include a logic gate for enabling the first value indicated as the count value of the first counter for output to the timing buffer circuit only for the period during which the control command is issued.
The semiconductor integrated circuit device may include a selection circuit for selecting one of the n clocks in accordance with a selection control input value and for supplying the selected clock as a clock to the first logic gate or the second logic gate, and a timing setting section for storing and outputting the selection control input value. The timing setting section may be a register. The output of the timing setting section may be set before shipment in accordance with production process conditions. The output of the timing setting section may be set before shipment in accordance with required operating speed.
According to the present invention, there is also provided a timing adjusting circuit for generating n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and for generating a control signal by being set in an active state in a prescribed operation cycle only for a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks.
Further, according to the present invention, there is provided a signal transmission system for transmitting and receiving signals using a plurality of signal lines, comprising a timing adjusting unit for adjusting the amount of signal delay caused during the transmission and reception of the signals in accordance with skew on each of the signal lines, thereby adjusting signal latch timing at a receiving circuit provided for each of the signal lines so that the latch timing becomes optimum for the signal line.
The timing adjusting unit may give, in effect, a variable delay to a clock used to drive each of the receiving circuits to latch each of the signals. The timing adjusting unit may include a phase interpolator that generates from a plurality of clocks with different phases a new clock having an intermediate phase. The timing adjusting unit may include a phase interpolator that generates from a plurality of clocks with different delay amounts a new clock having an intermediate delay amount. The timing adjusting unit may give, in effect, a variable delay to each of the signals at transmitting end.
The signal transmission system may further comprise a retiming circuit for retiming the plurality of signals latched at optimum timing from the plurality of signal lines so that all of the plurality of signals change synchronously with a common clock; and a deskew circuit for inserting, in the event of occurrence of a skew greater than or equal to a data cycle, a necessary amount of delay equivalent to an integral multiple of the data cycle.
The timing adjusting unit may include a plurality of latch circuits for latching the signals, and interleaving operations between two or more parts may be performed using the plurality of latch circuits. The plurality of latch circuits that perform the interleaving operations may be each constructed as a circuit employing a PRD method. The clock used to drive each of the receiving circuits to latch each of the signals may be derived from a signal on a dedicated clock line. The clock used to drive each of the receiving circuits to latch each of the signals may be generated internally, based on a phase comparison between a signal on a data line or a dedicated clock line and a reference clock internal to the receiving circuit.
The timing adjusting unit may include, at a receiving end, an optimum timing determining unit for determining an optimum point of the signal latch timing, and the optimum timing determining unit may determine the optimum point of the signal latch timing by using a first clock and a second clock having a predetermined phase difference with respect to the first clock.
The second clock may have a phase difference of approximately 180 degrees with respect to the first clock. The optimum timing determining unit may detect a data transient region by using the first clock and may determine the optimum point of the signal latch timing by using the second clock so that signal latching at the receiving circuit is achieved at optimum timing. The timing adjusting unit may include, at receiving end, an optimum timing determining unit for determining an optimum point of the signal latch timing, and the optimum timing determining unit may determine the optimum point of the signal latch timing by using a clock having a duty cycle of approximately 50%.
The optimum timing determining unit may detect a data transient region by using the clock and may determine the optimum point of the signal latch timing by using the complement of the clock so that signal latching at the receiving circuit is achieved at optimum timing. The timing adjusting unit may include, at transmitting end, an optimum timing determining unit for determining an optimum point of the signal latch timing, and the optimum timing determining unit may transmit data at such timing that a clock, at receiving end, occurs at an optimum point of data.
The optimum timing determining unit may include a calibration mode for transmitting data at first timing and a data transmission mode for transmitting data at timing shifted by a predetermined phase difference with respect to the first timing, and wherein the calibration mode may detect a transient region in the data of the first timing by using the clock at the receiving end, and the data transmission mode may ensure that the data of the timing shifted by the predetermined phase difference with respect to the first timing is latched by the receiving circuit by using the clock at the receiving end. The timing shifted by the predetermined phase difference with respect to the first timing may be timing having a phase difference of approximately 180 degrees with respect to the first timing.
The signal transmission system may further comprise a phase information extracting unit for extracting phase information of a clock on a clock line or a data line; and a storing unit for sending the phase information of the clock to each of the receiving circuits, and for storing for each of the receiving circuits a relative phase value representing the phase difference between the optimum receiving timing required at each of the receiving circuits and the clock actually used and wherein, when performing the signal latching, the optimum receiving timing at each of the receiving circuits is determined by taking a sum of the phase information of the clock and the stored relative phase value for each of the receiving circuits.
The timing adjusting unit may include, at receiving end, a delay circuit for delaying data. The delay circuit may be constructed as a variable delay circuit capable of delaying an analog signal.
Further, according to the present invention, there is also provided a timing signal generating circuit comprising a master circuit for generating by feedback control an internal signal having the same cycle or the same phase as that of an input reference signal; and a slave circuit for generating a timing signal having a prescribed timing relative to the reference signal by receiving the internal signal and a control signal from the master circuit.
A plurality of slave circuits may be provided for one master circuit. The master circuit may contain a circuit corresponding to the slave circuit so that the master circuit may also output a timing signal by itself.
The master circuit may comprise a comparator circuit for comparing the cycle or phase of the internal signal with that of the reference signal, a control signal generating circuit for varying the control signal in accordance with an output of the comparator circuit, and a variable delay line for outputting the internal signal by controlling a delay amount for the reference signal in accordance with the control signal.
The master circuit may be a DLL circuit which comprises a coarse delay control block for performing coarse delay control and a fine delay control block for performing fine delay control, and the slave circuit contains a circuit corresponding to the fine delay control block. The coarse delay control block may take taps off the delay line consisting of a plurality of delay units, and may perform coarse delay control by selecting an output of each of the taps, while the fine delay control block receives a signal for controlling the DLL circuit in the coarse delay control block and a signal subjected to the coarse delay control in the coarse delay control block, and performs fine delay control through an interpolator by using the coarse delay control signal.
The control signal generating circuit may include a charge pump circuit for controlling an output voltage level in accordance with an up signal and a down signal from the comparator circuit. The control signal generating circuit may include an up-down counter for counting an up signal and down signal from the comparator circuit and a D/A converter for performing digital-to-analog conversion on an output of the up-down counter.
The master circuit may comprise a comparator circuit for comparing the cycle or phase of the internal signal with that of the reference signal, a control signal generating circuit for varying the control signal in accordance with an output of the comparator circuit, and a voltage-controlled oscillator for generating an internal signal corresponding to the reference signal in accordance with the control signal.
The slave circuit may include a voltage-controlled oscillator for outputting the timing signal in accordance with the control signal from the master circuit. The control signal generating circuit may include a charge pump circuit for controlling an output voltage level in accordance with an up signal and down signal from the comparator circuit. The control signal generating circuit may include an up-down counter for counting an up signal and a down signal from the comparator circuit and a D/A converter for performing digital-to-analog conversion on an output of the up-down counter.
The slave circuit may include a variable delay line for outputting the timing signal by delaying the internal signal in accordance with the control signal from the master circuit. The slave circuit may include a phase interpolator for accepting input signals of different phases and for outputting a finer timing signal of an intermediate phase.
The input signals of different phases may be three-phase or four-phase clocks. The phase interpolator may include a voltage-to-current converting unit for converting a plurality of input voltage signals respectively to current signals, a current-to-voltage converting unit for converting the converted current signals back to voltage signals by varying voltage conversion factors, and a comparing unit for comparing a sum of the converted current signals with the reference signal.
The control signal sent from the master circuit to the slave circuit may be a control current signal. A control current signal generating circuit for generating the control current signal may be provided in the master circuit, and a current-to-voltage conversion circuit for converting the control current signal to a voltage signal may be provided in the slave circuit. The slave circuit may include an amplifier circuit whose response speed varies in accordance with a signal from the master circuit, and may generate a signal of sinusoidal waveform as the timing signal.
The slave circuit may be used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and the timing signal generating circuit may include timing signal adjusting unit, provided common to each of the slave circuits, for adjusting the timing signal so as to increase the S/N ratio of a transmitted and received signal. The timing signal adjusting unit may include a selecting unit for selecting an input or output signal of a circuit controlled by the timing signal from each slave circuit, and a timing signal generating unit for controlling output timing of the timing signal by detecting the level of the input or output signal of the circuit selected by the selecting unit.
The slave circuit may be used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and each of the slave circuits may include a timing signal adjusting unit for adjusting the timing signal so as to increase the S/N ratio of a transmitted and received signal.
In addition, according to the present invention, there is provided a semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit and at least one slave circuit, the master circuit and the slave circuit being formed on the same semiconductor chip used for the semiconductor integrated circuit device, wherein the master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control; and the slave circuit generates a timing signal having prescribed timing relative to the reference signal by receiving the internal signal and a control signal from the master circuit.
Furthermore, according to the present invention, there is also provided a semiconductor integrated circuit system employing a timing signal generating circuit comprising a master circuit and at least one slave circuit, the semiconductor integrated circuit system having a plurality of semiconductor integrated circuit devices, each of the semiconductor integrated circuit devices having the master circuit and/or the slave circuit and being formed on corresponding one semiconductor chip, wherein the master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal by feedback control; and the slave circuit generates a timing signal having prescribed timing relative to the reference signal by receiving the internal signal and a control signal from the master circuit.
According to the present invention, there is provided a phase interpolator comprising an analog periodic waveform generating unit for generating an analog periodic waveform, whose value varies in an analog fashion, from a digital periodic signal whose amplitude represents a digital value; a summed waveform generating unit for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by the analog periodic waveform generating unit from digital periodic signals displaced along time axis; a weighting control unit for controlling the weighting of each of the analog periodic waveforms; and an analog/digital converting unit for converting the summed waveform to a digital waveform.
The analog periodic waveform generating unit may include a sine wave generating circuit, and the weighting control unit may include a plurality of transfer gates connected in parallel and controlled for connection. Each transfer gate in the weighting control unit may have a transistor of the same size, and the weighting of the analog periodic waveform may be controlled by controlling the number of transfer gates caused to conduct. Each transfer gate in the weighting control unit may have a transistor of a different size, and the weighting of the analog periodic waveform may be controlled by causing at least one transfer gate having a transistor of a prescribed size to conduct.
The analog periodic waveform generating unit may include a plurality of CMOS inverters, and the weighting control unit may control the number of CMOS inverters to be connected. The analog periodic waveform generating unit may include a plurality of CMOS inverter output stages, and the weighting control unit may control the number of output transistors forming the plurality of CMOS inverter output stages.
The analog periodic waveform generating unit may be a high-frequency attenuation circuit for attenuating high-frequency components of the digital periodic signal, and the weighting control unit may convert an output of the high-frequency attenuation circuit into a current by means of a variable transconductor and apply the converted current to a common terminal. The analog periodic waveform generating unit may be an integrator circuit. The analog periodic waveform generating unit and the summed waveform generating unit may comprise a current polarity switching unit for switching the polarity of a current flowing from a constant current source to a common capacitive load by the digital periodic signal; and a current value control unit for controlling a current value of the current source.
The current value control unit may control the current value of the current source by an output of a D/A converter. The analog/digital converting unit may be a comparator for comparing the summed waveform with a reference level for conversion into a digital waveform. The weighting control unit may include a current-output D/A converter, and an output of the D/A converter may be controlled by being switched for connection to either a capacitive-coupled terminal or its complementary terminal.
The weighting control unit may be configured to vary the number of current sources to be connected to a load capacitance terminal. The weighting control unit may include a clamp circuit for holding a terminal voltage level within a fixed range. The phase interpolator may be configured so that the size of transistors to be switched and the quantization step size of a D/A converter are made variable to provide a desired linearity characteristic to a timing output versus a control signal.

Signal transmission system having a timing adjustment circuit


Systems and methods for automated conversational querying. The system includes a client device associated with a user, content sources including a website and a platform associated with the website. The platform includes a chat bot comprising a machine learning engine, an intent analysis system and a query system. The chat bot generates an interface window overlaid on the website, when the website is displayed on the client device. The chat bot generates an automated conversational dialog with the user via the interface window, and receives user input from the client device via the interface window, responsive to the automated conversational dialog. The intent system identifies an intent from the user input. The query system automatically queries at least one source among the content sources and obtains query results, based on the identified intent. The chat bot displays the query results on the interface window.

The advent of the internet has allowed users to access vast repositories of data and information. However, challenges still exist with respect to identifying relevant content for a given subject matter over the internet. For example, a user may attempt to navigate various websites, which may or may not be connected to each other (e.g., independent websites), to identify relevant content. The user may ultimately find relevant content, but this process can be tedious and time consuming. And the user may miss some relevant content, if the user is unaware of particular internet content sources that may contain the information to be searched.
Search engines exist that attempt to search for information on the internet, to mine content (e.g., web pages, images, available data (e.g., data located in one or more databases, one or more directories), etc.) related to a query. However, conventional search engines typically provide a list of all possible answers, which answers may or may not be relevant to the user's search. Moreover, the resulting content that is provided is typically fragmented information from various sources. Yet further, in conventional search engines, users typically need to provide the exact keyword to be searched to identify related content. Even with an exact keyword search, identifying relevant content typically involves multiple web page turns and/or loads before a user may obtain a desired result. Thus, even with conventional search engines, problems exist with the usability of the identified content provided to a user's web browser (e.g., because the process can still be tedious and time consuming to the user), as well as the accuracy of search results.
There is a need for improving content querying in internet environments, to improve not only the accuracy of the query results, but also the usability of the query results provided to the user. There is also a need to provide intelligent interactive and conversational assistance that may automatically and proactively suggest relevant content to a user and for facilitating automated interactive discussions.

Artificial intelligence system for providing relevant content queries across unconnected websites via a conversational environment


Disclosed is related to a printing device for performing a multi-color gravure offset printing operation in one rotation of a gravure offset roll for various shapes of printing material, and a method therefor. The printing device includes at least: a blanket roll having a cylindrical shape and moving in a first direction while rotating; an ink transfer unit including one or more ink transfer plates which is in contact with a lower end of the blanket roll; a squeeze unit moving in a second direction in a state in which one end thereof comes in contact with the ink transfer plate, wherein the second direction forms a predetermined angle with respect to the first direction or is orthogonal to the first direction. According to the present invention, an effect of enabling gravure offset printing in one printing cycle on various shapes of printing material is provided.

Multi-color gravure offset printing methods include a method of installing a plurality of plates around a drum with a single large radius described in Japanese Patent Application Laid-Open No. H09-277491 and a method of disposing a plurality of drums in parallel to each other (Japanese Patent Application Laid-Open No. 2008-168578), and the like. However, recently, there are problems with adjusting a position of a drum itself and ensuring reproducibility, maintaining precision and reproducibility of printing at a width of less than or equal to 100 μm when the printing material is moved in a conveyor manner, and the like. Further, it is highly likely that various problems with precision caused when a plurality of drums are used, such as distortion of parallel precision of installation positions of the plurality of drums caused by change in temperature, determination of parallel position, and the like, will occur. Although the width is less than or equal to 100 μm, due to the thickness being a few micrometers, there are problems, such as excessive electric resistance or a lack of sufficient color density. Furthermore, in the high functional printing device satisfying the problem, there are problems of difficulty of automation and parallel processing or change in quality of printing occurring during printing as time elapses from the view point of economically high efficiency printing. There are many factors that block supply of gravure offset printing when compared to a silk printing method, including a problem in which the roll is damaged due to solidification of a ultra violet (UV) ink in a drying process when UV rays touch a part of blanket roll and a problem in which printing is distorted due to a thickness of printing in a serial printing method.

Multi-color gravure offset printing device and printing method


A method to ascertain a network topology, wherein a request message is transmitted from a first network node to at least one second network node connected to the first network node, a second network node enters its associated node number in the network into the request message and forwards the request message to at least one third network node connected to the second network node, the request message is forwarded until all the network nodes arranged in the network and all connecting lines connecting the network nodes have been passed through, the request message is transmitted back to the first network node, and the network topology information, available in the form of the node numbers entered in the request message, is stored.

Communication networks and computer networks include network nodes, for example formed by communications installations and data processing devices, as well as the connecting lines connecting the individual network nodes to one another. In this context, a multiplicity of different network structures (also referred to in the literature as network topologies) are known, such as a star network, a ring network, a tree network, a chain network or a bus network.
In networks, a distinction is drawn between connectionless and connection-oriented networks, according to the topology of the respective network. Connectionless networks omit a signaling phase which precedes information transmission between communication terminals associated with the networks and within the context of which a connection is set up between the communication terminals. In a connectionless network, for example, an IP-oriented (Internet Protocol) computer network, an information packet to be transmitted is transmitted to each communication terminal associated with the network. The decision regarding which communication terminal processes the received information packet further or rejects it is made by the recipient of the information packet.
In a connection-oriented network, for example an ISDN-oriented communication network, in which information is transmitted from network node to network node via a connection set up previously within the context of a signaling connection, an important feature for optimum transmission of a message via the network is for the network topology to be known; i.e., for information to be held about how the individual network nodes are connected to one another.
The present invention is therefore directed toward providing methods which permit network topologies to be ascertained and visualized, particularly for a connection-oriented network.

Method for ascertaining and visualizing network topologies


A headphone includes a hanger and two speaker units respectively disposed at the two ends of the hanger. Each speaker unit includes a first shell; a second shell engaged with the first shell, a first air passage being formed between the first shell and the second shell, a second air passage being formed on the second shell, the second air passage having an opening direction different from an opening direction of the first air passage; a cover engaged with the second shell and having a plurality of holes on the cover; and a speaker disposed between the first shell and the second shell. When the speaker outputs sound, airflows generated by the speaker are exhausted through the first air passage, the second air passage and the holes so that the amount of air exhaust is stable and the output audio is of high quality.

1. Field of the Invention
The present invention relates to a headphone, and more particularly, to a headphone that has stable air exhaust and outputs high quality audio.
2. Description of Related Art
Headphones generally have speakers inside. The speakers generate sound waves by vibrating membranes therein. Various structures of headphones have been designed to make the audio coming out of the headphones smoother and of higher quality. For example, it is a common practice to form air holes on headphones.
Referring to FIG. 5, U.S. Pat. No. 4,058,688, discloses a headphone with a speaker unit 90. Multiple holes 92 are formed on a front cover 91 of the speaker unit 90 for a speaker 93 to transmit sound therethrough. In other words, the airflows generated by the speaker 93 flow through the holes 92. To make the sound smoother, multiple holes 95 are formed on a back cover 94 of the speaker unit 90.
However, because the holes 95 are formed on the back cover 94, a desired aesthetic design of the back cover 94 may not be achievable. In addition, to get a smooth and quality sound, the quantity of the holes 95 has to reach a certain number. Otherwise, the air exhaust will be affected and the sound quality will be degraded. With limited area of the back cover 94, it is a challenge to maintain the quality of the sound while controlling the manufacturing cost.


A computer-implement method and computer system may be configured to facilitate policyholder setup in connection with estate handling. An audible or visible chatbot avator or doppelgänger may lead a trustee, beneficiary, or family member through the estate of an impaired or deceased user. A computer system may have been provided with, or gather, sample voice and visual recordings associated with a user that are used to build the chatbot avatar that simulates the user audibly and/or visually. The computer system may have previously prompted the user for necessary items to properly handle their estate, such as information related to financial accounts, loans, insurance policies, etc. and user names and passwords to various electronic accounts.

Spouses, executors, beneficiaries and other trusted individuals often face difficult and time-consuming tasks collecting information and documentation used to close decedents' estates. There remains a need for systems and methods to improve this process. Systems and methods of these types should provide a high degree of security.
Conventional estate handling techniques may be inefficient, awkward, time consuming, inaccurate, timely, and/or frustrating for family members. Conventional estate handling techniques may have other drawbacks as well.

Policyholder setup in secure personal and financial information storage and chatbot access by trusted individuals

STATE FARM MUTUAL AUTOMOBILE INSURANCE COMPANY


A chip stack structure using conductive film bridge adhesive technology comprises a substrate, a first chip, at least one bridge element, a conductive film, and a second chip. The first chip is electrically connected to a first electrode of the substrate. The at least one bridge element has a first bridge surface and a second bridge surface at two ends, and the first bridge surface and the second bridge surface are electrically connected to the first chip and a second electrode of the substrate, respectively. The conductive film is electrically connected to the first bridge surface of the at least one bridge element. The second chip is stacked and electrically connected to the conductive film. Thus, the structure of the present invention not only facilitates the ease of stacking the chips but also increases the effectiveness of the chips heat dissipation and ability of withstanding electrical current.

1. Field of the Invention
The present invention is related to chip stack structure, especially related to a chip stack structure using conductive film bridge adhesive technology.
2. Description of Related Art
Since a single chip cannot withstand the electrical current of an entire system, it is generally required to use two or more chips to overcome this problem, however, the substrate area will be have to be increased due to placing the chips horizontally. As shown in FIG. 1, an integrated power module has a plurality of separated chips 1 disposed on a single substrate 2, and then welding wires 3 are bonded to electrically connect the chips with each other. However, the overall size of the package increases because the chip 1 becomes more dense in this kind of structure.
With the advancement of technology, electronic products tend towards miniaturization and providing high performance to meet the needs of customers. In order to improve the performance and the capacity rate of a single package structure, three-dimensional (3D) package is widely adopted in the present day. Two or more chips 1 are stacked in a single package structure in order to provide a 3D package with compactly stacked and interconnected chips 1. As shown in FIG. 2, a conventional chip stack structure 4 is disposed with a plurality of chips, which are stacked up and down on a substrate 2. In the chip stack structure 4, a first chip 1a is adhered to the substrate 2 by an adhesive, and a plurality of first welding wires 3a are bonded and electrically connected to first pads 5a on the surface of the first chip 1a and contacts 6 on the substrate 2. Then, a second chip 1b is disposed on the first chip 1a. The adhesive 7 is applied between the first chip 1a and the second chip 1b in advance to adhere the second chip 1b to the first chip 1a and partially covers the first welding wires 3a. The thickness of the adhesive 7 exceeds the arc height of the first welding wires 3a in case of the first welding wires 3a make contact with the second chip 1b. After stacking the second chip 1b, a plurality of second welding wires 3b are bonded to and electrically connected to second pads 5b of the second chip 1b and the contacts 6 on the substrate 2. Both this chip stack structure 4 and the one recited above use wire bonding for electrical connection between chips so there isn't any effective heat dissipation structure between the chips 1a, 1b. When the heat can't be timely dissipated, the effectiveness of the chips will decrease due to the increase in temperature. Moreover, the adhesive 7 in this case is easily interfered with due to high temperatures and welding wires, and there will be voids gathered in the adhesive 7. Once the number of voids is reaches a critical capacity, the adhesive bond of the adhesive 7 will be greatly reduced, which leads to the chips 1a, 1b not being able to be stacked successfully.
To sum up the above, the conventional chip stack structure has the above drawbacks and needs to be improved.

Chip stack structure using conductive film bridge adhesive technology


To provide an integrated IP network containing therein a plurality of separated IP networks with a variety of characteristics, such as IP telephone network, IP video network, IP electronic text network, best effort network, IP data multicast network and IP-based TV broadcast network. In the integrated IP network there are virtually installed a plurality of IP networks with various features, such as IP telephone network, IP video network, IP electronic text network, best effort network, IP data multicast network and IP-based TV broadcast network. An address management table is set in each of the network node devices installed at input points through which the integrated IP network is accessed from outside. The address management table is registered beforehand with terminal addresses and port numbers identifying the application programs (AP) in the terminal. The address and port number written in the IP packet entered into the integrated IP network are compared with those registered in the address management table to route, inside the integrated IP network, the IP packet to an appropriate IP network. The port number may not be used and only the addresses may be compared.

1. Field of the Invention
The present invention relates to an integrated IP (Internet Protocol) network of an IP network for computer communication based on the TCP/IP (Transmission Control Protocol/Internet Protocol) technology.
2. Description of the Related Art
The IP network designed to send and receive digitized voice data according to the TCP/IP technology (hereinafter referred to as an "IP telephone network") uses a communication circuit speed of about 64 Kbps to keep the arrival time of voice data below, for example, 0.1 second. An IP telephone network to send and receive a compressed video image of TV according to the TCP/IP technology (hereinafter referred to as an "IP video network") uses a communication circuit speed of, for example, 1.5 Mbps and allows a video data arrival time of a few minutes.
The IP telephone network to transfer texts of electronic vouchers according to the TCP/IP technology (hereinafter referred to as an "IP electronic text network") has a communication circuit speed of about 128 Kbps to keep the data arrival time less than 1 second. In this case, because the reliability is given a greater importance than those of voice transmission and TV video transmission, the communication error occurrence rate is kept less than one one-hundredth those of the IP telephone network and IP video network.
Other IP telephone networks include, for example, an "IP data multicast network" that transfers IP data such as electronic books and electronic newspapers from one sending source to a plurality of destinations, and an "IP-based TV broadcast network," an IP audio-visual network, which transfers (or broadcasts) both TV's voice data and video data to a plurality of destinations using multicast technology, one of technologies. These multicast type network differ from the preceding IP telephone networks in that they do not employ the one-to-one communication scheme.
As shown in FIG. 1, in the conventional IP network 20 as represented by the Internet, an IP packet 26-1, including IP telephone data, IP video data and IP electronic voucher text data, is dispatched from a terminal 23-1 within a LAN 21 to a terminal 23-2 in a LAN 22 through a router 24-1 in the LAN 21 and routers 22-1 to 22-4 in the IP network 20 and through a router 24-2 in a LAN 22. The Internet, while it cannot guarantee the communication speed and others during the IP transfer, is generally called a "best effort network" in the sense that it makes the best effort. The IP telephone data, the IP video data and the IP electronic voucher text data flow in an intermingled manner through the communication circuits in the IP network 20, as in this example. That is, the conventional IP networks do not contain therein a plurality of separated IP networks with various characteristics, such as the IP telephone network and IP video network, the IP electronic text network, the best effort network, the IP data multicast network and the IP-based TV broadcast network. For this reason and others, the IP telephone network, IP video network, IP electronic text network, best effort network, IP data multicast network and IP-based TV broadcast network have been constructed separately, giving rise to a problem of an increased overall cost of the entire IP network.
By referring to FIG. 2 a multicast type IP network 27-1 that transfers data from one originating source to multiple destinations will be explained. Reference numbers 27-2 to 27-9 represent routers, of which 27-2, 27-6, 27-7, 27-8 and 27-9 in particular are routers to which the users' IP terminals 28-1 to 28-9 can connect via communication circuits and which are also called network nodes. The routers 27-3, 27-4, 27-6, 27-7, 27-8 have a multicast-by-router table that tells each router to send a received IP packet to a plurality of communication circuits according to a multicast address contained in the received IP packet. In this embodiment, the multicast address specifies "MA1". The IP terminal 28-1 sends an IP packet 29-1 which has a multicast address "MA1" through the router 27-2. When it reaches the router 27-3, the router 27-3 copies the IP packet 29-2, checks the multicast-by-router table and transfers IP packet 29-3 and IP packet 29-4 onto communication circuits. The router 27-4 copies the received IP packet 29-3 and, according to the multicast-by-router table, transfers IP packet 29-5 and IP packet 29-6 onto communication circuits. The router 27-5 has no multicast-by-router table and so the IP packet 29-4 passes through the router 27-5 to be transferred as IP packet 29-7 to the router 27-8. The router 27-6 copies the received IP packet 29-5, checks the multicast-by-router table and transfers IP packet 29-8 to IP terminal 28-2 and IP packet 29-9 to IP terminal 28-3. The router 27-7 copies the received IP packet 29-6, references the multicast-by-router table and transfers IP packet 29-10 to IP terminal 28-4 and IP packet 29-11 to IP terminal 28-5. The router 27-8 copies the received IP packet 29-7, references the multicast-by-router table and sends the IP packet 29-12 to IP terminal 28-6, IP packet 29-13 to IP terminal 28-7 and IP packet 29-14 to IP terminal 28-8. When the source terminal 28-1 sends electronic books and electronic newspapers in a digital data format to the IP network 27-1, the IP network 27-1 functions as an IP data multicast network for distributing electronic books and electronic newspapers, with the IP terminals 28-2 to 28-8 representing IP terminals of the users purchasing the electronic books and electronic newspapers. When the source terminal 28-1 is replaced with a TV broadcast audio-visual transmission equipment and a TV program (i.e., voice and video) is broadcast, this IP network works as an IP-based TV broadcast network, with IP terminals 28-2 to 28-8 representing TV viewers' IP terminals with TV reception function.

The Distribution Systems Research Institute


A nasal mask for applying pressurized gas to a user's respiratory system. The mask includes an inflatable seal which is at least partially filled with a soft open cell foam. The seal includes a manual pump and a pressure release valve for inflating and deflating the seal. The mask includes an brow bar which is connected through a bridge to the mask body. The bridge can be adjusted to position the brow bar against the user's forehead for supporting an upper portion of the mask. Headgear for attaching the mask to the user is attached to the brow bar and is looped over a prong at a lower portion of the mask for securing the lower portion of the mask to the user. The mask can be easily removed from the patient while leaving the headgear and brow bar attached to the user.

Obstructive sleep apnea (OSA) is common sleep disorder suffered by a large number of people. When a person who suffers from OSA has an event, the airway collapses and is blocked, primarily during inspiration. The airway may remain blocked for a few seconds to more than one minute while the person struggles to breath. The person may wake or may move to change his or her sleep position to until the blockage is opened. Severe snoring is frequently a precursor to OSA. During severe snoring, the airflow to the patient's lungs may be restricted, but not totally blocked. One treatment for OSA is the application of a continuous positive airway pressure (CPAP) to the patient's respiratory system. This is most frequently accomplished by the patient wearing a nasal mask during sleep which is connected to a source of pressurized air. When a sufficient air pressure is applied to the nasal mask, the patient's airways become sufficiently inflated and remain open for unrestricted breathing. While evaluating a patient for CPAP treatment, a clinician determines the lowest effective pressure needed for keeping the patient's airway open during sleep.
Various types of CPAP apparatus are well known in the art. The basic CPAP apparatus has a blower which is connected through a pressurized air hose to a nasal mask. The CPAP apparatus is adjusted to provide the lowest effective pressure to the patient for preventing abnormal sleep events. More sophisticated CPAP apparatus includes features such as a ramp delay which applies a reduced pressure to the nasal mask for a period while the patient falls asleep, and then gradually increases the pressure to a programmed level. The CPAP apparatus also may vary the applied pressure to gradually increase the applied pressure in response to sensed sleep events, and to gradually decrease the applied pressure when no sleep events are sensed. In a bi-level form of CPAP apparatus, an effective therapeutic pressure is applied to the nasal mask when the patient begins to inhale and the pressure is reduced when the patient begins to exhale. Bi-level apparatus can increase the comfort of CPAP therapy by reducing the work of exhaling against the therapeutic pressure, particularly for patients who require a high therapeutic pressure.
Some patients do not comply with the prescribed CPAP treatment due to mask discomfort where it contacts the face, especially at the bridge of the nose. There has been significant work by CPAP equipment manufacturers to improve mask comfort, since the mask must be worn whenever the patient is sleeping. To be effective, the mask requires a comfortable seal which will adjust to a wide differences in facial configurations of different patients. The seal also must adjust to facial changes when a user changes sleep positions. A number of different seal configurations have been used in the past. These include flexible membranes which can conform to the face and the bridge of the nose, foam filled seals, inflated seals, and seals filled with a gel type material. Each type of seal has positive and negative features.
The mask is secured to the patient with headgear which typically is in the form of straps which extend around the head. Preferably, the headgear is designed so that it is easily adjusted by the patient and is easily attached to the patient. The patient should be able to remove the mask during the night and to easily reattach the mask, for example, if the patient needs to go to the toilet. However, many mask/headgear configurations are not easy for the patient to attach and remove.


A driving chip set includes a master chip and at least one slave chip. In the master chip, a master receiving terminal receives a data signal through a first data transmission interface; a processing unit generates a first partial data signal and a second partial data signal according to the data signal; a master buffer registers the first partial data signal; a master output terminal outputs the second partial data signal through a second data transmission interface. In the slave chip, a slave receiving terminal receives the second partial data signal through the second data transmission interface and it is registered by a slave buffer. The processing unit controls a master driver and a slave driver to output the first partial data signal and second partial data signal to a display panel. The display panel displays an image according to the first partial data signal and second partial data signal.

1. Field of the Invention
The invention relates to a driving chip of a display apparatus; in particular, to a display apparatus, a driving chip set, and an operating method thereof capable of saving power, maintaining data signal quality, and simplifying circuit structure.
2. Description of the Prior Art
In recent years, the low-voltage differential signal (LVDS) interface has become a standard of interface data transmission between the image processing unit and the display unit in a notebook computer or a television. However, with the increasing size of the display and the rising demand of image display quality, if the LVDS interface is still used to transmit data, the following three problems will occur: (1) the increasing cost of cable because the LVDS interface needs more data transmission cables; (2) when more data transmission cables are needed, more pins of the image processing unit and transmitter are also needed to increase the cost of packaging; (3) dedicated clock line is needed for the LVDS interface, and higher data transmission rate will cause the offset of data and clock line to make long data signal transmission become more difficult.
In view of this, the LVDS interface is replaced by some signal transmission interfaces with higher data transmission rate and less signal transmission lines, such as an embedded display port (eDP) interface, a mobile industry processor interface (MIPI), or a V-by-One interface.
In a large-size display, the source driver usually uses a dual chip set to drive the left part and the right part of the display panel respectively. As shown in FIG. 1, if the display uses the eDP interface to transmit data signal, a first chip 11 and a second chip 12 of the dual chip set 1 have a first receiving terminal Rx1 and a second receiving terminal Rx2 respectively to receive the data signal eDP transmitted through the eDP interface. The control signal CS is transmitted between a first bus B1 of the first chip 11 and the second bus B2 of the second chip 12.
The largest problem of this structure is that the data transmission rate of the eDP interface is higher than the data transmission rate of the LVDS interface and the eDP interface has higher requirement of data signal quality, and the power consumption of the first receiving terminal Rx1 and the second receiving terminal Rx2 receiving data signal through the eDP interface is larger than the power consumption of the first receiving terminal Rx1 and the second receiving terminal Rx2 receiving data signal through the LVDS interface. And, the first receiving terminal Rx1 of the first chip 11 and the second receiving terminal Rx2 of the second chip 12 must be trained before they use the eDP interface to receive the data signal; therefore, its complexity and power consumption are both increased.

Display apparatus, driving chip set, and operating method thereof


a modified structure of a dart-board comprised of a dart-board, made of paper board, plastic or other magnetic susceptible material, with surface divided into a multiple of scoring segment; a magnetic inductor made of magnetic inducing material provided behind and in the same size and shape of the dart-board to attract the dart point to land at; and a support frame with its inner contour having the same size and shape as that of the dart-board and the magnetic inductor to house both dart-board and magnetic inductor, a ring locking shield protruding inward provided to the edge of said opening to latch both dart-board and magnetic inductor; featuring that slits are provided without magnetic inductor at boundary line to abutted segments on the dart-board corresponding to the magnetic inductor so that when a dart with magnetic point lands on said boundary line, the dart will naturally be attracted by and guided to the segment to score.

The present invention relates to a modified structure of a dart-board, more particularly, to one that can guide the dart thrown and standing at the ring line that prevents scoring to fall in the scoring segment.
The prior art of the game of darts generally uses two types of dart, respectively are one with a metallic point and the other with a magnetic point. The former, essentially comprised of a dart with sharpened point fixed to a shaft barrel of the dart so that when thrown it may insert into the dart-board, presents more dangers as people in the playing area may get hurt by the dart; and the latter, essentially comprised of a dart with its point mounted in a magnetic member while the inner layer of the dart-board a metal panel to attract the dart thrown at, thus is safer than the former. The present invention is designed by modifying this type of magnetic dart-board.
The prior art of the magnetic dart-board is essentially comprised of a board made of magnetic susceptible material(e.g. paper board, PVC), with its surface divided into a multiple of segment as scoring areas; a support frame mounted behind the dart-board; and a magnetic inductor (e.g. a metal plate)in the size and shape exactly the same as those of the dart-board is provided between said dart-board and said support frame, so to attract the dart thrown at.
However, in the prior art of the magnetic dart-board usually will also attract the dart to stand just at the ring line between the scoring segments instead of falling into either scoring segment to prevent the scoring.


A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell""s performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

1. Technical Field
This invention generally relates to electronic circuits, and more specifically relates to a method for electronic circuit design.
2. Background Art
Integrated circuits (ICs) are semiconductor devices consisting of many components arranged on a base called a wafer. Semiconductors are formed from material that allows current to flow under certain circumstances, making them indispensable in all sorts of environments from computers to cellular phones to calculators and beyond. ASICs are integrated circuits that are designed to perform a specific function for a specific customer, such as a chip that controls a talking toy or a chip for use in a communications satellite. Frequently an ASIC will share some features with other ASICs previously produced. This partial duplication leads to the creation of standard cell libraries made up of components that perform certain logical functions. These componentsxe2x80x94the cellsxe2x80x94themselves consist of more basic units called devices. When an ASIC""s design calls for a certain function to be performed, a cell that accomplishes that function can be selected from the cell library instead of being designed from the ground up. This time-saving step becomes very important when it is considered that large ASIC manufacturers may produce several hundred ASICs in a year.
The design phase of an ASIC includes the performance of various tests to ensure the chip meets critical performance criteria, including the two fundamental concerns in chip design: timing and noise, which are defined in the next two paragraphs. If these or any other chip requirements are not met the chip must be redesigned and retested until they are. The redesign of a circuit involves such steps as altering the physical layout of chip cells, replacing certain cells with new cells, and changing chip parameters like power level or cell size.
The current trend in semiconductor design is toward lower operating power. Lower power means lower voltages supplied to the semiconductor, and lower voltages at which the semiconductor switches. This latter voltage for a cell is called the switching threshold for the cell. This switching threshold for the cell is the value of the input signal such that an input less than this value will be recognized by the cell as a xe2x80x9czero,xe2x80x9d and an input greater than this value will be recognized as a xe2x80x9cone.xe2x80x9d Because cells work by being switched on or off in response to precise voltage signals, it is important that those signals are not the result of unwanted noise in the circuit. In this context, xe2x80x9cnoisexe2x80x9d refers to an unwanted electromagnetic disturbance that reduces the clarity of a signal. Here, the signal is an input voltage sufficiently far above or below the cell threshold as to be unambiguously recognized as either a xe2x80x9czeroxe2x80x9d or a xe2x80x9conexe2x80x9d telling the cell to turn on or turn off. The disturbance is any such unwanted signal that exceeds the cell threshold and causes the cell to switch falsely. As operating power, and thus power grid supply voltage Vdd and cell switching threshold voltages decrease, noise spike voltages become a greater percentage of the switching threshold and become increasingly problematic, causing an increasing number of false switches.
More common than the false switching problem is the problem of switching delay. This is the timing problem mentioned above. Recall that the semiconductors which are the building blocks of all integrated circuits are materials that sometimes allow and sometimes prevent the flow of current. The opposite states of current flow and current cessation are sometimes referred to as xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d or as xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively. Timing errors can occur when adjacent wires undergo transitions that interfere with each other. For example, when one wire, the victim, is attempting a transition from on to off, an adjacent wire, the aggressor, might be transitioning from off to on. While the aggressor""s effect might be insufficient to cause a false switch (a voltage rise corresponding to the on position) in the victim, it can sometimes be enough to delay or even reverse for a moment the desired transition in the victim, thus preventing a smooth switch and lengthening the time needed for it. This is one way in which noise problems lead to timing problems.
One approach to fixing the noise/timing problem is to adjust various parameters of the system such as spacing, power, and cell size. Spacing adjustments, for example, are effective because they change the coupling capacitance between adjacent conductors. In other words, because noise can be coupled from one conductor to another by their mutual capacitance, increasing the separation between these wires reduces coupling capacitance and therefore reduces the amount of noise injected.
The effects of such changes or adjustments, whether to spacing, power, or some other parameter, can be predicted with reasonable accuracy; the difficulty lies in the fact that it is nearly impossible to predict exactly which change out of an uncountably large number of possible changes is necessary to fix a specific problem. Trial and error, therefore, becomes the only currently viable solution approach, but is itself severely flawed. Besides being inefficient and time consuming, it is ill-equipped to discover problems early in the chip design process. Yet noise sensitivity problems are best discovered as early in the design process as possible in order to avoid the costs of redesign or reconstruction activity.
There also exist farther drawbacks to the solution approach being described. Each parameter adjustment, besides being impossible to select with confidence, poses potentially unwanted and harmful consequences to other parameters in the system. Every adjustment propagates through the system, potentially degrading performance. Trial and error, clearly, leaves much to be desired as an approach to chip-design improvement.
The prior art describes cell libraries-collections of cells useful in redesigning circuits using this trial and error process. The method of replacing an under-performing original cell with an alternate cell from a pre-built cell library is known. A major problem with this basic approach is that a substitution made to fix a problem with one parameter of the IC often creates one or more problems with other parameters. For example, an original cell underperforming with respect to noise tolerance might be replaced with a more noise-tolerant cell. But that replacement cell may create a new set of timing problems that make it just as problematic as the original. A second replacement cell may have altered power requirements that worsen the problem further. Such introduced problems can propagate through the system, causing trouble spots all along the circuit path. Without a way to guarantee that a replacement cell fixes the problem it is intended to solve without causing new problems in the process, such trial and error substitution could potentially fall into an infinite loop where every attempted fix leads to further problems in IC performance. That is a worst-case and perhaps unlikely scenario but it would not be at all uncommon for trial and error problem solving to take at least several hours. With the demand for ASICs growing steadily, time saving techniquesxe2x80x94especially in the timexe2x80x94intensive design phase-are becoming increasingly more important. Therefore, there exists a need to provide an efficient way to address and fix ASIC design problems in a manner that avoids the creation of new problems that can propagate through the system.
According to the present invention, a cell library is provided, each cell having known values of one parameter but having differing values of another parameter. The library cells are ordered in such a way that successive cells in the order exhibit an orderly incrementation of the parameter being changed. Said another way, the cells are ordered from one extreme to the other extreme value of featured parameter F. In one embodiment of the invention the changing parameter can be noise tolerance and the known parameter can be timing. Other cell parameters including size, power requirements, and current capacity could also be either the changing or the known parameter. This means that a substitution of any cell from the library for any other library cell, or the original cell, will have a negligible effect on, to take the original example, the chip""s timing characteristics because that is the parameter held substantially constant or allowed to vary in a known and acceptable way. A chip designer can thus vary the noise tolerances of the IC as needed, confident that such modifications will not create timing problems in the circuit.
It will be understood that the idea of constructing a library with increasing noise rejection, no timing impact, and no size change is of limited use. It can generally be applied to multi-stage cells with limited opportunity for improvement of noise rejection. A more useful approach would be a library with increasing noise rejection and known timing change. Thus, although for simplicity the invention may at times herein be described in terms of a constant or substantially constant parameter, it will be apparent to those skilled in the art that the invention achieves broader utility when the parameter is not necessarily constant, but simply has known and acceptable variation.
One embodiment of the present invention thus involves the provision of a cell library containing IC design element cells sorted into groups of functionally-equivalent cells. Each of the cells in each group have a set of parameters, one of which is a parameter whose value is constant or allowed to vary in an acceptable way, and another of which is a changing parameter, all of which together comprise the total makeup of each cell. After an ASIC is designed its performance with respect to the changing parameter, called featured parameter F, is tested. If problems are found the underperforming cell is marked for replacement, the appropriate library group is accessed, and a replacement cell chosen. The replacement cell is the first unused cell in the library group. This process is repeated until the ASIC performance is satisfactory.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of certain embodiments of the invention, as illustrated in the accompanying drawings.

Method of integrated circuit design by selection of noise tolerant gates

International Business Machines Corporation


The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop)  flip-flop element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop)  flip-flop element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.

The present invention relates generally to the testing of integrated circuit devices, and more specifically to the testing of synchronous integrated circuit devices having a stress test mode or other test mode.
Stress test modes are commonly used in modern synchronous integrated circuit devices to subject the integrated circuit device to various types of tests which "stress" the device. It is important to stress various element and signals of the device for maximum fault coverage. For instance, the external clock signal supplied to the integrated circuit device is an important signal to test because it controls many of the gates contained within the device. Thus, for maximum fault coverage of the device, it is important to stress the external clock signal both at a low logic state and a high logic state. Difficulties are encountered in trying to establish the logic states of the device during a stress test mode. These difficulties are encountered in a memory cell stress test mode of the device, in which all rows and columns are enabled and bitlines true or bitlines complement of the memory cell are pulled to power supply voltage VSS, or in a periphery stress test mode in which all rows and columns of the device are disabled. The difficulty lies in the fact that master/slave latches on the inputs of the integrated circuit device do not allow data to flow all the way through the device since only one master latch or one slave latch will conduct at a time.
Another prior art problem encountered with synchronized integrated circuit test modes is that entering a test mode after the integrated circuit device has been powered-up can result in device latch-up. Once the device powers-up, it has initialized to a certain voltage, such as 3 volts or 5 volts. Transition to a test mode from this voltage condition causes huge current spikes which can result in device latch-up as all the rows, columns, bitlines, etc. of the device simultaneously switch from a normal operation mode to a test mode. It would thus be desirable to enter a test mode upon power-up of the device in order to avoid possible device latch-up.
There is thus an unmet need in the art to be able to initialize the entire data path of an integrated circuit device in a test mode during device power-up and to be able to adequately test the external clock signal of the device or a derivative clock signal thereof in both a high logic state and a low logic state.


A signal wire of a connector includes a housing, a connecting casing, a plug, a soft cable, and a connector. The front side of the plug is installed with two trenches. Terminals are installed in the trenches. The trenches can be inserted by a computer peripheral. The rear side of the plug is connected to the soft cable. The soft cable encloses a plurality of wires. The soft cable and the wires pass out of the round hole of the connecting casing. One end of the wire is secured to the terminal in the trench. Another end of the wire is connected to a connector. The connector can be connected to a circuit board of a computer. The soft cable is bendable so as to avoid that the plug is only inserted to one side of the circuit board. The position of the circuit board can be adjusted conveniently.

The present invention relates to a signal wire of a connector, and especially to connecting wire which is used to a circuit board of a computer or other related circuit board. Not only the assembly work is easy, but also the user may use it conveniently.
Referring to FIGS. 1 and 2, a prior art connector is illustrated. The connector includes a plug 10. The plug 10 is firmly secured to a circuit board 14. The plug 10 has two connecting bodies 11. A rear side of the connecting body 11 is installed with a plate 111. The plate 111 is capable of being connected to a computer panel 112. The plate 111 and the computer panel 112 can be screwed together by two screws 113.
The front side of each connecting body 11 is formed with a slot 12. The slot 12 may be inserted by a plug (not shown) of a computer peripheral (such as a mouse, a modem, etc.). A plurality of terminals 13 are installed in the slot 12. Each terminal extends out of the plug 10. The extending terminal 13 can be inserted to a circuit board 14 so that the computer peripheral can work successfully.
However, since the plug 10 must be firmly secured to the circuit board 14 and is inserted to a computer peripheral so that the computer peripheral can operate successfully. The plug 10 has a preset volume, and therefore, the updating work of the circuit board 14 is difficult due to an insufficient space.
Moreover, the plug 10 must be firmly secured to the circuit board 14, and thus the plug 10 and slot 12 are only fixed to one side of the circuit board 14. However, currently, there are many computer peripherals. If the device is not compatible to the plug 10 at one side of the circuit board 14, a further adaptor is necessary, thereby, the cost burden of the user is increased.
Furthermore, since the plate 111 and computer panel 112 must be screwedly locked by screw 113. The screw opener are necessary to assembly the two. This is convenient since the opener is often lost or forget. Moreover, if the locking force of the screw is too large, the thread is easy to be damaged so that the screw 113 will rotate idly. The screw must be assembled again. Thus, the resource is wasted and the assembly cost is increased. However, these are inconvenient and necessary to be improved.
Accordingly, the primary object of the present invention is to provide a signal wire of a connector, wherein the installing position and inserting direction of the plug can be adjusted effectively so as to avoid that the computer is difficult in assembly and updating due to an insufficient internal space. Various computer peripherals can be used with the present invention. No extra adaptor (not shown) is necessary. The cost is saved and the assembly work is convenient.
To achieve the objects, the present invention provides a signal wire of a connector including a housing, a connecting casing, a plug, a soft cable, and a connector. The front side of the plug is installed with two trenches. Terminals are installed in the trenches. The trenches can be inserted by a computer peripheral. The rear side of the plug is connected to the soft cable. The soft cable encloses a plurality of wires. The soft cable and the wires pass out of the round hole of the connecting casing. One end of the wire is firmly secured to the terminal in the trench. Another end of the wire is connected to a connector. The connector can be connected to a circuit board of a computer. The soft cable is bendable so as to avoid that the plug is only inserted to one side of the circuit board. The position of the circuit board can be adjusted conveniently. The assembly work is easy.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.


The invention concerns polymorphisms in the xcex21- and the xcex22-adrenergic receptors. The invention also pertains to methods and molecules for detecting such polymorphisms. The invention further pertains to the use of such molecules and methods in the diagnosis, prognosis, and treatment selection for cardiovascular diseases, obesity, and diabetes.

The invention relates to gene mutations that predispose an individual to cardiac disease, obesity, and diabetes. More specifically, the present invention relates to specific polymorphisms in the xcex21- and the xcex22-adrenergic receptor genes. The invention further relates to methods and molecules for identifying one or more polymorphisms in the xcex21- or the xcex22-adrenergic receptor genes.
Beta adrenergic receptors (xcex2AR) are the receptors for the endogenous catecholamines, epinephrine (adrenaline) and norepinephrine (noradrenaline). There are at least nine sub-types of adrenergic receptors (H. G. Dohlman et al., Annu. Rev. Biochem. 60:653-688 (1991); S. B. Liggett et al., In: Catecholamines, Bouloux, ed. W. B. Sounders, London (1993)), of which at least three sub-types are xcex2-adrenergic receptors.
The xcex21- and xcex22-adrenergic receptors (xcex21AR, xcex22AR) are expressed in many organs in the body, including heart, lung, vascular tissue, and pancreas (S. B. Ligget In: The Lung: Scientific Foundations, R. G. Crystal et al. (ed.) Lippincott-Raven Publishers, Philadelphia (1996); J. R. Carstairs et al., Am. Rev. Respir. Dis. 132:541-547 (1985); Q. A. Hamid et al., Eur. J. Pharmacol. 206:133-138 (1991)). In the heart, one or both of these receptors regulate heart rate and pumping function; in the lung the xcex2AR regulate airway tone; in the vasculature they regulate vascular tone; in adipose tissue they regulate lipolysis; and in the pancreas they contribute to insulin release. These receptors mediate not only the actions of adrenaline and noradrenaline, but a host of synthetic agonists as well.
The xcex21 adrenergic receptor has been cloned and sequenced (T. Frielle et al., Proc. Natl. Acad. Sci. (USA) 84:7920-7924 (1987)). The gene has been localized to chromosome q24-q26 of chromosome 10 (T. L. Yang-Feng et al., Proc. Natl. Acad. Sci. (USA) 87:1516-1520 (1990). The human xcex21AR has a deduced amino acid sequence of 477 amino acids and is structurally similar to the xcex22AR in many respects. Only a single polymorphism (identified by restriction fragment length polymorphism analysis (RFLP)) has been reported in the human xcex21AR (W. H. Berrettini, et al., Nucl. Acids Res. 16:7754 (1988). To date, polymorphisms resulting in amino acid changes in the xcex21AR protein have not been reported.
The gene encoding the human xcex22AR has also been cloned and sequenced (B. K. Kobilka et al., Proc. Natl. Acad. Sci. (USA) 84:46-50 (1987)). It is an intronless gene that has been localized to q31-q32 of chromosome 5. The deduced amino acid sequence consists of 413 amino acids, with seven clusters of hydrophobic residues thought to represent transmembrane spanning domains. The N-terminus is extracellular, containing two sites for asparagine-linked glycosylation. The transmembrane spanning domains are connected by three extracellular and three intracellular loops. The C-terminus is intracellular. Several polymorphisms in the xcex22AR gene sequence have been reported (E. Reihsaus et al., Am. J. Resp. Cell. Mol. Biol. 8:334-339 (1993); K.-U. Lentes et al., Nucleic Acids Res. 16:2359 (1988); and C. K. McQuitty et al., Hum. Genet. 93:225 (1994)).
Polymorphisms in the xcex22AR have been studied in the context of asthma (E. Reihsaus et al., Am. J. Resp. Cell. Mol. Biol. 8:334-339 (1993), herein incorporated by reference; K. J. Holroyd et al., Am. J. Respir. Crit. Care Med. (Abstract) 151:A673 (1995); D. M. Cooper et al., Am. J. Respir. Crit. Care Med. (Abstract) 153:A254 (1996); K. S. Tan et al., Am. J. Respir. Crit. Care Med. (Abstract) 155:A208 (1997)). There appears to be no difference in the distribution of xcex22AR polymorphisms between individuals suffering from asthma and normal individuals. There is evidence, however, of an association between one polymorphism and more severe asthma (Reihsaus et al.). More recently, these polymorphisms have been shown to be associated with the nocturnal asthmatic phenotype (J. Turki et al., J. Clin. Invest. 95:1635-1641 (1995)), bronchial hyper-reactivity (I. P. Hall et al., The Lancet 345:1213-1214 (1995)), and IgE levels (J. C. Dewar et al., J. Allergy Clin. Imm. (In Press)). Using site directed mutagenesis and recombinant expression in fibroblasts, the pharmacologic properties of these variants have been assessed in vitro (S. A. Green et al., J. Biol. Chem. 268:23116-23121 (1993); S. A. Green et al., Biochemistry 33:9414-9419 (1994))and in transgenic mice (J. Turki et al., Proc. Natl. Acad. Sci. (USA) 93:10483-10488 (1996)).
Given the importance of the xcex21- and the xcex22-adrenergic receptors in modulating a variety of physiological functions, there is a need in the art for improved methods to identify these polymorphisms and to correlate the identity of these polymorphisms with the other functions of xcex2-adrenergic receptors. The present invention addresses these needs and more by providing polymorphisms, molecules, and methods useful for the diagnosis and prognosis of cardiovascular diseases, obesity, and diabetes.


A multilayer capacitor including a base body, which is a dielectric substance; and a plurality of electrode layers, which is laminated in the base body and has a plurality of divided electrodes, in which there are at least three or more kinds of electrode layers having different number of electrodes, and the electrode layer having the most electrodes is interposed between the other electrode layers. The multilayer capacitor achieves high withstand voltage and high reliability with no damage to the size reduction and high capacitance of the capacitor and a mold capacitor having the multilayer capacitor built-in.

The present invention relates to a multilayer capacitor, in which a plurality of dielectric substrates having internal electrodes on the main surfaces thereof are laminated and capacitance is generated between the facing internal electrodes, and a mold capacitor having the multilayer capacitor built-in.
In an electronic device such as power supply, modem or the like, it is common to use a capacitor with a plurality of electronic parts in order to remove noise or to cut direct current. Following the rapid globalization in recent years, the size and cost reduction of an electronic device is highly demanded, and, accordingly, the size and cost reduction of electronic parts is also highly demanded. In addition, since the automatic mounting reduces cost and mounting area, surface-mount electronic parts are also highly demanded. Furthermore, incompatible features such as high performance, the reduction of feature fluctuation, the improvement of durability or the like are also highly demanded. Particularly, since a capacitor is widely used for the power supply or noise removal of plasma display, large-scaled liquid crystal display or the like, the high capacitance and high withstand voltage of the capacitor is also demanded.
FIG. 13(a) is a side cross-sectional view of a multilayer capacitor in the related art. FIG. 13(b) is a cross sectional view of the multilayer capacitor taken along the line G—G in FIG. 13(a). The multilayer capacitor 100 includes a multilayer body 110 formed of a plurality of laminated dielectric substrates 101. A plurality of divided internal electrode 102 is formed on the main surface of each dielectric substrate 101 forming the multilayer body 110. The multilayer body 110 is formed substantially in a cuboid, and a pair of external electrodes 103 is provided at both side surfaces, which face each other in the longitudinal direction of the multilayer body 110.
The multilayer capacitor 100 is formed by laminating a plurality of dielectric substrates 101, and the internal electrodes 102 are formed on the dielectric substrates 101 by screen printing, decalcomania, paste application or the like. That is, the dielectric substrates 101 having the internal electrodes 102 on the surface thereof are laminated so as to form the multilayer body 110.
In the multilayer capacitor 100 constructed as above, capacitance is generated between the layers of internal electrode 102 formed on the different dielectric substrates 101, and the summed capacitance contributes to the high capacitance of the capacitor (for example, see JP-A-2001-284157).
In addition, if voltage is applied to the multilayer capacitor 100 constructed as above, stress caused by piezoelectric effect is generated at certain portions. The stress is biggest in the vicinity of the central portion of the multilayer capacitor 100. Therefore, the stress influences most in the vicinity of the central portion of the multilayer body 110. In order to improve the withstand voltage of the multilayer capacitor 100, it is required to improve the withstand voltage of the multilayer capacitor in the vicinity of the central portion. Furthermore, what make the capacitor weak to the stress in the improvement of withstand voltage is, firstly, the voltage applied to the portions between the adjacent internal electrodes 102 formed on the main surface of the same dielectric substrate 101, and, secondly, the voltage applied to the portions between the adjacent internal electrodes 102 formed on the dielectric substrates 101 overlapped in the laminating direction.
However, in the multilayer capacitor in the related art, the internal electrodes 102 are formed on the main surface of each dielectric substrate 101 at regular intervals with inter-electrode distance W therebetween. Therefore, the inter-electrode distance W between the adjacent internal electrodes 102 formed on the same dielectric substrate 101 is equal throughout the multilayer capacitor 100. In addition, since each laminated dielectric substrate 101 has the same thickness, the interval between the internal electrodes 102, which are formed on the different dielectric substrates 101 and adjacent in the laminating direction, is also equal in the laminating direction.
Due to the above fact, when a certain voltage is applied to the multilayer capacitor 100, there occurs a difference between the withstand voltage in the vicinity of the central portion of the multilayer capacitor 100, which is the weakest portion to stress, and the withstand voltage in the other portions. In addition, the withstand voltage in the vicinity of the central portion, which is the weakest portion to stress, becomes the withstand voltage of the multilayer capacitor 100. As a result, there is a case that cracks are caused in the internal electrode due to the stress caused by the piezoelectric effect. Furthermore, there has been a problem in that countermeasures for achieving the high withstand voltage and high reliability have never been devised sufficiently.
In order to solve the above problem, it is possible to improve the withstand voltage by increasing the area of the main surface and the thickness of the main surface of the dielectric substrate 101. However, in this case, the size of the multilayer capacitor 100 increases, which is incompatible with the recent trend requiring the size reduction of a device. As a result, it is demanded to develop a multilayer capacitor capable of improving the withstand voltage and achieving the high capacitance with no size increase.

Matsushita Electric Industrial Co., Ltd.


Grass cutting machinery particularly suitable for mowing golf greens which are covered in early morning dew has an apparatus for preparing the grass in advance of the grass cutting blades. This relies on creating a flow of air around the dew covered grass to dislodge the dew from the grass. The flow of air can be effected by a blower, or suction.

The present invention relates to grass cutting machinery, and to attachments for use with such machinery.
It is common knowledge that conventional lawn mowers cannot achieve a satisfactory cut of a lawn that is covered in dew. This is a particularly troublesome and inconvenient problem facing grounds men who are required to mow golf greens early in the morning, before the greens can dry out. Since wet greens cannot be mowed directly with conventional lawn mowers, a common approach is to manually wipe the moisture off the green using a very long flexible cane which is switched across the turf. This pre-mowing operation is of course hard work and time consuming, and makes cutting the greens a two-stage process.
It is therefore an object of the present invention to provide means for cutting dew covered grass, without requiring separate prior preparation of the grass.
Accordingly, the present invention provides grass cutting machinery comprising a grass cutting element and means for creating a flow of air to dislodge water droplets from grass, prior to cutting.
In one embodiment of the present invention, blower means creates the flow of air. Preferably, the blower means comprises nozzle means positioned in advance of the grass cutting element. In use, the blower means dislodges water droplets from grass by blowing the droplets off the grass.
In an alternative embodiment of the present invention, suction means creates the flow of air. Preferably, the suction means comprises nozzles means positioned in advance of the cutting element. In use the suction means dislodges water droplets by sucking the droplets off the grass.


A predictive caching system for use in computer system having at least one portion of memory in which information is stored for retrieval, a general cache used to speed the operation of accessing such memory, and a processor for controlling the access of the memory comprising apparatus for discerning a pattern of access of the memory, apparatus operating in response to the pattern determined by the apparatus for discerning a pattern of access of the memory for determining a next address which will probably accessed in such memory if the pattern discerned continues, and apparatus for storing the information at the next address determined prior to the next access of the memory whereby the information at the next address is available without the need to access the memory.

1. Field of the Invention
This invention relates to caching arrangements used in computer systems and, more particularly, to methods and apparatus for caching data expected to be used by such systems.
2. History of the Prior Art:
In computer systems, the access of main memory to retrieve information often takes a substantial portion of the operational time. This occurs for various reasons. First, main memory is random access memory which is often sufficiently large that its cost is kept within bounds by using relatively slow memory devices. Second, in systems using virtual memory arrangements to increase the addressable space without increasing the physical size of the main memory, it is necessary to address information in both main memory and secondary memory such as magnetic disk storage by means of memory management arrangements which utilize look-up tables to translate virtual addresses to physical addresses. This indirect addressing requires a substantial amount of time.
For this reason, the use of cache memories to increase system speed has become prevalent in more advanced systems. A cache memory makes use of a relatively small amount of fast (and therefore expensive) random access memory in which recently used instructions, data, or both are stored as they are used by a processor. Such information is then available in the cache memory so that it may be more rapidly accessed by the associated processor when next required. The basic theory of caching is that, in general, information which has been recently used is more likely to be used sooner than is other information. The cache memory is often both physically faster than the random access memory used for main memory and is arranged so that it may be addressed more rapidly than may main memory by obviating the need for the look-up operation to determine physical addresses. Such caching arrangements have operated to greatly increase the speed of operation of computer systems for certain types of information.
Caching works well in situations where the same information is repeatedly utilized in carrying out an operation. An example of such a use is found in executing an instruction including a looping operation. Caching does not usually work well in situations in which entirely new information is used in each step of the operation. For example, in scrolling down the screen of a computer output display which shows approximately one thousand pixels of eight bit bit-mapped color information in each of the horizontal and vertical directions, approximately one megabyte of data is traversed. A typical cache memory may hold sixty-four kilobytes of information. A scrolling operation essentially reads information in a first scan line and writes that information to the next line below or above. When the cache is used to accomplish scrolling, it can hold only a few lines from such a frame buffer. Thus, except for the first few lines, none of the information which has been placed in the cache memory is reused so no increase in speed is accomplished. Moreover, since for the greatest part of the scrolling operation the processor is continually filling the cache memory with new information, the operation takes much longer using a cache memory than it would without a cache memory. In such a cache fill operation, the processor must first look to the cache memory for the information, determine that the information is missing in the cache memory, go to the look-up tables for the physical address of the information, access the information to be used in main memory, store that information in the cache memory replacing other information, and finally use the information. Such an operation must repeat continuously during a scrolling operation so that the fact that the operation takes longer than a simple access of main memory should not be surprising.
One method of increasing the speed of operation of a computer is to design the processor to handle instructions which are pipelined so that one instruction is executed during each clock cycle of operation. While the early pipelined computer systems using caching demonstrated a loss of approximately four instructions for each cache memory miss, the faster systems being designed at present will have a loss of as much as sixty-four instruction times for each cache miss. This is a very large delay in a fast computer system. For this reason, many systems now include methods for disabling the caching operation in situations in which it may delay the operation of the system. Although such methods eliminate the delays caused by the caching of certain information, they do not speed the handling of that information in any other way.

Predictive caching method and apparatus for generating a predicted address for a frame buffer