A voltage-controlled oscillator frequency range detector is disclosed that detects when the voltage-controlled oscillator frequency within a phase-locked loop is out of range and indicates the required direction of the frequency adjustment. The voltage-controlled oscillator frequency range detector includes a comparator circuit, which receives a voltage-controlled oscillator control voltage signal, and a frequency detector circuit, which receives a reference clock signal and a voltage-controlled oscillator clock signal. Decision logic circuitry, coupled to the comparator circuit and to the frequency detector circuit, receives at least one output from the comparator circuit and an output from the frequency detector circuit and indicates whether an adjustment to a voltage-controlled oscillator frequency is required and its direction.

1. Field of the Invention
The present invention relates generally to electrical circuits and, more particularly, to voltage-controlled oscillators.
2. Related Art
Frequency synthesizers, such as a multi-rate fractional-N frequency synthesizer, are well known. In a typical frequency synthesizer (e.g., a phase-locked loop), a frequency adjustment is required when the maximum or minimum frequency of the voltage-controlled oscillator (VCO) is not sufficient to synthesize the desired frequency. A common technique is to adjust the center frequency of the VCO by laser trimming certain circuit elements, such as a capacitor or a resistor, that control the VCO frequency to adjust the VCO center frequency to within its frequency-capture range.
One drawback of physical trimming is that the range of frequencies is permanently limited. For example, in a fractional-N synthesizer, which is capable of synthesizing hundreds of frequencies (e.g., each selected by a set of programmed bits), physical trimming permanently constrains the range of frequencies that can be synthesized to less than what could possibly be generated by the synthesizer. Furthermore, physical trimming incurs additional cost and time because the VCO frequency for each synthesizer must be measured and trimmed as necessary.
A VCO frequency range detector is disclosed herein. The VCO frequency range detector detects when the VCO frequency is out of range and indicates the required direction of the frequency adjustment. The VCO frequency range detector may be used, for example, as part of a VCO frequency-trimming block in a multi-rate fractional-N frequency synthesizer. Physical trimming is thus eliminated by introducing on-chip trimming circuitry that adjusts the VCO frequency when it is out of range by executing adjustments based on the signals received from the VCO frequency range detector.
In accordance with one embodiment of the present invention, a voltage-controlled oscillator frequency range detector includes a comparator circuit, which receives a voltage-controlled oscillator control voltage signal and provides at least one output signal based on a comparison of the voltage-controlled oscillator control voltage signal to a maximum or minimum voltage level, and a frequency detector circuit, which receives a reference clock signal and a voltage-controlled oscillator clock signal and provides an output signal indicating which is at a greater frequency. The voltage-controlled oscillator frequency range detector further includes a decision logic circuit coupled to the comparator circuit and to the frequency detector circuit. The decision logic circuit receives at least one output signal from the comparator circuit and the output signal from the frequency detector circuit and indicates whether a frequency adjustment to a voltage-controlled oscillator is required.
In accordance with another embodiment of the present invention, a method of detecting when a frequency of a voltage-controlled oscillator within a phase-locked loop is out of range includes receiving a voltage-controlled oscillator control voltage; comparing the voltage-controlled oscillator control voltage to a maximum voltage level and a minimum voltage level and providing a first result; receiving a reference clock signal and a voltage-controlled oscillator clock signal; comparing the reference clock signal to the voltage-controlled oscillator clock signal and providing a second result; and determining whether the frequency of the voltage-controlled oscillator is out of range based on the first result and the second result.
A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.

Voltage-controlled oscillator frequency range detector


A vehicle control device is a vehicle control device for a vehicle capable of coasting, in which when there is no acceleration or deceleration request to the vehicle while traveling, power transmission between an engine and drive wheels is cut off and the vehicle is allowed to travel by inertia, wherein in a state in which there is no acceleration or deceleration request to the vehicle while traveling and power is transmitted between the engine and the drive wheels, whether or not to implement the coasting is determined by comparing a required deceleration rate Dt which is estimated as a deceleration rate to be later required of the vehicle and a coasting deceleration rate Dn which is estimated as a deceleration rate during the coasting. Where it is determined to implement the coasting, power transmission between the engine and the drive wheels is cut off and the coasting is implemented, and where it is determined not to implement the coasting, power transmission between the engine and the drive wheels is maintained. As a result, the implementation of coasting that can provide a sense of anxiety or discomfort to the driver can be suppressed.

A vehicle is available that is capable of coasting in which an engine and drive wheels are disconnected while traveling and the vehicle travels by inertia in order to inhibit fuel consumption. For example, Patent Document 1 discloses a technique of taking an accelerator depression amount and a clutch revolution speed as indexes and determining whether or not to execute coasting on the basis of the movement of the coordinate points of those indexes on a coasting control determination map.
Patent Document 1: Japanese Patent Application Publication No. 2010-203544


A process for partially swapping real storage areas used by a program is utilized in a computer system which executes programs by multiprogramming under control of a virtual storage type operating system. A first portion of a real storage area, allocated to a program to be swapped out, remains allocated to that program while the contents of a second portion of the real storage area are saved in an auxiliary storage so that the second portion is deallocated from that program. The saved contents of the second portion stored in the auxiliary storage are loaded in the real storage when the program is to be swapped in.

The present invention relates to main storage management processes for a computer system using a virtual storage.
In a conventional computer using a virtual storage type operating system, a demand paging system is known as a main storage management system. More specifically, as described in HITAC Manual "VOS3/ES Center Managed -JSS3 Vol. 3-" (1987), pp. 58-80, or P. B. Hansen: "Operating System Principles", Prentice-Hall (1973), pp. 176-182 and 213-224, the main storage management system includes both paging and swapping processes.
The paging process maintains, in executable form, a job executed by a CPU while allocating to the job a real storage area which the job requires. It dynamically allocates and releases (deallocates) pages of a real storage to and from a virtual page which is a fixed length unit of a virtual storage. The time interval from the time when each of real pages allocated to a virtual page is referred to last to the current time (unreferenced time interval) is measured. When a shortage of real pages not already allocated to virtual pages occurs, the real pages are released in order of unreferenced time intervals.
The swapping process is used, on the other hand, to reserve further execution of a job under execution, to save the contents of a real storage allocated to the job in an auxiliary storage in order to release the area in the real storage (swap out), and then to load in the real storage all the saved contents when the job is recovered to a re-executable state (swap in). Paging is effected for each page in the real storage while swapping is effected for all pages which a program, for example, a job, is using.
In the conventional technique, if the capacity of the real storage area which a job to be swapped occupies is large, a quantity of transfer of data or a program deriving from swapping between the real storage and an auxiliary storage becomes large. These are overhead (unnecessary) operations for execution of programs by the computer. Therefore, a portion of time for which a central processing unit (CPU) and an input/output (I/O) device are used for purposes other than execution of programs increases in proportion to the quantity of real storage. Thus, a state is brought about that the job under execution is likely to wait for the CPU and I/O, and the processing efficiency and responsiveness of the system decreases. This state is called a slashed state. If paging is employed to solve a shortage of the real storage, paging occurs frequently because large-scaled jobs being executed compete with each other with respect to the real storage. Thus a slashed state is brought about disadvantageously as in the swapping of the large-scale job.
Japanese Patent Publication JP-A 60-54058 discloses a process for swapping a job with a reduced overhead. A swapping operation of a job which performs transactions is executed when the job completes one of the transactions and then enters into a waiting state. What is saved in the auxiliary storage is a program area (including not only an area for program instructions but also data buffer area designated by a user). The contents of work areas which the system has allocated to the program are not required for the subsequent transaction to be executed by the job, so they are not saved to the auxiliary storage but, rather, are released.
The above-mentioned prior art reduces an overhead on swapping by not saving data in work areas which are not to be used later by the job. The program area containing programs and data used later are all saved (swapped out), so the overhead due to the swapping is still large for a large scale job.
A multiple virtual storage system is also known in which each of the jobs can access a plurality of virtual storage spaces. Such a system has other problems with paging and swapping.
A computer system using such a paging type multiple virtual storage process is described, for example, in IBM Manual SA22-7200-0, "IBM Enterprise System Architecture/370 Principles of Operation", pp. 3-1 to 3-47, 5-26 to 5049 (Aug. 1988).
Specifically, as shown in FIG. 2 a virtual storage 100, a real storage 103, and an auxiliary storage 104 are each divided into units of a fixed length referred to as pages. A real page 108 and an auxiliary page 109 are allocated for each of virtual pages 106 and 107. For example, a j-th real page 108 and a k-th auxiliary page 109 are allocated to an i-th virtual page 106. The correspondence between these pages is provided by a conventional address converter (not shown). The virtual storage spaces include an address (data) space capable of accommodating both programs and data and data spaces each capable of accommodating only data. One job is capable o using one address space 101 and a plurality of data spaces 102. As shown in FIG. 3, the system includes a group of 16 space registers, designated generally by 201, which hold space identifiers, each indicative of one of virtual storage spaces to which belongs the address stored in each of a group of 16 general-purpose registers #0-#15 designated generally by 200. A reference bit storage 4 (FIG. 2) holds a reference bit corresponding to each real page, indicative of whether or not the corresponding real page has been referred to. FIG. 3 schematically shows the relationship between the contents of the group of general purpose registers 200, the group of space registers 201, and the spaces in the virtual storage. In FIG. 3, it is assumed that general purpose registers #1 and #2 have addresses in address space 101 in virtual storage 100 while general-purpose registers #3 and #15 each have addresses in one (102A or 102B) of data spaces 102 in virtual storage 100 and that the corresponding space registers #1, #2, #3 and #15 hold space identifiers o, 0, 3 and 1 of address space 101, address space 101, data space 102A and data space 102B, respectively. When a central processing unit (CPU) is taken away from the job under execution, the contents of each of the space registers 201, are saved in a space register saving area 211 in a job control table (JCT) 210 provided on real storage 103 and corresponding to the job. When the job is assigned to the CPU later on and the execution of the job is restarted, the saved data is again loaded in the group of space registers 201. The job control table 210 further includes a pair of address space identifier 214A and a real page pointer 213 indicative of the head of a list of real pages allocated to that address space, and plural pairs each of space identifier 212D of one data space and real pointer 213 indicative of the head of a list of real pages allocated to that data space. Reference numeral 214 denotes a pointer of a list of swapped-in jobs (in-job list) and a point of a list of swapped-out jobs (out-job list).
When pages allocated to a job are to be paged out in the prior art, contents of a virtual page having a longer unreferenced time interval are paged out irrespective of the virtual storage space (address space 101, data space 102) to which the job belongs. A real page allocated to a virtual page in a virtual storage space whose space identifier was stored in one of the space registers 201 often has a high probability that it will be used earlier than the real pages allocated to virtual pages in other virtual spaces among the virtual spaces used by the job.
However, if the unreferenced time for a real page having a high probability of earlier use is longer than that for a real page having a lower probability of earlier use, the former rather than the latter would undesirably be paged out.
Therefore, a paging process is desirable which reflects the degree of probability of earlier use of a real page.
Furthermore, in the above prior art, when a job is to be swapped in, real pages which were allocated to virtual pages are "swapped in" in an order of virtual spaces to which the virtual pages belong. The order of the virtual spaces is determined in accordance with a predetermined order of space identifiers. Generally, contents of the real page which were allocated to a virtual page belonging to a virtual storage whose space identifier was held in space register 201 when the job under execution directly before the job was swapped out often has a high probability that those contents will be used earlier than those of the real pages which were allocated to virtual pages in other virtual storage spaces among the virtual storage spaces the job used before.
However, in the above conventional process, if the identifier of a virtual space for a real page having a lower probability of earlier use precedes the identifier of a virtual space for a real page having a higher probability of earlier use within the predetermined order of the space identifiers, the contents of the former real page can be swapped in earlier than the contents of the latter real page. If the job is assigned the CPU and starts to be executed after start of swapping in of the job and before contents of all virtual pages in all the virtual storage spaces which were allocated to the job has been swapped in, it can occur that contents of real pages are swapped in yet correspond when a space identifier is reloaded in space register 201 for a virtual storage space to which the real pages are allocated. Thus, a fault interruption of a virtual storage occurs and execution of the job is delayed. Therefore, swapping which reflects the degree of probability of earlier use of a real page is desirable.

Process for partially swapping real storage areas used by a program between a real storage and an auxiliary storage


A method of and system for regulating voltage supplied by a local power supply to a remote load includes sensing a low frequency portion of the output voltage at the remote load, locally sensing a high frequency portion of the output voltage produced by the local power supply, and in response, controlling the output of the supply.

With an evolving need for faster computer systems, DC power supplies are employed to supply computer system components (e.g., processors, memory chips, etc.) with more current at decreased voltage levels for higher component operating speeds. In such low voltage/high current applications, voltage drops experienced between the power supply and the components, once deemed tolerable, are becoming problematic. For example, voltage drops due to parasitic impedance present in printed circuit board (PCB) traces and conductor interconnect points are no longer acceptable.
In addition, parasitic impedance may also affect the feedback system(s) used to regulate the power supply voltage. For example, by causing higher frequency content of the supply voltage to be filtered, additional phase delay may be introduced that reduces the stability of the feedback system and the accuracy of the output voltage being supplied to the computer system components (or other types of loads).

Method of and system for regulating output voltage


Methods and apparatus are provided for conveying configuration data to a programmable logic device integrated circuit. When the configuration data is loaded into configuration memory on the programmable logic device integrated circuit, the programmable logic device integrated circuit performs custom logic functions. The programmable logic device integrated circuit or an associated configuration device integrated circuit may be provided with power conversion circuitry and transceiver circuitry. The power conversion circuitry converts received radio-frequency signals into power. The power from the power conversion circuitry is provided to the transceiver, loading, and configuration memory circuitry. The transceiver circuitry is connected to an antenna that receives wirelessly-transmitted configuration data and is used to transmit confirmation messages following successful loading of the configuration data into the configuration memory.

This invention relates to programmable logic devices, and more particularly, to wireless programming of programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools use information on the hardware capabilities of a given programmable logic device to help the designer implement the custom logic circuit using the resources available on that given programmable logic device. When the design process is complete, the CAD tools generate configuration data files. The configuration data is loaded into the programmable logic devices to configure them to perform their desired custom logic functions.
Programmable logic devices can be programmed using special equipment called a programmable logic device programmer. In a typical scenario, large numbers of programmable logic devices are programmed with configuration data in an assembly-line fashion. The programmed devices are then installed in a system. Programmable logic devices can be programmed in this way at the original device manufacturer, electronics distributor, or at companies that are manufacturing products that use the programmable logic devices as parts.
Programmable logic devices can also be programmed after they have been installed in a system. For example, a configuration device that is located on the same board as a programmable logic device may be used to load configuration data into the programmable logic device when the board is powered up.
Both assembly-line programming and in-system programming rely on physical contact to form an electrical pathway between the source of configuration data and the programmable logic device. The need for physical contact during assembly-line programming can be burdensome, because it requires the transfer of programmable logic devices between hermetically sealed packages and the device programmer. Often thousands of parts must be handled in this way, which is time-consuming and cumbersome. In-system programming techniques are often not practical. For example, it is generally not possible to reprogram a programmable logic device after it has been installed in product such as a toy, industrial equipment, or a piece of consumer electronics. Physical programming methods also limit the recourses available to end manufacturers if the programmable logic device is accidentally programmed with an incorrect configuration. Often, the manufacturer is faced with the choice of reworking affected material or absorbing the loss.
It would therefore be desirable to provide improved programming processes for programmable logic device integrated circuits.

Programmable logic device integrated circuits with wireless programming


A system comprises a first enclosure comprising a plurality of device bays and a first enclosure virtual connect device that is configured to virtualize one or more of the device bays in the first enclosure. The system also comprises a second enclosure comprising a plurality of device bays and a management server communicatively coupled to the first enclosure virtual connect device. At least one bay in the first enclosure has a device included therein. That device uses an associated profile that defines, at least in part, how that device is virtualized. The management server is configured to migrate the profile for use by a device in a bay of the second enclosure.

Some computer systems comprise multiple enclosures contained, for example, within a rack. Each enclosure is capable of housing multiple computing devices such as servers (e.g., blade servers). In some such systems each server is operated according to a profile which defines such things as medium access control (MAC) addresses, World Wide Names (WWNs), from what source the server is to boot, etc. Operators of such systems generally cannot migrate the profiles between different enclosures. The inability to move profiles between enclosures can pose difficulties maintaining efficient usage of the computers and the applications that run thereon.

System using management server for migration of profiles for device bays in between enclosures

Hewlett-Packard Development Company, L.P.


A belt apparatus is configured to support the trousers worn by a person and to include a number of airbags that are deployable in a falling event to protect the person from bone breakages. The belt apparatus includes a flexible belt element and a fastener that appear and function in much the same way as an ordinary trouser belt, i.e., fitting through belt loops in trousers and being fastenable to itself to support the pair of trousers at the waist of the user. Despite the ordinary appearance of the belt apparatus, it includes one or more airbags internal thereto whose expansion is controlled by a control apparatus. Responsive to a falling event in a particular direction with respect to the user, the control apparatus triggers the rapid expansion of an airbag that is situated on the belt element in the particular direction with respect to the user.

Field
The disclosed and claimed concept relates generally to structures that are intended to protect a person from injury and, more particularly, to a belt apparatus that is structured to resist the breakage of bones as a result of a falling event.
Related Art
A person's bones are understood to gradually become more brittle and thus more subject to breakage as the person ages. It is also understood that a person's muscular tone and strength likewise decreases with age. The loss of muscular tone and strength can, along with other factors, can have a tendency to reduce balance and coordination in an older person, which can contribute to the potential that the person might experience a falling event, i.e., an event wherein the person falls onto a floor, against a wall, or against another object. The reduced muscular tone and strength also reduces the person's ability to catch himself or herself or to otherwise protect himself or herself during a falling event. Furthermore, the aforementioned brittleness of the bones in an aged person increases the likelihood that one or more bones might be broken as a result of a falling event.
It can therefore be said that, as a general matter, aged persons are relatively more likely to experience falling events, and such falling events are likely to involve a relatively greater impact because of the person's inability to catch himself or herself, with the result that an aged person is generally at a greater risk of the breakage of bones than a younger person. It is also generally understood that a significant skeletal break can be sufficiently detrimental to a health of an aged person that the aged person may die as a direct result of the breakage. At the very least, a significant bone breakage in an older person is detrimental to the person's health due to factors such as the increased potential for infection and the physical resources required to heal the bone break, and also due to the pain and suffering experienced by the person, as well as other factors.
It thus would be desirable to provide a solution that can help people, particularly aged people, to avoid bone breakages that would otherwise be significantly detrimental to the person's health.


A circuit for producing a data bit inversion flag comprises a first summed-current production unit for producing a first summed current, whose amplitude is proportional to the number of different data bits in two adjacent data words in a data burst, a second summed-current production unit for producing a second summed current, whose amplitude is proportional to the number of identical data bits in the two adjacent data words, and a current comparator comparing the first with the second summed current and producing a data bit inversion flag if the first summed current is greater than the second summed current.

1. Field of the invention
The invention relates to a circuit for producing a data bit inversion flag for the purpose of data inversion for a data burst which has been read from a memory chip, in particular for DDR-SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories).
2. Description of the Prior Art
FIG. 1 shows a computer system based on the prior art in which a memory chip and a controller chip interchange data via a common data bus. The increasing speed of computer processors or controllers requires a correspondingly higher speed for memory access operations or faster memory chips. The memory chip and the processor are clocked by means of a clock signal CLK.
Various generations of RAM stores have been developed, whose access rate rose constantly. The intervals of time in which new data which are read from the memory cell array or which are to be written are available at the data inputs/outputs of the memory chip in question were constantly shortened during this time. Taking synchronous dynamic RAMs (SDRAMs) as a basis, what are known as DDR-SDRAMs were developed, which have double the data rate. Such DDR-SDRAMs deliver data twice as quickly as conventional SDRAMs. DDR-SDRAMs do not double the clock rate, however, but rather two actions are executed in one clock cycle. Whereas conventional SDRAMs are always synchronized only to the rising clock edge of the bus clock, a DDR-SDRAM uses both the rising clock edge and the falling clock edge for data and command transmission.
The data transmission rate of the DDR-SDRAM, which corresponds to a double clock frequency, is almost 2 GHz for clock frequencies in the range from 800 MHz to 1 GHz.
During read access to the memory chip, data are read as a data burst, each data burst comprising a plurality of data words which each comprise a predetermined number n of data bits. The number of data bits within a data word corresponds to the bus width N of the data bus. In one data burst, for example, 4 data bits (m=4) each comprising 8 bits (n=8) are read. FIG. 2 shows the reading of a data burst from an SDRAM based on the prior art. The increasing operating frequency means that the inductive and capacitive coupling is increased, so that data corruptions arise. As the operating frequency increases, it becomes ever more difficult to transmit the data from the memory chip to the controller. A limitation in this context is the noise on the data lines of the data bus. The noise limits the validity period of the data and reduces the "data eye size". The more switching operations or data transitions occur on the data lines, the more the data corruptions increase, i.e. the bit error rate (BER) rises.
FIG. 3 shows the transmission of a data burst during a read access operation from a memory chip to a controller in a conventional data processing system based on the prior art. In the example shown in FIG. 3, a data burst containing 8 data words each comprising 8 bits is transmitted. When the memory chip has received a read instruction RD from the controller via a control bus, it transmits a data burst to the controller via the data bus after a certain latency. In the example shown, the memory chip transmits the following sequence of data words, namely: FF, 00, 00, EF, FF, 00, 02, FF. FIG. 3 indicates the number of bits arising in this context which change their value when moving from one data word to the next data word.
When moving from the first data word (FF) to the second data word (00), all the bits in the data word change their logic value. In the case of the next transition, none of the bits changes its logic value. When moving from the data word 00 to the data word EF, seven bits change their logic value.
To limit the noise caused by the switching, the GDDR4 (Graphics Data Double Rate) standard introduces what is known as data bit inversion (DBI). In this case, before the data are transmitted, a decoder is used internally in the memory chip to check how many data bits in a data word have changed relative to the data bit transmitted directly beforehand in the preceding data word. If the number of data bits which have changed exceeds half of the data bits in the data word, all the data bits in the subsequent data word are transmitted to the controller on the data bus in inverted form. The inversion of the data bits in the data word is indicated to the controller by additional transmission of a DBI flag. FIG. 4 shows such data bit inversion based on the prior art and for the example shown in FIG. 3.
Since more than half, namely, eight data bits change data state between the first two data words (FF, 00), the second data word is transmitted in inverted form as FF. Since likewise more than half of the data bits change their state between the inverted data word FF and the next data word 00 which is to be transmitted, the third data word is also transmitted to the controller in inverted form and as FF. Since only one data bit transition and hence less than half the number of data bits within a data word is inverted between the third inverted transmitted data word and the next data word EF to be transmitted, the fourth data word EF is transmitted to the controller in uninverted form etc. As can be seen from FIG. 4, the number of data bit transitions or switching bits is much smaller than in the case of a data transmission without data bit inversion, as shown in FIG. 3. FIG. 4 also shows the data bit inversion flag DBI transmitted in parallel, which indicates to the processor whether or not the received data word has been inverted.
FIG. 5 shows a circuit unit for data bit inversion in a data burst which has been read from a memory chip, based on the prior art. From the memory cell array, the entire data burst which has been read is first of all buffer-stored in a burst buffer store. By way of example, the burst buffer store is used to buffer-store m=4 data words each containing n=8 data bits. For each data word DW within the burst buffer store, an associated decoder is provided, for example m=4 decoders. Each decoder compares the data bits in a data word with those data bits in the preceding data word.
FIG. 6a shows a circuit design for a conventional decoder, as is used in the data bit inversion unit based on the prior art shown in FIG. 5. The data word which has been read from the burst buffer store is loaded into a register when an ENABLE signal (EN) is received.
At the same time, the preceding data word (DWi-1) in the data burst is likewise loaded into a register as a reference data word. FIG. 6b shows a conventional circuit arrangement for a DBI decision circuit based on the prior art. An XOR logic circuit compares the data content of the two registers bit by bit. A counting device counts the number of different data bits. A comparator compares the number of different data bits in the two data words with half the number of data bits within a data word. If the number of data bits within a data word is 8 bits, for example, the comparator compares the rounded-up number of different data bits with the value 4. If the number of different data bits is greater than half the number n of data bits within the data word, a data bit inversion flag (DBI) is set by the comparator. The DBI flag controls a multiplexer in the decoder internally. The data word DWi buffer-stored in the first register is switched through by the multiplexer either in inverted form or in uninverted form. When the comparator sets the DBI flag, there follows bit-by-bit inversion of the data bits. Once the comparator has finished the comparison, it forwards a READY indicator control signal to the next decoder within the cascade.
As can be seen from FIG. 5, the data words DW which are output by the decoders are applied to a parallel/serial converter which is activated by the READY control signal from the last decoder within the cascade. The parallel/serial converter converts the received data words and the associated data bit inversion flags into a serial data stream. A data bus is used to output a data burst comprising m data words, which each have a bit length n, and also m data bit inversion flags to the controller. As can be seen from FIG. 5, the decoders in the data bit inversion unit based on the prior art operate in serial fashion. The decoders are connected up as a cascade, i.e. a decoder I within the cascade always requires the output value from the preceding decoder i-1 within the cascade as reference data word in order to be able to make the necessary comparison. The parallel/serial converter P/S cannot start to convert the data words available in parallel form into a serial sequence until after the last decoder DECm within the cascade has finished the comparison and activates it by means of an ENABLE signal. The waiting time is thus m times the necessary decoding time for a decoder i within the cascade:Twait=m TDEC
If the decoding time for a decoder DECi within the cascade is 1 nanosecond, for example, and if a data burst comprises m=4 data words then the waiting time is 4 ns.
The increased waiting time results in an unwanted delay in the memory access time for data within the memory chip. This has an overall negative effect on the system performance. The serial processing during the DBI assessment results in a long time delay for the parallel data transmission, since it is necessary to wait until the decoding of the last data word within the data burst has ended. All the data which have already been processed have to wait this time until they can be processed further in parallel.
FIG. 6c shows an alternative conventional circuit arrangement for a DBI decision circuit within a decoder based on the prior art. In this conventional DBI decision circuit, the different data bits which an EXOR circuit detects between two adjacent data words are supplied to a memory in which a table is stored. For each of the 2n possible values, the stored table contains an associated data bit inversion flag value. If the number n of data bits within a data word DW is 8 bits, for example, then there are 28=256 possible combinations. For each combination for which the number of data bits having the value 1 is more than half n/2 the number n=8 of data bits within the data word, the stored data bit inversion flag DBI has a logic high value. Conversely, for each combination for which the number of logic high data bits is less than half the number n of data bits within a data word DW, the associated data bit inversion flag DBI is stored with the value 0. The memory thus forms a full decoder for all 2n bit combinations. The memory may be replaced by a logic circuit.
Both the data bit inversion decision circuit shown in FIG. 6b and the data bit inversion decision circuit shown in FIG. 6c based on the prior art are relatively slow. The necessary time for producing the data bit inversion flag DBI is thus relatively long, which means that the memory access time for accessing the memory chip is increased overall.
A further drawback of the conventional data bit inversion decision circuits shown in FIGS. 6b and 6c is that the circuit complexity is likewise relatively high, which means that the chip area required for integration of a semiconductor chip is large. This increases the costs of implementation.
It is an object of the present invention to provide a circuit for producing a data bit inversion flag in which the time required for producing the data bit inversion flag is minimal, which means that the memory access time is reduced.
The object is achieved in accordance with the invention by means of a circuit for producing a data bit inversion flag, having:
a first summed-current production unit for producing a first summed current, whose amplitude is proportional to the number of different data bits in two adjacent data words in a data burst,
a second summed-current production unit for producing a second summed current, whose amplitude is proportional to the number of identical data bits in the two adjacent data words in the data burst; and having
a current comparator which compares the two summed currents produced with one another and produces the data bit inversion flag if the first summed current is larger than the second summed current.
The inventive circuit for producing a data bit inversion flag may be preferably of purely analogue design. In comparison with the conventional DBI decision circuit, this avoids counting the EXOR results, which takes at least n clock cycles. The inventive circuit thus operates considerably more quickly.
In comparison with the conventional DBI decision circuit with full decoding, as shown in FIG. 6c, the inventive circuit avoids the relatively slow addressing and reading from a memory and the long signal propagation times which are required for an implementation with a logic gate. The inventive DBI decision circuit is thus much faster and, on account of the low circuit complexity, requires far less area for integration on a chip.
The idea on which the inventive circuit and the inventive method are based is to compare the number of different data bits in two adjacent data words in a data burst and the number of identical data bits in the two adjacent data words in the data burst with one another using a current balance.
The two summed-current production units may each be formed from transistors connected in parallel which are switched on the basis of the data bits.
Particularly, two adjacent data words may each be provided with an added supplementary data bit which has a firmly prescribed logic value, so that the number n of data bits within a data word is always uneven. By adding such a supplementary data bit with a fixed logic value, for example with a logic value 1, a certain decision is made even if the number of different data bits between two adjacent data words DW is precisely n/2. If the data words each comprise 8 bits, for example, and if precisely 4 bits of the two adjacent data words are unequal, then without adding a supplementary data bit the current balance would not swing distinctly in favour of inversion or noninversion.
The current comparator may be formed by a differential amplifier. This current comparator is preferably likewise of purely analogue design but delivers a digital result in the form of a data bit inversion flag.
The current comparator may be a clocked current comparator which is clocked by a data clock signal. This has the particular advantage that the current drawn by the inventive circuit for producing a data bit inversion flag is reduced overall, because clocked current comparators generally operate more quickly and draw no static current.
The current comparator may contain two inversion stages which each comprise two complementary transistors. The two complementary transistors in the first inversion stage may be connected to one another at a first node and the two complementary transistors in the second inversion stage may be connected to one another at a second node.
The invention circuit may be activated by a start control signal.
The current comparator may be connected to the first summed-current production unit at a third node and to the second summed-current production unit at a fourth node. The third node and the fourth node may particularly be shorted by means of at least one transistor when the inventive circuit has been deactivated.
The first node and the second node may held at a prescribed supply potential in the deactivated state of the inventive circuit by means of a PULL-UP circuit, the PULL-UP circuit may have transistors which are switched on the basis of the start control signal, and the two summed-current production units may be connected to one another at a fifth node.
The fifth node may be connected by a transistor to a prescribed supply voltage potential on the basis of the start control signal.
The data bit inversion flag may be tapped off for output thereof at the first node.
The first node and the second node are connected to a NAND gate for producing a Ready indicator signal (Ready).
The data bit inversion flag produced may control a multiplexer which takes the data bit inversion flag as a basis for switching through the present data word from the two adjacent data words in the data burst in inverted or uninverted form.
The transistors may be formed by MOS field-effect transistors. Particularly the MOS field-effect transistors may be N-MOS field-effect transistors.
The object is also achieved in accordance with the invention by means of a method for producing a data bit inversion flag, having the following steps, namely:                (a) a first summed current, whose amplitude is proportional to the number of different data bits in two adjacent words in a data burst, is produced;        (b) a second summed current, whose amplitude is proportional to the number of identical data bits in two adjacent data words in a data burst, is produced;        (c) the two summed currents produced are compared with one another; and        (d) the data bit inversion flag is produced if the first summed current is larger than the second summed current.

Circuit for producing a data bit inversion flag


A hand-held power tool includes a tool holder, a motor for rotational and/or percussive driving of the tool holder, and a magnetic field sensor disposed in a vicinity of the motor, where a magnetic field of the motor that is created by driving the tool holder by the motor is detectable by the magnetic field sensor. The hand-held power tool further includes a control device where the control device determines a load state of the motor in dependence on a detected magnetic field of the motor and differentiates between an idle mode of the hand-held power tool and a load mode of the hand-held power tool based on the determined load state of the motor.

The present invention relates to a hand-held power tool and to a method for operating a hand-held power tool.
Hand-held power tools often have load detection of an electric motor of the hand-held power tool. For example, the hand-held power tool can then be controlled in a closed-loop manner according to a determined load. In conventional hand-held power tool, the load is detected by measuring the current in the electronics of the hand-held power tool. The current measurement must be implemented in the power line. It is desirable to simplify and improve the load detection of an electric motor of the hand-held power tool.
Against this background, the object of the present invention is to provide an improved hand-held power tool and to improve a method for operating a hand-held power tool.
According to a first aspect, a hand-held power tool is provided. The hand-held power tool comprises a tool holder and a motor for rotational and/or percussive driving of the tool holder. The hand-held power tool also includes a magnetic field sensor for detecting a magnetic field of the motor that is created by the driving of the tool holder.
The hand-held power tool is for example a hammer drill, a chisel hammer, a combination hammer, a core drill or a screwdriver. The tool holder of the hand-held power tool is used to insert a rotatable tool, for example a drill or a chisel tool. The motor of the hand-held power tool is in particular an electric motor, for example an electric motor with an adjustable speed. The motor of the hand-held power tool is used in particular to set the tool in a rotary motion and/or an impacting motion by rotational and/or percussive driving of the tool holder. For example, the motor of the hand-held power tool is used to set the tool in rotation about a working axis by rotationally driving the tool holder around the working axis. By rotating the tool, an object, such as a base material and/or a wall, can be drilled. For example, the motor of the hand-held power tool is also used to set the tool in an impacting motion in a direction of impact by percussively driving the tool holder in the direction of impact. The direction of impact is in particular parallel to the working axis. An object can be chiseled by the impacting motion of the tool.
The hand-held power tool is set up for example in such a way that percussive driving of the tool holder does not begin until an object is machined. For example, by actuating a main switch of the hand-held power tool, the motor of the hand-held power tool is put into operation, as a result of which the motor rotates, for example at a specific motor speed. By putting the motor into operation, either only the motor rotates, for example in the case of a chisel hammer, or the motor and the tool rotate, for example in the case of a hammer drill. By pressing the switched-on hand-held power tool against the object to be machined, for example, the percussive driving of the tool holder is started. By starting the percussive driving of the tool holder, the tool performs impacting motions in the case of the chisel hammer and the tool performs rotary and impacting motions in the case of the hammer drill.
The magnetic field sensor of the hand-held power tool is arranged in the vicinity of the motor. The magnetic field sensor is for example a Hall sensor, a magneto-resistive sensor or a field plate sensor. However, other magnetic field sensors can also be used in the hand-held power tool. The magnetic field sensor detects the magnetic field of the motor that is created by the driving of the tool holder. In particular, the magnetic field sensor measures a magnetic field generated by a current-carrying conductor of the motor. This means that, with the aid of the magnetic field sensor, a current measurement of the motor can be carried out indirectly through the magnetic field measurement. In particular, by detecting the magnetic field of the motor, a current of the motor required to drive the tool holder is measured.
As a result of the magnetic field sensor, a contactless and accurate current measurement of the hand-held power tool, in particular the motor, can take place. In particular, the magnetic field sensor can be used as a basis for contactless and accurate load detection of the hand-held power tool, in particular the motor. In particular, it is not necessary for load detection to implement a current measurement in the electronics of the hand-held power tool.
Because load detection of the hand-held power tool can be carried out in a contactless and accurate manner by means of the magnetic field sensor, different operating states of the hand-held power tool can be detected and/or differentiated from one another.
According to one embodiment, the magnetic field sensor is arranged in the hand-held power tool in such a way that it detects as the magnetic field of the motor a magnetic field of a current that is consumed by the motor when the tool holder is driven.
The magnetic field sensor is arranged in particular in the area of a power line of the motor. The power line of the motor is in particular a current-carrying conductor that connects a power supply to the hand-held power tool, such as for example a rechargeable battery or a power cord, to the motor. By supplying power to the motor through the power line, the motor drives the tool holder to perform rotary and/or impacting motions. A current flowing through the power line is dependent in particular on a power output required to drive the tool holder. Consequently, a magnetic field generated by the current flowing through the power line is also dependent on the power output required to drive the tool holder. In particular, the current intensity of the current flowing through the power line is low when the hand-held power tool is operated under low load in the idle state, and the current intensity of the current flowing through the power line is high when the hand-held power tool is machining a workpiece, that is to say is operated under load.
Because the magnetic field sensor is arranged in the hand-held power tool in such a way that it detects as the magnetic field of the motor the magnetic field of the current that is consumed by the motor when the tool holder is driven, a then-applicable current intensity required for driving the tool holder can be detected. This means that the then-applicable power consumption of the motor can be recorded.
According to a further embodiment, the hand-held power tool has a control device for determining a load stale of the motor in dependence on the detected magnetic field.
In particular, the control device receives the magnetic field of the motor detected by the magnetic field sensor as a signal. The control device determines a load state of the motor, for example by comparison with specific limit values. The load state of the motor is dependent in particular on a load applied to the hand-held power tool. The load state of the motor is for example an idle mode and/or a low-load mode. In an idle mode, the motor of the hand-held power tool is in particular in operation, but no workpiece is machined. The load state of the motor may also be for example a load mode and/or a high-load mode. In a load mode and/or high-load mode, a workpiece is machined, in particular in a rotating and/or impacting manner.
Because the hand-held power tool has a control device for determining the load state of the motor in dependence on the detected magnetic field, different load states can be detected during operation of the hand-held power tool and differentiated from one another. For example, the idle mode can be differentiated from the load mode. For example, the low-load mode can be differentiated from the high-load mode. For example, a purely drilling mode can be differentiated from a drilling and impacting mode. For example, an idle mode can be differentiated from an impacting mode.
According to a further embodiment, the hand-held power tool has an operating time counter for recording an operating time of the motor in dependence on the determined load state.
For example, the control device has the operating time counter. The operating time counter has for example a memory unit. The operating time counter is in particular set up to record and store the operating time of the motor separately for certain detected load states. For example, the operating time counter records the operating time of the motor in the idle mode separately from the operating time of the motor in the (high-)load mode.
Because the hand-held power tool has the operating time counter for recording the operating time of the motor in dependence on the determined load state, detection of the motor operating time can be improved.
According to a further embodiment, the control device is set up to set, in particular control in an open-loop or closed-loop manner, the hand-held power tool in dependence on the determined load state.
For example, the control device is set up to set the hand-held power tool in dependence on the determined load state in such a way that the motor speed of the motor is changed in dependence on the determined load state. As a result, the speed of the motor can be adapted to the load state, and consequently the energy efficiency of the motor can be improved.
Because the load state can be accurately detected by means of the magnetic field sensor and the control device sets the hand-held power tool in dependence on the determined load state, the hand-held power tool can be set very well, in particular controlled very well in an open-loop or closed-loop manner.
According to a second aspect, a method for operating a hand-held power tool is provided. The hand-held power tool has a tool holder and a motor for rotational and/or percussive driving of the tool holder. The method comprises a step of detecting a magnetic field of the motor that is created by the driving of the tool holder. The method also comprises a step of determining a load state of the motor in dependence on the detected magnetic field.
Properties and advantages that have been described for the hand-held power tool apply correspondingly to the provided method for operating the hand-held power tool.
According to an embodiment of the second aspect, the step of detecting the magnetic field of the motor comprises detecting a magnetic field of a current that is consumed by the motor when the tool holder is driven.
The magnetic field of the current that is consumed by the motor when the tool holder is driven is detected for example by detecting the magnetic field of the current that flows through the power line described in connection with the hand-held power tool.
According to a further embodiment of the second aspect, a chiseling mode of the hand-held power tool is detected when the determined load state exceeds a specific limit value.
For example, the chiseling mode of the hand-held power tool is detected when the detected magnetic field and/or the current intensity determined from the detected magnetic field exceeds the specific limit value. In particular, the control device compares the detected magnetic field and/or the current intensity determined from the detected magnetic field with the specific limit value. The specific limit value is for example a specific magnetic field strength and/or a specific current intensity. Because the chiseling mode of the hand-held power tool can be detected with the aid of the magnetic field sensor, the hand-held power tool can be set depending on whether or not it is in chiseling mode.
According to a further embodiment of the second aspect, the method comprises a step of determining an operating time of the motor in dependence on the determined load state.
The operating time of the motor is determined for example from the operating time counter described in connection with the hand-held power tool.
According to a further embodiment of the second aspect, the determination of the load state of the motor in dependence on the detected magnetic field comprises a differentiation between an idle mode of the hand-held power tool and a load mode.
As a result, the hand-held power tool can be set depending on whether it is in the idle mode or load mode.
According to a further embodiment of the second aspect, the hand-held power tool is a hammer drill and the determination of the load state of the motor in dependence on the detected magnetic field comprises a differentiation between a purely drilling mode and a drilling and impacting mode.
The hammer drill has in particular three different operating states. In an idle mode of the hammer drill, the motor and the drill rotate, but no workpiece is machined. In a purely drilling mode, the motor and the drill rotate and the drill machines a workpiece by means of a rotary motion about the working axis. In a drilling and impacting mode, the motor and the drill rotate and the drill machines a workpiece by means of a rotary motion about the working axis and an impacting motion in the direction of impact.
In the case of the hammer drill, the determination of the load state of the motor in dependence on the detected magnetic field may comprise a differentiation between the idle mode, the purely drilling mode and the drilling and impacting mode. This means that the hammer drill can be set depending on whether it is in the idle mode, purely drilling mode or drilling and impacting mode.
According to a further embodiment of the second aspect, the hand-held power tool is a chisel hammer and the determination of the load state of the motor in dependence on the detected magnetic field comprises a differentiation between the idle mode and an impacting mode.
The chisel hammer has in particular two different operating states. In the idle mode of the chisel hammer, the motor rotates, but no workpiece is machined. In the load state and/or impacting mode of the chisel hammer, the motor rotates and the chisel tool machines a workpiece by means of an impacting motion in the direction of impact.
Because, in the case of the chisel hammer, the determination of the load state of the motor in dependence on the detected magnetic field comprises a differentiation between the idle mode and the impact mode, the hand-held power tool can be set depending on whether the chisel hammer is in the idle mode or the impact mode.
According to a further embodiment of the second aspect, the method comprises a step of setting the hand-held power tool in dependence on the determined load state.
The setting is for example an open-loop control of the hand-held power tool in dependence on the determined load state. The setting may also be a closed-loop control of the hand-held power tool in dependence on the determined load state.
According to a further embodiment of the second aspect, the selling of the hand-held power tool in dependence on the determined load state comprises a changing of a motor speed of the motor in dependence on the determined load state.
The control device has for example a processor and a computer program executed with the aid of the processor. The control device, for example the computer program, comprises in particular an algorithm or a number of algorithms which is/are set up to determine a load state of the motor in dependence on the detected magnetic field and/or to set the hand-held power tool in dependence on the determined load state.
The respective unit, for example the processor, can be implemented in terms of hardware and/or also in terms of software. In a hardware implementation, the unit can be formed as a device or as part of a device, for example as a computer or as a microprocessor. In a software implementation, the unit can be formed as a computer program product, as a function, as a routine, as part of a program code or as an executable object.
A computer program product, such as for example a computer program means, can be provided or supplied, for example, as a storage medium, such as a memory card. USB stick, CD-ROM, DVI), or in the form of a downloadable file from a server in a network. This can be done for example in a wireless communication network by transmitting a corresponding file with the computer program product or the computer program means.
The embodiments and features described for the method apply correspondingly to the hand-held power tool and vice versa.
The following description explains the invention with reference to exemplary embodiments and figures.

Hand-held power tool and method for operating a hand-held power tool


The present invention includes compounds that are useful for treating or preventing a HIV-1 infection in a mammal. In certain embodiments, the compounds cause cell-free virolysis of an HIV-1 virus. The presented invention further includes a method of causing virolysis of a virus using the compounds described therein. The presented invention further includes a method of treating or preventing an HIV-1 infection in a mammal in need thereof using the compositions described therein.

The human immunodeficiency virus-1 (HIV-1) is responsible for a global epidemic, with over 33 million infected people worldwide. The lifecycle of HIV-1 has been extensively studied in the hope of identifying a therapeutic intervention that blocks viral transmission or viability. As an example, the Highly Active Anti-Retroviral Therapy (HAART) is a therapeutic approach targeting one or more stages of the HIV-1 life cycle. Favorable clinical results with HAART have shown that targeting different stages of the viral life cycle simultaneously may reduce the viral evolutionary escape mechanism that leads to drug resistance. HAART has proven effective at delaying the onset of AIDS in HIV-positive individuals, but does not provide a cure for the infection itself.
Despite decades of research, no vaccine- or microbicide-based approaches for preventing HIV-1 transmission to non-infected individuals are yet available. Even within the current space of prospective microbicides, there are no examples of clinically used agents or combinations of agents that directly and specifically destroy mature HIV-1 particles before they gain entry to a target cell. In fact, the leading microbicidal candidate is based on tenofovir, a reverse-transcriptase inhibitor. Thus, at this time there is no known therapeutically effective agent that specifically prevents HIV-1 entry and irreversibly destroys the virus, e.g., a therapeutic agent that directly and specifically destroys mature HIV-1 particles before they gain entry to a target cell.
A mature HIV-1 virion is an approximately one-attoliter-sized bilayer-enveloped packet of cytoplasm stolen from the cell from which the virion budded, surrounding the RNA-containing nucleocapsid. HIV-1 enters target cells via interactions between the viral envelope protein spike, Env, with the surface-expressed CD4 receptor and a chemokine co-receptor (CCR5 or CXCR4). Env is a metastable heterotrimeric protein complex of three transmembrane gp41 subunits anchored to the viral membrane and three labile gp120 subunits that interface with gp41. The infection process starts with gp120 binding to CD4 and induction of a conformational change that exposes the co-receptor binding site. In turn, the fusion peptide sequence on gp41 inserts into the host membrane. Subsequently, gp41 transitions from a "pre-hairpin" complex into a collapsed, thermodynamically stable six-helix bundle, with the three N-terminal heptad repeats of each gp41 protomer forming the core and the three C-terminal heptad repeats folded into grooves along the outside of this core. This refolding process evidently brings the N- and C-termini of gp41 close together and, in so doing, brings the apposing membranes into close enough proximity that fusion is initiated. Spike-mediated fusion of viral and cellular membranes requires that one of its functions is to induce poration of viral membrane.
There is a need in the art to develop novel potent compositions that promote cell-free virolysis of HIV-1 virus. Such compositions would be useful for the prevention or treatment of HIV-1 infection. The present invention fulfills this need.

Compositions for promoting HIV-1 virolysis and methods using same


The invention is directed to a pancratic system in an optical apparatus having a guide tube wherein at least one lens is moved in the guide tube. At least two guide rails are provided between the lens and the guide tube for guiding the lens. The surfaces of the intermediate spaces between the guide rails are configured so as to be poorly reflective and the space between the guide rails is also configured so as to be poorly reflecting.

Pancratic systems are utilized wherever a change of the magnification (also of the zoom) is wanted.
Reflections caused by glancing incident light present a special constructive problem because of the high optical performance specifications for optical apparatus. This applies especially to pancratic systems wherein holders are guided and moved in a lubricated bore because reflections are clearly visible in such systems under specific conditions.
U.S. Pat. No. 3,441,339 discloses a photoobjective wherein a lens is fixedly mounted in a lens holder tube. This lens holder tube is guided in an inner tube of the objective tube via three discrete holding bodies. These bodies have a relatively large spacing with respect to each other. In this connection, reference can be made to FIG. 1 of U.S. Pat. No. 3,441,339.
U.S. Pat. Nos. 4,322,150 and 4,448,496 disclose a zoom objective wherein an inner tube body is guided via four pins in another inner tube body having four recesses. Here, reference can be made to FIGS. 2 and 3 of U.S. Pat. No. 4,322,150 and FIGS. 11 and 12 of U.S. Pat. No. 4,448,496.
Swiss Patent 492,991 discloses an objective having a changeable focal length wherein the lens holder has three threaded lugs which are guided in three slots of an inner tube as shown in FIGS. 5 and 6 of this patent.


A system includes multiple devices configured to emit and detect germicidal radiation. Each of the multiple devices operates in emitting mode when connected to a drive source in a forward bias configuration and operates in detecting mode when disconnected from the drive source or when connected to the drive source in a reverse bias configuration. Cycling circuitry generates a sequence of control signals that control switching circuitry to change the connections of the devices to the drive source in a cycle in which one or more of the multiple devices are switched to detecting mode and senses radiation emitted by one or more of the multiple devices simultaneously operating in emitting mode. Each device operating in detecting mode generates a signal in response to the sensed radiation. Detection circuitry detects signals of the devices operating in detecting mode and generates a detection output in response to the detected signals.

Radiation-based disinfection systems use short wavelength photonic emission, e.g., emission in the ultraviolet (UV) range, to reduce microorganisms in fluids (e.g. drinking water) or on surfaces. UV radiation emitted by the source of a radiation-based disinfection system disrupts biological functions of microorganisms and retards or prevents their reproduction. Degradation or failure of the radiation source and/or loss of UV transmittance of the substance being disinfected can present a health risk. Therefore, the radiation intensity of the disinfection system may be monitored to detect changes that could compromise the disinfecting capability of the system.

Disinfecting system with performance monitoring


The present invention includes: image capturing means (2) which captures a color image of a road via imaging means (7); area extraction means (3) which extracts areas having a similar color feature value from the captured color image of the road; white balance processing means (5) which performs, for each of the extracted areas, a white balance process of correcting each pixel data in the extracted area so as to reduce the degree of divergence in the level between color components according to a level balance between the color components of the pixel data in the extracted area; and road sign detection means (6) which detects a road sign on the road from the color image subjected to the white balance process. Thus, even if the road illumination state is partially different, it is possible to accurately detect a road sign such as a lane mark from the captured color image of the road via the imaging means such as a camera.

In recent years, there has been suggested a technology for detecting a lane mark such as a white line on a road such as an express highway by capturing an image of the road along which a vehicle travels with imaging means such as a CCD camera mounted on the vehicle and processing the captured image (for example, refer to Japanese Patent Laid-Open No. Hei 11(1999)-85999 (hereinafter, referred to as Patent Document 1)).
The white line detection device for a vehicle in Patent Document 1 extracts an edge point (negative edge point) where binary data changes from light (white) to dark (black) over the entire image area and an edge point (positive edge point) where binary data changes from dark (black) to light (white) by using a monochrome image (black and white binary image) of a traffic lane obtained by the camera mounted on the vehicle. Then, the white line detection device for a vehicle performs a Hough transform for the positive edge point and the negative edge point independently and combines their Hough transform results to detect a white line.
Furthermore, a road sign (lane mark or traffic sign) other than a white line such as, for example, a yellow line is occasionally used. In this situation, it is difficult to accurately detect the road sign from a monochrome image. Therefore, there has been suggested a technology for detecting a road sign using a color image (for example, refer to Japanese Patent No. 3333468 (hereinafter, referred to as Patent Document 2)).
When a road image is captured by a camera, however, the road may be partially shaded by a building around the road, for example, as shown in FIG. 3(a) or the road may be partially illuminated by the headlights of the vehicle in some cases. If the road image is captured in a situation where the road illumination state is partially different according to the light sources illuminating the road surface or the environment around the road as described above, for example, a shaded area is illuminated only by scattered light and a color feature value of pixel data varies. Therefore, the yellow line located in this area is not recognized as a line having the original yellow color. Accordingly, there has been a problem that it is difficult to appropriately detect a road sign even if a color image is used as in Patent Document 2 in some cases.

Vehicle and road sign recognition device


A process for preparing 3-hydroxythiolane which is characterized in reacting a compound of the following formula,

The present invention relates to a novel process for preparing 3-hydroxythiolane.
The known processes for preparing 3-hydroxythiolane are illustrated as follows.    (i) The compound is prepared by converting the amino group of L-asparagic acid into halogen atom, reducing its carboxyl groups into diol, subjecting it to cyclization reaction to prepare 3,4-epoxy-1-butanol, sulfonating said hydroxy group, and then cyclizing it with sodium sulfide (J. Org. Chem. 57, 4352 (1992)).    (ii) The compound is prepared by hydroborating 2,3-dihydrothiophene with an optically active diisopinocamphenylborane (J. Am. Chem. Soc. 108, 2049 (1986)).    (iii) The compound is prepared by reducing tetrahydrothiophen-3-one in the presence of optically active catalyst (J. Am. Chem. Soc. 115, 3318 (1993) and Tetrahedron Lett. 34, 785 (1993)).

Abstract: wherein X is halogen atom, and R2 is substituted or unsubstituted alkyl group, substituted or unsubstituted aralkyl group, or substituted or unsubstituted aryl group, with a metal sulfide.


The present invention provides PRMT5 inhibitors of Formula (I), wherein R1 is a non-hydrogen monovalent group; W is a direct bond or —NH—; T, U, and V are independently of each other selected from C and N; R2 is H or a halo; m is 1 or 2; X is a carbon, a nitrogen, or an oxygen; Y is C or N; Z is a direct bond or a carbon; R3 is H, a non-hydrogen monovalent group, an oxo group, a bivalent spiro ring-forming group, or a bivalent bridge-forming group; n is 1 or 2; and Formula (II) stands for a single bond or a double bond. Pharmaceutical products comprising the PRMT5 inhibitors and use thereof in treating proliferative disorders such as cancer, metabolic disorders, blood disorders, autoimmune diseases, and inflammatory diseases are also provided.

Epigenetic regulation of gene expression is an important biological determinant of protein production and cellular differentiation, and it plays a significant pathogenic role in a number of human disorders and diseases. Typically, epigenetic regulation involves heritable modification of genetic material without changing its nucleotide sequence, and it is mediated by selective and reversible modification of DNA and proteins (e.g., histones) that control the conformational transition between transcriptionally active and inactive states of chromatin. These covalent modifications can be controlled by enzymes, many of which are associated with specific genetic alterations that can cause human diseases. For example, the methylation of protein arginine is catalyzed by the protein arginine methyl transferases (PRMTs) family of methyltransferases. Such methylation is a common post-translational modification that regulates numerous cellular processes, including gene transcription, mRNA splicing, DNA repair, protein cellular localization, cell fate determination, and signaling. Three types of methyl-arginine species exist: ω NG monomethylarginine (MMA), ω NG, NG asymmetric dimethylarginine (ADMA) and ω NG, N′G symmetric dimethylarginine (SDMA).
There are nine PRMTs annotated in the human genome. The majority of these enzymes are Type I enzymes (PRMT-1, -2, -3, -4, -6, -8) that are capable of mono- and asymmetric dimethylation of arginine, with S-adenosylmethionine (SAM) as the methyl donor. PRMT-5, -7 and -9 are Type II enzymes that catalyze symmetric dimethylation of arginines. Each PRMT species harbors the characteristic motifs of seven beta strand methyltransferases, as well as additional "double E" and "THW" sequence motifs particular to the PRMT subfamily.
PRMT5 is a general transcriptional repressor that functions with numerous transcription factors and repressor complexes, including BRG1 and hBRM, Blimp1, and Snail. This enzyme, once recruited to a promoter, symmetrically dimethylates H3R8 and H4R3. Importantly, the H4R3 site is a major target for PRMT1 methylation (ADMA) and is generally regarded as a transcriptional activating mark. Thus, both H4R3me2s (repressive; me2s indicates SDMA modification) and H4R3me2a (active; me2a indicates ADMA modification) marks are produced in vivo. The specificity of PRMT5 for H3R8 and H4R3 can be altered by its interaction with COPR5 and this could perhaps play an important role in determining PRMT5 corepressor status.
Chromatin-modifying enzymes may play a role in diseases such as proliferative disorders, metabolic disorders, and blood disorders. For example, PRMTs play an important role in cancer. Aberrant expression of PRMTs has been identified in human cancers, and PRMTs are considered to be therapeutic targets. For example, global analysis of histone modifications in prostate cancer has shown that the dimethylation of histone H4R3 is positively correlated with increasing grade, and these changes are predictive of clinical outcome.
PRMT5 levels have been shown to be elevated in a panel of lymphoid cancer cell lines as well as mantle cell lymphoma clinical samples. PRMT5 interacts with a number of substrates that are involved in a variety of cellular processes, including RNA processing, signal transduction, and transcriptional regulation. PRMT5 can directly modify histone H3 and H4, resulting in the repression of gene expression. PRMT5 overexpression can stimulate cell growth and induce transformation by directly repressing tumor suppressor genes. In addition to its oncogenic functions in transcription and translation, the transcription factor MYC also safeguards proper pre-messenger-RNA splicing as an essential step in lymphomagenesis.
The loss of the enzyme methylthioadenosine phosphorylase (MTAP) confers a selective dependence on PRMT5 and its binding partner WDR77. MTAP is frequently lost due to its proximity to the commonly deleted tumor suppressor gene, CDKN2A. Cells harboring MTAP deletions possess increased intracellular concentrations of methylthioadenosine (MTA, the metabolite cleaved by MTAP). Furthermore, MTA specifically inhibits PRMT5 enzymatic activity. Administration of either MTA or a small-molecule PRMT5 inhibitor shows a preferential impairment of cell viability for MTAP-null cancer cell lines compared to isogenic MTAP-expressing counterparts. It has been revealed that PRMT5 has a potential vulnerability across multiple cancer lineages augmented by a common "passenger" genomic alteration.
PRMT5 also plays a role in hemoglobinopathies. The developmental switch in human globin gene subtype from fetal to adult that begins at birth heralds the onset of the hemoglobinopathies, b-thalassemia and sickle cell disease (SCD). The observation that increased adult globin gene expression (in the setting of hereditary persistence of fetal hemoglobin [HPFH] mutations) significantly ameliorates the clinical severity of thalassemia and SCD has prompted the search for therapeutic strategies to reverse gamma-globin gene silencing. Central to silencing of the gamma-genes is DNA methylation, which marks critical CpG dinucleotides flanking the gene transcriptional start site in adult bone marrow erythroid cells. It has been shown that these marks are established as a consequence of recruitment of the DNA methyltransferase, DNMT3A to the gamma-promoter by PRMT5. PRMT5-mediated methylation of histone H4R3 recruits DNMT3A, coupling histone and DNA methylation in gene silencing. PRMT5 induces the repressive histone mark, H4R3me2s, which serves as a template for direct binding of DNMT3A, and subsequent DNA methylation. Loss of PRMT5 binding or its enzymatic activity leads to demethylation of the CpG dinucleotides and gene activation. In addition to the H4R3me2s mark and DNA methylation, PRMT5 binding to the gamma-promoter, and its enzymatic activity are essential for assembly of a multiprotein complex on the gamma-promoter, which induces a range of coordinated repressive epigenetic marks. Disruption of this complex leads to reactivation of gamma gene expression. These observations provide the basis for developing PRMT5 inhibitors as targeted therapies for thalassemia and SCD.
Therefore, there exists a need for the development of small molecules that are capable of inhibiting the activity of PRMT5, and treating various PRMT5-related disorders and diseases.

Inhibitors of protein arginine methyltransferase 5 (PRMT5), pharmaceutical products thereof, and methods thereof


An electrode adapted for implantation on or about the heart and for connection to a system for monitoring or stimulating cardiac activity includes an electrode tip which has one electrode at the far or distal end of the electrode tip. The distal end of the electrode further includes a screen capable of conducting electrical signals and pulses. An insulative masking member is positioned over a portion of the screen to define an electrical conducting surface. A conductor for carrying current is located within the electrode tip and is electrically connected to the conducting surface.

Electrodes implanted in the body for electrical cardioversion or pacing of the heart are well known. More specifically, electrodes implanted in or about the heart have been used to reverse (i.e., defibrillate or cardiovert) certain life threatening arrhythmias, or to stimulate contraction (pacing) of the heart, where electrical energy is applied to the heart via the electrodes to return the heart to normal rhythm.
The sick sinus syndrome and symptomatic AV block constitute the major reasons for implantation of cardiac pacemakers today. Cardiac pacing may be performed by the transvenous method or by electrodes implanted directly onto the ventricular epicardium. Transvenous pacing may be temporary or permanent. In temporary transvenous pacing an electrode catheter is introduced into a peripheral vein and fluoroscopically positioned against the endocardium. Permanent transvenous pacing is performed under sterile surgical conditions. An electrode is positioned in the right ventricle or atrium through a subclavian vein, and the proximal terminals are attached to a pacemaker which is implanted subcutaneously.
Leads may be unipolar or bipolar. A unipolar lead system contains a single electrode in direct contact with the cardiac tissue which is connected to the negative terminal of the pacemaker with the second electrode positioned remotely, and usually consisting of the metallic pacemaker housing. In a bipolar lead system, the electrodes are in close proximity to each other and are situated within or on the heart.
In the past the surface areas of the tip electrodes have been relatively large. Typically, the electrodes have been at least equal in surface area to the cross section of the casing near the lead tip. In some applications, such as where patch type leads are used, the surface area of the electrode is much larger than the surface area associated with the diameter of the casing. In order to deliver an adequate charge to accomplish pacing of the heart, the entire surface area of the electrode must be charged to a certain level. Larger surface areas require larger amounts of energy. Energy is now an issue as the pulse generators are implanted subcutaneously within the patient. Health care costs are under constant downward pressure and insurance companies are trying to contain costs. Pacemaker replacement costs are less with a pulse generator having longer battery life since patients do not have to undergo operational procedures as often. Patients also benefit from longer battery lives, since a longer battery life means a longer time between hospital visits.
U.S. Pat. No. 5,405,373 discloses a distal end electrode having a tip with a surface which has a diameter equal to the diameter of the casing or base near the distal end electrode. In U.S. Pat. No. 5,405,373 the external surface of the electrode head is coated with a highly resistive insulating material, such as diamond-like carbon, which is deposited on the tip surface of the distal end electrode. The insulative layer is thin enough so that the threshold value is not affected. In other words, the coating or layer of insulating or dielectric material does not cause a standoff that would cause an increase in the pacing threshold. Depositing the layer of diamond-like carbon is both difficult and costly. This results in a pacing lead that is difficult and expensive to manufacture.
There is a need for a high impedance pacing lead that has a tip that is smaller in diameter than the casing near the electrode tip. Such an electrode tip would result in the use of less energy and increased battery life. There is also a need for a tip that accommodates eluting anti-inflammatory drugs. There is also a need for a pacing lead that maintains existing manufacturing techniques without adding an expensive process and new bio-materials into the human body.

Electrode for high impedance heart stimulation


A power amplifier structure having: a power divider for dividing power in a signal fed to an input port between a pair of output ports. Each one of a pair of amplifiers has: an input coupled to a corresponding one of the pair of power divider output ports; and an output. A power combiner is provided. Signals at the power divider output ports are fed to the inputs of the pair of amplifiers in a forward direction and then pass through the amplifiers in the forward direction towards the outputs of the pair of amplifiers. Connectors direct the signals at the amplifier outputs to the power combiners, the signal then passing through the power combiner to an output port in a direction opposite to the forward direction.

As is known in the art, microwave power amplifiers, such as, for example, GaAs Monolithic Microwave Integrated Circuit (MMIC) amplifiers, are used in a wide variety of applications. In one application, an input microwave signal is split, or divide, using a power splitter, herein after sometimes also referred to herein as a power divider, into two quadrature paths, each path is fed a different amplifier, after power amplification in the amplifiers, the amplifier outputs are recombined in quadrature using a power combiner into a single output signal. There are many types of power dividers and combiners. One of the most popular versions for these applications is a Lange splitter/combiner. The Lange requires tight spacing between signal traces and therefore requires a high technology board fabrication. Often, the splitter/combiner function is actually a separate part and therefore requires interconnects that can drive cost based on assembly yield. An example of two amplifiers that are split and combined using a Lange combiner is shown in FIGS. 1 and 2. All power amplifiers are limited ultimately by the amount of FET periphery that can be reliably fabricated onto one MMIC. This limitation is a balance of thermal considerations and yield. To overcome this issue, power combiners are sometimes used to combine multiple power amplifiers in order to increase the total output power of a unit amplifier (two MMIC amplifier) cell.
There are many different configurations of power combiners and trade-offs to each one. The design trade-offs could be power handling, bandwidth, physical constraints, etc. . . . . The most popular form of power combining power amplifier MMICs is called quadrature combining. The quadrature splitter/combiner arrangement, shown in FIGS. 1 and 2, is used to properly phase combine the overall signal. The input signal is split, as noted above, while delaying one of the power amplifier inputs by 90 degrees (in quadrature). When the signals are re-combined at the output of the power amplifiers, the other signal is delayed by 90 degrees so that both signals combine in phase. This maximizes the overall power combined. The quadrature combiner also has the benefit that any mismatch signal that comes from the power amplifier being terminated in the 4th, or isolation, port, as shown in FIGS. 1 and 2. This is particularly important so that the power amplifier does not load pull the amplifier that drives the input signal. This ultimately helps maximize the total combined output power of the channel.
There are many types of quadrature dividers and combiners including Lange, branch line and overlay, such as, for example, described in U.S. Pat. Nos. 4,185,258 and 6,437,661 where an upper and lower overlaying conductors in regions R1 and R2 as shown in FIG. 2. They are all 4 port devices, where the 4th port is the isolation port. The Lange and branch line combiners are planar combiners, while the overlay is a 3-dimensional layout technique. Lange combiners have very good performance but can be expensive due to the high cost of board fabrication due to tight line to line spacing. Branch line combiners are also used extensively in power amplifier MMIC combining but are often physically large planar structures with very little design flexibility. Overlay combiners are rarely used for power amplifier combining but add the potential for 3-dimensional integration.
In power amplifier combining, cost and size are important considerations to the transmit/receive module designer. The Lange design often is fabricated as separate placeable components due to the cost if the yield of the combiner drives the yield of an overall integrated board. As a component, the Lange drives cost as a separate part as well as adding manufacturing yield issues due to component placement and wire bond interconnect issues. The branch line combiner in itself is fairly low cost technology but is very cumbersome in size which ultimately limits design flexibility and increases overall cost due to overall board size. Overlay combiners can be made in commercial quality boards and can decrease the amount of real estate needed but often have minimal size improvement due to underutilization of the full 3-dimensional capability.
Combining of power amplifier MMICs using quadrature combiners is an established practice within the industry using Lange, branch line and overlay combiners. Some characteristics of Lange couplers are: High technology, high cost boards required for line to line spacing; The yield of this function often drives it to be a separate part which is prone to higher cost and yield fallout due to component placement and interconnect issues; Planar structure uses a lot of space in the x-y plane. Some characteristics of branch line couplers are: Large structure that takes up a lot of space in the x-y plane; very little design flexibility to allow for compact layout. Overlay coupler Industry practice does not fully utilize the z-dimension for compact design

Compact microwave power amplifier circuit


A system is provided for the controlling the transmission of best-effort filed data or programs on channels from one of plural controllers to one or more client nodes. A program is a group of files and has program information indicating to a client node how to use the files of the program. A channel is a virtual path, wherein a client node can receive program files from different channels in a separate fashion. Channels also have channel information. Multiple controllers are provided which self configure in rank order to control the schedule transmission of programs files on channels. Client nodes receive announcements of programs and channels from the controllers and selectively subscribe to the channels and programs. Client nodes can be instructed to positively acknowledge receipt of programs and also send back negative acknowledgements for ranges of data words in a program files not received. The negative acknowledgements can be consolidated to reduce the number of packets on the network. The format of packets carrying program files and acknowledgement/negative acknowledgement messages are specified.

Many networks are known which deliver "best-effort" data, i.e., data delivered with the best efforts of the system at any given instant of time. Such best-effort data need not be strictly delivered piece-wise at any given rate, but rather can be delivered at an arbitrary or variably fluctuating rate. Generally speaking, the efforts by which best-effort data are delivered across the network do not affect the usefulness or utility of the information.
Often, it is desirable to schedule the communication of best-effort data which is available or which can be retrieved and readily made available.
Several communication networks are known which can deliver video or audio signals (hereinafter, "audio-video signals"), such as a terrestrial broadcast network, a cable network and a satellite network. Each of these networks can also deliver digital audio-video signals. In addition, it is also possible to deliver digital audio-video signals via a telephone network, e.g., using T1 (or higher capacity lines) and so-called DSL of digital subscriber loop lines.
In each of the networks described above, the audio-video signals are intended to be delivered in real-time, i.e., for real-time consumption. Specifically, the digital audio-video signals are delivered nominally at a rate that matches the consumption (decode and presentation) rate of the signal. Thus, if the audio-video signal is to be displayed at 30 frames of video per second, the digital information representing the video is nominally delivered at the rate of 30 frames per second. However, in the case that the audio-video signal, or a component elementary stream thereof, such as a video signal, audio signal, closed-caption text signal, etc., is variably compressed, the actual instantaneous bit rate actually fluctuates. Thus, some temporary buffering is required at the receiver/decoder end of the audio-video signal. Such buffer space is of a limited, predetermined size and the flow of digital information through the buffer (more concretely, the time at which each piece of digital information is inputted to or removed from the buffer) is strictly controlled. Therefore, these signals can be considered to be consumed nominally (more or less) at the same rate at which they are delivered.
As noted above, digital audio-video signal data delivered by one of the above noted networks is variably compressed. For example, video can be compressed according to any of the following standards: MPEG-1, MPEG-2, MPEG-4, H.261, H.263, H.320, JPEG, etc. Likewise, audio can be compressed according to any one of the following standards: "MP3" (MPEG-1 Layer III), MPEG-2, AC-3, AC-4, G.720, ATRAC, "MLP" (Meridian Lossless Packing), Delta-Sigma, etc. If the audio-video signal is variably compressed, the amount of information needed to represent a "presentation unit" or a given unit of playback time (e.g., a frame or field of video, an audio frame, etc.) varies from presentation unit to presentation unit. Variably compressed signals have timing and scheduling constraints described in the above-noted incorporated applications. Suffice it to say that in a multiplexed signal of one or more audio-video signals, each elementary stream has a strict piece-wise time delivery schedule that must be observed to enable proper real-time consumption of a given audio-video signal. Also, care must be taken to ensure that the relative spacing of time stamps of a given audio-video signal within a stream is not disturbed too much and that the values of such time stamps are adjusted to reflect any relative movement.
Some of the above networks can also deliver best-effort data as well as real-time data. Herein, best-effort data includes virtually any kind of data which can be delivered independently of the above noted restrictions. Such data can be a file containing, for example, executable code, an e-mail message, music, video mail, an "EPG" (electronic program guide), a web page, etc. Generally, each data stream of the type noted above is not consumed in real-time, i.e., more or less as delivered, or if executed in real-time, is tolerant of pauses in delivery or presentation of the data stream.
International Patent Application No. PCT/IB00/00605 teaches a system, employed in Assignee's zBand™ product. In this system, a "scheduler" at the head-end of the broadband communication network schedules the transmission of individual best-effort streams and retrieves them for insertion into the audio-video signal according to the schedule. The best-effort data streams are received and stored at a client device or node, which also employs part of Assignee's zBand™ product. The client node can use the best-effort data stored thereat. For example, if the data is a new "core image" or executable code for operating the client node, the client node executes the code. If the data is a video file, the video file is made available for playback by an operator of the client node.
It is desirable to improve this system. For example, it is desirable to provide multiple cooperating, self-configuring sources of the file data. It is also desirable to enable reliable best-effort data transfer. It is also desirable to improve the features of the client nodes to facilitate best-effort data reception.

Method and system for scheduled streaming of best effort data


A cell contacting system for an electrochemical device is provided, which includes a plurality of cell groups having one or more electrochemical cells, each having a first and a second cell terminal. The first cell terminals follow each other along the longitudinal direction in a first cell terminal region of the electrochemical device and the second cell terminals follow each other along the longitudinal direction in a second cell terminal region of the electrochemical device. The cell contacting system includes at least one cell connector extending obliquely to the longitudinal direction and configured for electrically conductively connecting cell terminals of a first cell group in the first cell terminal region to cell terminals of a second cell group in the second cell terminal region, which cell contacting system reliably enables a relative movement between the cell terminals to be electrically connected to each other.

In known electrochemical devices with cell contacting systems of the kind stated above, prismatic electrochemical cells are arranged next to each other in the longitudinal direction of the electrochemical device in such a way that in each cell terminal region, cell terminals with a positive polarity and cell terminals with a negative polarity follow each other alternatingly in the longitudinal direction of the electrochemical device. For producing a series connection of said electrochemical cells, in each case two directly adjacent cell terminals of different polarity are electrically conductively connected to each other by means of a cell connector which extends in parallel to the longitudinal direction of the electrochemical device from the one cell terminal to the other cell terminal and is secured on both cell terminals, for example by welding or screwing.
It is known in the case of such cell contacting systems for compensating relative movements between the electrochemical cells, for example due to different heat expansion, to provide the cell connector with a balancing element, for example in the form of a shaft.
If, however, the space available between the cell terminals to be connected to each other is limited, then the geometry of such a compensating element is subject to tight restrictions, the functionality thereof thus being compromised.

Cell contacting system for an electrochemical device