A silicone gel formulation is described having a Voland hardness of from about 6 to 20 grams, a tack of from about 17 to 35 grams, and a stress relaxation greater than 50%. The material is especially suitable for sealing the back end of connectors containing a multiple fine wires with gauges between about 14 gauge and 28 gauge. It is particularly suitable to seal the back end of an automotive connector subjected to a wide variety of harsh environmental conditions.

Permanently sealing wires in the back end of the connector can be accomplished with epoxies or other fast curing adhesives. However, differences in thermal expansion properties of the adhesive and the wire jacket may cause hair line cracks or fractures which would permit moisture to enter the connector and cause corrosion. Sealing wires entering a connector where reentry is necessary creates additional problems. Mastics or greases can be used but these are messy and/or flow at higher temperatures.
Effective sealing where reentry is a requirement or desirable has been achieved through the use of gel sealing materials as described in U.S. Pat. Nos., 4,600,261; 4,680,233; 4,777,063 and 5,079,300. All these preceding patents are completely incorporated herein by reference for all purposes. These gel sealing materials are cross-linked polymer solids extended with a non reactive fluid extender. Alternatively, the gels may be a cross-linked system which includes an excess of a reactive fluid such as the vinyl group material so that it acts like an extender as exemplified by Sylgard 527.RTM. and as taught in U.S. Pat. No. 3,020,260, the disclosure of which is incorporated herein by reference for all purposes.
The gel material is a substantially dilute system which exhibits no steady state flow. As discussed by Ferry, a polymer gel is then a cross-linked solution whether linked by chemical bonds or crystallites or some other kind of junction. The absence of the steady state flow is the key definition of the solid like properties while the substantial dilution is necessary to give the relatively low modulus of gels. The solid nature is achieved by a microscopically continuous network structure formed in the material generally through crosslinking the polymer chains through some kind of junction or the creation of domains of associated substituents of various branch chains of the polymer. The crosslinking can be either physical or chemical as long as the crosslink sites are sustained at the use conditions of the gel.
Gels produced by mixing styrenic triblock copolymers such as styrene-ethylenebutylene-styrene (SEBS) and styrene-ethylene propylene-styrene (SEPS) etc. and parafinic oils are comprised of glassy styrenic micropheres interconnected by a fluid extended elastomeric phase. The microphase separated styrenic domains serve as the junction points in the systems. The SEBS and SEPS gels are examples of thermoplastic systems. Whereas, silicone gels of the present invention are examples of thermoset gels. This class of gels is chemically cross-linked through the use of a multifunctional cross linking agent.
Although the silicone gels described in the above referenced patents and brochures have been shown to effectively seal a wide variety of articles, difficulties often arise when trying to seal two fine wires generally in the gauge found in automotive connectors where the wires are located in close proximity such as the back end of a connector. Thus, it would be highly desirable to have the benefits and ease of use of a gel sealing material with preferred sealing characteristics for use with twin or multiple wires in for example an automotive connector wherein the gauges of wires are between 18 and 26 gauge wire.

Silicone sealing material exhibiting high stress relaxation


Some embodiments are directed to a method, corresponding system, and corresponding apparatus for detecting unexpectedly high latency, due to excessive retries of a given storage device of a set of storage devices. Some embodiments may comprise a processor and associated memory. Some embodiments may monitor one or more completion time characteristics of one or more accesses between the given storage device and one or more host machines. Some embodiments may then compare the one or more completion time characteristics with a given threshold. As a result of the comparison, some embodiments may report, by the one or more host machines, at least one error associated with the given storage device. The error may be unreported by the set of storage devices.

As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
The increased use of technology and computers has generated a corresponding increase in digital data. This ever-increasing digital data requires a corresponding ever-increasing amount of storage space. The need for storage space for digital data has been fueled through many changes in society. For example, home computer users increased storage of multimedia data, especially video and photographic data, has served to increase the amount of storage space needed. Likewise, industry also requires increased storage space. As more and more business is being conducted electronically, there has been an ever-increasing demand and need for the storage of this vast amount of business data. Furthermore, there has been a demand to digitize the storage of once paper files in an attempt to decrease the overhead cost of this paper generation and storage.
With this increase of digital data, there has been a corresponding further reliance upon the integrity and required accessibility of the digital data. While storage device reliability has increased, these devices have not become infallible. One type of error that occurs in digital systems is a soft error (also known as a soft media error). Soft errors may occur when a hard drive fails to complete an input/output (I/O) access on the first pass, but does complete the I/O access after several retries. As used herein, an I/O access may also be referred to as an "I/O" or an "access." As the I/O does complete, no blocks are reallocated, nor is the error reported to the operating system. When an excessive number of soft errors occur, drive performance may degrade significantly, and overall performance may be adversely affected. Such performance degradation may affect a range of products that include (and/or use) storage devices.
Existing approaches describe methods for soft error detection in storage subsystems. For example, U.S. Pat. No. 7,562,264, U.S. patent application Ser. No. 11/516,909 (hereinafter "Tangvald"), and EMC CLARIION RAID 6 TECHNOLOGY (hereinafter "EMC") describe soft error detection in storage subsystems. Existing approaches rely on writing two separate data sets and comparing the data sets to detect transient discrepancies between the data sets.

Method for detection of soft media errors for hard drive


Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from the memory. If a first index I is greater than data size S, a second index is generated and output prior to outputting invalid data stored in the memory at the location of the first index.

1. Field of the Invention
The present invention relates generally to digital communications technology applied to a transmitter/receiver in a base station and a transmitter/receiver in a mobile station having a turbo encoder. In particular, the present invention relates to a device and method for effectively implementing an interleaver for a turbo encoder. In addition, the present invention provides a technique for removing a puncturing-caused delay.
2. Description of the Related Art
The transmitters/receivers in digital communication systems include channel encoders and decoders. The most widely used channel encoders are convolutional encoders and turbo encoders. The turbo encoder has an internal interleaver that changes the order of data output from a memory relative to the original order of the memory data input by generating random read addresses.
In general, when puncturing a signal and outputting the next valid signal in the course of successive signal outputting, the puncturing causes an output delay, that is, non-successive output of valid signals before and after the puncturing. FIG. 1 is a block diagram of a conventional interleaver 10. In FIG. 1, reference numeral 11 denotes an address generator for generating addresses to change the sequence of input data when it is output. The address generator 11 generates (K−S) invalid addresses if the size S of the input data is less than the size K of a two-dimensional matrix. Reference numeral 12 denotes a puncturer for puncturing the invalid addresses.
FIG. 2 illustrates a puncturing-caused output delay in the conventional interleaver 10. Reference numeral 21 denotes an example of an output signal of the address generator 11 shown in FIG. 1. Marked portions 21A and 21B indicate the positions of the invalid addresses. The puncturer 12 receives the addresses in the signal 21 and outputs a signal 22 shown in FIG. 2, puncturing the marked invalid addresses. As seen from the signal 22, the address signal is non-continuous due to the puncturing and the address after the puncturing is delayed.
This conventional technology is applied mainly to channel encoders and channel decoders in UMTS (Universal Mobile Telecommunication System) and requires additional complex operations to process a delay.
FIG. 3 is a block diagram of a turbo encoder 35 for use as a channel encoder in the UMTS system. Transmission data is fed to a first component encoder 31 and an interleaver 32 through an input port 30 in the turbo encoder 35. The first component encoder 31 encodes the input data and outputs a first parity bit P1. The interleaver 32 changes the order of output data from the original order of the input data. A second component encoder 33 encodes the interleaved data and outputs a second parity bit P2. In the meantime, the input data is simply output as a systematic bit X. Thus, the turbo encoder 35 outputs the systematic bit X, the first parity bit P1, and the second parity bit P2 for the input transmission data.
A controller (not shown) in the UMTS system determines the size of the input data ranging from 40 to 5112 bits and notifies the turbo encoder 35 of the number of input bits. Then, the turbo encoder 35 encodes the input data. The input data varies in length. The interleaver 32 includes a memory for sequentially storing the input data as it is received, and an address generator for generating read addresses according to a predetermined interleaving rule in order to output the input data in a different order. For example, a two-dimensional matrix of size K with 15 rows R and 16 columns C is 240 (K=RC), which is needed to store input data of size S of 237 bits. Therefore, the memory sequentially stores the 237-bit input data in the 240 storing areas of the matrix, leaving 3 bits of storage area unused. The address generator generates addresses according to the interleaving rule. If an interleaving index I, generated according to a predetermined interleaving rule, is greater than the input data size S (237), the address is neglected. If the generated index I is less than or equal to the input data size S (237), data stored at the address in the memory is output to the second component encoder 33. Having to neglect the addresses larger than data size S causes non-continuous data transmission to the second component encoder 33, and creates a time delay. The delay makes it difficult to estimate an accurate processing time in the interleaver 32 and additional control circuitry is required to reconstruct the non-continuous data into a continuous data stream.
Therefore, a need exists for effectively implementing an interleaver for a turbo encoder and to provide a technique for removing a puncturing-caused delay.

This patent is subject to a terminal disclaimer.

Device and method for minimizing puncturing-caused output delay


Disclosed is a multilayer ceramic substrate for electronic applications including:. (a) at least one internal layer having vias at least partially filled with a metallic material; PA1 (b) at least one sealing layer having vias at least partially filled with a composite material that is a mixture of ceramic and metallic materials wherein at least one via from the internal layer is aligned with at least one via from the sealing layer; and PA1 (c) a cap of material interposed between the aligned vias.. Also disclosed is a method of forming the multilayer ceramic substrate.

This invention relates to multilayer ceramic substrates, and more particularly relates to multilayer ceramic substrates useful for electronics packaging and to a method for making such substrates.
Glass, ceramic and glass ceramic (hereinafter just ceramic) structures, usually and preferably multilayered, are used in the production of electronic substrates and devices. Many different types of structures can be used, and a few of these structures are described below. For example, a multilayered ceramic circuit substrate may comprise patterned metal layers which act as electrical conductors sandwiched between ceramic layers which act as insulators. The substrates may be designed with termination pads for attaching semiconductor chips, connector leads, capacitors, resistors, covers, etc. Interconnection between buried conductor levels can be achieved through vias formed by metal paste-filled holes in the individual ceramic layers formed prior to lamination, which, upon sintering will become a sintered dense metal interconnection of metal based conductor.
In general, conventional ceramic structures are formed from ceramic green sheets which are prepared by mixing a ceramic particulate, a thermoplastic polymeric binder, plasticizers and solvents. This composition is spread or cast into ceramic sheets or slips from which the solvents are subsequently volatilized to provide coherent and self-supporting flexible green sheets. After blanking, via formation, stacking and laminating, the green sheet laminates are eventually fired at temperatures sufficient to drive off the polymeric binder resin and sinter the ceramic particulates together into a densified ceramic substrate.
The electrical conductors used in formation of the electronic substrate may be high melting point metals such as molybdenum and tungsten or a noble metal such as gold. However, it is more desirable to use a conductor having a low electrical resistance and low cost, such as copper and alloys thereof.
Present state-of-the-art ceramic substrates are made from cordierite glass-ceramic particulate materials such as that disclosed in Kumar et al., U.S. Pat. No. 4,301,324. These substrates exhibit a dielectric constant of about 5 and a thermal coefficient of expansion (TCE) that closely matches that of silicon. It is desirable to fabricate substrates out of low dielectric constant materials so as to increase signal propagation speed, which varies inversely with the square root of the dielectric constant.
Prior to the cordierite glass-ceramic materials, alumina for a number of years had been an adequate dielectric material for microelectronic packaging. Alumina, however, has a dielectric constant approaching 10 which causes high signal propagation delay and low signal-to-noise ratio. Further, alumina has a TCE about twice as high as silicon which impacts the thermal fatigue resistance of the package. For low end applications, however, alumina (as well as other similar materials having a dielectric constant of about 10 and below) will be used for some time to come.
The present inventors, however, have discovered a vexing problem that is applicable to many multilayer ceramic materials and substrates fabricated therefrom.
It has been found by others that the vias do not completely seal to the ceramic material, thereby possibly resulting in a gap between the metallic via and the ceramic bulk material. This gap is undesirable as it reduces the hermeticity of the fabricated substrate as well as allowing fluids to seep into the substrate during processing. Accordingly, it has been proposed in Farooq et al., U.S. Pat. No. 5,073,180, the disclosure of which is incorporated by reference herein, to seal at least the top layer of a multilayer ceramic substrate with a composite via material consisting of metallic and ceramic (including glass) materials. The internal vias are essentially all metal. As taught by Siuta U.S. Pat. No. 4,594,181, the internal vias may also include small amounts of alumina or other ingredients to inhibit the densification of the metallic via.
What the present inventors have found is that at the interface between the composite sealing via and the metallic internal via, and/or at the interface between the internal via and the bulk ceramic, there is a mismatch of thermal coefficients of expansion and some difference in densification behavior during cofiring which makes the interface susceptible to fatigue failure when the substrate is exposed to thermal stress during post-firing processing. The result is that an unrepairable open may occur at one of the above interfaces. If the net containing the open cannot be rerouted, the entire substrate must be scrapped.
It is, therefore, a purpose of the present invention to have a substrate which does not suffer from such thermal fatigue-enhanced opens.
It is another purpose of the present invention to have a process for making such a substrate.
These and other purposes of the present invention will become more apparent after referring to the following description of the invention considered in conjunction with the accompanying drawings.

Multilayer ceramic substrate with capped vias

International Business Machines Corporation


A method for cleaning up a background application, a storage medium, and an electronic device are provided. The method includes the following. Collect multi-dimensional feature information associated with an application as samples to construct a sample set associated with the application. Extract feature information from the sample set to construct multiple training sets. Train each training set to generate a corresponding decision tree. Predict, with multiple decision trees generated, current feature information associated with the application and output multiple predicted results when the application is switched to the background, where the predicted results include predicted results indicative of that the application is able to be cleaned up and predicted results indicative of that the application is unable to be cleaned up. Determine whether the application is able to be cleaned up according to the multiple predicted results. Clean up the application when the application can be cleaned up.

At present, multiple applications with different functions are usually installed in electronic devices such as smart phones to meet various users' needs. Currently, the system of an electronic device supports simultaneous running of multiple applications, that is, when one application runs in the foreground, other applications can run in the background. If one or more applications running in the background are not cleaned up for a long time, available memory of the electronic device may be reduced, and central processing unit (CPU) occupancy is relatively high, resulting in that the electronic device runs slowly, a lag appears, power consumption is speeded up, and so on. Therefore, it is necessary to provide a method to solve the above problems.

Method for cleaning up background application, storage medium, and electronic device

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


The present invention enables desktop applications to access web services through Plug-ins and a Web Service Proxy Server. An administrator registers a web service by providing the URL of the WSDL file of the web service. The target desktop applications and the operations are identified using the WSDL file. Operations that are not compatible with the desktop applications are removed from a published list of operations. The administrator appends additional formatting information, communication standards and security policies to the WSDL file. A user accessing the web services is first authenticated and authorized. Thereafter, the user accesses the web services through Web Service Proxy Server. The communication with the web services complies with the standards and security policies specified in the WSDL files. The output data obtained from the web services are presented using template documents. These template documents are generated based on the formatting information provided in the WSDL files.

Most business organizations require that their computational resources and the required data be available wherever and whenever they are needed. It is also desired that the data be accessed using any desktop application in a platform independent manner. Once this accessibility is achieved, the organizations can share data, integrate their processes, and join forces to offer customized and comprehensive solutions to their end users.
Before the Internet gained popularity, most organizations stored their data in large databases handled by mainframes. Dumb terminals with no processing capability were used to connect to the mainframe. Mainframes were used to process the data and present the output using dumb terminals. The mainframes being extremely expensive were beyond buying capacity of most of the organizations.
Later years witnessed the evolution of distributed data processing techniques. These techniques allowed different computers to share data and also to allow one computer to control a process on another computer. The distributed data processing technique was more flexible and less expensive than mainframes. However, there are few disadvantages associated with distributed computing. Firstly, server computers are required to coordinate different computers to work towards a goal. Secondly, security is a concern in distributed computing as data is frequently transferred between different computers. Thirdly, the maintenance of a distributed network is complex as each computer has its own share of problems and errors.
With an increase in popularity of the Internet, much of the data is now available over the Internet in the form of web pages. Much of the data needed by the businesses is now accessible from a remote location using the Internet. The information is stored in centralized databases that serve a page at a time to individual users. Thus, the information is scattered in the form of web pages. The user needs to manually search many web pages to extract relevant data, which is resource intensive, inconvenient and time consuming.
In addition to sharing data, standalone applications and web services were developed to provide isolated functionality and data. Each application/web service has a specific format of accepting input and presenting output, implementing security policies for connecting with a client, etc. In order to access a web service, a user needs to satisfy all the requirements set forth by the web service. In other words, a client needs to be compatible with a web service in order to access it. Most of the times, a user needs to access many applications and web services to obtain the required information. For example, the user may need to collect data from one application or web service and provide it to another application or web service. In these cases, the client needs to be compatible with multiple web services and applications, which requires programming effort. Therefore, much time, cost and resources are expended in resolving these compatibility issues.
In order to address the compatibility issues and the manner in which business organizations and consumers use the Internet, a new converged computing model has evolved. This model aims at devising standard ways of building applications and processes to connect and exchange information over the Internet. Standards such as CORBA (Common Object Request Broker Architecture) and Microsoft's COM (Component Object Model) and DCOM (Distributed Component Object Model) were some of the attempts in this direction. However connecting and sharing information between different applications and processes gained momentum with the introduction of eXtensible Markup Language (XML) in 1996. XML is a flexible way to create common information formats and share both the format and the data between different applications and web services. Various XML-based ways of running procedures on remote machines and of sharing objects have evolved. Some of the most important developments have been the Simple Object Access Protocol (SOAP), Web Services Description Language (WSDL) and Universal Description, Discovery, and Integration (UDDI). SOAP is a way for a program running in one kind of operating system to communicate with a program in the same or another kind of an operating system. For example, using SOAP, a program running in Windows 2000 may communicate with another operating system such as Linux. WSDL is an XML-based language that is used to describe the services a business offers and to provide a way for individuals and other businesses to access those services electronically. UDDI is an XML-based registry for businesses worldwide to list themselves on the Internet. UDDI aims at streamlining online transactions by enabling companies to find one another on the Web and make their systems interoperable for e-commerce.
The advantages offered by XML are used by web services to provide services to various web users or collaboration systems in a platform independent manner. Web services provide a standard mechanism of publishing the interfaces of the computing resources on the network.
These web services available on web servers can be accessed by using various techniques. The user can avail these services by directly linking to the server via a web browser. A web browser is a customized application that supports web access capabilities for various collaboration systems. The data obtained from the web services needs to be collated and presented to the user in a suitable format. This collation and presentation is usually performed on desktop applications like collaboration tools. The data acquired from web services is accessed using various desktop applications. Today's standalone desktop applications rarely provide any capability in connecting and conversing with web services. For the few desktop applications that provide these capabilities, the capability is very limited. A complex programming effort is required in order to extend the capabilities of the desktop applications to access web services.
There exist few products in the prior art that allow existing desktop applications to access web services available on the Internet. One such product is Microsoft Office XP Web Services Toolkit 2.0 manufactured by Microsoft Corporation, Redmond Wash., USA. This product is used to access and utilize XML Web services. Web Service References Tool 2.0 is used in a client application to create a Microsoft Visual Basic Application (VBA) proxy class module from a WSDL file. This proxy class contains methods and program code that allow the user to invoke XML Web services. The user can further use this proxy class to write VBA macro/subroutines to access the web services.
Another product is Fincad XL 5 manufactured by FinancialCAD Corporation, Surrey, B.C., Canada. FinancialCAD Corporation provides customized plug-in for a MS Excel user to access its web services. The Fincad XL 5 plug-in provides spreadsheets that contain special Fincad XL 5 functions, called "remote functions". These functions provide programmatic access for Microsoft Excel spreadsheet users to the application services available to Fincad.net subscribers.
These products aid in accessing web services to a certain extent. However, one or more of the abovementioned products suffer from certain drawbacks. Firstly, the prior applications provide libraries/classes to enable access to web services. But, these applications need programming at the user's end, hence making the system difficult to use by people with little programming knowledge. Secondly, the interfaces provided by these products are predefined. This restricts the ability of the user to manipulate and compile data in a desired format. Thirdly, these products provide access only to a limited set of web services. This largely restricts the type of web services that can be accessed by the user.
Accordingly, there is a need for systems and methodology that allow existing desktop applications to access various web services available over the Internet. Also, there is a need for the system to be user friendly and involve no programming or scripting effort on user's part. Also, there is a requirement for a system that has provisions to present the output data received from the web services in a predefined format desired by the user. Also, in order to access all types of web services, there is a need for a system to ensure compatibility with web services, given the limits of the hosted desktop application. Further, there is a need for a system that facilitates sophisticated communication mechanisms that are originally supported (or not supported) by the desktop application. In addition, there is a need for a system that is not restricted to a specific set of web services.

Enabling existing desktop applications to access web services through the use of a web service proxy


Articles and methods include temporary decorations. Embodiments include temporary decorations applied to promotional articles. Embodiments include a method comprising creating a promotional article including applying a dissolvable decoration to a base item to create the promotional article, the dissolvable decoration being applied in such a manner so as to be removable from the base item by dissolving the dissolvable decoration using a solvent without substantially altering the original physical condition of the base item.

Promotional items include a variety of items decorated in some manner, for example, items decorated with a logo or some other message. The function of these promotional items may include advertisement or promotion of an event, or of products or services offered by one or more vendors. The promotional items may include hats, such as baseball hats, Tee-shirts, collared type shirts including golf shirts, keychains, drinking containers such as coffee mugs and tumblers, and watches.
When applying the decorations to these items, often the criteria as to what types of materials and methods to use includes considerations related to the attractiveness and the durability of the final promotional item. For example, with respect to a decoration such as a company logo applied to a shirt, the logo would generally be applied in such a way and using materials and methods so that the logo would not fade or shrink after either wearing or washing of the shirt, and thus become unattractive or unreadable as the decorated shirt is worn and washed. In most instances, the decoration on the promotional item would be intended to have a lifespan of at least that of the lifespan of the item to which the decoration is applied.
Because the decoration applied to a promotional item is intended to last as long as the item itself, the addition of the decoration may detract from the value of the item to the user. For example, a shirt may be decorated with a logo representing a particular employer event, for example a sales conference. The decoration may include text such as "Sales Conference XXXX," wherein the "XXXX" represents a particular year. Once the sales event is over, the user may be deterred from wearing the shirt on later occasions due to the logo, wherein the user no longer wishes to promote or be associated with the decoration as it relates to the particular event or time period. In a further instance, the shirt may indicate a particular status to be associated with the user at a particular point in time, for example "Staff" or "Traffic Control," but wherein the status is not intended to extend beyond a particular event or time period, and therefore the party issuing the shirt may not want the user to retain the indication of the status beyond the designated time period.
Knowing the user will not continue to use the base item after a particular time period, or that the promotional item may be discarded after the particular time period relevant to the promotional item, the base item may be selected to include a low quality or low cost base item. The result may be that the promotional item has limited value to the user receiving the promotional item. In addition, the user, and others exposed to and coming in contact with the promotional item, may view the parties distributing or associated with the promotional item as "cheap" or as providing low quality products and services because of the low quality and low cost of the base item used in creating the promotional item.

Article and method including a temporary decoration


There is provided an electroacoustic transducer including: an oscillation device (10) that outputs a sound wave (30) from a first vibrating surface, and outputs a sound wave (32), having an opposite phase to that of the sound wave (30), from a second vibrating surface which is opposite to the first vibrating surface; a waveguide (40) that is provided on the first vibrating surface and that includes an open end (46); a waveguide (50) that is provided on the second vibrating surface, and includes an open end (56) which faces the same direction as the open end (46); and a sound wave filter (80) that is provided in the waveguide (50) and attenuates the sound wave (32).

There is a piezoelectric type electroacoustic transducer known as an electroacoustic transducer used for a mobile apparatus or the like. The piezoelectric type electroacoustic transducer generates oscillation amplitude using expansion and contraction motion which is created when an electric field is applied to a piezoelectric vibrator. As a technology which relates to the piezoelectric type electroacoustic transducer, for example, there is a technology which is disclosed in Patent Document 1. This technology is used to connect a pedestal, which is used to paste up a piezoelectric element, to a support member through a vibrating membrane which has lower rigidity than the pedestal.
The piezoelectric vibrator is used for, for example, a superdirective speaker using ultrasonic wave. As a technology which relates to the superdirective speaker, for example, there are technologies disclosed in Patent Documents 2 to 5. The technology disclosed in Patent Document 2 is used to form an audible sound field at an arbitrary point in a space by controlling the phase of ultrasonic wave. The technology disclosed in Patent Document 3 is used to output ultrasonic wave in two directions, that is, a surface side and a rear surface side. The technology disclosed in Patent Document 4 relates to a superdirective speaker which combines an ultrasonic wave speaker with a wide area speaker. The technology disclosed in Patent Document 5 relates to a post for a man conveyor which includes a superdirective speaker that outputs ultrasonic wave, and a filter which attenuates the ultrasonic wave area of audible sound.


A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.

Embodiments of the present invention relate to semiconductor memory devices and methods of forming the same, and more particularly, to nonvolatile semiconductor memory devices and methods of forming the same.
Generally, semiconductor memory devices can be classified as volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Flash memory devices, which are nonvolatile memory devices, are highly integrated devices developed by combining advantages of an erasable programmable read only memory (EPROM) capable of programming and erasing data and an electrically erasable programmable read only memory (EEPROM) capable of electrically programming and erasing data.
Flash memory devices may be classified as NOR-type flash memory devices or NAND-type flash memory devices. The NAND-type flash memory device is advantageous in highly integrated devices because a plurality of memory cells are controlled at one time as a string. A NAND-type flash memory device includes ground select lines arranged on one side of a group of word lines and string select lines arranged on the other side of the group of word lines.

Nonvolatile NAND-type memory devices including charge storage layers connected to insulating layers


The invention teaches a system and method for catalyzing on a substrate. The system includes a light source and a digital light patterning device which is controlled by a controller coupled to a computer. The digital patterning device includes an array of liquid crystals, each of which being electronically controlled by the computer through the controller. When a liquid crystal is on, the light from the light source passes through the liquid crystal. When it is off, the light is blocked. According to the visual image pattern presented in the computer's interface, the array, wherein some crystals are on and some are off, shows a light pattern which is consistent with the visual image pattern on the computer screen. Accordingly, the patterned light is shed onto a substrate where the light catalyzes a chemical reaction proximate a substrate.

In semiconductor design, and more specifically in substrate patterning of computer chips, a number of photolithographic masks were commonly used. The process required photolithographic protection of sections of a substrate. The masks protected the semiconductor layers during etching. Each layer required a unique mask design. The cost to implement this type of design was increased since printing and patterning each mask separately required a lengthened amount of time and cost.
In integrated circuit design, technology advanced and discoveries were made involving the new apparatus for catalyzing a reaction on a substrate comprising a light source. In particular, the invention of the ultraviolet (UV) light source which is directed toward micromirrors. One advantage of catalyzing chemical reactions using UV light is that it provides photons having the required high energy for the reaction. UV light is also advantageous due to its wavelength providing high resolution. The micromirrors are strategically positioned to redirect light from a UV light source towards the substrate. A computer is then connected to control the micromirror positioning. A reaction chamber is then placed in the path of light. The micromirror redirects the light and catalyzes a chemical reaction imminent on the substrate. The light catalyzed reaction can occur on the surface of the substrate.
U.S. Pat. No. 5,626,784, issued to Garner, discloses a method for substrate patterning using a digital optical chemistry micromirror imager. The method is used for catalyzing a reaction on a substrate. The process involves a UV light, along with a micromirror which is positioned to redirect light from the UV light source. The redirected light catalyzes a chemical reaction on a substrate. While a computer is connected, it is used for the purpose of controlling the positioning of mirrors within the micromirror. This allows the light to be redirected to specific portions of a substrate. The substrate may be placed in a reaction chamber. The redirected light from the micromirror can catalyze a chemical reaction imminent to the substrate as the substrate is in a reaction chamber. The problem of this system is that the redirected light from the micro-mirror may not be sharp enough and the light pattern on the substrate may not be identical to the designed pattern.
What is desired is a system that provides a pattern of light exposure identical with the designed pattern and allows the light from the light source directly shed on the substrate.
What is further desired is that the light pattern provided by the system can be amended or changed via a user interface coupled to a computer.

Substrate patterning using a digital liquid crystal array


A motor control device includes a drive circuit to drive an H-bridge circuit to control a current fed to a motor, a drive command signal generator to generate a drive command signal including a pulse signal having predetermined drive frequency and duty for sending a command to drive the motor, a current detection circuit operable to output a comparison output signal based on comparison between a current detection signal of a motor current and a target value signal, a latch circuit to hold a current detection result based on an ON signal of the drive command signal and the comparison output signal, a gate circuit to drive the drive circuit based on the ON signal of the drive command signal and a latch output signal from the latch circuit, and a control unit that changes the duty of the drive command signal based on the current detection result.

1. Field of the Invention
The invention relates to a motor control device.
2. Description of the Related Art
Some motor control devices are known that are adapted to conduct an electronic throttle control of a vehicle by controlling rotation of a motor (see, e.g., JP-A-2000-18069).
In the motor control devices, a digital control using an inexpensive microcomputer is conducted for the valve opening control of an electronic throttle valve, an analog control is conducted for the current control of the motor provided at a minor loop of the opening control which requires a quick response and a high accuracy, and a variable frequency PWM (pulse width modulation) control is used as the current PWM control.
However, if the variable frequency PWM control is used as the current PWM control, a problem may occur that a variation in drive frequency causes a harsh buzzing noise etc. during the motor drive control.

KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO


A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noise, and to reduce the noise transfer function in a power amplifier.

In some applications of RF power amplifiers, noise can create problems. For example, in wireless communication systems, noise specifications are challenging. Some of the more difficult specifications to meet are for transmit noise appearing in the receive band. The ETSI GSM specification, for example, requires no more than −79 dBm noise power (measured in a 100 kHz bandwidth) between 935 MHz and 960 MHz, and the ETSI DCS specification requires no more than −71 dBm from 1805 MHz to 1880 MHz. Regardless of which specification a power amplifier is designed for, meeting the noise requirements of the specification is difficult.
Various factors make it difficult to meet the stringent noise specifications mentioned above. Power amplifiers having multiple nonlinear stages make the noise specification difficult to meet, since each gain stage contributes to the noise, and each stage can amplify and upconvert the noise of a previous stage. In addition, power amplifier designs that have a lot of active devices in the signal path, especially if slow devices are used, contributes to noise. In some power amplifier designs, it is not always sufficient to minimize the noise generated in the input stages. In these designs, it is also necessary to minimize the noise transfer function from the input stage to the output.

Circuit and method of establishing DC bias levels in an RF power amplifier


Electrical switch designed for high voltage and/or current and surrounded by a housing (2) divided into a first part (2′) forming a first compartment for taking up at least one switching device (3) and an appurtenant actuator device (4), and a second part (2″) forming a second compartment for connecting of at least one phase. At least the first part (2′) of the housing (2) is pressure sealed encapsulated and filled with oil under pressure.

In connection with oil installations on the bottom of the sea, there has been, in the last years, a development where the oil companies demand disconnecting switches and circuit breakers for high voltage and/or current, which can be installed or operated under water.
It is known that a type of medium voltage disconnector or disconnecting switch has been developed and delivered for use under water. Yet this can break and close the electrical circuit in a power-off or voltageless mode.
There are not any pure high voltage circuit breakers for underwater use, from the surface and down to depths as for example 3000-4000 m, or even deeper.


A stitching machine has a stitching head stationarily mounted above the table. A carriage frame is mounted above the table and below the head for movement in a Y-direction relative to the head. A carriage belt is rotatably mounted to the carriage frame for movement in an X-direction relative to the head and the carriage frame. The carriage belt and carriage frame are controlled by a computer. A plurality of cartridges are employed, each cartridge having a hoop for holding a tautly mounted fabric workpiece. A latch is mounted to the belt for engaging one of the cartridges for movement with the belt to perform stitching. A magazine holds a plurality of the cartridges and advances them automatically one at a time onto the table for engagement with the latch after the previous cartridge has been released by the latch.

This invention deals with automatic embroidery machines for stitching logos, patches, monograms and the like. These embroidery machines are operated by a computer or controller which is programmed to stitch the design in the desired colors. These machines have one or more heads mounted over a table. The operator will secure the workpiece, which may be a shirt, jacket, cap, patch or the like, to a frame such as a hoop. The hoop attaches to a carriage mounted at table level. The carriage has a computer controlled drive mechanism that moves the hoop over the table while the stitching is being performed. After each workpiece is stitched, the operator removes the workpiece from the hoop and attaches another. Usually a number of identical workpieces are to be made, and the number may be quite large.
The operator has to maintain close watch on the machine because of having to remove the workpiece once finished and install another. During the stitching time, which can be several minutes with complex designs, the operator is free to perform other tasks. However, this short amount of time may not be enough to perform any useful tasks. It is difficult for one person to handle the workpiece feeding process for more than one machine because of the timing. This results in lost time for the worker, decreasing productivity.

Automatic feed system for embroidery machine


Systems and apparatus for integrating an air switch and a power cord into an electric motor, and methods for assembling an electric motor including an integral air switch and an integral power cord, are described. In one embodiment, an air switch and a power cord are incorporated into an electric motor. No additional removable cover is required for the switch and cord. To eliminate the motor centrifugal switch, an air switch is provided to control energization and de-energization of the motor windings. The air switch includes a snap action switch to cut-out the start winding used for ensuring that the rotor has sufficient starting torque.

Known jetted bath tubs include a pump having a pump motor. The pump motor typically is an electric AC motor having start-and run windings. Energization of the motor windings is controlled, at least in part, by an operator actuated control switch and a centrifugal switch. The operator actuated control switch for jetted bath tub applications typically is an air switch. The centrifugal switch controls cut-out of the motor start winding based on rotor speed during motor start-up.
One known air switch used in jetted tub applications is a "push to start, push to stop" type air switch. The known air switch includes a normally open snap action switch and a spring-biased actuator. The snap action switch is electrically connected in series with a power line and the common connection of the pump motor start and run windings. The snap action switch includes a movable, spring-biased button which extends from the snap action switch housing. The button is normally biased to be in a fully extended condition, and when the button is fully extended, the snap action switch is in an open state. When the button is fully depressed inward towards the housing, the snap action switch is in a closed state.
The spring-biased actuator includes an actuating arm movable from and between first and second positions. In the first position, the actuating arm does not contact the snap action switch button. In the second position, the actuating arm is in contact with, and fully depresses, the snap action switch button. The actuator is biased so that the actuator arm is normally in the first position.
The air switch also includes an operator controlled air transmitter coupled to an air bellows. The transmitter includes a user depressible flexible diaphragm. When an operator presses against, and deforms, the flexible diaphragm, a pulse of air is delivered to the air bellows and causes the bellows to expand. The bellows acts against the actuator, and when the bellows expands, the position of the actuator changes. The air transmitter typically is located near or integral with the tub so that an operator in or next to the tub can depress the switch to initiate or stop pump operation.
More specifically, to initiate pump operation with the above described air switch, the operator depresses the air transmitter flexible diaphragm and a pulse of air from the air transmitter causes the air bellows to expand. The bellows acts against the actuator and causes the actuator to move from the first position to the second position. The actuator is latched into the second position and, as described above, depresses the button of the snap action switch. When the snap action switch button is depressed, the snap action switch closes and energy is delivered to the motor start and run windings through the power line.
Once the pump motor rotor reaches a predetermined speed during motor start-up, the centrifugal switch opens and the start winding is de-energized. The motor then operates with only the run winding energized.
To stop pump operation, the user again depresses the air transmitter flexible diaphragm and a pulse of air from the air transmitter again causes the air bellows to expand. The bellows acts against the actuator and causes the actuator to "unlatch" and move from the second position to the first position. As described above, the button of the snap action switch is not depressed when the actuator is in the first position. When the snap action switch button is not depressed, the snap action switch opens and the pump motor windings are de-energized.
The above described jetted bath tub pump motor application is referred to as a "user attended" application since the user has direct control over motor energization. There are many other "user attended" applications in addition to the jetted bath tub pump motor application.
Although the above described motor has proven reliable and satisfactory, it would be desirable to reduce the cost of such motor, in terms of both component cost and assembly cost. Particularly, eliminating the centrifugal switch would result in significant cost savings since the centrifugal switch is expensive. The centrifugal switch, however, controls energization of the start winding and such control is necessary for efficient motor operation during both motor start-up and run operations.
With respect to manufacture and assembly of the above described jetted tub motor, since the motor type for a jetted bath tub pump application generally is also utilized in other applications, the motor is manufactured and mostly assembled in a common assembly line with many other motors used for other applications. At a late point in assembly, motors for the jetted tub pump application are separated from the other motors on the line, and the air switch and power cord are added to the separated motors for the jetted tub pump application.
Since the air switch and power cord are added late in the assembly process, the air switch and the power cord typically are not mounted within the motor housing. Rather, the air switch and a portion of the power cord are housed within a removable cover which is removably secured to the motor endshield. The removable cover for the air switch and power cord, in one known form, is a molded thermoplastic housing.
Cost savings could potentially be realized by eliminating the above described removable cover. Due to the late point assembly of the air switch and power cord to the motor, however, the removable cover is required to protect these components and connections.
Accordingly, it would be desirable and advantageous to provide a low cost motor for jetted tub and other user attended applications. It would also be desirable and advantageous to provide such a low cost motor which is as reliable and safe as existing motors for user attended applications.
An object of the present invention is to provide a low cost motor for user attended applications, including for jetted tub pumps, by at least eliminating the centrifugal switch for controlling energization of the motor start winding.
Another object of the present invention is to eliminate the motor centrifugal switch without adversely affecting motor operation.
Still another object of the invention is to eliminate the removable cover for the air switch and associated power cord portion.

Systems and apparatus for controlling energization of electric motor windings, and methods of assembling motors


Embodiments of the present invention relate to password authentication. According to an embodiment of the present invention, a password associated with a user identification is received from a user device. The password is authenticated based on a preset relationship between a seed password and a graphical password associated with the user identification. The seed password consists of a string of characters. The graphical password is a directed path traversing all keys of a keypad in an order. Each of the keys represents one of the characters and is associated with an order number according to the order of the keys being traversed. The preset relationship is that the password consists of respective order numbers associated with respective keys representing corresponding characters of the seed password.

The present invention generally relates to security and more specifically, relates to password authentication.
Password authentication is a process of verification in which a user is involved to input a user identification and a password that are then checked against stored credentials within a computing system. The most common password-based authentication method used by the user is via textual-based password. Nevertheless, the textual password tends to be susceptible to shoulder surfing attack as the password may be peeped by other people or by a hidden camera nearby. The other method for authentication is via graphical-based passwords. Similarly, it also suffers from shoulder surfing attack. For example, malware or insecure equipment may be installed on a device used by the user, and keystrokes or other user actions on the device may be traced by a hacker. Therefore, there is an increasing need for a secure authentication mechanism.

International Business Machines Corporation


A dynamic I/O configuration and protocol includes a configurable data bus for optimizing data throughput. The configurable data bus includes multiple bi-directional data buses between a memory device and a controller to maximize the data transfer efficiency of operation sequences and thereby optimize data throughput to and from the memory device. Each of the bi-directional data buses are configured for utilization in both read operations from and write operations to the memory device. Using control input signal lines, the controller specifies a current operation to be performed and the data bus to be used to perform the current operation. The specific instructions that are provided from the controller to the memory device depend on the particular operation sequence being performed.

Random access memory (RAM) is a component used within electronic systems to store data for use by other components within the system. Dynamic RAM (DRAM) is a type of RAM which uses a capacitor-type storage and requires periodic refreshing in order to maintain the data stored within the DRAM. Static RAM (SRAM) is another type of RAM which retains the information stored within the SRAM as long as power is applied. SRAM does not require periodic refreshing in order to maintain the stored data.
RAM is generally organized within the system into addressable blocks, each containing a predetermined number of memory cells. Each memory cell within a RAM represents a bit of information. The memory cells are organized into rows and columns. Each row of memory cells forms a word. Each memory cell within a row is coupled to the same wordline which is used to activate the memory cells within the row. The memory cells within each column of a block of memory are also each coupled to a pair of bitlines. These bitlines are also coupled to local input/output (LIO) lines. These local input/output lines are used to read data from an activated memory array or write data to an activated memory array. The pair of bitlines includes a bitline and an inverse bitline. A memory cell is therefore accessed by activating the appropriate wordline and pair of bitlines.
In a typical memory subsystem utilizing synchronous SRAM, data is transferred to and from each SRAM via one or more data buses. A data bus is a set of one or more data transmission lines or pins (depending on the context), and may be uni-directional or bi-directional. If uni-directional data buses are used to transfer data in a memory subsystem, then each SRAM must have at least two distinct data buses, one to receive input data during write operations and one to send output data during read operations. If bi-directional data buses are used to transfer data in a memory subsystem, then each SRAM needs only one distinct data bus which will both receive input data during write operations and send output data during read operations.
As used herein, the term data bus configuration refers to the number of distinct buses and the type of data buses used by the memory, to transfer data during read and write operations. The type characteristic of the data bus refers to whether the data bus is uni-directional or bi-directional. The two data bus configurations commonly implemented in synchronous SRAMs are common I/O and separate I/O. The common I/O data bus configuration includes one bi-directional data bus used to transfer data for both read and write operations. The separate I/O data bus configuration includes two uni-directional data buses, one used to transfer data for read operations and one used to transfer data for write operations.
As discussed herein, the read protocol of an SRAM refers to the timing of the first piece of output data driven from the SRAM during a read operation. The two read protocols commonly implemented in synchronous SRAMs are register-flow through (R-FT) and register-register (R—R). Using the register-flow through protocol, the first output data is driven from the same rising edge of the input clock that latches the address and control information. The register-flow through protocol is also sometimes referred to simply as flow through protocol. Using the register-register protocol, the first output data is driven from the rising edge of the input clock, one cycle after the address and control information are latched. The register-register protocol is also referred to as a pipelined protocol.
As discussed herein the write protocol of an SRAM refers to the timing of the first piece of input data driven to the SRAM during a write operation. The three write protocols commonly implemented in synchronous SRAMs are early write (EW), late write (LW) and double late write (DLW). Using the early write protocol, the first input data is latched on the same rising edge of the input clock that latches the address and control information. Using the late write protocol, the first input data is latched on the rising edge of the input clock, one cycle after the address and control information are latched. Using the double late write protocol, the first input data is latched on the rising edge of the input clock, two cycles after the address and control information are latched.
As discussed herein, the burst protocol of an SRAM refers to how much data is transferred to and from the SRAM per read and write operation, and how many clock cycles it takes to transfer that data. The four burst protocols commonly implemented in synchronous SRAMs are single data rate burst of one (SDR-B1), single data rate burst of two (SDR-B2), double data rate burst of two (DDR-B2) and double data rate burst of four (DDR-B4). Using the single data rate burst of one protocol, one piece of data is transferred per read and write operation, in one clock cycle. Using this protocol, data is latched on by the SRAM, during write operations, and driven from the SRAM, during read operations, only on the rising edge of the input clock. Using the single data rate burst of two protocol, two pieces of data are transferred per read and write operation, in two clock cycles. Using this protocol, data is latched on by the SRAM, during write operations, and driven from the SRAM, during read operations, only on the rising edge of the input clock. Using the double data rate burst of two protocol, two pieces of data are transferred per read and write operation, in one clock cycle. Using this protocol, data is latched on by the SRAM, during write operations, and driven from the SRAM, during read operations on both the rising and falling edges of the input clock. Using the double data rate burst of four protocol, four pieces of data are transferred per read and write operation, in two clock cycles. Using this protocol, data is latched on by the SRAM, during write operations, and driven from the SRAM, during read operations, on both the rising and falling edges of the input clock.
As discussed herein, the operation protocol of an SRAM refers to the combination of read, write and burst protocols implemented in the SRAM. It should be noted that the register-flow through protocol is not typically implemented in high speed synchronous SRAMs because the flow-through access time of an SRAM severely limits the cycle time of the SRAM.
Any combination of read, write and burst protocols can be used with a common I/O data bus configuration. The four operation protocols commonly implemented in high-speed common I/O synchronous SRAMs are: 1) register-register, early write, single data rate burst of one; 2) register-register, late write, single data rate burst of one; 3) register-register, double late write, single data rate burst of one; and 4) register-register, late write, double data rate burst of two.
Any combination of read, write and burst protocols can be used with a separate I/O data bus configuration. The six operation protocols commonly implemented in high speed separate I/O synchronous SRAMs are: 1) register-register, early write, single data rate burst of one; 2) register-register, late write, single data rate burst of one; 3) register-register, late write, double data rate burst of two; 4) register-register, early write, single data rate burst of two; 5) register-register, late write, single data rate burst of two; and 6) register-register, late write, double data rate burst of four.
As discussed herein, an operation sequence refers to any sequence of read, write and deselect operations in which no superfluous deselector operations are included. That is, deselect operations are only included in the sequence if they are required by the SRAM due to its data bus configuration and/or operation protocol.
As discussed herein the data transfer efficiency (DTE) of an SRAM refers to how efficiently data is transferred to and from the SRAM during a given operation sequence. The data transfer efficiency value corresponds directly to data bus utilization percentage. If data is transferred on all of the SRAM's data buses every clock cycle during a given operation sequence, then the data transfer efficiency value of the SRAM for that particular sequence is equal to 100%. If there are dead cycles on the data buses, meaning that data is not transferred on all of the SRAM's data buses every clock cycle during a given operation sequence, then the data transfer efficiency value of the SRAM for that particular sequence is less than 100%. The more dead cycles on the data buses during a given operation sequence, the lower the data transfer efficiency value of the SRAM for the particular sequence.
For a given operation sequence, the data transfer efficiency of a synchronous SRAM can be calculated using the following equation:DTE=(N2*(R+W))/(N1*(R+W+D))  (1)In the above equation, the value R represents the number of read operations in the sequence, the value W represents the number of write operations in the sequence, the value D represents the number of deselect operations in the sequence, the value N1 represents the number of data buses implemented in the SRAM and the value N2 represents the number of clock cycles needed to transfer all of the data associated with each read and write operation. For a synchronous SRAM implementing the common I/O protocol, the values N1 and N2 are both equal to one, allowing the SRAM to have a maximum data transfer efficiency of 100%. For a synchronous SRAM implementing the separate I/O protocol with the single data rate burst of two or double data rate burst of four protocols, the values N1 and N2 are both equal to two, allowing the SRAM to have a maximum data transfer efficiency of 100%. For a synchronous SRAM implementing the separate I/O protocol with the single data rate burst of one or double data rate burst of two protocols the value N1 is equal to two and the value N2 is equal to one, allowing the SRAM to have a maximum data transfer efficiency of 50%.
It is assumed herein that the operation frequency of the memory subsystem is very fast, such that, if a bi-directional data bus is utilized to transfer data to and from the SRAM, it cannot change from transferring input data to the SRAM to transferring output data from the SRAM, or vice versa, reliably in the same clock cycle. The operation frequency of the memory subsystem is equal to the frequency of the input clock to the SRAM. It is further assumed herein that at least one dead cycle must be inserted on a bi-directional data bus during transitions between read and write operations such that no data is transferred on the data bus during the clock cycle in which the data bus changes state from output to input or input to output. No such restriction is assumed for a uni-directional data bus, since a uni-directional data bus, by definition, never changes state from input to output or output to input.
A typical interface between an SRAM controller and a common I/O synchronous SRAM is illustrated in FIG. 1. The SRAM controller 10 is coupled to the SRAM 20 to provide a clock input on the clock input signal line 12, to provide address inputs on multiple address input signal lines 14 and to provide operation control inputs on multiple control input signal lines 16. The SRAM controller 10 is also coupled to the SRAM 20 by multiple data input/output signal lines 18 forming the bi-directional data bus. The control input signal lines 16 include two signal lines to specify a current operation, including read, write and deselect operations.
As discussed above, because common I/O synchronous SRAMs use bi-directional data buses to transfer data, they require at least one dead cycle to be inserted on their data buses between the transitions between read and write operations and the transitions between write and read operations. Collectively, the transitions between read, write and deselect operations are referred to herein as operation transitions. A dead cycle is typically inserted on a bi-directional data bus synchronously, using a deselect operation. The number of deselect operations needed to insert one dead cycle on the data bus between operation transitions varies depending on the operation protocol of the SRAM.
The data transfer efficiency of common I/O synchronous SRAMs varies depending on the operation sequence. The more operation transitions in a given operation sequence, the more deselect operations needed in the sequence. As a consequence of having more deselect operations in the sequence, the data transfer efficiency of the SRAM is lower for that particular sequence.
The deselect requirements and data transfer efficiency for all four common I/O operation protocols are described below in reference to the exemplary operation sequence: READ. WRITE, READ, READ, WRITE. WRITE, WRITE. Timing diagrams of this sequence for each common I/O operation protocol are illustrated in FIGS. 2–5 and will be discussed below. In these examples, the data transfer efficiency is calculated based on a repeating sequence of these seven operations, and is determined by the number of deselect operations that must be inserted in the sequence. Each of the timing diagrams included in the examples of FIGS. 2–5 include the same clock signal and the same address and data information. The only difference between the examples of FIGS. 2–5, is the number of deselect operations required between operation transitions, which changes the timing of the occurrence of the address and data information. When calculating the data transfer efficiency of the different protocols for this exemplary operation sequence, the only number that varies between the different operation protocols is the number of deselect operations within the sequence. As described above, for common I/O protocols, the number of data buses implemented (N1) and the number of clock cycles needed to transfer all of the data associated with each read and write operation (N2) are both equal to one. In this exemplary sequence the number of read operations (R) is equal to three and the number of write operations (W) is equal to four.
A timing diagram of the register-register, early write, single data rate burst of one, common I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 2. Using this operation protocol, three deselect operations are required between each read to write operation transition to insert a dead cycle on the data bus. Using this operation protocol, it is not necessary to include any deselect operations between write to read operation transitions. The number of deselect operations (D) necessary in the exemplary sequence is therefore equal to six, which is three for each read to write operation transition. Accordingly the data transfer efficiency for this protocol is equal to 53.8%, for this example, as calculated in equation 2 below:DTE=(1*7)/(1*13)=53.8%  (2)
A timing diagram of the register-register, late write, single data rate burst of one, common I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 3. Using this operation protocol, two deselect operations are required between each read to write operation transition to insert a dead cycle on the data bus. Using this operation protocol, it is not necessary to include any deselect operations between write to read operation transitions. The number of deselect operations (D) necessary in the exemplary sequence is therefore equal to four, which is two for each read to write operation transition. Accordingly, the data transfer efficiency for this protocol is equal to 63.4%, for this example, as calculated in equation 3 below:DTE=(1*7)/(1*11)=63.4%  (3)
A timing diagram of the register-register, double late write, single data rate burst of one, common I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 4. Using this operation protocol, one deselect operation is required between each read to write operation transition and between each write to read operation transition to insert a dead cycle on the data bus. The number of deselect operations (D) necessary in the exemplary sequence is therefore equal to four, which is one for each operation transition. Accordingly, the data transfer efficiency for this protocol is equal to 63.4%, for this example, as calculated in equation 4 below.DTE=(1*7)/(1*11)=63.4%  (4)
A timing diagram of the register-register, late write, double data rate burst of two, common I/O operation protocol, applied to the exemplary sequence, is illustrated in FIG. 5. Using this operation protocol, two deselect operations are required between each read to write operation transition to insert a dead cycle on the data bus. Using this operation protocol, it is not necessary to include any deselect operations between write to read operation transitions. The number of deselect operations (D) necessary in the exemplary sequence is therefore equal to four, which is two for each read to write operation transition. Accordingly, the data transfer efficiency for this protocol is equal to 63.4%, for this example, as calculated in equation 5 below:DTE=(1*7)/(1*11)=63.4%  (5)
As illustrated and discussed above, the data transfer efficiency of the common I/O operation protocols, illustrated in FIGS. 3–5, at 63.4%, is greater than the data transfer efficiency of the common I/O operation protocol, illustrated in FIG. 2, at 53.8%. The common I/O operation protocols, illustrated in FIGS. 3–5, can be considered the most efficient because they achieve the maximum data transfer efficiency possible for any common I/O synchronous SRAM for the exemplary operation sequence.
As discussed above, the data transfer efficiency of common I/O synchronous SRAMs varies depending on the particular operation sequence. For the most efficient common I/O synchronous SRAMs, the data transfer efficiency is a maximum of 100% during operation sequences which consist of either all read operations or all write operations, with no operation transitions between read operations and write operations. Also, for the most efficient common I/O synchronous SRAMs, the data transfer efficiency is a minimums of 50%, when the sequence alternates between read and write operations every cycle.
The data transfer efficiency of most efficient common I/O synchronous SRAMs for various operation sequences is illustrated in the graphs of FIG. 6. Within FIG. 6, the horizontal axis corresponds to the average number of consecutive read operations in a given operation sequence and the various plots correspond to the average number of consecutive write operations in a given operation sequence. Each point on the various plots within FIG. 6 corresponds to the data transfer efficiency of that particular combination of consecutive read operations and consecutive write operations.
A typical interface between an SRAM controller and a separate I/O synchronous SRAM is illustrated in FIG. 7. The SRAM controller 28 is coupled to the SRAM 40 to provide a clock input on the clock input signal line 30, to provide address inputs on multiple address input signal lines 32 and to provide operation control inputs on multiple control input signal lines 34. The SRAM controller 28 is also coupled to the SRAM 40 by multiple data input signal lines 36 and multiple data output signal lines 38 forming the uni-directional data bus. The control input signal lines 34 include two signal lines to specify a current operation, including read, write and deselect operations.
Separate I/O synchronous SRAMs can be divided into two categories. The first category, category 1, includes separate I/O synchronous SRAMs that transfer data in two clock cycles, including SRAMs that operate according to the single data rate burst of two and double data rate burst of four protocols. The second category, category 2, includes separate I/O synchronous SRAMs that transfer data in one clock cycle, including SRAMs that operate according to the single data rate burst of one and double data rate burst of two protocols.
Category 1 separate I/O synchronous SRAMs use uni-directional data buses to transfer data, thereby eliminating the need to insert any dead cycles on their data buses between operation transitions. Therefore, category 1 separate I/O synchronous SRAMs do not require any deselect operations to be inserted between operation transitions. However, category 1 separate I/O synchronous SRAMs do require deselect operations to be inserted in certain operation sequences. Specifically, between each read to read operation transition and each write to write operation transition, one deselect operation must be inserted because each read and write operation initiated to a category 1 separate I/O synchronous SRAM occupies its associated data bus for two clock cycles. Consequently, the data transfer efficiency of category 1 separate I/O synchronous SRAMs varies depending on the particular operation sequence. The more read to read and write to write operation transitions within the sequence, the more deselect operations that are necessary. The more deselect operations necessary in the sequence, the lower the data transfer efficiency will be.
The deselect requirements and data transfer efficiency for all three category 1 separate I/O operation protocols are described below in reference to the same exemplary operation sequence discussed above: READ, WRITE, READ, READ, WRITE, WRITE, WRITE. Timing diagrams of this exemplary operation sequence for the category 1 separate I/O operation protocols are illustrated in FIGS. 8–10 and will be discussed below. In these examples, the data transfer efficiency is calculated based on a repeating sequence of these seven operations, and is determined by the number of deselect operations that must be inserted in the sequence. Each of the timing diagrams included in the examples of FIGS. 8–10 include the same clock signal and the same address and data information. The only difference between the examples of FIGS. 8–10, is the number of deselect operations required between operation transitions, which changes the timing of the occurrence of the address and data information. When calculating the data transfer efficiency of the different protocols for this exemplary operation sequence, the only number that varies between the different operation protocols is the number of deselect operations within the sequence. As described above, for category 1 separate I/O protocols, the number of data buses implemented (N1) and the number of clock cycles needed to transfer all of the data associated with each read and write operation (N2) are both equal to two. In this exemplary sequence the number of read operations (R) is equal to three and the number of write operations (W) is equal to four.
A timing diagram of the register-register, early write single data rate burst of two, category 1 separate I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 8. Using this operation protocol, one deselect operation is required between each read to read and write to write operation transition to insert a dead cycle on the data bus. The number of deselect operations (D) necessary in the exemplary sequence is therefore equal to three, which is one for each read to read and write to write transition. Accordingly, the data transfer efficiency for this protocol is equal to 70%, for this example, as calculated in equation (6) below:DTE=(2*7)/(2*10)=70%  (6)
A timing diagram of the register-register, late write, single data rate burst of two, category 1 separate I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 9. Using this operation protocol, one deselect operation is required between each read to read and write to write operation transition to insert a dead cycle on the data bus. The number of deselect operations (D) necessary in the exemplary sequence is therefore equal to three, which is one for each read to read and write to write transition. Accordingly, the data transfer efficiency for this protocol is equal to 70%, for this example, as calculated in equation (7) below:DTE=(2*7)/(2*10)=70%  (7)
A timing diagram of the register-register, late write, double data rate burst of four, category 1 separate I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 10. Using this operation protocol, one deselect operation is required between each read to read and write to write operation transition to insert a dead cycle on the data bus. The number of deselect operations (D) necessary in the exemplary sequence is therefore equal to three, which is one for each read to read and write to write transition. Accordingly, the data transfer efficiency for this protocol is equal to 70%, for this example, as calculated in equation (8) below:DTE=(2*7)/(2*10)=70%  (8)
It should be noted that the data transfer efficiency of all three of the category 1 separate I/O operation protocols is the same, and at 70% is greater than the data transfer efficiency of the most efficient common I/O operation protocols for this particular exemplary operation sequence.
As discussed above the data transfer efficiency of category 1 separate I/O synchronous SRAMs varies depending on the operation sequence. The data transfer efficiency is a maximum of 100% when the number of read to read and write to write transitions in a given operation sequence is equal to zero. Accordingly, to maximize the data transfer efficiency for category 1 separate I/O operation protocols, the sequence must alternate between read and write operations every cycle. The data transfer efficiency for category 1 separate I/O operation protocols is a minimum of 50% when the sequence is either all read operations or all write operations, thereby maximizing the number of read to read or write to write transitions in the sequence.
The data transfer efficiency of the category 1 separate I/O synchronous SRAMs for various operation sequences is illustrated in the graphs of FIG. 11. Within FIG. 11, the horizontal axis corresponds to the average number of consecutive read operations in a given operation sequence and the various plots correspond to the average number of consecutive write operations in a given operation sequence. Each point on the various plots within FIG. 11 corresponds to the data transfer efficiency of that particular combination of consecutive read operations and consecutive write operations.
Category 2 separate I/O synchronous SRAMs use uni-directional data buses to transfer data. Because each read and write operation initiated to a category 2 separate I/O synchronous SRAM occupies its associated data bus for only one clock cycle, the category 2 separate I/O synchronous SRAMs do not require deselect operations to be inserted between any sequence of read and write operations. Accordingly the data transfer efficiency of all three category 2 separate I/O operation protocols is independent of the operation sequence.
The deselect requirements and data transfer efficiency for all three category 2 separate I/O operation protocols are described below in reference to the same exemplary operation sequence discussed above: READ, WRITE, READ, READ. WRITE, WRITE, WRITE. Timing diagrams of this sequence for category 2 separate I/O operation protocol are illustrated in FIGS. 12–14 and will be discussed below. In these examples, the data transfer efficiency is calculated based on a repeating sequence of these seven operations. Each of the timing diagrams included in the examples of FIGS. 12–14 include the same clock signal and the same address and data information. The only difference between the examples of FIGS. 12–14, is the particular operation protocol, which changes the timing of the occurrence of the address and data information. When calculating the data transfer efficiency of the different protocols for this exemplary operation sequence because no deselect operations need to be added, each of the numbers within the data transfer efficiency calculation are the same for each of the category 2 separate I/O operation protocols. As described above, for category 2 separate I/O protocols, the number of data buses implemented (N1) is equal to two and the number of clock cycles needed to transfer all of the data associated with each read and write operation (N2) is equal to one. In this exemplary sequence the number of read operations (R) is equal to three and the number of write operations (W) is equal to four. Because no deselect operations are necessary for category 2 separate I/O protocols, the number of deselect operations (D) necessary in the exemplary sequence is therefore equal to zero.
A timing diagram of the register-register, early write, single data rate burst of one, category 2 separate I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 12. Using this operation protocol, no deselect operations are required. Accordingly, the data transfer efficiency for this protocol is equal to 50%, for this example, as calculated in equation (9) below:DTE=(1*7)/(2*7)=50%  (9)
A timing diagram of the register-register, late write, single data rate burst of one, category 2 separate I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 13. Using this operation protocol, no deselect operations are required. Accordingly, the data transfer efficiency for this protocol is equal to 50%. for this example, as calculated in equation (10) below:DTE=(1*7)/(2*7)=50%  (10)
A timing diagram of the register-register, late write, double data rate burst of two, category 2 separate I/O operation protocol, applied to the exemplary operation sequence, is illustrated in FIG. 14. Using this operation protocol, no deselect operations are required. Accordingly, the data transfer efficiency for this protocol is equal to 50%, for this example, as calculated in equation (11) below:DTE=(1*7)/(2*7)=50%  (11)
It should be noted that the data transfer efficiency for all three of the category 2 separate I/O operation protocols is equal to 50% and is less than the data transfer efficiency of all three of the most efficient common I/O operation protocols and all three category 1 separate I/O operation protocols for this particular exemplary operation sequence. As discussed above, the data transfer efficiency of category 2 separate I/O synchronous SRAMs is independent of the operation sequence. The data transfer efficiency of category 2 separate I/O synchronous SRAMs is always 50%.
Of the three categories of synchronous SRAM operation protocols that have been discussed, the data transfer efficiency of the category 2, separate I/O operation protocols is the lowest of the three. The data transfer efficiency of the category 2, separate I/O operation protocols is equal to 50%, regardless of the operation sequence. The data transfer efficiency of the other two categories of operation protocols, common I/O and category 1 separate I/O, are in the range of 50% to 100%, and depend on the particular operation sequence. The data transfer efficiency of the common I/O operation protocol is maximized for operation sequences with many read to read and write to write operation transitions and few read to write and write to read operation transitions. The data transfer efficiency of the category 1 separate I/O operation protocol is maximized for operation sequences with many read to write and write to read operation transitions and few read to read and write to write operation transitions. Currently, there is not a single system or protocol which maximizes the data transfer efficiency for operation sequences with many read to read and write to write transitions and many read to write and write to read operation transitions.

Dynamic input/output: configurable data bus for optimizing data throughput


An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of an top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.sup.+ substrate (1). When a higher potential than that of the emitter electrode (9a) is applied to the gate electrode (8a) with forward bias being applied between the electrodes (9a) and (10) so that the collector electrode (10) may be higher in potential than the emitter electrode (9a), the channel region (6a) turns to the N-type, and electrons move from the N.sup.+ layers (5a) through 26e channels (6a) to the N.sup.+ floating layers (5b).

1. Field of the Invention
The present invention relates to an insulated-gate bipolar semiconductor device and a method of manufacturing the same.
2. Description of the Prior Art
FIG. 4 is a sectional view showing a conventional insulated-gate bipolar transistor (IGBT). On an upper major surface of a P.sup.+ silicon substrate 1, an N.sup.+ buffer layer 2 and an N.sup.- drain layer 3 are formed in this order by, for example, epitaxial growth. P base regions 4 are formed on a surface of the N.sup.- layer 3 by selective diffusion or the like; and further, N.sup.+ emitter regions 5 are formed in each of the P base regions 4 by selective diffusion or the like. On a region 11 between the P regions 4 adjacent to each other in the N.sup.- drain layer 3, a gate electrode 8 is formed with interposition of a gate oxidation film 7, extending near the N.sup.+ emitter regions 5. An emitter electrode 9 is provided on both the N.sup.+ emitter regions 5 and the P.sup.+ base region 4 lying between the N.sup.+ emitter regions 5, in ohmic contact. On a lower major surface of the P.sup.+ substrate 1, a collector electrode 10 is provided in ohmic contact.
Now, the operation of the IGBT will be simply described. When voltage which is higher to some extent than the emitter potential is applied to a gate electrode 8 with forward bias voltage applied between the emitter electrode 9 and the collector electrode 10, a channel region 6 lying between each of the N.sup.+ emitter regions 5 and N.sup.- drain layer 3 and located just under the gate electrode 8 is inverted to the N-type. Then, electrons move from the N.sup.+ emitter region 5 through the channel region 6 into the N.sup.- drain layer 3. In accord with it, holes move from the P.sup.+ substrate 1 through the N.sup.+ buffer layer 2 into the N.sup.- drain layer 3, and eventually, the emitter electrode 9 and the collector electrode 10 become conductive with each other.
It is desirable that voltage between the emitter electrode 9 and the collector electrode which are conductive with each other (referred to as "ON-voltage" hereinafter) is low, but to reduce the ON voltage, it is necessary to make the design by which current passing through the region 11 to the N.sup.- drain layer 3 in the vertical direction can flow more easily there. Especially, this is imperative necessity because a resistively of the N.sup.- drain layer 3 rises when the carrier lifetime is shortened in the N.sup.- drain layer 3 by putting lifetime killer in to implement a high-speed operation of the IGBT.
To make the current flow more easily through the region 11 in the vertical direction, for example, the width l of the region 11 is made wider or the impurity in the region 11 is increased to make an N.sup.+ region 12, so as to reduce a value R of the resistance there (FIG. 5). However, making the width l too large or making the resistance value R too small, the withstand voltage retained while the device turns off is reduced. Specifically, depletion layers expand from the P base regions 4 into the N.sup.- layer 3 with an increase in forward bias; however, when the width l is small, the depletion layers from opposite sides join together at a relatively low voltage to moderate the electric field around, as shown by the broken line in FIG. 6A. Meanwhile, when the width l is large, the depletion layers do not easily join as shown in FIG. 6B, much more concentration of the electric field around the region 11 is caused, and the device is broken down. When the resistance value R becomes too small, the same phenomenon leads to a decline of the withstand voltage.
Thus, in the conventional IGBT, there arises the problem that it is difficult to reduce ON-voltage without reducing the withstand voltage.