A soil sample core system includes an outer cylinder having first and sec ends; a sample tube for sliding within the outer cylinder; a tip sleeve mounted to the first end of the outer cylinder; a push pipe which may be mounted to the second end of the outer cylinder to prevent the sample tube from sliding out of the second end; a tapered tip which may be selectively extended out of the tip sleeve and which may be selectively retracted into the push pipe; an end cap having a threaded bore which may be mounted to the second end of the outer cylinder in place of the push pipe; a threaded shaft threaded in the threaded bore; a piston rotatively mounted to one end of the threaded shaft for sliding within the outer cylinder; and a torque transmitting element mounted to the other end of the threaded shaft for transferring torque to thread the shaft through the threaded aperture.

The present invention generally relates to the field of ground soil coring equipment, and more particularly, to a soil sample core system in which a screw driven rotatable piston is used to drive a soil sample tube out of the system without disturbing the soil sample.
Many commercially available soil sampling tools usually consist of an outer cylinder and one or more serially stacked inner cylinders that fit within the outer cylinder. The tools are pushed into the ground by various means. The soil sample is collected inside the inner cylinder(s) which are usually thin wall tubes. The outer cylinder is relatively thick walled and acts as the strength member to which force is applied to push the tool through the soil. The inner tubes may also be "split" tubes, so that the tube can be "peeled" away from the soil sample.
A problem with soil sampling tools is that soil is also collected in the annulus formed between the outer and inner cylinders. If the soil is dense, abrasive, and compacted within the annulus, the inner tubes may become lodged or jammed so that they cannot easily be removed from the outer cylinder without disturbing the soil samples. When this happens, the jammed tubes need to be "hammered" out of the outer cylinder. However, such hammering generally disturbs, and in some cases destroys, the soil sample.
Therefore, a need exists for a tool for collecting soil samples which allows the soil samples to be removed without being disturbed.

The United States of America as represented by the Secretary of the Navy


A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage. The first and second resistors form a resistive divider that allows the predetermined reference voltage to track changes in the on-chip voltage source.

A programmable logic device (PLD) is an integrated circuit that is purchased by a user in an unprogrammed state, and then programmed by the user to implement the user's circuit design. PLDs typically include blocks of logic elements and interconnect resources that are programmably controlled by associated memory cells. PLDs are typically programmed using a device programmer and place-and-route software installed in a personal computer or workstation. The user enters the circuit design and information regarding a target PLD into the computer/workstation. The place-and-route software then "maps" the user's circuit design by assigning portions of the circuit design to selected logic element blocks of the target PLD, and assigning signal paths (nets) linking the portions to selected interconnect resources. A mapping solution is then generated that contains information regarding the on/off states of all memory cells of the target PLD. Some PLD types are programmed with the mapping solution by being placed on the device programmer and transmitting the mapping solution into the PLD from a computer/workstation through the device programmer. In other PLD types, the mapping solution is downloaded to a read-only-memory (ROM) that is accessed by configuration logic of the PLD during start-up. In addition, some PLDs are in-system programmable (ISP) in that they are programmed via serial interface after, for example, being soldered to a printed circuit board (PCB). In each PLD type, the mapping solution is utilized to configure the memory cells of the target PLD such that the target PLD implements the user's circuit design.
Several types of PLDs are currently available, including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). FPGAs typically include logic element blocks that are arranged in a matrix and separated by rows and columns of interconnect lines. In contrast, CPLDs typically include logic element blocks that receive input signals from a central interconnect matrix. The present application is primarily directed to CPLDs, but may also utilized in FPGAs and other types of PLDs.
FIG. 1 is a simplified block diagram showing circuitry utilized in some known CPLDs. In particular, FIG. 1 shows an interconnect matrix 100, a blank check circuit 150 and a multi-level voltage source 200.
Interconnect matrix 100 includes columns of first conductors (referred to as wordlines) 110 that are driven by wordline drivers 115, rows of second conductors (referred to as bitlines) 120 that are connected to sense amplifiers 125, and an array of memory cells 130 located between adjacent wordlines 110 and bitlines 120. Wordlines 110 transmit device input signals and feedback signals into interconnect matrix 100. The voltage level of high voltage signals transmitted on wordlines 110 is determined by multi-level voltage source 200. Bitlines 120 are normally maintained at less than system voltage (<Vcc) using relatively weak pull-up devices, and are pulled down when an associated memory cell 130 is turned on. An associated sense amplifier 125 amplifies the voltage level on each bitline 120 (which may vary by tens of millivolts). Each sense amplifier 125 generates a full logic level output signal in accordance with the sensed voltage level. The sense amplifier output signals are transmitted to associated PLD logic, and are also transmitted to blank check circuit 150. Memory cells 130 are typically implemented by re-writable read-only memories (ROMs), such as EPROMs, EEPROMs, flash EPROMs, or flash EEPROMs. Each memory cell 130 includes a control gate connected to a wordline 110, a source connected to a bitline 120, and a drain tied to ground. Each memory cell 130 also includes a floating gate that is programmed/erased by charging/discharging the floating gate using, for example, hot electron injection or electron tunneling. When erased, a memory cell 130 is turned on/off by an associated high/low wordline voltage. Conversely, when programmed, a memory cell 130 is not turned on (i.e., remains turned off) in response to high and low wordline voltage. For example, when memory cell 130(11) is erased, a high voltage on wordline 110(1) turns on memory cell 130(11), thereby connecting the source of memory cell 130(11) to ground and pulling down the voltage on associated bitline 120(1). In contrast, when programmed, memory cell 130(11) remains turned off even if a high wordline voltage signal is generated on wordline 110(1), and associated bitline 120(1) remains high.
Wordlines 110 must be driven at different voltage levels during different operation modes of interconnect matrix 100. By way of example, a voltage level of 10 to 12 volts may be required on wordline 110(1) to program memory cell 130(11), a voltage level of approximately 0 volts may be required to erase memory cell 130(11), and a voltage level of 5 volts may be required during normal operation. In addition, a voltage level of 7 to 8 volts may be used to verify that memory cell 130(11) is programmed, and a voltage level of 3 volts may be used to verify that memory cell 130(11) is erased. These various voltage levels are provided by multi-level voltage source 200.
Memory cell erase verification is performed after all of memory cells 130 of a PLD are erased, which is necessary before the PLD is programmed with a user's circuit design. The PLD may be erased by exposing it to ultraviolet light (e.g. standard UV EPROMs), or may be erased electrically (e.g. flash EPROMs and EEPROMs). With either method, a memory cell erase verification process (referred to herein as a blank check operation) is required to ensure that the erase cycle was successful in completely erasing all of the memory cells 130. A blank check operation is performed, for example, by sequentially applying a reference voltage of 3 volts to each wordline 110, and monitoring the resulting voltage levels on bitlines 120 using blank check circuit 150 in the manner described below. The reference voltage is selected to turn on fully-erased memory cells 130, but insufficient to turn on memory cells 130 that are not fully erased. For example, if the 3 volt reference voltage is applied to wordline 110(1) and memory cells 130(11), 130(21) . . . 130(n1) are fully erased, then all of the bitlines 120(1) through 120(n) will be pulled low. Conversely, if, for example, memory cell 130(11) is not fully erased, then bitline 120(1) will remain high when the reference voltage is applied to wordline 110(1). During the blank check operation, the high and low voltages on bitlines 120(1) through 120(n) are transmitted through sense amplifiers 125(1) through 125(n) to the blank check circuit 150.
As shown in FIG. 1, blank check circuit 150 includes a PMOS device P1 and parallel-connected NMOS devices N(1) through N(n). PMOS device P1 has a drain connected to a common node 155, a source connected to Vcc, a gate connected to ground, and is sized to provide a weak pull-up on common node 155. Each NMOS device N(1) through N(n) has a drain connected to common node 155 and a source connected to ground. In addition, each NMOS device N(1) through N(n) has a control gate connected to the output of an associated sense amplifier 125(1) through 125(n).
During a blank check operation, NMOS devices N(1) through N(n) remain turned off (common node 155 remains at a high voltage level) unless one or more of memory cells 130 are not fully erased, in which case at least one of NMOS devices N(1) through N(n) is turned on (common node 155 is pulled down). For example, if the reference voltage is applied to wordline 110(1) and memory cell 130(11) is not fully erased, then bitline 120(1) remains at a high voltage level. The high voltage level on bitline 120(1) is transmitted through sense amplifier 125(1) to the control gate of NMOS device N(1), thereby turning on NMOS device N(1) and pulling down common node 155. The low voltage level on common node 155 is detected by monitoring circuit 170, which notifies the user that the PLD is not fully erased. Therefore, blank check circuit 150 allows a simultaneous blank check of all memory cells 130 associated with a wordline 110 of interconnect matrix 100 by bringing the wordline 110 under test to the predetermined reference voltage while keeping all other wordlines at a low voltage.
FIG. 2 is a simplified block diagram showing an example of multi-level voltage source 200 that is connected to wordlines 110 through wordline drivers 115. Multi-level voltage source 200 includes a power multiplexer (power MUX) 210 that receives reference voltages from a 12 volt source 220, an 8 volt source 230, a 5 volt source 240, and a 3 volt reference voltage source 300, and also receives two or more control signals 260. In response to control signals 260, power MUX 210 transmits either a 12 volt signal, an 8 volt signal, a 5 volt signal, a 3 volt signal, or a 0 volt signal to wordline drivers 115 via output line 270. Reference voltages (such as the 3 volt reference voltage) are transmitted through a pass transistor in power MUX 210, and are therefore subjected to a threshold voltage drop of approximately 0.7 volts, and up to 2 volts (depending on body effect). Therefore, the voltage sources providing these reference voltages must transmit an input voltage that is approximately one threshold voltage drop above the required reference voltage.
In order to account for the voltage drop introduced by power MUX 210, reference voltage source 300 generates an output voltage of 3.5 to 4 volts. If the output voltage generated by reference voltage source 300 falls below the range of 3.5 to 4 volts, then the reference voltage applied to wordlines 110 may not be sufficient to turn on memory cells 130 (FIG. 1), even if they are properly erased. As a result, blank check circuit 150 may incorrectly indicate that a CPLD is not fully erased, thereby causing the user to repeat the erase procedure or incorrectly assume the PLD has a defective memory cell. For example, a typical memory cell 130 may have an erased threshold voltage Vth(er) of 2.5 volts. If reference voltage source 300 generates an output voltage of, for example, 3 volts, then the reference voltage applied to the memory cell will be approximately 2.3 volts. Because the reference voltage is below Vth(er), the memory cell may not turn on during a blank check operation, and the blank check operation may incorrectly indicate that one or more memory cells 130 are not erased. Incorrect blank check results may frustrate users, which can result in a loss of sales by the CPLD manufacturer. Therefore, it is important for reference voltage source 300 to adjust to variations in Vcc to produce a reliable 3.5 to 4 volt reference voltage.
FIG. 3 is a circuit diagram illustrating prior art reference voltage source 300 that includes programmable circuitry used to adjust for variations in process parameters such that a reliable 3.5 to 4 volt output voltage is generated for use during the blank check operation. Such variations in process parameters commonly arise during the production of CPLDS. For example, if a CPLD is designed to operate on a nominal Vcc of 5 volts (within a 4.5 to 5.5 volt range), then differences in fabrication process parameters may produce a reference voltage from source 300 in the range of 3.0 to 4.5 volts. To adjust for these variations, reference voltage source 300 is provided with programmable circuitry that is selectively utilized to "trim" the output voltage to the required 3.5 to 4 volt level.
Referring to FIG. 3, reference voltage source 300 includes a PMOS device P(31) that connects node 310 to Vcc, and programmable circuitry including several resistance paths that are controlled by control signals 320 to selectively connect node 310 to ground. An associated NMOS device N(31) through N(34) selectively controls each resistance path, and has a different resistance value that is determined by the particular NMOS resistance elements NR(31) through NR(37) located on that path. The resistance paths are selectively connected to node 310 NMOS devices N(31) through N(34), which are controlled by memory cells (not shown) that generate control signals transmitted on lines 320(1) through 320(4). For example, a first resistance path including resistance element NR(31) is connected between node 310 and ground by control signal 320(1) that is applied to the gate of NMOS device N(31). NMOS device N(32) is selectively turned on by control signal 320(2) to connect node 310 to ground along a second path including resistance element NR(32). NMOS device N(33) is selectively turned on by control signal 320(3) to connect node 310 to ground along a third path including serially-connected resistance elements NR(33) and NR(34). Finally, NMOS device N(34) is selectively turned on by control signal 320(4) to connect node 310 to ground along a fourth path including serially-connected resistance elements NR(35), NR(36) and NR(37). Each resistance element NR(31) through NR(37) is an NMOS device having a commonly-connected source and gate, and has a resistance value determined by the size (width and length) of the NMOS device. By controlling the size of each resistance element, the resistance paths provide a variety of resistances that allow adjustment of the voltage level at node 310. For example, if resistance element NR(31) has a width-to-length ratio of 8/4 and resistance element NR(32) has a width-to-length ratio of 2.4/4 (assuming Vcc is 4.5 volts), then the voltage level at node 310 is 2.52 volts if NMOS device N(31) is selected, or 2.70 volts if NMOS device N(32) is selected. Similarly, the resistance elements of the other paths are formed to provide a variety of resistance values for a given Vcc level.
Reference voltage source 300 is typically programmed during tests performed by the CPLD manufacturer before the CPLDs are sold to a user. During these tests, an acceptable range for source 300 is determined, a resistance path is selected, and memory cells (not shown) are programmed to produce control signals necessary to connect the selected resistance path between node 310 and ground, thereby adjusting the output voltage to 3.5 to 4 volts (if possible). Because this adjustment is performed before the CPLD is purchased, this adjustment is typically "transparent" to the user.
A problem with reference voltage source 300 arises when the Vcc power supply of a CPLD is at its minimum value (e.g., at 4.5 volts). When Vcc is at this minimum value, the voltage drop across PMOS device P(31) generates an output voltage that drops below the required 3.5 volts, thereby generating a reference voltage on wordlines 110 that is significantly less that the required 3 volt reference voltage. Specifically, the reference voltage is equal to Vcc-(Vtn+Vtp), where Vtn is the voltage drop introduced by power MUX 210, and Vtp is the voltage drop across PMOS device P(31). Therefore, if Vcc is at 4.5 volts or less, then the resulting output voltage drops below 3 volts, thereby generating incorrect blank check operation results, as described above. This results is an unreliable device that the CPLD manufacturer cannot sell, thereby reducing profit.
Another problem with reference voltage source 300 arises when the CPLD is subjected Vcc fluctuations during use. Typically, the reference voltage is set for a certain Vcc at a particular temperature and process corner. When Vcc fluctuates during use, the trip voltage of the sense amplifiers 125 changes with Vcc. As Vcc drifts upward, the reference voltage must also track Vcc to prevent blank check circuit 150 from incorrectly indicating programmed memory cells.

Enhanced blank check erase verify reference voltage source


A method of producing a surfacial marking (11) on a surface (1b) of a body (1) of transmissive material, whereby use is made of a laser beam (5) having a wavelength .lambda. to which the material is substantially transparent, which method comprises the following steps:. (a) providing a layer (3) of assistant material against the surface (1b), which assistant material is absorptive at the wavelength .lambda.; PA0 (b) directing the laser beam (5) through the body (1) onto the layer (3), so as to locally heat and ablate the layer (3).

The invention relates to a method of producing a surfacial marking on a surface of a body of transmissive material, whereby use is made of a laser beam having a wavelength .lambda. to which the material is substantially transparent.
Such a method is known from European Patent Application EP 531 584. In the method therein described, a layer of an assistant material is directly deposited on the surface. This material comprises at least two different species of transition metal ion, which differ in valency and/or atomic number (e.g. Ti.sup.3+ and Ti.sup.4+, or Ti.sup.3+ and Fe.sup.3+). When subsequently irradiated with a laser beam having a wavelength in the range 300-1600 nm, a heated plasma is generated in the assistant material, and this plasma interacts with and locally etches the surface of the transmissive material. After etching has been completed, the layer of assistant material is removed from the surface.

Method of producing a patterned surfacial marking on a transparent body


A detachable vehicle seat for children having a base and a backrest pivotally connected together by a connection mechanism. The connection mechanism includes a transverse latching bar and a restriction tab in the back of the seat. A cross-section of the latching bar has a short edge and a long edge, and the restriction tab has vertical receiving slots and apertures of differing heights. During assembly, the short edge of the latching bar is inserted into said apertures and restricted by its long edge from moving backwards, thereby preventing the bar from coming off of the receiving slots, thereby simplifying assembly or disassembly of the seat.

1. Field of the Invention
This invention relates to a detachable vehicle seat for children and, in particular, to a detachable assembly which makes use of a transverse latching bar and a restriction tab interlocked between the base and backrest.
2. Description of the Background Art
An increased number of people carry their baby or children in vehicles, since the economy is boosting. However, the seat belts equipped in a car are intended for use by adults and might be fatal if used for a baby or child. Therefore, in consideration of the safety of children, people must use a vehicle seat for children together with the seat belt, the use of which is regulated by many countries in the world.
The simplified vehicle seat for children sold on the market can usually be separated into a base and a backrest, to reduce the size of the seat during transportation, and can then be assembled, if necessary for use. FIGS. 1 and 1A show a prior art detachable vehicle seat for children which includes a backrest 1 and a base 2, wherein the backrest 1 has a lateral view of an N-shaped sealed positioning bar 11 extending from the bottom of the backrest. Positioning blocks 21 extend from the back side of the base 2 and are arranged symmetrically with an upward and downward crossed position. The method and procedure for detachment of this seat is 1) to turn over the backrest 1 downwards and lay it down (as illustrated in FIGS. 1B and 1C), 2) to move the backrest parallel to the base to disengage the positioning bar 11 from the outermost positioning block 21 (as illustrated in FIG. 1D), and 3) to tilt and turn over the backrest 1 to disengage the positioning bar 11 from the other positioning blocks 21 (as illustrated in FIG. 1E). This procedure can be reversed to assemble the vehicle seat.
It is clear from the above description and illustration that the assembly procedure of the prior art is complicated and may not be practical, since the user has to turn the backrest or the base over repeatedly is while assembling or dismantling the safety seat, which is inconvenient.


A method and apparatus for combining multiple image data files of differing sizes, resolutions, and formats in real time into a single data stream for conversion into halftone pixel data for printing by either single or multiple beam recording devices. The data of varying formats is received via a host interface which couples the data to a standard VME bus. The internal CPU reformats the data and stores it on disk memory. The data is routed by the CPU to one of a plurality of scan-line video processors which converts the data into halftone pixel data. The halftone data is routed to a single or multiple beam recording device for printing. A special low resolution image is prepared by the CPU for preview at a video work station.

The present invention relates generally to high resolution graphic production, and more specifically, relates to real time data processing of multiple image data to produce a composite.
In reproduction technology, it is often desirable to combine multiple texts, photographic images, and geometric shapes into a single proof based upon layout information generated by some form of digital input. This input may be generated by a digital scanner or electronic work station which is used to create a montage. The layout information may have a variety of formats and protocols.
The majority of color separation films produced in the graphic arts industry currently are made using drum output recorders. Three data types (i.e., contone, contour, and run-length) are commonly used for storing and manipulating images that are converted to halftone pixels for output to these recorders.
The conversion process is typically preceded by a lengthy pre-processing step called a final page run, in which the three data types are converted into a common data format and the multiple images of the same data type are merged into one single file. Even though the resulting data stream defines a high-quality, high-resolution, four color separated image, the final page run unfortunately takes about an hour to complete. The commercially available Hell Chromacom 1000 system coupled to a DC 350 output recorder operates in this fashion.
Higher speed can be achieved in lower quality systems. These typically employ flatbed rather than drum recorders. Such systems tend to have fewer levels of grey in the halftone pixels, lesser precision in the output process, and greater susceptibility to moire patterns. Typical, commercially available systems of this type include the Hell LS-210 system and the Scitex Raystar system. Even though these systems sacrifice quality of output for enhanced speed, real time operation is seldom achieved because the output recorder must frequently pause in mid-image to permit the hardware to convert multiple image data types into halftone pixels.
U.S. Pat. No. 4,729,037, Doelves, is concerned with the production of printed material using image input from multiple sources. The system is designed for production of catalogs using high resolution data to be received from a scanner and relatively lower resolution data from a digital memory. To function in near real time, the system requires the data to be presented from the data sources synchronously.
A more flexible system is disclosed in U.S. Pat. No. 4,849,822, Sing. In this system, data may be added to an image from a digital work station. This permits text to be placed over high resolution images. To permit mixing of these images, however, the lower resolution inputs must be expanded and synchronously intermixed with the higher resolution input. Thus, the various components of the final proof cannot be stored in memory without an inordinate amount of hardware. The result is that the work station operator is limited in his ability to manipulate the data.
The Sing system is further limited in the types of data which can be processed automatically without operator supervision. High resolution compressed data, for example, must be expanded under direct operator control before it can be intermixed with other data types. High resolution contour data involving a color change within a pixel must be similarly processed by the operator before being combined.
U.S. Pat. No. 4,419,690, Hammes, shows a system which has a limited capacity to process input data of varying resolutions. A more flexible system is shown in U.S. Pat. No. 4,647,962, Rosen, et al. Though the system of Rosen, et al. provides for a greater range in the resolution of the input data, combining multiple images in the same proof is not provided without direct operator supervision.
Thus, these systems have limited capability to combine multiple images of varying resolution in real time to produce a composite.

Method and apparatus for assembling a composite image from a plurality of data types

Minnesota Mining and Manufacturing Company


A wire-wound electronic component, a core for a wire-wound electronic component and a method for manufacturing a core for a wire-wound electronic component are provided. A winding core portion of a core of a wire-wound electronic component includes flanges at respective ends of the winding core portion, and project in directions perpendicular to an axial direction of the winding core portion. Concaves are positioned at corners formed of adjoining surfaces of the flanges that adjoin to the winding core portion and end surfaces of the flanges that are located at ends in a first perpendicular direction, which is one of the projecting directions of the flange. Connecting surfaces, which connect contact portions where the flanges contact with the winding core portion to the end surfaces, are at least part of inner peripheries of the concaves. All normal vectors of the connecting surfaces have components in the first perpendicular direction.

As a conventional core for a wire-wound electronic component, for example, a core of a wire-wound coil component disclosed by Japanese Patent Laid-Open Publication No. 2011-171544 (Patent Document 1) is known. Hereinafter, the wire-wound coil component 500 disclosed by Patent Document 1 is described. FIG. 22 is a sectional view of the wire-wound coil component 500 disclosed by Patent Document 1. FIG. 23 is a sectional view of the wire-wound coil component 500 disclosed by Patent Document 1 in the middle of a production process. FIG. 24 is a sectional view of a wire-wound coil component 500′ disclosed by Patent Document 1 in consideration of a manufacturing method of the wire-wound coil component 500. FIG. 25 is a sectional view of the wire-wound coil component 500′ in the middle of a production process. In FIGS. 22 and 23, a direction along the central axis of a winding core portion 501a of the wire-wound coil component 500′ is defined as an x-axis. In FIGS. 23 and 25, a direction in which molding dies to press magnetic cores 501 and 501′ are pulled away is defined as a y-axis.
As shown by FIG. 22, the wire-wound coil component 500 comprises a magnetic core 501, external electrodes 512a and 512b, and a winding wire 513. The magnetic core 501 is made of an insulating material, and comprises a winding core portion 501a, and flanges 501b and 501c. The winding core portion 501a extends in the x-axis direction. The flanges 501b and 501c are disposed at both ends of the winding core portion 501a.
The external electrodes 512a and 512b are provided on the flanges 501b and 501c, respectively. A winding wire 513 is wound around the winding core portion 501a, and both ends of the winding wire 513 are connected to the external electrodes 512a and 512b, respectively.
In the magnetic core 501 of the wire-wound coil component 500 structured as thus far described, the flanges 501b and 501c protrude from the winding core portion in a direction perpendicular to the x-axis direction, as shown by FIG. 22. Thereby, the flanges 501b and 501c protect the portion where the winding wire 513 is wound around the winding core portion 501a from heat radiated from a thermo-compression bonding device while the external electrodes 512 and the winding wire 513 are connected.
However, the existence of the flanges 501b and 501c is a cause of chips or cracks in the magnetic core 501 that break out during a production process of the magnetic core 501. The flanges 501b and 501c are molded by filling powder of the material of the core in a female die, and by pressing the filled powder with male dies 550 and 560 as shown by FIG. 23. However, if side surfaces S501 to S504 of the flanges 501b and 501c are parallel to the pull-away direction, frictions between the side surfaces S501 to S504 and side surfaces S509 to S512 of the male dies 550 and 560 occur during the pull-away process after the pressing process. Consequently, the magnetic core 501 may have chips or cracks.
For the reason above, the magnetic core 501 of the wire-wound coil component 500 shown by FIG. 22 actually, at both ends of the winding core portion 501a in the x-axis direction, has taper surfaces S501′ to S504′ tapering from the winding core portion 501a toward end surfaces S505 to S508 of the flanges as shown by FIG. 24. Thereby, at the same time as the molding-die pull-away process starts, the side surfaces S509′ to S512′ of the male dies separate from the taper surfaces S501′ to S504′. Accordingly, the frictions between the taper surfaces S501′ to S504′ and the side surfaces S509′ to S512′ of the male dies are suppressed, and occurrence of chips or cracks in the magnetic core 501′ can be suppressed.
However, as shown in FIG. 24, since the taper surfaces are disposed at both ends of the winding core portion 501a in the x-axis direction, the area of the magnetic core 501′ used for winding of the wire is reduced. Accordingly, the number of turns or the diameter of the winding wire 513 are limited, which prevents improvement in inductance.

Core for a wire-wound electronic component, a wire-wound electronic component and a method for manufacturing a core for a wire-wound electronic component


A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.

The present invention relates to a voltage control circuit having the function of detecting which one of a reference voltage and an external supply voltage, such as a power source voltage supplied via a cable by the function of cable power status (CPS) conforming to, e.g., IEEE 1394 standard, is higher.
With the wide proliferation of multimedia centering around personal computers, the function of processing enormous amounts of data such as image data at a high speed has been required of each information device. Concurrently, technology for increasing a rate at which data is transferred between devices has been becoming important. Under such circumstances, the IEEE 1394 standard has been proposed as technology which enables high-speed data transfer, based on which development has been pursued. The IEEE 1394 standard suggests a serial transfer method whereby a transfer rate is increased by unprecedentedly reducing the number of buses, while increasing an operational frequency for transfer.
FIG. 8 shows a part of a configuration of an IEEE 1394 network system. In FIG. 8, individual network devices are connected to each other via cables. Each of the cables is composed of four data lines (a pair of data lines and a pair of strobe lines), a power source line, and a ground line. Depending on the type of a cable, only four lines compose the cable without using the power source line and the ground line.
An LSI compliant with the IEEE 1394 standard can be divided into a PHY section for primarily controlling data input and data output and a LINK section for controlling a transfer protocol. During data reception, a signal is transferred from a transfer cable to the PHY section and then from the PHY section to the LINK section. During data transmission, the signal is transferred in the opposite direction.
Besides high-speed data transfer, the IEEE 1394 standard also supports the CPS function for supplying power from a power source via the data transfer cable. The IEEE 1394 standard includes a plurality of standards such as IEEE 1394_1995, IEEE 1394. A, and IEEE 1394. B and the CPS function is defined in each of the standards.
That is, in an LSI compliant with the IEEE 1394 standard, the CPS function should be operated when the power-source voltage supplied via the cable is within a specified range. Since the CPS function is the standard for the PHY section for controlling data input and data output, it is necessary for the PHY section to have the function of detecting whether or not the power source voltage supplied via the cable is within the specified range.
In the IEEE 1394_1995, e.g., the voltage supplied from the outside by the CPS function is defined to be 8 to 40 V. This means that the CPS function should be operated when the voltage is at least in the range of 8 to 40 V. To develop an LSI compliant with the standard, therefore, it is necessary to provide the function of detecting whether or not the voltage supplied from the cable is within the range of 8 to 40 V.
However, the application of a high voltage of 8 to 40 V directly to an LSI leads to the breakdown of the LSI and is not preferred. For this reason, the standard proposes reducing a supply voltage via a 400-k xcexa9 voltage dropping resistor and applying a reduced voltage to the PHY section. Consequently, the PHY section is so configured as to estimate the supply voltage by detecting the reduced voltage so that the accuracy of voltage drop as well as the accuracy of voltage detection are important factors in observing the standard.
As far as the present inventors have investigated, however, there has been proposed no circuit configuration which conforms to the standard.
FIG. 10 shows a circuit configuration of a voltage determining unit 15 conforming to the standard, which has been devised by the present inventors. In FIG. 10, a cable 12 is connected to an input terminal 51 of a voltage control circuit 50 via a voltage dropping resistor 11 (having a resistance value R0). In the voltage control circuit 50, a resistor element 52 (having a resistance value R1) is connected to the input terminal 51 to be disposed in series to the resistor 11. A current Icps flows from the cable 12 to the ground Vss and an external voltage VDD_ext is converted to a voltage Va in the voltage control circuit 50. A comparator 53 compares the converted voltage Va with a comparison voltage Vb and outputs a signal Vcps indicative of the result of comparison. The signal Vcps becomes HIGH when the converted voltage Va is higher than the comparison voltage Vb, which enables the detection of the supply of a voltage that can be supplied via the cable as the external voltage VDD_ext.
FIG. 11 is a graph showing the relationship between the external voltage VDD_ext and the converted voltage Va in the circuit configuration of FIG. 10. In FIG. 11, a power-source voltage VDD_int to the voltage control circuit 50 is assumed to be 3.3 V and a maximum withstand voltage Vmax is assumed to be 3.6 V. As shown in FIG. 11, the external voltage VDD_ext and the converted voltage Va are constantly in a proportional relationship in the circuit configuration of FIG. 10. The resistance value R1 is adjusted to such a value that the converted voltage Va does not exceed the maximum withstand voltage Vmax of 3.6 V even when 40 V is given as the external voltage VDD_ext. Hence,
R1=3.6xc2x7R0/(40xe2x88x923.6)=0.0989xc2x7400 k=39.56 kxcexa9
is derived from
xe2x80x833.6/R1=40/(R0+R1).
If the maximum value of the converted voltage Va is set to 3.3 V by allowing a margin,
R1=3.3xc2x7R0/(40xe2x88x923.3)=0.0899xc2x7R0=39.95 kxcexa9
is satisfied. Therefore, the resistance value R1 of the resistor element 52 is preferably adjusted to be in the range of 35 kxcexa9 to 40 kxcexa9. It will easily be appreciated that the resistance value R1 of the resistor element 52 varies depending on the voltage supplied via the cable, the maximum withstand voltage, or the resistance value of the voltage dropping resistor.
Although the reference voltage serving as the standard for determining the external voltage VDD_ext is 8 V, the reference voltage has been set to 7 V and the comparison voltage Vb has been set to 0.63 V, since it is common to set the reference voltage to the order of 5 V to 7.5 V by allowing a margin. The comparison voltage Vb is set appropriately based on the reference voltage and on the ratio between the respective resistance values of the voltage dropping resistor 11 and the resistor element 52.
In a circuit configuration as shown in FIG. 10, however, the external voltage VDD_ext and the converted voltage Va are in the proportional relationship and the converted voltage Va is about {fraction (1/10)} of the external voltage VDD_ext. If the external voltage VDD_ext varies greatly, therefore, the converted voltage Va changes only by about {fraction (1/10)} of the variation of the external voltage VDD_ext. Conversely, variations in comparison voltage Vb and variations in the detection accuracy of the comparator 53 are magnified ten times to affect the detection of the external voltage VDD_ext. Variations in the resistance of the resistor 52 also greatly affect the accuracy with which the external voltage VDD_ext is detected.
On the other hand, it is considered that an input to the comparator is preferably set to about xc2xd of the power-source voltage in terms of sensitivity. In the circuit configuration of FIG. 10, the level of the input to the comparator 53 is close to the ground potential Vss, which is not preferred in terms of detection accuracy.
It is therefore an object of the present invention to perform a high-accuracy comparison between an external voltage and a reference voltage in a voltage control circuit for implementing, e.g., the CPS function. To attain the object, the present invention has widened the range of a converted voltage in a region in which the external voltage is close to the reference voltage and shifted the range to higher voltages, thereby increasing the accuracy of comparison between the external voltage and the reference voltage.
Specifically, the present invention in a first aspect is a voltage control circuit for detecting which one of an external voltage supplied from the outside and a reference voltage serving as a standard for comparison is higher, the circuit comprising: an input terminal to which the external voltage is applicable via a voltage dropping resistor; voltage converting means for converting, in conjunction with the voltage dropping resistor, the external voltage applied to the input terminal to a voltage lower than the external voltage; and comparing means for comparing a converted voltage outputted from the voltage converting means with a specified comparison voltage corresponding to the reference voltage and outputting a signal indicative of the result of comparison as a signal indicative of which one of the external voltage and the reference voltage is higher, the voltage converting means performing a voltage conversion such that a ratio of an increment of the converted voltage to an increment of the external voltage is relatively high in a comparison region in which the external voltage is close to the reference voltage and relatively low in a region in which the external voltage is higher than in the comparison region.
In accordance with the present invention in the first aspect, the voltage converting means performs a conversion such that the ratio of the increment of the converted voltage to the increment of the external voltage is relatively high in the comparison region and relatively low in a region in which the external voltage is higher than in the comparison region. This provides a wide range of converted voltages in the comparison region, while controlling the converted voltage in a region in which the external voltage has a value higher than in the comparison region such that the converted voltage does not exceed the withstand voltage. This remarkably suppresses the influence given by the varying comparison voltage and the varying detection accuracy of the comparing means on the external voltage, so that the accuracy of a comparison made between the external voltage and the reference voltage is increased.
Preferably, the voltage converting means in the voltage control circuit comprises a diode or diode-connected transistor connected to the input terminal to be disposed in series to the voltage dropping resistor. Preferably, the comparing means in the voltage control circuit comprises comparison voltage generating means for generating the comparison voltage, the comparison voltage generating means comprising: a constant current source; and a diode or diode-connected transistor disposed in series to the constant current source.
Alternatively, the voltage converting means in the voltage control circuit comprises: a voltage dropping element connected to the input terminal to be disposed in series to the voltage dropping resistor; and a clamping circuit for limiting a voltage on a side of the voltage dropping element closer to the input terminal such that the voltage does not exceed a specified limit voltage.
Preferably, the clamping circuit comprises: a transistor disposed in parallel with the voltage dropping element; and a comparator for receiving a drain voltage of the transistor as one input and the limit voltage as the other input, an output of the comparator serving as an input to a gate of the transistor. Alternatively, the clamping circuit comprises a single diode or diode-connected transistor disposed in parallel with the voltage dropping element or a plurality of diodes or diode-connected transistors disposed in series to each other and in parallel with the voltage dropping element. Preferably, the voltage dropping element is a resistor, a diode, or a diode-connected transistor.
In a second aspect, the present invention is a network device connectable to a cable, the device comprising a voltage determining unit for determining whether or not an external supply voltage supplied via the cable is within a specified range, the voltage determining unit comprising: a voltage control circuit as recited in claim 1; and a voltage dropping resistor having one end connected to the input terminal of the voltage control circuit and the other end to which the external supply voltage is given.
In a third aspect, the present invention is a voltage control circuit for detecting which one of an external voltage supplied from the outside and a reference voltage serving as a standard for comparison is higher, the circuit comprising: an input terminal to which an external voltage is applicable via a voltage dropping resistor; a resistor element having one end connected to the input terminal and the other end grounded; and a comparator for comparing a voltage at the one end of the resistor element with a specified comparison voltage corresponding to the reference voltage and outputting a signal indicative of the result of comparison as a signal indicative of which one of the external voltage and the reference voltage is. higher.
Preferably, the voltage dropping resistor in the voltage control circuit has a resistance value of 400 kxcexa9 and the resistor element has a resistance value of 35 kxcexa9 to 40 kxcexa9.
Preferably, the specified comparison voltage is determined based on the reference voltage and on a ratio between respective resistance values of the voltage dropping resistor and the resistor element.
In a fourth aspect, the present invention is a method of detecting, in a network device, which one of an external supply voltage supplied via a cable and a reference voltage serving as a standard for comparison is higher, the method comprising the steps of: converting the external supply voltage to a voltage lower than the external supply voltage; and comparing a converted voltage obtained in the voltage converting step with a specified comparison voltage corresponding to the reference voltage, the voltage converting step performing a voltage conversion such that a ratio of an increment of the converted voltage to an increment of the external supply voltage is relatively high in a comparison region in which the external supply voltage is close to the reference voltage and relatively low in a region in which the external supply voltage is higher than in the comparison region.

Voltage control circuit network device and method of detecting voltage

Matsushita Electric Industrial Co., Ltd.


An ultrasound transducer includes an array of acoustic elements, an integrated circuit, and an interposer. The interposer includes conductive elements for electrically connecting the acoustic elements to the integrated circuit. The conductive elements are electrically connected to the integrated circuit. Solder is engaged between the acoustic elements and the conductive elements of the interposer such that the conductive elements of the interposer are electrically connected to the acoustic elements through the solder.

The subject matter disclosed herein relates generally to ultrasound systems, and more particularly to ultrasound transducers and methods for manufacturing ultrasound transducers.
Ultrasound systems typically include ultrasound scanning devices (e.g., an ultrasound transducer housed within a probe) that perform various ultrasound scans (e.g., imaging a body or other volume). The scanning devices include acoustic elements that transmit and receive ultrasound signals. The acoustic elements may be arranged in an array. The ultrasound signals received by the acoustic elements are used to generate an image of the body or other volume. For example, the received ultrasound signals may be used to generate an image of internal tissues of a patient, such as, but not limited to, an image of a patient's heart.
At least some known ultrasound systems include an interposer (e.g., a flex circuit) that is electrically and mechanically connected to the acoustic elements. The interposer extends between the acoustic elements and a thermal backing layer or electronics (e.g., one or more integrated circuits) that perform transmit and/or receive beamforming operations on the ultrasound signals. For example, the interposer may extend between the acoustic elements and beamforming electronics to provide an electrical connection between the acoustic elements and the beamforming electronics. Alternatively, and for example, the interposer extends between the acoustic elements and a thermal backing layer to mechanically connect the acoustic elements to the thermal backing layer. Some know interposers are cables that electrically connect the acoustic elements to one or more other components (e.g., an RF processor, a memory, a signal processor, a user input, beamforming electronics, a display, and/or the like) of the ultrasound system.
In some known ultrasound systems, an epoxy is used to mechanically connect or both mechanically and electrically connect the interposer to the acoustic elements. But, the mechanical connection provided by the epoxy may be susceptible to failure from environmental stresses. For example, the mechanical connection provided by the epoxy may fail when the ultrasound scanning device is exposed to water and/or other liquids over a period of time (e.g., when all or a portion of the ultrasound scanning device is soaked in water and/or another liquid). Failure of the mechanical connection between the acoustic elements and the interposer may electrically disconnect the interposer from the acoustic elements and thereby disrupt operation of the ultrasound system.

Ultrasound transducer and method for manufacturing an ultrasound transducer


Technologies are described herein for generating a mailbox specific frequent word list associated with a mailbox. In one method, an index scan is performed on catalogs to retrieve search data mapping words to emails containing the words. The search data is provided across multiple mailboxes. A universal frequent word list is generated based on the search data. The mailbox specific frequent word list is generated based on the universal frequent word list.

In recent years, electronic mail ("email") has become one of the most important forms of communication for various personal and business uses. The growth of e-mail communications has been spurred, at least in part, by the increasing number of devices capable of remotely accessing email. For example, many mobile devices, such as cellular phones, smartphones, and personal digital assistants ("PDAs"), are now capable of remotely and wirelessly accessing email through various pull-based and push-based e-mail access protocols.
A typical user's mailbox may contain hundreds or thousands of e-mails on a wide variety of topics ranging from the user's plans for lunch at her favorite cafe to the user's input regarding her workgroup's latest business project. A user's e-mails may also be utilized to infer information about the user. For example, a higher frequency of e-mails to certain people may indicate that the user has a closer relationship with those people. As a result, a user's mailbox can be a valuable source of relevant information about the user, especially for application programs that can utilize or benefit from such information.
It is with respect to these considerations and others that the disclosure made herein is presented.

Generation and use of an email frequent word list


The reproduction device comprises a decoding section, a threshold calculating section, and a musical data output section. The threshold calculating section calculates an average amplitude level in a predetermined section of an end portion of first musical data generated by the decoding section, and calculates a threshold for detecting a silent portion of the end portion of the first musical data on the basis of the calculated average amplitude level. The musical data output section removes a silent portion between the first musical data and the second musical data and reproduces them so that a position nearest to the end position of the first musical data at an amplitude level which is the threshold or more is a reproduction ending position and so that a position near the leading position of the second musical data at an amplitude level which is the threshold or more is a reproduction starting position.

1. Field of the Invention
The present invention relates to a reproduction device, a reproduction method and a computer usable medium having a computer readable reproduction program embodied therein for decoding compressed musical data and reproducing the decoded musical data while suppressing the occurrence of a gap causing sound interruption between pieces of music.
2. Description of the Related Art
Various musical data compression technologies such as MP3 (MPEG-1 Audio Layer III) and AAC (Advanced Audio Coding) have been standardized due to the spread of portable digital audio players (DAP).
In such compression technologies, data of a piece of music is managed as one music source, and one music source is divided into frames and compressed (encoded). In an encoding process of obtaining compressed musical data from a music source, a modified discrete cosine transform (MDCT) is used. An MDCT transform is performed making adjacent frames overlap each other, thereby having the advantage of preventing the occurrence of a noise on the boundary between the adjacent frames.
On the other hand, since an MDCT transform makes adjacent frames overlap each other, it needs, when expanding (decoding) data of a frame, data of a frame just before the frame to be expanded. Therefore, in encoding using an MDCT transform, a leading frame to which a silent portion is added is produced before the leading position of musical data. Likewise, an end frame to which a silent portion is added is produced after the end position of the musical data.
FIG. 1 shows an example of a waveform of the leading portion of a music source before encoding, and an example of a waveform of the leading portion of compressed musical data after encoding. As shown in FIG. 1, the compressed musical data after encoding is divided into frames, and a silent portion is added to the leading portion. The compressed musical data after encoding in FIG. 1 causes a delay of sound emission as compared with the musical data before encoding due to addition of a silent portion to the leading portion. FIG. 2 shows an example of a waveform of the end portion of a music source before encoding, and an example of a waveform of the end portion of compressed musical data after encoding. As shown in FIG. 2, a silent portion is added also to the end portion of the compressed musical data after encoding.
By the way, music compact discs (CDs) include so-called live disks on which a live performance music constituted by pieces of music connected with each other is recorded. When encoding is performed every music source of a piece of music obtained by playing back a live disk by a compression technology using the MDCT transform described above to produce compressed musical data, and then the compressed musical data is decoded to be reproduced, a gap occurs between the end portion of a piece of music and the leading portion of the next piece of music. By the occurrence of this gap, the sound is interrupted momentarily and an unnatural sound is reproduced.
The following techniques of eliminating such a gap between pieces of music are known.
(1) When music is switched from a piece of music to the next piece of music, cross-fade that fades out the sound of the end portion of a reproduced piece of music and simultaneously fades in the sound of the leading portion of a piece of music reproduced next (the next reproduced piece of music) is performed for several seconds, thus reproducing the pieces of music in such a manner, a gap between the pieces of music is inconspicuous. FIG. 3 shows an example of a waveform in which a reproduced piece of music indicated with a broken line and the next reproduced piece of music indicated with a solid line are cross faded.
(2) Information about the length of a music source is stored when encoding the music source, and gaps between pieces of music are eliminated based on the information, thereby reproducing the pieces of music without the occurrence of gaps between the pieces of music.
(3) Music sources of a plurality of pieces of music having no silent portion between pieces of music such as music sources of a live disk are stored in one file, thereby reproducing the pieces of music without the occurrence of gaps between the pieces of music. This technique is disclosed in Japanese Patent Application Laid-Open No. 2004-93729.
However, in the case of technique (1), pieces of music are not connected continuously as shown in FIG. 3, so that reproduced sound is unnatural. In the case of technique (2), a player reproducing pieces of music while eliminating gaps between pieces of music is limited to one corresponding to a device (encoder) which performs the encoding. In other words, the player is required to previously know what kind of encoding was performed. In the case of technique (3), the player is limited to one corresponding to the encoder as in the case of technique (2). Furthermore, the whole of music sources of two or more pieces of music is stored in one file, so that it is difficult to reproduce a desired piece of music immediately.

Reproduction device, reproduction method and computer usable medium having computer readable reproduction program emodied therein


A system and method for classifying failures of semiconductor integrated circuit dies using a unique input vector created from die level characterization data to classify wafer (process related) and die level (defect related) patterns. The failure classification may then be used to assign the appropriate yield loss by die. The classification results produced by the plurality of classifiers are examined with a preference towards assigning a wafer level failure classification to failure data for a die when any of the plurality of failure classification results indicates a presence of a wafer level failure.

In the semiconductor manufacturing industry, semiconductor fabrication processes are used to make a wafer on which a plurality of integrated circuit dies are formed. A fabrication process is run to produce thousands (or more) parts and it is not uncommon to produce some dies that have irreparable defects or failures. The percentage of the integrated circuit dies produced that are operational is referred to as the "yield" of the process.
In order optimize the wafer/chip yield, a semiconductor manufacturer allocates engineers to analyze the yield of a process by grouping die failures into categories or classifications. Thus, one of the primary functions of a yield analysis engineer is to troubleshoot die failures, communicate the failure information and quantify the loss (impact on the yield) associated with the identified failure categories or classes. It is necessary to classify the failures before troubleshooting the failure causes.
Current failure classification techniques are completely manual. Engineers manually review failure pattern data to group wafer and die failures into categories and estimate yield loss based on the amount of loss that an engineer assigns to a lot. The amount of loss assigned to each failure class/category (also called a "detractor") is based on the engineer's judgment, and therefore is subjective.
There are several problems with the current manual failure classification techniques. Because the yield analysis engineer uses his/her subjective judgment to assign a loss amount to a detractor, there is inherently a bias on the detractors. Classification becomes more difficult and the yield detractor analysis less accurate as the yield increases and the semiconductor fabrication process matures.

Die and wafer failure classification system and method


Monolithic cartridges including a plurality of nominally aligned polymer fibers can be used as stationary phase materials for liquid chromatography separations. Bundles of fibers are packed together so as to form capillary channels between the fibers. Different polymer compositions permit the “chemical tuning” of the separation process. The fibers can be physically or chemically bonded at spaced locations throughout the cartridge or can be packed together under pressure by use of an encasing wrap to form the capillary channels. Use of fibers allows a wide range of liquid flow rates with very low backpressures. Applications in HPLC, cap-LC, prep-scale separations, analytical separations, waste remediation/immobilization, extraction of selected organic molecules/ions from solution, purification of liquid streams (process waste, drinking water, pure solvents), selective extraction of cell matter and bacteria from growth media, and immobilization of cell matter and bacteria are envisioned.

The present invention relates to chemical analysis and cleansing of liquid streams and more particularly to liquid chromatography and wastewater treatment.
At present, liquid-phase chemical separations are usually performed in "columns" prepared by the packing of metal tubes with spherical beads that are composed of either silica or polystyrene and have diameters of 3 to 50 μm. The more or less inert beads provide solid supports that are chemically modified to produce a surface having targeted chemical characteristics. For example, in performing reversed-phase liquid chromatography, long carbon chains (C-18) can be affixed to the surfaces of the beads so as to produce a hydrophobic surface for the separation of non-polar organics. In some systems, beads can include particular surface polymers upon formation, precluding the necessity of post-formation modification of the materials.
Effective separations require dense packing of the beads into these columns to avoid dead-volume, which is any location within the column where turbulence can occur and interactions between molecules in the liquid and the surfaces of the beads are minimal. As a consequence of dense packing, high driving pressures (e.g., 2,000 to 5,000 psi) are required to overcome the backpressures that otherwise would prevent the liquid phase from moving through the densely packed columns.
Alternatively, highly porous "monoliths" are formed within the columns to generate high surface areas for interaction with the species that flow through the columns. Here, the high backpressures and a limited set of stationary phase chemistries can be restrictive. In the case of so-called "prep-scale" separations, the capital costs associated with producing large volume columns and the demands on the system hydraulics (i.e. pumps) are very high.

Monolithic structures comprising polymeric fibers for chemical separation by liquid chromatography


The method relates to the generation of interfaces that are structured around a window and can be displayed on the screen of a data processing system working in the graphics mode. The method is characterized in that a survey module is associated with the items incorporated in the interface, the module being arranged for displaying, in at least one survey window (16), an instantaneous synoptical table (18, 20) representing the constitution of all or part of the interface and composed on the basis of a descriptive status of the items (22), and that in the interactive mode, the creation and/or modification and/or incorporation of the items (22) is performed with the aid of at least one working window, preferably of the dialog window type, under the instantaneous control of the survey module. The invention also relates to an apparatus for performing this method.

For some years, it has been a goal to separate the interface module from the body of the user application, essentially to gain flexibility in creation and adaptation. This makes it easier for the interface developer to adapt his program to the hardware as needed, for instance when creating a capture mask or a display mask. The current trend is accordingly to develop interfaces independently of the body of the user application, and to assemble the two programs in the final phase, just before they are executed.
Microsoft has developed a graphics-mode user applications management system called MS-Windows, with which such applications interfaces can be generated by programming and executed. Even though this management system performs well for the end user, access to it is still difficult for the interface developer user, who must be an experienced programmer. In fact, such development cannot be done without learning various programming languages, such as C, beforehand, which is a very long, complicated process.

Method of generating interfaces for use applications that are displayable on the screen of a data processing system, and apparatus for performing the method


A cooling fan device for a computer including a fan device having a primary housing and a side housing. A computer casing a side walls having an area with air permeable holes, right positioning slots, and a left positioning slot. Projection parts of the primary housing are latched into the right positioning slots, and a flange part on a press plate is latched into the left positioning slot, such that the fan device can be quickly assembled on or disassembled from the computer casing without using screws.

(a) Field of the Invention
The present invention relates to a cooling fan locking device for a computer, and more particularly to a cooling fan locking device which can be quickly, conveniently assembled and disassembled without using screws.
(b) Description of the Prior Art
It is known that a conventional fan for a computer is always installed in an interior of a computer casing, and is always fixed with screws, which is very awkward and inconvenient in assembling and disassembling.


An electrical connector 2 includes terminal 4 in a housing 10 with a terminal position assurance member 30 backing up the resilient latches 18 holding the terminals 4 in housing cavities 16. The terminal position assurance member 30, inserted through the housing mating face 12, is shiftable between a partially inserted position, in which terminals 4 can be inserted into cavities 16 through the housing rear face 14 and a locked position after all terminals 4 have been properly inserted. The terminal position assurance member 30 includes a horizontal wall 36 insertable behind the housing latches 18 and panels 42 on either side. To shift the terminal position assurance member 30 to the locked position, the panel must deflect outwardly about a fixed front edge 46 and a fixed base edge 44 to permit an inwardly extending panel latching projection 50 to pass a housing shoulder 26. To prevent plastic deformation of the latching projection 50, the latching projection upper surface 52 is inclined and its height, measured relative to the panel 42 increases with distance away from the horizontal wall 36.

1. Field of the Invention
This invention relates to electrical connectors having terminal position or secondary locking members for insuring that all of the connector terminals are properly positioned in the electrical connector housing.
2. Description of the Prior Art
Terminal position assurance members are commonly used in electrical connectors that are used in the automotive industry. Improperly assembled electrical connectors pose a problem in any application in which electrical connectors must be assembled on wiring harnesses. If one terminal is not properly positioned, the entire harness can be defective and considerable time and effort may be necessary to diagnose this problem.
When a large number of connectors must be assembled and installed it becomes impractical to rely upon an operator to reliably install all of the terminals or to inspect to determine if automatic assembly equipment has properly loaded all of the connectors.
One approach that is commonly used in the automotive industry to counteract this problem is the use of terminal position assurance members that cannot be properly installed in a connector if any of the terminals in that connector are only partially inserted. These terminal position assurance members are commonly used with connector housings which have resilient latches that are integral parts of the molded plastic connector housing and extend into housing cavities to engage terminals inserted in the connector. One common approach is to employ a connector housing in which the terminals are inserted into housing cavities through a rear housing face after wires have been attached or crimped to the terminals. As the terminals are inserted further into the housing cavities, the terminal progressively deflect the housing terminal latches until the terminals pass the latches and the latches return to their normal position where they engage the terminals to prevent extraction of the terminals through the housing rear face. After the terminals are latched in this manner, a terminal position assurance member is inserted through the mating face of the connector housing. A ledge, shelf or wall on the terminal position assurance member then slides behind the latches to hold the latches in engagement with the terminals. However, if any one terminal is only partially inserted, the terminal position assurance will engage a deflected housing terminal latch and cannot be fully inserted. Incomplete insertion of the terminal position assurance member can then be used to detect an improperly assembled or loaded connector. One reason for inserting these terminal position assurance members through the front or mating face of the connector is that a partially inserted terminal position assurance member should prevent mating of the improperly assembled connector with a mating connector.
Electrical connector housing assemblies are commonly shipped with a terminal position assurance member latched to the connector housing in a partially assembled configuration in which the terminal latches are free to deflect during terminal insertion. Since the terminals are normally attached to wiring harnesses at a harness assembly location and not at a molding location, shipping in a partially assembled configuration is a common practice. However, it is important that the terminal position assurance member be latched in this partially inserted condition so that it cannot be extracted or fully inserted unless a minimum force, that is not typically encountered during shipping, is applied to the terminal position assurance member. Therefore the terminal position assurance members can include latching projections that hold the terminal position assurance members in the partially inserted and in a locked position. To shift the terminal position assurance member from the partially inserted to the locked position, that portion of the terminal position assurance member containing the latching projection must be flexible so that it can deflect to permit the latching projection to pass a latching shoulder on the housing. To allow for adequate deflection, the terminal position assurance members are normally molded from a non glass filled plastic that is flexible. However, care must be taken to prevent plastic deformation as the latching projection passes a harder, typically glass filled housing.
In one prior art connector the latching projections extend inwardly from vertical panels on the terminal position assurance member. The panels deflect outwardly, but to insure that a minimum force is applied before deflecting the panel so that the terminal position assurance member can be shifted to the locked position, this prior art connector employs a panel that if fixed along perpendicular lower and front edges so that the panel cannot shift as a conventional cantilever beam, fixed at only one edge. In this configuration the latching projections can be smeared or plastically deformed and the latching projections then cannot properly engage the housing to hold the terminal position assurance member in the latched configuration.

Electrical connector with dual position latched terminal position assurance


A crystallizing method for forming a poly-Si film is described as follows. First, forming an activated layer on a substrate, and the molecule structure of the activated layer includes carbon, hydrogen, oxygen and silicon. And then, forming an amorphous silicon film on the activated layer. Finally, performing an annealing process to crystallize the amorphous silicon film and transform it into a poly-Si film.

(1) Field of the Invention
The invention relates to a method for forming a poly-Si film though crystallizing an amorphous silicon film.
(2) Description of the Related Art
A poly-Si material has better attributes than an amorphous silicon material. Because of larger grain size, an electron is easier to move in the poly-Si material. That is, the mobility of the poly-Si material is higher than that of the amorphous silicon material. A transistor made of the poly-Si material has shorter reaction time than a transistor made of the amorphous silicon material. Comparing two liquid crystal displays at the same resolution, the one using a poly-Si TFT occupy less substrate area than the one using an amorphous silicon TFT, so that using the poly-Si TFT can increase the open ratio of the liquid crystal panel. Under the same brightness, the poly-Si TFT LCD can use a low-power backlight to reduce the power consumption. Therefore, the grain size of the poly-Si is an important factor affecting the efficiency of a TFT.
Presently, a poly-Si film is made on the substrate by Low Temperature Poly-Silicon (LTPS) process. The LTPS uses a excimer laser as a heat source. When the excimer laser irradiates on the substrate having an amorphous silicon film, the amorphous silicon film absorbs the energy of the laser to transform into the poly-Si film.
FIG. 1A and FIG. 1B shows a conventional method for manufacturing the poly-Si film. As shown in FIG. 1A, a nitride layer 11 is formed on a substrate 10. An oxide layer 12 is formed on the nitride layer 11. Subsequently, an amorphous silicon film 13 is formed on the oxide layer 12 by chemical vapor deposition (CVD) or sputtering. As shown in FIG. 1B, the amorphous silicon film 13 is irradiated by the excimer laser 15 to crystallize to form a poly-Si film 14. For acquiring larger grains, the energy of the excimer laser 15 should be able to almost completely melt the amorphous silicon film 13. Some non-melted grains remain on the interface between the oxide layer 12 and the amorphous silicon film 13. The melted amorphous film uses the non-melted grains as crystallization seeds to crystallize to form the poly-Si film 14.
However, the excimer laser is an pulse laser. The energy density of each pulse in the excimer laser is different from the other pulses. The larger energy density causes less amounts of crystallization seeds, and results in smaller grains and less homogeneity. According to the conventional method, the uncertain crystallizing direction makes it difficult to control the number and the location of the grain boundary. Under stable laser energy, it is necessary to reduce the crystallization energy and enlarge line beam size by an optical system to increase product output. Besides, more grain boundaries cause worse electrical characteristics of the poly-Si TFT.
To sum up, the conventional method is not capable of controlling the number and the location of the grain boundary, so that the crystallizing direction is uncertain, and it is not capable of reducing the laser energy requirement in the crystallization process, either. For reasons given above, the inventor submits a method for manufacturing the poly-Si film to improve the abovementioned disadvantages, and further, the method can be applied to manufacturing TFT.

Polysilicon film, thin film transistor using the same, and method for forming the same


The invention is directed to a method for isothermally amplifying a DNA sequence involving hybridizing a destabilizing DNA template to complementary nucleotide fragments to form a first nicked duplex; ligating the first nicked duplex to form a product duplex comprising the DNA sequence and the template, wherein the product duplex is capable of dissociating to release the DNA sequence and the template; and repeating these steps to generate multiple copies of the template and the DNA sequence. Further, the method may also involve hybridizing the DNA sequence to complementary destabilizing fragments or probes to form a second nicked duplex; ligating the second nicked duplex to form the product duplex comprising the DNA sequence and the template, wherein the product duplex dissociates to release the DNA sequence and the template; and repeating these steps to generate multiple copies of the template and the DNA sequence.

DNA-based systems have been developed that are capable of performing sophisticated functions initiated by molecular recognition. Key examples are the DNA walkers where directional motion or load pick-up, transfer, and release are achieved with molecular and spatial selectivity (Gu et al., 2010; Lund et al., 2010). However, attempts to develop autonomous DNA self-replicating systems without specific sequence requirements have in recent years lagged behind (Lincoln, 2009; Patzke et al., 2007; Ye et al., 2000; Zielinkski et al., 1987). As one of the hallmarks of organisms is their ability to amplify information and materials through biocatalysis and self-replication, the development of truly biomimetic systems capable of integrated functions requires incorporating amplification into self-assembly and nanotechnology (Aldaye et al., 2008; Patzke et al., 2007; Paul et al., 2004). Replicating DNA systems not only provide tools for DNA-based nanotechnology and insights into the origins of life, but also can be used to isothermally amplify signal in DNA detection, which can simplify the requirements for point-of-care diagnostics (Aldaye et al., 2008; Connolly et al., 2010; Orgel, 1992; Patzke et al., 2007; Paul et al., 2004).
One method for introducing amplification into DNA-based systems involves generating turnover in DNA-templated processes (Grossman et al., 2008). To achieve turnover, the DNA template that facilitates the reaction of two complementary fragment strands (FIG. 1, steps A-B) must dissociate from the product after it has formed (FIG. 1, step C). However, for ligation reactions, turnover is minimal under isothermal conditions owing to the enhanced affinity of the template for the ligated product (Grossman et al., 2008). Many detection strategies have thus focused on template-triggered scission and transfer reactions rather than ligations to avoid this product inhibition (Grossman et al., 2008). One strategy for introducing turnover into ligation reactions exploits the sensitivity of DNA to destabilizing modifications present in the middle of a duplex (Silverman et al., 2006; Ye et al., 2000; Zhan et al., 1997). By ligating strands at a destabilizing site, the stability of the hybridization complex can be modified without changing the temperature or any other reaction condition (Li et al., 2003). If the stabilities of the complexes before and after ligation are properly balanced, isothermal turnover should be achieved.

Nucleic acid amplification by a destabilization method


An apparatus and method of reducing power consumption in an integrated device having a first module with a mandatory operating frequency and a second module with a flexible frequency requirement. The integrated device is powered by a serial bus. The first module is segregated from the second module in the time domain by a frequency independent interface. The second module is then operated at a lower frequency when power conservation is needed. The operating frequency of the second module can be dynamically changed to improve performance of the second module when a power budget for the device permits.

1. Field of the Invention
The invention relates to reduction of power consumption. More specifically, the invention relates to reducing power consumption of an integrated microprocessor in a USB device to satisfy USB enumeration power requirements for bus powered devices.
2. Related Art
The Universal Serial Bus follows a protocol defined in Universal Serial Bus Specification, Version 1.0 (USB Spec). Modification of this specification can be expected from time to time. However, the USB Spec provides a standardized approach for peripheral interconnection with a host computer. The USB is set up in a tiered topology with a host on the top tier and USB hubs and functions on subsequent tiers. Each USB device, whether it be a hub or a function, has associated therewith a serial interface engine (SIE) which provides an interface between the hub or function and the transceiver which transmits or receives signals across the serial line. Generally, the SIE takes care of all the USB low level protocol matters such as bit stuffing, cyclic redundancy checks (CRCs), token generation, and handshaking.
From a power perspective, two types of USB devices exist, bus powered devices and self-powered devices. As the name implies, bus powered devices receive their required power supply from the USB. The USB Spec mandates that no bus powered device shall draw more than 1 unit current (100 mA) during enumeration. This extreme power limitation has precluded the integration of general purpose high performance microcontrollers into the USB module. Instead, stand alone USB controllers have been used to implement USB devices. This reduces a flexibility of the devices and requires increased technical support as multiple products must be maintained and supported instead of a single general purpose high performance microcontroller.
In view of the foregoing, it would be desirable to be able to reduce the power consumption of a general purpose high performance microcontroller integrated into a USB module so as to satisfy the USB specification during enumeration.

Low ICC enumeration scheme for bus powered USB device


Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory, a data de-randomizer circuit operable to de-randomize a read data set accessed from the solid state memory device, a soft data generation circuit operable to receive multiple instances of one or more elements the read data set and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to apply a soft decoding algorithm to the soft data to yield a decoded output. Each instance of a respective element may be read using a different reference value.

Data in a solid state storage device decays over time requiring more error correction capability over time. To correct additional errors, enhanced error correction circuitry may be employed. However, such enhanced error correction circuitry increases access latency.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for maintaining data in a solid state storage device.

Systems and methods for soft decision generation in a solid state memory system


An electronic device interface is provided that is selectively interconnectable to a portable electronic device. The interface is preferably interconnected to the portable electronic device via inwardly-biased arms that end in fingers that engage opposing edges or corners of the portable electronic device. The interface may receive a positioning grip that includes a support having at least one selectively deflectable surface.

Portable electronic devices, such as tablet computers, netbooks, readers, iPads®, Kindles®, personal computers, communication devices, and other similar mobile devices (hereafter "electronic device") have become increasingly popular. One drawback of these devices is that their size, shape and/or surface texture often renders them difficult to hold and tilt to an acceptable viewing angle. More specifically, it is often desirable to tilt the electronic device to enhance readability or functionality, which is usually done by hand. Those familiar with such devices will appreciate that after time, the user may become fatigued, which results in the reduction of holding force and associated stability. Holding an electronic device also does not permit the use of one or both hands for other activities that may be related to the functions being performed by an electronic device, e.g. typing. Further, some electronic devices are small, sleek, and have smooth surfaces, and are thus difficult to grasp.
Thus, it is desirable to provide a grip, i.e., a tactile user interface, for selective interconnection to the electronic device to facilitate holding and positioning thereof. Embodiments of the present invention, which will be described in detail below, provide a user interface for selective interconnection to an electronic device that allows static or dynamic user interaction with the associated electronic device, which also allows the electronic device to be used in a hands-free manner.

Positioning grip for a mobile electronic device


The present invention is directed to methods of treating a patient to prevent vein graft failure by administering a compound that inhibits the Notch signaling pathway.

The Notch Signaling Pathway
The Notch signaling pathway has been identified as playing an important role in many diverse biological functions, including differentiation, and cellular proliferation (see U.S. Pat. No. 6,703,221). This pathway is activated by four different transmembrane receptor subtypes (designated as Notch1-Notch4) that rely on regulated proteolysis. Expression patterns and functions of Notch depend on cell type and context. Following ligand binding, the receptor undergoes sequential cleavage by metalloproteases of the ADAM family (Bru, et al., Mol. Cell 5:207-216 (2000); Mumm, et al., Mol. Cell 5:197-206 (2000)) and the presenilin-dependent gamma-secretase (Selkoe, et al., Annu. Rev. Neurosci. 26:565-97 (2003); De Strooper, et al., Nature 398:518-522 (1999)). The final proteolytic cleavage step permits the intracellular domain of the Notch receptor to translocate to the cell nucleus where it interacts with transcription factors to induce target gene expression.
In the cell nucleus, the Notch intracellular domain undergoes ubiquitilation. Proteolytic processing of the Notch precursor protein by furin-protease and its trafficking to the cell membrane also determine turnover and availability of receptors, and, in turn, activation of this signaling pathway. Altered glycosylation of the Notch extracellular domain by Fringe protein family members may also modify efficiency of ligand binding.
Notch Signaling and Macrophage Activation
The Notch pathway contributes to biological processes during development and to disease mechanisms in adults (Bray, et al., Nat. Rev. Mol. Cell. Biol. 7:678-689 (2006); Artavanis-Tsakonas, et al., Science 284:770-776 (1999)). Direct cell-to-cell contract via the binding of a ligand to a Notch receptor, both of which are expressed on the cell surface, triggers downstream responses (Thurston, et al., Nat. Rev. Cancer 7:327-331 (2007)). We previously demonstrated that Dll4-mediated Notch signaling promotes macrophage activation (Fung, et al., Circulation 115:2948-2956 (2007); Fukuda, et al., Proc. Nat'l Acad. Sci. USA 109:E1868-1877 (2012)). Clinical and preclinical evidence has established the causal role of macrophages in arterial atherosclerosis (Aikawa, et al., Cardiovasc. Pathol. 13:125-138 (2004); Moore, et al., Nat. Rev. Immunol. 13:709-721 (2013)). Failing vein grafts also tend to contain macrophages (Fowkes, et al., Lancet 382:1329-1340 (2013)) but their role in the disease progression remains unclear.
Vein Graft Failure
Vein graft failure is a global health burden with no effective medical solutions (Owens, et al., Vasc. Med. 13:63-74 (2008)). Due to the pandemic of atherosclerotic peripheral artery disease (PAD) and the growing prevalence of underlying metabolic disorders (Fowkes, et al., Lancet 382:1329-1340 (2013)) the incidence of vein graft failure is rising. Although many mechanisms for arterial diseases have been established, the pathogenesis of vein graft failure remains incompletely understood. Autologous saphenous vein grafts (SVGs) are widely used for PAD because they remain patent longer than artificial conduits (Twine, et al., Cochrane Database Syst. Rev. CD001487 (2010)). Approximately 50% of lower extremity SVGs, however, become occluded or narrowed within a year (Conte, et al., J. Vasc. Surg. 43:742-751 (2006). When PAD grafts fail, the only available therapeutic options are devastating limb amputation or invasive and expensive angioplasty or surgical revascularization. Coronary artery SVGs also fail at high rates (Fitzgibbon, J. Am. Coll. Cardiol. 28:616-626 (1996)). Although current therapies such as statins can reduce the onset of complications of arterial diseases (e.g., myocardial infarction) (Libby, et al., Nat. Med. 8:1257-1262 (2002)), no effective medical solutions are available for vein graft failure.

Notch inhibition in the prevention of vein graft failure


A method and an associated apparatus for cleaning an inner wall of a mold part includes forming a chamber between displaced mold parts by introducing a casing between the mold parts. The casing enclosures a blasting device for introducing a blasting nozzle which directs a cleaning jet at the inner wall. The chamber encapsulates noise and particles which are produced during the cleaning process.

1. Field of the Invention
The subject matter of the invention includes a method and an apparatus for cleaning an inner wall of a mold. In particular, the present invention includes a method and apparatus for cleaning an inner wall of a mold for producing vehicle tires, by means of dry-ice pellets.
2. Related Art
An extremely wide range of cleaning methods are known for the purpose of cleaning metallic components. The cleaning methods may be subdivided into physical and/or chemical cleaning methods. The chemical cleaning methods are based on the particles of dirt which adhere to the component being subjected to a chemical reaction by the action of a cleaning agent and being detached from the component as a result. Special apparatuses, which are complex and very expensive, are necessary for carrying out chemical cleaning. As a result of the generally aggressive cleaning media, only high-quality, chemically resistant materials can be used in such cleaning apparatuses. Cleaning apparatuses which operate on a chemical basis are also subject to stringent legal regulations which can only be met by considerable outlay on equipment.
As an alternative to chemical cleaning, components may be cleaned by physical methods. In this case, the contaminants are removed mechanically from the component by abrasion. Abrasive media may be used for removing contaminants from a component. Abrasive media may be in the form of sand, cork or glass. Probably best-known method of mechanically removing contaminants from a component is the so-called sand-blasting method. Sand blasting is preferably carried out in separate chambers, in which the component is introduced and blasted by a sand-blasting device.
DE 43 14 264 C1 discloses a sand-blasting device which is suitable for cleaning rims of motor-vehicle wheels. The motor-vehicle rim which is to be cleaned is arranged in a housing, the base of which is of funnel-like design. The funnel-like base of the housing is connected to a sand-collecting area by a connecting duct. The sand-collecting area is connected to the sand-blasting device via a sand-feed line. The sand-blasting device may be located in the housing. According to DE 43 14 264 C1, it is possible for only the front, nozzle-like end of the sand-blasting device to project into the housing. This configuration of the apparatus for cleaning rim of motor-vehicle wheels minimizes the sand consumption since the cleaning sand runs around in a closed circuit.
In addition, U.S. Pat. No. 4,603,515 discloses a means for removing a layer of corrosion from the walls of the booster of a bomb. The layer of corrosion is removed by sand blasting. In order to remove the sand from the shell of the bomb, a vacuum means is provided.
Sand-blasted components subsequently have to be subjected to careful cleaning in order to ensure that the fine sand is removed from all possible niches of the component. The use of sand blasting for cleaning molds, in particular molds for producing plastic parts, is very costly because of the relatively high cost outlay for cleaning, which is necessary in order to remove the sand from all possible niches of the mold. The possible ways of cleaning components which have been described above require that the component which is to be cleaned is provided separately. In the case of molds of plastic-processing machines or molds for producing vehicle tires, then it is necessary for the mold to be removed from the machine. Once the cleaning operation has been carried out, the machine has to be set up anew. This procedure for cleaning molds is costly and results in the operating time of the machine being reduced considerably.
In order to avoid the removal and reinstallation of a mold, it is also known for such molds to be cleaned manually. This method of cleaning is hazardous to the personnel carrying out the cleaning since aerosols are produced during the cleaning operation, which may have an adverse effect on health if suitable protective measures are not provided for the personnel. In addition, cleaning of the inner wall of the mold can be difficult due to a multiplicity of narrow and short depressions.
It is also known for components to be cleaned by means of dry-ice pellets. Dry ice is carbon dioxide which has been converted into the solid physical state. Under atmospheric pressure, dry ice changes directly from the solid physical state into the gaseous state without any melt liquid being produced. Cleaning with dry ice thus has the advantage that no residues of the dry ice remain in the mold. With the aid of a carrier medium, e.g. air or nitrogen, the dry-ice pellets are blasted, via a cleaning nozzle, against the component which is to be cleaned. The pellets remove the contaminants from the wall of a component. The mechanical removal of the contaminants is assisted by the refrigerating action of the dry ice, which is at a temperature of at least -78.5.degree. C. During cleaning there is a high emission of sound. The source of the sound emission is the cleaning nozzle, through which the cleaning jet which contains dry-ice pellets emerges. A reduction in the sound emission at the cleaning nozzle has been achieved by a further development of the cleaning nozzle. However, the sound emission is still of such a magnitude that cleaning of a component can only be carried out if costly sound-insulation measures are taken.

Apparatus for cleaning an inner wall of a mold

L'Air Liquide, Societe Anonyme pour E'tude et l'Exploitation des Procedes Georges Claude


A lens barrel attachment including an attachment ring and a handle in which a click pin is housed. The attachment ring is rotatably fitted on a large-sized lens barrel. The handle is threadingly fitted in a handle hole formed in the attachment ring and extending in a radial direction thereof. The click pin is provided in an accommodation hole formed in the handle and urged by a spring to be engaged with engaging recesses formed on an outer surface of the lens barrel. The handle has a contact portion at the tip portion thereof. This contact portion is brought into frictional contact with the lens barrel to thereby fix the lens barrel to the attachment ring.

1. Field of the Invention
The present invention relates to a lens barrel attachment for attaching a lens barrel, especially a large-size lens barrel, to a tripod.
2. Description of the Related Art
Conventionally, a large-size lens barrel is attached to a tripod by a lens barrel attachment provided with an attachment ring having a tripod mount connected to the tripod and rotatably fitted on an outer surface of the lens barrel. Namely, the lens barrel and a camera to which the lens barrel is mounted are rotated relative to the attachment ring. Thus the posture of the camera can be changed vertically or horizontally.
This conventional lens barrel attachment is provided with a lock mechanism for locking the lens barrel and the lens barrel attachment at a predetermined position, and a click mechanism for fixing the camera when moving same vertically or horizontally. These mechanisms, however, are bulky and have a complicated structure.