The present invention provides a program control system comprises plural programs each of which includes an instruction to execute a process corresponding to each of plural statuses of the system, a program memory for storing the plural programs, a program counter for outputting an address of the memory at which a part of the plural programs to be executed is stored, the address including a flag which indicates one of the plural statuses, and execution means for reading one of the programs from the program memory in accordance with the address output by the program counter and executing the read program.

1. Field of the Invention
The present invention relates to a program control system which executes plural processes by switching according to the status.
2. Discussion of the Related Art
Conventionally, a CPU has executed process switching according to the status (or, referred to as Context Switch) by interrupt or branch instruction. FIG. 7 is a schematic view showing an ordinary CPU system. In the figure, a CPU is indicated by 41, a memory is indicated by 42, an address bus is indicated by 43, a data bus is indicated by 44, a data bus buffer is indicated by 51, an internal data bus is indicated by 52, a control signal I/O interface is indicated by 53, an instruction register is indicated by 54, an operation part (or arithmetic and logic unit, hereinafter referred to as ALU) is indicated by 55, a program status word (hereinafter, referred to as PSW) is indicated by 56, a register is indicated by 57, an instruction decoder is indicated by 58, a controller is indicated by 59, a program counter (PC) is indicated by 60, an address bus buffer is indicated by 61 and an internal address bus is indicated by 62.
The CPU 41 reads one of programs stored in the memory 42 and operates in accordance with the read content. The counter 60 specifies a position of storing the program, namely, an address. The CPU 41 outputs a value of the program counter 60 to the address bus 43 through the internal address bus 62 and the address buffer 61, for reading the contents of the memory 42. The contents, namely, the instructions are provided to the instruction register 54 through the data bus 44, the data bus buffer 51 and the internal data bus 52. A cycle of reading an instruction to be executed, as described above, is called a fetch cycle.
The instruction provided to the instruction register 54 by the fetch cycle is interpreted by the instruction decoder 58 to execute operation in accordance with the instruction, reading or writing the data from/to the memory, transfer to the I/O interface 53 or the like through the controller 59. At this time, carrying out of the operation is executed by the ALU 55, and operand or the result of operation is stacked in the register 57. Moreover, a flag indicating the status of the result of operation is stacked in the PSW 56. FIG. 8 illustrates an example of the PSW, which shows four flags. The flag N is set to 1 when the result of the operation is negative, otherwise it is set to 0. The flag Z is set to 1 when the result of operation is 0, and when the result of operation is other than 0, it is set to 0. The flag V is set to 1 when the operation causes overflow, and set to 0 when the operation causes no overflow. The flag C is set to 1 when the carry is generated in the operation, otherwise set to 0. There is, of course, a case where other flags are set in the PSW 56. A cycle executing various processes in accordance with the instruction read by the fetch cycle, as described above, is called an execution cycle. A register held inside of the CPU 41 frequently used for stacking data, such as the register 57 or the PSW 56, is called a system register. The CPU 41 basically repeats the fetch cycle and the execution cycle alternately.
Only if an external request of execution of other process is made, that is, an interrupt is made, the system proceeds to an interrupt processing cycle after the execution cycle. In FIG. 7, the interrupt is input through the control signal I/O interface 53. FIG. 9 is a flow chart showing a procedure of an ordinary interrupt process. In the figure, it is assumed that a process prior to the interrupt is process #1 and a process executed by the interrupt is process #2. In process #1, which is prior to the interrupt, the instruction fetch cycle in step 71 and the instruction execution cycle in step 72 are alternately repeated as described above. When the interrupt occurs, it is detected in step 73 and the system moves to the interrupt processing cycle.
In the interrupt processing cycle, values of the PSW 56 and the program counter 60 are first stacked in steps 74 and 75, and then the contents of the program counter 60 is changed in step 76. The address to be changed is determined in accordance with the type of the interrupt signal. At the branching destination address of the interrupt process, an interrupt processing program is located. In process #2, which is the interrupt processing program, the instruction fetch cycle in step 77 and the instruction execution cycle in step 78 are alternately repeated as same as process #1. At the end of the interrupt processing program, the system proceeds to steps 79 and 80, and further in steps 80 and 81, the values of the PSW 56 and the program counter 60 are restored to the former values, whereby the process returns to process #1 at the time when the interrupt occurs. This kind of ordinary interrupt operation is described in various references, such as "Transistor Technology", CQ publishing company, Vol. 6, 1991, pp. 456-458.
Other than the interrupt process, it is also possible to switch to the other process which is under execution. In this case, a branch instruction is used. FIG. 10 is a flow chart showing a procedure of processing an ordinary branch instruction and is indicating a case where process #1 branches into process #2. As described above, the instruction fetch cycle and the instruction execution cycle are alternately repeated in process #1. Steps 91 and 92 indicate fetch and execution, respectively, on the instruction prior to the branch instruction. If the process is changed by the branch instruction, a processing result or change of the external status, which is the condition of changing, is reflected in the PSW 56. The CPU 41 fetches the branch instruction in step 93, reads the status stored in the PSW 56 in step 94, and determines whether the status satisfies the branch condition in step 95. If the status does not satisfy the branch condition, fetch and execution of next instruction in process #1 are continued without branching as shown in steps 96 and 97. If the read status satisfies the branch condition, the value of the program counter 60 is changed to the specified address in step 98 to switch the process. Then, as shown in steps 99 and 100, fetch and execution of the instruction in process #2 are alternately repeated. The procedure of processing of such branch instruction is also described in various references, such as, the above-described "Transistor Technology"CQ publishing company, Vol. 6, 1991, pp. 448-449.
If it is required that the plural processes are executed by switching appropriately in accordance with the process result, change of the external status or external request with high-speed or in real time, there occur the following problems in process switching by interrupt or branch instruction in the CPU.
In the case of interrupt, processes of stacking in the PSW and the program counter, and changing of the program counter are carried out within the period of switching from one process to another (long interrupt). These processes cause overhead which cannot be ignored if quick operation for process switching is required. For example, as noted in "M68000 Microprocessor User's Manual", Motorola Inc., CQ Publishing Company, Appendix D, page 189, MC68000 requires 44 clocks during the period from accepting the interrupt to fetching the first instruction of the interrupt processing routine. In the case of the process which does not require stacking in the register such as the PSW (short interrupt), it is possible to reduce or delete the stacking operation, but the process of changing the program counter is still necessary, and is left as the overhead in process switching.
In the case of process switching according to the branch instruction, execution of the branch instruction itself, that is, reading the PSW, condition determination and changing the program counter, is necessary, and results in the overhead which cannot be ignored as same as the case of the interrupt process. In the case of MC68000 described above, 8 clocks or more are required even in the case of jump instruction without condition determination. The branch instructions must be located on the points having potentiality of occurrence of process changing in the program.
As described above, if the process switching is carried out by interrupt or branch instruction in the CPU, the overhead necessarily occurs in switching. The delay in processing caused by the overhead comes into problem if the process is desired to be executed at high-speed or in real time.
FIG. 6 illustrates an example of a process flow. The problem described above is now illustrated by taking the process flow shown in FIG. 6 as an example. In the process flow, the system repeats process 0 as a normal procedure. If request S is made, the system moves to process 1. If request T is made and request S is not made, the system moves to process 7. After execution of process 2, if zero (Z) status is 1, the system moves to process 3, and if it is 0, the system moves to process 5. Other movements are made unconditionally after execution of each process.
If the process flow is carried out by the conventional CPU, the interrupt process is needed to move from process 0 to process 1 or 7, and the branch instruction is needed to move from process 2 to process 3 or 5. Consequently, the overhead occurs on the point of interrupt or branch instruction for process switching, which may hinder the switching in real time, for example.


Provided are extrusion dies having entrance, orientation, merging (205), and exit (211) sections, which dies may be used to produce fibers having, e.g., oriented reinforcement materials (e.g., PTFE) dispersed within. The dies provide fibers having enhanced mechanical and processing properties. The orientation section comprises orientation channels (203) wherein a ratio of a cross-sectional area having of the channel inlet to a cross-sectional area of the channel outlet is between 2 and 45.

Efforts have been made in forming high-performance polymer fibers, but these efforts have not always yielded fibers having the optimal blend of mechanical properties and processability. Some of these efforts have included attempts to utilize fibrillated materials, but these attempts have met with only limited success. Accordingly, there is a long-felt need in the art for improved dies and related methods for forming improved fiber materials.


The system for transmitting and receiving a wideband speech signal includes an A/D converter for receiving an analog speech signal to convert it into a digital speech signal, a transmitter analysis filter for receiving the digital speech signal and dividing it into a baseband signal and an enhancement residual band signal, a standard baseband encoder for accepting the baseband signal and coding it using an ITU-T encoder, an additional baseband encoder for reducing standard coding distortion in the baseband signal, an enhancement residual band encoder for coding a signal obtained by removing the coded baseband signal from the original digital speech signal, and an IP network interface for multiplexing the coded standard and additional baseband signals and enhancement residual band signal.

(a) Field of the Invention
The present invention generally relates to a system and method for transmitting and receiving wideband speech signals.
(b) Description of the Related Art
A wideband speech signal has a frequency of 0˜8 kHz, which is twice that of a currently used telephone-line band, at 0˜4 kHz. The wideband speech signal is suitable for a next-generation speech communication system because it is less artificial than a signal of the telephone-line band, and has high intelligibility.
The G.711 is one of the methods of digitalizing and compressing a speech signal of the telephone-line band, which has been standardized by ITU-T (International Telecommunication Union-Telecommunication Standardization sector) for the first time. G.711 uses nonlinear pulse code modulation (u/A-PCM), and it is known that its performance is similar to the original speech signal at 64 kbit/s. Other speech compression methods standardized by ITU-T include G.726 (adaptive differential pulse code modulation, ADPCM, 32 kbit/s), G.728 (low delay code excited linear prediction, LD-CELP, 16 kbit/s), G.729 (conjugate structure algebraic code excited linear prediction, CS-ACELP, 8 kbit/s), and G.723.1 (ACELP/MP-MLQ, 5.3/6.3 kbit/s).
Among ITU-T standard speech coders, G.723.1 and G.729 were adopted as a VoIP (Voice over Internet Protocol) standard coder on the Internet. G.723.1, developed for the purpose of compressing multimedia signals at a low rate, is an algorithm capable of compressing and decompressing input speech at two bit rates of 5.3 kbit/s and 6.3 kbit/s. G.723.1 uses the analysis-by-synthesis method, which has the widest application field among speech coding methods, and provides toll quality as high as that of a wired network. ITU-T G.729 is an algorithm capable of compressing and decompressing input speech at the rate of 8 kbit/s using an algebraic codebook, and it also provides toll quality as high as that of the wired network. Furthermore, ITU-T G.729A (G.729 Annex A) has the same transmission parameter as that of G.729 so it has compatibility with G.729 and it has advantages in complexity. Accordingly, G.729A is widely used in actual systems.
The above-described speech coding methods or systems with low transmission rates that provide toll quality as high as that of wired networks have created new services in mobile communications and Internet phone services. In particular, VoIP on the Internet is being spread very rapidly due to inexpensive telephone charges. However, the aforementioned conventional coding methods or systems have had poor service quality because of low quality and long delay time caused by packet loss on the Internet. With the development of communication networks and protocols, however, most of the problems in the conventional coding methods or systems with respect to delay time generated on networks have been solved. Recently, attempts to extend a speech signal to a wideband signal having a frequency (0˜8 kHz) twice that of telephone-line band (0˜4 kHz) to improve toll quality have been made. However, the 16 kHz wideband speech codec, which has been already standardized, has no backward compatibility with the telephone-line band codec currently being used for VoIP services so a new communication system must be designed in order to use signals of the two different systems. Furthermore, since the wideband signal occupies a wide bandwidth, a network capable of processing a large amount of data is needed. Accordingly, there are many problems in providing new services with the current systems.

System and method for transmitting and receiving wideband speech signals

Electronics and Telecommunications Research Institute


A power consumption controller controls the power consumption of a physical server having a virtual server. A management server determines an unused CPU budget from the difference between the total amount of the loads of respective virtual servers and a hypervisor and the total CPU budget of the physical server. The management server determines the drive frequency of the CPU inside the physical server based on the unused CPU budget. The management server changes a CPU allocation budget related to the respective virtual servers and the hypervisor in accordance with the determined drive frequency. The hypervisor controls the CPU allocation budget and drive frequency in accordance with an indication from the management server.

1. Field of the Invention
The present invention relates to a server power consumption controller, and a method and computer program for controlling the power consumption of a server.
2. Description of the Related Art
A CPU (Central Processing Unit) mounted in a server computer (hereinafter the server), for example, is used for running an operating system (OS), an application program and so forth. To improve the processing efficiency of the server, the tendency from year to year has been to increase the number of CPUs mounted in the server.
In the meantime, the amount of power consumed by the server has also been increasing year by year. For example, there have been cases in which the total power consumption of the entire information processing system in a data center or other such system having large numbers of servers has increased beyond the allowable power capacity of the facility. Thus, the problem is that not only are electricity costs increasing, but also that the number of installed servers is being restricted.
Of a server's various hardware components, the CPU consumes the most power by far. Therefore, the power consumption of the server will increase in line with increasing the number and operating frequencies of the CPUs mounted in the server.
Further, the practice of integrating a plurality of processor cores into a single CPU, the so-called multiple core CPU, to enhance processing performance by executing a large number of programs in parallel is also progressing. The larger the number of cores inside the CPU, the greater the power consumption of the CPU.
Furthermore, since higher power consumption increases the load on the power source device, the life of the power source device or the like may be shortened.
Accordingly, to reduce the power consumption of the server, technologies for reducing the frequency of the CPU have been proposed (U.S. Pat. Nos. 6,845,456, 7,080,267 and 7,155,617). In these prior arts, power consumption and heat generation are lowered by forcibly reducing the CPU operating frequency and supply voltage when the CPU is idling or under a low load.
Now then, technology for disposing either one or a plurality of virtual servers on top of a single physical server is known. The technology, for example, is called server virtualization technology. The respective virtual servers can independently run their own separate OS. Server virtualization technology proportionally allocates the various types of computer resources of the physical server, such as the processor, memory, and disk device, to each of the virtual servers. Consequently, it is possible to make efficient use of the limited computer resources of the physical server.
A hypervisor running on the physical server is in charge of computer resource allocation and virtual server scheduling. The creation and deletion of a virtual server is implemented by the user (this includes the administrator; the same holds true hereinbelow) issuing an indication to the hypervisor. A virtual server is created by reserving computer resources and allocating these resources to the virtual server. This virtual server is deleted by releasing the computer resources that have been allocated to the virtual server.
The prior art disclosed in the above-mentioned Patent Documents makes it possible to reduce power consumption by lowering the frequency of the CPU. However, the prior art cannot be applied as-is to a physical server having either one or a plurality of virtual servers. That is, under a virtual server environment, simply using the prior art as-is does not make it possible to reduce power consumption without also lowering the functionality of the virtual server.
One problem has to do with the timing at which the frequency is lowered. Under a virtual server environment, a plurality of virtual servers may share a single CPU, and in this case, a plurality of virtual servers can be operated simultaneously using the same CPU.
Therefore, if the operating frequency of the CPU is lowered while one virtual server is in the idle state, the processing performance of the other virtual server sharing the CPU will also be lowered at the same time.
One other problem is the fact that lowering the operating frequency of the CPU also lowers the performance of the hypervisor that manages the virtual server. To make a virtual server environment functional requires a hypervisor for carrying out the dispatch processing and resource allocation processing for operating the respective virtual servers. Therefore, lowering the operating frequency of the CPU being used by the hypervisor not only impacts the virtual servers sharing the CPU, but also affects the operation of the hypervisor, thereby lowering the performance of the virtual servers as a whole.

Server power consumption controller, and method and computer program for controlling server power consumption

Abstract: Accordingly, the power consumption of the physical server is controlled.


A conveyor, comprising a conveyor frame having a pair of spaced side members each having a plurality of mounting means to mount a plurality of rollers in spaced relation between the side members, each roller being provided with a bearing means having a socket, the rollers being mounted in spaced relation between said pair of side members on stub spindles, each stub spindle having a support portion which inter-engages with a mounting means non-rotatably to mount the stub spindles on the side members, there being a pair of opposed stub spindles for each roller and each stub spindle having an end portion which is received in a socket provided at each end of the roller to permit each roller to rotate about a roller axis and wherein at least at one end of each roller the support portion and the mounting means are configured for inter-engagement by relative movement therebetween transverse to said roller axis characterised in that each stub spindle is provided with retaining means to retain the end portion of the stub spindle in the socket in which it is received.

This invention relates to a conveyor, hereinafter referred to as being of the kind specified, comprising a conveyor frame having a pair of spaced side members each having a plurality of mounting means to mount a plurality of rollers in spaced relation between the side members, each roller being provided with a bearing means having a socket, the rollers being mounted in spaced relation between said pair of side members on stub spindles, each stub spindle having a support portion which inter-engages with a mounting means non-rotatably to mount the stub spindles on the side members, there being a pair of opposed stub spindles for each roller and each stub spindle having an end portion which is received in a socket provided at each end of the roller to permit each roller to rotate about a roller axis and wherein at least at one end of each roller the support portion and the mounting means are configured for inter-engagement by relative movement therebetween transverse to said roller axis.
Such a conveyor is disclosed in EP-A-0621219 but requires, on site, stub spindles to be engaged in the sockets at opposite ends of each conveyor roller and the resultant combination of roller and two stub spindles be held together manually and then the stub spindles manipulated into the side members. This results in time, expense and inconvenience in assembly.
In a conveyor of the type specified, the rollers may be free running or driven. Articles may be placed directly on the conveyor rollers or on an endless conveyor belt which extends around the rollers to provide a greater support area for articles in a known manner. Such conveyors may extend horizontally or may be inclined.


Disclosed is a battery module capable of ensuring safety in use by breaking a bus bar when an overcurrent flows at the battery module. The battery module includes at least one unit cell, a case for accommodating the unit cell, and a bus bar electrically connected to the unit cell, wherein the bus bar includes a first metal plate, a second metal plate spaced apart from the first metal plate, and a metal bridge configured to connect the first metal plate and the second metal plate and having a lower melting point than the metal plate.

As portable electric products such as video cameras, portable phones and portable PC are more actively used, the importance of a secondary battery generally used as a driving source of such a portable electric product is increasing.
Different from a primary battery which may not be charged, a secondary battery allows charging and discharging and is actively studied in high-tech industries such as digital cameras, cellular phones, laptop computers, power tools, electric bicycles, electric vehicles, hybrid vehicles, mass-capacity power storage device or the like.
In particular, the use of a lithium secondary battery is gaining since it has a high energy density per unit weight and allows rapid charging in comparison to other existing secondary batteries such as lead storage batteries, nickel-cadmium batteries, nickel-hydrogen batteries, nickel-zinc batteries or the like.
The lithium secondary battery has an operating voltage of 3.6V or above and is used as a power source of a portable electronic device. In other cases, a plurality of batteries are connected in series or in parallel and used for high-power electric vehicles, hybrid vehicles, power tools, electric bicycles, power storage devices, UPS or the like.
The lithium secondary battery has a triple operating voltage in comparison to nickel-cadmium batteries or nickel-metal hydride batteries and is used more and more due to its high energy density per unit weight.
Depending on the kind of electrolyte, a lithium secondary battery may be classified into a lithium ion battery using a liquid electrolyte and a lithium ion polymer battery using a solid electrolyte. In addition, depending on the kind of polymer solid electrolyte, the lithium ion polymer battery may be classified into an all solid lithium ion polymer battery containing no electrolyte and a lithium ion polymer battery using a gel-type polymer electrolyte containing an electrolyte.
Lithium ion batteries using a liquid electrolyte mostly use a cylindrical or rectangular metal can as a container and are sealed therein by welding. A can type secondary battery using such a metal can as a container has a fixed shape and thus limits the design of an electric product which uses the battery as a power source. In addition, it is difficult to decrease the volume of the product. Therefore, a pouch type secondary battery prepared by putting an electrode assembly and an electrolyte into a pouch package made of a film and then sealing the same has been developed and used.
However, the lithium secondary battery may explode when being overheated, and so issues of ensuring safety is of major concern. The lithium secondary battery may be overheated due to various factors, of which an example is a case in which an overcurrent exceeding a limit flows through the lithium secondary battery. If an overcurrent flows, the lithium secondary battery generates Joule's heat and thus an internal temperature of the battery rapidly increases. In addition, the rapid increase of temperature causes a decomposition reaction of the electrolyte and thermal runaway, which may lead to explosion of the battery. An overcurrent may occur when a sharp metallic matter pierces the lithium secondary battery, when an insulation between a cathode and an anode breaks due to the shrinkage of a separator interposed between the cathode and the anode, when a rush current is applied to the battery due to an abnormal charging circuit or a load connected to the outside, or the like.
Therefore, the lithium secondary battery is coupled to a protection circuit in order to protect the battery against abnormal states such as the occurrence of an overcurrent. The protection circuit generally includes a fuse element which irreversibly disconnects a line where a charging or discharging current flows when an overcurrent occurs.
FIG. 1 is a circuit diagram for illustrating an arrangement and an operating mechanism of a fuse element employed in a protection circuit coupled to a battery module which includes a lithium secondary battery.
As shown in FIG. 1, a protection circuit includes a fuse element 1, a sense resistor 20 for sensing an overcurrent, a microcontroller 30 for monitoring an occurrence of an overcurrent and operating the fuse element 10 when an overcurrent occurs, and a switch 40 for switching the flow of an operating current to the fuse element 10 in order to protect a battery module when an overcurrent occurs.
The fuse element 10 is installed to a main line connected to the outermost terminal of the battery module. The main line represents a wire through which a charging current or a discharging current flows. In FIG. 1, it is depicted that the fuse element 10 is installed at a high potential line (Pack+).
The fuse element 10 is a three-terminal element, in which two terminals are connected to the main line through which a charging or discharging current flows and one terminal is connected to the switch 40. In addition, the fuse element includes a fuse 11 connected to the main line in series and disconnected at a specific temperature and a resistor 12 for applying heat to the fuse 11.
The microcontroller 30 monitors the occurrence of an overcurrent by periodically detecting voltages at both ends of the sense resistor 20, and turns on the switch 40 if it is determined that an overcurrent occurs. In this case, the current flowing through the main line flows to the fuse element 10 by bypassing and is applied to the resistor 12. Accordingly, the Joule's heat generated at the resistor 12 is conducted to the fuse 1a to raise the temperature of the fuse 11. If the temperature of the fuse 11 increases to a melting temperature, the fuse 11 is fused to irreversibly cut the main line. If the main line is cut, the overcurrent does not flow any more, which solves problems caused from the overcurrent.
However, the above techniques have several problems. For example, if the microcontroller 30 malfunctions, even though an overcurrent occurs, the switch 40 does not turn on. In this case, a current is not applied to the resistor 12 of the fuse element 10, and therefore the fuse element 10 does not operate. In addition, a space for disposing the fuse element 10 should be separately provided in the protection circuit, and a program algorithm for controlling operations of the fuse element 10 should be loaded on the microcontroller 30. Therefore, the spatial efficiency of the protection circuit deteriorates, and the load of the microcontroller 30 increases.

Battery module and bus bar applied to battery module


A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.

This invention is in the field of integrated circuit electrical testing. Embodiments of this invention are more specifically directed to the screening of ferroelectric memory cells that are potentially of weak long term reliability.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example placing capacitors above the transistor level, between overlying levels of metal conductors.
Ferroelectric technology is now utilized in non-volatile solid-state read/write random access memory (RAM) devices. These memory devices, commonly referred to as "ferroelectric RAM", or "FeRAM", or "FRAM" devices, are now commonplace in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers, defibrillators, and monitoring devices, due to the ultra-low power consumption of FRAM memory. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T-2C (two transistor, two capacitor) cells in which the two ferroelectric capacitors in a cell are polarized to complementary states. Another type of FRAM cell is based on the well-known "6T" CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors. Ferroelectric cells constructed in a 1T-1C (one transistor, one capacitor) arrangement, similar to conventional dynamic RAM memory cells, are attractive because of their small chip area, but at a cost of less robust read performance than the larger area 2T-2C and 6T cell types.
FIG. 1a illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a "coercive" voltage +Vα, the capacitor polarizes into the "+1" state. According to this characteristic, once polarized to the "+1" state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the "−1" state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance exhibited by a ferroelectric capacitor between its polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. While the ferroelectric capacitor has a linear capacitance, by virtue of its construction as parallel plates separated by a dielectric film (i.e., the ferroelectric material), it also exhibits significant polarization capacitance (i.e., charge storage) in response to changes in polarization state that occurs upon application of a polarizing voltage. For example, referring to FIG. 1a, the polarization of a ferroelectric capacitor from its "−1" state to its "+1" state is reflected in a relatively high capacitance C(−1), reflecting the storage of polarization charge in the capacitor in response to the change of polarization state by the voltage exceeding coercive voltage Vα. On the other hand, a capacitor that already in its "+1" state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned in the direction of the applied coercive voltage, causing little additional polarization charge to be stored. As will be evident from the following description, a stored logic state is read by interrogating the capacitance of the ferroelectric capacitors to discern its polarization state.
FIG. 1b illustrates, in cross-section, a typical construction of a portion of an integrated circuit including a ferroelectric capacitor and an n-channel metal-oxide-semiconductor (MOS) transistor. In this arrangement, a MOS transistor is realized at the surface of p-type substrate 10 (or well), at an active region disposed between isolation dielectric structures 15 formed by shallow trench isolation in this example. N+ source/drain regions 14 are formed into substrate 10 on opposing sides of polysilicon gate element 16 in a self-aligned manner. Gate element 16 is separated from the surface of the active region by gate dielectric 17, thus forming the transistor. Sidewall spacers 19 on the sides of gate element 16 are useful in forming source/drain region extensions, as known in the art. A ferroelectric capacitor is formed in this structure by a ferroelectric stack including conductive plates 20a, 20b (formed of an elemental metal, or a conductive metal compound such as a metal nitride, conductive metal oxide, or a silicide, or a stack of two or more of these layers) between which ferroelectric material 22 is disposed. In this example, ferroelectric material 22 consists of PZT. Bottom conductive plate 20a is connected to the source/drain region 14 by conductive plug 18 formed into a contact opening etched through dielectric film 13. As typical in conventional process flows, passivation films 24, 25, 26 (e.g., of aluminum oxide, silicon nitride formed by high-density plasma, and CVD silicon nitride, respectively) are deposited over the ferroelectric capacitor structure to minimize hydrogen contamination of ferroelectric material 22.
FIG. 2a illustrates a typical arrangement of a conventional 1T-1C FRAM cell 2jk, which represents a single memory cell residing in a row j and a column k of an array of similar cells 2. Cell 2jk includes n-channel pass transistor 4 and ferroelectric capacitor 6. The source/drain path of transistor 4 is connected between bit line BLk for column k of the array, and the top plate of ferroelectric capacitor 6; the gate of transistor 4 is controlled by word line WLj for row j of the array. The bottom plate of ferroelectric capacitor 6 is connected to plate line PL, which may be in common for all cells 2 in the array (or in a particular portion of the array, depending on the architecture). Those skilled in the art will recognize that 1T-1C FRAM cells are constructed similarly as conventional dynamic RAM memory cells.
FIG. 2b illustrates the arrangement of cell 2jk of FIG. 2a within an FRAM device, particularly in the read context. In this example, sense amplifier 8 is coupled to bit line BLk, and operates to compare the bit line voltage developed by read current iR to a reference voltage VREF generated by reference voltage generator circuit 9. As typical in the art for 1T-1C memory cells, the polarization state that exhibits the higher capacitance when sensed, which in this case is the "−1" polarization state, will be considered as the "1" data state, and the lower capacitance "+1" polarization state will be considered as the "0" data state. Cell 2jk is written by applying voltages to plate line PL and bit line BLk that, with word line WLj energized, polarizes capacitor 6 into the desired polarization state. In this example, a "0" data state corresponding to the "+1" polarization state of FIG. 1 is written by the application of a low voltage (Vss) to bit line BLk, turning on word line WLj, and then raising plate line PL to a high voltage (Vcc). Conversely, a "1" data state corresponding to the "−1" polarization state is written by the application of a low voltage (Vss) to plate line PL, turning on word line WLj, and then raising bit line BLk to a high voltage (Vcc).
The read operation of cell 2jk begins with the precharging of bit line BLk to a low voltage (e.g., Vss). As shown in FIG. 2c, once bit line BLk is precharged, word line WLj is energized to turn on transistor 4 and couple capacitor 6 to bit line BLk. The voltage of plate line PL from the low voltage Vss is then raised to the high voltage Vcc to interrogate the polarization capacitance of capacitor 6, according to the hysteresis diagram of FIG. 1. Specifically, the energizing of plate line PL induces a read current iR onto bit line BLk to develop a voltage on bit line BLk. As known in the art, the voltage level developed on bit line BLk depends on the capacitance exhibited by ferroelectric capacitor 6 in cell 2jk relative to the bit line capacitance. If capacitor 6 is in the "+1" polarization state, the read current iR will be relatively low and will thus develop a relatively low level bit line voltage V(0) as shown in FIG. 2c. Conversely, the "−1" polarization state of capacitor 6 will result in a relatively strong read current iR, and a higher level voltage V(1) at bit line BLk.
According to an "after-pulse sensing" approach as shown in FIG. 2c, sense amplifier 8 is activated at time tSA_ap, after the plate line PL pulse, at which time sense amplifier 8 compares the bit line voltage with the reference voltage VREF from reference voltage generator 9. To discern the stored data state, reference voltage VREF is set to a voltage between the expected low and high data state levels V(0), V(1), respectively (i.e., within the window ΔV of FIG. 2b). Following time tSA_ap, sense amplifier 8 drives bit line BLk to a full logic "1" level in response to detecting the higher bit line voltage V(1), and to a full logic "0" level in response to detecting the lower bit line voltage V(0), as shown in FIG. 2c. Another sensing approach, referred to as "on-pulse" sensing may alternatively be used; in this approach, sense amplifier 8 is activated during the plate line pulse, for example at time tSA_op as shown in FIG. 2c.
By way of further background, copending and commonly assigned U.S. Patent Application Publication US 2015/0357050, incorporated herein by reference, describes a data retention reliability screen of FRAM cells in which a reference voltage level for the read of a high polarization capacitance data state (e.g., a "1" state) is determined for each integrated circuit being tested. A number of FRAM cells in the integrated circuit are programmed to the "1" data state, and then read at an elevated temperature. The number of failing cells is compared against a pass/fail threshold to determine whether that integrated circuit is vulnerable to long-term data retention failure.
By way of further background, copending and commonly assigned U.S. application Ser. No. 14/857,873, filed Sep. 18, 2015 and incorporated herein by reference, describes a data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM), in which sampled groups of the memory cells are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
Another type of cell failure referred to as a "stuck bit" has been observed in modern 1T-1C ferroelectric memory cells. In the arrangement of cell 2jk described above relative to FIGS. 2a and 2b, these stuck bit failures are exhibited by cells that return a "1" data state regardless of their programmed state. Stated another way, a stuck cell is exhibited by an instance of cell 2jk programmed to a "0" data state (the "+1" polarization state of FIG. 1a), but that returns a "1" data state when read, as though it were programmed to the "−1" polarization state. It is believed that an instance of cell 2jk that is "stuck" in this manner has a defect in its capacitor 6 causing it to leak charge from the pulse applied to its plate line PL through pass transistor 4, increasing the signal at its bit line BLk and appearing as a "1" data state. These stuck bits cannot be programmed to a "0" data state that is sufficiently strong to return the "0" data state when read, for reasonable levels of reference voltage VREF. This failure mechanism of the stuck, or leaky, bit has been observed to develop over the operating life of the FRAM, for example as may be accelerated by a high temperature bake as commonly used to evaluate the reliability of a population of FRAM devices.
As known in the art, the sensing of 2T-2C cells in normal operation is based on a differential signal at complementary bit lines that are coupled to the accessed FRAM cell. By way of further background, a time-zero measurement of the slope of a cumulative fail bit distribution of half-cells in the 2T-2C memory, versus the reference voltage VREF is known in the testing of 2T-2C FRAM cells is used as a measure of time-zero polarization.

Screening for later life stuck bits in ferroelectric memories


The invention relates to a waste sludge treatment process in which a solid additive is mixed into sludge to produce solid products. The solid additive includes aggregate-like hydrophobic grains of peat.

Waste sludge may originate from a mechanical, biological or chemical process. Treated waste sludge often is a mixture of different types of waste sludges from these processes. Current efforts of sludge treatment are aimed at treating community or industrial wastewater sludge, industrial flour sludge and agricultural animal excrement sludge in such a way as to cause as few environmental problems as possible, and also, on the other hand, to utilize the sludge as efficiently as possible.
Currently, waste sludge is often treated by means of composting, which is a time-consuming process requiring periodic mechanical handling of the compost material to improve aeration. Lately it has become common practice to burn sludge, especially in the wood processing industry, which is not an efficient method due to the high moisture content of the sludge, but which makes it possible to get rid of undesirable waste.
For a long time it has been understood that it would be advantageous to treat waste sludge by means of rapid processes in which the sludge is utilized in producing solid products, such as biofuel. The basic method used in such processes consists of mixing organic binding agents with the waste sludge, forming grains, pellets or similar particles from the mixture by means of pressing or by using pressing as an intermediate phase of the process, and then drying them. However, there are several problems involved in such processing of waste sludge. First of all, it is difficult to efficiently extract water from the sludge. It is difficult because the water is bound to the cell structure of the sludge. Waste sludge is usually dried after compaction by means of centrifuging or a pressing method such as filter pressing. Even after drying by means of such a reasonably quick method that consumes a reasonable amount of energy, the water content of the waste sludge is typically in the magnitude of 70-80%. A second problem involves formation of a coherent mass that may be shaped without having to use such an abundance of coagulants or moisture-binding organic additives that it is not economically feasable to use the process extensively. A third problem involves drying the products formed from the material to make them stabile and coherent. This means that, for example, bacterial action must be stopped so it will not degrade the product.
Attempts have been made to treat waste sludge, for example, by adding milled peat to it and then pressing it. However, a pressing method has not been found that efficiently and economically extracts water from such a mixture and allows easily shaped and dried, coherent products to be made from the mixture. A number of proposals have been made regarding methods by which solid products suitable for use as fertilizers or topsoil additives may be produced from agricultural waste sludge, in particular, and suitable organic additives. However, such proposals, one of which is examined in more detail below, do not present an efficient solution to the above-mentioned problems. U.S. Pat. No. 5,389,114 presents a process for producing biofuel that includes several mechanical and chemical treatment phases and disinfection phases, of which the last is microwave radiation. The disadvantage of this method is its complexity and on the other hand, the fact that it is largely based on the use of chemicals.
Swiss Patent No. 683519 presents a solution in which an organic additive, such as straw or sawdust, is mixed into agricultural sludge and the mixture is strongly extruded to produce a homogenous mass and then heated and dried to produce a nearly dry product. The extrusion may be repeated, after which drying may also be repeated.
German Patent Application No. 4110950 presents a solution in which a topsoil additive is produced from underwater sludge by mixing it with particle-, fiber- or flake-like organic material with a large outer surface and low moisture content, thus eliminating the sludge structure, after which the resulting mixture may be further mixed and then granulated and dried. In light of the presented examples, it appears that the method is suitable for treating sludge with a composition that meets certain requirements and has a quite low water content.
In the method of both documents cited above, the process is based on simply mixing a sufficiently suitable organic additive with the sludge to produce a mass suitable for further treatment. In order for this to be economical on a large scale, the characteristics of the waste sludge must be especially suitable for the treatment. If a large quantity of additive is required, for example, noticeably more than the quantity of waste sludge itself, the economy of the method of treatment becomes poor, as it was already stated above.


A composition suitable for use in a powder coating process comprising a powdered polymer composition and a metal oxide based fluidization enhancer, or a metal oxide based flatting agent.

(1) Field of the Invention
This invention concerns powder coating compositions and particularly powder coating compositions that have improved fluidization properties as a result of including a small amount of a metal oxide fluidization enhancer in the composition. This invention is also a powder coating composition that includes a small amount of a novel metal oxide gloss reducing agent.
(2) Description of the Art
Polymer based powder coatings are solid particulate compositions which are generally applied to substrates to give the substrate a tough durable surface coating. Powder coatings are applied to substrates by electrostatic, corona, or tribocharge spray process in which the powder coating particles are electrostatically charged by the spray gun and the substrate is grounded or oppositely charged. The applied powder coating is then heated to melt and fuse the particles into a continuous coating and to cure the resulting coating. The powder coating particles which do not adhere to the substrate can be recovered for re-use. Powder coating compositions are generally free of added solvents and, in particular, do not use organic solvents and accordingly are nonpolluting.
Powder coating compositions generally comprise a solid film-forming resin, usually with one or more coloring agents such as pigments. They are usually thermosetting, incorporating, for example, a film forming polymer and a corresponding curing agent (which may itself be another film-forming polymer). Powder coating compositions are generally prepared by intimately mixing the ingredients, for example in an extruder, at a temperature above the softening point of the film-forming polymer(s) but below a temperature at which significant polymerization would occur. The extrudate is usually rolled into a flat sheet and reduced in size, for example, by grinding, to the desired particle size. The particle size distribution required for most commercial electrostatic spray apparatus is between 10 and 120 microns, with a mean particle size within the range of 15 to 75 microns, and preferably 25–50 microns. Examples of powder polymer coating compositions are disclosed in U.S. Pat. Nos. 5,461,089, 5,470,893, 5,614,323 and 5,229,460.
Powder polymers cure to a glossy finish. In some applications, however, gloss reduction to gloss is desired. Gloss reduction is typically achieved in powder paints by adding large inert particles known as "texturing agents" to the compositions. The texturing agents become encased in the cured polymer film and are large enough to give the final finish a rough appearance. Examples of large inert texturing agents include fibers, pigments, mica and abrasives, such as those disclosed in U.S. Pat. No. 5,470,893.
Powder polymer coating compositions are also difficult to fluidize and to keep free flowing during their delivery, application, and use because of the tendency of powder polymer coatings to cake, become compacted, and to agglomerate during storage, reclaim, and handling. The problem with fluidization is becoming more predominant as the particle size of the powder polymer compositions decrease.
Traditionally it has been typical to use precipitated or gelled silicas as free flow additives, particularly to larger particle size powder coatings. Precipitated silicas and gelled silicas are believed to enhance the free flow of powder polymer compositions due to their ability to absorb moisture in the form of water vapor or liquid which minimizes liquid bonding and liquid-liquid bridging between the powdered polymer particles. However, with smaller and smaller powdered polymer particles becoming the norm, improved additives that adsorb moisture and/or that enhance powder polymer performance are needed.
While existing powder coating compositions are satisfactory in many respects, there nevertheless exists a need for powdered polymer coating compositions that produce a low gloss finish. It is an objective of the present invention, therefore to provide a reduced gloss powdered coating composition. There is also a need for new fluidization enhancer compositions that can be combined with powdered polymer compositions, and especially with small particle size powdered polymer compositions in order to enhance powder polymer performance.

This patent is subject to a terminal disclaimer.


A packet broadcasting method broadcasts a data packet sent by a broadcasting source terminal to a number of broadcast destination terminals. A broadcasting apparatus having a peculiar DTE address is provided in a packet switching system and a broadcasting table having one or a plurality of broadcasting source terminals is defined in the broadcasting apparatus. The broadcasting apparatus registers a terminal other than a broadcasting source terminal into the broadcasting table as a broadcast destination terminal in response to a call set-up from such a terminal When the broadcasting apparatus receives a data packet from the broadcasting source terminal, a data packet having the same data as the received data packet is sent to the broadcast destination terminal.

The present invention relates to a packet broadcasting method, and more particularly, to a packet broadcasting method for group broadcasting a data packet transmitted by a broadcasting source terminal to a plurality of broadcast destination terminals.
A technique for broadcast communication or the broadcasting operation in a packet switching system, is described in JP-A-61-140251 is known.
In the prior art, a broadcasting table in which called terminals or destination terminals are defined for each calling terminal or source terminal is provided in a packet switching office, and the packet switching office performs the broadcasting operation on the basis of the broadcasting contents of the table.
In the prior art, since the broadcasting or the broadcast communication is performed in the packet switching office including the broadcasting function, it is necessary to add the broadcasting function in an existing packet switching network when the existing packet switching network is to realize the broadcasting. Accordingly, there is a problem that it is difficult to attain the broadcasting operation in the existing packet switching network. Further, there is a problem that a large amount of pre-defined data is required since destination terminals are required to be pre-defined for each source terminal effecting the broadcasting operation.
Furthermore, in the prior art, when a broadcast destination terminal is added or changed, it is necessary to change the pre-defined data stored in the packet switching office and accordingly flexibility is lacking in such a system. The broadcasting table is pre-defined for each source terminal effecting the broadcasting operation, while since the table has no table identification, only one group of destination terminals is pre-defined for each source terminal. Accordingly, there is a problem that it is impossible to select broadcast destination terminals depending on the contents of data to be broadcast.
In addition, in the prior art, when a data packet is transmitted to destination terminals, a packet switching office which has received the data packet from a source terminal directly transmits the data packet to all of the destination terminals individually. Accordingly, when the destination terminals are increased, there is a problem that a time required to perform the whole broadcasting operation in the packet switching office is lengthened to thereby enlarge differences in reception times of the data packet among the destination terminals and increase trunk traffic in the packet switching network which adversely affects other communication.


A signal strength indicator circuit, configured to detect a power of an output signal outputted by a power amplifier, includes a voltage gain circuit, a current gain circuit, a multiplier, and a buffer stage. The voltage gain circuit provides a first gain to the output signal to generate a first value of an indicating voltage when a voltage of the output signal is not greater than a threshold, and provides a second gain to generate a second value of the indicating voltage when the voltage of the output signal is greater than the threshold. The first gain is greater than the second gain. The current gain circuit generates an indicating current according to an input signal corresponding to the output signal. The multiplier multiplies the indicating voltage and the indicating current to generate an indicating power. The buffer stage converts the indicating power to the indicating signal.

Transmitting circuits are used in various wireless communication applications, and different transmission protocols specify the power range of the transmitted power of the transmitting circuit. Conventionally, the transmission circuit uses a power detector to detect the strength of the output signal and generates an indication of the transmitted signal strength based on the detected strength, wherein the indication indicates the transmitted power of the transmitting circuit. However, different transmission devices (e.g., antennas) or environmental factors (e.g., temperature) may cause the transmitted power to change, thereby causing the output signal strength to fail to meet the specifications of the transmission protocol. Furthermore, some transmission protocols specify a range of transmitted power up to 35 dB, and power detectors in conventional technologies cannot cover such a measurement range, resulting in inaccurate measurements. Therefore, how to adjust the measurement range of the power detector to cover the power range specified by the transmission protocol has become one of the most important issues of the related field.

Transmit-signal strength indicator circuit and transmitting circuit


An end-of-life indicator comprising a housing having a chamber therein and attachable to the water treatment device, a diaphragm disposed within the chamber, a rotatable cap having indicia disposed thereon adapted to cooperate with the housing, a spring device for rotating the cap with respect to the housing, an escapement device for regulating the rotational displacement of the cap and means for resetting the cap to a start position. The chamber is arranged for the ingress of water into the water treatment device to pressurize the chamber and the egress of water from the water treatment device to depressurize the chamber, the ingress and egress of water defining one fill cycle. The diaphragm is arranged to be moved by the pressurizing and depressurizing of the chamber. The escapement device are arranged to cooperate with the diaphragm and the spring device whereby predetermined incremental rotation of the cap is provided during each of the fill cycles.

Water treatment devices are well known in the art. Such devices are employed directly in a water system, either in-line or at a terminal end, or in self-contained batch systems. An example of an in-line system is an under the counter device which filters water prior to reaching the faucet. Terminal end devices include counter top and faucet mounted filtration systems. Self-contained batch systems include devices such as carafe units.
Typical water treatment devices employ mechanical filtration or chemical treatment. Mechanical filters treat water by preventing passage of particulates. As a mechanical filter approaches the end of its useful life, restricted flow due to particulate accumulation provides a ready indication that element replacement is necessary.
Chemical treatment (e.g., activated carbon-based and ion exchange media) employs processes such as adsorption and ion exchange for removing undesirable chemical species. A major drawback associated with chemical treatment is that the chemical media eventually becomes inactive, providing no such indication that the useful life of the chemical element has been exceeded.
As a result, various methods have been employed to indicate end of life to the user where it is not inherently provided by the behavior of the filter media. Illustrative is the method disclosed in U.S. Pat. No. 4,686,037. In the noted method, the user compares the color of the pre-filter with a reference strip to determine when the media requires replacement. The problem with this method, however, is that it is inherently subjective and, therefore, subject to error.
A more accurate means of indicating end of useful life of conventional treatment units is through devices which use a process commonly referred to as "flow totalization". These devices totalize the liquid volume which is passed through the treatment media.
Both electrical and mechanical "flow totalization" devices are known in the art. Illustrative are the devices disclosed in U.S. Pat. Nos. 4,918,426; 5,089,144; 4,681,677; and 5,536,394.
In U.S. Pat. Nos. 4,918,426 and 5,089,144 electrical flow totalization devices are disclosed which employ pressure transducers. The transducers include integrated outputs to calculate total volume. After a predetermined volume has been reached, a valve is electrically actuated to stop flow.
U.S. Pat. No. 4,681,677 discloses a mechanical flow totalization device which employs a turbine interconnected with a series of gears. The gears are designed and adapted to mechanically "add up" the volume of water passed through the device. The gears also cooperate with a valve that is adapted to stop flow after a predetermined volume of water has passed through the device.
In U.S. Pat. No. 5,536,394 a mechanical flow totalization device is disclosed which employs a float mechanism. The float is designed and adapted to rotate a pre-determined distance upon each fill cycle of the water treatment unit. Once the float has made a specific number of rotations and has traveled a complete distance across a support rod, the float rests in a position where it visible through an opening in a housing, indicative of the end of life of the water treatment unit.
Although flow totalization devices address the end of life problem(s), there are drawbacks. One major drawback is that flow totalization devices are often complex and, hence, expensive. Another drawback is that such devices can, and in many instances will, adversely effect the flow thru characteristics of the water treatment device (i.e. filter cartridge).
An additional drawback with mechanical flow totalization devices is that the devices are typically incorporated into the replaceable cartridge. This approach is unnecessarily wasteful and expensive.
It is therefore an object of the present invention to provide a device for indicating the end of useful life of a water treatment system that is mechanically simple, accurate and reliable.
It is another object of the invention to provide a device for indicating the end of useful life of a water treatment system which can be readily reset upon replacement of the cartridge and/or chemical media.
It is another object of the invention to provide a device for indicating the end of useful life which enhances the flow thru characteristics of the filter cartridge.
It is yet another object of the invention to provide a device for indicating the end of useful life which is readily adaptable to various batch water treatment systems.
These and other objects of the present invention will be apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.

End-of-life indicator for water treatment device


An electrical generating system includes a plurality of linear operating magnetos impeded within a roadway pavement, whereby the passage of vehicle wheels from moving motor vehicles directly depresses linear solenoid plungers for generating electricity, without the need for the extra energy consumption drawbacks, such as bellows, compressed air or ratchet mechanisms.

Among related patents include U.S. Pat. No. 6,204,568 of Runner, which has a ratchet plunger connected to air flow turbines for converting mechanical motion of vehicles moving in traffic to electrical energy.
Also, U.S. Pat. No. 4,614,875 of McGee has a similar vehicle wheel actuated electrical generator such as a rotor and stator generator, i.e., an AC generator or a DC dynamo.
The other patents disclose auxiliary mechanical devices such as inflatable bladders or gears that produce mechanical energy which is converted to electrical energy by a generator. These devices are not efficient because of the extra auxiliary mechanical step in producing electrical energy.
For example, U.S. Pat. No. 4,339,920 of Le Van, U.S. Pat. No. 4,322,673 of Dukess, U.S. Pat. No. 4,418,542 of Ferrell, U.S. Pat. No. 4,081,224 of Krupp, U.S. Pat. No. 4,212,598 of Roche, U.S. Pat. No. 4,173,431 of Smith and U.S. Pat. No. 6,172,426 of Galich all use vehicle tire movement responsive fluid compressors to produce electrical or mechanical energy.
Furthermore, U.S. Pat. No. 4,239,975 of Chiappetti uses a vehicle tire responsive flywheel to power an electrical generator.
Moreover, U.S. Pat. No. 4,238,687 of Martinez generates power from the movement of motor vehicle tires over a roadway with a plurality of pivoting treadles plates having ratchet teeth moving a ratchet turbine wheel.
In addition, U.S. Pat. No. 5,081,848 of Rawlings and U.S. Pat. No. 4,132,074 of Wendel describe underground pavement de-icers.
However, these patents do not describe an electrical generating system wherein a plurality of linear operating magnetos are physically imbedded within a roadway pavement. The passage of vehicle wheels from moving motor vehicles directly depresses linear solenoid plungers for generating electricity. This can be done without the need for the auxiliary energy consumption drawbacks of the known prior art patents, which need bellows, compressed air devices, etc. to convert the energy indirectly.

Vehicle actuated road imbedded magneto generator


An equalizing method and device for equalizing a received signal by renewing a filtering coefficient of a filter in an off-line system using a pre-stored reference signal. It is first determined whether or not a signal input to a high definition TV (HDTV) includes a field sync or not. If so, the detected field sync is stored in a memory as a training sequence. A filtering coefficient is calculated according to a predetermined algorithm, and a symbol error rate (SER) is calculated using the pre-stored reference signal. The filtering coefficient is transmitted to the filter when the calculated SER is lower than a predetermined value. The process of calculating the filtering coefficient, determining the level of the training sequence, and transmitting the filtering coefficient is repeated until a loop variable equals a loop constant, which indicates the number of off-line operations capable of being performed in a field, while increasing the loop variable when the calculated SER obtained is greater than or equal to the predetermined value.

The present invention relates to an equalizing method and an equalizer using a reference signal, and more particularly, to an equalizing method and an equalizer using a reference signal for efficiently removing or reducing multipath distortion in a digital signal demodulating system.
The current trend in the television market is to pursue large scale, realistic, and high definition TV. The Japanese are using high definition TV (HDTV) based on multiple subnyquist sampling encoding (MUSE) which is an analog transmitting method, the US has adopted the GA-HDTV system proposed by the Grand Alliance (GA), and some cable TV companies are interested in quadrature amplitude modulation (hereinafter referred to as QAM) as a digital transmission method.
Because the GA-HDTV adopts digital vestigial side band (hereinafter referred to as VSB) modulation, it is referred to as a GA-VSB type receiver. Here, VSB is used as an analog image signal modulation method in a conventional TV, and for digital signal modulation in the GA-HDTV. In the early digital spectrum compatible-TV (hereinafter referred to as DSC-TV) 2-VSB and 4-VSB were adapted using two and four levels, respectively, as its modulation method. However, the GA-HDTV adopts 8-VSB for terrestrial broadcast mode using 8-levels and 16-VSB for high speed cable mode using 16-levels as its modulation method.
The GA has proposed a schematic constitution of a receiver for demodulating such VSB signals, and the characteristics of the proposed receiver are as follows. First, the VSB receiver, different from other demodulators, detects data using only the In-phase channel (I-channel) signals and performs sampling according to a symbol rate. Therefore, the VSB receiver design is more simple than a QAM receiver which uses quadratrure channel (Q-channel) and I-channel at the same time, and the VSB receiver detects data at a relatively slow processing speed because, unlike a fractional rate receiver, it processes data at a symbol rate. Moreover, the proposed VSB receiver adopts coherent detection for demodulating modulated signals by reproducing carriers from the receiver for detecting digital data. Compared with incoherent detection, coherent detection is advantageous in that it can reliably detect data having the same signal-to-noise ratio, but the receiver design becomes more complicated due to the carrier reproduction circuit. Therefore, the proposed VSB receiver adopts two-step coherent phase detection using a frequency and phase locked loop (FPLL) and a phase tracking loop (PTL) to detect the phase of a transmitted signal.
The FPLL uses a pilot signal included in the VSB signal for estimating the phase of a transmitted VSB signal. Such a FPLL can easily be established using a conventional frequency error detecting circuit, and its constitution and efficiency is disclosed in document 1!: 1! R. Citta, "Frequency and Phase Lock Loop", IEEE Trans, on Consumer Electronics, vol, CE-23, no.3, pp.358-365, Aug. 1977.
The output of the FPLL is transmitted to the PTL via a channel equalizer, and the PTL functions to remove residual phase noise, i.e., phase error, from the output signal.
The GA-HDTV receiver constitution is nearly the same as a decision directed carrier recovery (DDCR) receiver disclosed in document 2!: 2! E. A. Lee and D. G. Messerschmitt, Digital Communication, Kluwer Academic Publishers, Boston, Mass., 1988, but different in that it estimates the rotating components of signal points using only I-channel sampled data and compensates phase error values based on the result.
FIG. 1 is a block diagram showing the constitution of a GA-HDTV receiver, which will be used to describe the VSB type GA receiver. This block diagram is disclosed in document 3!: 3! Grand Alliance HDTV System Specification, submitted to the ACATS Technical Subgroup, Feb. 1994.
In FIG. 1. a tuner 102 selects a desired channel signal among the HDTV signals received via an antenna. Generally, the output of the tuner 102 is a modulated HDTV signal having a 44 MHZ central frequency and a 6 MHZ bandwidth. However, the output of the tuner 102 is not superior in its inner filter characteristic and thus it passes not only the 6 MHZ band of HDTV signals but also a portion of the neighboring channel signals.
Because the neighboring channel signals cause interference in the desired channel signal, the output of the tuner 102 passes through a surface acoustic wave (SAW) filter 104 whose band width is precisely 6 MHZ.
An intermediate frequency (hereinafter referred to as IF) amplifier 106 maintains the input signal of an analog-to-digital (A/D) converter 112 at a proper level, and its gain is controlled by an auto gain control signal output from an auto gain control (hereinafter referred to as AGC) circuit 110.
Here, the proper level means 8-levels (.+-.1, .+-.3, .+-.5, .+-.7) to which is added a DC offset of 1.25, i.e., -5.75, -3.75, -1.75, 0.25, 2.25, 4.25, 6.25, 8.25.
The tuner 102 includes a high frequency amplifier (hereinafter referred to as an RF amplifier) therein, and thus if the gain of the IF amplifier is not sufficient, the gain of the RF amplifier is sufficiently regulated to match the signal being amplified according to the AGC signal.
By the way, the restoration of the carrier is performed by an FPLL circuit 108, which traces the pilot signals added to the output signal of the IF amplifier 106 and regulates the local oscillation frequency of the tuner 102 so that the pilot signal frequency is zero Hz. As a result, the FPLL circuit 108 restores the carrier and multiplies the restored carrier by the output of the IF amplifier 106 to demodulate it as a base-band signal.
The A/D converter 112 samples the output of the FPLL circuit 108 according to the symbol clock signal restored by a symbol timing and field sync restorer 114, and converts the sampled data to digital data.
The symbol timing and field sync restorer 114 generates symbol clock pulses for controlling the sampling timing of the A/D converter 112, supplies the field sync reference signals stored therein to an NTSC detector 116, restores the field sync by comparing the field reference signals with the field sync transmitted to each field, generates the operation clock signal for the entire system, and supplies a field sync control signal to an equalizer 120.
Referring to FIG. 2, showing a VSB data frame format of a GA-HDTV, the VSB data frame is constituted of two fields, each field constituted of one field sync segment and 312 data segments, and each data segment is constituted of four symbols for segment sync and 828 symbols for data and forward error correction (FEC) code.
Moreover, the segment sync is inserted in the eight-level digital data stream at the beginning of each data segment. Here, the segment sync constitutes a regular pattern of four symbols having +5, -5, -5, and +5 signal levels, respectively, and the other data is randomly constituted of the eight levels. Because the segment sync is a binary number (binary level) and should ensure its own stability without interfering with the NTSC signals of the co-channel, its level is determined to be .+-.5.
Additionally, a field sync segment, the first segment of each field, contains a field sync signal for indicating the initiation of a field (FIELD SYNC #1, and FIELD SYNC #2) therein.
FIG. 3 shows the VSB data field sync format of a GA-HDTV.
As shown in FIG. 3, the field sync segment is constituted of 832 symbols, the segment sync constitutes the first four symbols thereof, pseudo number PN 511 constitutes the following 511 symbols, three PN 63's constitute the following 189 symbols, and 24 symbols indicating 2-VSB, 4-VSB, 8-VSB, and 16-VSB modes and other information (104 symbols) constitute the remaining 128 symbols.
Here, PN 511, a predetermined signal sequence which is indicated as +5 and -5 levels, is used as a training sequence for equalizing, and the three PN 63 sequences are used as a field discriminating signal because the phase of the second PN 63 is reversed in every other field.
Referring to FIG. 1, the NTSC detector 116 including an NTSC removing filter (hereinafter referred to as NRF) filters out carrier components of the NTSC signals from the output of the A/D converter 112 for preventing the HDTV broadcast from being deteriorated under channel coherent circumstances when the HDTV and NTSC are simultaneously broadcast.
A DC offset remover 118 removes the DC offset which is due to the non-linearity of the pilot signal and the A/D converter 112 from the digital signals converted in the A/D converter 112.
That is, a small digital DC level (1.25) is transmitted while being added to the four symbol data segment sync having signal levels of +5, -5, -5, and +5 and the 828 symbol data having random levels among the eight levels (.+-.1, .+-.3, .+-.5, .+-.7), and which has the same effect as the pilot signal is added to the data signal. Moreover, the input and output of the A/D converter 112 show non-linear characteristics.
Therefore, the DC offset (1.25) due to the pilot signal and the DC offset due to the non-linearity of the A/D converter 112 should be removed so that an HDTV signal having an original signal level can be restored in a receiver. Accordingly, the DC offset remover 118 removes the DC offset by detecting the mean DC offset of the field sync, and subtracting the DC offset detected in the output of the NTSC detector 116 therefrom. Here, the DC offset is calculated by taking an average of the field sync in the unit of a frame because, e.g., the phase of the second PN 63 among the 189 symbols used as a field discriminating signal as shown in FIG. 3 is reversed in every other field and the absolute values thereof are the same.
The equalizer 120 removes the multipath distortion, in other words multipath noise, due to the transmitting signal passing through the transmission channel. Such multipath distortion results in a multipath channel due to wave deflection off a mountain, a group of buildings, or an airplane during terrestrial broadcasting. The multipath distortion causes delayed and attenuated image signals to be overlapped with the original signal, and distorts the frequency characteristics of the HDTV signal as well. A more detailed description of the NTSC detector 116 and the equalizer 120 will be given with reference to FIG. 4.
In the transmitter, a signal is modulated using Read-Solomon (hereinafter referred to as "RS") coding, an interleaving process, and trellis coded modulation (TCM) before transmission to reduce symbol errors generated during transmission. When the decoder receives a signal from the transmitter, a PTL 122 compensates for that portion of the phase error not completely corrected in the FPLL 108 and a channel decoder 124 decodes the signal received from the PTL 122.
The channel decoder 124 performs trellis decoding on the output of the PTL 122, deinterleaves the trellis decoded data, and error correction decodes the deinterleaved data.
The source decoder 126 variable length decodes the error correction decoded data output from the channel decoder 124, inverse quantizes the variable length decoded data, inverse discrete cosine transforms (IDCT) the inverse quantized data, decompresses the compressed data to restore the original data, and displays it on a display (not shown).
FIG. 4 shows a detailed partial block diagram of a conventional HDTV receiver of a GA-VSB type, and the constitution thereof is described in the above document 3!.
During simultaneous broadcasting of the NTSC and HDTV signals, e.g., when ATV (Advanced Television) and DVB (Digital Video Broadcasting) signals are included, the NTSC signal has a regular carrier frequency offset (about 0.89 MHZ) compared to the VSB signal. Thus, considered to be in base band, the NTSC signal is the same as a modulated carrier frequency corresponding to the frequency offset. Here, most of the NTSC signal energy is concentrated on the original DC component, i.e., the modulated carrier. Thus, when the NTSC mixing components pass through the NRF 204 of the NTSC detector 116, the modulated carrier component is removed and thus the NTSC signal effect on the HDTV signal is decreased.
The NTSC detector 116, using the reference signal, compares the field sync reference signal stored in the symbol timing and field sync demodulator 114 with the field sync output from the A/D converter 112, and determines whether the NTSC signal is mixed with the VSB signal using the accumulated values of the squared difference values.
In other words, the NTSC detector 116 is constituted of an original path through a mixer 201, a squaring circuit 202, and an integrator 203 for comparing the field sync reference signal output from the symbol timing and field sync restorer 114 with the field sync output from the A/D converter 112, and calculating the value of the accumulated squared result of the comparison, a path through the NRF 204, the NRF 205, a mixer 206, a squaring circuit 207, and an integrator 208 for comparing between the field sync output from the A/D converter 112 via NRF 204 and the field sync reference signal output from the symbol timing and field sync restorer 114 via the NRF 205, and calculating the value of the accumulated squared result of the comparison, a least error detector 209 for detecting and outputting the NTSC mixing HDTV channel components by comparing between the two path values, and a multiplexer 210 for selecting I-channel symbol data of the A/D converter 112 output via the NRF 204 or I-channel symbol data output directly from the symbol timing and field sync restorer 114 by using the detection signal output from the least error detector 209 as a selection control signal.
Here, the least error detector 209 generates an NRF controlling (NRF CON) signal for indicating whether or not the output of the A/D converter 112 follows the NRF 204 path in the NTSC detector 116, and transmits the NRF CON signal to a memory 216 of the equalizer 120 and a filter coefficient calculator 217.
The equalizer 120 is constituted of an L1 (herein 78) tab filter 211 as a forward transversal filter, an L2 (herein 177) tab filter 212, a subtractor 213 for subtracting the output of the L2 tab filter 212 from the output of the L1 tab filter 211, a slicer 214 for selecting the output level of the subtractor 213 from among the predetermined eight levels (.+-.1, .+-.3, .+-.5, .+-.7), a controlling switch 215 for supplying random data to L2 tab filter 212 during a data segment term and the training sequence to the memory 216 during the field sync segment term, the memory 216 for storing the training sequence inserted into the field sync segment output from the slicer 214 in every field according to the NRF controlling signal (NRF CON) of the least error detector 209, and the filtering coefficient calculator 217 for performing an equalizing process by renewing the filtering coefficients of the L1 tab filter 211 and the L2 tab filter 212 using the training sequence output from the subtractor 213 during the field sync segment term and outputting random data in a previous filtered state during the coefficient renewal term so that high speed tracking of a moving ghost signal can be possible. Such an equalizer is called a decision-feedback equalizer (DFE).
The filter coefficient calculator 217 calculates the filtering coefficients using a least mean square (LMS) algorithm in order to reduce the effect of noise on the training sequence used for coefficient renewal. During the coefficient renewal, a mean value is taken in every frame because the VSB signal has a different training sequence phase in every field. So, in this embodiment, the mean value is taken in a frame unit because in the second PN 63, the phase is reversed in every field of the field sync, as shown in FIG. 3. To use field mean, PN 511 and a first PN63 can be used. The LMS algorithm will be described later.
Additionally, the DC offset remover 118 filters out the DC offset by subtracting the DC offset transmitted from the filtering coefficient calculator 217 from the output of the NTSC detector 116. That is, because the field sync is transmitted with the DC offset (1.25) being added thereto, the filter coefficient calculator 217 obtains the DC offset value by taking the mean value of the first and second field syncs (FIELD SYNC #1, FIELD SYNC #2) and transmits it to the subtractor 118.
The equalizer 120 can use the reference signal transmitted in every field, random data and its error, or both at the same time. The equalizer shown in FIG. 4 uses both, i.e., the reference data and the random data. When the reference data is used, the coefficients of the tab filters 211 and 212 are to be adopted using the LMS algorithm.
Such an LMS algorithm is widely used and the basis thereof is to minimize the mean square error. When the input and output of the equalizer 120 are x(n) and z(n), respectively, the reference signal determining level is d(n), and the filtering coefficient is w.sub.i, EQU z(n)=W.sup.T (n-1)X.sup.T (n) (1) EQU e(n)=d(n)-z(n) (2) EQU W(n)=W(n-1)+2.mu..multidot.e(n)X(n) (3)
where,
X.sup.T (n)=X(n), X(n-1), . . . , X(n-N+1)!, PA1 W.sup.T =W.sub.0, W.sub.1, . . . , W.sub.N-1 ! PA1 i=0, 1, . . . , N-1, .mu. is constant and N is the tab number of the filter. PA1 (a) determining whether a signal input to a high definition TV (HDTV) includes a field sync or not; PA1 (b) storing a training sequence in a memory when the field sync is detected in the step (a); PA1 (c) calculating a filtering coefficient according to a predetermined algorithm; PA1 (d) determining the level of the training sequence stored in the step (b) and calculating a symbol error rate (SER) using the pre-stored reference signal; PA1 (e) transmitting the filtering coefficient obtained in the step (c) to the filter when the SER obtained in the step (d) is lower than a predetermined value; and PA1 (f) repeatedly performing the steps (c) through (f) until a loop variable equals a loop constant, which indicates the number of off-line operations capable of being performed in a field, while increasing the loop variable when the SER obtained in the step (d) is greater than or equal to a predetermined value. PA1 a first memory for storing a training sequence carried by the received signal in a field sync term according to a field sync control signal; PA1 a second memory for storing reference signals for 8-level and 15-level processes; PA1 a first filter for filtering the received signal; PA1 a second filter, connected to an output terminal of the equalizer; PA1 a subtractor for subtracting the output of the second filter from the output of the first filter and outputting an equalized signal; and PA1 filter coefficient calculating means for:
The LMS algorithm operates to minimize Ee.sup.2 (n)! and can be adapted to both an on-line system using input data continuously and an off-line system for storing data of a predetermined term in a memory.
In a conventional equalizer, considering the complicated calculation, hardware load, speed, etc., an off-line system is widely adapted rather than an on-line system.
Such an off-line system is also used in a ghost canceler for an NTSC broadcasting and is presently produced on a commercial scale. This ghost canceler is shown in document 4!: K. B. Kim, J. Oh, M. H. Lee, H. Hwang, and D. I. Song, "A New Ghost Cancellation System for Korean GCR," IEEE Trans. on Broadcasting, vol.40, no.3, pp.132-140, Sep. 1994.
The advantages of the off-line system are that it has a high convergent speed due to the predetermined reference signal, and that it can be constructed using a special hardware H/W clock rate, i.e., a clock which is slower than the system clock, considering the H/W speed.
Such an off-line system needs a method for controlling renewal of the filtering coefficients according to the degree of convergence of the LMS algorithm. A general LMS algorithm adopts a mean square error (MSE) detecting method, and the ghost canceler adopts a method for detecting the remaining peak value of a ghost signal using the characteristic of the auto correlation value of the reference data showing peak.
The GA-VSB type equalizer shown in FIG.4 adopts an off-line system which uses the reference signal. Another reason that the GA-VSB type equalizer uses an off-line system is because it performs an NRF process.
Considering simultaneous broadcasting of HDTV and NTSC signals, the GA-VSB type receiver performs an NRF process using a comb filter in order to reduce the NTSC signal to be mixed with the HDTV signal. Because NRF is a subtraction of two signals having full gains, the signal level increases from 8 levels to 15 levels and the carrier-to-noise (C/N) for the 15 level process is decreased by about 3 dB more than the 8 level process. That is, under the 15 level process, a stop & go (SAG) decision-directed algorithm can not be adopted and equalization is performed according to only the reference signal, which causes the convergent speed to deteriorate.
Here, the stop & go (SAG) decision-directed algorithm is described in document 5!: Giorgio Picchi and Giancarlo Prat: "Blind Equalization and Carrier Recovery Using `Stop-and-Go` Decision-Directed Algorithm" IEEE Trans. on Communications. vol., Com-35, no 9, pp 877-887, Sep. 1987.
Consequently, the off-line equalization driven by the reference signal is needed not only for speedy convergence in the initial state and precise equalization under general conditions but also for a converging operation of the 15-level equalizer under the circumstance where an NTSC signal is mixed with an HDTV signal.

Equalizing method and equalizer using reference signal


An antenna unit is provided. The antenna unit includes a first substrate, a first conductive layer, a second conductive layer, a first planar conductive ring and a feed conductor. The first substrate includes a first surface and a second surface, wherein the first surface is opposite to the second surface. The first conductive layer is disposed on the first surface. The second conductive layer is disposed on the second surface, wherein a main opening surrounded by a plurality of first conductive vias electrically connecting the first and the second conductive surface is formed on the second conductive layer, and the main opening defines a radiation cavity and center frequency. The first planar conductive ring surrounds the radiation cavity. The feed conductor feeds a wireless signal to the antenna unit. Both the first planar conductive ring and the feed conductor are placed between the first conductor layer and the second conductor layer.

1. Field of the Invention
The present invention relates to an antenna unit, and in particular relates to an antenna unit with improved isolation and beamwidth. The disclosed antenna unit is suitable for use in a phased-array antenna.
2. Description of the Related Art
FIG. 1 shows a conventional antenna 1, including an antenna substrate 10, a feed substrate 20, a microstrip patch 30, a ground plane 40 and a microstrip feed line 50. The antenna substrate 10 includes a first surface 11 and a second surface 12. The feed substrate 20 includes a third surface 21 and a fourth surface 22. The microstrip patch 30 is disposed on the first surface 11. The ground plane 40 is disposed on the third surface 21. The second surface 12 is connected to the ground plane 40. A coupling aperture 41 is formed on the ground plane 40. The microstrip feed line 50 is disposed on the fourth surface 22. The microstrip feed line 50 feeds wireless signals via the coupling aperture 41 to the microstrip patch 30. Conventional antennas typically have small bandwidths, undesirable back radiation and unwanted surface wave radiation issues. Additionally, when the conventional antennas are arranged in an array, isolation between the antennas is poor. c


A mounting apparatus includes a heat sink with two first mounting holes receiving two screws respectively, and a printed circuit board (PCB) with a second mounting hole, and a third mounting hole corresponding to the first mounting holes. The second mounting hole includes a second inserting hole, and a second accommodating hole extending from the second inserting hole along a first axis. The third mounting hole includes a third inserting hole, and a third accommodating hole extending from the third inserting hole along a second axis. One screw is inserted into the second inserting hole, and moved along a first axis to be received in the second accommodating hole. Another screw is angled into the third inserting hole, released to return to an upright position and received in the third accommodating hole.

1. Technical Field
The present disclosure relates to an apparatus for mounting a heat sink to a printed circuit board (PCB).
2. Description of Related Art
A heat sink is often mounted to a PCB via screws into screw holes on the PCB. With this mounting mechanism, an additional tool is needed to attach the screws, causing inconvenience and consuming considerable time in a factory assembly line.
Therefore, an apparatus for mounting a heat sink to a PCB is desired which addresses the described limitations.

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.