A level shift circuit includes first and second operation circuits, a bias circuit, and a current control circuit. The first and second operation circuits include high-voltage transistors and low-voltage transistors connected in series. The high-voltage transistors are controlled according to a potential at the interconnection point between the low-voltage and high-voltage transistors of opposite operation circuits. The bias circuit is provided in a one-to-one correspondence with the operation circuits and connected to the low-voltage transistors in series to activate the transistors in the stationary on state and decrease currents flowing into the transistors to a stationary current. The current control circuit connects to the bias circuit in parallel to increase the currents just after the low-level transistors are turned on to a high peak current. The low-voltage transistors are turned on/off alternately in response to the state transition of an input signal. An operation object is turned on/off according to the potential at the interconnection point between both of the transistors of the second operation circuit.

1. Field of the Invention
This invention relates to a level shift circuit used to operate, particularly, turn on/off operation objects of semiconductor devices or electronic circuit devices of MOS transistors, insulated bipolar gate transistors, bipolar transistors, etc., receiving a power supply voltage on the high-voltage side according to input signals on the low-voltage side.
2. Description of the Related Art
The semiconductor devices and electronic circuit devices as the operation objects need to be operated under a power supply voltage appropriate for their respective applications. Since a control system for them normally is built in an integrated circuit operating under a low power supply voltage of about 5 V, it is difficult to directly control the operation objects by output of the control system. Thus, it is necessary to place a level shift circuit to which the invention is applied between the control system and the operation object and usually the level shift circuit is built in the integrated circuit for the control system. FIGS. 1 and 2 show; examples of conventional level shift circuits fitted to the purpose.
FIG. 1 shows a circuit for operating a power MOS transistor 101 of an operation object indicated in the upper right corner of the figure by an input signal Si at a low voltage of 5-15 V shown in the lower left corner of the figure when the MOS transistor 101 operates upon reception of 300-V power supply voltage VH, for example. A drive circuit 102 of a gate of the MOS transistor 101 is provided and to operate the drive circuit 102 on the high-voltage side, for example, a 15-V floating power supply (not shown) is connected to the power supply voltage VH. The MOS transistor 101 is provided for driving a load 103 on/off.
The level shift circuit is made up of a transistor 104 for receiving the input signal Si and a voltage dividing circuit consisting of a pair of resistors 105 and 106 connected between the transistor 104 and the power supply voltage VH for turning on/off the MOS transistor 101 through the drive circuit 102 by dividing voltage by the voltage dividing circuit. When the input signal Si is high and the transistor 104 is turned on, an electric current flowing from the power supply voltage VH side causes a voltage drop to occur in the resistor 105 and the voltage drop is given to the drive circuit 102. The drive circuit 102 normally consists of a plurality of inverter stages and when receiving the voltage drop in the resistor 105 as an operation, voltage, turns on the MOS transistor 101, for example. A Zener diode 107 connected to the resistor 105 in parallel is provided to always hold the operation voltage constant and prevent an overvoltage from being applied to the input of the drive circuit 102.
In a conventional example in FIG. 2, an operation object 101 is operated. The operation object 101 is a CMOS circuit operating upon reception of high-voltage side power supply voltage VH of about 15 V by a low-voltage input signal Si of about 5 V at TTL level. Since the high-voltage side power supply voltage VH is by far lower than that in FIG. 1, the floating power supply for a drive circuit 102 is omitted. The conventional level shift circuit consists of a pair of operation circuits 110 and 120 comprising high-voltage transistors 111 and 121 and low-voltage transistors 112 and 122 connected in series for receiving the high-voltage side power supply voltage VH.
As shown in the figure, the input signal Si is given to the low-voltage transistor 112 of the operation circuit 110; a complementary signal to the input signal Si by an inverter 160 operating upon reception of 5-V low-voltage side power supply voltage VL is given to the low-voltage transistor 122 of the operation circuit 120. The high-voltage transistor 121 of the operation circuit 120 is controlled according to the potential at the interconnection point between the transistors 111 and 112 of the operation circuit 110. The high-voltage transistor 111 of the operation circuit 110 is controlled according to the potential at the interconnection point between the transistors 121 and 122 of the operation circuit 120. The drive circuit 102 of the operation object 101 is operated according to the potential at the interconnection point on the side of the operation circuit 120.
When the input signal Si is low, the low-voltage transistor 112 of the operation circuit 110 is turned off, but the low-voltage transistor 122 of the operation circuit 120 is turned on, whereby the high-voltage transistor 111 of the operation circuit 110 is turned on, whereby the high-voltage transistor 121 of the operation circuit 120 is turned off. Thus, the drive circuit 102 receives the same low operation voltage as the input signal Si. When the input signal makes the low-to-high state transition, the on/off state of each transistor of the operation circuits 110 and 120 is inverted and the drive circuit 102 receives high operation voltage. As understood from this, in the conventional example in FIG. 2, the on/off state of the high-voltage transistor becomes opposite to that of the low-voltage transistor in the stationary state, thus a current flows into neither the operation circuit 110 nor 120. A current flows only in the transient state just after the high-to-low or low-to-high state transition of the input signal Si is made, and the operation voltage that the drive circuit 102 of the operation object 101 receives is switched high/low.
However, the conventional level shift circuits as discussed above involve the following problems: In the conventional example in FIG. 1, the electric power consumed by the level shift circuit becomes easily large because of the tradeoffs with the operation speed for the operation object 101. That is, when the-transistor 104 in FIG. 1 is turned on, power consumption, the product of current flowing into the transistor 104 via the voltage dividing resistors 105 and 106 and the high-voltage side power supply voltage VH, occurs. To decrease the power consumption, the resistance value of the resistors 105 and 106 may be raised for decreasing the current. However, the operation speed for the operation object 101 is restricted by a time constant, the product of the electrostatic capacity on the input side of the drive circuit 102 and the resistance value of the resistor 105. To provide a desired operation speed, the resistance value of the resistor 105 needs to be set to a predetermined limit or less. This also applies to the resistor 106 forming a part of the voltage dividing circuit like the transistor 105. Therefore, the power consumption of the level shift circuit can be decreased only to one limit and moreover increases rapidly as the high-voltage side power supply voltage VH.
In contrast, in the conventional example in FIG. 2, a current flows into the operation circuits 110 and 120 of the level shift circuit only at the beginning of the logic state transition of the input signal Si, as described above, so that power is by far less consumed than that in the example in FIG. 1. If the high-voltage side power supply voltage VH becomes several ten V or more, the circuit as in FIG. 2 cannot deal with it, but this problem can be solved if power is supplied to the drive circuit 102 from a floating power supply, such as described with regard to FIG. 1. However, the test result of operating the level shift circuit revealed that the operation speed for the operation object 101 cannot much be increased.
That is, to increase the operation speed, the electrostatic capacity on the input side of the drive circuit 102 needs to be charged and discharged rapidly. To do this, first the on resistance of the transistors 121 and 122 of the operation circuit 120 must be decreased and it is desirable that the on resistance of the transistors 111 and 112 of the operation circuit 110 are also decreased. However, if the on resistance is decreased, a so-called through current transiently flowing into the operation circuits 110 and 120 at the state transition time of the input signal Si increases. If the time for which the through current flows is prolonged due to component transistor operation time variations, etc., transistor destruction or characteristic degradation become prone to occur. As a result in the conventional example in FIG. 2, the operation speed for the operation object 101 can be increased only in a safety range in which such trouble can be prevented from occurring.
Subsequently, another conventional example will be described which shows a level shift circuit (level shifter) for converting an input signal of narrow logic amplitude in a 3-V range, for example, into an output signal of wide logic amplitude in a 30-V range, for example.
For example, a level shift circuit for converting a selection signal at a low voltage level into a liquid crystal drive voltage at a high voltage level is built in a liquid crystal drive IC (liquid crystal driver) in addition to a power transistor at an output stage. Hitherto, the basic form of this level shift circuit has been a flip-flop circuit configuration of low power consumption type wherein two stages of CMOS are connected for applying feedback, as shown in FIG. 3. That is, a level shift circuit 10 shown in FIG. 3 has a CMOS inverter INV1 for generating, for example, from a logic input signal VIN of narrow logic amplitude (3 V=Vdd-Vss) produced by a power supply in a 3-V range (0 V (=Vss) to 3 V (=Vdd)) power supply, an inverted signal VIN* of opposite phase in the 3-V range, a first n-channel MOSFET (first switch MOS) l for pull down, opened/closed by the logic input signal VIN, a second n-channel MOSFET (second switch MOS) 2 for pull down, opened/closed by the inverted signal VIN* exclusively with the first n-channel MOSFET 1, a first p-channel MOSFET 3 connected to the first n-channel MOSFET 1 in a totem-pole manner (in series) between 30-V (0 V (Vss) to 30 V (Vcc)) high-voltage power supplies, for example, and closed as the second n-channel MOSFET 2 is closed, and a second p-channel MOSFET 4 connected to the second n-channel MOSFET 2 in a totem-pole manner between 30-V (0 V (Vss) to 30 V (Vcc)) power supplies and closed as the first n-channel MOSFET 1 is closed.
The first p-channel-MOSFET 3 and the second p-channel MOSFET 4 make up a flip-flop FF with drain nodes (storage nodes) N1 and N2 cross-connected to mutual gates. Here, an output signal Vout of wide logic amplitude of the level shift circuit 10 is taken out from the drain node N2 and its inverted output signal Vout* appears at the drain node N1.
In the level shift circuit 10 of the basic configuration, when the logic input signal VIN rises from low level 0 V (=Vss) of narrow logic amplitude to high level 3 V (=Vdd), the first n-channel MOSFET 1 is closed, and as the inverted signal VIN* of opposite phase falls to 0 V (=Vss), the second n-channel MOSFET 2 is opened. As the first n-channel MOSFET 1 is closed, 0 V (=Vss) is fed into the drain node N1 of the flip-flop FF and the voltage is defined as low level of wide logic amplitude. As the second n-channel MOSFET 2 is opened, the voltage of the drain node N2 floats and becomes once undefined. However, the second p-channel MOSFET 4 is closed according to the defined voltage 0 V of the node N1. Thus, the drain node N2 immediately is defined as high-level voltage 30 V (=Vcc) of wide logic amplitude. As a result, the first p-channel MOSFET 3 is opened. Thus, a p-channel MOSFET 5 at an output stage with its gate connected to the drain node N2 is opened.
In contrast, when the logic input signal VIN falls from high level 3 V (=Vdd) to low level 0 V (=Vss), the first n-channel MOSFET 1 is opened and the second n-channel MOSFET 2 is closed. 0 V (=Vss) is fed into the drain node N2 of the flip-flop FF and the voltage is defined as low level of wide logic amplitude. The voltage of the drain node N1 floats and becomes once undefined. However, the first n-channel MOSFET 3 is closed according to the defined voltage 0 V of the node N2. Thus, the drain node N1 immediately is defined as high-level voltage 30 V (=Vcc) of wide logic amplitude. As a result, the second p-channel MOSFET 4 is opened. Thus, the p-channel MOSFET 5 at the output stage with is closed.
Thus, the level shift circuit 10 provides the step waveform of the logic output signal VOUT of wide logic amplitude of low level 0 V (Vss) to high level 30 V (Vcc) with respect to the step waveform of the logic input signal VIN of narrow logic amplitude of narrow logic amplitude of low level 0 V (Vss) to high level 3 V (Vdd).
The level shift circuit 10 is made monolithic as a semiconductor integrated circuit (IC) together with a preceding-stage circuit (not shown) for generating the logic input signal VIN and the MOSFET 5 at the output stage. Thus, it is desirable to form the gate insulting films of the MOSFETs in one chip all as the same thickness from cost merits by reducing the manufacturing process steps. However, since the potentials of the drain nodes (storage nodes) N1 and N2 of the flip-flop FF in the level shift circuit 10 are reset to 0 V (Vss) alternately as the switch MOSs 1 and 2 are opened and closed. Thus, the source-to-drain voltage becomes a high voltage (about 30 V) in the first and second p-channel MOSFETs 3 and 4 making up the flip-flop FF and the MOSFET 5 at the output stage. Thus, transistors of a high voltage resistance structure formed with a low-concentration drain region of offset gate type are required. Further, since high voltage (about 30 V) is also applied between gate and source, between gate and drain, and between gate and substrate, the gate insulating films of the MOSFETs 3 to 5 must be formed furthermore thick as compared with those of MOSFETs of other low-voltage control circuits for the purpose of improving the gate voltage resistance.
A level shift circuit 20 shown in FIG. 4 is proposed in order to place the gate-to-source voltage resistance, gate-to-drain voltage resistance, and gate-to-substrate voltage resistance within 3-V voltage resistance. That is, the level shift circuit 20 has a configuration wherein in the level shift circuit 10 shown in FIG. 3, the gates of the first and second p-channel MOSFETs 3 and 4 making up the flip-flop FF are connected to 30-V (Vcc) high-voltage power supply via voltage regulation diodes D1 and D2 for diode clamper.
Assuming that the Zener voltage Vz of these voltage regulation diodes D1 and D2 is about 3 V, if the first n-channel MOSFET 1 is closed, the drain node N1 does not fall below Vcc-Vz=about 27 V because of voltage clamp of the voltage regulation diode D2, and the gate-to-source, gate-to-drain, and gate-to-substrate voltages of the second p-channel MOSFET 4 are placed within 3 V. Likewise, if the second n-channel MOSFET 2 is closed, the drain node N2 does not fall below about 27 V either because of voltage clamp of the voltage regulation diode D1, and the gate-to-source, gate-to-drain, and gate-to-substrate voltages of the first p-channel MOSFET 3 are placed within 3 V. The gate-to-source and gate-to-substrate voltages of the MOSFET 5 at the output stage are also placed within 3 V. The gate voltage resistance of the MOSFET 5 at the output stage as well as the MOSFETs 3 and 4 of the flip-flop FF needs only to be 3-V voltage resistance. Since 3 V or more is applied as the source-to-drain voltages of the switch MOSs 1 and 2 and the MOSFET 5 at the output stage, high-voltage resistance MOSFETs of an offset gate structure, etc., having a low-concentration drain region (circled in FIG. 4) are used for the MOSFETs 1, 2, and 5.
By the way, in the level shift circuit 10 shown in FIG. 3, in the stable (stationary) state of the flip-flop FF, current is not consumed on the principle except leakage current of the switch MOS 1 or 2 (saturation current of p-channel MOSFET 3 or 4), and only a minute through current flows into a 2-stage series circuit in the transition process of the flip-flop FF. Therefore, low power is consumed. On the other hand, in the level shift circuit 20 shown in FIG. 4, in the process in which the first switch MOS 1 is closed, the current which should be allowed to flow into the first switch MOS 1 is such a breakdown current to cause Zener voltage Vz to occur in the diode D2 more than the saturation current flowing into the first p-channel MOSFET 3 closed in the immediately preceding stable state (write current for placing the storage node N1 in low level), and in the process in which the second switch MOS 2 is closed, the current which should be allowed to flow into the second switch MOS 2 is equal to or greater than the sum of such a breakdown current to cause Zener voltage Vz to occur in the diode D1 more than the saturation current flowing into the second p-channel MOSFET 4 closed in the immediately preceding stable state (write current for placing the storage node N2 in low level) and a charge current to charge source-to-gate capacity (gate capacity) C5 of the p-channel MOSFET 5 at the output stage. After the first switch MOS 1 shifts to the stable state of the closed state of the MOS 1, the current which should be allowed to flow into the first switch MOS 1 may be a minute current (hold current) sufficient for the diode D2 to hold the Zener voltage Vz. After the second switch MOS 2 shifts to another stable state of the closed state of the MOS 2, the current which should be allowed to flow into the second switch MOS 2 may be a minute current (hold current) sufficient for the diode D1 to hold the Zener voltage Vz.
However, in the circuit configuration in FIG. 4, after the first switch MOS 1 reaches the stable state of the flip-flop FF of the closed state, the current of the same value as that at the state transition time of the MOS 1 still continues to flow into the first switch MOS 1, and after the second switch MOS 2 reaches another stable state of the flip-flop FF of the closed state, the current of the same value as that at the state transition time of the MOS 2 still continues to flow into the second switch MOS 2. Thus, large power is consumed.
Then, the present applicant proposes a level shift circuit 30 comprising drain current variable circuits 32 and 34 shown in FIG. 5. This level shift circuit 30 has source resistors R11 and R12 in series making up a source follower circuit (constant current circuit) together with the first n-channel MOSFET 1 operating in a non-saturation region, an n-channel MOSFET 6 for changing source resistance value for short-circuiting the source resistor R12, a one-shot circuit (monostable multivibrator) 7 for applying a change time limit pulse P1 of predetermined pulse width .DELTA.T1 to a gate of the MOSFET 6 at time t1 at which logic input signal VIN rises, source resistors R21 and R22 in series making up a source follower circuit (constant current circuit) together with the second n-channel MOSFET 2 operating in a non-saturation region, an n-channel MOSFET 8 for changing source resistance value for short-circuiting the source resistor R22, and a one-shot circuit 9 for applying change time limit pulse P2 of predetermined pulse width .DELTA.T2 (=.DELTA.T1) to a gate of the MOSFET 8 at time t2 at which logic input signal VIN falls, in the level shift circuit 20 shown in FIG. 4.
The first n-channel MOSFET 1, the source resistors R11 and R12, the n-channel MOSFET 6 for changing source resistance value, and the one-shot circuit 7 make up the first drain current variable circuit 32. The second n-channel MOSFET 2, the source resistors R21 and R22, the n-channel MOSFET 8 for changing source resistance value, and the one-shot circuit 9 make up the second drain current variable circuit 34.
At the time t1 of the state transition process of the flip-flop FF at which the logic input signal VIN rises, the MOSFET 6 is held closed only for the .DELTA.T1 time as the change time limit pulse P1 occurs. Thus, only the resistor R11 serves as the source resistors of the first n-channel MOSFET 1, causing drain current ID1 flowing into the first n-channel MOSFET 1 to increase rapidly. After the expiration of the .DELTA.T1 time, the MOSFET 6 is opened and the resistor R12 is connected to the resistor R11 in series, thus the drain current ID1 flowing into the first n-channel MOSFET 1 is decreased rapidly and is restored to a minute current. At the time t2 of another state transition process at which the logic input signal VIN rises, the MOSFET 8 is held closed only for the .DELTA.T2 time as the change time limit pulse P2 occurs. Thus, only the resistor R21 serves as the source resistors of the second n-channel MOSFET 2, causing drain current ID2 flowing into the second n-channel MOSFET 2 to increase rapidly. After the expiration of the .DELTA.T2 time, the MOSFET 8 is opened and the resistor R22 is connected to the resistor R21 in series, thus the drain current ID2 flowing into the second n-channel MOSFET 2 is decreased rapidly and is restored to a minute current. Thus, the drain currents ID1 and ID2 of the first and second n-channel MOSFETs become each rapidly increased drain current IMAX in the transition process of the flip-flop FF and power-saving drain current (static mode current) IMIN in the stable state, thus contributing to the reliable state transition and reduction in power consumption.
By the way, if the level shift circuit 30 in FIG. 5 is viewed as a dynamic circuit, in the configuration in which the power p-channel MOSFET 5 at the output stage is connected to either of drain nodes N1 and N2 of the flip-flop FF, the large source-to-gate capacity C5 can be assumed to be connected to one of the nodes. Thus, the scale of the elements and signal change timing symmetry in the level shift circuit 30 are lost inevitably.
That is, as shown in FIG. 5, when the gate of the p-channel MOSFET 5 at the output stage is connected to the drain node N2, if the first n-channel MOSFET 1 is closed at the time t1 and the second n-channel MOSFET 2 is opened, the second p-channel MOSFET 4 is closed. This second p-channel MOSFET 4 is built in, the chip as a comparatively large-scale element to rapidly discharge the source-to-gate capacity C5. Thus, it is a large element as compared with the first p-channel MOSFET 3 and a source-to-gate capacity C4 that cannot be ignored is parasitic on the second p-channel MOSFET 4 inevitably.
As a result, if the second n-channel MOSFET 2 is closed at the time t2 at which the logical input signal VIN falls and the first n-channel MOSFET 1 is opened, the voltage of the drain node N1 is hard to rise because of the source-to-gate capacity C4 at the beginning and the second n-channel MOSFET 2 still remains closed. Thus, almost all of the rapidly increased drain current IMAX flowing into the second n-channel MOSFET 2 at the state transition time passes through the second p-channel MOSFET 4 as a reactive current and is hard to flow through the voltage regulation diode D1 and on resistance of the second n-channel MOSFET 2 of comparatively large element scale is low. Therefore, falling of the gate voltage of the first p-channel MOSFET 3 (voltage of drain node N2) is delayed. Thus, the MOSFET 3 is closed after a time lag and Vcc voltage it is supplied to the node N2. However, the gate voltage of the second p-channel MOSFET 4 does not immediately rise because of the discharge time of the source-to-gate capacity C4, and is opened behind the time at which the second n-channel MOSFET 2 is closed.
As shown in FIG. 6, the rapidly increased drain current IMAX flows as a reactive current Q1 at the time interval between the time t2 at which the logic input signal VIN falls and the second n-channel MOSFET 2 is closed and the time t21 at which the second p-channel MOSFET 4 is opened. Likewise, the rapidly increased drain current IMAX also flows as a reactive current q1 at the time interval between the time t1 at which the logic input-signal VIN rises and the first n-channel MOSFET 1 is closed and the time t11 at which the first p-channel MOSFET 3 is opened. However, since the gate capacity of the first p-channel MOSFET 3 can be ignored, the time interval between the time t1 and the time t11 is fairly short as compared with the time interval between the time t2 and the time t21 and the reactive current q1 is also fairly short as compared with the reactive current Q1.
When the opening time of the second p-channel MOSFET 4, t21, is reached, all the rapidly increased drain current IMAX flowing into the second n-channel MOSFET 2 at the state transition time flows effectively through the voltage regulation diode D1, thus the voltage of the drain node N2, VOUT, falls by Zener voltage VZ from the power supply voltage Vcc and charging of the source-to-gate capacity C5 is first started.
Although short-circuit discharge is a moment as the second p-channel MOSFET 4 is closed, the source-to-gate capacity C5 is charged (charge amount Q2) with a comparatively large time constant corresponding to the product of the large capacity C5 and resistance of the source follower circuit containing the second n-channel MOSFET 2. Thus, the voltage of the drain node N2, namely, the output signal VOUT falls moderately in an exponential waveform. As a result, the turn-on time of the p-channel MOSFET 5 at the output stage, TON, is prolonged and is unbalanced with the turn-off time TOFF; the p-channel MOSFET 5 at the output stage has a poor switching characteristic.
To resolve the imbalance between the turn-on time TON and the turn-off time TOFF, the element area of the second n-channel MOSFET 2 itself can be formed on a large scale as compared with the first n-channel MOSFET 1 for increasing the current capacity to further increase the rapidly increased drain current IMAX flowing into the second n-channel MOSFET 2 at the state transition time to rapidly charge the source-to-gate capacity C5 from the time t21. This leads to an increase in the chip size, causing the cost of manufacturing a semiconductor integrated circuit to rise. In addition, the following imperfections on the operation can be pointed out:
(1) If the current capacity of the second n-channel MOSFET 2 itself is increased for rapidly charging the source-to-gate capacity C5 as described above, charging of the gate capacity C5 is not started until the opening time of the second p-channel MOSFET 4, t21, is reached. Thus, the turn-on time is made longer than the turn-off time by the charge time interval t21-t23, and the switching speed is slow. PA1 (2) If furthermore large rapidly increased drain current IMAX' (>IMAX) is caused to flow into the second n-channel MOSFET 2 at the state transition time, as shown in FIG. 6, to rapidly charge the source-to-gate capacity C5 of the p-channel MOSFET 5 at the output stage, the rapidly increased drain current IMAX' must be previously allowed to flow as a further large current through 2-stage series circuit (reactive current) Q1' at the time interval between the time at which the second n-channel MOSFET 2 is closed (the logic input signal VIN rises), t2, and the time at which the second p-channel MOSFET 4 is opened, t21. Thus, the reactive current increases and power consumption grows. PA1 (3) Because of current value variable circuit of time limit change type, the time limit for changing from the rapidly increased drain current IMAX to the power-saving drain current IMIN (time t11, time t23) depends uniformly on the pulse width .DELTA.T1, .DELTA.T2 of the change time limit pulse P2 by the one-shot circuit 7, 9. If the pulse width is too short, a change is made to the decreased drain current IMIN before the voltage of the node N1, N2 rises or falls sufficiently. As a result, the rising or falling is further delayed and the transition time (turn-on time, turn-off time) is prolonged. If the pulse width is too long, the rapidly increased drain current IMAX continues to flow unnecessarily still after the voltage of the node N1, N2 rises or falls sufficiently, thus power consumption increases. In fact, however, variations in element characteristics, temperature characteristic, etc., must be considered to set the pulse width .DELTA.T1, .DELTA.T2 on the long side. Therefore, power consumption grows at the state transition time.
Before it, a time lag occurs by the time the second p-channel MOSFET 4 is opened because of the source-to-gate capacity C4 parasitic on the second p-channel MOSFET 4. Thus, the turn-on time is prolonged as long as the time lag as compared with the turn-off time and is unbalanced with the turn-off time.
Therefore, a trade-off exists between improvement in the switching speed by shortening the turn-on time in (1) above and reduction in the reactive current at the state transition time.


Frequency of unnecessary face detection operations performed in a photographing apparatus is reduced, thereby reducing the power consumption by the face detection operations. A determining unit determines whether or not a photographing condition of the photographing apparatus satisfies a precondition for efficiently using a result of detection by a detecting unit, which detects an image representing a face from images taken through the imaging lens of the photographing apparatus. A controlling unit exerts control such that, if it is determined that the photographing condition of the photographing apparatus satisfies the precondition, the detecting unit carries out the detection, and if it is determined that the photographing condition of the photographing apparatus does not satisfy the precondition, the detecting unit does not carry out the detection.

1. Field of the Invention
The present invention relates to a photographing method and a photographing apparatus, which take a subject's image focused on an imaging surface through an imaging lens.
2. Description of the Related Art
Digital cameras, which detect an image representing a human face from taken images to automatically focus on the subject's face or to automatically change the zoom magnification so that the area representing the face in the detected image is enlarged, have been known (see Japanese Unexamined Patent Publication No. 2004-320286).
For use with such digital cameras, a method for automatically focusing on a subject's face, in which images for photographing conditions setting are taken when the shutter button is half pressed, and an image representing the face is detected from the images to focus on the face, has been known.
A digital camera using a "continuous face detection method" has been known. In the continuous face detection method, face detection for detecting an image representing a face from images taken for monitoring is constantly carried out even when the shutter button is not touched. Then, when a face is detected, the face is automatically focused. According to this method, the digital camera can be operated so that the face detection is always carried out and the detected subject's face is focused regardless of the operational state of the shutter button. Therefore, the display monitor can display images taken with the subject's face being always focused on, and photographing for recording an image (hereinafter may be referred to as "actual photographing") can be carried out with no waiting time.
Further as a mechanism for focusing on the face, an AF (automatic focus) mechanism using a contrast detection method has been known. In the contrast detection AF mechanism, images are taken while the focusing lens group is moved within its operation range, and the image having the maximum contrast, i.e., having the maximum focus evaluation value, is found from the images. Then, the focusing lens group is set at the position where the image with the maximum contrast has obtained (see Japanese Unexamined Patent Publication No. 2004-320286).
Since a large amount of image processing is carried out in the above-described face detection operation, power consumption by the face detection operation is also large in proportion to the amount of processing. Frequent use of the face detection will result in early depletion of the battery power for driving the digital camera. Therefore, there are demands for reduction of power consumption by the face detection operation.
The face detected in the face detection operation is photographed (actual photographing) and recorded in a memory or the like. Thus recorded images may include unnecessary images containing a blurred face(s) due to, for example, movement of the hand holding the camera. Therefore, there are also demands for avoiding the face detection under conditions where unnecessary images will be photographed even with use of the face detection function, that is, under conditions where the face detection function is not efficiently used.

Photographing method and photographing apparatus based on face detection and photography conditions


A bit synchronizing circuit that provides highly reliable data transmission at a high speed is provided. The circuit facilitates testing by using a plurality of clock signals that are generated based on a reference clock signal, each of the clock signals having unique phases. The circuit selects one of the clock signals as a writing clock signal that is suitable for a clock signal for synchronizing serial data, based on a synchronous timing signal. The synchronous timing signal is generated based on an edge signal that is generated based on an edge position of serial data. The edge position is determined for a plurality of groups of the clock signals, each group including clock signals chosen every predetermined number of the clock signals.

1. Field of the Invention
The present invention generally relates to a bit synchronizing circuit used in high-speed serial communications and a semiconductor device therewith.
2. Description of the Related Art
As widely known, data are generally transmitted and received by using a reference clock of the same frequency in high-speed serial communications, wherein a transmission speed of a transmission side and a reception speed of a receiving side are mutually predetermined. In order that the receiving side correctly receive the data transmitted from the transmission side, both sides need to operate synchronously. Although there is a method of supplying a clock signal for synchronizing with a data signal to the transmission and receiving sides, there are problems, such as signal wave distortion, reflection, interference in a cable, and interference in a board if the method is applied to recent high-speed serial communications at a clock speed of hundreds of MHz or tens of GHz. For this reason, redundant bits are added to the data signal on the transmission side, encoded such that transition of the data signal is secured at a fixed interval, and transmitted, instead of sending the clock signal used for communications apart from the data signal. On the reception side, since the data sent from the transmission side include timing information, the data are usually sampled, and excessive bits are decoded after the sampling.
For example, in the case of data that are NRZ (non-return to zero) encoded on the transmission side, the receiving side is required to generate a synchronous clock signal for data sampling by using a bit synchronizing circuit such that the data are correctly received. Therefore, a clock of a frequency higher than the transmission speed is supplied to the bit synchronizing circuit, and a circuit is constituted so that the synchronous clock is generated, the clock falling in the center of the data. Recently, the transmission speed of the serial communications interface has become up to hundreds of Mbps to several Gbps, and in order to realize the high-speed and highly reliable communications, the bit synchronizing circuit is required to provide high-performance and high reliability of the communications.
A conventional bit synchronizing circuit 100 used in high-speed serial communications is shown in FIG. 10. A reference clock signal REFCLK and a data input signal SDIN are provided to the bit synchronizing circuit 100. A phase comparison clock generation circuit 110 generates a bit operation clock signal (not shown in FIG. 10) of the frequency corresponding to the transmission speed from the reference clock signal REFCLK, and a total of eight clock signals CLK1-CLK8, each having different phases, are further generated based on the bit operation clock signal.
FIG. 11 is a timing chart of the reference clock signal, the bit operation clock signal, and the clock signals CLK1-CLK8 generated based on the bit operation clock signal. Each of the clock signals CLK1-CLK8 has a phase that is ⅛ cycle shifted in comparison with respective adjacent clock signals. Each of the clock signals CLK1-CLK8 is supplied to an input data edge detection unit 120 and a clock selection unit 140 via a route independent of other clock signals.
The input data edge detection unit 120 detects edge signals EDGE1-EDGE8, as a result of the data input signal SDIN and the clock signals CLK1-CLK8 with different phases being input. The edge signals EDGE1-EDGE8 are supplied to a clock judging (determining) unit 130. In the clock judging unit 130, a clock selection signal CKSL is generated from the edge position recognized based on the edge signals EDGE1-EDGE8. The clock selection signal CKSL and the clock signals CLK1-CLK8 are supplied to the clock selection unit 140.
In the clock selection unit 140, a clock signal for writing WRCK is generated, which is a clock signal for data sampling for a buffer 150 such as an elasticity buffer, based on the clock signals CLK1-CLK8 and the clock selection signal CKSL supplied.
The buffer 150 consists of a multi-bit FIFO or of single bit flip-flops, or many bits, and is for absorbing deviation in the frequency that is arranged beforehand by the transmission and reception sides and clock jitter. Generally in serial communication, an asynchronous FIFO, the width of which is one bit, and depth ranges from several bits to dozens of bits is used. A synchronized data SDOUT is output from the buffer 150, which is read by a circuit of the next stage, and is processed as received data.
FIG. 12 shows a configuration of the input data edge detection unit 120. The input data edge detection unit 120 includes data flip-flops (hereinafter called flip-flop) 121a-121h corresponding to the eight clock signals CLK1-CLK8, respectively, each of which is in a phase different from the others, and exclusive OR (EXOR) gates 122a-122h, quantity of which is the same as the flip-flops 121a-121h. The flip-flops 121a-121h receive the corresponding clock signals CLK1-CLK8, respectively, and the serial data input signal SDIN. Further, each of output signals DFF1-DFF8 from the flip-flops 121a-121h, respectively, is supplied to two EXOR gates. For example, the output of flip-flop 121b is supplied to the EXOR gates 122a and 122b, the output of flip-flop 121c is supplied to the EXOR gates 122c and 122b, and a flip-flop 121h output is supplied to the EXOR gates 122h and 122a.
Each of the EXOR gates 122a-122h outputs a signal (henceforth an edge signal) EDGE12, EDGE23, EDGE34, EDGE45, EDGE56, EDGE67, EDGE78, and EDGE89, respectively, which indicates edge position. An edge signal becomes "HIGH" when the data input signal SDIN changes at the timing of the phase difference of the two clock signals that are input. For example, the signal output from the EXOR gate 122a becomes "HIGH" when a data input signal changes at the timing of the phase difference of CLK1 and CLK2. The edge signals EDGE12-EDGE89 output from the EXOR gates 122a-122h are supplied to the clock judging unit 130 via independent routes.
Here, the number of clock signals having different phases is set at eight, however, the number may be different. Further, edge detection may be performed not by different phases but by a clock signal of a frequency higher than the transmission speed.
FIG. 13 is a timing chart of various signals related to the output timing of the clock signal WRCK for writing to buffer 150. As shown in FIG. 13, the first edge (rising edge) of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK1 and the edge (rising edge) of CLK2; the second edge (falling edge) of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK2 and the edge (rising edge) of CLK3; further, the third edge of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK3 and the edge (rising edge) of CLK4; and, furthermore, the last edge (falling edge) of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK2 and the edge (rising edge) of CLK3.
If an edge of the data input signal SDIN is detected, the detection pulse of a long period is output as a corresponding edge signal EDGE12-EDGE89. Based on the long detection pulse, CLK1 is output to EDGE12, the phase of CLK1 being about a half cycle late for sampling at the center of the input data. Similarly, CLK2 is output to EDGE23 as a synchronous timing signal, and CLK3 is further output to EDGE34. If there is no transition of edge in the synchronous timing signal and its cycle, the same clock as the previous cycle is output. Finally, the clock signal for writing WRCK to be output to the buffer 150 is generated.
Here, since the configuration after the input data edge detection unit 120, i.e., the operation of the timing of the clock judging unit 130, and the clock selection unit 140 shown in FIG. 12, are publicly known, an explanation thereabout is not presented.
Next, with reference to FIG. 14, a problem that may arise in the conventional bit synchronizing circuit 100 is explained. First, in order that the flip-flops 121a-121h operate normally, it is necessary to keep input data constant (setup hold) for a predetermined period before and after a clock. If the input data are not held to fixed values during the predetermined period, there is a possibility that output signals DFF1-DFF8 from the flip-flops 121a-121h become uncertain, i.e., neither 1 nor 0. This phenomenon is called "meta-stability". At the place where mark A″ is shown in FIG. 14, the output signal DFF2 from the flip-flop 121b should be "HIGH", however, the output signal DFF2 is in the meta-stable state, because the data input signal SDIN changes, and does not fill the setup hold timing requirement of the flip-flop 121b. Here, in FIG. 14, an example is shown where the level of the output signal DFF2, which is in the meta-stable state, shifts as the solid bold line indicates.
Further, at the place where mark B″ is given in FIG. 14, the output signal DFF6 from the flip-flop 121f should be "LOW". However, the output signal DFF6 becomes "HIGH" in the case that the data input to the flip-flop 121f delay because of manufacturing problems such as the input resistance of the flip-flop 121f for the SDIN being extraordinarily high, there being cross talk in the signal line relative to the flip-flop 121f, and timing variation due to manufacturing of the semiconductor device.
When a fault occurs in the output signal of the flip-flops, such as shown by the places marked by A″ and B″, correct generation of the clock signal for writing to buffer WRCK 150 cannot be attained. Depending on the configuration of the circuit, the signal is not output at the original timing, and a timing error occurs at sampling by the buffer 150, resulting in, e.g., lack of WRCK that causes data dropping, and generation of plural WRCK signals in one cycle that causes retrieving too many bits. With reference to FIG. 14, errors of the synchronous timing signal and the clock signal WRCK occur at the places marked by C″ and D″, respectively. The errors cause erroneous reception of the serial data.
It is generally known that the meta-stability degrades the reliability of the bit synchronizing circuit, in addition to the problem of variations in the characteristics due to manufacturing, and a fault of a flip-flop used by the edge detection unit in the bit synchronizing circuit, etc. Since the meta-stability causes an erroneous operation, it is required that the meta-stability occurring be prevented, and a bit synchronizing circuit that is meta-stability proof be provided in order to raise the reliability of the circuit.
When a bit synchronizing circuit is built in a semiconductor device, testing of the device is performed by using an LSI tester, wherein a signal that is synchronous to a predetermined timing is input to the device, and a signal output from the device is measured and compared with an expected value. Then, if the output is similar to the expected value, the device passes the test. Otherwise, the device is considered a reject. However, in the case of a bit synchronizing circuit that operates serial data asynchronously at a high speed, a large number of asynchronous input patterns to a system clock have to be prepared on the LSI tester. Further, even if an acceptable device is tested by using the asynchronous input patterns, the receiving data sometimes differs from the expected value in cycles by the input of the asynchronous signal. Furthermore, the difference in data can be subject to variations in manufacturing the semiconductor device. For these reasons, debugging and completing a test program that is capable of accurately selecting acceptable devices from rejects takes a long time. Accordingly, a technology that copes with these problems is wanted.
Conventionally, the following bit synchronizing circuits are known. For example, JPL 7-193562 discloses a totally digital bit synchronizing circuit that is capable of handling high speed communications without using a counter. Although the patented circuit employs a general-purpose clock multilayer circuit or a D flip-flop, as does the present invention, the patented circuit uses only one edge detection unit, resulting in unreliable operations when the flip-flop in the bit synchronizing circuit meets a meta-stable state, which is a cause of faulty operations.
Further, JPL, 9-36849, A discloses a bit synchronizing circuit and a bit synchronous method that realize optimal sampling of input data, the duty rate of which fluctuates, by detecting a rising edge and a falling edge of a signal from a data sampling unit, which is a component of the bit synchronizing circuit, and is for sampling an incoming signal and arranging the sampled signal into an n series of signals, another component thereof being a selection output unit for selecting a signal that is synchronized with a received burst signal out of the sampled n series of the signals. However, since this bit synchronous method uses both edges where a data value changes, there is a problem that the sampling cannot be performed at a high speed. Further, since only one circuit is used for detecting the edges, when the flip-flop of the bit synchronizing circuit comes to a meta-stable state, faulty operations occur, producing a problem of degraded reliability.
Furthermore, JPL, 10-247903, A discloses a bit synchronizing circuit that complies with a high-speed burst signal that is sporadically generated, input timing of which is uncertain, and complies with phase fluctuation without using a high-speed clock that exceeds receiving data speed. However, this circuit uses only one phase comparison circuit, and therefore, lacks reliability.

Bit synchronizing circuit configured to obviate errors from meta-stability


A belt conveyor or belt accumulator includes at least two tandem zones, each of which is defined by a motorized roller and at least one idler roller positioned along and between opposite sidewalls of the conveyor and a continuous belt routed around the motorized roller and the idler roller or rollers. The motorized roller is operable to drive the belt around the rollers to move articles along the respective zone. The belt may have a low modulus characteristic and may be initially stretched at least 0.75% in its lengthwise direction when the belt is reeved or routed around the rollers. The motorized roller of each zone may be independently operable, such as in response to an article sensor at each zone, to convey or accumulate articles on the respective zone of the belt conveyor.

It is known to provide zones of rollers along a roller conveyor, where each zone includes a motorized roller and a plurality of idler or freely rotating rollers. The motorized roller is typically operable to drive the idler rollers via a plurality of O-rings connecting each roller to an adjacent roller in the zone. Each zone may be independently operable to accumulate articles on a particular zone or zones or to generally continuously convey articles along the zones of the roller conveyor. However, such roller conveyors are not suitable for certain applications where belt conveyors are desired, such as for conveying small articles which may fall between the rollers or for applications where a belt conveyor may be required or desired for other reasons. Also, due to the low friction between the rollers and the articles being conveyed thereon, such roller conveyors are not suitable for providing accumulation of articles along an inclined or declined section of the roller conveyor.
Also, it is known to provide an angled discharge junction or connecting conveyor section at a discharge conveyor or station of a sorting system. The discharge junctions typically comprise a plurality of different length rollers rotatably mounted between a sidewall of the junction and an angled mating or connecting frame, such that the rollers are positioned in an ascending length order to define an angled mating edge or connection at the sorting system conveyor or transport path. The rollers are typically freely rotating rollers and function to transport articles from the transport or sorting system to a discharge conveyor or station at the opposite end of the angled junction. Articles are discharged from the transport system and may coast over the different length rollers and onto the discharge conveyor or station. It is also known to provide angled belted conveyor sections where a continuous belt is reeved around rollers and is operable to induct or discharge articles at a main conveying path or transport path. However, such angled belted conveyor sections typically include complicated routing paths for the belt beneath the conveyor section to properly align and track the belt around an end roller at the angled mating edge of the angled belted conveyor section.


The present invention relates to isolated nucleic acid sequences encoding polypeptides having protease activity, in which the polypeptides are obtainable from an alkalophilic Bacillus species having enhanced stability towards bleaching agents of the peroxy type. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the nucleic acid sequences as well as recombinant methods for producing the polypeptides.

1. Field of the Invention
The present invention relates to isolated nucleic acid sequences encoding polypeptides having protease activity, in which the polypeptides are obtainable from an alkalophilic Bacillus species having enhanced stability towards bleaching agents of the peroxy type. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the nucleic acid sequences as well as recombinant methods for producing the polypeptides.
2. Description of the Related Art
Detergents formulated with proteolytic enzymes are known to have improved properties for removing stains. For example, SAVINASE.TM. (Novo Nordisk A/S, Bagsvaerd, Denmark), a microbial protease obtained from Bacillus lentus has been introduced into many commercial brands of detergent.
WO 88/01293 discloses proteases obtained from an alkalophilic Bacillus species having enhanced stability towards bleaching agents of the peroxy type.
JP 1497182 discloses a DNA encoding an alkali protease Ya enzyme from Bacillus which is said to have good alkali and surfactant resistance and improves detergency.
Many detergents are alkaline in solution (e.g., around pH 10). There is a need for new proteolytic enzymes with high activity at high pH which are stable towards bleaching agents. Proteases of the type disclosed in WO 88/01293 possess these characteristics, and therefore, are highly desirable for use in detergent compositions. Heretofore, however, there has been no means of producing these enzymes recombinantly.
It is an object of the present invention to provide for recombinant production of these valuable enzymes.

Nucleic acids encoding a polypeptide having protease activity


The aid comprises a channel including a central web and flanges extending in a first direction, the channel is formed with a fin extending in a second direction opposite the first direction. The fin has at least one finger opening therein. The usual nail clipper is mounted in the channel with the operating lever extending away from the aid so that it is readily operable.

Nail clippers utilizing a pair of leaf spring elements secured together at one end and having cutting edges at the other end are well known. Usually a fulcrum post is rotatably mounted on one of the elements adjacent its cutting edge and extends through the other element for support of a fulcrum lever used to move the cutting edges toward each other to produce cutting.
Attempts have been made in the past to provide structure or accouterments for such clippers so that they will be easier to use. An example is the Tottenham U.S. Pat. No. 5,384,960 wherein rings are provided on the ends of the lever and the spring elements, the rings being adapted to receive the fingers or thumb of the user to improve the grip.
U.S. Pat. No. 3,744,131 to Manes discloses a clipper having a finger hook and thumb piece on the respective lever and cutting element.
Rommerdale U.S. Pat. No. 5,052,416 discloses molded plastic attachments for the lever and a clipping element to make them easier to use.
Sartore U.S. Pat. No. 3,997,966 proposes scissor-like thumb and finger handles to make the apparatus easier to use and direct.
While these improvements provide some help, no one of them permits the involvement of the entire hand to hold and operate the clipper. With such involvement, as I now provide, the clipper is much easier and more comfortable to direct and operate.


A stroller is convertible between an unfolded state and a folded state, and includes a handle frame disposed pivotally on a wheel frame and pivotable between an inclined position and a horizontal position. A brace member interconnects the handle frame and the wheel frame, and is convertible between a supporting state, where the handle frame is disposed at the inclined position and where the stroller is in the unfolded state, and a non-supporting state, where the handle frame is disposed at the horizontal position and is folded on the wheel frame and where the stroller is in the folded state. A retaining unit maintains the stroller in the folded state, and allows for a one-touch operation so as to permit the handle member to be biased by a biasing unit to the inclined position.

1. Field of the Invention
This invention relates to a stroller, and more particularly to a foldable stroller.
2. Description of the Related Art
Typically, to unfold a stroller after it is folded, the user needs to operate the stroller with both hands. This results in a troublesome unfolding process.


Access authorization is validated for an information processing system wherein a "slave device" such as a terminal desires access to information contained in or controlled by a "master device" such as a computer. Apparatus associated with the slave device receives validation data from the master device, modifies it according to a pre-determined algorithm implemented through logical circuitry in the apparatus, and returns the resulting "convoluted" data to the master device. The same validation data is convoluted in the master device through mathematical implementation of the algorithm. If the two sets of convoluted data match, it is presumed that the slave device is authorized to access information through the master device.

Information security is a major concern relating to information processing systems. Many approaches have been conceived to prevent unauthorized access to sensitive, confidential, or proprietary data, programs, or operations.
These approaches range from simple, physical control to complex and highly sophisticated electronic implementations of mathematical techniques. A summary of prior art techniques follows; these are shown in order of generally increasing complexity:
physical control PA0 electronic lock PA0 identification PA0 transmission coordination PA0 transmission security
mechanically locked enclosure or facility PA1 key-operated switch PA1 user must have proper program or data media PA1 plug-in access module PA1 key-pad whose keys must be depressed in specific sequence PA1 computer queries device for electrical identification code PA1 user enters personal name, code name, or password PA1 access card with magnetic or optical card identification PA1 computer verifies user's physical characteristic (e.g., fingerprint, voice, typing pattern) PA1 transmitting or receiving device signals or requests data transfer PA1 receiving device confirms receipt for transmission to continue PA1 data encoding: received data must be decoded (e.g., conversion of ASCII codes to alphanumeric characters) PA1 data encryption: received data must be decrypted (e.g., character substitution) PA1 data scrambling received data must be filtered and re-assembled (e.g., data manipulation and removal of extraneous data) PA1 input devices (keyboards, terminals, card readers, etc.) PA1 output devices (printers, plotters, displays, monitors, etc.) PA1 storage devices (disk units, tape units, etc.) PA1 other computers (work stations, remote computers, etc.) PA1 communication devices connected to other slave devices
Physical control, electronic locks, identification, and transmission coordination restrict access to the devices, data, programs, or operations. Transmission security does not necessarily preclude access to information, but data is not meaningful unless processed properly.
It has been demonstrated that no single nor combination of approaches or implementations can provide total security; at best, the amount of time, effort, or cost to gain unauthorized access is so great that it provides an effective deterrent.

Method and apparatus for validating authorization to access information in an information processing system


A stencil plate having a heat sensitive stencil paper sheet formed of a thermoplastic film and a porous support member, a non-woven fabric impregnated with ink, a frame member disposed so as to surround the non-woven fabric, an ink-impermeable film, and a peelable surface film having a high temperature heat resisting property that is superior to the thermoplastic film. The surface film may be a peelable member or there may be a peelable member adhered to the surface film so as to peel both, the peelable member having a projecting portion. When the projecting portion which projects from a frame member, is gripped and pulled, the surface film on a stenciled face, is gradually peeled away and removed from the stenciled face so that a heat sensitive stencil paper sheet in the stenciled condition is exposed.

1. Field of the Invention
This invention relates to a stencil plate.
2. Description of the Related Art
Heat sensitive stencil paper sheets which can be perforated by irradiation of infrared rays or by means of a thermal head are conventionally known. A typical one of the conventional heat sensitive stencil paper sheets includes a heat sensitive film and a porous thin paper sheet adhered to the heat sensitive film using a bonding agent. A stencil paper printing apparatus using a single cylinder, such as shown in FIG. 8, is known for using this described conventional heat sensitive stencil paper sheet. Referring to FIG. 8, the stencil paper printing apparatus includes a plate cylinder 62 which has a perforated photosensitive stencil paper sheet 64 wound on an outer periphery thereof with its porous support member positioned on the inner side. Ink is supplied from the inside toward the outer periphery of the plate cylinder 62. A press roller 66 is contacted under pressure with the plate cylinder 62 with printing paper 68 interposed therebetween while the plate cylinder 62 is driven to rotate to effect printing on the printing paper 68.
Shown in FIG. 9 is a second type of conventional stencil paper printing apparatus. Referring to FIG. 9, the stencil paper printing apparatus uses a heat sensitive stencil paper sheet 70 formed of a heat sensitive film. A porous support member 84 is adhered to the heat sensitive film and has a frame member 72 provided along a periphery of the porous support member 84. The porous support member 84 serves as an ink applying portion and is enclosed by the frame member 72 and an ink-impermeable cover sheet 74.
The stencil paper printing apparatus includes a pressing member 78, a receiving table 80 disposed in an opposing relationship to the pressing member 78, and a holding member 82 disposed at a peripheral portion of the face of the pressing member 78, opposed to the receiving table 80, for holding the heat sensitive stencil paper sheet 70 thereon. Ink is applied to the porous support member 84, surrounded by the frame member 72, of the perforated heat sensitive stencil paper sheet 70. Then the porous support member 84 and the frame member 72, attached on one side to heat sensitive stencil paper sheet 70, are covered with the cover sheet 74 on the opposite side prior to mounting on the pressing member 78. The heat sensitive stencil paper sheet 70 is held on the pressing member 78 by the holding member 82 and the pressing member 78 is moved toward, and pressed against, the receiving table 80 with printing paper 86 interposed therebetween to effect printing on the printing paper 86.
A stencil paper printing apparatus of the cylinder type described above has a large size. Since it can be used to print large stencils, it has a comparatively high running cost when required to print comparatively small amounts of material, i.e. only a small portion of the stencil has printing perforations.
On the other hand, the pressing type stencil paper printing apparatus has a comparatively small size. However, it has a disadvantage in that the user must apply the ink. Therefore, the hands or the clothes of the user may be soiled when the ink is applied and, since the ink is not readily applied with a uniform thickness, a regular print may not be obtained.
In order to improve the drawbacks of the conventional stencil paper printing apparatuses described above, the applicant of the present invention described, in Unexamined Japanese Patent Provisional Publication No. 4-166390 (published Jun. 12, 1992), a plate for stencil paper printing as shown in FIG. 10.
Referring to FIG. 10, the stencil plate 50 includes successive layers of a heat sensitive stencil paper sheet 56 formed of a thermoplastic film 52 and a porous support member 54 adhered to the thermoplastic film 52, a non-woven fabric 58 disposed on the heat sensitive stencil paper sheet 56 adjacent to the porous support member 54 and impregnated with ink, and an ink-impermeable film 59 serving as a base member. A perforation image is formed on the stencil plate 50 by heat melting the thermoplastic film 52 of the heat sensitive stencil paper sheet 56 by means of a stenciling apparatus which employs, for example, a thermal head. Such formation of a perforation image will be hereinafter referred to as stenciling.
The stencil plate 50, thus stenciled, is mounted onto a stamping member provided with a grip and the stamping member is pressed against printing paper to effect stencil paper printing.
However, with the stencil plate, when it is stenciled, for example, by means of a thermal head, a small amount of ink oozes from the perforation portions and, accordingly, there is the possibility that ink may stick to the thermal head and also to the face (printing face) of the thermoplastic film of the stencil plate.
A stencil plate which solves the above identified problem has been developed and is shown in FIG. 11. Referring to FIG. 11, the stencil plate 10 includes, as principal components thereof, a heat sensitive stencil paper sheet 12, a separator 14, a non-woven fabric 16 impregnated with ink, a frame member 18 disposed so as to surround the non-woven fabric 16, and an ink-impermeable film 20 serving as a base member.
The heat sensitive stencil paper sheet 12 includes, as shown in FIG. 13, a thermoplastic film 22, a bonding agent layer 24, and a porous support member 26. The thermoplastic film 22 is formed of a polyethylene terephthalate film (hereinafter referred to as PET film) approximately 2 .mu.m thick, but may alternatively be formed of a film of, for example, polypropylene or copolymer of vinylidene chloride-vinyl chloride. Preferably the PET film is 1 to 4 .mu.m thick. A thickness, of the PET film, of less than 1 .mu.m results in high production costs and does not provide sufficient strength. Accordingly, the PET film of such thickness is not suitable for practical use. The porous support member 26 is formed of thin porous paper which is made of, as a principal material, for example, natural fiber of Manila hemp, kozo (paper mulberry =Broussonetia kazinoki) or mitsumata (Edgeworthia papyrifera), synthetic fiber of polyethylene terephthalate, polyvinyl alcohol or polyacrylonitrile or semisynthetic fiber of rayon. The heat sensitive stencil paper sheet 12 structured as described above adheres, at four sides thereof, to the frame member 18 by means of a bonding agent layer 28 as shown in FIG. 12.
An opening 17 having a size corresponding to the size of the non-woven fabric 16 is formed at a central portion of the frame member 18 as shown in FIGS. 11 and 12. A small hole 19 for removing the separator 14 therethrough is formed at a right portion of the frame member 18 (as shown in FIGS. 11 and 12). Since the ink impregnated in the non-woven fabric 16 is an oil ink, the frame member 18 is made of a material which is not attacked by oil ink, such as, for example, vinyl chloride, polypropylene, polyethylene, polyacetal or polyethylene terephthalate.
The non-woven fabric 16 is impregnated, in a saturated condition, with the oil ink so that when a pressure is applied to it, the ink impregnated therein oozes from the non-woven fabric 16. The non-woven fabric 16 is made of a synthetic fiber of polyethylene, polypropylene or polyethylene terephthalate. Preferably the thickness of the non-woven fabric 16 is set greater than one half but smaller than three times the thickness of the frame member 18. Upon stenciling, while the heat sensitive stencil paper sheet 12 is moved by transporting the frame member 18, it is perforated by heat of a thermal head. Accordingly, if the thickness of the non-woven fabric 16 is excessively small, the heat sensitive stencil paper sheet 12 will sink into, upon stenciling, the inside of the frame member 18 and be moved out of contact with the thermal head thereby resulting in a failure to achieve complete perforation. On the other hand, if the thickness of the non-woven fabric 16 is excessively great, then it projects from the frame member 18 to be compressed against the thermal head. In this condition, the stencil plate 10 is prevented or hindered from being transported regularly by the frame member 18 during stenciling. Accordingly, because the stencil plate 10 is not transported properly in the predetermined pitch, or is transported obliquely due to the non-uniform thickness of the non-woven fabric 16, the perforations are improperly positioned. Preferably, the non-woven fabric 16 is set so that it is compressed, upon stenciling, by the pressing force of the thermal head so that it presents a thickness equal to that of the frame member 18.
The separator 14 is disposed between the heat sensitive stencil paper sheet 12 and the non-woven fabric 16. A portion thereof, shown in FIG. 12 as a right portion, extends through the small, oblong hole 19 formed in the frame member 18 and further between the frame member 18 and the film 20 to project beyond the end of the stencil plate 10.
The size of the separator 14 is set to be greater than the size of the non-woven fabric 16. More particularly, referring to FIG. 12, the area the separator 14 covers beyond the non-woven fabric 16 is defined by a chain line shown on the frame member 18. The separator 14 may be formed of mold separating paper produced by applying a silicon film to wood-free or glassine paper or of a resin film of polyethylene terephthalate or ethylene tetrafluoride (trade name: TEFLON). The material of the separator 14 is required to have the characteristic that it is low in wettability and, more particularly, the wetting angle is 45 degrees or more. Further, when mold separating paper or the like is employed, preferably a silicon film is formed not only on the face of the mold separating paper contacting the non-woven fabric 16 but also on the other face as well. When the wettability is high, or a silicon film is formed on only one face of the mold separating paper or the like, the ink may spread to the heat sensitive stencil paper sheet 12 side of the separator 14 and there is the possibility that, when perforations are formed, ink may ooze from the perforation portions.
The ink impermeable film 20, which serves as a base member, has a bonding agent layer 32 applied to an upper face (slanting line portion in FIG. 12) for adherence to the frame member 18 and the non-woven fabric 16. The film 20 is formed of a film of a resin which is not attacked by oil ink such as vinyl chloride, polypropylene, polyethylene or polyethylene terephthalate.
The stencil plate 10 described above is stenciled using a stenciling apparatus (not shown). Such a stenciling apparatus mirror-image prints the face of the thermoplastic film 22 of the heat sensitive stencil paper sheet 12 by means of a thermal head to heat the thermoplastic film 22 to melt and perforate same. When stenciling, the thermal head is pressed against the stencil plate 10 under a predetermined pressing force and, in this instance, since the separator 14 is disposed between the heat sensitive stencil paper sheet 12 and the non-woven fabric 16, even if the thermoplastic film 22 of the heat sensitive stencil paper sheet 12 is perforated, ink does not ooze from the perforation portions.
The stencil plate 10, stenciled in this manner, is mounted onto a stamping member 34 (shown in FIG. 14). The stamping member 34 consists of a handle portion 36, a cushion layer 38 and an adhesive layer 40. The stencil plate 10 is mounted onto the stamping member 34 by adhering the film 20 side of the stencil plate 10 to the adhesive layer 40 of the stamping member 34. Thereafter, the separator 14 (shown in FIG. 12) is pulled from the stencil plate 10. The stamping member 34 can then be pressed against a printing paper 42, whereupon the non-woven fabric 16 is compressed so that ink oozes from the perforated portions of the printing face of the stencil plate 10 and is transferred to the printing paper 42.
The conventional stencil plate 10, however, has several problems, such as the formation of irregular perforations caused by slippage between the separator 14, having a low wettability, and the heat sensitive stencil paper sheet 12 upon formation of an image on the heat sensitive stencil paper sheet 12, soiling of the thermal head of the perforating stenciling apparatus caused by ink oozing from an end face of the separator 14 to the heat sensitive stencil paper sheet 12 side, and the production of wrinkles in the heat sensitive stencil paper sheet 12 upon stamping caused by the admission of air between the non-woven fabric 16 and the heat sensitive stencil paper sheet 12 upon removal of the separator 14 after formation of an image.

Plate for stencil paper printing having a releasable film


A lighting apparatus includes a laser light modification unit for modifying laser light from a laser to form a modified light. The lighting apparatus further includes a first layer and an opposing second layer, where the laser light modification unit is between the first and second layers. One of these two layers includes a transparent material being transparent to the modified light. The laser light modification unit is configured to allow the modified light to pass through the transparent material.

US2006/0275599 A1 discloses a lighting apparatus having a layer of light-emitting diodes (LED) laminated between two layers of glass. This lighting apparatus is used for decorative as well as illumination purposes and can generate the impression of levitating light.
Such a lighting apparatus has the drawback that the illumination is limited by the power of the LEDs, i.e. it is not possible to use high power LEDs as the heat generated by LEDs often leads to the destruction of the glass.


A cone cake baking apparatus comprising: a horizontal baking tin having a plurality of circular openings, a vertical first side wall, and a vertical second side wall; and the first and second side walls each having a securing portion.

While it is well known in the prior art to utilize cup cake trays for baking cupcakes, the public domain does not contain an adequate apparatus for baking cone cakes. In particular, in order to cook a cone cake having a pointed bottom with available apparatus, it is necessary to fill the cone with cake material and place the cone cakes in a vertical position, lying down, on a cookie sheet. Moreover, while standard cupcake trays will more easily facilitate a flat bottom cone, baking such cones in cupcake trays often results in spillage or tipping of the cones during the baking process.


In order to improve the quality of cross-sectional images, which have been recorded along a longitudinal axis of a vessel of a body, it is proposed to add successive cross-sectional images to an overall cross-sectional image. Artifacts in the cross-sectional images are hereby weakened and pathological structures to be detected are high-lighted.

A device of this type is known from WO 97/32182 A1. The known device uses optical coherence tomography to produce cross-sectional images of vessels. In the simplest case, the probe unit of the device features a probe which represents the measuring arm of an interferometer. The probe unit further comprises a reference arm, the optical path length of which can be varied. Light, which features a short coherence length, is fed into both the reference arm and into the measuring arm. The light fed into the measuring arm passes through the probe and is guided to the vessel wall in the region of the probe tip which is located in the vessel to be examined. There the light in different tissue depths is reflected back to the probe tip, detected there and led back through the probe. The light passing back in the reference arm and in the measuring arm is superimposed and supplied to a detector. Modulation means are provided in the reference arm or in the measuring arm, by means of said modulation means the light can be modulated. When the light passing pack from the reference arm and from the measuring arm is interfered in the detector, the intensity detected by the detector is modulated by this modulation. Interference only occurs however when the optical path length of the light in the reference arm and in the measuring arm is approximately the same. By varying the optical path length in the reference arm across several coherence lengths, the photons reflected in each case in a specific tissue depth can result in interference. The probe can be designed such that a cross-sectional profile can be recorded in each instance at a position in the vessel. In the simplest case, this is effected by rotating the probe, with a depth profile being established in each instance in each angular position.
The processing unit arranged downstream of the probe unit then establishes a cross-sectional profile from the measuring signal supplied by the probe unit. As the probe is moved step-by-step through the vessel, the processing unit supplies a series of cross-sectional images one after the other.

Device for recording cross-sectional images


A data distribution system has a portable user terminal, which sends a portable terminal ID or memory card ID and electronic money are sent to a store-based terminal (10) and receives data content, a store-based terminal (11), which receives the portable terminal ID or memory card ID and electronic money from the portable user terminal (10), and which sends these to a billing center (12), along with a content ID and a store-based terminal ID, a billing center (12) that receives the content ID, the portable terminal ID or memory card ID, the store-based terminal ID, and the electronic money from the store-based terminal (11), and a content center (13), which receives the content ID, the portable terminal ID or memory card ID, and the store-based terminal ID, and which distributes data content, via the store-based terminal (11), to the portable terminal (10).

1. Field of the Invention
The present invention relates to a data distribution system, to a data distribution method, to a portable terminal capable of data reception and to a portable terminal capable of data transmission. It also relates to a recording medium onto which data content is recorded, and more particularly to a recording medium onto which are recorded data content that is scrambled differently, depending upon the transmission destination.
2. Description of the Related Art
In the past, there have been disclosures of a system for distributing such data as music data, using a communication circuit (for example, in the Japanese Laid-Open Patent Application publications H7-147063 and H9-146820), and a system for distribution of such data via a communications satellite (for example in the Japanese Laid-Open Patent Application publications H7-143081 and H10-163991).
At present, even with tastes in music diversifying, and fashions in music changing significantly in a short period of time, a content center can select the desired song from among its huge amount of stored data content, thereby making it possible to use an extremely large number of songs, and to quickly meet the diversifying tastes of consumers and quick changes in popularity.
In a data distribution system, a data distribution method, and a data playback system of the past, however, it was not easy to receive a small amount of money each time data was distributed with a low cost. Additionally, when data was sold at in a store, it was not easy to achieve a quick and accurate understanding of the demographics of the users (such as age and gender). In the case in which an existing medium such as Minidisc™ (MD) was used to stored data, it was not possible to charge a user for copies made and distributed between users via this medium. With the widespread utilization of such networks as the Internet, while it is possible to access music content from all over the world, from either a store or at home, there had not been a specific proposal for a network-ready terminal (audio equipment) that could be conveniently used to carry that music content around.
While a typical example of digital content is music data, such digital content also encompasses static images, moving images, document dada, game programs, and application software.
Because such digital data can be quickly and accurately copied, there is a great need to protect such data from illegal copying. With large amounts of diverse data being distributed, there is an increasing need for a fast data transmission and fast data playback.

DATA DISTRIBUTION SYSTEM, DATA DISTRIBUTION METHOD, PORTABLE TERMINAL WITH DATA RECEIVING CAPABILITY, PORTABLE TERMINAL WITH DATA TRANSMITTING/RECEIVING CAPABILITY, RECORDING MEDIUM ONTO WHICH DATA CONTENT IS RECORDED, ENCODING APPARATUS, AND DECODING APPARATUS


Disclosed is a method and apparatus for controlling the temperature of a container end portion during manufacture, said container being filled with a product 11, and comprising a substantially tubular body portion 10 of thin-walled plastic or laminated plastic material and a butt-weldable end-piece 13 at each end of the body portion, whereby a first end-piece is fitted to one end of the body portion and the product 11 is introduced into the container via the open end of the body portion, a second end-piece 13 is introduced into the said open body portion end to an intermediate position where it partially projects into the body portion 10, and the plastic material of the body portion end region and the second end-piece is softened through application of heat energy, characterized in that the end-piece 13, by means of relative displacement between it and the body portion 10, is pressed in to the body portion to its terminal position whilst cooling gas is supplied to the transverse wall 15 of the end-piece 13.

Tubes and bottles made from thin-walled plastic or plastic laminated material are used for packaging of, for example, creams, ointments and various other viscous chemical/engineering preparations. Swedish Patent Application 8800548-3 describes an end-piece and a method for manufacturing tubes or bottles by butt-welding an end-piece in both ends of a tubular-shaped body portion of thin-walled plastic or laminated plastic material.
The advantage of manufacturing tubes or bottles in this way is that the need to transport bulky empty containers over long distances is avoided. Accordingly the method allows the private packager to produce his own tubes or bottles without comprehensive equipment.
The tube or bottle produced according to the above method can be filled with its product via its opening, after which a cap is affixed over the opening with the aid of, for example, screw threads.
In many cases, however, it is desirable to provide a container which has been sealed in a controlled environment so that the customer can confirm that the packaging is unopened. This results in enhanced quality, both for the packaging and its contents.
During production of such a sealed container it is advantageous that filling with the product occurs between the fitting of the first end-piece, preferably tubularly formed, and the second end-piece.
In the method according to said Swedish Patent Application 8800548.3 tubular-shaped body portions are located on a rotary indexing table for movement between various stations. At one station each end-piece is introduced into the upper end of a corresponding body portion by a piston to an intermediate position where it partially projects into the body portion. This partially assembled work piece is then moved to the next station where heating energy is supplied to the circumferential end region of the tube and intersecting region of the end piece. Once a temperature is attained at which the material is sufficiently soft, the work piece is advanced to the subsequent station where a piston is reapplied to push the end piece to its terminal position. Rapid cooling of the welding site is then achieved by means of passages within the piston for a cooling fluid.

Method and apparatus for controlling the temperature of a container end portion during manufacture


Fasudil-containing preparations that despite the us of a container excelling in the visibility of contents without particularly blocking of light, exhibit high stability against light; and a method of improving the stability of the preparations against light of storing the same. By regulating the pH value of aqueous solution of fasudil charged in a colorless transparent container to ≦5.5, there can be provided fasudil-containing preparations excelling in stability against light; and can be provided a method of improving the stability of the aqueous solution of fasudil against light, or storing the same.

1-(5-Isoquinolinesulfonyl)homopiperazine hydrochloride (hereinafter referred to as "fasudil hydrochloride") having an excellent vasodilatation effect is commercially available under the trademark of "Eril Inj." (manufactured by Asahi Kasei Pharma Corp.) and clinically used as an injection preparation for improving cerebrovascular spasm after a subarachnoid bleeding operation and an accompanying brain ischemia symptom (Patent Document 1).
Fasudil hydrochloride crystals are known to include crystals not containing crystal water (hereinafter referred to as "fasudil hydrochloride anhydride") and crystals containing crystal water (hereinafter referred to as "fasudil hydrochloride hydrate") (Patent Document 2).
An aqueous solution of fasudil hydrochloride is known to produce decomposition products by irradiation of light. To reduce generation of the decomposition products by light irradiation, injections and the like containing an aqueous solution of fasudil hydrochloride are supplied to the market in a form shielded from light, e.g. filled into a brown container or the like.
An aqueous solution injection of fasudil hydrochloride filled into a colored container or a container coated with a light-shielding coating of which the transmission rate of tight particularly with a wavelength of 350 nm is 10% or less has been known (Parent Document 3).
[Patent Document 1] JP-B5-3851
[Patent Document 2] WO 97/02260
[Patent Document 3] JP-A-9-24085

Fasudil-containing preparation and method of improving stability thereof


A brick-like article feeding mechanism with nearly square travel path and quick returning function includes an eccentric apparatus composed of a slide block and a slide channel and cooperative spur gear and internal gear with a gear ratio of 1:4. In cooperation with synchronously driving sprockets, the pushing arms for feeding the article travel through a nearly square path. One side of the square travel path (loading travel) costs a period of time equal to the sum of the time cost by the other three sides (unloading travel) so as to achieve a quick returning function and synchronous operation.

The present invention relates to a brick-like article feeding mechanism with nearly square travel path and quick returning function, which is connected to a working apparatus such as a packing machine to perform synchronous and quick returning function.
With respect to an existing working apparatus such as a packing machine, the articles to be packed or processed must be first placed into the carrier by labor for the packing machine or other working apparatus to perform the next step. In order to reduce the cost for labor, speed up the production and increase the reliability, it is necessary to automatize the brick-like article feeding operation.
A variety of feeding devices are commercially available for performing different article feeding operation with respect to different products. Some of the feeding devices directly push the articles into the working apparatus via a conveyor without good synchronization with the working apparatus. Some other employ rollers and chains as well as pushing arms for pushing the articles. However, at the end of the pushing operation, the travel path of the pushing arms are arched. This makes the articles tend to fall down. In the case that the feeding operation is performed by a cylinder, the feeding frequency and speed will be limited.

Brick-like article feeding mechanism with nearly square travel path and quick returning function

Industrial Technology Research Institute


A new Impatiens plant particularly distinguished by double, rose-shaped, red and white flowers, semi-compact, upright, outwardly spreading and mounded plant habit, free flowering, good basal branching, and moderately vigorous growth habit, is described.

The present invention comprises a new and distinct cultivar of Impatiens, botanically known as Impatiens walleriana, and hereinafter referred to by the cultivar name 'Silte Redsar'. The new cultivar originated from a hybridization made in June 2004 in Andijk, The Netherlands. The female parent was the proprietary red star-flowered Impatiens plant 'ID04-377-1' (unpatented), while the male parent was the proprietary red star-flowered Impatiens plant 'ID03-1913' (unpatented). The seeds produced by the hybridization were sown in September 2004. A single plant selection was chosen for further evaluation and for asexual propagation in December 2004.
The new cultivar was created in 2004 and has been asexually reproduced repeatedly by vegetative cuttings and tissue culture in Andijk, The Netherlands and Gilroy, Calif. over a two-year period. The plant has also been trialed at Gilroy, Calif., Andijk, The Netherlands and Hillscheid, Germany. The present invention has been found to retain its distinctive characteristics through successive asexual propagations.
Plant Breeder's Rights for this cultivar were applied for the European Union on Dec. 14, 2006.


A variable vane shroud for a gas turbine engine comprises a cylindrically shaped body, a hole arranged at a circumference of the body, and a counterbore arranged concentrically around the hole on a radially inward facing surface of the body. The hole is for receiving a trunnion from a variable vane and the counterbore is for receiving a hub from the variable vane. A liner is inserted into the hole and counterbore such that the trunnion and hub are provided with a contact surface. The invention also provides a method for repairing a damaged counterbore in a variable vane shroud. A liner having a shape corresponding to a layer of material removed from the shroud is inserted into the void left by removing damaged material such that the counterbore is restored to pre-damaged dimensions.

The present invention is related to gas turbine engines, and in particular to variable vane counterbored holes for engine casings.
Gas turbine engines operate by combusting fuel in compressed air to create heated gases with increased pressure and density. The heated gases are ultimately forced through an exhaust nozzle, which is used to step up the velocity of the exiting gases and in-turn produce thrust for driving an aircraft. In turbofan engines the heated gases are used to drive a turbine for rotating a fan to produce thrust, and to drive a turbine for driving a compressor that provides the compressed air used during combustion. The compressor section of a gas turbine engine typically comprises a series of rotor blade and stator vane stages. At each stage, rotating blades push air past the stationary vanes. Each rotor/stator stage increases the pressure and density of the air. Stators convert the kinetic energy of the air into pressure, and they redirect the trajectory of the air coming off the rotors for flow into the next compressor stage.
The speed range of an aircraft powered by a gas turbine engine is directly related to the level of air pressure generated in the compressor section. For different aircraft speeds, the velocity of the airflow through the gas turbine engine varies. Thus, the incidence of the air onto rotor blades of subsequent compressor stages differs at different aircraft speeds. One way of achieving more efficient performance of the gas turbine engine over the entire speed range, especially at high speed/high pressure ranges, is to use variable stator vanes which can optimize the incidence of the airflow onto subsequent compressor stage blades.
A plurality of variable stator vanes are typically circumferentially arranged between outer and inner diameter shrouds, which are typically manufactured from steel alloys. The vanes typically include trunnion posts at their innermost and outermost diameters that extend through counterbored holes in the shrouds, respectively. Accordingly, it is desirable that the variable vanes have low-friction rotational movement within the counterbores. However, over the course of an engine lifetime, these counterbores become worn and weathered. In addition to normal vane-induced wear, operation in wet and/or salt-rich environments induces corrosion or pitting in the counterbores, which interferes with free rotation of the vane trunnions within the counterbores. In the case of severe wear or corrosion, it can be necessary to replace the entire compressor case or vane shroud in order to restore optimal free rotation to the variable vanes. This is undesirable because these parts are typically very costly due to the high-grade alloys and precision manufacturing necessary to produce these parts. Thus, there is a need for improved methods and systems for reducing or eliminating the effects of wear and corrosion on variable vane counterbored holes.

Hole liners for repair of vane counterbore holes


A method and circuit for receiving frame messages connected to one or more nodes, each controlled by a microcontroller, along a common transmission line of a multiplex communication system. The method includes the steps of: (a) receiving the type and target bytes, and responsive thereto generating a first interrupt signal to the microcontroller at the node; (b) commanding the microcontroller, responsive to receiving the first interrupt signal, for qualifying the frame message by retrieving and matching one or more of the type and target bytes with corresponding bytes stored in programmable memory within the microcontroller, and responsive thereto generating a qualified signal; and (c) receiving data bytes from the frame message only responsive to receiving the qualified signal from the microcontroller.

1. Field of the Invention
This invention relates to a multiplex transmission system of the type used in automotive applications for transmitting serial data message formats among a plurality of multiplex nodes connected to a common multiplex transmission line, and more particularly to a pulse width modulation multiplex transmission system operated in accordance with Society of Automotive Engineers standard J1850.
2. Prior Art
Messages transmitted from an originating node in a multiplex communication system normally include priority/type bytes describing the group or function of the nodes that should receive the message, in addition to target bytes that may define the specific address or addresses nodes to receive the message. The transmitting node must receive confirmation or acknowledgment that the addressed node has received the message.
A typical received node includes interface circuitry that includes programmable memory for storing the address of the node as well as the priority and/or type functions for which the node is responsible. These stored type and target bytes must then be compared by the interface circuitry with the type and target bytes of all incoming messages in order to determine if the message should be received and processed. Since programmable memory within the interface circuit represents an added cost that increases complexity without increasing functionality, it is desirable to provide a node interface circuit that offloads this function to the host microprocessor at the node that already includes programmable memory and comparators capable of performing this function.

Half-message based multiplex communication interface circuit which uses a main microcontroller to detect a match in addresses and generate a qualified signal


A flexible conductive film and its manufacturing method are provided. A flexible touch screen and a flexible touch display panel including the flexible conductive film are also provided. The manufacturing method of a flexible conductive film includes: providing a first substrate; applying a first conductive metal ink on the first substrate and forming a first conductive metal pattern; applying a polyimide varnish on a surface of the first substrate having the first conductive metal pattern; soaking the first substrate in deionized water after the polyimide varnish has been solidified; and detaching the solidified polyimide varnish and the first conductive metal pattern from the first substrate to obtain the flexible conductive film. The flexible conductive film prepared can be used in a flexible touch screen and a flexible display panel to improve the adhesion of nanosilver material to a flexible substrate, and to improve its stability of mechanical strength.

In the field of display technology, a metal mesh structure is more suitable for flexible display devices than brittle indium tin oxide due to its higher ductility. Although the metal mesh structure is flexible, it has a bad adhesion to a flexible polymer surface, rendering the stability of its mechanical strength unsatisfactory. Accordingly, for a better application of the metal mesh structure in the flexible display devices, improvement in the adhesion of the metal mesh structure to the polymer surface is desirable.

Flexible conductive film, its manufacturing method, flexible touch screen and flexible display panel

HEFEI XINGSHENG OPTOELECTRONICS CO., LTD.