A fastener (30) for fastening a paper retaining binder mechanism (18) to the spine (16) of a binder (10) and remaining entirely concealed from an outer surface of the binder. The fastener includes a circular anchor plate (38) and a vertically extending attachment post or eyelet (34). The post is a truncated cone of uniform taper. The anchor plate includes a circumferential reinforcing lip (48). The fastener is secured to the spine by a number of spurs (50) uniformly spaced about the circumference of the anchor plate. The eyelet extends perpendicular of the anchor plate and the binder mechanism seats on the eyelet by an opening (26, 28). The upper end of the eyelet is then deformed about the opening to secure the binder mechanism in place.

This invention relates to paper retaining ring binder mechanisms, and more particularly, to a spur eyelet having a uniform circular base for securing a ring metal of the ring binder mechanism to a spine portion of a binder.
Paper retaining ring binder mechanisms typically comprise a ring metal assembly, formed of metal, and including binder rings which are openable for the insertion and removal of material, such as hole-punched sheets of paper. The ring binders and a lever mechanism by which they are opened and closed all form part of the ring metal assembly. A plate covers the lever mechanism and usually includes provisions at each end for attachment of the ring metal to a spine section of the binder. One form of attachment includes the use of rivets secured to the binder and passing upward, through the ring metal. However, it has been found that other means of attachment are more secure and better able to withstand the rigors associated with daily binder use.
For cosmetic purposes, it is often desirable to incorporate a means for securing the ring binder mechanism to the binder which is not visible on the exterior surfaces of the binder. U.S. Pat. No. 5,755,513 to To, No. 5,160,209 to Schuessler, and No. 5,100,253 to Cooper each illustrate a fastener comprising an upright rivet structure mounted on a rectangular attachment plate and having a number of prongs adapted to grip an interior surface of a binder. The rivet structures in each of these patents are designed to pass through openings in the binder mechanism for attachment thereto.
While useful for their intended purpose, these fasteners suffer from several drawbacks. First, the prongs of each fastener are punched directly out of the attachment plate material; and, as best shown in FIG. 4A of the '513 patent, are surrounded by non-uniform amounts of material. This is due to the rectangular configuration of the attachment plate.
Second, the rectangular configuration further hinders automated assembly of the binders, as each fastener must be oriented such that the longest dimension of the attachment plate is properly oriented along the spine of the binder. Incorrect orientation will result in the interference between the cover portions and the attachment plate when the binder is folded closed.
Finally, the upright rivet structure commonly used in the prior art fasteners requires either a shoulder incorporated into the rivet structure itself, as is shown in the '513 patent, or a separate supporting means to hold the ring metal in position as the upper surface of the rivet is deformed to secure the ring metal, as is seen in the '209 and '253 patents.

Spur eyelet fastener with uniform circular base for securing ring binder mechanism


In a shaping processing apparatus which receives ATM cells as reception ATM cells which contains normal ATM cells and tagging ATM cells, a scheduling unit calculates a transmission time of the reception ATM cell based on a transmission time of a previous ATM cell belonging to a same connection as the reception ATM cell and transmitted immediately before the reception ATM cell and a predetermined time interval. A cell identifying unit identifies a connection number and cell priority of the reception ATM cell. The normal ATM cell has a higher cell priority than the tagging ATM cell. A mapping unit maps the reception ATM cell into a managing table based on the transmission time of the reception ATM cell to store the connection number and cell priority of the reception ATM cell in a storage area of the managing table. The managing table is associated with transmission times. The mapping unit outputs an address corresponding to the storage area as the write address to a shaping processing buffer such that the reception ATM cell is stored in the shaping processing buffer.

1. Field of the Invention
The present invention relates to an asynchronous transfer mode (ATM) self-flow control system, and more particularly to a shaping function which is used for traffic control in a user terminal transmission end, an ATM network transmission and reception ends or an ATM network.
2. Description of the Related Art
As well-known, all data are handled as ATM cells with 53-byte fixed length in an ATM system. A control data header is 5 bytes of the 53 bytes and an information field for a user data (called a payload) is 48 bytes. In this way, in the ATM system, a data sequence with this fixed length (a packet) is used as a unit of multiplexing and exchanging. In the header are written a data VCI (virtual channel identifier) for identifying a connection to which the ATM cell belongs, a data VPI (virtual pass identifier), a data CLP (cell priority identifier) for indicating whether or not discard of the ATM cell is permissible when congestion is generated, a data PT (cell class identifier) for identifying network control information, and a data for functions such as header error detection/control (HEC).
Here, the connection indicates a route used to transmit the ATM cell between the users. The ATM cells having different identifiers are prepared for communication between different users. The identifier is called a connection number. The connection number contains the above data VCI and data VPI. Also, the CLP bit which is defined in the header is the bit which indicates a discard priority of the ATM cell, as described above. The data CLP=1 indicates that the ATM cell has a high discard priority, and the data CLP=0 indicates that the ATM cell has a low discard priority. In this specification, the ATM cell of CLP=0 is referred to as a normal ATM cell or a usual ATM cell, and the ATM cell of CLP=1 is referred to as a tagging ATM cell. The tagging ATM cell has a discard priority higher than the normal ATM cell and is always possible to be discarded. That is, the tagging ATM cell may be transmitted when the transmission route is empty, if it does not affect to other ATM cells.
By the way, since such ATM cells are randomly transmitted from a transmission side, the ATM cells are received as the reception ATM cells which are temporally dispersed on the reception side, as shown in FIG. 14A. Here, in FIGS. 14A, A, B, C, D and E indicate the ATM cells. As shown in FIG. 14A, because each of the ATM cells has different transmission rates, there is a case that a large time interval is between the adjacent reception ATM cells as in the ATM cells B and C. Also, there is a case that small time intervals are between the adjacent reception ATM cells as in the ATM cells C, D and E. If the time interval between the adjacent reception ATM cells is so small that a lump of ATM cells is formed such as the ATM cells C, D and E, the transmission rates of the ATM cells sometimes become higher than a predetermined transmission rate. Such a lump of ATM cells is called a burst ATM cell group and it is said that the burst degree is high as the time interval between the ATM cells becomes smaller.
In order to reduce the burst degree, an operation is performed to separate a reception ATM cell from another reception ATM cell immediately before the reception ATM cell (Hereinafter, to be merely referred to as a previous ATM cell) by a predetermined time interval or more. For this purpose, a delay buffer is used to delay a reception ATM cell by the predetermined time interval. The function to correct the transmission rate of the ATM cell in this way, in other words, the function to adjust an ATM cell time interval is called "traffic shaping" or simply "shaping" in this technical field. That is, in the shaping, as shown in FIG. 14B, the transmission rates of the reception ATM cells are corrected to have a predetermined value in accordance with a preset parameter (requested transmission rate). Therefore, because the above delay buffer is used for the shaping, the delay buffer is also called a shaping processing buffer.
FIG. 1 shows the structure of a conventional shaping processing apparatus. The conventional shaping processing apparatus is composed of a shaping processing buffer 10, an ATM cell identifying section 20', a scheduling section 30 and a mapping section 40'.
The shaping processing buffer 10 can receive read/write addresses A'.sub.W/R outputted from the mapping section 40' to be described later, randomly write the reception ATM cells Cr in accordance with the read/write address A'.sub.W/R, and sequentially read the written ATM cells as transmission ATM cells Ct.
The scheduling section 30 calculates a time interval between a previous ATM cell of the same connection and a current ATM cell based on shaping algorithm so that the reception ATM cell Cr can be transmitted in an ideal ATM cell time interval. The scheduling section 30 determines a necessary delay quantity based on the calculated time interval, and outputs a storage address As of the reception ATM cell indicating an ideal transmission time to the mapping section 40'.
The mapping section 40' performs the mapping of the reception ATM cell Cr as follows. That is, the mapping section 40' detects whether or not the area corresponding to the storage address is empty, based on the reception ATM cell storage address As supplied from the scheduling section 30. When another ATM cell is already mapped into the storage address area so that a conflict is generated, search processing is executed for an empty storage address area which is the nearest to the storage address area for the address in a direction behind the storage address area to determine a new storage address area for the reception ATM cell Cr in the shaping processing buffer 10. The mapping section 40' stores related information such as the connection number of the reception ATM cell Cr and the data CLP in the empty storage address area. Also, the mapping section 40' outputs the reception ATM cell write address to the shaping processing buffer 10.
The ATM cell identifying section 20' outputs the ATM cell identifying result R'.sub.ci in accordance with the connection number. The mapping section 40' receives this ATM cell identifying result R'.sub.ci. As shown in FIG. 2, the mapping section 40' is composed of a transmission time managing memory 41' having (n+1) addresses, for managing the empty address areas and the connection numbers when the mapping is performed, and an address managing section 42' for the transmission time managing memory 41'.
Next, the operation of the conventional shaping processing apparatus shown in FIG. 1 will be described.
Here, it is assumed that the ATM cell stream in which normal ATM cells and a lot of tagging ATM cells are mixed in a same band to have a relatively high burst traffic characteristic. In this case, the ATM cell identifying section 20' extracts the connection number of a reception ATM cell Cr from the header of the reception ATM cell Cr and transfers to the mapping section 40'. Also, at the same time, the scheduling section 30 determines the transmission time of the reception ATM cell Cr as follows. That is, the scheduling section 30 finds an ideal or theoretical transmission time of the reception ATM cell Cr from shaping algorithm calculation based on the arrival time of the reception ATM cell Cr, the transmission time of the previous ATM cell having the same connection number, and the transmission time interval of the transmission ATM cell which is previously set for the connection number. Then, the scheduling section 30 transmits the determined ideal transmission time to the mapping section 40'.
When receiving the above various types of information, the mapping section 40' refers to the transmission time managing memory 41' for managing the address information. Thus, the mapping section 40' checks whether the storage address area corresponding to the ideal transmission time of the reception ATM cell Cr is empty. The transmission time managing memory 41' manages a storage area corresponding to the ideal transmission time of the reception ATM cell Cr. When it is determined that the storage address area corresponding to the ideal transmission time of the reception ATM cell Cr is empty, the mapping section 40' outputs the connection number of the reception ATM cell Cr and this address information to the address area as a write address of the shaping processing memory 10.
Also, various conventional examples which relate to the present invention are proposed. For example, In Japanese Laid Open Patent Disclosure (JP-A-Heisei 6-216929: hereinafter, to be referred to as a first conventional example), an "ATM switch" is disclosed in which ATM cells which are centered to a specific input line are processed using memories which are even arranged for input lines. In the first conventional example, the ATM cell conflict control state of the whole ATM switch is estimated. In a congestion state, the number of ATM cells to be transmitted is suppressed, and in the empty state, a lot of ATM cells are transmitted. Alternatively, the arrival time of the ATM cell is recorded in the ATM cell, and the arrival time of the ATM cell is considered based on the recorded arrival time such that an ATM cell having a long waiting time is transmitted. In order to reduce the congestion state of the ATM cells, it is necessary that the arrival time and the transmission time of the ATM cell are managed for a conflict control. However, the object of the first conventional example is to attempt to improve the non-equality of ATM cell traffic by the buffer management of the ATM switch. Therefore, the first conventional example has no relation with the shaping function according to the present invention.
Also, in Japanese Laid Open Patent Disclosure (JP-A-Heisei 4-115643: to be referred to, hereinafter, as a second conventional example) corresponding to U.S. Pat. No. 5,267,232, a "method of controlling a data transmission in ATM network" is disclosed. In the second conventional example, a network control is achieved in a simple mode, when a plurality of discard priorities exist in one virtual channel. The method is composed of a step of separately declaring traffic characteristic of whether there are only discard non-permitted ATM cells or whether there are mixed discard permitted ATM cells and discard non-permitted ATM cells, and a step of estimating an ATM cell discard ratio based on the declared traffic characteristic to execute connection accept desk control (CAC) in the network. The ATM cell discard ratio is separated based on whether there are only discard non-permitted ATM cells or whether there are mixed discard permitted ATM cells and discard non-permitted ATM cells in the multiplexed virtual channel. The ATM cell discard ratio is guaranteed by the network based on the estimated ATM cell discard ratio.
It should be noted that the discard permitted ATM cell in the second conventional example and the discard non-permitted ATM cell are equivalent to the tagging ATM cell and the normal ATM cell or the usual ATM cell of the present invention, respectively. The second conventional example discloses the technique to guarantee an ATM cell discard ratio for every virtual channel. Therefore, the second conventional example has no relation with the shaping function according to the present invention, like the above first conventional example.
In the above-mentioned conventional shaping processing apparatus, in the memory conflict control system which has a general shaping function, the shaping processing is performed without being conscious of the tagging ATM cell. That is, all the reception ATM cells are handled equally as the normal ATM cell without identifying the tagging ATM cell.
In a case where the above conventional examples are used, the burst degree is estimated by a network administrator, and the ATM cell delay buffer is designed in such a manner that the shaping processing can be sufficiently performed. However, when a lot of tagging ATM cells are contained in the ATM cells in the same band, there is a case that the burst is generated so that the ATM cells are received over a permission value of the ATM cell delay buffer. In this case, therefore, there is a problem in that the reception ATM cells over this permission value has been consequently discarded.
In accordance with, in order to solve this, it is necessary to increase the permission value of the ATM cell delay buffer which is necessary for the process shaping. However, it is obscure that the problem passes away if the buffer has what quantity. Also, if the buffer quantity is increased, a new problem occurs in which the hardware scale increases.

Method and apparatus for shaping processing in which discard of ATM cell effectively performed


A method and system for managing a secure configuration of a server blade on a network. The server blade has a Remote Supervisor Adapter (RSA) card, which contains a list of trusted Dynamic Host Configuration Protocol (DHCP) servers. A remote manager, which communicates with the RSA card via a hyper-secure network, maintains the list of trusted DHCP servers on the RSA card. When the server blade broadcasts a request for configuration parameters to join the network, a response offer is returned from a DHCP server. If the responding DHCP server is not on the list of trusted DHCP servers contained in the RSA card, then the offer is refused, and another DHCP server's offer is evaluated.

1. Technical Field
The present invention relates in general to the field of computers, and in particular to multiple blade servers housed in a server chassis. Still more particularly, the present invention relates to a method and system for filtering, through a secure remote supervisor, responses from Dynamic Host Configuration Protocol (DHCP) servers to a blade server's request for network configuration parameters, such that responses to the request for configuration parameters are only accepted from trusted DHCP servers.
2. Description of the Related Art
Server blade computers offer multiple server blades (boards) in a single chassis (blade chassis). Although each server blade may be under at least partial control of a primary server blade in the chassis, each server blade typically functions as an independent server to specific clients. A typical arrangement of such as system is shown in FIG. 1, in which a blade chassis 102, having multiple server blades 103a–c, is connected to a network 106, which connects to multiple clients 104.
In order to initially connect to network 106, each of the server blades 103 may utilize a network identification protocol known as Dynamic Host Configuration Protocol (DHCP). DHCP allows each server blade 103 to obtain an Internet Protocol (IP) network address and other configuration parameters from a DHCP server in a configuration servers network 108.
To initialize on the network 106, a server blade 103 broadcasts a request for configuration parameters to configuration servers network 108. One or more of the DHCP servers in configuration servers network 108 responds back to server blade 103 with a dynamic IP address along with lease information and other configuration parameters. If responses from multiple DHCP servers in configuration servers network 108 are put on network 106, then server blade 103 typically responds to the first DHCP server response to arrive at server blade 103.
A network initialization of server blade 103 as described is not secure, since the broadcasted configuration parameter request can result in a response from any DHCP server connected to server blade 103, including an unauthorized DHCP server attempting mischief. What is needed, therefore, is a method and system that prevents server blade initialization by an unauthorized DHCP server.

This patent is subject to a terminal disclaimer.

Method and system for restricting DHCP servers

International Business Machines Corporation


Provided are an image processing device, the operating speed of which is increased by reducing mirror bounce, a photographing apparatus having the same, and a photographing method. The image processing device includes a mirror disposed to revolve with respect to a shaft, a first guide unit disposed in a path of revolution of the mirror to lessen vibration of the mirror when the mirror revolves, and a first elastic unit applying predetermined elastic force onto the first guide unit while being engaged with the first guide unit.

1. Field of the Invention
The present invention relates to an image processing device, a photographing device having the same, and a photographing method, and more particularly, to an image processing device, the operating speed of which is increased by reducing mirror bounce, a photographing apparatus having the same, and a photographing method.
2. Description of the Related Art
It is now easier for novice photographers to take photographs like professional photographers due to digital single lens reflex (DSLR) cameras, which are single lens reflex cameras that take digital photographs.
A conventional DSLR camera is fabricated having a mirror which is installed to revolve within a predetermined angular range on an optical axis of a lens with respect to a shaft. At ordinary times, light of a subject, which is transmitted by a lens unit, is reflected from the mirror and imaged on a focus plate, so that a photographer can view the image of the subject, which is to be imaged on the focus plate, through the use of a pentaprism and a viewfinder. In this case, if a shutter-release signal is input, the mirror moves upward in order to retreat from the optical axis of the lens unit while revolving within the predetermined angular range about the shaft. When a shutter is driven to be open under the control of a shutter driving circuit, the image of the subject is formed on an imaging device.
In such a DSLR camera, while the mirror that moves upward during photographing, moves downward to return to the original position after the photographing, the mirror bounces upward due to the descending force thereof, thereby causing vibration of the mirror to a certain degree. For next photographing, the mirror needs to be stable without vibrating since operations for next photographing, such as auto focusing (AF), can be performed only when the mirror is stable. Thus, the amount of time needed for the mirror to stabilize is closely related to the operating speed of the camera. In particular, it is very important to reduce such mirror bounce for continuous photographing.

Apparatus for reducing mirror bounce, photographing apparatus comprising the same, and photographing method for the same


A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

A pseudo-SRAM has been known, which has a basic element of DRAM and is configured to be so operated as SRAM. The pseudo-SRAM is non-synchronous in view of the specification, which is similar to the conventional SRAM. The pseudo-SRAM is configured to have a basic element of DRAM. The pseudo-SRAM is so configured that operations, such as a refresh operation being unique to DRAM, are automatically performed by the inside thereof.
An example of the conventional non-synchronous semiconductor memory device configured to have a basic element of DRAM will hereinafter be described.
FIG. 1 shows an example of a configuration of the semiconductor memory device of this type. In this drawing, an address ADD is an external signal, and includes a row address designating a row of a memory cell array to be described below and a column address designating a column thereof.
An address input system 1 latches the address ADD and outputs an internal address LADD. An address transition detector circuit (ATD) 2 detects a transition of the internal address LADD and outputs a one-shot pulse signal OSP. An address multiplexer (MUX) 3 outputs, as an address MADD, one of the inputs which include an internal address LADD and a refresh address RADD to be described below.
A row decoder 6 decodes the address MADD for selecting a row of a memory cell array 7. The memory cell array 70 comprises a matrix array of memory cells similar to the general-purpose DRAM. A sense amplifier 71 amplifies a data signal on a bit line for a read operation. A column decoder 72 selects a column of the memory cell array 7. Although not illustrated herein, a precharge circuit for bit lines is provided accompanying the sense amplifier 71.
A refresh timer circuit 8G times a refresh time interval. A refresh control circuit 8H controls a series of refresh operations and generates a refresh control signal REFA for controlling a refresh timing accompanying to an external access and a refresh control signal REFB for controlling a self-refresh timing.
A refresh address generating circuit 8J generates an address RADD (hereinafter referred to as "refresh address") to be used for a refresh operation. An internal pulse generating circuit 9 generates a row enable signal RE, a sense amplifier enable signal SE, a pre-charge enable signal PE and a column enable signal CE.
Other than the above-described circuits, there are further provided a system of circuits for controlling read and write operations, another system of circuits for generating a substrate potential of the memory cell array and still another system of circuits for read and write operations of data to the memory cell array.
The read and write operations and the refresh operation of the semiconductor memory device of the prior art shown in FIG. 1 will, in sequence, be described with reference to a timing chart of FIG. 2.
A. Read and Write Operations
A read operation according to an address access will be described as one example. In this case, a chip select signal ICS and an output enable signal /OE are low, while a write enable signal /WE is high, wherein the address ADD is an externally supplied signal.
The address ADD is an input to the address input system 1 and is latched as an output as the internal address LADD. Except for the refresh, this internal address LADD is supplied as the address MADD as an output of the multiplexer 3 to the row decoder 6. At a timing defined by the row enable signal RE, the row decoder 6 selects one word line in the memory cell array 7, so that data of memory cells connected to this single row of this word line are read out onto respective bit lines. These data signals are amplified by the sense amplifier 71 at a timing defined by the sense amplifier enable signal SE.
On the other hand, based on a column address (not illustrated) included in the address ADD, and at a timing defined by the column enable signal CE, the column decoder 72 selects a bit line of the memory cell array 7, so that data on this bit line is supplied as an external output signal through the data output circuit system (not illustrated). Prior to the operation of reading data from the memory cells, bit lines are pre-charged based on the pre-charge enable signal PE.
In the above-described series of read operations, a transition of the internal address LADD is detected by the address transition detector circuit 2 which outputs a one-shot pulse signal OSP. By triggering this one-shot pulse signal OSP, the internal pulse generating circuit 9 outputs, at appropriate timings, the above-described row enable signal RE, the sense amplifier enable signal SE, the pre-charge enable signal PE and the column enable signal CE.
Consequently, the data is read out of the memory cell designated by the address ADD and supplied to the outside.
B. Refresh Operation (in Read Mode)
A refresh operation in a read mode as one of the active modes will subsequently be described with reference to a timing chart shown in. FIG. 2(a).
In the read mode, the semiconductor memory device according to this conventional technique shows a sequential performance of both the refresh operation and the read operation in the same cycle in accordance with the specification.
The address input system 1 latches an external input address signal A0 as the address ADD and then outputs the internal address LADD. The address transition detector circuit 2 detects a transition of the internal address LADD and outputs the one-shot pulse signal OSP.
Upon receipt of the one-shot pulse signal OSP, the refresh control circuit 8H starts the refresh operation. Upon the start of the refresh operation, the refresh address generator circuit 8J generates and outputs a refresh row address RO as the refresh address RADD. Under the control of the refresh control circuit 8H, the address multiplexer 3 supplies the refresh address RADD (the refresh row address RO) as the address MADD to the row decoder 60.
On the other hand, the internal pulse generating circuit 9 receives an input of the refresh control signal REFB from the refresh control circuit 8H, and outputs the row enable signal RE and the sense amplifier enable signal SE. The row decoder 6 receives inputs of the address MADD and the row enable signal RE and selects a word line designated by the refresh address RO for a predetermined time period defined by the row enable signal RE. Data signals of the memory cells connected to the selected word line are amplified by the sense amplifiers and then re-stored therein, whereby the data of the memory cells for the single row designated by the refresh address RO have been refreshed.
After the refresh operation has been finished for the row designated by the refresh row address RO, then the read operation is made in the same cycle. For example, the address multiplexer 3 receives the internal address LADD from the address input system 1 and supplies the internal address LADD as the address MADD to the row decoder 6. The row decoder 6 selects the word line designated by the row address X0 entered as the input address MADD. The sense amplifier 71 amplifies the data signal appearing on the bit line in the memory cell array 7. The amplified data is provided as an external output through a data output circuit (not illustrated).
C. Refresh Operation (in Stand-by Mode)
A refresh operation in a stand-by mode will be described with reference to a timing chart shown in FIG. 2(b). In the stand-by mode, the refresh control circuit 8H measures an amount of time which has occurred from a time of the last external request for access, so that if the the amount of time exceeds a predetermined refresh time, then the refresh control circuit 8H outputs the refresh control signal REFB to start the self-refresh operation.
In the above-described active mode, after the refresh operation accompanying the read and write operation, the refresh control circuit 8H starts the timer. After the predetermined time has elapsed, the refresh is automatically started by triggering the timer. In either the stand-by mode or the active mode, the retention of the data is ensured without starting the refresh from the outside, similarly to the general-purpose SRAM.
Meanwhile, with the pseudo-SRAM in accordance with the above-conventional technique, it is necessary to pre-charge the bit line for a subsequent access until a predetermined time (hereinafter referred to as a recovery time TWR) from a time when the write enable signal is inactivated after the write operation to the memory cell has been made. Accordingly, it is difficult for the pseudo-SRAM that the recovery time TWR becomes zero. The pseudo-SRAM of this conventional technique maintains the write operation to the memory cell in a time period that the write enable signal is in the active state, for which reason in this time period, the refresh can be executed.
For the pseudo-SRAM, a write cycle time TWP has an upper limit of a write cycle time TWP for the refresh operation.
The pseudo-SRAM has strict limitations to the recovery time and the write cycle time, and is different in the specification from the general-purpose SRAM.
A data write method referred to herein as a "Late Write" has been presented for removing the limitations on the specification.
This late write will, hereinafter, be described briefly. In the memory cycle with an externally given request for the write access, a given write address and a given write data are taken into the semiconductor memory device, while those write address and write data as taken will be retained in the inside of the semiconductor memory device until the next request for write operation is entered. The write operation to the memory cell is not executed in this memory cycle, but will be executed in a future memory cycle of the entry of the next request for the write operation to the memory cell. The late write is that the write operation to the memory cell is delayed to the memory cycle of the entry of the next request for the write operation.
In accordance with the late write, it is unnecessary to write data into the memory cell within the memory cycle when these write data have been taken, for which reason it is unnecessary to pre-charge the bit line after the write operation, thereby allowing the recovery time TWR to be zero similarly to the general-purpose SRAM. In the later memory cycle that the data are written into the memory cell, the write address and the write data have already been taken, for which reason the activation of the write enable signal causes a prompt start the write operation to the memory cell. After the data write operation to the memory cell has been made, then it is unnecessary to maintain the word line to be selected even in the write cycle. This allows allocating a subsequent time period for the refresh. This further makes it unnecessary to limit the write cycle time for ensuring the refresh operation.
With the use of the late cycle, it is possible for the pseudo-SRAM to operate similarly to the general-purpose SRAM.
In accordance with the above-described late write, however, it is possible, in case, that a series of the refresh operation, the read operation and the write operation appears in a later memory cycle than the cycle of the actual write operation, thereby disturbing subsequent operation in the next memory cycle.
This problem will be described concretely with reference to FIG. 3. FIG. 3 shows a timing of writing data (not illustrated) to addresses A1.about.A3.
In the initial state, the write enable signal /WE is high, and the operation mode is the read mode. At a time t110, an address ADD is transitioned to an address A1. At a time t112, the write enable signal /WE transitions to low, whereby data externally designated in the current or present cycle is taken as well as previous data having already been taken in the previous cycle are stored in late-write to the memory cell.
At the time t110, the transition of the address ADD occurs, whereby the refresh is executed. At a time t111, the refresh is finished, whereby the read operation is started. Once the read operation has been started, it is prohibitive to interrupt the read operation in view of protecting the data. The above-described late write operation of the data will wait for the read operation to be completed. As a result, the late write, which should be executed in the write cycle to the address A1, is interrupted into the other write cycle to the next address A2, thereby disturbing the refresh in this next write cycle.
In accordance with this example, in the write cycle to the address A1, a series of the refresh operation, the read operation and the write operation is executed, thereby causing an increased consumption of current.
The present invention has been made in view of the above-circumstances. An object of the present invention is to provide a semiconductor memory device allowing the refresh operation to be free from any interruption by the late write and reducing a current consumption in a write cycle having the late write operation.

Semiconductor memory device for preventing a late write from disturbing a refresh operation


The present invention is directed to a system and method for controlling microorganisms on a surface in a hatchery. The present invention is also directed to a system and method for controlling microorganisms on the surface of eggs. The present invention is further directed to a method for reducing the level of pathogen infection in a poultry flock.

Commercial flocks of poultry, such as chickens, turkeys, ducks, geese, quail and the like, can generally be classified as belonging to one of three flocks: the primary (or master) breeding flock, the secondary breeding flock, and the food flock. Poultry eggs can likewise be loosely classified into two general categories, hatching eggs, which are fertile eggs that are to be hatched into chicks (for the breeding flock or the food flock), and table eggs, which can be either fertile or infertile eggs that are intended for direct consumption.
The food flock, as its name implies, is intended for direct consumption, i.e., these are the birds that are purchased for food at a local grocery store. The secondary breeding flock produces both hatching eggs, from which the food flock is hatched, and table eggs intended for direct consumption. Birds are selected for membership in this flock based upon a number of factors, including the number and size of eggs produced and the characteristics of the birds hatched from these eggs (the food flock). The primary or master breeding flock also produces hatching eggs, from which the secondary breeding flock is hatched, but not table eggs. These birds are selected for membership in the master flock based upon their particular genetic characteristics as evidenced in the secondary breeding flock (second generation) and the food flock (third generation).
When food borne pathogens began to pose a major health issue, the poultry industry began to experience public pressure to remedy the problem of these pathogens. It has been found that a primary source of pathogen infection in chicks is the hatchery. Indeed, it is well documented that after a chick has been hatched, the chances are over 90% that it is a carrier of a number of pathogens which are dangerous to both consumers and other poultry in the flock (breeding or food). These pathogens include Salmonella spp. and Campylobacter spp., both of which have caused numerous cases of human intestinal diseases.
Even with the high probability of pathogen infection at hatching, the natural resistance to infection that develops in growing poultry nevertheless reduces the percentage of infected birds in the overall flock population. For example, in the case of salmonella, the percentage of contaminated chicks in the flock will drop from 90% of the population immediately following hatching to about 26% of the population in the houses in which the birds are grown and/or maintained. The effect of this bird's natural resistance is even more pronounced when the incidence of pathogen infection at hatching is reduced. For example, research has shown that chicks which are not infected with salmonella at hatching will resist infection during the period they are growing (e.g., 60 days or so) even if the grow house is contaminated.
The residual contaminated birds, however, remain a source of pathogen infection for the rest of the flock, breeding or food.
Moreover, in the case of the food flock, these residual contaminated birds are the most likely source of dangerous food borne pathogens when the flock is harvested.
A process known as competitive exclusion was proposed by Nurmi and Rantala, Nature, vol. 241, pp. 210-211 (1973), as a means for reducing the level of pathogen infection in poultry. This process involves administering intestinal bacteria from mature, healthy poultry to chicks whose intestinal bacteria were not yet established. The bacteria administered to the chicks competes with any pathogens that might be present in the gut of the chick, reducing the rate of colonization by the pathogens and thus the level of infection.
This method, however, has not provided completely satisfactory results. For example, the competing bacteria administered to the chicks may not colonize at a sufficient level to satisfactorily reduce the rate of colonization by the pathogen. In addition, over time, the pathogens tend to adapt to the presence of the competing bacteria and can actually colonize at a faster rate, thereby out-competing the competitive bacteria.
Thus, while the poultry industry has responded by treating many of the symptoms of the problems of pathogens, no practical solution has been offered which will cure the problem at its source: the hatchery. Accordingly, there remains a need for a system and method for controlling microorganisms associated with poultry.

System and method for controlling microorganisms associated with poultry


The present invention pertains to methods for dicing wafers which are capable of easily removing chips of an adhesive of a dicing tape adhering on the wafer during dicing by cleaning using cleaning water. One method of dicing a wafer includes sticking an adhesive member having a layer of adhesive on a surface of the wafer. An adhesive force of the adhesive member is reduced along a plurality of dicing lines on the wafer without reducing the adhesive force of the adhesive member between the plurality of dicing lines. After the adhesive force is reduced along the dicing lines, the wafer is diced along the plurality of dicing lines into a plurality of parts by a blade.

The present invention relates to a method of perfectly dicing a flat workpiece, for example a flat substrate made of quartz, silicon or the like on which LCD (Liquid Crystal Display) elements, solid state imaging devices such as CCD (Charge Coupled Device) elements, IC (Integrated Circuit) elements and the like are arranged, by for example a rotary blade to obtain the individual LCD elements, solid state imaging devices such as CCD elements, IC elements and the like; and an apparatus used for the method.
A related art method of and apparatus for dicing a workpiece will be first described with reference to FIG. 2.
FIG. 2 is a schematic side view of a related art dicing apparatus, with parts partially cutaway.
Referring to FIG. 2, reference numeral 1 indicates an apparatus for dicing a substrate (usually called "wafer", and hereinafter referred to as "wafer") made of quartz, silicon or the like on which many LCD elements, solid state imaging devices such as CCD elements, IC elements and the like are formed so as to manufacture the LCD elements, solid state imaging devices such as CCD elements, IC elements and the like. In FIG. 2, a wafer S composed of a quartz substrate, on the surface of which LCDs are formed, is used as a workpiece.
The dicing apparatus 1, while partially shown in the figure, includes a table 2 on which the wafer S as a flat workpiece is mounted in a horizontal state; a rotary blade 3 disposed over the table 2 movably in the vertical direction, which is finely adjustable in height and rotatable around a rotating axis 3A in the direction of an arrow R; and a drive unit (not shown) capable of advancing/retreating the rotary blade 3 while rotating it in a state in which the table 2 is fixed, that is, the wafer S is fixed in the horizontal state, or a drive unit (not shown) capable of rotating the rotary blade 3 at a specified height and moving the table 2 and the wafer S held in the horizontal state in the X-direction and the Y-direction.
The wafer S, which is a workpiece to be diced, has a front surface on which many LCD elements are formed in a matrix and a back surface stuck with a dicing tape T as an adhesive member. The dicing tape T is composed of a film base member B made of a plastic tape, on the surface of which a layer A of an adhesive Ab (hereinafter, referred to simply as "adhesive layer") is formed. The film base member B has a thickness of for example about 80 .mu.m, and the adhesive layer A has a thickness of for example about 10 .mu.m. An adhesive force (peeling strength) of the adhesive is selected in consideration of the strength and thickness of the wafer S, and it is usually in a range of from 100 to 1500 g for a tape width of 20 mm.
The adhesive layer A of the dicing tape T is directly stuck on the back surface of the wafer S.
The separation of the wafer S into the individual LCD elements using the dicing apparatus 1 is performed as follows. The wafer S is mounted and fixed on the table 2 in a horizontal state with the dicing tape T side down; the rotary blade 3 is rotated in the direction of an arrow R; and the wafer S stuck with the dicing tape T is diced along a dicing line usually having a width of about 170 .mu.m between the LCD elements while the table 2 is moved in the x-direction and Y-direction, to a thickness equivalent to the total of the entire thickness of the wafer S and about a half of the thickness of the adhesive layer A. The LCD elements are thus separated from each other, but are stuck on the dicing tape T which is not cut yet.
The related art method of and apparatus for dicing a workpiece, however, has a disadvantage. Specifically, chips (silicon, quartz) Da of the wafer S and chips Db of the adhesive of the adhesive layer A are, during dicing, scattered by a rotating force of the rotary blade 3, and adhere on the surface of a portion, near the dicing line, of the wafer S. Of these chips Da and Db adhering on the wafer S, the chips Da of the wafer S can be removed by cleaning using a dicing water or the like; however, the chips Db of the adhesive once adhering on the surface of the wafer S cannot be removed by simple cleaning, if the adhesive has a high adhesive force. Such chips Db cause a vital dust failure for the LCDs, solid state imaging device such as CCDs, or ICs which are presently advanced in integration and fine-geometries.


The present invention discloses a hand brake mechanism having a gravity based release hold mechanism with a visual indicator to prevent unwanted application of the railcar brakes and indicate such release hold condition. The release hold mechanism comprises a gravity based member pivotally linked to a release shaft preventing reverse rotation of the release shaft causing an unintended take-up of the chain. A detent retaining device disposed within the railcar hand brake housing further provides improve reliability of the operation. The gravity based member incorporates an indicator portion having a reflective coating to indicate such release hold position of the railcar hand brake.

Railway car hand brake mechanisms are well known in the art. They usually include a relatively large, rotatable hand wheel disposed in a vertical plane and mounted on a shaft which, through a gear train, can rotate a chain drum to wind up a chain that is secured at its end remote from the chain drum to the brake rigging of the railway car. As the hand wheel is rotated in one direction, the brakes are applied and rotation of the hand wheel shaft in the opposite direction is prevented by a pawl which engages a detent wheel on the hand wheel shaft.
These hand brake mechanisms further include a clutch mechanism for facilitating gradual release of the brake. When a hand wheel is rotated clockwise (as viewed from the front of the unit), such rotation is transmitted directly through a drive shaft, a pinion, a gear, and a winding drum to take up slack of a chain connected to the brake rigging. When resistance is offered by the chain to further rotation of the hand wheel, such resistance, acting back through the drum, the gear, and pinion, causes a nut to be advanced on a threaded portion of the drive shaft to move against a ratchet member which is clamped between respective friction surfaces on the nut and on the drive shaft, thus causing the drive shaft, ratchet, and the nut to rotate as a unit. A pawl prevents rotation of the ratchet in the opposite direction. The hand wheel torque is increased until a state of static equilibrium is reached, or at the point at which the brakes are fully applied, whereupon rotation of the hand wheel is terminated, and the clamped ratchet, by means of the holding pawl, prevents the chain from unwinding.
The clutch mechanism also provides for quick release of the brakes by operating a release handle which effects disengagement of the normally engaged clutch and thereby allows free rotation of the pinion and gear to release the chain load while the nut and ratchet are held stationary by the holding pawl. The brakes may also be released by disengaging the pawl from the detent wheel but this causes rapid rotation of the hand wheel and the gears of the gear train.
To avoid rapid rotation of the hand wheel, hand brake mechanisms have been devised which are known as "quick release" mechanisms. U.S. Pat. No. 4,368,648 titled Hand Brake for Railroad Car teaches such a hand brake having a quick release mechanism. The quick release mechanism includes a releasable connecting means between the hand wheel shaft and the gear train. When the connecting means is released, the gears of the gear train rotate rapidly, without constraint by the pawl and detent wheel, but the hand wheel remains stationary. The teachings of U.S. Pat. No. 4,368,648 are hereby incorporated in present application by reference thereto.
It has been found that when a hand brake is quick released using the handle, the chain may not be fully expelled from the hand brake, thus maintaining residual tension due to lack of sufficient slack. This residual tension may set the hand brake, especially as the railcar travels around a curve. As a result the brakes may be applied unintentionally during railcar motion. As can be seen, it is desired to incorporate a positive means assuring that the brake is in a released and hold position and that the chain is fully released and provides sufficient slack to avoid unintentional setting of the hand brake.
Another long felt need in present hand brakes is related to their not having a positive visual indication of the hand brake being in the released hold position as viewed from the outside by railcar operating personnel and, particularly, providing such indication during darkness of nightfall. One of the challenges that must be overcome is the fact that railcars are painted in many different colors and may be contained within the same train consist.

Release hold mechanism with gravity weighted indicator flag


A security information and graphic image fusion system to be used with verification equipment to provide a tamper proof labeled article having security information thereon. The label comprises a printable sheet having at least one invisible IR or UV image, or both, printed thereon, at least one visible image printed thereon, and an over-coating layer thereon. The invisible IR or UV image, or both, provide security information. The visible image provides the graphic image. The label is permanently fused by an in-mold molding process to an article made of plastic, rubber or the combination thereof to render it tamper proof.

The present invention relates to labels and methods of producing labels that may be incorporated into plastic products, rubber products, and the like by fusion to provide security information and a graphic image. The present invention is further related to labels that provide security information, and labeled articles incorporating the labels.
Plastic and rubber materials are used to form and package a wide variety of products. However, many products or packaging may be subject to fraudulent or illegal sale or distribution. Additionally, plastic or rubber products or packaging may be subject to counterfeiting. For example, injectable and oral drugs may be packaged in plastic or rubber packaging, and these drugs may be subject to fraudulent sale or distribution. Such fraudulent use of plastic and rubber products may be detrimental to the health and safety of consumers. Additionally, the fraudulent sale or distribution of plastic and rubber products may adversely affect the profitability of manufacturers and sellers of the products and packaging.
There remains a need in the art for labels that provide authentication and verification of plastic and rubber products.

Security information and graphic image fusion


In a semiconductor device, a vocoder processing unit requests, after executing a first vocoder process being one of an encoding process and a decoding process and before executing a following second vocoder process being other one of the encoding process and the decoding process, a cache memory to prefetch first program data to be used for the second vocoder process from an external memory.

The present invention relates to a vocoder processing method, a semiconductor device and an electronic device.
In recent years, a wireless communication terminal that transmits and receives voice as a digital signal includes a vocoder processing unit (vocoder), which encodes a voice signal to be transmitted and decodes a received voice signal. For example, Japanese Unexamined Patent Application Publication No. 2003-216198 discloses an ASIC (Application Specific Integrated Circuit) for a vocoder process.
Meanwhile, Japanese Unexamined Patent Application Publication No. 9-259040 discloses a technique relating to an improvement in the hit rate of a cache memory (cache hit rate).

Vocoder processing method, semiconductor device, and electronic device


A cigarette case includes a cigarette casing including a corner outlet; a double-layer hinged cover including a first slit proximate the outlet and a second slit proximate the adjacent other corner; and a spring biased ejection means within the cover and including a pivotal L-shaped ejector, a pivotal trigger, a pivot bar, a link moveable in the first slit and including an end pusher extending through the first slit, the link having the other end pivotably secured to one portion of the ejector, and a sliding member moveable in the second slit and pivotably secured to the other end of the pivot bar, the sliding member including a door extending through the second slit to block the outlet when the case is closed. Pivoting the trigger will pivot the pivot bar to move the sliding member and the link to cause the pusher to eject a cigarette from the outlet.

1. Field of Invention
The invention relates to accessories for smoking tobacco and more particularly to a spring based pivot mechanism for ejecting a cigarette contained in a cigarette case.
2. Description of Related Art
Cigarette cases are well known devices. Typically, cigarettes are parallel arranged as one row or two vertical rows. It is often that the fingers taking out a cigarette may contact adjacent cigarettes (e.g., filter ends) unintentionally. This, however, may leave germs on the filter end and further spread germs on the filter end into the mouth while smoking. Hence, it is unsanitary.
There have been numerous suggestions in prior patents for cigarette cases having an automatic cigarette dispensing mechanism. For example, U.S. Pat. No. 5,265,717 discloses a cigarette case for automatically lighting and ejecting a cigarette contained therein. However, its mechanism incorporates many components including pivots, gears, carousel, springs, and electrical devices. Hence, it is relatively complex in constructions, costly to manufacture, trouble-prone, and unreliable in use.
Thus, it is desirable to provide a cigarette case having a simple mechanism for dispensing a cigarette contained therein in order to overcome the inadequacies of the prior art.

Pivot mechanism for ejecting a cigarette contained in a cigarette case


In an optical system, first green light reflected by a first diffractive optical element propagates in a left direction by repeating total reflection within a first light guide unit, is reflected by a third diffractive optical element, and is guided to a left eye. First red light reflected by a fifth diffractive optical element propagates in a left direction by repeating total reflection within a second light guide unit, is reflected by a seventh diffractive optical element, and is guided to a left eye. First blue light reflected by a ninth diffractive optical element is reflected by an eleventh diffractive optical element, and is guided to a left eye.

1. Technical Field
The present invention relates to an electronic apparatus which may display a three-dimensional (3D) image.
2. Related Art
In recent years, a technology for head mounted display (hereinafter, referred to as "HMD") using a hologram optical element has been known. In JP-A-2010-33026 (see, FIG. 4), a technique for guiding an image displayed in a single display device to the left and right eyes is disclosed. In this technique, the same image is viewed by the left and right eyes.
In addition, in JP-A-2008-527440 (see, FIG. 1), a technique for guiding an image for a left eye to the left eye and guiding an image for a right eye to the right eye is disclosed. In this technique, different images are viewed by the left and right eyes.
However, in the technique disclosed in JPA-2010-33026, the same image is viewed by the left and right eyes, and therefore a 3D image cannot be displayed.
Meanwhile, in the technique disclosed in JP-A-2008-527440, different images are viewed by the left and right eyes, and therefore the 3D image can be displayed. However, two display devices are required, so that their configurations are complex, and the overall size of the HMD is increased.


An ink-jet head comprises a passage unit, a reservoir unit, an actuator unit, and a flexible cable. The reservoir unit stores ink in an ink reservoir, and supplies the ink into the passage unit. The actuator unit is fixed to a portion of the passage unit spacedly confronting the reservoir unit. The flexible cable is connected with the actuator unit in order to supply a drive signal to the actuator unit. A channel is formed in the reservoir unit, the channel penetrating through the reservoir unit in a direction across a face of the passage unit where the actuator unit is fixed. The flexible cable connected with the actuator unit is extended out through the channel.

1. Field of the Invention
The present invention relates to an ink-jet head that ejects ink onto a record medium and thereby conducts a recording.
2. Description of Related Art
An ink-jet head is applicable to a recording apparatus such as printers and facsimile machines, etc. The ink-jet head comprises a passage unit that includes a plurality of nozzles and pressure chambers, an actuator that selectively applies ejection energy to ink contained in the respective pressure chambers, and the like.
One of known actuators has a layered structure of a plurality of piezoelectric sheets made of piezoelectric ceramic (see U.S. Pat. No. 6,631,981). With such a construction, the actuator is fixed onto a face of a passage unit opposite to a face thereof provided with nozzles, and the actuator is connected with a flexible cable acting as a power supply member. One end portion of the flexible cable connected with the actuator extends along a plane of the piezoelectric sheet.
The ink-jet head sometimes further includes a reservoir unit that stores ink having supplied from an ink supply source such as an ink tank and supplies the ink to the passage unit. The reservoir unit is fixed to the passage unit in such a manner that a portion thereof can spacedly confront the passage unit. The actuator is fixed to a portion of the passage unit spacedly confronting the reservoir unit.
One end of the flexible cable is connected with the actuator unit, and the other end thereof is extended out along an outer face of the reservoir unit toward a side of the reservoir unit away from the passage unit, in order that the other end can be connected with a control substrate, etc., that controls driving of the head.


In the manner of a tubular heater, a temperature sensor comprises a metallic tubular jacket with internal resistance wire coil embedded in insulating material and closing pieces having electrical connection members, so that a very simple, robust and high temperature-resistant temperature sensor with a measuring range up to e.g. approximately 750.degree. C. is obtained. The temperature sensor jacket can be earthed or grounded. For operating the temperature sensor there is appropriately a test current in the mA range in the case of a test voltage in the mV range, whose temperature-dependent changes are processed by means of an electronic amplifier.

The invention relates to a temperature sensor with a temperature-sensitive sensing element, which can be placed in a substantially protected manner in a sensor casing, as well as to a method for its manufacture.
Temperature sensors usually operate on the basis of the thermal expansion of a liquid or solid, or if constructed as electrical or electronic temperature determination devices, on the basis of the temperature-dependent change to the electrical resistance value of the sensing element or temperature sensor. The resistance values can change linearly/non-linearly or positively/negatively with the temperature. Particularly in the case of resistance sensors the temperature for the measurement is determined in a spatially closely defined area, because the precision resistor or the thermocouple is located in the tip or front region of the sensor casing. Known temperature sensors are usually very sensitive to thermal, electrical, electromagnetic and mechanical loading or overloading and it is very difficult to obtain an earthing action or security against short-circuiting. In addition, known temperature sensors are expensive to manufacture, whilst also being prejudicial to the environment when use is made of problematical materials such as sodium or potassium. It is usually difficult to fit known temperature sensors.


Systems and methods for remotely locking and unlocking vehicle accessory locks of vehicle accessories positioned on a vehicle are disclosed. The vehicle includes main doors with locks that are remotely lockable and unlockable using main door lock actuators. Vehicle includes a vehicle controller that receives a user signal from a user, first determines a main door actuation command based on the first signal, and first transmits, based on the main door actuation command, a first actuation command signal to the main door lock actuators. The system includes accessory lock actuator(s) operably coupled to the accessory lock(s), accessory lock controller(s) operably coupled to the accessory lock actuator(s), and a gateway controller operably coupled to the vehicle controller. Gateway controller second determines an accessory lock actuation command based on the first actuation command signal, and second transmits, based on the accessory lock actuation command, a gateway signal to the accessory lock controller.

Vehicle accessories of various types provide vehicle users convenient ways to extend the usefulness of their vehicles. In many such accessories employed by users on their vehicles, the vehicle accessories include locks for securing the accessory to the vehicle and/or securing contents being stored in or on the accessories.
In at least some known vehicle accessories, accessory locks are power locks. In such examples, use of the accessory power locks may require users to carry more than one key fob with their vehicle ignition key. In other known examples, hard wiring of the power accessory locks to the vehicle's battery requires running wires through the body of the vehicle, which not only require labor-intensive procedures and numerous additional parts beside the accessory and accessory locks themselves, but also may void vehicle warranties for such issues as body corrosion.
Therefore, a need exists in the field of lockable vehicle accessories for devices, systems, and methods for remotely locking and unlocking vehicle accessory locks that provide users more convenience, that are less expensive and less time-consuming to install, that are easier to operate and maintain, that require fewer modifications to vehicles to which they are attached and/or to the vehicle accessories themselves, and which make attaching the vehicle accessories to vehicles less likely to violate vehicle warranty conditions.


A digital scale is compensated for hysteresis by characterizing an envelope pattern of increasing and decreasing linearity attributes thereof defining the limits of hysteresis error. Polynomial expressions define this envelope pattern and a correction procedure is developed which is based upon offsets from the envelope pattern as well as the merging characteristics of deviations evidenced from complex loading histories. The latter historical data are used to identify loading progression transitions necessary for the generation of correction values.

Investigators seeking to improve the accuracy of force-measuring devices such as weighing scales are called upon to consider and attempt compensation for a variety of phenomena such as drift, anelastic creep, temperature induced effects, and hysteresis. The latter, hysteresis phenomenon, has posed significant problems for many years and finds its origin in the load cells or transducers of force measuring devices. Typically, a force measuring device will be configured having a weight receiving platform supported, in turn, by a load cell incorporating a counterforce or structure stressed by and responding in strain between loads applied to the platform and the device or scale ground. Force measuring instrumentation of the load cell, such as strain gauges and the like, react to such strain to provide an output, typically requiring correction for the above phenomena. Hysteresis, or as it is sometimes called, "Internal Friction" appears in the output of the transducer when a series of loads are applied and then removed in any of a myriad of sequences. In a typical course of scale usage these sequences of loading, for the most part, are of a random nature, for example, loads extending in value from partial to full being added and either fully or only partially removed from the scales. Comparing the outputs or readings of the devices as such loads are removed with the readings, at the same load, as the loads are being applied, results in a difference. This difference is considered to be hysteresis. The hysteresis effect arises primarily from the material properties and geometry of the weighing apparatus transducer. For example, all counterforce materials, whether metal or glass/ceramic exhibit hysteresis to varying degrees. Conventional, epoxy based strain gauges, as are used extensively in weighing devices, also exhibit hysteresis and contribute significantly to the overall hysteresis seen in scale outputs. Apart from strain gauge generation of the effect, the hysteresis phenomenon may also arise from the method of mounting or applying a load to the scale transducer. In this regard, there often is a slippage or movement between the load cell and the scale structure which is manifested as hysteresis.
A conventional approach to improving the hysteresis effect has been to improve the quality of the counterforce or transducer material. For example, lower levels of hysteresis are exhibited by forming the load cells of such materials as beryllium-copper or glass/ceramic materials. However, these approaches are considered overly-expensive for employment with scale structures intended for conventional utilization. The latter materials also are subject to certain manufacturing difficulties. Improvement in hysteresis has been achieved for certain applications by varying production parameters and heat treating procedures. However, these techniques are heuristic in nature and essentially non-repeatable from component to component. While a hysteresis effect will appear in the strain gauges of load cell instrumentation, other sensors such as those representing the vibrating wire or capacitor technique do not exhibit hysteresis in and of themselves but the phenomenon will appear in the output of cells having such instrumentation, inasmuch as it remains within the overall counterforce structure.
With the advent of microprocessor driven instrumentation, a practical approach to this phenomenon will be to achieve a predictive method for digital correction of hysteresis at the load cell output. However, this approach requires an accurate quantification of the hysteresis based behavior of load cells. Such a predictive digital correction approach has been successfully introduced with respect to creep pheomenon. See in this regard U.S. Pat. No. 4,691,290 entitled "Creep-Compensated Weighting Apparatus" by Griffen, issued Sep. 1, 1987, and assigned in common herewith.

Hysteresis-compensated weighing apparatus and method


A compound truck leveler for use upon a driveway abutting a loading dock is provided that includes an incline portion having a trailing edge disposed further from the driveway than its leading edges, and a decline portion having a leading edge rigidly attached to the trailing edge of the incline portion and disposed further from the driveway than its trailing edge. The leveler is pivotally attached to a pivot apparatus rigidly attached to the driveway adjacent to the front of the leveler wherein the leveler is limited only to rotational movement about the pivot apparatus between lowered and raised positions. Preferably, the leveler also includes an extension portion extending towards the loading dock and rigidly attached to the decline portion wherein the extension is substantially parallel with the driveway in the lowered position. The pivot point of the leveler is preferably disposed further from the driveway than the rear of the leveler.

A variety of truck levelers have been devised to adjust the height of different trailers to properly match the deck of the trailer to the height of the dock. By aligning the height of the trailer and the dock the loading and unloading of cargo is facilitated.
One such device is seen in U.S. Pat. No. 4,624,446 to Gould which discloses a reinforced platform pivotally mounted to the ground at one end and includes a support assembly having hydraulic cylinders. In operation the rear wheels of a truck trailer are backed onto the platform and then the non-mounted end of the platform is lifted by the hydraulic cylinders until the deck of the trailer is equal to the height of the dock.
A similar device is disclosed in U.S. Pat. No. 4,765,792 to Cherry et al. which also discloses a pivotally-mounted and hydraulically-raised platform. In addition to the disclosure of Gould, the device includes mounting the hydraulics inwardly from the non-mounted end of the platform and an aperture in the non-mounted end of the platform to accommodate a truck restraining device.
Another design is disclosed in U.S. Pat. No. 6,368,043 to Leum et al. which teaches a low-profile truck leveler. In this design a low-profile leveler is enabled through the use of a raised rear beam and two lateral beams that extend above the upper surface of the platform. In addition, a central beam adds further to the leveler's strength and rigidity.


A control valve for a variable displacement compressor. The control valve has a valve body for regulating a gas passage. A bellows actuates the valve body in accordance with an operating pressure introduced to a pressure sensing chamber. A solenoid biases the valve body with a force based on the electric current supplied to the solenoid. A cylindrical cap is fitted to a cylindrical portion provided on a housing of the control valve. The bellows is located in the pressure sensing chamber. The axial position of the cap in relation to the cylindrical portion is adjusted such that the bellows is positioned at a specific initial position when a pressure having a predetermined magnitude is introduced to the pressure sensing chamber and when a current having a predetermined value is supplied to the solenoid. The cap is secured to the cylindrical portion by crimping with the bellows positioned at the initial position.

The present invention relates to a displacement control valve incorporated in variable displacement compressors that are used in vehicle air conditioners
Japanese Unexamined Patent Publication No. 7-180659 discloses one type of a variable displacement compressor. As shown in FIG. 9, the compressor includes a cylinder block 204 and a rear housing 205 secured to each other with a valve plate 206 in between. A supply passage 202 is defined in the cylinder block 204 and the rear housing 205. The rear housing 205 includes a discharge chamber 201 and a suction chamber 208. The discharge chamber 201 is connected to a crank chamber (not shown) by the supply passage 202. The supply passage 202 is regulated by a displacement control valve 203. The control valve 203 controls the opening amount or the supply passage 202 in accordance with the cooling load thereby adjusting the amount of highly pressurized refrigerant gas that is supplied to the crank chamber from the discharge chamber 201. Accordingly, the pressure in the crank chamber is changed. Changes in the crank chamber pressure alter the difference between the pressure in the crank chamber and the pressure in cylinder bores (not shown). This adjusts the inclination of a swash plate (not shown) of the compressor and ultimately changes the displacement of the compressor.
The control valve 203 includes a reed valve flap 207 for opening and closing the supply passage 202. The reed valve flap 207 is located on the valve plate 206. The rear housing 205 further has a pressure sensing chamber 209 defined therein. The chamber 209 is communicated with the suction chamber 208 and accommodates a bellows 210. The bellows 210 functions as a pressure reacting member that is expanded and collapsed in accordance with the pressure in the suction chamber 208. The distal end of the bellows 210 is coupled to a rod 211. The distal end of the rod 211 contacts the reed valve plate 207. The rod 211 transmits expansion and contraction of the bellows 210 to the valve plate 207. Accordingly, the valve plate 207 opens or closes the supply passage 202.
The pressure sensing chamber 209 opens to the rear end of the rear housing 205. The opening is machined to form a threaded portion 212 for receiving a threaded plug 213, to which the bellows 210 is fixed. The plug 213 also has a recess 213a defined in its rear end for receiving a fastening tool. The plug 213, to which the bellows 210 is fixed, is screwed into the threaded portion 212 by rotating the plug 213 by a fastening tool engaged with the recess 213a. In this manner, the bellows 210 is installed in the pressure sensing chamber 209. At this time, the initial position of the bellows 210 in the axial direction is determined by the position of the plug 213, which is determined by the number of rotation it is given. The initial position of the bellows 210 determines the responsiveness of the reed valve 207 to the pressure in the suction chamber 208.
However, in the control valve 203, the threaded portion 212 is formed in the wall of an opening of the pressure sensing chamber 209, and the plug 213 must be threaded to correspond to the threaded portion 212. This complicates the manufacture and assembly of the control valve 203 and increases the cost.
Also, it is difficult and troublesome to accurately determine the initial position of the bellows 210 in the axial direction by changing the position of the plug 213. After determining the initial position of the bellows 210, operation of the compressor in a vehicle can displace the bellows 210 from the determined initial position.

Control valve in variable displacement compressor and its assembling method

Kabushiki Kaisha Toyoda Jidoshokki Seisakusho


In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.

1. Field of the Invention
The present invention relates to signal detection in a communication system, and, in particular, to signal detection using noise prediction.
2. Description of the Related Art
Digital communication receivers sample an analog waveform and then detect the transmitted data from the sampled waveform. FIG. 1 shows a block diagram of a type of communication system 100 termed a generic SERDES (serializer/deserializer) communication channel, where impairments added in the channel are due to characteristics of a physical transmission medium for the channel, such as a backplane. In a primary channel 150, data u(n) at a transmitter is modulated by modulator 101. Modulator 101 employs modulation, such as non-return to zero (NRZ) or pulse amplitude modulation (PAM), to generate a modulated data signal a(n). The modulated data a(n) is then transmitted through backplane channel 103 after pre-equalization or pre-filtering through a transmit FIR filter (TXFIR) 102. After passing through backplane channel 103, the analog signal a(n) might be filtered by the receiver's equalizer (RXEQ) 104 which might include a continuous time filter (shown in FIG. 1 as an analog equalizer or "AEQ"). The analog signal y(t) provided by RXEQ 104 is sampled by sampler 105 at the baud rate based on a CDR sampling clock generated by a clock/data recovery (CDR) circuit (not shown in FIG. 1) to generated samples y(n).
The phase of the analog waveform applied to RXEQ 104 is typically unknown and might include a frequency/phase offset between the frequency at which the original data was transmitted and the nominal receiver's sampling clock frequency of the CDR circuit.
The CDR circuit desirably causes sampling of the analog waveform y(t) such that when the sampled waveform y(n) is passed through a data detector 106, the data is recovered properly despite that the phase/frequency of the analog waveform y(t) is not known. The CDR circuit is often implemented as an adaptive feedback circuit and the feedback loop adjusts the phase and frequency of the nominal clock to produce a modified clock, termed a recovered clock, employed by sampler 105.
After sampling y(t) to produce sampled output y(n)=y(nT), where T is the sampling and baud period, data detector 106 generates an estimate â(n) of the original modulated data a(n). Data detector 106 might be implemented as a simple slicer (a decision device based on an amplitude threshold) or a more complicated detector, such as a sequence or Viterbi detector. For high-speed applications, data detector 106 is often implemented as a slicer that is also clocked by the CDR sampling clock signal from the CDR circuit. The slicer quantizes the values of y(n) to a binary "1" or "0" based on the sampled analog value y(n) and a slicer threshold st. The slicer threshold st might typically be 0, as indicated in FIG. 1. If the input to the slicer at sampling moment n is w(n) (which, for FIG. 1, might be equivalent to y(n)), then the output value â(n) of the slicer is given as follows in equation (1), where the logic "1" and "0" are represented as corresponding signed values "1" and "−1":
                                          a            ^                                          (            n            )                          =                  {                                                                      1                  ,                                                                                if                                                                                w                                                                    (                        n                        )                                                                              >                                      s                    t                                                                                -                    1                                    ,                                                            otherwise                                                                        (        1        )            The estimates â(n) of the original modulated data a(n) are applied to demodulator 107 which demodulates the estimates â(n) to generate estimates û(n) of the original data u(n).
Several other impairment sources are also shown in FIG. 1. The left side of FIG. 1 shows a number of cross-talk paths 151(1) though 151(Nx) whose individual path outputs sum to create an overall cross-talk impairment signal v(t) added to the signal path of primary channel 150. Also shown in FIG. 1 is additive noise n(t) that might arise during processing within RXEQ 104 (e.g., n(t) is self-noise or output-referred noise of the AEQ). Although the figures herein each show the pre-filtering in the cross-talk paths with filters TXFIR 153(1) though TXFIR 153(Nx) similar to TXFIR 102 of primary channel 150, this is not necessarily the case in practice and does not affect the analysis herein.
As data rates increase for a particular SERDES channel application, the SERDES channel's performance degrades. Consequently, many SERDES channel applications use a decision feedback equalizer (DFE) at the receiver in conjunction with the pre-equalization through the transmit FIR filter (TXFIR).
FIG. 2 shows a block diagram of a SERDES system 200 such as discussed above with respect to FIG. 1 incorporating a traditional DFE 108. A correction, z(n), generated by DFE 108 is subtracted in combiner 109 from the signal, y(n), from sampler 105 to produce signal w(n) as given by equation (2):w(n)=y(n)−z(n).  (2)The output z(n) of DFE 108 is given by equation (3):z(n)=Σl=1Lb(l)â(n−l),  (3)where b(l) represents the coefficients of the L-tap DFE.
From equation (3), DFE 108 receives as its input the past L-modulated data estimates (also referred to herein as "decisions") from data detector 106 ending at â(n−1). DFE filtering as given in equation (3) does not employ the current decision at â(n) so that the filtering operation of the DFE is causal. In operation, the entire DFE loop correction is desirably performed within one baud period T before the next correction is needed. In some cases, to avoid a speed bottle neck at very high data rates, a well-known technique is often employed whereby the DFE terms are pre-computed and selected based on the amplitude values of y(n). With this technique, since a DFE feedback loop is absent, the process of generating the DFE "corrected" decisions might be pipelined.
A DFE has the benefit of canceling post-cursor inter-symbol intereference (ISI) without enhancing input noise/cross-talk. However, the DFE does not directly cancel residual cross talk in the primary channel.

Noise prediction-based signal detection and cross-talk mitigation


The invention is directed to a control element, particularly in a central control unit. A magnet clamping system is integrated into a control element in order to render the function “slider setting” unequivocal. In addition to an actuator head that is positioned on a shaft, which is guided in a cylinder, for example, and at least one circuit board having LEDs, the control element includes a magnetic device having a designated magnet, which is functionally connected to the actuator head. When the actuator head is moved vertically by sliding, the magnetic device lifts off the magnet due to tilting, which causes a code disc attached to the actuator head to be brought into an inclined position such that a light flow on the light barriers formed by the LEDs is disrupted and/or opened up. In a further embodiment, this control element also includes press and rotate functions.

1. Field of the Invention
The present invention relates to a control element, particularly in a central control unit.
2. Description of the Background Art
From "Mensch-Maschine-Interface," Proseminar Software for automotive control devices, by Gary Weissenbacher, pages 7 to 10, a control element is disclosed, which in addition to rotate and press functions, is also provided with tilt and slide functions on the same operative plane.
With these conventional devices, the tilt and slide functions of the control knob or the actuator knob can lead to indefinable positions of the knob, and thus the function selection.
An activation element similar to a joystick with a preferably flat configuration, is disclosed in DE 101 52 978.3. The activation element is configured such that the activation knob can be brought, or pressed, into four different contact positions, whereby only one contact is made. A contact mat used in the activation element can be clipped onto a circuit board, and is a quadruple contact mat. In the contact center, space is provided in the contact mat for an LED so that the symbols on the activation element can be illuminated.


Techniques, systems and computer program products are disclosed for providing sensor mapping. In one aspect, a method includes receiving input from a user. The received input includes at least one of motion, force and contact. In addition, a sensor signal is generated based on the received input. From a choice of data structures a data structure associated with a selected application having one or more functions is identified. The data structure indicates a relationship between the generated sensor signal and the one or more functions of the selected application. The generated sensor signal is selectively mapped into a control signal for controlling the one or more functions of the selected application by using the identified data structure.

For different software/firmware applications, the intended purpose and the degree of user input needed may vary across a wide spectrum. These applications can use at least one of two types of input by a human operator: (1) text input, and (2) spatial input. Spatial input translates to control signals that can include defining the x-y coordinates of a mouse cursor, the direction in which a character should move in a game, the orientation and zoom level of a 3D object in a computer aided design (CAD) package or the like.


A cleaning implement includes a cleaning head having a cleaning operation surface on a bottom, a holding portion arranged on the side opposite the cleaning head, a pipe for coupling the cleaning head and the holding portion, and a valve opening and closing device provided to the pipe so as to be able to hold a first container for receiving a first fluid or a second container for receiving a second fluid. The holding portion includes a lever coupled to the valve opening and closing device so as to open and close a first valve of the first container or a second valve of the second container. A first ejection nozzle can eject the first fluid forward of the cleaning head, and a second ejection nozzle can eject the second fluid rearward of the cleaning head.

1. Field of the Invention
The present invention relates to cleaning implement. More particularly, the present invention relates to cleaning implements adapted to covers for floors or carpets, for example, and including a liquid supply device.
2. Related Art
By way of example, a cleaning implement including a liquid supply device is designed to have a cleaning head arranged at a distal end of a stem and a manual operation part arranged at a grip of the stem. A pressure-pump-type discharge container and a pump pusher are arrange at the distal end of the stem, and a coupling member for coupling the manual operating part to the pump pusher is arranged along the stem. By manual operation applied to the manual operation part, the pressure-pump-type discharge container is pressed through the coupling member and the pump pusher, discharging a solution from the discharge container to the cleaning head. Refer, for example, to Patent Document 1 (Japanese Published Unexamined Patent Application 2004-337454).
According to Patent Document 1, the cleaning implement allowing wet wiping is provided, which can operate quietly, discharge a solution stably, and contribute to weight reduction.


A call progress monitor and algorithm for placing a telephone call over the telephone lines. The algorithm is hierarchically arranged having three major routines or portions: tone detection, signal recognition and situation recognition. The tone detection portion of the algorithm measures the power at each of a predetermined number of frequencies of interest. In accordance with one improvement, the data is sampled at a fraction of the rate at which it is supplied, for example, on a T1 channel. The signal recognition portion of the algorithm detects the presence of a particular signal and this stage of the algorithm has been modified to more precisely detect voice. Specifically, power within a voice filter band is compared with power at other predetermined frequencies and a decision is made based on this information. Furthermore, another improved aspect is that data for an entire Epoch is accumulated and stored in a buffer prior to processing as a group. The situation recognition portion of the algorithm determines that a certain sequence or pattern of signals has occurred with a particular timing or cadence.

The present invention relates to a system and method for detecting and discriminating between tone signals and voice particularly on a telephone line.
The prior aforementioned application addresses a need to assist and monitor a computer, such as a telephone network special services switch, placing a telephone call over a telephone network. Specifically, that system and method recognizes and distinguishes the various call progress signals and special information signals, for example, which tell the computer that a particular telephone number is not in service.
It has been discovered that certain telephone systems in common use in the United States and abroad handle particular signals on telephone lines differently. Moreover, certain telephone systems inherently remove certain low frequencies that are useful in detecting and discriminating voice from other signals. The present invention relates to an improvement in the basic system and algorithm of the prior application and, in particular, to a modified voice detection scheme as well as other processing speed enhancement aspects.

Method for monitoring telephone call progress


Compositions are disclosed that induce broadly HIV theraputic and vaccine inducing antibodies against diverse HIV clades and relate to the ability to identify HIV gp120-derived short peptide sequence immunogens and various therapeutic compositions made from the identified peptides which compose CCR5 binding sites. Also disclosed are methods of selecting peptide sequences that are likely candidates for drugs which will offer effective treatment in such areas as Alzheimer's disease, psoriasis, multiple sclerosis and other diseases associated with the human inflammatory cascade as well as related retroviruses such as HTLV-1, the cause of tropical spastic paraparesis.

It is widely believed that a vaccine capable of protecting against HIV-1 infection and AIDS will require immunogens that induce high levels of antibodies with potent neutralization activity against primary isolates of the viruses, irrespective of their geographical origin, subtype or genotype specificity a goal that current vaccine candidates fail to even approach. Therefore, identification of epitopes that mediate broad neutralization is important for rational vaccine design and development. Particularly important is the development of vaccine candidate antibodies to the Clade C sub-types, present in developing nations, compared to the predominant North American Clade B subtype, and comprising an emergent strain with world-wide relevance.
The HIV envelope is the predominant target of neutralizing antibodies in HIV-infected individuals. Some neutralization epitope clusters appear to be exposed at least partially on gp120 env protein of primary and/or monocytotropic isolates. Despite extensive studies, over 20 years, no immunogen capable of eliciting broad vaccine neutralization has been found. For this reason a vaccine against HIV infection has been elusive.
The specific invention involves identification of short sequences of gp120 which bind to the co-receptor CCR5 which identifies peptides capable eliciting antibodies with potent neutralizing activity for diverse HIV strains and peptides that are an important component of an immunization strategy for HIV-1 protection. Antibodies produced to these attachment sequences, comprising binding site peptide immunogens, are anticipated to confer protection against infection by the HIV virus, irrespective of strain, and are also expected to be therapeutic, that is their passive administration will reduce viral levels and provide clinical benefits in persons already infected with HIV
The neutralizing antibody response to HIV-1 infection. Anti-human immunodeficiency virus type neutralization antibodies first appear months after the viremia following initial infection. Early-arising neutralization antibodies are highly type specific. Neutralizing antibodies response may broaden later in infection (16) but usually remain poor and occur sporadically in the majority of patients, including long-term infected individuals.
Neutralization antibodies recognize the HIV-1 envelope glycoproteins, which consist of the gp120 exterior and gp41 transmembrane glycoproteins. The gp120 glycoproteins bind the target CD4 and chemokine receptors CCR5 and CXCR4. Antibodies have in a very few instances been raised to epitopes of the gp120 which are only expressed after gp120 forms a complex with CD4. It is believed that the actual co-receptor binding site, a desired vaccine target, only forms upon CD4 association with gp120. These CD4 induced (CD4i) antibodies block CCR5 and CXCR4 binding of gp120-sCD4 complex. The number of CD4i antibodies isolated from HIV-1 infected humans is low.
Most initial work with HIV-1 vaccines was directed at developing vaccines that elicited neutralization antibodies. These neutralizing antibodies have been narrow in their action and specific almost entirely to strains of the inoculating virus in animal models. These antibodies therefore are not of broad specificity and would not make good vaccine candidates.
Most successful vaccines block virus binding to its receptor(s), which for HIV are the co-receptors CXCR4 and CC5(1, 2). Thus the identification of the co-receptor binding site, a focus of intense scrutiny for the past 20 years, which has not been accomplished until now, would be expected to produce an immunogen capable of yielding the desired broad neutralization of diverse strains suitable for vaccine use.
The subject of this application, in part, is an antibody against a biologically active co-receptor binding site. This antibody showed potent inhibition of gp120-sCD4 complex binding to the CCR5 receptor in studies in vitro and antibodies raised to the proper peptide conformation induce broadly neutralizing antibodies which are therefore expected to provide protective immunity against HIV-1 infection. i.e. a vaccine.
In over more than 10 years, only a few human MAbs that mediate broad and potent neutralization of most HIV-1 isolates have been isolated. Two of these MAbs bind to the surface of gp120 (MAbs b12 and 2G12) (3, 4), and one binds to an epitope just proximal to the membrane spanning domain of gp41. MAb b12 recognizes a complex discontinuous epitope involving the C3-V4 region of gp120 and carbohydrate. MAb 2F5 binds to a linear epitope on the ectodomain of gp41; however, the simplicity of this epitope is deceptive and probably more complex than the six-residue linear sequence MAbs b12, 2G12, and 2F5 have shown in vitro neutralizing activity against a wide variety of primary isolates. All recombinant envelope-based vaccine candidates tested so far in clinical trials, even including epitopes known to mediate broad neutralization did not elicit significant neutralizing antibodies against primary isolates. The peptide based vaccine candidates also fail to elicit adequate immune response.
Homologous sequences to peptide DAPTA (Dala1-peptide T-amide, (5)) are present within V2 of numerous HIV-1 isolates (we have examined 4,078 sequences). Our results with a polyclonal, and a purified IgG antibody against the peptide DAPTA, showed significant neutralization activity against primary and laboratory adapted strains, raising the prospect that the eight sequences from the carboxyl terminus of V2 domain, in close proximity to the bridging sheets represent a new neutralizing epitope.
Generation of Polyclonal Peptide DAPTA Antiserum.
To generate affinity purified antibodies, six rabbits were immunized by sequential subcutaneous injections of: 1) 75 μg peptide DAPTA suspended in Freund's Complete Adjuvant (day 1), 2) 75 μg DAPTA suspended in Freund's Incomplete Adjuvant (day −20) and 3) 150 μg DAPTA without adjuvant (day 35). To test for seroconversion, rabbits were bled from the ear vein on day −1 and weekly thereafter and the sera tested by enzyme-linked immunosorbent assay (ELISA) using microtiter plates coated with purified peptide DAPTA and goat anti-rabbit IgG conjugated to horseradish peroxidase. The seropositive rabbits were subsequently bled by cardiac puncture. Peptide DAPTA antibody present in the antisera was purified by affinity chromatography using affinity sepharose column coupled to purified peptide DAPTA.