A transmission relay system includes a receive antenna with first radiating elements, a transmit antenna with second radiating elements, and processing devices through which the first radiating elements and the second radiating elements are connected. The processing devices are in the form of processing systems all of which induce the same propagation time-delay. Each system connects a given first radiating element to a corresponding given second radiating element defined firstly by an angular position relative to a second axis of symmetry specific to the transmit antenna offset substantially 180.degree. relative to an angular position of the given first radiating element relative to a first axis of symmetry specific to the receive antenna and parallel to the second axis of symmetry and secondly by an eccentricity in the transmit antenna which is a function of an eccentricity of the given first radiating element in the receive antenna.

1. Field of the Invention
The present invention concerns a transmission relay system, or re-transmitter unit, which receives a first signal on a first carrier frequency from a remote point to re-transmit on a second carrier frequency a second signal in the form of a beam covering a geographical area. The first and second carrier frequencies can be the same and the first and second signals modulating these two carrier frequencies can be the same signal.
The invention finds applications in satellite telecommunication systems, for example. Embodiments of the invention apply to a surveillance satellite system or a low altitude satellite system. The signal carried by the first carrier frequency is transmitted by a ground station to a satellite. A transmission relay system in the latter re-transmits a signal carried by the second carrier frequency.
2. Description of the Prior Art
One prior art solution uses beam forming networks (BFN) which adjust the phase of the signal produced by each radiating element to form a beam that is transmitted with a particular wavefront defining the orientation of the beam.
As shown in FIG. 1, in some satellite telecommunication networks at least one satellite 1 re-transmits each signal UP received from a base station 2 in the opposite direction to this received signal. Thus the satellite 1 is used as a relay to form a beam DOWN covering a geographical area centered on the base station from which it has received a signal. In such applications conventional beam forming networks can be used. This then implies complex processing on board the satellite for the application concerned.
A first objective of the invention is to remedy this drawback by providing a transmission relay system of low technical complexity for an application of the type limited to re-transmitting the received signal in the opposite direction.
A second objective of the invention is to provide a particularly advantageous transmit and receive antenna geometry.


A method is proposed for measuring tools on a machine tool with a measuring device, wherein by means of a movement of a spindle of the machine tool the measuring device is temporarily positioned at a measuring point on the machine tool in order to carry out one or more measurements, the measuring point differing from a spindle mount. Furthermore, a measuring apparatus is proposed which is embodied in such a way that the measuring device can be positioned at a measuring point on the machine tool for a measuring operation by means of a spindle movement of a machine tool, said measuring point differing from a spindle mount.

Methods which are designated in the introduction and measuring apparatuses are already known in various embodiments from the prior art.
In one embodiment, a tool measuring device is attached to a table of a machine tool in a position in which tools which are arranged in a spindle of the machine tool can reach the measuring device to be measured by it.
Before a measurement operation, the tool measuring device is standardized. To do this, a standardization tool whose geometry is known is used. The standardization tool approaches a sensor of the tool measuring device in a rotating or stationary fashion until the latter outputs a signal to a machine tool controller. The signal is used by a machine tool controller to store the position of the axle.
Tools to be measured are moved to the tool measuring device in the same ways as the standardization tool. From the difference between the axle values and the axle values of the standardization it is possible to calculate the geometry of the tool. There are various possible ways of transmitting signals from the tool measuring device to the tool machine controller. For example, the signal transmission is carried out with a cable. It is also known to transmit coded infrared signals to a receiver device which is connected to the machine tool controller by means of a cable. Instead of encoded infrared light signals it is also possible to use encoded radio signals.
The described procedure has a series of disadvantages. The tool measuring device is located in a fixed location on the machine tool. If it is the machine table, which normally is appropriate, the clamping surface for the workpiece is restricted.
In particular, tool measuring devices which are mounted on a machine table are at risk of collision. Any collision can result in damage.
Furthermore, a tool measuring device on a machine table is subjected to soiling by the processing of a workpiece, which runs off onto the machine table.

Method for measuring tools with a measuring device, and measuring apparatus with a measuring device for measuring tools


One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming FinFET semiconductor devices using a replacement gate technique and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device "A" that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source drain regions. Even if an epi "merger" process is not performed, an epi growth process will typically be performed on the fins C to increase their physical size.
In the FinFET device A, the gate structure D may enclose both sides and the upper surface of all or a portion of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a single fin FinFET device, the "channel-width" is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned "OFF" is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the "fin" channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond. The gate structures D for such FinFET devices may be manufactured using so-called "gate-first" or "replacement gate" (gate-last) manufacturing techniques.
For many early device technology generations, the gate structures of most transistor elements (planar or FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon (TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called "gate last" or "replacement gate" technique. The replacement gate process may be used when forming planar devices or 3D devices. FIGS. 1B-1E simplistically depict one illustrative prior art method for forming an HK/MG replacement gate structure using a replacement gate technique on a planar transistor device. As shown in FIG. 1B, the process includes the formation of a basic transistor structure above a semiconducting substrate 12 in an active area defined by a shallow trench isolation structure 13. At the point of fabrication depicted in FIG. 1A, the device 10 includes a sacrificial gate insulation layer 14, a dummy or sacrificial gate electrode 15, sidewall spacers 16, a layer of insulating material 17 and source/drain regions 18 formed in the substrate 12. The various components and structures of the device 10 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 14 may be comprised of silicon dioxide, the sacrificial gate electrode 15 may be comprised of polysilicon, the sidewall spacers 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopants for PMOS devices) that are implanted into the substrate 12 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 10 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon/germanium that are typically found in high performance PMOS transistors. At the point of fabrication depicted in FIG. 1B, the various structures of the device 10 have been formed and a chemical mechanical polishing (CMP) process has been performed to remove any materials above the sacrificial gate electrode 15 (such as a protective cap layer (not shown) comprised of silicon nitride) so that at least the sacrificial gate electrode 15 may be removed.
As shown in FIG. 1C, one or more etching processes are performed to remove the sacrificial gate electrode 15 and the sacrificial gate insulation layer 14 to thereby define a gate cavity 20 where a replacement gate structure will subsequently be formed. Typically, the sacrificial gate insulation layer 14 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 14 may not be removed in all applications.
Next, as shown in FIG. 1D, various layers of material that will constitute a replacement gate structure 30 are formed in the gate cavity 20. Even in cases where the sacrificial gate insulation layer 14 is intentionally removed, there will typically be a very thin native oxide layer (not shown) that forms on the substrate 12 within the gate cavity 20. The materials used for the replacement gate structures 30 for NMOS and PMOS devices are typically different. For example, the replacement gate structure 30 for an NMOS device may be comprised of a high-k gate insulation layer 30A, such as hafnium oxide, having a thickness of approximately 2 nm, a first metal layer 30B (e.g., a layer of titanium nitride with a thickness of about 1-2 nm), a second metal layer 30C—a so-called work function adjusting metal layer for the NMOS device—(e.g., a layer of titanium-aluminum or titanium-aluminum-carbon with a thickness of about 5 nm), a third metal layer 30D (e.g., a layer of titanium nitride with a thickness of about 1-2 nm) and a bulk metal layer 30E, such as aluminum or tungsten.
Ultimately, as shown in FIG. 1E, one or more CMP processes are performed to remove excess portions of the gate insulation layer 30A, the first metal layer 30B, the second metal layer 30C, the third metal layer 30D and the bulk metal layer 30E positioned outside of the gate cavity 20 to thereby define the replacement gate structure 30 for an illustrative NMOS device. Typically, the replacement gate structure 30 for a PMOS device does not include as many metal layers as does an NMOS device. For example, the gate structure 30 for a PMOS device may only include the high-k gate insulation layer 30A, a single layer of titanium nitride—the work function adjusting metal for the PMOS device—having a thickness of about 3-4 nm, and the bulk metal layer 30E.
FIG. 1F depicts the device 10 after several process operations were performed. First, one or more etching processes were performed to remove upper portions of the various materials within the cavity 20 so as to form a recess within the gate cavity 20. Then, a gate cap layer 31 was formed in the recess above the recessed gate materials. The gate cap layer 31 is typically comprised of silicon nitride and it may be formed by depositing a layer of gate cap material so as to over-fill the recess formed in the gate cavity and, thereafter, performing a CMP process to remove excess portions of the gate cap material layer positioned above the surface of the layer of insulating material 17. The gate cap layer 31 is formed so as to protect the underlying gate materials during subsequent processing operations.
As the gate length of transistor devices has decreased, the physical size of the gate cavity 20 has also decreased. Thus, it is becoming physically difficult to fit all of the layers of material needed for the replacement gate structure 30, particularly for NMOS devices, due to the greater number of layers of material that are typically used to form the gate structures for the NMOS devices, within the reduced-size gate cavity. For example, as gate lengths continue to decrease, voids or seams may be formed as the various layers of material are deposited into the gate cavity 20. FIG. 1G is a somewhat enlarged view of an illustrative NMOS device that is provided in an attempt to provide the reader with some idea of just how limited the lateral space 20S is within the gate cavity 20 of an NMOS device as the various metal layers 30A-30D are formed in the gate cavity 20. In FIG. 1G, the internal sidewall surfaces of the spacers 16 define a gate cavity 20 having a substantially uniform width 20S throughout the height or depth of the gate cavity 20. As the layers of material in the gate stack for the device are formed in the cavity 20, the remaining space 39 within the gate cavity 20 becomes very small. As the latter metal layers are formed, the lateral space 39 may be about 1-2 nm in width or even smaller. In some cases, the space 39 may be essentially non-existent. This may lead to so-called "pinch-off" of metal layers such that voids or seams may be formed in the overall gate stack, which may result in devices that perform at levels less than anticipated or, in some cases, the formation of devices that are simply not acceptable and have to be discarded. Additionally, an etch-back process is traditionally performed on the layers 30A-D to make room within the upper portion of the gate cavity 20 for a bulk conductor material, such as tungsten and aluminum, and a gate cap layer. During this recess etching process, some form of a protective material must be formed in the gate cavity 20 above the metal layer 30D to protect desired portions of the underlying metal layers during the recess etching process. If the lateral space 39 (to the extent it exists) cannot be reliably filled with such a protective material, such as a flowable oxide material, then the recessing etching process cannot be performed for fear of removing undesired portions of the metal layers during the course of performing the recess etching process.
Over recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the "packing density," i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end that is connected to a respective metal line in the metallization layer by a conductive via. As device dimensions have decreased, the conductive contact elements in the contact level have to be provided with critical dimensions in the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. For this reason, contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structure, the gate electrode structures are used as etch masks for selectively removing the silicon dioxide material in order to expose the source/drain regions of the transistors, thereby providing self-aligned trenches which are substantially laterally delineated by the spacer structures of the gate electrode structures.
However, the aforementioned process of forming self-aligned contacts results in an undesirable loss of the materials that protect the conductive gate electrode, i.e., the gate cap layer and the sidewall spacers, as will be explained with reference to FIGS. 2A-2B. FIG. 2A schematically illustrates a cross-sectional view of an integrated circuit product 40 at an advanced manufacturing stage. As illustrated, the product 40 comprises a plurality of illustrative gate structures 41 that are formed above a substrate 42, such as a silicon substrate. The gate structures 41 are comprised of an illustrative gate insulation layer 43 and an illustrative gate electrode 44 that are formed in a gate cavity 20 using a gate-last processing technique. An illustrative gate cap layer 46 and sidewall spacers 48 encapsulate and protect the gate structures 41. The gate cap layer 46 and sidewall spacers 48 are typically made of silicon nitride. Also depicted in FIG. 2A are a plurality of raised source/drain regions 50 and a layer of insulating material 52, e.g., silicon dioxide. FIG. 2B depicts the product 40 after a contact opening 54 has been formed in the layer of insulating material 52 for a self-aligned contact. Although the contact etch process performed to form the opening 54 is primarily directed at removing the desired portions of the layer of insulating material 52, portions of the protective gate cap layer 46 and the protective sidewall spacers 48 get consumed during the contact etch process, as simplistically depicted in the dashed regions 56. Given that the cap layer 46 and the spacers 48 are attacked in the contact etch process, the thickness of these protective materials must be sufficient such that, even after the contact etch process is completed, there remains sufficient cap layer material and spacer material to protect the gate structures 41. Accordingly, device manufacturers tend to make the cap layers 46 and spacers 48 "extra thick," i.e., with an additional thickness that may otherwise not be required but for the consumption of the cap layers 46 and the spacers 48 during the contact etch process. In turn, increasing the thickness of such structures, i.e., increasing the thickness of the gate cap layers 46, causes other problems, such as increasing the aspect ratio of the contact opening 54 due to the increased height, increasing the initial gate height, which makes the gate etching and spacer etching processes more difficult, etc.
As device dimensions continue to shrink, self-aligned contacts are needed to prevent an electrical short between the gate and the source/drain contact element. As noted above, in prior art processing techniques, a relatively thick gate cap layer 46 (e.g., silicon nitride) is formed to protect the underlying metal layers in the gate electrode 44 from being exposed during the source/drain contact etch process which results in the formation of the contact opening 54 (see FIGS. 2A-2B). If the gate electrode materials are exposed during the contact etch process, then an electrical short will be formed between the gate electrode 44 and the source/drain contact element (not shown) that will be formed in the contact opening 54. There are two ways to "make room" in the gate cavity 20 for the gate cap layer 46 by recessing the work function metal materials within the gate cavity 20. A first approach involves filling the remaining portions of the gate cavity 20 with a relatively thick work function metal until it (collectively) is "pinched-off" within the gate cavity 20, and thereafter performing an etching process to recess it down, thereby making room for the gate cap layer 46. This approach is very challenging due to the fact that the work function metals are typically comprised of multiple layers of metal (e.g., TiN/TiC/TiN. TiN/TaC/TiN, etc.) that are layered within the gate cavity 20 so that a uniform recess is not easy to form by a single etch-back process. Also, due to the "pinch-off" that typically occurs when forming such layers of metal, there are inevitable void/seam formations due to the very small size of the gate cavity as these material layers are formed, which further increases the difficulty of the etch-back process that is performed to recess the various metal layers. A second approach involves formation of relatively thinner work function metal layer(s) so as to not "pinch-off" the gate cavity 20, then fill in the sacrificial material, such as OPL or a flowable oxide, that can reliably fill the remaining portions of the gate cavity 20. Then, the sacrificial material may be recessed so as to expose the desired portions of the work function metal to be removed, the exposed portions of the work function metals are then removed by etching while the remaining portions of the sacrificial material protect the underlying metal layers. Thereafter, the sacrificial material may be removed from within the gate cavity 20. While this latter approach tends to produce better results, as gate lengths continue to shrink (e.g., 15 nm or less), the required work function metal thickness (e.g., 7 nm) simply fills too much of the gate cavity, with the result being that there is little, if any, space left within the gate cavity 20 for the sacrificial material that is used in the recess etching process.
The present disclosure is directed to various methods of forming FinFET semiconductor devices using a replacement gate technique and the resulting semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.

Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices

International Business Machines Corporation


The present invention relates to an aqueous transfer buffer that provides superior efficiency in transferring polypeptides of a broad range of molecular weight from a matrix used in electrophoresis to another immobilized surface. Also disclosed are electrophoretic methods and devices in which the aqueous transfer solution of this invention is used.

1. Field of Invention
This invention resides in the field of electrophoretic transfer of macromolecules, such as proteins and nucleic acids, and relates in particular to the transfer of polypeptide species from a matrix following electrophoresis, during which the polypeptide species were separated, to a second substrate for further detection and characterization.
2. Description of Prior Art
Electrophoresis is a fundamental tool in the modern laboratories of biological research. Typically, macromolecules such as proteins and nucleic acids become separated during electrophoresis as they migrate through a solid matrix in an electrical field. At the conclusion of an electrophoresis procedure, the macromolecules are found in distinct locations of the matrix depending on characteristics of the molecules such as molecular weight and electrical charge. Further studies of such macromolecules often require that the molecules be relocated to a second substrate where better reaction conditions are permitted. Electroblotting is one example of the post-electrophoresis transfer.
Numerous methods of electroblotting are well known and frequently practiced in the art. The transfer process is usually carried out in a liquid or semi-liquid environment where the macromolecules within an electrophoresis matrix, such as a polyacrylamide gel, is transferred to a second matrix suitable for further analysis, such as a membrane of nitrocellurose, nylon, etc. The movement of the macromolecules from the electrophoretic matrix to the analytical matrix is facilitated by an aqueous transfer buffer, which plays an important role in the efficiency of the transfer.
Various publications describe transfer buffers useful for the purpose of electroblotting, see, e.g., Towbin et al. (1979) Proc. Natl. Acad. Sci. USA 76:4350-4354; Timmons and Dunbar (1990) Methods in Enzymology 182:679-688. The present inventors provide a new aqueous transfer buffer that offers improved transfer efficiency, especially for polypeptides of relatively low molecular weight range.


A method for administering a camptothecin to a patient comprising: injecting into a patient a pharmaceutical composition comprising an aqueous suspension of microdroplets suitable for intravenous delivery, the microdroplets having a mean diameter between 200 Angstroms and one micron, the microdroplets comprising a substantially water-insoluble, pharmacologically acceptable liquid, a camptothecin dissolved in the water-insoluble, pharmacologically acceptable liquid, and an outer layer comprising a phospholipid. The pharmaceutical composition is particularly well suited for delivering camptothecins, particularly 9-nitro-camptothecin intravenously.

1. Field of the Invention
This invention relates to compositions and methods for delivering camptothecin, in particular, 9-nitro-camptothecin, to patients by injection and treating diseases associated with abnormal cell proliferation such as cancer.
2. Description of Related Art
Camptothecin was isolated from the plant, Camptotheca acuminata, in the 1960""s (Wall, M. et al. (1966) J. Am. Chem. Soc. 88: 3888-3890). Camptothecin has a pentacyclic ring system with only one asymmetric center in ring E with a 20(S)-configuration. The pentacyclic ring system includes a pyrrole quinoline moiety (rings A, B and C), a conjugated pyridone (ring D), and a six-membered lactone (ring E) with an xcex1-hydroxyl group (i.e., an xcex1-hydroxy lactone).
Camptothecin itself is highly lipophilic and poorly water-soluble. Sodium camptothecin that is solubilized by sodium hydroxide in water was used in clinical trials in the early 70""s and found to have antitumor activity. However, this formulation of camptothecin administered via i.v. caused unpredictable side effects such as myelosuppression and hemorrhagic cystitis. Clinical trials with sodium camptothecin were eventually discontinued because of these toxicities and the lack of consistent antitumor activity.
Continued evaluation of this agent showed that the sodium carboxylate salt is only 10% as potent as the native camptothecin with the closed xcex1-hydroxy lactone ring intact (Wall et al. in (1969) xe2x80x9cInternational Symposium on Biochemistry and Physiology of the Alkaloids, Mothes et al. eds. Academic Verlag, Berlin, 77; Giovanella et al. (1991) Cancer Res. 51:3052). Studies also showed that camptothecin and its derivatives undergo an alkaline hydrolysis of the E-ring xcex1-hydroxy lactone, resulting in a carboxylate form of camptothecin. At pH levels below 7.0, the xcex1-hydroxy lactone E-ring form of camptothecin predominates. However, intact lactone ring E and xcex1-hydroxyl group have been shown to be essential for antitumor activity of camptothecin and its derivatives.
Camptothecin and its derivatives have been shown to inhibit DNA topoisomerase I by stabilizing the covalent complex (xe2x80x9ccleavable complexxe2x80x9d) of enzyme and strand-cleaved DNA. Inhibition of topoisomerase I by camptothecin induces protein-associated DNA single-strandbreaks which occur during the S-phase of the cell cycle. Since the S-phase is relatively short compared to other phases of the cell cycle, longer exposure to camptothecin should result in increased cytotoxicity of tumor cells. Studies indicate that only the closed xcex1-hydroxy lactone form of the drug helps stabilize the cleavable complex, leading to inhibition of the cell cycle and apoptosis.
To preserve the xcex1-hydroxy lactone form of camptothecin, camptothecin and its water insoluble derivatives have been dissolved in N-methyl-2-pyrrolidinone in the presence of an acid (U.S. Pat. No. 5,859,023). Upon dilution with an acceptable parenteral vehicle, a stable solution of camptothecin was obtained. The concentrated solution of camptothecin was also filled in gel capsules for oral administration. It is believed that such formulations increase the amount of lipophilic xcex1-hydroxy lactone form of camptothecin that diff-use through the cellular and nuclear membranes in tumor cells.
T. G. Burke, A. E. Staubus, A. K. Mishra and H. Malak (xe2x80x9cLiposomal Stabilization of Camptothecin""s Lactone Ring.xe2x80x9d J. Am. Chem. Soc. 1992, 114, 8318) and T. G. Burke, A. K. Mishra, M. C. Wani and M. E. Wall (xe2x80x9cLipid bilayer partitioning and stability of camptothecin drugs.xe2x80x9d Biochemistry 1993 May 25;32 (20):5352-64) have demonstrated that harboring of camptothecin drugs into phospholipid bilayer membranes stabilized the xcex1-hydroxy lactone moiety of camptothecin drugs against hydrolysis. In comparison to hydrolysis half-lives in PBS at 37xc2x0 C. of approximately 15 to 30 min, lipid bilayer membrane-bound camptothecin drugs were found to be stable even for periods up to 72 hours. These authors have determined an iodide ion induced quenching behavior of camptothecin""s fluorescence indicative of intercalation of camptothecin molecules between the phospholipid acyl chains of membrane bilayers, a protected environment removed from the aqueous interface. The potential for stabilization of camptothecin""s xcex1-hydroxy lactone ring structure in this environment led to the expectation that lipid bilayer intercalation might conserve the biologically active form in vivo, thereby permitting the active form to be delivered via liposomal bilayers into a biological host (U.S. Pat. No. 5,552,156).
Z Mi and T. G. Burke (xe2x80x9cDifferential interactions of camptothecin lactone and carboxylate forms with human blood components.xe2x80x9d Biochemistry 1994 Aug 30;33 (34):10325-36) exploited the intrinsic fluorescent emissions from the xcex1-hydroxy lactone and carboxylate forms of camptothecin in order to elucidate their markedly different interactions with the various components of human blood. It was found that in PBS at pH 7.4, human serum albumin (HSA) preferentially binds the carboxylate form of camptothecin with a 150-fold higher affinity than the xcex1-hydroxy lactone form. These interactions cause camptothecin""s xcex1-hydroxy lactone ring to open more rapidly and completely in the presence of HSA than in the protein""s absence. In human plasma, at pH 7.4 and 37xc2x0 C., they have observed camptothecin""s xcex1-hydroxy lactone ring to open rapidly and fully to the carboxylate form (half-life=11 min; % xcex1-hydroxy lactone at equilibrium, 0.2%). They concluded that camptothecin carboxylate""s fluorophore locates in a hydrophobic binding pocket in native HSA. In whole blood versus plasma, camptothecin""s xcex1-hydroxy lactone was found to display enhanced stability resulting in an increased half-life of 22 min and an equilibrium xcex1-hydroxy lactone concentration of 5.3%. The enhanced stability of camptothecin in human blood was found to be due to drug associations with the lipid bilayers of red blood cells. Although camptothecin xcex1-hydroxy lactone hydrolysis slows down and the equilibrium xcex1-hydroxy lactone form concentration rises on intercalation within phospholipid bilayers, the membrane-bound drug still remains thermodynamically and kinetically too labile in the presence of albumin and the concentration of the active xcex1-hydroxy lactone form in plasma remains insufficient. Thus, the liposomal bilayers cannot be considered as a pragmatic delivery system for this drug. It is speculated that a principal deactivation channel of membrane bilayer-bound camptothecin is facilitated via high affinity of the carboxylate form of the drug with albumin in-vivo compared to a relatively lower affinity of the xcex1-hydroxy lactone form of the drug with the membrane bilayers.
U.S. Pat. Nos. 5,552,156 and 5,736,156 describe liposomes and micelles of surfactant molecules for intravenous delivery of camptothecins. In liposomes, the camptothecin can reside bound to and partially in the membrane interlayer or dissociate into the internal enclosed aqueous layer in direct contact with water where the camptothecin lactone is not stable to hydrolysis. In micelles of surfactant molecules, the camptothecin is either in the central hydrocarbon portion of the micelle, bound to the micelle membrane or bound to the outside of the micelle. However, while camptothecins are less stable in micelles than in liposomes, especially in poly(ethylene oxide)-containing micelles, the amount of camptothecin compound that can bind to the membrane layer in a liposome is limited to the dimensions of the membrane and to the requirement that the membrane remain intact to prevent rupture of the liposome. The ratio of lipid to camptothecin in liposomes is generally greater than 150, and the lactone of the camptothecin slowly hydrolyzes because of the reported equilibrium between bound and free camptothecin.
The present invention provides novel injectable formulations of camptothecin, including analogs, derivatives, and pharmaceutically active metabolites of 20(S)-camptothecin, referred to herein as camptothecin compound. The present invention also provides methods of manufacturing these formulations, kits containing these formulations and methods of using these formulations to treat patients having diseases associated with abnormal cell proliferation, such as cancer.
One class of injectable formulations comprise micron and submicron size particle suspensions of a camptothecin. These micron and submicron size particle suspensions of camptothecin substantially reduce deactivation of the canptothecin by hydrolysis in-vitro and by plasma components in-vivo. The particle suspensions of the present invention display efficacy in the treatment of diseases associated with abnormal cell proliferation such as cancer when injected intravenously into mammals containing such diseases. The micron and submicron size particle suspensions of xcex1-hydroxy lactone-containing camptothecin drugs of this invention are preferably substantially stable to autoclaving, undergoing sterilization without suffering from hydrolytic deactivation of the xcex1-hydroxy lactone or substantial change in particle size. The particle suspensions can be autoclaved, cooled, and stored for long periods without undergoing agglomeration, flocculation, or aggregation.
In one embodiment, the injectable formulation comprises an aqueous suspension of solid particles suitable for intravenous delivery, the solid particles comprising a camptothecin, the solid particles having mean diameters between about 0.05 xcexcm and 10 xcexcm, the particles coated with a 0.3 xcexcm to 3.0 xcexcm thick layer of a membrane-forming amphipathic lipid.
In another embodiment, the injectable pharmaceutical composition comprises an aqueous suspension of solid particles suitable for intravenous delivery, the solid particles comprising a camptothecin, and a 0.3 nm to 3.0 xcexcm thick outer layer comprising a membrane-forming amphipathic lipid; wherein the solid particles have mean diameters between about 0.05 xcexcm and 10 xcexcm.
In yet another embodiment, an injectable pharmaceutical composition is provided which comprises: a dispersion of micrometer to submicrometer size solid particles in an aqueous carrier solution comprising one or more pharmaceutically acceptable tonicity modifier agents, the solid particles comprising a camptothecin, a first coating of not more than 10% w/w of a substantially water-insoluble, pharmaceutically acceptable lipophilic agent in which the camptothecin drug is insoluble or poorly soluble, and a second coating of at least one membrane-forming surface stabilizing amphipathic lipid, wherein the dispersion does not aggregate, flocculate, or agglomerate, and the particles do not grow in size above a volume weighted mean diameter of 10 xcexcm upon thermal sterilization.
In yet another embodiment, an injectable pharmaceutical composition is provided which comprises: a dispersion of micrometer to submicrometer size solid particles in an aqueous carrier solution comprising one or more pharmaceutically acceptable tonicity modifier agents, the solid particles comprising: a camptothecin, and a coating of at least one membrane-forming surface stabilizing amphipathic lipid, wherein the dispersion does not aggregate, flocculate, or agglomerate, and the particles do not grow in size above a volume weighted mean diameter of 10 xcexcm upon thermal sterilization.
In yet another embodiment, a pharmaceutical composition suitable for intravenous administration to a mammal is provided which comprises: an aqueous suspension of particles having mean diameters between about 0.05 xcexcm and 10 xcexcm, the particles comprising a camptothecin having an intact lactone ring, a membrane-forming amphiphatic lipid coating an outer surface of the particle, and one or more tonicity modifying agents, wherein the ratio of lipid to camptothecin in the particle is less than about 150:1 moles: mole, and wherein the mean diameters of the particles increase less than 100% upon thermal sterilization.
Another class of injectable formulations comprise an aqueous dispersion of microdroplets suitable for intravenous delivery, the microdroplets comprising a camptothecin. It is noted with regard to the microdroplet formulations that the camptothecin may be present where it is dissolved in a water-insoluble, pharmacologically acceptable liquid. The camptothecin may also be present in a solid form in addition to being dissolved in the water-insoluble, pharmacologically acceptable liquid. For example, the camptothecin may be present in the water-insoluble, pharmacologically acceptable liquid beyond the solubility of the camptothecin in the liquid.
In one embodiment, the injectable pharmaceutical composition comprises: an aqueous suspension of microdroplets suitable for intravenous delivery, the microdroplets having a mean diameter between 200 Angstroms and one micron, the microdroplets comprising a substantially water-insoluble, pharmacologically acceptable liquid, a camptothecin dissolved in the water-insoluble, pharmacologically acceptable liquid, and an outer layer comprising a phospholipid.
In another embodiment, the injectable pharmaceutical composition comprises: a dispersion in an aqueous carrier solution comprising one or more pharmaceutically acceptable tonicity modifier agents and liquid droplets of micrometer to submicrometer, the droplets comprising a substantially water-insoluble, pharmaceutically acceptable lipophilic liquid vehicle a camptothecin dissolved in the lipophilic liquid vehicle, and an outer layer surrounding the droplet comprising at least one membrane-forming amphipathic lipid, wherein upon thermal sterilization the dispersion does not aggregate, flocculate, agglomerate, or coalesce, and the droplets do not grow in size above a volume weighted mean diameter of 10 xcexcm.
In yet another embodiment, the injectable pharmaceutical composition comprises: an aqueous carrier solution comprising one or more pharmaceutically acceptable tonicity modifier agents; a dispersion of liquid droplets of a first size distribution, the liquid droplets comprising a substantially water-insoluble, pharmaceutically acceptable lipophilic liquid vehicle, solid particles of a camptothecin of a second size distribution, and an outer layer surrounding the droplet comprising at least one membrane-forming amphipathic lipid; wherein the first size distribution is in the range of submicrometer to micrometers, and the second size distribution is smaller than the first size distribution; and wherein upon thermal sterilization, the dispersion does not aggregate, flocculate, agglomerate, or coalesce, and the droplets do not grow in size above a volume weighted mean diameter of 10 xcexcm.
The camptothecins used in the formulations of the present invention may be an analog, a derivative or a pharmacologically active metabolite of 20(S)-camptothecin. In one embodiment, the camptothecin compound in the formulation has poor water solubility, for example having a water solubility of 10 xcexcg/ml or less.
Examples of the camptothecins include, but are not limited to, 20(S)-camptothecin, 9-nitro-20(S)-camptothecin, 9-amino-20(S)-camptothecin, 7-ethyl-10-(4-(1-piperdino)-1-piperdino)-carbonyloxy-camptothec in, 7-ethyl-10-hydroxy-20(S)-camptothecin, 10,11-methylenedioxy-20(S)-camptothecin, 9-chloro-20(S)-camptothecin, 9-bromo-20(S)-camptothecin, 9-hydroxy-20(S)-camptothecin, and 11-hydroxy-20(S)-camptothecin.
With regard to each of the formulations described herein, the camptothecin compound preferably contains a xcex1-hydroxy lactone ring and is most preferably 9-nitro-20(S)-camptothecin.
According to these various embodiments, the pharmaceutical composition preferably has a pH less than 7, preferably a pH less than 6 and in one embodiment, a pH between 5 and 6.
Also according to these various embodiments, the membrane-forming amphipathic lipid optionally comprises a phospholipid. The phospholipid may optionally be selected from the group consisting of saturated phospholipids, unsaturated phospholipids, synthetic phospholipids, natural phospholipids, and combinations thereof. The phospholipid may optionally be selected from the group consisting of natural and synthetic lipids, hen egg-derived phospholipid, egg phospholipid, purified egg phospholipid, soy phospholipid, dimyristoyl lecithin, didodecanoyl lecithin, dioeoyl lecithin, dilinoeoyl lecithin, alpha-palmito-beta-oleoyl lecithin, alpha-palmitoyl-beta-linoleoyl lecithin, alpha-oleoyl-beta-palmitoyl lecithin, diarachidonyl lecithin, alpha-palmito-beta-myristoyl lecithin, dimyristoyl phosphatidic acid, dipalmitoyl phosphatidic acid, distearoyl phosphatidic acid, phosphatidyl serine, phosphatidyl inositol, dimyristoyl phosphatidyl glycerol, dipalmitoyl phosphatidyl glycerol, dioctadecanoyl phosphatidyl ethanolamine, dioleoyl phosphatidyl ethanolamine, dihexadecyl phosphatidyl ethanolamine, dilauryl phosphatidyl ethanolamine, dimyristoyl phosphatidyl ethanolamine, dipalmitoyl phosphatidyl ethanolamine, Lipoid E80, Lipoid ES, Lipoid 90H, and Lipoid 100H. In one particular variation, the phospholipid comprises Lipoid E80.
Also according to these various embodiments, the outer layer may further comprises cholesterol.
Also according to these various embodiments, the camptothecin may be present in amounts of up to about 25% w/w, more preferably up to about 5% w/w. The camptothecin may be present in amounts of from about 0.05% w/w to about 5% w/w, and optionally from about 0.1% w/w to about 1% w/w. In one particular variation, the camptothecin is present in amount of about 0.2% w/w.
Also according to these various embodiments, the membrane-forming amphipathic lipid may be present in amounts of from 0.2% w/w to about 5% w/w, more preferably in amounts of from 1% w/w to about 5% w/w. In one particular variation, the membrane-forming amphipathic lipid is present in amounts of about 4% w/w.
According to each of the above embodiments, the mean diameters of the particles and droplets preferably increase less than 100% upon storage at room temperature (23xc2x0 C.) for at least 1 month, more preferably at least 3 months, more at least 6 months, and most preferably at least 1 year.
Also according to each of the above embodiments, the lipophilic liquid vehicle is optionally present in amounts up to about 40% w/w, more preferably in amounts up to about 25% w/w, and most preferably in amounts up to about 20% w/w. The lipophilic liquid vehicle is also preferably present in amounts greater than 0.5% w/w.
The various compositions and kits of the present invention may be used in methods to treat patients suffering from abnormal cell proliferation such as cancer including hematological malignancy and tumors. In one embodiment, the method comprises: providing a pharmaceutical composition according to the present invention; and administering a therapeutically effective amount of the pharmaceutical composition intravenously to a patient in need thereof. According to the method, the camptothecin compound preferably contains a xcex1-hydroxy lactone ring and is preferably 9-nitro-20(S)-camptothecin.

Method for administering camptothecins via injection of a pharmaceutical composition comprising microdroplets containing a camptothecin


A tool is provided for removal and installation of computer disk drive connectors of various sizes. The tool is a useful, easy to use, inexpensive device. The same device is a useful tool for removing hex head screws commonly used in computers. The apparatus is also lightweight and compact thereby making it easy to transport and store within the computer, and to use with one hand.

Computers are widely used in almost every industry, and also widely used by consumers. Technology for computer systems is rapidly changing as new products emerge on a daily basis. The new products are becoming easy to install. As a result, many computer users are installing the new products themselves.
Additionally, the new computer products typically require large amounts of storage, or even new types of disk drives. Consequently, a computer user or service person is required to remove and install disk drive equipment and other equipment to and from the computer. Computers sometimes become damaged or in need of repair. A technician must disassemble and reassemble the computer to fix it. Lastly, during the manufacturing process of computers, various components of the computer must be assembled repeatedly. During the installation, modification, manufacture, and repair of computers, computer users and service persons often must remove various parts of the computer, including disk drive power connectors and hex head screws.
Disk drive connectors are comprised of two parts, male and female, which when engaged, provide an electrical connection from the computer system to individual disk drives. The connectors have several internal components which frictionally engage to provide the electrical and structural connection. The outcome is a large surface area which is frictionally engaged when the connectors are joined. As a result, a relatively large force is required to connect and disconnect the connectors, which is often done by humans. The connectors are compact, as space in a computer is at a premium. The connectors have a small rib which is used to apply force when removing or installing the connector. The considerable amount of force required, in combination with the small surface area of the rib to which the force is applied, results in substantial difficulty and inefficiency for the removal and installation of the connectors.
Frustrated with the magnitude of force required to remove the connectors by hand, individuals may resort to using sharp instruments or other potentially damaging devices to install or remove computer connectors, thereby increasing the risk of damage to equipment and electrical connections within the computer. Furthermore, individuals may also use excessive force when removing the connectors, or place excessive force in a localized area of the connector, which results in severed electrical connections.
Accordingly, there is a need for a better way to provide enough force to effectively handle computer connectors. What is also needed is a way to deal with a variety of connectors and screws within the computer.

Tool for installing and removing computer connectors


A new and distinct cultivar of New Guinea Impatiens plant named ‘Balcebredep’, characterized by its single type dark red-colored flowers, variegated medium green and yellow green-colored foliage, and moderately vigorous, compact, and mounded growth habit.

The present invention relates to a new and distinct cultivar of New Guinea Impatiens plant botanically known as Impatiens hawkeri and hereinafter referred to by the cultivar name 'Balcebredep'.
The new cultivar originated in a controlled breeding program in Arroyo Grande, Calif. during November 2003. The objective of the breeding program was the development of New Guinea Impatiens cultivars with numerous large flowers, excellent basal branching, and a compact, mounded growth habit.
The new New Guinea Impatiens cultivar is the result of cross-pollination. The female (seed) parent of the new cultivar is the proprietary Impatiens hawkeri breeding selection designated 7824-3, not patented, characterized by its single type medium red-colored flowers, dark green-colored foliage, and upright growth habit. The male (pollen) parent of the new cultivar is the proprietary Impatiens hawkeri breeding selection designated 7830-2, not patented, characterized by its single type dark red-colored flowers, dark green-colored foliage, and upright growth habit. The new cultivar was discovered and selected as a single flowering plant within the progeny of the above stated cross-pollination during April 2004 in a controlled environment at Arroyo Grande, Calif.
Asexual reproduction of the new cultivar by terminal stem cuttings since April 2004 at Arroyo Grande, Calif. and West Chicago, Ill. has demonstrated that the new cultivar reproduces true to type with all of the characteristics, as herein described, firmly fixed and retained through successive generations of such asexual propagation.


A display panel for a liquid crystal display comprising a timing controller and a plurality of source drivers is provided. The timing controller receives a differential signal (LVDS/TMDS/DVI) to generate a plurality of TTL signals and a sync signal. Each of the source drivers comprises at least one bus directly connected to the timing controller to receive corresponding TTL signal. The timing controller comprises a clock line, coupled to the source drivers for transmission of the sync signal. Each TTL signal comprises a corresponding image information. The TTL signals, sequentially transmitted by the bus, conform to the transistor-to-transistor logic (TTL) standard.

1. Field of the Invention
The invention relates to a liquid crystal display, and in particular, to a liquid crystal display circuit design.
2. Description of the Related Art
FIG. 1 shows a conventional display panel. The display panel comprises a timing controller (TCON) 102 for receiving differential signals like LVDS/TMDS/DVI, and two buses each coupled to a plurality of source drivers 104. For example, all of the odd source drivers 104 may couple to the one bus, while all the even source drivers 104 may couple to the other bus. Given a 6-bits gray level, a total of 18 transmission lines is required to deliver red, blue and green information from the TCON 102 to each source driver 104. Thus two buses utilize 36 transmission lines in total. If the gray level is 8 bits, 48 transmission lines are required. After the TCON 102 receives the LVDS/TMDS/DVI signals, the corresponding image information is transmitted to the source drivers 104 via the transmission lines. Signals on the transmission lines electrically conform to the TTL logic standard, and have a voltage of 3.3 V or 5V. The display panel also comprises a reference voltage generator 106, providing voltages based on gamma correction parameters.
FIG. 2 shows a conventional advanced display panel. The TCON 202 comprises a bus, both ends of which are equipped with terminators 208. All source drivers 204 simultaneously couple to the bus, thus the number of required transmission lines is reduced by half that of FIG. 1. Given a 6-bits gray level, the TCON 202 only requires 18 transmission lines to couple all source drivers 204. After the TCON 202 receives the LVDS/TMDS/DVI signals, image information is delivered to the source drivers 204 via the transmission lines, and signals on the transmission lines electrically conform to the reduced swing differential signal standard (RSDS). Similarly, the display panel also comprises a reference voltage generator 206, providing voltages based on gamma correction parameters.
FIG. 3 shows a conventional point-to-point display panel. The TCON 302 connects to each source driver 304 with individual transmission lines, and signals on the transmission lines conform to the point-to-point differential signal (PPDS) standard. The transmission lines are exclusive for each individual source driver 304, therefore the bus clock need not be shared, and the transmission rate can be significantly increased. Moreover, only a few transmission lines are required to deliver red, green, blue, and additional data. Similarly, the display panel also comprises a reference voltage generator 306, providing voltages based on gamma correction parameters.
Although PPDS reduces the number of transmission lines and the cost of PCBs, additional DC biased current is still required, thus, the power provided is inadequate for portable products. Additionally, with the progress of current technology, logic voltage requirement have been reduced from 5V to 1.8V/1.5V, making the implementation of differential signal will be more difficult.

Display panel for liquid crystal display


An outdoor card playing surface is provided including a table cover having at least one bore formed therein. A plurality of thin rectangular playing cards each have a top face with a common design thereon and a bottom face with playing indicia formed thereon. Each of the playing cards further has a hole formed therein. At least one peg is mounted within the bore of the cover for releasably receiving the hole of any one of the playing cards.

1. Field of the Invention
The present invention relates to playing card tables and more particularly pertains to a new outdoor card table for preventing wind and other adverse weather conditions from removing playing cards from a recipient surface.
2. Description of the Prior Art
The use of playing card tables is known in the prior art. More specifically, playing card tables heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art playing card tables include U.S. Pat. No. 4,844,457; U.S. Patent Des. 281,178; U.S. Pat. No. 4,055,124; U.S. Patent Des. 355,316; U.S. Pat. No. 3,964,403; and U.S. Patent Des. 292,353.
In these respects, the outdoor card table according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of preventing wind and other adverse conditions from removing playing cards from a recipient surface.


A customized light module comprising is provided according to one embodiment of this disclosure. The customized light module, according to this embodiment, includes a housing, a light source, a removable decorative cap and a battery. The housing includes a stem configured to secure the customized light module within an aperture of an article of footwear. The light source is coupled with the housing. The decorative cap may be removably coupled with the housing and may be configured to illuminate when the light source is illuminates. The battery may be accessibly secured within the housing with a two-stage mechanism. The two-stage mechanism, for example, may include a child lock. In some embodiments, the housing has at least two configurations: a first configuration and a second configuration. A circuit is created between the battery and the light source in the first configuration and closed in the second configuration.

For a number of years articles of footwear and various items of clothing have been sold with decorative attachments. These attachments have either been lighted and non removable or removable and non lighted, neither of which have had the ability to be both lighted and removable or to be further customized by the wearer and activate or deactivated at will.


A network device includes at least one first network port, at least one second network port, a MUX unit and a switching unit. The MUX unit is connected to the at least one first network port. The MUX unit includes a trunk circuit and an output. The trunk circuit is configured to aggregate data packets received at the at least one first port into a trunk group and to output trunked data packets to the output. The switching unit is connected to the output of the MUX unit and to the at least one second network port. The switching unit is configured to switch the trunked data packets to the at least one second network port.

1. Field of the Invention
This invention relates to systems and methods for switching data within a data communications network. In particular, the present invention is related to systems and methods of isolating a group of network clients connected to a network device, such as a switch, router, repeater, etc.
2. Description of the Related Art
Over the last several years, the proliferation of the Internet has had a significant impact on many industries, especially the computer industry. The Internet has grown into an enormous worldwide system of computer networks to which virtually any large or small computer network, or individual computer, may be connected. Internet access is typically obtained via an Internet Service Provider (ISP). ISPs provide access to the Internet for their customers usually through membership subscriptions in conjunction with service level agreements (SLAs). ISPs make at least a portion of their income on service fees such as subscription fees, on demand provisioning of services, etc. One technique employed by ISPs is to regulate the amount of Internet bandwidth (i.e., data speed) that a customer is entitled based upon how much they pay. By regulating the amount of bandwidth available to each customer, ISPs may provide different levels or qualities of service at different rates.
Recently, a new class of service providers is targeting the needs of businesses and individuals in a multi-tenant unit (MTU), which is a generic term for a residential neighborhood, a building or group of buildings that accommodate more than one tenant. Examples of MTUs include high-rise office buildings, commercial business parks, hotels, college and university campus dormitories, and apartment buildings.
In addition to access to the Internet, ISPs, cable operators, and competitive local exchange carriers (CLECs) can leverage Internet access to offer a variety of value-added services to both business and residential subscribers, each available at an incremental additional fee or as part of a bundled services package. These same service providers also need the ability to change their services to meet shifting customer demands. A flexible, intelligent network infrastructure is needed that requires few changes to provision new services. Such networks in order to be successful must be easy to manage, monitor, and maintain, and also must be able to change with technology.
CLECs are now using fiber in metropolitan area networks (MANs) to deliver Ethernet connections to buildings having Category 5 wiring. For example, referring to FIG. 1, a group of subscribers may access the Internet via a Digital Subscriber Line Access Multiplexer (DSLAM) device, downstream from the Internet 100. A DSLAM is a network device, usually at a telephone company central office (CO), that receives signals from multiple customer Digital Subscriber Line (DSL) connections and puts the signals on a high-speed backbone line using multiplexing techniques. Depending on the product, DSLAM devices connect DSL lines with some combination of asynchronous transfer mode (ATM), frame relay, or Internet Protocol networks. DSLAM enables a phone company to offer business or homes users the fastest phone line technology (DSL) with the fastest backbone network technology (ATM).
DSLAM switches using ATM are circuit switches similar to telephone switches. Each subscriber 104 to 108 may be connected to the DSLAM 102 via ATM or DSL lines. Point-to-point protocol (PPP) is used to communicate subscribers 104 to 108 with the DSLAM 102. However, if the DSLAM 102 is changed to Ethernet and configured to use internet protocol (IP), then without any additional system or method to isolate the subscribers from one another, each subscriber will have direct access to each other via PPP. In order to provide security and isolation, typically a virtual LAN (VLAN) is established for an individual subscriber or a group of subscribers. A VLAN may be useful to isolate and restrict traffic between different departments in a company, such as a payroll, sales, engineering, and marketing, or to isolate and restrict traffic to different segments or nodes of a network. There are numerous types of VLANS, such as port configuration VLANs, MAC-based VLANs, LAYER 3 VLANs, IP Multicast VLANs, and Rule-based VLANs.
One disadvantage of a port-configuration VLAN is that a separate VLAN must be used for each port on the DSLAM 102 in order to provide security and isolation to each subscriber connected thereto. For example, referring to FIG. 2, shown is a block diagram of an Ethernet switch 102 connecting subscribers 104 to 108 to the Internet. As shown by a dotted line, in order to isolate each subscriber, a VLAN is added to the configuration of switch 102. Since VLANs are their own subnet, each VLAN takes up one IP address. Therefore, under this configuration, an undesirable high number of IP addresses are used. Also, each VLAN requires its own configuration and control, and switch 102 must be configured for each VLAN set up (i.e., for each subscriber connected thereto). As subscribers are added or subtracted, resources are spent configuring and reconfiguring network devices. Therefore, under this configuration, more time and money are spent on configuration and implementation of the Ethernet connections.
Accordingly, there is a need for new and improved systems and methods for providing Ethernet connections and while providing security and isolation users.

System and method for isolating network clients


A multi-master hybrid bus apparatus is provided. The multi-master hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple multiple master circuits with one or more slave circuits via heterogeneous communication buses. In examples discussed herein, the multiple master circuits can correspond to multiple physically separated master circuits or multiple bus ports provided in a single master circuit. In a non-limiting example, the hybrid bus bridge circuit is coupled to the multiple master circuits via multiple radio frequency front-end (RFFE) buses and to the slave circuits via at least one single-wire bus (SuBUS) consisting of a single wire. By bridging the multiple master circuits to the slave circuits based on a single hybrid bus bridge circuit, it may be possible to enable flexible heterogeneous bus deployment in an electronic device (e.g., a smartphone) with reduced cost and/or footprint.

Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.
The redefined user experience requires higher data rates offered by wireless communication technologies, such as Wi-Fi, long-term evolution (LTE), and fifth-generation new-radio (5G-NR). To achieve the higher data rates in mobile communication devices, a radio frequency (RF) signal(s) may first be modulated by a transceiver circuit(s) based on a selected modulation and coding scheme (MCS) and then amplified by a power amplifier(s) prior to being radiated from an antenna(s). In many wireless communication devices, the power amplifier(s) and the antenna(s) are typically located in an RF front-end (RFFE) circuit communicatively coupled to the transceiver circuit(s) via an RFFE bus as defined in the MIPI® alliance specification for radio frequency front-end control interface, version 2.1 (hereinafter referred to as "RFFE specification").
In this regard, FIG. 1 is a schematic diagram of an exemplary RFFE bus apparatus 10 as defined in the RFFE specification. The RFFE bus apparatus 10 includes an RFFE master 12 coupled to a number of RFFE slaves 14(1)-14(M) over an RFFE bus 16. According to the RFFE specification, the RFFE bus 16 is a two-wire serial bus that includes a data line 18 and a clock line 20 for communicating a bidirectional data signal SDATA and a clock signal SCLK, respectively. The RFFE bus 16 operates at a first data rate.
Further according to the RFFE specification, each of the RFFE slaves 14(1)-14(M) is required to have a unique slave identification (USID) and the RFFE bus apparatus 10 can support fifteen (15) USIDs between hexadecimal value 0x1 and hexadecimal value 0xF (0x1-0xF). The RFFE specification further assigns hexadecimal value 0x0 to represent a broadcast slave identification (BSID) for all the RFFE slaves 14(1)-14(M). According to the RFFE specification, each of the RFFE slaves 14(1)-14(M) is assigned one of the 15 USIDs by a system integrator. Accordingly, in the RFFE bus apparatus 10, it is possible to connect up to 15 RFFE slaves 14(1)-14(15) to the RFFE master 12 via the RFFE bus 16.
The RFFE specification also allows any of the 15 USIDs to be used as a group slave identification (GSID) to identify an RFFE slave group. For example, the RFFE bus apparatus 10 includes five RFFE slaves associated with USIDs 0x1-0x5, respectively. The RFFE slaves associated with USIDs 0x1-0x3 may be clustered into a first RFFE slave group and the RFFE slaves associated with USIDs 0x4-0x5 may be clustered into a second RFFE slave group. The first RFFE slave group and the second RFFE slave group may be assigned USIDs 0x6 and 0x7, respectively. In this regard, the USIDs 0x6 and 0x7 are now used as GSIDs to identify the first RFFE slave group and the second RFFE slave group, respectively. Notably, there will be a lesser number of USIDs available to identify the RFFE slaves 14(1)-14(M) if any of the 15 USIDs are used to represent a GSID.
The RFFE master 12 is configured to communicate with the RFFE slaves 14(1)-14(M) based on RFFE command sequences (e.g., register-write command sequence, register-read command sequence, trigger command sequence, etc.). According to the RFFE specification, only the RFFE master 12 can initiate an RFFE command sequence on the RFFE bus 16.
Each of the RFFE command sequences can be associated with a USID, a GSID, or a BSID. When an RFFE command sequence is communicated based on a specific USID, the RFFE command sequence is addressed to a specific RFFE slave among the RFFE slaves 14(1)-14(M) that is identified by the specific USID. When an RFFE command sequence is communicated based on a specific GSID, the RFFE command sequence is addressed to respective RFFE slaves among the RFFE slaves 14(1)-14(M) associated with the specific GSID. For example, if the command sequence is communicated with GSID 0x6, then the command sequence will be addressed to the RFFE slaves associated with the GSID of 0x6. When an RFFE command sequence is communicated based on the BSID, all of the RFFE slaves 14(1)-14(M) on the RFFE bus 16 will be able to receive the RFFE command sequence.
However, not all communications require a two-wire serial bus like the RFFE bus 16. In some cases, a single-wire serial bus may be sufficient or even desired for carrying out certain types of communications between circuits. In this regard, FIG. 2 is a schematic diagram of an exemplary conventional hybrid bus apparatus 22 in which a single-wire bus (SuBUS) bridge circuit 24 is configured to bridge communications between the RFFE master 12 in FIG. 1 with one or more SuBUS slaves 26(1)-26(N). Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.
The SuBUS bridge circuit 24 is coupled to the SuBUS slaves 26(1)-26(N) over a SuBUS 28 having a single data wire 30. Accordingly, the SuBUS 28 is configured to operate at a second data rate that can be faster or slower than the first data rate of the RFFE bus 16. The SuBUS bridge circuit 24 may be coupled to the RFFE master 12 via the RFFE bus 16. In this regard, the SuBUS bridge circuit 24 and the SuBUS slaves 26(1)-26(N) are also RFFE slaves, such as the RFFE slaves 14(1)-14(M) coupled to the RFFE master 12 in the RFFE bus apparatus 10 of FIG. 1. In this regard, the SuBUS bridge circuit 24 and the SuBUS slaves 26(1)-26(N) are configured to be identified by the RFFE master 12 based on the 15 USIDs ranging from hexadecimal value 0x1 to hexadecimal value 0xF (0x1-0xF).
Notably, the SuBUS 28 differs from the RFFE bus 16 in several aspects. First, the RFFE bus 16 includes the data line 18 and the clock line 20, while the SuBUS 28 includes only the single data wire 30. Second, the SuBUS bridge circuit 24 is configured to communicate with the SuBUS slaves 26(1)-26(N) based on SuBUS command sequences, which may be compatible but different from the RFFE command sequences communicated over the RFFE bus 16. In this regard, the SuBUS bridge circuit 24 may perform command conversion between the RFFE command sequences and the SuBUS command sequences to facilitate communications between the RFFE bus 16 and the SuBUS 28. Third, the RFFE bus 16 may be configured to operate at the first data rate and the SuBUS 28 may be configured to operate at the second data rate, which is different from the first data rate. In this regard, the SuBUS bridge circuit 24 may buffer SuBUS data payloads prior to communicating over the RFFE bus 16 to help compensate for a difference between the first data rate and the second data rate.
Similar to the RFFE slaves 14(1)-14(M) in FIG. 1, the SuBUS bridge circuit 24 and the SuBUS slaves 26(1)-26(N) need to be respectively identified by a USID. As discussed in FIG. 1, the RFFE bus apparatus 10 can support 15 USIDs between hexadecimal value 0x1 and hexadecimal value 0xF (0x1-0xF). In this regard, the SuBUS bridge circuit 24 can be identified by a specially assigned USID among the 15 available USIDs and the SuBUS slaves 26(1)-26(N) can be identified by the remaining 14 USIDs excluding the specially assigned USID. For example, if the SuBUS bridge circuit 24 is identified by the specially assigned USID of 0x1, then the SuBUS slaves 26(1)-26(N) can only be identified by USIDs ranging from 0x2 to 0xF. Like the RFFE slaves 14(1)-14(M), the SuBUS slaves 26(1)-26(N) may also be accessed via a BSID and a GSID as previously described in FIG. 1.
The conventional hybrid bus apparatus 22 may be employed in combination with the RFFE bus apparatus 10 to enable flexible heterogeneous bus deployment in an electronic device (e.g., a smartphone). However, the SuBUS bridge circuit 24 as presently defined is only capable of bridging the SuBUS slaves 26(1)-26(N) with only a single RFFE master 12. As such, it may be necessary to employ additional SuBUS bridge circuits to bridge the SuBUS slaves 26(1)-26(N) to additional RFFE masters, thus increasing cost and/or footprint of the conventional hybrid bus apparatus 22. Hence, it may be desirable to bridge the SuBUS slaves 26(1)-26(N) to multiple RFFE masters based exclusively on the SuBUS bridge circuit 24.


A multi-medium store-and-forward exchange apparatus is connected to a plurality of line networks to convert a data received from a data originator terminal into another sort of data corresponding in attribute to another sort of line network and to transmit the converted data to a destination terminal. When the destination terminal does not handle the data to be transmitted from the data originator terminal, the store-and-forward exchange apparatus converts the data into another sort of data which can be handled at the destination terminal, and then transmits the converted data from its network controller in the apparatus. Further, an identification data of a terminal is registered to which a data arrival is announced at the time of the data reception in the form of a medium (voice, character or picture data) message previously prepared in the store-and-forward exchange apparatus. Identification data are allocated to individual system users, each user determines a terminal to be used depending on the attribute of the data to be transmitted, and the data to be transmitted is transmitted to the terminal.

1. Field of the Invention
The present invention relates to a multi-medium store-and-forward exchange apparatus for performing transfer, storage and conversion of various sorts of data and a method of controlling the apparatus, and more particularly, to a multi-medium store-and-forward exchange apparatus which is connected to a plurality of line networks so that the apparatus converts data received from communication terminals of one line network into data suitable for different line networks and sends the converted data to associated party terminals of the different line networks and a method of controlling the apparatus.
2. Description of the Related Art
A prior art store-and-forward exchange apparatus of the type referred to above has been connected to a single line exchange network so that the apparatus receives data from a terminal through the line exchange network and sends it to a party terminal through the same network.
There recently has been suggested a store-and-forward exchange apparatus connected to a plurality of line exchange networks of different types, including a voice line exchange network for transmitting voice signals, a picture line exchange network for transmitting picture data and a character line exchange network for transmitting character data.
The conventional store-and-forward exchange apparatus is basically designed so that the apparatus sends a voice signal received from a voice terminal (which generates the voice signal), to a party terminal through one of the lines connected to the voice line exchange network, sends a picture signal received from a picture terminal (which generates the picture signal), to a party terminal through one of the lines connected to the picture line exchange network, and sends a character signal received from a character terminal (which generates the character signal), to a party terminal through one of the lines connected to the character line exchange network. For this reason, when all the lines connected, e.g., to the picture line exchange network are in use but there is idle one of the lines connected, e.g., to the character line exchange network, the prior art store-and-forward exchange apparatus cannot transmit the data received through the picture line exchange network to the party terminal but must wait until one of the lines connected to the picture line exchange network becomes idle.
In order to remove the above disadvantage, it may be considered to determine the number of lines depending on the expected amount of the communication for each sort of media. Even in this case, however, when the amount of communication to line exchange network is unexpectedly increased, the transmission to terminals connected to that line exchange network is delayed and thus equal servicing to every terminal cannot be realized. For the purpose of overcoming this disadvantage, it may be considered to increase the number of lines connected to each of line exchange networks. This, however, involves another problem that the cost becomes high.

Multi-medium store-and-forward exchange apparatus and method of controlling the apparatus


A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells. A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) uses both a differential amplifier (360) included within a D-flip-flop circuit (114) and a reference voltage provided by a reference voltage circuit (365) to compare addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

Dual port memories are useful for a wide variety of applications. They have special usefulness in the areas of communications and multiprocessor systems. In multiprocessor systems, one processor may write data into the array and the other processor may read data out. In particular, dual port RAMs (Random Access Memories) are especially well suited for a communications application known as Asynchronous Transfer Mode (ATM). In an ATM switch, large amounts of data must be transferred between two processing devices. Another communications application is a standard IEEE 802.3 (commonly known under the trademark "Ethernet" available from Digital Equipment Corporation) communications router. These types of applications have a need for a dual port memory which is inexpensive but includes a large array.
Conventionally, dual port random access memories (RAMs) were constructed using one of two techniques. In the first technique, each memory cell was truly dual port and thus required eight transistors. Because the large dual port memory cells make the array itself quite large, integrated circuit memories based on this technique are expensive. A second technique utilizes standard single port static RAM cells with a partitioned array. If both ports simultaneously attempt to access the same partition, then one of the accesses must be delayed. As the number of partitions increases, the likelihood that a collision will occur decreases, but the cost increases due to the extra decoding and collision detection circuitry. Thus, what is needed is a large dual port RAM which uses conventional single port SRAM cells but which is also inexpensive and fast. These needs are met by the present invention whose features and advantages will be further described with reference to the drawings and the accompanying description.

Comparison circuit utilizing a differential amplifier


A mailbox mounting bracket for a mailbox. The mailbox mounting bracket comprises a lower first member and an upper second member. The lower first member has a T-shaped transverse cross sectional profile and the upper second member defines a mating T-shaped recess. The T-shaped recess of the upper second member captively receives and encloses the T-shaped transverse cross sectional profile of the lower first member such that three sides of the lower first member are completely surrounded by the upper second member while a fourth side of the lower first member is only partially surrounded by lower legs of the upper second member and is at least partially exposed so as to facilitate attachment of the lower first member to a surface of a mailbox post. The upper second member is slidably moveable relative to the lower first member.

Many mailboxes are located in places along the road that are difficult to access. This frequently makes delivering the mail and retrieving mail challenging. A number of mailboxes are positioned far from the road, which makes it harder for a postal worker to deliver the mail. Often times, people try to retrieve their mail from an automobile and frequently need to get out of their vehicle or lean out the window in order to access fully their mailbox. People in wheelchairs also have challenges in retrieving their mail due to obstacles, such as curbs, located in front of the mailbox. In addition, during the winter, many people do not properly clear or remove heavy snow adjacent their mailboxes and this hinders mail delivery services as well as retrieval of the mail by the customer. Lastly, many people have inferior/failing mailbox mounting brackets, for mounting their mailboxes to mailbox posts, that cannot reliably withstand the elements associated with winter.


Corner studs (10, 10′) have webs that are folded into two parts (16, 18) separated by an angle of between about 150° and 270°. These studs are used at corners formed where two framing walls meet. The first wall has upper and lower channel members with continuous flanges. The second wall has upper and lower channel members with squared ends that abut continuous flanges of upper and lower channels of the first framing wall. Studs (10, 10′) are provided which webs that include flange-receiving slots (12, 28) that extend from the ends of the studs (10, 10′) longitudinally inwardly along a bend line (14) between the two web parts (16, 18). The flanges (36, 52) are received within these slots (12, 28) so that a first portion of the studs (10, 10′) can be installed into the channel space of the first channel member and the remaining portion of the studs (10, 10′) can be installed into the channel space of the channel members of the second wall.

Building walls intersect each other at corners and at locations between the corners. U.S. Pat. No. 4,689,930 granted Sep. 1, 1987 to Robert J. Menchetti, discloses is a corner stud to which two standards studs are connected. U.S. Pat. No. 3,363,377, granted Jan. 16, 1968, to Melvin H. Beckman, and U.S. Pat. No. 4,283,892, granted Aug. 18, 1981 to Larry B. Brown, each disclose studs constructed to be usable at an intersection of a first wall with a second wall between corners. There is a need for intersection studs for use at intersections between corners and a utilization of such studs that facilitates construction of the walls while reducing both material and labor. It is the primary object of the present invention to fill this need.
Framing walls are formed from upper and lower horizontal channel members, sometimes referred to as "tracks", and vertical studs extending between the channel members. The opposite ends of the studs fit within channel spaces provided by the channel members and the studs are connected to the side flanges of the channel members by mean of screws. For economical reasons, it is desirable to install the channel members for a wall without having to cut out portions of the flanges at the intersection of the wall by a perpendicular wall. It is desirable to be able to abut the square cut end of the channel of the perpendicular wall against the flange of the first wall. The problem with this arrangement is that the flange of the channel member of the first wall that span across the end of the channel member of the second wall, prevents the placement of the ends of the corner studs in both of the channel spaces where they meet at the intersection. It is an object of the present invention to provide a stud that is constructed to allow a first portion of its end to be positioned in the channel space of one side of the flange and the remaining portion of the end of the stud to be positioned in the channel space on the opposite side of the flange.


A sheet including an olefin thermoplastic elastomer obtainable by dynamically heat-treating 100 parts by weight of a mixture of 40-90% by weight of (A) an olefin polymer rubber having a Mooney viscosity at 100.degree. C. (ML.sub.1+4 100.degree. C.) of 5-100 and substantially free from unconjugated diene and 60-10% by weight of (B) an olefin polymer in the presence of 0.005-0.5 part by weight of an organic peroxide and 0.05-4 parts by weight of N,N'-m-phenylenebismaleimide or divinylbenzene. Said sheet is excellent in light resistance and thermal aging resistance. A laminate including said sheet and a use thereof are also provided.

1. Field of the Invention
The present invention relates to a sheet comprising an olefin thermoplastic elastomer having excellent light resistance and thermal aging resistance, a laminate comprising said sheet and a use thereof. More precisely, the invention relates to a sheet comprising an olefin thermoplastic elastomer having excellent duration properties, particularly light resistance or the like, which is excellent in external appearance and touch or the like and which may be substituted for plasticized polyvinyl chloride material; a laminate constituting said sheet; and an internal finish material for automobile constituting said sheet or laminate.
2. Background Information
Thermoplastic elastomers have found wide application in industrial products including automobile parts, electric appliance parts and sundry goods since the time consuming vulcanization step is not required in the productions of them and they can be processed using a conventional molding machine for a thermoplastic resin.
On the other hand, moldings of improved quality have hitherto been known which were produced by laminating a skin material onto a molded thermoplastic resin to impart improved external appearance and soft touch. As the skin material, for example, a plasticized polyvinyl chloride material lined with a foamed layer of polyolefin or polyurethane in order to impart cushioning properties has been used.
The polyvinyl chloride skin material, however, has the problem that it has a large specific gravity and an inferior light resistance. Therefore its surface appearance is significantly deteriorated when used as a skin material for an automobile part which is exposed to direct sun light. In addition, since it is plasticized by containing a large amount of plasticizer, it has a problem in that the windshield and the like become fogged up due to the plasticizer when used as an internal finish skin material for automobile.
Furthermore, since polyvinyl chloride generates hydrogen chloride gas upon combustion due to its chemical structure, it has the added problems in that its incineration after use should not be permitted from an environmental viewpoint, and that it tends to erode various processing apparatuses.
In order to solve the above described problems, it was proposed to produce a skin material by using an olefin thermoplastic elastomer comprising ethylene-.alpha.-olefin-unconjugated diene copolymer rubber as the rubber component (JP-A-4-73112).
However when ethylidenenorbornene was used as the unconjugated diene, the properties of the product deteriorated within a short period upon exposure to light.
When dicyclopentadiene is used as the unconjugated diene, deterioration of the properties within a short period is less significant (JP-A-5-279524), but there is still the problem that the thermal aging resistance of the product was not sufficient. Therefore, when a thermoplastic elastomer sheet containing one of these unconjugated dienes is applied for a use in which light resistance is particularly required, such as a skin material for the instrument panel of automobile, a large amount of light stabilizer must be used in order to prevent light aging. As the result, problems arose because the sheet became dirty due to the light stabilizer deposited on the surface of the sheet or the windshield was fogged up by sublimed light stabilizer.
The object of the present invention, therefore, is to solve these problems of the conventional art and to provide a sheet comprising an olefin thermoplastic elastomer having excellent light resistant and heat resistant properties, a laminate comprising said sheet and an internal finish material for an automobile comprising said sheet or laminate.
After extensive research toward solving these problems, the present inventors have found that the light deterioration and the heat deterioration are less significant when an olefin thermoplastic elastomer is produced using an olefin polymer rubber free from unconjugated diene and using particular amounts of a specific cross-linking agent and a specific cross-linking aid. The present invention has been completed on the basis of such findings and further improvement.