A glass break detector is disclosed that uses a neural network to determine if an audio signal is breaking glass. A characteristic extraction unit is used to extract a set of signal characteristics from a time domain signal based on the audio signal. The set of signal characteristics is the set of the magnitudes of the discrete Fourier transform coefficients of an acquired time domain signal, or the Fourier transform coefficients themselves. A classifier is connected to the characteristic extraction unit. It is a two-layer neural network that uses the set of signal characteristics to accurately determine whether the acquired time domain signal represents breaking glass.

The present invention relates generally to glass break detectors, and more particularly to glass break detectors that use neural networks to determine if an atmospheric wave was created by glass breaking.
In an era of high crime, property owners are concerned about the security of both their property, and persons on the premises. Thus, security systems for both the home and business have experienced an increase in demand. Glass break detectors are a necessity for any security system that is used to safeguard structures having glass windows and doors.
One approach that has considered involves the use of a window mounted piezoelectric glass detector. This device detects vibrations that occur when glass breaks. These devices have been fairly reliable in detecting glass breaks and do not respond to false conditions such as knocking on the glass. However, piezoelectric glass break detectors have a significant drawback. Multipane windows, or rooms with multiple windows, require separate detectors and wiring for each pane of glass. Thus, these devices can be both costly and unsightly under these circumstances.
In another approach that has been considered, analog audio discriminators have been developed to solve the problems associated with the window mounted units. These units include a microphone for converting the sound to an electrical signal. An analog processor detects glass breakage by measuring the slope of the electrical signal. However, these analog devices also have a significant drawback. They are prone to false alarms because they are unable to discriminate between glass break sounds and similar sounds.
In yet another approach that has been considered, a digital audio discriminator has been developed to reduce the number of false alarms and increase the accuracy of the detector. A Harris 800 supercomputer was used to analyze Power Spectral Density (PSD) of glass break signals and in doing so, identify the dominant features of breaking glass. A neural network was developed and trained to recognize the dominant features identified by the super computer. The resultant digital glass break detector was very sophisticated. It included a microphone that converted sound energy into an electrical signal, analog to digital conversion, and a digital signal processor (DSP) to process the resultant digital signal. The DSP calculated the PSD of the digital signal and extracted the dominant features of the PSD. The dominant features were used by a neural network embedded in the DSP to evaluate the digital signal. There is a significant drawback to this approach as well. The processing power of a DSP is needed to extract the dominant features from the signal and use them to perform neural network processing. Unfortunately, DSPs are expensive and the resultant device may not be affordable for many home owners.
Thus, a need exists for a glass break detector that incorporates the sophistication and accuracy of a neural network without the costs associated with complex digital signal processing.
Existing problems with current state of the art glass break detectors are addressed by the present invention. An inexpensive processor calculates a set of signal characteristics such as the discrete fourier transform coefficients of an acquired time domain signal using a Discrete Fourier Transform or a Fast Fourier Transform. The magnitudes of each coefficient may also be used. A two-layer neural network uses the set of signal characteristics to accurately detect breaking glass. This design eliminates the unnecessary and overly complex processing used in calculating the PSD and evaluating the dominant features of the PSD. Thus, the efficient design of the present invention has no need for an expensive DSP. The present invention is implemented using a floating point processor that costs a few dollars. The present invention features an extremely accurate and low-cost glass break detector.
One aspect of the present invention is an apparatus for detecting breaking glass in an environment. The apparatus comprises: a sensor unit for acquiring a time domain signal from the environment; a characteristic extraction unit connected to the sensor for extracting a set of signal characteristics from the time domain signal; and a classifier connected to the characteristic extraction unit, wherein the set of signal characteristics are used by the classifier as an input data set to determine whether the time domain signal represents breaking glass.
In another aspect, the present invention includes a method for detecting breaking glass in an environment. The method comprising the steps of: acquiring a time domain signal from the environment; extracting a set of signal characteristics from the time domain signal; and, classifying the time domain signal by using the set of signal characteristics as a set of input data. to determine whether the time domain signal represents breaking glass.
In yet another aspect, the present invention includes a method for fabricating an apparatus for detecting breaking glass in an environment. The method comprising the steps of: providing a sensor unit for acquiring a time domain signal from the environment; providing a characteristic extraction unit connected to the sensor for extracting a set of signal characteristics from the time domain signal; providing a classifier connected to the feature extraction element; and training the classifier by inputting a plurality of collected signal samples to the classifier and setting an output of the classifier to a desired value, wherein the classifier is trained to determine whether the time domain signal represents breaking glass by learning to associate the plurality of collected signal samples with a corresponding desired output.
Additional features and advantages of the invention will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the invention as described herein, including the detailed description which follows, the claims, as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary of the invention, and are intended to provide an overview or framework for understanding the nature and character of the invention as it is claimed. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate various embodiments of the invention, and together with the description serve to explain the principles and operation of the invention.

Apparatus and method for detecting glass break


A roller assembly including a coupling for connecting the assembly to a panel and a roller for transferring the weight load of the panel to a sill, the roller being received in the sill and oriented for rotation about an axis which extends in a direction parallel to the weight load. The roller including a skirt that includes a brush section for sweeping debris off a surface of the sill.

Folding door systems can be either top hung or bottom rolling.
An advantage of a top hung system over a bottom rolling system is hardware used to mount a folding door in an overhead track, at a head of the system, is generally less likely to be subject to dirt and debris contamination. The hardware can accommodate larger rollers so the rolling performance is generally superior. As a result of accommodation of larger rollers, the top hung system can generally hold heavier panels.
A disadvantage of the top hung system is the head requires additional structural support to prevent the system from sagging under the weight. Also, panels of the folding door are more likely to require remedial re-adjustment should the head sag.
With the bottom rolling system, there is no need to provide additional support for the head as the weight load of the door is transferred directly into the floor. There is also no need to provide adjustment as the doors follow the contour of the floor.
However, rollers used in the bottom rolling system are more susceptible to contamination. Generally, the rollers have to be kept relatively small so as to keep the height of the threshold/sill to a minimum. However, smaller rollers tend to have a reduced load bearing capacity, generate more noise and require application of higher opening and closing forces to operate properly.

Roller assembly for a folding door system


A system and method for reliably cleaning the nozzle face of each head while flexibly coping with changes in specification for a product to be manufactured. The film forming apparatus has a plurality of heads for jetting droplets, each having an nozzle in a nozzle face; and a common head cleaning mechanism for collectively cleaning the nozzle faces, so that the head cleaning mechanism is not substantially affected by a change in the pitch between the heads, or the like. Typically, the head cleaning mechanism has a wiping sheet for wiping the nozzle faces; a supply unit for feeding the wiping sheet towards the nozzle faces; and a roller for pressing the wiping sheet against the nozzle faces while the wiping sheet is fed from the supply unit, so that an unused cleaning face can always be supplied to each nozzle face.

1. Field of the Invention
The present invention relates to a film forming apparatus having a plurality of heads, a head cleaning method for cleaning each head, a device manufacturing system for manufacturing a device, and a device manufactured by using the film forming apparatus or by a manufacturing process which includes the head cleaning method. In particular, the present invention relates to a film forming apparatus, a head cleaning method, and a device manufacturing system for reliably cleaning each nozzle face while flexibly coping with changes in specification for a substrate to be manufactured, and relates to devices manufactured using the film forming apparatus, the head cleaning method, and the device manufacturing system.
2. Description of the Related Art
According to recent improvements in various kinds of electronic devices such as computers, portable information devices, and the like, demand and applicable fields for liquid crystal devices, in particular, color liquid crystal devices, have increased. Such liquid crystal devices use a color filter substrate for colorizing the display image. In order to manufacture the color filter substrate, an inkjet method is known, in which color filter elements R (red), G (green), and B (blue) are formed as a specific pattern on the substrate.
In order to implement the inkjet method, an inkjet system having a plurality of inkjet heads for jetting ink droplets has been developed. Each inkjet head has an ink chamber for temporarily storing ink which is supplied from an external device, a pressure generating element (e.g., piezo element) functioning as a driving force for jetting a specific amount of ink stored in the ink chamber, and a nozzle face having an opening (i.e., nozzle) through which each ink droplet is jetted from the ink chamber.
The inkjet heads are arranged at an equivalent pitch so as to form a set of heads, and ink droplets are jetted while the substrate is scanned by the set of heads which is moved in a specific direction (e.g., the X direction), so that R, G, and B inks are supplied to the substrate. On the other hand, the position of the substrate in the Y direction, which is perpendicular to the X direction, is controlled at the side of a stage on which the substrate is placed.
Regarding the substrate to be manufactured (e.g., the color filter substrate), high resolution is required and thus finer patterns should be formed. In consideration of these circumstances, it is necessary for each inkjet head to very accurately supply each ink droplet (of R, G, or B) on a specific area. Therefore, each inkjet head should straightly jet a specific size of ink droplet towards a target point on the substrate. However, if ink remains on the nozzle face, the remaining ink may obstruct desired jetting of ink droplets. Such remaining ink is produced when a portion of an ink droplet adheres to the nozzle face, and it is difficult to completely prevent the occurrence of remaining ink when ink is used.
In order to solve this problem, a cleaning mechanism for wiping remaining ink which is adhered on the nozzle face may be provided for each inkjet head. However, this method causes another problem; that is, it is difficult to flexibly cope with diversified specifications for the substrate, where diversification of the substrate has been accelerated.
That is, when the size of the substrate (e.g., color filter substrate) to be manufactured, the pitch for pixels, or the like is changed in the specification, in the set of the heads, the arrangement pitch between the inkjet heads or the degree of inclination of each inkjet head with respect to the scanning direction can be changed; however, it may also be required to adjust the position of the cleaning mechanism for each inkjet head or to replace all the cleaning mechanisms. Such adjustment imposes a great burden on the worker or operator, and in addition to that, improvement of productivity may be obstructed.

Film forming apparatus, head cleaning method, device manufacturing system, and device


A system provides a description of a road segment using location reference points. The system may receive traffic information about a road segment along a road. The system may determine two sets of location reference points based on the traffic information. The system may generate a description of the road segment based on the two determined sets of location reference points.

1. Priority Claim
This application claims the benefit of priority from European Patent Application 11 158 720.0, filed Mar. 17, 2011, which is incorporated by reference.
2. Technical Field
The present disclosure generally relates to navigation systems, and more specifically relates to navigation systems operable to provide accurate road descriptions to users or vehicles.
3. Related Art
In the past, paper and other hardcopy maps were used by explorers and drivers to navigate through geographic areas. With the advent of technology, explorers, drivers and vehicles used by such explorers and drivers now may use navigation systems to assist in providing geographic travel and route information. A need exists for a navigation system that can create or generate a unique description of an area or route that may be of importance to a user, in order to provide accurate and relevant information.


Systems and methods for monitoring a computer network are provided. A network monitoring system generates a plurality of monitoring packets. The plurality of generated monitoring packets travel along respective paths through the computer network across a plurality of monitored links to respective destination nodes. Every monitored link in the computer network is included in at least one path. Each monitoring packet includes forwarding information which identifies each of the monitored links the monitoring packet is to traverse along its respective path. The network monitoring system tracks receipt of the generated monitoring packets by the respective destination nodes to detect faulty links.

The present disclosure relates generally to monitoring computer networks, and, more particularly, to detecting faulty links in a computer network.
Computer networks may include any number of routers and other devices that direct the transmission of data from one location to another. For example, a source (e.g., a computer, a smart phone, a server, a data center, a router, etc.) may transmit data using any number of different paths in a computer network to reach a destination (e.g., another computer, smart phone, data center, router, etc.). Each path is typically composed of multiple links between intermediate nodes in the network. Complete and partial failures of network links can result in congested, and in some cases, failed communications. In large networks, identifying faulty links can be quite challenging.

Systems and methods of sending a packet in a packet-switched network through a pre-determined path to monitor network health


A method and apparatus for delivering therapeutic radiation (112) to a radiotherapy target (119) in a patient (114) includes a diagnostic X-ray source (124, 125) connected to a treatment couch (116), facing a first side of the patient. An imaging device (118) is connected to the treatment couch facing a second side of the patient. The diagnostic X-ray source and the imaging device move in lockstep with movement of the treatment couch. The patient is in a fixed position relative to the treatment couch.

In radiation therapy a high dose of radiation is applied to cancerous tissue in order to destroy it or to at least slow its growth. It is critical to accurately apply the radiation so that the target receives most of the dose and surrounding healthy tissue is spared. For this reason, imaging systems have been incorporated into radiation treatment systems in order to determine if the treatment target is in the correct location when the patient is positioned relative to the treatment beam. Also, since the target may move due to respiration and other physiological processes, even when the patient remains stationary, it is desirable to obtain images of the target immediately before and during radiation treatment. A number of inventions have been directed at imaging the target before or during radiation treatment.
One means of obtaining an image of the target region is to use the therapeutic beam as the imaging source to create a portal image. The drawback of this approach is that portal images have very low contrast due to the high energy of the therapeutic beam. U.S. Pat. No. 5,471,516 solves this problem by incorporating a lower energy diagnostic X-ray source into the treatment head to produce a diagnostic portal image.
U.S. Pat. No. 6,888,919 discloses a radiotherapy machine with a first pivotal gantry that contains a therapeutic radiation source and a second pivotal gantry that contain opposing diagnostic X-ray source and imager. The diagnostic radiographic imaging unit can be rotated around the patient to provide a data set that can be used to produce a three-dimensional reconstruction of the region around the target.
U.S. Pat. No. 6,778,850 discloses a radiotherapy machine with two diagnostic X-ray sources mounted above the treatment couch that capture images of the target region from different perspectives. The simultaneously captured images are used to create a three-dimensional mapping of the target region.
U.S. Pat. No. 6,914,959 discloses a combined radiotherapy and CT imaging system. The CT system can be used to capture planning images and images of the target during treatment. In this way, the patient need not be moved between the planning and treatment phase.
A shortcoming of present methods of imaging a radiation therapy target is that they do not enable the capture of an image of the target region in which detectability of the target is optimal for all positions of the treatment couch. Furthermore, some of the present methods require that the diagnostic source be moved in order to capture several images of the target region that may be used to reconstruct a three-dimensional image. This can preclude near real-time target localization.
An object of the present invention is to provide an imaging system that can capture images of a radiation therapy target region, using desired capture conditions for which the radiation target can be detected, without the use of internal markers. Another object of the present invention is to maintain the desired capture conditions when the treatment couch is moved. Another object of the present invention is to obtain images in which the target is detectable without the need to move the imaging source or detector during the image acquisition process so that the target can be localized in near real-time.

System for the real-time detection of targets for radiation therapy


The present invention provides a control circuit with multiple power sources, which accepts an output signal from a comparator circuit. This control circuit with multiple power sources contains two components: one is a voltage transferring circuit, which connects to the comparator and accepts the first and the second input voltages to react the controls of respective output signals for generating the first voltage potential and the second voltage potential; another is an output circuit, which connects to the voltage transferring circuit to react the controls of the first voltage potential and the second voltage potential for deciding the correct output from the first input voltage or the second input voltage.

There are two main power sources of a LCD Driver (Liquid Crystal Display Driver): one is provided by an external power supplier for voltage Vdd, and another is generated by the LCD's internal circuit for voltage Vpp. And, the substrate voltage of the chip's PMOS inside the LCD driver must be higher than the voltages of source electrode and drain electrode, or the heavy leakage current will go through the source electrode or drain electrode to the substrate of PMOS to destroy the chip.
But in current general LCD driver's internal circuit, the output voltage is usually higher than the voltage that the power supplier provides after a period of running time. And for some applications of consumptive products, the output voltage of a running LCD driver may be higher or lower than the voltage that the power supplier provides.
Therefore, the substrate voltage of PMOS must be able to adjust dynamically to maintain the substrate voltage at the highest voltage value inside the chip.
Please refer FIG. 1, which shows the circuit of traditional technique that may modify the output voltage Vout to Vin or Vpp. But for some applications that need to generate two different output voltages to control different circuits, the circuit in FIG. 1 cannot reach this requirement because of its only one output voltage.
So, based on the weak point of traditional technique and with hard working, finally the applicant researches and designs the present invention named "A Control Circuit with Multiple Power Sources".

Control circuit with multiple power sources


A method of testing for misregistration in a multiple layer printed circuit board includes providing an electrical test pattern on one or more layers of the board, testing for an electrical signal between the test pattern and a test reference, and determining layer-to-layer misregistration based on the results of the testing. A method of manufacturing a multiple layer board that is configured to facilitate non-destructive testing of layer-to-layer misregistration includes forming an electrical test pattern on a first layer and forming a corresponding electrical test reference on a second layer. Then, a connecting pathway is formed between the test reference and the test pattern, including the first and second layers, with testing for an electrical signal between the test reference and the test pattern determining layer-to-layer misregistration of the first layer with respect to the second layer.

The use of multiple layer printed circuit boards, (hereinafter "PCBs"), in electronic devices has become wide spread throughout many industries. As devices and their electrical components become ever smaller, the density of the components and their connecting leads on the layers of the PCBs has increased. In addition, the use of more layers has been necessary to appropriately connect the additional components.
Multiple layer PCBs are made one layer at a time and then sandwiched together. Usually, the layers are in registration with respect to each other within designated manufacturing tolerances. During manufacturing, however, there is opportunity for each layer to experience growth, shrinkage or warping due to material properties affected by the manufacturing processes. In addition, alignment tolerances and other quality control issues may affect the stacking and alignment of the layers. As a result, layer-to-layer misalignment may occur between two or more layers within the multiple layer PCB.
Connections between the layers are necessary and are usually provided by holes drilled through one or more layers and plated to supply the electrical connection. When the layers of a PCB are not aligned correctly, the plated connection holes, also known as vias, may not line up with corresponding sites on another layer. When the layer-to-layer registration is off by a large margin, the via may not connect to the intended site at all. During subsequent electrical testing of the PCB, the misregistration will be discovered based on an electrical conduction failure of the via. Catching faulty PCBs at this stage of the manufacturing process is relatively easy and less costly to correct.
When the layer-to-layer registration is off by a smaller margin, the via may have a slight electrical connection and, thus, pass the electrical testing. When this PCB subsequently undergoes further manufacturing or assembly processes, the inadequate electrical connection may then cause a failure in the board. Failure at this stage of manufacturing or assembly is more costly, due to the added time and labor input into the formation of the PCB.
In some situations, the misregistration of the layers may cause a misalignment situation wherein there is enough electrical connection provided to pass both electrical testing of the board and subsequent manufacturing and/or assembly processes. However, the inadequacy of the electrical connection has the potential for causing reliability problems, such as early failure of the PCB during its intended use. These types of failures can be extremely costly and potentially dangerous and, thus, should be avoided by being detected during the formation process.
Implantable medical devices, such as cardiac rhythm management devices (e.g., pacing systems and defibrillators) and a variety of implantable muscle or nerve stimulators, conventionally include a battery-powered electronic pulse generator coupled to an electronic circuit assembly contained within a sealed metal housing. The electronic circuit assembly typically comprises a plurality of interconnected PCBs that function to control the operation of the implantable device.
A significant concern for manufacturers of implantable electronic devices is ensuring an adequate level of quality control and reliability in the electronic circuit assembly, and in particular in the circuit boards. Therefore, the ability to quickly and easily verify the quality of each PCB is important. The ability to detect misregistration of layers at the PCB formation stage would improve both the quality and reliability of the PCBs, as well as decrease manufacturing costs.

Multiple layer printed circuit board having misregistration testing pattern


Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Technological innovations in semiconductor fabrication technologies are driving market demands for semiconductor memory devices providing higher storage capacity, higher speed, higher integration density, and lower power consumption. The downscaling of semiconductor memory devices to submicron design rules and beyond, however, coupled with increased storage capacity poses technological challenges with respect to maintaining performance and reliability. For instance, as memory capacity increases and the pitch between adjacent patterns are made narrower, the layout of the memory arrays and peripheral devices become more problematic, especially with regard to memory core layout. When designing memory circuits, it is desirable to minimize the length and loading of wordlines. Indeed, if wordlines are too long/narrow and/or have too many memory cells connected to each wordline (i.e., a large load), wordline enable driver circuits will consume more power to drive the wordlines, and the speed of driving wordlines can decrease. To mitigate the impact on device performance with line rule downscaling and increased memory density, various memory circuit architectures have been employed including, for example, hierarchical memory bank architectures and hierarchical word line driver structures with sub word line architectures.
For instance, FIGS. 1A˜1C are schematic illustrations of a semiconductor memory device having a conventional hierarchical memory bank architectures and hierarchical word line driver framework. FIG. 1A illustrates a semiconductor integrated circuit memory chip (10) having a memory cell array with a memory capacity of 1 Gb, which is divided into a plurality of memory banks, Bank A, B, C and D (or more generally, Bank-i) (e.g., 4 memory banks of 256 Mb). Each memory bank Bank-i can be independently operated with associated peripheral circuits including column decoders (11) and row decoders (12), and well as other I/O circuitry for outputting/inputting data via peripheral data I/O pads (13). Each memory bank Bank-i comprises decoder circuits and core circuits that are arranged in "unit blocks," as depicted in FIG. 1B. In particular, FIG. 1B schematically illustrates a conventional layout of each memory bank (Bank_i) in FIG. 1A, wherein each memory bank (Bank-i) comprises a plurality of 256 unit blocks BL(i) including 16 unit blocks along an x-direction (bitline/column direction) and 16 unit blocks along a y-direction (wordline/row direction).
FIG. 1C schematically illustrates a conventional layout pattern for each unit block BL-i in the memory bank Bank-i for a memory device utilizing a hierarchical sub-word line driver scheme. Each unit block BL-i includes a cell array (20), sub-word line driver (SWD) arrays (21), bit line sense amplifier (BSLA) arrays (23) and conjunction circuit blocks including PXiD driver blocks (22) and LA driver (LADRV) blocks (24). The unit block pattern BL-i depicted in FIG. 1C is repeated in both x and y directions over the memory bank Bank-i such that each memory cell array block (20) is disposed between two BLSA blocks (23) in the x (column) direction of bit lines and such that each memory cell array block (20) is disposed between two sub-word line drivers (21) in the y (wordline) direction. In one conventional hierarchical word line framework, each block sense amplifier (23) is shared by two memory cell array blocks (20) to the left and right of the BLSA (23) and each sub-word line driver (21) is shared by two memory cell array blocks (20) above and below the SWD block (21) using an interleaved layout framework, as is known in the art.
By way of specific example, FIG. 2A is a schematic illustration of one conventional framework of a unit block BL-i such as depicted in FIG. 1C in a semiconductor device having a hierarchical divided wordline scheme. As shown in FIG. 2A, a memory cell array (200) includes an array of memory cells MC (each having a cell transistor and cell capacitor in a DRAM memory) located at the intersection of a bit line BL or BLB and a sub-word line WL. The bit lines are connected to the memory cells MC and to corresponding sense amplifiers SA in BLSA blocks (230) and (231) using an open bitline architecture, for example, as is known in the art. The BSLA blocks (230) and (231) are driven by control signals generated by drivers in respective LADRV blocks (240) and (241). In the hierarchical divided wordline scheme, a wordline is divided into a plurality of sub-wordlines WL that are driven using corresponding sub-wordline driver blocks (210) and (211) located above and below the memory cell array (200). In the exemplary embodiment of FIG. 2A, there are 256 sub word lines WL that are connected to the memory cells in corresponding rows of memory cells (where the rows extend in the Y-direction). The SWD array (210) includes a plurality of sub word line driver SWD circuits that are connected to and drive the even sub wordlines (WLO, WL2, . . . WL252, WL254) in the array (200) and a memory cell array of next lower unit block below. The SWD array (211) includes a plurality of sub word line driver circuits that are connected to and drive the odd sub wordlines WL1, WL3, . . . WL253, WL255 in the array (200) as well as a memory cell array of a next upper unit block.
The SWDs in the SWD arrays (210) and (211) are connected to normal (main) wordlines NWE and sub wordline enable lines from respective PXiD drivers (220) and (221), respectively. Each SWD circuit in the even SWD array (210) drives a corresponding even sub word line in response to control signals input thereto via a corresponding normal wordline NWE (i) and a wordline enable signal generated by the PXiD drivers (220). Each SWD circuit in the odd SWD array (211) drives a corresponding odd sub word line in response to control signals input thereto via a corresponding normal wordline NWE (i) and a wordline enable signal generated by the PXiD drivers (221). The PXiD driver blocks (220) and (221) are connected to word lines PXI<0:3>, where each normal wordline NWE-i controls a group of 4 subwordlines, wherein a given subwordline in the group is activated in response to a corresponding one of the wordlines PXI (0, 1, 2, 3). For instance, NWE (0) controls subwordlines WL0, WL1, WL2, and WL3 in response to wordline enable signals PXi<0-3>, NWE (1) controls subwordlines WL4, WL5, WL6 and WL7 in response to wordline enable signals PXi<0-3> and NWE (63) controls subwordlines WL252, WL253, WL254, and WL255 in response to wordline enable signals PXi<0-3>. With reference to FIG. 1B, there is a set of normal wordline enable lines NWE(0)-NEW(63) that extends in the y-direction for each alternating even/odd column of 16 blocks (in the y direction) such that each odd and even SWD block in each even and odd column is connected to each NWE line of the corresponding set of normal wordline enable lines NWE(0)-NEW(63).
FIG. 2B schematically illustrates an exemplary embodiment of the PXiD driver (220) and the SWD array (210) of FIG. 2A. The PXiD driver (220) comprises a PXiD generator (220a), a PXiDB generator (220b) and a PXiDG generator (220c). The SWD array (210) comprises a plurality of SWD circuits (SWD0, 2, 4, . . . 14) which are connected to and drive corresponding even subwordlines WL0, WL2, WL4, . . . , WL14). Each NWE is connected to a pair of adjacent even SWDs in the even SWD array (220) as well as a corresponding pair of adjacent odd SWDs in the odd SWD array (211) (not specifically shown in FIG. 2B). The PXiD generator (220a), PXiDB generator (220b) and PXiDG generator (220c) generate word line activation control signals that are output on line PxID(0)/PXIDB(0)/PXiDG(0) to activate the subword line drivers (SWD(0), SWD(4), SWD(8), . . . ) in each group of 4 sub word lines, as well as word line activation control signals that are output on lines PxID(2)/PXIDB(2)/PXiDG(2) to activate the subword drivers (SWD(2), SWD(6), SWD(10), . . . ) in each group of 4 sub wordlines.
FIG. 3 is a flow chart that illustrates a method for accessing memory in a semiconductor memory device having a hierarchical wordline scheme such as described above. In general, for a given memory bank, Bank-I, a 12 bit address (A0, . . . A11) is decoded to activate a sub wordline within one of the 256 memory cell arrays of the unit blocks. The upper four bits (A8, A9, A10, A11) are decoded to select 1 of 16 of the adjacent vertical memory blocks (step 30) (n4=16). The next seven upper address bits A2˜A7 are decoded by a row decoder to generate one of 64 normal word line enable signals NWE<0:63>. The lower two address bits A0, A1 are decoded by PXI decoders to drive a corresponding one of the sub word lines PXI<0:3>. As a result, one sub wordline out of the groups of 4 sub wordlines associated with the selected NWE is active where 4K bits of memory cells are enabled.
FIG. 4 illustrates a conventional sub word line driver circuit (40), which may be implemented for the SWDs in the even and odd SWD arrays (220) and (221) of FIG. 2A, for example. In general, a sub-word line driving circuit (40) drives a sub-word line WL in response to control signals NWE, PXID, PXIDG and PXIDB, and includes NMOS transistors T1, T2, T3 and T4. The sub word line driver (40) includes four control input nodes connecting to PXiD, PXiDG, PXiDB and NWE control signal lines, two power nodes for VPP and VSS and an output node N5 connected to a subword line WL. The NMOS transistor T3 has a channel connected between the NWE input (node N4) and a node N5 and a gate G3 connected to the word line activation signal PXiDG. The NMOS transistor T2 has a channel connected between control input node N1 (signal PXiD) and the output node N5 and a gate G2 connected to a boosting node N3. The NMOS transistor T1 has a channel connected between the gate G2 of transistor T2 and the NWE input node N4 and a gate G1 connected to the power voltage VPP input. The NMOS transistor T4 has a channel connected between the output node N5 and ground voltage node VSS and a gate G4 connected to a control signal input node PXiDB.
FIG. 5 is a timing diagram that illustrates operation of the sub-word line driver (40) of FIG. 4. In particular, FIG. 5 illustrates various voltage waveforms of control voltages NWEi, PXiD, PXiDB and PXiDG that are applied to drive a subwordline WLi. At time to, before an active operation, all of the signal lines shown in FIG. 5 are at Vss except PXIDB, which is an active low level IVCC that is applied to the gate G4 of transistor T4 to cause the WL at node N5 to be pulled down to VSS such that sub-word lines WL are precharged to Vss. At time t1, when a corresponding word line enable signal NWEi is activated, the boosting node N3 is charged from VSS to VPP-Vth by an overlap capacitance existing between the gate G2 and drain (N1) of the transistor T2 (where Vth denotes a threshold voltage of the NMOS transistor T1). Therefore, the boosted voltage VPP is supplied to the sub-word line WL through the NMOS transistor T2. At time t2, the control voltage PXiDB transitions to VSS causing transistor T4 to turn off. At time t3, the control signals PXID and PXIDG are asserted. The control signal PXiD is enabled to VPP, which causes the voltage at boosting node N3 to increase to 2 Vpp-Vth. This causes the corresponding sub-word line driver SWD to drive the corresponding sub-word line to Vpp. The NMOS transistor T3 serves to maintain the sub-word line WL in logic "low" state when the main word line driving signal NWE is in logic "low" state and the sub-word line driving signal PXID is in logic "high" state. After the access operation is complete, the sub-word line driver precharges the sub-word line WL to Vss.
Conventional semiconductor memory devices having a sub word line driver structure as described above may have an increased layout area due to the presence of the sub wordline driver arrays between the memory arrays. When designing semiconductor memory devices with sub word line driver framework, it is important to minimize the layout area required for the sub wordline drivers. Indeed, the layout area of the sub word line driving circuits has a significant influence upon the overall operating efficiency of the device memory device and the level of integration that may be achieved.

Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density


The invention includes a router and adapter enabling to receive any type of vendor Intelligent Network protocol message, then to direct the message (according to predefined rules) and ultimately, to translate one type of message into a unified format in order to meet with the destination protocol requirements and the mediating method according to the present invention enable communication between different (SSP) telephone message switching protocols and different control point system (SCP) message protocols; the method is based on conversion processes that enable identification of message definitions and information and the creation of unified message records.

The present invention relates to telephony systems and, more particularly, to a telephony system that enables telephony service providers to use various Intelligent Network services.
With the growing need to respond to a wide variety of requirements for communications, consideration has been directed toward making networks highly intelligent. Hence, the IN (Intelligent Network) has been proposed for this purpose.
An Intelligent Network (IN) is a service-independent telecommunications network. That is, intelligence is taken out of the service switching point (also referred to as SSP) and is handled by service control points (SCP) where the service logic is located. This provides the network operator with the means to develop and control services more efficiently. In such an IN, a plurality of intelligent peripherals (will be abbreviated to IP) and pluralities of vender feature nodes (VFN) are used as terminal devices.
Each of the terminal devices is connected to a service control point (SCP) through a service switching point (SSP), which is operable in a manner similar to a conventional exchange system. Each of the SCPs is managed by a service management system (SMS), which has a database. Having the service control points located separately from the switching facilities allows services to be added or changed without having to redesign switching equipment.
By way of illustration, a call handling procedure in a conventional IN based prepaid system is performed as follows:                A prepaid subscriber dials a number that is received by a service switching point (SSP) at the telephone company central office.        The SSP detects the event and sends a query request to the SCP based on the call source and destination and additional billing rules located in the database.        The SCP returns the SSP corresponding charging parameters and the maximum call duration allowed. If the subscriber's balance is lower then the amount required for making the call, the call request is denied. Otherwise the SSP connects the subscriber to the destination requested, and upon termination of the call a charge request sent to the SCP.        Other examples of services that may be provided by SCP include area number calling, disaster recovery and do not disturb services.
The SSP communicates with each SCP by transmittal of a service control request message (from the SSP to the SCP). The SCP executes a call control operation, which provides service to a user connected through the SSP. The call control operation is determined by the service control request message.
Therefore, in conventional Intelligent Networks, the SCP should be designed to respond to the service control request message and to provide the service to each user as long as the service control request message has the format determined for the SCP.
In practice the SSP may not always be connected to terminal devices that have the service control request message of the same format, but may be connected to a plurality of terminal devices that are different in species from one another. In this case, the SCP is supplied from each of the terminal devices through the SSP with service control request messages of format that are different from one another in order to specify the species of the terminal devices.
In addition, at times, a new model SSP may partially substitute an old model of SSP, both of which may be connected to the same SCPs. According to prior art it is impossible for an SCP to communicate with both SSPs.
Hence, in conventional Intelligent Networks, each SCP can neither respond to different service control request messages nor cope with the coexistence of the old and the new model SSPs. Simply put, each user (SSP) is designed to communicate with one specific SCP.
This situation, whereby an SSP can only be defined to communicate with a specific SCP, creates a limitation for telecom providers. A company providing telecom services, which has purchased an Intelligent Network platform from a certain vendor, will probably need to purchase all additional Intelligent Network services and solutions from the same vendor. For example, if a telecom service provider has purchased an Ericsson switchboard he would be obliged to use Ericsson SCP to supply the additional Intelligent Network solution
This limitation becomes more acute when the same telecom provider is interested in an additional service that only a second vendor can provide. In this case, the telecom provider would not be able to purchase additional services since the provider's SSP can only send the request to the originally defined SCP.
A possible way to get round the limitation created by the prior art is to relate the Intelligent Network service to designated numbers rather than to a specific user. The problem created using this solution is that the telecom provider would not be able to relate each service to a destination number but to a range of numbers, making the procedure impossible to manage.
Another deficiency of the prior art Intelligent Network service configuration is that two different services can't be integrated. For example, if a virtual number service and prepaid costumer service are from different equipment providers, the operator is unable to provide integrated service, thus the operator needs to build a new integrated service.    IN platforms are complex systems and require in-depth understanding of their architecture and protocols. Although IN standards such as CS-1 and CS-2 were defined and accepted by the industry, each switch vendor enhances its protocol so more capabilities can be added. Newer standards such as CAMEL and PARLAY are not yet widely adopted by the industry and it will take the vendors a few years to implement and market them. This makes things more difficult and more complicated for IN solution developers.    Prepaid systems are closed systems. They do not provide any open API for third party developers in order to integrate with these systems and exploit the capabilities of prepaid infrastructure. Thus many Data and Value Added Services (VAS) providers are not able to integrate to prepaid systems and are unable to offer these services to prepaid subscribers.    Telecom operators invest millions of dollars and a great deal of time in buying, assimilating and operating prepaid systems. Replacing or upgrading these systems is done every few years due to the high costs involved. Thus telecom operators are looking for a low cost solution that can offer an easy way to interconnect Data and VAS with the prepaid systems, thus enabling them to maximize revenues from existing and new services.    Telecom operators invest time and money in developing services that cannot communicate with one another. In order to provide integration of different services, the operators need to buy a new service and manage plural provisional databases.

Method and system for integrating multi services for intelligent networks


The present invention relates to a method and apparatus for the prevention of fouling of process streams by the application of electric charge on process components. The electric charge may be attractive or repulsive to the foulants, they may be constant or variable and may be applied to any section of the process stream where convenient and wherein their preventive effects are optimized.

In a number of industrial applications, it is either necessary or desirable to transfer heat from one fluid to another. This transfer is most commonly performed by a heat exchanger. Heat exchangers perform their function by using various flow designs and arrangements of different fluids, between which heat is transferred. These devices find use in refineries, fossil-fuel and nuclear power plants, in the chemical industry, air conditioning and refrigeration, as well as in cooling applications for small scale power devices. Oftentimes, they are given different names depending upon the environment in which they are used. Condensers, coolers, superheaters, evaporators, and other devices, are all properly considered heat exchangers.
One prominent application of heat exchangers is in distillation processes. These processes involve the separation of multi-component mixtures into purified fractions by one or more cycles of vaporization and condensation. Because the vaporized and condensed states are of different internal energies, heat transfer to and from these states is the most common means used for their interconversion.
In the petroleum industry, an interconversion method known as fractional or differential distillation is used. This technique is important for the separation of multi-component liquids in which the individual liquids have boiling points that lie close together. This technique involves repeated vaporization and condensation. Heat exchangers are of particular importance here. Due to the multi-component nature of the distillate and its multiple boiling points, the heat exchanger must be efficient enough to allow the closest possible thermal contact between the rising vapor and the descending condensate. Thus, efficient, trouble-free heat exchangers have particular applicability for use in connection with the refining of petroleum products and in the chemical and petrochemical industries.
Heat exchangers operate most efficiently where the surface area of the heat exchanger that is in contact with the medium to which heat is transferred is maximized. One way to achieve improved heat transfer is to minimize any contaminants located on the heat transfer surfaces. When heat exchange surfaces are deposited with particulates and other matter, thereby decreasing the effective area of the heat transfer surfaces, they are "fouled." Such fouling will adversely affect the heat exchange process and can potentially have a major negative impact on the economics of a refining operation. While minor fouling leads to a tolerable decrease in the efficiency of heat exchangers, this effect becomes more pronounced over time as the extent of fouling increases. In more extreme cases, fouling may lead to total failure of the heat exchanger with significant economic costs.
In petroleum refining applications, a common type of fouling is caused by particulate fouling. This may occur by the slow accumulation of foreign material, but is more likely to come from the breakdown of catalytic material used in the petroleum industry. Catalyst is often fabricated into small particles in which the active catalyst is immobilized onto a solid support with the goal of maximizing the catalyst surface area. Oftentimes, the catalyst is impregnated into the pores of a solid support. With time, the catalyst particles degrade and migrate into areas where they may foul equipment. The heat exchanger is one piece of equipment that is particularly susceptible to fouling due to the need to keep its surfaces contaminant-free. The small particle, high surface-area catalysts used in the refining industry are of the ideal configuration to cover the surface of the heat exchange element and decrease its efficiency. The most common scenario of particulate fouling by catalysts in petroleum refining is by the mechanisms of migration and attachment.
For example, Clarified Slurry Oil (CSO) heat exchangers are used in the field of petroleum refining in connection with fluid catalytic cracking units. They play an integral role in keeping the Fluid Catalytic Cracking Unit (FCCU) in heat balance and at maximum charge rate. The heat source of the main distillation column is the FCCU reactor effluent entering between the Light Cycle Oil (LCO) draw and the distillation tower bottom.
The CSO heat exchangers in a typical oil refining process are susceptible to fouling when the catalyst containment efficiency of the FCCU cyclone separators decreases. This event will usually occur near the end of run or when the integrity of the catalyst containment equipment is compromised. Fouling occurs when a layer of catalyst particles accumulates on the heat transfer surfaces of the heat exchanger. This layer of catalyst reduces the efficiency of the heat exchanger to transfer heat as a result of the loss of heat transfer surface area on the fouled surfaces.
One interim response to such a situation is to decrease the FCCU feed rate. This has the undesirable effect of decreasing product throughput.
The typical curative response to such a situation is to take the unit off-line and perform cleaning maintenance. While this will regenerate the apparatus to its earlier efficiencies, it is also an undesirable remedy. Whenever the FCCU is in turndown mode or is taken off-line for unscheduled maintenance, the refiner is losing the opportunity to operate the FCCU at its optimal revenue-generating capacity. Unplanned maintenance is much costlier than planned maintenance. Resources must be secured with little if any, lead time. The effect on unit operations costs of downstream units (e.g., wastewater treatment) will increase.
Moreover, cleaning the CSO heat exchangers is also a potentially dangerous task. A high pressure steam lance is typically used to remove the fouling layer. Liquid temperatures are approximately 700° F. The process is labor intensive and the liquids used have the potential to cause severe burns to personnel performing the operation. Any mechanism to eliminate or reduce the frequency of such maintenance will be beneficial to refining operations.
Because of the undesirable effects associated with fouled exchangers, there have been many attempts to address the problem.
For example, U.S. Pat. No. 4,370,236 teaches the purification of hydrocarbons by the electrostatic precipitation after the formation of an aqueous admixture of the hydrocarbon. The '236 purification method requires the precipitation of foulants. Additionally, the teaching of the '236 patent requires, among other things, the formation of an aqueous liquid.
In a somewhat related field, there have been efforts to address particulate fouling in gaseous streams. U.S. Pat. No. 5,318,102 to Spokoyny, et al., teaches how to improve resistance to fouling in heat exchangers for gas streams through the use of plate packs. Plate packs are a unique configuration of an array of heat transfer plates. This array affords a gradual decrease in pressure of the gas stream while maintaining good thermal contact with the gas and minimizing particulate deposition. This process only contemplates gaseous streams and fails to consider other fluids and, in particular, petroleum streams. U.S. Pat. No. 4,885,139 to Sparks, et al. also focuses on gaseous streams; in particular, on the removal of acidic gases from gaseous flow streams. Sparks also fails to consider fluids and requires a complex multistage process. Finally, U.S. Pat. No. 6,089,023 to Anderson et al. teaches a method that employs a decrease in temperature of the exhaust gas stream, thereby improving the efficiency of a subsequent electrostatic precipitation. Anderson, like Spokoyny and Sparks, is directed toward gaseous streams.
One common practice in the petroleum refining industry used to address the problem of foulants uses an arrangement of columns or chambers packed with ferrous metallic particles to which a charge is applied. The hydrocarbon fluid to be purified of contaminants is passed through the columns. While this method utilizes electric charge for purification, it is in actuality, a form of chromatography, as the contaminant particles are trapped by the column packing. The Gulftronics™ catalyst separator is currently the most common known commercial embodiment of this technology. It is a modular (skid mounted) apparatus designed to be placed in the CSO circulation loop. CSO enters the individual chambers of the Gulftronics™ which are aligned in series. Each chamber is filled with ferrous metallic spheres. An electronic charge is applied to these spheres to attract the catalyst particles to their surface, thus clarifying the CSO stream. Once the spheres accumulate enough catalyst particulates, the electric charge is turned off and the flow is redirected to new or regenerated purification chambers or back to the FCCU riser or to a slurry settler. When an adequate amount of time to purge the saturated chambers has elapsed, the flow may again be redirected to the original purification chambers which now contain reconditioned spheres. This method and apparatus entails complex hardware and requires intensive scheduled maintenance. The chromatographic columns must be regenerated or replaced as they become saturated. A non-chromatographic method which does not involve column regeneration or column switching is desirable. Moreover, space must be allocated for it immediately upstream of the CSO heat exchangers. Piping modifications must be made to tie the apparatus into the CSO circulation loop. Piping modifications must be made from the prior art apparatus into the FCCU riser or a slurry settler.
Because of the shortcomings of the prior art, the need presently exists for a simple in-line method to prevent or minimize fouling in these complex liquid streams.

In-line method and apparatus to prevent fouling of heat exchangers


A light emitting element drive apparatus includes a differential signal processing circuit for performing logic processing of input complementary image signals that are 180.degree. out of phase and at least one control signal using a differential circuit while maintaining the complementarity of signals to generate complementary output signals, and a switching circuit which is driven by the complementary output signals to supply a drive current to a light emitting element.

1. Field of the Invention
The present invention relates to a drive apparatus for a light emitting element (e.g., a semiconductor laser) used as a recording light source in an image forming apparatus or the like.
2. Related Background Art
The applicant of the basic application filed in Japan has proposed such a light emitting element drive apparatus in Japanese Laid-Open Patent Application No. 8-56034. This drive circuit turns on/off by switching the differential circuit using bipolar transistors. FIG. 1 shows the drive circuit of this prior art. Referring to FIG. 1, this circuit comprises differentially connected npn transistors 101 and 102, an insulating-gate-type NMOS transistor 103 which has a drain connected to the common emitter of the npn transistors 101 and 102 and performs constant current operation, and a semiconductor light emitting element 104 having a cathode connected to the collector of the transistor 101 through a parasitic inductance 106 of the line.
As the semiconductor light emitting element 104, a semiconductor laser or the like is used. A latent image is formed on a photosensitive medium (not shown) by turning on/off this light emitting element in accordance with image data. This circuit also has a load resistor 105 connected to the collector of the transistor 102, a parasitic inductance 107 of the line between the anode of the semiconductor light emitting element 104 and a power supply 115 as a high-potential reference voltage source, a junction capacitance 108 (C.sub.j) of the semiconductor light emitting element 104, emitter-collector capacitances 109 and 110 of the transistors 101 and 102, and a drain-gate capacitance 111 of the NMOS transistor 103 which operates as a constant current source.
One terminal of a resistor 112 is connected to the gate of the NMOS transistor 103 and one terminal of a capacitance 113. The other terminal of the resistor 112 is connected to the gate and drain of an NMOS transistor 114. The other terminal of the capacitance 113 is connected to a ground potential 116 as a low-potential reference voltage source. Inverters 117 and 118 supply complementary switching signals 121 and 122 to the bases of the differentially connected transistors, respectively. A constant current source 119 supplies a constant current to the NMOS transistor 114. Data 120 turns on/off the light emitting element.
The input data 120 is converted into the complementary signals 121 and 122 by the inverters 117 and 118 and supplied to the bases of the transistors 101 and 102. By switching the differential circuit comprised of the transistors 101 and 102 in accordance with the input data, the drain current from the NMOS transistor 103 as a constant current source is supplied to the light emitting element 104 or stopped.
The drive circuit shown in FIG. 1 is used for the engine of an LBP (Laser Beam Printer) or the like. In this case, the input data 120 corresponds to image data supplied to the printer. When the image data 120 is at high level, the light emitting element is turned off. When the image data 120 is at low level, the light emitting element is turned on. In FIG. 1, the NMOS transistor 103 is used as a constant current source to obtain a current pulse free from ringing or overshoot.
The applicant of the basic application filed in Japan has also proposed an image forming apparatus using the electrophotography process in Japanese Laid-Open Patent Application No. 8-46273. The image forming apparatus of this prior art will be described with reference to FIGS. 2A and 2B. Referring to FIG. 2A, this apparatus comprises a semiconductor laser drive circuit 201, a semiconductor laser control IC 202, a semiconductor laser diode (to be referred to as an LD hereinafter) 206, and a photodiode (to be referred to as a PD hereinafter) 207. This apparatus also has a sequence controller 203 for driving the image forming apparatus and controlling the electrophotography process, a CPU 204 of the sequence controller 203, an image controller 205 for converting character data from the host computer into dot data, a power supply line 214, and a ground line 213.
The semiconductor laser drive circuit 201 is integrated as the control IC 202. The control IC 202 has an arrangement shown in FIG. 2B. High-frequency band closed loop characteristics are realized by amplifiers 250 and 251. The light emitting amount of the LD 206 is controlled to a light amount designated by a light amount control signal 211 from the sequence controller 203 in units of pulses of an image signal. When a forced lighting signal 212 or an image signal 210 is active low, a drive current is supplied to the LD 206 through an AND circuit 253 and the amplifier 250. When the LD 206 emits light, a photocurrent flows to the PD 207. The amplifier 251 compares the set value output from a data conversion circuit 252 on the basis of the light amount control signal 211 from the CPU 204 with the photocurrent to the PD 207 and controls the light emitting amount of the LD 206 to the target light amount.
FIG. 3 shows signals at various sections of the circuit shown in FIG. 2A. A paper sheet 230 has a printing area 231. The image signal 210 is turned on/off in the printing area 231 in accordance with a horizontal synchronizing signal to form a latent image on a photosensitive medium. At this time, the light amount control signal 211 is set at a predetermined voltage (voltage value at which the light emitting amount of the LD 206 has a desired value). The light amount of the LD 206 can be changed by changing the value of the light amount control signal 211. In this case, as the voltage of the light amount control signal 211 becomes low, the light emitting amount of the LD 206 becomes large. To lower the resolution or increase the image density, the value of the light amount control signal 211 is set to be smaller. Outside the printing area 231, the light amount control signal 211 is turned off (high level) and used as a mask signal for the image signal 210. Hence, even when the image controller 205 turns on the image signal 210 outside the printing area 231, the LD 206 is prevented from emitting light.
In the image forming apparatus, the motor and optical system including the semiconductor laser are driven as a preprocess for printing. At this time, the sequence controller 203 turns on (low) the forced lighting signal 212 to forcibly turn on the LD 206 independently of image input, thereby testing the operation of the optical system including the LD 206. When the forced lighting signal 212 is to be turned on, the light amount control signal 211 must be set at predetermined value. In the image forming apparatus having the above arrangement, the horizontal synchronizing signal (BD signal) used as a synchronizing signal of each line is obtained by causing the LD 206 to emit light before the printing area 231 and detecting the laser beam with a sensor (BD sensor) set at a predetermined position. In forming the BD signal as well, the forced lighting signal 212 is turned on, and the light amount control signal 211 is set at a predetermined value.
This processing of masking the image signal outside the printing area and forcibly turning on the semiconductor laser diode is performed by the sequence controller 203. Instead, the sequence controller 203 may supply a light amount control signal 211 and forced lighting signal 212 to the semiconductor laser drive circuit 201, so the processing is executed on the semiconductor laser drive circuit 201 side. With this arrangement, the processing load on the sequence controller can be decreased. In addition, since image processing which is normally done by the sequence controller is executed by a versatile gate array or the like, degradation in pulse width reproducibility of the image signal from the image controller can be prevented.
FIG. 4 shows a two-input NOR circuit using a general ECL (Emitter Coupled Logic). A differential circuit is formed by a pair of npn transistors 301 and 302 and an npn transistor 303. The circuit has a constant current source 304 for supplying a constant current to the differential circuit, resistors 305 and 306 as the load of the differential circuit, a power supply line 308, and a ground line 307. Complementary outputs 309 and 310 from the differential circuit are connected to the input terminals (base electrodes of npn transistors 311 and 312) of a level shift circuit comprising the npn transistors 311 and 312 and constant current sources 313 and 314. This level shift circuit adjusts the DC level of the output from the NOR circuit to the input range of the subsequent stage. Outputs 315 and 316 from the level shift circuit are complementary outputs from the NOR circuit. Inputs 317 and 318 to the NOR circuit are input to the bases of the npn transistors 301 and 302, respectively. A reference voltage 319 is used to determine high or low level of the inputs 317 and 318 and input to the base to the npn transistor 303.
In the circuit shown in FIG. 4, when at least one of the inputs 317 and 318 is larger (higher) than the reference voltage, at least a corresponding one of the transistors 301 and 302 is turned on, and the transistor 303 is turned off. Hence, the constant current from the constant current source 304 flows to the load resistor 305, and the output 309 from the differential circuit and the output 315 from the NOR circuit go low. To the contrary, no current flows to the resistor 306. The output 310 from the differential circuit equals the power supply voltage, and the output 316 from the NOR circuit goes high, so an output signal complementary to the output 315 is output.
On the other hand, when both the inputs 317 and 318 are smaller than the reference voltage, both the transistors 301 and 302 are turned off, and the transistor 303 is turned on. The current from the constant current source 304 flows to the load resistor 306, and the output 310 from the differential circuit and the output 316 from the NOR circuit go low. To the contrary, no current flows to the resistor 305. The output 310 from the differential circuit equals the power supply voltage, and the output 315 from the NOR circuit goes high, so an output signal complementary to the output 316 is output. As described above, the circuit shown in FIG. 4 operates as a NOR circuit (output 315) or an OR circuit (output 316) for receiving the signals 317 and 318. By selecting the load resistor and the constant current value so the transistors operate in the nonsaturation region, a circuit arrangement allowing high-speed operation and suitable for high-speed signal processing is realized.
For current print systems using laser beam printers, image or photograph output, higher-speed processing, and higher resolution are increasingly required. For a laser diode, a switching speed of several ten MHz to several hundred MHz is required. Additionally, to realize a higher image quality, it is essential to obtain high reproducibility of output pulse width of a laser diode. The scheme of controlling the current to the light emitting element by switching operation of the differential circuit using bipolar transistors shown in FIG. 1 is advantageous for high-speed processing. However, this circuit poses the following problems because a single image signal is received by the control IC, and complementary input signals to the differential circuit are generated in the control IC using inverters.
As the first problem, when a single image signal is converted into the complementary signals 121 and 122 using the inverters 117 and 118 and input to the differential circuit formed by the transistors 101 and 102, a delay difference is generated between the two signals because the signal 122 passes through the second inverter 118, so the output pulse width of the laser diode shifts from the original image signal. More specifically, both the signals 121 and 122 temporarily go high or low due to the delay difference. During this time, the current from the constant power supply 111 nearly equally flows to the transistors 101 and 102. The current flowing to the light emitting element is 1/2 the predetermined amount and cannot reach the threshold current for light emission. During this time, no light emission occurs, and the light pulse width becomes small. This appears as a line width difference (decrease) in output from the LBP. The delay time per inverter is several tenth to one nsec. This poses no problem when the speed or resolution is low. However, when an operation speed of several ten MHz to several hundred MHz is required, the delay poses a serious problem.
The second problem is noise. Use of a single image signal is disadvantageous because RF noise is generated on a substrate on which a control IC is mounted or a semiconductor substrate on which a light emitting element drive circuit is integrated as the operation speed becomes higher. As a high-speed logic circuit, the ECL circuit shown in FIG. 4 can be used. However, complementary inputs cannot be processed except when the circuit is used as an inverter. To perform signal processing as shown in FIGS. 2A and 3, the image signal must be temporarily converted into a single output and processed, and then complementary signals must be generated again. In this case, however, the initial purpose of obtaining a noise-free signal by transmitting complementary signals cannot be achieved. In addition, the circuit scale becomes large to result in an increase in cost.


The disclosed embodiments illustrate methods and systems for managing a conversation between a first user and a customer care agent. The method includes extracting one or more features from a first conversation between said first user and said customer care agent. The first conversation corresponds to an ongoing conversation over an electronic communication medium. The method includes determining a score for a feature. The score indicates a deviation of a value of said feature from an average of values of said feature determined from historical conversations involving said first user. The method includes aggregating said score for each of said one or more features of said first conversation. Thereafter, the method includes redirecting said first conversation of said first user to a third user during said first conversation based on said aggregation. The third user manages said first conversation between said first user and said customer care agent.

As computers and software proliferate, a need for a help desk assistance may be critical for those customers who may not be technically sophisticated. The need for the help desk assistance may be provided either through customer care representatives, or automated agents. Usually, the customer care representatives may be trained to handle limited problems that the customers frequently face while using a product or a service. Further, the customer care representatives usually have a predefined set of steps that will ask the customers to follow in order to overcome a problem. This may lead to the customers becoming frustrated. On the other hand, the automated agents may be trained only to handle certain common problems. Typically in such scenarios, the customer problem is unknown to the automated agents. Further, a highly valued customer is unhappy with the automated agent's support. Hence, organizations may face a very challenging task to maintain their communication with their customers. Thus, such methods may not result in a good customer experience.

Customer relationship management system based on electronic conversations


A extended use elevated urinal tray for high volume usage mounted wall urinals (32) to prevent urine splatters (34) from accumulating on the floor or a mat underneath the urinals extreme edge (30) comprising a base frame portion (18) adapted for placement on the floor underneath the urinal (32) and allows variability for urinal users of different foot sizes placement and an elevated sloped tray portion (10) disposed on the base portion that does not come in contact with the urinal users shin (38) or ankle (36) area and covers the open space (40) between the users ankles and high shin area that urine splatters transit to accumulate on the floor; equipped with a detachable member (26) near the downward end of the sloped tray capable of receiving, and absorbing urine deposits until such time the absorbent material (28) is emptied, replenished and replaced for continued use.

This invention relates to the placement of an elevated urinal tray for preventing urine from accumulating on a restroom floor or on a mat underneath the urinal. More specifically, the current inventions intended purpose is to is to prevent a urinal user at high volume public type restrooms, such as restrooms at large sporting events, restaurants and concerts from having to step on a urine saturated mat or urine puddled on the floor.


D-glyceric acid has been found to enhance alcohol metabolism and thereby prevent adverse effects of alcohol consumption. D-glyceric acid is administered concurrently with alcohol, to accelerate the elimination of the alcohol from the body. D-glyceric acid is converted into D-glyceraldehyde and further into glycerol in reactions catalysed by NADH-aldehyde dehydrogenase and NADH-alcohol dehydrogenase complexes, which are produced in excess during alcohol oxidation, in the cells of alcohol-metabolising tissues. In these reactions, the NADH complexes become NAD-aldehyde dehydrogenase and NAD-alcohol dehydrogenase complexes. These complexes in turn accelerate the oxidation of alcohol, which is paralleled by enhancement of acetaldehyde oxidation to metabolically harmless acetic acid. D-glyceric acid or its salt or ester is used for the manufacture of a pharmaceutical preparation for enhancing the metabolism of alcohol. A method of enhancing the metabolism of alcohol in a subject by administering said compounds an effective amount of D-glyceric acid or its salt or ester is disclosed. An oral or parenteral preparation comprising said compounds is also disclosed.

It is known that 5% of the ethyl alcohol i.e. ethanol (hereinafter alcohol), C2H5OH, ingested by a human being is excreted unchanged while the remaining 95% is degraded to acetaldehyde (hereinafter AcA), CH3CHO, in the cells of alcohol-metabolising tissues, mainly the liver. This reaction (Reaction 1) takes place in the cytoplasm of hepatocytes and is catalysed by the local enzyme alcohol dehydrogenase, ADH. The reaction uses one molecule of the coenzyme nicotinamide-adenine dinucleotide, NAD, per each molecule of alcohol:

During the reaction, NAD and ADH form an enzyme-coenzyme (ADH-NAD) complex, with NAD being concurrently reduced to NADH. The NADH is then detached, and the ADH is ready to repeat the reaction by accepting a new NAD molecule. The cell has a limited capacity to oxidise NADH back to NAD, which determines the maximum velocity of the reaction. A normal liver metabolises alcohol at the rate of about 8 g/h. The rate is independent of the concentration of alcohol in blood. There is an excess of ADH enzyme for the reaction.
The AcA molecules converted from alcohol move into cytoplasmic organelles known as mitochondria where they are oxidised to acetic acid, CH3COOH, in a reaction (Reaction 2) catalysed by the enzyme aldehyde dehydrogenase, ALDH:

In this reaction, too, one molecule of the coenzyme NAD is reduced to NADH. Both the latter and the NADH previously accumulated in the cytoplasm are reoxidised to NAD in the mitochondrial respiratory chain at the maximum capacity of this system. The maximum capacity of the mitochondrial respiratory chain depends on the overall level of metabolism of the body.
The above-described process of alcohol metabolism is illustrated in FIG. 1.
The metabolically harmless acetic acid, derived from alcohol through AcA, is oxidised to carbon dioxide and water mainly in extrahepatic tissues.
The capacity of cells to oxidise NADH back to NAD is exceeded during alcohol degradation according to Reactions 1 and 2. As a result, cells accumulate an excess of NADH compared with NAD. This change in the cellular oxidation-reduction equilibrium, which always takes place in connection with alcohol metabolism, causes inhibition of NAD-mediated enzyme reactions typical to the normal metabolism of the hepatocyte. The most important of these inhibited systems is the citric acid cycle. A positive NADH/NAD ratio, leading to inhibition of the citric acid cycle, is considered the most important reason for the development of alcohol-induced fatty liver.
In a normal liver, 99% of the alcohol brought by blood circulation is metabolised to acetic acid. The remaining 1% is released as AcA into the circulation. So, the capacity of the alcohol-metabolising tissues is not fully sufficient to oxidise all the AcA formed in Reaction 1 to acetic acid according to Reaction 2. This is evident, for instance, from the fact that the venous blood flowing out of the liver during alcohol metabolism carries a 15-μM concentration of AcA (Eriksson and Fukunaga 1992).
The acute toxicity of AcA (mouse LD100=0.75 g/kg) is severalfold compared with that of alcohol (mouse LD70=6.5 g/kg).
As explained above, during alcohol use about 1% of AcA normally "escapes" Reaction 2 in the liver and enters the blood circulation at the rate of about 1 mg/min (60 mg/h). If the alcohol consumption is sufficient to maintain a concentration of alcohol in blood for 24 hours (200 g of alcohol is enough, i.e. the amount contained in a half-liter of distilled spirit), the amount of AcA released into the circulation is on average 1.5 g. As a single dose, this amount of AcA would be enough to kill 100 mice each weighing 20 g.
Still larger amounts of AcA than those mentioned above are released into the blood circulation in case of impaired ALDH activity. A reduction as small as 10% in the capacity of hepatic ALDH triples the amount of AcA leaked into the circulation.
ALDH can be inhibited by certain drugs, such as disulfiram (Antabuse®). In a person on disulfiram therapy, ingestion of a few grams of alcohol will produce very unpleasant symptoms lasting up to several hours. The symptoms include headache and a flushed skin. Dyspnoea and nausea are also common, as are tachycardia and hypotension. The symptoms are due to AcA accumulation in the body.
Heavy use of alcohol is followed by hangover, a familiar consequence of alcohol intoxication. A person fearing hangover may seek to prolong his/her use of alcohol. The fact that efforts to develop an adequate pharmacological means of treating hangover have so far been unsuccessful may also contribute to such behaviour. Alleviation of hangover has been attempted by vitamins and trace elements (cf. U.S. Pat. No. 4,496,548). A major part of hangover symptoms may be due to the toxic effects of AcA.
Biochemical and medical research suggests a major role for AcA in the development of alcohol dependence. These conclusions are based on the changes that AcA induces in the structures of cerebral neurotransmitters. AcA has also been found to inhibit enzymes involved in protein synthesis and to alter the immunological properties of tissues. Through such mechanisms, AcA may in fact play a more significant role than alcohol in the aetiology of many alcohol-related diseases, such as brain damage and hepatic cirrhosis and also compulsive drinking itself.
As explained above, it has become clear that elevation of the NADH/NAD ratio, which suppresses normal metabolism in alcohol-metabolising tissues, and the release and accumulation of AcA in the systemic circulation and thereby in the entire body are major mechanisms in the development of alcohol-related health problems.
In view of the above-mentioned facts, AcA-binding compounds have been deployed to reduce the amount of AcA released into the systemic circulation and to lessen the consequences of such release. These compounds include the sulphur-containing amino acids cysteine and methionine. Oral administration of methionine to experimental subjects during alcohol drinking has yielded 20% reductions in blood AcA concentrations (Tabakoff et al. 1989). It should be noted, however, that methionine-bound AcA may later detach, thus obliterating the minor benefit achieved. Furthermore, methionine and other similar substances do not affect the rate of alcohol metabolism, nor the NADH/NAD ratio.
In addition to the above-mentioned methods, it has been proposed that the adverse health effects of alcohol might be reduced with agents that modify the rate of alcohol metabolism:
Both the amount of AcA released from the liver and the NADH/NAD ratio can be lowered by 4-methylpyrazole, 4-MP. This is an ADH inhibitor which slows down Reaction 1 (see page 1). As a result, the production of AcA is reduced and, with less substrate, Reaction 2 becomes more effective allowing more extensive conversion of AcA to acetic acid. Owing the diminished total capacity of the reactions, there is no intracellular accumulation of NADH. 4-MP is useful in special circumstances requiring deceleration of alcohol metabolism, e.g. in the management of methanol poisoning. 4-MP is not suited to addressing the aforementioned problem of AcA accumulation. Because of its decelerating effect on alcohol elimination, it would be impossible to use in conjunction with conventional alcohol drinking (risk of alcohol poisoning).
The accelerating effect of fructose on the rate of alcohol elimination has been known for a long time (Crownover et al. 1986). The elimination rate may be enhanced by up to 20% but this requires large doses (1-5 g/kg) to be taken together with the alcohol. Trials have been conducted of the prevention of hangover symptoms by means of fructose, without tangible benefit. It has been established that acceleration of alcohol metabolism by fructose is effected specifically through Reaction 1. This method of increasing the rate of alcohol metabolism leads to the formation of a corresponding amount of AcA which the cell is unable to metabolise to acetic acid. This is reflected as a corresponding elevation of AcA concentration in the blood flowing out of the liver (Eriksson and Fukunaga 1992).
It has also been known for a long time that D-glyceraldehyde (hereinafter D-GA; see FIG. 3, "Metabolism of fructose", (Harper et al. 1977)), a metabolite of fructose, has an accelerating effect on alcohol metabolism (Thieden et al. 1972). The effect of D-GA on the metabolism of AcA is similar to that of fructose, in that the accelerating effect on alcohol metabolism takes place via Reaction 1 and not via Reaction 2. Akin to fructose, D-GA therefore tends to cause AcA accumulation.
U.S. Pat. No. 4,450,153 presents a solution whereby blood alcohol concentration can be rapidly reduced using an alcohol oxidase enzyme isolated from certain species of yeast. Said enzyme degrades alcohol to AcA in the extracellular space. This causes large amounts of AcA to enter the blood circulation and, consequently, a risk of AcA poisoning.
The present invention offers substantial remediation of the shortcomings presented above.


A resonance oscillator comprises an active, e.g. disk-shaped, oscillator part (2) which is brought into contact, forming a couple oscillator, with a passive, comparatively longer oscillator part. This oscillator part, which basically determines the resonant frequency, consists of a variable-length solid column or liquid column (11) the length of which can be varied continuously in the direction of the sound vector in order to change the resonant frequency. The active oscillator part (2) is mounted on the base of an elongated resonance container (6) which contains the liquid that forms the liquid column (11). The length of the liquid column is varied by sliding a piston (5). The resonance container (6) is bounded by a corrosion-resistant, high-strength covering disk (7) of minimal thickness and is connected to an equalizing container (9) which receives the liquid displaced by the piston from the resonance container and returns the liquid to the resonance container.

A resonance oscillator of this type is already known from FR-A-374 934. The known resonance oscillator is designed for operations in sea water. As the resonant chamber, it has a cylindrical body which is open on one end and is connected with the surrounding region via openings formed in its holder. The resonant chamber is not filled with a sealed-off liquid volume. Rather, it is filled with the same liquid that is to be sounded. Further, this prior art reference discloses as an acoustic pick-up a cylindrical part attached inside onto the ship's wall, the base thereof, via an outside thread provided at the base, being screwable to an inside thread of the cylindrical pick-up. Also in this case, the resonant chamber is connected with the ambient sea water through an opening in the ship's wall and does not form a sealed-off liquid volume. Thus, in the prior art the density values of sea water and the sound velocity in sea water are effects which have to be accepted from the beginning. Moreover, resonance adaptation takes place only on the side of the receiver while on the side of the transmitter no change in the length of the resonant chamber is provided at all. The application range therefore is restricted.


In one embodiment, the present invention includes noise reduction circuits and methods. In one embodiment, cross coupled switching transistors incorporate bias voltages between the control terminal of each transistor and the drain of the other transistor. The bias voltages increase the voltage on each transistors drain terminal and reduce noise upconversion in the system. In one embodiment, the source voltages of each transistor may be increased to linearize the circuit and further reduce noise. In another embodiment, a current is coupled to a PN junction to generate a low noise bias voltage. The bias voltage is used to bias capacitors of a selectively activated and deactivated capacitance to reduce noise. Features and advantages of the present invention may be implemented in an oscillator circuit, which may be used in a communication system, for example.

The present invention relates to noise reduction, and in particular, to circuits and methods to reduce noise in oscillator circuits.
Noise is a common problem in circuit design. Noise in integrated circuits may be caused by a variety of phenomena and may adversely affect the performance of the circuit or system in which the circuit operates. FIG. 1 is an example of a typical oscillator circuit that is affected by noise. Oscillator circuit 100 includes an inductive load "L" and capacitive load "C" that are driving by a pair of switching transistors 101 and 102. In this example, the switching transistors 101 and 102 are configured as a cross-coupled pair, where a gate of transistor 101 is coupled to the drain of transistor 102, the gate of transistor 102 is coupled to the drain of transistor 101, and the sources are coupled together and to ground. Ideally, oscillator circuit would resonate at the following frequency:ω=1/sqrt(LC).However, noise in the circuit will cause the oscillation frequency to vary from the ideal resonant frequency. Such variations from the ideal resonant frequency may cause deleterious effects on the performance of other system functions.
To understand how noise affects a circuit, such as an oscillator circuit, it is helpful to understand how individual devices in the circuit introduce noise into the system. FIG. 1 further illustrates the noise generated by MOS devices, such as the transistors 101 and 102. Plot 150 shows two noise components. The first noise component is referred to as flicker noise (or 1/f noise). As illustrated in plot 150 at 111, flicker noise decreases with increasing frequency. For example, flicker noise may decrease at a rate of −10 db/decade. The second component of noise is thermal noise, which is illustrated at 112. Thermal noise is regarded as the same across frequencies. As illustrated in plot 150, at some frequency fk the flicker noise 111 may fall below the thermal noise 112.
When devices are combined into a circuit, the noise components are converted into system errors or system noise. For example, plot 160 in FIG. 1 illustrates how the device noise components of from plot 150 are converted into phase noise in oscillator 100. As illustrated in plot 160, flicker noise is converted into a −30 dB/decade phase noise component 113 and the thermal noise is converted into a −20 dB/decade phase noise component 114. The intersection of these two noise components occurs at a frequency of Δfk1, which is sometimes referred to as the noise corner frequency. This phase noise profile expresses the frequency component shifts in the oscillator output signal around the resonant (or center) frequency of the oscillator.
From plot 160, it can be seen that low frequency noise components can cause a significant impact on a circuits performance, including degradation of the frequency stability of an oscillator, for example. Thus, it is desirable to reduce noise in oscillators and other circuits. The present invention solves these and other problems by providing noise reduction circuits and methods.

Bias circuit to reduce flicker noise in tunable LC oscillators