A shift register of the present disclosure includes a plurality of stages. Each stage includes transistors belonging to a first group for activating a Q node, transistors belonging to a second group for discharging odd and even QB nodes, transistors belonging to a third group for being activated by the odd and even QB nodes and for discharging the Q node, and a sensing circuit for sensing a threshold voltage of at least one of the transistor belonging to the third group at a period when the Q node is discharged. The shift register of the present disclosure avoids the problem of erroneous operation due to lowering of device characteristics.

1. Field of the Disclosure
This specification relates to a shift register, and particularly, to a shift register having a sensing circuit for quantitatively measuring a threshold voltage shifted level of a thin film transistor, which is deteriorated due to a continuously applied direct-current (DC) voltage, in a shift register having thin film transistors using oxide silicon as an active layer, and a flat panel display device having the same.
2. Background of the Disclosure
With the development of various portable devices such as mobile phones and notebook computers and information electronic devices such as HDTV for outputting images with high resolutions and high qualities, demands on flat panel display devices applied to those devices are gradually increasing. Examples of the flat panel display device include Liquid Crystal Display (LCD), Plasma Display Panel (PDP), Field Emission Display (FED), Organic Light Emitting Diode (OLED) and the like.
The flat panel display device requires a large substrate, such as glass, and a Thin Film Transistor (TFT), which is to be applied as a display device switching and driving element (component) having an excellent performance without an increase in costs. Among others, an amorphous silicon TFT (a-Si TFT) is a representative element which is widely used as an element which can be uniformly formed on a large substrate over 2 m in size with low costs.
However, with the trend of size-increases of the display device and a high image quality, high-performance elements are also required. Thus, there is a limit to using the conventional a-Si TFT, which exhibits about 0.5 cm2/Vs of mobility, as an element of a large flat panel display device.
Therefore, a high-performance TFT having mobility higher than the a-Si TFT and a fabrication technology therefor are needed. Also, the conventional a-Si TFT involves a problem in reliability, as the worst shortcoming, in that its initial performance is unable to be maintained due to its element characteristic being continuously deteriorated as it operates.
Many studies for overcoming the limit of the a-Si TFT have been continuously conducted, and a representative one is an oxide-silicon TFT.
The oxide-silicon TFT exhibits higher carrier mobility than the a-Si TFT. This may be very advantageous in implementing a driving circuit for controlling switching elements as well as the switching elements within a display panel disposed on the flat panel display device.
FIG. 1A is a schematic view showing a structure of a shift register for a flat panel display device according to the related art, and FIG. 1B is a view showing an equivalent circuit for one stage of the shift register shown in FIG. 1A.
The related art flat panel display device may include a shift register for applying gate output signals sequentially to each horizontal line of pixels on a display panel in order to display an image by sequentially turning on each pixel on the display panel.
As shown in FIG. 1A, a typical shift register includes a plurality of stages 1ST to nST for outputting output voltages Vout to gate lines formed on a display panel (not shown) in synchronization with a clock signal CLK. With the configuration, the first stage 1ST receives a start signal Vst to output a first gate output signal Vout-1 of high level for a first horizontal period 1H, and the second stage 2ST receives the first gate output signal Vout-1 as the start signal Vst to output a second gate output signal Vout-2 of high level. When the nth gate output signal Vout-n is finally output by the nth stage nST, an operation for one frame is completed.
Each of the stages 1ST to nST includes a plurality of transistors. FIG. 1B exemplarily shows one stage of a shift register having 8 transistors. As shown in FIG. 1B, one stage of the shift register includes a first transistor T1 and a sixth transistor T6 diode-connected to each other and turned on in response to a start signal Vst such that the first transistor T1 charges a Q node Q and the sixth transistor T6 discharges a QB node QB, a fifth transistor T5 turned on in response to charging of the Q node Q for discharging the QB node QB, a second transistor T2 for charging the QB node QB with a high potential driving voltage Vdd in response to a reverse clock signal CLKB, a third transistor T3 turned on in response to charging of the QB node QB for discharging the Q node Q, a fourth transistor T4 turned on in response to a reset signal RST for discharging the Q node Q and charging the QB node QB, a seventh transistor T7 electrically connected to one side of the charged Q node Q and turned on in response to the high voltage charged in the Q node Q for outputting a non-reverse clock signal CLK as an output signal Out therethrough, and an eighth transistor T8 turned on by the charged QB node QB for inducing the clock signal CLK outputted through the seventh transistor T7 to be lowered to a low potential.
As the TFT of the thusly configured shift register is implemented with oxide silicon TFTs, it is expected to highly improve performance by virtue of high mobility. However, in view of characteristics of the oxide silicon TFT, initial threshold voltage (int-threshold) characteristics are irregularly observed depending on positions, and the initial threshold voltage may be shifted on some of the TFTs. In particular, the third transistor T3 connected to the QB node QB, to which a high-level DC voltage is continuously applied for most of driving time, may be deteriorated. Accordingly, its device characteristics may change.
Consequently, the voltage level of the Q node Q connected to the third transistor T3 may be varied and thereby the gate output voltage Vout-n may not be regularly outputted due to an erroneous operation.

Shift register and flat panel display device having the same


A process for operating a dry-compression vacuum pump with at least one pump chamber and at least one rotor driven by an electric motor, and to a vacuum pump suitable for this operating process. To reduce operational shutdowns for maintenance purposes without any risk to the pump, it is proposed that application-specific phenomena leading to deviations from the normal operating status or their effects be monitored and, after a predetermined deviation quantity has been attained at which operation of the vacuum pump could be adversely affected in future, steps be taken to remove the causes thereof.

Dry-compression vacuum pumps are pumps which have oil-free pump chambers. The advantage offered by these pumps is that they are capable of generating a vacuum which is free of hydrocarbons. Therefore, they are preferably employed for the evacuation of chambers in which etching, coating or other vacuum treatment or vacuum production processes are run. In particular, Roots pumps or multi-stage claws pumps are well-proven in practice as dry-compression pumps, i.e., dual shaft vacuum pumps having one or several stages. A pair of rotors is located within each stage. The rotating motion with respect to the rotors themselves and with respect to the walls of the pump chamber is such that no contact is established.
When employing dry-compression pumps in connection with the processes mentioned above, or also for evacuation of vacuum chambers in which chemical processes are run, it is often the case that, depending on the type of application, solids or liquids enter the pump. As long as these are only pumped through the pump, they will hardly impair operation of the pump. However, generally these substances are chemically aggressive or at least chemically or physically reactive, so that these may cause abrasions (in the case of liquids, for example) or the formation of layers (in particular, when dust is in involved). In both cases there exists the danger of reduced service life for the vacuum pump. In the presence of aggressive liquids, wear effects are increased. The danger of dust exists in particular when the pumping semiconductor process gases. In this kind of application the circumstances may be such that extremely fine solid particles may be formed during the compression phase of the gases, i.e. when the gases which are to be removed pass through the vacuum pump. Solid particles which enter the vacuum pump either directly or indirectly may deposit themselves in the pump chamber, where they at first only cause a narrowing of the slit between the rotors. Further deposits may cause the rotors to touch, so that the solid particles are rolled on to the surfaces of the rotors. When the deposits increase further, then the layer which is rolled on to the rotors thickens, so that a force is created which forces the rotors and thus the shafts of the rotors apart. In particular, when the rolled on layer increases further, this will damage the bearings and result in a failure of the pump.

Process for operating a dry-compression vacuum pump as well as a suitable vacuum pump for implementation of this process


MOF (metal organic framework)-modified materials and methods of making and methods of using same. The MOFs are covalently bound to the materials. Examples of suitable materials include fibers and thin films. The MOF-modified materials can be made by forming MOFs in situ such that they are covalently bound to the materials. The MOF-modified materials can be used in methods where gases and/or toxic chemicals are absorbed.

Metal-Organic Frameworks (MOFs) and Metal-Organic Polyhedra (MOPs) are a recently-identified class of porous polymeric material composed of highly selective assemblies exhibiting large surface areas and composed of metals linked through organic groups. MOFs are focus of research for a range of applications such as "host" molecules for gases and other molecules. In addition, due to their high porosity MOFs allow the "host" molecules to be captured inside their structure. The trapped molecule can then be part of a selective chemical reaction.
Despite the newness of this field, gas sorption properties of MOFs suggest many practical applications. For example, the application of MOFs-polymer mixed matrix membranes such as polyimides has been demonstrated. The MOFs allowed the polymer to infiltrate the pores of these structures, improving the interface and mechanical properties of the polymer. Also of recent interest has been the utilization of MOF films on stainless steel fibers for solid-phase microextraction of volatile and harmful benzene homologues. MOFs selectively adsorbed methane; therefore mixed matrix membranes from MOFs and poly (3-acetoxyethylthiophene) (PAET). The results showed that when compared to the pure polymer, the mixed matrix membranes exhibited enhanced methane permeability.

Metal organic framework modified materials, methods of making and methods of using same


A drive/control circuit integrated brushless motor is provided that has high rotating precision, satisfactory noise resistance and high output, and is suited to be smaller to save as much space as possible. The motor is a brushless motor provided with circuit integrated core with an FG pattern formed uniformly along the entire circumference by including a pattern system FG, and arranging a Hall element on a surface of a circuit substrate opposite the surface formed with the FG pattern and a noise cancel pattern.

1. Field of the Invention
The invention relates to a brushless motor used as a main motor for simultaneously driving various mechanisms such as a copying machine and a laser beam printer. More particularly, the invention relates to a brushless motor including a stator core (iron core) around which a stator coil is wound, a rotor attached with a ring-shaped magnet, a Hall element for detecting the position of the rotor, and a speed detector for detecting the rotating speed of the rotor, and integrally incorporating a drive/control circuit for rotatably driving and controlling the rotor and a motor.
2. Description of the Related Art
Recently, document products such as a copying machine and a laser beam printer are oriented to have high image quality, high-speed printing and coloring, and to simultaneously realize such, tend to use a so-called tandem system that includes a photosensitive drum for each color. The conventional configuration including one drum now is a configuration including two drums or four drums, and thus the apparatus unavoidably becomes larger. To suppress such enlargement, however, the main motor for driving various mechanisms is required to be thinner, smaller, to save as much space as possible, and to have high output.
The brushless motor integrally incorporating a motor section including a stator equipped with a stator core (iron core) suitable for high output, and a drive/control circuit for rotatably driving and controlling the motor is generally used as the main motor, and the entire motor including the circuit section is required to be thinner, smaller, to save as much space as possible, and to have high output.
To this end, the outside dimension of the stator part of the motor section and the circuit section is desirably made as close as possible to the dimension of a square circumscribing the rotor part, and similarly, the height dimension is desirably made as close as possible to the height dimension of the rotor part.
Conventionally, the well-known brushless motor including the stator core (iron core) includes a rotor in which a ring-shaped magnet having a plurality of magnetic poles facing the stator core (iron core) is provided on the inner peripheral surface of the rotor yoke and a stator assembly in which the stator coil (armature coil) is wound around each stator core (iron core). The stator assembly is attached to a circuit substrate (stator base) equipped with a Hall element (position detecting element) and a drive circuit for rotatably driving the rotor by way of a housing (bearing holder). The rotating position of the rotor is detected by detecting the magnetic pole of the magnet of the rotor with the Hall element (position detecting element), and from the drive circuit to where the output signal of the Hall element is input, the drive current controlled in accordance with the output signal of the Hall element (position detecting element) is supplied to the stator coil (armature coil). The stator coil (armature coil) then generates a magnetic field corresponding to the rotating position of the rotor. The rotor is configured (hereinafter referred to as a first conventional art) so that a continuous rotating force is generated by the interaction of the magnetic field generated by the stator coil (armature coil) and the magnetic pole of the magnet (refer to e.g., JP-A 8-88964 (1996).).
FIG. 6 shows a configuration of a conventional brushless motor.
In FIG. 6, reference character 1 refers to a shaft, reference character 2 refers to a rotor yoke, reference character 3 refers to a magnet, reference character 4 refers to a stator coil (armature coil), reference character 5 refers to a stator core (iron core), reference character 6 refers to a Hall element (position detecting element), reference character 7 refers to a drive circuit, reference character 8 refers to a circuit substrate (stator base), reference character 9 refers to a bearing, and reference character 10 refers to a housing (bearing holder).
In the conventional brushless motor, the Hall element 6 is arranged at a position where the magnetic flux of the magnet 3 of the rotor is easily picked up, that is, on the inner diameter side of the magnet 3 on the surface side facing the magnet 3 of the circuit substrate (stator base) 8 to obtain the output necessary for position detection from the Hall element (position detecting element) 6. When arranged at such position, however, the Hall element (position detecting element) 6 is also arranged close to the stator coil (armature coil) 4, and thus the magnetic field generated by the excitation of the stator coil (armature coil) 4 influences the Hall element 6 as a noise, and a stable position detection may not be performed.
As high output is required, particularly, in the brushless motor used as a so-called main motor for simultaneously driving various mechanisms such as a copying machine and a laser beam printer, a large amount of current must flow to the stator coil (armature coil) 4. If the drive current is increased, however, the magnetic field generated at the stator coil (armature coil) 4 becomes large, which generated magnetic field influences the Hall element 6, thereby making a stable position detection difficult.
As shown in FIG. 7, a solution for the above problem includes a technique (hereinafter referred to as a second conventional art) for preventing the magnetic field generated by the excitation of the stator coil (winding wire) 4 from influencing the Hall element (detecting element) as noise with a configuration in which one portion of the magnet 3 arranged in the rotor yoke 2 is exposed from the rotor yoke 2, the Hall element (detecting element) 6 is arranged exterior to the magnet 3 in correspondence to the exposed portion of the magnet 3, and the leakage flux of the exposed portion of the magnet is detected (refer to e.g., JP-A 8-172763 (1996)).
Further, a solution different from the second conventional art includes a technique (hereinafter referred to as a third conventional art) in which the magnetic field generated by the excitation of the stator coil (driving coil) 4 is assumed to influence the output waveform of the Hall element (position detecting element) 6 thus producing deformation at a zero cross point of the output waveform, the deformation being produced in a direction that delays the current feed switching timing toward the stator coil (driving coil) 4, and as shown in FIGS. 8 and 9, a driving magnet 3a and a position detecting magnet 3b are arranged as the magnet (driving magnet) 3 of the rotor in such a way that the boundaries where the magnetic poles are opposite poles with respect to each other contact, thereby eliminating the delay of current feed switching by inversing the output of the Hall element (position detecting element) 6 so that the deformation of the output waveform is produced in a direction that accelerates the current feed switching toward the stator coil (armature coil) 4 (refer to e.g., JP-A 7-327351 (1995)).
More specifically, as shown in FIG. 9, the driving magnet 3a and the position detecting magnet 3b are arranged on the magnet (driving magnet) 3 of the rotor in such a way that the boundaries where the magnetic poles are opposite poles with respect to each other contact. Further, the Hall element (position detecting element) 6 is arranged on the circuit substrate (substrate) 8 at a position facing both the position detecting magnet 3b and the stator core 5 with which the stator coil (driving coil) 4 is wound. The planar arrangement of the Hall element 6 is configured as shown in FIG. 10, where the Hall element (detecting element) 6U of U phase, the Hall element (detecting element) 6V of V phase, and the Hall element (detecting element) 6W of W phase are arranged in correspondence to the each teeth of the U phase, the V phase and the W phase of the stator core (iron core) 5. The arrow indicates the direction of rotation.
According to this configuration, the composite magnetic field of the magnetic field generated by the excitation of the stator coil (driving coil) 4 and the magnetic field of the position detecting magnet 3b is detected by the Hall element (position detecting element) 6, thereby eliminating the delay of current feed switching toward the stator coil (driving coil) 4.
FIGS. 11A to 11G (FIGS. 9A to 9G of JP-A 7-327351 (1995)) shows that the magnetic field of the U phase and the W phase generated by the excitation of the stator coil (winding wire) 4 influences the output waveform of the Hall element (detecting element) 6U of the U phase, thus producing deformation at the zero cross point of the output waveform. The deformation is produced in a direction that delays the current feed switching timing toward the stator coil (driving coil) 4. FIG. 11A is the generated magnetic field of the driving magnet toward the Hall element (detecting element) 6U, FIG. 11B is the generated magnetic fields of the U and W phase cores, FIG. 11C is the generated magnetic field of the U and W phase cores toward the Hall element (detecting element) 6U, FIG. 11D is the generated magnetic field of the composite cores of U and W phases toward the Hall element (detecting element) 6U, FIG. 11E is the output waveform of the Hall element (detecting element) 6U, FIG. 11F is an enlarged view of the horizontal axis of the main part of FIG. 11E, and FIG. 11G is the generated magnetic field of the actual W phase core.
FIGS. 12A to 12E (FIGS. 3A to 3E of JP-A 7-327351 (1995)) show that the output of the Hall element (position detecting element) is inversed and the deformation of the output waveform is produced in a direction that accelerates the current feed switching toward the stator coil (driving coil). FIGS. 12A and 12B show the magnetic field toward the Hall element (detecting element) 6U and the magnetic field toward the core, FIG. 12C shows an output waveform of the Hall element (detecting element) 6U, FIG. 12D shows an enlarged view of the horizontal axis of the main part of FIG. 12C, and FIG. 12E shows an enlarged view of the generated magnetic field of the W phase core.
In the brushless motor used as the main motor for simultaneously driving various mechanisms such as a copying machine and a laser beam printer, not only the rotating speed of the motor, but the rotating phase in relation with the various mechanism sections of the apparatus driven by way of an output shaft and a decelerating mechanism attached to the output shaft must also be accurately controlled. Thus, the brushless motor requires a speed detector having a certain degree of resolution.
The speed detector of the brushless motor suited for the above application includes a so-called pattern FG system. The ring-shaped FG magnet subjected to NS multi-pole magnetization along the circumferential direction is arranged on the rotor side, the FG pattern including the generator wire elements of the same number as the magnetized poles of the FG magnet connected in series along the circumferential direction is arranged on the stator side, and the speed detecting signal (FG signal) of the frequency proportional to the rotating number of the motor produced in the FG pattern by the rotation of the motor is obtained. When incorporating the speed detector of the FG pattern system in the brushless motor, a configuration in which the driving magnet of the motor and the FG magnet are integrated by performing magnetization for the driving magnet on the inner peripheral side of the rotor magnet and NS multi-pole magnetization for the FG magnet (hereinafter referred to as FG magnetization) on the end face side, and the FG pattern is formed on the circuit substrate of the motor is desirable as a configuration with no influence on the shape of the motor and no additional component.
However, in either of the second conventional art and the third conventional art, an adverse effect arises due to performing FG magnetization on the end face on the circuit substrate (substrate) side of the magnet (driving magnet) of the rotor.
That is, the Hall element (position detecting element) must be arranged in the vicinity of the end face on the circuit substrate (substrate) side of the magnet (driving magnet) of the rotor, and thus the influence of FG magnetization formed on the end face of the magnet (driving magnet) of the rotor cannot be avoided, and a stable position detection becomes difficult.
In the second conventional art, the influence of FG magnetization can be prevented by spacing the Hall element (position detecting element) away from the magnet (driving magnet) of the rotor to an extent the influence of FG magnetization can be neglected with the dimension of one portion of the magnet of the rotor exposed from the rotor yoke being sufficiently large to an extent the influence of the FG magnetization can be neglected, but when the exposed portion of the driving magnet is large, the leakage flux increases thus increasing loss or unnecessary magnetic noise. Alternatively, the influence of FG magnetization can be prevented by attaching the Hall element (position detecting element) so as to float from the surface of the circuit substrate (substrate) by a certain extent, but this may increase the attachment cost and the like of the Hall element (position detecting element).
The third conventional art acts counter to the technically necessary configuration, and thus the FG magnetization becomes impossible to be performed on the end face of the circuit substrate (substrate) side of the magnet (driving magnet) of the rotor.
As shown in FIG. 13, as a solution for the above conventional problem in the brushless motor used as a so-called main motor for simultaneously driving various mechanisms such as a copying machine and a laser beam printer, a technique (hereinafter referred to as fourth conventional art) for preventing the influence on the Hall element (position detecting element) as noise with a configuration in which the rotor magnet 3 is extended toward the circuit substrate (print substrate) 8 side, and the Hall element (position detecting element) 6 is arranged on the circuit substrate (print substrate) 8 so that the direction of magnetic sensitivity is in the radial direction at a position facing the extended portion to greatly reduce the components in the radial direction of the magnetic field (leakage flux) generated by the excitation of the stator coil 4 at the position of the Hall element (position detecting element) 6, is adopted (refer to e.g., JP-U 57-113681 (1982)).
In the fourth conventional art, the rotor magnet 3 is extended toward the circuit substrate (print substrate) 8 side, and thus the gap between the end face of the rotor magnet 3 and the circuit substrate (print substrate) 8 can be reduced. Therefore, by performing FG magnetization on the end face on the circuit substrate (print substrate) 8 side of the rotor magnet 3 and forming the FG pattern on the circuit substrate (print substrate), the magnetic flux from the FG magnet that interlinks with the FG pattern becomes large. That is, the configuration is suitable for incorporating the speed detector of FG pattern system. Further, with regard to the influence of the magnetic field generated by the FG magnet of the rotor magnet (driving magnet) 3, the stable position detection becomes possible since the component in the radial direction at the position of the Hall element (position detecting element) 6 is small.
The brushless motor adopting the fourth conventional art and integrally incorporating the drive/control circuit for rotatably driving and controlling the rotor with the motor is shown in for example, FIG. 14. A configuration (hereinafter referred to as fifth conventional art) for fixing, in addition to the rotor magnet (driving magnet) 3, the FG magnet (speed detecting magnet) 11 on the end face on the side of the circuit substrate 8 of the rotor magnet (driving magnet) 3, or on the upper end face of the driving magnet 3 herein, is proposed (refer to e.g., JP-U 7-9078 (1995)). Reference character 12 is the FG pattern (speed detecting flat coil) and is formed on the lower surface of the circuit substrate 8. The drive/control circuit for rotatably driving and controlling the rotor of a control integrated circuit 13 and the like is mounted on the upper surface of the circuit substrate 8. The speed detecting magnet 11 is a ring-shaped magnet and the N, S magnetic poles of the same number as the number of turns of the FG pattern (speed detecting flat coil) 12 are magnetized alternately along the circumferential direction on the upper end face of the speed detecting magnet 11. The FG pattern (speed detecting flat coil) 12 faces the upper end face of the speed detecting magnet 11. When the speed detecting magnet 11 rotates integral with the rotor yoke 2, the FG pattern (speed detecting flat coil) 12 is induced to the speed detecting magnet 11 to output the speed detecting signal or a signal having a frequency corresponding to the rotating speed of the rotor yoke 2. A space 14 is provided between the control integrated circuit 13 and the upper surface of the circuit substrate 8, and electronic chip components 15 are arranged in the space 14.
The Hall element 6 is arranged at the bottom surface side of the circuit substrate 8, and a plurality of them are arranged at a position close to the FG pattern (speed detecting flat coil) 12. Reference character 16 is a motor attachment plate having an area substantially covering the entire upper surface of the motor, and is arranged near the circuit substrate 8 so that the bottom surface contacts the upper surface of the control integrated circuit 13.
The control integrated circuit 13, the electronic chip components 15 and the like are arranged on the upper surface of the circuit substrate 8, as mentioned above. On the lower surface of the circuit substrate 8, the FG pattern (speed detecting flat coil) 12, a circuit pattern and the like is printed, and the Hall element 6 and the like is arranged, as mentioned above. An outer lead 17 of the control integrated circuit 13 is projected out toward the lower surface of the circuit substrate 8.
In the configuration of the fifth conventional art, although the chip components 15 are mounted between the control integrated circuit 13 and the circuit substrate 8 to reduce the outer diameter of the motor (circuit substrate), a gap must be formed between the control integrated circuit 13 and the chip components 15 and thus the motor is prevented from being thin.
The speed detector of FG pattern system has the FG pattern (speed detecting flat coil) 12 arranged so as to surround the vicinity of the stator core 5, and thus the noise generated from the stator coil 4 is easily picked up. Thus, a so-called cancel pattern for canceling the components produced by such noise must be arranged in parallel with the outer peripheral side or the inner peripheral side of the FG pattern (speed detecting flat coil) 12.
Particularly, as the PWM driving method is generally adopted to enhance the power supply efficiency of the motor in the above mentioned main motor, the noise level generated from the stator coil 4 becomes very large. Further, in the conventional brushless motor for the main motor, the driving method of supplying the drive current that generates the magnetic field, which has the waveform of FIG. 11B (FIG. 9B of JP-A 7-327351 (1995)) showing the third conventional art, from the stator core to the stator coil (winding wire) 4 is adopted, and thus a rapid magnetic field change occurs and becomes the cause of influence on the FG pattern. The cancel pattern for the noise is thus essential.
Generally, the speed detector of FG pattern system reduces the influence of run-out and the like of the rotor part (FG magnet) during rotation or eccentricity of the FG magnet of the rotor part, and thus the length in the radial direction of the generator wire elements of the FG pattern must be longer than the length in the radial direction of the FG magnet.
When reducing the outer diameter of the motor while satisfying the above essential conditions, in the configuration of the fifth conventional art, the Hall element 6 is arranged on the same side as the FG pattern 12 of the circuit substrate 8, and in order to secure the length of the generator wire elements of the FG pattern with the inner peripheral diameter of the FG pattern 12 or the inner peripheral diameter of the cancel pattern being a diameter sufficiently smaller than the inner peripheral diameter of the FG magnet 11, the installing position of the Hall element 6 must be moved toward the shaft center of the motor. The distance between the rotor magnet 3 and the Hall element 6 thus increases and a sufficient position detection signal is not obtained. In order to reduce the distance between the rotor magnet 3 and the Hall element 6, the FG pattern 12 and the cancel pattern 18 around the Hall element 6 must have a configuration so as to narrow the width, as shown in FIG. 15, or to circumvent toward the outer side of the shaft center of the motor. In this case, the length of the generator wire elements becomes uneven, and worsens the speed detecting precision.

Brushless motor with speed detector having noise cancel pattern

Matsushita Electric Industrial Co., Ltd.


An optical measuring system for fitting spectacles to a subject and/or for diagnosing and/or monitoring ocular diseases and/or disorder in the subject, and methods of use thereof. The system includes at least one image capturing device for capturing at least one image of at least part of the face of the subject. The system also includes at least one movable mount for mounting the image capturing device in front of the subject and moving the image capturing device relative to the subject; and at least one processor operatively connected to the image capturing device for generating a three dimensional (3D) model of the at least part of the face of the subject. The at least one processor is also configured to determine, from the 3D model generated, one or more optical measurements of the subject.

The process of fitting spectacles to an individual involves more than selection of a spectacle frame and suitable prescription lenses. To correctly fit spectacles, the spectacles must be tailored to fit the particular individual's unique physical characteristics, including head shape and size.
Measurements, such as, e.g., horizontal pupil distance, vertical pupil height, nose width, temple length and head width, must be taken, so that when the prescription lenses are edged to fit the spectacle frame the optical centres of the left and right prescription lenses at least align with the pupil positions of the individual.
Such measurements are sometimes crudely taken by hand with an optometrist or optician using a hand-held ruler or hand-drawn scale with hand-placed ink dots to take the measurements on the selected spectacle frame.
Typically, however, the measurements are taken using sophisticated mechanical devices, such as, e.g., a pupilometer or a digital centration device, in order to fashion correctly fitting spectacle frames. Such sophisticated mechanical devices, however, typically, require comprehensive training, and, in some cases, the employment of trained professionals, all at considerable expense.
Alternatively, an optometrist or optician may place a spectacle frame measuring device on the individual to take the measurements.
However, the inherent problem with taking measurements by hand or using such devices as described above is the potential for error in the measurements taken. Specifically, potential errors in crude hand-derived measurements, use of the devices, and/or in correlating the measurements taken using those devices to the spectacle frame selected by the individual.
Another problem with the above described practices and/or devices, is that they are typically incapable of determining more complex measurements, such as, e.g., the centre of rotation of each eye, which is becoming increasingly more important in the lens design process.

Optical measuring and scanning system and methods of use


A method and apparatus for processing order control, in which a load of an examination work to review a processing order of lots is reduced and all the lot flows are conditioned so as to move at an almost constant speed with the result that not only can accuracy in scheduling of delivery and so on be improved but degradation of the lot flows is also prevented from occurring in advance. A proper number R of in-process lots and others are obtained and lots are stacked before each of apparatuses so as to be equal in number to the proper number R of in-process lots, thereby a target of the number Cg of processing processes can be achieved. Since proper numbers of in-process lots in cases where a method in which a plurality of lots are simultaneously processed is employed and where a substitute processing method is employed can be obtained, some of the lots can be transferred to other fabrication apparatuses if the number of lots accumulated before an fabrication apparatus exceeds the proper number R of in-process lots. Furthermore, a previous process of a fabrication apparatus can process lots confirming a signal color at the next process thereof since signals each displaying a color corresponding to in-process levels of lots residing in the lot buffer can be provided to the respective fabrication apparatuses.

1. Field of the Invention
The present invention relates a method and apparatus for processing order control, and particularly to a method and apparatus by which optimization is achieved of a physical flow of lots each configured by a group of wafers in a semiconductor fabrication line.
2. Description of Related Art
First, descriptions will be given of constituents associated with a physical flow of lots (hereinafter referred to as a lot flow) and of workings of the constituents using FIG. 32, which is a schematic illustration of a semiconductor fabrication line. Following this, descriptions will be given of constituents of a production control system, which is an apparatus to control a lot flow, and of workings of the constituents using FIGS. 33 and 34. Finally, description will be given of a flow chart of a control method for a lot flow using FIG. 35.
FIG. 32 shows a schematic illustration of a semiconductor fabrication line. In FIG. 32, a symbol 100 denotes a server computer of a production control system (hereinafter referred to as a server). The server means to receive a request and an instruction from a client computer (hereinafter referred to as a client) and basically to transmit neither a request nor an instruction to a client. A symbol 20 denotes communication cables connecting between the constituents, and symbols 30a to 30e client computers (hereinafter referred to as PCs; a digit or a letter 1, i, l, k and l following the abbreviation PC denote serial numbers). Symbols 40, 40a to 40d denote fabrication apparatuses for a semiconductor device, an inspection instrument or the like. For example, Stepper, CMP (Chemical Mechanical Polishing), CVD (Chemical Vapor Deposition) or Etcher are names directly showing features of semiconductor fabrication methods, respectively, which are adopted as names of a fabrication apparatus or an inspection instrument each without any modification. While there are available various other fabrication apparatuses, typical kinds among them are selected herein. Stepper m means the mth one among a plurality of steppers. This also applies to cases of CPMn, CVD0 and Etcher p. Symbols 50, 50a and 50b denote a lot A or/and a lot B, respectively, each of which lots includes a plurality of silicon wafers that serve as substrates of semiconductor products. The lot A (50a) and lot B (50b) denote that those are lots to which respective different fabrication methods are applied. In a case where the lots are subjected to the same fabrication method, those are different in fabrication position in the fabrication line in which fabrication methods are applied. A symbol 46 denotes a transport route running along the fabrication methods; a symbol 60 an operator carrying out transportation of a lot 50 or the like in the semiconductor fabrication line; 70 a carrier for a lot 50, serving mainly for transportation over a short distance; and 80 an inter-bay transport system, serving mainly for transportation over a long distance. The term xe2x80x9cbayxe2x80x9d used here means a region where apparatuses 40a of the same kind form a group and for example, a bay is used in a way of expression such as a bay in which steppers reside.
Then, a flow of the lot A (50a) will be described. The operator 60 or the lot carrier 70 transports the lot A (50a) to Stepper m (40a) and sets the lot A (50a) at a processing position. After processing conditions are input to Stepper m (40a) and the processing is completed, the operator 60 or the lot carrier 70 transfers the lot A (50a) to the inter-bay transport system 80. The inter-bay transport system 80 transports the lot A (50a) to the bay of Etcher p (40d). The operator 60 or the lot carrier 70 receives the lot A (50a) from the inter-bay transport system 80 and transports the lot A (50a) to Etcher p (40d) to set the lot A (50a) at a processing position. Thereafter, description is omitted since that of Stepper m is duplicated. Such processings and transportations are repeated till completion of all the fabrication process of the lot A (50a). Description of a case of the lot B (50b ) is also omitted since description is repeated in the same way except for a transport pattern.
FIG. 33 shows internal constitution of the production management system of production control system (server) 100, the client 30 and others of FIG. 32. In FIG. 33, a symbol 110 denotes a data base in the server 100 and the interior is configured in the following way: A symbol 120 or 130 stores process flow data of respective lots 50 therein. The term xe2x80x9cprocess flowxe2x80x9d means data in which fabrication orders and processing conditions are defined and which includes the entire information and a plurality of process step groups. The entire information includes information on all of the lots 50 such as lot numbers. Other information such as product kind codes and delivery times is further included in the entire information, but details of the other information are omitted. A given process has a serial number showing a place in the order of processes, the name of an apparatus 40 or the like in which a processing is carried out and progress states of a process showing processing-completed, in-process or not-processed, respectively, wherein the term xe2x80x9cin-processxe2x80x9d means a state in which a work awaits its turn. In addition, the process has processing conditions, specified date and time for start or end of the process and so on, but the details are omitted. There are a plurality of process flow files: for example, a process flow file 120 used for the lot A and a process flow file 130 used for the lot B.
Symbols 140 and 150 denote in-process work management files in which data for in-process management for apparatuses 40 and so on is stored and the data for the in-process work management files include a plurality of lot numbers in process of the apparatuses 40 and the numbers of the lots in process thereof. Since the apparatuses 40 are present in plural number, for example, the in-process management files 140 and 150 are used for Etchers p and CVDo, respectively.
Symbols 160 and 170 denote processing history files in which data of processing histories of the lots 50 in the respective apparatuses 40 is stored and a data of one record is input in the file each time a lot 50 is processed in one of the apparatuses 40. Items of a record include: specified dates and times (while there is also a specified date and time for start or end of a processing, only the date and time for end of a processing is shown for each lot in FIG. 32); lot numbers; times (durations from start to end of processing) and others. Although the items of a record further include processing conditions and information on a person in charge of processing and so on, details of the items are omitted. Since the apparatuses 40 or the like are present in plural number, for example, the processing history files 160 and 170 are used for Etcher p and CVDo, respectively.
A symbol 180 denotes a computation section performing input/output processings of data with the data base 110 or processing/computation of data in the server 100, a symbol 190 denotes a communication section, 30e1 a communication section in PC1 (30d), and 30e2 a computation section performing processing/computation of data in PC1 (30d). The communication sections 190 and 30e2 both control transmission/reception of data between the computation sections 180 and 30e2. A symbol 30e3 is a display section in PC1 (30d) and displays a data processed/computed in the computation section 30e2. The data to be displayed includes set-up information for Etcher p in a file 30e31, a special command in a file 30e32 or the like, both to be described later. The set-up information of Etcher p 30e31 includes lot numbers, priority numbers each to determine the processing order, the number of wafers and so on. Although the set-up information further includes processing conditions, specified dates and times for in-process works and so on, details of the information are omitted. The special command file 30e32 includes names of the apparatuses 40 and ways of lot flow in which processing of the lot 50 or the like to reach the apparatuses 40 or the like is stopped and the lot 50 or the like is forced to wait its turn at the process where the processing is stopped, and in which the lot 50 or the like is ascended in the order of processing to reach its destination earlier. A symbol 30e4 denotes an input section incorporated in PC1 (30d) which controls inputting of a person in charge when a process gets started or an inspection result.
FIG. 34 describes workings of the production control system 100 shown in FIG. 33 using a flow chart, taking up a case where one process is progressed as an example. The term xe2x80x9cis progressedxe2x80x9d means to complete the processing. As shown in FIG. 34, a data of completion of processing in Etcher p (40d), for example, in the 96th process (123) of the lot A (50a) is first transmitted from the input section 30e4 of PC1 (30d) through the computation section 30e2 of PC1 (30d), communication section 30e1 of PC1 (30d) and the communication section 190 of the server 100 to the computation section 180 of the server 100 (step S100). The computation section 190 of the server 100 that has received the data accesses to the data base 110 and changes xe2x80x9cin-processxe2x80x9d of Etcher p (40d) into xe2x80x9cprocessing-completedxe2x80x9d thereof in the 96th process (123) of the process flow file 120 for the lot A (50a) (step S102). The computation section 180 of the server accesses to the data base 110 and deletes the lot A (142) from in-process lot numbers of the in-process management file 140 for Etcher p (40d). The counter 146 for the number of in-process lots is decreased by one from 13 to 12 (step S104). The computation section 180 of the server accesses to the data base 110 and extracts process information from the corresponding process flow file 120 with a lot number of the in-process management file 140 for Etcher p (40d) as key. The extracted data group constitutes the latest information in the set-up information file 30e31 for Etcher p (40d) (step S106). The computation section 30e2 of PC1 (30d) requests transmission of the latest data of set-up information in the set-up information file 30e31 from the computation section 180 of the server 100 (step S108). The computation section 30e2 of PC1 (30d) rearranges the set-up information in the set-up information file 30e31 for Etcher p (40d) which has received from the computation section 180 of the server so as to be in the ascending order of an in-process position greater than a priority order greater than an in-process data and time (step S110). The term xe2x80x9cin-process positionxe2x80x9d means to determine such that a case where a lot is currently in process of one of the apparatuses 40 or the like is a lot xe2x80x980 process earlierxe2x80x99 and a case where a lot is in the previous first process of the one of the apparatuses 40 or the like is a lot xe2x80x981 process earlier.xe2x80x99 The term xe2x80x9cascending orderxe2x80x9d means to sort lots based on in-process positions so as to be in the order of xe2x80x980 process earlier,xe2x80x99 xe2x80x981 process earlierxe2x80x99 and xe2x80x982 process earlierxe2x80x99 starting with the xe2x80x980 process earlierxe2x80x99 with increase in in-process position. With the above procedure, the in-process position of lot A (50a) moves from Etcher p (40d) in the 96th process (123) to the CVDo in the 97th process (124). Then, a similar procedure is performed on the CVDo (40c) in program flow from step S112 to step S120.
The computation section 190 of the server 100 changes xe2x80x9cnot-processedxe2x80x9d of the CVDo in the next process (124) of the process flow file 120 for the lot A (50a)to xe2x80x9cin-processxe2x80x9d thereof (step S112). The computation section 180 of the server accesses the data base 110 and adds the lot A (142) into in-process lot numbers in the in-process management file 150 for CVDo (40e). The counter 156 for the number of in-process lots is incremented by 1 from 3 to 4 (step S114). The computation section 180 of the server accesses the data base and extracts process information from the corresponding process flow file 130 with a lot number in the in-process management file 150 for CDVo as key. The extracted data group is the latest set-up information for CVDo (40e) (step S116). The computation section 30e2 of the PCk (30c) requests transmission of the latest data of set-up information for CVDo (40e) from the computation section 180 of the server 100 (step S118). The computation section of the PCk (30c) rearranges the set-up information file 30e31 for CVDo (40e) which has received from the computation section 180 of the server so as to be in the ascending order of an in-process position greater than a priority order greater than an in-process date and time (step S120).
Description will be made of an optimization method for a lot flow in in-process management of the lot 50 or the like as described above using FIG. 35. FIG. 35 shows a flow chart for a conventional lot flow control computation. As shown in FIG. 35, the flow chart is divided into three regions in a broad sense: a target determination region for a first one (step S200), a judgment region for a second one (steps S202, S204 and S206) and a lot flow instruction region for a third one (steps S208, S210, S212 and S214). First, as shown by a graph in the target determination region (step S200), a target value for the number of processing lots per day of the apparatus 50 or the like is obtained. To be more detailed, movement of the number of processing lots per each day through one month in the apparatus 50 or the like is recorded. For example, the movement of the number of processing lots per each day can be obtained by extracting data from the processing history file 160 for Etcher p (40d). The numbers of processed lots per day included in the upper 5 places are selected from the list obtained by sorting data of the movement of the numbers of processing lots per day in the ascending order of the number of processing lots, and the average of the 5 numbers is obtained and adopted as the target value, which is updated once per month.
The judgment region includes three judgment conditions (steps S202, S204 and S206). First, it is judged whether of not the number of processing lots on the previous day (track record) exceeds the target value (step S202). If the track record is judged to exceed the target value, program flow goes to step S204, while if judged not to exceed, program flow goes to step S206. At step S204, it is judged whether or not the number of in-process lots is less than the number m of lots in excessive supply, which is arbitrarily set. If the number of in-process lots is judged to be less than the number m of lots in excessive supply, program flow goes to step S208, while judged not to be less than the number m, program flow goes to step S210. On the other hand, at step S206, it is judged whether or not the number of in-process lots is less than the number n of lots in short supply, which is arbitrarily set. If the number of in-process lots is judged to be less than the number n of lots in short supply, program flow goes to step S212, while if judged not to be less the number n, program flow goes to step S214.
The lot flow instruction region includes four kinds of instructions (steps S208, S210, S212 and S214). At step S206, there is shown the order of lot processing in a case where there is no special problem in a lot flow. To be concrete, lots are sorted so as to be in the ascending order of an in-process position greater than a priority order greater than an in-process date and time and processing is performed from the lot 50 or the like in the top place in the order. What is to be considered in connection with the in-process date and time is that a method of first-in first-out (FIFO) is adopted. At step S210, a special instruction is issued to stop the lot 50 or the like which would otherwise flow into one of the apparatuses 40 in a later process since in-process lots are in excessive supply for the one of the apparatuses 40 in the later process. At step S212, the situation is reverse from step S210 and a special instruction is issued to force the lot 50 or the like to flow quickly since in-process lots are in short supply. At step S214, a special instruction is issued to investigate a cause for delay in lot processing and restore the current lot processing state to normal, since the lot processing has been delayed for the cause.
A conventional lot flow control method has had two problems since the method has a configuration as described above. The special instructions (at steps S210 and S212) are issued to all of PC30 and others and PC 30 and others reexamine the processing order of the lot 50 or the like according to the special instructions (at steps S210 and S212). The term xe2x80x9creexaminexe2x80x9d means that after investigating the subsequent processes (for example, 5 processes) of the lot 50 and others, if there is an apparatus 40 or the like corresponding to any of the special instructions (at steps S210 and S212), a place of the lot 50 or the like in the processing order is changed. Since there were no clear rules in the reexamination procedure in the prior art and in addition, such a procedure was conducted by a human hand, there was a problem that the reexamination work was a considerably heavy load. Furthermore, in a case where the special instructions (at steps S210 and S212) are issued, a problem has still been left unsolved since there arises a state where a lot 50 or the like is quickly processed, but another lot 50 stops in sudden, and therefore, all of the lot flow gets into a situation like a behavior of an aircraft in an air turbulence, making a delivery schedule or the like very hard to plan and carry out.
As an example of a lot flow control, a method is available, in which, as disclosed in Japanese Patent Laid-Open No. Hei 3-290703, part of lots already in process on an apparatus is redistributed on another apparatus or over other apparatuses in proportion to processing capacities of apparatuses to improve an efficiency of the lot flow. The above described methods are effective to relieve an already degraded lot flow state like a traffic congestion where as a result of concentration of lots onto a specific apparatus, a long time is required for each lot to pass through the apparatus. However, a problem has still remained since the methods are not effective for a preliminarily preventive measure for degradation of lot flow.
It is accordingly an objective of the present invention, which has been made in order to solve the above described problems, is to provide a method and apparatus for processing order control by which a load of an examination work as shown in each of the instructions (at steps S210 and S212) is reduced in which the processing order of the lots 50 is reviewed based on processing capacities of the apparatuses 40 or the like and each of the numbers of in-process lots 50 or the like.
It is another objective of the present invention to provide a method and apparatus for processing order control by which all of the lot flow is rectified to a state in which lots do not move as if an aircraft is in an air turbulence but move at an almost constant rate like a steady flow to increase an accuracy in scheduling deliveries and so on.
It is still another objective of the present invention to provide a method and apparatus for processing order control by which degradation of a lot flow can be prevented in advance.
According to a first aspect of the present invention, there is provided a processing order control method for controlling an order in processing that processing objects receive from a processing apparatus, respectively, comprising the steps of a processing waiting time computing of obtaining a processing waiting time per process by dividing a total processing waiting time during which a processing object is placed in a processing waiting state where the processing object awaits processings given by the processing apparatuses in a predetermined time, by the number of processing processes that the processing object receives in the predetermined time; an average processing time computing of obtaining an average processing time per process per processing object for a processing apparatus by dividing a total processing time spent for processings that the processing objects receive from the processing apparatus, by the number of processing processes and by the number of processing objects; a number of waiting processing objects computing of obtaining a proper number of waiting processing objects that receive processings in a processing apparatus by dividing the processing waiting time per process obtained by the step of the processing waiting time computing, by the average processing time per process per processing object for the processing apparatus obtained by the step of the average processing time computing; and a control of conducting control to equalize an actual number of processing waiting objects that receive processings in a processing apparatus with a proper number of waiting processing objects obtained by the step of the number of waiting processing objects computing which processing objects receive processings in the processing apparatus.
According to a second aspect of the present invention, there is provided a processing order control apparatus having processing objects and a processing apparatus that process the processing objects, comprising: processing waiting time computing means for obtaining a processing waiting time per process by dividing a total processing waiting time during which a processing object is placed in a processing waiting state where the processing object awaits processings given by the processing apparatuses in a predetermined time, by the number of processing processes that the processing object receives in the predetermined time; average processing time computing means for obtaining an average processing time per process per processing object for a processing apparatus by dividing a total processing time spent for processings that the processing objects receive from the processing apparatus, by the number of processing processes and by the number of processing objects; the number of waiting processing objects computing means for obtaining a proper number of waiting processing objects that receive processings in a processing apparatus by dividing the processing waiting time per process obtained by the processing waiting time computing means, by the average processing time per process per processing object for the processing apparatus obtained by the average processing time computing means; and control means for conducting control to equalize an actual number of processing waiting objects that receive processings in a processing apparatus with a proper number of waiting processing objects obtained by the number of waiting processing objects computing means which processing objects receive processings in the processing apparatus.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.

Method and apparatus for processing order control


A container for storing and transporting articles, such as leadframes. The container includes a base with a planar wall having an upwardly facing surface defined by a peripheral edge, and at least two upwardly extending, opposite posts secured to the upper surface of the planar wall. The posts are spaced interiorly from the peripheral edge of the upwardly facing surface wherein each post has an outwardly facing surface and an inwardly facing surface that is tapered outwardly from the top of the post to the bottom of the post. The articles are positioned between the inwardly facing surfaces of the posts. A cover is releasably securable to the planar wall of the base. The cover includes a top wall and a peripheral, downwardly extending wall formed to the outer periphery of the top wall. The peripheral wall is positioned adjacent the peripheral edge of the upwardly facing surface of the base and outwardly with respect to the posts of the base when securing the cover to the base.

This invention relates generally to containers for storing and transporting articles, and more particularly to a container which is capable of receiving a plurality of leadframes therein.
Oftentimes fragile articles, such as leadframes, requiring to be stored and/or transported are placed in bulky packaging which is designed to protect the articles. Although many of these packages are effective in maintaining the articles in a safe condition, they are difficult to handle due to their awkward size and shape, and are difficult to open. For leadframes, the packages are usually box-shaped, and sized for accommodating the leadframes securely therein.
One problem associated with such leadframe packages is that since they are fabricated from injection molded plastic, a new package design must be created for leadframes having varying shapes and sizes. Thus, for example, a leadframe having dimensions in plan view of two by nine inches would require a different and separate package than a leadframe that is three by nine inches. There is presently a need in the container art for a single container which can be easily manipulated so as to accommodate varying leadframe sizes.

Container for storing and transporting leadframes


A self-reinforced masonry block comprises a main body having opposed substantially parallel stacking surfaces and at least one tubular cell defined therethrough from one stacking surface to the other. At least one confining reinforcement is embedded in the main body to surrounding a corresponding cell. Each confining reinforcement extends substantially entirely along the longitudinal length of its corresponding cell and terminates inwardly of the stacking surfaces. The self-reinforced masonry blocks may be used in construction of a grout-filled, vertically reinforced masonry block wall, with the self-reinforced masonry blocks being used for those portions of the wall where the grouted cells are prone to crushing due to high levels of compressive stress, and conventional unreinforced masonry blocks being used for other portions of the wall. A method for making the self-reinforced masonry blocks is also described.

Common masonry walls are made of hollow concrete blocks and mortar; the hollow portions of the blocks are typically referred to as "cells". The cells reduce the weight of block that the mason must lift into place during construction, and also enable vertical reinforcement to be installed in the wall. For added resistance to lateral loads, grout and vertical reinforcements, such as steel reinforcing bars, are placed in the cells of the block. Filling of the block cells also enhances the compression strength of concrete block walls under vertical loads. Placing vertical steel reinforcing bars in the block cells enhances the flexural strength of the wall to improve ductility through yielding of this reinforcing bar. However, the extent of ductility is limited by compression failure of the concrete block at relatively low compression strain.
In seismic design for earthquake loading, concrete block shear walls that are intended to resist the horizontal forces caused by seismic motion must be reinforced to increase their flexural strength and to develop some ductility and energy dissipation properties. However, it is very challenging to achieve sufficient ductility and energy dissipation prior to compression failure of the concrete block. Reinforced concrete block construction must often be designed for nearly twice as much lateral loading as the more ductile competing construction materials such as reinforced concrete structures and steel structures. Hence, reinforced concrete block construction is often not economically competitive and sometimes not technically feasible. Changes in recent building codes have imposed limitations affecting reinforced masonry construction with the result that use of this most common building material has been significantly limited.
Another aspect of structural design relates to the limit states with which building design must comply, namely the "serviceability limit state" and the "ultimate limit state". The serviceability limit state deals with the normal course of building performance under expected loads, and requires that in these circumstances the building should not show any sign of distress and should function in the intended manner. The ultimate limit state is directed to providing a margin of safety against failure by designing for a higher load than is actually anticipated and by making allowance for variability in material strength, for example to deal with unexpected overloading or weaknesses that may develop.
More recently, the concept of design to accept damage but prevent collapse has been introduced, particularly in relation to seismic forces and other forces that are more difficult to predict. This design concept is directed to conditions beyond the ultimate limit state, at which point permanent damage is experienced. Where a structure has been appropriately designed to accept damage but prevent collapse, in conditions beyond the ultimate limit state but within the design limit, the structure may be visibly damaged but will retain most (at least 80%) of its original strength and, in the case of earthquakes, the additional accepted damage produces increased ductility and energy dissipation. This additional ductility and energy dissipation allows design for lower lateral forces for cases of low probability of occurrence such as either the 1 in 475 year or 1 in 2500 year earthquake that is currently designed for in most countries. In the event of such an earthquake, damage would occur but the building would not collapse and thus deaths, injuries and collateral damage may be reduced. Depending on the extent of damage, it might be economical to repair the building.
There are two related but separate aspects of behavior of grout-filled hollow masonry block construction subjected to vertical compression, such as is created in concrete block shear walls by gravity loading and by loading resulted from lateral seismic forces: interaction between grout in the cells and the mortared hollow masonry block, and brittle compression failure of grout-filled hollow masonry block.
Reference is first made to the interaction between grout in the cells and the mortared hollow masonry block. In standard hollow block construction, compression failure occurs at stresses well below the compressive strength of individual blocks as a result of incompatibility between the mortar and the block material. Under vertical compression, the larger lateral expansion of the softer mortar creates lateral tension in the blocks which results in development of vertical cracks through the webs and face shells of the block, leading to sudden crushing of the combined material at relatively low levels of vertical strain. Thus, compressive strength of the combination can be predicted based on mortar type and compressive strength of the block. However, when grout is used to fill the cells created in the hollow concrete block construction, addition of this third material creates a more complex condition where the different stress-strain properties of the grout, the discontinuities in the column of grout created by imperfect alignment of the block cells from course to course, wedging action due to the tapered shape of face shells and webs, and shrinkage of the grout, all combine to produce a lower material strength than attained in the ungrouted assemblage. The addition of the grout increases the overall capacity of the structure but, when considering the increased solid area of the grouted cross-section, the stress at failure is typically about 25% lower than for ungrouted hollow masonry, with strength based on failure load (capacity) divided by the effective net area of the assemblage. Increasing the grout strength has only a minor effect on the overall compressive capacity.
Although changes in geometry of the cells in the hollow masonry block and use of shrinkage compensating grout can reduce the decrease in observed strength, these approaches are not fully effective and have undesirable economic impact. Reducing the volume of grout to about 25% of the gross volume and improving the vertical alignment of the cells in successive courses of block masonry can help address the undesirable decrease in strength. For example, for a nominal 20 cm (8 inch) block, a 100 mm (4 inch) diameter cylindrical shaped cell occupies approximately 21% of the gross volume and gross cross-sectional area and, combined with positioning of these blocks so that the cells align from course to course, results in higher compressive strength than traditional grouted hollow block construction.
Turning now to brittle compression failure of grout filled hollow masonry block, despite the improved compressive strength created by the block geometry described above, the mode of compression failure remains the same: development of vertical cracks and sudden crushing/crumbling of the grouted assemblage. This brittle property of grouted masonry and of concrete products in general has been understood for some time as a limiting factor in use of concrete block construction, particularly for seismic design where economic design requires ductile behavior.
It has been shown that lateral confinement of brittle materials such as concrete creates a state of tri-axial compression under vertical axial compression loading so that both higher strengths of the material are obtained and much higher vertical strains are reached prior to crushing and crumbling of the block under the vertical compression load. Both the strength increase and the greater deformability can be used to create more ductile reinforced concrete block shear walls to better resist lateral earthquake load.
A number of strategies have been employed in attempts to introduce lateral confinement into grouted concrete block construction. These confining methods are generally passive in that vertical deformation is required to introduce the confining effects. With vertical compression of the material, lateral expansion of the material takes place where the ratio between the amount of lateral expansion and the vertical compression is known as Poisson's Ratio. At low levels of loading, this ratio is about 0.21 but at high levels of stress this can increase significantly and create what is referred to as dilation. Introduction of confining reinforcement to resist the lateral expansion introduces tension in the horizontal (lateral) reinforcement and a balancing amount of lateral compression in the grouted concrete block. The tri-axial state of compressive stress in the confined region is what creates the much higher compressive strength and greatly increased deformability of the confined material.
One method using a confining reinforcement to enhance the compression capacity and deformability of a grouted section involves placing steel wire mesh, perforated plates, and/or fiber reinforced polymer (FRP) fabric/laminates within the mortar bed joints. For example, Priestley (Priestley, M. J. N. Ductility of Unconfined and Confined Concrete Masonry Shear Walls. TMS Journal, July-December 1981, pp. 28-39) studied concrete masonry prisms confined with 3 mm thick stainless steel plates within the mortar beds. The plates were cut to the net shape of the masonry units so that there was no interference with the grouted cells, with a 5 mm edge allowance for pointing the mortar bed joints. The confined prisms showed increased strength, higher strains at peak load, and a much flatter falling branch of the stress-strain curves. PCT Patent Application No. PCT/US2005/25477, published as WO2006/020261, teaches other methods using confining reinforcement.
U.S. Pat. No. 5,809,732 teaches concrete masonry blocks with one or more external plates that are formed with the plates anchored through the block to enable items to be anchored to a wall built with these blocks. A masonry wall can be constructed using masonry blocks with external plates at preselected locations to anchor items to the wall by attaching them to the plates. The external plates are directed to supporting the anchoring function rather than to reinforcing the wall.
Another proposed technique was to provide lateral confinement for just the grout, for instance by using a spiral coil shape of reinforcement placed inside the block cell prior to grouting.
Hart et al. (Hart, G. C. et al. The Use of Confinement Steel to Increase the Ductility in Reinforced Concrete Masonry Shear Walls. TMS Journal, July-December 1988, pp. 19-42) conducted a comprehensive test program to investigate different types of confinement such as wire mesh, a modified "Priestley Plate", hoops and spirals. In order to maintain consistent vertical reinforcing throughout all prism tests, one No. 6 bar was provided in each cell. The conclusions were: (1) unreinforced and vertically reinforced unconfined prisms behaved identically and failed in a brittle manner; (2) all types of confinement had a positive effect on the descending portion of the stress-strain curve and increased the area under the stress-strain curve; (3) the Priestley Plate provided the greatest confinement; and (4) the open wire mesh confinement type performed well.
For concrete block construction with standard block sizes, placing confining reinforcements within the mortar bed joints, as suggested by Priestly, means using a 200 mm (8 inch) vertical spacing between the confining reinforcements (i.e., the distance between successive bed joints). Such a large spacing limits the effectiveness of the confinement and effectiveness of support against buckling of enclosed vertical compression reinforcement. Reducing the height of the blocks to reduce the spacing distance demands handling more blocks and laying more mortar, which can dramatically increase construction cost. Similarly, increased construction labour is associated with placement of spiral coil reinforcements inside the block cell prior to grouting. In addition, the effectiveness of such reinforcement is limited because, for a typical grouted cell occupying less than 45% of the solid volume, less than 30% of the section can be effectively confined. Following crumbling of the block and grout outside of the spiral, the residual confined area is prone to buckling and cannot develop sufficient extra strength to compensate for the area lost after the material outside of the confined region fails in compression.
Thus, achieving increased ductility in masonry block construction using techniques mentioned above involves practical difficulties and may also involve significantly increased labour costs.

Self-reinforced masonry blocks, walls made from self-reinforced masonry blocks, and method for making self-reinforced masonry blocks


A processor includes a multi-stage pipeline having a plurality of stages. Each stage is capable of receiving input values and providing output values. Each stage performs one of a plurality of data transformations using the input values to produce the output values. The data transformations collectively approximate at least one of: a discrete cosine transform and an inverse discrete cosine transform. The stages do not use any multipliers to perform the data transformations.

The discrete cosine transform (DCT) is a very useful and important transformation in a wide range of signal processing systems. For example, the discrete cosine transform and its inverse transform (IDCT) are often two of the core operations in audio, image, and video coding systems. These transforms have even been adopted by several international coding standards, such as the Joint Picture Expert Group (JPEG), H.261, H.263, Moving Picture Experts Group 1 (MPEG-1), MPEG-2, and MPEG-4 standards.
Both the discrete cosine transform and its inverse transform involve intensive computational processes. For example, a direct implementation of an eight-point, one-dimensional discrete cosine transform typically involves sixty-four multiplication operations and fifty-six addition operations to convert input data into DCT coefficients. Other implementations of the discrete cosine transform attempt to reduce this complexity. These implementations, often referred to as "Fast DCT" algorithms, typically involve twenty-nine addition operations and between eleven and sixteen multiplication operations.
A problem with these implementations of the discrete cosine transform and its inverse transform is that they involve floating point multiplication operations. Floating point operations are typically slow and require larger areas when implemented in hardware. Also, the longer execution time required for floating point operations typically results in greater power consumption. This may be troublesome in applications such as mobile multimedia devices like digital cameras, videophones, and pocket computers, which often have limited power, processing resources, and memory.

Method and system for fast implementation of an approximation of a discrete cosine transform


Transitioning to a suspend to RAM sleeping state while also protecting against power losses while sleeping is provided. System state context data is saved to non-volatile storage and components in the computer system prepare to transition to a suspend to disc sleeping. A transition to the suspend to RAM sleeping state is then effected. Alternatively, after the system context is saved and the components are prepared to transition, the system may wake to a working state. The components may be directed to prepare for transitioning to a suspend to RAM sleeping state, and then the BIOS may be directed to execute the transition. In either embodiment, if power to the system is lost while the system is in the suspend to RAM system state, then the system may resume to a working state by reading the context file stored to non-volatile storage.

A computer system typically may be in one of many standby states, including "sleeping" states. An open industry specification called Advanced Configuration and Power Interface (ACPI) establishes industry-standard interfaces for configuration and power management directed by computer operating systems. The ACPI establishes system sleeping states, commonly designated, "S1," "S2," "S3," and "S4," with each sleeping state defined to allow implementations that can tradeoff cost, power, and wake latencies. Additionally, the ACPI specification defines the sleeping states such that a system can support multiple sleeping states, allowing the system to transition into a particular sleeping state for a predefined period of time and then transition to a lower power/higher wake latency sleeping state.
The S1 sleeping state is a low wake latency sleeping state, and in this state no system context is lost and hardware maintains all system context. System context generally is the volatile data in the system that is not saved by a device driver. The S2 sleeping state is a low wake latency sleeping state similar to the S1 sleeping state except that a state of a central processing unit (CPU) and system cache typically are lost and control starts from the CPU's reset vector after a wake event. The S3 sleeping state is another low wake latency sleeping state where typically all system context, CPU state, cache, and chip set context are lost, and only system memory is maintained. During the S3 sleeping state, hardware maintains memory context and restores some CPU configuration context. Control starts from the CPU's reset vector after a wake event.
During the S1, S2, and S3 sleeping states, power to RAM is maintained, and therefore, each of these sleeping states may be referred to as "suspend to RAM" sleeping states. The S4 sleeping state is the lowest power, longest wake latency sleeping state supported by the ACPI. To reduce power to a minimum, it is assumed that the hardware platform has powered off all devices, and the platform context is maintained. In the S4 sleeping state, power to RAM may be eliminated, and the system context is stored to disc or other non-volatile storage. Therefore, the S4 sleeping state may be referred to as a "suspend to disc" sleeping state. The ACPI also defines a system state S0, which is a system working state.
The latency period for waking a system in a suspend to RAM sleeping state, such as the S1, S2, or S3 sleeping state, is shorter than for a system in the suspend to disc sleeping state, such as the S4 sleeping state. The delay involved in transitioning to a working state from a suspend to disc state may create a disincentive to placing a computer in the suspend to disc state. The user, for example, may prefer a suspend to RAM sleeping state so that resuming to a working state may occur more rapidly than from a suspend to disc sleeping state.
A problem with choosing a suspend to RAM sleeping state over a suspend to disc sleeping state, however, arises if power to the system is lost. Because the system context is written to RAM for the suspend to RAM sleeping states, power is needed to maintain the system context in RAM. If power is lost while a system is in the, for example, S3 sleeping state, the context will be lost, and a full or lengthy boot process may be required. Moreover, any work in progress may be lost.
If, however, a system in the suspend to disc sleeping state (e.g., the S4 state) loses power, upon regaining power, the system wakes normally. This is because the system context was previously written to non-volatile storage. FIG. 1 depicts a flow diagram of a typical method 10 for transitioning from a working state such as the S0 state to a suspend to disc state, such as the S4 sleeping state. The method 10 includes transitioning to the suspend to disc state in a system that subsequently loses power. The loss of power is indicated by the dashed line 15. The method 10 also includes transitioning to the working state after regaining power, shown as the steps below the dotted line 15.
At step 11, device drivers or components in a system are notified that the system will be transitioning to the S4 sleeping state. This step may occur after the operating system queries application programs and device drivers of the viability of transitioning to a sleep state and after the operating system receives indications that the applications and drivers are ready for the transition. Alternatively, the operating system may tell the applications and/or the device drivers of the transition without first asking. At step 11, each device driver saves its state. At step 12, a context file comprising the context of the system may be written. The operating system may write the context file. At step 13, the operating system may communicate with firmware containing basic routines that help to transfer information between elements within the computer during, for example, start-up, sleep, or shut-down operations. The firmware may be a basic input/output system (BIOS). The operating system may direct the BIOS or other firmware or hardware to transition to the S4 sleeping state. At step 14, power to the system is lost.
At step 16, power is regained. Upon regaining power, the system reads the context file at step 17. At step 18, the operating system may restore the system to the working state it was in before entering the S4 sleeping state (i.e., before step 11).
In some systems, when a BIOS is notified of a transition to a suspend to RAM state, such as the S1, S2, or S3 states, the BIOS may write a system context file to non-volatile storage even if another entity, such as an operating system, has saved state to RAM. If the BIOS writes this file and, while in the suspend to RAM state, power is lost, the BIOS file may be used to wake the system when power is regained. Problems may arise, however, with attempting to wake the system with the BIOS context file because the BIOS may not have been aware of the current state of the system when creating the file. The system context that the BIOS saves to disc thus may not be reliable and may not reflect a current state of the system.
Therefore, there is a need for systems and methods for providing a reliable capability of a computer system to wake to a working state from a suspend to RAM sleeping state while safeguarding context information and work in progress in the event that the computer loses power while in the suspend to RAM state.

Systems and methods for providing power-loss protection to sleeping computers systems


A serial interface packet information detection and control method for a Mobile Industry Processor Interface is disclosed. The serial interface packet information detection and control method includes receiving and decoding a packet; generating a control signal according to packet information of a header of the packet; and disabling a function register according to the control signal.

1. Field of the Invention
The present disclosure relates to a serial interface packet information detection and control method and the receiver thereof, and more particularly, to a serial interface packet information detection and control method and the receiver thereof, which can enable/disable a function register according to a packet information so as to timely turn off the writing function of the function register in transmitting processes, thereby preventing errors from being written into the function register—which might cause the display device function mistakenly—and enhancing protection against noise in the transmitting processes.
2. Description of the Prior Art
As science and technology develop rapidly, handheld devices such as smart phones and personal digital assistants (PDA) have integrated more and more communication and display techniques so as to realize various application functions. In order to manipulate various application functions simultaneously, it requires a high-speed processing interface between a processor and a display panel (i.e. between a host and a slave) of a smart handheld device to speed up data transmission and thus improve display quality or touching functions of the panel. The mobile industry processor interface (MIPI) is a high-speed serial interface used widely in current industry. However, in the conventional techniques, if interference resulting from noise occurs in data transmitting processes, errors may be written into a function register of the receiving terminal, which causes abnormal display operations.
Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating a conventional packet 10 which complies with a MIPI Display Serial Interface (DSI) long packet protocol. As shown in FIG. 1, the packet 10 comprises a header 100, a payload 102 and a footer 104. The header 100 comprises a data identifier (data ID) field 106, a word count field 108 and an Error Correcting Code (ECC) field 110. The payload 102 comprises the data fields D0, . . . , Dn. The footer 104 comprises an error checking code field.
In short, the Error Correcting Code field 110 can ensure the reliability, the validity and the completeness of the data of the data identifier field 106 and the word count field 108. When a receiver receives the packet 10 via the MIPI Display Serial Interface, the receiver can determine whether any error occurs according to the Error Correcting Code field 110. If any error is found, the error is corrected instantly or following parts of the packet 10 are ignored. As a result, even if the header 100 is interfered by noise, inaccurate data is not written.
In the payload 102, the footer 104 comprises the error checking code field which can determine the completeness of the received payload 102 after checks. However, during the process of receiving the payload 102, if the payload 102 is interfered, the inaccurate payload 102 resulted from the interference may still be written or even executed. In such a situation, since in the application of the MIPI Display Serial Interface, the first data of the data field D0 is usually a Display Command Set (DCS) and is associated with an address of a display command function register in the receiver, which is utilized to configure the function of the display device, such as turning off the display device, turning on the display device, changing the orientation of the display device. Therefore, if the data field D0 is interfered and thus executed inaccurately, it may cause abnormal display operations of the display device—for example, the display device is mistakenly switched off. As a result, there is still room for improvement in the field.

Serial interface packet information detection and control method and receiver thereof


A method for the deburring of tubular parts made from cast iron, wherein, between two deburring operations, the position of at least one active point of the grinding wheel is measured, and, after having thus measured the position of a number of points, the trajectory of the grinding wheel corresponding to the grinding wheel profile, as defined by these points, is calculated.

This invention relates to a method and apparatus for deburring a series of parts along a seam line of each part.
Deburring is an important operation in the manufacture of cast parts, especially with respect to cast iron, since burns may have an adverse effect on their service behavior. For example, when the male end of a tubular part is inserted into another tubular part including the interposition of a sealing lining, the presence of an over-thickness or a hollow along the seam line, resulting from improper deburring, can contribute to a fault in the sealing.
The deburring of parts in series by a rotary grinding wheel results in wear of the grinding wheel. One conventional practice is to monitor the quality of the deburring and to trim the active profile of the grinding wheel as the quality of deburring decreases. This process, however, is costly and is limited by the coarseness of the grinding wheel since it is difficult to trim a very coarse grinding wheel. However, increases in the grain size of the grinding wheel make it possible, with only moderate expenditures of energy, to increase the productivity of deburring.


A plate-shaped circuit board configured to receive a detection signal from a detector is housed in a case and is held by a holder with a flat substrate surface thereof intersecting with a bottom surface of a cover member. The holder is attached to the cover member. The cover member includes a cover body, and elongated supporting portions projecting from the bottom surface of the cover body into the case. The supporting portions each include a pair of support projections that support one of opposite side surfaces of the circuit board along a projecting direction of the supporting portions. The holder includes a flat portion provided with engagement pieces engageable with a second substrate.

In some pressure transmitters and other physical quantity measuring devices, a circuit board receives a detection signal from a detector for detecting a physical quantity, and a signal from the circuit board is outputted to an external device or to a display.
In typical examples of the above physical quantity measuring devices, a circuit board is disposed in parallel with a bottom surface of a holder, and an outer periphery of the circuit board is pressed at regular intervals using a plurality of engagement portions or claws of the holder (Patent Literature 1: JP-A-2005-300186, Patent Literature 2: JP-A-10-318871, Patent Literature 3: JP-A-2007-155505 and Patent Literature 4: JP-A-11-351994).
In other typical examples, a circuit board is disposed perpendicular to a bottom surface of a holder, the circuit board having a first end bonded to a joint-side support body and a second end bonded to a connector-side support body (Patent Literature 5: JP-A-2013-205418 and Patent Literature 6: JP-A-9-138170).
The typical examples of Patent Literatures 1 to 4 require the outer periphery of the circuit board to be held relative to the bottom surface of the holder at an accurate position using the plurality of engagement portions and claws. It is complicated to attach the circuit board at the accurate position.
Further, when the physical quantity measuring device is used in ship or the like, the circuit board may be displaced due to the rolling of the ship or the like, but it is doubtful whether or not necessary measures are taken to deal with a vibration problem in the typical examples.
Specifically, in the typical examples of Patent Literatures 1 to 4, the circuit board, which is pressed using the engagement portions or claws, may be displaced or detached from the engagement portions or claws in response to a vibration applied to the device.
In the typical examples of Patent Literatures 5, 6, both ends of the circuit board each need to be bonded to the holder or the joint, which results in an inefficient device assembly.
Especially in the typical example of Patent Literature 5, the end of the circuit board needs to be machined into a joint shape and bonded to the support body, which also results in an inefficient device assembly.


An inertial measurement unit (IMU) is provided that includes a container that defines a cavity. A sensor suit or ISA having a housing is provided in the container of the IMU. A dampening material is provided between the housing of the ISA and the container of the IMU. The dampening material may be applied by coating, spraying, or dipping, or may be separately molded and then inserted, if desired. A sway space may also be provided between the ISA and the IMU container.

In certain environments, it may be necessary to isolate mechanically sensitive assemblies from shock, vibrational, and acoustic energy. In many applications, this may be accomplished by placing the sensitive components within some form of container or housing. The need to isolate a device from shock, vibrational, and/or acoustic energy may be particularly acute when the device is an inertial sensor assembly (ISA), which may include a sensor suite of an inertial measurement unit (IMU). An ISA typically includes inertial sensors that detect acceleration and/or rotation in three axes. Usually, three accelerometers and three rotational rate sensors are arranged with their input axes in a perpendicular relationship. The sensors may generally be rigidly and precisely mounted within an ISA housing along with related electronics and hardware. Commonly, the housing of the ISA may be mounted to a container of the IMU, and the IMU may be rigidly and precisely mounted to a frame of a vehicle, such as an aircraft, missile, or other object.
Some applications expose the IMU to extremely high dynamic environments, such as ballistic applications wherein a projectile may be fired from a gun. Traditionally, the inertial sensors were protected to some degree from relatively low level shock and vibration through the use of vibration isolators. However, such vibration isolators often do not protect the inertial sensors form higher vibration and shock levels that are often present in many high dynamic environments. Therefore, it may be desirable to provide a mechanism to attenuate energy transfer to the inertial sensors in relatively high shock and vibration environments, particularly in ballistic and other high dynamic applications, to increase the performance of the inertial sensor system.