A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.

Reference is now made to FIG. 1 which illustrates a circuit diagram of a conventional non-volatile memory cell 10. The cell 10 comprises a first transistor 12 and a second transistor 14. The first transistor 12 is a memory transistor and is configured with a floating gate structure 16 known to those skilled in the art. The floating gate structure 16 can be implemented in a number of ways: for example through the use specific process steps or by the use of a capacitor connected at the gate of a conventional NMOS transistor. The wordline (WL) for the cell 10 is connected to the gate (control terminal) of the memory floating gate first transistor 12. The second transistor 14, comprising for example a conventional NMOS transistor, functions as a select transistor for the memory floating gate first transistor 12. A select signal (SEL) is applied to the gate of transistor 14. The source-drain paths of the first and second transistors 12 and 14 are connected in series. The drain terminal of the floating gate first transistor 12 is coupled to a bit-line (BL) and a source terminal of the select second transistor 14 is coupled to a source-line (SL). The transistors 12 and 14 are formed in a common P-well (PW). To program the cell 10, charge is stored at floating gate structure 16. The construction, configuration and operation of the cell 10 are well known to those skilled in the art.
FIG. 2 illustrates a block diagram of an exemplary non-volatile memory 20 including a plurality of cells 10 arranged in an array 22. The memory 20 may be implemented as a discrete memory circuit or embedded with other circuitry, such as processing circuitry, in a system on chip (SoC) integrated circuit. FIG. 3 illustrates the details of a portion of the array 22 within memory 20, and in particular shows a subset of the array formed by cells 10 arranged in two sectors. The illustrated number of cells is exemplary only, and those skilled in the art understand that each sector may include many more cells and that the memory will include many more sectors. A word-line (WL) driver circuit 24 is used to select/de-select the word-lines in different operations by applying signals to the gates of the memory floating gate first transistors 12 of individual ones or groups of cells 10. A select line (SEL) driver circuit 26 is used to select/de-select memory cells 10 in different operations by applying signals to the gates of the select transistors 14 of individual ones or groups of cells 10. The voltage levels of the signals applied by the SEL-driver 26 and WL-driver 24 control the operation to select or de-select a particular memory cell 10 as well operate the cell in a number of different operating modes including programming and erase. A column decoder circuit 28 and pre-decoder circuit 30 are used to select the bit-lines (BL< >) and source-lines (SL< >) of the one or more memory cells 10 desired in the programming or erase operations. A charge-pump 32 generates the on-chip high voltage(s) required during program and erase operations for application to specific nodes of the memory cells. The voltage generator block 34 is included as a part of the charge pump 32 for the memory. The high voltages and other multiple voltages are generated by the block 34 from the pumped voltage and routed to different blocks of the memory for selection and application to the memory cells.
The programming operation of the cell 10 utilizes the well-known Fowler-Nordheim (FN) tunneling effect. To perform FN-tunneling, high voltages are required which are generated on-chip through the charge-pump 32 and voltage generator 34 for application to the cells 10. The FN process is well known in the art. Biasing of the nodes of the memory cell in a particular way achieves the FN tunneling effect and programs a desired data value at a selected memory cell. Reference is now made to Table 1 which illustrates the different voltages required in an exemplary implementation to bias a memory cell 10 during a programming operation:
BLBL(programmed(not program-WLSEL0/SEL1cell)med cell)PWSLSelectedVHIGH0/00(VHIGH/3)00 orsector(VHIGH/3)Non-00/00(VHIGH/3)00 orselected(VHIGH/3)sector
Reference is now made to FIG. 4A which illustrates, in the context of a subset of the array and column decoding circuitry, the programming operation conditions and a resulting leakage path situation. The required voltages are provided with response to a selected sector and non-selected sector (see, FIG. 3). With respect to the selected sector, in order to program a memory cell 10, a VHIGH voltage is applied through the word-line to the gate of the memory floating gate first transistor 12 for the cell 10 being programmed and the bit-lines of that cell are driven to logic "0". The voltage VHIGH is well in excess of logic "1" voltage, for example comprising a voltage of about 15-18V. Also within the selected sector, and with respect to each memory cell 10 that is not being programmed, the VHIGH voltage is applied through the word-line to the gate of the memory floating gate first transistor 12 and the bit-lines of that memory cell 10 are driven to a VHIGH/3 voltage (provided by the voltage generator 34) in order to inhibit the programming operation. During the programming operation, the select transistors 14 in all cells 10 are turned OFF by driving the gate terminals of the select transistors to logic "0" (i.e., applying a Vgs=0).
The array configuration shown in FIG. 3 provides for all bit-lines in the array to be shared across sectors. Thus, the voltages applied to the bit-lines with respect to selected cells 10 in one sector (the selected sector) are also applied to the cells in other sectors (the non-selected sectors).
It is evident that in applying the VHIGH/3 voltage at some of the bit-lines in order to inhibit the programming of non-selected cells in the selected sector, this will force some of the bit-lines at high voltage. Within the selected sector, the select transistor 14 accordingly sees a Vds at the VHIGH/3 voltage because the memory cell 10 is fully ON. However, the select transistor has an assumed state of being perfectly switched OFF because the Vgs=0 for this transistor. Nonetheless, this select transistor 14 exhibits leakage (reference 40 in FIG. 4A) of the sub-threshold conduction type due to the presence of a high Vds at the NMOS select transistor 14. The sub-threshold conduction for the NMOS select transistor is high, and the problem with this leakage is exacerbated at fast corners and high temperature. With respect to the non-selected memory cells in the non-selected sectors, and assuming the non-selected cells are depleted, a high Vds is also seen across the associated NMOS select transistors and this results in a further contribution of sub-threshold array leakage. Indeed, the overall leakage in programming operation can be very high with memories having a larger density cut. For example, for a cut-size of 4 Kbit, this leakage is ˜600 uA @ 150 degrees C.
FIG. 4B illustrates simulation results for a memory of the type shown in FIG. 4A and having a 4 Kbit array density operating in programming mode. The simulation results show that during a worst case the array leakage exceeds 600 uA. This leakage will become the current load for the charge-pump during programming.
A similar concern with leakage exists with respect to the erase operation which is also a high voltage operation. The erasing operation of the cell 10 also utilizes the well-known Fowler-Nordheim (FN) tunneling effect. To perform FN-tunneling, high voltages are required which are generated on-chip through the charge-pump 32 for application to the cells 10. The FN process is well known in the art. Biasing of the nodes of the memory cell in a particular way achieves the FN tunneling effect and erases a desired data value at a selected memory cell. Reference is now made to Table 2 which illustrates the different voltages required to bias a memory cell 10 during an erase operation:
BLBL(programmed(not program-WLSEL0/SEL1cell)med cell)PDPWSLSelected0VHIGHFloatingFloating0VHIGHVHIGHsectorNon-VHIGHVHIGHFloatingFloating0VHIGHVHIGHselectedsector
Reference is now made to FIG. 5A which illustrates, in the context of a subset of the array and column decoding circuitry, the erase operation conditions and the leakage path situation. In the erase operation, the word-line in the selected sector is driven to logic "0" and the p-well (PW) is biased at the VHIGH voltage generated by the charge-pump. Those skilled in the art recognize that parasitic diodes exist in the transistors 12 and 14 between the bulk-source junction and bulk-drain junction. So, the source and drain terminals of the memory cell will be charged to a voltage equal to VHIGH-Vt (where Vt is the threshold voltage of the bulk to source-drain junction). Because the bit-lines and source-lines of the whole array are shared, this high voltage of VHIGH-Vt is transferred to the drain terminal of the column decoding transistors within the column decoder 28. In order to protect a first level 44 of the column decoding transistors, the gate and source of the included first level transistors are biased during erase at a 2VHIGH/3 voltage level generated by the charge pump of the voltage generator block 34. Similarly, a next level 46 of column decoding sees a stress at the 2VHIGH/3 voltage. In order to protect the second level 46 of decoding, the gate and source of the included second level transistors are biased at the VHIGH/3 voltage level. The source terminals of the transistors in the second level 46 of the column decoding are also biased through pull-up transistors 48 in a program related circuitry 50 section (FIGS. 2 and 5A) to the VHIGH/3 voltage level (where the included pull-down transistors 54 are controlled in an OFF state by driving their gate terminals to logic "0"). The pull-down transistors 54, however, will see a Vds of the VHIGH/3 voltage level. There is accordingly a sub-threshold leakage current 56. Because the pull-up and pull-down transistor circuits 48/54 within the program related circuitry 50 are repeated in dependence on the number of source-lines and bit-lines and eventually the sector size, it will be understood that the larger the sector the greater the number of circuits 48/54 that are needed, and correspondingly the higher the sub-threshold leakage. For a sector size of 256 bits this leakage is around ˜100 uA @ 150 degrees C.
FIG. 5B illustrates simulation results for a memory of the type shown in FIG. 5A and having a 4 Kbit array density operating in erase mode. The simulation results show that during a worst case the array leakage exceeds 90 uA. This leakage will become the current load for the charge-pump during programming.
The leakages during programming and erase operations are not negligible and need to be supported by the on-chip charge-pump. The voltages VHIGH, 2VHIGH/3 and (VHIGH/3) are generated by voltage generator block 34 and specifically responsive to the operation of the charge-pump 32. It is thus noted that the leakage currents during both programming and erase become the current load for the charge-pump. If the charge-pump 32 is not able to support the array leakage, then the memory write and erase operations may fail or may be performed erroneously.
One solution to this problem is to design the charge pump 32 as a very low impedance circuit that can support the anticipated leakage during program and erase operations. A drawback of this solution is that the charge pump will occupy a larger amount of integrated circuit area (due for example to an increased size storage capacitor and additional pumping stages) and there will be a corresponding increase in power consumption. Additionally, this solution drives towards a chip that lacks modularity because any changes in the density of memory array will require a re-design of the charge-pump in order to support the leakage. Such a redesign may adversely affect circuit area and power consumption.
Further, while this leakage is very large in fast corner and higher temperature conditions, in typical operating conditions it is noted that no or very little leakage may occur. The provision of a strong charge-pump to support this anticipated leakage at the fast corner and high temperature conditions accordingly presents an over-design for the typical operating conditions where current load for the charge-pump is lower. In this case, with a stronger charge pump, the charge pump ripple will be more prominent. It may not be possible to control the ripple and the reliability of the memory operation could then suffer.
There is accordingly a need in the art to reduce or remove the leakage in a non-volatile memory array during program and erase operations which will help in reducing the area occupied by the charge pump and further reduce the power consumed not only by the charge pump but also with respect to the entire system (for example, the system on chip (SoC) which includes the memory array).

Non-volatile memory with reduced sub-threshold leakage during program and erase operations


A character input method according to the present invention includes the steps of when a user brings a mouse cursor into contact with the term input box of a web browser or website, or clicks the term input box one or more times, displaying a character input window, in which two or more character buttons and a completion button for enabling the input of a signal indicative of the completion of the entry of one or more characters are arranged, in abutment with the term input box; when one or more of the character buttons are clicked, entering one or more characters cor? responding to the clicked character buttons into the term input box; and when the completion button is clicked, generating an activation signal so that an search engine associated with the term input box is run using the characters, entered into the term input box, as search data.

Recently, there is a tendency of the whole world to be connected by a single network via the Internet communication network using computers. The Internet has been already developed into part of a life. The Internet is not temporarily used only by persons in a specific group for specific purposes, but has become means from and through which normal persons obtain living information and enjoy their leisure.
Although there may be many reasons for the increase in the population of the use of the Internet, the development of the operating system of Personal Computers (PCs) to the Windows Operating System that is easier and more convenient to use than Disk Operating System (DOS) that is difficult to use has played an important role.
One of the characteristics of the above-described Windows Operating System is that means for inputting commands is not limited to a keyboard but convenient and various input means, such as a mouse, a joystick and a digitizer, can be used at the same time, which enables a user to execute desired predetermined commands without being aware of the operating system or instructions of a computer system.
However, in the above-described environment, it is essential to use a keyboard in order to enter the address of a home page, an ID, a password, or a search term. This is fundamentally caused by the characteristic in which characters have many elements, that is, the English alphabet has 26 characters and the Korean alphabet has 33 characters (including consonant digraphs and vowel pairs).
Furthermore, a handicapped person who cannot use a keyboard due to the impairment of his or her hands but can use a mouse or a joystick or an old person or a child who is poor at the manipulation of a keyboard inevitably visits only frequently visited domains solely depending on a mouse because he or she must enter the address of a desired home page into an address bar in the form of a text character string while browsing the Internet, so that there arises a problem in that he or she limitedly uses the Internet that includes great functionality and a large amount of information.
In order to overcome the above problem, a character input window configured to enable desired characters to be input only using a mouse and a character input method using the character input window were proposed.
The prior art character input window and the prior art character input method using the character input window will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a diagram showing an example of a screen of a typical web browser, FIG. 2 is a diagram showing a state in which a prior art character input window is displayed on a web browser, and FIG. 3 is a diagram showing the construction of the screen of the prior art character input window.
As shown in FIG. 1, a typical web browser 10 includes a web page window 12 for displaying an accessed web page, a toolbar 14 for displaying tools required for the use of the web browser 10, and an address bar 16 for enabling the address of a website to be entered therein. Furthermore, when an accessed web page corresponds to a portal website or a website, a search box 18 for enabling a search term to be entered therein appears on a web page.
In this case, when a mouse cursor is located on the address bar 16 or the search box 18 and a signal is input using a function button (not shown) of a mouse so as to activate a character input window, a character input window 20 appears on the web browser, as shown in FIG. 2. The character input window 20 is provided with a virtual keyboard 22 configured to have an arrangement substantially identical to the key arrangement of an actual keyboard, a preview box 24 for displaying a relevant character when a user locates a mouse cursor on the virtual keyboard 22 and performs a click, and activation buttons 26 for generating an activation signal to send or cancel an input character.
Accordingly, when a user clicks a character key of the virtual keyboard 22 using a mouse, a corresponding character appears in the preview box 24. When the corresponding activation button 26 is pressed after the completion of the input of the character, the character appearing in the preview box 24 is entered in the address bar 16 or the search box 18. That is, when the prior art character input window 20 is used, characters can be entered into the web browser 10 only using the mouse.


A method for calibration of an industrial robot is provided. A calibration device comprising devices for emitting a calibration beam within the working range of the robot, and an interruption detector which detects an interruption in the calibration beam are arranged. During the calibration process, a calibration tool supported by the robot hand and comprising a sphere with a known radius is moved towards the calibration beam. When an interruption in the calibration beam is detected, the output signals from the position transducers of the robot axes are read and stored. This process is repeated a plurality of times with different configurations of the robot. Thereafter, the calibration parameters of the robot are calculated based on the kinematic equations of the robot, the read and stored position transducer signals, and the known radius.

An industrial robot may be viewed as a chain consisting of stiff links. Two links are joined to each other in such a way that they are rotatable in relation to each other around an axis of rotation, or displaceable in relation to each other along a linear movement path. An industrial robot usually has six axes of rotation. The last link in the chain may consist of a tool which, depending on the field of application, may be a gripper, a glue gun or a welding gun. In the following, the links in a robot will be referred to as arms, and their lengths will be referred to as arm's lengths.
For each of the above-mentioned axes of rotation or linear movement paths, servo equipment with a driving motor and a position transducer is provided, the transducer delivering a signal which is a measure of the angle of rotation of the actual axis in relation to a reference position. The servo system of each axis is supplied with a reference value of the angle of rotation or linear movement of the axis, and the driving motor of the axis causes the robot the move until the axis position indicated by the position transducer of the axis corresponds to the reference value supplied to the servo system. In order for the position and orientation of the tool to correspond to the desired values, the mechanical structure of the robot and the parameters, so-called kinematic parameters, which describe it must be known with a high accuracy. Since the kinematic parameters are not exactly the same for each robot, the individual deviations from an ideal robot, that is, the kinematic error parameters of the robot, must be known if a high accuracy is to be attained.
Examples of kinematic error parameters are variations in the lengths of the arms, so-called arm's length errors, obliquities in the axes of rotation in relation to each other, so-called axis-attitude errors, and lateral displacements of the axes in relation to each other, so-called axis-offset errors. These deviations arise during manufacture of the different mechanical components and during the assembly thereof. To this is to be added the fact that the angle indicated by the position transducer of an axis must with great accuracy correspond to the actual angle of rotation of the arm which is controlled with the aid of the axis in question, the so-called encoder offset value. To determine the deviation of an individual robot from an ideal robot, various forms of calibration methods are used.
From Swedish patent document 9303757, a calibration method is known in which a spherical calibration body with a known radius is used. A calibration tool, comprising a sphere with a known radius, mounted on the robot hand is brought into contact with the calibration body in a number of different robot configurations. When the calibration tool and the calibration body are in contact with each other, position transducer signals are read and stored. Thereafter, the calibration parameters of the robot are calculated on the basis of the kinematic equations of the robot, a model of the relationship between axial position and position transducer signal, the known radius, and the read and stored position transducer signals.
The disadvantage with this calibration method is that the robot has to make contact with the calibration tool and that the calibration body has a limited extent. Upon the repeated contact between the robot and the calibration body, mechanical stresses may build up in the robot which may, in turn, lead to an unreliable calibration result. The fact that the reading is performed upon mechanical contact between the calibration tool and the calibration body leads to variations in the reading position; for example, the calibration body may be somewhat resilient upon contact with the calibration tool. The limited extent of the calibration body reduces the possibilities of varying the robot configurations, which in turn affects the accuracy in the calibration.

Method and device for calibration of movement axes of an industrial robot


A counter circuit uses a plurality of counter circuits so as to be used in all products employing a counter circuit in a semiconductor device, and thereby performs a multi-bit linear burst sequence operation. The counter circuit for embodying a linear burst sequence includes: a low order counting means which responds to an external clock signal and an external counting control signal, receives and counts a least significant first bit data among base input signals having bits ranging from a first bit to a N-th bit, and then generates a first data signal and a first high order control signal; and a plurality of high order counting means which receive bits ranging from a second bit successively connected to the least significant first bit to N-th bit, perform a counting operation, and generate a second data signal and a second high order control signal. The high order counting means which responds to the high order control signal and the counting control signal which are generated from the high order counting means of a previous bit of a present input bit, performs a counting operation, and outputs data signal.

1. Field of the Invention
The present invention generally relates to a counter circuit. More particularly, it relates to a counter circuit which uses a plurality of counter circuits so as to be used in all products employing a counter circuit in a semiconductor device, and thereby performs a multi-bit linear burst sequence operation.
2. Description of the Conventional Art
FIG. 1 shows a conventional counter circuit. The conventional counter circuit generates a clock synchronizing sign 1 CNT_CLOCK for synchronizing a counting operation. The low level bit counter and high level bit counter are responsive to the clock synchronizing signal CNT_CLOCK changing from a low level signal L to a high level signal H, or from a high level signal H to a low level signal L. The low order bit counter generates a first output signal OUT0 which is high(H).fwdarw.low(L).fwdarw.high (H).fwdarw.low(L). The high order bit counter responds to the output signal of the low order bit counter and then generates a second output signal OUT1 being low(L).fwdarw.low(L).fwdarw.high(H).fwdarw.high(H).fwdarw.low(L).fwdarw.lo w(L).fwdarw.high(H).fwdarw.high(H).
The conventional counter circuit does not receive an input signal (e.g., address, etc.) that functions as a base signal in a linear burst sequence operation. Accordingly, the conventional counter circuit cannot make an output signal according to the linear burst operation based on the input signal, and thus cannot be used in a device having the linear burst sequence operation.

Counter circuit for embodying linear burst sequence

Hyundai Electronics Industries Co., Ltd.


A robotic eel may comprise a plurality of torque reaction engines, an inertial mass, and a fin. Each of the plurality of torque reaction engines oscillates an inertial mass about an axis, producing a torque reaction on and oscillation of an external shaft. Oscillation of the external shaft bends a beam of the robotic eel. Bending the beam of the robotic eel produces at least one of a traveling or a standing wave in the beam. The traveling wave may be communicated to a second torque reaction of the plurality of torque reaction engines and to the fin, producing thrust.

U.S. patent application Ser. No. 15/101,901 discloses a torque reaction engine (TRE), use of which in a watercraft achieves a fish-like motion. The resulting craft swims like a fish or marine mammal, without the myriad parts that plague other mechanical craft that attempt to swim like a fish or marine mammal.
At times it may be desirable to swim in other modes, such as like an eel. Eels swim by generating body waves, wherein the body waves travel the length of their bodies.


The present invention relates to combination therapies for melanoma, and in particular, metastatic melanoma. Drugs for use in such therapies in include MEK inhibitors combination with cardiac glycosides.

I. Technical Field
The present invention relates generally to the fields of medicine and oncology genetics. More particularly, it relates to the combined use of MEK inhibition and cardiac glycosides to treat melanoma, particularly metastatic melanoma.
II. Related Art
Melanoma is a malignant tumor of melanocytes. Melanocytes are cells that produce the dark pigment, melanin, which is responsible for the color of skin. They predominantly occur in skin, but are also found in other parts of the body, including the bowel, oral cavity and the eye. Melanin also protects the deeper layers of the skin from the sun's harmful ultraviolet (UV) rays. When people spend time in the sunlight, the melanocytes make more melanin and cause the skin to tan. This also happens when skin is exposed to other forms of ultraviolet light (such as in a tanning booth). If the skin receives too much ultraviolet light, the melanocytes suffer genetic damage and can be transformed into cancerous melanoma cells.
Because of the link to cumulative sun exposure, the chance of getting melanoma increases with age, but many young people also get melanoma. In fact, melanoma is one of the most common cancers in young adults. Each year in the U.S., more than 50,000 people—young and old—learn that they have melanoma. And, according to a WHO report, about 48,000 melanoma related deaths occur worldwide each year. The treatment includes surgical removal of the tumor, and if melanoma is found early while relatively small and thin, complete removal gives a high cure rate. The chance of the melanoma coming back or spreading depends on how deeply it has invaded into the layers of the skin. Thus, the more progressed the lesion, the great the chancer for recurrence and/or metastasis. For melanomas that recur or spread, treatments include chemo—plus immunotherapy or radiation therapy, but the prognosis for such patients, including those exhibiting metastatic disease (AJCC Stage III and IV) is poor, with 5-year survival rates being less than 10%. As such, improved treatments for melanoma, particularly for advanced metastatic disease, are urgently needed.

The Board of Regents of the University of Texas System


A storage system comprises a storage compartment having a compartment door, a plurality of latches for latching the door, a plurality of slave cylinders coupled to the latches, and a master cylinder in fluid communication with the slave cylinders for causing the slave cylinders to simultaneously unlatch the latches.

Overhead stowage bins of commercial aircraft are required to stay closed during turbulence and all other flight conditions. To satisfy this requirement, the bins are equipped with dual retention latch mechanisms, which have redundant latches. A bin is opened only if all of its redundant latches are released simultaneously. In addition, force for releasing the latches should be sufficient to prevent uncommanded opening under all flight conditions.
A dual retention latch mechanism may include a mechanical actuation linkage for opening a bin. The linkage should satisfy the following constraints: it should apply a sufficient force to release both latches simultaneously; and it should be simple and easy to operate with a single hand.
Due to these constraints, the mechanical linkages in commercial aircraft are typically heavy and complex. In a commercial aircraft having sixty bins, for instance, the linkages can add more than one hundred pounds of weight to the aircraft. This additional weight increases fuel costs and other aircraft operating costs.


An apparatus includes a navigation device having a display device and a processing device coupled thereto and configured to present on the display device an indicator of a legend location, determine at least one travel metric corresponding to at least one legend location, and present the at least one travel metric in tandem with the indicator of the legend location. The at least one travel metric includes one or more of the following: a travel route distance to the legend location from a current physical location, an estimated time of arrival at the legend location, and an estimated duration of travel to the legend location from the present physical location. A corresponding method is also provided.

The subject matter disclosed herein relates to methods and corresponding navigation devices and, more particularly, to methods and corresponding apparatus for presenting a travel metric on a display device of a navigation device.
Navigation devices or navigation systems, as are commonly understood in the art, are typically utilized to determine a present physical location of the navigation device (or of a user of the device) and/or a route to a destination. Such devices may be installed within a vehicle (such as an automobile, a boat, an aircraft, or the like), while other permutations include portable electronic devices (such as portable dedicated navigation devices or mobile phones). Navigation devices often include or interface with a display device capable of presenting a graphical representation of a navigation map. If programmed with a destination, navigation devices may also show one or more suggested routes to the destination and possibly include graphical, textual, and/or auditory commands that instruct a user of the navigation device how to traverse the route.
Often, a navigation device will show an estimated time of arrival (ETA) to the route destination or a remaining distance to travel to the route destination. However, though suitable for some purposes, such an approach does not necessarily meet the needs of all application settings and/or users. For example, if a user wants to know an ETA or a distance to a certain location, the user is required to enter and set the location as the route destination.

Method and apparatus for presenting a travel metric


Apparatus and method for generating control inputs for a disc drive dual stage actuator having primary and secondary actuator motors used to maintain a head adjacent a rotatable disc surface. An h-infinity hardware controller generates the control inputs in relation to an actual position signal, a desired position signal and a unique set of coefficients for each selected head. The coefficients are selected by obtaining an output response for each head, selecting the coefficients in relation to the output response for each head, and storing the coefficients in a nonvolatile memory location of the disc drive. The appropriate set of coefficients are thereafter loaded as each head is selected in turn during normal drive operation.

This invention relates generally to the field of magnetic data storage devices, and more particularly, but not by way of limitation, to an h-infinity controller which provides control inputs to a disc drive actuator to maintain a head adjacent a selected track on a rotatable disc.
Disc drives are used as primary data storage devices in modern computer systems and networks. A typical disc drive comprises a head-disc assembly (HDA) which houses mechanical portions of the drive, and a printed circuit board (PCB) mounted to an outer surface of the HDA which supports electronic circuitry used to control the HDA.
A typical HDA includes one or more rigid magnetic storage discs which are journaled about a rotary hub of a spindle motor to form a rotatable disc pack, and an actuator assembly which supports an array of heads adjacent tracks defined on the disc surfaces. An actuator motor, such as a voice coil motor (VCM), rotates the actuator assembly, and hence the heads, across the disc surfaces. The control circuitry on the PCB includes a read/write channel which interfaces with the heads to transfer data between the tracks and a host computer, and a servo control system which drives the VCM to provide head positional control.
Continued demand for disc drives with ever increasing levels of data storage capacity have led disc drive manufacturers to seek ways to increase the density of data bits that are stored on each disc surface. High performance disc drives of the present generation typically achieve area bit densities measured in several gigabits per square centimeter, Gbits/cm2. Higher recording densities can be achieved by increasing the number of bits that are stored along each track, and/or by increasing the number of tracks per unit width across each disc. Storing more bits along each track generally requires improvements in the read/write channel electronics to enable the data to be written (and subsequently read) at a correspondingly higher frequency. Providing higher track densities generally requires improvements in the servo control system to enable the heads to be more precisely positioned over the discs.
In an effort to achieve higher track densities, disc drive manufacturers are increasingly moving to implement so-called xe2x80x9cmicroactuators,xe2x80x9d which are secondary motors suspended by actuator assemblies to provide fine (secondary) positional adjustment of the heads over and above the coarse (primary) positional adjustment provided by the VCMs. A variety of microactuator constructions have been recently proposed in the art, including the use of an inductive rotor/stator arrangement as exemplified by U.S. Pat. No. 5,657,188 issued to Jurgenson et al.; the use of piezoelectric transducers as exemplified by U.S. Pat. No. 6,002,549 issued to Berman et al.; and microelectronic machine (MEM) implementations as discussed in U.S. Pat. No. 5,711,063 issued to Budde et al.
The basic operational concept of an actuator assembly with both primary and secondary motors (also referred to as a xe2x80x9cdual-stagexe2x80x9d actuator) is relatively straightforward; the primary motor is used to bring the selected head within a given range of tracks, after which the secondary motor operates to bring the head over one particular selected track from the range of tracks. Implementation of the servo control electronics to provide the necessary control signals to the primary and secondary motors, however, has thus far proved to be a rather daunting task.
At present, one proposed solution is to provide a high performance programmable device (such as a digital signal processor, or DSP) with extensive programming algorithms in order to carry out the required dual-stage servo control. Such an approach is discussed, for example, by United States Pat. No. 5,978,752 issued to Morris. While operable, there is a continued need for robust and cost-effective controller solutions that can be implemented for both high performance single stage and dual stage actuators in a cost-effective manner and which are easily adapted to different design configurations and to different head/media combinations.
The present invention provides an apparatus and method for improving disc drive actuator control.
In accordance with preferred embodiments, a disc drive is provided with a rotatable actuator which supports an array of read/write heads adjacent a corresponding number of recording surfaces in a rotatable disc stack. A servo engine, characterized as a high-speed hardware circuit, generates control inputs for the actuator to carry out track following operations wherein a selected head is caused to follow a corresponding track.
The actuator can be characterized as a single-stage actuator having a single actuator motor (such as a voice coil motor, VCM), or alternatively can be characterized as a dual-stage actuator having both a primary actuator motor (VCM) and an array of secondary microactuators which controllably move each head. The control inputs for the motor or motors are determined in relation to an actual position signal for the head, a desired position signal for the head and a unique set of coefficients, or table lookup values, that are individually determined and loaded for each head.
The coefficients are selected by obtaining an output response for each head, selecting the coefficients in relation to the output response for each head, and storing the coefficients in a nonvolatile memory location of the disc drive. The appropriate set of coefficients is thereafter loaded into the hardware controller as each head is selected in turn during normal drive operation.
Each set of coefficients comprises the results of intermediate calculations for state equations used to determine the control input values. In this way, the hardware controller efficiently obtains solutions for the control inputs for the primary and secondary motors in a number of clock cycles corresponding to the length of the multi-bit input (actual position and desired position) words, by serializing the input words and using these as addresses to access the appropriate coefficients. The hardware controller further advantageously allows track following operations to be offloaded from a programmable processor of the disc drive, which enables the disc drive design to utilize a single processor for top level control of data transfer operations and velocity controlled seek operations.
The use of different sets of coefficients by head enables the hardware controller to be adapted for each head/disc combination. That is, as each new head is selected, a new set of table lookup values appropriate for the new head are loaded into the hardware controller, providing accurate, adaptive control. Moreover, dual-state actuators have inherently complex response characteristics, and the use of h-infinity controller synthesis provides an efficient way to reduce the uncertainties associated with dual-stage actuator design.
The servo engine is advantageously incorporated into an application specific integrated circuit (ASIC) housing other related circuits of the disc drive, such as demodulation (demod) circuitry used to condition servo signals readback from the disc surfaces. A special purpose random access memory (RAM) configuration is used to significantly reduce the time required to load each set of coefficients as each new head is selected in turn.
These and various other features and advantages which characterize the present invention will be apparent from a reading of the following detailed description and a review of the associated drawings.

Adaptive h-infinity hardware controller for disc drive actuator control


A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.

Wire bonding techniques have been proposed that allow wire bonding on an electrode pad of a semiconductor device in a case where a semiconductor element is formed below the electrode pad. In U.S. Pat. No. 6,261,939 corresponding to JP-A-2003-518739, thicknesses of an interlayer dielectric layer and a wiring layer positioned below the electrode pad is increased to between 1 micrometer (μm) and 2 μm. In JP-A-H8-236706, a wiring layer is multilayered below the electrode pad. Thus, a crack in the layer and a break in the semiconductor element are prevented. In U.S. Pat. No. 5,502,337 corresponding to JP-3432284, a via hole is formed around an electrode pad and not formed below the electrode pad. In US 2005/0258484A1 corresponding to JP-A-2006-5325, a copper (Cu) electrode pad is exposed to an insulation film or a passivation film, and a surface of the copper electrode pad is coated with an aluminum (Al) film. Thus, the copper electrode pad has a large thickness. While protecting the copper electrode pad from corrosion damage, the aluminum film helps reduce a bonding impact force transmitted to lower layers.
However, in the structures of U.S. Pat. No. 6,261,939 and JP-A-H8-236706, it depends on patterns of the layers, whether the crack in the layer and the break in the semiconductor element can be prevented, or not. It has been confirmed that the crack in the layers and the break in the semiconductor element cannot always be prevented. In the structure of U.S. Pat. No. 5,502,337, since the via hole is formed around the electrode pad, drain and source wiring of a power element (i.e., a semiconductor switching element) must be extended accordingly. As a result, an effective length of the wiring is increased, and a wiring resistance and a parasitic inductance of the wiring are increased accordingly. In particular, it is likely that the wiring resistance of the wiring become large, because the wiring become very thin at the lowest layer.
In the structure of US 2005/0258484A1, addition processes are required to form the copper electrode pad coated with the aluminum film. As a result, manufacturing step and cost are increased accordingly. Further, since the copper electrode pad narrows toward its top, a top portion of the copper electrode pad vibrates during wire bonding. Therefore, adhesion of the copper electrode to the semiconductor device is reduced due to the vibration. The vibration may cause cracks in the interlayer dielectric film. Furthermore, the aluminum film on the copper electrode pad is plastically deformed during the wire bonding and pushed off the top portion of the copper electrode pad. As a result, the aluminum film is thinned and cannot suitably reduce the bonding impact force.
One approach to reduce transmission of a bonding impact force to a lower layer is to increase thickness of an upper wiring layer. Lately, multilayered wiring of a semiconductor device is typically formed by a dual-damascene process. In the dual-damascene process, as disclosed, for example, in JP-3403058, a wiring trench and a via trench are formed in an insulation film formed on a semiconductor substrate. A wiring material such as copper (Cu) is filled in the wiring trench and the via trench so an upper wiring layer is connected to a lower wiring layer through a via. Thus, the upper wiring layer and the via are formed in the same step so that time required to form the wiring can be reduced.
FIGS. 21A-21C illustrate a conventional method of forming wiring of a semiconductor device. First, as shown in FIG. 21A, an insulation film 212 is formed on a semiconductor substrate 210 on which a lower wiring layer 211 is formed. Then, a first resist pattern for a via trench 213 is formed by a photolithography process. Then, the insulation film 212 is etched to a predetermined depth by using the resist pattern as a mask. Thus, the via trench 213 is formed.
Then, as shown in FIG. 21B, the insulation film 212 is etched by using a second resist pattern as a mask, until the lower wiring layer 211 is exposed. The second resist pattern is shaped corresponding to the first resist pattern and has a width greater than that of the first resist pattern. Thus, a wiring resist 215 is formed, and the via trench 213 reaches the lower wiring layer 211.
Then, as shown in FIG. 21C, a barrier layer 216 and a seed layer 217 are formed in the via trench 213 and the wiring trench 215. Then, a wiring material is filled in the via trench 213 and the wiring trench 215. The barrier and seed layers 216, 217 prevent the wiring material from diffusing into the insulation film 212. After filling, the excess wiring material is removed by, for example, a chemical mechanical polishing (CMP) process. Thus, a via 218 and an upper wiring layer 219 are formed. For example, the via 218 has a thickness of 1 μm, and the upper wiring layer 219 has a thickness of 1 μm.
In a combined integrated circuit (IC) including a complementary metal-oxide semiconductor (CMOS), a bipolar transistor, and a power element (i.e., semiconductor switching element), there has been a need to increase thickness of an upper wiring layer 219 to absorb a bonding impact force, to improve heat dissipation, or to withstand an increased current of the power element.
To increase the thickness of the upper wiring layer 219, thickness of an insulation film 212 needs to be increased accordingly. However, when the insulation film 212 having increased thickness is formed by using the conventional method illustrated in FIGS. 21A-21C, it is likely that the thickness of the insulation film 212 is nonuniform.
Further, since the amount of etching the insulation film 212 is increased accordingly, it is likely that the depth of the wiring trench 215 is nonuniform. Therefore, the insulation film 212 is over-etched to ensure that the via trench 213 reaches the lower wiring layer 211. If the insulation film 212 is over-etched excessively, the depth of the via trench 213 becomes very small so that the via 218 becomes very thin. As a result, the distance between the lower and upper wiring layers 211, 219 become very small so that a short-circuit may occur due to an increase in a leak current.

Semiconductor device, wiring of semiconductor device, and method of forming wiring


A sheet thickness measuring device includes: an illumination unit that outputs a light that is illuminated into a stack of sheets from a first area defined on one of faces including a top face, a bottom face, and side faces of the stack of sheets; a detection unit that detects a light amount distribution of light entered into the stack of sheets and propagated to a second area through the stack of sheets, the second area defined on one of the side faces of the stack of sheets; and a calculation unit that calculates a thickness of a sheet in the stack of sheets based on the light amount distribution detected by the detection unit.

In a printer, such as a laser printer, which prints an image on a sheet including various types of sheets such as cardboard, copying sheet and OHP films, information on a thickness and type of the sheet is required for optimizing various conditions for printing and fusing processes. Conventionally, such information specifying a type of sheet subjected to the print out is manually input by a user. However, such manual input deteriorates convenience for the user. Accordingly, a technique is desired, which automatically determines a type of a sheet with high accuracy before starting to feed and convey the sheet for the print out.
A conventional device for optically measuring a sheet thickness in a state where the sheets are stacked on a tray in the printer, which will be referred to as an optical sheet thickness measuring device, will be described. The optical sheet thickness measuring device measures the thickness of the sheet in a state where two or more sheets are stacked on top of one another before the sheets are conveyed. An example of such device is disclosed in JP-A-2005-104723.
As a main configuration, the conventional optical sheet thickness measuring device stores the sheets in a state where two or more sheets are stacked and aligned on a tray and illuminates a side face of the stack of sheets by a light source from obliquely above or from obliquely below in order to emphasize irregularity at the side face of the stack of sheets. A light reflected from an area where directly illuminated by the light source is captured by a light receiving element, and a peak-to-peak distance is calculated from a wave pattern of the received light regarding brightness and darkness that are caused by the stacked sheets, thereby obtaining the thickness of the sheet. Since a light intensity of the reflected light is large at edges of the sheets and the light intensity of the reflected light is small at gaps between the sheets, there appears a lower peak at the gaps in light amount.
However, when only the light reflected by the directly illuminated area of the side face of the sheet stack is captured, it is difficult to obtain from the peak such contrast that is sufficient to find the accurate thicknesses of the respective sheets. And there is a possibility that a thickness of two or more sheets instead of single sheet is detected, causing it difficult to detect the accurate thickness of the sheet. Also, since the thickness of each individual sheet ranges from 60 μm to 300 μm, the thickness of two or more sheets may be erroneously detected as the thickness of thick sheet if the sheet thickness is reliably detected.

Sheet thickness measuring device and image forming apparatus


A system (10) and method for removing heat from an engine compartment in a motor vehicle where heat generated by operation of a heat engine (12) that propels the vehicle tends to collect. Engine heat is collected in a thermofluid in a reservoir forming an evaporator (14) where the thermofluid absorbs heat sufficient to evaporate it. The vapor naturally migrates to a condenser (22) that is cooled sufficiently to condense the vapor back to liquid phase. The liquid falls by gravity back to the condenser.

The nature of the thermodynamic cycle on which a heat engine operates requires that heat of combustion be rejected to a waste heat medium. In an air-cooled engine, the medium is air that surrounds the engine. In a liquid-cooled engine, the medium is liquid that circulates through coolant passages in the engine where it is heated before passing to a radiator where the heat is transferred to air that flows through the radiator, although some amount of heat is also rejected directly to air surrounding the engine by radiation and convection.
A motor vehicle typically houses the engine in some sort of a compartment. Most cars and trucks have a front engine compartment that is bounded frontally by a front end structure that includes the radiator and rearwardly by the occupant compartment, or cab. The sides of the engine compartment are bounded by fender structures, and the top by a hood that can be opened to provide access to the engine compartment.
Underhood temperature is a matter of concern to vehicle designers because excessively high temperatures can have adverse effects on the performance and durability of various devices and systems. Space within an engine compartment is often at a premium, and the more crowded an engine compartment becomes, more components are exposed to engine compartment heat, and the movement of air through the engine compartment that can aid to some extent in limiting underhood temperatures becomes more difficult.
Engine operating temperature is affected by various factors. Higher operating temperatures may be necessary in order to enable compliance with relevant emission control regulations. That can add to engine compartment heating.
The cooling system of a liquid cooled engine is typically sized to allow the engine to operate at a desired engine operating temperature, but even when a cooling system is sized to accommodate higher engine operating temperatures, more engine heat is transferred by convention, conduction, and/or radiation to devices in the engine compartment, to the structure bounding the engine compartment, and to air in the engine compartment, and that heat isn't removed by the liquid cooling system. Moreover, placement of a radiator in certain vehicles causes at least some of the engine heat that is rejected at the radiator to pass through the engine compartment.

Thermosyphon heat reduction system for a motor vehicle engine compartment

International Truck Intellectual Property Company, LLC


An apparatus for reducing noise of a gear pump through uneven pitch-simulated control includes a calculation unit to calculate different control current values for each tooth of a teeth order by applying a teeth number, the teeth order, and a teeth angle of the gear pump in which a plurality of teeth are evenly formed, a storage unit to map and store the teeth order and the different control current values corresponding to the teeth order for each tooth, and a current controller to variably generate the control current value mapped corresponding to the teeth order when each tooth reaches a reference position when the gear pump rotates by a motor, wherein the control current value is added to a reference current value of a motor control signal and applied to the motor.

Generally, if a plurality of blades installed in an exterior circumference of an impeller is evenly disposed, there is a problem that noise is generated in a frequency band corresponding to the number of the blades when the impeller is operated.
To solve the above problem, conventionally, a method in which the blades are disposed at an uneven pitch arrangement is used, thereby reducing sound pressure and minimizing a pulsation sound (e.g., a low frequency peak) generated by the blades being unevenly disposed has been proposed.
However, in the case of an electric hydraulic pump, since two gears are engaged, the teeth of the gear must be disposed evenly. Therefore, it is not possible to apply the uneven pitch gears to the electric hydraulic pump. Further, there is a problem that noise is generated in a frequency band corresponding to the number of teeth when the electric hydraulic pump is operated.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Conventional technology is disclosed in Korea Patent Laid-open 10-0872294 (Dec. 5, 2008) and U.S. counterpart Pub. No. 2010/0054949.

Apparatus for reducing noise of gear pump through uneven pitch-simulated control and method thereof


Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.

1. Field of the Invention
This invention relates to a hetero-semiconductor structure possessing an SOI structure containing a silicon-germanium mixed crystal and a method for the production thereof at a low cost with high productivity.
2. Background Art
In recent years, a method for effecting high speed operation of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) integrated circuits by utilizing a technique called "strained silicon" has been attracting attention. The strained silicon technique consists in enhancing the mobility of electrons or positive holes as the carrier in the channel of the MOSFET by utilizing a silicon layer deformed so as to increase the lattice constant.
To increase the lattice constant of the silicon layer used for the channel, numerous methods for disposing a silicon-germanium mixed crystal adjacent to the pertinent silicon layer have been proposed, as disclosed in JP-A 6-252046, for example. These conventional methods are characterized by depositing a silicon-germanium film by vapor phase deposition on a silicon wafer and thereafter depositing a silicon layer, again by vapor phase deposition. Since the lattice constant of germanium is 4% larger than that of silicon, by controlling the compositional ratio of silicon-germanium mixed crystal, it is possible to impart the necessary strain to the channel layer. More often than not, the proportion of germanium is selected to be in a range of 10-30 mol %.
This strained silicon technique may be used in combination with the so-called SOI (Silicon On Insulator) structure, this combination then known as SGOI (Silicon-Germanium On Insulator). The latter combination can be produced by bonding a first substrate prepared by depositing a multilayer film containing a silicon-germanium mixed layer by vapor phase deposition, and a second substrate furnished with an oxide film, and then removing the first substrate to a certain depth by polishing or etching, as disclosed in JP-A 10-308503. This technique is thus a combination of the SOI technique and the strained silicon technique. Combination with a SIMOX (Separated by IMplanted OXygen) technique (JP-A 4-264724), another typical method for the production of SOI wafers, has also been proposed. For example, a method for forming a buried oxide film in a silicon-germanium mixed crystal layer by depositing a silicon-germanium mixed crystal on a silicon substrate and thereafter implanting oxygen ions and subsequently subjecting the resultant composite to a high temperature heat treatment is proposed in JP-A 9-321307. JP-2001-148473 discloses a method for producing an SGOI wafer possessing a high germanium concentration by the so-called ITOX technique, i.e. by decreasing the thickness of the SOI film by oxidizing the film at high temperature, thereby increasing the germanium concentration in the SOI film.
U.S. Pat. No. 4,975,387 discloses a method for forming a silicon-germanium surface layer by depositing an amorphous silicon-germanium layer on a silicon substrate and oxidizing the resultant composite in an atmosphere of steam.
Production of silicon-germanium mixed crystals by the zone method from a silicon raw material doped with germanium has also been proposed. JP-A 8-143389, for example, discloses a method for forming a bulk single crystal by adjusting the germanium concentration in a liquid phase, thereby controlling the concentration of germanium in the solid phase. These conventional methods of production, however, have entailed numerous problems.
Specifically, when a technique such as that disclosed in JP-A 6-252046 is employed, the silicon-germanium mixed crystal layer intended to impart strain must be sufficiently relaxed until the lattice constant assumes a magnitude conforming to the inherent composition. The relaxation of lattice must be relied on for generation of dislocations. When the dislocation thus generated extends to the region used by the relevant device, it may induce the device to malfunction. Various measures have been proposed to safeguard against this danger. One of the methods, as disclosed in JP-A 6-252046 and JP-A 5-129201, comprises depositing a so-called graded buffer layer, i.e. a layer wherein the compositional ratio of germanium gradually increases during the formation of a silicon-germanium mixed crystal layer by vapor phase deposition, thereby preventing the dislocation from threading to the surface layer. Attaining the necessary compositional ratio of germanium by this technique necessarily results in deposition of thick films, markedly impairing productivity, and heightening the cost of production as a result. U.S. Pat. No. 6,039,803 discloses inclining the main orientation of the silicon substrate by 1-8 degrees from the normally adopted direction of <100>. However, even the use of this method cannot be expected to attain sufficient inhibition of dislocation, since this method entails the problem of requiring deposition of a graded buffer layer.
The combination of the SOI structure and the strained silicon technique which is disclosed in JP-A 9-321307 and JP-2001-148473 does not require formation of a thick silicon-germanium mixed crystal layer as described above. However, the process still requires deposition of a silicon-germanium mixed crystal layer, necessitating a complicated process of production, and heightening the cost of production.
A method for forming an epitaxial layer by depositing an amorphous silicon-germanium layer and subsequently oxidizing the deposited layer in an atmosphere of steam as disclosed in U.S. Pat. No. 4,975,387 requires a separate apparatus for the growth of the amorphous film. Most amorphous film forming devices are susceptible to contamination with impurities. This method, therefore, is not a satisfactory process for the production of wafers for use in high-speed devices desired for present and future production.
Growth of silicon-germanium mixed crystals by the Czochralski technique or by the zone melting technique disclosed in JP-A 8-143389 necessitates a large amount of a germanium raw material. Since the germanium raw material is expensive, the production of a crystal having such a high germanium concentration in the range of 10-30 mol % required for a strained silicon substrate has only little merit commercially. Further, an attempt to grow from a liquid phase a single crystal containing germanium at such a high concentration is technically difficult because growth tends to produce dislocations.

Semiconductor substrate and method for production thereof


Disclosed is an improved artificial liver comprising a static liver-slice culture apparatus which is much more effective than a conventional hepatocyte bioreactor in removing toxins present in the plasma of a patient suffering from hepatic failure.

Acute hepatic failure resulting from a variety of causes has been reported to afflict approximately 2,000 pediatric and adult patients per year in the United States (Berk, P. D. and Popper, H., American Journal of Gastroenterology, 69, 349-400(1988)). In spite of the understandings gained by determining the inciting etiology in 60-80% of hepatic failure cases, treatment of this disease still focuses on patient stabilization and expectant management until either the patient's liver recovers or liver transplantation is carried out. It is reported that liver transplantation has increased the survival rate of fulminant hepatic failure patients from less than 20% to greater than 50% (Tygstrup, N. and Ranek, L., Seminar Liver Disease, 6, 129-137(1986)); Schafer, D. F. and Shaw, B. W. Jr., Seminar Liver Disease, 9,189-194(1989); Campbell, D. A. Tr. et al., American Surgeon, 8, 546-549(1991); Isai, H. et al., Transplantation Proceeding, 24, 1475-1476 (1992)).
However, it is difficult to obtain a timely donor liver, and a patient waiting for a donor liver requires an extracorporeal liver support system until a new liver is procured. Such system renders the patient stable and increases the survival rate after the transplantation.
For many years, it has been assumed that the vast majority of toxins which cause hepatic coma are small dialyzable molecules. As a result, most liver support systems and therapeutic regimens used in the past have relied mainly on blood detoxification. However, the pathogenesis of acute hepatic failure is complex and many investigators have suggested that isolated viable hepatocytes be used in the construction of a liver support system not only to provide detoxification but also to restore missing synthetic functions of the liver. In line with this suggestion, a conventional artificial liver has been designed based on the use of a bioreactor containing isolated living hepatocytes packed typically in hollow fiber membranes.
Although isolated hepatocytes used in the conventional bio-reactor exhibit some desirable effects arising from intercellular interactions thereamong, such effectiveness is limited due to the lack of cell to connective interactions which characterize the liver in its in vivo state. Therefore, the conventional artificial liver has been found to be only marginally effective in various clinical studies. Accordingly, an artificial liver device comprising liver slices or tissues has been proposed by some investigators (Nose, Y. et al., ASAIO Trans., 358-362(1963)); Soyer, T. et al., Surg. Forum, 23, 346(1972); Soyer, T. et al., Am. J. Surg., 126, 20-24(1973); Kimura, K. et al., Artif. Organs, 4, 297-301(1980)), but the development of an efficient system based on the use of liver slices or tissues has not been successful, mainly due to difficulties in maintaining liver slices viable and functional in such a system.

Artificial liver composed of a liver-slice culture apparatus

Cheonggu Apt. 103-1306, #929 Mok 6-dong, Yangcheon-gu


A liquid crystal display module includes a bottom case; a backlight assembly on the bottom case; a liquid crystal panel on the backlight assembly; a top case covering peripheral portions of the liquid crystal panel; a main supporter having a frame shape and surrounding side portions of the liquid crystal panel; a plurality of guide ribs on an outer side of the main supporter; a driving PCB on the plurality of guide ribs and inclined such that a distance between the driving PCB and the outer side of the main supporter increases along a direction of the bottom case to the top case due to the guide ribs; and a COF film connecting the driving PCB to the liquid crystal panel.

1. Field of the Invention
The present invention relates to a liquid crystal display module.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a perspective view of a LCD module according to the related art.
Referring to FIG. 1, the LCD module 10 includes a liquid crystal panel 45, a backlight assembly 65, a main supporter 60, a top case 70 and a bottom case 15.
The bottom case 15 is located at the bottom of the LCD module 10. A reflector 20 is located on an inner surface of the bottom case 15. The backlight assembly 65 is located on the reflector 20. The backlight assembly 65 includes a plurality of lamps 30 parallel to one another, and a plurality of optical sheets 40 on the lamps 30. The plurality of optical sheets 40 includes a diffusion sheet 41, a prism sheet 42 and a protection sheet 43. The main supporter 30 has a rectangular frame shape and surrounds the plurality of optical sheets 40 and the liquid crystal panel 45. The main supporter 30 is coupled with the bottom case 15. The top case 70 is located at the top of the LCD module 10. The top case 70 covers peripheral portions of the liquid crystal panel 45 and is coupled with the main supporter 60 and the bottom case 15. A pair of lamp guiders 35 fixes both ends of the lamps 30. The lamp guiders 35 are coupled with the bottom case 50.
A gate driving PCB (printed circuit board) 54 and a data driving PCB 56 are coupled with the liquid crystal panel 45 using TCP (tape carrier package) technology. TCP technology uses a TAB (tape automated bonding) film which connects the driving PCBs 54 and 56 to the liquid crystal panel 45. However, it is difficult to make inner leads in the TAB film straight, and there thus is a limit to achieving the fine pitch required for high resolution.
To achieve the fine pitch, COF (chip on flexible printed circuit) technology has been suggested. COF technology uses a COF film on which gate or data driving chip is installed directly. The COF film has a double-layered structure without adhesives and copper lines in the COF film are very thin, for example, 8 μm, and the fine pitch is thus feasible. Accordingly, the COF film is employed in high resolution LCD devices.
However, as the size of the LCD module has recently increased, due to material property and elasticity of the COF film connected to the liquid crystal panel, the liquid crystal panel is thus lifted up off a correct position. Accordingly, the LCD module is defective, and production efficiency is reduced.
FIG. 2A is a perspective view illustrating a portion of the LCD module according to the related art, and FIG. 2B is a perspective view illustrating a portion of the main supporter of the LCD module according to the related art.
Referring to FIGS. 2A and 2B, the liquid crystal panel 45 is placed on an inner peripheral portion of the main supporter 60. A plurality of COF films 80 connect the data driving PCB 56 to the liquid crystal panel 45. The COF film 80 is bent at about 90 degrees angle along an outside of the main supporter 60, and the data driving PCB 56 is thus placed on the outer side of the main supporter 60.
A plurality of moving obstacles 85 are installed on a side frame of the main supporter 60. The moving obstacle 85 functions to prevent the liquid crystal panel 45 from moving away in a horizontal direction and fix the liquid crystal panel 45 at a right position.
The large-sized LCD modules, for example, of 19 inches or more may have a problem that the liquid crystal panel 45 is lifted up due to the elasticity of the COF film 80 after an assembling process while the smaller-sized LCD modules seldom have the problem.
FIG. 3 is a view illustrating the problem that the liquid crystal panel of the LCD module according to the related art is lifted up.
Referring to FIG. 3, the backlight assembly (65 of FIG. 1) is coupled with the main supporter 60, then the liquid crystal panel 45 and the data driving PCB 56 are placed on the main supporter 60, then a gasket 90 is coupled with an outer side of the data driving PCB 56, then the top case (70 of FIG. 1) is assembled, and thus, the LCD module is completed. The gasket 90 functions as a buffer to prevent the data driving PCB 56 from being damaged due to an external impact or pressure in an assembling process. For example, the gasket 90 is made of a styrofoam.
The COF film 80 is bent at about a 90 degree angle by a worker's applying a force to the COF film 80. After the COF film 80 is bent and the gasket 90 is located on the data driving PCB 56, the top case is assembled. When the top case is assembled, the gasket 90 is pressed by a force, for example, the top case, and the data driving PCB 56 is thus closely attached to and fixed to the main supporter 60. Sine the data driving PCB 56 is closely attached to the main supporter 60 due to pressing the gasket 90, the COF film 80 is warped. In other words, the data driving PCB 56 goes toward the main supporter 60 due to pressing the gasket 90, and thus, the data driving PCB 56 changes in position between before assembling the top case and after assembling the top case. This position change of the data driving PCB 56 causes the COF film 80 to be warped. As the LCD module increases in size, and the COF films 80 in the LCD module increase in number. Accordingly, in the large-sized LCD module, the elastic force of the COF films 80 due to the warpage of the COF films 80 is large so that the liquid crystal panel is lifted up by a distance "F".
As described above, the problem of abnormally moving the liquid crystal due to the elastic force of the COF films occurs in the assembling process, and the production efficiency is thus much reduced.


A noise suppressor includes a first differential-mode transmission module, a second differential-mode transmission module and a common-mode absorption module. The first and second differential-mode transmission modules are configured to receive a differential signal at one of the first and second differential-mode transmission modules, and output the differential signal at the other of the same. The common-mode absorption module is electrically connected to a reference node, and is configured to absorb common-mode noise of the differential signal from at least one of the first differential-mode transmission module or the second differential-mode transmission module.

Differential transmission is widely used in high speed digital transmission systems. However, in real systems, signal energy experiences transition from differential mode to common mode because of unfavorable reasons such as vias existed in the circuit board, and traces on the circuit board that are asymmetric in structure, or that are mismatched in length. Therefore, common-mode noise is generated, and radiation interference appears on interior and exterior of the systems. Conventional common-mode noise suppressors, which suppress common-mode noise by reflecting the same, may be utilized to reduce radiation interference.
Referring to FIG. 1, a conventional reflective common-mode noise filter 1 for use in a high speed digital transmission interface transmits a differential signal and reflects common-mode noise. However, when the high speed digital transmission interface is electrically connected to another circuit element of a peripheral module, such as a wireless transmitter, the reflected common-mode noise may flow to the circuit element and cause interference thereto.


Disclosed herein is a device includes: a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and outputting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and outputting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.

1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device, and more particularly relate to a semiconductor device including a level shift circuit that converts the voltage amplitude of a signal.
2. Description of Related Art
Some semiconductor devices include a level shift circuit that converts the amplitude of a signal. There are two types of the level shift circuit, one of which is designed to decrease the signal amplitude and the other is designed to increase the signal amplitude. Among the two types, the level shift circuit designed to decrease the signal amplitude can foe configured by a simple inverter circuit. This is because the amplitude of the input-signal is larger than the amplitude of the operating voltage of the inverter circuit, and therefore at either logic level of the input signal, one of the transistors that constitute the inverter circuit can be reliably switched to the off state.
On the other hand, when the level shift circuit designed to increase the signal amplitude is configured by a simple inverter circuit, one of the transistors that constitute the inverter circuit cannot foe reliably switched to the off state depending on the logic level of the input signal. This causes a leak current. Therefore, in the level shift circuit designed to increase the signal amplitude, a circuit method as described in Japanese Patent Application Laid-open No. 2001-36388, in which two cross-coupled transistors are used, and an input signal and its inverted signal are used to turn on either one of the transistors, is mainly employed.
However, in the level shift circuit described in Japanese Patent Application Laid-open No. 2001-36388, there is sometimes a difference between the timing at which an output signal is changed in response to a change of an input signal from a first logic level to a second logic level and the timing at which an output signal is changed in response to a change of an input signal from the second logic level to the first logic level. When there is the difference between the timings as described above, it causes a difference in duty ratio between the input signal and the output signal. Therefore, a problem arises, for example, in that the effective width (window width) of read data is decreased,

Semiconductor device having level shift circuit


A system and method in a combined cycle power plant includes a processor modeling plant level performance by considering the interrelation between outputs of the gas turbine and the steam turbine. The model can be computational, predictive, or both. The model may be used to control subsystems of the plant (including the gas turbine and the steam turbine) to achieve a target plant performance. The model may also be used to diagnose or maintain subsystems of the combined cycle power plant.

A combined cycle power plant uses both gas and steam turbines to generate the total plant power output. The gas turbine may be considered the primary power source. Exhaust (waste heat) from the gas turbine is used to generate steam that powers the steam turbine, which generates additional power as a secondary source. Existing systems control operation of the gas turbine, the steam turbine, or other plant subsystems to affect plant performance without considering the interrelationship between the gas turbine and the steam turbine. Further, existing systems do not consider the interrelationship between the gas turbine and the steam turbine or the overall plant operations in assessing problems or in maintaining subsystems.

System and method for controlling and diagnosing a combined cycle power plant


Heat exchanger comprising at least a first plate (11) and at least a second plate (12) overlapping and reciprocally joined to each other in correspondence with respective coupling surfaces (13).

Plate-type heat exchangers used, for example, as refrigerating or evaporator plates are known, inside which a heat-carrying fluid, gaseous or liquid, is made to pass.
Compared to other types, plate-type heat exchangers have a reduced thickness, a large heat exchange surface, a better heat exchange coefficient, as well as simplified maintenance operations, in order to satisfy particular application requirements from the point of view of sizes, costs and practicalities.
These known heat exchangers, an example of which is shown in the attached FIG. 1, comprise two or more plates 101 overlapping and joined to each other by means of heating and/or rolling methods, that is, by means of the technique also known as "Roll Bond", an example of which is described in document U.S. Pat. No. 2,690,002.
This production technique provides that detaching material 102 is deposited on at least one of the two plates 101 to be joined according to a predefined pattern coordinated with the shape of passage channels 103 to be obtained, in order to define the transit circuit of the heat-carrying fluid. The detaching material 102 is deposited starting from at least one peripheral edge 104 of the two plates 101.
Subsequently, the two plates 101 are made to overlap each other and to pass through at least one pair of rolling rolls/cylinders. Before and/or during rolling, the two plates are also heated to a temperature lower than their melting temperature.
The rolling action allows to weld the two plates together on the entire surface of reciprocal contact, except for the surface portions affected by the detaching material.
Subsequently, in proximity to at least one peripheral edge 104 of the plates 101, and where a portion of detaching material 102 is present, at least one slit 105 is made between the two plates 101 suitable to house a device to deliver compressed air. The pressure of the air that is delivered has to be high enough to deform at least one of the two plates, in correspondence with the detaching material 102 and along the entire deposition path thereof. The deformation of at least one of the two plates 101 therefore allows to define the channels 103 intended for the passage of the heat-carrying fluid.
Furthermore, in order to allow the circulation of the heat-carrying fluid in the passage channels 103 defined above, it is known to make, on at least one of the lateral edges 104, at least one entry aperture and one exit aperture of the heat-carrying fluid. These entry and exit apertures, or at least one of them, can correspond substantially to the slit 105. Alternatively, the entry and exit apertures of the heat-carrying fluid are also obtained by depositing, before the rolling and in the desired position, the detaching material which subsequently, by deformation of at least one of the plates 101, allows to obtain the apertures.
Connection elements 106 are then associated to the apertures, for example by welding.
This mode of connecting the connection elements 106 in proximity to the peripheral edge 104 significantly limits the diameter that the connection elements can have, since they have be welded on the perimeter edge of the heat exchanger, or rather, this perimeter edge does not offer a large welding area and therefore cannot guarantee an adequate stability. Consequently, this limits the quantity of heat-carrying fluid that can be introduced into the heat exchanger, limiting the performance indexes thereof.
Furthermore, the particular mode of axial feed, substantially coplanar to the plates 101, of the heat-carrying fluid limits the flexibility of installation of the heat exchanger, since for some applications the presence of connection elements in proximity to the peripheral edges can be an obstacle to the installation.
There is therefore a need to perfect a heat exchanger, in particular a plate-type heat exchanger of the Roll-bond type, which can overcome at least one of the disadvantages of the state of the art.
In particular, the need is felt to provide a heat exchanger of the Roll-bond type that offers a solution that is effective, structurally stable and versatile with respect to the needs above.
US 2013/032319, WO 2014/154883, WO 217/190253 and US 2014/224452 all concern conventional plate-type heat exchangers, in which the individual plates and corresponding holes are obtained separately, for example by molding, therefore the application of possible connectors can occur at any step of the assembly procedure without involving particular production problems.
It is therefore a purpose of the present invention to provide a plate-type heat exchanger of the Roll-bond type which is particularly effective and versatile.
It is also a purpose of the invention to provide a heat exchanger in which the position of the connection elements is not constrained to the perimeter edges of the plates.
Furthermore, it is also a purpose of the present invention to provide a Roll-bond type heat exchanger which has higher performances than known solutions, in particular which offers improvements from the point of view of the heat exchange, of the feed of the heat-carrying fluid and the stability of the welds.
It is also a purpose of the present invention to reduce the load losses during the feed of the heat-carrying fluid into the heat exchanger.
The Applicant has devised, tested and embodied the present invention to overcome the shortcomings of the state of the art and to obtain these and other purposes and advantages.

Heat exchanger and corresponding production method

Abstract: Between the coupling surfaces (13), at least one passage channel (14) for a heat-carrying fluid is made, by deforming at least one of the two plates (11, 12).


The meter system of the present invention allows for automated water utility resource measurements, data collection and exercise of control and notification of fire hydrant water usage and includes: a portable water meter that is releaseably mountable onto a discharge nozzle of the fire hydrant; a flow sensor that senses the water flow rate passing therethrough the portable water meter; a processor that is configured to receive, process, and/or store data from the flow sensor; and a satellite positioning system that is adapted to receive satellite position determining signals. The hydrant meter system further includes a communication device that is adapted to transmit the processed flow signal and the processed positioning signal to a remote server system via a communication medium.

Utilities provide commodities such as electricity, gas and water to the public, preferably at the least possible cost to each consumer. However, each year utilities are subject to increasing costs due to distribution losses. While certain amounts of electricity, gas, water and other commodities are lost due to the technical limitations of the various distribution systems, large quantities of these commodities are stolen. These "non-technical distribution losses" are typically written off by the various utilities as unrecoverable due to a general lack of evidence available to prove energy theft. Unfortunately, such theft and losses have become an increasing problem for many utilities.
For water utilities, theft from fire hydrants for construction projects and the like is an increasing problem. Frequently, a discharge nozzle cap of a conventional fire hydrant is removed from the bonnet of the hydrant and a control valve is moved to the open position by a non-utility person to allow water flow from the fire hydrant. This theft poses a public health and welfare threat as the municipality's primary water source for the community can be reduced below safe levels. For example, an open flowing fire hydrant causes a significant decrease in the pressure of the water supply main. This results in an inability to fight fires within an entire section or loop part of the supply main grid as generally all of the nearby fire hydrants on that portion of the grid are rendered useless.
Automated meter reading for consumption rate of different utility resources such as water, gas or electricity has become more desirable compared to the methods using meters that require manual reading and recording of the consumption levels. One type of automated "local" means of collecting meter reading requires an operator to be in close physical proximity of the meter to obtain the meter reading, such as, for example by using touch read methodologies, and transporting the data to a central computer.
Another type of automated meter reading is based on collection of data by telephone lines or radio transmission. The meter reading, in both cases, may be collected through the phone lines connected to the meter, i.e., phone read, or communicated to a portable hand-held computer. The radio based meters, such as those provided in U.S. Pat. Nos. 4,652,877 and 4,782,341 issued to Gray and incorporated herein by reference, were more widely used since the reading could be collected as an operator drove by the meter (drive-by system), or in combination with the touch read system, be read manually. The radio read is particularly desirable in areas where the meter, specifically the water meter, is inside a pit at a distance from the building and away from a power source. However, in such systems, the antenna was disposed outside of the meter and was hardwired to the mechanical register through the meter housing so the signals passing from the register to the RF transmitter were not wireless.
In the noted methodologies, the collected data from each utility meter must be transported to a central computer and compiled for billing, statistical or any other services that the utility companies may provide to their customers. Each of the aforementioned automated meter reading techniques still requires a large amount of manpower and is susceptible to errors in entry and transportation of data. Moreover, the utility companies cannot exercise any control or provide notifications to their customers without using additional manpower, cost and potentially less reliable means of communication.
Conventionally, each utility meter is associated with a particular address to which utility companies associate the complied collected data from the particular utility meter. However, in the water utility market, fire hydrants are not associated with a specific billing address. Rather, they are spread about a water utilities supply grid in accordance with appropriate municipal code. Thus, stolen water from a fire hydrant is not typically captured and billed by conventional metering systems.
Typically, water utilities attempt to have using parties pay for the water that they use from the water supply grid by having the using party mount a portable fire hydrant meter onto the fire hydrant. Conventional portable fire hydrant meters operate on the basis of a mechanical odometer that identifies the consumption of the water consumed. These fire hydrant meters can use electronic reading of the odometer wheels. The odometer is typically read at the end of the job and the difference between the end-of-job reading and the initial reading determines the amount of utility water used. As one would expect, the user pays for the water used. The prior art fire hydrant meters provided no ability to restrict the amount of water consumed by the user. Further, they did not provide an ability to monitor the actual real-time consumption of water.
Consequently, a need exists for an improved system for automated water utility resource measurements, data collection and exercise of control and notification of water hydrant water usage.

Portable hydrant meter and system of use thereof


A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.

1. Field of the Invention
The present invention relates to a printed circuit board (PCB), and more particularly to a PCB having vias for reducing reflections of input signals.
2. General Background
In modern communications, transmission speed of signals has become quicker and quicker. Signal integrity refers to fidelity of signal curves. However, qualities of signals are often reduced because of signal reflection that is caused by discontinuity of impedance in transmission lines of the PCB.
More signal transmission layers are needed because of the increasing density of signal lines. So it is inevitable that the signal transmissions between different layers of a PCB should be achieved through conductive vias. Design of the conductive vias is crucial in the design of multilayer PCBs. The vias can be divided into three types according to their usage and process of manufacture. They are blind vias, buried vias, and through vias. The blind vias are usually located on a surface of the top layer or bottom layer of the PCB to connect signals between surface layers and inner layers. The buried vias are located in the inner layers, and the through vias penetrate through all the layers of the PCB to complete electrical connections among all the layers. When a connection between the vias and transmission lines is necessary, discontinuity of impendence of transmission lines affects the integrity of the signals.
Referring to FIG. 1, a conventional via of a PCB comprises a drill hole 11, a pad 13, and an anti-pad 15. The drill hole 11 is a through hole. The pad 13 is located at opposite signal layers. So there are two same pads 13. The anti-pad 15 is located at non-connective layers. Referring to FIG. 2, a circuit parameter module of a via comprises two capacitances C0, C1 and an inductance L. The magnitude of the capacitance C0 or C1 is affected by sizes of the pad and the anti-pad. The approximate capacitance of each pad 13 is determined according to the following formula:
  C  =            1.41                    ɛ        r                          D        1                  T                      D        2            -              D        1            Wherein ∈r is the dielectric constant of the PCB, T is the thickness of the PCB layers to which the via is connected, D1 is the diameter of the pad, D2 is the diameter of the anti-pad. Referring to FIG. 1, in the prior art, D10=D12. Effects of an equivalent capacitance are greater than that of the inductance, therefore, the impedance of the whole via is counted as follows:
      C          via                                      1        =                    C        10            +              C        12              =                  2        ×                  C          10                    =              2        ×                              1.41                                      ɛ              r                                                  D              10                                    T                                              D              20                        -                          D              10
In the designing process, the size of the via is designed to be smaller to reduce the stray capacitance of the via.
Commonly in the design process, diameters of the pad and the anti-pad of the via are reduced simultaneously. Thereby, the reflection of the input signals is reduced because of a reduction in a capacitance of the corresponding pad. However, the diameter of the pad connected with the output signals is reduced as well, which results in a reduction in reflection of the output signals, therefore, the error of the output signals is larger which affects the signal integrity of the output signals. When the signals are transmitted, the capacitance of the pad connected with the input signal lines is large, so the impedance of the pad is small nearly to the point of being a short circuit, however, the signal lines have a certain impedance. Therefore, the impedance of the transmission lines are discontinuous, and large reflections are caused.
What is needed, therefore, is a PCB having vias designed for reducing the reflections of input signals.

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.