A hot-wire type flowmeter for measuring a flow rate of a fluid in a passage comprises a pair of support pins extending in parallel with an axis of the passage and an electrical resistor supported between the support pins in the passage. The resistor includes a pipe made of an electrically insulating material, a resistor wire wound on the pipe, and a pair of lead wires. The lead wires are secured to opposite end portions of the pipe and extend in opposite directions and in parallel to each other. The resistor is supported by the support pins through the lead wires.

The present invention relates to a hot-wire type flowmeter which is suitable for use in measuring intake air flow rate in an internal combustion engine.
Flow rate measuring systems are known in which flow rate of a fluid in a main passage is determined by sensing the flow rate in a by-pass passage through which a part of fluid flowing in the main passage flows at the predetermined ratio. This type of system is disclosed, for example, in Japanese Patent Unexamined Publication No. 57-105551, Japanese Utility Model Unexamined Publication No. 56-163668 and U.S. Pat. No. 4,709,581.
In this type of flow rate measuring system having a by-pass passage, the by-pass passage rejoins the intake passage at the narrowest portion of a restriction or orifice provided in the intake passage. Therefore, air is introduced into the by-pass passage, an amount of which corresponds to the air flow in the intake passage, by virtue of the pressure difference generated in the restriction in the intake passage.
Meanwhile, Japanese Unexamined Publication No. 55-48614 discloses a hot-wire type flowmeter in which flow velocity of fluid is measured by making use of the fact that a quantity of heat transferred from a heated electrical resistor wire to the flowing fluid is varied in accordance with the flowing velocity of the fluid.
Electrical resistors for use in hot-wire type flowmeters of the kind described are disclosed, for example, in Japanese Patent Unexamined Publication No. 59-104513, Japanese Patent Unexamined Publication No. 59-151020 and U.S. Pat. No. 4,793,176. These electrical resistors generally have a pipe made of, for example, ceramics, and a platinum wire wound around the pipe and connected at its both ends to lead wires which extend axially through an axial bore in the pipe.
In this type of electrical resistor, both end portions of the platinum wire are beyond both longitudinal end edges of the pipe so as to be connected to the lead wires. The platinum wires tends to slip on these edges and, hence, is liable to be cut, resulting in an inferior productivity
In general, a hot-wire type flowmeter of the type exhibits a higher sensitivity or quicker response to a change in the fluid flow rate or temperature when the heat insulation between the electrical resistor which is to be hot and the associated members of normal temperature is enhanced. Elongating the lead wires on both ends of the electrical resistor is an effective measure for enhancing the above-mentioned heat insulation. As a matter of practice, however, the length of the lead wires is limited because the size of the fluid passage in the flowmeter is limited and because the electrical resistor has to be disposed perpendicular to the flow of fluid in such a restricted passage.
Japanese Patent Unexamined Publication No. 59-104513 discloses an electrical resistor in which lead wires are orthogonally bent to have greater length. This arrangement, however, impairs the mechanical strength of the lead wires.
Japanese Patent Unexamined Publication No. 62-127632 discloses a hot-wire type flowmeter in which an electrical resistor is connected between a pair of lead lines which extend along the fluid passage, in such a manner that the electrical resistor extends across the path of the fluid in the fluid passage. This flowmeter also is impractical because its construction is complicated.


An intake manifold is manufactured by assembling resin-molded parts without using any cores, so that compactness, light-weight, low-cost and improvement of engine performance can be achieved. A inner pipe is fit-inserted into a cylindrical tubular part of an outer pipe, thereby a outer pipe support is fixed on. By fitted parts, a positioning of a direction of circumference of the outer pipe and the inner pipe is performed. The air from a inlet flows into a sarge tank through a throttle valve. Afterward, the air flows from a manifold passage inlet to a manifold passage so as to lead to intake ports of engine cylinders by passing from a straight passage through an outlet.

1. Field of the Invention
The present invention relates to internal combustion engines and particularly to an intake manifold for multi-cylinder engines, an intake control unit utilizing the intake manifold and an intake manifold manufacturing method.
2. Description of Related Art
Utilizing the so-called intake inertia effect is an effective technique for improving performance in automotive internal combustion engines by increasing the air intake efficiency. However when the cross sectional area of the intake passage is fixed, the length of the intake passage at which maximum effect is delivered, becomes shorter as engine speed increases.
A method is publicly known in the conventional art in Japanese Laid Open Patent 60-216064 proposing cylindrical rotary valves operating according to engine speed and an intake control unit to distribute the required air for combustion in spiral intake passages in the same number of engine cylinders and enclosing the periphery of the rotary valves.
This intake control unit has a cylindrical casing mounted coaxially with the rotary valve at the periphery of the rotary valve. At the upper part of the casing, branch pipes equal in number to the engine cylinders are provided. These branch pipes are fixed on the cylinder head and connected with the intake port of the engine cylinder. As a result of this, an air intake system is constructed such as the air flows into each engine cylinder through the rotary valves and the spiral intake passages.
However, in the technology of the related art, the cylindrical casing provided on the periphery of the rotary valve and the plurality of branch pipes diverging from the casing were integrated with as a piece of intake manifold. Also, since each branch pipe provided a spiral intake passage enclosing the periphery of the rotary valve, core melting molding was utilized for producing the casing and the branch pipe into one piece. Especially, in order to achieve a light-weight of vehicle, it has been required that the above-mentioned parts are to be resinification.
However, the core melting molding needed for manufacturing the case and branch pipes (in other words, the intake manifold) had the drawback of requiring core production or troublesome melting processes after molding of the core. Therefore, it resulted in the disadvantage that the manufacturing process was not convenient.
In addition, another problem was that the intake inertia effect was unsatisfactory since air leaks occurred from the gap needed for rotary valve rotation.

Multi-cylinder engine intake manifold, intake control unit using that intake manifold and manufacturing method


A vacuum degassing and solvent delivery apparatus for those solvents being utilized in high pressure liquid chromatographic operations and/or applications. The degassing and delivery apparatus of the present invention is designed for attachment directly to a solvent reservoir, such as a double-ended bottle having a threaded portion along the bottom end thereof. The arrangement facilitates ease of installation and removal of the vacuum degassing, recycling and delivery apparatus so as to accommodate a variety of installation applications and requirements. The solvent degassing system of the present invention further includes the utilization of an atmospheric impermeable composite tubing structure which is effective for isolating fluids from atmospheric contamination during transport.

The present invention relates generally to an improved vacuum degassing, recycling and solvent delivery apparatus for solvents utilized in high pressure liquid chromatographic operations and/or applications, and wherein the solvent degassing, recycling and delivery apparatus is adapted for removable retention on a solvent reservoir, and wherein the system is essentially self-priming. The vacuum degassing solvent treating arrangement of the present invention is particularly designed for use in those systems wherein portions of the solvent being utilized are recycled back to the original supply reservoir and where degassing is necessary for solvent use. The solvent degassing system of the present invention further includes, as a feature, the utilization of an atmospheric impermeable composite tubing structure which is effective for isolating fluids from atmospheric contamination during transport.
The present invention is an improvement over the vacuum degassing systems disclosed in U.S. Pat. No. 5,340,384 (Sims), and that system disclosed in copending application Ser. No. 08/688,439, both of which are assigned to the same assignee as the present invention. The content of U.S. Pat. No. 5,340,384 and application Ser. No. 08/688,439 are incorporated by reference herein. While the systems disclosed in the U.S. Pat. No. 5,340,384 patent and application Ser. No. 08/688,439 function well, the present arrangement provides an advantage in terms of versatility in use and also in priming of the system.
One of the analytical chemical operations which involves the use of liquid solvents in which dissolved gases, particularly air, is detrimental and undesirable is high pressure liquid chromatography (hereinafter referred to as HPLC). In HPLC applications, the presence of small quantities of dissolved gases interferes with the accuracy and indeed the total sensitivity of the system and its operation. Furthermore, if the dissolved species is chemically reactive, such as oxygen from dissolved air, the quality of the liquid solvent is adversely affected. As the quantity of the dissolved species increases, the adverse affect likewise increases. Thus, in order to avoid these undesirable side effects, the dissolved species are typically removed by one or more degassing operations. The overall operation, particularly the HPLC operation, is rendered far more efficient when degassing can be undertaken expeditiously and without incurring additional or significant delays. Additionally, the system of the present invention utilizes a form of atmospheric impermeable composite tubing which effectively transports the liquid solvents through the system so that the solvent is isolated from potential contaminants such as the oxygen component in ambient air.
In the past, various techniques have been employed for removal of dissolved gases from HPLC solvents. These included heating of the liquid or alternatively, subjecting the solvent liquid to a reduced pressure or vacuum. Exposure of the solvent to a source of ultrasonic energy has also been employed. Degassing involving the passing of a fine stream of an inert gas such as helium or the like through the solvent has also been utilized in the past. Helium degassing and/or sparging has certain disadvantages including the selective removal of certain volatile components of mixed solvents, and furthermore requiring the presence of large vessels for the helium supply. Membrane apparatus has been successfully employed for vacuum degassing of HPLC solvents.
In certain HPLC applications, it is desirable to employ a degassing apparatus which has been thoroughly cleaned and the presence of even trace amounts of any previously employed solvent have been eliminated. In accordance with a feature of the present invention, a quick changeover vacuum degassing device has been developed which is adapted for removable retention on a solvent reservoir, particularly a bottle having a threaded opening along its bottom or base. The degassing device includes a threaded means for engaging the base threaded opening of the reservoir or bottle, with the degassing system being conveniently confined within a shrouded zone forming a vacuum chamber for housing and retaining the degassing tubing. The inlet to the reservoir is preferably arranged and disposed in the upper end of the double-ended bottle, and for purposes of accommodating flow, a vent hole may be positioned in the cap area accommodating the inlet tube. Thus, by simply engaging the threads and screwing the attachment mechanism onto the base of the bottle, the vacuum degassing and recycling apparatus of the present invention is expeditiously placed into the system for operation. Also, the apparatus of the present invention contains means for readily receiving and coupling tubing of the type typically utilized in HPLC applications, and further includes the utilization of atmospheric impermeable composite tubing which effectively isolates the solvent, particularly solvent which has been previously degassed, from exposure to atmospheric contaminants. Additionally, an integral valve structure is conveniently incorporated into the degassing mechanism.

Solvent receptacle and degasser for use in high pressure liquid chromatography


In a method for producing an SOI wafer comprising steps of implanting ions from a bond wafer surface to form an ion-implanted layer inside the wafer, bonding the ion-implanted bond wafer surface and a surface of a base wafer via an oxide film or directly, and forming an SOI wafer by delaminating by heat treatment a part of the bond wafer at the ion-implanted layer, the bond wafer is a silicon wafer that consists of a silicon single crystal grown by Czochralski method, that is occupied by N region outside OSF generated in a ring shape and that has no defect region detected by Cu deposition method. Thereby, even an extremely thin SOI layer having a thickness of 200 nm or less, can provide an SOI wafer that has an excellent electric property without micro pits caused by acid cleaning, and can be produced without increasing the number of processes.

Conventionally, as a substrate for a device, an SOI wafer wherein a silicon active layer (an SOI layer) is formed on a support substrate has been widely utilized. As a method for producing such an SOI wafer, for example, it is known that a bonding method in which two silicon wafers are bonded together via an oxide film. In ion implantation delamination method which is one of bonding methods, an oxide film (an insulator layer) is formed on a surface of a silicon wafer (a bond wafer) to be a silicon active layer or a base wafer to be a support substrate, and an ion-implanted layer is formed inside the bond wafer by implanting ions such as hydrogen from one side surface of the bond wafer. Further, after this bond wafer is bonded to the base wafer via the oxide film, delamination is performed at the ion-implanted layer by heat treatment. Thereby, an SOI wafer in which a thin silicon active layer is formed on the base wafer via the oxide film can be obtained.
Further, there are also some cases that an insulator support substrate is used and a bond wafer is bonded to this directly, i.e., without an oxide film.
In the case of producing an SOI wafer as described above, a silicon wafer on the surface of which micro pit defects with 50 nm or more in size exist has been generally used as a bond wafer. However, in recent years, the demand for thinning the silicon active layer increases, and the demand for quality of a silicon wafer applicable to this has also become strict.
In order to reduce defects in the silicon active layer, there has been proposed the use of an epitaxial layer or a silicon single crystal in so-called a neutral region (N region) where there exist no defects caused during growth of the single crystal which is called grown-in defects such as FPD, LSTD and COP.
For example, there has been proposed a method for producing an SOI wafer by forming an epitaxial layer on a silicon wafer (a bond wafer), implanting boron ions into the epitaxial layer, subsequently bonding the wafer to a support substrate via an oxide film, and further grinding and polishing the back surface of the bond wafer (for example, see Japanese Patent Laid-open (Kokai) No. 10-79498 (on pages 4–6, in FIG. 2)).
However, in the case of using the wafer on which the epitaxial layer is formed as the bond wafer as described above, defects in the SOI layer can be improved, but there has been a problem that the production cost remarkably increases because the process for growing the epitaxial layer increases.
On the other hand, as a bond wafer, in the case of using a silicon wafer grown in N region where no micro defect such as FPD and COP exists, although it is required to accurately control growth conditions of a silicon single crystal, there is an advantage that process for forming the epitaxial layer is not needed.
N region will be explained herein. It is known that in the case of changing a growth rate V from high speed to low speed in the direction of a crystal growth axis in a CZ pulling apparatus with a usual furnace structure (hot zone: HZ) having a large temperature gradient G at the vicinity of a solid-liquid interface in a crystal, a defect distribution diagram as shown in FIG. 9 can be obtained.
In FIG. 9, V region is a region that contains a large amount of vacancies, i.e., depressions, pits, or the like caused by lack of silicon atoms, and I region is a region that contains a large amount of dislocations or clusters of excess silicon atoms caused by existence of excess silicon atoms. It has also been confirmed that there exists a neutral (hereinafter occasionally abbreviated as N) region that contains no (or little) lack or excess of the atom between V region and I region, and defects called OSF (Oxidation Induced Stacking Fault) are distributed in a ring shape (hereinafter occasionally referred to as OSF ring) near a boundary of V region when observed in the cross section perpendicular to a crystal growth axis.
When the growth rate is relatively high, there exist grown-in defects such as FPD, LSTD and COP, which are considered due to voids consisting of agglomerated vacancy-type point defects, at a high density over the entire radial direction of the crystal, and a region containing these defects becomes V region. Further, along with lowering of the growth rate, the OSF ring is generated from the periphery of the crystal. There exist at a low density outside the OSF ring, L/D (Large Dislocation: an abbreviation for interstitial dislocation loop, such as LSEPD, LFPD and the like) defects (huge dislocation clusters) which are considered due to dislocation loops consisting of agglomerated interstitial silicon atoms, and the region where these defects exist becomes I region (occasionally referred to as L/D region). When the growth rate is further lowered, the OSF ring shrinks to the center of the wafer and disappears, so that the entire plane becomes I region.
N region located between the V region and the I region and outside the OSF ring becomes a region containing no FPD, LSTD and COP to be generated due to voids as well as no LSEPD and LFPD to be generated due to interstitial silicon atoms. In addition, it has been recently found that by further classifying N region, as shown in FIG. 9, there exist Nv region (the region where a lot of vacancies exist) adjacent to the outside of OSF ring and Ni region (the region where a lot of interstitial silicon atoms exist) adjacent to I region, and that when performing thermal oxidation treatment, a lot of oxygen precipitates are generated in Nv region and little oxygen precipitates are generated in Ni region.
Although such an N region conventionally existed only in a part of a plane of wafer, a crystal having N region over the entire radial plane (the entire surface of wafer) has been able to be manufactured by controlling V/G that is a ratio of a pulling rate (V) to an axial temperature gradient (G) at a solid-liquid interface.
Also, in the manufacture of an SOI wafer, as described above, there has been proposed a method in which a silicon single crystal wafer having N region over the entire surface is used as a bond wafer.
For example, there has been proposed an SOI wafer wherein a silicon single crystal is pulled by controlling a ratio of the pulling rate V to the axial temperature gradient G at a solid-liquid interface of the crystal (V/G) within a predetermined range when it is pulled by Czochralski method (CZ method), and the silicon wafer in N region is used as a bond wafer (for example, see Japanese Patent Laid-open (Kokai) No. 2001-146498 (on pages 5–8) and Japanese Patent Laid-open (Kokai) No. 2001-44398 (on pages 2–4, in FIG. 1)).
However, when performing oxidation treatment for bonding the bond wafer and the base wafer together and oxidation treatment for adjusting the thickness of an SOI layer, and subsequently cleaning with hydrofluoric acid to remove an oxide film, even if the silicon single crystal grown in N region is used as the bond wafer, there has been the case that a failure such that the SOI layer was almost entirely or partially destroyed could occurred. Especially, the failure as described above often occurs when a thinner SOI layer is formed. Also, in case that making an SOI layer thinner is further required in future, it is apprehended that the SOI layer may be remarkably degraded even if the silicon wafer grown simply in N region as above is used as a bond wafer and in addition, it is also expected that the quality of the insulator oxide film between the SOI layer and the base wafer may be deteriorated.

SOI wafer and a method for producing an SOI wafer


The present invention relates to peptides that can inhibit the infection of HIV, and more particularly, to peptides consisting of less than 30 amino acids which can introduce a helix capping motif into a peptide derived from C-terminal helical region (its 628-646th amino acid region) of gp41, an envelope glycoprotein of HIV, as well as consisting of the symmetrical bivalent peptide through the introduction of a branched amino acid, Fmoc-Lys(Fmoc)-OH at C-terminus of its peptide, and induce a more stable helical structure thus inhibiting the infection of HIV.

1. Field of the Invention
The present invention relates to peptides that can inhibit the infection of HIV, and more particularly, to peptides consisting of less than 30 amino acids which can introduce a helix capping motif into a peptide derived from C-terminal helical region (its 628-646th amino acid region) of gp41, an envelope glycoprotein of HIV, as well as consisting of the symmetrical bivalent peptide through the introduction of a branched amino acid, Fmoc-Lys(Fmoc)-OH at C-terminus of its peptide, and induce a more stable helical structure thus inhibiting the infection of HIV.
2. Description of the Related Art
Host cell infection by HIV is mediated by the binding between envelope glycoproteins of HIV and receptors of a host cell such as CD4 and chemokine receptors (Berger, AIDS, 11, S3-16, 1997; Doranz et al., Immunol. Res., 16, 15-28, 1997; Moore et al., Current Opin. Immunol., 9, 551-562, 1997). When gp120 of HIV binds CD4 of a host cell, gp120 undergoes a structural change so that it can bind a chemokine receptor in a host cell. Once the binding is completed, a hydrophobic amino terminal fusion peptide region of gp41 of HIV can be inserted in the membrane of a host cell. Then, three gp41 envelope glycoproteins form a six-stranded a-helical bundle, in which three N-peptides associate to form the central trimeric coiled-coil and three C-peptides pack obliquely in an antiparalllel manner on the surface of the coiled-coil core. This bundle structure is involved in a fusion between HIV cell membrane and a host cell membrane as a result thus enabling the core of HIV to penetrate into the cytoplasm of a host cell (Chan and Kim, Cell, 93, 681-684, 1998). Gp41, a glycoprotein present on the envelope of HIV, is also involved in the fusion between HIV envelope and human cell membrane. Gp41 consists of a fusion peptide which exhibits an activity on cell membrane fusion, an N-terminal helical region, a C-terminal helical region, a transmembrane region, and a cytoplasmic region. Peptides derived from N- and C-helical region of the extracellular domain of gp41 can bind to each other in an aqueous solution due to their strong interactions and thus form a very stable complex consisting of six helices from three N-peptides and three C-peptides. The above interaction between the two helical regions is known to play a crucial role in the activity of cell fusion as well as the structural stability of gp41 protein itself. Therefore, it becomes obvious form the above that any substance that can inhibit the above interaction between the two helical regions will be able to inhibit the stability as well as the function of gp41, which will eventually lead to the inhibition of HIV infection thus becoming a promising therapeutic agent for AIDS treatment. In particular, hydrophobic interactions among three nonpolar residues (Trp628, Trp631, and IIe635 of gp41) of C34 peptide (the 628th-661st amino acid) derived from C-terminus of gp41 and a cavity formed by C-terminal portion of the coiled-coil core are known to be important in antiviral activities. These structural features imply that the formation of a helical structure is a prerequisite for the binding between a C-peptide and an N-terminal helical region. DP178, a 36-mer peptide(638th-673rd amino acid, SEQ ID NO.1: YTSLIHSLIEESQNQQEKNEQELLELDKWASLWNWF) derived from C-terminal helical region of gp41 is also known to inhibit gp41-mediated cell fusion, and 1 ng/mL of DP178 has about 90% inhibitory activity on cell fusion mediated by gp41. DP178 is known to inhibit cell fusion by binding an N-terminal helical region of gp4l thus preventing its interaction with the C-terminal helical region of gp41. DP178 and its modified peptides having an antiviral activity consisted of at least 34-36 amino acids and they did not form a secondary structure in an aqueous solution. However, when the ith and the (i+7)th amino acid residues of a peptide consisting of 27 amino acids derived from C-terminus of gp41 without an antiviral activity are chemically cross-linked, the above peptide formed a helical structure and showed an antiviral activity. Hence, helical stabilization of the C-peptides appears to be an important factor in promoting binding affinity for the coiled-coil motif of gp41 as well as for anti-HIV activity(Judice, Proc. Natl. Acd. Sci. USA, 94,13426-13430, 1997).
However, thus obtained peptides have drawbacks as specified below. First, a peptide should have at least 30 amino acids to be able to inhibit gp41-mediated cell fusion and this incurs a lot of expense in synthesizing those peptides. Second, there requires an additional method to chemically link amino acid residues in order to obtain a peptide with a helical structure or a bivalent sequence. Therefore, it has been a long-felt need to develop a peptide with an antiviral activity which consists of relatively less amino acids compared to traditional peptides which have more than 36 amino acids and forms a stable helical structure in an aqueous solution without necessitating complicated post-synthetic modifications.
To solve the above problems, the inventors of the present invention introduced a helix-capping motif into both N-terminus and C-terminus of a peptide derived from a C-terminal helical region of gp41 or substituted into amino acids that can facilitate the formation of a helical structure in order to stabilize a helical structure of a peptide and subsequently confirmed that the peptides can inhibit the cell fusion of HIV via a strong interaction with N-terminal helical region of gp41. The object of the present invention is to provide peptides that can inhibit the infection of HIV containing helix-capping motifs at both ends of a 19-mer peptide (628th-646th region) derived from C-terminus of gp41, an envelope glycoprotein of HIV.

Peptides for inhibition of HIV infection

Korea Institute of Science and Technology


An induction system in an engine is provided. The air induction system includes an induction conduit including an air flow passage in fluidic communication at least one combustion chamber in the engine and a passive-adsorption hydrocarbon trap positioned within the induction conduit, a portion of the passive-adsorption hydrocarbon trap defining a boundary of the air flow passage, the passive-adsorption hydrocarbon trap including a breathable layer coupled to a substrate layer coupled to the induction conduit, a hydrocarbon adsorption layer interposing the breathable layer and the substrate layer.

Evaporative emissions may be caused by fuel vapor escaping from various systems, components, etc., in an engine or other portions of a vehicle. For example, fuel sprayed into an intake manifold, by a fuel injector, may remain on the walls in intake manifold after the engine is shut down and not performing combustion. Consequently, fuel vapor may flow out of the intake system during engine shut down. As a result, evaporative emissions may be increased and in some cases exceed government mandated requirements. Evaporative emissions also have an environmental impact. For example, the emission may create a haze when exposed to sunlight.
Therefore, systems have been developed to capture fuel vapor in intake conduits to reduce evaporative emissions. For example, US 2006/0054142 discloses an intake system with a hydrocarbon trap positioned at a low point in the intake system to capture fuel vapor. Fuel vapors may be absorbed and released from the hydrocarbon trap to reduce evaporative emissions.
However, the Inventors have recognized several drawbacks with the intake system disclosed in US 2006/0054142. For example, the hydrocarbon trap is integrated into a housing of a conduit in the intake system thereby increasing the manufacturing cost of the intake system, as well as reducing the adaptability of the hydrocarbon trap. Moreover, the activated carbon is directly coupled to the housing. The direct attachment of the activated carbon to the housing may inhibit the trap from being easily removed, repaired, and/or replaced, and may increase manufacturing costs. Furthermore, the activated carbon may not properly adhere to the housing. As a result, the activated carbon may be released into the intake system and flow downstream into the engine, degrading engine operation. Additionally, fuel stored in the activated carbon may degrade the housing. Moreover, the hydrocarbon trap is positioned at a low point in the intake system, thereby constraining the position of the hydrocarbon trap.
As such, in one approach an induction system in an engine is provided. The air induction system includes an induction conduit including an air flow passage in fluidic communication with at least one combustion chamber in the engine and a passive-adsorption hydrocarbon trap positioned within the induction conduit, a portion of the passive-adsorption hydrocarbon trap defining a boundary of the air flow passage, the passive-adsorption hydrocarbon trap including a breathable layer coupled to a substrate layer coupled to the induction conduit, a hydrocarbon adsorption layer interposing the breathable layer and the substrate layer.
In this way, the substrate layer may be securely attached to the intake conduit, reducing the likelihood of degradation of the intake conduit via fuel in the adsorption layer and/or degradation of the engine via release of the hydrocarbons. Additionally, when the substrate layer is coupled to the breathable layer to enclose the hydrocarbon adsorption layer, the passive-adsorption hydrocarbon trap may be separately constructed from the induction conduit. As a result, the passive-adsorption hydrocarbon trap may be placed in a greater number of locations when compared to an adsorption layer integrated into an induction conduit. Moreover, the manufacturing costs may be reduced when the hydrocarbon trap is separately constructed from the induction conduit.
In some examples, the breathable layer and an inner wall of the housing of the induction conduit may be contiguous with one another and positioned to form a continuous, uninterrupted linear surface (e.g., without sharp edges, ledges, shelves, or other discontinuities) defining the boundary of the air flow passage, thereby reducing losses in the air flow passage. Further in some examples, the diameter or cross-sectional area of the air flow passage may remain constant transitioning into a section of the induction conduit having the passive-adsorption hydrocarbon trap coupled thereto. As a result, losses in the air flow passages are further reduced, thereby maintaining the efficiency of the induction system.
In another example, an example system comprises an air box having an air filter, the air box having a hydrocarbon trap and a removable lid, and internal reinforcing structures creating one or more pockets; and a hydrocarbon trap material positioned within one or more of the pockets, the lid defining a boundary of the air flow passage, the air box including a layer coupled over the pockets In another example, structural reinforcing elements may be on another wall of the air box, thereby forming the pockets, rather than or in addition to on the lid. In this way, structural reinforcing members that are used to reduce NVH may be re-purposed to form a low cost and effective hydrocarbon trap.
It should be understood that the summary above is provided to introduce in simplified form a selection of concepts that are further described in the detailed description. It is not meant to identify key or essential features of the claimed subject matter, the scope of which is defined uniquely by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure.

Induction system including a passive-adsorption hydrocarbon trap


A semiconductor device includes a substrate, a semiconductor chip provided on the substrate, a plurality of terminals provided on a first side of the substrate, each electrically connected to the semiconductor chip and a plurality of test pads for performing electrical characteristic tests on the semiconductor chip, each test pad being electrically connected to a respective terminal in one-to-one correspondence.

1. Field of the Invention
The present invention relates to semiconductor devices and methods for inspecting and testing semiconductor devices and, more specifically, to BGA (ball grid array) semiconductor devices and inspection and test methods therefor.
2. Description of the Related Art
As semiconductor technology evolves, the complexity of the circuitry capable of being placed on a semiconductor chip increases while at the same time, the size of the semiconductor package decreases. In order to take full advantage of evolving semiconductor technology, the number of signal input/output (I/O) leads per chip must increase, requiring a reduction in spacing between adjacent peripheral I/O leads on the semiconductor device.
A quad-flat-pack (QFP) semiconductor device has been used for relatively low pin count surface mount applications. A QFP device can allow an outer lead pitch of 0.5 mm. Although some applications of QFP can allow for an outer lead pitch of 0.4 mm or even 0.3 mm, this generally results in a lower assembly yield. The body size of QFP devices is typically on the order of 28 mm or less, resulting in a peripheral I/O pin count far below that necessary in many applications.
FIGS. 9A-9C depict the operational flow of QFP devices being tested utilizing a conventional test setup. QFP devices 51 are initially prearranged in an insulated plastic tray 53 with their leads 52 positioned on the lower side, as shown in FIG. 9A. A DUT (device under test) board 55 having a socket 54 designed to accommodate QFP device 51, is situated on contact probes 57 provided on test head 56 (e.g., an electrical measurement and/or test device). Socket 54 has a plurality of electrical contacts (not shown) each corresponding to a lead 52 of QFP device 51. The electrical contacts include leads which extend to the bottom of DUT board 55, where additional contacts are provided, each corresponding to a contact probe 57. Contact probes 57 provide I/O signals between test head 56 and QFP device 51 under test. That is, the side of DUT board 55 opposite to which socket 54 is mounted, is electrically connected to test head 56 via contact probes 57.
Typically, utilizing automated equipment (not shown), a QFP device 51 is picked up and removed from tray 53 and placed into socket 54, as shown in FIG. 9B. The QFP device is then subjected to a predetermined series of electrical tests and/or measurements by test head 56. After the tests and/or measurements are completed, the tested QFP device is returned to a second tray 53', with the same side facing up, as shown in FIG. 9C.
Although such a QFP semiconductor device provides a sufficient number of peripheral I/O pins for many applications, as noted above, the maximum number of I/O pins is still far less than that necessary in many applications.
To provide a higher peripheral I/O contact count, a ball-grid-array (BGA) semiconductor device is often employed. The BGA semiconductor device allows an I/O pad or ball pitch, on the order of 1.5 mm for high I/O requirements, typically resulting in 225 I/O connection points (e.g., see Nikkei Electronics, Feb. 14, 1994, p60-p67).
FIGS. 7A and 7B show in cross-section and a top plan view, respectively, a typical BGA device. In the typical BGA device, semiconductor chip 32 is die-bonded to one side of substrate 31 utilizing a heat resistant bonding resin such as die-bonding epoxy plastic 37. Each electrical I/O connection of semiconductor chip 32 is electrically connected to a corresponding conductor pattern 41 (the shaded portion as shown in cross-section in FIG. 7A) via a bonding wire 33. Each conductor pattern 41 extends via a through-hole 34 to the opposite side of substrate 31 as shown. Solder resist 38 is provided on the device to electrically insulate and protect conductor patterns 41, and a molding resin 36 encapsulates semiconductor chip 32 and bonding wires 33. Solder balls 35 are formed on a bottom surface of the device and provide I/O connection points. Each conductor pattern 41 is electrically connected to a corresponding solder ball 35. Solder balls 35 thus form terminals that can be electrically connected to a test head or to a BGA socket for providing electrical signals to and from semiconductor chip 32.
Additional solder balls 40 may be provided in the central portion of the device for the transfer of heat to and from semiconductor chip 32. For example, through-holes 39 and conductor pattern 42 act as thermal piers for the transfer of thermal radiation (e.g., heat) from solder balls 40 to semiconductor chip 32 during a semiconductor heating process performed during chip testing. In addition, they also act as heat sinks to provide radiational cooling by transferring heat away from semiconductor chip 32 when the semiconductor chip is operating.
An inspection method is known according to which test pads are provided on the face of the printed-circuit board, opposite the area to which the BGA is mounted (Nikkei Electronics, Feb. 14, 1994, p68-p73). In another well-known method, which helps to facilitate inspection after mounting, a scan design method is utilized for an automatic testing process for ASICs (Nikkei Electronics, Mar. 20, 1989, P209-p216).
Utilizing conventional techniques to test the BGA package semiconductor device, it is necessary to electrically connect each I/O solder ball 35 to a test probe. Typically, this is accomplished by bringing a probe such as a pin 83 or a socket 81 (shown in FIGS. 8A and 8B) into contact with each solder ball. The probes may or may not be provided with a spring 82 for urging the probes toward the solder balls. Pressure is applied to the BGA package so that the solder balls are forced against the probes, to ensure positive electrical contact between the probes and the solder balls. However, this procedure can result in the generation of flaws such as dents or chips on the surfaces of the solder balls. For example, as shown in FIG. 8A, a socket probe 81 can be used to electrically connect each solder ball 35 of a BGA device to a specially designed test head. However, the solder forming the solder balls is typically a very soft material. Accordingly, when the BGA device is pressed down, urging solder balls 35 against socket probes 81, the solder balls may tend to deform as shown. As shown in FIG. 8B, if pin-type probes 83 are used, the solder balls may tend to dent or chip.
Such irregularities or flaws on the solder balls are unacceptable, since the solder balls are designed for mating with corresponding contacts in a BGA mounting socket. Accordingly, any irregularities or flaws on the solder balls may prevent good electrical contact from being made between the solder balls and the mounting socket contacts.
To perform comprehensive testing of a semiconductor device, the device is often heated to a predetermined temperature utilizing a heat plate and then subjected to additional electrical tests. Heating of a BGA device is conventionally performed by placing the BGA device on the heat plate with the solder balls on the heating surface. However, heating the semiconductor device in this manner is inefficient and time consuming. In addition, since the solder balls on a BGA device are arranged closely together, it is important that a visual inspection of the ball grid array be performed. However, such a visual inspection requires additional steps to be performed in the typical test procedure. For example, during electrical testing the BGA device is currently arranged on a test head socket with the solder ball side of the device face down on the test head. However, visual inspection of the ball grid array requires that the BGA device be flipped over or inverted to allow the surface of the semiconductor device having the solder balls to be viewed. This requires more test time per device and also requires more complex and costly automated equipment to invert the semiconductor device.

BGA package semiconductor device and inspection method therefor


A rolled sheet product dispenser, including a base and a shaft oriented coaxially with the base. The shaft has a first end and a second end, with the first end being attached to the base. A bracket includes at least one mounting surface, and a base engagement element is attached to the base, the base engagement element being operable for detachable engagement with the bracket. The bracket is operable to position the shaft horizontally when the base engagement element is engaged with the bracket, and the shaft is dimensioned to allow insertion of the shaft within a roll of a rolled sheet product.

Several devices have been proposed for storing and dispensing rolled sheet products, for instance paper or plastic sheet product packaged by rolling the paper or plastic sheet product around a central hollow core roll. However, such dispensing devices typically only secure the rolled sheet product in one of a vertical or a horizontal orientation. Such a limitation restricts the utility and portability of the device. Furthermore, conventional rolled sheet product dispensing devices secured to a wall or other surface require that a user locate themselves near the dispenser to operate the dispenser and obtain rolled sheet products.
Therefore there is a need for a rolled sheet product dispensing device that allows storing and dispensing of the rolled sheet product in both a horizontal and vertical orientation, and that is conveniently and easily adjusted between a horizontal orientation and a vertical orientation. Furthermore, there is a need for a rolled sheet dispensing device that permits convenient and easy securing of the device to a surface through the use of a mounting bracket, and convenient detachment from the mounting bracket to allow location of the device on a horizontal surface and dispensing of the rolled sheet product in any location.


A resin-sealed semiconductor device comprising a semiconductor chip having pad electrodes formed on a circuit forming surface in the interior of the main surface and inner leads cemented to the semiconductor chip through an insulator for electric insulation such that ends of the inner leads reach the edge of the circuit forming surface of the semiconductor chip, wherein common conductors, which are connected with at least one of power supplying inner leads and/or grounding inner leads, and at least one of the inner leads are coupled on the semiconductor chip, and wherein the configuration of the common conductors and the inner leads coupled together is virtually L-shaped, T-shaped, -shaped, or cross-shaped.

1. Field of the Invention
The present invention relates to a resin-sealed semiconductor device and, more particularly, to a resin-sealed semiconductor device of an LOC (Lead-On-Chip) arrangement suitable for mounting on a semiconductor chip having a large-scale integrated circuit.
2. Description of the Prior Art
In packages of the prior art, in order to have a semiconductor chip constantly increasing in scale mounted in a standardized package size, there are proposed packages of the so-called LOC arrangement for example in Japanese Patent Laid-open No. 61-241959 and Japanese Patent Laid-open No. 2-246125.
The package of the LOC arrangement provides a resin-sealed semiconductor device in which inner leads extended from outer leads are cemented to the circuit forming surface of a semiconductor chip through a film insulator, common conductors engaged With the inner leads are disposed on the film insulator, and pad electrodes formed on a portion of the semiconductor chip uncovered by the film insulator are electrically connected with the inner leads and the common conductors by bonding wires or the like.
In the above described resin-sealed semiconductor device, the inner leads engaged with the common conductors are those of power supply system such as a power supplying inner lead (Vcc) and a grounding inner lead (Vss). The number and positions of the inner leads of power supply system engaged with the common conductors are specified in a standard prescribing the lead terminal names.
Accordingly, when the number of the inner lead of power supply system engaged with the common conductor is one, for example when the package is of an SOJ (Small Out-line J-bend) type, if the number of the outer lead of power supply system located in the center of one side of the package is one, the inner lead formed of the common conductor and the inner lead of power supply system have a T-shaped configuration and, in addition, both ends of the common conductor being the top bar of the letter T are not coupled with any other inner leads. Therefore, a twist of the common conductor around the inner lead of power supply system is liable to occur.
On the other hand, when there are a pair of outer leads of power supply system (Vcc outer lead and Vss outer lead) located in the center of one side of a package of the SOJ type, the configurations of the inner leads formed of the common conductors and the inner leads of power supply system become L-shaped connected only with the outer leads independent of each other. Hence, as a matter of course, twists are equally liable to occur.
Further, when the number of the outer leads of the same power supply system located at one side of an SOJ package is two and they are disposed at both ends of the side, the configuration of the inner lead formed of the common conductor and the inner leads of power supply system becomes .pi.-shaped. Though a certain improvement in preventing occurrence of a twist is shown in this case over that of the T-shaped or L-shaped configuration, it is impossible to thoroughly eliminate the twist.
When a twist is present at the portion of the inner lead transforming into the common conductor, there is the possibility that the adhesive strength between the insulator and the inner lead or the common conductor becomes ununiform and the top surfaces of the end portion of the inner lead and the common conductor become different in level, and eventually an inclination is produced in the semiconductor chip.
As a consequence of the foregoing, there has been the possibility in executing the wire bonding that stabilized wire bonding becomes unachievable because supersonic energy is not transmitted effectively and a bonding wire crossing over the common conductor comes in touch with it and causes a short because the common conductor is rising. Further, when the semiconductor chip is inclined, there has been the possibility in the injection of sealing resin that great imvalance is produced between the flowing speed of the resin at the upper portion of the chip and that at the lower portion of the chip and, hence, failure in resin forming is produced such as a resin-unfilled portion or a void of resin.
An object of the present invention is to provide a resin-sealed semiconductor device, in which, even if a large number of outer leads of power supply system are used and they are disposed in various positions, stabilized wire bonding and stabilized resin forming can be performed.

Semiconductor device having inner lead arrangement with enhanced stability


A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host.

Example embodiments of the inventive concepts described herein relate to a memory controller and an operating method thereof.
A semiconductor memory device is a memory device which is fabricated using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and so on. Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.
The volatile memory devices may lose stored contents at power-off. The volatile memory devices include a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), and the like. The nonvolatile memory devices may retain stored contents even at power-off. The nonvolatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and so on.
The semiconductor memory device may be controlled by a memory controller according to a request from a host. The memory controller may communicate with the host through a host interface. That is, the memory controller may write or read data to or from the semiconductor memory device according to the host request. The nonvolatile memory device and the memory controller may constitute a data storage device. As an operating speed of a host increases and a bandwidth of the host interface improves, there may be a demand for increased performance of the memory controller.

Systems and methods for DMA controller for checking the status of metadata prior to or simultaneously when transferring data to host


The response process of disturbance recovery control is divided into a follow-up phase, a convergence phase, and a stable phase. A feedback control device includes a first phase switching unit (3) which switches to the follow-up phase, a second phase switching unit (4) which switches to the convergence phase, a third phase switching unit (5) which switches to the stable phase, a first manipulated variable determining unit (6) which outputs a manipulated variable which makes the controlled variable follow up the set point in the follow-up phase, a second manipulated variable determining unit (7) which outputs a manipulated variable which makes the controlled variable converge near the set point in the convergence phase, and a third manipulated variable determining unit (8) which outputs a manipulated variable which makes the controlled variable stable at the set point in the stable phase.

The present invention relates to a process control technique and, more particularly, to a feedback control method and feedback control device which perform disturbance recovery control by giving a manipulated variable to a controlled system so as to make the controlled variable recover to the set point at the time of application of a disturbance.
Conventionally, PID control has been known as a highly practical general control theory. As an advanced control theory like modern control theory, for example, simple adaptive control (SAC) has been known. According to either of the control theories, a manipulated variable MV is output as a control computation result to a controlled system so as to make a controlled variable PV recover to a set point SP at the time of application of a disturbance, and control computation is performed on the basis of a deviation Er between the controlled variable PV and the set point SP.
General PID control is a linear control theory, and is a control theory based on the assumption that a control system including a controlled system becomes a linear system. In practice, however, a controlled system does not have linearity in a strict sense, and PID control can tolerate slight nonlinearity. For example, heating by a halogen lamp in a RTP (Rapid Thermal Process) used in a semiconductor manufacturing apparatus is a system with strong nonlinearity to which PID control cannot be simply applied. In this case, even PID control can be used if only the stability of a control system is to be pursued. However, PID control cannot cope with operation under the condition that a fast temperature rise and a response waveform with a little overshoot are required as in an RTP.
Assume that the nonlinearity of a control system can be approximated by a characteristic curve K shown in FIG. 14. In this case, when the controlled variable PV is to be made to recover to the set point SP with a fast temperature rise (fast disturbance recovery) at the time of application of a temperature-decreasing disturbance, the manipulated variable MV (heating output) becomes 100% at the time point when the deviation Er between the set point SP and the controlled variable PV is large. As a consequence, an average process gain characteristic curve has a large gradient as indicated by "Kav1" in FIG. 14. As the temperature rises and the deviation Er decreases, the manipulated variable MV decreases to, for example, about 20%. In this case, an average process gain characteristic curve becomes another characteristic curve having a small gradient as indicated by "Kav2" in FIG. 14.
When the PID parameters of a PID controller are adjusted in conformity with specifications for fast disturbance recovery, and the PID controller is applied to a strong nonlinearity system like that shown in FIG. 14, a temperature rise curve (disturbance recovery waveform) becomes like a curve PV in FIG. 15. That is, in the first half period of response, overshoot occurs in the controlled variable PV as in a case wherein a controlled system with an excessively large process gain is controlled, whereas in the second half period of response, control operation occurs such that the controlled variable PV follows up to the set point SP at extremely low speed as in a case wherein a controlled system with an excessively small process gain is controlled. As a result, a temperature rise curve like that shown in FIG. 15 appears. This control is not suitable for a controlled system for which a response waveform with a little overshoot is required as in the case of a semiconductor manufacturing apparatus. In addition, adjustment of PID parameters falls out of the range of a linear control theory, and hence is very difficult to realize.
An advanced adaptive control theory such as simple adaptive control (SAC) is designed to automatically correct the internal parameters of a control computation unit so as to always obtain proper control characteristics with respect to variations in the process gain characteristic of a controlled system. However, for proper automatic correction (adaptive operation) for the internal parameters, control computation must be performed by a sufficient number of times in a transient state. In fast disturbance recovery, the time required for a temperature rise is about 1.0 to 1.5 sec, as shown in FIG. 16A. If, therefore, the control cycle is 50 msec, the number of times of control computation in disturbance recovery is about 20 to 30.
The number of times of control computation allowed to follow up a change in process gain due to strong nonlinearity characteristics under such conditions is about two to three at best, as shown in FIG. 16B. This number of times of control computation is simply too small to make adaptive operation properly function. At practical level, a technique based on an advanced adaptive control theory can obtain the stability of control, in the end, at best, but cannot make a controlled system with strong nonlinearity characteristics smoothly achieve fast disturbance recovery. This technique is substantially directed to only ensure stability in application to not only fast disturbance recovery but also other operations. Furthermore, there are no guidelines for practical standards concerning settings of many parameters to be set in advance for proper adaptive operation.
As described above, according to the conventional PID control theory, proper disturbance recovery control cannot be realized for a controlled system with strong nonlinearity, and it is difficult to adjust PID parameters.
In addition, according to an advanced adaptive control theory such as simple adaptive control (SAC), in a controlled system with strong nonlinearity characteristics, when the controlled variable is to be made to recover to the set point at high speed, since the number of times of control computation allowed is too small to make adaptive operation properly function, proper disturbance recovery control cannot be realized. In addition, it is difficult to adjust parameters.

This patent is subject to a terminal disclaimer.

Feedback control method and feedback control device


A television set include a DVD-IC 20 for outputting a composite signal a containing subtitle information and closed caption information, a TV-IC 10 for outputting an OSD signal b based on the closed caption information identified in the composite signal a, and a serial bus connecting the DVD-IC 20 and the TV-IC 10. The DVD-IC 20 informs the TV-IC 10 of the setting status of subtitle display based on the subtitle information in a DVD player. The TV-IC 10, if the setting of subtitle display based on the subtitle information in the DVD player is ON, turns OFF the setting of subtitle display based on the closed caption information in the television receiver, thereby prohibiting an OSD signal b from being outputted.

1. Field of the Invention
The present invention relates to an information recording device including a signal processing unit for converting received digital broadcasting signals into analog video and audio signals and a recording unit for recording the digital signals converted again from the converted analog video and audio signals on a recording medium.
2. Description of the Related Art
Nowadays, BS digital broadcasting and CS digital broadcasting have been started and terrestrial digital broadcasting is soon commercially practical. The advantage of the digital broadcasting resides in achievability of data broadcasting as well as fineness or clearness of an image or picture and speech or sound. The data broadcasting provides beneficial matters for viewers such as EPG (Electronic Program Guide), teletext broadcasting, program contents, etc.
However, a present information recording device (recording appliance) is designed to disable the digital broadcasting from being recorded, as it is, except D-VHS (Data-VHS), taking copyright into consideration.
Specifically, the DVD apparatus (DVD recorder) which is an existing information recording device includes a signal processing unit for converting received digital broadcasting signals into an analog video and audio signals and a recording unit for recording the digital signals again converted from the converted analog video and audio signals on a recording medium.
Incidentally, techniques for prohibiting copying, taking copyright into consideration are disclosed in, e.g., JP-A-10-093914 and JP-A-2002-077761.


An electrical connector assembly (10) comprising a housing (20) with a latch arm (30), a CPA (40) received in the latch arm (30), an inner housing (50) received within the housing (20), a wire seal (60) disposed on the inner housing (50) and retained by a seal retainer (70) and posts (51), a wire cover (80), and a header housing (90). Wire seal (60) includes wire receiving slits (67) therein for advantageously receiving wires (17) during an insulation displacement type wire termination operation, and wire seal (60) includes frusto-conical sections for insuring that wires are sealed against the retainer (70), and inner housing (50).

Sealed electrical connectors are used in the automotive industry to protect electrical connections from moisture or other contaminants. Insulation displacement type contacts are advantageously used in the automotive industry for inexpensive, reliable mass termination of wires in electrical connectors. Conventional automotive sealed electrical connectors are constrained to use wire crimp technology, and require the assembly step of inserting the crimped terminal or the housing through the seal, thus risking damage to the seal. What is needed is a seal which can withstand the temperature and vibration inherent in an automotive environment, but is advantageously adapted for use with insulation displacement type contacts without diminishing its sealing performance.
A known sealed connector is disclosed in U.S. Pat. No. 5,100,335. This crimp technology connector system requires a seal having slits formed therein, but the slits are not used to enhance assembly of the electrical contacts within the assembly. Rather, the slits are used to interlock the seal with projections on the connector housing wall.
The present invention has solved the foregoing problem by providing a seal for use with an electrical connector having insulation displacement type contacts therein, but which seal is reliably operative to seal against moisture and other contaminants.

Seal for use with an electrical connector comprising insulation displacement type contacts


Disclosed herein is a method of sending and receiving (or transceiving) audio stream in a wireless communication system. The method performed by a first device includes receiving reference codec information from a second device, performing an audio codec negotiation procedure for determining an audio codec to be used to send and receive audio stream to and from a third device, checking whether the audio codec determined through the audio codec negotiation procedure is identical with the audio codec supportable by the second device, and operating in bypass mode or conversion mode based on a result of the check.

Field of the Invention
The present invention relates to a wireless communication system and, more particularly, to a method and apparatus for transmitting and receiving audio streams in a wireless communication system supporting Bluetooth communication.
Discussion of the Related Art
Bluetooth is one of representative short-distance radio technologies in which various devices (e.g., a smart phone, a PC, an earphone, and a headphone) are interconnected and exchange information. Furthermore, Bluetooth is a technology applied to most of smart phones, PCs, and notebooks and is easily used by many people. The easy pairing procedure of Bluetooth stably provides connectivity between devices. A recent low energy (LE) technology consumes less power and can stably provide information of several hundreds of KB.
The core specification of a Bluetooth standard technology is divided into a basic rate/enhanced data rate (BR/EDR) and low energy (LE).
The Bluetooth low energy (hereinafter referred to as "BLE") is a technology issued since Bluetooth Specification V4.0 and was designed for the purpose of high energy efficiency to existing Bluetooth.
The BLE technology may not be suitable for the real-time transmission of an audio stream in which a data transmission request is periodically generated because it has been designed so that a connection procedure is performed only when a data transmission request is generated between a master device and a slave device.
That is, when a slave requests data transmission and reception, a BLE master performs connection with the slave within a short time, exchanges required data with the slave within a relatively short time, and then performs disconnection.
In conventional Bluetooth communication, control and data transmission functions between a Bluetooth headset and a Bluetooth device (e.g., a smart phone) are provided using a hands free profile (HFP) for a telephone call (e.g., VoIP).
In conventional Bluetooth communication, from a viewpoint of an audio codec, a small number of codecs are mounted on a Bluetooth headset, and a smart phone performs a codec conversion so that audio stream data is transmitted and received between the Bluetooth headset and a remote terminal.
As described above, end to end audio stream delay and power consumption of a smart phone are increased due to a codec conversion in a smart phone.
In a Bluetooth device, a technology for call control, such as VoIP services (e.g., SIP, Skype, GoogleTalk, and FaceTime), through a smart phone or a PC is recently proposed.
In the case of the VoIP service, in general, an (audio) codec negotiation procedure between Bluetooth devices is performed prior to call connection between the Bluetooth devices.
Furthermore, in order to provide mutual compatibility between Bluetooth devices, a plurality of codecs must be mounted on and provided to a smart phone or a Bluetooth headset.
However, the application of a plurality of codecs to a Bluetooth headset is not preferred if limited resources (e.g., processing power and a memory unit) are taken into consideration. The application of a plurality of codecs to a smart phone inevitably increases the delay of the transmission and reception of end to end audio streams and power consumption of a Bluetooth device as described above.

Method and apparatus for transmitting and receiving audio stream in wireless communication system


A gas bag module includes a gas generator (10), a gas bag (28) in flow connection with the gas generator, and a module covering. The module covering covers the gas bag and has a separate central part (18) after opening of the module covering. The gas bag module further has a holding device (12) for the central part. The holding device has guide means (14, 16, 20, 22) which on inflation of the gas bag (28) permit a displacement of the central part (18) and delimit a displacement of the central part (18).

A conventional gas bag module normally has a gas generator, a gas bag and a module covering.
From DE 199 04 072 A1 there is known a gas bag module with a module covering and a ring-shaped gas bag, which is able to be inflated through an annular gap around the opened covering in a funnel shape in the direction towards the vehicle occupant. Only a slight movement of the entire module covering out from the module in the direction towards the occupant (unfolding direction) is permitted, this movement being so small that the occupant can not come into contact with the covering.
Through the invention, the final position of the module covering on unfolding of the gas bag is to be reliably established, the opening and the unfolding of the gas bag is to be improved and the gas bag is to assume a defined final position.


A medical imaging diagnosis apparatus for measuring the composite thickness of the tunica intima and the tunica media of a blood vessel of a subject by acquiring image data on the blood vessel. In order to improve the accuracy of the IMT measurement of the composite thickness, the medical imaging diagnosis apparatus has extracting means for extracting the tunica intima and the tunica externa of the blood vessel on the basis of the brightness information of the image data to measure the composite thickness of the tunica intima and the tunica externa of the vessel in reference to the two extracted regions.

An ultrasound diagnostic apparatus being a kind of medical imaging diagnostic apparatus obtains image data by transmitting/receiving ultrasonic waves between an object being examined via a probe and reconstructing ultrasound images (for example, B-mode images) based on echo signals generated from the object.
In such ultrasound diagnostic apparatus, the measurement of intima media thickness (hereinafter referred to as IMT) of a blood vessel wall is implemented in order to identify arteriosclerosis or cardiovascular diseases at an early stage. A blood vessel wall is formed with a trilaminar structure consisting of tunica intima, tunica media and tunica externa in due order from the lumen side where blood flows. IMT is the sum of the thickness of the tunica intima and the tunica media, in other words the distance from the inner wall of the tunica intima to the inner wall of the tunica media.
In the ultrasound apparatus for measuring IMT, for example, the brightness distribution in the thickness direction of a blood vessel wall of image data in one line is obtained, and the local maximal point having the maximum brightness of the brightness distribution is set as tunica externa reference point A. The second local maximal point that appears from tunica externa reference point A in the lumen side is set as tunica intima reference point B. Then IMT measurement is performed by setting minimum point C that appears in the lumen side from tunica media reference point B as the inner wall of the lumen, as well as setting the midpoint between point D having the minimum brightness of the brightness distribution and tunica externa reference point A as the inner wall of the lumen (refer, for example, to Patent Document 1).    Patent Document 1: JP-A-99-318896
However, with the technique in Patent Document 1, once in a while minimum point C does not appear clearly in the lumen side from the tunica media reference point in the brightness distribution of image data. Also, setting the midpoint between point D and tunica externa reference point A as the inner wall position of the tunica externa is based on empirical rules obtained from factors such as clinical results. Due to the individual variability of objects being examined, there are cases that IMT cannot be measured accurately. Therefore there is a demand for improvement of IMT measurement.
It is the objective of the present invention to provide a medical imaging diagnostic apparatus and method with improved accuracy for the measurement of IMT.

Medical imaging diagnosis apparatus and medical imaging diagnosis method


Disclosed herein is an ink composition, including: a pigment; acetylenediol having an HLB of less than 4; and an anionic surfactant, in which the mass ratio of the acetylene diol to the anionic surfactant is 0.30 to 4.0.

1. Technical Field
The present invention relates to an ink composition, an ink set, and a black ink set.
2. Related Art
As a liquid ejecting apparatus for ejecting liquid onto a target, an ink jet printer for ejecting ink onto a recording medium (hereinafter, simply referred to as a printer) is known. In this printer, in order to reduce the ejection failure of ink, cleaning for discharging the ink or the like thickened from an injection nozzle for ejecting ink has been appropriately carried out.
In this cleaning, a nozzle formation surface provided with nozzles is sealed with a suction cap, and then a space (in the suction cap) hermetically closed with the nozzle formation surface and the suction cap is vacuumed up by a suction pump. That is, in the cleaning, a space having negative pressure is formed in the discharge direction of ink, and the thickened ink or like is discharged from a nozzle by using the negative pressure.
In such cleaning, generally, the ink discharged from the nozzle is sucked by the suction pump through the suction cap, and is then discharged to an ink recovery unit as a liquid recovery unit. In such an ink recovery unit, an ink absorber for absorbing ink is contained. This ink absorber absorbs the discharged ink, thereby recovering the ink discharged from the suction pump.
As an example of the technology focusing on an ink recovery unit, JP-A-2006-21451 is known. JP-A-2006-21451, for the purpose of providing a liquid absorber for eliminating the bubbles contained in the liquid discharged from an outlet of a suction pump to a liquid recovery unit and smoothly absorbing and recovering the discharged liquid, discloses a liquid absorber for absorbing the liquid discharged from an outlet of a suction means depressurizing the space by suctioning liquid and gas, in which the liquid absorber includes a defoaming agent for eliminating the bubbles contained in the liquid discharged from the outlet.
However, in the technique described in JPA-2006-21451, there is a problem that a mechanism for supplying a defoaming agent to the liquid absorber of the liquid recovery unit in a recording apparatus is further required.
Further, the ink sucked through the nozzle contains the bubbles generated therein by the suction (negative pressure). Through the suction cap, fine bubbles are discharged together with the thickened ink. Since it is difficult for these bubbles to be absorbed by the ink absorber in the suction cap, an ink composition accumulates in the suction cap, and eventually the ink composition overflows from the suction cap. When the ink composition overflows from the suction cap, there is a concern that the nozzle formation surface is contaminated during the cleaning, and thus cleaning-induced ejection failure occurs.

Ink composition, ink set, and black ink set


A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.

The present invention relates to a semiconductor storage device and its manufacturing method, particularly, an electrically erasable programmable nonvolatile semiconductor storage device and its manufacturing method.
Also, the invention relates to a semiconductor storage device, as well as its manufacturing method, in which semiconductor storage elements and semiconductor switching elements are mounted compositely on one identical substrate.
Also, the invention relates to portable electronic equipment and IC cards equipped with such a semiconductor storage device or semiconductor device.
As a semiconductor storage device, there has conventionally been a flash memory that is a memory element that allows electrical writing and erasing (e.g., see "A handbook for flash memory techniques," edited by Fujio Masuoka, K. K. Science Forum, Aug. 15, 1993, pp. 55–58). A structural cross sectional view of the flash memory element is shown in FIG. 34. As shown in FIG. 34, the flash memory element is composed of a floating gate 1506 made of polysilicon placed on a semiconductor substrate 1501 via a first oxide 1504, and a control gate 1507 made of polysilicon placed on the floating gate 1506 via a second oxide 1505. On the surface of the semiconductor substrate 1501, a pair of source/drain diffusion regions 1502, 1503 are disposed. The end portions of the gate electrodes 1506, 1507 are respectively laid above the end portions of the source/drain diffusion regions 1502, 1503. The control gate 1507 plays the role of a gate electrode of an Field Effect Transistor (FET) in the flash memory. Moreover, between the control gate 1507 and the semiconductor substrate 1501, the first oxide 1504, the floating gate 1506 and the second oxide 1505 are disposed. Therefore, the flash memory is a memory element which is provided with a memory film (floating gate) serving as a charge retention section disposed in a gate insulator portion of the FET so as to implement the function of changing a threshold voltage of the FET depending on a charge amount stored in the memory film.

Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card


In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate xe2x80x9cblack siliconxe2x80x9d comprising:

1. Field of the Invention
The invention generally relates to the modification of apparatus to cause elimination or reduction of black silicon during a DT (deep trench) etching process during fabrication of integrated circuits (ICs) or chips, in which there is etching into a silicon substrate features used to form microelectronic devices. In particular, the invention relates to the elimination or reduction of black silicon during the DT etch which may serve as a trench capacitor of a memory cell, by causing sheath shaping on the lower electrode assembly in an etching reactor.
2. Description of the Related Art
Integrated circuit (IC) technology has recently moved from large-scale integration (LSI) to very large scale integration (VLSI) and is expected to grow to ultra-large scale integration (ULSI) in the very near future. These advancements in monolithic circuit integration is possible by virtue of improvements in manufacturing equipment and the materials and methods used in preparing semiconductor wafers into IC chips.
Several factors impose increasingly strict requirements on the basic integrated circuit fabrication steps of: masking; film formation; doping and etching; and dielectric insulation.
These factors are: the incorporation of IC chips of increasingly complex devices and circuits; the use of greater device densities and smaller feature sizes, and smaller separation; the use of composite conductor layers; and the use of the third wafer dimension of depth as well as the surface area to form buried or trench capacitors (DT).
In this connection, the ability to etch narrow, deep, high aspect ratio trenches is vital to the formation of buried or trenched capacitors. Further, single crystal silicon trench isolation is increasingly being used in semiconductor research as an alternative to other device isolation technologies, due to the fact that trench dielectric isolation offers a number of advantages, such as relatively small surface area requirements, small width-to-depth ratios, and a vertical wall profile.
A further and significant advantage of the trench technology is its relative simplicity of process. For example, to create a buried capacitor or dielectric isolation structure using trench technology entails reactive ion etching (REI) a groove into a single crystal silicon substrate, oxidizing side walls of the groove or trench, filling the groove with oxide dielectric or a polysilicon, and planarizing the surface.
However, xe2x80x9cblack siliconxe2x80x9d is one of the prevalent etch obstacles during the etching process. Black silicon is caused by the presence of surface contaminates such as residual oxides, that act as localized etched mask. Consequently, the areas beneath these micromasks are not etched away until the contaminates are completely eroded, thereby causing the bottom of the finished trenched substrate to develop a rough, light-scattering dark surface appearance that is responsible for the name xe2x80x9cblack siliconxe2x80x9d.
Black silicon formation at the edge of a wafer can also cause loss of chips and therefore directly contributes to chip yield loss.
One of the mechanisms for black silicon formation is the erosion of the boron doped silicate glass (BSG) mask at the edge that causes the exposure of the silicon surface. The higher BSG/Nitride etch rate at the periphery of the wafer is caused by the focusing of ions from the focusing dielectric ring placed around the wafer in the DT (deep trench) etch tool.
U.S. Pat. No. 5,874,362 disclose a method for etching a high aspect ratio, straight walled opening in silicon, in which the opening is characterized by a rounded bottom. The process is conducted by forming a plasma from a precursor gas etch mixture of HBr as the main etchant, using oxygen to provide protection for the side walls of the openings and to control selectivity with respect to the oxide etch mask, employing a fluorine-containing gas to remove residual contaminates from the side walls of the openings, and etching a silicon body until an opening of the desired depth is formed. The use of a brominate and gas chemistry in this process is said to overcome the problem of black silicon.
A method of and apparatus for improving etch uniformity in remote source plasma reactors with a powered wafer chuck or pedestal is disclosed in U.S. Pat. No. 5,662,770. The invention addresses the uniformity problem which arises due to non-uniform power coupling between a wafer and the walls of the etch chamber by increasing the impedance between the wafer and the chamber walls by placing a cylindrical dielectric quartz wall around the wafer if silicon is to be etched selectively with respect to silicon dioxide.
A plasma etch apparatus with heated scavenging surfaces is disclosed in U.S. Pat. No. 5,477,975. The plasma etch reactor is operated by introducing a gas into the reactor which disassociates as a plasma into an etched species which etches oxide films on a work piece in the reactor and a non-etching species combinable with the etched species into an etch-preventing polymer condensable onto the work piece below a certain deposition temperature, thereby providing an interior wall comprising a material which scavenges the etching species, and maintains a temperature of the interior wall above the deposition temperature.
U.S. Pat. No. 5,292,399 disclose a plasma etching apparatus with conductive means for inhibiting arcing. The conductive means for inhibiting arcing from electrical charges accumulating on one or more non-conductive protective surfaces on members at Rf potential within the apparatus includes one or more conductive plugs extending through one or more of the protective surfaces or a conductive ring surrounding the wafer on the top surface of a metal pedestal.
Accordingly, there is a need in the art of fabricating integrated circuits or chips, where features are created by etching into the silicon substrate deep trenches (DT) which serve as a trench capacitor, to flatten the self-developed negative dc bias (Vdc) sheath boundary beyond the edge of the wafer, and thereby reduce DT mask erosion at the wafer periphery to eliminate or reduce xe2x80x9cblack siliconxe2x80x9d in the DT etch.
There is a further need in the art of fabricating integrated circuits or chips where features are created by etching into the silicon substrate a deep trench that serves as a trench capacitor, to reduce DT mask erosion by utilizing a silicon source to provide a deposition component at the edge of the wafer, to assist in the elimination or reduction of black silicon in the DT etch.
In general, the invention relates to utilizing an electrode configuration with a focusing sheath of a lower electrode assembly in an etching reactor through an innovation that flattens the sheath at the wafer periphery, to effectively defocus ions from the boundary of the self-developed negative dc bias (Vdc). Towards this end, a disc, preferably of silicon, is added to modify an existing quartz ring used as an insulator that is not easily eroded by the etching environment, and the silicon disc is easily replaced without replacing the entire wafer chuck/clamping ring mechanism. By shaping the Vdc sheath at the wafer surface to defocus the ions and thereby reduce the erosion of the BSG mask, elimination and/or reduction of black silicon is accomplished in the DT etch.
One object of the present invention is to provide a modification to the typical electron configuration with focusing sheath used in DT etch to fabricate integrated circuits or chips in which the features created by etching into a silicon substrate are those which are deep trench (DT) features that serve as trench capacitors.
Another object of the present invention is to provide a modification of the typical electron configuration with focusing sheath used in the fabrication of integrated circuits or chips in which features are created by etching into a silicon substrate a deep trench which serves as a trench capacitor, by flattening the sheath at the wafer periphery to effectively defocus the ions that accelerate across the sheath from a dielectric focus ring that forms a boundary of self-developed negative dc bias that causes erosion of the BSG mask at the edge of the wafer to create exposure of the silicon surface, that results in black silicon formation at the edge of the wafer.
In general, the invention is accomplished by the addition of a silicon disc, preferably silicon, in the form of a ring adjacent to a normally present insulating quartz ring, so that the voltage developed in this peripheral area is the same as that over the waferxe2x80x94thereby creating a condition in which there is an extension of the flat sheath boundary beyond the wafer edge so that the ions are now normal to the wafer surface and thus unfocused or defocused. The shape of this new sheath results in a reduction of the mask erosion at the wafer edge (since the etch rate of BSG is dependent upon ion energy), and thereby protects the silicon surface from exposure to the plasma during the entire DT etch process.

Elimination/reduction of black silicon in DT etch

Abstract: a) providing a plasma etch reactor comprising walls defining an etch chamber;

Abstract: b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer;

Abstract: c) providing a dielectric wall in proximity to and around a periphery of the wafer;

Abstract: d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall;

Abstract: e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and

Abstract: f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of the etch chamber, to provide extension of a Vdc flat sheath boundary beyond and into a defocusing relationship to the wafer edge to reduce mask erosion and eliminate occurrence of xe2x80x9cblack siliconxe2x80x9d formation.


A switch has a first electrical terminal, a second electrical terminal spaced from the first electrical terminal and an elongate conductive switch blade for bridging the terminals. The switch blade has a first end portion pivotally connected with the first electrical terminal for movement of the switch blade between open and closed positions. The switch blade has a second end portion positioned adjacent the second electrical terminal when in the closed position. A plurality of elongate fingers are secured by spring loading to the second end portion of the switch blade. The fingers are arranged adjacent to each other along opposing sides of the second end portion to form an open jaw structure that extends from the second end portion of the switch blade and makes wiping electrical contact with the second electrical terminal as the switch blade is moved into the closed position.

Three phase non-segregated disconnect switches find application in generator compartments for supplying electricity to a power grid. These switches must be capable of withstanding short circuit tests in the order of 80 kA.
One type of disconnect switch used in the three phase non-segregated application comprises a pair of spaced apart elongated blade members which span the distance between first and second electrical terminals of the switch. Typically these spaced apart blades include a spacer between the blades. One end of the blades is pivotally attached to one of the terminals and the other end of the blades has inside edges of the blades making wiping contact with the second electrical terminal. In this switch, as many as three bolts pass through the blades, and springs and nuts are mounted on these bolts so as to control spring loaded compression of the blades with the second electrical terminal. While this spring switch configuration provides a reliable switch for making and breaking the connection at the second electrical terminal, the spring switch does not respond well to 80 kA short circuits in the three phase non-segregated application. During a short circuit, the three phases of the spring switch blades are attracted to each other causing the blades of adjacent phases to be attracted towards each other resulting in at least one of the blades being pulled from the second electrical terminal. This results in arcing and welding of this blade to the second terminal.
Another known construction for a three phase non-segregated disconnect switch is a bolted switch. The bolted switch typically has double switch blades for each phase that carries a bolt that is received within a groove of the second electrical terminal. While the bolted switch is able to withstand the 80 kA short circuit condition, this switch is relatively expensive to manufacture and tends not to be as reliable over time in making and breaking the connection with the second electrical terminal.


There is provided an event management system and a storage media for identifying and logging event information for a plurality of loosely coupled subsystems. The event management system and the storage media include an application for reporting an event message in response to an occurrence of a particular event, and an event logging routine, responsive to receiving the error message, for identifying a source of the error message and for obtaining detailed error information for the error message at a time frame when the particular event occurs. In addition, the event management system and storage media include an event viewer for viewing the detailed error information.

Existing operating systems include error handling tools that identify and log errors that occur during the operation of the operating systems and provide a user with the ability to view the logged errors. Although most applications running in the operating system's environment provide error messages when errors occur, these error messages are often technical in nature and may not be easily understood by the user. Therefore, the error handling tools not only identify and log these errors but, in addition, they describe the errors to the user in an easily comprehensible format. For example, the Windows NT.RTM. operating system by Microsoft Corporation includes an event log that collects error messages from applications, device drivers and the operating system itself to a common location that the user can access. The Windows NT.RTM. operating system also includes an event viewer that permits the user to view the error messages in the order of their occurrences.
The error handling tools of existing operating systems work fine for a self-contained environment, but do not operate well in a client/server environment having one or more client applications and service providers. In particular, the client application has the burden of understanding the error messages and to log a meaningful text for the message, but this task is difficult to manage in a client/server environment. If an error is encountered when the client application requests a service from a particular service provider, the service provider returns an error code that must be interpreted by the client application.
For existing error handling tools, the client application must have advance knowledge of the possible types of service failures. Otherwise, the client application would not be able to provide meaningful information regarding the nature of the error. This poses problems in a client-server environment because the client application and applications of the service providers are loosely coupled and developed independently, and it is not practical to change an application as its underlying service provider evolves. It is, therefore, difficult for a client application to obtain meaningful information for an error message within a client/server environment.
The present invention resolves the above problems by providing a mechanism for a client application that identifies the source of a service error and obtains detailed error information at the time the error occurs. In particular, the mechanism accesses the error message information specific to the service that encounters the error and, then, reports that information as part of its error handling operation. The present invention also functions in a plurality of nested subsystems in which a subsystem that detects a particular problem is identified among a group of subsystems that are called in a nested manner. Accordingly, the present invention automatically handles the operation of reporting events whose source subsystem is different from that of the reporting subsystem without requiring the reporting subsystem to have advance knowledge of the possible errors that could be encountered.

Error management system for supporting the identification and logging of error messages


A toilet paper dispenser that is configured to retain and subsequently dispense a plurality of toilet paper rolls. The toilet paper dispenser further includes a front wall, a rear wall and two side walls that are configured to create a container that is generally rectangular in shape having an interior volume. Contiguously mounted to the front wall proximate the upper portion of the container is a door hingedly mounted to allow access to the interior volume for loading of toilet paper rolls. An access flap is mounted generally beneath the door contiguous with the front wall and is hingedly mounted to provide access to the interior volume for retrieval of depleted toilet paper rolls. The access flap further includes a slot that is configured to dispense sheets of toilet paper from the adjacent toilet paper roll substantially disposed within the interior volume of the container.

Good hygiene is a routine practice for most individuals and is practiced on a daily basis. Toilet paper is a routine part of practicing good hygiene. Toilet paper holders have been in use for years and are routinely located proximate a toilet for a user to access when required. Typically, a conventional toilet paper holder is comprised of a U-shaped bracket or dual post structure that is secured to the wall or cabinet with a spring-loaded telescoping member intermediate the opposing forks of the toilet paper holder. This typical installation is designed for rotatably supporting a single roll of toilet paper.
One problem with toilet paper holders is that the typical toilet paper holder can only secure one roll at a time. As the toilet paper holder is emptied an individual must have a refill roll available and change the roll frequently. If the roll is not filled for the next individual to make use of the restroom facilities it can create a difficult situation for that individual.
Another issue with typical toilet paper holders is that they leave the toilet paper roll exposed whereby the exposed toilet paper is easily accessible to children or pets who often proceed to unwind at least a portion of the toilet paper roll. This creates excessive waste and frustration for the individual required to clean up after the pet or child.
Accordingly, there is a need for a toilet paper dispenser that has the ability to store and subsequently dispense a plurality of toilet paper rolls and simultaneously conceal and protect the toilet paper rolls inhibiting any unwanted dispensing of the toilet paper roll contained therein.

Multiple toilet paper holder and dispenser