A decoder circuit that selects a grayscale voltage responsive to digital input includes a first transistor circuit that selects grayscale voltages greater than a certain voltage and a second transistor circuit that selects grayscale voltages less than the certain voltage. The two transistor circuits are formed in separate substrates, one substrate being a well formed in the other substrate, or both substrates being wells formed in a third substrate. The substrate of the first transistor circuit is biased at a higher potential than the substrate of the second transistor circuit. This biasing scheme enables all selected grayscale voltages to propagate quickly through the decoder circuit.

1. Field of the Invention
The present invention relates to a decoder circuit for selecting-an analog voltage such as an analog grayscale voltage for a liquid crystal display.
2. Description of the Related Art
A thin-film-transistor (TFT) liquid crystal display generally includes a microelectronic chip, sometimes referred to as a source driver chip, that receives and decodes an m-bit input signal in order to select and output one of 2m positive and 2m negative analog grayscale voltages. The output voltage is supplied to the source electrodes of transistors in the display.
FIGS. 1 and 2 show examples of conventional decoder circuits used for output of positive voltages in a source driver chip. These circuits comprise p-channel metal-oxide-semiconductor (PMOS) transistors formed in an n-type well or n-well 10 biased at the positive power supply potential (VDD). The analog grayscale voltages are generated by a resistor ladder (not shown). Although typical values of m are six to ten, enabling the circuit to select from sixty-four (26) to one thousand twenty-four (210) analog voltage levels, circuits with four-bit and eight-bit input are shown for simplicity.
FIG. 1 shows a four-bit decoder circuit that selects and outputs one of sixteen analog grayscale voltages according to the combination of four input bit signals. Inverters 10, 11, 12, 13 invert the input signals: inverter 10 is coupled between an input node G0 and an output node G0B, inverter 11 is coupled between an input node G1 and an output node G1B, inverter 12 is coupled between an input node G2 and an output node G2B, and inverter 13 is coupled between an input node G3 and an output node G3B.
Nodes VH0 to VH15, which receive the sixteen analog grayscale voltages, are connected to the source electrodes of PMOS transistors P0_0 to P0_15. The gate electrodes of the even-numbered-transistors P0_0, P0_2, P0_4, P0_6, P0_8, P0_10, P0_12, P0_14 are connected to node G0. The gate electrodes of the odd-numbered PMOS transistors P0_1, P0_3, P0_5, P0_7, P0_9, P0_11, P0_13, P0_15 are connected to node G0B.
A node Net1_0 is connected to the drain electrodes of transistors P0_0, P0_1 and the source electrode of transistor P1_0. A node Net1_1 is connected to the drain electrodes of transistors P0_2, P0_3 and the source electrode of transistor P1_1. A node Net1_2 is connected to the drain electrodes of transistors P0_4, P0_5 and the source electrode of transistor P1_2. A node Net1_3 is connected to the drain electrodes of transistors P0_6, P0_7 and the source electrode of transistor P1_3. A node Net1_4 is connected to the drain electrodes of transistors P0_8, P0_9 and the source electrode of transistor P1_4. A node Net1_5 is connected to the drain electrodes of transistors P0_10, P0_11 and the source electrode of transistor P1_5. A node Net1_6 is connected to the drain electrodes of transistors P0_12, P0_13 and the source electrode of transistor P1_6. A node Net1_7 is connected to the drain electrodes of transistors P0_14, P0_15 and the source electrode of transistor P1_7.
Among transistors P1_0 to P1_7, the gate electrodes of the even-numbered transistors P1_0, P1_2, P1_4, P1_6 are connected to node G1 and the gate electrodes of the odd-numbered transistors P1_1, P1_3, P1_5, P1_7 are connected to node G1B. A node Net2_0 is connected to the drain electrodes of transistors P1_0, P1_1 and the source electrode of transistor P2_0. A node Net2_1 is connected to the drain electrodes of transistors P1_2, P1_3 and the source electrode of transistor P2_1. A node Net2_2 is connected to the drain electrodes of transistors P1_4, P1_5 and the source electrode of transistor P2_2. A node Net2_3 is connected to the drain electrodes of transistors P1_6, P1_7 and the source electrode of transistor P2_3. Among transistors P2_0 to P2_3, the gate electrodes of the even-numbered transistors P2_0, P2_2 are connected to node G2 and the gate electrodes of the odd-numbered PMOS transistors P2_1, P2_3 are connected to node G2B. A node Net3_0 is connected to the drain electrodes of transistors P2_0, P2_1 and the source electrode of transistor P3_0. A node Net3_1 is connected to the drain electrodes of transistors P2_2, P2_3 and the source electrode of transistor P3_1. The gate electrodes of transistor P3_0 and transistor P3_1 are connected to node G3 and node G3B, respectively. An output node OUT is connected to the drain electrodes of transistors P3_0, P3_1. The transistors are accordingly connected in a tree structure with the output node OUT as the root node.
The n-well 10 in which transistors P0_0 to P0_15, P1_0 to P1_7, P2_0 to P2_3, P3_0, and P3_1 are formed is connected at one or more points to a power supply node and held at a power supply potential VDD equal to or greater than the highest of the analog grayscale voltage levels at nodes VH0 to VH15.
In this circuit, the states of the output node OUT depend on the combinations of the logical states of nodes G0 to G3 as shown in FIG. 3. That is, one of the sixteen voltage levels at nodes VH0 to VH15 is selected and output to the output node OUT according to the combination of the states of nodes G0 to G3, which are indicated individually in FIG. 3 and also as a hexadecimal (HEX) input code. When nodes G0 to G3 are all at the low or '0' logic level, for example, transistors P0_0, P1_0, P2_0, and P3_0 are all turned on, so that the voltage level at node VH0 is output to the output node OUT. The other voltage levels at nodes VH1 to VH15 do not propagate to the output node OUT because the gate electrode of at least one of the transistors on each of the paths from nodes VH1 to VH15 to the output node OUT is at the high or '1' logic level and the relevant transistor is turned off.
FIG. 2 shows an eight-bit decoder circuit that selects and outputs one of two hundred fifty-six analog grayscale voltages (received at nodes VH0 to VH255) according to the states of eight input signals (received at nodes G0 to G7). The increased number of input signals and analog grayscale voltages and the resulting increased number of transistors cannot all-be shown in the drawing, but the circuit configuration follows the same plan as in FIG. 1.
In the circuit shown in FIG. 2, the states of the output node OUT depend on the combination of the logical states of nodes G0 to G7 as shown in FIG. 4. For each combination, one of the two hundred fifty-six voltage levels at nodes VH0 to VH255 is selected and output at the output node OUT. When nodes G0 to G7 are all at the '0' logic level (the input code is hexadecimal 00 h), for example, transistors P0_0, P1_0, P2_0, P3_0, P4_0, P5_0, P6_0, P7_0 are all turned on and the voltage level at node VH0 is output to the output node OUT. The other voltage levels at nodes VH1 to VH255 do not propagate to the output node OUT because the gate electrode of at least one of the transistors on each path from nodes VH1 to VH255 to the output node OUT is at the '1' logic level and the relevant transistor is turned off.
Further details of the circuits in FIGS. 1 and 2 can be found in Japanese Patent Application Publication No. 2000-183747, which discloses a resistor ladder for generating a plurality of grayscale voltages and a selection circuit for selecting one of the grayscale voltages output from the resistor ladder.
A problem with the above circuit configuration is that when the selected analog grayscale voltage is much lower than the substrate (n-well) voltage of the PMOS transistors, a comparatively long selection time becomes necessary, degrading the response speed of the circuit, and in some cases the expected analog grayscale voltage level is not obtained.
FIG. 5 is a graph illustrating current characteristics of a typical PMOS transistor. The horizontal axis indicates the gate-source voltage VGS, that is, the gate potential minus the source potential. The horizontal axis indicates the drain current IDS, that is, the current flowing from the source terminal to the drain terminal. The multiple curves correspond to different values of the substrate-source voltage VBS, which is the substrate potential minus the source potential. The arrow indicates the direction of, increasing substrate-source voltage VBS. It can be seen that the drain current IDS decreases not only with increasing gate-source voltage VGS, but also with increasing substrate-source voltage VBS.
FIG. 6 is an exemplary graph illustrating the analog grayscale voltages corresponding to the eight-bit input codes in the eight-bit decoder circuit shown in FIG. 2. The two hundred fifty-six analog grayscale voltages are related as follows:VH255>VH254>VH253> . . . >VH2>VH1>VH0Voltage VH255 is the highest level, closest to the power supply potential VDD, and voltage VH0 is the lowest level. When transistors P0_0 and P0_255 are selected, voltages are applied to their terminals as shown in FIGS. 7 and 8. In this case, if the gate-source voltages VGS of transistors P0_255 and P0_0 are denoted VGS—255 and VGS—0, respectively, and their substrate-source voltages VBS are denoted VBS—255 and VBS—0, these voltages are given by the following equations:VGS—255=0(ground level)−VH255=−VH255VBS—255=VDD−VH255VGS—0=0(ground level)−VH0=−VH0VBS—0=VDD−VH0
A source driver for driving a TFT liquid crystal typically has a positive analog grayscale voltage range from about (½)·VDD to VDD−0.2 volts. If voltages VH255 and VH0 are set to these values (VH255=VDD−0.2 and VH0=(½)·VDD), the above equations become:VGS—255=−VH255=0.2−VDDVBS—255=VDD−VH255=0.2VGS—0=−VH0=−(½)·VDDVBS—0=VDD−VH0=(½)·VDDUnder these conditions, if the operating point of transistor P0_255 is indicated by point A in FIG. 5, the operating point of transistor P0_0 is at point B. The drain current IDS at point B is significantly less than the drain current IDS at point A. That is, the current IDS that flows when analog grayscale voltage VH0 is selected is significantly less than the current IDS that flows when analog grayscale voltage VH255 is selected, and this difference shows up in the response times of these decoder circuit during the selection period.
When the two hundred fifty-six analog grayscale voltages decrease in sequence from VH255 to VH0 (VH255>VH254>VH253> . . . >VH2>VH1>VH0) as shown in FIG. 6, if the gate-source voltage VGS and substrate-source voltage VBS applied when transistors P0_255 to P0_0 are selected are denoted VGS—255 to VGS—0 and VBS—255 to VBS—0, respectively, these voltage are related as follows:VGS—255<VGS—254<VGS—253< . . . <VGS—2<VGS—1<VGS—0VBS—255<VBS—254<VBS—253< . . . <VBS—2<VBS—1<VBS—0If the drain currents IDS of transistors P0_255 to P0_0 are denoted IDS—255 to IDS—0, then from the graph in FIG. 5, these currents are related as follows, illustrating one of the characteristics of a PMOS transistor:IDS—255>IDS—254>IDS—253> . . . >IDS—2>IDS—1>IDS—0This indicates that the higher the analog grayscale voltage is, the larger the current becomes, and the lower the analog grayscale voltage is, the smaller the current becomes. The response time of a transistor decreases as the current flowing through it increases, so if the response times of transistors P0_255 to P0_0 are denoted T255A to T0A, they are related as follows:T255A<T254A<T253A< . . . <T2A<T1A<T0AThis indicates that the higher the analog grayscale voltage is, the shorter the response time becomes, and the lower the analog grayscale voltage is, the longer the response time becomes. FIG. 9 is a timing diagram illustrating the response at the output node OUT when analog grayscale voltages VH255 and VH127 are selected repeatedly in alternation. The analog grayscale voltages selected according to the input codes correspond to those shown in FIG. 4.
The notation TMAX in FIG. 9 indicates the maximum allowable response time. When the voltage at the output node OUT does not reach the selected analog grayscale voltage level within this time, a liquid crystal display fault such as a bright or dark line or an irregular color may appear.
From the relationship T255A<T254A<T253A< . . . <T2A<T1A<T0A, the response time at the output node OUT is the shortest when analog grayscale voltage VH255 is selected, and is longer when other analog grayscale voltages are selected. The output node OUT reaches voltage level VH255 quickly, and response time T255A is sufficiently shorter than TMAX that no display fault occurs.
When analog grayscale voltage VH127 is selected, the voltages VGS, VBS are given as follows:VGS=−VH127, VBS=VDD−VH127Assuming from the grayscale voltage graph in FIG. 6 that the analog grayscale voltage VH127 is set such that VH127=(¾)·VDD, the above voltages VGS, VBS can be expressed as follows:VGS=−(¾)·VDD, VBS=(¼)·VDDThe current IDS in this case, which is given by point C in FIG. 5, is about half the current IDS that flows when analog grayscale voltage VH255 is selected. Therefore, the response time at the output node OUT is approximately doubled, but the output node OUT still reaches voltage level VH127 within a time not exceeding TMAX.
FIG. 10 is a timing diagram illustrating alternate selection of analog grayscale voltages VH255 and VH7 and the resulting response waveform at the output node OUT. Since the current IDS that flows when voltage VH7 is selected approaches the current at point B in FIG. 5, the response time T7A at the output node OUT becomes much longer than the response time T127A. The output node OUT now needs nearly the whole of time TMAX to reach voltage level VH7, but since the condition T7A<TMAX is still met, no display fault occurs.
FIG. 11 is a timing diagram illustrating alternate selection of the analog grayscale voltages VH255 and VH0 and the resulting response waveform at the output node OUT. Since the current IDS that flows when voltage VH0 is selected is given by point B in FIG. 5, it is very greatly decreased, and the response time T0A at the output node OUT becomes even longer than response time T7A, exceeding the allowable time TMAX. In this case, since the output node OUT fails to reach the selected analog grayscale voltage level VH0 within the necessary time, the liquid crystal display cannot display the expected color, which may cause display faults such as, for example, a bright or dark line or an irregular color. Furthermore, if the analog grayscale voltage range is widened and voltage level VH0 is further decreased, or if the VGS and VBS characteristics of the PMOS transistors are degraded, the operating point when voltage VH0 is selected may move from the point B to point D in FIG. 5. At point D the gate-source voltage VGS fails to exceed the PMOS transistor threshold voltage (VTH), so the current IDS falls to substantially zero.
FIG. 12 is a timing diagram illustrating the response waveform at the output node OUT when the transistors operate at point D in FIG. 5. When the selection is changed from voltage VH255 to voltage VH0, the output node OUT begins to approach voltage level VH0, but then the gate-source voltage VGS of transistor P0_0 crosses the PMOS transistor threshold voltage (VTH), so transistor P0_0 turns off before the output node OUT reaches voltage level VH0. Therefore, the output voltage level at the output node OUT cannot reach voltage level VH0 even after an indefinitely long time.
As described above, in the conventional circuit, the voltages VGS and VBS increase as the selected analog grayscale voltage decreases, which may lead to a great reduction in current flow through the transistors in the decoder circuit. Resulting problems are that the selected analog grayscale voltage cannot be output within the necessary time, and in some cases cannot be output at all.


A method for preventing colorectal cancer in a patient possessing human tropomyocin isoform TC22 is disclosed. The method comprises: (a) detecting a serum protein concentration of TC22 in a patient and (b) administering to said patient prior to detecting colorectal cancer in said patient a therapeutically effective amount of a chemotherapeutic composition comprising a chemotherapeutic compound that reduces the level of TC22, wherein the chemotherapeutic compound is selected from the group consisting of sulfasalazine, 5-amino-2-hydroxybenzoic acid, osalazine, and balsalazide.

Colorectal cancer, or cancer of the colon and rectum, is the second leading cause of cancer-related deaths in the United States, and the third most common cancer overall. The American Cancer Society estimates that each year more than 50,000 Americans die from colorectal cancer and approximately 155,000 new cases are diagnosed, accounting for 15% of all types of tumor. Eighty to 90 million Americans (approximately 25% of the U.S. population) are considered at risk because of age or other factors. More women over the age of 75 die from colorectal cancer than from breast cancer. The 5-year survival rate remains at approximately 45%.
The exact causes of colorectal cancer are unknown, but the disease appears to be caused by both inherited and lifestyle factors. Known predisposing conditions for colorectal cancer include familial adenomatous polyposis (FAP), hereditary nonpolyposis colon cancer (HNPCC), Lynch I Syndrome, Lynch II Syndrome, family cancer syndromes, adenomatous polyps (sessile or tubular), and inflammatory bowel disease, including both chronic ulcerative colitis (UC) and Crohn's disease.
Autoimmunity has been emphasized in the pathogenesis of UC. Autoimmune responses (both humoral and cellular) against human tropomyosin (TM) isoform 5 (hTM5) in UC have been reported (Gastroenterology 114:912, 1998, Clinical Immunology 101:289, 2001). hTM 5 is the predominant TM in colon epithelial cells and is expressed on the colon epithelial cell surface which may be critical for autoimmune effector response.
WO 03/007890, the contents of which are incorporated herein by reference in their entirety, discloses a novel hTM isoform, TC22. TC22 is strongly associated with colonic neoplasia and carcinoma (with almost 100% sensitivity) but is not detected in normal colon epithelium (Gastroenterology 123:152, 2002). TC22 is identical to hTM5 apart from the C-terminal domain. Recently, a pilot study of non-dysplastic, colonic tissues from UC and normal subjects showed that TC22 expression was associated with UC complicated with primary sclerosing cholangitis and long standing pancolitis—the two conditions known to be strongly associated with colon cancer in UC (Xin, Jeng et al., "Expression of a Novel Biomarker in Colonic Mucosa of Patients with Ulcerative Colitis At High Risk For Colon Cancer," Gastroenterology vol. 126, T1229 (2004)).
U.S. Pat. Nos. 5,498,608 and 5,905,073 disclose the use of 2-hydroxy-5-phenylazobenzoic acid derivatives as colon cancer chemopreventive and chemotherapeutic agents. However, the mechanism by which these chemotherapeutic agents operate is not entirely understood.

Chemoprevention of colorectal cancer by mesalamine/sulfasalazine

RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY


Systems and methods for quantitatively imaging retinal blood vessel oxygen saturation using retinal auto-fluorescence (AF) are provided. One or more excitation sources can be used to provide light to the retina, and retinal AF can be detected by one or more detectors. The quantitative level of oxygen saturation in the blood can be determined based on the intensity of AF.

Oxygen supply to retinal neurons is vital to their survival and functions. Reduced oxygen supply leads to hypoxia in the retina, which can have pathological consequences, including retinal edema (especially in the macular region), neovascularization, and even cell death. This is seen in many retinal diseases, including diabetic retinopathy, age-related macular degeneration, glaucoma, and retinopathy of prematurity. Assessing the oxygen saturation in the retinal vasculature is therefore of great clinical value.

Retinal blood vessel oximetry using retinal auofluorescence

The Florida International University Board of Trustees


An in-line coaxial circuit assembly having a first portion with a first electrical connector interface on a first end and a second portion having a second electrical connector interface on a second end. The first portion and the second portion adapted to couple together along an outer wall of at least one of the first portion and the second portion. A cylindrical outer conductor section coaxial with the outer wall may be formed in at least one of the portions. The coupling of the first portion and the second portion forms an enclosed cylindrical PCB chamber between the outer conductor section and inner conductor or outer wall, if present. A PCB may be positioned within the PCB chamber, the PCB coupled to the inner conductor through a slot in the outer conductor section, if present.

Electrical circuits such as filters, surge suppression, DC bias injection and or monitoring assemblies of various configurations have been adapted into modular assemblies for easy insertion in-line with coaxial transmission lines. Typically, a housing having a desired coaxial connector interface at either end is formed with a chamber adapted to receive a printed circuit board (PCB) with the required components and interconnecting circuitry. To minimize the opportunity for moisture infiltration, electrical interference and or vibration failure the PCB chamber is fully enclosed and environmentally sealed within the housing.
To minimize the degradation of signals in the transmission line from impedance discontinuities, the assembly typically has a pass through section along a longitudinal axis with center and outer conductor dimensions and spacing similar to those of the expected coaxial transmission line the housing is designed to be used with. Therefore, the PCB chamber has typically been formed as an off-axis extension of the housing in the form of a generally rectangular milled or cast cavity of the surrounding housing. Because the PCB chamber cavity(s) are off-axis, with respect to the pass through section, forming the prior housing requires separate axis specific housing re-mounting steps to complete milling operations during manufacture, significantly increasing the cost of the resulting assembly.
In-line coaxial assemblies with a cylindrical central cavity, formed coaxial with the pass through section have been used to enclose spiral inductor surge suppressor elements that couple the inner conductor to the outer conductor, without a PCB. However, the central cylindrical inner cavity presents a significant impedance discontinuity with respect to the dimensions of the associated coaxial cable and the lack of a PCB prevents the use of more complex electrical circuits.
The increasing competition for in-line RF assemblies has focused attention on cost reductions resulting from increased materials, manufacturing and service efficiencies. Further, reductions in required assembly operations and the total number of discrete parts are desired.
Therefore, it is an object of the invention to provide an apparatus that overcomes deficiencies in the prior art.


A transmission line driver and a serial interface data transmission device including the same are provided. The transmission line driver includes a pre-driver configured to generate and output differential input data signals based on a serial transmission data signal, a differential amplifier configured to receive the differential input data signals and to output differential output data signals, and a common mode controller configured to drive the differential output data signals to a predetermined common mode voltage in an idle mode. Accordingly, power consumption can be reduced and a common mode specification can be supported.

FIG. 1 illustrates a conventional transmission line driver 100. The transmission line driver 100 is included in a high-speed serial interface device and has a source coupled logic (SCL) structure. The transmission line driver 100 includes a first transistor 110, a second transistor 115, a current source 120, a first resistor 130, and a second resistor 140 that are connected as shown.
The first transistor 110 is connected to a first power supply terminal and a first output terminal 101 and is switched in response to a first input signal "in" input from a first input terminal. The first transistor 110 is an NMOS transistor and is connected to the first power supply terminal via the current source 120. A ground voltage is applied to the first power supply terminal. A first output signal "out" is output via the first output terminal 101.
The second transistor 115 is connected to the first power supply terminal and a second output terminal 102 and is switched in response to a second input signal "ip" input from a second input terminal. Like the first transistor 110, the second transistor 115 is an NMOS transistor and is connected to the first power supply terminal via the current source 120. A second output signal "outb" is output via the second output terminal 102.
The first resistor 130 is connected to a second power supply terminal Vdd and the first output terminal 101 and the second resistor 140 is connected to the second power supply terminal Vdd and the second output terminal 102. The resistance value of the first and second resistors 130 and 140 is about the same as a terminal resistance value Rt (e.g., 50 ohms) of a differential transmission line connected with the first output terminal 101 and the second output terminal 102.
The first input signal "in" and the second input signal "ip" are generated based on a serial transmission data signal. In a normal mode, the first input signal "in" and the second input signal "ip" have different logic levels; therefore, the first transistor 110 and the second transistor 115 operate complementarily. Accordingly, a differential output voltage of the transmission line driver 100 (i.e., a difference between the first output signal "out" and the second output signal "outb") is I×(50Ω//50Ω) [V] in the normal mode. "I" is the amount of current flowing in the current source 120. When the differential output voltage is 1000 mV, I=20 [mA]. However, as a power supply voltage (e.g., Vdd) is decreased, influence of power consumption occurring in the transmission line driver 100 is increased. Therefore, it may be desirable to reduce the current "I" flowing in the current source 120, which induces power consumption in the transmission line driver 100.

Transmission line drivers and serial interface data transmission devices including the same


A data compression apparatus and method for improving data compression efficiency are provided. The data compression apparatus includes a searcher for calculating costs, by searching domain blocks arranged in forward direction in a search range, between a range block and the domain blocks and for generating distance and difference information, by searching the costs in backward direction, between the range block and the domain block that incurs the lowest cost and a coder for encoding the distance and difference information into compressed data of the range block.

1. Field of the Invention
The present invention relates to a data compression apparatus and method. More particularly, the present invention relates to an apparatus and method for improving a memory compression ratio and access speed.
2. Description of the Related Art
Typically, digital data processing systems equipped with memory devices operate with various memory management techniques for efficient memory utilization. One approach is to compress data in a writing mode and to decompress the data for use in a reading mode. In this case, an increase of a compression ratio improves memory utilization, but reduces compression/decompression speed, resulting in an increase of memory access time. In contrast, a low compression ratio decreases the memory access time, but the memory utilization is degraded. Accordingly, there is a need to develop a data compression/decompression method that is capable of achieving a high compression ratio without compromising memory access speed.

This patent is subject to a terminal disclaimer.


A ceramic fiber composite structure particularly suitable for use as a hot gas cleanup ceramic fiber composite filter and method of making same from ceramic composite material has a structure which provides for increased strength and toughness in high temperature environments. The ceramic fiber composite structure or filter is made by a process in which a continuous ceramic fiber is intimately surrounded by discontinuous chopped ceramic fibers during manufacture to produce a ceramic fiber composite preform which is then bonded using various ceramic binders. The ceramic fiber composite preform is then fired to create a bond phase at the fiber contact points. Parameters such as fiber tension, spacing, and the relative proportions of the continuous ceramic fiber and chopped ceramic fibers can be varied as the continuous ceramic fiber and chopped ceramic fiber are simultaneously formed on the porous vacuum mandrel to obtain a desired distribution of the continuous ceramic fiber and the chopped ceramic fiber in the ceramic fiber composite structure or filter.

The present invention relates in general to a new and useful ceramic fiber composite structure and a method of making same and, in particular, to a ceramic fiber composite filter useful for hot gas cleanup applications which employs a distribution of continuous ceramic fiber and chopped ceramic fibers throughout the filter which results in a unique, lightweight construction having improved strength and toughness.
Furnace exhaust gases resulting from the combustion of fossil fuels typically contain many impurities. Filters have been used to reduce or eliminate the impurities in such furnace exhaust gases. However, there is an increased need for improved filters which are capable of withstanding higher temperatures and pressures for removing particulates from hot combustion gases.
Advanced coal-fired power generation systems such as integrated gasification combined cycle (IGCC) or pressurized fluid bed combustor (PFBC) based systems rely on hot gas filtration equipment to meet turbine inlet gas stream requirements and clean air requirements. In the case of the pressurized fluidized bed combustor (PFBC), the combustion gas stream is provided at a temperature of approximately 1600.degree. F. (871.degree. C.) and it contains both coal ash and fluidized bed material.
In order to maintain system efficiency, it is necessary that the filter system operate at or close to the combustion temperature. Both metal and ceramic tubular or candle (closed-end tube) filters are used to separate the particulates from the gas stream at elevated temperature. Tube filters and candle filters both utilize rigid ceramic filter elements. In tube filter systems, the ceramic filter element is mounted between tube sheets and the gas flows from the inside to the outside of the element. In candle filter systems, the dirty gas is on the outside of the filter element and clean gas flows into the inside of the element. Ash accumulations on the filter surface are removed by back-pulsing with high pressure gas applied in the reverse flow direction at regular intervals ranging from a few minutes to a few hours. Since the back-pulse gas may be at ambient temperature or only slightly pre-heated, the back-pulse process subjects the filter material to a significant thermal transient condition. In addition, unpredictable system upsets, such as combustor or turbine trips, may result in even more severe thermal transients. Filter failures have been attributed to the accumulation of damage caused by these types of thermal transients. Finally, the hot gas filters must also be resistant to the corrosive effects of any alkali, sulfur, and steam components contained within the hot combustion gas stream.
The ceramic filter elements are typically made of a dense, coarse-grained refractory material, such as Cordierite or silicon carbide, and bonded with a second phase. The bond phase may be crystalline or glassy and it is critical to the strength and corrosion resistance of the filter. The open porosity of such monolithic filter materials is approximately 40 percent. The bend strength of monolithic filter materials is in the range of 1 to 4 ksi (ksi=1000 lbs-per square inch). The fracture behavior is brittle which typically results in catastrophic failure of the filter element.
Various ceramic fiber-based filter elements are under development. These include vacuum formed chopped ceramic fiber filters, chemical vapor infiltration (CVI) bonded ceramic fiber filters, and sol-gel bonded continuous ceramic fiber filter elements. One type of filter is produced by vacuum forming chopped or discontinuous ceramic fiber on a mandrel using standard non-woven or felt production methods. The vacuum formed chopped ceramic fiber preforms are impregnated with aluminum oxide and/or silicon dioxide colloidal solutions and heat treated to develop a bond at the fiber contact points. The resulting filter element exhibits bend strengths in the range of 200 to 500 psi (pounds per square inch). Higher strength is required to meet the thermal and mechanical demands of this application. The filters composed of continuous ceramic fibers bonded by chemical vapor infiltration silicon carbide exhibit acceptable strength, but may not be chemically stable in the oxidizing or other corrosive environments of a pressurized fluidized bed combustion system.
A similar type of high temperature ceramic composite filter is disclosed in U.S. Pat. No. 5,196,120 to White. The ceramic fiber filter is useful in filtering gases at elevated temperatures, such as those from a furnace, and the filter is composed of ceramic fibers coated with an intermediate carbonaceous layer and an outer coating of silicon carbide using chemical vapor deposition. In one embodiment, the filter has a rigid preform base of continuous ceramic fiber strands. Discontinuous fibers may be applied as an optional step following production of the preform, by immersing the preform in a slurry tank and creating a vacuum inside the preform to attract the discontinuous fibers (see Col. 3, line 52 to Col. 4, line 5). White thus teaches that a vacuum wound preform coated with a slurry of chopped fiber is known. Instead, the preform and discontinuous fibers are treated with phenolic resin, and then heated in successive steps to cure and bind the fibers together. Further, White also indicates that winding of the preform and the coating with chopped fiber slurry are two distinct steps, rather than one simultaneous, continuous step. The resulting preform is therefore comprised of separate layers of continuous fibers and chopped fibers.
Singh et al. (U.S. Pat. No. 5,407,734) teaches a ceramic fiber composite laminated tape. The tape is composed of a layer of fibrous material, with spaces between the fibers, which is coated with a slurry of ceramic fiber whiskers and organic binding material. Several tapes are then combined and laminated to form the composite tape. The laminated tape is then heated to drive off the organic binding material and hot pressed to form the composite. Singh et al. discloses the use of silicon and aluminum compounds for making the ceramic fiber. Singh et al. also discusses prior slurry coating techniques and bonding techniques. In col. 1, lines 16-35 of Singh et al. states that passing a filament through slurry does not attract enough matrix components, and that chemical vapor deposition methods of binding the materials is too slow.
Farris et al. (U.S. Pat. No. 5,102,601) teaches fabricating a composite by extruding a viscous fiber and passing the fiber through a water bath to cause coagulation of the fiber material before winding it on a take-up roll. This teaching of this patent is distinct from the present invention in that it does not coat a fiber with slurry in the tank, but is instead using the tank to cure the fiber material.
Stinton et al. (U.S. Pat. No. 5,075,160) discloses a filter for removing particulate matter from high temperature flowing fluids, particularly gases, that is reinforced with ceramic fibers and coated with a thin layer of a protective and bonding refractory applied by chemical vapor deposition (CVD) techniques. A thin and extended layer of a ceramic felt, paper, etc. forms the preform which is coated with the ceramic, and is advantageously silicon carbide (SiC).
The use of chemical binders with some ceramic fiber and metal composites is disclosed in an article by Jeng-Maw Chiou and D.D.L. Chung, entitled, "Improvement of the temperature resistance of aluminum-matrix composites using an acid phosphate binder--Part 1--Binders", appearing in the Journal of Materials Science 28, p.1435-1446, .COPYRGT. 1993 Chapman & Hall. The article discusses various binder compositions, such as silica and phosphate binders, and their uses in forming ceramic-metal matrix compositions.
Eggarstedt, of Industrial Filter & Pump Mfg. Co., Inc. discusses work performed under DOE contract DE-FG02-92ER81349 from Jul. 22, 1992 to Feb. 17, 1995 in a paper entitled "IF&P Fibrosic.TM. Filters". The paper discloses formation of ceramic filter elements using vacuum formed chopped ceramic fiber. However Eggarstedt does not disclose any simultaneous application or use of continuous ceramic fibers in addition to the chopped fiber, in contrast to the present invention.
There remains a critical need to develop a more rugged hot gas filter tube material in order to improve the reliability of the aforementioned advanced energy systems.

Method of making a continuous ceramic fiber composite hot gas filter


A head band device for protecting a wearer's eyes from perspiration from the wearer's forehead is provided. A substantially nonabsorbent band includes a front band portion and two side band portions. The gutter structure extends from an outer surface of the band. The gutter structure includes a gutter base and a gutter lip. The gutter structure in combination with the front band portion and at least part of the first and second side band portions forms a perspiration channel with a generally U-shaped cross-section. The gutter base has a first thickness at a central portion thereof. The gutter base has a second thickness at end portions thereof. The first thickness is greater than the second thickness. The gutter base slopes from the central portion downward toward the end portions thereof, transitioning from the first thickness to the second thickness. A closure system has two fasteners and an elastic loop member.

When a person perspires, the perspiration from one's forehead flows downward and often flows into one's eyes. To overcome this problem numerous head bands are known which absorb the perspiration on the forehead before it can flow into one's eyes. In this respect, throughout the years, a number of innovations have been developed relating to perspiration absorbent head bands, and the following U.S. patents are representative of some of those innovations: U.S. Pat. Nos. 5,073,989, 5,590,422, 5,901,381, and 5,926,849. One problem associated with any head band that absorbs perspiration is the problem of saturation. When the head band becomes saturated with perspiration, it can no longer absorb perspiration. As a result, either the wearer must take the head band off and squeeze out the absorbed perspiration, or excess perspiration will flow out from the saturated absorbent. Hence, these is a need for a head band that prevents sweat from getting in one's eyes, even after a long period of time when conventional head bands would be saturated and dripping perspiration into one's eyes.

Perspiration redirecting head band device


A frequency dividing circuit, which is easy to form as an IC and which offers reduction both in size and power consumption, has a register "a" for storing the difference between the denominator and the numerator of the fractional frequency dividing ratio, another register "b" for storing the numerator of the fractional frequency dividing ratio, a selector for selecting one of the registers and connecting the selected register to a computing unit, a flip-flop for picking up the output from the computing unit in timing with the signal to be frequency-divided, a comparator for comparing the value stored in the register "a" and the value held by the flip-flop, and a logical circuit for computing AND of the output from the comparator and the signal to be frequency-divided.

1. Field of the Invention
The present invention generally relates to a frequency dividing circuit and, more particularly, to a frequency dividing circuit having a frequency dividing ratio which is a rational number smaller than 1. The present invention is also concerned with a frequency dividing method and a telephone terminal device which employ the frequency dividing circuit.
2. Description of the Related Art
A conventional frequency dividing circuit having a fractional frequency dividing ratio, i.e., a rational number smaller than 1, incorporates an oscillating circuit. Such an oscillating circuit employs a PLL (Phase Lock Loop) which uses, as a comparative frequency, the frequency obtained by dividing a base clock frequency by the denominator of the frequency dividing ratio. Known also is a frequency dividing circuit having a counter for receiving a base clock signal and a logical circuit or a storage device which receives the output from the counter so as to select the clock pulses to be delivered from among the base clock pulses.
A description will be given of the conventional frequency dividing circuit which employs PLL, with specific reference to FIG. 6. The circuit shown in FIG. 6 is designed to produce, upon receipt of input pulses of a frequency f.sub.0, output pulses at a fractional frequency dividing ratio of N.sub.2 /N.sub.1. The circuit has the following components: a counter 41 which divides the input frequency f.sub.0 by the denominator N.sub.1 of the frequency dividing ratio, i.e., multiplies the same by 1/N.sub.1, to determine the quotient f.sub.0 /N.sub.1 ; a phase comparator 42 which performs phase comparison by using the quotient f.sub.0 /N.sub.1 as the comparative frequency; a low-pass filter (LPF) which passes the output from the phase comparator 42; a voltage-controlled oscillator (VCO) which oscillates at a frequency corresponding to the output voltage derived from the LPF 43; and a counter 45 which divides the output oscillation pulses of the VCO 44 by the numerator N.sub.2 of the frequency dividing ratio.
Representing the oscillation frequency of the VCO 44 by f.sub.1, the quotient f.sub.1 /N.sub.2 produced by the counter 45 is delivered to the phase comparator 42 which performs phase comparison between the quotient f.sub.1 /N.sub.2 and the quotient f.sub.0 /N.sub.1 and produces a voltage corresponding to the phase differential. This voltage is delivered to the VCO 44, so that the VCO oscillates at a frequency corresponding to this voltage. In this system, the two inputs which are input to the phase comparator 42 are made to progressively converge into two signals which have an equal frequency with a constant phase differential therebetween. Consequently, the condition of f.sub.0 /N.sub.1 =f.sub.1 /N.sub.2 is established to provide the output frequency f.sub.1 which is given by f.sub.1 =f.sub.0 N.sub.2 /N.sub.1, whereby clock pulses of the frequency f.sub.1, which is the result of frequency-division at the fractional frequency-dividing ratio of N.sub.2 /N.sub.1, is obtained at the output terminal of the VCO 44.
This frequency dividing circuit, which incorporates the oscillation circuit employing PLL, has to deal with an analog voltage corresponding to the phase differential, so that the whole circuit inevitably incorporates both analog and digital circuits, making it difficult to construct the whole circuit in the form of an integrated circuit (IC). As a consequence, the scale of the circuit is enlarged and the power consumption is increased. Another problem is that a comparatively long time is required until the clock frequency is stabilized, due to characteristics of the automatic control.
The later-mentioned type of frequency dividing circuit, which relies on the combination of a counter with a logical circuit or a storage device, can be constructed purely digitally and, hence, contributes to miniaturization of the circuit through circuit integration and also to reduction in power consumption. This type of frequency dividing circuit, however, is still unsatisfactory in that it cannot fully meet the requirements of performance posed by current electronic devices.

Frequency dividing circuit, frequency dividing method and telephone terminal device incorporating the frequency dividing circuit


A helmet which performs good ventilation and which is capable of mitigating the uncomfortable feeling due to sound is provided. The shock absorbing liner includes front ventilation holes to communicatively connect the front openings to the inside of the shock absorbing liner, outside air paths disposed in a space on an outer side relative to an inner surface of the shock absorbing liner, and communicative holes to communicatively connect the inside of the shock absorbing liner to the outside air paths. The outside air paths include primary flow paths disposed to be connected to the rear opening and secondary flow paths. The communicative holes communicatively connects positions on an outer surface of the shock absorbing liner except positions of the primary flow paths, to the inside of the shock absorbing liner. The secondary flow paths are disposed to connect the communicative holes to the primary flow paths.

Field of the Invention
The present invention relates to a helmet including an outer shell which has front openings and rear openings, and including air conduits or paths for ventilation inside.
In the present specification, directions associated with the helmet are defined based on the helmet wearer in an upright position, specifically, the side which the helmet user naturally faces is regarded as the front side and the other directions such as the rear direction, the right direction, and the left direction are accordingly defined.
Description of the Prior Art
Examples of a helmet in which air paths are disposed have been described in Japanese Patent Nos. 751575 and 1965000.
Japanese Patent No. 751575 describes a configuration of a helmet in which grooves are disposed on the outer surface of a shock absorbing liner such that the grooves and the inner surface of the shell configure air paths linked to a rear edge of the helmet, and communicative holes are disposed so as to communicatively connect the inner surface of the shock absorbing liner to those air paths.
Japanese Patent No. 1965000 describes a configuration of a helmet in which at least a part of a shock absorbing liner consists of an outer layer and an inner layer, air paths are formed on inner side of the combined layers, and communicative holes are disposed so as to communicatively connect the inner surface of the shock absorbing liner to those air paths.


A micro oscillating element includes a frame and an oscillation section connected to the frame via a torsional joining section. The oscillation section includes a movable functional section, an arm section and a first comb-tooth electrode. The arm section extends from the functional section. The first comb-tooth electrode includes first electrode teeth extending from the arm section in a direction intersecting the arm section. The micro oscillating element further includes a second comb-tooth electrode to cooperate with the first comb-tooth electrode for causing the oscillation section to oscillate about an oscillation axis defined by the torsional joining section. The second comb-tooth, electrode includes second electrode teeth extending from the frame in a direction intersecting the arm section.

1. Field of the Invention
The present invention generally relates to a micro oscillating element having an oscillation section capable of rotary displacement. In particular, the present invention relates to a micromirror element, an acceleration sensor, an angular velocity sensor, and a vibration element, for example.
2. Description of the Related Art
In recent years, elements having a microstructure formed by micromachining technology have been put to practical use in various technological fields. In the field of optical communication technology, for example, minute micromirror elements having a light reflecting function are gaining attention.
In optical communication, optical signals are transmitted using optical fiber as a medium, and an optical switching device is typically used to switch the transmission path of the optical signal from one fiber to another fiber. To achieve favorable optical communication, the characteristics required of the optical switching device include a large capacity, high velocity, and high reliability during the switching operation. With these considerations in mind, high expectations are being placed on optical switching devices incorporating a micromirror element manufactured using micromachining technology. A micromirror element is capable of performing switching processing between an input side optical transmission path and an output side optical transmission path in the optical switching device without converting the optical signal into an electrical signal, and is therefore suitable for obtaining the characteristics listed above.
A micromirror element comprises a mirror surface for reflecting light, and is capable of varying the direction in which the light is reflected by oscillating the mirror surface. Electrostatic micromirror elements which use electrostatic force to tilt the mirror surface are employed in many devices. Electrostatic micromirror elements can be divided into two main types, those manufactured by so-called surface micromachining technology, and those manufactured by so-called bulk micromachining technology.
In surface micromachining technology, material thin film corresponding to each constitutional region is machined into a desired pattern, and such patterns are laminated successively to form the various regions constituting the element, such as a supporting and fixing portion, an oscillation section, a mirror surface, and an electrode portion, and a sacrificial layer which is removed at a later stage. In bulk micromachining technology, on the other hand, a material substrate is itself etched to form the fixing and supporting portion, the oscillation section, and so on into a desired form, whereupon the mirror surface and electrodes are formed with thin film. Bulk micromachining technology is described in Japanese Unexamined Patent Application Publication H9-146032, Japanese Unexamined Patent Application Publication H9-146034, Japanese Unexamined Patent Application Publication H10-190007, and Japanese Unexamined Patent Application Publication 2000-31502, for example.
One of the technological items required of a micromirror element is that the mirror surface for reflecting light has a high degree of flatness. However, with surface micromachining technology, the mirror surface that is ultimately formed is thin, and therefore buckles easily. Accordingly, it is difficult to achieve a high degree of flatness on a mirror surface with a large surface area. Conversely, with bulk micromachining technology, the relatively thick material substrate itself is cut into by etching technology to form a mirror supporting portion, and the mirror surface is provided on the mirror supporting portion. Hence the rigidity of even a mirror surface with a large surface area can be secured. As a result, a mirror surface having a sufficiently high degree of optical flatness can be formed.
FIG. 32 is a partial perspective view of a conventional micromirror element X6 manufactured according to bulk micromachining technology. The micromirror element X6 comprises a mirror supporting portion 61 provided with a mirror surface 64 on its upper face, a frame 62 (partially omitted from the drawing), and a pair of torsion bars 63 connecting the mirror supporting portion 61 and frame 62. Comb-tooth electrodes 61a, 61b are formed on the pair of end portions of the mirror supporting portion 61. A pair of inwardly-extending comb-tooth electrodes 62a, 62b is formed on the frame 62 corresponding to the comb-tooth electrodes 61a, 61b. The pair of torsion bars 63 defines an oscillation axis A6 of the oscillating operation of the mirror supporting portion 61 in relation to the frame 62.
In the micromirror element X6 constituted in this manner, one set of the comb-tooth electrodes provided close to each other for generating a driving force (electrostatic attraction), for example the comb-tooth electrodes 61a and 62a, are oriented in two tiers when no voltage is applied, as shown in FIG. 33A. However, when a predetermined voltage is applied, the comb-tooth electrode 61a is attracted toward the comb-tooth electrode 62a, as shown in FIG. 33B, whereby the mirror supporting portion 61 is rotationally displaced. More specifically, when the comb-tooth electrode 61a is charged positively and the comb-tooth electrode 62a is charged negatively, the comb-tooth electrode 61a is attracted toward the comb-tooth electrode 62a, and thereby the mirror supporting portion 61 is rotationally displaced about the oscillation axis A6 with the torsion bars 63 being twisted. By driving the mirror supporting portion 61 to tilt in this manner, the reflection direction of the light that is reflected by the mirror surface 64 provided on the mirror supporting portion 61 is switched.
To miniaturize the micromirror element X6 along the oscillation axis A6, the length L61 of the mirror supporting portion 61, which occupies most part of the element, need be shortened. However, shrinking the length L61 cannot easily be compatible with maintaining the driving force enough to oscillate the mirror supporting portion 61.
In the micromirror element X6, the plurality of electrode teeth of the respective comb-tooth electrodes 61a, 61b are supported on the mirror supporting portion 61 at intervals in the oscillation axis A6 direction, and therefore the number of electrode teeth of the comb-tooth electrodes 61a, 61b is restricted by the length L61 of the mirror supporting portion 61. As a result, the number of electrode teeth constituting the set of comb-tooth electrodes 61a, 62a and the number of electrode teeth constituting the set of comb-tooth electrodes 61b, 62b are restricted by the length L61 of the mirror supporting portion 61. Furthermore, in order to secure enough driving force to drive the oscillating operation of the mirror supporting portion 61, or in other words to secure the electrostatic attraction that can be generated between the comb-tooth electrodes 61a, 62a and the comb-tooth electrodes 61b, 62b, a sufficient surface area to allow the electrode teeth of the set of comb-tooth electrodes 61a, 62a to face each other and a sufficient surface area to allow the electrode teeth of the set of comb-tooth electrodes 61b, 62b to face each other must be secured. To secure such a surface area enabling the electrode teeth to face each other when the length L61 of the mirror supporting portion 61 has been reduced, a method of reducing a width d1 of each electrode tooth and narrowing a gap d2 between the electrode teeth such that the number of electrode teeth of the comb-tooth electrodes 61a, 61b, 62a, 62b is set at no less than a fixed number, or a method of increasing the distance between the mirror supporting portion 61 and the frame 62 and increasing a length d3 of each electrode tooth, may be considered.
However, reducing the width d1 and increasing the length d3 of the electrode teeth lead to a reduction in mechanical strength in the width direction of the electrode teeth. As a result, when a voltage is applied as described above with reference to FIG. 33B, the electrode teeth deform in the width direction thereof, causing a defect whereby the electrode teeth stick to adjacent teeth. Further, reducing the gap d2 between the electrode teeth leads to difficulties in the manufacturing process of the micromirror element X6, decreases in yield, and so on.
Hence there are difficulties involved in miniaturizing the micromirror element X6 through contraction of the oscillation axis A6 direction while maintaining enough driving force to drive the oscillating operation of the mirror supporting portion 61. In micro oscillating elements such as the micromirror element X6, a characteristic whereby large rotary displacement and a high speed oscillating operation can be realized at a low drive voltage is typically demanded of the region in which the oscillating operation takes place, but in order to obtain such a characteristic, the driving force for driving the oscillating operation of the oscillation section must be held at no less than a fixed level.

Micro oscillating comb tooth element with two interesecting oscillation axes


The terminal portions 222a, 222b of the contacts having the contact portions 221a, 221b belonging to (2n/2)-th contact portion tier 2-21 are arranged so as to be alternately allocated to the first terminal portion tier 1-22 and the second terminal portion tier 2-22.

This invention relates to an electrical connector and, in particular, relates to an electrical connector having an insulator and a plurality of contacts arranged in line in the width direction of the insulator, wherein the contacts each have a contact portion contactable with a first connection object such as a mating connector and a terminal portion adapted to be fixedly connected to a second connection object such as a printed circuit board.
As this type of electrical connector, there is one in which contact portions of a plurality of contacts are arranged in a plurality of contact portion tiers superposed in the vertical direction (height direction) of an insulator (housing), while, terminal portions of the contacts having the contact portions belonging to (arranged or located in) the respective contact portion tiers are arranged so as to be allocated to one or the other of two terminal portion tiers superposed in the vertical direction of the insulator.
Such an electrical connector is disclosed, for example, in Japanese Unexamined Patent Application Publication (JP-A) No. H7-335343. This publication discloses an electrical connector in which contact portions of a plurality of contacts are arranged in first to fourth contact portion tiers superposed in the vertical direction perpendicular to the width direction of an insulator. In this electrical connector, terminal portions of the contacts having the contact portions belonging to the first contact portion tier and terminal portions of the contacts having the contact portions belonging to the second contact portion tier are arranged in a first terminal portion tier, while, terminal portions of the contacts having the contact portions belonging to the third contact portion tier and terminal portions of the contacts having the contact portions belonging to the fourth contact portion tier are arranged in a second terminal portion tier.
In an electrical connector having an even number of contact portion tiers like the above electrical connector, terminal portions of contacts can be allocated to two terminal portion tiers in a balanced manner.
On the other hand, in an electrical connector having an odd number of contact portion tiers, terminal portions of contacts having contact portions belonging to the middle contact portion tier (e.g. the second contact portion tier when the total number of contact portion tiers is three or the third contact portion tier when the total number of contact portion tiers is five) are allocated to only one of a first terminal portion tier and a second terminal portion tier. Therefore, one of the terminal portion tiers has a greater number of terminal portions than the other terminal portion tier. This difference in number of terminal portions causes a difference in size between occupation spaces of both terminal portion tiers, particularly in the width direction of the electrical connector. Since the occupation space of the entire electrical connector depends on the terminal portion tier having the larger occupation space, it inevitably becomes large in size. This is disadvantageous for miniaturization of the electrical connector.
Further, in an electrical connector of the type adapted to sandwich a plate-shaped second connection object such as a printed circuit board between both terminal portion tiers thereof, the number of terminal portions for connection to one of plate surfaces of the second connection object becomes greater than that of terminal portions for connection to the other plate surface. Therefore, the stability of the electrical connector with respect to the second connection object is poor so that there is a possibility that the electrical connector is inclined in temporary fixing before soldering the terminal portions so as to be offset from the correct position and, after soldering the terminal portions, unwanted stress is applied to the soldered portions.

Electrical connector having contacts with contact portions arranged in three contact portion tiers

Japan Aviation Electronics Industry, Limited


There is provided novel thermosetting resin composition. A thermosetting resin composition comprising a polymer having at least one structural unit of the following Formula (1):

In recent years, higher integration of semiconductor devices has been required with enhancement in the performance and miniaturization of electronic appliances such as cell phones and IC cards. As a procedure for higher integration, the finer pattern of semiconductor elements themselves, and a stack structure in which semiconductor elements are stacked longitudinally have been investigated. In production of the stack structure, an adhesive is used for junction between the semiconductor elements.
In production of the stack structure, flip chip bonding has been known as a method of mounting an IC chip on a substrate. This is a method in which a plurality of bumps (projected terminals) are disposed and electrically connected to electrode terminals on the substrate. An underfill agent is used to seal a gap between the substrate and the IC chip and protect the IC chip against moisture and an exterior stress. As the underfill agent, a composition containing an epoxy resin has been used (e.g., Patent Documents 1 and 2). Conventionally, a method in which an underfill agent is injected after connection of a substrate and an IC chip to bumps (post-applied underfilling), and then thermally cured has been often used. However, miniaturization of bumps, a decrease in pitches, and an increase in the size of IC chips make the post-applying of an underfill agent difficult. As a countermeasure, a pre-applied underfilling will be mainly employed in the future, in which an underfill agent is previously formed on a wafer with bumps, the wafer is diced, and the diced IC chip is subjected to flip chip bonding.
In such flip chip bonding, bumps are connected readily after bonding of underfill. Therefore, a conventional adhesive described in Patent Document 3 makes it difficult to prevent generation of voids. This is because the adhesive is momentarily exposed to high temperature in an uncured state.
A wafer-on-wafer (WOW) structure in another method of producing a stack structure described in Patent Document 4 makes it difficult to employ a low molecular weight component that causes voids and a component that has low heat resistance and is decomposed. This is because the WOW structure requires adhesion between wafers without generation of voids.
A thermosetting resin composition containing a compound having an aromatic benzoxazine ring as a main chain has been known (e.g., Patent Documents 5 and 6). A benzoxazine resin having excellent heat resistance and electrical characteristics has been also known. The thermosetting resin composition containing a compound having an aromatic benzoxazine ring as a main chain described in Patent Documents 5 and 6 has low crosslink density and high linear expansion coefficient at a temperature equal to or higher than the glass transition point. Therefore, there is a concern of reduction in reliability caused by occurrence of cracks and peeling due to thermal history.
As a known technique, a technique of mixing an epoxy resin in a benzoxazine resin to improve the crosslink density has been known. However, a cross-linking reaction of the mixed resin is slow, and sufficient crosslink density is not obtained. As a countermeasure, a technique of adding an epoxy resin curing agent, which is typified by an imidazole-based compound, has been widely known. However, since the epoxy resin curing agent has low heat resistance, there is a concern of reduction in reliability caused by generation of voids.

Abstract: {wherein each of R1 and R2 is independently a hydrogen atom or a C1-4 alkyl group, X is a single bond or a divalent organic group, and Y is an arylene group of the following Formula (2):

Abstract: (wherein Z1 is a carbonyl group or a —CONH— group, Z2 is a C1-5 alkylene group or a 5- or 6-membered divalent saturated heterocyclic group containing at least one nitrogen atom, and Z3 is a 5- or 6-membered aromatic heterocyclic group containing two nitrogen atoms in which at least one of hydrogen atoms may be substituted by a C1-5 alkyl group)}.


A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.

1. Technical Field
The embodiments described here relate to a semiconductor integrated circuit (IC) and a method of controlling the same and, more particularly, to semiconductor IC and a method of controlling the same including a delay locked loop (DLL) circuit.
2. Related Art
In general, a DLL circuit is commonly used to provide an internal clock signal that is led by a predetermined time interval in a phase more than a reference clock signal obtained by converting an external clock signal. The DLL circuit generates a phase difference between the internal clock signal used in a semiconductor IC and the external clock signal by delaying the internal clock signal due to a clock buffer and a transmission line, such that it can be used to solve a problem of long output data access time. The DLL circuit performs a function of controlling the phase of the internal clock signal to lead by predetermined time interval ahead of the external clock signal.
The DLL circuit includes a clock input buffer to buffer the external clock signal, thereby generating a reference clock signal. Then, the delay clock output through the delay line provides a delay value acquired by modeling delay amount by delay elements existing in a path transmitted up to a data output buffer to the delay clock signal to generate a feedback clock signal. The DLL circuit includes a phase detector to perform comparison and detecting a phase of the reference clock signal and the feedback clock signal, such that it generates a delay control signal to allow the delay line to control the delay amount provided to the reference clock signal to generate the delay clock signal. The phase detecting signal output from the phase detector includes information upon which phase of the reference clock signal and the feedback clock signal leads. According to the information, the delay line provides positive delay time or negative delay time to the reference clock signal.
However, in order to achieve a high speed operation of the semiconductor IC, the semiconductor IC tends to use higher frequency clock signals. Accordingly, the DLL circuit performs a delay fix operation for the high frequency clock signals. As a result, the reference clock signal and the feedback clock signal input to the phase detector within the DLL circuit become a high frequency clock signal, such that they have a very short period. In the DLL circuit using the high frequency clock signal, as described above, even when slight jitter components are included in the reference clock signal or the feedback clock signal when the phase detector compares and detects the phase, errors occur in the phase comparing and detecting results. In many instances, the clock signals generated inside the DLL circuit substantially include the jitter components. This can serve as a factor for degrading reliability of the phase comparison and detecting results. These errors degrade performance of the DLL circuit and increase a defect rate of a data output operation of the semiconductor IC including the DLL circuit.

Semiconductor integrated circuit and method of controlling the same


The present disclosure relates to the field of semiconductor packaging processes, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with an exposed conductive structure; forming a passivation layer on the surface of the semiconductor substrate and a surface of the exposed conductive structure; etching the passivation layer to form a recess, where a bottom of the recess exposes one end of the conductive structure; forming an adhesion layer on a surface of the recess; and etching to form a hole in the bottom of the recess.

With the shrinking of the feature size of the semiconductor integrated circuit devices, the requirements for the semiconductor packaging processes technology are becoming increasingly stringent. The through-silicon via (TSV) packaging technology is to connect the chips vertically to realize the interconnection between the chips. It can realize the maximum stacking density in the three-dimensional (3D) direction and minimum overall size of the chips, and substantially improve speed and lower the power consumption performance of the chips.
The manufacturing process of the TSV packaging technology involves wafer hetero-bonding. It needs to control the depth of the contact surface of the metal layer at 1 to 5 nm, which imposes extremely high requirements for the process technology, making it hard to control. If the metal layer is too deep, there will be an open circuit between the metal sand cannot be connected. If the metal layer is too shallow, when the metal layer is squeezed by the bonding surface, it will be separated even after bonding or short-circuit with the adjacent metal layer. Therefore, it is necessary to control the stability of the back-side via exposure device in the chemical-mechanical process to avoid the open circuit problem of a too deep metal layer and the short circuit problem of a too shallow metal layer during chemical mechanical planarization, which is a technical problem that needs to be solved urgently.

Semiconductor structure and forming method thereof


Stable non-toxic pesticide composition having fungicidal and insecticidal properties including a pesticide that is nontoxic to mammals; one or more disinfectants; a vegetable oil; and one or more stabilizing agents. In one example, one or more stabilizing agents are selected and are present in an amount in combination with the selection and amount of a pesticide, one or more disinfectants, and a vegetable oil to provide the composition with stability upon application to a substrate effective to allow lethality against one or more target pests.

Conventional methods of eliminating pests (e.g., fungi, mosquitoes, flies, wasps, woodlice, bugs, beetles, grasshoppers, locusts) are toxic, carcinogenic, teratonogenic, expensive, and/or inefficient. Although many toxic pesticides (e.g., DDT, Lindan, Chlordan, etc.) are relatively inexpensive, they leave behind contamination in ground soil, water, plants and other substrates to which they may be applied in an attempt to come into contact with the target pests. This contamination works its way into humans and other mammals directly and up through the food chain. In some cases pesticide contamination can be measured in an area of application many years later.
Attempts have been made to utilize biological pesticides to mitigate the contamination that is known with toxic pesticides. However, biological pesticides suffer from poor stability over time in storage and after application. Thus, their efficacy has been limited to short-term, immediate uses.
The term "disinfectant" stands for substances or mixtures of substances for combating pathogenic microorganisms, or microorganisms that cause putrefaction, e.g. bacteria, viruses, fungus including spores. Disinfectants can minimize the risk of an infection of humans or animals, or minimize the onset of putrefaction. Since some bacteria, molds, yeasts and viruses can lead to severe diseases, disinfection cannot be dismissed from the everyday life in the medical sector and private households. The importance of disinfection for the well being of humans is often underestimated. In previous centuries more people died as a result of the large epidemics (the plague, cholera, pox or the flu) than were killed during the wars. As late as the beginning of the 20th century, severe bacterial infections were often a deadly disease even in the industrialized nations. In the countries of the so-called third world even today infectious diseases, mostly stemming from inadequate hygienic situations, claim countless deaths. Therefore a high demand for effective and inexpensive disinfectants exists, especially in the medical sector. This demand also exists in the agrarian sector particularly for fungicidal substances.
In order to obtain a highly disinfectant effect, in the past, above all, highly persistent chemical composites were used as disinfectants in order to have an effective and long-lasting protection against microorganisms. But this persistence leads to huge problems with respect to environmental aspects. The highly persistent disinfectants accumulate in the groundwater and/or the food chain, and thereby lead to ecological and health problems. For example, ecological problems can arise when disinfectants in high concentration reach biological wastewater treatment plants. In case of high concentrations of this disinfectant the microorganisms, which are necessary there, are affected in their growth, which can lead to a partial or complete failure of the wastewater treatment plant. Furthermore, persistent composites can accumulate in the sewage sludge.
A further disadvantage of conventional disinfectants is the development of resistances. Resistant causative organisms survive the treatment with the disinfectant, and can pass on their resistance to non-resistant microorganisms via the transmittal of extra chromosomal genetic material. Disinfection of microorganisms, which have developed a resistance this way, can lead to severe diseases. While this problem can currently be observed mainly in the sectors of hospitals (hospitalism) and farm animals, one can fear that such problems in the future can also occur in the sector of private households, given the fact that disinfectants are used more and more in household cleaning agents.
In order to overcome the health and ecological disadvantages of such persistent disinfectants, the use of less dangerous substances has been considered in the past, especially the use of natural substances with potential for disinfectant properties. Here it has turned out to be a disadvantage that the disinfectant effect is weaker and/or less long lasting, so that the advantage of better environmental compatibility is gained in exchange for disadvantages in regards to effectiveness and protection from microorganisms. Due to this drawback, less importance has been awarded to such ecologically compatible disinfectants and the use of environmentally hazardous compounds prevail.


A radio channel control method includes: collecting a real-time user experience index for access to a media service by a user terminal, and collecting a media service transmission parameter of the media service provided by a server; determining whether the real-time user experience index is less than a user experience index defined in a user experience level of an ordered traffic package of the user terminal, and if the real-time user experience index is less than the user experience index defined in the user experience level of the ordered traffic package of the user terminal, calculating, by using the real-time user experience index and the media service transmission parameter, a radio channel parameter that is required by the user experience index; and transmitting the radio channel parameter to a core network device.

At present, China Mobile has launched a data exchange platform (2 cm) in Hong Kong, and all users of the 4 G Pro series service plan of China Mobile Hong Kong Company Limited can freely buy and sell a traffic package included in their package plans by using the data exchange platform, to prevent the traffic from becoming invalid due to expiration. A traffic package is freely bought and sold on the data exchange platform in a unit of GB, and is freely priced within a range from HK$ 11 to HK$ 46. In addition, the data exchange platform may also charge a trading fee of HK$ 11 per unit.
However, it is found in practice that, after a user orders a traffic package and in a defined time period of the ordered traffic package, user experience (for example, watching a ball game or watching a video) in accessing a media service cannot be ensured, and enthusiasm for traffic trading cannot be aroused.

Radio channel control method, traffic package trading and recommending methods, and related device


Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.

The present invention relates generally to integrated circuits (ICs) and more specifically to the detection and adjustment of signal characteristics.
Integrated circuits (ICs) typically include many switching elements, such as transistors. These switching elements are configured to perform a variety of circuit functions.
The operation of a transistor is typically affected by its process, voltage, and temperature ("PVT"). The "process" component of PVT refers to the process of manufacturing a transistor. The process is often classified as "fast", "slow", "nominal", or anywhere in between. A transistor manufactured using a fast process will transmit signals at a faster rate as compared to a transistor manufactured using a slower process. Likewise, a transistor manufactured using a slow process will transmit signals at a slower rate as compared to a transistor manufactured using a faster process. Once a transistor is manufactured using a particular process, the effect of the process is fixed. Thus, the "process" component of PVT cannot be adjusted to change the operating characteristics of a manufactured transistor.
The "temperature" component of PVT is the temperature at which the transistor operates. Similar to the process used to manufacture a transistor, the temperature at which a transistor operates affects how a transistor operates. In particular, the rate at which a transistor transmits a signal is affected by the temperature at which the transistor operates. For example, a transistor operating at a reference temperature requires a first voltage to transmit signals at a first rate. If the temperature of the transistor decreases, less voltage is needed to transmit signals at the first rate. Similarly, if the temperature of the transistor increases, more voltage is needed to transmit signals at the first rate. The "temperature" component of PVT varies during operation of the transistor. While there is some control over the temperature of an IC, such temperature cannot be sufficiently adjusted to result in a change in its operating characteristics.
The only component of PVT that can be varied effectively during operation to adjust a transistor's characteristics is its voltage. The optimum supply voltage of a transistor varies depending on the transistor's process (e.g., fast or slow) and the transistor's operating temperature. A conventional solution to the variation in the optimum supply voltage is to set the supply voltage to a worst-case value. In transistors manufactured with a fast process or operating at a low temperature, this conventional solution often results in too much power being supplied to a transistor, with the excess power being dissipated.
As an example, if a circuit designer determines (e.g., via simulation of an IC having many transistors) that a transistor manufactured with a slow process needs 3.2 V as a supply voltage, the circuit designer may provide a supply voltage of 3.2 V to each transistor on the IC. If another transistor on the IC was manufactured with a fast process, however, that transistor may only need a supply voltage of 3.0 V. When 3.2 V is supplied, excess power is dissipated on the transistor that only needs 3.0 V as a supply voltage. As the number of transistors on the IC that were manufactured with a fast process (or are operating at a low temperature) increases, the amount of dissipated power increases.
For example, a serializer/deserializer (SerDes) is a circuit that converts parallel data to serial data and vice-versa. FIG. 1 shows an example SerDes circuit 100 having a pre-amplifier 105 in communication with one or more loads (e.g., latches 110-125) over a communication channel 130. The communication channel 130 may be a wire, a backplane, or any medium (e.g., air) that can transmit an output of the pre-amplifier 105 to the latches 110-125. Because the pre-amplifier 105 is transmitting its output signal over communication channel 130, the load (i.e., latches 110-125) seen by the pre-amplifier 105 may not be known. As a result, estimates of the load for fast and slow processes are used in simulation. The simulation often produces a worst-case design of the pre-amplifier 105 for a given load to allow for a load manufactured with a slow process. As stated above, this worst-case design typically results in excess power being dissipated.
FIG. 2 shows a block diagram of a transmitter 205 in communication with a receiver 210 over a communication channel 215. A signal's slew rate, or maximum rate of change with respect to time, typically degrades or changes if not optimized before the signal is transmitted over communication channel 215. This degradation is typically due to nonlinearities and imperfections in the communication channel 215. Further, the signal's swing, or the signal's maximum amplitude, may also degrade as the signal is transmitted over the communication channel 215 if the signal's swing is not optimized for the communication channel 215.
The communication channel is often modeled after making one or more assumptions about the transmitted signal's swing and the transmitted signal's slew rate. As a result, a circuit transmitting a signal via the communication channel operates in an optimum manner as long as the assumptions are correct. Usually, however, the assumptions do not account for secondary effects and, as a result, the circuit does not operate in an optimal manner.
Therefore, there remains a need to detect and correct characteristics (such as slew rate and swing) of a transmitted signal.

Method and apparatus for detecting and adjusting characteristics of a signal


A roll stand is designed to unwind a material web (60) to a printing machine (2) or other production machine from an unwinding roll (13) in the roll stand and for a stoppage-free automatic shifting to a new roll (5), when the unwinding roll has been emptied to the desired degree. In accordance with the invention, tension is detected in the material web, which while braked in the roll stand is fed into the production machine. Based on that detection, the power supplied to or from a power receiving or power supplying system is regulated in such a way that the tension in the material web, which is fed in to the production machine, is kept constant.

Generally automatic roll-shifting roll stands are used for high speed rotational printing machines. These automatically operating roll stands are designed in such a way, that when the unwinding roll almost is finished, the new roll automatically or through manually actuated signals will start rotating, driven either by central means or by means of driving belts, which are pressed against the periphery of the roll. Well-tried and functioning systems are used to carry out the joining, the so called flying pasting.
For the required synchronization between the speed of the unwinding web and the circumferential speed of the new roll conventional electronic comparative systems are used comprising pulse transducers, current converters and similar components. These systems are comparatively complicated and are not capable of ensuring a complete synchronization. Also, often various control systems are used for the braking and the acceleration, which during various phases are required in connection with the shifting process, which provides an additional complicating factor.
Also, sometimes it is necessary to load the roll stand laterally and not, as is the conventional way to do it, between the printing units and then forward towards that roll stand which belongs to the printing machine. The reason for this is a desire to build the entire plant more compact, which however makes it more difficult to simultaneously also obtain an uncomplicated yet very efficient roll shifting.


The invention is to provide a paper feeding apparatus and a driving method thereof for an office machine. The office machine includes a paper accommodating device and a paper processing apparatus. The paper accommodating device is for accommodating paper sheets to be processed by the paper processing apparatus. The paper feeding apparatus is for feeding the paper sheets accommodated by the paper accommodating device one by one to the paper processing apparatus. The paper feeding apparatus includes a pickup roller, a delivery roller, a pair of feeding rollers, a detection device, a transmission gear assembly, a drive motor and a controller. The detection device detects a leading edge and a trailing edge of the paper sheet delivered by the paper feeding apparatus. In particular, the paper feeding apparatus is a simple-configuration, light-weight and compact component and capable of feeding paper sheets accurately. During feeding operation of the paper feeding apparatus, the rollers of the paper feeding apparatus are driven rotating in respective direction or stopped rotating so as to feed the paper sheets accurately.

The present invention relates to a paper feeding apparatus and a driving method thereof for an office machine, such as a printer, a copy machine, a scanner, a fax, a multi-function office machine or an all-in-one office machine.
An office machine inevitably requires a paper feeding apparatus for feeding paper sheets to be processed by the office machine. The related prior arts refer to the following: U.S. Pat. Nos. 5,392,092; 5,296,908; 4,798,374; 4,975,749; 4,984,779; 5,016,061; 4,846,456; 5,054,768; 4,905,054; 4,979,727; and 5,228,669.
A typical paper feeding apparatus of an office machine must meet the needs of feeding the paper sheets accurately. The paper feeding apparatus should feed the paper sheets in order, such that a misfeed or a double feed of the paper sheets does not take place. Moreover, the leading edge of the delivered paper sheet should be well aligned so that distortion of the sheet does not occur during the process performed by the office machine.
The current design for office machines gravitate towards the desk-top type, multi-function and even all-in-one design in order to increase usefulness and portability. The so-called multi-function or all-in-one office machine combines the functions of various office equipments into one. Obviously, the current office machine still requires simple-configuration, light-weight and compact components to reduce weight of the machine and space occupied by the machine. Accordingly, an objective of the invention is to provide a simple-configuration, light-weight and compact paper feeding apparatus for an office machine. Moreover, the paper feeding apparatus feeds paper sheets into the office machine accurately.
In addition, another objective of the invention is to provide a method for driving such simple-configuration, light-weight and compact paper feeding apparatus. Moreover, the method can drive the paper feeding apparatus feeding paper sheets into the office machine accurately.
The objective of the invention is to provide a paper feeding apparatus for an office machine. The office machine includes a paper accommodating device and a paper processing apparatus. The paper accommodating device accommodates paper sheets to be processed by the paper processing apparatus. The paper feeding apparatus feeds the paper sheets accommodated by the paper accommodating device one by one to the paper processing apparatus. In particular, the paper feeding apparatus is simple-configuration, light-weight and compact, and feeds paper sheets into the office machine accurately.
According to a preferred embodiment of the invention, the paper feeding apparatus includes a pickup roller, a delivery roller, a pair of feeding rollers, a detection device and a driving device. The detection device detects a leading edge and a trailing edge of the paper sheet delivered by the paper feeding apparatus. The pickup roller selectively picks up an uppermost sheet of the paper sheets accommodated by the paper accommodating device. The delivery roller delivers the paper sheet picked up by the pickup roller. The feeding rollers selectively blocks delivery of the paper sheet, or selectively delivering the paper sheet delivered from the delivery roller to the paper processing apparatus. The detection device detects a leading edge and a trailing edge of the paper sheet being delivered by the paper feeding apparatus. The driving device, in response to the result detected by the detection device, selectively drives the rotation of the pick roller, delivery roller and feeding rollers.
Another objective of the invention is to provide a driving method for driving such paper feeding apparatus so as to feeding paper sheets by the paper feeding apparatus into the office machine accurately.
According to the driving method, while the feeding apparatus starts picking up and feeding the paper sheets, the driving device drives the pickup roller rotating in a first direction to pick up the uppermost sheet of the paper sheets accommodated by the paper accommodating device, drives the delivery roller rotating in the first direction to deliver the paper sheet delivered from the pickup roller, and drives an active roller of the feeding rollers rotating in a second direction, opposite to the first direction, to block the paper sheet delivered from the delivery roller. While the leading edge of the paper sheet delivered through the paper feeding apparatus is located between the delivery roller and the feeding rollers, after a delay of short period of time, the driving device stops driving the pickup roller, drives the delivery roller rotating in the first direction still, and drives the active roller rotating in the first direction to deliver the paper sheet delivered from the delivery roller to the paper processing apparatus.
The advantage and spirit of the invention may be understood by the following recitations together with the appended drawings.

Paper feeding apparatus and driving method thereof for office machine