The present invention relates to novel N-substituted azetidine derivatives < of the formula (I); wherein SERMF is a Selective Estrogen Receptor Modilator fragment; X is no atom, O, S, CH2, carbonyl, N—R5; R1 is H, (C1-8)alkyl, (C3-8)cycloalkyl, (C3-6)heterocycloalkyl, (C2-6)alkenyl, (C2-6)alkynyl, (C1-4)alkylcarbonyl, (C1-4)alkoxy(C2-4)alkyl, (C3-6)cycloalkyl(C1-3)-alkyl, (C3-6)heterocycloalkyl(C1-3)alkyl, each independently optionally substituted with one or more halogen, nitrile, hydroxyl or (C1-2)alkyl; R5 is H, (C1-3)alkyl, optionally substituted with one or more fluorine; R17, R18 and R19 are independently of each other H, fluorine, nitrile or (C1-3)-alkyl, optionally substituted with one or more fluorine; or a prodrug, isotopically-labelled derivative or pharmaceutically acceptable salt thereof, > to pharmaceutical compositions comprising these compounds and to their use in therapy, in particular to their use for the prevention or treatment of ovulatory dysfunction, uterine cancer, endometrium cancer, ovarian cancer, endometriosis, osteoporosis, prostate cancer, benign prostatic hypertrophy, and breast cancer, in particular ER-positive breast cancer, more in particular ER-positive, hormone treatment-resistant breast cancer. Said N-substituted azetidine derivatives have estrogen receptor alpha (ERa) antagonistic and—in certain embodiments—selective estrogen receptor downregulating (SERD) activity in ER-positive breast cancer cells.

The estrogen receptor (ER) is a ligand-activated transcription factor that belongs to the nuclear hormone receptor superfamily. Estrogens play an important role in the regulation of a number of physiological processes, both in females and males. In humans, two different ER subtypes are known: ERα and ERβ, each with a distinct tissue distribution and with different biological roles. ERα has high presence in endometrium, breast cancer cells, ovarian stroma cells, and in the hypothalamus. The expression of the ERβ protein has been documented in kidney, brain, bone, heart, lungs, intestinal mucosa, prostate, bladder, ovary, testis, and endothelial cells. For a review see: J. W. Ullrich and C. P. Miller, Expert Opin. Ther. Patents, 16 (2006) 559-572.
Well-known examples of SERMs are tamoxifen and raloxifene. Tamoxifen, for example, behaves like an estrogen in bone and endometrium, whereas it behaves like an anti-estrogen in breast tissue. SERMs are furthermore characterized by two common structural features: a phenolic hydroxyl group (or a bioisostere thereof) and a side chain containing a basic amine. At the time of administration in vivo, the hydroxyl group of a SERM may not yet be present; it may be formed in vivo by de-masking of a prodrug (for example by demethylation of a phenolic methoxy group or by hydrolysis of a phenolic ester group) or by metabolic introduction (for example the metabolic conversion of tamoxifen into 4-hydroxy-tamoxifen, an active metabolite of tamoxifen). Examples of side chains containing a basic amine are 2-(dimethylamino)ethoxy (like in tamoxifen), 2-(1-piperidinyl)ethoxy (like in raloxifene), and 2-(1-pyrrolidinyl)ethoxy (like in lasofoxifene). Upon binding of a SERM to the estrogen receptor, the basic amine in the side chain forms an interaction with amino acid residue Asp351 (in ERα) or Asp303 (in ERβ) resulting in a conformational change of the receptor. For reviews on SERMs see: C. P. Miller, Current Pharmaceutical Design 8 (2002) 2089-2111; V. C Jordan, J. Med. Chem. 46 (2003) 883-908, and J. H. Pickar et al.; Maturitas 67 (2010) 129-138.
Breast cancer is the predominant neoplastic disease in women. ERα is a major driver of breast cancer progression. Multiple existing treatment approaches aim to reduce estrogen levels or block its binding to ERα thereby minimizing tumor progression or even inducing tumor regression in ER-positive breast cancer. Tamoxifen is a first generation SERM used for first-line treatment of ER-positive breast cancer (see V. C. Jordan, Nature Reviews Drug Discovery, 2 (2003) 205-213). Efficacy in breast cancer treatment is seriously compromised by intrinsic or newly developed resistance to anti-hormonal therapy such as treatment with tamoxifen or aromatase inhibitors. Such resistance can exist or develop as a result of ER phoshorylation or regulation of key components in hormone receptor and/or growth factor signal transduction pathways (see V. C. Jordan and B. W. O'Malley, J. Clin. Oncol. 25 (2007) 5815-5824; V. C. Jordan, J. Nat. Cancer Inst., 98 (2006) 657-659; S. J. Cleator et al., Clinical Breast Cancer 9 (2009) S6-S17).
Tamoxifen resistance is driven by the residual agonist activity of tamoxifen and its 4-OH metabolites. Second generation SERMs such as toremifene, droloxifene, idoxifene, arzoxifene, and raloxifene have failed to improve upon the efficacy of tamoxifen in the treatment of ER-positive breast cancer and/or demonstrated cross-resistance with each other (V. Deshmane et al., J. Clin. Oncol. 25 (2007) 4967-4973); J. H. Pickar et al., Maturitas 67 (2010) 129-138).
Fulvestrant, a steroidal C7-substituted 17β-estradiol derivative and a pure ER antagonist without the partial agonist activity which is so typical for the SERMs, is the only marketed SERD (Selective Estrogen Receptor Downregulator) efficacious in second-line treatment of breast cancer. Besides antagonizing ERs, fulvestrant also effectively downregulates ERα protein levels in cells. This SERD activity inhibits ERα-driven proliferation and tumor growth (in contrast to tamoxifen which upregulates ERα). Fulvestrant, when administered i.m. once a month at 250 mg is equally effective to tamoxifen in treatment of ER-positive advanced breast cancer (A. Howell et al., J. Clin. Oncol. 22 (2004) 1605-1613). In second-line treatment of ER-positive tamoxifen-resistant breast cancer, fulvestrant, when administered i.m. once a month at 250 mg, is equally effective to aromatase inhibitors, despite relatively poor bioavailability and/or target exposure which limits its clinical efficacy (Robertson et al., San Antonio Breast Cancer Symposium, 2009; Linden et al., San Antonio breast Cancer Symposium, 2007).
Other known SERDs are ICI 164,384, i.e. a structural analogue of fulvestrant, GW5638, i.e. a structural analogue of tamoxifen, and GW7604, i.e. a structural analogue of 4-hydroxy-tamoxifen. For a review on SERDs see: M. Fan et al., Breast Cancer Res. Treat. 103 (2007) 37-44.
Merck has reported a series of 2,3-dihydrobenzo[b][1,4]-oxathiine derivatives, in which a modified (i.e. a bis-methylated pyrrolidinylethoxy) basic amine side chain all at once behaved as a SERD instead of as a SERM. However, when said modified basic amine side chain was placed on other SERM-derived chemical scaffolds, such as the benzothiophene of raloxifene, the tetrahydronaphthalene of lasofoxifene and the indole of bazedoxifene, these modified compounds did not behave as SERDs. See page 561 of J. W. Ullrich and C. P. Miller, Expert Opin. Ther. Patents, 16 (2006) 559-572, and references 18 and 101-103 cited therein.
Hence, there is a need for new, potent ERα antagonists, which would preferably have ER downregulating activity (in breast cancer cells), do not stimulate proliferation in ER-positive, hormone treatment-resistant breast cancer cells, be orally administrable, and be useful in the treatment of inter alia ER-positive, hormone treatment-resistant breast cancer.
Apart from the treatment of breast cancer, SERMs have also been used in the treatment of a number of other disorders and/or diseases. The treatment of ovulatory dysfunction by tamoxifen and clomiphene citrate, which induce ovulation, is described by A. Steiner et al. in Human Reproduction 20 (2005) 1511-1515; and by J. H. Pickar et al. in Maturitas 67 (2010) 129-138. J. H. Pickar et al. in Maturitas 67 (2010) 129-138 also describe the treatment of uterine cancer, endometrium cancer, osteoporosis, prostate cancer, and benign prostatic hypertrophy using SERMs. S. J. Ellem and G. P. Risbridger in Nature Reviews Cancer 7 (2007) 621-627 also describe the treatment of prostate cancer and benign prostatic hyperplasia (or hypertrophy). The treatment of ovarian cancer is described by G. M. Clinton and W. Hua in Crit. Rev. Oncol. Hematol. 25 (1997) 1-9. S. E. Bulun in N. Engl. J. Med. 360 (2009) 268-279 reviews the role of estrogen and estrogen receptor signaling in endometriosis.


The operational bandwidth of a servo control circuit can be increased using a plurality of servo processors that handoff between them the responsibility for controlling head positioning in response to sequentially occurring servo patterns.

The present invention generally relates to controlling head movement and, more particularly, to controlling head movement relative to a sequence of servo patterns on a media.
A typical data storage disk drive includes a plurality of magnetic recording disks which are mounted to a rotatable hub of a spindle motor and rotated at a high speed. An array of read/write heads is disposed adjacent to surfaces of the disks to transfer data between the disks and a host device. The heads can be radially positioned over the disks by a rotary actuator and a closed loop servo system.
The servo system can operate in two primary modes: seeking and track following. During a seek, a selected head is moved from an initial track to a target track on the corresponding disk surface. Upon reaching the target track, the servo system enters the track following mode wherein the head is maintained over the center of the target track while data is written/read. During track following, prerecorded servo data sensed by the head is demodulated to generate a position error signal (PES), which provides an indication of the position error of the head away from the track center. The PES is then converted into an actuator control signal, which is fed back to an actuator to position the head.
Typically, a microprocessor executes both the servo code that controls servo functionality and data control code that controls the communication interface between the disk drive and a host, cache management, defect table management, and other disk drive management functions. The servo code must operate at a higher priority than the data control code to ensure that the servo control loop efficiently and accurately carries out head positioning during seek and track following operations. It is becoming increasingly more difficult to ensure that in such a configuration that the servo code can be executed at a sufficiently high operational bandwidth as the computational complexity of the servo code increases and as additional functionality is added to the data control code.

Servo processors that alternately control head positioning relative to sequential servo patterns


Bermudagrass ‘ST-5’ is provided. The new and distinct dwarf variety has excellent shade tolerance, superior tawny mole cricket non-preference, small seed heads, and thrives in hot and humid conditions. The asexually reproduced triploid variety is reliably propagated vegetatively.

The present invention relates to a new and distinct cultivar of bermudagrass botanically known as Cynodon transvaalensis×Cynodon dactylon, and herein referred to as 'ST-5.'
The new bermudagrass is a product of a planned breeding program conducted by the Inventors in Tifton, Ga. The objective of the bermudagrass breeding program is to create new plant cultivars with improved commercial qualities. This cultivar is commercially important for its superior shade tolerance and other qualities, which are enumerated herein.
Pedigree and history: Several C. transvaalensis parents (unpatented) were crossed with several C. dactylon parents (unpatented) in Tifton, Ga. Crosses were made in the field by surrounding each C. transvaalensis parent with a C. dactylon parent in 6-feet square plots. All crosses were in close proximity, and resulted in somewhat random parentage of all resulting progeny. Progenies were planted from the cross combinations. Once established, the plots were mowed three times per week at one-fourth inch height setting on the mower. Plants that maintained density, color, and tawny mole cricket non-preference were selected in the fall of the second year after planting. One selection, 'ST-5' (ST for shade tolerant), was identified as a nice dwarf and tested for nine years in three field (full sun) and three shade tests in Tifton, Ga. Bermudagrass 'ST-5' was also tested for insect resistance in Tifton, Ga.
Asexual reproduction of the new bermudagrass by vegetative terminal cuttings in a controlled environment in Tifton, Ga., since 1993, has shown that the unique features of this new bermudagrass are stable and reproduced true to type in successive generations.

University of Georgia Research Foundation


The invention utilizes colloidal silica soot (62) in a semiconductor process for chemical-mechanical planarizing a semiconductor integrated circuit workpiece (24) with a slurry (60). The particulate abrasive agent colloidal solid sphere fused silica soot (62) provides a beneficial CMP slurry/process for semiconductor device manufacturing compared to standard semiconductor CMP slurries with conventional colloidal sol-gel or fumed silica.

Semiconductor integrated circuit chemical-mechanical planarizing slurries are utilized by the semiconductor industry in the manufacture of integrated circuit devices. Various semiconductor integrated circuit layers are stacked on top of a semiconductor substrate. The stacked layers are deposited and formed on the semiconductor substrate so that electrical connections can be made to the devices incorporated in the semiconductor substrate wafer and the devices can perform their intended functions (such as computations and computer processing). Chemical-mechanical planarization utilized in the stacking of such layers and formation of such electrical connections to remove deposited materials and provide flat planar surfaces.
Application of colloidal suspensions for polishing planarizing advanced materials has become an exceedingly critical aspect of final part formation for the semiconductor integrated circuit microelectronics industries. Silica and alumina colloids are formed through various techniques and typically require expensive precursor materials in order to ensure the highest purity products. Solutions are stabilized with buffer systems to pH and solids loading values that result in optimal semiconductor workpiece surface finish attainment. Particle size distribution can be adjusted to control the final surface finish as well as the ability to clean residue abrasive particles from workpiece surfaces after processing. The present invention describes the application of colloidal silica soot produced as a byproduct of chemical vapor deposition processing of glasses in the semiconductor integrated circuit finishing industry, specifically for application to silicon wafers, oxide coating on such wafers, conductive metals used in microelectronic devices (e.g., aluminum, copper, tantalum, tungsten, etc.), and ceramics used in microelectronics (e.g., silicon nitride and silicon carbide).
The abrasive particles of a CMP slurry effect the slurry chemistry and its use. The slurry solution must be adjusted to a pH that will allow for attainment of the best surface finish and the solution must be stabilized from agglomeration and pH shifts during storage. For conventional colloidal silica abrasives designed for microelectronic applications, buffers solutions using mixtures of various bases and salts are incorporated for stabilization anywhere between pH 5-12. Most common for colloidal silica solutions stabilized for single-crystal silicon polishing is a buffer adjustment to pH 10-11. For the Soot of the invention, a likewise adjustment can be made using a potassium-based buffer solution.
With regards to polishing of interconnecting metals in microelectronic integrated circuit devices (e.g., aluminum, copper, tantalum, tungsten, etc.) the soot materials offer advantages including (1) relatively large particle size (>0.25 μm) with spherical morphology and (2) added stabilization of TiO2—SiO2 over SiO2. The inventive soot materials demonstrate four preferred points in specific application to the chemomechanical polishing (planarization) of microelectronic materials such as copper, aluminum, tungsten, and silicon as well as related carbides and nitrides:
First, the Ti doped soot shows significantly improved stability at low pH (<pH 5) as compared to the pure silica soot. This provides the doped soot with better dispersion properties and beneficial performance when being applied as a polishing compound at pH <5.
Second, the pure undoped fused silica soot is shown to be of greater resistance to dissolution at high pH (pH >5), suggesting that the soot would perform in a superior manner that the Ti doped soot for microelectronic applications in this pH range.
Third, the decreased surface area of the inventive soots (10-20 m2/gram) as compared to competing silica particle materials (100-400 m2/gram) such as fumed silica suggests that these soot particles can be dispersed in solution using less dispersion aids, thus eliminating sources of contamination or unwanted levels of dispersion aids used.
Fourth, the spherical nature and particle sizes of the inventive soot materials suggest that the mechanical performance of the soot materials used as abrasive particles would not scratch the surface being polished.

This patent is subject to a terminal disclaimer.

Semiconductor processing silica soot abrasive slurry method for integrated circuit microelectronics


A plasma etching method and apparatus, a control program and a computer-readable storage medium storing the control program are provided. The method is provided for performing a plasma etching on a silicon oxide film through an amorphous carbon mask, wherein the plasma etching is performed by using an etching gas containing a fluorocarbon gas, an oxygen gas, a helium gas and at least one of an argon gas, a krypton gas and a xenon gas.

Conventionally, in a manufacturing process for a semiconductor device, a hole such as a contact hole is formed in a silicon oxide film by plasma etching. When, for example, a resist is used as a mask for the plasma etching of the silicon oxide film, it is well known that a gaseous mixture of C4F6/O2/Ar is employed as an etching gas to improve the selectivity of the silicon oxide film against the resist (For example, see Japanese Patent Laid-open Application No. 2002-100607).
Furthermore, also known for the plasma etching of the silicon oxide film is a method for improving the in-surface uniformity of the plasma etching by changing a mixing ratio of Ar and He, which are used as dilution gases (see, for example, Japanese Patent Laid-open Application No. 2002-252213).
However, as semiconductor devices are getting miniaturized, the diameters of contact holes and the like are also required to be reduced to, for example, not greater than 70 nm. To meet such requirements, it is necessary to replace a conventionally employed KrF resist with an ArF resist. Since, however, plasma resistance of the ArF resist is weak, there has been made an attempt to plasma etch the silicon oxide film by using a hard mask made of, e.g., amorphous carbon. In this case, amorphous carbon is first plasma etched into a predetermined pattern by using the ArF resist as a mask, and plasma etching of the silicon oxide film is then conducted by using the amorphous carbon of the predetermined pattern as a mask.
When plasma etching the silicon oxide film by using the amorphous carbon as a mask, however, a sufficient selectivity of the silicon oxide film against the amorphous carbon (a ratio of an etching rate of the silicon oxide film to an etching rate of the amorphous carbon) cannot be obtained.
As described above, conventionally, when plasma etching the silicon oxide film by using the hard mask made of the amorphous carbon to form a fine pattern, there has been a problem that it is difficult to obtain a sufficient selectivity of silicon oxide film against the amorphous carbon (the ratio of the etching rate of the silicon oxide film to the etching rate of the amorphous carbon).

Plasma etching method and apparatus, control program and computer-readable storage medium storing the control program


An applicator is configured to apply a substance on a portion of the human body and comprises an applicator element. The applicator element comprises at least two walls forming therebetween a cavity suitable for retaining the substance, at least one slot that extends along a longitudinal axis and through which the substance contained in the cavity is dispensed in order to be applied, and at least one opening whereby the cavity opens to the outside. In embodiments, the opening comprises at least one portion with a width in a plane extending transversely to the slot that is greater than a width of the slot in the same plane.

French patent document No. 2,730,704 describes an applicator provided with at least one slot at the end of a stem. Such an applicator cannot retain much substance. French patent document No. 2,730,704 describes an applicator that can hold more substance. This applicator presents an annular cylindrical space that communicates with a slot at the end of a stem. Such an applicator is unsuitable for certain uses in which it is desirable for the slot to be disposed otherwise, whether for ergonomic reasons or due to the nature of the region to be treated.

Applicator including an applicator element for applying a substance, in particular a cosmetic or another care product


A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes depositing a first portion of a film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas and the oxidizing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas) and regulating the chamber to a pressure in a range from about 200 torr to about 760 torr throughout deposition of the conformal layer. The method also includes depositing a second portion of the film as a bulk layer. Depositing a second portion of the film includes maintaining the ratio of the (silicon-containing processing gas):(oxidizing gas) substantially constant throughout deposition of the bulk layer and regulating the chamber to a pressure in a range from about 200 torr to about 760 torr throughout deposition of the bulk layer. The method also includes exposing the substrate to nitrous oxide at a temperature less than about 900° C. to anneal the deposited film.

The fabrication sequence of integrated circuits often includes several patterning processes. The patterning processes may define a layer of conductors, such as a patterned metal or polysilicon layer, or may define isolation structures, such as trenches. In many cases the trenches are filled with an insulating, or dielectric, material. This insulating material can serve several functions. For example, in some applications the material serves to both electrically isolate one region of the IC from another, and electrically passivate the surface of the trench. The material also typically provides a base for the next layer of the semiconductor to be built upon.
After patterning a substrate, the patterned material is not flat. The topology of the pattern can interfere with or degrade subsequent wafer processing. It is often desirable to create a flat surface over the patterned material. Several methods have been developed to create such a flat, or "planarized", surface. Examples include depositing a conformal layer of material of sufficient thickness and polishing the wafer to obtain a flat surface, depositing a conformal layer of material of sufficient thickness and etching the layer back to form a planarized surface, and forming a layer of relatively low-melting point material, such as doped silicon oxide, and then heating the wafer sufficiently to cause the doped silicon oxide to melt and flow as a liquid, resulting in a flat surface upon cooling. Each process has attributes that make that process desirable for a specific application.
As semiconductor design has advanced, the feature size of the semiconductor devices has dramatically decreased. Many circuits now have features, such as traces or trenches, less than a micron across. While the reduction in feature size has allowed higher device density, more chips per wafer, more complex circuits, lower operating power consumption and lower cost among other benefits, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries.
An example of the type of manufacturing challenge presented by sub-micron devices is the ability to completely fill a narrow trench in a void-free manner. To fill a trench with silicon oxide, a layer of silicon oxide is first deposited on the patterned substrate. The silicon oxide layer typically covers the field, as well as walls and bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench. As the trench gets narrower and the aspect ratio (the ratio of the trench height to the trench width) increases, it becomes more likely that the opening of the trench will "pinch off".
Pinching off a trench may trap a void within the trench. Under certain conditions, the void will be filled during a reflow process, for example where the deposited silicon oxide is doped and experiences viscous flow at elevated temperatures. However, as the trench becomes narrower, it becomes more likely that the void will not be filled during the reflow process. Moreover, several types of applications call for the deposition of undoped silicon oxide (sometimes referred to a undoped silicate glass, "USG"), which is difficult to reflow even at elevated temperature. Voids resulting from pinching-off are undesirable as they can reduce the yield of good chips per wafer and the reliability of the devices.
One possible solution to this problem is a two-step process wherein a first deposition step is performed under process conditions with a low (silicon-containing gas):(oxidizing gas) ratio and low deposition rate for achieving the desired gap-fill. After this first step is performed, the flow of silicon-containing process gas to the chamber is interrupted, and then a second distinct deposition step is performed under different conditions with a high (silicon-containing gas):(oxidizing gas) ratio and a high deposition rate for bulk fill. However, such a two-step process may exhibit reduced throughput due to the extended time required in the first step, and also the time consumed in halting the process gas flow and changing the apparatus configuration between the first and second steps.
Therefore, it is desirable to be able to fill narrow gaps with dielectric material in a void-free manner. It is also desirable that the process used to deposit the dielectric material be efficient, reliable, and result in high yield of devices.

Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill


A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.

1. Field of the Invention
The present invention relates to a semiconductor device having a structure in which part of a semiconductor substrate is isolated via an insulating layer. Moreover, the present invention relates to a method of manufacturing the semiconductor device.
2. Description of the Related Art
The performance of semiconductor elements used in Si-LSIs, in particular, MOSFETs has been enhanced year by year with advances in LSI technology. However, a limit to the lithography technique is indicated in light of recent process techniques, while saturation of mobility is indicated in light of element physics. For this reason, it is very difficult to achieve high performance of the semiconductor elements.
The following technique has attracted special interest as a method of improving electron mobility, which is one of the high-performance indices of an Si-MOSFET. According to the technique, strain is applied to an active layer for forming elements. The strain is applied to the active layer, and thereby, the band structure changes and carriers contained in a channel are prevented from scattering. Thus, it is expected to enhance the mobility. More specifically, a compound crystal layer consisting of a material having a lattice constant larger than silicon (Si) is formed on an Si substrate. For example, a strain-relaxed SiGe compound crystal layer (hereinafter, referred simply to as SiGe layer) having 20% Ge concentration is formed on the Si substrate. When an Si layer is formed on the SiGe layer, a strained Si layer to which strain is applied is formed according to the difference in the lattice constant. The following report has been made (e.g., see J. Welser, J. L. Hoyt, S. Takagi and J. F. Gibbons, IEDM 94-373). According to the report, when the strained Si layer is used as a channel of the semiconductor device, it is possible to obtain electron mobility of about 1.76 times as much as the case where a non strained Si channel is used.
In order to form the foregoing strained Si channel on an silicon-on-insulator (SOI) structure, the present inventors realized a device structure using the following method. According to the method, the strained Si layer is formed on the strain-relaxed SiGe layer on a buried oxide layer (e.g., see T. Mizuno et al., 11-3, 2002 Symposia on VLSI Tech.). A transistor having such a structure is excellent in short channel effect (SCE) and reduction of parasitic capacitance; therefore, it serves to realize high-performance elements.
However, if the scale-down further advances, for example, a 35 nm node element will be produced in future. In this case, the thickness of the strained Si channel is experimentally ⅓ to ¼ of the gate length, that is, several nanometers, and thus, becomes extremely thin. For this reason, there is a possibility that the crystal layer deteriorates. For example, if the strained Si layer is given as one example, the lattice spacing between a front-end layer and a back-end strain-applied layer is percent (%) order to apply strain. As a result, crystal defect resulting from strain occurs in crystal.
If the strained Si channel contacts with a semiconductor material different from Si, for example, front-end SiGe layer, there is a possibility that Ge diffuses from the SiGe layer to the strained Si layer. This is a factor of causing a strain change, carrier transportation change or increase of interface state in the element producing process and in the device operation. For this reason, there is a possibility that element characteristics are degraded.
Meanwhile, one-chip technique development, typical of DRAM embedded process, is important as a technique required for manufacturing logic operation elements applied to a next generation computer system. The foregoing embedded process has attracted special interest for the following reason. Because, the embedded process is a technique of forming a logic circuit and a memory elements such as DRAM on the same substrate, and reducing power consumption and cost while maintaining high speed operation. In this case, high performance elements having high processing speed are required as the logic circuit. On the other hand, high-quality semiconductor devices must be manufactured in view of yield to form the memory elements.
In the technique of integrating high-performance logic element and high-quality memory element on the same substrate, it is necessary to break down a limit of high-performance logic element resulting from a limit of scale-down. In addition, there is a limit in the method of integrating high-quality memory elements on the single substrate like the conventional technique. Moreover, the following various problems are mixed; as a result, there is a problem that it is more and more difficult to achieve integration between generations. The various problems are as follows.
Reduction of element performance enhancement effect resulting from the advance of scale-down
Cost Increase
Increase of the number of manufacturing processes
Difficulty of circuit design by drive force reduction resulting from high integration
Consequently, it is necessary to realize the technique of integrating logic elements requiring higher performance and memory elements requiring higher quality and higher integration on the same substrate. It has been desired to realize a semiconductor device which is adaptable to reduction of cost and number of processes, and to realize a method of manufacturing the semiconductor device.

Semiconductor device and method of manufacturing the same


An apparatus for use in a processing chamber is provided. A consumable is within the processing chamber. A scale is positioned to measure a mass of the consumable.

This disclosure relates to the manufacturing of semiconductor devices. More specifically, the disclosure relates to the manufacturing of semiconductor devices in a processing chamber with consumable parts.
In the manufacture of semiconductor devices, the semiconductor may be processed in a processing chamber. Some processing chambers have consumable parts. For example an etch chamber may have a consumable edge ring, which is etched over time. Other processing chambers may have consumables over which layers are deposited over time.


Object-oriented software-based systems may be optimized by providing a data representation which is initially permitted to be completely dynamic such that at compile time representation need not be specified and thereafter the data structure and representation is progressively optimized. The invention is based on the recognition that the important data structures in object-oriented systems are not the objects but rather the slots, i.e., the attributes of objects.

This invention relates to the field generally known as artificial intelligence and more particularly to programming in frame-based systems or more generally to object-oriented systems. Specifically, this invention relates to techniques for software development of an object-oriented system.
In the past, optimization of software-based systems and specifically of object-oriented systems has been dependent on the developer. While no solution for general software-based systems is known, characteristics of object-oriented systems have features which, according to the invention disclosed hereinafter, permit developer-independent optimization.
Many known computer languages support static data representation. Fewer languages support dynamic data representation. In static data representation, the decision on the internal layout of the data structure and representation is made at compile time of the computer program. All static data representation systems require prior specification of individual language, of each individual field and of each data type, such as integer, floating point, aggregate or the like. This greatly reduces flexibility of programming and data handling and extends the development time, although it does provide the best possible performance, since data access characteristics ar all determined at compile time. An example of an object-oriented language with static data representation capability is the C++ language.
In a language capable of dynamic data representation, the decision on internal layout of data structure is deferred until run time of the program, which allows efficient applications development. The dynamic representation capability is an important distinction over static data representation. The proto-typical example of an object-oriented language capable of dynamic data representation is the SmallTalk language of Xerox Corporation. Because of frequent and extensive lookup at program run time, the typical system with a dynamic data structure yields significantly slower run-time performance than a comparable system having a static data structure. Although it allows for easy applications development, SmallTalk does not run many practical applications in a generally acceptable amount of time. As a consequence, programmers may use SmallTalk or other similar languages with dynamic data structures during system development but thereafter recode a production system in another language which supports static data representation.
It is therefore desireable to provide a programming environment which is easy and flexible for development of a software-based system and which does not require extensive reengineering in a different language for production of a software-based system.
The problem area herein addressed is not to be confused with the area of database management, where database management systems employ dynamic look-up capabilities as part of an indexing scheme on a revisable database. The problem addressed herein is how to minimize recoding of source code in a generalized object-oriented programming environment.
What is needed is a programming environment and methodology that allows delay until compile time of any specification about how static the structure is to be, and what is needed is a range of options between the formation of a dynamic data structure and the formation of a fully static data with commensurate improvements over a program with fully dynamic data representation.

Mosaic objects and method for optimizing object representation performance in an object-oriented representation system


A system and method are described for efficiently filtering and restoring tables within an enterprise application server. For example, one embodiment of the invention detects that a filtering function has been selected for a particular table node and responsively stores elements from the table node within a backup table collection. The filtering function is then performed to generate a filtered table node containing a subset of elements specified by the filtering function. Subsequently, upon detecting that the filtering function has been disabled, the table node may be restored from the backup table collection.

1. Field of the Invention
This invention relates generally to the field of data processing systems. More particularly, the invention relates to a system and method for efficiently filtering and restoring tables within a multi-tiered enterprise network.
2. Description of the Related Art
Multi-Tiered Enterprise Computing Systems
Traditional client-server systems employed a two-tiered architecture such as that illustrated in FIG. 1a. Applications 102 executed on the client side 100 of the two-tiered architecture are comprised of a monolithic set of program code including a graphical user interface component, presentation logic, business logic and a network interface that enables the client 100 to communicate over a network 103 with one or more servers 101. A database 104 maintained on the server 101 provides non-volatile or "persistent" storage for the data accessed and/or processed by the application 102.
The "business logic" component of the application represents the core program code of the application, i.e., the rules governing the underlying business process (or other functionality) provided by the application. The "presentation logic" describes the specific manner in which the results of the business logic are formatted for display on the user interface. The "database" 104 includes data access logic used by the business logic to store and retrieve data.
The limitations of the two-tiered architecture illustrated in FIG. 1a become apparent when employed within a large enterprise. For example, installing and maintaining up-to-date client-side applications on a large number of different clients is a difficult task, even with the aid of automated administration tools. Moreover, a tight coupling of business logic, presentation logic and the user interface logic makes the client-side code very brittle. Changing the client-side user interface of such applications is extremely hard without breaking the business logic, and vice versa. This problem is aggravated by the fact that, in a dynamic enterprise environment, the business logic may be changed frequently in response to changing business rules. Accordingly, the two-tiered architecture is an inefficient solution for enterprise systems.
In response to limitations associated with the two-tiered client-server architecture, a multi-tiered architecture has been developed, as illustrated in FIG. 1b. In the multi-tiered system, the presentation logic 121, business logic 122 and database 123 are logically separated from the user interface 120 of the application. These layers are moved off of the client 125 to one or more dedicated servers on the network 103. For example, the presentation logic 121, the business logic 122, and the database 123 may each be maintained on separate servers, 126, 127 and 128, respectively.
This separation of logical components and the user interface provides a more flexible and scalable architecture compared to that provided by the two-tier model. For example, the separation ensures that all clients 125 share a single implementation of business logic 122. If business rules change, changing the current implementation of business logic 122 to a new version may not require updating any client-side program code. In addition, presentation logic 121 may be provided which generates code for a variety of different user interfaces 120, which may be standard browsers such as Internet Explorer® or Netscape Navigator®.
The multi-tiered architecture illustrated in FIG. 1b may be implemented using a variety of different application technologies at each of the layers of the multi-tier architecture, including those based on the Java 2 Enterprise Edition™ ("J2EE") standard, the Microsoft .NET standard and/or the Advanced Business Application Programming ("ABAP") standard developed by SAP AG. For example, as described below, in a J2EE environment, the business layer 122, which handles the core business logic of the application, is comprised of Enterprise Java Bean ("EJB") components with support for EJB containers. Within a J2EE environment, the presentation layer 121 is responsible for generating servlets and Java Server Pages ("JSP") interpretable by different types of browsers at the user interface layer 120.
J2EE Application Server Architecture
FIG. 2a illustrates a typical J2EE application server 200 in which the presentation layer is implemented by a "Web container" 211 and the business layer is implemented by an Enterprise Java Bean ("EJB") container 201. Containers are runtime environments which provide standard common services 219, 209 to runtime components. For example, the Java Naming and Directory Interface ("JNDI") is a service that provides application components with methods for performing standard naming and directory services. Containers also provide unified access to enterprise information systems 217 such as relational databases through the Java Database Connectivity ("JDBC") service, and legacy computer systems through the J2EE Connector Architecture ("JCA") service. In addition, containers provide a declarative mechanism for configuring application components at deployment time through the use of deployment descriptors.
As illustrated in FIG. 2a, each layer of the J2EE architecture includes multiple containers. The Web container 211, for example, is itself comprised of a servlet container 215 for processing servlets and a Java Server Pages ("JSP") container 216 for processing Java server pages. The EJB container 201 includes three different containers for supporting three different types of enterprise Java beans: a session bean container 205 for session beans, a entity bean container 206 for entity beans, and a message driven bean container 207 for message driven beans. A more detailed description of J2EE containers and J2EE services can be found in RAGAE GHALY AND KRISHNA KOTHAPALLI, SAMS TEACH YOURSELF EJB IN 21 DAYS (2003) (see, e.g., pages 353-376).
Table Generation and Filtering
The display of data records in tables and forms and the associated editing of the tables and forms (e.g., selecting, deleting, sorting, etc) by clients are central functions in Web-based applications. Thus, various techniques are provided within the J2EE architecture for creating and working with tables in response to client requests. In particular, under a model-view-controller ("MVC") architecture, illustrated in FIG. 2b, Web-based content using tables may be created within the Web Container 211 using "controllers" 240 and "views" 251-252 that operate in conjunction with "models" 260 within the EJB container 201. A detailed description of the MVC architecture is beyond the scope of the present application but, briefly, the controller 240 manages the underlying table structure and data, referred to in FIG. 2b as a table node 250. The table structure is presented to Web clients 220 in the form of one or more "views" 251-252 which indicate, for example, how the table is presented within a Web page. Controllers may be implemented by servlets and views by Java server pages. The model 260 within the EJB container 201 provides an interface between the controller 240 and the underlying table data stored within the database 123. See, e.g., GHALY and KOTHAPALLI mentioned above for additional detail on the MVC architecture at pages 148-152.
Once the table node 250 is generated, it may be filtered and/or otherwise modified in response to requests from Web clients. For example, as part of a search request a Web client may designate a filtering operation such as "only display client records in the table beginning with the letters DE." As a result the table node will be filtered and the results provided to the client.
One problem which existed in prior configurations, however, was the manner in which the table node was restored following a filtering operation. In particular, following a filtering operation, if a user desired to once again view the unfiltered table (or to perform a new filtering operation), the system would fully restore the table node (e.g., via communication with the EJB container 201 and/or database), thereby consuming a considerable amount of processing capacity and bandwidth. Accordingly, more efficient techniques for table filtering and regeneration are needed.

System and method for efficiently filtering and restoring tables within a multi-tiered enterprise network


There is provided a method for handling mobility synchronization measurements. The method is performed by a wireless device. The method comprises receiving an indication to perform mobility measurements on a set of transmission beams associated with a unique identity. The method comprises checking if the unique identity has previously been stored by the wireless device. The method comprises, if the unique identity has not previously been stored by the wireless device, performing mobility measurements on the set of transmission beams to determine synchronization information of the set of transmission beams. The method comprises storing the unique identity and the synchronization information of the mobility measurements.

In communications networks, there may be a challenge to obtain good performance and capacity for a given communications protocol, its parameters and the physical environment in which the communications network is deployed.
For example, handover is a vital part of any cellular communications network. A handover may be defined as the process of transferring an ongoing connection of a wireless device from one radio access network node (denoted the serving radio access network node) to another radio access network node (denoted the target radio access network node) in order to accomplish a transparent service over a large coverage area. The handover should be performed without any loss of data transmission to/from the wireless device, and with as small interrupt as possible for the wireless device.
To enable a handover, it is necessary to find a suitable target cell as served by the target radio access network node, and to ensure that it is possible to sustain reliable communication to/from the wireless device in the target cell. Candidates for suitable target radio access network nodes (and/or target cells) are usually stored in so-called neighbor lists, which are stored at least at the serving radio access network node.
For a wireless device (WD) to receive or measure on a target cell (i.e., an area served by a target radio access network (RAN) node), it needs be synchronized with the cell (i.e., with the target node). In legacy systems, all RAN nodes continuously transmit synchronization signals that WDs in neighbor cells use for synchronization with target cell. Examples include, but are not limited to, the synchronization channel (SCH) in Wideband Code Division Multiple Access (WCDMA) based communications networks and the primary and secondary synchronization signals in Long Term Evolution (LTE) based communications networks. The synchronization is usually achieved by correlating the received signal with a known signal; in LTE the correlation may be performed in both time and frequency domain. The synchronization procedure is often dived into several steps where the frequency and time resolution and is improved for each step. For time synchronization, the steps may include finding symbol, slot and frame timing.
Future cellular communications networks may use advanced antenna systems to a large extent. With such antennas, signals will be transmitted in narrow transmission beams to increase signal strength in some directions, and/or to reduce interference in other directions. When the antenna is used to increase coverage, handover between narrow transmission beams in neighboring RAN nodes may become a necessity. The serving RAN node also needs to decide if a beam switch or beam update is necessary within the own cell. The transmission beam through which the RAN node is currently communicating with the WD is called the serving beam and the transmission beam it will hand over to, or switch to, is called the target beam. The serving beam and the target beam may be transmission beams of the same or different RAN node.
In a cellular system with an advanced antenna system that uses narrow beams, beam updates for a WD might recur quite often. To synchronize and measure on the different candidate beams, the WD) must thus potentially perform extensive timing synchronization procedures, especially in non-synchronized networks. For the WD, the synchronization procedure may be quite complex, since it may need to measure on many transmission beams at once.
Hence, there is still a need for improved handling of mobility synchronization measurements.


A floor scrubbing machine for tile and other hard surface floors has a low enough profile height that it can be operated bodily under furniture or equipment such as, for example, seats in fast food stores. This floor scrubber has three principle functioning components, comprising a tank for cleaning solution and means to apply that solution to the floor, a powered scrub brush to agitate the solution on the floor, and a vacuum pickup squeegee system which dries the floor after scrubbing by removing spent solution from the floor to an on board tank. Floor scrubbers are known which comprise the three above elements, but are too tall to operate under the seats of fast food stores, except with a remote wand attachment which is cumbersome and slow. Other floor scrubbers are known which are low enough to operate bodily in such places but lack a vacuum pickup squeegee system for drying the floor, and leave a hard surface floor unacceptably wet, or require following operations to dry it. The present invention overcomes the shortcomings of these prior art floor scrubbers.

The rise of fast food chains has been a phenomenon of our times. All over the country one finds these stores that sell hamburgers, french fries, chicken, soft drinks and such for taking out or eating on the premises. As with any food service business, zealous attention to cleanliness is essential in these establishments, and ease of cleaning is given careful thought in the design of the stores. This architectural foresight often shows in the floors, which are usually surfaced with ceramic tile, and in the seats and tables provided in the dining areas, which are commonly built with cantilevered supports so that most of the floor area under them is unobstructed. These features, of course, are intended to make it easier to clean the floor, which gets all kinds of food dropped on it, as well as mud, snow etc. tracked in from outdoors.
However, these under seat areas do not have a very high floor clearance. A survey of a group of fast food stores found that almost two-thirds of them had seats with a largely unobstructed area under them which had a vertical clearance from the floor to the undersides of the seats that was between eleven and fifteen inches. It is not easy to clean the floor under these seats because scrubbing machines built low enough to get under them and do a good fast job of cleaning and drying the floor are not available. Various types of floor cleaning machines are used, but none of them is completely satisfactory.
So-called automatic scrubbers are available which are comprised of a tank for cleaning solution and means to apply that solution to the floor, one or more powered rotating scrub brushes to agitate it on the floor and a vacuum pickup squeegee system to dry the floor after scrubbing by removing the solution from the floor to an on board tank. These do good fast cleaning, and their vacuum pickup squeegees leave a hard surfaced floor barely damp. It will be dry enough to walk on safely and will be completely dry in a few minutes. However, they are intended for cleaning aisles and open areas, and they are too tall to get under equipment and furniture that have only eleven to fifteen inches of floor clearance. This is because these scrubbers have relatively large tanks, they require a substantial plenum space above the water level in their recovery tanks to assist in controlling foam, and commonly their vacuum fans are placed above their recovery tanks. The best that can be done when scrubbing the floor of a fast food store with these machines is to park them in the aisle and use a wand attachment with a long vacuum hose to clean under the seats. The wand is cumbersome and slow to use. Typical examples of this type of floor scrubber are the Drynamic.about. 170 floor cleaning system made by Tennant Trend of Niagara Falls, N.Y., and the Convertamatic.about. high-speed floor maintenance machines made by Advance Floor Machine Company of Spring Park, Minn.
Other floor cleaning machines are available which have small bodies with a low enough profile height to be pushed bodily under equipment and furniture having a floor clearance of even less than eleven inches. They all have one or two powered rotating scrub brushes and do a good job of cleaning the floor. However, there isn't enough room in one of their small bodies for a system to dry the floor after scrubbing, which necessitates following after them with a wet vac or a mop and a wringer bucket. This substantially increases the time needed to clean and dry a floor. An example is the Windsor Grouthog.about. made by Windsor Industries Inc. of Englewood, Colo.
The need for water pickup is recognized in some of these low profile scrubbers, but there isn't room enough in their bodies for a vacuum pickup squeegee system so they are built with other means to pick up used scrub water. Thus the Rotowash machines distributed by R. E. Whittaker Co. of New Castle, Pa., have two rotating cylindrical scrub brushes which fling water onto a slowly rotating drum between them. This water is carried up and over the top of the drum where a scraper wipes it off and directs it into a recovery tank. Experience has shown, however, that such water pickup systems do not dry a floor anywhere nearly as well as a vacuum pickup squeegee system does. Nothing has been found that will dry a hard surface floor as well as a vacuum pickup squeegee system, and to our knowledge the prior art has not produced a low profile scrubber with one.
Many fast food stores resort to a mop and a wringer bucket, and the results of using them leave much to be desired. Mopping is slow work, tends to slop dirty water on adjoining walls, and will leave a wet or still dirty floor if carelessly done.
Fast food stores are not alone in facing this problem. Other types of business establishments have furniture and equipment with a vertical clearance from the floor up to the lowest part of the equipment that is similar to the clearance under seats and tables in fast food stores. Examples might be counters and ovens in institutional kitchens such as in hospitals, nursing homes and schools, also work benches, storage racks, or machine tools in industrial plants. The present invention could be useful in such places, but for simplicity we will limit our discussion to fast food stores.
It is apparent that there is a long felt need which has been unfilled at least as long as there has been a fast food industry for a hard floor cleaning machine having the elements of an automatic scrubber (i.e. solution storage and distribution, powered scrubbing brush, and vacuum pickup squeegee with storage of dirty water) but capable of being pushed bodily under seats and tables (or other equipment having similar clearance above a floor) and scrubbing there as well as present automatic scrubbers do in aisles or other unobstructed areas.


An X-ray CT apparatus includes an image generating unit, a discrimination unit, a monochromatic X-ray image generating unit, a combined-image generating unit and a display unit. The image generating unit generates a plurality of reference material images corresponding to respective ones of a plurality of reference materials on a basis of pre-reconstruction data of multi-energy obtained by scanning a subject. The discrimination unit discriminates each of a plurality of materials contained in an imaging region of the subject on a basis of the plurality of reference material images. The monochromatic X-ray image generating unit generates a monochromatic X-ray image at energy determined by each of the plurality of discriminated materials. The combined-image generating unit combines a plurality of monochromatic X-ray images corresponding to the plurality of materials and to generate a combined image. The display unit displays the combined image on a display device.

An X-ray CT apparatus, which provides information on a subject as images based on intensity of X-rays transmitted through the subject, plays an important role in many medical actions including diagnosis and treatment of diseases and surgical planning.
Recent X-ray CT apparatuses use a technique known as dual energy scanning. The dual energy scanning as referred to herein is a technique for acquiring images by scanning a subject using two different types of X-ray tube voltage. CT which uses dual energy scanning is referred to as "dual energy CT."
The X-ray CT apparatus which uses the dual energy scanning technique separates materials based on information obtained using two different types of X-ray tube voltage and can thereby obtain various images such as monochromatic X-ray images, density images, effective atomic number images, or artifact-free images (images with reduced artifacts). Note that the X-rays used in this case are continuous spectrum X-rays containing various energies and having a specific energy distribution.
In conventional art, various types of images are obtained using the dual energy scanning technique. However, there is a problem in that it is difficult to select one of conceivable candidate energies because plural materials are considered to be usually contained in radiographic coverage and optimum energy for diagnostic imaging varies depending on a subject's diagnosis region, materials, and the like. In determining whether or not an energy value is optimum for diagnostic imaging, factors taken into consideration include, for example, whether there are large differences in CT value, providing clear contrast or whether bones and artifacts can be removed.
Suppose, for example, an X-ray CT apparatus generates monochromatic X-ray images using the dual energy scanning technique. When soft tissue contained in radiographic coverage is diagnostically imaged, differences in CT value are large at relatively low energy, providing clear contrast and making it easy to diagnostically image the soft tissue, but the differences in CT value are small at relatively high energy, providing low contrast and making it difficult to diagnostically image the soft tissue. Thus, from the perspective of diagnostic imaging of soft tissue, relatively low energy has to be selected as optimum energy for generation of monochromatic X-ray images. On the other hand, high energy is advantageous to removal of bones and artifacts contained in radiographic coverage. Then, from the perspective of capability to remove bones and artifacts, relatively high energy has to be selected as optimum energy for generation of monochromatic X-ray images. In such cases, it is difficult to select one of conceivable candidate energies.
As another example, suppose metal artifacts (artifacts stemming from man-made objects containing metal) are produced during diagnostic imaging of soft tissue. As described above, from the perspective of diagnostic imaging of soft tissue, relatively low energy has to be selected as optimum energy for generation of monochromatic X-ray images. However, because metal artifacts are reduced at relatively high energies, from the perspective of reducing metal artifacts, relatively high energy has to be selected as optimum energy for generation of monochromatic X-ray images. This also makes it difficult to select optimum energy for generation of monochromatic X-ray images.

X-ray CT apparatus, image processing apparatus, and image processing method


Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.

Image sensors are found in a variety of consumer electronics and industrial electronics. For example, digital cameras, digital video systems, and other image capture devices, such as copiers, use image sensors to capture a scene and convert the scene into an image. One type of image sensor that is commonly used in image capture devices is a solid-state image sensor, such as a complementary metal-oxide semiconductor (CMOS) image sensor. When a pixel array of the solid-state image sensor is exposed to light, photosensitive sensors of the pixel array convert the light into voltage. The voltage generated by respective photosensitive sensors is subsequently measured and used to generate or reconstruct an image.

Image sensor configured to reduce blooming during idle period

Taiwan Semiconductor Manufacturing Company Limited


A control device includes a control module controlling a polarity switching unit connected electrically to a motor unit of a food processor to provide a first current path for an input power signal through the motor unit when the control module is operated in a processing mode, and further controlling the polarity switching unit to provide a second current path for the input power signal through the motor unit when the control module is operated in a braking mode. A power control unit is connected electrically to the motor unit and the control module, and controls the power control unit such that the power control unit reduces an amount of the input power signal that flows through the second current path during a braking period when the control module is operated in the braking mode.

1. Field of the Invention
The invention relates to a control device, more particularly to a control device for a motor unit of a food processor.
2. Description of the Related Art
In a conventional food processor, a cutting blade member is driven by a motor unit to rotate during a processing period when operating in a processing mode. However, rotation of the cutting blade member does not stop immediately when the conventional food processor is deactivated.
FIGS. 1 and 2 illustrate a conventional control circuit for an alternating current series motor 11 of a food processor (not shown). The motor 11 has two stator coil units 112, 113, and a rotor coil unit 111. The conventional control circuit includes a controller (not shown) operable in a processing mode and a braking mode, and first and second switches 13, 12 interconnecting electrically the stator coil units 112, 113 and the rotor coil unit 111. Each of the first and second switches 13, 12 includes a common node (C), a first switch node (NC) and a second switch node (NO). The first switch nodes (NC) of the first and second switches 13, 12 are connected to each other. The second switch node (NO) of the first switch 13 is connected electrically to one end of the stator coil unit 112 that is connected to one end of the rotor coil unit 111. The common node (C) of the first switch 13 is connected electrically to one end of the stator coil unit 113. The first switch node (NC) of the second switch 12 is connected electrically to the other end of the rotor coil unit 111. The common node (C) of the second switch 12 is connected electrically to the other end of the stator coil unit 113.
When the controller is operated in the processing mode, the first and second switches 13, 12 are controlled by the controller so as to connect the common node (C) to the first switch node (NC) in the first switch 13 and to connect the common node (C) to the second switch node (NO) in the second switch 12, as shown in FIG. 1, so that a first current path indicated by the arrows in FIG. 1 for an alternating current signal (AC) through the motor 11 is generated.
On the other hand, when the controller is operated in the braking mode, the first and second switches 13, 12 are controlled by the controller so as to connect the common node (C) to the second switch node (NO) in the first switch 13 and to connect the common node (C) to the first switch node (NC) in the second switch 12, as shown in FIG. 2, so that a second current path indicated by the arrows in FIG. 2 for a residual power signal in the stator coil unit 113 through the rotor coil unit 111 is generated.
Since a voltage supplied to the rotor coil unit 111 in the second current path has a polarity opposite to that in the first current path, sparks or vibration may occur during the transition from the processing mode to the braking mode.
Furthermore, the residual voltage signal in the stator coil unit 113 is insufficient to stop rotation of the motor 11 within a short amount of time. Therefore, safety during a relatively long braking period cannot be ensured.

Control device for a motor unit of a food processor


A scanner driver of a galvanometric scanner system includes an analog drive circuit; a control unit 31 for storing and holding optimized data formed from combinations of optimal values of circuit constants set in advance in accordance with a plurality of drive modes of a galvanometric scanner; and an electronic trimmer for changing the circuit constants of the analog drive circuit. The control unit selects one of the optimized data in accordance with an external input, and sets or updates parameters of the circuit constants via the electronic trimmer in accordance with the selected optimized data. When a drive mode of the galvanometric scanner system is changed, the scanner driver can accordingly be optimized readily and quickly.

In a galvanometric scanner system, variable resistors and other elements are used to adjust driver circuit constants of a scanner driver, which is an analog driver, according to a variety of drive modes (drive modes based on, for example, different loads, drive patterns, and response characteristics) so as to optimize the operating characteristics of the scanner driver.
For example, a galvanometric scanner system for light beam scanning includes a galvanometric scanner for oscillating a mirror for light beam scanning within a predetermined angular range and a dedicated scanner driver for driving the galvanometric scanner. A function generator or an external command generator that includes a personal computer and a D/A converter provides a real-time drive command to the scanner driver so as to drive the galvanometric scanner according to predetermined drive control specifications.
The scanner driver includes a plurality of variable resistors and other elements for adjusting the operating characteristics of the scanner driver. To adjust the operating characteristics, an adjuster is connected to the galvanometric scanner and the adjuster is used to adjust the variable resistors and other elements so as to optimize the driver circuit constants in such a way that operating characteristics most suitable to a drive mode are obtained.
For example, optimal operating characteristics of the scanner driver in a case where the galvanometric scanner is to be moved at high speed over a wide range (coarse control) differ from those in a case where the galvanometric scanner is to be moved with high positioning precision over a short distance (fine control). To drive the galvanometric scanner from a position A to a target position B, it is necessary to change an applied command voltage from the command voltage "a" corresponding to the position A to the command voltage "b" corresponding to the position B. The change from the command voltage "a" to the command voltage "b", which are outputted from the external command generator, corresponds to a command for the scanner driver only indicative of the final target position B. Therefore, the path and time from the position A to the position B are set by adjusting the circuit constants of the analog scanner driver. For example, in a case where the drive pattern is set in such a way that the difference between the command voltages "a" and "b" is large, it is necessary to adjust the circuit constants of the scanner driver so as to optimize the operating characteristics in such a way that the galvanometric scanner can be driven with no large amount of overshoot.
Patent Document 1 discloses a galvanometric scanner system using analog input and output values. In Patent Document 1, a variety of drive patterns are stored and held in the scanner driver to drive the galvanometric scanner in an optimal manner. Patent Document 2 discloses a limited-rotation electromagnetic motor with a detector that can be used as a galvanometric scanner for mirror scanning.
[Patent Document 1] JP-A 2005-338450
[Patent Document 2] JP-A 7-31119
As described above, in a galvanometric scanner system, a plurality of variable resistors and other elements are manipulated to adjust the driver circuit constants so as to optimize the operating characteristics of the scanner driver for a variety of drive modes.
To optimize the operating characteristics of the scanner driver, however, it is necessary to adjust a large number of parameters. For example, to adjust the control gain, damping characteristics, integration constant, filter characteristics (resonance characteristics), and robustness of the scanner driver, it is necessary to manipulate a large number of variable resistors, variable capacitors, and other elements. Therefore, the adjusting is not readily performed and is time-consuming.
Since the use of such an adjustment method does not allow flexible adjustment of the scanner driver, optimal operation cannot be achieved when the drive mode of the galvanometric scanner is changed after the adjustment. In this case, it is necessary to connect an adjuster again to the scanner driver and change the variable resistance and other parameters so as to perform adjustment for optimizing the driver operating characteristics (circuit constants). Such adjustment is time-consuming and difficult to perform on the user side.

Method for adjusting drive characteristics of scanner driver of galvanometric scanner


Disclosed is a communication modulator with sample rate conversion. The modulator comprises a symbol mapping module configured to map an input bitstream to a symbol sequence; a pre-distortion module configured to multiply the symbol sequence by a discrete frequency response to produce a pre-distorted symbol sequence; a modulation module configured to modulate the pre-distorted symbol sequence to a time-domain baseband sample sequence; a sample rate conversion module configured to convert the sample rate of the baseband sample sequence to a different sample rate to produce a sample-rate-converted baseband sample sequence; and an up-conversion module configured to up-convert the sample-rate-converted baseband sample sequence to an intermediate frequency signal. The discrete frequency response by which the pre-distortion module multiplies the symbol sequence is configured to compensate for passband droop introduced to the sample-rate-converted baseband sample sequence by the sample rate conversion module.

With the advance in digital signal processing and wireless communication technologies, software defined radio (SDR) has become a reality. For SDR with multi-protocol and/or multiband capabilities, sample rate conversion (SRC) is an important element in the digital signal processing architecture of the SDR. Using SRC, digitally modulated discrete-time signals at different sample rates specific to different protocols and/or frequency bands are up-sampled into discrete-time signals with a common sample rate, which are then converted into an analog signal by a digital-to-analog (D/A) converter at the common sample rate. At the receiver, the received signal is digitised by an analog-to-digital (A/D) converter at the common sample rate and, again using SRC, variously down-sampled into streams of discrete-time signals at different sample rates specific to different protocols and/or frequency bands. Different sample rates may even be used in a single communication protocol, such as the IEEE 802.11g wireless local area network (WLAN) specification.
Using a fixed sample rate for D/A and A/D converters in an SDR-type multiband or multi-protocol communication system has a number of advantages. For example, it preserves the modularity of the system, reduces the system complexity, and provides better reconfigurability. Also, the D/A or A/D converter with a fixed sample rate has much lower jitter than a D/A or A/D converter with an adjustable sample rate. If the D/A or A/D converter operates with a fixed clock, the clock-jitter performance can be significantly improved and system integration can be greatly simplified.
In a digital communication system, the D/A or A/D sample rate is usually four to eight times the data symbol rate. If a band-pass signal is to be generated or received in the digital domain, such as in a multiband system, the sample rate will be significantly higher than that multiple. When the desired sample rate is an integer multiple of the symbol rate, the up-sampling or down-sampling process is straightforward. However, there are many applications where the ratio by which the discrete-time signal must be up-sampled or down-sampled is not an integer. Hence, the SRC method used should be able to accommodate an arbitrary non-integer conversion ratio.
SRC is theoretically a process of continuous-time signal reconstruction, or interpolation, followed by re-sampling at the desired sample rate. The interpolation is ideally realized by a Nyquist low-pass filter, which converts the discrete-time signal to a continuous-time signal without distortion. Since the ideal Nyquist filter is neither possible nor necessary in practice, how to select and implement an appropriate interpolation filter is the key issue for efficient SRC.
Various SRC structures have been proposed. The most popular and computationally efficient approach for SRC is to use the cascaded integrator-comb (CIC) filter due to its simple implementation (no multiplication is required). However, there are a few drawbacks with the CIC filter. First, it has a very wide transition band, and introduces attenuation in the passband of interest. An additional decimating low-pass filter is usually required to compensate for the passband droop. Second, it works only when the conversion ratio is rational-valued. Third, for some conversion ratios, CIC filtering has to be performed at a very high intermediate sample rate. To avoid the second stage decimating filter, different sharpened CIC filters have been proposed. However, the wide transition band and the limitation to rational-valued conversion ratios remain the same. A method for irrational conversion ratio SRC has been proposed based on the use of parallel CIC filters and linear interpolation, but the passband droop is even worse.
Different types of piecewise polynomial interpolation can be used for arbitrary ratio SRC, but the computational cost is very high. For example, the polynomial coefficient calculation requires multiplications in the order of P2 to P3, where P is the order of the polynomial, and the interpolation calculation requires additional multiplications in the order of P to P2. The Farrow structure which consists of a filter bank and a fractional delay multiplication block is widely used for efficient implementation of piecewise polynomial interpolation, but the required number of multiplications is still P2+P.
A B-spline is a piecewise continuous function which is constructed through repeated convolution of a basis function with itself. B-splines are suitable for interpolation due to their high degree of smoothness. A P-th order B-spline is of regularity P−1, meaning that it is continuously differentiable P−1 times. A centred B-spline can be efficiently implemented using the Farrow structure. However, since the frequency response of a B-spline is a power of the sinc function, the passband droop is still significant. Time-domain pre-filtering is normally implemented in B-spline interpolation for passband droop compensation, which considerably increases the interpolation complexity.
A typical digital communication system uses a transmitter filter (or pulse shaping filter) to limit the bandwidth of the transmitted signal. A receiver filter, which is usually a matched-filter having the same magnitude response as that of the transmitter filter, sometimes combined with an equalizer, is used in the receiver to achieve high signal-to-noise ratio and low inter-symbol interference. These filters are typically implemented digitally in the time domain for an SDR. Thus, combining the transmitter filter or the receiver filter with the SRC seems to be an attractive solution to relax the constraints on the SRC interpolation filter and to achieve overall complexity reduction. Using this approach, an SRC structure which includes a pulse shaping filter to compensate for the passband droop has been proposed. Unfortunately, since the CIC filter is still used for SRC, the application of this method is limited to rational conversion ratio SRC. Moreover, the pulse shaping filter design is complicated as it resorts to linear programming. An arbitrary ratio SRC structure using B-splines has been proposed, which combines the interpolation filter with the transmitter/receiver filter and compensates for the passband droop by digital filtering operating in the discrete-time domain at an up-sampled intermediate sample rate. However, the required discrete-time-domain digital filtering still contributes significantly to the complexity of the SRC processing.

Arbitrary sample rate conversion for communication systems

Commonwealth Scientific and Industrial Research Organisation


A vehicle ramp is formed as a unitary sheet metal member and has a inclined ramp portion provided with longitudinally spaced rows of stiffening bosses and a flat reinforcement area at a lower end of the ramp. A raised wheel rest portion has a generally flat bottom surface and is reinforced by a transverse projection which terminates at a pair of longitudinally extending side depression formed at the junction of the wheel rest portion and the ramp. A pair of raised rails extend completely along the sides of the ramp and wheel rest portion, and downwardly along the sides of an end wall which forms the elevating rear support portion of the ramp. The stiffening bosses are arranged in alternating rows of three and four bosses per row. A stop is formed at the junction of the wheel rest portion and the elevating support portion and has a rearwardly inclined transverse stiffening projection. The particular arrangement of bosses, side rails, and various depressions and projections provide a strong support ramp with a reduced metal thickness and weight without sacrificing safety.

1. Technical Field
The invention relates to vehicle ramps of the type for supporting a wheel or wheels of a vehicle sufficiently clear of the ground to enable a person to slide under the vehicle for underside inspection and/or repair purposes.
More particularly, the invention relates to a vehicle ramp formed as a single stamp sheet metal member of a relatively light gauge yet which is exceedingly strong and safe.
2. Background Information
Many vehicle owners perform routine maintenance and repairs on their vehicles. In order to gain easy access to the underside of the vehicle they will elevate either the front or rear portion of the vehicle on which they are working to provide such access. Various portable ramps have been used by amateur auto mechanics and vehicle owners for this purpose. These ramps are usually formed of metal and have various configurations to enable the vehicle wheel to be driven up an incline portion of the ramp, afterwhich it settles into a wheel retaining area of the ramp.
Prior examples of such metal ramps are shown in U.S. Pat. Nos. 2,279,464, 2,450,648, 3,638,910, 3,847,376, 3,870,277, 3,917,227, 4,421,300 and 4,050,403; and in U.S. Pat. Nos. D 228,301, D 232,020, D 237,162, D 239,610 and D 313,102.
Although many of these prior art ramps are satisfactory for their intended purpose, it is always desirable to be able to manufacture such a ramp at a reduced cost and of a lighter weight, in order for it to be more easily handled by the user, but without sacrificing any safety to the user thereof. It is also desirable to manufacture such a vehicle ramp as an integral one-piece member free of moving parts which require manipulation and are subject to breakage and maintenance.
Therefore, the need exists for an improved vehicle ramp which enables the user to drive one of the vehicle wheels along the ramp to a safe resting position, whereat the vehicle will be safely supported for subsequent repair and maintenance, by a lightweight, yet sturdy and durable device, free of moving parts which require extra manipulation by the user thereof.


A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.

In semiconductor processing, processing techniques can be used to decrease package size of semiconductor devices. Generally in package processing, semiconductor dies are placed active surface side down on an adhesive material situated on a process carrier substrate, and encapsulated with a molding material, which is then cured. The molding material can be any appropriate encapsulant, for example, a silica-filled epoxy molding compound, a plastic encapsulation resin, or other polymeric material such as silicones, polyimides, phenolics and polyurethanes. The encapsulated die panel is then separated from the adhesive material and process carrier substrate and cleaned to remove any remaining adhesive. Additional processing can then be conducted on the exposed surface of the dies to build-up a multi-layer circuit interconnect. An interconnect is generally composed of alternating layers of an insulating or dielectric material and metal (e.g., traces, interconnects, etc.). The interconnect is typically formed using photolithography and plating techniques. Solder balls can be formed or dropped on solder ball pads formed in a final metallization layer, for making electrical connections to a PCB. The dies can then be singulated by cutting through designated areas to form single or multiple semiconductor device packages.
Solder ball pads are formed on a semiconductor die to provide means for transferring electrical signals and power to and from circuitry of the semiconductor die through solder balls, conductive bumps, etc. In a multilayered circuit interconnect, an insulative layer or solder mask (also called a passivation layer) is formed over the final metallization layer that has been laminated or formed on an insulating layer. The final metallization layer typically includes solder ball pads, circuit traces, through-hole vias, etc. An opening is formed in the solder mask to expose a portion of the solder ball pad and a solder ball may be attached or formed on the exposed pad area. In semiconductor processing, it is important to have a good connection and adhesion of metal layers and insulating layers to prevent cracking of the insulating layers which can reduce package integrity and reliability and lead to chip failure.

Solder pad for semiconductor device package


According to one embodiment, in response to a request received from an application by a launch module hosted by an operating system and executed by a processor to dynamically load a library, a library validation module hosted by the operating system extracts a first team identifier (ID) from the application, where the first team ID identifies an application provider that provides the application. The library validation module extracts a second team ID from the library, where the second team ID identifies a library provider that provides the library. The first team ID and the second team ID are compared to determine whether the first team ID matches the second team ID. In response to determining that the first team ID matches the second team ID, the launch module launches the library to allow the application communicate with the library; otherwise, the request is denied.

Security concerns for all types of processor-based electronic devices, and particularly for computing devices, have become a significant concern. While some concerns may relate to detrimental actions which may be undertaken by defective code implemented by such devices, the greater concerns relate to the ramifications of various types of attacks made upon such devices through malicious code, including code conventionally known in the field by a number of names, including "viruses," "worms," "Trojan horses," "spyware," "adware," and others. Such malicious code can have effects ranging from relatively benign, such as displaying messages on a screen, or taking control of limited functions of a device; to highly destructive, such as taking complete control of a device, running processes, transmitting and/or deleting files, etc. Virtually any type of imaginable action on a processor-based device has been the subject of attacks by malicious code.
A number of methodologies have been used in an attempt to reduce or eliminate both the attacks and influence of malicious or defective code. Generally, these methodologies include detection, prevention, and mitigation. Specifically, these methodologies range from attempts to scan, identify, isolate, and possibly delete malicious code before it is introduced to the system or before it does harm (such as is the objective of anti-virus software, and the like), to restricting or containing the actions which may be taken by processes affected by malicious or defective code.
Applications are among the most critical elements of a modern security architecture. While applications provide amazing productivity benefits for users they also have the potential to negatively impact system security, stability, and user data if they are not handled properly. An application may be executed within a restricted operating environment such as a sandbox or virtual machine to prevent the application from accessing any resource beyond the restricted operating environment. In another method, an application may be executed only if the application has been authorized by a trusted source. However, such authorization is typically provided when the application is distributed prior to the execution. However, it does not prevent an application from dynamically loading a library that the application is not entitled to communicate, even if the library may be authorized by the trusted source.

Method for validating dynamically loaded libraries using team identifiers


An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.

1. Field of the Invention
This invention relates generally to memory devices and, more particularly, to an apparatus and method for storing analog or multi-level signals in a memory device.
2. Description of the Related Art
Electronic storage devices are currently capable of storing analog signals. In general, these storage devices use one of two approaches to store analog signals. One approach is to convert the analog signal into a digital signal using an analog-to-digital ("A/D") convertor. The digital signal is then stored in a conventional digital memory device, such as, for example, SRAM and DRAM memories. While the digital approach provides high quality and accurate reproduction of the analog signal, such as an audio signal, the use of A/D and D/A convertors increases the overall complexity of the memory device. Additionally, digital storage of analog signals typically requires a large memory capacity.
The other approach involves storing the analog signal directly to a nonvolatile memory cell. FIG. 1 represents a conventional analog storage device 100. Conventional analog storage device 100 includes a sample and hold ("S/H") circuit 102, a comparator 104, a comparator send circuit 106, a comparator entry circuit 108, a high voltage charger and sensor 110, and a memory cell 112. Typically, memory cell 112 is part of a large array of memory cells; however, for simplicity the example is limited to one memory cell 112.
FIG. 2 represents a flow chart 200 illustrating how analog storage device 100 operates. First, S/H circuit 102 samples an analog signal at a predetermined sample rate to obtain and hold a sample voltage (step 202), which is indicative of the analog signal. Next, S/H circuit 102 sends the sample voltage to a first input of comparator 104 (step 204). Comparator 104 compares the sample voltage at the first input of comparator 104 to the voltage at a second input of comparator 104 (step 206). During the first iteration of this procedure, the second input of comparator 104 is initialized to a predetermined value. Based on the comparison, comparator 104 determines whether the first input and the second input are approximately equal (step 208). If comparator 104 determines the inputs are approximately equal (i.e., within a predetermined tolerance), then the voltage level currently stored in memory cell 112 is considered equal to the sample voltage and the process stops (step 210), otherwise comparator send circuit 106 sends a charge signal to high voltage charger 110 (step 212). High voltage charger 110 increases the voltage stored in memory cell 112 by sending a programming voltage pulse to memory cell 112 for a predetermined length of time (step 214). After a predetermined length of time, high voltage charger 110 increases the magnitude of the programming voltage pulse by a predetermined amount (step 216). Comparator entry circuit 108 then senses the voltage signal currently stored in memory cell 112 (step 218). Comparator entry circuit 108 sends the sensed voltage read from memory cell 112 to the second input of comparator 104 (step 220). Steps 206 to 220 are repeated until the sampled voltage and the voltage sensed from memory cell 112 are equal, at which time the process stops at step 210. U.S. Pat. No. 4,890,259, issued to Richard T. Simko, discloses details of such a conventional analog storage device.
Thus, the second approach to storing analog signals uses an iterative, trail and error programming process. In other words, the memory cell receives an initial programming voltage pulse corresponding to a low sample voltage. The programming voltage pulse is then incremented by a fraction of a volt. This process of programming and incrementing continues until the voltage programmed into the memory cell equals the sampled analog input voltage. In the above noted U.S. Pat. No. 4,890,259, charging the memory in this fashion can involve up to 400 iterations. Programming the memory cell through the above described iterated process, therefore, takes a significant amount of programming time. It would be desirable to reduce the programming time.


A process for cooling, phase separating, rectifying and stripping a hydrocarbon containing feed gas stream to recover a heavy hydrocarbon product wherein a predominant amount of the refrigeration for the process is provided from a single loop vapor recompression refrigerator employing a mixed refrigerant.

A process for the recovery of a heavy hydrocarbon product (i.e., C.sub.2 + or C.sub.3 + hydrocarbons) from a hydrocarbon containing stream using the sequential steps of cooling, phase separating, rectifying and stripping is taught in the art. Specifically, U.S. Pat. No. 4,622,053 by Tomlinson, et al. discloses such a process. Tomlinson further discloses that the refrigeration for the process can be provided by a two-stage (two loop) cascade refrigerator (the preferred embodiment) or a single loop vapor recompression refrigerator employing a mixed refrigerant. It has now been found, however, that the efficiency of Tomlinson's cycle incorporating the sequential steps of cooling, phase separating, rectifying and stripping wherein the predominant amount of refrigeration is provided by a single loop vapor recompression refrigerator employing a mixed refrigerant can be significantly improved.
Other prior art of general relevance showing various individual steps that are relevant to the technical field of the present invention, including phase separating, rectifying via low temperature dephlegmation and stripping include: U.S. Pat. Nos. 4,002,042; 4,272,270; 4,356,014; 4,526,596; 4,507,133; 4,608,068; 4,664,687; 4,675,036; 4,707,170; 4,714,487 and 4,718,927.

Process for the recovery of C.sub.2 + or C.sub.3 + hydrocarbons