A microcomputer includes dedicated output transistors for driving a bus for access to an external memory. The output transistors are smaller in size than transistors for other input/output ports. The microcomputer and the external memory are interconnected through a double-sided printed-circuit board forming a multi-chip module (MCM). The module has pin assignments substantially the same as those of a single-chip microcomputer. Selector circuits are included in the module to test specifically the external memory connected to the selectors.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly a microcomputer and a multi-chip module incorporating the same.
2. Description of the Prior Art
A growing number of connection terminals attached to semiconductor devices have been making it increasingly difficult to route the wiring properly for installing such a device onto a substrate. When mounted on a substrate of an enlarged scale, semiconductor devices are required to have a bus structure whose driving capacity should be large enough to transmit signals accurately throughout the substrate. These developments have been accompanied by extraneous radiation noise that requires suitable techniques for reduction. In addition, given the fact that test costs form an increasing proportion of overall semiconductor fabrication expenditures, there is a growing need for designs that facilitate testing procedures.
Some typical conventional examples relevant to the scope of this invention are described below.
FIG. 14 is a block diagram outlining the basic design of a circuit comprising a conventional microcomputer. In FIG. 14, reference numeral 1 stands for a printed-circuit board; 2 for a microcomputer comprising a ROM; 3 for an external memory; 4 and 5 for a first and a second peripheral circuit respectively; and 6 and 7 for a bus each. The external memory 3 is connected with the microcomputer 2 via the bus 6 interconnecting the circuit elements. The peripheral circuits 4 and 5 are connected with the microcomputer 2 via the bus 6 and are also connected to each other by way of the bus 7.
Upon access to the external memory 3, the microcomputer 2 transmits data and an address thereto over the bus 6. The microcomputer 2 also utilizes the bus 6 when controlling the peripheral circuits 4 and 5. The peripheral circuits 4 and 5 use the bus 7 for data exchanges therebetween.
FIG. 15 is a block diagram showing a typical configuration of the microcomputer 2. In FIG. 15, reference numeral 65 represents an output transistor group connected to the bus 6. The output transistor group 65 is activated when the microcomputer 2 either accesses the external memory 3 or controls the peripheral circuits 4 and 5. Here, it should be noted that the bus 6 connected to the external memory 3 has a large parasitic capacitance since it is also connected to the peripheral circuits 4 and 5. The need to drive that bus 6 at a high speed makes it impossible to reduce the driving capacity of the transistors constituting the output transistor group 65.
The first conventional example works as follows: a microcomputer terminal is selected to access the internal ROM functions as a normal port. In extended memory mode in which the microcomputer 2 gains access to the external memory 3, the bus functions as an address or data bus operating at a high speed. Illustratively, where the microcomputer 2 operates on a basic clock of 10 MHz, the external memory 3 is accessed in 100 ns. The microcomputer 2 accesses the internal ROM and, as needed according to the program contained therein, gains access to the peripheral circuits 4 and 5 via the terminal acting as the normal port also connected to the external memory 3. The speed at which to access the peripheral circuit 4 or 5 does not exceed the speed in accessing the external memory 3. If the second peripheral circuit 5 needs to be controlled both by the microcomputer 2 and by the first peripheral circuit 4, these circuit elements must be interconnected using suitable signals over the bus 7.
FIG. 16 is an explanatory view showing how a plane formed by a current loop forms an angle with respect to an observation point. In FIG. 16, reference numeral 62 stands for a closed circuit formed by a current, 63 for a plane constituted by the current circuit, and 64 for a power supply. According to Denshi Gijutsu ("Electronic Technology," a Japanese publication) 1996, Vol. 38, No. 5, the amount of radiation energy EM stemming from extraneous radiation noise is given by the expression (1) below: EQU E.sub.M =120{.sqroot. (.mu..sub.S /.epsilon..sub.S)}.pi..sup.2 IS(e.sup.-JKr /.lambda..sup.2 d)sin .theta.(V/m) (1)
where .mu..sub.S stands for relative magnetic permeability, .epsilon..sub.S for relative dielectric constant, I for the amount of current, S for the area occupied by the loop formed by current, Kr for propagation coefficient, .lambda. for wavelength, and .theta. for the angle between observation point and plane formed by current loop.
Because a plurality of circuit elements such as the peripheral circuits 4 and 5 and external memory 3 are connected to the bus 6, their wiring needs to be routed suitably over the printed-circuit board. Since the load capacitances of these circuit elements are parasitic on the wiring of the bus 6, the output transistor group 65 needs to have a driving capacity large enough to drive the bus 6 at high speed. However, the use of transistors with large driving capacities necessarily entails an increase in currents that flow through the wiring provided the impedance of external elements remains constant.
FIG. 17 is a graphic representation showing how time and voltage are related in comparing leading edges of output waveforms of transistors with different driving capacities. As illustrated in FIG. 17, a transistor with a large driving capacity generally produces an output waveform 71 with a steeper leading edge and a smaller wavelength .lambda. than a transistor with a small driving capacity yielding an output waveform 72. That is, as per the expression (1) above, transistors with large driving capacities are bound to have growing amounts of radiation energy E.sub.M stemming from extraneous radiation noise.
Although it is conceivable to use a buffer on the printed-circuit board to suppress currents so as to increase the driving capacity of the bus 6, the scheme has the disadvantage of increasing the number of parts used. In any case, the wiring tends to be elongated and parasitic capacities are raised, which makes it difficult to boost the speed of circuit operation. That is because wiring delay is generally proportionate to capacity and resistance involved. Furthermore, any of the conventional techniques above for enhancing the driving capacity of the output transistor group 65 entails an increased amount of currents. This promotes power dissipation and involves an increase in extraneous radiation.
In another conventional basic board design of circuits such as a circuit including the microcomputer in FIG. 14, it has become difficult to optimize the layout of the numerous circuit elements. One conventional solution to that bottleneck is the adoption of a multi-layer board concept at the basic design stage whereby signal lines are routed across layers. Another solution is to have peripheral elements mounted on the back of the board in a double-sided printed-circuit design.
FIGS. 18A and 18B show pin terminal arrangements of a conventional microcomputer 2' and of an external memory 3'. FIG. 18A is a pin terminal layout view of the external memory 3', and FIG. 18B is a pin terminal layout view of the microcomputer 2'. In the two figures, reference numerals 30a through 30h denote lines and pin terminals connecting the microcomputer 2' to the external memory 3' via the bus 6, the pins and lines being interconnected where they have the same reference numerals. Between the two layout views, the pin terminals 30a through 30h connecting the microcomputer 2' to the external memory 3' via the bus 6 do not match in sequence. The layout mismatch requires lines to be crossed on the board, which makes it impossible to route the wiring over the shortest possible distances.
In another conventional semiconductor integrated circuit design, the circuits inside a chip share common power supplies with the exception of special-purpose components (clock, analog power supply, etc.). FIG. 19 is a schematic view outlining power supply connections of a conventional microcomputer. In FIG. 19, reference numeral 2e stands for a microcomputer; 33' and 34' for a power supply line and a ground line respectively; 39' and 40' for a power supply pad and a ground pad respectively; 37b and 38b for a bus each; 37a for an output transistor group for driving the bus 37b connected to an external memory; and 38a for an output transistor group for driving the bus 38b connected to peripheral circuits.
The third conventional example works as follows: the power supply line 33' connected to the power supply pad 39' supplies power not only to the output transistor group 37a but also to the output transistor group 38a. The ground line 34' connected to the ground pad 40' feeds both output transistor groups 37a and 38a with ground potential. When transistors in the output transistor group 37a connected to the memory bus 37b are switched at high speed, the wavelength .lambda. in the expression (1) above is diminished. This oscillates the power supply line 33' at a high frequency of, say, 100 MHz, generating radiation noises inside the chip. Such radiation noise propagates through the other power supply line to reach other output pins which release the noises.
According to another conventional chip layout design, multi-chip module (MCM) technology allows a plurality of bare chips to be assembled into a single module that is small and lightweight. Because the multi-chip module has numerous wires, the inclusion in a single package of both a microcomputer and a memory subject to access at high frequency contributes to reducing the quantity of the wiring on the board. This setup, however, requires a general-purpose memory to be installed in the multi-chip module. The arrangement is costly for the manufacturer. It is thus desired to replace such a memory with an inexpensive built-in mask ROM of a single-chip microcomputer.
FIG. 20 is a block diagram of a conventional multi-chip module (MCM) constitution. In FIG. 20, reference numeral 53' stands for an MCM package; 54' for a microcomputer; 55 for an external memory; 101 for a normal port; 102 for a memory bus; 57 for a normal port input/output signal line group of the microcomputer 54'; and 58 for a memory bus signal line group of the microcomputer 54'. The memory bus signal line 58 is connected to the external memory 55 but, with no need to attach to any other component, is not connected to any external terminal of the MCM package 53'.
The microcomputer of FIGS. 14-17 configured as described above, is characterized by a large parasitic capacitance of the bus 6. That proves to be a major impediment to improving the access speed of the device as a whole. Attempts to boost the operating speed increase the amount of currents resulting in higher power dissipation in conjunction with the driving capacity of output transistors; extraneous radiation noise is also promoted.
The microcomputer of FIGS. 18A-18B configured as described above, has an elongated bus 6 extending from the microcomputer 2. This structure enlarges the area S of the loop formed by currents. According to the expression (1) above, the structure increases extraneous radiation noise. Because the wiring on the board is routed over long distances, the parasitic capacitance is increased along with signal delays, which keeps the speed of circuit operation low.
The microcomputer 2e of FIG. 19 configured as described above, has its output transistor groups 37a and 38a switched at high speed, generating radiation noise therebetween. The noise tends to propagate over the power supply line 33' and ground line 34.
The multi-chip module (MCM) configured as described above, has a microcomputer chip and a general-purpose memory chip simply wired on a multi-chip module board. Compared with the single-chip microcomputer setup, the example most often has disparate pin arrangements between the chip and the memory and are subject to worsening noise or power dissipation characteristics. This requires devising a complicated basic design.
The multi-chip module (MCM) of FIG. 20, configured as described above, has the memory bus signal line 58 connected only to the microcomputer 54' and external memory 55. Because the memory bus signal line 58 is not connected to any external terminal of the multi-chip module package, it is impossible to submit the external memory 55 to product inspection and failure analysis.
The microcomputer 54' thus needs to incorporate a circuit for evaluating the inspection and analysis functions in advance or is required to be programmed to let such evaluation be performed in a predetermined manner. These arrangements permit little degree of freedom in inspection and analysis procedures. Furthermore, it is necessary to develop anew test patterns by which to subject the multi-chip module 53' to product inspection. Such development takes time.


Provisioning resources in public cloud infrastructure to perform at least part of electronic design automation (EDA) tasks on the public cloud infrastructure. Performance metrics of servers in the public cloud infrastructure and performance history of a user's past EDA tasks are maintained to estimate operation parameters such as runtime of a new EDA task. Based on the estimation, a user can provision appropriate types and amounts of resources in the public cloud infrastructure in a cost-efficient manner. Also, a plurality of EDA tasks are assigned to computing resources in a manner that minimizes the overall cost for performing the EDA tasks.

1. Field
This disclosure relates generally to provisioning resources on public cloud infrastructure or hybrid cloud infrastructure to perform electronic design automation (EDA) tasks.
2. Description of the Related Art
An electronic design automation (EDA) refers to software tools or processes of designing integrated circuit (IC) devices with the aid of computing devices. An EDA process generally includes, for example, system design operations, logic design and functional verification, synthesis, netlist verification, design planning, physical implementation, analysis and extraction, physical verification, resolution enhancement, and mask data preparation. EDA tools dedicated to one or more of these tasks are commercially available from EDA tool developers such as Synopsys, Inc. of Mountain View, Calif. Generally, the EDA tool developers grant licenses to use the EDA tools in return for licensing fees. The licensing fees increase as the number and types of accessible EDA tools increase.
As more components are integrated into an IC device and more functions are accommodated in the IC device, some EDA task sets have come to require a large amount of computing and storage resources. Some EDA task sets may take days, weeks or even months to accomplish. To reduce such an extended runtime or meet other constraint conditions, EDA task sets may be divided into multiple smaller EDA tasks and then executed on multiple computing resources (e.g., servers) in parallel. Some EDA tasks may take longer to finish while other EDA tasks may finish in relatively short time. Also, accomplishment of an EDA task may be a prerequisite to performing another EDA task. Hence, a careful planning of the EDA tasks is needed to accomplish the EDA tasks within the constraint conditions.
If computer resources are under-provisioned, the EDA task set may not be finished within time. Hence, in many cases, redundant computing resources are provisioned to ensure that the EDA tasks are finished within time. However, over-provisioning computing resources increases the cost associated with the EDA tasks.
Generally, the EDA task sets are performed intermittently depending on the design cycle of the designer's IC devices. During times when a new IC device is not being developed, the developer's servers or server farms may remain idle. If the servers or server farms are under-provisioned, however, there may be insufficient resources when the designer is actively designing the IC devices. The large fluctuation in the computing demand as a result of the design or product cycle renders performing the EDA tasks entirely in private infrastructure inefficient.

Efficient provisioning of resources in public infrastructure for electronic design automation (EDA) tasks


A method of installing a movable roof assembly in the roof of a vehicle, wherein the vehicle having an open roof construction including a top section with a roof opening and a sliding roof mounted on the roof opening, the sliding roof including a center bar positioned substantially across a mid region of the roof opening for increasing safety of occupants in the vehicle, the center bar being fixedly attached to a rigid body of the vehicle. The center bar is preferably accessible from the interior of the vehicle and is adapted to house at least one vehicle accessory such as roller sun blinds, storage compartments and/or light fittings.

1. Field of the Invention
The invention relates to a vehicle provided with an open roof construction that allows opening of the vehicle roof.
2. Description of Related Art
An increasing percentage of car buyers want a sliding roof with a large slide opening and/or a large glass surface.
For instance, the published German Patent Application 38 02 380 shows a vehicle roof having a large roof opening which can be covered by two roof panels positioned one behind the other. The rear panel can be removed after unlocking it and the front panel can first be tilted in the manner of a so-called spoiler roof such that front panel is first tilted so that the rear edge is raised, and then can be slid backwards.
The published German Utility Model 29 512 643 shows a vehicle having a spoiler roof consisting of two panels which are positioned one behind the other and are slidable in the longitudinal direction of the vehicle. The spoiler roof includes a means for pivoting the panels upwards into the ventilation position and for moving them in the opposite direction into the closed position.
These known constructions do not have a roof cross-member which greatly increases the safety of the occupants in the event of a collision. While it is true that such a roof cross-member fitted between the B-pillars of the body of a vehicle are known in conventional vehicles having a small roof opening, such roof cross-member would have to be removed if the abovementioned vehicle roof construction is to be used. However, such removal of a roof cross-member is not desirable since the sliding roof construction does not provide the same level of safety to the vehicle occupants as the roof cross-member.
The primary object of the present invention is to provide a vehicle with an open roof construction which improves the safety of the occupants over prior art vehicles having open roof constructions.
According to one embodiment of the present invention, the vehicle with an open roof construction includes a center bar which increases safety of the vehicle occupants and is adapted to be fitted with accessories for the vehicle. In this regard, the center bar is fixed to the body of the vehicle such as the vehicle""s top section in the mid region of the roof opening. The center bar may also be accessible from the interior of the vehicle and can be provided with numerous vehicle accessories housed thereon.
The center bar can thus, replace the center cross-member which may be provided in standard vehicles, such cross-members being removed to provide a large open roof construction.
Preferably, the center bar may be fixed to the vehicle body using fixing brackets.
If the open roof construction is provided with a frame that delimits the edges of the roof opening, the ends of the center bar can alternatively be fixed to the frame.
The center bar can serve to house a wide variety of accessories, such as two roller sun blinds, one that can be moved forward from the center bar and one that can be moved to the rear from the center bar into the working position, storage compartments and light fittings.
Vents may be provided, as well as light fittings, at the rear edge of the rear panel.
Movement of the front panel can be implemented in various ways. Preferably, the front panel is adapted to slide over the rear panel following a lifting movement.
These and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the invention when viewed in conjunction with the accompanying drawings.

Method of installing a movable roof assembly in the roof of a vehicle


A system for matching a optical filter characteristic of a first filter tunable in wavelength with an optical first signal comprises a modulator for modulating at least a part of the first signal with a modulation signal before being applied to the first filter. An analyzing unit derives a control signal for tuning the first filter by analyzing the modulated first signal after passing the first filter in conjunction with the modulation signal.

The present invention relates to tunable filters.
Tunable filters, such as Fiber Fabry-Perot tunable filters (FFP-TFs), can be used in connection with laser sources e.g. for suppressing source spontaneous emission (SSE) noise representing an undesired optical power in parts of the spectrum other than the lasing frequency itself. However, the central wavelength in transmission spectrum of the tunable filter must well match with the wavelength of the laser signal in order not to unduly decrease optical power of the laser signal. The filter is therefore tuned in wavelength to ensure that the maximum of the tunable filter pass band is fixed to the frequency of the peak lasing intensity.
Beside an initial adjustment of the filter maximum to the laser peak frequency, a continues adjustment might be required in order to correct for mismatches between filter and laser caused e.g. by tuning the laser frequency, thermal variations in the filter, or frequency drift in the laser.
In U.S. Pat. No. 5,552,919, the central wavelength in the transmission spectrum of the tunable filter is periodically and minutely modulated. An error signal is generated for use in tracking the central wavelength of the filter to the wavelength of the laser by analyzing the modulated filter output.
Although no details of an "Automatic Laser Tracking Filter—ALTF", as published by Micron Optics, Inc. in its "2001 Test Instruments" brochure, see http://www.micronoptics.com/altf.htm, are disclosed, it appears that the ALTF makes use of the same principle as disclosed in the aforementioned U.S. Pat. No. 5,552,919, i.e. dithering the filter characteristics for deriving a control signal to displace the filter characteristics. After passing the tunable filter, a small fraction of the optical power is tapped off and sent to a detector. The electrical signal from the detector is fed to a scan and lock circuitry. A phase lock loop (PLL) ensures that the maximum of the tunable filter pass band is fixed to the frequency of peak lasing intensity.


The present invention provides aligned fine particles that are aligned on a substrate. An organic coating film is bonded to surfaces of the fine particles is formed on the surfaces of the fine particles. An organic coating film bonded to a surface of the substrate is formed on the surface of the substrate. The organic coating film on the surfaces of the fine particles is bonded to the organic coating film on the surface of the substrate, whereby the fine particles are immobilized and aligned on the substrate. Thus, it is possible to align the fine particles of a nanometer scale in a specific direction. When fine magnetic particles are used, a magnetic recording medium for high recording density can be obtained, and a high-density magnetic recording/reproducing apparatus can be provided.

1. Field of the Invention
The present invention relates to aligned fine particles in which fine particles whose surfaces are coated with an organic coating film are aligned on a surface of a substrate, a method for producing the same and a device using the same. The present invention also relates to industrial applications thereof, that is, a magnetic recording medium for high density magnetic recording/reproduction in which fine magnetic particles are aligned on a substrate, a magnetoresistive device, and a semiconductor device utilizing fine particles.
2. Description of the Related Art
There have been methods for forming fine particles on a surface of a substrate for a long time. Conventional and typical techniques include a method of dipping a substrate in a fine particle solution in which fine particles are dispersed, a method of dripping fine particles on a surface of a substrate for bar coating, and a method of dripping a fine particle solution as above on a surface of a substrate and then applying it over the surface by rotation.
Furthermore, a method for forming an organic thin film on surfaces of fine particles has been under development for a few years. JP1(1989)-309902A discloses a method of coating surfaces of fine particles with an organic material comprising a chlorosilane compound or the like, and a method for forming a film made of fine particles on a surface of a substrate. In addition, it recently has been reported in a scientific magazine (Science, Mar. 17, 2000) that a monomolecular film-like film is formed on surfaces of fine particles, and they are formed on a surface of a substrate. This method has broken the limit of the crystal grain size control of a conventional thin film magnetic recording medium, and has received attention as an attempt to control magnetic domains by the size of the fine particles.
A method for forming a pattern of fine particles is disclosed in JP2(1990)-9196.
A tunnel magnetoresistive device utilizing fine particles has been proposed (Science, vol. 290, Nov. 10, 2000, page 1131).
In the field of semiconductor devices, dot memory devices employing nanoparpticles as their floating gates are expected to serve as a high-speed operable non-volatile memory (e.g., S. Tiwari et al. Applied Physics Letter, vol. 68, page 1377, 1996). In the dot memory devices, metallic or semiconductor fine particles of several nm or less are used to carry charges.
However, none of the conventional and typical techniques such as dipping a substrate in a fine particle solution in which fine particles are dispersed, dripping fine particles on a surface of a substrate for bar coating, and dripping the fine particle solution on a surface of a substrate and then applying it over the surface by rotation can control the thickness of the fine particles on the order of the fine particle size. In addition, as the fine particle size becomes smaller, the distribution of the thickness of the fine particles on the surface of a substrate becomes larger.
JP 1(1989)-309902 is valuable as a basic patent for coating the surfaces of fine particles with a monomolecular film, but fails to disclose a method for immobilizing the fine particles on the surface of a substrate, and thus presumably has problems in the practical use, the production, and the durability.
In the above-described article (Science, Mar. 17, 2000), a method for controlling the thickness of a film comprising fine particles is not established, and this article only discloses that fine particles are placed on the surface of a substrate as in the above-described patent and seems to have a problem in adhesion between the substrate and the fine particles and thus a large problem in the practical use, the production, and the durability. When producing a magnetic recording medium by such a method, it is difficult to apply fine particles in a uniform thickness on the entire area of a HDD drive (at least 1 square inch) that is in practical use at present.
In the conventional methods, only one type of fine particles is used. However, not only one type but a plurality of types of fine particles may be required to produce a functional device. There is no disclosure or conception of such a method in the prior art.
JP2(1990)-9196 is valuable as one approach for forming a pattern of fine particles, but fails to disclose coupling between fine particles and a substrate as in the above-described patent and article, so that this also seems to have problems in the practical use, the production, and the durability.
Also when forming a magnetoresistive device employing fine particles, it is important to disperse the controlled number of layers of fine particles having uniform sizes.
When applying this technique of employing fine particles to semiconductors, it is essential to form ultrafine particles having uniform particle sizes in a high density and uniformly on a tunnel insulating layer. However, the conventional techniques have not succeeded at it.

Aligned fine particles, method for producing the same and device using the same

Matsushita Electric Industrial Co., Ltd.


A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal intervals. As a result, continuity and repeatability in patterns may be maintained and pattern defects may be minimized or prevented.

1. Technical Field
The present disclosure relates to a memory device, and more particularly, to a NAND type non-volatile memory device and a method for forming the same.
2. Discussion of the Related Art
Non-volatile memory devices retain stored data even when no power is supplied to it. One example of a non-volatile memory device is a flash memory device. The flash memory device writes and erases data using electric signals. The flash memory device may be classified as a NOR type flash memory device or a NAND type flash memory device. Since the NOR type flash memory device is capable of performing high speed random access, it is widely used in devices that require high speed operation. Since the NAND type flash memory device has an excellent programming and erasing speed and can be easily realized in high integration, it is widely utilized in high-capacity storage units.
The NAND type flash memory device includes a plurality of cell strings. Each cell string includes a plurality of unit cells connected in series. A string select transistor and a ground select transistor are connected to two sides of each of the unit cells, respectively. The unit cells and select transistors are formed on an active region of a semiconductor substrate. The NAND type flash memory device applies a predetermined bias into the active region. Accordingly, the NAND type flash memory device has a structure in which a bias is applied into a well.
A structure for applying a well bias is discussed in Korean Patent Publication (NO. 1999-31469). According to the structure, a region where a well contact is formed is larger than a neighboring region where a cell string is formed. Additionally, to form the well contact, a portion of gate lines may be cut. Accordingly, continuity and/or repeatability of patterns become(s) irregular due to the well contact in the semiconductor substrate. Due to the irregularity of continuity and/or repeatability in the patterns, a photolithography process becomes unstable. For example, because of a difference in an amount of scattered reflection during exposure due to the discontinuity and non-repeatability of patterns, product defects occur during a photolithography process. Accordingly, other neighboring patterns (e.g., an active region where cells are formed, gate lines and/or select gate lines in cells) where the well contacts are formed may have an irregular form. Consequently, since the distribution of the non-volatile memory cells becomes irregular, it may cause characteristic deterioration and malfunction in the NAND type non-volatile memory device. Since there is a trend towards highly-integrated semiconductor devices, the minimum line width of the device is reduced. Therefore, pattern defects due to the discontinuity and/or non-repeatability in patterns occur more frequently.

NAND type non-volatile memory device and method of forming the same


A viewing system configured to combine multiple spectral images of a scene, the system includes a spectral beam separator configured to split an incoming beam of radiation into a first and a second beam of radiation, the first beam of radiation including radiations substantially in a first spectral band and the second beam of radiation including radiations substantially in a second spectral band; an image intensifier configured to intensify the second beam of radiation, the image intensifier including a photocathode configured to produce a flux of photoelectrons with substantially increased efficiency when exposed to the second beam of radiation, the photocathode constructed and arranged to substantially absorb all the radiations in the second beam of radiation; a current amplifier configured to amplify the flux of photoelectrons; and a display system configured to display an image of the scene in the second spectral band based on the amplified flux of electrons simultaneously with an image of the scene in the first spectral band.

1. Field
The present application relates to an imaging system.
2. Description of Related Art
Night vision cameras are the mainstay of security systems, search and rescue systems, air traffic control systems, as well as in certain astronomical and scientific missions. Night vision cameras are designed to operate in low illumination conditions where both low intensity visible light and near-IR light (both ambient as well as black body radiation) are utilized for image formation. In military and security related applications, due to the harsh and rapidly changing environmental conditions under which cameras need to operate, two separate video displays are provided, one for the visible spectrum and the other for the near infra-red spectrum. The color camera displays the image when the ambient light intensity is high enough, such as when the subject frame is illuminated by an external visible light source (at dawn or dusk). When the ambient light is low, the night vision camera is turned on to view the same subject frame in low light conditions.
A night vision camera includes an image intensifier to amplify the image by several orders with little distortion. Typically, in the image intensifier, the incident low light (lower than 500 μlux) flux is first converted to electron current in a photoconductive layer. This current is further amplified by 104 to 105 times using an appropriate current amplifier. On the back of the current amplifier, a phosphor layer is deposited which emits greenish light in response to the current incident. As the current amplifier amplifies the incident light faithfully, the emitted greenish light will be a replica of the incident low light image. This greenish light may be focused into the object piece of a Black and White (B/W) CCD camera to obtain the final night vision video. Generally, the current intensifier has an upper limit on the total amount of charge it can deliver in its lifetime after which the gain dramatically drops. Therefore, the regions that are exposed to high intensity light quickly lose their ability to provide high gain, leading to noise, black spots, and graininess in the video over continued operation of the camera.
In real world situations, such as in hot pursuit of a suspect in an otherwise low light urban setting, the above night vision camera will work adequately providing excellent video until a bright light source such as a passing car's headlights or a street light comes into view. In such a scenario, the night vision video shows distinct "blooming", i.e., whitening of a large part of the screen which blankets parts of the image that are otherwise in a low light region for the sensors. It takes a relatively long time for the current intensifier to recover from the blooming. The net loss of information during recovery of the current intensifier and/or during the switching from the night vision camera to the visible camera could be very costly under critical mission conditions. Also, the repeated exposure to blooming causes the current intensifier to degrade quickly, as explained above, much faster than the manufacturer specified lifetime of the device leading to video noise.

Imaging system with negative electron affinity photocathode


A method of printing a pattern having vertically oriented features and horizontally oriented features on a substrate utilizing dipole illumination, which includes the steps of: identifying background areas contained in the pattern; generating a vertical component mask comprising non-resolvable horizontally oriented features in the background areas; generating a horizontal component mask comprising non-resolvable vertically oriented features in the background areas; illuminating said vertical component mask utilizing an X-pole illumination; and illuminating said horizontal component mask utilizing a Y-pole illumination.

Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (for example, but not limited to a silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole array of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire reticle pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the "scanning" direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally<1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole-procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another, by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes-can be obtained, for example, from the book "Microchip Fabrication: A Practical Guide to Semiconductor Processing", Third-Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such "multiple stage" devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD's well below the available light source wavelengths. For instance the current production wavelength of 248 nm is being pushed towards patterning of CD's smaller than 100 nm. This industry trend will continue and possibly accelerate in the next 5–10 years, as described in the International Technology Roadmap for Semiconductors (ITRS 2000).
This continued demand for improved performance has resulted in the development of various techniques aimed at improving resolution. Such techniques are typically referred to as Resolution Enhancement Techniques (RET's) and comprise a very wide range of applications. Examples include: light source modifications (e.g. Off-Axis Illumination), use of special masks, which exploit light interference phenomena (e.g. Attenuated Phase Shift Masks, Alternating Phase Shift Masks, Chromeless Masks, etc.), and mask layout modifications (e.g. Optical Proximity Corrections).
Of the foregoing techniques, dipole illumination is one of the most attractive T candidates due to its high image contrast for dense pitches and superior resolution capabilities. As is known, dipole illumination is an extreme case of OAI and is capable of providing enhanced imaging contrast with improved process latitude for very low K1 imaging.
However, one of the limitations associated with dipole illumination is that a single illumination only enhances resolution for features that are orthogonal to the illumination pole axis. As a result, in order to take full advantage of dipole illumination during wafer printing, the mask pattern must be decomposed into horizontal and vertical orientations. Once the mask pattern is converted in this manner, a Y-pole exposure is utilized to image the horizontally oriented features, and a X-pole exposure is utilized to image the vertically oriented features. One important aspect of dipole illumination is that when imaging the horizontally oriented features, the vertically oriented features must be protected (i.e., shielded) so the vertically oriented features are not degraded. The opposite is true when vertically oriented features are imaged (i.e., the horizontally oriented features must be protected).
FIG. 1 illustrates the basic concepts of double dipole imaging. As stated, typically there are at least two exposures when utilizing dipole illumination. In the first exposure, the X dipole aperture 10 provides a maximum aerial image intensity (i.e., maximum modulation) for the vertical portion of the lines 12 to be printed. The resulting image profile is illustrated by line 24 in FIG. 1. In the second exposure, which utilizes the Y-dipole aperture 16, there is no image modulation for lines 12. It is noted, however, that during the second exposure using the Y-dipole aperture, the vertical portions of the lines 12 need to be shielded so that the vertical features formed during the first exposure are not degraded during the second exposure. FIG. 1 illustrates shielding the lines 12 with shields 15, each of which is 20 nm wide in the horizontal direction. As a result, when exposing the horizontal lines using the Y dipole aperture, there is substantially no imaging (i.e., modulation) of the vertical features 12. The aerial image is a DC modulation as shown by line 17 in FIG. 1, which corresponds to the 20 nm shielding. The final aerial image intensity, which is represented by line 14 in FIG. 1, corresponds to the sum of the first exposure using the X dipole aperture and the second exposure using the Y dipole aperture.
It is further noted that, assuming the exposure energy is constant, increasing the width of the shielding from a 20 nm shield 15 to a 40 nm shield 20 for the vertical lines 12 causes the minimal intensity level of the resulting image to shift to a lower level. This, is represented by line 22 in FIG. 1, which rep resents the aerial image associated with the vertical portions of the features. As shown, the aerial image 22 is just a DC modulation. However, it is lower than the DC modulation 17 associated with the 20 nm shield. As a result, the composite image 19 formed utilizing the 40 nm shielding provides better imaging results than the composite image 14 formed utilizing the 20 nm shielding.
As a result of the need to separate the horizontally and vertically oriented features, one of the challenges for the lithographer, when utilizing dipole illumination, is determining how to convert the original IC design data into its horizontal or vertical pattern components and generate two masks for the dual exposure process that can take full advantage of the dipole imaging performance. One factor that reduces performance and which should be considered when generating the mask patterns is background light due to lens flare or scattering. As: is known, lens flare results in unwanted background light (i.e., noise) that degrades the image contrast at the image plane. Thus, it is desirable to reduce "flare" as much as possible. This is especially true when utilizing dipole illumination techniques due to the multiple exposures associated therewith.
The "aerial image with flare" is equal to the "aerial image without flare" convolved with a point-spread function (PSF) plus the scattering. The foregoing can be expressed as:Iflare(x, y)=Inoflare{circle around (×)}PSFflare+Inoflare(I−TIS)  (1)                where TIS is the total integrated scattering (TIS) for lens having a surface roughness with a Gaussian like distribution. Under such conditions, TIS can be expressed as:TIS=[(4πσ cosθ)/λ]2  (2)        where λ is the wavelength of the exposure tool, σ is the rms roughness of the lens, and θ is the scattering angle. As a result of current lens making capabilities, which result in lens exhibiting extremely low surface roughness, the foregoing equation can be approximated as:TIS˜1/λ2  (3)
Equation (3) makes clear that as the wavelength of the exposure tool is reduced, the amount of scattered light increases significantly. For example, the total integrated scattering (TIS) of light for an exposure tool having a wavelength of 193 nm is approximately 1.65 times greater that the TIS associated with an exposure tool having a wavelength of 248 nm.
It is noted that the first term is equation (1) is the "diffuse halo" which causes the focused image to spread out. The second term in equation (1) is the contribution due to scattering. The overall effect is an unwanted DC background light that reduces the aerial image contrast. Furthermore, besides the negative impact on image contrast, flare is also unevenly distributed across the scanning slit and is not uniform with the exposure field, which can cause intrafield CD variations. Therefore, protecting features and reducing background stray light becomes increasingly critical. The issue of how to reduce or negate the effects of background stray light becomes even more important as the wavelengths of the exposure tools are reduced.
Currently, one known technique for reducing the negative effects of flare comprises the step of adding solid chrome shielding on the large areas of the mask pattern (i.e., background portions) that do not contain any geometry (i.e., features). As shown in FIGS. 2a and 2b, when utilizing dipole illumination, the solid chrome shielding, referred to as background light shielding (BLS), is applied to the background areas in both the horizontal mask and the vertical mask. The solid chrome shield functions to protect the background, area during both exposures. FIG. 2a illustrates an example of the use of this shielding technique in conjunction with the printing 6f horizontally oriented features 29 utilizing the Y dipole 16. As-shown in FIG. 2a, each of the vertical features 27 are provided with shielding 210 (i.e., main feature shielding) in the manner discussed above in conjunction with FIG. 1. In addition, the solid chrome shield 220 is provided in the background area where there are no features to be imaged on the wafer. In a similar manner, FIG. 2b illustrates the vertical mask, in which the horizontal oriented features are shielded, while the vertical features are printed. As shown, the vertical mask also includes a solid chrome shield 220 disposed in the background area. It is further noted that both the horizontal mask and the vertical mask contain assist features 103 (e.g., scatter bars).
However, as a result of such background shielding 220, when utilizing a positive resist, the intensity in the background areas becomes too low to completely clear the resist. FIGS. 3a and 3b illustrate a simulated resist pattern corresponding to the portion of the masks of FIGS. 2a and 2b defined by area 30, which includes the solid chrome shielding 220. The simulation was performed assuming NA(numerical aperture)=0.75, ArF double exposure x-pole, y-pole, σouter/(σinner=0.89/0.65. As is shown by FIGS. 3a and 3b, portions of the resist 221 in the background areas remain after illumination using the vertical and horizontal masks. As a result, a third exposure utilizing a trim mask is necessary in order to completely remove the resist from the background shielded areas. Thus, such a solution for reducing the effects of flare is undesirable as it results in an increase in the number of exposures and masks required for imaging the wafer. Referring to FIG. 3a, the areas indicated by reference numeral 51 correspond to the areas where resist remains after the double exposures, and these areas are contrasted against areas of either the vertical or horizontal mask that had chrome disposed thereon (i.e., either feature or shielding).
Furthermore, the foregoing solid chrome shielding technique can also negatively interfere with assist features, such as scatter bars, and cause the assist features to print underneath the shielding of either the horizontal or vertical mask, as-also illustrated in FIGS. 3a and 3b. For example, referring to FIG. 3b, as shown in the resist simulation, the assist features 103, which are intended to be sub-resolution, are printed as a result of the BLS 220. This problem imposes an additional constraint on the placement of assist features, which can prevent the assist features from being placed in the optimal position, thereby causing a reduction in printing performance.
Accordingly, there exists a need for a method for negating the effects of flare in the exposure process which does not result in an increase in the number of exposures and masks required for imaging the wafer, and which does not impact the use and/or placement of assist features in the mask.

Orientation dependent shielding for use with dipole illumination techniques


An ion implanting apparatus is provided, which prevents a failure of the processing object caused by a scattering of the deposited particles of the ion species on an inner surface of a through hole of a member that forms a beam geometry of an ion beam. Since at least an inner surface of the through hole 222 of the member 220 having a through hole and being capable of forming a beam geometry is coated with a thermal spraying film, unwanted deposition of the ion species on the inner surface of the through hole 222 is inhibited. Moreover, since a deposition film generated on the surface of the thermal spraying film has an unoriented poly-crystalline structure that exhibits extremely higher inter-layer adhesiveness, a failure of the processing object caused by a scattering of the particles peeled-off from the deposition layer is prevented.

1. Technical Field
The present invention relates to an ion implanting apparatus that is capable of irradiating an ion beam over a semiconductor wafer to implant ion species, and in particular, relates to an ion implanting apparatus that is capable of forming a beam geometry by passing an ion beam through a through hole of a member.
2. Related Art
Currently, an ion implanting apparatus is utilized for implanting ion species into a semiconductor wafer. Such ion implanting apparatus is described as follows in reference to FIG. 10 and FIG. 11. An ion implanting apparatus 100 shown here includes a main part that comprises an ion gun 110, an aperture member 120, a wafer holding unit 130 or the like, which are linearly arranged.
The ion gun 110 produces ion species supplied from an ion source (not shown) to create an ion beam. The aperture member 120 is formed by, for example, machining carbon graphite, and is provided with a slit-shaped through hole 122 formed in a flat member body 121.
The wafer holding unit 130 includes a rotation stage 131 and a slide mechanism (not shown), and the rotation stage 131 holds a plurality of silicon wafers 140 that are to be processed. The rotation stage 131 revolves a plurality of silicon wafers 140 that are held thereon, and the slide mechanism reciprocates the rotation stage 131 along a vertical direction.
In the ion implanting apparatus 100 having the above-described configuration, an ion beam emitted by the ion gun 110 passes through the through hole 122 of the aperture member 120, so that a beam is shaped to have the corresponding geometry.
A plurality of silicon wafers 140 that are revolved and vertically reciprocated by the wafer holding unit 130 are consecutively exposed over the ion beam having such beam geometry, so that the ion species is equivalently injected over the entire surfaces of a plurality of silicon wafers 140.
The aperture member 120 as described above may alternatively be referred to as, for example, a resolving aperture, a beam aperture, a slit member or the like, and, regardless of the name of the member, the member is composed of a flat member provided with a slit-shaped through hole 122 formed therein, as shown in FIG. 11.
Currently, various proposals for ion implanting apparatuses as described above are made (see, for example, Japanese Patent Laid-Open No. H10-25,178 (1998), Japanese Patent Laid-Open No. H11-149,898 (1999) and Japanese Patent Laid-Open No. H11-283,552 (1999)).
Further, an ion implanting apparatus is also proposed which is configured such that at least a surface of various members located in paths for an ion beam is formed of high purity silicon (not shown). In this ion implanting apparatus, even if particles of contaminants are generated from the members in the paths for the ion beam, the particle is necessarily composed of high purity silicon, and, therefore, a contamination of a silicon wafer can be prevented.
In addition to above, it is disclosed in the related art documents that the above-described high purity silicon may be composed of amorphous silicon deposited on the member surface by a chemical vapor deposition (CVD) process, amorphous silicon deposited by a sputter process, a silicon grown by an epitaxy process or the like (see, for example, Japanese Patent Laid-Open No. H03-269,940 (1991).
Since a gas of ion species is constantly generated in a periphery of an ion beam in the ion implanting apparatus 100 as described above, the ion species is deposited to form a thin film on an inner surface of the through hole 122 of the aperture member 120, as shown in FIG. 12, during the long term operation.
Then, the thin film deposited on the inner surface of the through hole 122 of the aperture member 120 may be peeled off by exposing thereof with the ion beam, and may be eventually scattered to a silicon wafer 140 as a contaminant, as shown in FIG. 13.
In this case, the above-described contaminant may adhere onto a surface of the silicon wafer 140, or may generate damage in the surface of the silicon wafer 140 by a collision of the contaminant, eventually necessitating the disposal of the silicon wafer 140.
For example, a high-current ion implanting apparatus (not shown) or the like utilizes a batch system that retains a large number (e.g., 13 pieces) of silicon wafers 140 therein, and therefore, once a failure is generated as described above, a large number of silicon wafers 140 should be disposed at the same time.
In addition to above, while contaminants generated from the member are composed of silicon in the case of employing the ion implanting apparatus described in the aforementioned Japanese Patent Laid-Open No. H03-269,940, when the contaminants collide with a surface of a silicon wafer, damages may be generated therein. Even if no damage is generated, the presence of contaminants of silicon adhered onto the surface of the silicon wafer may cause a failure in the later semiconductor process.

Ion implanting apparatus for forming ion beam geometry


A liquid crystal display device including a liquid crystal panel being capable of gradation display is provided with a LUT and a drive signal generation section for adjusting gradation curve's distortion with respect to a viewing angle, which indicates a relation between a gradation and a luminance ratio on a display screen of the liquid crystal panel. With this arrangement, it is possible to freely switch on the display screen of the liquid crystal panel between a wide viewing angle display and a narrow viewing angle display. Therefore, it is possible to provide a liquid crystal display device which adjusts the gradation curve's distortion with respect to the viewing angle on the display screen to obtain a high contrast and an excellent gradation curve in a wide range of viewing angle, thereby improving a display quality level of a display screen; and which realizes a display screen with a narrow viewing angle, thereby allowing information not desired to be seen by other people to be securely displayed thereon.

Generally, an active matrix type liquid crystal display device has a structure of a pair of glass substrates opposed and fixed which between a liquid crystal is filled in a space. More specifically, transparent common electrodes are provided on one glass substrate, a large number of transparent pixel electrodes are provided in a matrix manner on the other glass substrate, and a circuit for individualistically applying voltages to the pixel electrodes.
The liquid crystal display device performs display operation with sandwiched polarizing plates in the foregoing structure, so that it has a characteristic of a narrow viewing angle.
To increase a viewing angle, have been proposed liquid crystal display devices utilizing IPS (In Plane Switching), MVA (Multi domain Vertical Aline), or ASV (Advance Super View) mode as a physical technique such as divided orientation.
Here, the following will explain a typical technique for increasing a viewing angle.
First, referring to FIG. 27, TN (Twisted Nematic) mode will be explained as follows. In FIG. 27, bold and black lines represent crystal elements.
FIG. 27 shows the movement of the liquid crystal elements in the TN mode. When no voltage is applied (voltage is OFF), the liquid crystal elements are oriented as shown on the left in the drawing. As a voltage is applied, the liquid crystal elements are caused to stand as shown in the middle of the drawing. When a maximum voltage is applied, the liquid crystal elements are oriented as shown on the right in the drawing. Each gradation level is expressed by change in applied voltages.
In the foregoing TN mode, the liquid crystal elements are oriented obliquely and a viewing angle characteristic occurs depending on the oriented direction. Here, the occurrence of the viewing angle characteristic means the state in which display image cannot appear normally depending on the angle at which a display screen is viewed.
Such a viewing angle characteristic occurs because the liquid crystal elements have a bar shape and a polarization characteristic. More specifically, when a voltage is applied, the liquid crystal elements, each of which has the same characteristic, move in the same direction. This causes the viewing angle characteristic with respect to the leaning angles of the liquid crystal elements.
Conventionally, to reduce the effects by the polarization characteristic of the liquid crystal, an orientation dividing method is adopted as shown in FIGS. 28(a) and 28(b). Unlike the usual orientation, the method reduces the polarization characteristic by dividing the orientation of pixels in the different orientation directions so as to disperse the orientation directions of the liquid crystal.
This orientation dividing method does not cause the viewing angle characteristic of the liquid crystal elements in the TN mode, so that it is possible to realize the increased viewing angle.
Secondly, referring to FIGS. 29(a) and 29(b), the IPS (In Plane Switching) mode will be explained as follows.
In the IPS mode, as shown in FIG. 29(a), the longitudinal direction of the liquid crystal elements is in parallel to the panel plane, so that although the IPS mode has a low dependency on a physical viewing angle, it has a wavelength dependency on light that transmits the liquid crystal element, and the amount of this wavelength dependency causes change in the viewing angle. Also, human eyes have a wavelength characteristic, so that the wavelength dependency changes in luminance on the display screen. This causes the problem of a narrow viewing angle.
Conventionally, to realize an increased viewing angle, proposed has been a method of dividing the orientation in zigzag so as to cancel the wavelength dependency (super IPS).
Note that, the IPS mode has two major disadvantages:
(1) Response speed is low; and
(2) Transmittance is extremely poor.
Next, referring to FIG. 30, the VA (Vertical Alignment) mode will be explained as follows.
In the VA mode, as shown in FIG. 30, when no voltage is applied (OFF), the longitudinal direction of the liquid crystal elements is vertical to the panel plane. When a voltage is applied (ON), the longitudinal direction of the liquid crystal elements is horizontal to the panel plane. Therefore, viewing angle characteristic improves when a voltage is ON and OFF. Incidentally, in a halftone at which a mediate voltage is applied, the liquid crystal elements are oriented obliquely in one direction, which causes the viewing angle characteristic. The viewing angle characteristic in this case is in the same level as that of the TN mode.
Thus, in the VA mode, the viewing angle characteristic occurs in the halftone, which results in the problem of the narrow viewing angle.
Note that, as compared with the IPS mode, the VA mode has the following characteristics:
(1) Response speed is high;
(2) Contrast can be gained because black level is high in quality; and
(3) Transmittance is better than that of the IPS mode, although it is worse than that of the TN mode.
To improve the viewing angle characteristic of the halftone in the VA mode, the following MVA (Multi-domain VA) mode has been proposed.
Next, referring to FIGS. 31(a) and 31(b), the MVA mode will be explained as follows.
The MVA mode is the mode in which the VA mode is subjected to orientation division. Such an orientation division can improve the viewing angle characteristic of the halftone.
More specifically, as shown in FIG. 31(a), an object having a structure of a substantially triangular shape on cross section is applied onto the panel plane, and oriented films are further formed thereon. Therefore, as shown in FIG. 31(b), because of the foregoing object on the panel plane, the liquid crystal elements lean along the object when a voltage is applied, which produces the effects of divided orientation in the halftone. In such a manner, an increased viewing angle is realized in the VA mode.
Note that, the VA mode can improve the viewing angle characteristic by the divided orientation as described above; however, it does not improve so much as the IPS mode.
Furthermore, unlike the foregoing physical method such as the divided orientation, Japanese Laid-Open Patent Publication No. 121144/1995 (Tokukaihei 7-121144; published on May 12, 1995) (a Japanese equivalent to the U.S. Pat. No. 5,847,688) proposes a liquid crystal display device in which a viewing angle is electrically increased, utilizing a plurality of different gamma characteristics based on an input image signal.
Incidentally, the width of the viewing angle in the liquid crystal display device is defined by the width of the area where a contrast ratio of white to black is not less than a predetermined value. Note that, a gradation curve is also an important element for the accurate reproduction of images. Since the gradation curve does not significantly change depending on the viewing angle in display devices, except for a liquid crystal display device, such as a cathode-ray tube monitor and a plasma monitor, the definition of the width of the viewing angle is usually considered to be no problem.
However, the gradation curve is an important element for the reproduction of images. For example, in a display device of 256 gradation levels, the gradation curve when viewed from the front has:
a luminance ratio=(n/255)2.2, and
the gradation curve when viewed from the side has:
a luminance ratio=(n/255)1.0, where "n" is a gradation.
At this moment, in case of the display of a gray color with gradation level 128, the gradation level 128 is displayed when viewed from the front. On the other hand, a gray color with gradation level 186 is displayed when viewed from the side, and a whitish display is made as compared with when viewed from the front.
Further, in case where the gradations of R, G, B are different, the difference in gradation display is remarkable. For example, when R is at gradation level 0, G is at gradation level 128, and B is at gradation level 255, the luminance ratio of the front is R:G:B=0:0.22:1. On the other hand, the luminance ratio of the side is R:G:B=0:0.50:1, which indicates the change into a strongly green-tinged display.
As described above, even the same original data is changed into different image depending on the change in the gradation curve.
Therefore, in view of a contrast ratio, the liquid crystal display devices utilizing the wide viewing angle modes such as ISP, MVA, and ASV modes realize a wide viewing angle. However, the gradation curve is different when viewed from the side. This means a lack of image reproduction when viewed from the side.
Thus, the difference in the gradation curve between when viewed from the front and from the side is referred to as distortion of gradation curve.
Further, the liquid crystal display device disclosed in the foregoing publication increases the viewing angle by improving the viewing angle characteristic when viewed from the side, using gamma characteristic, so that the gradation curve when viewed from the front distorts. Especially, in case where the viewing angle characteristics at the both sides sandwiching the front deviates in the same direction as that of the target gamma characteristic, it is necessary to largely change the gradation curve when viewed from the front.
This means to bring about the deterioration of the image reproduction when viewed from the front.
As described above, in all of the conventional liquid crystal display devices realizing an increased viewing angle, the gradation curve when viewed from the front is different from that when viewed from the side, in other words, the gradation curve's distortion with respect to the viewing angle occurs in the display image, so that image when viewed from the front is different from that when viewed from the side. As a result, it is impossible to obtain an excellent quality of image in a wide range of viewing angle, which causes the problem of the deterioration in a display quality level.
Further, the conventional liquid crystal display device has a constant range of viewing angle, it is necessary to replace the display deice itself when change in the range of viewing angle is desired as in the case when information desired to be shown to other people is arranged so as to be shown to many other people and the case when information not desired to be shown to other people is arranged so as not to be shown.


A closure for a beverage bottle includes a plug element having a disk shaped head portion and a hollow cylindrical portion which seals with the inner surface of the opening of the bottle. An annular projection is formed around the circumference of the bottle 12 near its mouth. The closure further includes a cap element which fits over the plug element and which includes with a skirt having an annular recess which locks onto the annular projection of the bottle. A first precut line is provided in the cap, extending around its circumference and a second precut line portion extends from the distal edge of the skirt to the first precut line across the annular recess. The cap may be disengaged from the bottle by cutting through the second precut line and the first precut line.

The present invention relates to a cap/plug closure for sealably closing the opening of a bottle.
When a bottle containing a beverage "carbonated" with carbon dioxide gas or other dissolved gas has its temperature raised or when it is moved about in a user's hand, the internal pressure within the bottle may be elevated, causing a plug closing the mouth of the bottle to become disengaged with the result that the carbon dioxide or other gas dissolved in the beverage escapes. To prevent such an accident, an external annular protrusion (hereinafter "rib") is formed at a position in the vicinity of the mouth of the bottle, e.g. a bottle for a champagne or the like, and a wire is wrapped around the neck of the bottle below the rib and around the plug to retain the plug within the bottle.
In the case of a wine, a portion of the bottle, including the mouth sealed with a plug and a part of the neck, is covered with a metallic cap.
The above type seal presents the danger that a user's finger may be injured by the wire when the latter is disengaged from the bottle. In addition, in packaging, since the placing of the wire on the neck of the bottle is by hand, assembly is time-consuming and expensive.
With a bottle having its mouth and plug covered with a metallic cap, there is the danger that a user's finger may be injured by the metallic cap when the latter is disengaged or removed from the bottle. Additionally, since the mouth of the bottle is closed with a metallic cap, the cost of the bottle is increased and, moreover, the metallic cap represents a waste injurious to the environment.

Bottle and closure with separable cap and plug elements


A method for the production of a robust, chemically stable, crystalline, passivated nanoparticle and composition containing the same, that emit light with high efficiencies and size-tunable and excitation energy tunable color. The methods include the thermal degradation of a precursor molecule in the presence of a capping agent at high temperature and elevated pressure. A particular composition prepared by the methods is a passivated silicon nanoparticle composition displaying discrete optical transitions.

1. Field of the Invention
The present invention relates to the field of nanotechnology. In particular, to compositions and methods of making Group IV metal nanoparticles and their applications.
2. Description of the Relevant Art
The term "nanoparticle" generally refers to particles that have an average diameter between about 1 nm to 100 nm. Nanoparticles have an intermediate size between individual atoms and macroscopic bulk solids. Nanoparticles typically have a size on the order of the Bohr exciton radius, or the de Broglie wavelength, of the material, which allows individual nanoparticles to trap individual or discrete numbers of charge carriers, either electrons or holes, or excitons, within the particle. The spatial confinement of electrons (or holes) by nanoparticles is believed to alter the physical, optical, electronic, catalytic, optoelectronic and magnetic properties of the material. The alteration of the physical properties of a nanoparticle due to confinement of electrons is generally referred to as quantum confinement effects.
Nanoparticles may exhibit a number of unique electronic, magnetic, catalytic, physical, optoelectronic and optical properties due to quantum confinement effects. For example, many nanoparticles exhibit photoluminescence effects that are significantly greater than the photoluminescence effects of macroscopic molecules having the same composition. Additionally, these quantum confinement effects may vary as the size of the nanoparticle is varied. For example, size-dependent discrete optical and electronic transitions exist for clusters of Group II-VI semiconductors (e.g., CdSe) or Group III-V semiconductors (e.g., InAs).
This loss of energy level degeneracy, however, has not previously been observed in the optical properties of Group IV nanoparticles (e.g., silicon (Si) nanocrystals). In Si, for example, the lowest lying energetic transition violates conservation of momentum; therefore, light absorption requires phonon assistance (a phonon is a quanta of vibrational energy), resulting in a very low transition probability. Consequently, bulk Si photoluminescence is very weak. Quantum confinement in Si nanocrystals and porous Si, however, leads to enhanced luminescence efficiencies with quantum yields that have reached as high as 5% at room temperature and blue-shifted "band gap" energies. However, in sharp contrast to their direct band gap semiconductor counterparts, Si nanocrystals have not displayed discrete electronic transitions in the absorbance and photoluminescence excitation (PLE) spectra.
The wet chemical techniques used to synthesize Group II-VI and III-V semiconductors have not been readily applied to Group IV materials, largely due to the high temperatures required to degrade the necessary precursors. Typically the temperature required to degrade the necessary Group IV precursors exceeds the boiling points of typical solvents. Furthermore, the strong covalent bonding of Si requires temperatures higher than the Group II-VI materials to achieve highly crystalline cores. Moderate progress has been made with alternative solution-phase reduction of Si salts and aerosol methods. These methods, however, have produced nanocrystals with extremely broad size distributions. Aerosol methods have required a thick oxide coating to stabilize their structure, which has been shown recently to significantly affect the photoluminescence (PL) energies of porous Si.

Light-emitting nanoparticles comprising octanol as a passivating agent, and method of making same


The present disclosure provides a method and system for performing fault diagnosis by bearing noise detection. The method provides: collecting noise in bearing detection, the noise comprising bearing noise and operating condition noise; subjecting the collected noise to pre-processing, to obtain a first time domain signal and a second frequency domain signal; and inputting the first time domain signal and second frequency domain signal to a bearing fault diagnosis model. The bearing fault diagnosis model includes a characteristic extraction model and a fault discrimination model, the characteristic extraction model subjects the first time domain signal and second frequency domain signal to characteristic extraction separately to obtain a first characteristic associated with a time domain shock peak and a second characteristic associated with a fault frequency peak. Moreover, the fault discrimination model combines the first characteristic and second characteristic, and performs fault discrimination on the basis of a combined characteristic.

Bearing noise is a key parameter in bearing quality control; certain early-stage bearing defects can be detected by bearing noise detection in the production line. However, there is a strong correlation between noise and bearing type; for example, different bearing types exhibit differences in bearing dimensions, material and grease, etc., and noise varies because of this. Thus, a trained detection model for a particular type of bearing cannot be used for other new types of bearing directly.
Another problem with typical bearing noise detection models is that detection is completely dependent on certain key parameters of the bearing, such as fault frequency (BPFI, BPFO, etc.) and relatively stable and accurate rotation speed information. However, in some cases, information of these parameters is very difficult to collect, e.g. information relating to bearing type is lacking or bearing speed information is lacking.
Existing bearing detection algorithms need to collect a large amount of bearing data relating to bearing information in order to retrain a model for a new type of bearing. This not only wastes time and costs, but also cannot support rapid expansion in an ever increasing number of new applications. In addition, in cases where bearing type and speed information is absent, specialized personnel need to perform diagnosis manually, or diagnosis needs to be performed with very simple diagnosis logic (e.g. RMS threshold or trend); thus, detection efficiency and detection precision are relatively low.
Thus, there is a need to develop a universal method and system which are capable of performing fault determination by automatic bearing noise detection without the need for bearing information, so as to increase the efficiency of bearing noise detection by increasing the generalization capability of an automatic detection model for bearing noise.

Method and system for performing fault diagnosis by bearing noise detection


An air delivery system may include a housing, a first liquid-to-air membrane energy exchanger (LAMEE), and a desiccant storage tank. The housing includes a supply air channel and an exhaust air channel. The first LAMEE may be an exhaust LAMEE disposed within an exhaust air channel of the housing. The exhaust LAMEE is configured to receive the outside air during a desiccant regeneration mode in order to regenerate desiccant within the exhaust LAMEE. The desiccant storage tank is in communication with the exhaust LAMEE. The exhaust LAMEE is configured to store regenerated desiccant within the desiccant storage tank. The regenerated desiccant within the desiccant storage tank is configured to be tapped during a normal operation mode.

Embodiments of the present disclosure generally relate to air delivery systems, such as HVAC, air handling, heat pump, and energy exchange systems, and, more particularly, to control systems and methods for air delivery systems.
Enclosed structures, such as occupied buildings, factories and the like, generally include a heating/ventilation/air conditioning (HVAC) system for conditioning outdoor ventilated and/or recirculated air. The HVAC system typically includes a supply air flow path and an exhaust air flow path. The supply air flow path receives pre-conditioned air, for example outside air or outside air mixed with re-circulated air, or air from another source, and channels and distributes the pre-conditioned air into the enclosed structure. The pre-conditioned air is conditioned by the HVAC system to provide a desired temperature and humidity of supply air discharged into the enclosed structure. The exhaust air flow path discharges air back to the environment outside the structure. Without energy recovery, conditioning the supply air typically requires a significant amount of auxiliary energy, particularly in environments having extreme outside air conditions that are much different than the required supply air temperature and humidity. Accordingly, energy exchange or recovery systems are used to recover energy from the exhaust air flow path.
Conventional energy exchange systems may utilize energy recovery devices (for example, energy wheels and permeable plate exchangers) or heat exchange devices (for example, heat wheels, plate exchangers, heat-pipe exchangers and run-around heat exchangers) positioned in both the supply air flow path and the exhaust air flow path. Liquid-to-air membrane energy exchangers (LAMEEs) may be fluidly coupled so that a desiccant liquid flows between the LAMEEs in a run-around loop, similar to run-around heat exchangers that typically use aqueous glycol as a coupling fluid.
A liquid desiccant system is generally a direct contact system, in which the liquid desiccant removes moisture from the air it contacts. The temperature and humidity of the supply air that contacts the liquid desiccant may be modified by manipulating the temperature and concentration of the liquid desiccant. However, known desiccant-based HVAC energy exchange systems lack processes for conditioning the liquid desiccant to maintain supply air conditions.

Control system and method for a liquid desiccant air delivery system


The present disclosure is related to a light emitting diode. The light emitting diode may include a pixel unit which may include a first sub-pixel. The first sub-pixel may include a dummy electrode layer and a first electrode layer on the dummy electrode layer. The dummy electrode layer may include a first reflective layer. The first electrode layer may include a second reflective layer and a second transparent conductive layer on the second reflective layer.

As compared to other display apparatuses such as liquid crystal display (LCD) apparatuses, the organic light emitting diode (OLED) display apparatuses are self-emitting apparatuses that do not require a backlight. Having advantages such as fast response, wide viewing angle, high brightness, more vivid color rendering, thinner and lighter, the organic light emitting diode (OLED) display apparatuses have found a wide range of applications in display field.

Light emitting diode with microcavities and different reflective layers and fabricating method thereof, display substrate, and display apparatus

BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.


Variable backspace in electrode assemblies for high pressure sodium lamps is achieved by employing a hollow electrode base which has one end formed to frictionally engage an electrode, which electrode includes a solid core having a coil about one end thereof. The solid core is inserted into the electrode base a given distance and is maintained in this position by friction until welding is accomplished. The electrode base is provided with a positioning ring which is formed at the time the base is first formed. The electrode assemblies can be utilized with lamps having different arc lengths while using arc tubes having the same size.

In high pressure sodium (HPS) lamps, the arc tube is made from monocrystalline alumina (sapphire) or polycrystalline alumina (PCA). Gas-tight ceramic-to-metal seals between the discharge tube and a pair of niobium current inleads, which have tungsten cathodes affixed thereto, close the ends of the discharge tube. Niobium (which may include an addition of about 1% zirconium) is used as the inlead material because its coefficient of thermal expansion closely matches that of the alumina arc tube. Further, niobium is resistant to sodium at high temperatures and has a relatively high permeability for hydrogen, allowing hydrogen impurities in the arc tube to escape therefrom and to be sorbed by a getter in the outer bulb which surrounds the arc tube. The niobium current inlead can take the form of a wire (U.S. Pat. No. 4,538,091) or a tube (U.S. Pat. Nos. 4,559,473; 5,026,311; 5,424,608) on which the tungsten electrodes are fixed, usually by crimping and/or welding or by brazing, usually with titanium.
A critical feature of HIPS lamps is the arc length, defined as the interior distance between electrode tips within the arc tube. In order to control the position of electrodes inside an arc tube, a positioning feature is provided on the niobium inleads. This positioning feature can be welded fine wires on the inlead, such as are shown on the above-mentioned U.S. Pat. No. 5,026,311; wire clips attached frictionally, such as shown in U.S. Pat. No. 4,538,091; deformations formed on the inlead, such as shown in U.S. Pat. Nos. 4,559,473 and 4,937,494; or specially shaped, cooperative apertures formed in the end seals of the arc tubes such as shown in U.S. Pat. No. 5,424,608. The location of the positioning feature is important in determining the backspace, the backspace being the distance between the upper or lamp side surface of the positioning feature and the top of the cathode coil. This spacing determines the arc length. Whatever feature has been employed in the past, if the inlead is to be useable on multiple lamp types, it has been necessary that it be formed at a different position on the inlead. This operation can increase the cost of manufacturing lamps and can lead to errors in electrode selection.

Method of making cathode assembly for high pressure sodium lamps


A method of preoperatively selecting an intraocular lens to be implanted into an eye to postoperatively render the eye emmetropic or ametropic with a desired postoperative refraction comprises determining the location of the lens haptic plane of the eye, the corneal power of the eye and the axial length of the eye, choosing the desired postoperative refraction and assuming a lens to be implanted, the lens having a known power and geometry, including an offset between the lens haptic plane and an anterior vertex of the lens as if it was in its implanted state. With these parameters and refractive indices of the ocular fluids, a calculation is made to determine whether or not, postoperatively, focus will fall on the retina of the eye. If, from the calculation, it is determined that focus will not fall on the retina of the eye, another lens with a different power and/or geometry is assumed to be implanted and the calculation is repeated until the focus is calculated to fall on the retina of the eye. A lens of the nearest power available for which focusing on the retina was calculated is then selected for implantation.

To obtain a desired postoperative refractive outcome of an intraocular lens implantation--emmetropia or ametropia--, there are several methods in use to determine which dioptric power the intraocular lens to be implanted, should have. The correct implant power to choose depends on the axial distance from the cornea, at which the intraocular lens (IOL) will end up in the eye.
With the present techniques, the axial position of the IOL can only be estimated.
Two major schools exist today for estimating the axial position of the IOL.
One school describes the optics of the eye in terms of thin lens theory.
In this connection reference is hereby made to:
1) Fedorov S N, Kolinko A L. Estimation of optical power of the intraocular lens. Vestn. Oftamol 1967;80(4):27-31, PA0 2) Colenbrander M C. Calculation of the power of an iris clip lens for distant vision. Br J Ophthalmol 1973;57:735-740, PA0 3) Hoffer K J. Mathematics and computers in intraocular lens calculation. Am Intra-Ocular Implant Soc J 1975;1(1):4-5, PA0 4) van der Heijde G L. A nomogram for calculating the power of the prepupillary lens in the aphakic eye. Bibliotheca Ophthalmol 1975;83:273-275, PA0 5) Thijssen J M. The emmetropic and the iseikonic implant lens: computer calculation of the refractive power and its accuracy. Ophthalmologica 1975;171:467-486, PA0 6) Binkhorst R D. The optical design of intraocular lens implants. Ophthalmic Surg 1975;6(3):17-31, and PA0 7) Holladay J T, Prager T C, Chandler T Y, et al. A three-part system for refining intraocular lens power calculations. J Cataract Refract Surg 1988;14:17-24. PA0 8) Sanders D R, Retzlaff J, Kraff M, et al.: Comparison of the accuracy of the Binkhorst, Colenbrander, and SRK.TM. implant power prediction formulas. Am Intra-Ocular Implant Soc J 1981; 7:337-340, PA0 9) Sanders D R, Retzlaff J, Kraff M C. Comparison of the SRKII.TM. formula and other second generation formulas. J. Cataract Refract Surg 1988;14:136-141, and PA0 10) Sanders D R, Retzlaff J, Kraff M C, Gimbel H V, Raanan M G. Comparison of the SRK/T formula and other theoretical and regression formulas. J Cataract Refract Surg 1990; 16:341-346. PA0 11) Olsen T. Theoretical approach to intraocular lens calculation using Gaussian optics. J Cataract Refract Surg 1987; 13:141-145, PA0 12) Haigis W. Strahldurchrechnung in Gausscher Optic zur Beschreibung des Linsen-Systems Brille-Kontaktlinse-Hornhaut-Augenlinse (IOL), in: Schott K, Jacobi K W, Freyler H (Hrsg): 4 Kongr. d. Deutsch. Ges. f. Intraokularlinsen Implant., Essen 1990. Berlin, Heidelberg, New York, Springer Verlag 1990, and PA0 13) Kashiwagi T. Ray tracing error correction in ophthalmic optics. J Cataract Refract Surg 1991; 17:194-198, PA0 a) determining the location of the lens haptic plane of the eye, PA0 b) determining the corneal power of the eye, PA0 c) determining the axial length of the eye, PA0 d) choosing the desired postoperative refraction, PA0 e) assuming a lens to be implanted, said lens having a known power and geometry, including the offset between the haptic plane of said lens and the anterior vertex of said lens as if it was in its implanted state, PA0 f) calculating from the parameters given by a), b), c), d) and e), as well as the refractive indices of ocular fluids, whether or not, postoperatively, focus will fall on the retina of the eye, PA0 g) if that is not the case, repeating steps d)-f) assuming another lens with a different power and/or geometry, until focusing on the retina is calculated in step f), and PA0 h) selecting for implantation, the lens of the nearest power available for which focusing on the retina is calculated in step f).
The axial position of the IOL is mostly considered to be a constant, often referred to as the ACD constant. The value of the constant depends to some extent on the IOL model. In the thin lens theory, this constant represents the postoperative distance between the principal planes of the cornea and of the IOL.
Another school applies retrospective statistical analysis of clinical data to determine a coefficient, the so called A-constant, in a linear equation, known as the SRK formula, linking corneal dioptric power K, eye length L, IOL power and postoperative refraction.
In this connection reference is made to:
The linear relationship mentioned above, is not a theoretically correct representation of the optics of the eye, but the SRK approach is most widely used because it is simple and, in clinical practice, yields results similar to the thin lens theory approach.
The SRK/T formula in the above reference 10), is a hybrid between the two approaches.
In both schools, further refinement entails corrections depending on mainly eye length.
The following references:
apply thick lens theory, which is physically more exact, but the general problem of pre-estimating the axial position of the IOL remains.
The position of the IOL optic is determined by its fixation in the eye. Fixation is mostly obtained by means of attachments to the optic, so called loops, that hold the lens in place by spring action against ocular tissue. The most common site of placement of the IOL today is inside the capsular bag. Alternative placements are in the ciliary sulcus and in the anterior chamber angle. Lenses that are fixed to the iris also exist, but fixation is then not by spring action. There are also lenses meant for capsular bag placement that do not possess loops or exert spring action, such as disc lenses, plate lenses, and capsular bag filling lenses.

Method of selecting an intraocular lens to be implanted into an eye


[Problem] In a vehicular rotating electrical machine apparatus mounted in an electric vehicle or a hybrid electric vehicle, a rotating electrical machine apparatus in which a rotating electrical machine and an inverter unit to control the rotating electrical machine are integrated is miniaturized, and its torque characteristic and efficiency are improved.

In recent years, against the background of prevention of global warming, emission reduction of CO2 has been demanded. The reduction of CO2 in an automobile means an improvement in fuel consumption performance, and as one of the solutions, the development and commercial application of an electric vehicle (EV) or a hybrid electric vehicle (HEV) has been pursued.
Especially, functions requested for a rotating electrical machine mounted in a hybrid electric vehicle include idling stop at the time of vehicle stop, energy regeneration during deceleration running, torque assist during acceleration running, and the like, and the fuel consumption performance can be improved by realizing these.
As the rotating electrical machine for this, a motor generator is transversely mounted at the outside of an engine, a belt is stretched between the motor generator and a crank shaft pulley, and bidirectional driving force transmission is performed between the motor generator and the engine.
At the time of electric operation, DC power of a battery is converted into AC power by an inverter. This AC power is supplied to the motor generator, and the motor generator is rotation driven. This rotation force is transmitted to the engine through the belt, and the engine is started. On the other hand, at the time of electric power generation, part of the driving force of the engine is transmitted to the motor generator through the belt, AC power is generated, and this AC power is converted into DC power by the inverter and is stored in the battery (see, for example, patent document 1).
Patent document 1: JP-A-2001-95103 (FIG. 1, FIG. 2)

Vehicular rotating electrical machine apparatus

Abstract: [Means for Resolution] Since an inverter unit 4 is cooled by cooling air forcibly formed by a cooling fan 28, the inverter unit 4 is efficiently cooled. Then, heat radiating fins 401a, 402a and 403a of heat sinks 401, 402 and 403 can be miniaturized, and consequently, the inverter unit 4 is miniaturized, and mountability of the inverter unit 4 to a rear bracket 19 is improved. Further, since the inverter unit 4 and a rotating electrical machine 2 are cooled by the cooling air formed by the cooling fan 28, the cooling medium of the inverter unit 4 is used also as the cooling medium (cooling air) of the rotating electrical machine 2, and a cooling structure is simplified.