System and method for high-speed and high-precision digital to analog conversion. A preferred embodiment comprises a dual-resistor ladder digital-to-analog converter with a coarse resistor ladder and a fine resistor ladder, wherein resistors in the fine resistor ladder are implemented using transistors. When the effective resistances of switches used in a switching circuit are properly matched with the resistance of the resistors, the differential non-linearity and the integral non-linearity of the digital-to-analog converter can be minimized. The use of transistors to implement switches and resistors can help to eliminate mismatches arising from different fabrication steps and materials, further improving the performance of the digital-to-analog converter.

Digital-to-analog converters (DACs) are used in a wide variety of today's electronic devices. DACs can be used in many different applications, such as control systems, positional control systems, digital audio systems, digital video systems, biotechnology sensor systems, and so forth. Depending upon the application, a DAC can be specified with many different performance characteristics, including resolution (a number of bits being converted into an analog signal), conversion speed, linearity, noise, and so forth.
An important performance measure for a precision DAC is the DAC's linearity, i.e., the accuracy of the conversion across the possible range of inputs. The DAC's linearity can be measured by its differential non-linearity (DNL) and integral non-linearity (INL). The DAC's DNL can be expressed as a difference between an expected ideal step output of the DAC and an actual step output of the DAC, while the DAC's INL is the integral of the DNL. A DAC's DNL can be dependent on factors, such as mismatches between resistances of switches and resistors in a dual-resistor ladder DAC, for example.
With reference now to FIG. 1a, there is shown a diagram illustrating a prior art block diagram of a dual-resistor ladder DAC 100. The dual-resistor ladder DAC 100 comprises two resistor ladder networks, a coarse resistor ladder 105 and a fine resistor ladder 110 that are coupled together with a first switching circuit 115. In a typical dual-resistor ladder DAC, all of the resistors in the coarse resistor ladder 105 would have substantially the same resistance and all of the resistors in the fine resistor ladder 110 would have substantially the same resistance to ensure that each voltage step across each resistor in the fine resistor ladder 110 is equally spaced while the fine resistor ladder 110 is being shunted to any resistor in the coarse resistor ladder 105. A voltage reference (VREF), provided to the coarse resistor ladder 105 is divided by the resistors in the coarse resistor ladder 105. A voltage drop across a resistor in the coarse resistor ladder 105, selected by the first switching circuit 115 as a function of the X most significant bits of the binary number being converted, is then provided to the fine resistor ladder 110, where the second switching circuit 120 selects a voltage potential in the fine resistor ladder 110 as a function of the Y remaining bits of the binary number being converted. The binary number being converted is Z bits long, wherein Z=X+Y. The chosen voltage potential in the fine resistor ladder 110, which corresponds to a specific Z bits long digital code is then the output of the dual-resistor ladder DAC 100.
With reference now to FIG. 1b, there is shown a diagram illustrating a prior art implementation of a dual-resistor ladder DAC 100. As shown in FIG. 1b, the coarse resistor ladder 105 can be implemented as a linear sequence of resistors, such as resistor 107, wherein each resistor in the coarse resistor ladder 105 has the same resistance (within manufacturing tolerances). The number of resistors in the coarse resistor ladder 105 can be dependent upon the length of the binary number being converted as well as the number of bits being provided to the first switching circuit 115. For example, if the binary number being converted is 12 bits long and six bits are provided to the first switching circuit 115, then the number of resistors in the coarse resistor ladder 105 is 26=64.
The first switching circuit 115 includes a digital decoder 117, which is capable of decoding the binary bits being provided to the first switching circuit 115 into a signal used to control the state of a plurality of switches, such as switch 118 or switch 119. For example, if six bits are provided to the first switching circuit 115, then the digital decoder 117 could produce either a logic "ON" or a logic "OFF" on 65 signal lines coupled to the 65 switches to control the state of the switches. For example, a particular combination of bit values could result in the digital decoder 117 asserting signals to close switch 118 and switch 119, while having all other switches open in the switching circuit 115, resulting in the coupling of the resistor 107 from the coarse resistor ladder 105 to the fine resistor ladder 110.
The fine resistor ladder 110 includes a linear sequence of resistors, such as resistor 112, wherein each resistor in the fine resistor ladder 110 has the same resistance. The first switching circuit 115 is capable of coupling a first terminal of a resistor in the coarse resistor ladder 105 to the beginning of the linear sequence of resistors in the fine resistor ladder 110 and a second terminal of the resistor in the coarse resistor ladder 105 to the end of the linear sequence of resistors in the fine resistor ladder 110.
The second switching circuit 120 includes a digital decoder 122, which is capable of decoding the binary bits being provided to the second switching circuit 120 into a signal used to control the "ON" or "OFF" state of a plurality of switches, such as switch 123. The binary bits provided to the second switching circuit 120 are the remaining bits from the binary number being converted. For example, if the binary number is 12 bits long and the six most significant bits are provided to the first switching circuit 115, then the second switching circuit 120 is provided with the remaining six less significant bits. The six bits provided to the digital decoder 122 could result in a signal being asserted to one of 64 signal lines coupled to the 64 switches to control the state of the switches. For example, a particular combination of bit values could result in the digital decoder 122 asserting signals to close the switch 123 (while having all other switches in the second switching circuit 120 open) to couple a node below the resistor 112 to the output of the dual-resistor ladder DAC 100.
With reference now to FIGS. 2a and 2b, there are shown diagrams illustrating configurations of a prior art dual-resistor ladder DAC 200, wherein switches in the switching circuits of the dual-resistor ladder DACs are implemented with transistors. MOS transistors, such as NMOS and PMOS transistors, are typically used to implement an integrated version of the dual-resistor ladder DAC 200. The diagram shown in FIG. 2a illustrates two MOS transistors, transistor 212 and transistor 214, out of a plurality of MOS transistors used in the first switching circuit of the dual-resistor ladder DAC 200 to couple resistors, such as resistor 205, of the coarse resistor ladder 105 to the fine resistor ladder 110. The transistor 212 and the transistor 214 couple a first terminal (shown as node 206) and a second terminal (shown as node 207) of the resistor 205 to the fine resistor ladder 110. The fine resistor ladder 110 contains a sequence of resistors "R2" 222. The diagram shown in FIG. 2b illustrates a configuration of the dual-resistor ladder DAC 200 for a different digital input code (X+1 and X+2 as opposed to X for the configuration shown in FIG. 2a, for example), wherein two MOS transistors, transistor 262 and transistor 264, couple a resistor 255 of the coarse resistor ladder 105 to the fine resistor ladder 110. The transistors 262 and 264 couple the first terminal (the node 206) and a second terminal (shown as node 257) of the resistor 255 to the fine resistor ladder 110.
A disadvantage of the dual-resistor ladder DAC 200 as shown in FIGS. 2a and 2b is that there is an error introduced by switches (transistors, such as transistor 212 and transistor 214) between the coarse resistor ladder 105 and the fine resistor ladder 110. For example, when a digital input code changes from X to X+1, a voltage step is expressible as
                              R          2                +                  2                                R                          sw              ,              on                                                            2                                R                          sw              ,              on                                      +                  64                                                                          R            2                                          (                        V                      n            +            1                          -                  V          n                    )        ,where R2 is the resistance of the resistors in the fine resistor ladder 110 and Rsw,on is the on-state resistance of the switches, and is
      2              R              sw        ,        on                        2                    R        sw              +          64                    R        2            larger than the regular voltage step in the fine resistor ladder 110, e.g., when the digital input code changes from X+1 to X+2. In order to minimize this error, the on-state resistance of the switches should be low, which would demand an undesirably large W/L ratio for the switches.
With reference now to FIGS. 3a and 3b, there are shown diagrams illustrating configurations of a prior art dual-resistor ladder DAC 300, wherein the error introduced by switches between the coarse resistor ladder 302 and the fine resistor ladder 328 can be eliminated by altering the on-state resistance of the switches. The elimination of the error introduced by the switches can be achieved by configuring the switches so that a sum of their on-state resistances is substantially equal to the resistance of a resistor in the fine resistor ladder 328. That is, the on-state resistance of the switches between the coarse resistor ladder 302 and the fine resistor ladder 328 is considered as one resistor unit in the fine resistor ladder 328. As a result, one poly resistor R2 in the fine resistor ladder 328 can be removed. Hence, there are now 63 R2 resistors in the fine resistor ladder 328, while there are 64 R2 resistors in the fine resistor ladder 110 (FIG. 2a). Therefore, as shown in FIG. 3a, a voltage potential at a node 325 corresponds to digital input code X+1 when the fine resistor ladder 328 is coupled to a node 306 and a node 307 of the coarse resistor ladder 302 (the two terminals of resistor 305), and the voltage potential at node 355 can correspond to digital code X+2 when the fine resistor ladder 328 is coupled to node 306 and node 308 (the two terminals of resistor 304) of the coarse resistor ladder 302.
The diagram shown in FIG. 3b illustrates the coupling between the coarse resistor ladder 302 and the fine resistor ladder 328 for digital input code X+2, For digital input code X+2, which is one least significant bit (LSB) greater than digital input code X+1, the fine resistor ladder 328 is switched so that it now is coupled to a node 308 and the node 306 (therefore, shunting a resistor 304) in the coarse resistor ladder 302. This can be accomplished by turning off switch 314 and turning on a switch 310 while keeping the switch 312 on. The voltage potential at a node 355 should be the output of the dual-resistor ladder DAC 300 for digital input code X+2, which is one LSB higher than the voltage potential at node 325. The difference between the voltage potentials is due to the presence of the on-state resistance from the switch 312 (resistance=2*Rsw,on=2*R2/2=R2) between the node 355 and the node 306. To ensure that the voltage drop on each resistor in the fine resistor ladder 328 is evenly spaced (to obtain good DNL performance), it is key to maintain the on-state resistance of each switch to be equal to
            R              sw        ,        on              =                  1                              k            ′                                          W            L                                          (                                          V                G                            -                              V                S                            -                              V                T                                      )                              =                        R          2                2              ,wherein VG is the gate voltage of the MOS transistor, VS is the source voltage of the MOS transistor, VT is the threshold voltage of the MOS transistor, W/L is the ratio of gate width to gate length, and k′ is a dielectric constant.
One disadvantage of the prior art shown in FIGS. 3a and 3b is that the on-state resistance of the MOS transistor, which is operating in a triode region and functioning as a switch, is a function of the source voltage, VS. Unfortunately, in the first switching circuit, the VS of the MOS transistors changes depending upon the position of the resistor in the coarse resistor ladder 302 to which the MOS transistor is coupled. For example, the VS for a MOS transistor coupled to a resistor near the top of the coarse resistor ladder 302 will be larger than the VS for a MOS transistor coupled to a resistor near the bottom of the coarse resistor ladder 302. Since VS changes for the different MOS transistors, to keep the on-state resistance of each switch equal to
                    R        2            /      2                  (                        R                      sw            ,            on                          =                              1                                          k                ′                                                          W                L                                                          (                                                      V                    G                                    -                                      V                    S                                    -                                      V                    T                                                  )                                              =                                    R              2                        2                              )        ,the size ratio (W/L) of each MOS transistor must be specifically designed so that each MOS transistor will have substantially the same effective resistance. Furthermore, if the reference voltage of the dual-resistor ladder DAC changes, the effective resistance of the MOS transistors will also change. Therefore, the MOS transistors may need to be redesigned for different customer requirements or for different applications.
Another disadvantage of the prior art shown in FIGS. 3a and 3b is that the resistors and transistors used in the DAC are created using different manufacturing processes (or steps). Therefore, the variances in manufacturing and materials can result in differences in the effective resistances of the resistors and the transistors. Variations in manufacturing, for example, due to differences in materials and temperatures, can result in differences in the resistances of the resistors and transistors as manufactured, resulting in impedance mismatches and increased non-linearity for the DAC.
With reference now to FIG. 4, there is shown a diagram illustrating a prior art implementation of a dual-resistor ladder DAC 400, wherein MOS transistors are used as switches. The dual-resistor ladder DAC 400 features a two-stage decoding/switching mechanism in both a coarse resistor ladder 405 and a fine resistor ladder 425 to help reduce complexity of digital decoding circuitry in the dual-resistor ladder DAC 400. The dual-resistor ladder DAC 400 includes the coarse resistor ladder 405 that comprises a plurality of resistor/switch banks, such as resistor/switch bank 407. The diagram shown in FIG. 4 illustrates the coarse resistor ladder 405 with four resistor/switch banks. However, depending upon the number of binary digits being converted by the coarse resistor ladder 405 as well as the size of the individual resistor/switch banks, the number of resistor/switch banks can differ.
The resistor/switch bank 407 comprises a linear sequence of resistors, such as resistor 408 and resistor 410. Coupled to the linear sequence of resistors are one of two sequences of switches implemented using MOS transistors, with the sequences of resistors made up of MOS transistors such as transistor 409 and transistor 411. A first sequence of switches, such as the sequence that includes the transistor 409, can be coupled to a first terminal of odd numbered resistors, such as resistor 408, in the linear sequence of resistors, while a second sequence of switches, such as the sequence that includes transistor 411, can be coupled to a first terminal of even numbered resistors, such as resistor 410, in the linear sequence of resistors. If the coarse resistor ladder 405 is provided with six binary digits, then an implementation of the coarse resistor ladder 405 can include four resistor/switch banks and each resistor/switch bank can include a linear sequence of 16 resistors with two sequences of eight switches each.
An interconnection bus, shown in FIG. 4 as bus 415, couples a sequence of switches in the coarse resistor ladder 405 to a second level of switches 420. There is a separate interconnection bus 415 for each of the two sequences of switches (labeled as SW1) in the coarse resistor ladder 405 to one of two second level of switches 420 (labeled as SW2). Each of the second level of switches 420 includes multiple switches, such as switch 422, again implemented using MOS transistors. As shown in FIG. 4, the second level of switches 420 includes eight switches, selected using three binary digits from the binary number being converted. The three binary digits are decoded to generate a signal that can be used to close one of the eight switches in both the left side set of switches and the right side set of switches, coupling the coarse resistor ladder 405 to either a top terminal or a bottom terminal of the fine resistor ladder 425. For example, the first sequence of sequence of switches can be coupled to the bottom terminal of the fine resistor ladder 425 while the second sequence of switches can be coupled to the top terminal of the fine resistor ladder 425.
The fine resistor ladder 425 can include a plurality of switch/resistor banks, such as switch/resistor bank 427. The number of switch/resistor banks in the fine resistor ladder 425 can depend upon the size of the individual switch/resistor banks. For example, as shown in FIG. 4, six bits are being decoded by the fine resistor ladder 425 and with each switch/resistor bank having eight resistors (such as resistor 428) and eight switches (such as switch 429). One switch/resistor bank has seven resistors and eight switches. This being due to one resistor being replaced with the on-state resistance of the two switches coupling the coarse resistor ladder 405 and the fine resistor ladder 425. With the number of binary digits being decoded by the fine resistor ladder 425 and the size of the individual switch/resistor banks, there are eight switch/resistor banks in the fine resistor ladder 425. When in operation, the eight switches in one of the eight switch/resistor banks are all turned on simultaneously, then the eight-level outputs of the chosen switch/resistor bank are provided to a bus 430 that couples all outputs from the switch/resistor banks to an output switch bank 435, which includes a plurality of switches, such as switch 437. A number of the bits provided to the fine resistor ladder 425 are used to select one of the switch/resistor banks (as shown in FIG. 4, three bits are used to select one of the eight switch/resistor banks). The remaining bits provided to the fine resistor ladder 425 are then used to select one of the outputs from the selected switch/resistor bank, becoming the output of the dual-resistor ladder DAC 400 (shown in FIG. 4 as VOUT).

Digital-to-analog converter with triode region transistors in resistor/switch network


The present invention provides a drive device having slip stoppers that can reliably prevent skewed movement of or damage to a belt.. The drive device pertaining to the present invention has a roller, a drive roller, a belt that is suspended and moves over these rollers, and slip stoppers that are mounted to the roller and prevent the belt from moving in a skewed fashion. The slip stopper comprises a base into which the roller is inserted, a first wall that is located on the edge of the base that faces the belt and that is essentially perpendicular to the inner surface of the base and a second wall that extends outward continuously from the first wall and is tilted toward the other edge of the base.

1. Field of the Invention
The present invention pertains to (i) a drive device having slip stoppers that reliably prevent skewed movement of or damage to a belt, and more particularly, to a fusing device, used in an image forming apparatus such as a printer or a copying machine using the electrophotographic method, which has slip stoppers that prevent skewed movement of the fusing belt used for the heat-pressure fusing, or (ii) a transfer device, used in an image forming apparatus such as a printer or a copying machine using the electrophotographic method, that has slip stoppers that prevent skewed movement of the transfer belt.
2. Description of the Related Art
In a drive device that drives a belt, skewed movement of the belt easily occurs due to misalignment of the drive axes that drive the belt. Skewed movement of a belt may cause various problems in the belt drive device.
For example, image forming apparatuses such as printers or copying machines using the electrophotographic process are equipped with a fusing device that fuses the unfused toner image held onto a sheet, i.e., a recording medium. While various fusing methods are available, the heat-pressure fusing method is generally used. The fusing device using this heat-pressure method may be of a belt type or a heat roller type depending on the specific form of the rotatable member. Japanese Laid-Open Patent Application Hei 6-318001 discloses one example of a fusing device of the belt type.
A belt-type fusing device such as the one disclosed in said patent application (Hei 6-318001) has a drive roller and a heat roller having a built-in heat source, as well as a fusing belt that moves while being suspended over the pair of rollers, and the fusing belt is heated to a certain temperature by means of the heat from the heat roller. In this belt-type fusing device, the unfused toner on the sheet is conveyed such that it faces the fusing belt, and therefore, it is preheated by means of the radiating heat from the fusing belt before it reaches the nipping area where the fusing belt and the pressure roller are in pressure contact. As a result, the temperature at the nipping area may be set lower in a belt-type fusing device than in the roller fusing method, which makes fusing devices of this type more compatible with the demand for reduced energy consumption and quick printing. Further, since the toner is not melted to an unnecessary extent because the nipping area temperature can be set relatively low, the advantage is obtained that the amount of the releasing agent (such as silicone oil) that is used to prevent the transfer of the toner to the fusing belt, i.e., the offset phenomenon, may be reduced to one tenth of what is needed in the roller fusing method.
On the other hand, however, in belt-type fusing devices, if the fusing belt that is suspended between the rollers moves in a skewed fashion, the fusing belt may become damaged, or image noise may occur in the fused image.
The same problem exists in the transfer device that transfers the developed toner image held on the photoreceptor, which is the image carrier, in image forming apparatuses such as printers or copying machines using the electrophotographic method. In other words, the transfer device transfers the toner image from the photoreceptor to the transfer belt surface or the surface of a recording medium such as copy paper that is held on the transfer belt. When this is done, if the transfer belt moves in a skewed fashion, the image is transferred to a position that is offset from the initial targeted position, making accurate transfer impossible, or the transfer belt comes into contact with various components of the image forming apparatus, causing damage to the transfer belt.

Drive device, and fusing device and transfer device including said drive device


The present invention relates to phenolic thioetheramides of the formula ##STR1## wherein R.sup.1 and R.sup.2 are tert-alkyl or phenyl, Alk.sup.1 and Alk.sup.2 are alkylene; X is sulfur or oxygen, m is 0, 1, or 2; and R is ##STR2## wherein R.sup.3 and R.sup.4 are hydrogen or alkyl and Alk.sup.3 is alkylene.

1. Field of the Invention
The present invention relates to phenolic thioetheramides and more particularly relates to the novel compounds of formula I which are specific 5-lipoxygenase inhibitors and are useful, for example, as anti-inflammatory, and anti-allergy agents. Compounds of the present invention may be useful in treating arthritis, asthma, and psoriasis. Compounds of the present invention which stimulate or modulate superoxide generation may be useful as adjunctive therapeutic agents in the treatment of infections. Those compounds which inhibit superoxide generation may be useful in treating conditions in which superoxide radicals are involved.
2. Background Information and Related Art
It is well recognized that arachidonic acid, an essential unsaturated fatty acid, is enzymatically oxygenated to various products, including, prostaglandins, thromboxanes, the 5-, 11-, 12- and 15-hydroxyeicosatetraenoic acids (HETEs, DIHETEs) and hydroperoxyeicosatetraenoic acids (HPETEs) and the leukotrienes, all of which have potent physiological effects. The leukotrienes, which are produced via the 5-lipoxygenase pathway, are the major contributors to the onset of the symptoms of asthma, and mediators for immediate hypersensitivity reactions, inflammation and other allergic responses.
Leukotrienes are found in inflammatory exudates and are involved in the process of cellular invasion during inflammation. The term "leukotrienes" is used as a generic term to describe a class of substances, such as slow-reacting substance (SRS) which is an important mediator in asthma and other hypersensitivity reactions. Immunologically generated SRS is usually referred to as slow-reacting substance of anaphylaxis (SRS-A). SRS-A consists of leukotrienes (LT) known as A.sub.4, B.sub.4, C.sub.4, D.sub.4, and E.sub.4 LTC.sub.4 is at least 100 times more potent than histamine in causing long lasting bronchoconstricting effects. The leukotrienes also increase vascular permeability and cause decreased cardiac output and impaired ventricular contraction. LTB.sub.4 may be an important mediator of inflammation in, for example, inflammatory bowel disease.
Chemotaxis is a reaction by which the direction of migration of cells is determined by substances in their environment. It is one of the major processes bringing leukocytes from the blood to an inflammatory site, whether the inflammation is caused by an infectious agent, allergic challenge, or other pro-inflammatory stimuli. LTB.sub.4 is not only chemotactic for neutrophils and monocytes, but is also highly active in stimulating eosinophil locomotion. LTB.sub.4 also stimulates calcium influx and aggregation of polymorphonuclear leukocytes and LTB.sub.4 may, thus, play an important role in mediating both acute and chronic inflammation.
Rheumatoid spondylitis is characterized by an acute neutrophil flareup in the joint which is associated with elevated levels of LTB.sub.4. LTB.sub.4 is also present in gouty effusions; and exposure to urate crystals is known to stimulate LTB.sub.4 production by neutrophils. Accordingly, the 5-lipoxygenase inhibitors of the present invention through inhibition of neutrophil attraction and activation in arthritic joints should reduce the protease and oxidative burden believed responsible for joint destruction in arthritic diseases.
Aspirin and the other non-steroidal anti-inflammatory agents (NSAIDs) such as indomethacin, ibuprofen, fenoprofen, and the like, inhibit the synthesis of prostaglandins via the cyclooxygenase pathway of arachidonic acid metabolism. These prostaglandin synthetase inhibitors generally exhibit anti-inflammatory, anti-pyretic and analgesic activity, and are widely used in the treatment of arthritis. The non-steroidal anti-inflammatory agents can lead to the formation of additional pro-inflammatory derivatives of arachidonic acid produced through the 5-lipoxygenase pathway which play a role in immediate hypersensitivity reactions and also have pronounced inflammatory effects. Administration of the NSAIDs alone can produce allergic reactions including bronchospastic reactivity; skin rashes; syndrome of abdominal pain, fever, chills, nausea and vomiting; and anaphylaxis. For this reason, aspirin and the other non-steroidal anti-inflammatory agents (NSAIDs) are generally contraindicated for patients suffering from asthma or who have previously exhibited allergic sensitivity to aspirin or other NSAIDs.
Prior to the recognition of the significance of the 5-lipoxygenase pathway of arachidonic acid metabolism in allergic reactions and inflammation, the search for effective therapeutic agents was based primarily on those agents which treated the symptoms of allergy and inflammation. There has since been effort to develop new drugs which selectively block the formation of the mediators of these conditions, and the present invention provides new chemical entities which are inhibitors of the 5-lipoxygenase and/or cyclooxygenase pathway and are useful in the treatment of asthma, rheumatoid arthritis, psoriasis, and other allergic, hypersensitivity, and inflammatory conditions. In addition, those compounds which stimulate superoxide generation may be useful in the adjunctive therapy of microbial infections.
See Goodman and Gilman's, The Pharmacological Basis of Therapeutics (7th Edition, 1985) p. 660-673; P. A. Ward, et. al., "Oxygen Radicals, Inflammation and Tissue Injury," FREE RADICAL BIOLOGY & MEDICINE, 5: 403-408 (1988); and C. E. Cross, et. al., "Oxygen Radicals and Human Disease," ANN. INT. MED., 107: 526-545 (1987).
The present invention provides compounds which block the 5-lipoxygenase metabolic pathway and, therefore, block the formation of the leukotrienes responsible for allergy and inflammation, and represent therapeutic agents which are useful in the treatment of allergic and hypersensitivity reactions and inflammation, alone, or also may be utilized in combination with other lipoxygenase inhibitors or with cyclooxygenase inhibitors such as the non-steroidal anti-inflammatory agents.
Recently, oxygen radicals have been implicated in the pathogenesis of many diseases. This implication is reflected by the many conferences devoted to this topic, books on the subject of free radicals and disease, and the appearance of two new specialized journals: Free Radical Research Communications, and Free Radical Biology and Medicine.
Much is known about the physicochemical properties of the various oxygen radicals, but knowledge of their overall importance in the initiation and amplification of human disease is limited. Some clinical conditions in which oxygen radicals are thought to be involved are discussed in Cross, C. E., et al., "Oxygen Radicals and Human Disease," ANN. INT. MED., 107:526-545 (1987) (see Table 1, p. 527) and Ward, P. A., et al., "Oxygen Radicals, Inflammation, and Tissue Injury," FREE RADICAL BIOLOGY & MEDICINE, 5:403-408 (1988). Among the clinical conditions in which oxygen radicals are thought to be involved are, for example, inflammatory-immune injury, autoimmune diseases, ischemia-reflow states, aging disorders, cancer, cigarette-smoke effects, emphysema, acute respiratory distress syndrome (ARDS), atherosclerosis, rheumatoid arthritis, senile dementia, cataractogenesis, retinopathy of prematurity, and contact dermatitis.
Oxygen radicals are capable of reversibly or irreversibly damaging compounds of all biochemical classes, including nucleic acids, protein and free amino acids, lipids and lipoproteins, carbohydrates, and connective tissue macromolecules. These species may have an impact on such cell activities as membrane function, metabolism, and gene expression. Oxygen radicals are formed in tissues by many processes (see Cross, et al., p. 528, Table 2). These are believed to be both endogenous, such as mitochondrial, microsomal and chloroplast electron transport chains; oxidant enzymes such as xanthine oxidase, indoleamine dioxygenase, tryptophan dioxygenase, galactose oxidase, cyclooxygenase, lipoxygenase, and monoamine oxidase; phagocytic cells such as neutrophils, monocytes and macrophages, cosinophils, and endothelial cells; and antioxidation reactions; and exogenous, such as redox-cycling substances, drug oxidations, cigarette smoke, ionizing radiation, sunlight, heat shock and substances that oxidize glutathione. They may be involved in the action of toxins such as paraquat, cigarette smoke, and quinone antitumor drugs.
Generation of reactive oxygen species is a critical event in successful host defense against invading organisms. Both neutrophils and macrophages rely on a variety of oxidants to damage bacterial constituents (see V. L. Shepherd, "The role of the respiratory burst of phagocytes in host defense," SEMIN. RESPIR. INFECT. (United States) June 1986, 1(2) p. 99-106).
Various thioether compounds have been described previously. For example, U.S. Pat. No. 4,711,903 and its continuation-in-part, U.S. Pat. No. 4,755,524 disclose compounds of the formula ##STR3## wherein: R.sub.1 and R.sub.2 are the same or different and independently represent tert-alkyl or phenyl; A represents methylene or methylene substituted by alkyl, dialkyl or hydroxy, provided that when A includes hydroxymethylene, the hydroxymethylene group is not adjacent to a heteroatom; B represents sulfur, sulfoxide, sulfone, oxygen, --NH-- or nitrogen substituted by alkyl, phenyl, benzyl, substituted phenyl or substituted benzyl; C represents methylene or methylene substituted by alkyl; R.sub.3 represents CO.sub.2 H, CO.sub.2 -alkyl or a tetrazole group; m is 0 or 1, n is 2, 3 or 4 and p is 1, 2 or 3; and the pharmaceutically acceptable salts thereof. The compounds are specific inhibitors of 5-lipoxygenase and are useful in the treatment of local and systematic inflammation, allergy and hypersensitivity reactions and other disorders in which agents formed in the 5-lipoxygenase metabolic pathway are involved.
European Patent Application Publication No. 0131221 discloses compounds of the formula: ##STR4## in which Ar is phenyl or phenyl substituted by one to three of varied substituents, for example, alkyl, alkoxy, hydroxy, etc.; Q is oxygen, sulfur or an NH group; A is straight or branched chain, optionally substituted, alkylene and R is hydrogen or straight or branched alkyl, optionally substituted by alkoxy, hydroxyl, carboxyl, alkoxycarbonyl, etc.; and n is 0, 1 or 2. The disclosed compounds are indicated to have anti-inflammatory and anti-allergic properties through inhibition of undefined anaphylactic and anaphylactoid reactions, although no test data are provided. The preferred compounds are stated to be those in which Q represents oxygen and n is 0 without mention of any preference among the numerous possible substituents for R or substituted phenyl as Ar. In contrast to the invention disclosed in the foregoing publication, the compounds of the present invention all have a sulfur atom at the position corresponding to Q as well as having di(tertiary)-alkyl or diphenyl groups as substituents on the phenol moiety corresponding to the substituted Ar group in the above publication which, as described therein, may or may not comprise a phenol. Moreover, it is noted that the compounds of the present invention have been found to possess specificity for the inhibition of 5-lipoxygenase which is an important distinctive property not attributed to the compounds in the foregoing publication. Those of ordinary skill in the art will appreciate that the compounds of formula I of this invention, including their surprising specific 5-lipoxygenase inhibitory properties, are, therefore, not specifically described in the aforementioned EPA publication No. 0131221.
U.S. Pat. Nos. 4,029,812, 4,076,841 and 4,078,084 disclose compounds of the formula ##STR5## comprising 2-(3,5-di-tert -butyl-4-hydroxy-phenyl) thio carboxamides. The compounds are indicated to be useful in lowering plasma lipid levels including serum cholesterol and triglyceride levels.
U.S. Pat. No. 4,153,803 discloses cholesterol-lowering phenoxyalkanoic acid esters of the formula ##STR6## wherein, when Y is sulfur, X is hydrogen, benzyl, benzyloxy or benzylthio or substituted derivatives thereof; R is hydrogen, halogen, hydroxy, alkyl or alkoxy, A.sup.1 and A.sup.2 are hydrogen or alkyl and Z is amine or azacyclohydrocarbonyloxy.
U.S. Pat. No. 4,663,333 discloses compounds of the formula ##STR7## wherein: R.sub.1 and R.sub.2 are the same or different members of the group consisting of halo, phenyl, substituted phenyl and a ##STR8## group wherein n, m and p are independently an integer of from 1 to 8 provided n+m+p is equal to or less than 10; X is thio, sulfinyl or sulfonyl; Alk.sub.1 is straight or branched chain lower alkylene of 1 to 6 carbon atoms, R.sub.3 is lower alkyl, Alk.sub.2 is straight or branched chain alkylene of 1 to 4 carbon atoms; R.sub.4 is selected from the group consisting of hydrogen halo, hydroxy, lower alkyl and lower alkyxy; and the pharmaceutically acceptable salts there of. The compounds inhibit 5-lipoxygenase and are useful in the treatment of inflammation, allergy and hypersensitivity reactions and other disorders of the immune system. European Patent Application EP 0372409 published Jun. 13, 1990 discloses that these compounds are useful in inhibiting the invasive activity of tumor cells and the resulting metastasis.
European Patent Application EP 0190685 discloses heterocyclic amides represented by the formula ##STR9## wherein R.sub.1 and R.sub.2 are the same or different members of the group consisting of halo, phenyl, substituted phenyl and a ##STR10## group wherein q, r and t are independently an integer of from 1 to 8 provided that q+r+t is equal to or less than 10; Y is thio, sulfinyl or sulfonyl; Alk is straight or branched chain lower alkylene, and R.sub.3 is a heterocyclic amine represented by the formula: ##STR11## wherein R.sub.4 is selected from the group consisting of hydrogen, lower alkyl, phenyl, substituted phenyl, benzyl, substituted benzyl, carboxyl or carboxyloweralkyl; X is selected from the group consisting of N-R.sub.4, and CH.sub.2 ; m is 2 or 3; n is 2 or 3 when X is O or N-R.sub.4 and n is 1 to 3 when X is CH.sub.2 ; p is 0 to 2; and the pharmaceutically acceptable salts thereof. The compounds inhibit 5-lipoxygenase and are useful as anti-inflammatory and anti-allergy agents. European Patent Application EP 0372410 published Jun. 13, 1990, discloses that these compounds are useful in inhibiting the invasive activity of tumor cells and the resulting metastasis.
European Patent Application EP 0190682 discloses anilides represented by the formula ##STR12## wherein: R.sub.1 and R.sub.2 are the same or different members of the group consisting of halo, phenyl, substituted phenyl and a ##STR13## group wherein n, m and p are independently an integer of from 1 to 8 provided that n+m+p is equal to or less than 10; X is thio, sulfinyl or sulfonyl; Alk is straight or branched chain lower alkylene; R.sub.3 is hydrogen or lower alkyl; and R.sub.4 is phenyl or substituted phenyl. The compounds inhibit 5-lipoxygenase and are useful in the treatment of allergy and hypersensitivity reactions and inflammation.
U.S. Pat. No. 4,857,558 discloses methods for inhibiting lipoxygenase and includes pharmaceutical formulations comprising a pharmaceutical carrier and an effective lipoxygenase inhibiting amount of a compound of the formula ##STR14## wherein: R.sub.1 and R.sub.2 are the same or different members of the group consisting of 1,1-dimethylethyl, halo, phenyl and substituted phenyl; Alk is straight or branched chain lower alkylene; R.sub.4 is hydrogen or lower alkyl; R.sub.3 is hydrogen or lower alkyl or a cycloalkyl group of from 3 to 8 carbon atoms. The disclosed compounds inhibit 5-lipoxygenase and are useful in the treatment of allergy and hypersensitivity reactions and inflammation.
United Kingdom Patent No. 1,557,622 discloses 3,5-di-tertiary-butyl-4-hydroxyphenyl pyridine compounds of the formula: ##STR15## or a pharmaceutically acceptable acid addition salt thereof, wherein: y is --O--, --S-- or --N(R.sup.4)-- [wherein R.sup.4 is a hydrogen atom, an alkyl group having 1 to 4 carbon atoms (e.g. methyl, ethyl, propyl or butyl), an aralkyl group (e.g. benzyl, methoxybenzyl or phenethyl)];
each of R.sup.1 and R.sup.2 is a hydrogen atom, a hydroxyl group or an alkyl group having 1 to 4 carbon atoms (e.g. methyl, ethyl, propyl or butyl); PA0 R.sup.3 is a hydrogen atom, a hydroxymethyl group or a group of the formula: ##STR16## m is 0 or 1; and n is 0, 1, 2 or 3. PA0 R.sub.1 stands for a hydrogen atom or a lower alkyl radical, PA0 R.sub.2 stands for one of the groups, ##STR18## CN, and, in case n equal 0 and R.sub.1 is a hydrogen, it can only be C.sub.6 H.sub.5 and in case n equal 1, it can also be OH, whereby R.sub.3 stands for an alkyl radical with 1 to 5 carbon atoms and R.sub.4 and R.sub.5, which may be the same or different, stand for hydrogen atoms, lower or medium alkyl radicals or, together with the nitrogen atom, stand for a ring that may contain another heteroatom, PA0 n stands for 0 or 1
Preferable compounds of the formula are those wherein Y is --O-- or --N(R.sup.4)-- (wherein R.sup.4 is as defined above). These compounds are said to have antiarterosclerotic, antihyperlipidemic, cerebral vasodilating and antithrombotic activities, and are useful as drugs for the treatment of eschemic vascular diseases in mammals such as artherosclerosis, cardiac infarction, angina pectoris, cerebral infarction, cerebral hemorrhage, renal infarction, intermittent claudication, transient cerebral attack or thrombosis.
German Offenlegunsschrift 1 936 463 discloses phenols having the formula ##STR17## in which X and Y, which may be the same or different, stand for hydrogen or halogen atoms or lower alkyl radicals,
as well as with the corresponding phenolates. The phenols are said to have biocidal activity but they are said to be above all suitable as intermediates for the preparation of biocidal substances, for example, phosphate esters and carbamates.


A backup ring for a seal assembly including a body having a radially outer surface and a radially inner surface, an opening in the body extending from the radially outer surface toward the radially inner surface, the opening being receptive to a line to guide and protect the line. A wellbore system including a borehole in a subsurface formation, a string disposed in the borehole, a seal system disposed in the string, the system including a backup ring comprising a body having a radially outer surface and a radially inner surface and an opening in the body extending from the radially outer surface toward the radially inner surface, the opening being receptive to a line to guide and protect the line and a method for running a line along a seal system.

In the resource recovery industry seal systems are ubiquitously used to temporarily or permanently hold a pressure differential in a borehole. Systems may sometimes also need to pass control lines, electric lines, etc. These may be passed below an element of the seal system and then spliced while running in the hole but time is lost and cost is substantial due to actions required for splicing and for testing of the splices to ensure functionality and regulatory compliance. Innovations that permit the passage of lines beyond seal systems without the need for splicing operations would be well received by the art.

Backup ring with control line protection, systems, and methods


A processing system having a testing mechanism that can read out data from a memory such as a ROM without increasing the number of logic circuits to simplify the circuit construction by utilizing the testing mechanism. The processing system includes an address register in the testing mechanism of a chip part connected to the memory in parallel with the other registers, a selector for selecting and sending out either test data from the testing mechanisms or read-out data from the memory. A control unit is further provided so as to set a leading address of the data to be read out from the memory to the address register by the shift operation, to switch the selector to send out the read-out data from the memory, and then, to count up the address of the address register in accordance with a data number to read out, and to read out the data from the memory. This processing system can be applied to a system having the testing mechanism of a JTAG circuit and the like.

1. Field of the Invention
The present invention relates to a processing system including a computer system having a testing mechanism (for example, a JTAG circuit as a boundary scan architecture) for testing a high-density printed circuit board, particularly to a technique for reading out data from a memory such as a ROM by using the testing mechanism.
2. Description of the Related Art
High-density integration in chip parts including LSIs has eagerly been sought in recent years and more complicated circuits can be mounted on a smaller chip. The surface mounting technique on a printed circuit board has also advanced so that more chips can be mounted on the printed circuit board. Owing to the advancement of these fields, a higher-performance system can be built up in a smaller size; on the other hand, it has become difficult to test chip parts on such a printed circuit board.
Accordingly, to test such a high-density printed circuit board, JTAG (Joint Test Action Group) has proposed aboard testing technique (test simplifying technique) as a standard of IEEE standard 1149.1. In this board testing technique, a boundary scan architecture (hereafter, referred to as JTAG circuit) is defined as a testing mechanism incorporated into chip parts including LSIs.
In this JTAG circuit (also mentioned as JTAG scan circuit), shift-type scan chains are provided with input and output pins of chip parts mounted on a printed circuit board and the scan chains for the chip parts are connected on the printed circuit board. Thereby, the state of the input and output pins can be controlled and observed only by the scan shift operation without directly probing the input and output pins of the chip parts on the printed circuit board.
A general circuit construction of the JTAG circuit will be described with reference to FIG. 6. The circuit is comprised of five tap access ports (hereafter referred to as TAP for abbreviation) 501.about.505 as described later, a TAP controller 51, a data register group 52, an instruction register (IR) 53, a data register selector 54 output selecting circuit 55 and a gate circuit 56.
The TAP 501 is an input terminal to receive a test clock signal TCK, and the TAP 502 is an input terminal to receive a test mode selecting signal TMS. The TAP 503 is an input terminal to receive data necessary for testing, this TAP 503 is hereafter noted as a test data input TDI. The TAP 504 is an output terminal to supply a test result of an LSI (chip) provided with the JTAG circuit, this TAP 504 is hereafter noted as a test data output TDO. Furthermore, the TAP 505 is to receive a test reset signal TRST to initialize test logic in the JATG circuit.
The TAP controller 51 controls, by means of the test mode selecting signal TMS and the test clock signal TCK, the shift operation whereby the input data from the test data input TDI is sent to the instruction register 53 or to the data register group 52. Furthermore, this TAP controller 51 controls the register selecting operation by the output selecting circuit 55 and the gate operation by the gate circuit 56.
The data register group 52 consists of a user test data register 520, boundary scan register 521, and bypass register 522.
The user test data register 520 stores an arbitrary test data that a user individually determines, and is composed of shift registers. The boundary scan register 521 is composed of one stage shift registers provided in correspondence with terminals of the part (here, an LSI) to be tested, and captures or holds signals appearing on the terminals of the LSI on the basis of the theory of the scan test The bypass register 522 is composed of one stage shift registers, and it enables the input data from the test data input TDI to bypass the circuit between the test data input TDI and the output selecting circuit 55 so that the input data can go through the circuit as it is from the test data output TDO. Therefore, this bypass register 522 is used when bypassing data from this JTAG circuit to the other JTAG circuit on the subsequent stage.
On the other hand, the instruction register 53 writes a command (register designating command) from the test data input TDI by the shift operation.
The data register selector 54 analyzes the command written in the instruction register 53, and selects the register specified by the command out of the data register group 52. The data are written into the register selected by this data register selector 54 by the shift operation When either the boundary scan register 521 or user test data register 520 is selected, the data are written; when the bypass register 522 is selected, the bypassing operation mentioned above is done by the bypass register 522.
The output selecting circuit 55 is composed of a multiplexer (MUX) 551 and 552.
The multiplexer 551 is controlled by the TAP controller 51 to select one of the registers 520.about.522 of the data register group 52, and sends out data of the selected register.
The multiplexer 552 is controlled by the TAP controller 51 to select either the data from the data register group 52 (the output from the multiplexer 551) or the data from the instruction register 53, and sends out the selected data.
The gate circuit 56 is controlled by the TAP controller 51 to open or close, and when the gate circuit 56 opens, sends out the data from output selecting circuit 55 (the data from the multiplexer 552) to the test data output TDO.
The JTAG circuit thus constructed is usually applied to the test of a printed circuit board containing chip parts into which the JTAG circuit is integrated. However in recent years, it has been done to set data during a test or normal operation in a circuit such as a register in a system logic circuit (data loading), or to read out data from a circuit such as a register in a system logic circuit (data sensing). The access command issued to a system logic circuit by using the JTAG circuit is called the JTAG command.
In the JTAG circuit performing a data loading or data sensing by the JTAG command, as shown in FIG. 7, a JTAG instruction register (hereafter, abbreviated as JIR) 523 and a JTAG data register (hereafter, abbreviated as JDR) 524 are provided in replacement of the user test data register 520 shown in FIG. 6.
The JIR 523 functions as a storage of the command for controlling the system logic circuit in this LSI and consists of shift registers (or, shift registers and latch circuits), and sequentially shifts and receives the input data from the test data input TDI. When a specific command is set in this JIR 523, the command in the JIR 523 is transferred into a command analyzing unit in the command control unit (not illustrated), and the command is analyzed therein.
The JDR 524 functions as a storage of the data to be written into the system logic circuit in this LSI and the data read out from the system logic circuit in this LSI, and consists of shift registers (or, shift registers and latch circuits) in the same manner as the JIR 523.
When the data are written into this JDR 524, the input data from the test data input TDI are sequentially shifted and received. When specific data are set, the data in the JDR 524 are transferred to a processing unit in the foregoing command controlling unit, and a process is executed on the basis of an analyzed result by the foregoing command analyzing unit. It is possible, for example, to set data in the register of the system logic circuit performing a normal operation, to set a specific value to a counter, or to reset only a specific circuit in this LSI.
On the contrary, it is possible to read out the data of the system logic circuit performing a normal operation from the test data output TDO through the JDR 524. Namely, the data set in the register in the system logic circuit are transferred to the JDR 524, the data of the JDR 524 are sequentially shifted, and thereby, the shifted data are sent out from the test data output TDO.
The data-write into the JIR 523 or JDR 524 is done, as described above, with a shift operation when the data register selector 54 selects the JIR 523 or JDR 524.
Next, the operation of the JTAG circuit (executing operation of the JTAG command) comprising the JIR 523 and JDR 524 will be described with reference to FIG. 8. FIG. 8 is a flow chart showing a state transition of the test logic. The state transition of the test logic is controlled by the TAP controller 51 to embody various test states The TAP controller 51 is controlled by the test clock signal TCK, test mode selecting signal TMS, and test reset signal TRST entering from the TAP 501, 502, and 505, respectively
Immediately after initialized, the TAP controller 51 is in the TEST-LOGIC-RESET state (S201). In this state, the test logic is unavailable, and the normal operation of the system logic is 15 possible.
Each of the states is transferred in accordance with the state of the test mode selecting signal TMS when the test clock signal TCK rises When the state is in the TEST-LOGIC-RESET state (S201), for example, the test clock signal TCK rises, and if the test mode selecting signal TMS at that moment is "0", the state is transferred to the RUN-TEST/IDLE state (S202); if the test mode selecting signal TMS at that moment is "1", the state is held in the TEST-LOGIC-RESET state (S201).
The RUN-TEST/IDLE state (S202) is the basic state during a test being executed, which is a state that a scan operation is about to start, or an intermediate state during the scan operation
When the state is transferred to the SELECT-DR-SCAN state (S203), the scan sequence is initialized.
Next, the state is transferred into the CAPTURE-DR state (S211) or into the SELECT-IR-SCAN state (S204) in accordance with the state of the test mode selecting signal TMS. Here, the transition to the SELECT-IR-SCAN state (S204) to perform a scan operation to the instruction register 53 will be described. When the state is transferred to the SELECT-IR-SCAN state (S204), the scan sequence of the instruction register 53 is initialized.
When the state is transferred to the CAPTURE-IR state (S205), a fixed pattern is captured in the shift registers forming the instruction register 53. This fixed pattern has a fixed binary code "01" in the lower two bits, and an information intrinsic to a design can be incorporated into this pattern. The data of the instruction register 53 can be read out through the test data output TDO while shifting the data.
When the state is transferred to the SHIFT-IR state (S206), the shift registers forming the instruction register 53 are connected to the test data input TDI and the test data output TDO. When the test mode selecting signal TMS is "0", and every time the test clock signal TCK rises, the data are shifted toward the test data output TDO. If the instruction register 53 is constituted with 8 bits, repeating the shift operation eight times enables specific data to be written into the instruction register 53. Furthermore, sending out the data of the instruction register 53 to the test data output TDO while repeating the shift operation enables the data of the instruction register 53 to be read out.
When the shift operation finishes, the state is transferred to the EXIT1-IR state (S207) to end the scan operation. In this EXIT1-IR state (S207), setting the test mode selecting signal TMS to "0" and rising the test clock signal TCK transfers the state to the PAUSE-IR state (S208); setting the test mode selecting signal TMS to "1" and rising the test clock signal TCK transfers the state to the UPDATE-IR state (S210).
When the state is transferred to the PAUSE-IR state (S208), the shift operation of the instruction register 53 is paused in a serial pass between the test data input TDI and the test data output TDO. This state is utilized when a new pattern is loaded into an internal memory from an external memory.
In the PAUSE-IR state (S208), setting the test mode selecting signal TMS to "1" and rising the test clock signal TCK transfers the state to the EXIT2-IR state (S209) to stop the scan. When the scan operation is further needed, in the EXIT2-IR state (S209), setting the test mode selecting signal TMS to "0" and rising the test clock signal TCK transfers the state again to the SHIFT-IR state (S206) to perform the shift operation. when ending the scan operation, in the EXIT2-IR state (S209), setting the test mode selecting signal TMS to "1" transfers the state to the next UPDATE-IR state (S210).
When the state is transferred to the UPDATE-IR state (S210), new instruction data shifted to the shift registers are latched to be sent out in parallel When all the data are completely latched, execution of the instruction starts.
If a bypass instruction is loaded, for example, into the instruction register 53, the bypass register 522 is selected and is connected to the test data input TDI and the test data output TDO so as to bypass the data by the shift operation.
If an instruction "JIR SET" or "JDR SET" is loaded into the instruction register 53, the JIR 523 or JDR 524 is selected and is connected to the test data input TDI and the test data output TDO so as to execute the data loading into the JIR 523 or JDR 524 and the data sensing from the JIR 523 or JDR 524, namely, the data scanning by the sift operation.
On the other hand, the state S203 and S211 through S216 in FIG. 8 shows the state in which the scan operation is executed to the boundary scan register 521, bypass register 522, JIR 523, or JDR 524.
When comparing the scan operation by the state S203 and S211 through S216 with the scan operation to the instruction register 53 described in the state S204 through S210, there are differences in the two points: (a) the registers to be scanned are four registers 521 through 524 of the data register group 52 against the instruction register 53; (b) the number of shifting in the scan operation is varied depending on which one of the registers 521 through 524 is selected to be scanned.
However, the state transition is substantially the same, the state S203 and the S211 through S216 correspond to the state S204 through S210, respectively, and the description will be omitted.
In the denotation of the state S204 through S210, "IR" meaning the instruction register 53 is changed into "DR" meaning the data register 52 in the denotation of the state S203 and the S211 through S216, which is a difference in the notation.
FIG. 9 illustrates a total construction of a processing system (computer system) employing chip parts into which the JTAG circuit described above with FIGS. 7 and 8 is incorporated. The processing system is comprised of a service processor (hereunder, abbreviated as SVP) 101, an interface circuit hereunder, abbreviated as SCI(System Console Interface)! 102, and a mother board 103.
The SVP 101 is connected to the mother board 103 through the SCI 102 to control the maintenance and operation of the total system. The SVP 101 issues commands to control: the registers in the printed circuit boards 103-1 through 103-m constituting the mother board 103, a data-write into a memory, and a data read-out from a memory.
The chip parts such as LSIs mounted on the printed circuit boards 103-1 through 103-m are provided with the JTAG circuits described in FIG. 7. The SVP 101 also controls the JTAG circuits through the SCI 102. Accordingly, the SCI 102 and the printed circuit boards 103-1 through 103-m in the mother board 103 are connected by signal lines 104 to transmit and receive commands and data so as to control the JTAG circuits.
Incidentally, the conventional computer system has been trying to improve the performance of the central processing unit (CPU) itself in order to cope with users' needs. However, with this approach alone, the increasing users' needs cannot be satisfied in some aspects, and recently, the parallel processing computer has attracted a considerable attention.
The parallel processing computer constitutes one computer system in which several to some hundreds of processing units called processor element (PE) are connected to be able to communicate each other, and the PEs each can execute the processes, thereby improving performance as a system by executing the parallel processes.
The units constituting such a computer system each are composed of a plurality of printed circuit boards as shown in FIG. 9. The printed circuit boards each are provided with a clock signal from a clock oscillator, and a plurality of the printed circuit boards operate synchronously with the clock signal. However, the printed circuit boards each have intrinsic characteristics of their own, and generally, the circuit boards having an identical circuit construction will have deviations in the operational timing among the printed circuit boards.
In order to annul the deviations in the timing, clock tuning latches are provided on each of the printed circuit boards. Setting specific clock tuning data according to the characteristics of the printed circuit boards to the corresponding latches and making the clock timing to coincide with each other among the printed circuit boards will annul the deviation in the timing so that the total unit can operate synchronously with one clock.
The process to set specific clock tuning data to clock tuning latches is called a clock tuning process. Generally, this clock tuning process is done for a start-up period of the system from the moment the system is powered to the start of the operation, as follows.
In the units constituting the computer system, continuously connecting the clock tuning latches on the printed circuit boards forms one loop (tuning scan loop), and sending the clock tuning data to be set to the latches into the foregoing loop sequentially according to the sequence to connect the latches and repeating the shift loads the clock tuning data into the specific latch. The clock tuning data and the data intrinsic to the printed circuit boards which are necessary for the start-up of the system, and others are stored in advance in an EEPROM described later in FIG. 10 or the like, and are read out from the EEPROM or the like at the start-up.
Next, FIG. 10 illustrates a construction of important parts of the processing system that performs the foregoing clock tuning process. The processing system shown in FIG. 10 is virtually identical to the processing system shown in FIG. 9. FIG. 10 further illustrates a detailed construction of the printed circuit board 103-x functioning as an MCU (Main Control Unit) of a plurality of the printed circuit boards constituting the mother board 103 and a detailed construction of the SCI 102.
As shown in FIG. 10, the printed circuit board 103-x includes three LSI-1, LSI-2, and LSI-3, each of which is provided with the JTAG circuit as a JTAG testing unit 100 as described in FIG. 6 or 7. Connecting these JTAG testing units 100 in a chain forms a round scan chain in the printed circuit board 103-x. And, the SCI 102 is provided with a JTAG control unit 104 that controls the JTAG testing units 100 namely, writes desired data into the registers (refer to FIG. 7) of the JTAG testing units 100.
Furthermore, the system shown in FIG. 10 is provided with an EEPROM (nonvolatile memory) 105 of, for example, 8 Kbytes connected to the LSI-2 in the printed circuit board 103-x functioning as an MCU. This EEPROM 105 holds the clock tuning data of the printed circuit boards constituting the mother board 103, and the other data necessary for the start-up of the system that are intrinsic to the printed circuit boards.
At the start-up of the processing system, the data stored in the EEPROM 105 needed to be read out in order to execute the foregoing clock tuning process. Accordingly, the processing system shown in FIG. 10 is provided with, apart from the aforementioned JTAG testing units 100 and the JTAG control unit 104, a data load unit 106, EEPROM read-out control unit 107, and data transfer unit 108 on the SCI 102, and is provided with an address write unit 109 and address register (ADRS) 110 on the LSI-2 connected to the EEPROM 105.
The data load unit 106 receives data read-out designating data as well as address data (leading address, read-out data number) at the start-up of the processing system from the SVP 101, and sends the leading address of the data to be read out to the 20 address write unit 109 in the LSI-2 of the printed circuit board 103-x.
The address write unit 109 sets the leading address from the data load unit 106 to the address register 110, and the data in an address set in the address register 110 are read out from the EEPROM 105 to the EEPROM read-out control unit 107.
The EEPROM read-out control unit 107 sends out a count-up designation address-up (AD UP)signal! to the address register 110 in order to count up the address set to the address register 110 one by one for the read-out data number from the leading address, and on the other hand sends out the data read out from the EEPROM 105 to the data transfer unit 108. The data transfer unit 108 transfers the data read out from the EEPROM 105 to a memory (DM) 111 for a DMA (Direct Memory Access) of the SVP 101.
According to the foregoing construction at the start-up of the processing system, the read-out designation such as the clock tuning data as well as the address data (leading address, read-out data number) are sent out to the data load unit 106 of the SCI 102 from the SVP 101. The leading address of the address data is sent out from the data load unit 106 through the address write unit 109 to be set to the address register 110 in the LSI-2.
The data in accordance with the address set to the address register 110 are read out from the EEPROM 105, and the read-out data are transferred to the DM 111 of the SVP 101 through the EEPROM read-out control unit 107 and the data transfer unit 108. The address set to the address register 110 is counted up one by one for the read-out data number from the leading address by the EEPROM read-out control unit 107, and the data such as the clock tuning data requested by the SVP 101 are sequentially read out from the EEPROM 105 into the SVP 101. And, the SVP 101 executes the initialization of the clock tuning process and the like using the read out data.
However, the processing system shown in FIG. 10 has to be provided with a single-purpose circuit as a mechanism to read out the clock tuning data and the like stored in the EEPROM 105, namely, the data load unit 106, EEPROM read-out control unit 107, address write unit 109 and the like, which invites complexity of the circuit construction.

Processing system having testing mechanism


An independent suspension (10) of a vehicle includes a knuckle (22) intended to carry a wheel (W), a damper (12) connected at a bottom end thereof to the knuckle (22), and a plurality of arms (14, 24) connected to a body (B) of the vehicle and the knuckle (22). A hinge device (30; 34) is interposed between the damper (12) and knuckle (22) to allow the damper (12) and knuckle (22) to rotate relative to each other about an axis of articulation (H) that is oriented to form an acute angle with a horizontal. A torsional stiffness control device (32; 34; 34, 70) is interposed between the damper (12) and knuckle (22) to control torsional stiffness of an articulated connection between the damper (12) and knuckle (22) about the axis of articulation (H).

1. Field of Invention
The invention relates, generally, to a vehicle independent suspension and, more particularly, to improvement of elasto-kinematic performance of the vehicle independent suspension architecture commonly known as "MacPherson architecture."
2. Description of Related Art
The MacPherson suspension architecturt is fundamentally based on the idea of using the damper as an integrating part of the structure of the suspension. With referenceto FIGS. 1 and 2 of the attached drawings, which schematically show an example of vehicle front suspension accordnig to the MacPherson architecture, in perspective view and in front elevation, respectively, the suspension includes a damper 12 rigidly connected at its bottom end to a wheel-carryrng knuckle 22 (hereinafter simply referred to as "knuckle"), trianaular lower arm 14 having two transversely inner attachment points 16 and 18 for articulated connection to the vehicle body (indicated "B" in FIG. 2 ) and a transversely outer attachment point 20 for articulated connection to the knuckle 22, and a steering rod 24 having a transversely inner attachment point 26 for connection to the vehicle steering control mechanism and a transversely outer attachment point 28 for articulated connection to the knuckle 22. By virtue of the rigid connection between damper and knuckle 22 , the longitudinal and lateral forces acting on the wheel produce bending and shear stresses in the damper and are transmitted to the vehicle via the top mount of the damper.
The main advantages of the MacPherson architecture are the low cost and the small overall size. Since the functions of shock absorption, of provision of a mount for the spring and of reaction to the loads acting on the wheels are performed by the damper, it is in fact possible to obtain a considerable reduction in the number of components of the suspension, with resulting reduction in the cost thereof. Moreover, removing the upper lateral control arms leads to a reduction in the overall size of the suspension, which allows, in case of a front suspension, to obtain more space available for the engine, which is particularly advantageous in front-wheel drive motorcars with transversely-mounted engine and gearbox units.
The MacPherson architecture suffers however from the drawback of having low kinematic performances, with regard in particular to the camber change during the bump/rebound motion of the wheel. The performances of the MacPherson architecture in terms of load absorption are low, in particular with regard to the longitudinal forces acting on the wheel in case of braking or impact. More specifically, the longitudinal stiffness provided by the MacPherson architecture at the wheel center is much higher than that required to ensure good comfort performances. A further drawback of the MacPherson architecture is the reduced possibility to differentiate the toe change response of the suspension in traction and in braking Moreover, in the MacPherson architecture all the longitudinal compliance of the suspension is provided by the lower triangular arm, whose geometry is largely determined by the necessity to meet the requirement to combine high longitudinal compliance with high lateral stiffness, and therefore less freedom is left to the designer.
Additionally, according to the MacPherson architecture the point of maximum longitudinal stiffness of the suspension is located at the top mount of the damper, and accordingly the longitudinal stiffness of the suspension at the contact patch between the wheel and the road is much lower than that at the wheel center (in proportion to the vertical distances of these two locations from the top mount of the damper - point of maximum longitudinal stiffness), for example 50% to 75%. This has a detrimental effect on braking response. Since all the longitudinal compliance is provided by the lower arm, the ball joint between the lower arm and the knuckle undergoes significant longitudinal displacements, which results directly in castor loss in braking and hence in loss of stability of the vehicle. The practical result of this is that the designer is compelled to reduce the longitudinal compliance at the wheel center to avoid an excessive longitudinal compliance at the contact patch and hence excessive castor loss in braking.
It is therefore an object of the invention to provide a motorcar independent suspension which has better performances than the MacPherson architecture discussed above in terms of load absorption, particularly with regard to longitudinal forces, while retaining the advantages of this known architecture in terms of cost and overall size.


A machine for winding film, a method of manufacturing spools of pre-stretched film, and spools of pre-stretched film obtained as a result, are disclosed. The method of winding spools of pre-stretched stretchable film includes importing oscillation to the film with a component perpendicular to the axis of the film. For example, during pre-stretched and winding of the film on a take-up spool, a feed spool, i.e. a spool from which the stretchable film for stretching is taken, is caused to oscillate, and/or the take-up core is caused to oscillate. This ensures that successive layers of film are offset, in particular at the margins of the film. Spools of film obtained in this way do not have portions of extra thickness and lower tension at the margins as is the case prior art spools of pre-stretched film.

Prior stretching advantageously includes a step of paying out the film from a feed spool, a step of stretching it, and a step of winding the stretched film on a take-up spool or core, ready for subsequent use.
Immediately after being stretched, stretchable film is subject to relaxation which leads, over a period that is substantially equal to 48 hours, to the elastic return force being reduced substantially by 50%.
In French patent application No. 92 10254 published under the No. FR-A-2 695 102, the Applicant describes a method of manufacturing pre-stretched film that is relaxed under the stretching tension, and in European patent application No. 97 401 005.0 published under the No. EP-A1-0 806 284, the Applicant describes a method of manufacturing pre-stretched film that is relaxed under low mechanical tension.
Pre-stretched film of known type is wound on cylindrical cores. The film is paid out from the core and is wrapped, e.g. helically, around a load to form an outer wrapping thereabout.
Unfortunately, pre-stretched stretchable film wound on a core turns out to be particularly fragile. For example, being dropped on the ground runs the risk of creating zones of weakness or holes in the margin of the film. Such zones of weakness or such holes in the margin of the film can start tears while a load is being wrapped, or even worse, while a wrapped load is being handled or transported, with the attendant risk of the load being dislocated.
In addition, when the thickness of a film is not absolutely constant, and the film is wound on a core, in particular a core made of card, then overlap zones are generated at the margins between successive layers that impede proper paying out of the film during wrapping, and this can go as far as causing the film to tear.
U.S. Pat. No. 5,531,393 describes a machine for anticipated stretching of a stretchable film for the purpose of texturing the film to facilitate unwinding. The margins of the film are folded over. Reciprocating horizontal motion of the take-up spool spreads out the resulting extra thickness.
GB-A-2 288 594 describes a device provided with means for winding film on a horizontal axis spool driven with reciprocating motion.
Neither of those two documents describes or suggests forming frustoconical or substantially conical end zones that facilitate unwinding of the film, particularly when it is done manually.

Machine for winding film, a method of making spools of pre-stretched film, and spools of prestretched film obtained thereby


An electrolytic capacitor capable of operating at 75 g or greater is provided having a case with a base and a lid, with a wound capacitor element positioned on its side, lengthwise along the bottom of the base and with the underside of the lid pressed against the length of the capacitor element, to frictionally engage the capacitor element. The case is provided with inwardly projecting surfaces, including a bulkhead at one end of the capacitor element and ridges on the lid, which function as barriers to restrict movement of the capacitor element within the case. A compartment is created at one end of the case, to allow space for terminals, which are embedded in a non-conductive support matrix.

Wound capacitors, such as aluminum electrolytic capacitors, are often used in environments where they are subject to relatively high vibration, impact and centrifugal force. For example, capacitors are commonly incorporated into deep well drilling equipment and the electrical circuitry of aircraft and spacecraft. Typical wound capacitors are rated to withstand g-forces of up to 25 g. Subjecting the capacitor to higher g-forces may result in failure of the capacitor.    Rubin—U.S. Pat. No. 4,584,630 discloses a mounting spacer for an electrolytic capacitor. The mounting spacer is a flexible plastic sheet, which when folded and inserted inside the tubular casing provides alignment and support for the capacitor section.    Hutchins et al.—U.S. Pat. No. 4,987,519 disclose an aluminum electrolytic capacitor having a fluoro-plastic member at each end of the capacitor element. An inwardly directed annular bead deforms the case and engages the fluoro-plastic member to create a seal.    Bruvelaitis et al.—U.S. Pat. No. 6,307,734 disclose an electrolytic capacitor having a silicone potting compound surrounding the capacitor within the canister (case). Indentation 108 in canister 102 compresses the silicone compound against the capacitor element to maintain the capacitor element firmly in place.    Ashino et al.—US Patent Application No. 2012/0154984 disclose an electrolytic capacitor with a tape material wound around the outside of the capacitor element. The metal case is crimped inward to engage the tape material, thereby fixing the capacitor element in place relative to the case.
Despite the various prior art attempts to align, support and stabilize a wound capacitor element in a case, there remains a long felt need for a capacitor capable of functioning in high g-force applications.


A system and method generate private keys for devices participating in a self-certified identity based encryption scheme. A private key is used by the devices to establish a common session key for encoding digital communications between devices.

Due to a convergence of multiple technologies, an ever increasing number of devices are now able to seamlessly communicate wirelessly with the Internet or wirelessly exchange communications between themselves. This convergence has resulted in the vision of the Internet of Things (IoT) gaining more traction through recent years. In the Internet of Things, millions of entities or devices (i.e. Things) will be connected to one another. These devices, which comprise devices or entities such as smart chips, smart plugs, smart watches, smart phones, smart vehicles, smart buildings, and etc., either communicate directly with one another or via the Internet.
As the Internet of Things spreads into more areas, these devices become more prone to cyber-attacks from hackers or unauthorized users as a compromised device would grant a malicious user access to the network to which the device belongs. Hence, it is of utmost importance that a security protocol be set in place to allow one entity to verify the authenticity of a peer entity, with which it communicates with, before data is exchanged between these two entities. In addition to the above, once the authenticity of the entities have been verified, a secret key known to only these two entities, has to be established to facilitate the signing of data messages between these entities. This is to ensure that data communicated between these two entities will not be compromised even if the data were intercepted or redirected.
A common method of establishing a secret key for signing data communications between entities involves the pre-sharing of a common symmetric secret key between the relevant parties. For such a method, data messages that are to be transmitted between the entities will be signed using this pre-shared or pre-agreed-upon secret key. If the receiving entity is able to decrypt the received message using this pre-shared secret key, this implies that the authenticity of the sender has been verified and the receiver may then proceed to process the decrypted message accordingly. Unfortunately, this method is not scalable and is quite inflexible as it requires the common secret to be pre-shared or communicated to all trusted entities or devices before the entities or devices may communicate with one another. In the IoT setting, the high mobility of devices is a norm and devices that are required to exchange data with one another may not have had the opportunity to establish a secret key beforehand.
Another approach that has been proposed utilizes public key infrastructure (PKI) based solutions whereby key-pairs allocated to each authorized entity are bound to its holders by means of a public key certificate. The key pair then utilizes a public key cryptosystem such as public-key encryption or digital signature methodologies to sign data messages or to verify the authenticity of a sender by validating the public key certificate of the sender. The setup and maintenance of such public key infrastructures are notoriously expensive and require entities to constantly maintain contact with a PKI server to validate the respective public key certificates.
Yet another approach that has been proposed utilizes identity based cryptography methodologies to authenticate entities and to sign data messages. Such identity based cryptosystems are special public key cryptosystems, which are based on bilinear pairing and utilize an entity's identity, such as user name, email address, telephone number, IP address, etc. as the public key and a corresponding private key is then derived from the entity's identity by a Key Generation Centre which contains a master secret key, which is utilized in the generation of private keys for entities. The downside of this approach is that bilinear pairing is an expensive and time consuming computation process.
Another inherent weakness of existing identity based cryptographic schemes is that users' private keys are usually generated by a Key Generation Centre. As the users' private keys are escrowed to the key generation centre, this means that the key generation centre will possess all the private keys of the users of the scheme. If the key generation centre were ever to become compromised, this would mean that all the users of the system would be compromised as well.
For the above reasons, those skilled in the art are constantly striving to come up with a system and method to generate private keys for users of an identity based signature scheme whereby the private keys are only made known to each respective user. The private keys are then utilized with the identity based signature scheme to verify the authenticity of users of the scheme and to generate a common session key that is to be used to encode data messages between verified users.

System and method for computing private keys for self certified identity based signature schemes


A packing carton for packing pouch-type beverage containers stands on two sides, referred to as bottom surfaces, while in the open state and comprises halves which are open at their respective tops. Each bottom surface is delimited on four sides by carton sides, and the halves have a common longitudinal side, which is bent in the middle when in the open state, and comprises stiffening flaps on the transverse sides. The stiffening flaps are extensions on the transverse sides. A machine for closing such a packing carton is also disclosed, as well as a related method for closing the packing carton.

1. Field of the Invention
The invention relates to a packing carton for packing pouch-type beverage containers, to a machine for closing a packing carton and to a method for closing a packing carton.
2. Description of the Related Art
The packing of individual containers, in particular of individual, pouch-type containers in cartons or other packing alternatives, e.g. for dispatch, transport and storage, hereinafter termed "packing cartons," is known from the prior art. Such packing cartons are often made of corrugated cardboard or, like packing cases, are reinforced in certain areas by two layers of cardboard provided in parts. The packing of containers using machines for the packing carton is known as well.
A reinforced carton is known from European Patent No. EP2013093 B1. Document G9420577 discloses a packing carton made, in particular, of cardboard and having a closure made of cardboard. German Patent No. DE19745854 C1 discloses a method and a device for packing bags in packing cartons.
However, the prior art solutions suffer from the problem that, for stability reasons, non-corrugated cardboard can sometimes not be used without an additional reinforcement, e.g. by double layers. This leads to higher materials costs and increased complexity, which should preferably be avoided.
Also, it should be possible to carry out a packing method as efficiently and fast as possible, and it should be tailored to the packing carton.

Packing carton and related machine and method

INDAG GESELLSCHAFT FUR INDUSTRIEBEDARF MBH & CO. BETRIEBS KG


A board 1 according to the present invention includes a board main body 3; electronic parts 5 electrically connected to and mounted on the board main body 3; and an under-fill material 19 with which a part between the board main body 3 and a surface of the electronic parts 5 electrically connected to the board main body is filled. A hole 21 passing through a layer 19a of the under-fill material that flows outside from a connecting area of the electronic parts 5 and the board main body 3 is provided for electrically connecting other parts to the board main body.

The present invention relates to a board and a method for producing the same. More particularly, the present invention relates to a board on which electronic parts are mounted by using an under-fill material and a method for producing the board.
As a method for mounting electronic parts, for instance, a semiconductor chip on a board such as a wiring board with high density, a flip chip bonding method is known. In the flip chip bonding method, a solder bump is provided on an electrode pad of the semiconductor chip so that the chip is mounted on an electrode pad formed in the board on which the chip is to be mounted so as to be aligned with the electrode of the chip through the solder bump. A gap between the mounted chip and the board is filled with an under-fill material mainly for the purpose of preventing a stress resulting from a difference in coefficient of thermal expansion between the chip and the board from being concentrated to a solder bump connected part. As the under-fill material, a resin including filler such as silica is employed.
The under-fill material is injected to a part between the chip and the board by a capillary action, and then hardened by heating. When the under-fill material is heated, the fluidity of the resin of the under-fill material is increased so that a part of the under-fill material flows outside from the part between the chip and the board. To avoid the insufficiency (causing a void) of the under-fill material with which the part between the chip and the board is filled, the under-fill material is ordinarily somewhat excessively used. This also promotes the outflow of the under-fill material by heating it.
When there is a pad for connecting other parts to the board on the surface of the board on which the chip is mounted, the flowing out under-fill material may possibly reach the area of the pad so that the under-fill material prevents the connection of other parts to the board. In order to meet such a problem, various proposals have been hitherto made. For instance, as disclosed in Patent Document 1, a technique has been known that a dam groove is formed for preventing the expansion of the under-fill material flowing out on a solder resist on which the pad of the board protrudes or a technique that a dam frame for preventing the expansion of the under-fill material is attached to the solder resist in place of the dam groove. As a technique for improving these techniques, the Patent Document 1 discloses a technique that a process (a process for applying another material to the solder resist, a roughening process by applying a laser on the surface of a solder resist, etc.) is carried out so that a part of the surface of the solder resist is apt to readily repel the under-fill material without using the dam groove or the dam frame to prevent the outflow of the under-fill material.
[Patent Document 1] JP-A-2000-164610
In the usual techniques for preventing the under-fill material from flowing out, a part having the under-fill material flowing out from a chip area cannot be used for connecting other parts than the chip. Accordingly, such techniques for preventing the outflow cause a factor of preventing a mounting with a higher density. Further, in the technique for treating the surface of the solder resist, an operation for applying another material or applying the laser is added.

Board having electronic parts mounted by using under-fill material and method for producing the same


A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

1. Technical Field
The invention relates generally to semiconductor integrated circuits, and more particularly to antifuse elements.
2. Background Art
In the field of semiconductor integrated circuits, it is generally known to construct fuse elements that can be programmed (either optically or electrically) to provide an electrical open circuit in a link that normally provides a conductive path when activated. Such elements are used for example to set a sequence of address bits for a redundant line of memory cells, or to set product information that is subsequently read when a system is first powered up.
It is also known to provide an "antifuse," which is a programmable element that provides a selective short circuit. This is typically done by providing a stimulus that decreases the resistance of a programmed element. See for example U.S. Pat. No. 5,242,851, "Programmable Interconnect Device and Method of Manufacturing Same," which teaches the use of a line of intrinsic polysilicon that decreases in resistance from 10G ohms to 500 to 100 ohms when programmed. In U.S. Pat. No. 5,557,136, "Programmable Interconnect Structures and Programmable Integrated Circuits," two titanium-tungsten layers are separated by amorphous silicon, which breaks down during programming to form a conductive filament where it is thinned. Selective silicide formation as an antifuse is taught in U.S. Pat. No. 6,051,851, "Semiconductor Devices utilizing Silicide Reaction." Conductor-filled vias as a programming element are taught in U.S. Pat. No. Re. 36,893, "Anti-Fuse Structure For Reducing Contamination of the Anti-Fuse Material."
A particular type of antifuse that has been used more recently is the "insulator antifuse," in which reliance is placed on dielectric breakdown of an insulator between conductors to provide the decreased resistance. U.S. Pat. No. 5,909,049, "Antifuse Programmed PROM Cell," discloses a composite insulator of oxide, oxide-nitride, oxide (or O—N—O) that breaks down at an applied voltage of 10–18 volts to program the cell by melting the silicon below the insulator. U.S. Pat. No. 6,020,777, "Electrically Programmable Antifuse Circuit," teaches a MOS capacitor that is programmed by Fowler-Nordheim tunneling current when the applied voltage is 2×Vdd.
All of the above teachings rely on high programming voltages or currents to substantially alter the physical or electrical properties of the programmed element. With increasing device integration, applying these high stresses to elements to be programmed increases the possibilities of damaging non-programmed circuit elements. For example, a programming voltage of 18 volts will impart electrical fields that will damage other integrated circuit elements in adjacent circuits. At the same time, it is important for the antifuse to undergo a large resistance change so that it can be reliably sensed.
Accordingly, a need has developed in the art for antifuses that can be programmed at lower applied programming energies, while still creating an indication of its programmed state.

International Business Machines Corporation


A capacity management system and method. The system includes a demand management module and a planning engine. The demand management module receives a demand comprising a request for a quantity of a device and a corresponding required date. The planning engine converts original planning buckets with varying bucket lengths into target planning buckets that have substantially identical bucket lengths. The planning engine further retrieves a cycle time of the device, and selects one of the target planning buckets accordingly. The planning engine also plans a capacity in the selected target planning bucket according to the quantity of the device.

The present disclosure relates generally to supply chain management, and, more particularly, to capacity management systems and methods using planning buckets with substantially identical bucket length.
In the supply of products, the supply chain performs the functions of material purchasing, transformation of materials into intermediate and finished products, and distribution of finished products to clients. Supply chain management has become important in meeting the goals of reduced inventory, increased productivity, and enhanced competitiveness. Manufacturing and distribution facilities have limited resources and capacity, hence, not every client request may be met. For example, some requests may be promised but unfulfilled, some clients may receive inadequate supply, and other requests may be rejected. Consequently, effective management of capacity in supply chain management, without excess capacity loss, has become an important aspect for a product supplier who needs to control manufacture or distribution.
In the supply chain, clients transmit demands to a supplier. The demand may include a request for a particular quantity of a device by a specific date. The supplier plans its internal or external manufacturing schedule according to these received demands, and allocates capacity for manufacturing products to satisfy each client. After receiving orders corresponding to demands from clients, the supplier starts to manufacture the products.
Conventionally, a planning approach divides a continuous planning horizon into discrete time buckets, such as months, and plans capacity for respective time buckets. For example, in FIG. 1, if a demand D for a device is specified in time bucket TB4 and a cycle time for the device is 2 time buckets, the planning bucket containing a capacity consumption point for the demand D falls in time bucket TB2, and a capacity C is consumed for the demand D.
Since bucket lengths vary from month to month, however, if two substantially identical demands are specified in different time buckets, the planning buckets must be determined according to corresponding bucket lengths, thereby causing irregular plan results. For example, FIG. 2A illustrates an example wherein the time buckets are determined according to calendar month, and each month (January through July) has a demand (D1˜D7) for a device having a 29-day cycle time. The corresponding capacity consumption points (CP1˜CP7) for respective demands are illustrated in FIG. 2B. Since the bucket length of February is 28 days, the capacity consumption point CP2 for demand D2 falls in January, and the specified capacity in January comprises capacity C1 for demand D1 and capacity C2 for demand D2 as shown in FIG. 2C. In the example, the plan result is irregular, and the same situation will occur as the cycle time is about multiples of 30 days (e.g., 29, 30, 31, 59, 60, 61, 89, 90, 91, etc). Expected capacity consumption, however, should be balanced and smooth for all planning buckets to facilitate effective long-term planning. The conventional mechanism, however, is unable to generate smooth capacity consumption results for capacity management.

Taiwan Semiconductor Manufacturing Co., Ltd.