When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true. The result of logical sum is used as matched data logical-OR information. In a primary searching operation, the associative memory (1) is supplied with the search data (12) to provide the matched data logical-OR information on matched data logical-OR lines. Then, the associative memory (1) carries out a secondary searching operation supplied as search data with the matched data logical-OR information obtained by all of storage data coincident upon the primary searching operation. Only a match line (5) coincident with the matched data logical-OR information is selected as the secondary search result. The associative memory is used in a network router to calculate an optimum memory address signal (403) by encoding the selected match line (5). In response to the memory address signal (403), a memory data signal (405) enabling shortest network connection is produced as a transfer network address (413). The transfer network address (413) is combined with a data area (412) and a destination network address (411) contained in input transfer data (408) to produce output transfer data (409).

The function that calculates the optimum transfer route is indispensable to a conventional network router (hereinafter simply called a router) in a computer network system, as follows.
Referring to FIG. 19, a conventional computer network will be described. A user or subscriber of the network has a user's terminal, such as a computer terminal, for connection to the network. A user's terminal is assigned with a specific network address in accordance with a predetermined rule when it is connected to the network in order to be distinguished from other user's terminals. Herein, the network address is represented by a numeral of a plurality of digits of, for example, first through fourth digits (a, b, c, d). The predetermined rule defines a hierarchical structure of the network address. The predetermined rule defines a hierarchical structure of the network address. For example, the first digit of the numeral represents a nation, such as England, Germany, and Japan. The second digit of the numeral represents a city in the nation, and the third digit of the numeral represents a company name in the city. In the following description, these hierarchical items will be called segments. Referring to FIG. 19, each segment is depicted by a rectangular block. Specifically, the network includes a first segment (SEGMENT1), second segment (SEGMENT2), and a third segment (SEGMENT3) at a highest hierarchical level. The first segment (SEGMENT1) and the second segment (SEGMENT2) include a fourth segment (SEGMENT4) and fifth segment (SEGMENT5), respectively. The fourth segment (SEGMENT4) and the fifth segment (SEGMENT5) include a sixth segment (SEGMENT6) and a seventh segment (SEGMENT7), respectively. A user's terminal (PC) 401-1 exists in the sixth segment. The first segment has a network address (1, *, *, *) in which a first digit alone is specified as "1". The fourth segment subordinate to the first segment has a network address (1, 2, *. *) in which first and second digits "1" and "2" are specified. The sixth segment subordinate to the fourth segment has network address (1, 2, 2, *) in which first through third digits "1", "2", and "2" are specified. Thus, the user's terminal 401-1 in the sixth segment has a specific or unique network address (1, 2, 2, 1). The second segment has a network address (2, *, *, *) in which a first digit alone is specified as "2". The fifth segment subordinate to the second segment has a network address (2, 1, *, *) in which first and second digits "2" and "1" are specified. The seventh segment subordinate to the fifth segment has network address (2, 1, 1, *) in which first through third digits "2", "1", and "1" are specified. A symbol "*" contained in these addresses represents "don't care".
In order to connect or establish communication between a plurality of user's terminals in the network, each segment is provided with a router. As illustrated in FIG. 19, the first segment is provided with the first router 400-1, the second segment is provided with the second router 400-2, the third segment is provided with the third router 400-3, the forth segment is provided with the forth router 400-4, the fifth segment is provided with the fifth router 400-5, the sixth segment is provided with the sixth router 400-6, and the seventh segment is provided with the seventh router 400-7. Each router in the corresponding segment is supplied from any user's terminals or any routers connected to the router with transfer data and a transfer address annexed thereto. With reference to the transfer address and the relationship of connection of network apparatuses, the router calculates an optimum transfer route and transfers the transfer data via the optimum transfer route thus calculated. As illustrated in FIG. 19, each router is connected to any user's terminals or any routers subordinate to the corresponding segment. In addition, the third router 400-3 is connected Lo the router 400-1, the router 400-4, the router 400-6, the router 400-2, and router 400-7.
The user's terminals are not directly connected by the use of the communication channels but carry out communication by controlling the transfer of communication data by the use of communication control functions of the routers. Thus, communication channels as limited resources are saved.
Next referring to FIG. 20, the third router 400-3 will be described by way of example. Other routers have a similar structure. The third router 400-3 memorizes, as network address information or data, the network addresses for the segments except the third segment to which the third router 400-3 belongs. Each digit of each network address is represented by a binary number of two bits. Thus, each network address is represented by a bit sequence of eight bits in total. For example, a network address (1, *, *, *) is represented by a bit sequence (01, 00, 00, 00). Hereinafter a bit sequence represented as above-mentioned representation is called a storage data. Since the symbol "*" represents "don't care" for each of second through fourth digits, it is necessary to indicate that the first and the second bits (01) in the bit sequence (01, 00, 00, 00) alone are valid and the remaining bits (00, 00, 00) are invalid. For this purpose, mask information (or mask data) is combined with the storage data. In the illustrated example, the mask information (or mask data) is given by a bit sequence (00, 11, 11, 11). Herein, "0" and "1" represent a mask invalid state and a mask valid state, respectively. In the third router 400-3, the storage data or data and the mask information are stored in an associative memory 116, as illustrated in FIG. 20. The first associative memory word 117-1 stores the network address (1, *, *, *) for the segment 1 to which the router 400-1 belongs. The second associative memory word 117-2 stores the network address (2, *, *, *) for the segment 2 to which the router 400-2 belongs. The third associative memory word 117-3 stores the network address (1, 2, 2, *) for the segment 6 to which the router 400-6 belongs. The fourth associative memory word 117-4 stores the network address (1, 2, *, *) for the segment 4 to which the router 400-4 belongs. The fifth associative memory word 117-5 stores the network address (2, 1, 1, *) for the segment 7 to which the router 400-7 belongs. The associative memory 116 has searching (or retrieving) function or mask searching function in addition to write/read functions of writing and reading storage data (namely, the address data) at a designated memory address in the matter similar to an ordinary memory circuit. Specifically, The associative memory 116 has the mask searching function to put the only mask match line 119 corresponding to the storage data with the least number of bits in a mask valid state, in the mask match lines 119 corresponding to one of the storage data coincident with the search data 102 taking the mask information into account, into a valid state. The encoder 402 encodes the mask match lines 119-1 through 119-5 that the associative memory 116 supplies into a memory address signal 403.
The memory 404 stores network addresses of the routers 400 corresponding to the segment network addresses each of which comprises the storage data and the mask information and each of which is stored in each associative memory word 117 of the associative memory 116. In the memory 404, each router network address is memorized in a word corresponding to the associative memory word 117 of the associative memory 116 where a corresponding network address is memorized. For example, the network address (1, *, *, *) is stored in the first associative memory word 117-1 of the associative memory 116 while the router network address of the router 400-1 (FIG. 19) corresponding thereto is stored in the first word of the memory 404. Similarly, the network address of the router 400-2, the network address of the router 400-6, the network address of the router 400-4, and the network address of the router 400-7 are stored in the second word, the third word, the fourth word, and fifth word of the memory 404, respectively. Supplied with the memory address signal 403 as a read address, the memory 404 produces a memory data signal 405 stored in the word designated by the memory address signal 403.
A cooling apparatus 414 cools the conventional associative memory 116 with large generation of heat. The cooling apparatus 414 can consist of for example, an air-cooling fan.
Although not illustrated in the figure, each router has a CPU for controlling the above-mentioned operation of the router.
Next, description will be made about a sending data operation in the conventional network controlled by the routers. It is assumed here that the transfer data supplied to the router 400-3 have a destination network address (1, 2, 1, 1). As a result of search by the associative memory 116, (1, *, *, *) in the first associative memory word 117-1 and (1, 2, *, *) in the fourth associative memory word 117-4 are coincident. Among those coincident network addresses, the network address (1, 2, *, *) in the fourth associative memory word 117-4 has the least number of bits in a mask valid state so that only the mask match line 119-4 corresponding to the fourth associative memory word 117-4 is put into a valid state. Therefore, the encoder 402 produces "4" as the memory address signal 403. In response to the memory address signal 403, the memory 404 produces as the memory data signal 405 the network address for the router 400-4. Consequently, the router 400-3 transfers the input transfer data having the destination network address (1, 2, 1, 1) to the router 300-4. The router 300-4 is responsive to the transfer data and performs the operation similar to that mentioned above. Thus, the transfer data are successively transferred from router to router until the user's terminal at the destination network address (1, 2, 1, 1) is reached.
Herein, referring to FIG. 15, a typical conventional associative memory will be described. As disclosed in Japanese Unexamined Patent Publication (JP-A) No. 11-073782 (073782/1999), an associative memory 116 comprises a two-input/one-output n-bit selector 128, first through m-th n-bit associative memory words 117, an n-bit latch 21, and a controller 131. Each associative memory word 117-j (where j is and integer variable between 1 and m, both inclusive) comprises first through n-th associative memory cells 118-j-1 through 118-j-n and a latch 123-j. Each of the associative memory words 117-j is connected to the corresponding data word line 106-j and the corresponding mask word line 111-j as input lines and to the corresponding mask match line 119-j and the first through the n-th shortest mask lines 122 as output lines and to the first through the n-th bit lines 103 as data input/output lines.
Each of the associative memory cells 118-j-k (where k is and integer variable between 1 and n, both inclusive) is connected to the corresponding data word line 106-j and the corresponding mask word line 111-j as input lines, and to the corresponding data match line 107-j, the corresponding mask match line 119-j, and the corresponding shortest mask line 122-k as output lines, and to the corresponding bit line 103-k as data input/output line.
Each associative memory cell 118-j-k comprises a data cell 108-j-k, a comparator 113-j-k, a mask cell 112-j-k, a mask comparator 120-j-k, and logical gate 121 -j-k. The data cell 108-j-k is for storing "data" bit information at a corresponding bit of storage data supplied from an external source through a bit line 103-k. The comparator 113-j-k is for comparing the "data" bit information memorized in the data cell 108-j-k and "search" bit information 102-k at a corresponding bit of search data supplied from the external source. The mask cell 112-j-k is for storing "mask" bit information of a corresponding bit of mask information supplied from the external source through the bit line 103-k. The mask comparator 120-j-k is for comparing the "mask" bit information memorized in the mask cell 112-j-k and "shortest mask" bit information 127-k at a corresponding bit of shortest mask information produced from the n-bit latch 126.
In this example, a valid state and an invalid state are represented by "1" and "0", respectively, for all of the mask information, the shortest mask lines 122-1 through 122-n, the data match lines 107-1 through 107-m, and the mask match lines 119-1 through 119-m.
The data cell 108 stores as the storage data the state on a corresponding bit line 103 on which the write data is driven when a corresponding data word line 106 is in a valid state, or supplies the storage data stored therein to the corresponding bit line 103 on which the write data is not driven when a corresponding data word line 106 is in a valid state. When the corresponding data word line 106 is in an invalid state, no operation is performed for the corresponding bit line 103. Irrespective of the state of the corresponding data word line 102, the storage data stored therein is supplied to the comparator 113 in the same associative memory cell 118.
The mask cell 112 stores as the mask information the state on a corresponding bit line 103 on which the write data is driven when a corresponding mask word line 111 is in a valid state, or supplies the mask information stored therein to the corresponding bit line 103 on which the write data is not driven when a corresponding mask word line 111 is in a valid state. When the corresponding mask word line 111 is in an invalid state, no operation is performed for the corresponding bit line 103. Irrespective of the state of the corresponding mask word line 111, the mask information stored therein is supplied to the comparator 113 in the same associative memory cell 118.
Prior to the start of the searching operation, the data match line 107 is precharged to a high level or pulled up by a resistor (not shown) to be put into a valid state "1".
The comparator 113 is supplied with the value of the search data on the corresponding bit line 103, the storage data stored in the data cell 108 in the same associative memory cell 118, and the mask information stored in the mask cell 110 in the same associative memory cell 118. When the mask information is in a valid state or when the value on the corresponding bit line 103 and the storage data stored in the data cell 108 are coincident with each other, the data match line 107 is put into an opened state. Otherwise, the comparator 113 puts the data match line 107 into an invalid state "0". Thus, the wired AND logic connection is achieved such that, when all of the comparator 113, n in number, in the associative memory word 117 render the data match line 107 in an opened state, the data match line 107 is out into a valid state "1" and otherwise into an invalid state "0". In other words, upon the searching operation, only when all of the storage data stored in an associative memory word 117 is completely coincident with the bit lines 103-1 through 103-n except those bits excluded from a comparison object by the corresponding mask information, the data match line 107 is put into a valid state "1" and otherwise into an invalid state "0". Alternatively, an ordinary logical gate may be used as far as the similar operation is performed.
The logical gate 121 supplies an invalid state "0" to the shortest mask line 122 when the data match line 107 in the same associative memory word 117 is in a valid state "1" and the mask information stored in the corresponding mask cell 112 is in an invalid state "0". Otherwise, the logical gate 121 puts the shortest mask line 122 into an opened state.
Each of the shortest mask line 122-1 through 122-n is pulled up by a corresponding register 125 to be put into a valid state "1". The shortest mask line 122-k (where k is and integer variable between 1 and n, both inclusive) is connected to all of the corresponding logical gates 121-1-k through 121-m-k, m in number, by a wired AND logic connection. Thus, when all of the first though m-th logical gates 121 connected to the corresponding shortest mask line 122 render the shortest mask line 122 in an opened state, the shortest mask line 122 is put into a valid state "1" and otherwise into an invalid state "0".
The latches 123-1 though 123-m store the states of the data match lines 107-1 through 107-m in the associative memory words 117-1 through 118-m as stored states, respectively, when latch control signal 124 is in valid state. In order to produce the stored states, each latch 123 is connected to the mask match line 119 in the same associative memory word 117 by the wired logic connection. The latches 123-1 through 123-m supply to the corresponding mask match lines 119-1 through 119-m with an invalid state "0" when the stored data have an invalid state "0", respectively, and put the corresponding mask match lines 119-1 through 119-m into an opened state when the stored data have a valid state "1".
Upon completion of the searching operation, only one of the mask match lines 119-1 through 119-m is put into a valid state while the others are put into an invalid state. The mask match line 119 put into a valid state corresponding to one of the storage data coincident with the search data 102 which has the least number of bits excluded from the search object by the mask information. Each of the mask match lines 119-1 through 119-m are pulled up by a resistor (not shown) prior to start of the searching operation or precharged to a high level to be put into a valid state "1".
Each of the mask comparator 120 compares the state of the mask information stored in the corresponding mask cell 112 and the shortest mask information on the corresponding bit line 103. Upon coincidence, the mask comparator 120 puts the corresponding mask match line 119 into an opened state. Upon incoincidence, the mask comparator 120 supplies an invalid state "0" to the corresponding mask match line 119. Thus, the wired AND logic connection is achieved such that, when all of the associative memory calls 118, n in number, and the latch 123 in the same associative memory word 117 render the mask match line 119 in an opened state, the mask match line 119 is put into a valid state "1" and otherwise into an invalid state "0".
In other words, upon the searching operation, only when the mask information stored in the associative memory word 117 is completely coincident with the bit lines 103-1 through 103-n and the state of the data match line 107 stored in the latch 123 is a valid state "1", the mask match line 119 is put into a valid state "1" and otherwise into an invalid state "0". The n-bit latch 126 stores the states of the shortest mask lines 122-1 through 122-n as stored states when a latch control signal 124 is in a valid state. The n-bit latch 126 supplies the stored states to the latch output lines 127-1 through 127-n.
With reference to the state of a selection signal 129, the two-input/one-output n-bit selector 128 selects, as output data to be supplied to the bit lines 103-1 through 103-n, either the search data 102-1 through 102-n or latch output lines 127-1 through 127-n.
The controller 130 supplies a latch control signal 124 and a selection signal 129 synchronizing with a clock signal 130, in order to control operation of the associative memory 116.
Next referring to FIG. 16, the associative memory cell 118 will be described. Two bit lines 103a and 103b correspond to each bit line 103 illustrated in FIG. 15. In FIG. 15, each single bit line 103-i collectively represents these bit lines 103a and 103b. Through the two bit lines 103a and 103b, writing and reading of the data into and from the memory cell and the input of the search data 102 are carried out. Upon writing the data or the input of the search data 102, the bit line 103b is supplied with an inverted value of a value on the bit line 103a. The data call 108 is a typical SRAM (Static Random Access Memory) comprising inverted logical gates (G101 and G102) 301 and 302 with one's input and output terminals connected to the other's output and input terminals, respectively, a MOS (Metal Oxide Semiconductor) transistor (T101) 303 connecting the output terminal of the inverted logical gate (G102) 302 to the bit line 103a and rendered conductive when the data word line 106 has a high level, and a MOS transistor (T102) 304 connecting the output terminal of the inverted logical gate (G101) 301 to the bit line 103b and rendered conductive when the data word line 106 has the high level.
The mask cell 112 is also a typical SRAM comprising inverted logical gates (G103 and G104) 309 and 310 with one's input and output terminals connected to the other's output and input terminals, respectively, a MOS transistor (T107) 311 connecting the output terminal of the inverted logical gate (G104) 310 to the bit line 103a and rendered conductive when the mask word line 111 has ha high level, and a MOS transistor (T108) 312 connecting the output terminal of the inverted logical gate (G103) 309 to the bit line 103b and rendered conductive when the mask word line 111 has the high level.
The comparator 113 comprises a MOS transistor (T103) 305, a MOS transistor (T104) 306, a MOS transistor (T105) 307, and a MOS transistor (T106) 308. The MOS transistor (T103) 305 and the MOS transistor (T104) 306 are inserted between the bit lines 103a and 103b in cascade. The MOS transistor (T103) 305 is rendered conductive when the inverted logical gate (G101) 301 in the data cell 108 produces an output of a high level. The MOS transistor (T104) 306 is rendered conductive when the inverted logical gate (G102) 302 in the data cell 108 produces an output of a high level. The MOS transistor (T105) 307 and the MOS transistor (T106) 308 are connected between a low potential and the data match line 107 in cascade. The MOS transistor (T105) 307 is rendered conductive when a junction or node of the MOS transistor (T103) 305 and the MOS transistor (T104) 306 has a potential of a high level. The MOS transistor (T106) 308 is rendered conductive when the inverted logical gate (G103) 309 in the mask cell 112 produces an output of a high level. When both the bit line 103a and the inverted logical gate (G101) 301 produce outputs of a high level or when both the bit line 103b and the inverted logical gate (G102) 302 produce outputs of a high level, the junction of the MOS transistor (T103) 305 and the MOS transistor (T104) 306 has a high level to render the MOS transistor (T105) 307 conductive.
Therefore, when the storage data stored in the data cell 108 and the search data 102 on the bit lines 103a and 103b are different from each other, the MOS transistor (T105) 307 is rendered conductive. The MOS transistor (T106) 308 is put into an opened state and conductive state when the mask information stored in the mask cell 112 is "1" and "0", respectively. The data match line 107 is pulled up to a high potential by the resistor (not shown) or precharged to a high potential prior to the start of the searching operation. This provides the wired AND connection such that, when a plurality of the associative memory calls 118 are connected to the data match line 107 through the MOS transistors (T106) 308, the data match line 107 is given a low level if at least one associative memory cell 118 produces an output of a low level.
When both the MOS transistor (T105) 307 and the MOS transistor (T106) 308 are conductive, the associative memory cell 118 supplied an invalid state "0" to the data match line 107. Otherwise, the data match line 107 is put into an opened state. Specifically, when the mask information is "1", the data match line 107 is put into an opened state. When the mask information is "0", the data match line 107 is put into an opened state and supplied with an invalid state "0" when the search data 102 on the bit lines 103a and 103b and the storage data stored in the data cell 108 are coincident with each other and different from each other, respectively.
Next, the logical gate 121 and the shortest mask line 122 will be described. The shortest mask line 122 is pulled up by a register 125 (FIG. 15) to be put into a valid state "1" prior to a searching operation. The logical gate 121 comprises MOS transistors (T109 and T110) 313 and 314 connected in cascade between the shortest mask line 122 and a low potential. The MOS transistor (T109) 313 is put into a conductive state and an opened state when a data match line 107 is in a valid state "1" and an invalid state "0", respectively. The MOS transistor (T110) 314 is put into a conductive state and an opened state when an inverted logical gate (G103) 309 in the mask cell 112 produces an output of a high level and a low level, respectively, i.e., when the mask information stored in the mask cell 112 is in an invalid state "0" and a valid state "1", respectively. Thus, the logical gate 121 supplies an invalid state "0" to the shortest mask line 122 when the data match line 107 is in a valid state "1" and the mask information stored in the mask cell 112 is in an invalid state "0". Otherwise, the logical gate 121 puts the shortest mask line 122 into an opened state.
Next, description will proceed to the operation of the mask comparator 120 and the mask match line 119. The mask match line 119 is pulled up to a high potential by a resistor (not shown) or precharged to a high potential prior to the searching operation. The mask comparator 120 comprises MOS transistors (T111, T112, and T113) 315, 316, and 317. The MOS transistors (T111 and T112) 315 and 316 are connected in cascade between the bit lines 103a and 103b. The MOS transistor (T111) 315 is put into a conductive state when the inverted logical gate (G103) 309 in the mask cell 112 produces an output of a high level. The MOS transistor (T112) 316 is put into a conductive state when an inverted logical gate (G104) 310 in the mask cell 112 produces an output of a high level. The MOS transistor (T113) 317 is connected between a low potential and the mask match line 119. The MOS transistor (T113) 317 is put into a conductive state when a junction or node of the MOS transistor (T111) 315 and the MOS transistor (T112) 316 has a potential of a high level.
When both the bit line 103a and the inverted logical gate (G103) 309 produce outputs of a high level or when both the bit line 103b and the inverted logical gate (G104) 310 produce outputs of a high level, the junction of the MOS transistor (T111) 315 and the MOS transistor (T112) 316 has a potential of a high level so that the MOS transistor (T113) 317 is put into a conductive state. Otherwise, the MOS transistor (T113) 317 is out into an opened state.
Therefore, when the mask information stored in the mask cell 112 is different form the search data 102 on the bit lines 103a and 103b, the MOS transistor (T113) 317 is put into a conductive state to supply an invalid state "0" to the mask match line 119. Upon coincidence, the mask match line 119 is put into an opened state.
Thus, a wired AND connection is achieved such that, when at least one of the associative memory cells 118 connected through the MOS transistor (T113) 317 to the mask match line 119 produces a low level, the mask match line 119 is given a low level and otherwise a high level.
Next referring to FIG. 17, description will be made about the operation when the above-mentioned conventional associative memory 116 is used in calculating the transfer network address in the router 400-3 in FIG. 19. Referring to FIG. 18, this operation will be described by the use of a timing chart. It is assumed here that the associative memory 116 comprises five words of eight bits. Therefore, the storage data and the mask information stored in each of the associative memory words 117-1 through 117-5 are quite similar to those of the associative memory 116 in FIG. 20. The associative memory 116 memorizes the connection information except the network address (3, *, *, *) of the router 400-3 in FIG. 19. Specifically, the associative memory word 117-1 stores in binary numbers the storage data (01, 00, 00, 00) and the mask information (00, 11, 11, 11) to implement (1, *, *, *) Likewise, the associative memory words 117-2, 117-3, 117-4, and 117-5 stores (2, *, *, *), (1, 2, 2, *), (1, 2, *, *), and (2, 1, 1, *), respectively.
Description will proceed to the searching operation by supplying as the search data 102 the network address (1, 2, 2, 1), in quadridecimal numbers, of the user's terminal (PC) 401-1 in FIG. 19.
At first, all of the data match lines 107-1 through 107-8 are precharged to a high level ("1") to be put into a valid state "1" at the timing (1) in FIG. 18. Next, the two-input/one-output 8-bit selector 128 is responsive to the selection signal 129 which the controller 131 supplies, and selects the search data 102 to deliver the search data 102 to the bit lines 103-1 through 103-8 at the timing (2) in FIG. 18. Therefore, the quadridecimal notations (1, *, *, *), (1, 2, 2, *) and (1, 2, *, *) respectively stored in the associative memory words 117-1, 117-3 and 117-4 in the associative memory 116 are coincident with the search data 102 on the bit lines 103. Accordingly, the data match lines 107-1, 107-3 and 107-4 are put into a valid state "1" while the remaining data match lines 107-2, and 107-5 are put into an invalid state "0".
Herein, the shortest mask line 122-1 produces the logical product "0" of the mask bit information "0", "0" and "0" in the associative memory words 117-1, 117-3 and 117-4 at bit positions corresponding to the shortest mask line 122-1. The shortest mask line 122-2 produces the logical product "0" of the mask information "0", "0" and "0" in the associative memory words 117-1, 117-3 and 117-4 at bit positions corresponding to the shortest mask line 122-2. Likewise, the shortest mask lines 122-3, 122-4, 122-5, 122-6, 122-7, and 122-8 produce the logical product "0" of "1", "0" and "0", the logical product "0" of "1", "0" and "0", the logical product "0" of "1", "0" and "1", the logical product "0" of "1", "0" and "1", the logical product "1" of "1", "1" and "1", and the logical product "1" of "1", "1" and "1", respectively. As a result, the binary notation "00000011" is delivered to the shortest mask lines 122-1 through 122-8. In this state, the latch control signal 124 that the controller 131 supplies is put into valid state. The latches 123-1 through 123-5 store the states of the corresponding match lines 107-1 through 107-5, respectively, while the n-bit latch 126 stores the states of the shortest mask lines 122-1 through 122-8. Accordingly, the latches 123-1, 123-2, 123-3, 123-4, and 123-5 store "1", "0", "1", "1", and "0", respectively, while the n-bit latch 126 stores the binary notation "00000011". The n-bit latch 126 delivers the stored state "00000011" to the latch output line 127-1 through 127-8.
Next, at the timing (3) in FIG. 18, all of the mask match lines 119-1 through 119-8 are precharged to a high level to be put into a valid state "1".
At the timing (4) in FIG. 18, in response to the selection signal 129 which the controller 131 supplies, the two-input/one-output 8-bit selector 128 selects the latch output line 127 and supplies the information "00000011" on the latch output line 127 to the corresponding bit lines 103-1 through 103-8. Thereafter, the associative memory 116 starts a second searching operation. In the second searching operation, use is made of the states of the mask match lines 119-1 through 119-8 while the states of the data match line 107-1 through 107-8 are ignored.
The mask information stored in each of the associative memory words 117-3 and 117-5 is completely coincident with the states "00000011" on the bit lines 103-1 through 103-8 so that the corresponding mask match lines 119-3 and 119-5 are put into an opened state. Since the mask information stored in any other associative memory words 117-1, 117-2, and 117-4 is not coincident, the corresponding mask match lines 119-1, 119-2, and 119-4 are supplied with an invalid state "0".
The latch 123-1 puts the corresponding mask match line 119-1 into an opened state because the stored state is "1". The latch 123-2 delivers the stored state "0" to the corresponding mask match line 119-2. The latch 123-3 puts the corresponding mask match line 119-3 into an opened state because the stored state is "1". The latch 123-4 puts the corresponding mask match line 119-4 into an opened state because the stored state is "1". The latch 123-5 delivers the stored state "0" to the corresponding mask match line 119-5.
Therefore, the mask match line 119-1 is put into an invalid state "0" because the mask comparators 120-1-1 through 120-1-8 of the associative memory word 117-1 produce "0" although the latch 123-1 is in an opened state. The mask match line 119-2 is put into an invalid state "0" because the mask comparators 120-2-1 through 120-2-8 of the associative memory word 117-2 produce "0" and the latch 123-2 produces "0". The mask match line 119-3 maintains a valid state "1" because the mask comparators 120-3-1 through 120-3-8 of the associative memory word 117-3 are in an opened state and the latch 123-3 is in an opened state. The mask match line 119-4 is put into an invalid state "0" because the mask comparators 120-4-1 through 120-4-8 of the associative memory word 117-4 produce "0" although the latch 123-4 is in an opened state. The mask match line 119-5 is put into an invalid state "0" because the mask comparators 120-5-1 through 120-5-8 of the associative memory word 117-5 are in an opened state although the latch 123-5 produces "0".
Consequently, only one of the mask match line 119-1 through 119-5 corresponding to a particular one the associative memory words 117-1 through 117-5 is in a valid state "1" upon completion of the second searching operation at the timing (4). Specifically, the storage data preliminarily stored in the particular associative memory word (117-3 in the illustrated example) is selected in the first search operation as coincident with the search data 102 taking the mask information into account while the mask information preliminarily stored is selected in the second searching operation as coincident with the states of the shortest mask lines 122-1 through 122-8 obtained by the first searching operation at the timing (2). It will therefore be understood that, in the mask match lines 119 corresponding Lo one of the storage data coincident with the search data 12 taking the mask information into account, the only mask match line 119-3 corresponding to the storage data with the least number of bits in a mask valid state is put into a valid state.
As described above, the associative memory 116 supplies the comparison result of the search data 102 and the storage data stored in the first through m-th associative memory words 117 to the first through the data match lines 107 upon the first searching operation, and supplies the comparison result of the value on the latch output line 127 and the mask information stored in the first through m-th associative memory words 117 to the first through the match lines 107 upon the second searching operation. For this purpose, the associative memory cell 118, n in number, in the each of the first through m-th associative memory word 117 the requires two kinds of comparing means, comparators 113 comparing the storage data and mask comparators 120 comparing the mask information.
Herein, when it is assumed that each of the inverted logical gates comprises two MOS transistors, the associative memory cell 118 comprises 18 MOS transistors as readily understood from FIG. 16. Since both the data cell 108 and the mask cell 112 are typical SRAMs, the circuit area of each transistor comprising these is similar to the circuit area of the minimum MOS transistor, in general.
However, as illustrated in FIG. 15, each of the data match lines 107-1 through 107-m is connected to the first through n-th comparator 113 in the corresponding associative memory word 117 by a wired AND logic connection so that the data match line 107 requires enough length to achieve this connection. Thus, the parasitic capacitance of each of the data match lines 107-1 through 107-m is very large so that the MOS transistors that composes the comparator 10 and the logical gate 11 require large circuit area in order to drive the large parasitic capacitances of each of the data match lines 107. For example, in case of 0.25 micron meter rule manufacturing process, the wiring length is required about 1 millimeter in order to connect to 64 comparators, so that the parasitic capacitance of each data match line 107 is about 0.3 pF. Accordingly, the size of each transistor that drives above-mentioned capacitance requires about 10 to 30 times as large as the size of the minimum transistor for the manufacturing process. Likewise, each of the mask match lines 119-1 through 119-m is connected to the first through n-th mask comparator 120 by a wired AND logic connection so that the size of each transistor that composes the mask comparator 120 requires about 10 to 30 times as large as the size of the minimum transistor for the manufacturing process. In the meanwhile, as illustrated in FIG. 15, each of the shortest mask lines 122-1 through 122-n is connected to the first through m-th logical gates 121 by a wired AND logic connection so that the shortest mask lines 122 requires enough length to achieve this connection. Thus, the size of each transistor that composes the logical gate 121 requires about 10 to 30 times as large as the size of the minimum transistor for the manufacturing process.
Herein, it is assumed that the circuit area of each MOS transistor that composes the comparator 113, the mask comparator 120, and the logical gate 121 is 10 times as the circuit area of the minimum MOS transistor and the circuit area of a typical SRAM is 6 times as the circuit area of the minimum MOS transistor. Accordingly, as readily understood from FIG. 16, the circuit area of the associative memory cell 118 is 102 times as the circuit area of the minimum MOS transistor, in other words, the conventional associative memory 116 has only 1/17 of the storage capacity in comparison with a SRAM that has the same chip area.
As described above, the data match lines 107-1 through 107-m are supplied with the comparison result upon the first searching operation, and the mask match lines 119-1 through 119-m are supplied with the comparison result upon the second searching operation. Therefore, the conventional associative memory requires maintaining the comparison result of the first searching operation until the start of the second searching operation. Herein, if the associative memory 116 comprises the first through 32768th 64-bit associative memory words and the latch 123 comprises 10 MOS transistors, about 330,000 transistors are required in order to compose the latch 123, 32,768 in number. In other words, irrespective of number of bits of the storage data, the chip area of the conventional associative memory increases by a circuit area of the latch 123-1 through 123-m, m in number.
In the meanwhile, each of the data match lines 107-1 through 107-m, m in number, and the mask match lines 119-1 through 119-m, m in number, except one mask match line that is put into a valid state upon completion of the searching operation, discharge the charge that is precharged thereto through the corresponding MOS transistor for every searching operation. Therefore, if the associative memory comprises the first through 32768th 64-bit associative memory words, the parasitic capacitance corresponding to 65,535 lines requires being precharged, as given by 32,768×2−1=65,535. The parasitic capacitance of the shortest mask lines 122-1 through 122-n is negligible because the shortest mask lines 122-1 through 122-n are n in number. In other words, power consumption of the conventional associative memory mainly comprises the power that is consumed when the data match lines 107 and mask match lines 119 are precharged for every searching operation. Herein, it is assumed that each parasitic capacitance of the data match line 107 and mask match line 119 is 0.3 pF, and that the supplied voltage is 2.5V, and that the period of the clock signal 130 is 20 ns. Accordingly, as described above, in case of 0.25 micron meter rule manufacturing process, the power consumption of the whole chip is very large as given by (0.3 pF×2.5V)×2.5V/20 ns×65,535=6.1 W. Therefore, since each of the data match lines 107-1 through 107-m, m in number, and the mask match lines 119-1 through 119-m, m in number, except one mask match line that is put into a valid state upon completion of the searching operation, requires being precharged to be out into a valid state Prior to the start of every searching operation, the conventional associative memory has very large power consumption.
As described above, the conventional router requires a plurality of the associative memory 116 since the storage capacity of the associative memory 116 is small. Therefore the conventional router generates a large amount of heat so that the cooling apparatus 414 is requires as illustrated in FIG. 20. Further, the data transfer rate decreases since the conventional router requires comparing to the results of the searching operation supplied from a plurality of the associative memory in order to calculate the final result of the searching operation.
It is therefore an object of this invention to provide an associative memory which produces the signal identifying, among the storage data coincident with the search data, particular storage data corresponding to the mask information with the least number of bits in a valid state, and has large storage capacity per unit of chip area.

Associative memory having a mask function for use in a network router


A current direction detection circuit includes a monitoring transistor having a control terminal and an output terminal respectively connected with a control terminal and an output terminal of a ground side output transistor; an impedance element having one terminal connected with an input terminal of the monitoring transistor and the other terminal grounded; first and second constant-current sources; a diode-connected reference transistor interposed between the first constant-current source and ground potential; and a sensing transistor interposed between the second constant-current source and the impedance element and having a control terminal connected with the control terminal of the reference transistor. The current direction detection circuit is small yet capable of minimizing power loss of a switching regulator.

1. Field of the Invention
The present invention relates to a current direction detection circuit that, when reverse direction current flows in a ground side output transistor, is capable of detecting the flow of current, and relates to a switching regulator including the current direction detection circuit.
2. Description of the Related Art
A switching regulator is provided with a power source side output transistor, that defines a main switching element, between a terminal that inputs power and a terminal that is connected with the load and outputs a predetermined DC voltage, and maintains a predetermined DC voltage by turning on/off (conductive/non-conductive) the power source side output transistor. Such regulators are of small size and are capable of achieving high power efficiency and thus are widely used. In recent years, synchronous rectifying switching regulators have been used (see, for example, Japanese Patent Application Laid-open No. 2000-92824), in which a ground side output transistor is additionally provided, defining a synchronous rectifying switching element. Such synchronous rectifying switching regulators make it possible to further improve power efficiency.
FIG. 3 shows the layout of a conventional synchronous rectifying switching regulator. The switching regulator 101 includes a power source side output transistor 111 defined by a P type MOS transistor and a ground side output transistor 112 defined by an N type MOS transistor connected in series between the input power source VCC and ground potential; a smoothing circuit 113 whose input terminal is connected to a point between the two transistors 111, 112 and whose output terminal is connected with the output terminal OUT, respectively; a regulator control circuit 115 that outputs a control signal A and control signal B that perform on/off control of the power source side output transistor 111 and ground side output transistor 112 so as to maintain a predetermined DC voltage in response to feedback input of the voltage of the output terminal OUT; a current direction detection circuit 116 that, when reverse direction current flows in the ground side output transistor 112, detects the reverse direction current and outputs a control signal F; and a ground side output transistor control circuit 117 that outputs an output signal C for controlling the ground side output transistor 112 in accordance with the control signal B and control signal F. In this case, a load 114 is connected at the outside to the output terminal OUT. Also, the smoothing circuit 113 includes a smoothing coil 140 having one terminal connected with the connection point (node D) of the power source side output transistor 111 and the ground side output transistor 112 and the other terminal connected with the output terminal OUT, and a smoothing capacitor 141 having one terminal connected with the output terminal OUT and the other terminal grounded. Also, the control signal A and the control signal B that are output by the regulator control circuit 115 have substantially the same waveform.
The current direction detection circuit 116 includes a comparator 120 that performs a comparison by respectively inputting the voltage of the node D at its inversion input terminal and ground potential at its non-inversion input terminal. Also, the ground side output transistor control circuit 117 includes an AND circuit 130 that inputs the control signal B of the regulator control circuit 115 and the control signal F of the current direction detection circuit 116, and a buffer 131 that delivers an output with an increased current capability.
Next, the operation of the switching regulator 101 will be described with reference to FIG. 4. In FIG. 4, VB is the voltage of the control signal B of the regulator control circuit 115, VC is the voltage of the output signal C of the ground side output transistor control circuit 117, IO is the current flowing in the ground side output transistor 112, and VD is the voltage at the node D. It should be noted that FIG. 4 shows the waveform when the load 114 is light, the case where the load 114 is large is not shown.
In the period in which control signal B is low level, the output signal C is low level, and the ground side output transistor 112 is turned off. The control signal A is also low level, so the power source side output transistor 111 is turned on. Consequently, the current IO flowing in the ground side output transistor 112 is zero, and the voltage VD at the node D is high level.
Since, when the control signal B is high level, the control signal A is also high level, the power source side output transistor 111 is turned off. When the voltage VD at the node D drops, becoming lower than the ground potential, the control signal F becomes high level, with the result that the ground side output transistor 112 is turned on. In this way, first of all, current IO in the positive direction flows from ground potential to the node D. When this happens, the voltage VD at the node D drops from ground potential by an amount of the voltage that is acquired by multiplying this current IO and the on resistance of the ground side output transistor 12.
After this, the current IO gradually decreases linearly, and, in response thereto, the negative voltage VD at the node D gradually rises in linear fashion. If the load 114 is large (not shown), the initial current value is large prior to the commencement of decrease of the current IO. Therefore, before the current IO will become a current in the reverse direction, the control signal B returns to low level after the lapse of a period in which the control signal B is high level. In contrast, if the load 114 is light, the current IO becomes a current in the reverse direction before the high level period of the control signal B has lapsed. This reverse direction current is a current that flows out towards the ground potential, so it represents a power loss and the power efficiency of the switching regulator 101 is lowered to that extent. Accordingly, when the current becomes a reverse direction current, this is detected by the current direction detection circuit 116, which outputs low level control signal F. As a result, the voltage VC of the output signal C becomes low level and the ground side output transistor 112 is thereby forcibly turned off, so that the flow of this current in the reverse direction is minimized.
Thus, when the load is light, the ground side output transistor 112 is forcibly turned off when the current IO flows in the reverse direction, thereby making it possible to increase the power efficiency. The inventor of the present application, as a result of studies directed at achieving further improvements in power efficiency, discovered that there is a certain delay (period to in FIG. 4) from detection of the reverse direction current of the ground side output transistor 112 by the current direction detection circuit 116, before ground side output transistor 112 is turned off, and this delay allows a reverse direction current to flow for a certain period of time, which therefore results in power loss. Also, since the voltage VD at the node D has a wide range of variations from the power source voltage to below ground potential, the comparator 120 of the current direction detection circuit 116, which has as its input voltage a voltage of such a wide range of variations, must be larger in terms of the size of its circuitry compared with an ordinary comparator, whose input voltage is a voltage having a narrow range of variations.
Also, with the switching regulator 101, as shown in FIG. 4, there is a risk that a swing, i.e., ringing of the gradually decaying voltage generated after the forcible turning off of the ground side output transistor 112 will cause the voltage VD at the node D to drop below ground potential, resulting in instantaneous activation of the current direction detection circuit 116, with consequent wasted power consumption or generation of noise.

Current direction detection circuit and switching regulator having the same


This specification describes, in part, a technique for dynamic assignment of multiple antennas to different radio subsystems in a wireless device. The technique may include using an adaptive algorithm to allocate antennas to different radio subsystems as a function of, for example, application requirements, power requirements, and/or channel/network conditions. The specification also describes, in part, a technique for adaptively optimizing the use of the assigned antennas and other transmission parameters for each radio subsystem.

The invention relates to wireless transceivers, and more specifically to wireless transceivers with multiple radio subsystems and multiple antennas.
Many wireless devices support multiple wireless systems and/or standards. For example, many cellular handsets support cellular communication via one or more of the cellular phone standards and also support Bluetooth radio communication. Similarly, many wireless LAN radio cards support the 802.11b, 802.11g, and/or 802.11n standard in the 2.4 GHz radio band as well as the 802.11a and/or 802.11n standard in the 5 GHz band. Radio signals transmitted and received through such multimode devices are transmitted and received through one or more antennas on the device.
Typically, the allocation of antennas to a particular radio subsystem is static. It would be advantageous to be able to allocate antennas dynamically.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.


A vibrating element includes: drive vibrating arm supported to the base portion and extending in a direction of the second axis; and detection vibrating arm supported to the base portion at a position different from the drive vibrating arm and extending in the direction of the second axis. When the vibrating element is subjected to rotation about the second axis while the drive vibrating arm being reciprocally driven in a direction of the first axis, an amount of displacement of the detection vibrating arm in a direction of the third axis at a position distant from the base portion by a distance y1 along the direction of the second axis is greater than an amount of displacement of the drive vibrating arm in the direction of the third axis at a position distant from the base portion by the distance y1 along the direction of the second axis.

1. Technical Field
The present invention relates to a vibrating element, a vibrator, an electronic apparatus, and a moving object.
2. Related Art
In the related art, for example, angular velocity sensors (vibration gyro sensors) that detect a physical quantity such as an angular velocity or an acceleration and are used for body control in vehicles, self-position detection of car navigation systems, vibration control correction (so-called camera-shake correction) for digital cameras or video camcorders, or the like have been known.
In an angular velocity sensor including a vibrating element called an "H type" including a pair of drive vibrating arms and a pair of detection vibrating arms, the drive vibrating arms flexurally vibrate (drive-vibrate) close to or away from each other by energization. In this state, when an angular velocity about a predetermined axis is applied to the angular velocity sensor, the drive vibrating arms flexurally vibrate in opposite directions with the Coriolis force, and consequently, the detection vibrating arms flexurally vibrate (detection-vibrate) in opposite directions. With the detection vibrations of the detection vibrating arms, charge is generated at electrodes provided on the detection vibrating arms. By detecting the charge, the angular velocity applied to the angular velocity sensor can be obtained.
In such an angular velocity sensor, adjustments of frequencies such as the resonance frequency of drive vibration of the drive vibrating arm, the resonance frequency of detection vibration of the detection vibrating arm, and a detuning frequency as a difference between the resonance frequency of the drive vibration and the resonance frequency of the detection vibration are carried out for preventing variations in the frequencies of products after manufacture (for example, refer to Japanese Patent No. 4107768). For example, the adjustment of the detuning frequency is carried out by changing the mass of the drive vibrating arm or the detection vibrating arm by providing a weight on the drive vibrating arm or the detection vibrating arm, or removing a portion of the provided weight. The resonance frequency of drive vibration of the drive vibrating arm is moved away from the resonance frequency of detection vibration of the detection vibrating arm for the reason that if they are proximate to each other, noise is introduced into signals output from the angular velocity sensor due to the influence of the drive vibration of the drive vibrating arm.
However, in the angular velocity sensor in the related art, the amount of change in detuning frequency per unit mass is small. For this reason, the mass of the drive vibrating armor the detection vibrating arm needs to be greatly changed to bring the detuning frequency to a target value, which involves a problem of disturbing the balance of the drive vibrating arm or the detection vibrating arm and thus deteriorating characteristics.

Vibrating element with an increased amount of change in detuning frequency per unit mass, vibrator, electronic apparatus, and moving object


Catalytic reforming of a naphtha feed with large-pore zeolites containing Group VIII metals and Group IA or Group IIA metal cations.

This invention relates to a catalytic reforming process using zeolite catalysts. Catalytic reforming is a process for treating naphtha fractions of petroleum distillates to improve their octane rating by producing aromatic components and isomerizing normal paraffins to isoparaffins from components present in naphtha feedstocks. Included among the hydrocarbon reactions occurring in reforming processes are: dehydrogenation of naphthenes to aromatics, dehydrocyclization of paraffins to aromatics, and hydrocracking of paraffins to lighter gases with a lower boiling point than gasoline. Hydrocracking reactions which produce light paraffin gases are not desirable as they reduce the yield of products in the gasoline boiling range.
Natural and synthetic zeolitic crystalline aluminosilicates containing Group VIII metals and Groups IA and IIA metal cations exhibit catalytic properties for various types of hydrocarbon conversions including catalytic reforming.
U.S. Pat. No. 4,789,656 issued to Chen et al. discloses a process for synthesizing Beta Zeolite catalyst. A noble metal component is incorporated into the beta zeolite catalyst. Noble metals which are incorporated within the zeolite include metals of Groups IB, IIB, VA, VIA or VIIIA.
U.S. Pat. No. 4,652,360 issued to Dessau discloses a reforming process using ZSM-5 and ZSM-11 zeolite catalysts having a silica to alumina ratio of at least 12 containing a Group VIII metal. The zeolite is base exchanged with Group IA metal cations.
U.S. Pat. No. 4,835,336 issued to McCullen discloses a process for converting a C.sub.6 -C.sub.12 paraffinic hydrocarbon feed to aromatics with a noble metal, low activity medium pore size zeolite catalyst including a beta zeolite catalyst.
U.S. Pat. No. 4,867,864 issued to Dessau discloses a reforming process using a non-acidic beta zeolite catalyst composition containing a Group VIII metal. The acidity of the catalyst is reduced by treating it with a solution containing Group IA or Group IIA metal cations.
U.S. Pat. No. 4,927,525 issued to Chu discloses catalytic reforming processes with improved zeolite catalysts. This reference discloses the use of beta zeolite in reforming processes. The beta zeolite described in this reference contains a noble metal and an alkali metal. The noble metal is selected from the group consisting of platinum, iridium, osmium, palladium, rhodium and ruthenium. The alkali metal is selected from the group consisting of lithium, sodium, potassium and rubidium.
The effect of alkali metal loading on catalytic activity is shown in Examples 7-11 of U.S. Pat. No. 4,927,525. These examples show that certain zeolitic catalysts which have a Li.sup.+ :AlO.sub.2.sup.- ratio of less than 1 are inferior to zeolitic catalysts which have Li.sup.+ :AlO.sub.2.sup.- ratios greater than 1. Therefore, this reference teaches that by lowering the ratio of AlO.sub.2 :Li to less than 1, the catalytic reforming properties of these materials are improved.
I have found that the catalytic reforming properties of the beta zeolite catalyst and other large-pore zeolites are significantly improved when the molar ratio of aluminum to Group IA or Group IIA metal cations is between about 1.0 and 4.0. These properties include high catalyst stability at low pressure, high catalyst activity, and lower methane and ethane production.

Reforming naphtha with large-pore zeolites


The holding elements (28), designed as hook-gripper elements (26), are driven in a circulating manner by means of a drive arrangement (44) in a plane at right angles to a stack (16) of printed products that have back margins (20). In the takeover section (46), the cantilever arm (36) of a hook-gripper element (26) comes to bear against the back margin (20) of the topmost printed product (14) of the stack (16). The hook-gripper element is then guided in a sliding manner on the printed product (14) in the direction of a stop, until the hook mouth (38) of the hook-gripper element (26) has seized the back margin (20). From the takeover section up to the transfer of the printed product (14) separated in this way from the stack (16), the direction of movement of the hook-gripper element (26) has a component toward the stop and a component away from the stack (16).

The present invention relates to an apparatus for individually separating stacked printed products having a back margin and an edge that is opposite the back margin.
An apparatus of this type is disclosed in U.S. Pat. No. 5,542,656, which discloses a device having suction heads that are anchored on a continuously rotating rotor driven by swivel arms. The swivel arms are driven with regard to their swiveled position by a swivel drive that is superposed on the rotary drive of the rotor such that they enter the takeover point in a pushing operation and leave it in a pulling operation. At the reversal point, the suction heads seize the edge of the respectively topmost product of a stack. Their tilting movement at the reversal point causes the edge of the product seized to be definitely and reliably separated from the neighboring printed product. The edges of the printed products are placed, one after the other, into grippers of a transporting-away device. The edges of the printed products are placed into the grippers by the suction heads that are swivelled during the circulation.

Apparatus for individually separating stacked printed products


A method detects narrow band interference in wireless networks by first thresholding each block of samples to produce thresholded samples. The samples are normalized frequency magnitudes obtained from a spectrum of a wireless signal in a channel. Each block of the thresholded samples is summed to produce a thresholded value for each block. Then, thresholded values are autocorrelated to determine whether a bandwidth of the wireless signal is consistent with narrow band interference.

In wireless local area networks (WLANs), it is necessary to detect spectrum occupancies and spatial directions of radio transmitters. This is particularly important because WLANs typically use an unregulated band, e.g., 2.4 G Hz, where many devices can operate concurrently.
For example, many devices, such as cordless telephones, car alarms, baby monitors, video senders, wireless speakers, cameras, game controllers (Xbox and Wii), and ZigBee, wireless fidelity (WiFi) and Bluetooth devices use the 2.4 GHz frequency, the same frequency at which devices designed according to the Wi-Fi standards 802.11a, 802.11g and 802.11n operate, collective known as AGN. This can cause a significant decrease in speed, or sometimes the total blocking of the Wi-Fi signal the interference is present.
It is well known that microwave ovens (MWOs) emit radio frequencies in this band that interfere with the normal operation. A WLAN device (access point or client terminal) has the ability to detect and avoid interference from other WLAN devices, primarily, though the operation of the Multiple Access Control, (MAC), protocol. However, in the case of non-WLAN devices, such as MWOs, there is no method to coordinate the use of the unregulated wireless spectrum. Thus, interference from non-WLAN devices, such as MWOs degrades performance.
Without the ability to coordinate spectrum use across systems (WLAN and non-WLAN), some methods adapt the WLAN system to the presence of interference. For example, changing the operating channel of the WLAN in response to the detection of interfering signals on a current operating channel, or modifying the data rate or coding scheme accordingly. In any event, it is necessary for WLAN devices to be able to detect the presence of interfering signals, and respond accordingly.
It is preferred that the detection of the interference is performed using existing, commercial WLAN hardware to minimize cost. Fortunately, some WLAN hardware does provide access to some signal physical layer data that can be used for interference detection.
For example, the Qualcomm Atheros 9280 AGN, WLAN chipset provides access to raw fast Fourier transform (HT) data of the received signal. Specifically, the chip can provide the magnitude of the received signal in each FFT bin that is normally used for data demodulation. Thus, the device provides a coarse estimate of the frequency spectrum of the received signal.
One system called Airshark uses the Atheros WLAN hardware to perform passive detection of various non-WiFi devices, Rayanchu et al., "Airshark: detecting non-WiFi RF devices using commodity WiFi hardware." Proceedings of the 2011 ACM SIGCOMM conference on Internet measurement conference. ACM, 2011. However, this system requires nearly continuous scanning of the channel by the hardware for detection purposes. Therefore, that system cannot be used as a conventional normal WLAN device that transmits user data.

Detecting narrow band interference in wireless networks using spectral analysis

Mitsubishi Electric Research Laboratories, Inc.


According to an embodiment, a magnetic disk has a plurality of second servo sectors and a plurality of third servo sectors each arranged between two second servo sectors of the plurality of second servo sectors, in which the second and third servo sectors are arranged in a circumferential direction. A controller performs a first demodulation for detecting a servo mark and demodulating a burst pattern on the servo data in each second servo sector. The controller performs a second demodulation for demodulating the burst pattern without detecting the servo mark, on the servo data in each third servo sector. The controller performs the second demodulation on the servo data in a fourth servo sector which is one of the plurality of second servo sectors in a case where the detection of the servo mark fails when the first demodulation is performed on the servo data in the fourth servo sector.

A magnetic disk included in a magnetic disk device has servo sectors in which servo data is written, which are arranged at intervals in a circumferential direction. When writing to the magnetic disk, the magnetic disk device acquires position information representing the present position of a magnetic head by demodulating servo data, and controls the position of the magnetic head based on the acquired position information.
The servo data includes a servo mark and a burst pattern. The servo mark is data representing the start of servo data. The burst pattern is data for detecting the offset amount of the position of the magnetic head from a track center.
The magnetic disk device uses the detection of the servo mark in order to determine the timing for demodulating a burst pattern written in rear of the servo mark. If the detection of the servo mark fails, the magnetic disk device cannot demodulate the burst pattern written in rear of the servo mark, and thus the positioning accuracy of the magnetic head deteriorates.

Toshiba Electronic Devices & Storage Corporation


An electronic component has a substrate, electrode layers for the bottom electrode, top electrode and, optionally, one or more intermediate electrodes, and has intermediate functional layers, these electrode layers include an electroconductive oxidic compound, at least one electrode layer is composed of EuO.sub.x, wherein 1.ltoreq.x.ltoreq.2, LiTi.sub.2 O.sub.4, LiV.sub.2 O.sub.4, SrVO.sub.3, Eu.sub.x NbO.sub.3, Na.sub.x WO.sub.3, A.sub.2 P.sub.8 W.sub.32 O.sub.112, wherein A=K, Rb,RTl, Na.sub.x Ta.sub.y W.sub.1-y O.sub.3, Na.sub.1-x Sr.sub.x NbO.sub.3, LaTiO.sub.3 CeTiO.sub.3, CaVO.sub.3, La.sub.1-x Sr.sub.x VO.sub.3, SrCoO.sub.3, CaRuO.sub.3, SrRuO.sub.3, BaRuO.sub.3, BaPbO.sub.3, SrMoO.sub.3, Sr.sub.0.5 La.sub.0.5 O.sub.3, La.sub.4 BaCu.sub.5 O.sub.13-x, La.sub.2-x Sr.sub.x CuO.sub.4-.delta., YBa.sub.2 Cu.sub.3 O.sub.7-.delta., Bi.sub.2 Sr.sub.2 CaCu.sub.2 O.sub.8.sub.+d, Bi.sub.2 Sr.sub.2 CuO.sub.6+d, Bi.sub.2 Sr.sub.2 Ca.sub.2 Cu.sub.3 O.sub.10+d, Tl.sub.2 Ba.sub.2 CaCu.sub.2 O.sub.8, TlBa.sub.2 CuO.sub.6+d, Tl.sub.2 Ba.sub.2 Ca.sub.2 Cu.sub.3 O.sub.10+d, La.sub.4 BaCu.sub.6 O.sub.15, Gd.sub.1-x Sr.sub.x VO.sub.3, CaCrO.sub.3, SrFeO.sub.3, EuNbO.sub.3, SrIrO.sub.3, CaMoO.sub.3, BaMoO.sub.3, Bi.sub.3 Ru.sub.3 O.sub.11, VO.sub.2, CrO.sub.2, MoO.sub.2, WO.sub.2, PtO.sub.2, RuO.sub.x, wherein 1.5.ltoreq.x.ltoreq.2, IrO.sub.x, SnO.sub.2-x, La.sub.3 Ni.sub.2 O.sub.7, La.sub.3 Ni.sub.3 O.sub.10, M.sub.2 V.sub.2 O.sub.7-x, wherein M=Tm, Lu, M.sub.2 Mo.sub.2 O.sub.7, wherein M=Nd,Sm,Gd, Lu.sub.2 Ru.sub.2 O.sub.7, Pb.sub.2 Ru.sub.2 O.sub.7, Bi.sub.2 Ru.sub.2 O.sub.7, Pb.sub.2 Os.sub.2 O.sub.7, Tl.sub.2 Os.sub.2 O.sub.7, Pb.sub.2 Ir.sub.2 O.sub.2, Tl.sub.2 Rh.sub.2 O.sub.7-x, K.sub.0.3 MoO.sub.3, Rb.sub.0.3 MoO.sub.3, Tl.sub.0.3 MoO.sub.3 M.sub.x V.sub.2 O.sub.5, wherein M=Cu,Na, Mo,.sub.17 O.sub.47 or Tl.sub.2 O.sub.3-x, or of physical mixtures and/or solid solutions of the oxidic compound or physical mixtures and/or solid solutions of the oxidic compounds to which is a 50% by weight of further compounds or metals is added. This electrode layer exhibits an improved adhesion and it does not passivate itself.

The invention relates to an electronic thin-film component comprising a substrate, electrode layers for the bottom electrode, top electrode and, optionally, one or more intermediate electrodes, and comprising functional intermediate layers, said electrode layers including electroconductive, oxidic compounds.
Such components can be discrete components or multifunctional, multi-component systems, such as non-volatile ferro-electric memories, dynamic random-access write-read memories, integrated capacitors, thin-film actuators, thin-film resistors, piezo-electric sensors, piezo-electric transducers, pyroelectric sensors, electro-optic components or modules comprising integrated passive components (ICM).
For example, for applications in non-volatile ferro-electric memories, piezo-electric transducers, sensors and actuators as well as pyroelectric sensors, functional layers of perovskites of the composition PbZr.sub.x Ti.sub.1-x O.sub.3, wherein x=0.3-0.7, as well as Pb.sub.1-1.5y La.sub.y Zr.sub.x Ti.sub.1-x O.sub.3, wherein y=0.3-0.07, x=0.4-0.6, and Pb.sub.1-1.5y La.sub.y TiO.sub.3, wherein y=0.05-0.16, are stacked between electrodes. High-frequency modules for filtering applications in accordance with the state of the art, comprising capacitors and resistors include combinations of SiO.sub.2 and Si.sub.3 N.sub.4 as the functional layers.
In these and other thin-film components, platinum is used as the electrode material, which is preferred to other electrode materials, such as Cu, Al or Ag/Pd, to preclude reactions of the electrode material with the material of the functional layers, for example perovskites, when said material is sintered during its manufacture in an oxygen atmosphere at 600-800.degree. C. However, connecting the platinum electrode to the substrate is problematic. In order to obtain a good adhesion of the Pt electrode layers to a customary substrate, such as silicon with SiO.sub.2 insulating layers, an adhesive layer, for example a thin Ti layer must additionally be provided as an intermediate layer between Si/SiO.sub.2 and Pt. Also in the case of optimized electrode layers and adhesive layers, the adhesion of the Pt electrodes after sintering of the perovskite layers is often insufficient. As a result, the entire capacitor assembly including the bottom electrode becomes detached from the substrate during the post-treatment. This is the reason why for many applications high-reliability components can yet not be manufactured.
Apart from the integration of perovskite layers in semiconductor ICs, for example, for integrated capacitors, ferro-electric, non-volatile memories or random-access write-read memories, as well as for pyroelectric and piezo-electric components, perovskite layers are also used in the manufacture of modules comprising integrated passive components. In these modules, the perovskite layers are used as dielectrics in thinfilm capacitors and are deposited between electrodes, such as Pt electrodes. Also in this application, the poor adhesion of platinum layers to substrate materials, such as Si/SiO.sub.2 or Al.sub.2 0.sub.3 and to functional layers, such as oxidic perovskite layers comprising Pb.sub.1-1.5y La.sub.y Zr.sub.x, Ti.sub.1-x O.sub.3 wherein 0.53<x<1 and y=0.05-0.15 or Pb(Mg, Nb).sub.x Ti.sub.1-x,O.sub.3, wherein 0.65<x<1 is clearly a disadvantage.
A further disadvantage of the Ti/Pt electrode layers resides in that this material system can only be deposited by means of vacuum techniques, such as cathode-ray sputtering or electron-beam evaporation. Said methods, however, involve high investments as well as high operating costs as, for example in the case of a cathode ray process, expensive Pt targets must be purchased.
Perovskite layers, such as PbZr.sub.x Ti.sub.1-x O.sub.3, wherein x=0.2-0.7, on Si substrates with a Ti adhesion layer and a Pt layer as bottom electrode as well as a Pt layer as the top electrode are used in a new type of memories, i.e. ferro-electric non-volatile memories. A plurality of investigations have revealed, however, that such ferro-electric memory cells demonstrate, dependent upon the deposition conditions, a greater or smaller degree of fatigue. The switched charge of such ferro-electric memory cells decreases clearly after several hundred switching cycles, as a result of which such memory cells are no longer functional. Although the phenomena responsible for the occurrence of fatigue in these materials are so far unknown, other electrode materials in combination with the known functional layers must be used to eliminate this fatigue.
To overcome this disadvantage, EP-A-0 495 114 proposes a semiconductor component on which a ferro-electric film, forming an active element on a semiconductor substrate, is integrated by means of electrodes which form a laminar structure with the ferro-electric film, one or both of the electrodes forming the laminar structure being an oxidic conductor which is predominantly composed of either ITO (mixed crystal of indium oxide and tin oxide), ruthenium oxide, rhenium oxide, tungsten oxide, chromium oxide or molybdenum oxide. These oxide electrodes are manufactured by means of sputtering. Apart from the ITO layer, these oxide layers are very brittle and, partly, ill conducting.

Electronic component and method of manufacturing same


A method for driving an LED backlight device using pulse width modulation with an additional timer to manage the power consumption, thermal output, and lighting level of the device with improved resolution. The method includes receiving a commanded brightness level, and using an n bit pulse width modulator that has a nominal time period (Pn) to assert a plurality of pulses in accordance with an output of the n bit pulse modulator. A modulator output value is assigned to each one of K states of a K state timer that has a timer period (PT). The plurality of pulses is output according to the modulator output value during each nominal time period occurring within the timer period. Power to the display is supplied in accordance with the plurality of pulses.

The present invention relates generally to control of light emitting diode (LED) devices and in particular to control of LED backlights using pulse width modulation.
A light emitting diode, or LED, comprises a diode that emits visible light when current passes through it. LEDs have several applications. Certain display devices, for example, but not limited to, aircraft cockpit displays, use an array of LEDs to backlight and illuminate a liquid crystal display (LCD). Controlling the amount of light emitted by the LED array is desirable to adjust the brightness of the display. The brightness level impacts the ease with which the display may be viewed under certain lighting conditions, such as bright sunlight or dark environment; and individual viewer comfort level with the display.
In some applications, the brightness level is more than a convenience factor. For example, in the aviation environment, if the display is illuminated too brightly at night, the excessive brightness may adversely impact the pilot's night vision. Impaired night vision adversely impacts the safety of flight.
The brightness level additionally impacts the amount of power required to operate the device as well as the heat given off by the display. Power consumption affects the length of time the device can operate on battery power and the electrical load placed on the vehicle power supply systems. The heat given off by the display also affects what, if any, cooling of the display and surrounding equipment is required. Cooling devices add cost and complexity to equipment and systems. In aircraft/spacecraft applications, cooling systems add unwanted additional weight to the vehicle. Furthermore, if the display generates too much heat, touching or otherwise operating the display may cause discomfort to the user.
The amount of light emitted by the diode can be controlled by controlling the amount of power supplied to the diode where power equals voltage times current (P=V*I). In certain prior art devices, a microprocessor device is coupled to drive circuitry that controls the LED display brightness. In such designs, a technique known as pulse width modulation (PWM) is used to control the power supplied to the device. Under control of the microprocessor, the drive circuitry supplies current to the LED for a predetermined amount of time, or one pulse width. In this manner, by varying the number of pulses received and the width of the pulses, the total power supplied to the LED, and hence the brightness can be controlled.
One significant limitation on this prior art design is that the pulse frequency and duration are limited by the resolution with which the pulse frequency and width can be defined by the microprocessor. For this reason, it is not always possible to control the LED display with the specificity and precision desired. This fact may result in the LED display being too bright at one setting, but too dark at the next available setting. In an aviation environment, this fact can cause the cockpit display to be illuminated too brightly at night even on the lowest available setting.
Correction of the above deficiencies cannot presently be accomplished without a complete redesign of the microprocessor/driver hardware. Redesign is frequently impractical because often, the pulse width modulation output of the microprocessor is part of a predefined set of operations purchased with the selected microprocessor chip; and its resolution is limited by the number of bits the microprocessor can output. Redesign of standard LED drive circuit hardware is also undesirable due to the cost of custom designing and fabricating such circuits.

Method, apparatus and computer program product for controlling LED backlights and for improved pulse width modulation resolution


A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.

A spouted wafer plating apparatus that performs plating of a wafer processing surface by a face-down method, is known. In a conventional face-down method, the wafer processing surface is faced downward. Then, a peripheral portion of the wafer processing surface is covered with a mask member, and electrodes are pressed against the peripheral portion of the wafer processing surface inside the mask member.
In the conventional method, when the wafer becomes thinner, a crack may occur in the wafer when the electrodes are pressed against the peripheral portion of the wafer processing surface.

Semiconductor device, substrate for semiconductor device and method of manufacturing the semiconductor device


An apparatus and associated a method are described for performing gas analysis on a gas sample. The method comprising exciting the gas sample with one or more electromagnetic energy sources and obtaining optical absorption signals associated with the gas sample prior to application of a catalytic process to the gas sample as well as during and/or after application of the catalytic process to the gas sample. The obtained optical absorption signals may then be processed using differential calculation approaches to derive information associated with the gas sample, which may include for example information conveying concentrations of certain specific gases in the gas sample. In some implementations, the optical absorption measurement system is configured to use the one or more electromagnetic energy sources to excite the gas sample to produce first optical absorption signals. The optical absorption measurement system is also configured to apply a catalytic process to the gas sample to derive a modified gas sample and to use the one or more electromagnetic energy sources to excite the modified gas sample to produce second optical absorption signals. Information may then be derived at least in part by processing the first optical absorption signals and second optical absorption signals. The apparatus and associated method may find practical uses in a variety of fields including, without being limited to, the field of dissolved gas analysis (DGA) for detecting/monitoring faults in liquid-insulated electrical equipment as well as equipment used for mine safety, particularly coal mines; equipment for analyzing gases that emerge from the bore hole during drilling for natural gas and oil and equipment for identifying gas leaks in underground natural gas lines as well as other areas.

There are various devices commercially available that use optics-based methods, such as infrared light (IR) and/or ultra-violet (UV) light, to detect and to obtain gas concentration measurements from a sample gas. These monitors vary significantly by their design and even by their basic operating principles depending on the manufacturer.
Typically optical gas analysis devices, such as IR-based as well as UV-based gas analysis devices, rely on the principle that when molecules in a gas sample are exposed to light, they absorb light as they shift into an excited molecular state, as illustrated in FIG. 1. For each type of gas component, the absorbed wavelengths are different and form gas specific "fingerprints", which can be used to identify specific gas components and to quantify the concentration of such gas components in the gas sample. FIG. 2 is a schematic illustration of such a typical optical gas analysis device. As depicted, a typical optical gas analysis device 260 would include a light source 262, one or more band-pass filters 263, a gas cell 264 (for holding a gas sample to be an a mirror 266, and detectors 268. By using the one or more band-pass filters 263 to select specific wavelengths and then measuring the light received at the detectors 268, it is possible to derive measurements conveying, concentrations of some specific types of gases. Note that some gas molecules like O2, N2, H2 do not absorb light on mid IR-range wavelengths meaning that other sensing technology and/or a different wavelength range would be needed to measure those gases.
While the principles of operation of optical gas analysis devices, such as IR-based as well as UV-based gas analysis devices, are known, challenges arise when applying these principles it certain practical implementations in particular it implementations in which it is desirable to obtain gas concentration measurements for trace quantities of certain specific gases. In particular, conventional systems are typically unsuitable for measuring a quantity of a specific gas when the quantity of the specific gas present in a gas sample is very small relative to the gas sample and these conventional systems are neither sufficiently sensitive nor sufficiently selective to be able to discern trace quantities of specific gases.
One specific practical area in which it is desirable to obtain gas concentration measurements for trace quantities of specific gases in a gas sample is in the field of dissolved gas analysis (DGA) for detecting/monitoring faults in liquid-insulated electrical equipment. Electrical insulating liquid (such as for example mineral oil) is commonly used in equipment that serves in the generating, transmitting, and distributing of electrical power. Such equipment generally includes transformers (sometimes called oil-immersed transformers), tap-changers and circuit breakers. In such equipment, the liquid acts both as an electrical insulating medium and a vehicle for heat dissipation. When a fault occurs in such electrical equipment, fault gases may evolve in the insulating liquid.
Some of the gases that are typically associated with specific fault types in such equipment are hydrogen (H2), Carbon Dioxide (CO2), Carbon Monoxide (CO), Ethane (C2H6), Methane (CH4), Ethylene (C2H4) and Acetylene (C2H2). Analysis of one or more of such fault gases may be used to provide a diagnosis of the health of electrical equipment.
In this regard, various practical Dissolved Gas Analysis (DGA) applications have been previously suggested for detecting such fault gases in equipment that serves in the generating, transmitting and distributing of electrical power.
For example, U.S. Pat. No. 6,391,096 to Waters describes an apparatus for performing dissolved gas analysis on electrical insulating oil which makes use of a gas chromatograph to analyze the fault gases. The contents of the aforementioned document are incorporated herein by reference. The apparatus includes a tubular membrane extractor column for extracting the fault gases from the oil, where the column includes a plurality of composite hollow fiber tubes coated with a thin layer of a non-porous gas permeable polymer, making each tube gas permeable, but not dielectric fluid permeable. Diffusion of the fault gases occur through the fiber tubes until equilibrium exists on both sides of the phase barrier. The time required to reach equilibrium or near equilibrium conditions depends upon factors such as pressure and temperature, the size of the diffusing molecules and the permeation properties of the media, as well as the flow rate of the oil carrying the gases for equilibrium.
U.S. Pat. No. 8,347,687 to Cunningham describes an apparatus for performing dissolved gas analysis on electrical insulating oil which makes use of photo-acoustic spectroscopy (PAS) to analyze the fault gases. The contents of the aforementioned document are incorporated herein by reference. The apparatus includes a gas extraction module in which the fault gases are released from the oil by means of an agitator into a head space of the module. After a period of agitation, head space equilibrium is achieved, and the gases are pumped into an analysis cell where measurements of the head space gases are performed with a PAS module. The apparatus conveniently includes a fluid conduit configuration which enables the measure of oil samples from different sources relatively easily while minimizing or avoiding cross contamination.
A deficiency associated with many commonly used apparatuses performing dissolved gas analysis on electrical insulating liquid (such as for example electrical insulating oil) using infra-red absorption methods is that they frequently require relatively large sample gas volumes to be able to detect the minimal concentrations of fault gases that are relevant for detecting emerging faults in liquid-insulated electrical equipment. For example, such minimal concentrations may represent gas levels as low as 1 ppm in the case of acetylene. The requirement for relatively large sample gas volumes, however, increases manufacturing costs of other systems in the apparatus, including those required to maintain the liquid/gas samples within a specific operational temperature range to ensure measurement accuracy and reproducibility. In addition, the relatively large sample gas volumes required often lead to increases in the period of time required to extract the fault gases from each sample the time required to reach equilibrium), which negatively impacts the time-resolution and accuracy of dissolved-gas concentration measurements of many conventional DGA apparatuses.
Another challenge associated with the use of IR absorption methods to obtain dissolved-gas concentration measurements for trace quantities of DGA gases is that the sample gas frequently contains amounts of gases other than the targeted DGA gases as well as vapours, including water vapour, and the presence of such compounds in the sample gas may interfere with optical spectroscopy-based methods designed to quantify the concentrations of the DGA gases.
Against the background described above, it is clear that there remains a need in the industry to provide improved optical spectroscopy-based gas analysis apparatuses and methods for measuring concentrations (including trace quantities) of certain specific gases in a gas sample that alleviate at least some of the deficiencies of the existing apparatuses and methods.

This patent is subject to a terminal disclaimer.

Apparatus and method for performing gas analysis using optical absorption spectroscopy, such as infrared (IR) and/or UV, and use thereof in apparatus and method for performing dissolved gas analysis (DGA) on a piece of electrical equipment


A voltage follower circuit comprising an nMOS transistor whose drain is connected to a power source and a pMOS transistor whose drain is connected to the source of the nMOS transistor and whose source is grounded, wherein input voltage is connected to the gates of nMOS and pMOS transistor. A source of the nMOS transistor is connected to an output terminal, and the output terminal is grounded through capacitance.

A voltage follower circuit is conventionally known as a buffer amplifier. The conventional circuit, shown in FIG. 1, maintains the output voltage level by grounding the source of a MOSFET transistor through resistor R1. When the value of R1 is small, the level of the output voltage is lowered. When the value of R1 is large, the output voltage Vout follows the input poorly because of the increase of the time constant associated with parasitic capacitance C1.