An image capture device capable of capturing high quality images is disclosed. The image capture device comprises a shift register, each pixel of which has a plurality of transfer electrodes extending in a direction crossing a transfer direction of information charges. A potential well formed by function of the transfer electrodes is used to store and transfer information charges generated in response to light incident on a pixel. In this image capture device, during image capture, information charges are stored in a plurality of potential wells substantially separated from each other, and, during transfer, information charges stored in at least two of the plurality of potential wells are combined by addition to be transferred.

1. Field of the Invention
The present invention relates to an image capture device in which a captured image has an improved image quality, and to a controller of such an image capture device.
2. Description of the Related Art
FIG. 17 shows a structure of an image capture device 100 including a CCD solid state image capture element. The image capture device 100 includes a CCD solid state image capture element 102, a timing control circuit 104, and a driver circuit 106. The CCD solid state image capture element 102 has an image capture section 2i, a storage section 2s, a horizontal transfer section 2h, and an output section 2d. In response to a clock pulse having a predetermined frequency and an external control signal, the timing control circuit 104 generates a control signal for use in controlling the image capture, vertical transfer, horizontal transfer, and output of the CCD solid state image capture element 102. The control signal is input to the driver circuit 106. In response to the control signal generated from the timing control circuit 104, the driver circuit 106 outputs a clock pulse at a necessary time to each of the image capture section 2i, the storage section 2s, the horizontal transfer section 2h, and the output section 2d of the CCD solid state image capture element 102.
In response to the clock output from the driver circuit 106, the CCD solid state image capture element 102 performs image capture, vertical transfer, horizontal transfer, and output. In the image capture section 2i, light receiving pixels constituting respective bits are arranged in a two-dimensional matrix. Light incident on the image capture section 2i is subjected to photoelectric conversion in the light receiving pixels so that information charges are generated. Application of a vertical transfer clock causes vertical shift registers of the image capture section 2i to transfer the two-dimensional array of information charges generated in the image capture section 2i to the storage section 2s at high speed. As a result, information charges for one frame are held in vertical shift registers of the storage section 2s. Then, the information charges are transferred from the storage section 2s to the horizontal transfer section 2h in units of one line. Further, application of a horizontal transfer clock causes transfer of the information charges from the horizontal transfer section 2h to the output section 2d in units of one pixel. The output section 2d converts the amount of charge for each pixel to a value of voltage, and outputs the change in the value of voltage as an output of the CCD.
The image capture section 2i and the storage section 2s include vertical shift registers in which a plurality of channel regions extend in parallel with each other in a vertical direction (corresponding to the longitudinal direction of the CCD solid state image capture element 102 shown in FIG. 17) and a plurality of transfer electrodes intersect the channel regions. Each bit of the shift registers functions as one of the light receiving pixels arranged in the two-dimensional matrix.
As shown in FIGS. 18A to 18C, the image capture section 2i has a structure in which a plurality of shift registers are formed in a surface region of a semiconductor substrate 9. FIG. 18A is a schematic plan view showing a part of a related art image capture section 2i, and FIGS. 18B and 18C are cross-sectional side views taken along lines A-A and B-B, respectively, of FIG. 18A.
As shown in FIG. 18B, a P well 11 doped with a p-type impurity is formed in the n-type semiconductor substrate 9. An N well 12 highly doped with an n-type impurity is formed in a surface region on the P well 11. The term "surface region" as used herein refers to a region near the surface of the semiconductor substrate 9. In order to separate the channel regions of the vertical shift registers, separation regions 14 consisting of p-type impurity regions are formed by ion implantation of a p-type impurity in parallel with each other at predetermined intervals in the N well 12. Adjacent separation regions 14 are used to electrically divide the N well 12 so that a region existing between the separation regions 14 constitutes a channel region 22, that is, a transfer path for transferring information charges. The separation regions 14 form potential barriers between adjacent channel regions, and electrically separate the channel regions 22.
An insulating film 13 is formed on the surface of the semiconductor substrate 9. A plurality of transfer electrodes 24 formed of polysilicon films are arranged in parallel with each other so as to intersect the extending direction of the channel regions 22 at right angles, with the insulating film 13 being interposed between the channel regions 22 and the transfer electrodes 24. With reference to the related art image capture section 2i, a group of three adjacent transfer electrodes 24-1, 24-2, and 24-3 constitutes one pixel.
FIG. 19 shows a state of potential distribution within the N well 12 along a channel region 22 during image capture. For capturing an image, one transfer electrode 24-2 of each group of transfer electrodes 24 is turned on, and potential wells 50 are formed in the channel region 22 below the transfer electrodes 24-2. By turning off the other transfer electrodes 24-1 and 24-3, information charges are stored in the potential wells 50 formed below the turned-on transfer electrodes. During transfer, as shown in FIG. 20, transfer clocks φ1, φ2, and φ3 of three phases are applied to each combination of three transfer electrodes 24-1, 24-2, and 24-3 constituting one pixel. Thus, the potential in the channel region 22 extending below the transfer electrodes 24-1, 24-2, and 24-3 is controlled to transfer information charges.
Similarly to the image capture section 2i, the storage section 2s also includes vertical shift registers. The vertical shift registers included in the storage section 2s are shielded from light, and each bit of the shift registers functions as one of storage pixels that store information charges.
In addition, as shown in FIG. 6, a CCD solid state image capture device intended for capturing color images includes two types of columns of color filters: columns having red (R) transmitting filters and green (G) transmitting filters arranged alternately along the vertical transfer direction, and columns having green (G) transmitting filters and blue (B) transmitting filters arranged alternately along the vertical transfer direction. The two types of columns are arranged alternately in a direction crossing the vertical transfer direction. A matrix of pixels formed in this manner enables capture of color images.
However, in the image capture device and the control method thereof according to the above-described related art, transfer is performed by sequentially passing information charges from each pixel to the next. Therefore, such related art device and method have problems in that a long period of time is required for vertical transfer and in that a high quality image cannot be obtained.
For example, in cases where no mechanical shutter is provided for the image capture section 2i, in response to light continuously incident on the pixels of the image capture section 2i, the image capture section 2i continues to generate electric charges even during a period of transfer. Such electric charges may cause noise called "smear". The electric charge that causes such noise is referred to as "smear charge". The amount of smear charge increases in accordance with the increase in the length of period during which information charges are transferred from the image capture section 2i to the storage section 2s. As a result, strong noise will remain in captured images.
Further, in cases where, as in the related art, only one transfer electrode of each group of transfer electrodes in the image capture section 2i is turned on to capture an image, the amount of charge that can be stored in a potential well during image capture is limited. Therefore, if, for example, the image capture section 2i receives light coming from a high brightness subject, the available sensitivity and dynamic range may be insufficient in some cases. Still further, the amount of information charge generated during a period of image capture may exceed the capacity of a potential well, resulting in a reduced dynamic range of the captured image.

Image capture device and controller of image capture device


The invention describes an acoustic liner for use with a magnetic field gradient coil, especially for use in magnetic resonance imaging (MRI) systems. The liner comprises an acoustic sheet (12), preferably of compressible material, adapted to be fitted to the gradient coil, and an acoustic conducting path (10) for carrying an electrical current provided on or in the sheet, arranged such that in use a current pulse can be applied to the gradient coil and a current pulse can be applied to the acoustic conducting path in synchronism therewith, wherein the acoustic conducting path is arranged such that Lorentz forces on the acoustic conducting path in a magnetic field cause the acoustic conducting path to move relative to the gradient coil in such a way that the inner surface (9) of said acoustic sheet remains substantially stationary.

The invention relates to acoustic liners for magnetic field gradient coils, in particular those used for magnetic resonance imaging (MRI).
In a magnetic resonance imaging (MRI) system, a gradient coil is employed to produce a linear magnetic field gradient, defined with respect to 3 orthogonal directions (X, Y and Z). The gradient coil is often a cylindrical structure placed in the center of the bore of a superconducting magnet where a strong and stable magnetic field exists. The gradient coil generally consists of a set of copper conductors arranged in a pattern around the surface of the cylindrical structure. The pattern is calculated to produce the linear field gradient, and methods of calculation and construction of such gradients are well described in the literature. Most gradient coils are of the xe2x80x98active screenedxe2x80x99 type whereby a primary and secondary set of conductors are provided spaced radially apart and connected in series opposition so as to cancel any external field. This arrangement is used in order to reduce eddy currents induced in conducting materials, for example the cryogenics of a superconducting magnet, located outside the structure.
The gradient coils do not normally provide a constant static field gradient. In operation, a pulse of current is applied to the gradient coils to produce the required field gradients over a short period of time. There are a variety of different pulse sequences commonly used. Most current pulses have a short xe2x80x98rise-timexe2x80x99 of the order of 1 millisecond and are repeated at regular intervals during the acquisition of an image.
A common problem with gradient coils is the acoustic noise which is generated during operation.
When a current pulse is applied to the gradient coils in the presence of a magnetic field, a Lorentz force acts on the conductors, causing them to move. Since the pulses are applied at a relatively high frequency, the result is that the gradient coil structure vibrates, creating acoustic noise. As most MRI systems are designed such that there is a patient in the form of a person or animal located inside the magnet and gradient coils, this acoustic noise can be uncomfortable for the patient. Indeed, as magnetic fields become larger and higher gradient strengths are used the acoustic noise can be so intense as to constitute a danger to the patient""s hearing, and measures must be taken to protect the patient from it.
A need therefore exists to reduce or eliminate the acoustic noise produced by a gradient coil.
Previous attempts at reducing the noise have tended to concentrate on making the structure of the gradient coils as stiff and as heavy as possible to reduce the amplitude of vibration, or to provide a layer of xe2x80x98soundproofingxe2x80x99 material within the gradient in order to absorb the mechanical energy.
U.S. Pat. No. 5,764,059 discloses a means of reducing acoustic noise by encasing closed loop conductive pathways in a potting material chosen to maximise the velocity of sound within it. The Lorentz forces acting on different parts of each loop cancel each other so that the total resultant force on the loop is zero. The vibration of opposite sides of each loop with respect to each other is prevented by means of encasing the loop in rigid material.
The present invention provides an acoustic liner for use with a magnetic field gradient coil in a magnetic resonance imaging (MRI) system, the liner comprising
an acoustic sheet, adapted to be fitted to the gradient coil in such a way that the inner surface of the sheet is movable relative to the gradient coil, and
an acoustic conducting path for carrying an electrical current provided within or connected to the sheet,
arranged such that in use a current pulse can be applied to the gradient coil and a current pulse can be applied to the acoustic conducting path in synchronism therewith, wherein
the acoustic conducting path is arranged such that Lorentz forces on the acoustic conducting path in the magnetic field produced by the MRI system cause the acoustic conducting path to move relative to the gradient coil in such a way that the inner surface of said sheet remains substantially stationary.
The acoustic conducting path is preferably in the form of a coating which is so thin that it is flexible, to which can be applied a current pulse in synchronisation with the current pulse applied to the gradient coil. The compressible material may be rubber foam.
When a current pulse is applied to the gradient coils, a corresponding pulse is applied to the acoustic conducting path and there will be a Lorentz force on the acoustic conducting path, just as there will be on the gradient coils. This will cause it to move and compress (or expand) the flexible compressible material. If the phase and amplitude of the current pulse are chosen to cause the inner skin to move an equal and opposite amount to the original gradient inner surface then the net movement of the surface of the sheet of compressible material will be zero. As this is the surface in contact with the air, little or no sound will be generated.
The gradient coil is very stiff whilst the sheet is very compressible. The force required to cause movement of the compressible sheet is therefore much less than the force required to cause the same movement of the gradient coil. Therefore that the current required to move the acoustic coils is much less than the current used to drive the gradient coil.
The acoustic conducting path will obviously have an effect on the magnetic field gradient generated. Due to the fact that the current through it is much less than the current through the gradient coils this will not always be significant, but it is important to minimize this effect to prevent any interference with the imaging process.
One way of achieving this is to provide that the liner flirter comprises an additional acoustic conducting path for carrying an electrical current located on the surface of the sheet of flexible, compressible material adapted to be fitted to the magnetic field gradient coil. Preferably the acoustic conducting path and the additional acoustic conducting path are connected in series opposition.
The acoustic conducting path and the additional acoustic conducting path may comprise identical conducting paths separated by the sheet of compressible material.
As the two conducting paths are wired in opposition the current flowing on one side of the compressible material will be in the opposite direction to the current flowing on the other at all positions and the net magnetic field produced will be small. A refinement to this is to calculate the two conducting paths either side of the compressible material to be slightly different such that the net magnetic field produced by the pair at the center is further reduced.
Preferably the acoustic conducting path and the additional acoustic conducting path are arranged such that the coupling between the gradient coil and the sum of the acoustic conducting path and the additional acoustic conducting path is substantially zero. This will ensure that little or no current or voltage will be induced by the gradient coil across the pair of conducting paths.
The acoustic conducting path and additional acoustic conducting path may be arranged such that there is a mutual inductance between the acoustic conducting paths and the gradient coil, whereby the resistance, inductance and coupling constant to the gradient coil are such that the induced current and corresponding decay characteristic in the acoustic conducting paths achieve at least in part the desired acoustic cancellation.
An alternative method of providing acoustic conducting paths which will not interfere with the imaging process is to arrange for a single pattern on the inner skin of the liner, wherein the pattern itself is arranged to produce a linear field gradient whilst still matching as closely as possible the vibration pattern of the gradient coil. If this field is small compared to the field produced by the gradient then it can be accommodated without detriment to the imaging process by xe2x80x98signal conditioningxe2x80x99 of the gradient drive such that the gradient field and the field produced by the acoustic conducting path add to produce the resultant field originally required.
An alternative embodiment of the invention is to use a rigid tube as the acoustic liner, but provide active support means at a plurality of points around its surface between the gradient coil and acoustic liner it e.g. piezoelectric position transducers. During operation of the gradient coils an appropriate signal is applied to the active support means in anti-phase to the vibration of the gradient coil at the position of each support means such that the motion of the acoustic liner is cancelled.
According to a second aspect, the invention provides a means for generating a magnetic field gradient, comprising
a field gradient coil,
an acoustic sheet, fitted to the gradient coil in such a way that the inner surface of the sheet is movable relative to the gradient coil
an acoustic conducting path for carrying an electrical current provided within or connected to the sheet,
means for providing a current pulse to the field gradient coil and a current pulse to the acoustic conducting path in synchronism, wherein
the acoustic conducting path and the means for providing a current pulse thereto are arranged such that, in use, Lorentz forces on the acoustic conducting path cause the acoustic conducting path to move relative to the gradient coil in such a way that the inner surface of said sheet remains substantially stationary.
In a further embodiment of the invention, a similar acoustic liner is applied to the ends of the magnet structure. The gradient coil is mounted to the magnet and its vibration will be transmitted to the magnet itself which will produce acoustic noise. The acoustic liner at the end would take the form of a substantially flat xe2x80x98pancakexe2x80x99 fixed to each end and would prevent acoustic noise being transmitted into the room occupied by the magnet.


The invention concerns a device (1) for generating protocol data for an injection pen (2). The device (1) comprises a motion sensing unit (13) including one or more of a gyroscope and an accelerometer in order to generate one or more of a gyro signal and an acceleration signal. The device comprises a signal processing unit (14) which implements an analyser which is configured to analyse one or more of the gyro signal and the acceleration signal and to generate protocol data reflecting an adjusted dosage of a medicament. Optionally, the analyser is configured to generate protocol data reflecting delivery of the adjusted dosage of the medicament.

Many patients need therapies based on individualized injections of medicaments. For example, patients suffering from diabetes often require individualized injections of insulin multiple times every day. Medicaments such as insulin are delivered in doses that normally correspond to individual characteristics of a patient, such as body mass, age, blood sugar level, gender, etc, and to the current behaviour of the patient, such as the intention to have a meal.
Multiple daily injections (MDI) using an injection pen is a widely applied method in therapy, such as in insulinotherapy. Injection pens include an injection needle for delivery of the medicament from a reservoir of the injection pen into the patient. Injection pens further include a dosing mechanism for adjusting a dosage of the medicament and an activation mechanism for delivery of the adjusted dosage of the medicament into the patient.
Usually, injection pens are purely mechanical devices. An injection pen usually accommodates multiple dosages of the medicament so that a patient can use the same injection pen multiple times. Typically, the reservoir of the injection pen can be replaced.
Delivering an individualized dosage of a medicament using an injection pen includes performing a sequence of several steps with the injection pen, such as, for example, the following steps. In a first step, the patient adjusts the dosage of the medicament to be delivered by manipulating a dosing mechanism of the injection pen, such as by rotating by an appropriate angle a dosing adjustment wheel of the injection pen. After having adjusted the dosage of the medicament, in a second step, the patient inserts the injection needle into the body by penetrating the skin with the injection needle. After having inserted the injection needle into the body, in a third step, the patient initiates the delivery of the adjusted dosage of the medicament by manipulating the activation mechanism, such as by pressing a delivery push-button of the injection pen. After having initiated the delivery of the dosage of the medicament, in a fourth step, the patient waits for a while in order to avoid leak out of the medicament. After having waited for a while, in fifth step, the patient retracts the injection pen. After having retracted the injection pen, in a sixth step, the patient replaces the injection needle. After having replaced the injection needle, in a seventh step, the patient puts away the injection pen.
MDI patients have to carefully record protocol data about each injection of the medicament. Protocol data typically includes the dosage of the injection and the time of the injection. On the basis of protocol data, time and/or dosage of future injections can be determined. Protocol data is kept in a diary. Often, protocol data is manually recorded in a diary book or manually entered into a diary of a portable electronic device, such as a smartphone, a personal medical assistant, etc. The portable electronic device can be configured to analyse the protocol data and to inform the patient about the time and/or dosage of future injections, for example about the need of a further injection after the lapse of a time period or in case the patient is approaching the time of day when the patient usually eats a meal. The portable electronic device can be configured to inform the patient about the need of a further injection by generating an alarm, such as an optical alarm, an acoustical alarm, a vibration etc.
For many patients and/or in many situations, it is difficult to correctly and consistently update protocol data of each injection. For example, the portable electronic device may generate an alarm signalling that an injection is required when the patient is in a business meeting, in a traffic jam, or otherwise averted. In such situations, the patient usually delays the injection. However, after the delay and after having performed the injection, the patient may forget to update correctly the time of the injection. In another scenario, it may happen that the patient injects an incorrect dosage of the medicament, for example because the patient incorrectly adjusts the dosage or because the patient retracts the injection pen too early. In such situations, it may happen that the patient is not even aware that the protocol data needs to be adjusted. Moreover, even if the patient is aware of the incorrect dosage, it may happen that the patient forgets to adjust protocol data accordingly.
Poor management of individualized injections of medicaments can lead to serious and potentially life threatening complications. An accidental double insulin injection may result into a hypoglycaemic coma requiring hospitalization of the patient.
Several systems on the market allow basic logging functionality for MDI patients. For example, clip on adapters for an injection pen are available which determine and display the time since last injection. Replacement caps allow entering of bolus dosage.
WO2010/112575 relates to an arrangement for administering insulin or other medicines from a cartridge. A dosing knob enables setting and administering of a dose. The arrangement includes means for determining a set dose. The means for determining a set dose can include electrical contacts or magnetic elements which produce on the basis of a relative interaction of corresponding electrical contacts or magnetic elements an electrical signal in accordance to the rotation of the dosing knob. Data reflecting a set dose can be transmitted to a central data processing system.
US2016/0030683 discloses smart sensors that can be coupled to or retrofitted onto injection pen injectors. The smart sensors improve tracking of drug self-administration and stop medication errors that occur primarily through self or automated injection, e.g. due to incorrect or incomplete dosing, excessive dose or rate, incorrect drug, or drug degradation. The smart sensor can be in-line with respect to a drug delivery system's path of delivery. The pen can have a needle adapter that includes the smart sensor. Quickconnect interlocking means allow for coupling and decoupling of the components. The smart sensor is capable of wirelessly communicating with a portable user interface. The sensor can be a fluid detection sensor being in contact with the fluid. The sensor can use impedance spectroscopy. Other sensing techniques can include optical, electrical, mechanical, thermal and/or rheological techniques.
EP2427236A2 discloses a medication injection supervisor device comprising a sensor to detect an injection automatically. The sensor includes a micro switch or a micro optics subsystem. Usage data is detected. Usage data includes time of injection. Dosage of an injection is recorded. A display is included to display injection data.
WO2012001493A2 discloses a replaceable cap for a transdermal liquid dosing device such as an insulin pen. The cap includes an elongate hollow body with a first open end which can be placed over a front part of the dosing device and a second closed end opposite the first end. The cap body also includes a cavity which opens into the interior of the cap body and which houses a control unit which includes a timer unit, a switch mechanism that stands at least partially proud of the cavity so as to project into the interior of the body, and a timer display unit which displays time counted by the timer unit on an outer surface of the body of the cap. The switch mechanism is engaged by abutment of a surface of the front part of the dosing device when the cap is placed on the dosing device, and released when the cap is removed from the dosing device, the engagement and/or releasing of the switch mechanism causing the timer unit to reset after the elapse of a predetermined period of time, the time since the timer unit was last reset thereby indicating the time that has elapsed since the dosing device was last used.

Device for generating protocol data for an injection pen


An oscillator control system includes a phase-locked loop having a programmable frequency divider operative within the loop. A switch is further included within the phase-locked loop to permit the loop to be open or closed in response to an input signal. A counter accumulates oscillator clock signal counts between each successive rising edge portion of the applied sync signal. A pair of shift registers sequentially store successive clock signal counts for the current and previous sync signal intervals. The output counts are compared for consistency by producing a difference signal therebetween which is utilized to control the phase-locked loop switch and close it once the consistency of sync signal has been established. The output counts of the shift registers are combined and used to provide a scaling factor which sets the frequency division of the programmable frequency divider within the phase-locked loop and properly scales the oscillator frequency to the sync signal frequency.

Computer display monitors provide a convenient interactive capability which virtually all interactive computer systems rely upon. One of the most common types of computer display monitors is that utilizing a cathode ray tube display system. In such monitors, a cathode ray tube is provided which directs one or more intensity modulated electron beams at a phosphor display screen. In systems utilizing a raster scan, the electron beams are scanned at different frequencies in the horizontal and vertical display directions while the electron beams are intensity modulated by the video information to produce the desired video display. Because it is generally desirable to provide relatively flat display screens housed with compact monitor housings, the geometric relationships between the cathode ray tube electron source or sources and the display screen gives rise to a variety of geometric distortions of the scanned raster. In addition, other sources of distortion such as scanning system nonlinearity exacerbate these geometric distortions. In virtually all computer monitors, the scan process is adjusted or corrected to accommodate these problems in a process generally known as "geometric correction". Basically, this process involves utilizing the horizontal and vertical scan rate signals available within the scanning and synchronizing system to generate corrective signals. Since the use of such correction systems relies upon the appropriate relationship between horizontal and vertical scan signals, their synchronization and timing, and the corresponding predictable area of the raster scan display, accurate geometric correction requires reliable synchronizing signals.
The process of geometric correction is further complicated by the tendency of most computer display monitors to operate at a plurality of scan frequencies often extending over a substantial frequency range.
Thus, there arises a need in the art for reliable scan synchronizing systems to supply the necessary signals for accurate geometric correction of the display appropriate for use in the demanding environment of multifrequency display monitors.
Accordingly, it is a general object of the present invention to provide an improved geometric correction system. It is a more particular object of the present invention to provide a reliable source of accurately synchronized scan related signals for use in forming geometric correction signals suitable for use in multifrequency monitors.

Phase locked loop made operative when stable input sync signal is detected


A design assistance device assists design of a processing device to execute processing and includes an acquirer, divider, communication code generator, and outputter. The acquirer acquires processing code describing content of the processing. The divider divides the processing code into modules and determines, for each of the modules, an execution environment in which the module is to be executed, from among a plurality of execution environments provided on the processing device. The communication code generator generates, when a module of the plurality of modules includes partial processing prioritized for execution in a second execution environment other than a first execution environment determined for execution of the module, a communication code for communication between the first execution environment and the second execution environment to execute the partial processing in the second execution environment. The outputter outputs the plurality of modules and the communication code to the processing device.

In recent years, a computer provided with multiple execution environments by inclusion of multiple OSs and multiple processors is often used as a controller such as a programmable logic controller (PLC). This requires a designer to take into consideration characteristics of each execution environment such as available libraries and operating performance in designing applications that operate in each environment, rendering design work complicated.
To address a difference in execution environments, a method for automatically changing a discrepancy in source code derived from the difference in execution environments is proposed (refer to Patent Literature 1, for example). Patent Literature 1 discloses a device that processes a generated source code based on a processing rule corresponding to a platform to be used and outputs a source code corresponding to the platform.

Assistance device, design assistance method and program


There is provided an improved process for preparing cefixime. Thus, for example, 7-amino-3-vinyl-3-cephem-4-carboxylic acid is reacted with 2-mercapto-1,3-benzothiazolyl-(Z)-2-(2-aminothiazol-4-yl)-2-(methoxycarbonyl)-methoxyimino acetate in tetrahydrofuran and water at 4° C. in the presence of triethylamine. The reaction mass is extracted with ethyl acetate. 7-[2-(2-Amino-4-thiazolyl)-2-(methoxycarbonylmethoxyimino)acetamido]-3-vinyl-3-cephem-4-carboxylic acid triethylamine salt present in the aqueous layer is hydrolyzed with sodium hydroxide in less than 30 minutes and aqueous hydrochloric acid is added immediately to adjust the pH to 4.8 to 5.2. Then, aqueous hydrochloric acid is added at 35° C. to adjust the pH 2.5 and cooled to crystallize cefixime trihydrate in high purity.

U.S. Pat. No. 4,409,214 disclosed 7-Acylamino-3-vinylcephalosporanic acid derivatives and pharmaceutically acceptable salts thereof. These compounds are antibacterial agents. Among them Cefixime, chemically 7-[2-(2-amino-4-thiazolyl)-2-(carboxymethoxyimino)acetamido]-3-vinyl-3-cephem-4-carboxylic acid is an orally active cephalosporin antibiotic and is more potent against gram-negative bacteria. Cefixime is represented by the following structure:

Processes for the preparations of Cefixime and related compounds were disclosed in U.S. Pat. No. 4,409,214, J. Antibiotics (1985), 38, 1738 and WO 95/33753, U.K. Patent Application No. 2 330 140, U.K. Patent Application No. 2 330 141, U.S. Pat. No. 6,313,289, WO 98/06723 and U.S. Pat. No. 6,800,755 B2.
U.K. Patent Application No. 2 330 141 described the process for preparing cefixime by hydrolyzing in a halogenated aliphatic hydrocarbon (e.g., methylenedichloride) ester compound of formula-A:
wherein R represents (C1-C4) alkyl group;with potassium carbonate in the presence of phase transfer catalyst at ambient temperature for 30-90 minutes.
U.K. Patent Application No. 2 330 140 described a process for preparing cefixime by treating the compound of formula A with an inorganic base in dim ethyl formamide and water for 1 hour 30 minutes to 2 hours and isolating cefixime.
U.S. Pat. No. 6,800,755 B2 described a process for preparing cefixime by dissolving alkyl ester of formula A in water and water immiscible solvent such as ethyl acetate using sodium bicarbonate, hydrolyzing with sodium hydroxide at 0-25° C. and isolating cefixime by acidifying the reaction mass.
The processes described in U.K. Patent Application No. 2 330 141, U.K. Patent Application No. 2 330 140 and U.S. Pat. No. 6,800,755 B2 suffer from any of the following problems: a) color and quality are poor, b) contamination of cefixime with high boiling point solvent such as dimethyl formamide. The removal of the residual solvents is difficult owing to sensitivity of cefixime to high temperature.
J. Antibiotics (1985), 38, 1738 described processes for preparing cefixime involving protection and deprotection steps. The processes described required purification of cefixime by column chromatography. Methods involving column chromatographic purifications cannot be used for large-scale operations, thereby making the process commercially not viable.
Process for preparing cefixime described in U.S. Pat. No. 4,409,214 and WO 95/33753 are lengthy involving many protecting and deprotecting steps and so not commercially viable.
U.S. Pat. No. 6,313,289 B1 described the purification of cefixime by forming a crystalline amine salt of crude cefixime, converting the salt into sulfuric acid addition salt of cefixime and recovering pure cefixime from sulfuric acid addition salt of cefixime.
WO 98/06723 is related to cefixime dicyclohexyl amine salt and purification of cefixime via dicyclohexyl amine salt.
The purification of cefixime by the processes described in U.S. Pat. No. 6,313,289 B1 and WO 98/06723 are lengthy and complicated involving many crystallizations, neutralizations and salt formations.
The present invention is an improved, commercially viable process solving the aforesaid problems associated with processes described in the prior art.


A developing unit includes an impressed member to which a voltage is impressed, a contact member which is made of a metal wire rod and urged by an elastic force to make contact with the impressed member and to be connected electrically with the impressed member, and a supporting plate member which supports the contact member at an inner surface side and exposes a part of the contact member as a contact part for an outer connection to an outer surface from an attaching hole.

1. Field of the Invention
The present invention relates to a developing unit used in an image forming device such as a copy machine, a printer and a facsimile machine for adhering a developer on an electrostatic latent image and developing the electrostatic latent image, and to an image forming device having the developing unit.
2. Description of the Related Art
In the above-described image forming device, when developing an electrostatic latent image, a bias voltage is impressed or a voltage is impressed for charging a developer (toner). An electrical wiring becomes necessary for the impressing operation. As an example of such a wiring, according to a first conventional image forming device, a bias electrode consisting of a piano wire, a stainless steel wire for a spring, a phosphor bronze wire or the like is provided on a sleeve flange. One end of the bias electrode is formed in a coil spring shape and makes contact with an electrode plate. According to a second conventional image forming device, a coil spring is used for feeding a bias voltage to developer charging members provided on both end parts of the developer carrier in a longitudinal direction. In case the developing unit can be inserted into or removed from the image forming device, an electrode for an outer connection is provided in a developing unit for feeding the voltage from the image forming device. Conventionally, an electrode consisting of a leaf spring is used.
By the wiring structure processed into the coil spring shape used in the first conventional image forming device, an attaching method is difficult. According to the second conventional image forming device, a structure for inserting in the coil spring becomes necessary, and a place where the coil spring can be used becomes limited. In addition, a sheet metal processing becomes necessary for the electrode structure formed by the leaf spring and the manufacturing costs increase.

Developing unit and image forming device having the developing unit


In a preferred embodiment, there is provided a protecting group for protecting the thiol side chain of a cysteine residue, the protecting group comprising a Diels-Alder cycloadduct of a furan and a maleimide, and optionally, a linker interposed between the thiol side chain and the Diels-Alder cycloadduct.

Peptide synthesis involves formation of amide bonds between multiple amino acids by the condensation reaction of the carboxyl group of one amino acid with the amino group of another amino acid. To synthesize a peptide of specific amino acid sequence, solid phase peptide synthesis may be used to form a peptide chain using successive reaction and introduction of preselected amino acids to a solid insoluble and porous support, which includes a polymeric resin bead having a reactive linker group for attaching a growing peptide chain. The reactive linker group may include an amino group, and the amino acids to be introduced to the solid support may be protected on the N-terminus (and possibly the side chain as needed), using known protecting groups, such as tert-Butyloxycarbonyl (Boc) or fluorenylmethyloxycarbonyl (Fmoc) protecting group.
Solid phase peptide synthesis may involve repeated cycles of coupling and N-terminal deprotection reactions, with washing of the resin bead between each cycle. Specifically, a first N-terminus protected amino acid is coupled to the amino group of the reactive linker group in the solid support, and the amino acid is deprotected to leave the amino functional group of the amino acid available to form an amide bond with a second N-terminus protected amino acid. The cycles are repeated with a preselected sequence of amino acids, and until the peptide of the desired length and sequence is formed. The peptide as formed is then cleaved from the solid support, isolated and purified, and may be subject to further treatment.
Aside from the primary peptide sequence which may be obtained with solid phase peptide synthesis and which will fold into defined secondary structures, disulfide bonds play an important role in the organization of proteins and peptides, such as determining the ternary structure. Formation of correct disulfide bonds between correct cysteine residues may thus facilitate formation of correct three-dimensional structure, especially in short peptides. Disulfide bonds may however present challenges in synthesizing peptides and proteins by way of biotransformations; while the linear sequence may be readily programmed into DNA, the information regarding which disulfide bonds should be formed is often regulated by additional factors and is part of the post-translational modifications.
It has been recognized that a synthesized peptide intended to function as a natural peptide of the same amino acid sequence and with specific disulfide bonds may require further treatment during and after peptide synthesis to ensure that the synthesized peptide possesses the same natural disulfide bonds. Previously, orthogonal protection of the thiol side chains (involved in forming disulfide bonds) of cysteine residues have been used to effect selective deprotection and disulfide bond formation after peptide synthesis. Specifically, a crude peptide is formed with cysteine residues having their respective thiol side chains protected with a protecting group, such as acetamidomethyl, tert-butyl, 3-nitro-2-pyridine sulfenyl, 2-pyridine-sulfenyl or trityl, and which remains on the thiol side chains after peptide synthesis. By having each pair of specific cysteine residues intended to form a disulfide bond having orthogonal protection independent from other pairs of cysteine residues, it has been possible to successively deprotect different pairs of cysteine residues and introduce regioselectivity to disulfide bond formation.
Peptide synthesis may thus employ multiple pairs of cysteine protecting groups, in cases where multiple cysteine bonds are desired. A bioactive peptide ordinarily possesses both the linear amino acid sequence and the specific disulfide bonds made in the naturally-occurring material, which if present contribute to the three dimensional structure. For example, if there are 8 cysteines in a short peptide, these would make 4 disulfide bonds, and there would be 70 (8!4) possible structures containing 4 disulfide bonds that can be generated, where only 1 is the desirable compound. Such need for increasing degrees of orthogonality between protecting groups increases the complexity of the peptide, and requires specialist and fine-tuning of peptide synthesis conditions, as well as iterative cycles of reaction and purification to isolate the desired compound and remove the unwanted reagents. This is a slow, costly and inefficient process, which may lead to low yields and complex purification problems, and which may effectively prohibit scalability to produce larger amounts of the desired peptide.
An improvement may reside with use of a common class of protecting groups that are removed under the same trigger and differ from one another only by the threshold level of that trigger. This may preferably involve only a single reagent introduced to the reaction mixture, with slow increase of its concentration. An existing example involves use of acid-sensitive end-caps, although such approach has two complications: the acidic conditions used for deprotection are not compatible with the conditions required to dimerize the cysteine residues, and the dynamic range between the acid-sensitivity of the protecting groups is insufficient to provide the required levels of selectivity, with chemistry relegated between a pH of 0 and 5, sufficient for no more than three different acid-sensitive protecting groups (e.g. triggered at pH=0, 2.5 and 5). However, 2.5 pH units may not provide sufficient discrimination in reaction rates to ensure complete selectivity, and being triggered at pH 5 may result in background cleavage at neutral pH and may also limit synthetic operations available to the chemist making the peptide.
It has thus been appreciated that known regioselective formation of disulfide bonds may be associated with greater costs, time and complexity and reduced yield and selectivity, often stemming from the need to develop customized residues and protecting groups, and in the absence of any general approach to providing orthogonal protection.

Thermally sensitive protecting groups for cysteine, and manufacture and use thereof


The invention is an improved anatomical doll that has a clear tummy and back that swivel open to reveal either removable or non-removable organs. The removable organs are held in place by indentations in the abdomen of the doll, whereas each of the non-removable organs has an individual recess that allows the non-removable organ to be hidden further within the abdomen. An alternative embodiment of the invention is to provide a doll with missing limbs and corresponding prosthetic limbs. The primary benefit of the improved anatomical dolls is to provide a means to educate small children about the human anatomy, especially children that need an upcoming surgical procedure explained to them.

A. Field of the Invention
The present invention relates to the field of dolls, more specifically, dolls that illustrate the various organs and missing limbs with corresponding prosthetics.
Children undergo various medical procedures everyday, which requires special attention in explaining the upcoming procedure to the child. In light of this sensitive time, there is a need for a doll that can illustrate the various internal organs or limbs that may be impacted by the upcoming procedure. An additional use of said doll would be to provide a basic lesson in Anatomy to children.
B. Discussion of the Prior Art
As a preliminary note, it should be stated that there is an ample amount of prior art that deals with dolls. As will be discussed immediately below, no prior art discloses a children.
The Coomansingh Patent (U.S. Pat. No. 6,159,017) discloses a doll with preprogrammed auditory internal organs for a useful tool of teaching children about the human body. However, the doll disclosed under the Coomansingh Patent does not have organs that are either removable or non-removable, nor does the doll feature missing limbs with corresponding prosthetics.
The Levin Patent (U.S. Pat. No. 5,295,694) discloses a game and method of playing said game to simulate a minimally invasive surgical procedure. However, the game disclosed under the Levin Patent does not utilize a doll with a clear tummy and back that open to expose either removable or non-removable organs, and/or missing limbs with corresponding prosthetics.
The Summerville Patent (U.S. Pat. No. 4,822,285) discloses a toy doll with internal organs. However, the toy doll disclosed under the Summerville Patent resembles a cat, as opposed to a human. Furthermore, the toy doll does not have missing limbs with corresponding prosthetics, or organs that may be non-removable.
The Mavrikis Patent (U.S. Pat. No. 5,232,369) discloses a handicapped doll having a removable hair piece and missing limbs with corresponding prosthetics. However, the handicapped doll disclosed under the Mavrikis Patent does not have a clear tummy or back that reveal organs that may either be removed or pushed further into the abdomen via a recess that hides the organ.
The Munson Patent (U.S. Pat. No. 2,678,505) discloses a toy doll for simulating surgery. However, the toy doll disclosed under the Munson Patent does not have a clear tummy and back, and the abdomen does not have indentations to hold the removable organs or non-removable organs that have recesses to hide said non-removable organ.
The Pedersen Patent (U.S. Pat. No. Des. 310,856) illustrates a design for an anatomically correct doll, which does not have a clear tummy and back, removable or non-removable organs, and/or missing limbs with corresponding prosthetics.
The Anatomical dolls by The Feelings Company, Inc., are an example of non-patent prior art, which does not have a clear tummy and back, removable or non-removable organs, or missing limbs with corresponding prosthetics.
While the above-described devices fulfill their respective and particular objects and requirements, they do not describe a therapeutic doll that provides for the advantages of the therapeutic doll. In this regard, the therapeutic doll departs from the conventional concepts and designs of the prior art.


A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

The present invention relates to a signal processor incorporating digital to analog converters. More particularly, the present invention relates to methods and apparatus for varying the circuit configuration, output voltage range (the difference between the lowest possible output voltage and the highest output voltage) and level (the variance, however small or large, between ground and the lower limit of the output signal range) of such a signal processor.
A digital to analog converter (DAC) converts a digital input word to an analog output. Signal processors which utilize DACs typically operate in either a unipolar or bipolar mode, both of which will be briefly described below.
The generic equation for determining VOUT in unipolar and bipolar signal processor is shown in Equation 1:                               V          OUT                =                  G          *                      V            REF                    *                      (                                          K1                *                                                      INPUT                                                              xe2x80x83                                                            CODE                                                        MAX                                                              xe2x80x83                                                            INPUT                                                              xe2x80x83                                                            CODE                                                              -              K2                        )                                              (        1        )
where MAX INPUT CODE is the maximum value of INPUT CODE or 2nxe2x88x921, when INPUT CODE is an n-bit digital word, G is the gain of the signal processor and K1 and K2 are constants that determine the configuration mode. In the unipolar mode configuration (e.g., when the output voltage varies from 0 volts to 5 volts or from 2.5 volts to 7.5 volts) K1=1 and K2=0 so that VOUT varies between 0 and |G*VREF|. In the bipolar mode configuration (e.g., output voltage varies from xe2x88x925 volts to 5 volts, K1=2 and K2=1 so that VOUT varies between xc2x1G*VREF.
FIG. 1 shows an example of a previously known unipolar signal processor 10, which receives an input voltage VREF, control signal UPDATE and INPUT CODE, and generates analog output VOUT. INPUT CODE typically is an n-bit digital word that signal processor 10 uses to convert digital input voltage VREF to analog output VOUT. UPDATE is a binary input signal which determines when the INPUT CODE can be used to convert VREF to produce a new VOUT. When UPDATE is LOW, VOUT remains substantially constant. When UPDATE changes from LOW to HIGH, DAC 10 converts VREF to analog output VOuT based on the INPUT CODE.
Signal processor 10 includes current converter (DAC) stage 12, op-amp 22, capacitor 24 feedback resistor 20 and switch-resistance compensation element SF. Current converter stage 12 includes R-2R ladder 14, switches 161 to 16n and latch and decoder 18 and switch-resistance compensation element ST.
The R-2R ladder 14 is coupled between VREF and switches 161 to 16n, and includes n branches each containing a resistor 25i and a termination branch having resistor 27 and switch-resistance compensation element ST. The R-2R ladder 14 includes a resistor 23 between the top nodes of each branch. Typically, resistors 25 are twice as large as resistors 23. Termination branch resistor 27 is of the same value as resistors 25i. Switch-resistance compensation element ST of the termination branch is connected to GROUND. Resistor 27 and switch-resistance compensation element ST of the termination branch serve to balance the impedance of the R-2R ladder 14 at each top node. Without the termination branch, the current flowing through each branch would differ and thereby cause errors in the current conversion process.
The INPUT CODE in combination with the reference voltage causes an intermediate current, IDAC to flow according to Equation 2, R is the input impedance of the R-2R ladder:                               I          DAC                =                              (                                          V                REF                            R                        )                    *                      (                                          INPUT                                                  xe2x80x83                                                CODE                                            MAX                                                  xe2x80x83                                                INPUT                                                  xe2x80x83                                                CODE                                      )                                              (        2        )
Feedback resistor 20, feedback switch-resistance compensation element SF, op-amp 22 and capacitor 24 form a current to voltage converter. The op-amp 22 has an inverting input (xe2x88x92) coupled to current converter 12, feedback resistor 20 and capacitor 24, a non-inverting input (+) coupled to GROUND, and an output coupled to VOUT. Capacitor 24 is coupled between inverting input (xe2x88x92) and VOUT to provide a first feedback loop around the op-amp 22. This first feedback loop is not required for operation. Feedback resistor 20 and switch-resistance element SF are coupled between inverting input (xe2x88x92) and VOUT to provide a second feedback loop around the op-amp 22. Switch-resistance compensation element SF, like switch-resistance compensation element ST, is required for matching of the on-resistance of switches 16i from the R-2R ladder 14.
The current to voltage converter operates to convert intermediate current IDAC to the output voltage VOUT. The resulting, VOUT is shown in Equation 3:                               V          OUT                =                                            -                              I                DAC                                      *            R                    =                                    -                              V                REF                                      *                          (                                                INPUT                                                        xe2x80x83                                                      CODE                                                  MAX                                                        xe2x80x83                                                      INPUT                                                        xe2x80x83                                                      CODE                                            )                                                          (        3        )
FIG. 2 shows a bipolar signal processor 30 which includes circuit 14, comprising an inverting amplifier 40 and gain resistors 42 and 44 coupled between VREF, and current converter 12. Amplifier 40 and gain resistors 42 and 44 serve to invert input voltage VREF. Inverted VREF (i.e., xe2x88x92VREF) is used to generate IREF, as described above in FIG. 1. Alternatively, amplifier 40 and resistors 42 and 44 could be located external to signal processor 30 in the signal path.
VREF is also coupled to level resistor 38, which is then coupled to the inverting input of op-amp 22 via switch-resistance compensation element SO. Capacitor 24 and feedback resistor 36 are coupled between inverting input (xe2x88x92) and VOUT to provide first and second feedback loops, respectively, around op-amp 22. This is one technique for applying opposite polarity to the current converter and to the level circuitry, a condition which is required for operation of the DAC. However, other suitable techniques for establishing this condition are well-known in the art. Switch-resistance compensation elements SO and SF are included in the circuit to match the impedance of the resistors and switches in the R-2R ladder 14 described above in FIG. 1.
A first signal path from VREF to VOUT via level resistor 38, feedback resistor 36 and op-amp 22, inverts the input signal VREF at VOUT. A second signal path from VREF to VOUT via gain resistors 42, 44, inverting amplifier 40, current converter 12 and op-amp 22, produces the voltage shown in Equation 4 at VOUT:
V=xe2x88x92IDAC*2Rxe2x80x83xe2x80x83(4)
where IDAC is defined by Equation 2. The total output voltage at VOUT is the combination of the voltage from the first and second signal paths and is shown in Equation 5:                               V          OUT                =                              V            REF                    *                      {                                          2                *                                  {                                                            INPUT                                                                    xe2x80x83                                                                  CODE                                                              MAX                                                                    xe2x80x83                                                                  INPUT                                                                    xe2x80x83                                                                  CODE                                                        }                                            -              1                        }                                              (        5        )
Equation 5 equals the desired result of the voltage conversion shown in Equation 1 for a bipolar configuration where K1=2, K2=1 and G=1. Thus, for a 10 volt input (VREF=10), the first signal path yields a voltage of xe2x88x9210 volts, while the second signal path provides a voltage between 0 and 20 volts based on the INPUT CODE so that VOUT has a range of xc2x110 volts.
The prior art consists of various configurations of signal processor 10 and/or signal processor 30 from FIGS. 1 and 2 in monolithic or discrete form. The configuration was typically chosen to be unipolar or bipolar only and connected permanently as such. To make the configuration switchable between unipolar and bipolar modes, however, extra discrete switches and operational amplifiers have been added, as shown in FIG. 3.
In FIG. 3, non-inverting amplifier 52 and switch 56 are connected to the signal processor 30 from FIG. 2. Amplifier 52 has inverting input (xe2x88x92) and its output coupled to resistor 38 and noninverting input (+) coupled to switch 56. Switch 56 is provided to couple noninverting input (+) to either VREF or VOUT based on an external logic signal. The signal processor in FIG. 3 operates in unipolar mode when switch 56 connects noninverting input (+) of amplifier 52 to VOUT and operates in bipolar mode when switch 56 connects noninverting input (+) of amplifier 52 to VREF. Otherwise the signal processor in FIG. 3 operates in essentially the same manner as those described above in FIGS. 1 and 2 based on the selected mode. The additional external op-amp 52 (and switch 56) adds an offset and, as such, may provide less than optimum dc performance of the signal processor.
Additionally, the ac performance of the signal processor is not optimum due to the finite bandwidth and slew rate of this op amp. A specific implementation of the circuit shown in FIG. 3 is shown in the data sheet for LTC 1597 produced by Linear Technology Corporation of Milpitas, Calif.
Accordingly, it is the object of this invention to provide methods and apparatus for varying the circuit configuration, output voltage range and level of a signal processor in a monolithic solution without the need to add substantial external circuitry, complexity and cost.
The signal processor of the present invention includes a converter circuit and utilizes resistors (or other suitable impedance elements) and programmable switches to control whether the signal processor operates in unipolar or bipolar mode, to set the output voltage range, the level of the circuit and/or to provide an asymmetrical range for output signal. Sets of resistors and programmable switches are preferably provided in a level resistor circuit and/or a feedback resistor circuit to enable the invention.
In an alternative embodiment a signal processor that receives an input signal, a first control word and a second control word, and provides an output signal is provided. The signal processor includes at least two control elements, each of which receives an input signal and a control word and provides a respective intermediate signal. The input signal for one of the control elements is the output signal of the signal processor. This embodiment of the signal processor also includes a summing element that receives a combination of the intermediate signals such that the level, linearity or output signal range of the output signal are programmable based on the control words.
In one embodiment, the signal processor can include a programmable level circuit which functions as a third control element, receives an additional digital word, and preferably serves to adjust the level of the circuit.
Additionally, the present invention can preferably use a single reference voltage to provide an asymmetrical output range by selecting the appropriate resistor and switch combination for the level and feedback resistor circuits.
The present invention also provides for a method of varying the configuration, output voltage range or level of a signal processor. The method determines the mode of operation of the circuit (e.g., unipolar or bipolar), the output voltage range or the level of output signal using programmable switches.
Another embodiment of the invention is a signal processor circuit that receives an input signal and produces an output signal based on the input signal.
The signal processor circuit preferably includes at least one processing element that is adapted to perform a process on the input signal in order to produce the output signal. The signal processor circuit preferably provides a signal-dependent current.
The signal processor circuit preferably also includes a signal level node and a buffer coupled between the processing element and the signal level node. The buffer buffers the signal level node from the signal dependent current.

Circuits, systems, and methods for signal processors that buffer a signal dependent current


A precipitated silica characterised by the presence of specific acid sites on its surface and a process for its manufacture.

The use of precipitated silica as a reinforcing filler in polymeric compositions, as catalyst support, as anticaking agent, as rheology modifier or abrasive in toothpaste compositions is known.
There is always the need of precipitated silica which can be successfully used in multiple applications such as reinforcing filler in polymeric compositions and catalyst or catalyst support.

Precipitated silica and process for its manufacture


A technique to provision a converted infrastructure (CI) includes generating task definitions to configure respective ones of compute, storage, and network components of a converged infrastructure (CI) when invoked. Each task definition includes a task identifier (ID), one or more component configuration commands, and one or more task arguments through which one or more corresponding component configuration parameters are passed to corresponding ones of the one or more component commands. The technique further includes automatically invoking each of the task definitions by task ID according to an ordered sequence in order to configure the CI. The automatically invoking includes providing the one or more component configuration commands and the corresponding one or more passed configuration parameters of each invoked task definition to the respective ones of the CI components.

A data center, cloud resource, or the like, may be implemented in the form of a converged infrastructure (CI). The CI is a set of integrated Information Technology (IT) components, such as storage, network, compute, and virtualization software and/or device components. The components of the CI must be initially configured, i.e., provisioned, prior to a first operational use of the CI. Commands to provision each component must conform to a vendor specification for the given component, i.e., the syntax and structure of such provisioning commands must follow different configuration data models defined by the different component vendors. Additionally, a user may be required to provide/input configuration information in a vendor-specific format to construct the provisioning commands that configure the corresponding vendor component. As a result of the vendor-specific nature of provisioning, conventional provisioning approaches typically use a collection of vendor-specific provisioning systems for the CI, each system to provision a corresponding one of the different vendor-specific components of the CI. The need for the different vendor-specific provisioning systems, and the need for the user to be aware of the different vendor-specific configuration inputs, add complexity to provisioning operations, unnecessarily burden the user, and generally make automated provisioning difficult to achieve.

Automated technique to configure and provision components of a converged infrastructure


First and second terminals between which a predetermined source voltage is applied and between which are connected, a plurality of electronic circuit blocks connected in series, and a plurality of semiconductor devices which are turned on when voltages exceeding predetermined threshold voltages thereof are applied thereto. The sum of threshold voltages of the plurality of semiconductor devices is higher than the source voltage. The semiconductor devices are forward-connected in series between the first terminal and the second terminal, wherein connection points among the plurality of electronic circuit blocks connected in series are connected to selected connection points among the plurality of semiconductor devices connected in series so that at least one of the semiconductor devices is connected in parallel in respective one of the plurality of electronic circuit blocks.

1. Field of the Invention
The present invention relates to a reduction in the values of currents flowing through an electronic circuit device such as a semiconductor integrated circuit and a reduction in power consumption.
2. Description of the Related Art
With the development of portable apparatuses, it has been recently desired that semiconductor integrated circuits such as an LSI, etc. provide less power consumption for longer battery life. As effective means for realizing the less power consumption, the operating voltage may be lowered. It has been said in general that since power consumption is given by the product of the voltage and current, both the voltage and current can be reduced by lowering the operating voltage, whereby a synergistic effect results in a reduction in power consumption.
When the current value is reduced, power wiring is rendered easy and manufacturing costs are also reduced. It is however general that a source voltage used for the entire system using a semiconductor integrated circuit is constant and the source voltage used for the entire system is supplied to the semiconductor integrated circuit.
FIG. 5 is a circuit diagram showing a conventional configuration wherein two types of electronic circuit blocks are activated by a source voltage of 3.3 volts. In the drawing, reference numeral 1 indicates a power terminal, reference numeral 2 indicates a ground (GND) terminal, and reference numerals 3 and 4 indicate electronic circuit blocks such as semiconductor integrated circuits or the like electrically connected in parallel between the power terminal 1 and the ground terminal 2. Since loads on the electronic circuit blocks 3 and 4 vary in time sequence when the two electronic circuit blocks 3 and 4 are activated, the two electronic circuit blocks 3 and 4 cannot be put in use by simply series-connecting them between the source voltage and the ground. Therefore, it is known in general that the two electronic circuit blocks 3 and 4 are used by connecting them in parallel between the source voltage and the ground as shown in FIG. 5.
Assuming that the values of currents that flow through the electronic circuit blocks 3 and 4, are defined as I.sub.1 and I.sub.2 respectively as shown in FIG. 5, power W.sub.1 to be used by the entire electronic circuit blocks 3 and 4 is expressed in the following equation: EQU W.sub.1 =3.3.times.(I.sub.1 +I.sub.2) (1)
Thus, when the voltage applied to the system is constant, the achievement of the reduction in power consumption needs to reduce (I.sub.1 +I.sub.2).
The currents flowing through the respective electronic circuit blocks 3 and 4 can be reduced by providing voltage converters to activate the electronic circuit blocks 3 and 4 at low voltages and lowering voltages applied across the electronic circuit blocks 3 and 4. In such a case, however, power to be used by the voltage converters themselves is added together and each voltage converter needs a large area. It is therefore so difficult to incorporate them into a small chip such as a semiconductor integrated circuit.
Since the conventional electronic circuit device is constructed as described above, a problem arises in that it encounters difficulties in realizing the reduction in power consumption while holding its size and cost reductions.


A molding die set includes a first molding die which comprises cavities and a parting surface; a second molding die which comprises cavities and a parting surface arranged to face the first molding die; and an O-ring supported on the first molding die to surround the cavities and to have a peripheral line which does not extend outwardly from the parting surface.

This application claims the priority of Application No. H11-315311, filed Nov. 5, 1999 in Japan, the subject matter of which is incorporated herein by reference.
The present invention relates to a molding die set used for fabricating a semiconductor apparatus, and to a method for fabricating a semiconductor apparatus using such a molding die set.
According to a conventional technology, surface voids and/or inner voids may be made in a semiconductor package when a semiconductor apparatus, such as IC and LSI, is resin-molded using a thermosetting resin. Thus molded package is treated as defective. In order to prevent voids in a semiconductor package, a mold chase unit is designed to be able to reduce the pressure therein.
Accordingly, an object of the present invention is to provide a molding die set whereby a molding process can be carried out at a desirable pressure-reduced condition in cavities.
Another object of the present invention is to provide a semiconductor device package which is fabricated to reduce voids generated in a molded package.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
(1) First Aspect of the Present Invention
According to a first aspect of the present invention, a molding die set includes a first molding die which comprises cavities and a parting surface; a second molding die which comprises cavities and a parting surface arranged to face the first molding die; and an O-ring supported on the first molding die to surround the cavities and to have a peripheral line which does not extend outwardly from the parting surface.
In the first aspect of the present invention, the second molding die may have a projection which extends outwardly from the parting surface so that the projection is in contact with the O-ring when the first and second molding dies are clamped to each other. In one case, the first molding die may have a groove in which the O-ring is completely contained, and the projection of the second molding die may have an end which goes into the groove to be in contact with the O-ring when the first and second molding dies are clamped to each other. In another case, the first molding die may have a groove in which the O-ring is supported, the O-ring partially being exposed from the groove toward the second molding die, and the projection may have an end which is wider than the groove so that an outer surface of the projection is in contact with the exposed portion of the O-ring when the first and second molding dies are clamped to each other. In still another case, the first molding die may have a side with a groove in which the O-ring is supported, and the projection may have an inner side which is in contact with the O-ring when the first and second molding dies are clamped to each other.
(2) Second Aspect of the Present Invention
According to a second aspect of the present invention, a molding die set includes a molding die which comprises cavities, ejector holes each of which extends to the corresponding cavity; ejector pins each of which is movably arranged inside the corresponding ejector hole; and sealing members each of which air-seals the corresponding ejector hole.
In the second aspect of the present invention, the sealing members may be O-rings each of which is arranged to surround the corresponding ejector pin. In one case, the molding die set may further include a cavity block comprising the cavities; and a cavity holder supporting the cavity block. Each of the ejector holes is formed through the cavity block and cavity holder to have a wider diameter portion in which the O-ring is set. Each of the ejector pins may have a flange which is in contact with the corresponding O-ring to improve air sealing function.
(3) Third Aspect of the Present Invention
According to a third aspect of the present invention, a molding die set includes a molding die which comprises cavities, pressure reducing paths formed around the cavities; and a plurality of pressure reducing ports connected to the pressure reducing paths, each of the pressure reducing ports being arranged so as to minimize the distance from the farthest cavity.
In the third aspect of the present invention, the cavities may be arranged on two parallel lines in each of the first and second molding dies, the pressure reducing paths are arranged at the both sides of the lines of cavities, and the pressure reducing ports are arranged at least at the center of each of the pressure reducing paths.
A semiconductor device package according to the present invention is fabricated using one of the above described molding die sets of the first to third aspects of the present invention.


A context-sensitive pre-evaluation analysis of a set of rules is performed based on the circumstance or the current state of a rule clause directed to an infrequently changing condition. A group of multiple-clause rules are identified which each have a clause defining an infrequently changing condition for evaluating a state of a resource. The current state of the resource is monitored. If the identified group of multiple-clause rules, which cannot evaluate as TRUE under the context of the current state the resource, the identified group of multiple-clause rules are excluded from consideration by the rules engine. The rules engine will then encounter fewer rules to evaluate for a solution. The identified group of multiple-clause rules is further analyzed in the context of the infrequently changing condition for the current resource state. State metrics that are defined by clauses of the identified multiple-clause rules, those that cannot evaluate as TRUE, are identified. Those metrics are then also excluded from consideration by the rules engine. Thus, the rules engine will encounter fewer rules and/or event states that cannot be evaluated to a solution. The context-sensitive pre-evaluation analysis of the rules is performed out-of-band as the rules engine traverses the rule.

The present invention relates to the analysis of rules for application to state event information. More particularly, the present invention relates to context sensitive analysis of rules for evaluating the state of a managed resource.
Within the past two decades the development of raw computing power coupled with the proliferation of computer devices has grown at exponential rates. This growth along with the advent of the Internet have led to a new age of accessibility—to other people, other systems, and to information. This boom has also led to some complexity in the systems. The simultaneous explosion of information and integration of technology into everyday life has brought on new demands for how people manage and maintain computer systems.
Additionally, the complexity of these systems and the way they work together has and will create a shortage of skilled IT workers to manage all of the systems. The problem is expected to increase exponentially, just as the dependence on technology has. As access to information becomes omnipresent through PC's, hand-held and wireless devices, the stability of current infrastructure, systems, and data is at an increasingly greater risk to suffer outages and general disrepair.
One new model of computing, termed "autonomic computing," shifts the fundamental definition of the technology age from one of computing, to that defined by data. The term "autonomic" comes from an analogy to the autonomic central nervous system in the human body, which adjusts too many situations automatically without any external help. Similarly, the way to handle the problem of managing a complex IT infrastructure is to create computer systems and software that can respond to changes in the IT (and ultimately, the business) environment, so the systems can adapt, heal, and protect themselves. In an autonomic environment, components work together, communicating with each other and with high-level management tools. They can manage or control themselves and each other.
Self healing technologies are one of the pillars of autonomic computing and on demand. Self-healing requires detecting problematic operations (either proactively through predictions or otherwise) and then initiating corrective action without disrupting system applications. The first step toward this direction is problem determination. In an autonomic computing environment, problem determination uses an intelligent control loop to collect system information, analyze it by applying problem determination rules, plan appropriate responses, and then make necessary adjustments to resolve problems. Self-healing systems are typically rule driven—rules define what the system should do to diagnose and correct a problem. However, a conventional problem determination system can have hundreds or thousands of rules, and must evaluate many of these rules frequently.

International Business Machines Corporation


A new and distinct cultivar of Impatiens plant named ‘Duessphotpk’ characterized by its upright, outwardly spreading and mounding plant habit; vigorous growth habit; freely branching habit; dark green-colored leaves; early and freely flowering habit; hot pink-colored flowers; and good garden performance.

The present invention relates to a new and distinct cultivar of New Guinea Impatiens plant, botanically known as Impatiens×hybrida and hereinafter referred to by the name 'Duessphotpk'.
The new Impatiens plant is a product of a planned breeding program conducted by the Inventor in Encinitas, Calif. The objective of the breeding program is to create new uniform Impatiens plants with numerous attractive flowers and good garden performance.
The new Impatiens plant is a naturally-occurring whole plant mutation of a proprietary selection of Impatiens×hybrida identified as code number NN-1166-X0000, not patented. The new Impatiens plant was discovered and selected by the Inventor as a single flowering plant from within a population of plants of the parent selection in a controlled greenhouse environment in Encinitas, Calif. on Dec. 8, 2014.
Asexual reproduction of the new Impatiens plant by terminal vegetative cuttings in a controlled greenhouse environment in Encinitas, Calif. since Jan. 9, 2015 has shown that the unique features of this new Impatiens plant are stable and reproduced true to type in successive generations.


A method for obtaining an approval of an electronic fund transfer (EFT) disbursement file from a user of a remote system and transferring the EFT disbursement file to a payments processor. The method comprises generating a digest, by performing a hash of the EFT disbursement file, and transferring the digest to the remote system along with authorization control code. The authorization control code drives the remote system to obtain a digital signature of authenticated attributes, which includes the digest, and generate an authorization response. The method further comprises receiving the authorization response from the remote system and transferring an electronic funds submission to the payments processor. The electronic funds submission comprises the payment transaction file and at least a portion of the authorization response comprising the digital signature.

A typical business utilizes an accounting software system (or an accounting module to its enterprise resource planning system or other database systems) that maintains a database of the business' transactions with its customer, vendors, employees, banks, and other third parties associated with the business. Such accounting systems are typically architected as a transaction database wherein data is input into the system through predefined transactions and extracted from the system utilizing database reporting modules.
In the early accounting systems, payments to third party payees were effectuated entirely outside of the accounting software system. An appropriately authorized operator would utilize a reporting module to obtain a listing of payments to be made to various payees. The operator would then issue a payment draft or check to each payee either by manually filling in payment information in a pre-printed draft form or by entering the payment into a secure check printing software system which, in turn, prints each draft on either a pre-printed form or on blank check stock. After the drafts are printed, the operator will enter one or more payment transactions into the accounting system to indicate that the payments have been issued.
With advanced payment management solutions, the accounting system may output a payments file which includes a plurality of records, each reflecting a payment to be issued. An appropriately authorized operator would import the payments file to the payments management solution. A check printing module of the payments management solution prints a draft corresponding to each record within the payments file on either a pre-printed form or on blank check stock. After the drafts are printed, the operator will typically enter only a single acknowledgement transaction into the accounting system to indicate that all payments within the payments file have been issued.
More advanced solutions may support electronic fund transfer payments. More specifically, the payments management solution may receive a payments file from the accounting system and generate a plurality of electronic fund transfer transactions for execution by an applicable financial institution.
When an electronic fund transfer transaction file is transferred to a financial institution, there is a well recognized need for the financial institution to be assured that the transaction file is accurate and appropriately authorized. One known solution utilized for assuring that a transaction file is accurate and appropriately authorized is a system utilized by the Bankers Automated Clearing System (BACS) and referred to as BACSTEL IP. In the BACSTEL IP system, a member financial institution (or some other trusted certificate authority) issues a digital certificate—which binds a public key of an asymmetric key pair to a user who is known to have the authority to authorize electronic fund transaction payments (e.g. an authorized user). The digital certificate and the private key of the key pair is securely stored on a smart card or other hardware key that is issued to the authorized user.
The authorized user runs a BACSTEL IP digital signature software component on his or her computer along with a program for interfacing with the financial institutions BACSTEL IP systems and an interface to a smart card reader.
The digital signature software component receives a data file from a higher level system and performs the following processes. First, the component performs a first SHA-1 hash of the data file to generate a 160-bit string commonly known as a digest. An SHA-1 hash is a well known secure hash algorithm developed by the National Institute of Standards and Technology which is useful for generating a 160-bit hash of any data file with a size up to 264 bits in length. The component then combines the digest with other message attributes such as the current date and attribute type. The combination is referred to as the authenticated attributes. The authenticated attributes are then SHA-1 hashed to generate a second 160-bit hash string. The second 160-bit string is passed to the user's smart card. The smart card returns a digital signature of the 160-bit string along with the user's digital certificate and certificate chain. The component then generates a data structure known as a PKCS#7 which includes the digest, the digital signature, and the authorized user's digital certificate and certificate chain. The PKCS#7 and the electronic fund transfer transaction file are then passed to the BACSTEL IP systems.
The smart card, in conjunction with its PC resident driver code, comprises executable code which receives data for digital signature, prompts the authorized user to input a secret PIN number for authentication, and, in response to receiving the correct PIN number, returns a digital signature of the file along with the user's certificate and certificate chain.
When an authorized user is ready to submit an electronic fund transfer file to the BACSTEL system, the following process is used to assure that the transaction file is accurate and appropriately authorized.
First, the user's system presents the electronic fund transfer transaction file to the digital signature software component. As discussed above, the component will return a PKCS#7 data structure which includes a digest of the transaction file, a digital signature of the authenticated attributes, and the user's digital certificate and certificate chain.
The user's system then establishes a secure socket layer (SSL) connection to the financial institution's BACSTEL system. After the SSL connection is established, the BACSTEL system provides an authentication challenge to the user's system. The authentication challenge includes a randomly generated message.
Upon receipt of the authentication challenge, the user's system presents the random message to the digital signature software component which returns a digital signature and the user' digital certificate and certificate chain. These are passed back to the BACSTEL system.
After receiving an indication that the BACSTEL system has authenticated the user (the digital signature is that of the authorized user identified in the digital certificate), the user's system presents the PKCS#7 data structure and the transaction file to the BACSTEL system.
The financial institution can verify the integrity of the transaction file by verifying the signature (e.g. calculating a hash of the authenticated attributes for comparison to the result of decrypting the digital signature). If the digital signature is valid, the bank is assured that the transaction file presented to the BACSTEL system is the same transaction file presented to the digital signature software component.
There exists a desire in the industry to manage payments utilizing a payments solution located on a centralized server that is accessible by remote thin client devices over open networks such as the Internet. This client server architecture retains all data on the centralized server resulting in the payment data being more secure and more easily audited. Further, the entire payment solution being located on a centralized server is more easily maintained than multiple remote systems.
The problem with the above described digital signature solution is that it requires that the entire transaction file be located on the user's system so that it can be presented to the digital signature software component. This creates at least one problem.
If the transaction file is originally generated on a centralized server, the entire transaction file must be transferred to the remote client for digital signature. If the file is large, transferring the file can require significant network bandwidth and/or significant down load time if the user's connection is at a low data rate—such as dial-up. Further, transferring the transaction file to the remote client opens additional opportunities for a security breach as the transaction file may be inadvertently (or intentionally) stored in an insecure location on the remote client. Further yet, transferring the transaction file to the remote client creates audit issues as it would be possible to alter the transaction file on the user's system prior to digital signature and presentation to the BACSTEL system.
What is needed is a payments management system that includes a server and thin client architecture and enables a remote approver to authorize a payments file in a manner that does not suffer the disadvantages of transferring a transaction file to a user's remote system.

Method for remotely authorizing a payment transaction file over an open network


A semiconductor integrated circuit which includes an optical device for performing optical communication and which exhibits a predetermined function. This semiconductor integrated circuit includes a first electricity supply portion, which is connected to the optical device, and a second electricity supply portion, which differs from the first electricity supply portion and is connected to the optical device.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and to a semiconductor integrated circuit arrangement device and process, and more particularly relates to a semiconductor integrated circuit which includes an optical device for optical communication and is structured so as to exhibit a predetermined function, and to a semiconductor integrated circuit arrangement device and process for arranging this semiconductor integrated circuit at a predetermined position.
2. Description of the Related Art
Heretofore, semiconductor integrated circuits which include optical devices and are structured so as to exhibit predetermined functions have been proposed. When such a semiconductor integrated circuit is being arranged at a printed circuit board, it is not judged whether or not the optical device(s) function(s) properly. Consequently, it has been possible for semiconductor integrated circuits equipped with unsatisfactory optical devices to be arranged at printed circuit boards.
Furthermore, conventionally, semiconductor integrated circuits have been arranged at printed circuit boards as described below (see Japanese Patent Application Laid-Open (JP-A) No. 11-273816). Specifically, optical devices dedicated to positioning are provided beforehand at each of a semiconductor integrated circuit and a printed circuit board. When the semiconductor integrated circuit is being arranged at the printed circuit board, the semiconductor integrated circuit is positioned at the printed circuit board at a position at which conditions of light emission and light reception, by the optical devices for positioning which have been provided at the semiconductor integrated circuit and the printed circuit board, are optimal.
However, even if a semiconductor integrated circuit is positioned at a printed circuit board using optical devices for positioning in this manner and the optical devices for positioning are disposed at accurate positions, there may be fabrication errors and the like unrelated to the optical devices for positioning, which may cause a mounted optical device to be disposed at a position which is offset from an original position.

Semiconductor integrated circuit and semiconductor integrated circuit arrangement device and process