A debris collection apparatus for a maritime vessel includes a shroud and a plurality of support structures. Each of the plurality support structures include a boot defining a cavity and configured to be secured to the vessel, a foot sized to fit within the cavity and including a frame having a rotatably mounted first universal swivel, a staff cap including a staff cap terminal having a rotatably mounted second universal swivel rotatably, a stabilizer base configured to be secured to the vessel and including a body having a rotatably mounted third universal swivel, an elevational staff section removably connected to the first universal swivel and staff cap terminal, and a horizontal staff section removably connected to the second and third universal swivels. The foot is inserted into the boot to secure the support structures in a rigid position, and the shroud is connected to both staff caps and the vessel.

A variety of temporary structures have been utilized for years in an attempt to prevent debris and material from entering waterways and/or damaging adjacent marine structures during the demolition of maritime vessels. Exemplary temporary structures that have been utilized in the past include nets, cloth, wooden structures, and metal shields, which have all been variously employed on a case-by-case basis to prevent debris and materials from falling into adjacent water.
However, these structures are generally single use, "stick built" (e.g., they are a one time construction built to fit a specific structure that is being protected), difficult to erect and disassemble, utilize materials that cannot be safely reutilized once installed, and require an extensive amount of manpower and unrecoverable capital investment to create.
Despite the above-identified issues, there has been a lack of advancement in this field. This may be at least partially attributed to the wide variety of marine structures that are contemplated for protection. For example, buildings, bridges, ships, piers, wharfs, and quays, are all marine structures that are contemplated for protection, but each requires a different type of structural protection in order to provide acceptable results. While there are thousands of these marine structures in the world, there is little to no specialization in companies dedicated to the specific application of demolishing maritime vessels and a corresponding lack of effort to standardize protection structures to be used during the demolition of the maritime vessels, which amounts to a small but vital component of that work.
Due to the lack of uniformity between structures and a broad approach to completing a demolition project, with or without sensitivity to the underlying regulatory requirements, the known systems do not offer the flexibility and protection that is desired and/or required by both regulations and prudence on the part of the operator.
What is needed in the art is a debris collection apparatus for maritime vessels for securing and containing debris and falling material during demolition and other activities and that includes continuously stable support mechanisms, is movable and adjustable to protect different structures, can be quickly and easily erected and dismantled, and can be reused on the same vessel or other vessels. These and other needs are addressed by the adjustable debris collection apparatus of the present disclosure.

Adjustable debris collection apparatus for maritime vessels and associated methods


A stereotactic radiosurgery including a collimator adapted movably to an irradiation head, a driving apparatus for changing a position of the collimator while keeping a position relation in which a center line of a hole of the collimator coincides with a line connecting an apex of a radiation cone and a center portion of the focus, and a control apparatus for detecting a position error between an irradiating direction of the radiation and the center portion of the focus, driving the collimator driving apparatus and moving the collimator to a position at which the detected position error is offset.

This invention relates to a stereotactic radiosurgery for effecting medical treatment by concentrating stereotactically a narrow beam of a radiation on one point. More particularly, the present invention relates to a stereotactic radiosurgery which will be suitable for correctly concentrating a radiation on one stereotactic point for a defect of mechanical accuracy of a gantry for irradiating a radiation and for any focuses.
An irradiation method of a radiation referred to as a "stereotactic method" has drawn an increasing attention. It is a method of medical treatment which imparts a high dose of a radiation to only a focus from multiple directions and destroys the focus. According to this method, the dose of the radiation to normal tissues around the destroyed focus is extremely small, and any adverse effects on the normal tissues can be eliminated.
Stereotactic radiosurgeries include a multi-beam source system radiosurgery referred to as a "Gamma Unit" and a mono-beam source system radiosurgery (PCT Japan Publication No. Hei-2-503521 (W089/05171) entitled "Stereotactic Radiosurgery System SRS 200 Isocentric Subsystem", PHILLIPS).
The former comprises a hemispherical collimator having a large number of irradiation holes and a cobalt 60 sealed beam source situated outside this collimator, and can accomplish medical treatment by applying concentratedly a gamma dose from a large number of cobalt 60 beam sources situated hemispherically to a focus. The latter rotates a gantry with the focus of a patient as a center by the use of an electron beam accelerator, etc, and can concentratedly irradiate the radiation to the focus from all directions while rotating a treatment couch. Accordingly, both can apply a large dose as an accumulated dose to the focus, and can reduce the dose to the normal tissue by a dispersion effect of the dose.
However, the former uses a large number (about 200) of cobalt 60 as the beam source. Since cobalt 60 has half life, exchange becomes necessary, and problems of maintenance and management occur. Furthermore, since the cost of the apparatus is high, this system has not yet been wide spread. The Gamma Unit of this system is exclusively for the head, and is not suitable for the chest and the abdomen at which the focus moves with the respiration. Accordingly, stereotactic surgery using the electron beam accelerator according to the latter has been expected. Stereotactic radiosurgical treatment using the electron beam accelerator will be explained generally with reference to FIGS. 1 and 2. A gantry 102 of an electron beam accelerator rotates with a horizontal axis 123 being the center, and a beam passes through an irradiation head 113 mounted to the radiation gantry 102, and is narrowed and irradiated to a focus. A point of intersection 120 between the horizontal axis 123 and the beam center 121 irradiated by a collimator is an isocenter, and the focus of a patient is brought into conformity with this position. The beam center must always catch the point of intersection 120 even while the gantry 102 is rotating with the horizontal axis 123 being the center. The radiation can be irradiated to the focus from all directions by operating in a composite way the rotation of the gantry 102 and the rotation of a treatment couch 112 inside a horizontal plane.
The gantry and the irradiation head mounted to the gantry are very heavy. Therefore, if any shake or deflection occurs during the rotation of the gantry as indicated by dotted line in FIGS. 1 and 2, the beam center cannot catch the focus and the focus of the radiation beam does not pass through the isocenter as represented by reference numerals 120a and 120b. When the medical treatment is carried out under such a state, the ratio of the dose to the focus and the dose to the normal tissue becomes small, so that the destroying effect of the focus becomes also small and even the normal tissue might be destroyed. Moreover, followup performance of the irradiation head, which is a heavy device, with the chest and the abdomen moving with the respiration is low, and the system must be increased in scale to accomplish this operation.

Radiosurgery effecting position correction of collimator


A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates and, more particularly relates to monitor structures on the substrates.
2. Description of the Related Art
The manufacture of large scale integrated circuits in a mass production facility involves hundreds of discrete processing steps beginning with the introduction of blank semiconductor wafers at one end and recovering the completed chips at the other. The manufacturing process is usually viewed as consisting of the segment wherein the semiconductor devices are formed within the silicon surface (front-end-of-line) and the portion which includes the formation of the various layers of interconnection metallurgy above the silicon surface (back-end-of-line). Most of these processing steps involve depositing layers of material, patterning them by photolithographic techniques, and etching away the unwanted portions. The materials consist primarily of insulators and metal alloys. In some instances the patterned layers serve as temporary protective masks. In others they are the functional components of the integrated circuit chip.
While most development has been directed towards the manufacture of semiconductor based electronic circuits, there has recently been considerable interest in integrating electro-mechanical devices such as electric motors, springs cantilevered devices, and mechanical switches and oscillators within these electronic circuits. The repertoire of material along with a variety of available deposition and selective etching methods which have been developed in the integrated circuit industry along with a refined patterning technology have made possible the manufacture of tiny mechanical devices with movable elements. A movable element, for example the rotor of an electric motor, is patterned of material deposited onto a sacrificial layer, within a stator element. The sacrificial layer is then removed by selective isotropic etching which undercuts the rotor, freeing it from the substrate. Cantilevered devices such as mechanical switches, tuning forks or other oscillators, and leaf springs are similarly formed partially over a sacrificial layer, with an anchored portion connected to a subjacent structure.
In order to monitor the integrated circuit manufacturing process, test structures, representative of the circuit elements are typically incorporated in regions of the wafer outside the integrated circuit chips. Examples of these inline test devices include a dumb-bell structure testable with a four point probe to establish proper resistance of a deposited layer, or long serpentine metal lines which can be tested to establish the presence of particulate defects by testing for electrical opens and shorts. These devices are often designed much larger than their corresponding elements in the integrated circuit so they can be tested at various stages during processing.
Typically, these test devices are formed in the saw kerf which separates the circuit chips. In some instances, the test devices are formed in a designated chip site, referred to as a test site. However, this is usually avoided because it utilizes valuable product chip real estate.
In a product, which has micro electro-mechanical systems (MEMS), it is also desirable to have representative test structures to perform timely in-line testing of these devices as well. A problem with forming electro-mechanical test structures in the wafer kerf, or even in test sites, is that considerable particulate debris can be generated by the fracturing of free standing or lightly attached elements of these test structures. The expression "lightly attached" is used herein to indicate a structural element, for example, a long cantilever with a relatively small region of attachment to the substrate, thereby rendering it easily broken off. It is therefore desirable to have test structures for electro-mechanical devices which are designed to provide useful in-line testing but not having free standing or even lightly attached elements like their circuit counterparts.
FIG. 1 is a schematic cross sectional view showing a prior art MEMS device. The MEMS device comprises a central bearing 124a, a rotor 120b and a stator 120a in the semiconductor structure area 115 of the substrate 110. It also comprises a monitor pattern 124b in the semiconductor monitor structure area 118. The polysilicon plate 16 serves as an electric shield. Before forming the pattern in FIG. 1, a relieving process is used to remove sacrificial layers (not shown) in the semiconductor structure and the semiconductor monitor structure. The relieving process usually is a wet etch process and may lift off the semiconductor monitor structure 124b if the semiconductor monitor structure 124b is not well anchored to the substrate 110. The lift-off of the semiconductor monitor structure 124b results in a particle issue that reduces the yield of the MEMS devices. In order to resolve the particle issue, the semiconductor monitor structure 124b should be well anchored to the substrate 110 by increasing the contact area between the semiconductor monitor structure 124b and the substrate 110. But when the semiconductor monitor structure 124b becomes complicated, the design of maintaining the contact area between the monitor structure 124b and the substrate 110 also becomes complicated. Such a design has increased inconvenience for fabricating the MEMS devices.
Further, process monitors in the saw kerf of the wafer, with non-anchored or lightly attached mechanical elements, would release significant (or more than normal) debris during wafer dicing. U.S. Pat. No. 5,668,062 shows that when integrated circuit chips contain mechanical devices, in this instance mechanical mirrors, that the chips cannot be protectively coated during wafer dicing. Steps must be taken to eliminate metal fragments in the saw debris and which would otherwise lodge under the movable mirrors. The solution taught by the reference involves defining scribe line extensions of the array scribe lines to the edge of the wafer, whereby the scribe line extensions as well as the array scribe lines are free of the metal which is used to form the mirrors. While the procedure is very narrow in scope, the reference nevertheless shows that a specific type of debris (aluminum flakes during the dicing operation) compromises the proper function of MEMS devices.
U.S. Pat. No. 6,337,027 B1 teaches the formation of MEMS devices which are formed from in an epitaxial layer on a sacrificial silicon substrate. The devices, still on the substrate, are then bonded onto pedestals on a glass substrate. The sacrificial silicon substrate is then removed by spray etching, leaving the individual devices mounted on the supporting pedestals. The reference includes several methods of encapsulation of the complete MEMS devices before the substrate is diced using laser scribing.
U.S. Pat. No. 6,150,186 teaches the coating of a metal wire spring bonded to a silicon substrate to form a more resilient spring. The coating method improves the mechanical properties of the spring. The coating method may also be used to improve the resiliency of other spring devices such as a cantilevered spring.
U.S. Pat. No. 5,660,680 cites procedures for forming various useful micro structures such as tubes and beams as well as micro sensing and actuating devices by the use of patterned sacrificial molds in which the devices are formed and thereafter released by etching away the mold.

Taiwan Semiconductor Manufacturing Co., Ltd.


A system and method of reporting a status of another system through an electronic price label (EPL). The system includes the EPL and a computer coupled to the EPL which monitors the status of the second system and causes the EPL to display a status message indicating the status of the second system. The second system may include a POS system, credit authorization system, or any other in-store system.

The present invention relates to system monitoring and status reporting systems, and more specifically to a system and method of reporting a status of another system through an electronic price label (EPL) system.
Retail establishments typically include a plurality of separate computer systems or networks. Each of these systems has a central back-office server. For example, the point-of-sale (POS) system provides item price and other information to checkout terminals after items are scanned at the checkout terminals.
Another system is the credit authorization system which allows a POS system to clear credit card and check purchases.
Another system is the EPL system. EPL systems typically include a plurality of EPLs for each merchandise item in a retail establishment. EPLs typically display the price of corresponding merchandise items on retail establishment shelves and are typically attached to a rail along the leading edge of the shelves. A retail establishment may contain thousands of EPLs to display the prices of the merchandise items. The EPLs are coupled to a central server from where information about the EPLs is typically maintained in an EPL data file. Price information displayed by the EPLs is obtained from the PLU file.
Retail establishment personnel must monitor the condition of these individual networks in the back office where the computers reside. Thus, when personnel are working in the merchandise and produce aisles, they do not notice system errors when they occur.
Therefore, it would be desirable to provide a method of reporting the status of the one or more systems, including the EPL system, at many locations throughout a retail establishment. It would further be desirable to use the EPLs to display system status messages for these systems.

System and method of reporting a status of another system through an electronic price label system


A nonaqueous electrolyte rechargeable battery includes a positive electrode, a negative electrode, and a nonaqueous electrolyte. The positive electrode and the negative electrode occlude and discharge lithium irons. The nonaqueous electrolyte contains an additive and a polycyclic aromatic hydrocarbon. The additive includes an organic solvent having a donor number of 18 to 24. A content of the polycyclic aromatic hydrocarbon is 0% to 2.0% of a total mass of the nonaqueous electrolyte.

With rapid market expansion of portable electronic devices, such as a laptop computer and a cell phone, demands of small-sized high capacity rechargeable batteries with a high energy density and excellent charging and discharging cycle characteristics have been increased for use in threes electric devices. In order to meet such demands, nonaqueous electrolyte rechargeable batteries have been developed. A nonaqueous electrolyte rechargeable battery uses alkali metal ions, such as lithium ions, as a charge carrier, and causes an electrochemical reaction in accordance with reception of charged particles of the charge carrier.
With regard to a nonaqueous electrolyte rechargeable battery used for vehicles, such as electric vehicles, higher durability performance has been required to meet with the expected lifetime of the vehicles. In a nonaqueous electrolyte rechargeable battery, if an irreversible reaction, such as incorporation of lithium into a coating when the coating is formed, advances in addition to a regular battery reaction occurring during charging and discharging, the amount of lithium that can contribute to the battery reaction decreases. The decrease in the amount of lithium results in deterioration of a charging and discharging capacity.
For example, JP2010-102841A describes a nonaqueous electrolyte lithium-ion secondary battery with improved durability. JP2010-102841A aims to minimize the decrease in energy density due to irreversible capacity in initial charging and discharging by using a high-capacity positive electrode. As a positive electrode active material that is consumed by the initial irreversible capacity specific to a negative electrode active material including at least one selected from silicon (Si), silicon oxide (Si) and carbon (C), a higher capacity lithium-containing composite nitride represented by a formula Li3-XMXN (M is one or more transition metals selected from cobalt (Co), nickel (Ni), and copper (Cu), and x is equal to or greater than zero and equal to or less than 0.8) is used. Therefore, the weight of the positive electrode active material that is not used for charging and discharging after the initial discharge is reduced, and hence the energy density of the nonaqueous electrolyte lithium-ion secondary battery increases.
That is, in the secondary battery of JP2010-102841A, the total amount of lithium in the cell is increased by using the high capacity positive electrode. Therefore, even if the lithium is deactivated by the irreversible reaction, the absolute amount of the lithium in the battery is secured, and hence the high capacity is achieved.
In the secondary battery where the source of lithium is merely added in the positive electrode, as JP2010-102841A, the capacity seems to be increased. However, it is difficult to restrict the advance of the irreversible reaction, which is a substantial cause of the capacity deterioration. Although the durability improves for the amount of lithium added, the capacity eventually reduces. Accordingly, the effect is not highly expected in use for a long time.

Nonaqueous electrolyte rechargeable battery


A vehicle may receive sensor data captured by a sensor, determine that the sensor data represents an object in the environment, and determine a collision probability associated with a predicted collision between the vehicle and the object. Based at least in part on the collision probability, a position of a headrest of the vehicle may be determined relative to a head of an occupant of the vehicle. The headrest may be adjusted in one or more directions prior to occurrence of the predicted collision to minimize injury to the occupant due to the collision.

Safety is an important consideration in the design and construction of vehicles. In some instances, vehicles may have systems that help detect potential collisions to alert a driver or, in the case of an autonomous vehicle, attempt to perform actions to avoid the collision or lessen the severity of the collision. Many vehicles also have safety systems, such as airbags and seatbelts designed to prevent or minimize injury to occupants during a collision. However, existing safety systems may not provide adequate protection for certain types of collisions such as collisions in which occupants are rear facing (e.g., facing a direction opposite the direction of collision).

Adjusting headrest based on predicted collision


Captured element shoulder joint implant may be configured with a captured humeral ball; in a reverse shoulder configuration; to have a barrel- or disc-like humeral head to recessed glenoid articulation; and so forth. Multi-point fixation glenoid component may be provided. A humeral implant may have a universal joint connection, which can be mounted to or in a humeral bone and provide for a center of movement generally within a volume defined by an upper head of a normal humerus.

Various shoulder joint implant art is known. Such an implant can be an ensemble for total or perhaps partial joint replacement of the main joint of the shoulder, the glenohumeral joint, the configuration of which, conventionally, attempts to mimic the configuration of the natural glenohumeral joint, generally having an implanted artificial humeral component with a ball-like head, say, of metal or ceramic, which articulates in and against a generally shallow open cup, say, of polyethylene or metal, of an implanted artificial glenoid component in a total arthroplasty or perhaps against the natural glenoid cup in a hemiarthroplasty. As good as such art can be, it is not without its drawbacks. Among these are that natural range of motion is difficult if not well nigh impossible to achieve, and the shoulder, being an enarthrodial joint and the joint of the body with the greatest range of motion by way of having its head held in place to a great extent by means of muscle, fibrous capsule and ligamentous tendon structures in a shallow cup, the "glenoid," can be prone to dislocation, even after joint replacement surgery with a device of such art. The most frequent cause of unsuccessful shoulder joint replacement is failure of fixation through loosening of known glenoid components, not infrequently caused by compromise of mounting of a metal shell holding the cup, or compromise of a cemented plastic cup, to a surgically prepared portion on the quite thin and fragile scapular bone (glenoid area). This deficit of glenoid area supporting bone may need to be addressed.
Reverse shoulder implants are also known. In such implants, a ball head is provided as part of the glenoid component, with a corresponding cup as part of the humeral component. Such art, too, is not without its drawbacks, among which may include dislocation and/or glenoid component loosening as with the more anatomically conventional shoulder joint implants discussed in general above.
It would be desirable to improve upon the art. It would be desirable, in particular, to provide a shoulder joint implant that ameliorates if not solves in general one or more of the problems in the art, notably dislocation, loosening and/or supporting bone deficit of the glenoid area, and motion range. It is desirable to provide alternative(s).


Boosting operation of a charge pump is performed at a fixed period irrespective of the state of a load. A regulator for controlling a charge pump includes: a frequency dividing circuit generating a frequency-divided clock having a period that is twice that of a boost clock; a voltage dividing circuit generating a plurality of divided voltages having voltage values that differ from one another; a comparator circuit comparing each of the divided voltages and a reference voltage and outputting a plurality of comparison-result signals; a selection signal generating circuit reading in logic of each of the comparison-result signals in synch with an edge of the frequency-divided clock and outputting selection signals; a duty converting circuit outputting a plurality of clocks having different ON duties; a selector selecting any one of the plurality of clocks or “H”-level logic as a PWM signal based upon the selection signals; and a gate circuit taking the logical AND between the frequency-divided clock and the PWM signal and generating control signals for controlling series-parallel switching.

A portable information device such as a mobile telephone or PDA (Personal Digital Assistant) usually has a display panel for displaying information and a circuit (a driver IC) for driving the display panel, which is formed by a semiconductor integrated circuit (IC). A portable information device uses a comparatively low-voltage battery as an external power supply, but the display panel usually requires a voltage higher than that of the supply voltage of the battery. For this reason, the driver IC generally incorporates a power supply circuit for generating the necessary driving voltage by boosting the supply voltage.
An example of such a power supply circuit is illustrated in Patent Document 1. Specifically, as shown in FIG. 1, a power supply circuit 1 of charge-pump type has a charge pump 10 and a regulator 20. With this arrangement, the pulses of a clock signal CLK1 that causes the charge pump 10 to perform a boosting operation are skipped by the regulator 20 in accordance with the output voltage of the charge pump 10, whereby a voltage (a target voltage) obtained by boosting supply voltage VDD up to a desired voltage value is output from the charge pump 10 as Vout. A detailed description of the structure and operation of the charge pump 10 and regulator 20 are set forth in Patent Document 1 and are omitted here.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-20971A (FIGS. 3, 4)

Step-up power supply circuit and stepping-up method


Optimizing a performance of a software function withing a content distribution network, such as a software-implemented virtual cable modem termination system (CMTS) network, a virtualized Radio Access Network (vRAN), a Passive Optical Network (PON), or a Wi-Fi network. The performance may be optimized by dynamically changing a deployment location within the content distribution network for the software function from an original location to an updated location using an instance management platform. The deployment location may be dynamically changing in response to a variety of trigger conditions or concerns, such as but not limited to a difference in compute resources, responding to latency needs or tolerances, and a desired cohabitation of data or other software.

In some cases, a network architect might decide to implement a function within the network at a different location than that chosen by another network architect. For example, one cable operator may choose to implement a software function solely at a central location in the cable network, while another cable operator might implement that same function at multiple locations throughout the cable network. The choice of where to implement each software function is typically made before installation of hardware resources and that deployment choice typically cannot change during ongoing use of the cable network, at least not without considerable effort and cost.
If the location at which a software function is performed is changed, then that change typically requires a tremendous amount of effort due to new or updated hardware installation, the resulting software installation, and the testing associated with the new hardware and software, to say nothing of the associated financial cost. As a result, the deployment location of software typically does not migrate absent a serious undertaking of upgrading a good-sized portion of the network, typically performed precisely for the sole purpose of redesigning the process flow for that software.
A network designer may base the decision of where to deploy certain software functions in a network based, at least in part, upon the anticipated availability of compute resources at various locations within the network. A compute resource encompasses some amount of hardware resources and software resources bounded for the purposes of executing or performing some number of functions, typically but not necessarily, software functions. For example, a set of compute resources dedicated to a software function may include a certain amount of hardware memory, CPU processing cycles, and a certain amount of access to persistent storage. Another example of a compute resource is a portion of network bandwidth allocated to a software function. Technically speaking, a portion of network bandwidth is not a characteristic of a hardware device upon which a software function executes; nevertheless, network bandwidth is another dimension that may be monitored, controlled, and shared between software functions.
In a cable network, a certain amount of compute resources resides at the headend, while a certain amount of compute resources resides somewhere between the headend and the customer premises equipment (CPE). Compute resources may reside outside the cable headend at a Remote PHY Node (RPN), at a Remote MAC-PHY Node (RMN), or at a switch, for example. Compute resources may exist at different relative locations in terms of proximity to the headend/datacenter and the cable subscriber. FIG. 1 is a block diagram that depicts one example of a Cable Modem Termination System (CMTS) environment as known in the prior art. Compute resources may be available at a plethora of locations accessible via the Internet, at the CCAP Core (located at the cable headend), at each RPN, at each Remote PHY Device (RPD) comprised within an RPN, and at each cable modem (which may, but need not be DOCSIS compliant). A greater amount of compute resources is typically available at the headend/datacenter, but the use of compute resources in the headend typically involves greater latency with respect to the end user using customer premises equipment (CPE) than those compute resources disposed closer in proximity in the network to the end user.

Dynamic adjustment of deployment location of software within a network


A solid-state imaging device is manufactured according to the steps below. A lattice-shaped rib forming member, which is an aggregation of a plurality of frame-shaped ribs for configuring a plurality of solid-state imaging devices, is resin-molded. An aggregate wiring board is used, which has regions corresponding to a plurality of the wiring boards, and in which a plurality of the wiring members are provided in each of the regions, and the imaging element is fastened to each region of the aggregate wiring board and the electrodes of the imaging elements and the wiring members are connected by a thin metal wire. The rib forming member is placed on the wiring board face and joined to the wiring board face, so that the imaging element is disposed inside the lattice elements of the rib forming member. The transparent plate is fastened to an upper face of the rib forming member, and each housing is cut in a direction perpendicular to the base portion, and in a direction dividing into two the width of the rib forming member, and separating the solid-state imaging devices into individual pieces It is possible to make a low cost housing, avoiding deformations caused by a difference in thermal expansion between the wiring board and the ribs made of a resin, when forming a plurality of housings together.

Solid state imaging devices, which are widely used for video cameras and still cameras and the like, are provided in the form of a package, in which an imaging element such as a CCD or the like is mounted on a base made of an insulating material, with the photodetecting region being covered by a transparent plate. In order to make the device more compact, the imaging element is mounted as a bare chip on the base. Referring to FIG. 7, the following is an explanation of the solid-state imaging device disclosed in JP H5-267629A as a conventional example of these types of solid-state imaging devices.
In FIG. 7, numeral 21 denotes a base, on the top face of which is formed a recess portion. An imaging element chip 22 is formed in the center of the recess portion. The base 21 is provided with a lead terminal 24, a lead side pad 25 of which is connected by a bonding wire 26 made of metal to a bonding pad 23 of the imaging element chip 22. A package is formed for the purpose of protecting the imaging element chip 22 by integrally forming a rib 28 on an upper surface of a peripheral portion of the base 21 and fastening a transparent sealing glass plate on top of it.
This type of solid-state imaging device is mounted on a circuit board with the sealing glass plate 27 facing upward, as shown in FIG. 7, and the lead terminals 24 are used to connect it to the electrodes on the circuit board. Although not shown in the drawings, a lens barrel incorporating an imaging optical system whose relative position to the photodetecting region formed in the imaging element chip 22 is adjusted with a predetermined precision is mounted on top of the sealing glass plate 27. During the imaging operation, object light that has passed through the imaging optical system incorporated in the lens barrel is focused on the photodetecting region and photoelectrically converted.
The above-described conventional example of a solid-state imaging device has a housing structure in which the rib 28 is formed on the upper surface of the peripheral portion of the base 21. The casting mold for molding the housing with resin is matched to the housing specification and must be made for each product, leading to an increase in the manufacturing cost.
For that reason, a process using a wiring board which can be manufactured more cheaply, and using a process of molding resin ribs onto the wiring board is conceivable. However, when molding resin ribs onto the wiring board, deformations of the housing such as warping and twisting tend to occur, caused by the difference in thermal expansion between the wiring board containing metal wires and the rib made of a resin. This problem is particularly conspicuous when manufacturing a plurality of housings for solid-state imaging devices all together.
Also, for the purpose of suppressing the scatter of light incident on the internal space of the housing, the ribs sometimes are provided with a taper. The taper direction differs according to the design of the solid-state imaging device. However when the taper direction is provided such that the rib width increases away from the board surface (called a "reverse taper" below), an impediment to rib resin molding develops. That is to say, if the housing structure is formed integrally with the rib 28 on the upper surface of the peripheral portion of the base 21, or if the rib is resin-molded onto the wiring board, mold release after molding of the portion of the forming die which forms the internal space of the housing becomes problematic because of the rib's reverse taper.

Method for manufacturing solid-state imaging devices

Matsushita Electric Industrial Co., Ltd.


The present disclosure relates to a method of modifying a conventional injector (e.g., a high pressure direct fuel injector) and to the modified injector resulting therefrom. The modified injector provides a fluid flow rate and/or fluid spray plume (i.e., pattern) which is different than the fluid flow rate and/or fluid spray plume (i.e., pattern) of the original conventional injector. In one embodiment, provided is a modified injector used in internal combustion engines for fuel delivery directly into the combustion chamber.

Delivering fuel directly into the combustion chamber of a modern internal combustion engine is an important aspect of modern engine design and an important aspect regarding operation of spark-ignited or compression-ignited engines. The advantages of gasoline direct injection ("GDI") versus port gasoline injection ("PFI") are increased fuel efficiency and higher specific power output. Exhaust gas emissions levels can also be more accurately controlled with direct injection systems. Direct fuel injection, or Gasoline Direct Injection, now commonly used in modern multi-cylinder gasoline engines in the transportation industry, can enable up to a 12% fuel consumption improvement versus low pressure port fuel injection systems. North American light-duty vehicle market penetration of direct injected engines sold in new vehicles has grown from approximately 3% in 2008 to approximately 30% in 2013 and beyond in 2015. The global automotive market for gasoline direct injection is projected to grow at a compounded annual growth rate of 18% by 2018.
In a gasoline direct injection system, gasoline is supplied via a low pressure pump, usually operating at 3-6 bar (40 psi to 90 psi), to a high pressure piston pump, usually located on the cylinder head of an internal combustion engine. The high pressure piston pump is usually driven by the camshaft via a tri-lobe or quad-lobe gear and the high pressure piston pump supplies fuel at high pressure, usually from 130 bar to 350 bar (2,000 psi to 5,000 psi), to a fuel distribution rail. The fuel distribution rail is usually mounted to the cylinder head or intake manifold, along the longitudinal access of an engine, in alignment with a bank of cylinders. FIG. 1 is an image of a conventional high pressure gasoline direct injector 100. The direct fuel injector 100 is in fluid supply with the distribution fuel rail at proximal end 101 thereof. The direct fuel injector 100 is provided with fluid seal 102. The direct fuel injector 100 is installed in the engine, usually in the cylinder head, at a specific orientation to the combustion chamber, where the solenoid body 103 of the direct fuel injector 100 and the pintle shaft 104 are housed within the cylinder head injector bore, in order to inject fuel directly into the combustion chamber via the nozzle 105 at the distal end of the direct fuel injector 100. The direct fuel injector 100 is sealed to the combustion chamber via the Fluoropolymer seal 106. A multi-cylinder engine typically uses a plurality of such direct fuel injectors.
FIG. 2 is a close-up image of the nozzle 105 of the high pressure direct fuel injector 100 at the distal end of the injector, which nozzle 105 has a plurality of orifices 201, 202, 203, 204, 205, 206 which each deliver a flow of fuel into the combustion chamber. The quantity, orientation and size of the orifices is specific to each engine application. Electrical signal and power to the direct fuel injector 100 are delivered via the electrical connector 107. FIGS. 1 and 2 are purely illustrative examples of a common high pressure direct fuel injector. Variations in feature design, dimensions, nozzle geometry, electrical connectors and specifications are commonplace in the market for specific variation to each engine application, resulting in a high degree of design variation and component complexity.
The precise control over the volume of injected fuel, the start of injection ("SOI"), and the injection duration are specifically varied based on engine speed and load inputs. These parameters are controlled on a cycle by cycle basis, through an engine control unit ("ECU") by the engine management system ("EMS"), which EMS system operates mathematical models to precisely output the exact fuel injection parameters. These functions of the ECU require considerably more complex processing and memory, as direct injection and EMS must have very precise algorithms for good performance and drivability.
The benefits of gasoline direct injection are derived not only from the precise fuel metering capability and superior fuel atomization at high pressure, but also from the direct fuel delivery and the associated cooling effects. Unlike a port injection fuel system, where fuel is delivered into an intake air path, the direct injection system does not deposit fuel on the interior walls of the intake track, thereby eliminating losses in consumption and control. Direct injection of fuel to the combustion chamber contributes a significant cooling effect to the intake air charge of an internal combustion engine, which cooling is effective in mitigating knock , or pre-detonation or pre-ignition events, which could be present in a non-direct injected engine, especially at high speed and high load operating conditions. The in-cylinder charge cooling provided by GDI allows direct injection engines to operate at higher geometric compression ratios than their port injected counterparts, increasing cycle efficiency. Also, the lack of a fuel film on the intake manifold walls allows for a broader range of fuel cutoff on engine coasting.
The conventional gasoline direct injector is a highly precise and precision assembled component. FIG. 3 is a section illustration of the internals of a common high pressure direct injector 300, with proximal end 301 and distal end 302. The direct fuel injector 300 utilizes a pintle ball 303 and conical seat 304 in the nozzle 305 to seal the fluid passage at the tip of the direct fuel injector 300. The pintle ball 303 is mounted to the pintle shaft 306 and is actuated most commonly by a solenoid 307, and in some cases, by a Piezo-electric crystal system. The solenoid 307 is held in the closed position by spring 308, to maintain a closed seal between the pintle ball 303 and conical seat 304. Energizing the solenoid 307 lifts the pintle ball 303 from the conical seat 304 to allow fluid to pass through the nozzle 305 and into the combustion chamber of an engine. The solenoid 307, when energized, moves to a positive stop position within the injector assembly. The stop position is associated with what is commonly referred to as the solenoid gap, which gap is the distance between the longitudinal position of the solenoid when closed and the longitudinal position of the solenoid when energized and seated against the stop. This solenoid gap can range, for example, from 80 microns (0.080 mm) to 500 microns (0.500 mm) in a conventional high pressure gasoline direct injector, and is critical to the flow rate and flow characteristics of the fluid injected into the combustion chamber. The pintle assembly 309, outside housing 310 and the nozzle 305 (from which fluid flows through high precision orifices and in which the pintle conical seat 304 is located) are precisely machined and assembled to tolerances ranging from, for example, 25 micrometers (0.025 mm) to 5 micrometers (0.005 mm). In addition, the conventional direct injectors are designed to provide a specific fuel flow rate and spray plume shape into the combustion chamber. The nozzles are specifically designed and are precision machined for each different engine combustion chamber design. The design diameter of fluid passages in a conventional gasoline direct injection nozzle, as seen in FIG. 2, can range from, for example, 150 micrometers (0.150 mm) to 350 micrometers (0.350 mm) and typically require high precision computer controlled machining centers, or special electron discharge machining centers, or even high precision laser drilling operations to achieve high precision tolerances. The dimensions and tolerances of a modern conventional high pressure gasoline direct injector present a specific challenge to modification of the same.
The high performance aftermarket for conventional low pressure port fuel injection systems is well established. However, the low pressure port injector is a well-known technology and does not require the level of precision or complexity of a direct injector. The complexity of direct injector manufacturing, high precision tolerance performance and engineering challenges have thus far prevented aftermarket modification of the conventional gasoline direct injector. Attempts at disassembly of a conventional direct injector usually result in the destruction of the direct injector. Attempts to add additional holes to an existing nozzle of a direct injector or attempts at enlarging existing holes in a nozzle of a direct injector usually result in damage to the pintle seat seal, rendering the direct injector unusable due to excessive fuel leakage and/or failure to accurately meter fuel. Attempts of simply grinding the nozzle to expose more fluid passages usually result in the destruction of the fluid spray plume pattern, resulting in uncontrollable fuel injection to the combustion chamber, as well as excessive in-cylinder wall wetting, and wetting of the piston ring pockets and crevices.
Attempting to tune gasoline direct injected engines (with the conventional injector flow rate) to generate higher power is difficult. This is because the only available variables that can typically be manipulated (in the case where injector fuel flow rate is not increased) are start of injection time, total injection duration (the open time), and, to a lesser extent, fuel pressure (running into the limitation of the fuel pump's ability to sustain high flow rates at full pressure). A direct injection engine, where the injector injects directly into the cylinder, is limited in injection window to the intake stroke of the piston, or, in crank rotation terms, limited to 180 degrees of the 720 degrees in a four stroke engine cycle. As the engine rotational speed (RPM) increases, the time available to inject fuel decreases. Hence, all other factors being equal, a gasoline direct injected engine needs higher-capacity injectors with the appropriate spray plume characteristics to achieve higher power.
The use of adapters mounted to the nozzle end of a fuel injector, which adapters assist in enhancing the fuel delivery or modifying the fuel delivery intent of the original injector, such as is prevalent with air-assisted adapters (see, e.g., U.S. Pat. Nos. 6,092,741, 4,982,716, 5,224,458, 5,520,157, 5,597,121, 5,772,122, 5,904,299, 6,095,437) which introduce a stream of air to the fuel via the adapter, with nitrous injection (see, e.g., U.S. Pat. Nos. 6,997,401, 7,533,661) which introduce a stream of nitrous to the fuel via the adapter, gaseous dual fuel injection systems (see, e.g., U.S. Pat. No. 9,038,599) which introduce methane, propane or a form of natural gas into the fuel stream via the adapter; or with surface collision injection mechanisms (see, e.g., U.S. Pat. Nos. 4,925,110, 4,982,716, 5,301,879) which collide a fuel stream with a surface within the adapter, is well practiced in the art of port fuel injector modification. However, these existing fuel injector adapters are typically applied to low pressure fuel injection systems and, furthermore, are typically applied to fuel injectors located in the intake track of an internal combustion engine.
Therefore, a new approach for the modification of a conventional gasoline direct injector is provided by various embodiments of the present invention. This new approach provided by various embodiments of the present invention maintains high precision of the conventional direct injector assembly while permitting modifications in fuel flow and matching of the appropriate in-cylinder spray plume to the application engine combustion chamber.

Method of modifying a conventional direct injector and modified injector assembly


Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprises a first multiplexer for selecting a certain input data from first group of the input data in response to a first selection control signal and a second multiplexer for selecting a certain input data from second group of the input data in response to a second selection control signal; a second multiplexing circuit for setting a sequence of output data from the first multiplexing circuit in response to a third selection control signal; and a second latch circuit comprises a third latch for latching a first output data from the second multiplexing circuit in response to a first output latch control signal and a fourth latch for latching a second output data from the second multiplexing circuit in response to a second output latch control signal. The invention cuts down the overall chip size and current consumption of the pipe latch circuit by reducing the number of multiplexers necessary for arranging the pre-fetched data in a predetermined output order.

1. Field of the Invention
The present invention relates to a semiconductor memory device and specifically, to a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device.
2. Discussion of Related Art
In general, data input and output operations of synchronous semiconductor memory devices are carried out in sync with an internal clock signal generated on basis of an external clock signal. Such synchronous semiconductor memory devices include single data rate (SDR) synchronous dynamic random access memory (SDRAM), double data rate (DDR) synchronous DRAM, and DDR2 SDRAM. Among them, the DDR2 SDRAM generally uses a 4-bit pre-fetch scheme. The 4-bit pre-fetch scheme is a data processing way reading 4-bit data out of memory cells in parallel in response to a single read command and then outputting the read 4-bit data through the same data input/output pin for two clock cycles. Such a DDR2 SDRAM is generally configured as shown in FIG. 1. FIG. 1 is a schematic block diagram of a multi-bit pre-fetch type semiconductor memory device including a conventional pipe latch circuit. Referring to FIG. 1, the semiconductor memory device 10 includes a controller 11, an address input circuit 12, a bank controller 13, an internal core circuit 14, an input/output gating circuit 15, a pipe latch circuit 16, an output driver 17, an input circuit 18, and an input receiver 19. The pipe latch circuit 16 receives data bits D0˜D3 supplied from the input/output gating circuit 15 through a global input/output line GIO and outputs the data bits D0˜D3 in the order of data by a sequential or interleaving mode in response to control signals PIN, SOSEZ0, SOSEZ1_RD, SOSEZ1_FD, RPOUT, and FPOUT. From FIG. 1, operations of internal blocks of the semiconductor memory device 10, except the pipe latch circuit 16, may be easily understood by those skilled in this art, so it will not be described in detail.
FIG. 2 is a detailed block diagram of the pipe latch circuit shown in FIG. 1. Referring to FIG. 2, the pipe latch circuit 10 includes a first latch circuit 20, a first multiplexing circuit 30, a second multiplexing circuit 40, a second latch circuit 50. The first latch circuit 20 includes latches 21˜24 simultaneously latching the data bits D0˜D3, which are pre-fetched from the global input/output line GIO, in response to the control signal PIN. The multiplexing circuit 30 includes multiplexers 31˜34. The multiplexers 31 and 32 select the data bits D0 and D1 independently, which are supplied from the latches 21 and 22, in response to the control signal SOSEZ1, and output the selected data bits as second data bits PRE_FD1 and PRE_FD2 respectively. The multiplexers 33 and 34 select the data bits D2 and D3 independently, which are supplied from the latches 23 and 24, in response to the control signal SOSEZ0, and output the selected data bits as second data bits PRE_FD1 and PRE_FD2 respectively. The multiplexing circuit 40 includes multiplexers 41˜42. The multiplexer 41 selects the first selected bits PRE_RD1 and PRE_RD2 in response to the control signal SOSEZ1_RD, and outputs the selected data bit. The multiplexer 42 selects the second selected bits PRE_FD1 and PRE_FD2 in response to the control signal SOSEZ1_FD, and outputs the selected data bit. The second latch circuit 50 includes latches 51 and 52. The latch 51 holds (or latches) an output signal of the multiplexer 41 in response to the control signal RPOUT, and outputs the latched signal as an output data bit RDOB. And, the latch 52 holds (or latches) an output signal of the multiplexer 42 in response to the control signal FPOUT, and outputs the latched signal as an output data bit FDOB. Here, the control signals SOSEZ0, SOSEZ1_RD, and SOSEZ1_FD are enabled in response to generation of the read command. As a result, an order of the data bits D0˜D3 output from the pipe latch circuit 16 is arranged by the control signals SOSEZ0, SOSEZ1_RD, and SOSEZ1_FD. Meanwhile, the conventional pipe latch circuit 16 aforementioned includes six multiplexers to arrange the data bits D0˜D3 in a predetermined output order. Since the pipe latch circuit is constructed with the feature that one input/output pin is connected to three or four output terminals, the pipe latch circuit more occupies the circuit area as the number of input/output pins of the semiconductor memory device increases. As a result, a size of the pipe latch circuit may hinder in designing a layout construction for internal circuits of the semiconductor memory device. Furthermore, a dimensional increase of the pipe latch circuit causes an increase of the overall chip size.

Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure


A check valve is provided to each discharge port, which communicates between a corresponding working chamber and a high pressure chamber in an integrated compressor/expander apparatus. A valve mechanism, which is opened in a motor mode, is provided to communicate between the working chamber and the high pressure chamber.

1. Field of the Invention
The present invention relates to a fluid machine, which is operable in a pump mode for pressurizing and discharging fluid and is also operable in a motor mode for converting fluid pressure exerted at the time of expansion of fluid into kinetic energy and thereafter outputting the kinetic energy as mechanical energy, and also relates to a waste heat recovering system having the same.
2. Description of Related Art
In a previously proposed vapor compression refrigeration system, which has a Rankine cycle, when energy is recovered through the Rankine cycle, a compressor of the vapor compression refrigeration system is used as an expander, as disclosed in, for example, Japanese Patent No. 2540738.
In the compressor, gas, such as gas phase refrigerant, is drawn into a working chamber upon input of external mechanical energy to the compressor and is compressed by reducing a volume of the working chamber, and thereafter the compressed gas is discharged from the compressor. In the expander, high pressure gas is introduced into the working chamber, and the working chamber is expanded by the pressure of the high pressure gas to output, for example, mechanical energy. Thus, when the compressor is used as the expander, a flow direction of refrigerant needs to be reversed.
However, in the invention recited in Japanese Patent No. 2540738, a refrigerant inlet and a refrigerant outlet of the expander (compressor) used at the time of recovering energy are the same as a refrigerant inlet and a refrigerant outlet of the compressor (expander) used at the time of exerting refrigeration capacity in the vapor compression refrigeration system. Thus, the single compressor cannot be used as the expander. As a result, one of the Rankine cycle and the vapor compression refrigeration system cannot be operated properly.
More specifically, in the compressor, the gas is compressed by reducing the volume of the working chamber upon displacement, i.e., movement of a movable member, such as a piston or a movable scroll. Thus, a check valve is provided in a discharge port, which communicates between the working chamber and a high pressure chamber (discharge chamber), to prevent backflow of the gas from the high pressure chamber to the working chamber.
On the other hand, in the expander, the high pressure gas is conducted from the high pressure chamber to the working chamber to displace, i.e., to drive the movable member and thereby to obtain mechanical output. Thus, even in a case where a means for reversing the gas inlet and the gas outlet is provided in the above arrangement, when the compressor is operated as the expander, the high pressure gas cannot be supplied to the working chamber due to the presence of the check valve, which blocks flow of the high pressure gas into the working chamber. As a result, the compressor cannot be used as the expander even if the means for reversing the gas inlet and the gas outlet is provided.
Furthermore, a volume, i.e., a capacitance of the compressor is normally determined at the time of operation of the vapor compression refrigeration system. However, the pressure exerted in the compressor at the time of operation of the Rankine cycle is higher than the pressure exerted in the compressor at the time of operation of the vapor compression refrigeration system. Thus, even when the same weight flow rate of gas is used in both the time of operation of the vapor compression refrigeration system and the time of operation of the Rankine cycle, a volume flow rate of the Rankine cycle is reduced in comparison to a volume flow rate of the vapor compression refrigeration system. As a result, a rotational speed of the compressor used as the expander is reduced, and a degree of leakage of fluid per rotation of the compressor is increased to decrease an efficiency of the expander.

Fluid machine operable in both pump mode and motor mode and waste heat recovering system having the same


Embodiments of the disclosure are directed to methods, systems, and devices for the use of portable devices, such as a vehicle driven by a user, that are distinctive physical objects and can be presented to an authentication system for authentication purposes. More specifically, the portable device may be used as a source of information for the authentication system that can be verified. Images may be captured of the portable devices in order to determine their distinctive features for comparison to other physical objects registered to the user. The portable devices may also be a source of metadata, or additional contextual information associated with those portable devices or their interaction with the authentication system. The image data and/or the metadata associated with a portable device can be verified for fraud or risk analysis.

In today's technological environment, a user may interact with a variety of computer systems to achieve specific tasks or obtain specific resources. For example, on any given day, a user might interact with a first computer system to gain entry into a train terminal, a second computer system to access his or her office building, a third computer system to log onto his or her employers network, and a fourth computer system to purchase coffee. To interact with each of these computer systems, a user may need to remember specific credentials (e.g. username and password) or carry around entry cards storing credentials (e.g. train pass, credit card, etc.). The credentials are usually required by the various computer systems to authorize access to the user, and are typically managed and stored in a dedicated database specific to the individual computer system for which they were issued. However, this may enable fraudulent interactions where another user steals the specific credentials (or cards storing credentials) in order to obtain access to the various computer systems.
To deal with this issue, tokens are frequently used in order to serve as a surrogate. For example, a token may refer to, or be associated with, a personal account number used to identify a user. Even if the token is somehow compromised (e.g., another user steals the token), the underlying accounts or credentials will not be compromised. However, the use of tokens obfuscates the underlying account information and makes it difficult to perform traditional fraud or risk analysis. Accordingly, there exists a need for contextual information associated with the token to be passed to these various computer systems for enabling fraud or risk analysis to be performed.
Embodiments of the invention address this and other problems, individually and collectively.

System and method for fraud risk analysis in IoT


A tri-phase surge protector comprises a first zinc oxide ceramic body; a first electrode layer on a surface of the first zinc oxide ceramic body and having a first electrode, and the first electrode includes a first terminal; a second electrode layer on another surface of the first zinc oxide ceramic body; a second zinc oxide ceramic body on the second electrode layer; a third electrode layer on another surface of the second zinc oxide ceramic body and having a second electrode, and the second electrode includes a second terminal; a third zinc oxide ceramic body on the second electrode layer and at the second zinc oxide ceramic body; and a fourth electrode layer on another surface of the third zinc oxide ceramic body and having a third electrode, and the third electrode includes a third terminal. The invention also discloses a method for manufacturing a tri-phase surge protector.

1. Field of the Invention
The present invention relates to a tri-phase surge protector and its manufacturing method, and more particularly to a tri-phase surge protector and its manufacturing method that design a three-wire L-N-G protection on a zinc oxide ceramic body to improve the life and reliability.
2. Description of the Related Art
Referring to FIG. 1 for a bottom view and a side view of a prior art surge protector, the prior art surge protector includes a zinc oxide ceramic plate 6 having a conductive layer 7a on both top and bottom sides of the zinc oxide ceramic plates, a copper wire 8 (usually a tin plated copper wire) soldered on an electrode surface 7, an epoxy resin powder coated on an external layer for insulating electric charges and resisting moisture. The operating principle of the prior art surge protector uses a grain boundary phenomenon of the zinc oxide ceramic plate 6 to protect a voltage surge occurred at both ends and discharge surge energy by dissipating the heat, and thus its operation has to produce an electric current passing through the body of the zinc oxide ceramic plate 6 to convert surge energy into heat.
Referring to FIG. 2 for the schematic view of using a prior art surge protector to protect a three-wire L-N-G power supply, the surge protector is traditionally used for protecting a three-wire L-N-G power supply. Generally, three independent surge protectors 9 are used for protecting the power supply from being damaged by a surge occurred in the L-N-G terminals, wherein each surge protector 9 independently completes the protection between two wires.
Refer to FIGS. 3(a), 3(b), and 3(c) respectively for the bottom view, the side view, and the schematic equivalent circuit diagram of a three-terminal single-layer device as disclosed in JPN Pat. No. 59-5601, JPN Pat. No. 59-5601 based on the purpose of simplifying the circuit to design a three-terminal single-layer device 100. From its appearance, the three-terminal single-layer device 100 includes three terminals d, e, f, but the equivalent circuit diagram as shown in FIG. 3(c) shows that such method only protects the terminals d-f, and e-f, and there is no appropriate protection between the terminals d-e. Since there is no physical volume (grain boundary) between d and e for passing the terminal, therefore a breakdown will occur at d with respect to e under an appropriate electric field, and the surge energy cannot be removed by dissipating heat. There is no equivalent surge protector existed between d and e in the equivalent circuit diagram as shown in FIG. 3(c), and thus the design is incomplete for the protection.
Referring to FIGS. 4(a) and 4(b) respectively for the bottom view and the side view of a three-terminal single-layer device as disclosed in R.O.C. Pat. No. 313713, R.O.C. Pat. No. 313713 improved the design of the three-terminal single-layer device 120 as depicted in FIG. 3. From its appearance, the three-terminal single-layer device 120 includes three terminals g, h, k. In FIGS. 4(a) and 4(b), if an abnormal voltage occurs at each time of starting, it is necessary to have a breakdown (which produces a current) occurred at a terminal (assumed to be g in this embodiment) of the electrode 121 with respect to the electrode 123 on another side, and the electrode 123 produces a second breakdown (which produces a current) occurred at a terminal h of the electrode 122 or a terminal K of the electrode 123, and thus it is necessary to pass the current through the ceramic body twice for protecting the device each time. In other words, it is necessary to use the original designed area (121, 122 and 123) twice (121+122 or 122+123 or 121+123) to complete the protecting function. Such arrangement not only lowers the reliability, but also provides a resistance much smaller than three independent surge protectors (having a working area equal to 121 or 122 or 123) under the same lightning strike condition because the equivalent area is half of the original design.
Therefore, the present invention provides a tri-phase surge protector and its manufacturing method that design a three-wire L-N-G protection on a zinc oxide ceramic body to improve the product life and reliability.

Tri-phase surge protector and its manufacturing method


A wireless communication system includes a primary station which has a transmitter for transmitting wireless signals on a downlink, and a plurality of secondary stations each having a receiver for receiving signals on the downlink and a transmitter for transmitting on an uplink. In a normal, loaded condition a synchronization channel and a data channel are present on the downlink and closed power control is achieved by measuring the signal to interference ratio (SIR) in a received downlink transmission, comparing the measured SIR with a target SIR and sending a power adjust indication on the uplink to cause the primary station to adjust its transmitted power on the downlink. The secondary station monitors the downlink and, in response to detecting an unloaded cell condition, determines a target SIR offset which it applies to the target SIR to overcome interference from the presence of the synchronization channel on the downlink.

Under UMTS standards based on W-CDMA (W-Code Division Multiple Access) techniques, the downlink as well as the uplink dedicated physical channel (DPCH) is power controlled. In particular, from the user equipment (UE) point of view, it means that more or less power can be asked of the base or primary stations (BS) forming the fixed network in order to reach the Quality of Service (QoS) determined by the network itself. In the UMTS standard this QoS is measured in terms of the Block Error Rate (BLER) and refers to Outer Loop Power Control. In order to reach the expected QoS, the UE implements an algorithm, which translates the BLER requirement into a target SIR (Signal to Noise and Interference Ratio). This algorithm is frequently termed the target SIR algorithm. The 3GPP standard specification does not specify a method of defining the target SIR algorithm. It is left to individuals and/or manufacturers to set their own definitions.
One of the challenges in defining the target SIR algorithm is the fact that the target SIR may vary during communication, due to a variable propagation environment, variable required BLER, and/or possible reconfiguration of the Dedicated Physical Channel (DPCH). Once the target SIR has been calculated, the UE compares the SIR measured on a slot basis on the received DPCH with the target SIR. If the measured SIR is below the target SIR, the UE will require more power from the BS. Conversely, if the measured SIR is above the target SIR, the UE will signal the BS to decrease its transmitted power. This procedure is referred to as the Inner Loop Power Control.
Depending on the algorithm chosen for the target SIR, the performance of the receiver will be affected. In particular there are requirements in the UMTS standard specifying the maximum power a UE can ask and the maximum BLER allowed, as well as the convergence time to the required quality, for several propagation scenarios. Operators also have their own criteria in terms of maximum downlink power. Operators compare each UE to a reference UE and a UE unable to reach the desired quality at less or equal to the corresponding downlink power supplied to the reference UE may be rejected. An efficient target SIR algorithm is therefore needed.
Known proposals for open loop power control in third generation wireless communication systems are disclosed in US 20050243752 A1, EP 1067815 A1, US 20050099968 A1, WO 2005032011 A1, US 20050085255 A1 and GB 2408419 A1. US 20050243752 A1 discloses a target SIR which is adjusted based on a filtered scaling factor derived from a comparison of cell loading with a threshold. More particularly the target SIR is increased when the cell loading is high. EP 1067815 A1 discloses increasing a target SIR if the cell load is greater than a threshold. US 20050099968 A1 identifies that the synchronisation channel SCH is transmitted without being channel coded, that is scrambled, and may be regarded as a source of interference degrading the dedicated control channel DCCH if they overlap. In order to resolve this problem it is proposed that the target SIR be increased whenever the DCCH and SCH overlap. WO 2005032 011 A1 discloses setting of a target SIR based on frame errors in a dedicated physical data channel (DPDCH) and the field transmitted through the backward DPDCH. US 20050085255 A1 discloses setting a target SIR based on information from a number of channels. Finally, GB 2408419 A1 discloses setting the target SIR depending on the type of service provided.
Important points relating to setting the target SIR procedure are:                (1) The target SIR is in general a very long-term procedure requiring decoding of hundreds of blocks in order to have good BLER statistics before changing the target SIR value. This target SIR value is consequently very stable in time.        (2) The target SIR initial value is also important. Two approaches to setting this value can be found in the literature. In one of the two approaches a high value is set to ensure the decoding whatever the propagation conditions and in the other of the two approaches an average value, determined after analysis of the test cases provided in the standard, is set.
None of these prior proposals consider open loop power control when unloaded cell conditions prevail. Unloaded cell conditions are a realistic case in the field and a common case in Inter-operability Test (IOT). The main characteristics of unloaded cells are: low interference from other users, good lor/loc (ratio between in-band received signal power and other surrounding cells interference power), SCH (Primary Synchronisation Channel (PSCH) used for slot timing and Secondary Synchronisation Channel (SSCH) used for frame synchronisation) and Primary Common Control Physical Channel (PCCPCH).

Wireless transmission power control method and system


Burner for gas oven comprising a device for retaining a flame of the burner, separating the flame from a mixing chamber capable of receiving a flow of primary air and gas to form a gaseous mixture. The flame retention device is provided with a mesh comprising metal threads, capable of allowing said gaseous mixture to pass through the mesh, said mesh comprising at least one main zone and a pilot zone which are adjacent. The pilot zone having, according to a main direction of the flame of the burner, a thickness greater than the thickness of the main zone, capable of slowing down the gaseous mixture passing through the pilot zone relative to the mixture passing through the main zone. The burner comprises at least one orifice capable of receiving a secondary air flow.

1. Field of the Invention
The invention generally relates to heating systems for ovens, particularly gas heating systems.
2. Description of the Relevant Art
In the field of gas burners for ovens, the ovens are used in large commercial or institutional kitchens.
The energy produced by the combustion is recovered in thermal form. The products of the gas combustion pass through, for example, heat exchanger tubes where they are cooled to remove the thermal energy therefrom. Apart from possible pressure losses in the heat exchanger tubes or in chimney flues, the combustion gases from the burner are substantially at atmospheric pressure. The mechanical energy of the combustion gases from the burner is a drawback, causing vibrations and noise in the oven.
A gas cooker fitted with hollow heating elements passed through by combustion products from a gas burner is known. One drawback of this type of burner is the limited thermal power. More specifically, when the flow of the mixture of air and inflammable gas increases, the propagation speed of the combustion of the flame in the gas mixture flow may be lower than the speed of the flow of the mixture and the flame blows off the burner. If the phenomenon is not rapidly corrected, the flame is blown out and extinguished. Conversely, if the gas mixture flow is lower than the propagation of the flame, said flame may go upstream of the burner. A further drawback of this type of oven is that under the effect of the thermal variations and the mechanical effects of the combustion gas flow, the heating elements, brought to a high temperature, may start to vibrate. This causes an unpleasant noise and reduces the lifespan of the oven.
A flame retention plate is known for a gas burner. This plate plays the role of a distribution screen for the gas mixture streams. It comprises a compressed network of interwoven threads. This structure allows gas streams to pass in a substantially evenly distributed manner over the entire surface of the plate and a uniform distribution of the flame produced. However, this type of burner has the drawback of being restricted in the thermal output per cm2 of the retention plate. Moreover, this type of burner aims to produce flames of relatively low height and where the thermal output is localised close to the retention plate. It is apparent that this type of burner is suitable for heating, from the outside, water coils for domestic boilers, for example. For ovens, it is desirable to heat the heat exchanger tubes from the inside. It is desirable to distribute the flame to reduce hot spots.
A flame retention device is known, comprising several identical rings composed of a compressed network of interwoven metal threads. The gas mixture passes through the rings in a radial manner. Each of the rings produces a radial circular flame. The rings are coaxial and superposed over one another and separated by solid crosspieces, which are not passed through by the gas mixture. The external diameter of the solid crosspieces is less than the external diameter of the rings of the compressed network. Pilot flames are formed in the grooves corresponding to the crosspieces. The aforementioned drawback, namely that of increasing thermal energy solely at the point of the retention plate of the burner, is accentuated here, as the combustion gases are propagated radially relative to the axis of the burner.
A burner provided with porous tubular body elements is known. The wall of the tube is made of a compressed network of threads. A plurality of tubular shapes are axially nested in one another to form a burner of larger dimensions. The stabilisation of the flame is improved by a deflector plate. In this type of burner, the thermal energy is released radially relative to the axis of the burner.
A burner head has been disclosed where a sealed combustion chamber opens into a plurality of heat exchanger tubes passed through by the combustion gases. A housing surrounding the combustion chamber brings fresh air to the heat exchanger tube inlet to reduce the temperature of the transition between the combustion chamber and the heat exchanger tubes. In this type of burner, the air contributing to the combustion of the inflammable gas is entirely contained in the gas mixture upstream of the combustion chamber. The combustion products are discharged through heat exchanger tubes by an outlet manifold. The drawback with this type of burner is that, for limiting the combustion products which are not oxidised by combustion, it is necessary to introduce into the gas mixture, which passes through the burner, excess air relative to the stoichiometric proportions of the gas. For a given thermal output of the burner, the over-supply of air may cause a detachment of the flame. Even if the detachment of the flame is limited, however, the over-supply of air reduces the thermal output of the flame.
A need exists for a burner for a gas oven which alleviates the aforementioned drawbacks and, in particular, which allows the thermal energy of the burner to be increased, by avoiding the detachment of the flame and by distributing said flame.


The different signal generation circuit has a first transistor MP2 connected between a first power supply line Vcc and a first output terminal OTP and a gate connected to a first node, a second transistor MN2 connected between the first output terminal OTP and a second power supply line GND and a gate connected to a second node, and a delay circuit 31 and 13 connected between the first node and the second node.

1. Field of the Invention
The present invention relates to a differential signal generating circuit, and more particularly, to a differential signal generating circuit having a current spike suppressing circuit for suppressing a current spike generated at current change-over of a differential switch and reduce the power consumption.
2. Description of the Prior Art
Heretofore, a differential signal generating circuit 16 as shown in FIG. 8(a) has been known as a differential signal generating circuit for driving a high speed differential switch by means of a CMOS circuit. This differential signal generating circuit 16 is interposed between a D type flip-flop (referred to as DFF hereinafter) 17 for taking synchronism with data, and a differential switch 18 comprising p-channel MOS transistors MP3, MP4, and MP5. The differential signal generating circuit 16 receives a positive phase input IN and generates mutually opposing positive and negative phase signals OTP and OTN.
The differential signal generating circuit 16 formed by inverters 22-24, 32, 42, and 43 in multistages is used as shown in FIG. 9(a). In this circuit, specific output signals are obtained by connecting the inverters 22, 24, 32, and 43 so as to form even-numbered stages on the side of the positive phase output OTP, and by connecting the inverters 22, 23, and 42 so as to form odd-numbered stages on the side of the negative phase output OTN. Here, the sizes of the inverters are chosen, by taking the size of the inverters 22-24 unity, to be 2 for the inverter 32, and 3 for the inverters 42 and 43. In addition, the channel width W and the channel length L of the transistor MP3 are taken to be 250 .mu.m and 3 .mu.m, respectively, and the channel width W of the transistors MP4 and MP5 is set to be 60 .mu.m.
In order to obtain a differential switch operating at a higher speed, a DFF17A which generates a negative phase output ON as a data output in addition to the positive phase output Q, as shown in FIG. 8(b), may be used. A differential signal generating circuit 16A for using the negative phase output QN may be formed by inserting equivalent digital signal transmission circuits between the positive phase input IN and the positive phase output OTP, and between a negative phase input INN and the negative phase output OTN, respectively. For example, as shown in FIG. 9(b), the positive phase output OTP may be obtained by serially connecting the inverter 22 receiving the positive phase input IN and the inverter 42 driving the gate of the transistor MP4 of the differential switch 18, and the negative phase output OTN may be obtained by serially connecting the inverters 23 and 43.
The circuit of the DFF17 comprises p-channel MOS transistors MP31-MP34, n-channel MOS transistors MN31-MN34, and inverters 51, 52, 55, and 56, as shown in FIG. 10(a), forming a normally used CMOS D flip-flop. When a clock CK, positive relative to the level of a data signal input to a data input terminal D, changes from low level to high level (a clock with the level opposite to the positive phase clock CK is input to a negative phase clock terminal CKN), the DFF17 instantaneously fetches the signal level of data D and outputs the signal as a positive phase data Q. In the circuits in FIG. 10(a), and in FIG. 10(b) to be mentioned presently, the size of the inverters 51-52 is set to be 1.5, and that of the inverters 36 and 55-57 is set to be 0.75, by taking the size of the inverter 22 unity, and the channel width of the transistors is set to be 4 .mu.m.
In the DFF17A in FIG. 8(b), for the positive phase data output Q and the negative phase data output QN, the configuration is so arranged as to generate equivalent output signals by suppressing the increase in the number of elements. The circuit of the DFF17A is formed by adding a latch part consisting of inverters 36, 53, and 57, p-channel MOS transistors MP35 and MP36, and n-channel MOS transistors MN35 and MN36, to the output of the inverter 51, as shown in FIG. 10(b).
The differential switch 18 comprises a p-channel MOS transistor MP3 which is a constant current source, and p-channel MOS transistors MP4 and MP5 for switching the current. The transistors MP4 and MP5 are connected to the positive phase output OTP and the negative phase output OTN, respectively, of the differential signal generating circuit 16 so as to let a current flow in the transistor MP4 or MP5 to which is input the signal with the lower level of the two outputs.
In order to suppress the current spike at a current output terminal IO or ION through adjustment of the rise and fall times of the positive phase output OTP and the negative phase output OTN of the differential signal generating circuit 16 supplied to the differential switch 18, a circuit as shown in FIG. 9(c) is also employed. This circuit is disclosed in the Digest Paper No. 10.5, 1 entitled "A 350-MS/S 3.3-V 8-bit CMOS D/A Converter Using a Delayed Driving Scheme" of the 1995 Custom Integrated Circuits Conference (CICC).
The circuit in FIG. 9(c) uses similar component elements as in the circuit in FIG. 9(b), but the gate electrodes of p- and n-channel MOS transistors MP21, MP22 and MN21, MN22 are arranged to be driven by mutually different signals. Namely, the gate electrodes of the transistors MP21 and MP22 are connected to the outputs of the inverters 22 and 23, respectively, and the gate electrodes of the transistors MN21 and MN22 are connected to the inputs INN and IN, respectively, which are opposite in phase to the outputs of the transistors MN21 and MN22. As a result of such a connection, the signals of the p-channel MOS transistors MP21 and MP22 are delayed by an amount corresponding to one stage component of the inverter relative to the signals of the n-channel MOS transistors MN21 and MN22.
The circuit of the prior art differential signal generating circuits described above will be explained using the result of verification of transient analysis of the circuit operation by appropriately setting the sizes of respective transistors. What is meant by the size of the transistor is the channel width W, and the channel length L means the minimum producible length of the transistor. Further, the sizes of the inverters are set to be 2 for the inverter 32, 3 for the inverters 42 and 43, 1.5 for the inverters 51-53, and 0.75 for the inverters 36 and 55-57.
When the differential switch 18 in FIG. 8(a) is switched at a high frequency of several hundreds of MHz, sometimes there occur a nonconductive state, though momentarily, in the operation of the transistors MP4 and MP5, and as a result, a current spike is generated in the current output terminal IO or ION. This current spike has a drawback in that when the current path in either one of the transistors MP4 and MP5 is switched to the other current path, it prolongs the settling time before the current generated at the current output terminal IO or ION attain a stationary condition, obstructing the differential switching operation at high speed.
In other words, if the MOS transistors MP4 and MP5 are turned on simultaneously in the differential switch 18, the drain voltage of the transistor MP3 is raised and charge is accumulated in the portion connected to the drain. When either of the transistors MP4 or MP5 is turned off in this state, the accumulated charge is suddenly discharged and produces a spike at its output terminal IO or ION. Consequently, it takes time before the current settles stably in a stationary state, which gives rise to a problem that it obstructs the high speed operation of current switching of the differential switch.
The above problem will be described in more detail in the following.
First, the various transistors are set so as to give a normal threshold voltage which is 1/2 of a power supply voltage 3.3 V for the sizes of the inverters of the differential signal generating circuit 16 in FIG. 9(a). The result of verification of transient analysis when clocks and data as shown in FIGS. 11(a) and 11(b) are input for the combination of the circuit 16 having these inverters and the DFF17 in FIG. 10(a) as in FIG. 8(a), is shown by H of the positive phase output OTP and J of the negative phase output OTN in FIG. 12(a). From the figure it can be seen that the intersection P of the voltage waveforms at approximately the time 30 ns is about 2.8 V. In other words, since the gate potentials of both transistors MP4 and MP5 have values near the power supply voltage 3.3 V, both transistors are in states close to deenergized state, so a current spike L as shown in FIG. 14(a) is generated at the current output terminal IO.
The reason for this is the difference in the number of stages of the inverters in FIG. 9(a), namely, the positive phase output OTP side has one more stage of the inverter 24 than the OTN side, gaining more delay corresponding to this component, and tends to cause the voltage intersection P to be generated at a position closer to the power supply voltage side. That the gate voltages of the transistors of the differential switch are high means that the rise of the voltage waveforms is fast and their fall is slow. That is, owing to the fact that both transistors are of p-channel type, they are turned off soon if the rise is fast, and are turned on late if the fall is slow. In other words, both transistors are likely to be turned off simultaneously, and in the opposite case, the time for both transistors to remain turned on becomes long.
Even when the channel width W of the p-channel MOS transistor is made to be 14 .mu.m equal to the channel width W of the n-channel MOS transistor for the purpose of improving on this point, the intersection P of the positive and negative phase voltage outputs at 30 ns is reduced by only about 1.5 V, as shown in FIG. 12(b), and gives rise to a current spike L as indicated in FIG. 14(b).
Further, in order to reduce the size of the current spike L, a drive circuit may be configured as in FIG. 8(b) where the positive and negative phase signal paths are formed equivalently by using a DFF17A as in FIG. 10(b) for obtaining both of positive and negative phase outputs and a differential signal generating circuit 16A as shown in FIG. 9(b). In these circuits, the channel width W of each of the p- and n-channel MOS transistors in FIG. 9(b) is set to be 14 .mu.m in order to slow down the rise and hasten the fall of the inverters 22 and 23. This is arranged so as to make the three times the area of the inverter of reference size equal to the total sum of the gate areas of the MOS transistors. In addition, the values of W and L of the transistors in the other figures are set to be the same as before if their symbols are identical.
The simulation result of the verification of transient analysis using this circuit is shown in FIG. 13(a). Although the intersections R and P of the positive phase output OTP and the negative phase output OTN which arise at about the times 25 and 30 ns, respectively, show an improvement, the size of the current spike L at the current output terminal IO shown in FIG. 15(a) has a large value as in FIG. 14(b).
When the circuit in FIG. 9(c) instead of that in FIG. 9(b) is used as a mean for improving the current spike, the result of simulation of the transient analysis verification of the circuit where the channel width W of the p- and n-channel MOS transistors MP21, MP22 and MN21, MN22 is set to be 14 .mu.m is shown in FIG. 13(b). In this case, it is possible to reduce the waveform intersections R and P, where the positive and negative phase outputs OTP and OTN cross each other at about 25 and 30 ns, respectively, to about 0.5 V, and make the current spike L at the current output terminal IO small as in FIG. 15(b).
However, in this circuit the signals in the p-channel MOS transistors MP21 and MP22 are delayed than the signals in the n-channel MOS transistors MN21 and MN22 by the amounts corresponding to the inverters 22 and 23. Accordingly, when the gate input signals are inverted, there arises a state in which both of the p- and n-channel MOS transistors MP21, MP22 and MN21, MN22 find themselves in the energized state. Because of this, there is a problem in that the through current gets very large, and the number of elements of the DFF in FIG. 10(b) is increased, so that there are more defects than in the aforementioned circuit (the circuit in FIG. 8(a) using the circuits in FIG. 9(a) and FIG. 10(a)).
The simulation result of the transient analysis verification of these circuit is shown in FIGS. 16(a) and 16(b). Namely, for the circuit in FIG. 8(a) using the circuits in FIG. 9(a) and FIG. 10(a), the changes in the current consumption are represented by the peak current 3.95 mA and the mean current 238 .mu.A as shown in FIG. 16(a). For the circuit in FIG. 8(b) using the circuits in FIG. 9(c) and FIG. 10(b), the changes in the current consumption are represented by the peak current 6.11 mA and the mean current 354 .mu.A.

Differential signal generating circuit having current spike suppressing circuit