A vacuum microelectronic transistor which can operate at a high speed and has a high mutual conductance. The vacuum microelectronic transistor comprises an emitter for emitting electrons therefrom, a collector for receiving electrons from the emitter, and a pair of gate electrodes for controlling arrival of electrons from the emitter to the collector. The emitter and collector are disposed in an encapsulated condition on a substrate such that electrons emitted from the emitter run straightforwardly in vacuum to the collector while the gate electrodes are located adjacent and across a route of such electrons from the emitter to the collector. Also, a process of manufacturing such vacuum microelectronic transistor is disclosed.

1. Field of the Invention
This invention relates to a vacuum microelectronic transistor wherein electrons flow in vacuum and a process of manufacturing the same.
2. Description of the Prior Art
A semiconductor device wherein electrons flow in semiconductor is limited in high speed operation due to an upper limit to mobility of electrons in the semiconductor. Therefore, attention has focussed in recent years to vacuum microelectronics wherein electrons flow in vacuum, and many investigations are being made in vacuum microelectronics.
A transistor as shown in FIG. 1 is known as a vacuum microelectronic transistor. Referring to FIG. 1, the transistor shown includes a conductive silicon (Si) substrate 1, an emitter 2 of a conical shape formed on the silicon substrate 1, and an insulating film 3 formed on the silicon substrate 1 around the emitter 2. A gate electrode (or base) 4 and a collector (or anode) 5 are formed on the insulating film 3.
The transistor of FIG. 1 performs a transistor operation suck that electrons (e.sup.-) are emitted from the emitter 2 and flow through the in vacuum to the collector 5, the flow of such electrons to the collector 5 is controlled by the gate electrode 4.
In the transistor shown in FIG. 1, in order for electrons emitted from the emitter 2 to reach the collector 5, the direction of movement of the electrons must necessarily be changed a great extent as indicated by the arrow marks in FIG. 1. Therefore, electrons cannot be accelerated to a very high speed, and accordingly, high operation of the transistor cannot be achieved.


Aspects for achieving individualized protected space in an operating system are provided. The aspects include performing on demand hardware instantiation via an ACE (an adaptive computing engine), and utilizing the hardware for monitoring predetermined software programming to protect an operating system.

As is generally understood in computing environments, an operating system (O/S) acts as the layer between the hardware and the software providing several important functions. For example, the functionality of an O/S includes device management, process management, communication between processes, memory management, and file systems. Further, certain utilities are standard for operating systems that allow common tasks to be performed, such as file access and organization operations and process initiation and termination.
Within the O/S, the kernel is responsible for all other operations and acts to control the operations following the initialization functions performed by the O/S upon boot-up. The traditional structure of a kernel is a layered system. Some operating systems use a micro-kernel to minimize a size of the kernel while maintaining a layered system, such as the Windows NT operating system. FIG. 1 illustrates an example diagram of a typical layered structure, such as for the Windows NT operating system. As shown, the applications 10 lie above the O/S 20, where each application typically resides in its own memory space. The micro-kernel 30 interacts with a hardware abstraction layer 40 (e.g., with device drivers) associated with hardware layer 50. The line 60 represents a demarcation line indicating the separation between which normally is considered the user space of the applications, and the protected space of the operating system.
While the typical structure provides a well-understood model for an operating system, some problems remain. One such problem is the potential for crashing the machine once access below the demarcation line 60 is achieved. For example, bugs in programs that are written for performing processes below the demarcation line, e.g., device drivers that interact with the hardware abstraction layer, protocol stacks between the kernel and the applications, etc., can bring the entire machine down. While some protection is provided in operating systems with the generation of exceptions in response to certain illegal actions, such as memory address violations or illegal instructions, which trigger the kernel and kill the application raising the exception, there exists an inability by operating systems to protect against the vulnerability to fatal access.
An approach to avoiding such vulnerability is to limit which software is trusted within an operating system and utilizing control mechanisms that check all other programming prior to processing. Relying on software to perform such checks reduces the ability to limit the amount of software that is trusted. A hardware solution would be preferable, but, heretofore, has been prohibitive due to the level of instantaneous hardware machine generation that would be necessary.
Accordingly, what is needed is an ability to achieve a protected operating system through on demand hardware monitoring. The present invention addresses such a need.

Method and system for achieving individualized protected space in an operating system


A camera fixing device includes a fixing assembly fixed to an external component, a mounting assembly for mounting the camera; and a connection assembly connected between the fixing assembly and the mounting assembly; the connection assembly comprises a first ball head, the mounting assembly comprises a second ball head, a first end of the connection assembly comprises a first receiving space which receives the first ball head and allows the first ball head to rotate therein, and a second end of the connection assembly comprises a second receiving space which receives the second ball head and allows the second ball head to rotate therein. Due to the fact that the ball head can rotate in the corresponding receiving space, the camera fixing device of the present invention can flexibly rotate and realize an omnidirectional shooting in a three-dimension space.

Nowadays, cameras have become an essential item for outdoor trips; since handheld shooting often easily causes blurry picture due to shaking of the camera, a holding device is typically adopted to hold the camera such that the handheld shooting can be avoided.
However, when the camera is mounted in the existing holding device, the shooting direction is often single and the rotation is inflexible, which cannot meet the multi-direction and multi-angle shooting requirement. Moreover, when the holding device is fixed to a smooth object, the stability is poor; in addition, the camera is mounted in the holding device in a simple way, which cannot meet the shooting requirement of high stability in motion.


An object is to provide possible web quality estimation for changes in network quality without simulating each combination of network qualities or acquiring operation log information in advance. One aspect of the present invention is a web quality estimation device that estimates web quality which is a processing time of a web content, based on input of a content identifier of the web content and one or more network qualities, and includes: a content characteristic storage unit that stores correspondence information between a content identifier for identifying a web content and one or more content characteristics for a plurality of web contents; and a web quality estimation unit that receives input of a content identifier and one or more network qualities, refers to the corresponding information to acquire one or more content characteristics corresponding to the input content identifier, and estimates web quality from the one or more content characteristics and the input one or more network qualities.

With advanced communication networks and sophisticated devices, a large variety of services and contents are being provided via the Internet. Among them, web content is now provided including not only entertainment-related, but also business-related, which has become indispensable to our lives.
It is known that the processing time of web content (hereinafter referred to as web quality) has a strong correlation with the user experience quality. Further, in terms of web quality, improvement of network quality is important because the transfer time on the network accounts for a large proportion. Therefore, in order to satisfy the web quality that allows the user to comfortably use web content, it is required to clarify the relationship between the web quality and the network quality. Therefore, it is important to estimate the web quality so that a change in the web quality due to a change in the network quality can be grasped.
In a conventional web quality estimation, dependency relationships between objects that make up a web page and operation log information of the page as operated are acquired, and latency, which is one of the network qualities, is used (NPL 1).
Further, in another web quality estimation, object groups to be processed at the same time is estimated based on an operation log measured in advance, and the processing time when two network qualities of latency and throughput change for each object group is calculated (PTL 1).

Web quality estimation apparatus and program

Nippon Telegraph and Telephone Corporation


A new Raspberry plant particularly distinguished by being a primocane raspberry plant having favourable fruit color and flavour, large and firm berry, and good tolerance to raspberry pests and diseases, is disclosed.

The present invention comprises a new and distinct cultivar of red raspberry, botanically known as Rubus idaeus L., and hereinafter referred to by the cultivar name 'Erika'. 'Erika' was produced from an open pollination of the female parent 'Autumn Bliss' (U.S. Plant Pat. No. 6,597).
The new cultivar was created in 2002, in Trentino, Italy and has been asexually reproduced repeatedly by root cuttings since May 2007. The present invention has been found to retain its distinctive characteristics through successive asexual propagations in Trentino, Italy.
Plant breeder's rights were applied for with the European Union on Mar. 12, 2007. 'Erika' has not been made publicly available more than one year prior to filing of this application.


A cleaning blade failure prediction processor for an image forming apparatus includes a pixel count acquisition circuit to acquire pixel count data of a cleaning target of a cleaning blade. The cleaning target is divided into a plurality of areas in a main scanning direction of the cleaning target. The pixel count acquisition circuit acquires a pixel count for each of the plurality of areas of the cleaning target. The cleaning blade failure prediction processor also includes a first cumulative pixel count calculation circuit to calculate a cumulative pixel count for each of the plurality of areas of the cleaning target, a second cumulative pixel count calculation circuit to calculate a cumulative pixel count per distance traveled of the cleaning target, and a deformation identification circuit to determine whether or not the cleaning blade shows signs of deformation according to the cumulative pixel count per distance traveled.

1. Technical Field
Embodiments of the present invention generally relate to a cleaning blade failure predictor and an image forming apparatus, and more particularly, to a cleaning blade failure prediction processor for predicting a failure resulting from deformation of a cleaning blade that contacts and cleans a cleaning target, and to an image forming apparatus incorporating the cleaning blade failure prediction processor:
2. Background Art
Various types of electrophotographic image forming apparatuses are known, including copiers, printers, facsimile machines, or multifunction machines having two or more of copying, printing, scanning, facsimile, plotter, and other capabilities. Such image forming apparatuses usually form an image on a recording medium according to image data. Specifically, in such image forming apparatuses, for example, a charger uniformly charges a surface of a photoconductor serving as an image carrier. An optical writer irradiates the surface of the photoconductor thus charged with a light beam to form an electrostatic latent image on the surface of the photoconductor according to the image data. A development device supplies toner to the electrostatic latent image thus formed to render the electrostatic latent image visible as a toner image. The toner image is then transferred onto a recording medium directly, or indirectly via an intermediate transfer belt. Finally, a fixing device applies heat and pressure to the recording medium carrying the toner image to fix the toner image onto the recording medium.
In such image forming apparatuses, after the toner image is transferred from the photoconductor, there may be residual toner that fails to be transferred from the photoconductor and therefore remaining on the photoconductor. Similarly, after the toner image is transferred from the intermediate transfer belt, there may be residual toner that fails to be transferred from the intermediate transfer belt and therefore remaining on the intermediate transfer belt. To remove such residual toner, the image forming apparatuses typically include cleaners provided with cleaning blades that contact the photoconductor or the intermediate transfer belt to remove residual toner therefrom.

Cleaning blade failure prediction processor and image forming apparatus incorporating same


A driving-force distribution control device includes a distributing mechanism, a distribution controller, an anti-skid brake system, an acceleration detector, a synthesized acceleration calculator and a control coefficient controller. The distributing mechanism is operable to variably distribute a driving force from an engine to individual drive wheels of a vehicle. The distribution controller is operable to control the distributing mechanism based on a running state of the vehicle. The acceleration detector is operable to detect a first acceleration in a front-rear direction and a second acceleration in a left-right direction of the vehicle. The synthesized acceleration calculator is operable to calculate a synthesized acceleration of the first acceleration and the second acceleration. The control coefficient controller is operable to indiscretely vary control coefficients for restricting the control of the distribution controller when the anti-skid brake system is activated, according to the calculated synthesized acceleration.

1. Field of the Invention
The present invention relates to a driving-force distribution control device for distributing a driving force properly to individual drive wheels of a vehicle.
2. Description of the Related Art
Drive wheels of an automobile is provided with a differential gear (a differential device) between the left wheels and the right wheels. As a result, the automobile can turn smoothly while allowing a difference in the rotating speed between the left-right wheels at the turning time. Generally in the case of a four-wheel drive vehicle, moreover, not only the aforementioned left-right wheel differential gear but also a differential gear (a center-diff) is disposed between the front wheels and the rear wheels so that the rotating speed difference between the front and rear wheels can be allowed.
In recent years, vehicles imaging to be used on rough roads, and vehicles imaging to be used for sporty driving are frequently provided with a differential limiting device for limiting the differential motion due to the differential gear. This differential limiting device is represented by a limited slip differential (LSD), which can be electrically or mechanically controlled to distribute a proper driving force to the desired drive wheels even if any drive wheel slips.
Further, there has been developed a driving force distributing system, which is intended not only for the case of a mere slip of drive wheels, but also positively activates the aforementioned LSD to improve the turning performances, the accelerating performances and the stability performances of the vehicle. This driving force distributing system is exemplified by a front-rear wheel driving-force distributing mechanism capable of changing the driving force distribution of the front-rear wheels, a left-right wheel driving force distributing mechanism capable of changing the driving force distribution of the left-right wheels, an electronic control LSD, an electronic control coupling or the like.
On the other hand, a vehicle equipped with an anti-skid brake system (ABS) has been developed and put into use so that the vehicle can be reliably decelerated while retaining its steerability during breaking.
Here, the vehicle having both the aforementioned driving-force distributing system and the ABS have a problem that the control by the driving-force distributing mechanism and the control by the ABS interfere with one another. For example, Japanese Patent Publication No. 2005-104233A discloses a technology that can solve that problem and improve the control affinity between the driving-force distributing system and the ABS. According to this technique of Japanese Patent Publication No. 2005-104233A, the control mode of the driving-force distributing system is suitably interchanged in response to the action/inaction of the ABS between an ordinary mode and a control mode (an ABS corresponding mode) that does not obstruct the effect by the ABS control, and in the ABS corresponding mode, switching depending on whether the road surface μ is a high μ (corresponding to a dry asphalt road surface) or a low μ (corresponding to a wet asphalt road surface). On the high-μ road, more specifically, the control by the left-right wheel driving-force distributing mechanism is given preference, but the control by the ABS is given preference for the longitudinal direction. On the low-μ road, the control mode is changed so that the entire control by the ABS is given preference. Moreover, the specific control modes of the driving-force distribution control are exemplified by the rotating speed difference control (a ΔN control) between the front-rear wheels and the left-right wheels, the acceleration corresponding control, the deceleration corresponding control and so on. On the high-μ road, the control is made to reduce the controlled variable only for the ΔN control. On the low-μ road, the controlled variable of the ΔN control is further reduced so that only the ΔN control is made without the acceleration corresponding control or the deceleration corresponding control.
In the aforementioned technique disclosed in Japanese Patent Publication No. 2005-104233A, the control mode of the driving-force distributing system during operation of the ABS basically switches two ABS corresponding modes (for the high-μ road and the low-μ road). Therefore, the technique raises a problem that the driving force cannot be finely distributed on an intermediate μ road (e.g., a wet asphalt road surface or the unpaved road), on a snow road of the road, or on an extremely low-μ road (e.g., a frozen road or on ice).
In case the road surface μ is near the switching threshold value of the two ABS corresponding modes, moreover, there arises another problem such a hunting or control under different modes despite the vehicle is running on the same a sudden change in the control from a normal run on a common road surface may occur and results in unstable control.
Among the various control modes of the driving-force distribution control, moreover, the acceleration corresponding control or the deceleration corresponding control, other than the ΔN control, belongs to either the controlled variable reducing or ON-OFF switching operation like that of the ΔN control. As a result, the fine reduction control matching the characteristics (i.e., the interfering degree to the control by the ABS) cannot be made and may raise a problem in the interference with the control by the ABS or the reduction in the control performance (e.g., the turning performances).

Driving-force distribution control device

Mitsubishi Jidosha Kogyo Kabushiki Kaisha


A packer assembly features one or more elements that preferably swell when in contact with well fluids and have a feature in them that responds to an applied load in a given direction by retaining such a boost force with a locking mechanism. A single element can have two such mechanisms that respond to applied forces from opposed directions. Friction force for adhering the element to the mandrel is enhanced with surface treatments between them that still allow the locking mechanisms to operate.

Packers and plugs are used downhole to isolate zones and to seal off part of or entire wells. There are many styles of packers on the market. Some are inflatable and others are mechanically set with a setting tool that creates relative movement to compress a sealing element into contact with a surrounding tubular. Generally, the length of such elements is reduced as the diameter is increased. Pressure is continued from the setting tool so as to build in a pressure into the sealing element when it is in contact with the surrounding tubular.
More recently, packers have been used that employ elements that respond to the surrounding well fluids and swell to form a seal. Many different materials have been disclosed as capable of having this feature and some designs have gone further to prevent swelling until the packer is close to the position where it will be set. These designs were still limited to the amount of swelling from the sealing element as far as the developed contact pressure against the surrounding tubular or wellbore. The amount of contact pressure is a factor in the ability to control the level of differential pressure. In some designs there were also issues of extrusion of the sealing element in a longitudinal direction as it swelled radially but no solutions were offered. A fairly comprehensive summation of the swelling packer art appears below:
I. References Showing a Removable Cover Over a Swelling Sleeve
                1) Application US 2004/0055760 A1
FIG. 2a shows a wrapping 110 over a swelling material 102. Paragraph 20 reveals the material 110 can be removed mechanically by cutting or chemically by dissolving or by using heat, time or stress or other ways known in the art. Barrier 110 is described in paragraph 21 as an isolation material until activation of the underlying material is desired. Mechanical expansion of the underlying pipe is also contemplated in a variety of techniques described in paragraph 24.                2) Application US 2004/0194971 A1
This reference discusses in paragraph 49 the use of water or alkali soluble polymeric covering so that the actuating agent can contact the elastomeric material lying below for the purpose of delaying swelling. One way to accomplish the delay is to require injection into the well of the material that will remove the covering. The delay in swelling gives time to position the tubular where needed before it is expanded. Multiple bands of swelling material are illustrated with the uppermost and lowermost acting as extrusion barriers.                3) Application US 2004/0118572 A1
In paragraph 37 of this reference it states that the protective layer 145 avoids premature swelling before the downhole destination is reached. The cover does not swell substantially when contacted by the activating agent but it is strong enough to resist tears or damage on delivery to the downhole location. When the downhole location is reached, pipe expansion breaks the covering 145 to expose swelling elastomers 140 to the activating agent. The protective layer can be Mylar or plastic.                4) U.S. Pat. No. 4,862,967
Here the packing element is an elastomer that is wrapped with an imperforate cover. The coating retards swelling until the packing element is actuated at which point the cover is "disrupted" and swelling of the underlying seal can begin in earnest, as reported in Column 7.                5) U.S. Pat. No. 6,845,322
This patent has many embodiments. The one in FIG. 26 is foam that is retained for run in and when the proper depth is reached expansion of the tubular breaks the retainer 272 to allow the foam to swell to its original dimension.                6) Application US 2004/0020662 A1
A permeable outer layer 10 covers the swelling layer 12 and has a higher resistance to swelling than the core swelling layer 12. Specific material choices are given in paragraphs 17 and 19. What happens to the cover 10 during swelling is not made clear but it presumably tears and fragments of it remain in the vicinity of the swelling seal.                7) U.S. Pat. No. 3,918,523
The swelling element is covered in treated burlap to delay swelling until the desired wellbore location is reached. The coating then dissolves of the burlap allowing fluid to go through the burlap to get to the swelling element 24 which expands and bursts the cover 20, as reported in the top of Column 8.                8) U.S. Pat. No. 4,612,985
A seal stack to be inserted in a seal bore of a downhole tool is covered by a sleeve shearably mounted to a mandrel. The sleeve is stopped ahead of the seal bore as the seal first become unconstrained just as they are advanced into the seal bore.
II. References Showing a Swelling Material under an Impervious Sleeve
                1) Application US 2005/0110217
An inflatable packer is filled with material that swells when a swelling agent is introduced to it.                2) U.S. Pat. No. 6,073,692
A packer has a fluted mandrel and is covered by a sealing element. Hardening ingredients are kept apart from each other for run in. Thereafter, the mandrel is expanded to a circular cross section and the ingredients below the outer sleeve mix and harden. Swelling does not necessarily result.                3) U.S. Pat. No. 6,834,725
FIG. 3b shows a swelling component 230 under a sealing element 220 so that upon tubular expansion with swage 175 the plugs 210 are knocked off allowing activating fluid to reach the swelling material 230 under the cover of the sealing material 220.                4) U.S. Pat. No. 5,048,605
A water expandable material is wrapped in overlapping Kevlar sheets. Expansion from below partially unravels the Kevlar until it contacts the borehole wall.                5) U.S. Pat. No. 5,195,583
Clay is covered in rubber and a passage leading from the annular space allows well fluid behind the rubber to let the clay swell under the rubber.                6) Japan Application 07-334115
Water is stored adjacent a swelling material and is allowed to intermingle with the swelling material under a sheath 16.
III. References Which Show an Exposed Sealing Element that Swells on Insertion
                1) U.S. Pat. No. 6,848,505
An exposed rubber sleeve swells when introduced downhole. The tubing or casing can also be expanded with a swage.                2) PCT Application WO 2004/018836 A1
A porous sleeve over a perforated pipe swells when introduced to well fluids. The base pipe is expanded downhole.                3) U.S. Pat. No. 4,137,970
A swelling material 16 around a pipe is introduced into the wellbore and swells to seal the wellbore.                4) US Application US 2004/0261990
Alternating exposed rings that respond to water or well fluids are provided for zone isolation regardless of whether the well is on production or is producing water.                5) Japan Application 03-166,459
A sandwich of slower swelling rings surrounds a faster swelling ring. The slower swelling ring swells in hours while the surrounding faster swelling rings do so in minutes.                6) Japan Application 10-235,996
Sequential swelling from rings below to rings above trapping water in between appears to be what happens from a hard to read literal English translation from Japanese.                7) U.S. Pat. No. 4,919,989 and 4,936,386
Bentonite clay rings are dropped downhole and swell to seal the annular space, in these two related patents.                8) US Application US 2005/009363 A1
Base pipe openings are plugged with a material that disintegrates under exposure to well fluids and temperatures and produces a product that removes filter cake from the screen.                9) U.S. Pat. No. 6,854,522
FIG. 10 of this patent has two materials that are allowed to mix because of tubular expansion between sealing elements that contain the combined chemicals until they set up.                10) US Application US 2005/0067170 A1
Shape memory foam is configured small for a run in dimension and then run in and allowed to assume its former shape using a temperature stimulus.
IV. Reference that Shows Power Assist Actuated Downhole to Set a Seal
                1) U.S. Pat. No. 6,854,522
This patent employs downhole tubular expansion to release potential energy that sets a sleeve or inflates a bladder. It also combines setting a seal in part with tubular expansion and in part by rotation or by bringing slidably mounted elements toward each other. FIGS. 3, 4, 17-19, 21-25, 27 and 36-37 are illustrative of these general concepts.
The various concepts in U.S. Pat. No. 6,854,522 depend on tubular expansion to release a stored force which then sets a material to swelling. As noted in the FIG. 10 embodiment there are end seals that are driven into sealing mode by tubular expansion and keep the swelling material between them as a seal is formed triggered by the initial expansion of the tubular.
What has been lacking is a technique for automatically capturing applied differential pressures to a set element, particularly when set by swelling in reaction to exposure to well fluids, and retaining that force in the element to retain or/and boost its sealing capabilities downhole. The present invention offers various embodiments that capture boost forces from differential loading in the uphole or downhole directions and various embodiments to accomplish such capture in a single element or multiple elements on a single or multiple mandrels. Those skilled in the art will more readily appreciate the scope of the invention from a review of the description of the preferred and alternative embodiments, the drawing and the claims that appear below and define the full scope of the invention.


A method of operating a direct current motor fan assembly is provided in which a motor controller operates to apply full power to kick-start a motor to overcome static forces. As soon as a sensor determines that the motor has begun to rotate, the motor controller changes the motor drive level from full power to a predetermined lower level to maintain a desired rotational speed.

It is common to use Pulse Width Modulation ("PWM") to control the speed of direct current, dc, motors that are utilized with fans in computer applications. Advantageously, PWM control provides for accurate motor speed control.
To reduce fan generated noise and also to reduce power consumption, most modern computers utilize fan controllers to respond to temperatures within the computer and to vary the speed of a fan to provide enough cooling to maintain a desired temperature.
Typically, the fan motor is not operated until such time as there is a need for cooling. It is desirable to be able to initially operate the fan at a low speed to provide cooling of slight temperature increases. However, the static friction of any motor is much higher than dynamic friction of the rotating motor. To assure quick starting of direct current fan motors, it is common to "kick-start" the motor by applying a dc current pulse of fixed time duration to get the rotor in motion and then switch to PWM signals that represent the desired motor rotational speed. The optimum period of the kick-start pulse is determined by the motor and the load inertia and is best determined experimentally as that which gives the most reliable starting performance. In many applications, the fan motor is run at full power for one second to assure that the static friction has been overcome and the motor is rotating.
The drawback to the kick-start is that fan is initially run at full speed and then slows down to the needed speed.
It is highly desirable to provide a motor controller arrangement that minimizes initial fan roar that occurs during timed kick-start operation.


Provided is a communication system including a transmitter and a receiver which carry out communication by establishing connection of their plurality of communication layers. The transmitter generates a connection request containing a command and data required for connecting a number of contiguously adjacent layers among the plurality of communication layers and transmits the connection request to the receiver. The receiver receives a connection request containing a command and data required for connecting a number of contiguously adjacent layers among the plurality of communication layers, extracts the command and data from the connection request, and establishes connection for the plurality of communication layers based on the command and data. In this way, the time taken to establish connection is reduced. Therefore, even when the connection is cut off during the data exchange, the connection can be established again without taking much time, allowing quick recovery of data exchange.

In recent years, picture quality of CCD (Charge Coupled Device), which is used in various mobile devices including a mobile phone, a digital camera, a digital video camera, and a PDA (Personal Digital Assistant), has increased, allowing easy image pick-up of digital image with high quality.
The image taken by a CCD is often stored in a storage medium, so as to be sent as an attachment file of an e-mail, transmitted as an image file via wired/wireless communication to be displayed in a different device, or printed on a paper to be handed from one to another. In this way, the image is used as shared data.
Wireless communication, particularly one using infrared light, is often used for data transfer in such various ways for sharing digital images. This communication method enables easy transfer of image files without physical connection or medium exchange from the mobile device to other display devices, a printing device, a recording device, other mobile devices, or to a personal computer.
Examples of the typical infrared communications using IrDA (Infrared Data Association) are described in the following Documents 1 through 5.    Document 1: Infrared Data Association Serial Infrared Link Access Protocol (IrLAP) Version 1.1 (Jun. 16, 1996)    Document 2: Infrared Data Association Serial Infrared Physical Layer Specification Version 1.4 (May 30, 2003)    Document 3: Infrared Data Association Link Management Protocol (IrLMP) Version 1.1 (Jun. 23, 1996)    Document 4: Infrared Data Association 'Tiny TP': A Flow-Control Mechanism for use with IrLMP Version 1.1 (Oct. 20, 1996)    Document 5: Infrared Data Association Object Exchange Protocol (OBEX) Version 1.3 (Jan. 3, 2003)
To make the communication more flexible, a conventional communication method using IrDA or wireless LAN strictly defines a data link layer (or link layer), a transport layer, an application layer etc., and carries out negotiations, retransmission etc. in each layer. Further, in the negotiation for establishing connection, the IrDA-D1.1, which generally performs communication with a large number of terminals, focuses on secure connection for all terminals, thereby requiring many sequences. In addition to this, confirmation of transmission in the link layer or in the MAC layer, which is a part of the link layer, is carried out on the packet basis in the IrDA-D1.1. Note that, a personal computer (PC) carries out plural-transmission, while the all other devices mostly carry out single-transmission.
In spite of the flexibility for realizing various applications, those rigorous communication layers are defined through a complicated procedure, thereby increasing the overhead required for communication. The complicated procedure, which results from rigorous separation of layers, particularly causes an increase of communication overhead. Moreover, though the confirmation of retransmission for each packet helps to increase communication reliability, it also decreases communication speed.
The connection overhead can be ignored in a long time communication, but it becomes a serious problem if the data is transferred in a short time. The rigorous retransmission also decreases communication efficiency. Particularly, when a person carries out operation for instantly transmitting data, it is sometimes preferable that the operation (communication) is completed in a short time, and the person can carry out retransmission if the transmission fails. For example, when an infrared remote controller of TV or the like failed to receive a command for changing the channel, and therefore the TV did not carry out the command, the user may operate to reissue the command for channel change.
There are many advantages in the conventional method of using strictly-separated layers, establishing connection for each layer, and carrying out retransmission on the packet basis. Therefore, by adding a function of changing communication procedure according to communication condition, application, and/or user's instruction, more flexible communication is realized.
The following will explain an existing IrDA protocol as a prior art of the present invention.
Since the infrared light used for infrared communication such as IrDA has directivity, a shield between the devices will completely disable data transfer. However, if there is no shield between the devices, high-speed data transfer is possible.
IrDA is broken into Very Fast IR (VFIR) with a maximum speed of 16 Mbps, Fast IR (FIR) with a maximum speed of 4 Mbps, and SIR (Serial Infra Red) with a maximum speed of 115.2 kbps. However, in commercially available products, the maximum speed is up to 4 Mbps.
FIG. 27 shows a schematic procedure of establishment of data transfer state through the IrDA standard, which is one of standards of infrared communication. In this example, "establishment of data transfer" means establishment of a state in which the system becomes capable of data transfer of target images, documents etc.
A first station serves to look for the other party at the beginning of transmission. That is, the first station requires establishment of data transfer state and outputs a "station search command (XID command)". On the other hand, a second station serves to accept the request and outputs a "station search response (XID response). A request (order) from the first station to the second station is called a command, and a reply from the second station to the first station is called a response.
The XID command serves to look for a potential second station within a certain distance in which the first station is capable of transmission. The slot numbers denote ascending numbers sequentially put on the commands.
After receiving the XID command, the second station outputs the XID response, that is a "station search response, so as to notify the first station of its existence. The first station outputs a predetermined number of XID commands, and then outputs the final XID command labeled with the slot number 255. That is, the command with the slot number 255 is the final command.
Next, the first station notifies the second station of the setting values required for communication, such as data size, using a SNRM command. The second station receives the command and carries out comparison between the received setting value and its own setting value, and then transmits a UA response to the second station so as to notify an allowable value.
The following more specifically describes establishment of data transmission state.
In IrDA standard, the number of packets of XID command transmitted from the first station is often selected from 1, 6, 8, or 15. As shown in FIG. 27, when 8 packets of XID command is transmitted each time, the 1st to 8th packets are given slot numbers from 0 to 7. Then after outputting the 8 commands, the final XID command with the slot number of 255 so that the receiving end will notify that it is the final packet. That is, if the predetermined number is 8, 9 XID commands are required. Then, after 500 m seconds since the final packet is sent, the 1st through 8th packets are transmitted again. These packets are transmitted with a time interval of 25-85 m seconds.
The second station does not always output the XID response immediately after receiving the XID command, but outputs the response after receiving a packet with an arbitrary (a random value) slot number. For example, when 8 packets of XID command is transmitted each time, the second station arbitrarily determines whether it outputs the XID response after receiving the 1st packet or after receiving the 8th packet. For example, in FIG. 27, the second station outputs the XID response after receiving the fourth packet (slot number=3).
According to SIR, IrDA standard specifies that the XID command and the XID response are transferred at 9600 bps. This is much slower than the transfer speed of data frame (described later), which is sent at 4 Mbps. Also, because of the transmission of plural XID commands, unreliability for immediate response, and the 500 ms blank period after 2 to 16 XID commands are sent, transmission/reception of the XID command and the XID response takes a longer time.
Through these processes, the search for the receiving end is completed, and the first and the second stations become ready to establish connection in data link layer.
After the search, the first and second stations exchange a SNRM command and an UA response in the data link layer. The SNRM command contains data required to set parameters for data communication, such as communication speed, upper limit of packet size, maximum time to hold the transmission right, allowable number of packets for continuous transmission, number of dummy pulse given to stabilize optical characteristic in 115 kbps or 9600 bps communication, minimum waiting time for transmission after the packets arrive from the other end, duration of disconnection state which occurs when the volume of the received packets is less than the default value, and plural different connection addresses given to the respective devices etc. With this process, the connection in the link layer is completed, and data transfer condition is satisfied.
After the data transfer condition is thus satisfied, the connection is also established in the upper layers. FIG. 27 shows a sequence of connection establishment in the network layer, transport layer, and session layer. This figure shows a state after the establishment is completed, and all processes are performed in the way of data exchange (by exchanging I flames (described later)).
Conventionally, the transmission through IrDA standard can be performed at 4 Mbps when a high-speed communication mode is applied, however, the waveform in transmission/reception is specified as 4 PPM mode. FIG. 29 shows a relation between data and data pulse in the 4 PPM mode. As shown in the figure, (1), (2), (3) and (4) express 00, 01, 10 and 11, respectively, that is, a data pulse of each of four 125 ns periods making up a 500 ns period expresses different 2-bit information depending on where in the time period it is placed.
Further, in IrDA standard, transmission is performed on a frame basis. FIG. 30 shows a frame of IrDA standard, which is constituted of a preamble field, a start flag, an address field, a control field, a data field, a FCS, and a stop flag. Among these, the preamble field is used for generation of reception clock which is used in a reception circuit of the device in the receiving end. Further, the FCS includes a code for error detection, for example, an error detection code or an error correction code.
Further, there are various kinds of frames, such as an I (Information) frame for information transfer, an S (Supervisory) frame for supervision/control of communication, or a U (Unnumbered) frame for connection or shutdown of communication. The information for identifying those I, S U frames is contained in the control field.
Since data transmission cannot be completed within 1 frame in most cases, the data is divided into plural I frames. Each of I frames contains the main data (data to be transmitted) in the data field, and is given a sequence number by which any omission of data can be found. With this arrangement, highly-reliable communication is realized. The S frame has no data field for containing data, and is used for transmission of notification of condition, such as establishment of communication, or a busy state, or used for a request for retransmission or the like. The U flame is called a non-numerical frame as it has no sequence number like those of the I frames. The U frame is used for setting of communication mode, report of response and irregular condition, or establishment of data link.
FIG. 31 is a sequence diagram showing general procedure of the foregoing communication mode. The A station transmits SNRM frame to the B station so as to request establishment of data transfer state. After receiving the SNRM frame, the B station outputs the DM frame when communication is not possible, and outputs a UA flame indicating acceptance of the request when communication is possible. The SNRM frame, DM frame, UA frame are all U frames. When the station B transmits the UA frame, data transmission state is established in both A and B stations, and data transfer becomes ready to be performed.
In this example, the A station transmits data having been divided into I frames to the B station. First, the A station transmits the first data frame, a 0th I frame to the B station. The B station transmits a response frame (data transfer request frame) given a number "1" (next to "0") as a command indicating "transmit the first data". This response frame is a RR frame, one of the S frames. After confirming the response frame from the B station, the A station transmits the first I frame containing divided frames. This procedure is repeated for a required times, thereby improving communication accuracy in communication of a plurality of I frames.
Alternatively, it is also possible to use a data transfer method in which a plurality of 1 frames are serially transmitted from the A station. In this case, when all I frames are transmitted, the station A transmits a DISC frame (U frame), indicating a command of shutdown, to the B station, so as to terminate the connection. Then, when the B station transmits a UA frame (U frame) indicating acceptance for shutdown, the communication is shut off. Further, in the case of communication error or the like in either of the A or B station, the station transmits a request for shutdown, thus the communication is shut off.
In IrDA, wireless communication is performed in the manner above. However, due to the characteristics of light, when the infrared interface between the communication devices exceeds a certain angle (±15 in IrDA standard) or exceeds a certain distance (20 cm or 1 m in IrDA), the communication fails in process of transmission even when a highly reliable communication method is employed.
This is because search for station and information exchange takes some time in the IrDA transmission, requiring frequent confirmation of data transmission/reception between the transmitter and the reception device, thereby decreasing transfer efficiency. As a result, the communication is more likely to fail in process of transmission.
For example, Japanese Laid-Open Patent Application Tokukai 2004-509527 (published on Mar. 25, 2004) discloses a method of transferring a file from one device to another via wireless communication so as to displaying the file in a device in the receiving end, but the same problem occurs when infrared light is used.

Transmitter, receiver, communication system, communication method, non-transitory computer readable medium


The present invention relates to a homeopathic formulation comprising dilutions of Arnica, Calendula, Echinacea, Hypericum, Silver, Sulfur, Thiosinaminum, Urtica, and methods for treating pain, inflammation, scar tissue, itching/pruritus and infection using same.

Historically aches, pains and bodily discomfort have engaged people, as well as their animals and pets, for thousands of years. Yet, when one looks at the pain remediation marketplace of today, it becomes apparent that no one product has as yet been developed that has the ability to offer one hundred percent relief, particularly pain relief to any one individual. As such, people today desiring to reduce or stop their suffering from pain/aches and/or pruritus will often attempt to seek relief from the use of one or more drugs from the category of non-prescription and/or prescription drugs that are in fairly large abundance worldwide, with hundreds from which to choose.
Unfortunately many of these drugs have unwanted side effects that can often compromise health and well-being; they include overdosing, severe allergic and/or hypersensitivity reactions, unsightly rashes, moderate to severe breathing difficulties, suicidal thoughts, blurry vision, gastric upset, and liver dysfunction. These drugs can also cause death, even when drug instructions are followed assiduously. Clearly there is a need for a safer if not a better alternative.

Compositions and methods for treatment of pain


A system for increasing lidar sensor coverage for use by a vehicle is described herein. The system includes a two lidar sensors oriented to emit light beams toward a surface proximate the vehicle. The system also includes at least one mirror associated with each lidar sensor configured to reflect light beams emitted away from the surface. The at least one mirror reflects the light beams toward the surface, thereby increasing lidar sensor coverage associated with the respective lidar sensor. The lidar sensors receive lidar returns, either directly from the surface or reflected off the mirror and may generate sensor data associated with an area proximate the vehicle. A vehicle computing system controls the vehicle based in part on the sensor data.

Autonomous vehicles are becoming increasingly more common in numerous industries, such as construction, mining, rail, forestry, agriculture, waste management, and the like. Autonomous vehicles include multiple sensor systems configured to detect objects proximate to the vehicles. A vehicle computing system receives sensor data from the sensor systems and determine an action for the vehicle to take. For example, an autonomous vehicle operating in a construction zone detects an object proximate the vehicle, and determines to slow down or change course, such as to yield to the object. In such an example, the autonomous vehicle is configured to maximize the field of vision around the machine.
Autonomous vehicles often include lidar sensors to monitor an area proximate the vehicle. Many lidar sensors designed for use on autonomous vehicles emit laser pulses (e.g., light beams) in a 360-degree pattern around the lidar sensor and detect objects based on pulse returns after reflecting off an object. To detect objects in the area proximate the vehicle, oftentimes lidar sensors are angled to emit laser pulses toward the ground in the area proximate the vehicle. This angled orientation of a lidar sensor results in a substantial portion (e.g., 45%, 50%, etc.) of the 360-degree pattern of laser pulses emanating toward the sky (e.g., unused). Due in part to the angled orientation to capture the environment proximate the vehicle, in order to effectively monitor the area, the autonomous vehicle requires a plurality of sensors situated around the vehicle. In at least one example, an autonomous vehicle includes four lidar sensors to monitor the area in front, behind, and on each side of the vehicle. However, the plurality of lidar sensors and increased computing complexity in processing data from each sensor renders the sensor system prohibitively expensive in many industries.
Example embodiments of the present disclosure are directed toward improving upon the lidar sensor coverage described above.

Systems and methods for increasing lidar sensor coverage


A transducer comprising a pair of spaced magnets at least partially forming a tunnel having a central axis. A coil having a first and a second side wall and an upper and a lower wall at least partially forms the tunnel. A reed having a central portion extends through the tunnel. The reed has a stationary end, a deflection end, and a tip portion which lies at least partially between the magnets, wherein the reed is mounted for deflection towards or away from the respective magnets.

It is known that transducers include a coil with a first air gap or tunnel, magnetic members, such as spaced apart permanent magnets, having a second air gap or tunnel, and a reed armature. The first and second air gaps are generally aligned, with the armature reed extending through the first and second air gaps.
The arrangement is such that when the moving part of the reed shifts in one direction or another away from a centralized position between the two poles, the magnetic flux is caused to flow in one direction or the other along the reed and hence through the coil. The reed is attached to a diaphragm and in this way the vibrations of the diaphragm caused by received sound are converted into corresponding currents in the coil or vice versa. If the transducer experiences a shock e.g., from being dropped, the reed can be easily damaged due to over deflection or unwanted deflection in the horizontal and/or vertical directions. In addition, the tip portion of the reed may strike the magnet with considerable force on the upper or lower side walls of the tunnel formed within the coil. Reference can be made to U.S. Pat. No. 5,647,013 for one such arrangement.
To reduce and prevent unwanted deflection of the armature's reed, the tunnel of the transducer can be tapered (inwardly or outwardly) from the fixed or stationary end of the armature toward the deflection end of the reed. In addition, a contact point can extend into the tunnel to reduce or prevent unwanted horizontal deflection of the armature reed. These previous techniques still require the reed to contact the surface of the tunnel and this contact can cause damage to the reed.
This invention is designed to prevent these and other problems.

Electro-acoustic transducer with resistance to shock-waves


An aeroplane comprising a fuselage elongated in a longitudinal direction of the aeroplane is provided. The aeroplane includes a wing attached to the fuselage in a midsection of said fuselage in the longitudinal direction, such that part of the fuselage extends forward of the wing toward a front extremity of the fuselage, and part of the fuselage extends from the rear of the wing toward a rear extremity of the fuselage. A rear fuselage section includes at least one engine attached to the fuselage and located to the rear of the wing. The one or more engines attached to the fuselage are attached in a rear position such that only parts of the aeroplane located in a projection space of the one or more engines attached to the fuselage and the rear fuselage does not include any aerodynamic surfaces intended to assure stability and/or aerodynamic control of the aeroplane.

Nowadays in the field of aircraft, an architecture comprising an elongated fuselage in which passengers or cargo are transported and a wing attached to the fuselage in a central portion of the fuselage between the front extremity of the fuselage and the rear extremity of the fuselage is widely used and may be considered conventional.
This conventional architecture is used widely because of the advantages it offers both in terms of both aerodynamics and in operational terms for the aeroplane.
For aerodynamic purposes, the elongated fuselage provides a usable volume that may be substantial while retaining a reduced midship frame, while the aspect ratio may be relatively large, both of these factors helping to limit aerodynamic drag.
Operationally, the elongated shape of the fuselage means that a sufficient number of exits can easily be provided to enable rapid passenger embarkation and disembarkation operations and still ensure the number of emergency exits required according to regulations, since the length on the fuselage occupied by the wing arrangement is moderate relative to the length of the fuselage itself and therefore not obstructive.
Although this conventional architecture is very frequently used in the field of transport aircraft, it still comprises two quite distinct families in respect of the propulsion engines.
In the first family, the propulsion engines are mounted under the wing, most often two or four engines are disposed symmetrically relative to the fuselage, as with the Airbus A320 (two engines) or A380 (four engines) for example, and in a second family the propulsion engines are mounted at the rear and on either side of the fuselage, as on the SE210 Caravelle aeroplane, for example, and possibly inside or above the fuselage.
In order to deliver the thrust required by transport aircraft, as soon as the mass of the aeroplane exceeds a few tens of tons, the engines used are turbojet engines or turboprop engines having turbines as power generators, and which most often entail the use of blowers with a large diameter or propellers with varying degrees of complexity.
In order to contain debris, which may arise during the operation of the engine, designers occasionally resort to shielding, which is fitted around ducted rotating parts such as blowers, but when the energy involved is considerable this method of containing engine debris becomes impractical, that is to say the additional weight becomes unacceptable.
In order to prevent sensitive parts of the aeroplane from being damaged, for example the parts containing flight controls or vital structures, the engines are located in such positions that the possible trajectories of the engine debris cannot bring it into contact with said sensitive parts or cause damage that would endanger the aeroplane.
In the case of engines mounted at the rear of the aeroplane, the problem is more difficult to address due to the concentration of flight controls in the rear section of the fuselage, which is relatively small and is also where the aeroplane empennages are located in conventional architectures, the horizontal and vertical stabilising empennages.
Nowadays, designers have overcome the problems of installing rear jet engines by a positioning, particularly a longitudinal positioning of the jet engines that is limiting but possible due to the relatively small dimensions of said jet engines, and/or because the energy of debris that might be associated with the engine is limited, and by multiplying the flight control systems.
Unfortunately, the appearance for various reasons of engines that have rotating parts with larger diameters, particularly engines with unducted counter-rotating propellers, which in some respects seem to be simpler to install at the rear of the fuselage than under the wing, simply reintroduces the problem of dealing with debris.
The designs for installing such engines consist in known manner of replacing the conventional jet engines with these engines by adapting the support pylons whose function is to ensure a distance between the axis and the engine according to the diameter of the rotating parts, as in U.S. Pat. No. 5,443,229, for example, but these solutions are able to simply contain the consequences of the breakup of a rotating part of the engine, which is likely to cause damage to the aeroplane flight control systems, particularly the rear empennages or a section of the structure of the empennages or the rear fuselage, damage that must then be taken into account at the design stage.
The implementation of such solutions is therefore very expensive and complex, and is the source of various less than optimal conditions, particularly in terms of weight and aerodynamics.
In addition, other objects, desirable features and characteristics will become apparent from the subsequent summary and detailed description, and the appended claims, taken in conjunction with the accompanying drawings and this background.

Airplane having a rear propulsion system


The present invention relates to a method for producing an anionic surfactant granule, which includes granulating an anionic surfactant powder in a granulator having an agitating blade, while adding water, at a temperature of the granule being higher by 0.5 to 30° C. than a boiling point of water under a pressure of the inside of the granulator.

Anionic surfactants are mixed with other surfactant or a builder to be used in laundry detergents and kitchen detergents, foaming agents for toothpaste, emulsifiers for medicines and cosmetics, and other detergents.
There have been known forms of an anionic surfactant, including granule produced by drying an aqueous solution, slurry, or paste of an anionic surfactant (hereinafter, simply referred to as the aqueous solution group of anionic surfactant), and products therefrom such as powder, needle, noodle, and flake. A conventional method for producing an anionic surfactant granule includes drying an aqueous solution etc. of an anionic surfactant as a starting material to remove water, and then optionally processing a dried product by a secondary processing such as crushing and granulating.
Conventional methods for producing an anionic surfactant granule include, for example, spray-drying such as a method of spray-drying a low concentration slurry containing water in an amount of 60 to 70% by weight (JP-A55-69698 and JP-A53-39037) and a method of spray-drying a high concentration slurry of an alkylsulfate having a solid content of 60 to 80% by weight (JP-A54-106428). JP-A2-222498 discloses a method of drying a high concentration paste raw material for detergent containing water in an amount of 20 to 35% by weight with a vacuum thin film dryer.

Method for producing anionic surfactant granule


In an environment in which storages are intensively collected, many unused areas are generated and no storage resources can be efficiently used as a storage pool. The capacity utilization (data capacity) of a storage device (volume) allocated to a computer is obtained and future capacity utilization is estimated from a change in the data capacity. The capacity of the storage device is compared with upper limit securing capacity and lower limit securing capacity values indicating the upper and lower limits of appropriate allocating capacity calculated from this estimated capacity utilization. When the capacity of the storage device is greater than the upper limit securing capacity, a different storage device, having at least the lower limit securing capacity and no more than the upper limit securing capacity, is allocated from the storage pool, and the storage device allocated previously is collected in the storage pool.

The present invention relates to a method for centrally managing plural storage devices.
In recent years, a technique for connecting a computer and plural storage devices by way of a network (storage area network (SAN)) and centrally managing the plural storage devices connected to the SAN has been proposed.
As a method for managing plural storage devices connected to a SAN, there is a technique for centrally managing a storage device (volume), among the plural storage devices connected to the SAN, as a storage pool, and efficiently using the memory capacity of the storage device connected to the SAN.
In a conventional system, capacity is added, by on-demand from a storage pool, when the volume capacity become short due to insufficient estimation of the capacity being used, at an insufficient time point. (For example, see (Patent Literature 1) JP-A-2002-222061 at p. 9, FIG. 11).
It is difficult to accurately estimate the capacity utilization in advance and to allocate the needed volume. In the past, when the capacity utilization (data capacity) was not increased as estimated, an unused storage area would remain and never be used.
In an environment in which storage devices are intensively consolidated and many volumes exist, it will happen that many unused and useless storage areas remain unused. Since such unused storage areas in volumes are unused, but cannot be utilized as the storage pool, the storage resources can not be efficiently used.

Managing method for optimizing capacity of storage


A transfer circuit includes a plurality of cascaded latch circuits. Two consecutive latch circuits in the transfer circuit complementarily enter a latching state and a transparent state in response to the applied clock signal, and data/a signal is transferred through the transfer circuit in response to the clock signal. A clock control circuit is provided for controlling an operation of each of the latch circuits. The clock control circuit detects that the latch circuit in a next stage of the corresponding latch circuit enters the latching state to permits transfer of the signal/data of the corresponding latch circuit to the subsequent stage in accordance with the corresponding clock signal. It is possible to prevent the data/signal from being transferred while the latch circuit at the next stage is in the transparent state to accurately transfer the data/signal. A clock synchronous data transfer and processing device reliably preventing racing is implemented with a simple circuit configuration.

1. Field of the Invention
The present invention relates to a synchronous signal transfer and processing device for transferring a signal/data in accordance with a clock signal. More specifically, the present invention relates to a configuration for avoiding racing on the signal transfer path of the synchronous type signal transfer and processing device.
2. Description of the Background Art
A clock synchronous processing scheme of transferring and processing a signal synchronously with a clock signal is normally employed for high speed signal/data processing. According to this synchronous processing scheme, data/signal is transferred and processed by controlling the operation state of a latch circuit or a flip-flop circuit for holding the data/signal in synchronization with a clock signal.
The synchronous processing scheme for transferring and processing a signal synchronously with a clock signal allows a signal/data to be processed in a pipeline fashion, achieving high-speed processing. In addition, since signal/data (to be simply referred to as "data" hereinafter) processing timing and data transfer timing are determined by a clock signal, a margin for processing start timing can be decreased and high-speed data processing can be implemented. Further, since a data processing cycle is determined by a clock signal cycle, high-speed processing is achieved.
According to the above-stated clock synchronous processing scheme, clock signals as same in timing and less different in phase as possible should be transferred to many latch circuits or flip-flop circuits, in order to allow these latch/flip-flop circuits to operate at the same timing. For that reason, various clock distribution schemes are employed to transmit a main clock signal from a clock input buffer or the like with a clock skew as small as possible. These clock distribution schemes include a clock tree scheme for transmitting clock signals to the respective latch or flip-flop circuits through clock branch paths arranged in a tree-like form, a clock mesh scheme for transmitting a main clock signal through clock distribution paths arranged in a meshed form, a fishbone scheme for providing a branch path on a main clock transmit line extending almost linearly, driving this branch path by a clock driver and transferring clock signals to the respective latch or flip-flop circuits and the like.
FIG. 28 shows an example of the configuration of a conventional synchronous data processing and transfer device. In FIG. 28, the clock tree scheme is employed as the clock distribution scheme by way of example.
In FIG. 28, a clock distribution system includes a clock driver DR0 for buffering a main clock signal MCLK, and clock drivers (repeaters) DR1a to DR1c, arranged at predetermined intervals on a clock distribution path LP0 coupled to a clock distribution node ND0, for buffering clock signals on clock distribution path LP0, respectively. Clock drivers DR1a to DR1c transmit the clock signals to clock branch paths LP1a to LP1c coupled to clock distribution nodes ND1a to ND1c, respectively.
Parasitic capacitance Ca and parasitic resistance Ra exist on clock distribution path LP0. In addition, parasitic resistance Rb and parasitic capacitance Cb due to interconnection line capacitance and resistance also exist on clock transmission lines driven by clock drivers DR1a to DR1c, respectively.
In these clock distribution routes, main clock signal MCLK from clock driver DR0 is transmitted through clock distribution paths arranged in a tree-like form. The distribution paths arranged in a tree-like form are arranged symmetrically with respect to clock driver DR0 transmitting main clock signal MCLK so that the paths transmitting the clock signals are made equal in delay time. On each respective branch path of this clock tree, a signal propagation path between a clock terminating node of the final stage and a main cock signal input node is set to have as equal interconnection line delay as possible to make clock skews on respective clock terminating nodes as small as possible.
Signal processing related circuitry includes latch circuits LTa to LTc arranged corresponding to clock drivers DR1a to DR1c, respectively. Latch circuits LTa and LTc have the same configuration and operate in a common phase. Latch circuit LTb operates in a reversed phase to latch circuits LTa and LTc. Specifically, each of latch circuits LTa and LTc includes an inverter IVa that receives clock signal CLK from the corresponding clock driver, a transfer gate TXa that is rendered conductive, when clock signal CLK from the corresponding clock driver is at H level, to pass a signal received from the circuit in a preceding stage, an inverter IVb that receives the signal transmitted through transfer gate TXa, an inverter IVc that inverts the output signal of inverter IVb and transmits the inverted output signal to the circuit at the next stage, and a tri-state inverter TVa that is made active, when the output signal of inverter IVa is at H level, to invert the output signal of inverter IVb for transmission to the input node of inverter IVb.
Latch circuit LTb includes an inverter IV1 which receives clock signal CLK from corresponding clock driver DR1b, a transfer gate TXb which is made conductive, when the output signal of inverter IV1 is at H level, to pass a signal transmitted from the circuit in a preceding stage, an inverter IV2 which receives the signal transmitted through transfer gate TXb, an inverter IV3 which inverts the output signal of inverter IV2 and transmits the inverted output signal to the circuit at the next stage, and a tri-state inverter TV1 which is made active, when clock signal CLK from corresponding clock driver DR1b is at H level, to invert the output signal of inverter IV2 for transmission to the input node of inverter IV2.
A delay circuit DLa is interposed between latch circuits LTa and LTb. A delay circuit DLb is interposed between latch circuits LTb and LTc. These delay circuits DLa and DLb are provided for preventing data to be latched from being rewritten by an applied signal if latch circuits LTa to LTc simultaneously turn into a transparent state due to a clock skew.
As shown in FIG. 28, on the clock distribution path, clock drivers DR1a to DR1c are arranged corresponding to latch circuits LTa to LTc, respectively so that clock transmission paths from main clock signal MCLK to respective latch circuits LTa to LTc have same a signal transmission delay as possible. It is intended to make the operation timing of each of latch circuits LTa to LTc as same as possible to achieve synchronous data transfer.
In this arrangement, when transfer gates TXa turn conductive in respective latch circuits LTa and LTc and latch circuits LTa and LTc turn into a transparent state of passing an applied signal, transfer gate TXb of latch circuit LTb is in a nonconductive state, and latch circuit LTb is in a latching state. Therefore, the output data of latch circuit LTa is not captured by latch circuit LTb and latch circuit LTc transmits latch data of latch circuit LTb to the circuit at the next stage. On the other hand, when transfer gates TXa of respective latch circuits LTa and LTc are nonconductive and latch circuits LTa and LTc are in a latching state, transfer gate TXb of latch circuit LTb is in a conductive state and latch circuit LTb is in a transparent state. Therefore, latch circuit LTb transmits the latched data of latch circuit LTa to latch circuit LTc at the next stage.
As shown in FIG. 28, by alternately setting latch circuits LTa to LTc in the transparent state and latching state, it is possible to sequentially transfer data from latch circuits LTa to LTc synchronously with clock signal CLK.
However, line parasitic resistance and line parasitic capacitance exist on each of clock distribution paths LP0 to LP1c shown in FIG. 28. If the lengths of the clock transmission paths are equal for all latch circuits LTa to LTc, the clock transmission paths for latch circuits LTa to LTc have the same clock propagation delay and a clock skew is hardly caused. However, the clock distribution paths differ in interconnection length, and therefore in parasitic resistance and parasitic capacitance, according to the arranged positions of latch circuits LTa to LTc. Thus, a clock skew occurs in clock signals CLK transmitted from clock drivers DR1a to DR1c to respective latch circuits LTa to LTc.
FIG. 29 is a timing chart representing the operations of the circuit device shown in FIG. 28 when a clock skew occurs. In FIG. 29, a clock skew occurs in clock signal CLK arriving at latch circuits LTa to LTc due to the difference in interconnection line delay. FIG. 29 shows an example of a state in which clock signal CLK arrives at the node (clock input node) NA of transfer gate TXa of latch circuit LTa earliest and arrives at the control node NB of transfer gate TXb of latch circuit LTc latest.
If a clock skew occurs as shown in FIG. 29, a period, in which both the control signals at control nodes (clock input nodes) NA and NB of latch circuits LTa and LTb become H level, is caused. If latch circuit LTa takes in an applied signal synchronously with the rise of clock signal CLK for transference to the circuit at the next stage, when transfer time for transferring data from latch circuit LTa to latch circuit LTb is shorter than an overlap period in which both the control signals at clock input nodes NA and NB are at H level, data to be latched by latch circuit LTb is rewritten by the data taken in by latch circuit LTa, and an erroneous rewriting occurs. This malfunction is generated due to the competition between the clock signal and the data, and therefore, it is referred to as "racing".
To prevent such racing, delay circuits DLa and DLb are arranged as shown in FIG. 28. By arranging delay circuit DLa, time required for transmitting data DA captured by latch circuit LTa to the input of latch circuit LTb is made longer than an overlap period TS as shown in FIG. 30. In this arrangement, even if latch circuits LTa and LTb both turn into a transparent state, the latched data of latch circuit LTb is not rewritten by new data DA, making it possible to avoid racing.
However, if delay circuits DLa and DLb are arranged on the data transmission path, the number of components of logical gates disadvantageously increases and a layout area and power dissipation disadvantageously increases.
Further, the following procedure is required in an actual analysis of a circuit operation. Timing verification is performed for each signal transmission path. The clock timing of each latch circuit is adjusted based on the result of the timing verification. Therefore, it is necessary to interpose delay circuits, taking into account an optimum delay amount which do not influence the setup times of the latch circuits.
Specifically, as shown in FIG. 31, if data DA is transferred, valid data is transferred and latched by, for example, latch circuit LTa after clock signal CLK rises and then delay time TD of the delay circuit in the preceding stage passes. It is necessary to turn the latched data of latch circuit LTa into a definite state before clock signal CLK rises and latch circuit LTa enters a latching state. Time period in which this latched data is held in a definite state before the latch circuit enters a latching state is referred to as "setup time Tsu".
Accordingly, if the cycle time of clock signal CLK is determined, when delay time TD becomes longer, setup time Tsu becomes shorter. In this case, there is caused a probability that the data in the definite state cannot be latched and unascertained data is transferred to the latch circuit at the next stage, causing a malfunction. Therefore, if delay time TD is increased, the cycle time of clock signal CLK cannot be shortened, making it impossible to achieve high-speed operation.
A configuration aiming to prevent the above-stated racing issue and to decrease the number of components on signal transmission paths is disclosed in, for example, Japanese Patent Laid-Open No. 10-40692(1998).
FIG. 32 is a schematic block diagram showing a structure of a conventional synchronous transfer and processing device. In FIG. 32, cascaded flip-flops FFa to FFc of three stages are shown. Gate circuits AGa to AGc generating control signals are arranged corresponding to flip-flops FFa to FFc, respectively. Each of gate circuits AGa to AGc receives clock signal CLK and a control signal for the flip-flop at the next stage. Specifically, gate circuit AGa receives clock signal CLK and the output signal of gate circuit AGb. Gate circuit AGb receives clock signal CLK and the output signal of gate circuit AGc. Gate circuit AGc receives clock signal CLK and the output signal of a gate circuit provided corresponding to a flip-flop at the next stage which is not shown. The clock signal may be transferred to respective flip-flops FFa to FFc through clock distribution circuitry or may be transferred from a common clock driver.
If a control signal applied to a clock input T from each of corresponding gate circuits AGa to AGc turns H level, each of flip-flops FFa to FFc enters into a latching state and outputs data taken in when the control signal is at L level. That is, if the control signal applied from each of corresponding gate circuits AGa to AGc is at L level, each of flip-flops FFa to FFc takes in data applied to an input D thereof and outputs the taken in data from an output Q.
FIG. 33 shows an example of the configuration of each of flip-flops FFa to FFc shown in FIG. 32. Since flip-flops FFa to FFc have the same configuration, the configuration of a flip-flop FF is representatively shown in FIG. 33. In FIG. 33, flip-flop FF includes an inverter IV 10 which inverts a control signal applied to clock input T, a transfer gate TX10 which is rendered conductive, when the output signal of inverter IV10 is at H level, to pass a signal applied to an input node D, an inverter IV11 which inverts the signal applied through transfer gate TX10, an inverter IV12 which inverts the output signal of inverter IV11, a tri-state inverter buffer IV 13 which is made active, when the signal applied to clock input node T is at the H level, to invert the output signal of inverter IV 11 for transmission to the input of inverter IV11, a transfer gate TX11 which is rendered conductive, when the control signal applied to clock input node T is at H level, to transmit the output signal of inverter IV12, an inverter IV14 which receives the signal applied through transfer gate TX11, an inverter IV 15 which inverts the output signal of inverter IV 14 for transmission to output node Q, and a tri-state inverter buffer IV 16 which is made active, when the output signal of inverter IV 10 is at H level, to invert the output signal of inverter IV14 for transmission to the input of inverter IV14.
Flip-flop FF shown in FIG. 33 consists of latch circuits cascaded in two stages. These latch circuits are alternately set in a latching state and in a transparent state. That is, when the control signal applied to clock input node T is at L level, transfer gate TX10 is rendered conductive, transfer gate TX11 turns nonconductive, and the data applied to input node T is inverted by inverter IV11 and transmitted to inverter IV12. In this state, tri-state inverter buffer IV13 is in an inactive state and in output high-impedance state. Therefore, the output signals of inverters IV11 and IV12 change according to the data applied to input node D. On the other hand, transfer gate TX11 is nonconductive and the data of output node Q does not change.
When the control signal applied to clock input node T attains H level, transfer gate TX10 turns nonconductive, transfer gate TX11 turns conductive and the signal taken in when the control signal is at L level is transmitted to output node Q through inverters IV14 and IV15. In this state, tri-state inverter buffer IV13 is also activated and the previously taken in data is latched by inverter IV11 and tri-state inverter buffer IV13. Therefore, flip-flop FF takes in the data applied to input node D when the control signal applied to clock input node T is at L level, latches the taken in data and outputs the captured data from output node Q when the control signal attains H level.
FIG. 34 is a timing chart representing the operations of the circuit device shown in FIG. 32. In FIG. 34, operations in the case where clock signal CLK applied to flip-flop FFc has the longest delay and clock signal CLK applied to flip-flop FFa has the shortest delay are shown for simplification of description.
When clock signal CLK is at L level, each of gate circuits AGa to AGc outputs a signal at an L level irrespectively of the state of the flip-flop at the next stage. When the control signal applied to clock input node T is at L level, each of flip-flops FFa to FFc takes in data applied to input node D, but the signal at output node Q does not change. When clock signal CLK applied to gate circuit AGc attains H level, the output data of flip-flop FFc changes, transfer gate TX10 connected to input node D of flip-flop FFc turns nonconductive and flip-flop FFc enters a latching state.
When the output signal of gate circuit AGc attains H level, since clock signal CLK is at H level, gate circuit AGb rises the control signal applied to clock input node T of flip-flop FFb to H level. Accordingly, the output data of flip-flop FFb changes and flip-flop FFb enters a latching state.
When the control signal outputted from gate circuit AGb rises to H level, the control signal outputted from gate circuit AGa attains H level, the output signal of flip-flop FFa changes, and flip-flop FFa enters a latching state.
In the circuit device shown in FIG. 32, therefore, after the flip-flop at the next stage enters a latching state, the output data of the flip-flop in the preceding stage changes, thereby preventing erroneous latching of data by the flip-flop at the next stage. That is, as shown in FIG. 32, new data is outputted to the flip-flop at the next stage after this flip-flop turns into a latching state, thereby preventing data from piercing through the flip-flops due to a clock skew as shown in FIG. 35. FIG. 35 shows operations in a case where clock signal CLK applied to flip-flop FFa leads in phase the clock signal CLK applied to flip-flop FFb. As shown in FIG. 35, if a clock skew occurs, when flip-flop FFa turns into a latching state in response to the rise of clock signal CLK, flip-flop FFb is in a signal taking-in state and takes in the output data of flip-flop FFa. Therefore, when clock signal CLK to flip-flop FFb rises, flip-flop FFb turns into a latching state and outputs the output data of flip-flop FFa within the current clock cycle of clock signal CLK. Therefore, data to be transferred after one clock cycle in a correct operation is outputted from flip-flops FFa and FFb in the same cycle, and a malfunction occurs.
It is intended to avoid such data piercing, using gate circuits AGa to AGc shown in FIG. 32.
However, where with the gate circuits shown in FIG. 32, the flip-flop at the next stage enters a latching state and then the corresponding latch circuit enters the latching state in accordance with clock signal CLK to change the output data of the flip-flop, the transmission path of this control signal sequentially propagates the control signal through a series of flip-flops.
It is now considered a data transmission path comprised of flip-flops FF0 to FFn as shown in FIG. 36. Gate circuits AG0 to AGn-1 are provided corresponding to flip-flops FF0 to FFn-1, respectively. Each of gate circuits AG0 to AGn-1 receives corresponding clock signal CLK and a control signal for the flip-flop at the next stage. Flip-flop FFn at the final stage is supplied only with clock signal CLK.
Consider a case where clock signal CLK applied to flip-flop FFn has the longest delay on the data transmission path shown in FIG. 36. In this case, after flip-flop FFn enters a latching state, flip-flop FFn-1 at a preceding stage of flip-flop FFn turns into a latching state and outputs an output signal. Accordingly, in order to set flip-flop FF0 in the first stage in a latching state and to change the output signal of flip-flop FF0, the transmission delays of gate circuits AG0 to AGn-1 are added to the delay time of clock signal CLK. As shown in FIG. 37, therefore, when clock signal CLK applied to flip-flop FFn in the final stage rises to H level after elapse of time Ti since clock signal applied to flip-flop FF0 in the first stage rises to H level, the output signal outputted from gate circuit GA0 attains H level after elapse of signal transmission delay time T2 through gate circuits AG0 to AGn-1. Consequently, the latch circuit in the output stage of flip-flop FF0 in the first stage is required to take in the latch data of the latch circuit in the input stage and transfers the taken-in data to flip-flop FF1 at the next stage within time period T3. However, the setup time of the latch circuit in the output stage of the flip-flop FF0 cannot be sufficiently ensured, with the result that data in an indefinite state may be outputted. If a logical processing circuit is interposed between flip-flops FF0 and FF1, in particular, the processing time of this logical processing circuit cannot be sufficiently secured, with the result that high-speed processing cannot be achieved.
Moreover, the latch time of each of flip-flops cannot be sufficiently secured, leading to a problem that the flip-flops may malfunction.

Synchronous signal transfer and processing device


The invention relates to the field of computer analysis of text documents. More specifically it relates to the field of artificially intelligent systems capable of analyzing responses to Request for Quotation (RFQ).

When a company submits a Request for Quotation to a number of potential suppliers, it is important not to spend too much time reviewing responses that do not satisfy requirements of the company submitting the RFQ. In most cases when responses to RFQ's come into a company through the mail persons at that company have to review and sort the responses and usually write up a summary of whether the response is acceptable to the company. In addition it is desirable to be able to quickly evaluate potential responses to an RFQ in an efficient and accurate manner.
With the invention of the Internet more and more companies are sending out RFQ's over the Internet. Companies are then responding over the Internet to the company with a quotation. In order to process these quotations efficiently the present invention provides an artificial intelligent system capable of analyzing quotes and extracting information relating to the RFQ.


Methods and apparatus for a frequency selective limiter (FSL) having a magnetic material substrate that tapers in thickness and supports a transmission line that has segments and bends. The segments, which differ in width and are substantially parallel to each other, such that each segment traverses the substrate on a constant thickness of the substrate.

As is known in the art, a frequency selective limiter (FSL) is a nonlinear passive device that strongly attenuates radio-frequency (RF) or microwave signals, both of which will be referred to as RF signals in the following, above a predetermined threshold power level, while passing signals below the threshold power level with only modest loss called insertion loss. One feature of the FSL is the frequency selective nature of the high-power limiting: low power signals close in frequency to the limited signals are substantially unaffected (i.e., the FSL only attenuates such signals by the insertion loss).
A typical implementation of an FSL includes a stripline transmission-line structure using two layers of ferrite material, typically yttrium iron garnet (YIG), disposed about the stripline, with the stripline having a fixed length and a fixed width along the length of the FSL, with a constant magnetic field applied to the ferrite. Such structures are relatively simple to fabricate and provide adequate RF magnetic fields in the ferrite to realize a critical power level of approximately 0 decibels relative to one milliwatt dBm) when using a single crystal ferrite. One known method of reducing the threshold power level is to use a lower-impedance stripline at the cost of increasing the insertion loss. An external matching structure can be used to improve the impedance match to external circuits, but this technique reduces the bandwidth and increases the insertion loss of the FSL. Permanent biasing magnets can be mounted to, or near, the FSL structure to produce a bias field. The direction of the DC magnetic field relative to the strongest RF magnetic field is typically either parallel or perpendicular. The strength of the magnetic field within the structure is one factor in determining the operating bandwidth of the limiter.
Conventional FSL devices may include in-plane tapering of the width of the signal conductor using a variety of coplanar and microstrip transmission lines with both parallel and perpendicular biasing. The purpose of tapering is to reduce insertion loss in the regions that are not above their absorption threshold. However, prior art has only tapered the conductor width along the signal propagation direction.

Transversely tapered frequency selective limiter


A wafer cleaning method and system including a combined high frequency signal, a low frequency signal, and in one embodiment a biased voltage signal, allows cleaning particles and impurities off of fine-structured wafers, through application of an acoustic field to the wafer through a cleaning liquid which fosters micro-bubble formation for effective cleaning while buffering micro-bubble growth which would otherwise damage the wafer.

1. Field of the Invention
This invention relates to methods and systems for cleansing semiconductor wafers and other items requiring extremely high levels of cleanliness, while minimizing damage to the wafer or object being cleaned.
2. Description of the Related Art
Systems employing megasonic or ultrasonic cleaning processes have been widely used to remove particles and defects from objects such as silicon wafers used in the semiconductor industry. The wafers are sometimes cleaned, for example, in a liquid or fluid into which megasonic energy is propagated. These megasonic cleaning systems safely and effectively remove particles from objects, where a system typically includes a signal generator, a piezoelectric transducer, and a transmitter, among other components. The transducer is electrically excited by a signal that causes it to vibrate, and the transmitter transmits the resulting vibration into the cleaning liquid in a processing tank. For an object such as a silicon wafer, the agitation of the cleaning liquid produced by the megasonic energy loosens particles and contaminants on the semiconductor wafers. Such contaminants are thus vibrated away from the surfaces of the wafer.
While the size of silicon chips has increased, the width of a circuit line (the line width) on the chips has become smaller in order to fit more devices on each chip. As a result, the critical particles too small to be effectively removed by older cleaning systems should be removed, but without wafer structure damage: these small particles and defects, on the order of about 0.16 μm or below, should be removed to ensure proper circuit function. At the same time, the removal process should not damage the fine structure of the chip.
A megasonic cleaning system typically creates a megasonic field, where the field is applied to an object in a cleaning fluid, such as, for example, a detergent liquid or hydrofluoric acid. The megasonic field causes bubbles to appear, pulsatingly vibrate, and collapse in the cleaning fluid. This process of bubble formation and collapse in a megasonically agitated liquid—cavitation—is the main contribution factor for effective particle removal from objects.
Cavitation is a physical phenomenon. In a liquid or other fluid energized by an acoustic field, bubbles are generated when the amplitude of negative pressure of sound waves exceeds the threshold pressure for cavitation of the liquid. Generally, the cavitation threshold is determined by the time interval of negative pressure cycles in the sound waves as they move through the liquid, along with other factors including but not limited to liquid gas content, temperature, viscosity, and liquid surface tension. Bubbles can contain vacuum, gas, liquid vapor, or a mixture thereof. The bubbles continue to pulsate and grow, and fresh gas or water vapor will continue to diffuse into the bubbles, in a process called microstreaming. Generally, negative acoustic pressure causes the bubbles to grow, and positive acoustic pressure limits the size of bubbles or provokes collapse.
Once the surface tension of a bubble is insufficient to withstand the positive pressure cycles caused by the sound waves of the applied acoustic field, the bubble collapses. The bubble collapse typically generates concentrated pressure, high temperatures, and shock waves in the cleaning liquid. The speed of bubble collapse is typically more than 300 m/sec., and high temperatures in the liquid often occur within the order of a nanosecond. As with the cavitation threshold, factors including gas content, temperature, viscosity, and liquid surface tension between the liquid and the bubbles typically influence the bubble size and density in the cleaning liquid or other fluid.
Cavitation and microstreaming, while important to wafer cleaning, also substantially increase the risk of damage to the fine structures on objects such as silicon wafers, including, for example, fine patterns on the wafers or thin films covering the wafers. Large bubbles often interact with the object to be cleaned resulting in substantial damage rather, than cleaning, where the damage often results from the violent pressure and shock waves from cavitation bubble collapse near the object. From a cleaning efficiency point of view, although a high density micro bubble field is needed to clean an object in a megasonic cleaning processes, that field must not be so strong as to damage fine structures and films on the wafer or object to be cleaned.
One solution to this problem is an increase in megasonic frequency applied to the cleaning liquid. The increase in frequency results in a shorter sonic wavelength, smaller negative sound pressure cycles in sound waves, and thus formation of smaller, less damaging bubbles. Another solution is a decrease in megasonic power. However, both of these solutions have a fundamental flaw when applied alone: although the average cavitation intensity (and hence wafer damage) is decreased in the local liquid region close to the wafer, the local bubble density decreases as well. The decrease in local bubble density hinders the cleaning effectiveness of the megasonic process. Thus, while bubble size is advantageously buffered, bubble quantity is buffered as a side effect, resulting in less effective cleaning.
While many investigations have been made into the control of various megasonic process parameters, such as, for example, changes in train time, degas time, burst time, and quiet time of sound waves, it is the use of continuous sound waves that generates the highest cleaning efficiency. So while changes in these various wave times typically modify cleaning process parameters, they cannot optimize the cavitation cleaning process: only continuous sound waves have the lowest cavitation threshold for bubble production at a selected frequency. For example, increasing quiet time or degas time for a megasonic field can decrease average cavitation density to avoid possible damage on the wafer or object, but this process decreases the efficiency of cleaning and decreases the usable wafer yield.
A need remains for a simple and practical method and device for controlled buffering of cavitation processes in an acoustic field, ultrasonic or megasonic, where enough cavitation density is generated to clean objects well while bubble size is controlled to avoid damage to objects.

Megasonic cleaning system with buffered cavitation method