A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circuit is provided in which multiple PEs share their connections to multiple data bits in the memory array. Each PE is associated with a plurality of memory buffer registers, which stores data read from (or to be written to) one or two memory data bits. In horizontal (normal) mode connection the memory bits are selected so that all the bits of a given byte are stored in the same PE, i.e., each set of buffer registers associated with a respective PE contains one byte as seen by an external device. In vertical (bit serial) mode, each set of buffer registers contains the successive bits at successive locations in the memory corresponding to that PEs position in the memory word. The selection is achieved utilizing a multiplexer on the input to the register and a pair of tri-state drivers which drive each data line.

1. Field of the Invention
The present invention relates to the field of computer memory devices and, more particularly to the connection of a massively parallel processor array to a memory array in a bit serial manner to effect a byte wide data reorganization.
2. Description of the Related Art
The fundamental architecture used by all personal computers (PCs) and workstations is generally known as the von Neumann architecture, illustrated in block diagram form in FIG. 1. In the von Neumann architecture, a main central processing unit (CPU) 10 is used to sequence its own operations using a program stored in a memory 12. The memory 12, referred to herein as "main memory", also contains the data on which the CPU 10 operates. In modern computer systems, a hierarchy of cache memories is usually built into the system to reduce the amount of traffic between the CPU 10 and the main memory 12.
The von Neumann approach is adequate for low to medium performance applications, particularly when some system functions can be accelerated by special purpose hardware (e.g., 3D graphics accelerator, digital signal processor (DSP), video encoder or decoder, audio or music processor, etc.). However, the approach of adding accelerator hardware is limited by the bandwidth of the link from the CPU/memory part of the system to the accelerator. The approach may be further limited if the bandwidth is shared by more than one accelerator. Thus, the processing demands of large data sets, such as those commonly associated with large images, are not served well by the von Neumann architecture. Similarly, as the processing becomes more complex and the data larger, the processing demands will not be met even with the conventional accelerator approach.
It should be noted, however, that the von Neumann architecture has some advantages. For example, the architecture contains a homogenous memory structure allowing large memories to be built from many smaller standard units. In addition, because the processing is centralized, it does not matter where the data (or program) resides in the memory. Finally, the linear execution model is easy to control and exploit. Today's operating systems control the allocation of system memory and other resources using these properties. The problem is how to improve processing performance in a conventional operating system environment where multiple applications share and partition the system resources, and in particular, the main memory.
One solution is to utilize active memory devices, as illustrated in FIG. 2, in the computer system. Put simply, active memory is memory that can do more than store data; it can process it too. To the CPU 10 the active memory looks normal except that it can be told to do something with the data contents and without the data being transferred to the CPU or another part of the system (via the system bus). This is achieved by distributing processing elements (PEs) in an array 14 through out the memory structure, which can all operate on their own local pieces of memory in parallel. In addition, each PE 16 within the PE array 14 typically communicates with each other, as illustrated in FIG. 3, to exchange data. Thus, active memory encourages a somewhat different view of the computer architecture, i.e., "memory centered" or viewed from the data rather than the processor.
In a computer system having active memory, such as illustrated in FIG. 2, the work of the CPU 10 is reduced to the operating system tasks, such as scheduling processes and allocating system resources and time. Most of the data processing is performed within the memory 12. By having a very large number of connections between the main memory 12 and the processing resources, i.e., the PE array 14, the bandwidth for moving data in and out of memory is greatly increased. A large number of parallel processors can be connected to the memory 12 and can operate on their own area of memory independently. Together these two features can provide very high performance.
There are several different topologies for parallel processors. One example topology is commonly referred to as SIMD (single instruction, multiple data). The SIMD topology contains many processors, all executing the same stream of instructions simultaneously, but on their own (locally stored) data. The active memory approach is typified by SIMD massively parallel processor (MPP) architectures. In the SIMD MPP, a very large number of processors (usually a thousand or more) of relatively simple PEs are closely connected to a memory and organized so that each PE has access to its own piece of memory. All of the PEs execute the same instruction together, but on different data. The instruction stream is generated by a controlling sequencer or processor.
The SIMD MPP has the advantage that the control overheads of the system are kept to a minimum, while maximizing the processing and memory access bandwidths. SIMD MPPs, therefore, have the potential to provide very high performance very efficiently. Moreover, the hardware consists of many fairly simple repeating elements. Since the PEs are quite small in comparison to a reduced instruction set computer (RISC), they are quick to implement into a system design and their benefit with respect to optimization is multiplied by the number of processing elements. In addition, because the PEs are simple, it is possible to clock them fast and without resorting to deep pipelines.
In one exemplary massively parallel processor array, each PE 16 in the PE array 14 uses only a single pin to connect to the memory 12. Thus, a one bit wide data connection is provided. When this is done, data is stored "bit serially" so that successive bits of a binary value are stored at successive locations in the memory 12. This storage format is referred to as "vertical" storage. Thus data read from and written to each PE will be read and stored, respectively, "vertically" in successive locations in the memory 12 as illustrated in FIG. 4. Thus, in FIG. 4, if each PE 16a-16n in a row 22 of PE array 14 is an eight bit PE, i.e., it operates on eight bits of data at a time, the data in the memory will be stored in eight successive vertical locations as illustrated. As noted above, each PE is connected to memory 12 by a one bit wide data connection 24. Thus, data from PE 16c will be stored in a byte sized area 20 of memory 12 in successive locations in area 20, i.e., it will be stored vertically as illustrated by arrow 30. The storage of data bit serially has a number of benefits. First, the number of data wires per PE 16 to the memory 12 is kept to a minimum. Second, it allows for variable precision arithmetic to be more easily and efficiently implemented. For example, ten, twelve, or fourteen bit numbers can be stored and processed efficiently. Third, in some cases, the difference in speed of the memory access versus the PE cycle time can be matched by serializing the data access.
There are some drawbacks, however, with storing the data from the PE array 14 bit serially. For example, in most applications, a chip containing a SIMD MPP array 14 and its associated memory 12 will have some form of off-chip interface which allows an external device, such as for example CPU 10 as illustrated in FIG. 2, to access the on-chip memory 12. CPU 10 sees data stored word-wide, i.e., "horizontally" as illustrated by arrow 32 in FIG. 4, referred to as normal mode. Thus, for external devices to access data stored vertically requires that the data be reorganized, i.e., converted, to the normal mode before being transferred from the memory to the external device, or converted by the external memory device before it can be used.
Converting between the two formats, i.e., normal and vertical, can be performed within the PE array 14 or within the external device that needs access to the data, but it would be more efficient to store the data in a single format, thus avoiding having to store it in one format and convert it to another. Preferably, the single format would be the normal format used by the external devices.
Thus, there exists a need for a connection between a PE array and main memory in a MPP such that software data conversion is not required, and data can be stored in a normal mode or vertical mode in the memory.

Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner


Systems and methods provide a security function for a device or applications running on a device. A lock tap sequence is entered by a user when the device is to be locked. When the user desires to unlock the device, the user enters a unlock tap sequence. If the lock tap sequence matches the unlock tap sequence, the device is unlocked.

Over time, smartphones have become more capable and their use has increased. With the increasing use of smartphones for everyday tasks also comes the increasing risk of losing sensitive data. One way to protect against such loss is the use of a lock screen to secure a smartphone. A lock screen can be built into the phone (i.e., a "default" lock screen) or it can be a separate application that may be obtained from third parties. While lock screens can provide some security, many users are not satisfied with currently available lock screens. They either provide too little security or require too much effort to be unlocked. Additionally, conventional lock screens that are based on gesture recognition typically suffer from the weakness that if the gesture data is collected from a wet surface or using greasy fingers, the lock screen becomes unusable.

Gesture recognition for device unlocking

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The pull device comprises a stem or body, a pull structure at one of the stem or body; an end bar or crossbar at the other end of the body or stem and extending transversely of the stem or body for extending through at least one hole in at least one end of a free tip end portion of a strap of a restraint for facilitating pulling of the strap through a locking box of the restraint in a single pull.

1. Field of the Invention
The present invention relates to a pull device for pulling the free tip end portion of at least one strap of a strap restraint which may be received through a locking box and relates to a strap restraint having structure, namely a hole at and adjacent an end of a free tip end portion of the strap for facilitating engagement of the pull device with the free tip end portion of the at least one strap. The strap may be foldable and is placed over a wrist of a person being restrained. Preferably two straps are used and are jointly pulled to fasten and lock the restraints around the wrists of the person being restrained. Also, the pull device can be removed from the one or two straps for reuse after it's initial use.
2. Description of the Related Art
Heretofore, foldable strap restraints have been proposed for use in restraining an individual being apprehended by police and military personnel.
Examples of previously proposed foldable strap restraints are disclosed in the following U.S. patents:
U.S. Pat. No.PATENTEE5,669,110Parsons5,802,675Parsons6,101,682Parsons
As disclosed in the Parsons U.S. Pat. No. 6,101,682, two separate flexible straps are provided each having a free tip end portion passing through a locking box. Detents are provided in each locking box and are arranged to resiliently engage a saw-tooth ribbed surface on each strap to retain the strap once it has been pulled through a central opening of the locking box to prevent the straps from being withdrawn once the free tip end portions are pulled outwardly from the locking box.
While these restraints have been well received by the military and law enforcement communities, some difficulty has been incurred in gripping the free tip end portions and pulling them through the locking box. In this respect, the ratcheting arrangement between the detent and or detents of the saw-tooth ribbed surface creates a significant amount of friction, which impedes movement of the straps. As a result, the free tip end portions of the straps are not always pulled equally such that the user often has to pull one strap tip at a time. Further note that it is easier to hook and pull the free tip end portions of the straps than it is to pinch and pull the free tip end portions. Still further the user typically is wearing gloves which makes it even harder to pinch and pull the free tip end portions.
Additionally, the locking box with the foldable strap restraints are carried in a pocket in a pair of pants or in a jacket or may be mounted with a clip on a belt worn around the waist. Typically a number of pairs of restraints are carried on a carbineer attached to tactical holding of or on a uniform. While such positioning of the foldable strap restraints and an associated locking box has proved satisfactory there are times when the user encounters difficulty in retrieving the foldable strap restraints from their stored position on his or her belt or clothing when the locking box snags on the user's clothing.
As will be described in greater detail hereinafter, the strap restraints and the pull device of the present invention provide cooperating structure for providing quick retrieval of the strap restraints and facilitate even and/or equal pulling on the free tip end portion of the strap or straps as well as simple retrieval of the strap restraints.

Abstract: The strap restraint comprises at least one strap having a free tip end portion and the strap having a hole in the strap adjacent an end of the free tip end portion of the strap for receiving a bar of a pull device.


Disclosed are a light emitting diode illumination apparatus and a control method thereof. The light emitting diode illumination apparatus includes a light source that includes a plurality of light emitting diode channels including one or more light emitting diodes, and emits light by application of a rectified voltage obtained by converting an AC voltage, and a control circuit that selectively provides current paths according to a change in a level of the rectified voltage through a plurality of switching circuits connected to the light emitting diode channels, and controls pulse widths of control pulses provided to the switching circuits such that an current supplied to the light source of each channel follows a waveform of the rectified voltage.

1. Field of the Invention
The present invention relates to an illumination apparatus, and more particularly, to a light emitting diode illumination apparatus and a control method thereof.
2. Description of the Related Art
For energy reduction, an illumination technology employing a light emitting diode (LED) as a light source has been continuously developed.
Particularly, a high brightness light emitting diode has advantages differentiated from other light sources in various factors such as an energy consumption amount, lifespan, or light quality.
However, an illumination apparatus employing a light emitting diode as a light source has a problem that many additional circuits are necessary due to a characteristic in which the light emitting diode is driven by a current.
An example developed in order to solve such a problem is an AC direct type illumination.
Since an AC direct type light emitting diode illumination generates a rectified voltage from commercial AC power to drive a light emitting diode and directly uses the rectified voltage as an input voltage, the AC direct type light emitting diode illumination has a good power factor.
An example of the aforementioned AC direct type light emitting diode apparatus is disclosed in Korean Patent Registration No. 10-1128680.
However, with the widespread of a light emitting diode illumination, an illumination apparatus employing a light emitting diode as a light source is required to guarantee low power consumption and an improved power factor, and to have simple parts and a simple structure.

Light emitting diode illumination apparatus and control method thereof


A User Equipment (UE), a method for determining a resource, a method for reporting a resource, and a system for distributing a resource are provided. The method for determining a resource includes: if transmission data on the carrier reaches maximum transmission data supported in a scope allowed by Service Grant (SG), and a transmission power of the UE is capable of improving a data transmission rate of the carrier, and the carrier and the other one carrier of the dual carriers are incapable of completing transmitting total buffer status data in the same delay period, determining that a resource distributed to a UE on one carrier of dual carriers of the UE is insufficient; otherwise, determining that the resource distributed for the UE on the carrier is sufficient. Therefore, a solution for reporting the resource of the dual carriers is provided, so as to improve a network performance.

With the development of mobile communications technologies, the 3rd Generation (3G) technology is evolved continuously. High Speed Downlink Packet Access (HSDPA) technology and High Speed Uplink Packet Access (HSUPA) technology are important evolution of the 3G technology. The HSUPA implements high speed uplink data transmission through a series of key technologies, such as 10 ms/2 ms short frame, the physical layer using Hybrid Automatic Repeat reQuest (HARQ), and the quick scheduling to a UE by a Node Base (Node B).
In the HSUPA, Enhanced Dedicated Transport Channel (E-DCH) is used to bear user data, and the E-DCH is categorized into a scheduling E-DCH (configured to bear non-real-time services), and a non-scheduling E-DCH (configured to bear real-time services). As for the scheduling E-DCH, the scheduling grant at the network side determines when the UE may transmit data on the E-DCH. The scheduling grant information Absolute Grant (AG) and the scheduling grant information Relative Grant (RG) are borne respectively through an E-DCH Absolute Grant Channel (E-AGCH) and an E-DCH Relative Grant Channel (E-RGCH). Whether the network side delivers the grant AG or RG is determined by Scheduling Information (SI) reported by the UE and whether the network side is satisfied with a carrier resource distributed to the UE.
In the prior art, only a method for determining whether a resource distributed to a UE on a single carrier is sufficient under a condition of the single carrier is described, and after dual carriers are introduced, no specific solution for determining whether the resource distributed to the UE on the dual carriers is sufficient is given. With the wide application of the dual carriers, determining whether the resource distributed to the UE on the dual carriers is sufficient is a problem to be solved urgently.

User equipment, method for determining resource, method for reporting resource, and system for distributing resource


A method of locating a talker in a reverberant environment comprises receiving multiple audio signals from a microphone array that include direct path audio signal and reverberation signal components. The direct path audio signal components of the multiple audio signals are detected and are used to weight the multiple audio signals. A position estimate based on the weighted audio signals is then calculated. Periods of speech activity are detected and a final position estimate is generated during the periods of speech activity.

Localization of audio sources is required in many applications, such as teleconferencing, where the audio source position is used to steer a high quality microphone towards the talker. In video conferencing systems, the audio source position may additionally be used to steer a video camera towards the talker.
It is known in the art to use electronically steerable arrays of microphones in combination with location estimator algorithms to pinpoint the location of a talker in a room. In this regard, high quality and complex beamformers have been used to measure the power at different positions. In such systems, location estimator algorithms locate the dominant audio source using power information received from the beamformers. The foregoing prior art methodologies are described in Speaker localization using a steered Filter and sum Beamformer, N. Strobel, T. Meier, R. Rabenstein, presented at the Erlangen work shop 99, vision, modeling and visualization, Nov. 17–19th, 1999, Erlangen, Germany.
U.K. Patent Application No. 0016142 filed on Jun. 30, 2000 for an invention entitled "Method and Apparatus For Locating A Talker" discloses a talker localization system that includes an energy based direction of arrival (DOA) estimator. The DOA estimator estimates the audio source location based on the direction of maximum energy at the output of the beamformer over a specific time window. The estimates are filtered, analyzed and then combined with a voice activity detector to render a final position estimate of the audio source location.
In highly reverberant environments, reflected acoustic signals can result in miscalculation of the direction of arrival of the audio signals generated by the talker. This is due to the fact that the energy of the audio signals picked up by the beamformer can be stronger in the direction of the reverberation signals than for the direct path audio signals. The effects of reverberation have most impact on audio source localization at the beginning and the end of a speech burst. Miscalculation of the direction of arrival of the audio signals at the beginning of a speech burst can be caused by a strong reverberation signal having a short delay path. As a result, the direct path audio signal may not have dominant energy for a long enough period of time before being masked by the reverberation signal. In this situation, the DOA estimator can miss the beginning of the speech burst and lock on to the reverberation signal. Miscalculation of the direction of arrival of the audio signals at the end of a speech burst can caused by a reverberation signal that masks the decaying tail of the direct path audio signal resulting in beam steering in the wrong direction until the next speech burst occurs.
In an attempt to deal with the effects of reverberation during talker localization, two approaches have been considered. One approach uses a priori knowledge of the room geometry and the reverberation (interference) and noise sources therein. Different space regions within the room are pre-classified as containing a reverberation or noise source. The response of the beamformer is then minimized at locations corresponding to the locations of the pre-classified reverberation and noise sources.
The second approach uses a computationally complex Crosspower Spectrum Phase (CPS) analysis to calculate Time Delay Estimates (TDE) between the microphones of the microphone array. Unfortunately, it is known that performance of TDE methods degrade dramatically in the highly reverberant conditions.
As will be appreciated, the above-described approaches to deal with the effects of reverberation suffer disadvantages. Accordingly, a need exists for an improved method for talker localization in a reverberant environment. It is therefore an object of the present invention to provide a novel method and system for talker localization in a reverberant environment.

Robust talker localization in reverberant environment


A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. In order to abut the gate conductors together, the upper level transistor is inverted relative to the lower level transistor. The inverted, upper level transistor thereby comprises a gate conductor residing in an elevation level below the gate dielectric and source/drain implants of that transistor. Direct coupling of one transistor gate conductor to another transistor gate conductor not only minimizes the overall routing between those conductors for the benefit of a high performance circuit, but also is particularly attuned to inverter circuits which utilize mutually connected gate conductors.

1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to multi-level transistor fabrication and high performance interconnect arranged therebetween.
2. Description of the Relevant Art
The structure and the various components, or features, of a metal oxide semiconductor ("MOS") are generally well known. A MOS transistor typically comprises a substrate material onto which a patterned gate conductor is formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which a portion of the substrate known as a "well" exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e., CMOS) are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnect to the junctions must be as small as possible. Many modern day processes employ features which have less than 1.0 .mu.m critical dimension. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decreases. Smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the lower resolutions needed for submicron features. To some extent wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
There are many numerous other techniques used to achieve a higher density circuit, however, these techniques as well as others still must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot in all instances offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects ("SCE") generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection ("HCI"). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric field can give rise to so called hot carriers and the injection of those carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since those carriers can become trapped and skew the turn-on voltage of the ensuing transistor.
It appears as though even the most advanced processing techniques cannot avoid in all instances the problems which arise as a result of high density fabrication. As features are shrunk and are drawn closer together across a single topological surface, the closeness of those features causes numerous problems even under the most advanced processing conditions. It therefore appears that there may be a certain limitation beyond which feature sizes cannot be reduced if those features are to reside on the single elevational level. It would therefor be desirable to derive a processing technique which can produce features on more than one level. That is, it would be beneficial that this multi-level processing technique produce both active (transistors) and passive (capacitors and resistors) in three dimensions so as to enhance the overall circuit density without incurring harmful side effects associated with feature shrinkage and closeness.
Before a multi-level transistor fabrication process can be introduced, however, that process must pay careful attention to the interconnection between the transistors placed on separate levels. Therefore, it is desirable to derive an interconnect scheme which can connect various features on one elevation (topological) level to features on another level. That interconnection must be as short as possible in order to minimize resistance in critical routing conductors between transistors. The desired fabrication process must therefore incorporate not only multi-level fabrication but also high performance interconnect routing as an essential part of that process. For example, it would be desirable to incorporate a relatively short interconnect between gate conductors of a pair of transistors. For example, an inverter arrangement employs an interconnected pair of p-channel and n-channel transistor gate inputs. High performance interconnection of those inputs implies that the resistance and capacitance be as small as possible to lessen the load seen by the upstream circuit. Without a mechanism to achieve high speed interconnection, multi-level fabrication is limited in its application.

Multilevel transistor fabrication method having an inverted, upper level transistor


A resin sealing device includes a lower die, an upper die which is arranged over the lower die, on a lower surface side of which a concave portion is provided, and to a bottom surface peripheral portion of the concave portion of which a projection portion projecting toward an opening portion side of the concave portion to raise partially a bottom surface is provided, and a protection film provided on a lower surface side of the upper die and adhered along a concave surface of the concave portion by adsorbing, wherein the stacked wiring substrate is sealed with a resin by making a fused resin flow into a cavity including a space between the stacked wiring substrate from a resin supplying portion, in a state that the stacked wiring substrate in which a plurality of wiring substrates are stacked via connection bumps is arranged and sandwiched between the lower die and the concave portion of the upper die.

1. Field of the Invention
The present invention relates to a resin sealing method in a stacked wiring substrate for sealing a resin between wiring substrates stacked via connection bumps and a resin sealing device.
2. Description of the Related Art
In the prior art, there are various semiconductor devices of a resin sealing type. In Patent Literature 1 (Patent Application Publication (KOKAI) Hei-8-142106), it is set forth that, in a device for molding one surface of a semiconductor chip mounted on a substrate with a resin, an adsorbing means for adsorbing/supporting a substrate by means of an air suction is provided to one of an upper die and a lower die, and the adsorbing/supporting means for adsorbing/supporting a release film for making the pealing easy is provided to the other of the upper die and the lower die.
Also, in Patent Literature 2 (WO 2007/069606 A1), it is set forth that a second wiring substrate is stacked/connected onto a first wiring substrate on which a semiconductor chip is mounted via solder balls, then a resultant structure is placed between upper and lower dies, and then a mold resin is filled between the first and second wiring substrates from an opening portion of the dies.
As explained in the column of related art described later, when the resin is filled between the wiring substrates stacked via the connection bumps by the transfer molding method using the mold dies, the connection failure between the wiring substrates is caused in some cases because the upper wiring substrate is pushed up by the inflow of the resin.

Resin sealing method in stacked wiring substrate


A mixture of a carrier, a binder and additives is used for germinating units containing seeds or the like growth-suited parts of a plant, and the units are available either separately or coherently in form of seed or plant tapes. The carrier comprises one or more substances selected from the group consisting of vermiculite, perlite, zeolite, cellulose materials, burned clay, rock wool or the like substances. The binder comprises polyvinyl alcohol, polyethylene glycol or other plant-compatible binders, such as water or water-containing polysaccharides or mixtures thereof. The additives comprise plant protecting agents, plant nutrients, surfactants, water-absorbing substances, water-carrying substances and other additives with favourable effects on germination and plant growth.

EP publication No. 0,380,448 discloses a seed pellet comprising a coated seed, where the coating for instance is made of vermiculite, binder, water-absorbing material and additives pressed together about the seed on a pelleting press. The seed pellet is intended to be sowed directly in the field, and nothing is stated about the seed pellet being placed in a small pocket in actual germinating units, neither in separate germinating units nor in germinating units in seed or plant tapes.
EP publication No. 0,260,106 discloses a plant growth medium prepared by mixing vermiculite, perlite and a gel-forming material in water and mixing said mixture with plant nutrients. The mixture is dried and shaped into sheets, pellets, granules or the like comprising seeds. No water-absorbing material is used, and it is not a question of inserting the mixture in pockets in the germinating units either. Being without the water-absorbing material it is no longer certain that sufficient moisture and simultaneously sufficient air exist about the roots of the plant.
EP publication No. 0,373,348 discloses a growth medium for plants. This growth medium comprises for instance a filler, such as vermiculite, perlite and the like together with charcoal or activated carbon plus polyacrylamide (SAP) plus possibly peat moss. The prepared medium does not, however, comprise a binder which can ensure that the polyacrylamide is uniformly distributed in said medium by being adhered to the filler.
None of the above mixtures have a completely satisfying effect in the above germinating units.

Mixture of a carrier and additives for use in germinating units containing seeds or similar growth-suited parts of a plants as well as a method of producing the mixture


According to embodiments of the present invention, a lens comprising a refractive index profile configured such that rays of light propagating in the lens form an at least substantially plane wavefront at an at least substantially vertical plane of the lens, is provided. The profile is configured to vary in an at least substantially bell curve shape along a radial direction of the lens. The lens includes a plurality of layers configured to generate the profile, wherein each layer of the plurality of layers comprises at least a first film and a second film arranged one above the other.

Photonic integrated circuits (PICS) based on waveguide technology to manipulate light signals on a chip level can be employed in information processing, communication and optical sensing etc. For photonic integrated circuits, there are two fundamental but very important requirements 1) small waveguide cross-section with a strong light confinement so that one single chip can contain multiple integrated optical devices, and 2) low loss optical coupling to/from the photonic chip for the purpose of chip interconnection.
Nanophotonic waveguide, based on for example silicon or indium phosphide (InP) semiconductor, has a high refractive index contrast between the core and cladding, which leads to a strong light confinement with a sub-wavelength cross-section and a corresponding sub-wavelength mode field diameter. This makes it superior in dense photonic integration and promising for photonic system/network on chip. On the other hand, optical fiber is widely used for light guiding and interconnection, e.g., in optical communication. The typical mode field diameter of an optical fiber is a few micrometers (e.g., it is ˜10.5 μm for a standard single mode fiber at a wavelength of 1.55 μm). Therefore, this mismatch of mode field profiles between the nanophotonic waveguide and optical fiber leads to a high coupling loss when interconnection of photonic chips is required, for example to optical fibers.
As an example, FIG. 1A shows schematic cross-sectional views of a silicon nanophotonic waveguide 100 and a single mode optical fiber 120 of the prior art, to illustrate the high coupling loss between the nanophotonic waveguide 100 and the single mode fiber 120. As shown in FIG. 1A, the silicon nanophotonic waveguide 100 includes a waveguide core 102 and a silicon-on-insulator substrate 104 including a buried silicon oxide 106 on top of a silicon substrate 108. The buried silicon oxide 106 acts as a cladding. For illustration purposes, the waveguide core 102 of the silicon nanophotonic waveguide 100 may have a width, w, of about 400 nm and a height, h, of about 300 nm. The refractive index for the silicon waveguide core 102 is about 3.45 and the refractive index for the buried silicon oxide cladding 106 is about 1.45, at the wavelength of 1.55 μm.
As a comparison, FIG. 1A also shows the cross-sectional view of a standard single mode fiber 120 including a fiber core 122 surrounded by a cladding 124. For illustration purposes, the radius, r, of the fiber core 122 is about 4.15 μm.
FIG. 1B shows a plot 130 of the mode field profile 132 of the silicon nanophotonic waveguide 100 (FIG. 1A) and the mode field profile 134 of the single mode optical fiber 120 (FIG. 1A), along the y-direction as indicated in FIG. 1A at the wavelength of 1.55 μm. As shown in FIG. 1B, the two mode field diameters or mode field profiles 132, 134, are distinctly different. Therefore, a direct butt coupling between these two optical modes may cause a coupling loss of about 20 dB due to this mismatch, even when perfect alignment between the nanophotonic waveguide 100 (FIG. 1A) and the optical fiber 120 (FIG. 1A) is achieved.
In order to reduce the coupling loss between a nanophotonic waveguide and an optical fiber, a simple and commonly used setup in laboratory involves a discrete lens with a typical millimeter size between the optical fiber and the waveguide to focus the light from the optical fiber to the nanophotonic waveguide (or expand the light beam from the nanophotonic waveguide to match the fiber). For example, FIG. 2 shows a schematic side view of a coupling arrangement 200 of the prior art, using an objective lens 202 positioned in between a waveguide 204a and a single mode optical fiber 206a. The nanophotonic waveguide 204a is placed on a waveguide holder 206a, the optical fiber 206a is placed within a fiber holder 206b and the objective lens 202 is placed in a corresponding lens holder 206c. The coupling arrangement 200 is configured such that the waveguide core 204b of the waveguide 204a and the fiber core 206b of the optical fiber 206a are aligned with each other and in addition, aligned to an optical axis, as represented by the dotted line 208, of the objective lens 202.
However, such a coupling method as illustrated by the coupling arrangement 200 of FIG. 2 has two main problems. One of the problems involves complicated assembling requirement and high packaging cost. The coupling arrangement 200 of FIG. 2 is a discrete alignment in free space, which involves 5-axis adjusters or 5-freedom adjusters for an optical fiber. FIG. 3 shows a schematic view of an optical fiber 300, illustrating a five-axis adjustment in order to adjust or align the vertical-axis y 302, the optical axis z 304, the horizontal axis x 306, the pitch angle 308 and the yaw angle 310. Therefore, proper alignment in these 5 axes is required, increasing the complexity of the optical coupling process.
In addition, as shown in FIG. 1B, a nanophotonic waveguide has a sub-wavelength spot size. However, an objective lens used for focusing light typically has a millimeter-scale size and focusing distance. Therefore, assembly based on this alignment in free space is complicated, which increases the packaging cost significantly and is not suitable for mass production.
Another problem is degraded performance of optical lens for sub-wavelength optical beams. Generally, two types of optical lens are available for applications in fiber optics, such as a conventional objective lens or a conventional graded refractive index or gradient-index lens (GRIN lens) for expanding or focusing light beams. However, both the conventional objective lens and the conventional GRIN lens have limited numerical apertures. As numerical aperture determines the resolution that can be achieved by a lens, both the conventional objective lens and the conventional GRIN lens do not have good resolution. Therefore, these available conventional lenses (eg. a GRIN lens based fiber collimator) can work reasonably well for expanding a light beam with a micro/millimeter scale beam size, but suffers from severe aberration when the light beam has a sub-wavelength spot size. As a result, coupling systems using these conventional lenses may not achieve much improvement in the coupling efficiency.
Optical coupling to a nanophotonic waveguide using, for example, an asymmetric GRIN lens with a low refractive index contrast, is no longer adequate due to the fact that the low refractive index contrast gives a low numerical aperture (NA) for the lens and therefore is not able to bend the light rays that are propagating at large angles around. In addition, even at high NA, a conventional GRIN lens with a parabolic refractive index profile is no longer adequate due to severe spatial aberration of the light beams at the focal plane, caused by the large-angle light rays of the focusing beam. Therefore, the use of the conventional low-index-contrast GRIN lens or the high-index-contrast GRIN lens with the conventional parabolic profile for optical coupling do not lead to a good coupling efficiency between an optical fiber and a nanophotonic waveguide due to the above-mentioned issues.
While photonic integrated circuits or photonic chips have been under fast development, benefiting from the fabrication techniques developed in the micro-electronics industry, the above-mentioned optical coupling problems present a barrier in engineering and commercialization of the photonic chips.
In order to achieve a high coupling efficiency between a nanophotonic waveguide and an optical fiber, various coupling schemes have been proposed and demonstrated numerically or experimentally in the prior art. These include using an inverse taper, a grating structure, and/or a bi-level mode converter. While these proposed structures may improve the coupling efficiency, specific requirements are required in order to achieve the necessary coupling efficiency. For example, the coupling scheme using an inverse tapered nanophotonic waveguide requires a thick buried oxide layer, while the approach using the grating structure requires a vertical or a tilted fiber-alignment.

Lens and a method of forming the same, a method of generating a refractive index profile for a lens and a photonic package

Agency for Science, Technology and Research


A main object of the present invention is to provide a connection structure for a solar power generation module that has much better impact resistance at low temperature and flame retardancy even when made thinner and more compact. A connection structure for a solar power generation module according to the present invention is a connection structure for a solar power generation module, which links a solar power generation module with a cable for connecting to the solar power generation module, and includes a specific thermoplastic resin composition.

In a solar power generation module (hereinafter, sometimes referred to simply as "module") that converts solar light energy into electricity, a connection structure, such as a junction box or a connector, is provided in each module for connecting a cable between modules in order to extract the electricity in a useful form. A bypass diode, for example, is arranged in the junction box, so that even if the output of a module has decreased because the surface of a solar power generation module is partially in shadow, or a battery cell is broken, the effect of such a problem can be minimized. In this case, since the bypass diode generates heat, the whole junction box needs to be heat resistant. Proposed countermeasures against this heat generation have included increasing the number of diodes, attaching a metal heat sink in order to conduct the heat away, and dissipating the heat by increasing the volume of the junction box (e.g., refer to Patent Documents 1 and 2).
As the material forming the connection structure, such as a junction box and a connector, a thermoplastic resin may be used, for example.
Since solar power generation modules are often placed outside, the thermoplastic resin forming the connection structure, such as a junction box and a connector, not only needs to have the performance that is conventionally required for electrical and electronic component applications, such as electrical insulating properties typified by anti-tracking performance, and excellent flame retardancy, mechanical properties, impact properties, water resistance, chemical resistance, and dimensional stability, but to also have impact strength at low temperatures.
Further, since the length of service of solar power generation modules is increasing, it is now important for the thermoplastic resin forming the connection structure, such as a junction box and a connector, to have thermal aging resistance properties (properties that maintain performance when exposed for a long duration to a high-temperature usage environment). In addition, the connection structure, such as a junction box and a connector, needs to have a good design and to be space saving.
In response to such needs, a connection structure for a solar power generation module has been proposed that has excellent impact properties at low temperature and long-term heat resistance even when being made thinner and more compact (e.g., refer to Patent Document 3).

Connection structure for solar power generation module


A wiring board on which an electronic component is to be mounted includes a resist having an opening exposing a joint face which is part of the surface of a wiring layer and to which a terminal of the electronic component is to be joined. In the placing step, the electronic component is placed on the wiring board such that the terminal covers the opening entirely and contacts the solder paste applied onto the joint face. Next, the solder paste applied onto the joint face is heated to melt solder and soften thermosetting resin. This allows the solder to gather in a first space within the opening closed with the wiring layer and the electronic component, while allowing the thermosetting resin to gather in a second space formed between a top side of the resist and a lateral side of the electronic component.

Low-melting-point solders have been conventionally used as a joining material for electrically joining an electronic component to a wiring board. Conventionally, in order to enhance the joining strength between the wiring board and the electronic component, the solder serving to join them together has been formed in a fillet form. The solder formed in a fillet form is called a solder fillet. However, the solder fillet is insufficient for enhancing the joining strength, and when the component mounting board is exposed to external impact, the electrical junction between the wiring board and the electronic component may be broken.
Under these circumstances, in order to further enhance the joining strength, one proposal suggests the use of a solder paste including a low-melting-point solder and a thermosetting resin, as a joining material (see, for example, Patent Literature 1). When this solder paste is used in mounting to form a solder fillet, a cured resin film 104 is formed on a solder fillet 103 as illustrated in FIG. 9 (see, e.g., Patent Literature 2). Specifically, the solder paste is applied onto a joint face between an electronic component 102 and a wiring board 101, and then, the solder paste is heated, thereby to melt the solder and soften the thermosetting resin. As a result, the solder and the thermosetting resin are separated from each other, and the solder whose specific gravity is high moves downward to form the solder fillet 103, while the thermosetting resin whose specific gravity is low moves upward to form the cured resin film 104. In that way, the solder fillet 103 is reinforced by the cured resin film 104, and consequently, the joining strength is enhanced.
When an improper mounting of the electronic component (e.g., poor junction) or a defect of the electronic component itself is detected in the produced component mounting board, the component mounting board is subjected to repair work. Here, the repair work is to remove the mounted electronic component from the wiring board, and then re-mount a new electronic component on the wiring board. The electronic component is removed with the use of a tool such as a suction nozzle, while the joint (solder fillet and thermosetting resin) is heated until the solder fillet becomes molten and the thermosetting resin is softened.

Method and system for producing component mounting board

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


Disclosed is a pharmaceutical composition or food composition for the treatment or prevention of hypertension, containing a peptide isolated from a fraction of a flounder surimi hydrolysate as an active ingredient and is based on the finding that the flounder surimi has an effect of reducing blood pressure, and the hydrolysate of the flounder surimi, the fraction of the hydrolysate of the flounder surimi and peptides isolated from the fraction of the hydrolysate of the flounder surimi have an inhibition activity against an angiotensin I converting enzyme (ACE). Thus, peptides isolated from the fraction of the hydrolysate of the flounder surimi can be used for pharmaceutical compositions or food compositions for treating or preventing hypertension. Also, the present invention is based on the finding that the hydrolysate of the flounder surimi and peptides isolated therefrom have radical scavenging effect and a protective effect against oxidative stress and are thus capable of inhibiting ROS production, lipid peroxidation and apoptosis. Accordingly, peptides isolated from fractions of the hydrolysate of the flounder surimi can be used for food compositions for antioxidation.

Hypertension is the most common chronic circulatory system disease occurring in 15 to 20% of adults worldwide, which is accompanied by relatively mild symptoms, but requires more active and steady care and treatment of patients because organs that function normally gradually lose functions thereof due to high blood pressure may cause fatal complications such as stroke, heart failure and coronary artery disease. The World Health Organization (WHO) defines a case where the maximum blood pressure is 160 mmHg or higher and the minimum blood pressure is 95 mmHg or higher, as hypertension. Hypertension is classified into spontaneous hypertension, the cause of which is not elucidated and secondary hypertension caused by a specific disease. More than 90% of hypertension is known to be spontaneous hypertension. More than 600 million people worldwide suffer from hypertension and 3 million people die of hypertension each year. For this reason, hypertension emerges as a global problem.
Inert angiotensin I, which is present in vivo, is transformed into angiotensin II which has vasoconstrictor activity through cleavage of C-terminal His-Leu by an angiotensin converting enzyme (ACE) to contract the blood vessels, and promotes the secretion of aldosterone in the kidney to increase body fluid levels and thereby elevate blood pressure. Thus, inhibition in the activity of ACE can lower the production of angiotensin II, which is the cause of elevation in blood pressure, thereby inhibiting increase in blood pressure.
ACE inhibitors such as enalapril and ramipril have been developed and are commercially available for suppressing hypertension. However, dysgeusia, leukocytopenia, angioedema, liver dysfunction and the like were found as side effects caused by the use of these drugs.
Thus, there has been a continuing demand for studies associated with antihypertensive effects from natural substances, and ACE inhibitors isolated from soy protein hydrolysates, chitosan and milk casein have been accepted as functional food for individual recognition by the Food and Drug Administration.
Meanwhile, when oxygen present in a stable state in vivo is transformed into reactive oxygen species (ROS) such as superoxide anion radical (O2−), hydroxyl radical (OH−), hydrogen peroxide (H2O2), singlet oxygen (1O2), and the like, nonselective and irreversible destructions are induced in proteins, lipids, DNA and the like, as ingredients constituting cells in the body. As such, since oxidative stress was found to be a key cause of various diseases, research has been actively conducted to develop reactive oxygen species scavengers that are capable of effectively removing reactive oxygen species (ROS) in vivo. Particularly, there is an urgent need to develop new natural material-based reactive oxygen species scavengers that have potent reactive oxygen species scavenging activity and better safety.
There has been a continuous demand for research on the acquisition of antioxidant and antihypertensive effects from natural substances. In particular, bioactive peptides can be produced by various protein hydrolysis enzymes, and peptides derived from natural substances serve as potential physiological regulators during the metabolic process while food is digested in the intestines. In addition, antioxidant, antibacterial and antihypertensive efficacies can be expected depending on the structure, composition and amino acid sequence.
In addition, since antihypertensive and antioxidant agents, which have been produced through conventional chemical synthesis methods, were found to have problems such as side effects, efforts to obtain antihypertensive and antioxidative substances from natural substances have been continuing all over the world. In addition, in order to find new substances that can be utilized in various applications such as pharmaceuticals as well as food materials such as enzymes and health supplements, there is active research on natural living organisms, especially natural living organisms that can be easily mass-cultured and bred.

Flounder surimi having antioxidant and antihypertensive effects and method of preparing the same

JEJU NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION


The invention is embodied in a parameter encoder for identifying selected parameters of a digitally sampled incoming signal lying within a receiver bandwidth, wherein the receiver bandwidth is divided into plural contiguous frequency channels, each channel having a channel bandwidth, whereby the incoming signal is divided into plural channelized signals lying in respective ones of the plural frequency channels, the parameter encoder includes plural channel processors connected to receive respective ones of the channelized signals, each of the channel processors including Fourier transform apparatus for producing a frequency value and an amplitude value for each sample of the respective channelized signal. The parameter encoder embodying the invention further includes a channel arbitrator including comparator apparatus for comparing the amplitude value with a predetermined threshold, comparing the amplitude value with the corresponding amplitude values of adjacent ones of the channels and comparing the frequency value with corresponding frequency values of adjacent ones of the channels, and processor apparatus for sensing whether a detected signal lies in the respective channel based upon at least one of: (a) determination of a corresponding amplitudes values of the respective channel and its adjacent neighbor channels relative to the predetermined threshold, (b) determination of predominance of the frequency value over corresponding frequency values of adjacent neighbor channels, (c) determination of a difference between the frequency value and that of an adjacent neighbor channel exceeding a predetermined frequency threshold.

1. Technical Field
The invention is related to parameter encoders of the type which classify a received RF signal in accordance with a predetermined set of parameters, such as frequency, pulse width, amplitude, time of arrival, type of modulation, and the like.
2. Background Art
Various digital RF receiver systems include a digital channelizer which divides a wide receiver frequency band into many narrow frequency "bins" or channels, so that the receiver can and digitally process each individual channel separately. Such a digital RF receiver may be employed in a digital cellular telephone system, for example. As another example, it may be employed with a parameter encoder. A parameter encoder is a device in a digital RF receiver which characterizes each received RF signal in accordance with a predetermined set of parameters, such as frequency, pulse width, amplitude, time of arrival, type of modulation, and the like, and transmits that information to a user. The user may be an electronic communication system. The division of the wide frequency band into narrow channels is best performed using uniform polyphase filter banks of the type well-known in the art. The highest RF frequency which can be processed is limited by the sampling rate capability of the polyphase filters. As is well-known, the Nyquist rate is the minimum sampling rate at which a particular RF frequency can be measured, and is equal to twice the particular RF frequency. The bank of polyphase filters must be able to run at the Nyquist rate corresponding to the highest frequency of the RF band of the receiver. Stated differently, the reason that a filter bank would be operated at this rate is that this is the slowest rate at which it can be operated to cover the receiver's RF frequency band, and determines the clock rate for which the hardware must be designed. By thus minimizing the hardware clock rate, hardware costs are minimized.
Digital receivers using uniform polyphase filter banks operating at the Nyquist rate suffer from the problem of aliasing between channels. Aliasing is a problem that occurs in all digital systems, and manifests itself by making frequencies outside the Nyquist bandwidth map to frequencies that are either higher or lower than the actual frequency of the received signal, a significant problem.
One way of eliminating aliasing between channels is to oversample the received signal and run the hardware including the polyphase filter banks at a rate exceeding the Nyquist rate. However, oversampling the signal and running the hardware at the higher rate is not desirable because it makes building the hardware for a wide frequency bandwidth (e.g., 1 GHz) costly or difficult, if not impossible with current technology.
Another way of eliminating aliasing between channels for a given RF signal bandwidth is to employ filters with narrower frequency bins (i.e., "narrower" filters) and employ a proportionately greater number of such narrower filters in the polyphase filter bank. However, narrowing the filters and increasing their number is not desirable because it increases the physical size of the hardware, and therefore increases the power consumption and heat dissipation.
The present invention is directed to eliminating or ameliorating the problem of aliasing between channels without increasing the sampling rate and without increasing the number of filters. In particular, the invention is directed to more reliable ways of processing a received signal whose apparent frequency is near a frequency boundary separating adjacent channels. More specifically, the invention is directed to a more reliable measurement of the frequency of a received signal of a frequency near the boundary between adjacent channels.

Uniform discrete fourier transform filter parameter encoder


Controllers for dry eye treatment apparatus and methods are described herein which generally comprise a patch or strip affixed to the skin of the upper and/or lower eyelids to deliver heat to the one or more meibomian glands contained within the underlying skin. The treatment strip or strips include one or more strips configured to adhere to an underlying region of skin in proximity to one or both eyes of a subject such that the one or more strips allow for the subject to blink naturally without restriction from the one or more patches. A controller is in communication with the one or more strips and is programmable to monitor a temperature of the one or more strips to provide a treatment therapy above a threshold temperature of, e.g., 39° C., and below a maximum temperature of, e.g., 48° C., over a treatment period of 12 minutes.

Tears are a complex mixture of water, lipids, mucus, proteins and electrolytes and this mixture helps to maintain a smooth, lubricious, and optically clear optical surface and also helps to protect the eyes from infection. The tear film has three basic layers: oil, water, and mucus and problems or disturbances in any of these layers can cause ocular surface problems including dry eye symptoms.
The outermost layer of the tear film is typically comprised of an oil layer containing fatty acids and lipids (meibum), which are produced primarily by sebaceous glands called the meibomian glands located along the eyelid margin. The oil layer smoothes the tear surface and retards evaporation of the aqueous or watery middle layer. However, if the meibomian glands fail to produce enough oil, produce suboptimal fatty acid mixtures, or if the glands become obstructed or clogged, the watery layer typically evaporates too quickly causing dry eyes. A blockage or inflammation of the meibomian glands can, among many things, lead to enlarged glands or infections, inspissated secretions, styes, chalazia, hordeolum, or preseptal cellulitis. Dry eyes are thus common in people whose meibomian glands are obstructed or functioning improperly. The aforementioned are some examples of meibomian gland dysfunction which is also sometimes referred to as evaporative dry eye.
The middle watery layer of tears is composed primarily of an aqueous solution, which is produced by the lacrimal glands and accessory glands (tear glands). The middle layer cleanses the eyes and washes away foreign particles or irritants, maintains a clear optical medium, and keeps the ocular surface moist. The innermost layer of the tear film is composed primarily of mucus, which helps to spread the tears evenly over the surface of the eyes. A lack of mucus in the tear film is also associated with dry eye syndrome.
As discussed above, the meibomian glands are oil-secreting glands located within both the upper and lower eyelids. There are approximately 30 to 40 glands along the upper eyelid and approximately 20 to 30 glands along the lower eyelid with the ducts for each of the glands opening along the inner edge of the free margin of the respective lids by minute foramina through which their secretion is released to prevent the lids adhering to each other or to the ocular surfaces. An example of the location of the meibomian glands is illustrated in the cross-sectional view of the upper eyelid UL shown in FIG. 1A which illustrates the relative positioning of a single meibomian gland MG. Other glands and anatomical features are illustrated for reference, e.g., the glands of Wolfring GW, tarsus TR, gland of Moll GM, gland of Zeis GZ, gland of Krause GK, upper fornix UF, conjunctiva CN and cornea CR of the eye which is partially covered by the upper eyelid UL. As illustrated, the meibomian gland MG is positioned along a length of the upper eyelid UL (and lower eyelid LL) with the duct opening along the inner edge of the eyelid UL in proximity to a surface of the underlying eye.
FIG. 1B illustrates a front view of a patient's eye having the upper eyelid UL and lower eyelid LL in a closed position, such as when the patient blinks. As shown, the meibomian glands MG may be seen aligned adjacent to one another over both the upper UL and lower eyelids LL. FIG. 1C also shows a perspective view of a patient's eye in the open position to illustrate how the meibomian glands are typically aligned relative to one another when the patient's eye is opened.
Blinking is thought to be the primary mechanism to open the orifice of the meibomian glands to allow for the release of oil secretions from the glands. The natural blinking motion and blinking force causes the upper lid to pull or drag a sheet of the lipids secreted by the meibomian glands over the two underlying layers of the tear film thus forming the protective coating which limits the rate at which the underlying layers evaporate. It is estimated that at least 65% of meibomian gland disease or dry eye results from a defective lipid layer or an insufficient quantity of such lipids that results in accelerated evaporation of the aqueous layer. Hence, eyelid closure or blinking disorders, or other disorders that affect proper tear distribution, may also cause or exacerbate meibomian gland dysfunction or dry eye.
As the eyelids close in a total blink, the superior and inferior fornices, which hold a reservoir of tears, are compressed by the force of the preseptal muscles and the eyelids move toward one another. The upper eyelid, for instance, moves over the eye while exerting upon the eye surface a force which helps to clear the front of the eye of debris, insoluble mucin, and also expresses the oil secretions from the meibomian glands. The lower lid moves horizontally in the nasal direction and pushes debris toward both punctae, the openings that ultimately drain into the nasal cavities.
As the eyelids open the tear film is redistributed where the upper lid pulls the aqueous phase via capillary action and the lipid layer spreads as quickly as the eyelids move. Hence, eyelid movement is accordingly important in tear-film renewal, distribution, turnover, and drainage.
For a variety of reasons, the meibomian glands can become blocked, plugged, inflamed, or occluded resulting in meibomian gland dysfunction and dry eye disease. The obstruction that triggers the disease can occur anywhere within the meibomian gland, for instance, at the gland's surface or orifice preventing normal lipid secretions from flowing; in the main channel of the gland which may be narrowed or blocked; or in other locations deeper within the gland that lead to the main channel.
Treatments for blocked meibomian glands may include a number of conventional treatments. One course of treatment includes the application of soap and cleaning agents, eyelid scrubs, antiseptics, or antibiotics to reduce eyelid inflammation. Antibiotics such as tetracycline, doxycycline, minocycline, metronidazole, azithromycin, bacitracin, or erythromycin can be administered orally or topically to help regulate or improve meibomian gland lipid production. Inflammation on the surface of the eye may also be controlled with topical drugs such as corticosteroids or cyclosporine (RESTASIS®, Allergan, Inc., CA), or other anti-inflammatory compounds or immune-suppressants. Evidence suggests that ocular surface inflammation is not only associated with meibomian gland dysfunction but also with dry eye syndrome.
Other examples of dry eye treatments may include the application of prescription eye inserts for people with moderate to severe dry eyes symptoms who are unable to use artificial tears. An eye insert, e.g., hydroxypropyl cellulose (LACRISERT®, Merck & Co., Inc., NJ), may be inserted between the lower eyelid and eye. The insert dissolves slowly to release a substance which lubricates the eye. Alternatively, special contact lenses or amniotic membrane transplants may be used to shield the surface of the eye to trap moisture.
In other treatments, the patient's tear ducts may be closed to prevent the tear film from draining away from the surface of the eye too quickly by procedures such as insertion of punctal plugs into the tear ducts or cauterizing the tissues of the drainage area. Aside from implants or cauterizing treatments, dry eye syndrome may be treated using pharmaceutical agents such as eyedrops, ointments which coat the eyes, etc. Artificial tears, gels, ointments, autologous serum tears, or albumin drops have all been employed in the treatment of dry eye.
Additionally, warm compresses are also typically placed over the eyes and are used to restore function to the meibomian glands by melting any lipid plugs as well as incorporating massaging of the lids which may further express meibomian gland contents. However, application of warm compresses often can require their application two to three times daily during which time patients may incorrectly target only one of the affected lids and are also prevented from seeing out of the treated eye because of the compresses. Warm compresses pose multiple issues such as noncompliance, poor persistence, or high variability. Compresses may be too hot, further exacerbating inflammation, or they may cool too quickly preventing adequate therapeutic effect.
Other treatment devices have also been developed which cover the entire affected eye to apply heat and a massaging force directly to the affected eyelids. However, such devices, like the compresses, require that the patient's eyes be temporarily but completely obstructed during the treatment resulting in discomfort, lost productivity, and potentially lower compliance among patients. Additionally, these treatments require visits to a physician or healthcare provider, and thus are labor intensive, inconvenient, expensive, and consequently are not as well-suited for widespread consumer adoption.
Accordingly, there exists a need for methods and apparatus which are relatively simple to routinely use for the patient or physician to use and which also allow for the patient to continue their normal activities, is non-obtrusive and non-disruptive, and which also take advantage of the patient's natural physiological activities to facilitate treatment.

Controller for dry eye treatment systems


Systems, methods, and apparatus, including software implementation, are disclosed providing drift prediction of output values for manometers. A signal or other indication may be provided for or in relation to a capacitance manometer when a servicing, replacing, and/or zeroing event is predicted or determined to be required, based on a history (e.g., timestamps) associated with previous zeroing events. Previously recorded timestamps can be curve fit with suitable functions to calculate or predict future maintenance, calibration, and/or replacement events for a manometer. Such signals or indications can be generated as an on-screen indication, and could also be available upon interrogation of the manometer via a digital communications link or system.

Pressure transducers have been employed in a myriad of applications. One such transducer is the capacitance manometer which provides very precise and accurate measurements of pressure of a gas, vapor or other fluid. Applications include precise pressure measurement and high-precision gas and vapor delivery systems, which have become very important in many industrial applications, for example in the semiconductor industry for wafer and chip fabrication, although other applications are known. Such fluid delivery systems typically also include, but are not limited to, devices such as mass flow controllers (MFCs) and mass flow verifiers (MFVs) to regulate and/or monitor the flow of gases and vapors.
Capacitance manometers typically use a flexible diaphragm forming or including an electrode structure and a fixed electrode structure spaced from the diaphragm so as to establish a capacitance there between. Variation in pressure on one side of the diaphragm relative to the pressure on the opposite side of the diaphragm causes the diaphragm to flex so that the capacitance between the electrode structure of the diaphragm and the fixed electrode structure varies as a function of this differential pressure. Usually, the gas or vapor on one side of the diaphragm is at the pressure being measured, while the gas or vapor on the opposite side of the diaphragm is at a known reference value, whether at atmosphere, or some fixed high or low (vacuum) pressure, so that the pressure on the measuring side of the diaphragm can be determined as a function of the capacitance measurement.
When a capacitance manometer is used to measure pressure and the diaphragm flexes to provide a capacitance change, it is expected that when the pressure on the measuring side of the diaphragm returns to the same pressure as the reference side (the "zero state"), the instrument will indicate a "zero" reading. However, over time, for various reasons, the reading will drift from zero when the manometer returns to a zero state. Accordingly, the manometer reading must be zeroed and calibrated from time to time to return the reading to zero for the zero state. For prior art capacitance manometers, determination of whether the manometer needs to be zeroed (e.g., have its zero-reading calibrated) has typically been decided on a time related basis, e.g., every six months, or on a routine basis, e.g., every preventative maintenance cycle (PM), or never. The choice of how often to zero the manometer is typically left to the discretion of an operator or user (e.g., a semiconductor process engineer). Such a decision has typically been based on a human inspection of previous drifts.
Any recording of accumulated drift for prior art capacitance manometers, has typically been accomplished by measuring such drift manually during routine zeroing. A judgment by the user then would then need to be made about the zeroing frequency, or whether the manometer has reached the end of its useful life.
In practice, users have typically not made such judgments due to various reasons including lack of time and/or complexity of factors involved. Instead, users have typically decided to zero or replace a manometer in reaction to an alarm on the related process tool or system or when they notice the manometer can no longer be zeroed (out of adjustment). In either case, the replacement or zeroing of the manometer causes an unexpected equipment failure problem (down time of the tool or system). Such unscheduled maintenance or replacements are something that must be dealt with outside of routine maintenance schedules, which is costly in terms of efficient use of the overall tool or system.
Thus, users have had to make a priori judgments about the frequency of zeroing. Determination of whether a manometer needs routine maintenance such as recalibration has generally not been done. Any recording of the manometer cumulative zero changes are typically also performed manually, an inconvenient process. In fact, the user generally only knows when a problem exists when there is a tool or system alarm.
What is desirable, therefore, are systems, methods, and apparatus that address the limitations noted for the prior art by predicting and/or indicating when a capacitance manometer, such as those used for high-precision fluid delivery systems, requires zeroing, maintenance, and/or replacement, and automatically calibrating the system to correct for drift when possible.

Capacitance manometers and methods relating to auto-drift correction


A rescue boat capable of use on ice, strewn water, water, snow and dragged over rigid surfaces is described. The rescue boat comprises a hull fabricated from a lamination of fiber materials having a specific orientation to provide flexibility for shock absorbing. An inner keel beam is retained along a central longitudinal axis of the hull on an inner surface of the hull. A transom cowling extends across opposed sidewalls of the hull and merges into a transom wall laminated with the hull. One or more transverse seating frames are secured across the opposed sidewalls by connecting brackets and adapted to transfer impact forces with the sidewalls. One or more vertical rigid support posts are secured to the inner keel beam and an associated one of the one or more transverse seating frames for transmitting vertical impact forces between the inner keel beam and the one or more transverse seating frames.

Very little innovations have been made to develop a small rescue boat which is capable of being used on water and ice and other surfaces and wherein the craft is displaced by two or more rescue persons capable of dragging the small craft over ice flows and land surfaces as well as on bodies of water. The craft, although small, must resist to the wear-and-tear of such environment and be capable of supporting ideally five people whereby a rescued person can be carried by the small water craft. Large ice canoes exist for racing over bodies of water strewed with broken ice and open water but these are constructed of wood ideally using cedar planks which nowadays is covered with a polyester material such as fiberglass. These canoes have a length of over twenty feet and a width of sixty-five inches and capable of accommodating 5 people. In the early Nineteen Nineties such canoes were modified using composite fiberglass sheeting material impregnated with polyester resins but these structures were very rigid and were therefore subjected to damage when impacted by heavy rigid objects such as large pieces of ice. By the mid nineteen nineties these canoes were modified wherein the length thereof was increased to 28 feet and the width up to 50 inches whereby to increase the structural rigidity of the canoes but this created another problem in that the canoe was very heavy and was not flexible to absorb impact forces without damage thereto.
With the advent of Kevlar material a solution appeared to be promissing as such material was very rigid. However, it had too much flexibility for this type of water craft and additional reinforcement was therefore necessary and the weight thereof had to be increased. Although these canoes were used mainly for racing over ice strewn waters or transporting material over such waters they were not reliable for use as a rescue craft due to its lack of flexibility and rigidity and also of its heavy weight.
However, the experience acquired in the construction of such canoes led to the development of the rescue boat of the present invention and one which would be capable of resisting impact, one which would have flexibility, durability and be of light weight so that it could be easily displaced by two or more rescue persons and accommodate up to five persons.


The present invention relates to an optical connector including, a ferrule within which an integrated optical fiber is fixed, a clamp portion disposed at a rear of the ferrule, the clamp portion comprising: a base component and a lid component facing the based component, where the base component and the lid component together are configured to clamp an end portion of the integrated optical fiber and an end portion of a naked optical fiber abutting the end portion of the integrated optical fiber, and a naked optical fiber guide portion disposed at a rear of the clamp portion, where the naked optical fiber guide portion comprises a through hole through which the naked optical fiber can be inserted, and that guides the naked optical fiber to the clamp portion by the through hole.

1. Field of the Invention
The present invention relates to a field assembly optical connector that connects an optical fiber end-on to a rear end of an integrated optical fiber which is inserted into a ferrule and fixed therein, and that is capable of being assembled together with the optical fiber.
2. Description of Related Art
When optical fiber core wires are connected end-on to each other, it is common practice to remove the coating on the core wire tip portions so as to expose the naked optical fibers, and to then connect the two naked optical fibers together end-to-end. A known optical connector of this type is an optical connector in which, in order to maintain a state in which a short length of optical fiber that is already inserted into a ferrule and fixed therein (this may be referred to below simply as an 'integrated optical fiber') is placed end-to-end with an optical fiber that is inserted from the outside (this may be referred to below simply as an 'insertion optical fiber') and then connected thereto, a clamp portion that sandwiches the abutting end portions of the two optical fibers between two halves of a clamping component is provided in the rear part of the ferrule (see, for example, Japanese Unexamined Patent Application, First Publication No. 2005-208220).


A packaged optical pellicle is provided which includes a pellicle made up of a pellicle membrane and a pellicle frame, and a pellicle package. The pellicle membrane is designed to be tensioned over and mounted to one side of the pellicle frame. A protective cover is removably mounted to the opposite side of the pellicle frame. The protective cover includes opposing portions which extend outwardly beyond the outer periphery of the pellicle frame. The pellicle package includes a base and a top, with the base having a centrally disposed recessed portion and a peripheral portion for supporting the opposing portions of the protective cover. The top of the pellicle package is adapted to fit onto the base, the top having engagement surfaces for engaging the opposing portions of the protective cover and biasing those portions onto the shoulder of the base. It is normal that the protective covering be in the form of a membrane which is of greater thickness than the pellicle membrane, but this is not a critical part of the invention. It is also typical that the engagement portions or surfaces of the top of the package extend in a manner parallel to the shoulder of the base. In any event, the present invention provides a packaging system in which the pellicle is supported such that the pellicle membrane is not contacted by any of the surfaces of the pellicle package during packaging, shipment, and removal from the package.

The present invention relates to optical pellicles, and more particularly to an optical pellicle packaging system.
In the semi-conductor chip industry it is well known that pattern transfer from the photomask to substrate is accomplished by exposing a mask to a light source. During the pattern transfer process, also called the photolithographic process, patterns on the photomask are projected onto the substrate which has been treated with a photosensitive substance. This results in the mask etchings being reproduced onto the substrate. Unfortunately, any foreign substance on the surface of the mask will also be reproduced on the substrate and therefore will interfere with proper pattern transfer to the substrate.
To eliminate contamination of the mask surface, a framed, thin membrane known as a pellicle is mounted on the mask surface, such that the pellicle membrane extends parallel to the mask at a predetermined distance spaced away from it. Any contamination which would ordinarily land on the mask surface instead falls onto the pellicle membrane.
Pellicles substantially eliminate the above problem because contamination on the pellicle membrane will not be projected onto the substrate. The frame of the pellicle supports the membrane at a distance spaced away from the mask surface so any particles or other contaminants on the pellicle membrane will be out of focus during pattern transfer.
The use of pellicles can increase the quality of the resulting circuit, thereby dramatically improving circuit fabrication productivity. Consequently, it is no surprise that pellicle manufacturing techniques have become increasingly important because high quality pellicles are critical to the success of the photolithographic process.
During the pellicle manufacturing process, it is important to minimize the possibility of either relatively large or small contaminant particles being deposited on the pellicle membrane. Relatively large particles are unacceptable because they may be reproduced in the substrate during photolithography even though they are out of focus. Equally unacceptable are particles (whether large or small) that are deposited on the underside of the pellicle membrane or the pellicle frame. Such particles may drop onto the mask surface during photolithography which is precisely what is to be avoided by using pellicles.
It is also critical that the pellicle membrane be extremely transparent and uniform across its surface. Because of this, pellicle membranes are normally extremely thin and are therefore quite fragile. Existing packaging systems often hold an optical pellicle in such a manner that the pellicle membrane itself is in contact with the pellicle package. This contact can damage the pellicle membrane in such a way that it is torn and is therefore not usable. It is also possible that the pellicle membrane can be damaged in the less visible fashion, but in such a way that particulate or other debris could rub off of the peripheral edges of the pellicle membrane which contact the package. This is a more dangerous type of damage, because it would not be immediately visible to the person who is involved in installing the pellicle onto a photomask. Such debris or particulate generated at the peripheral edges of the pellicle membrane could fall directly onto the more centrally disposed portions of the pellicle membrane, or worse yet, could become deposited on the photomask. In either event, there is a serious possibility that the existence of such particular could reduce the performance of the photolithography operation, event though the reason for having an optical pellicle is to improve the productivity of such operations.
One conventional packaging system such as that described above is disclosed in U.S. Pat. No. 4,697,701 to Ming Haw Ying. It can be seen in FIG. 3 of this patent that the top of the package directly contacts the peripheral portions of the optical pellicle membrane.
Thus, it is an object of the present invention to develop a pellicle packaging system which avoids the drawbacks and limitations of the prior art proposals. More specifically, the invention has as an object to develop a packaging system in which the pellicle membrane itself is not in contact with any portion of the packaging system, so to prevent any damage to the pellicle membrane during packaging, transport, and unpackaging of the pellicle. It is also an object of the present invention to develop a pellicle packaging system which is inexpensive to fabricate, which is extremely clean, and which may be used by one having minimal amount of skill, education or training.