A technique maintains priority of packets transmitted over a heterogeneous network by a hybrid node coupled to the network. The hybrid node assigns each packet a transmission priority (TP) level as it traverses protocol layers of a communications stack of the node. An application programming interface extension provides a tagging mechanism for conveying the TP levels from higher protocol layers of the stack to lower layers. The TP levels are then converted to information that is "tagged" to the packets and these tagged packets are then apportioned among a plurality of communication sessions based on the TP level assigned to each packet. The tagged packets and their associated sessions preserve the priority and order of the packets across the heterogeneous network.

Data communication in a computer network involves the exchange of data between two or more entities interconnected by communication links and sub-networks. These entities are typically software programs executing on hardware computer platforms, such as end stations and intermediate stations. Examples of an intermediate station may be a router or switch which interconnects the communication links and subnetworks to enable transmission of data between the end stations. A local area network (LAN) is an example of a subnetwork that provides relatively short distance communication among the interconnected stations; in contrast, a wide area network (WAN) enables long distance communication over links provided by public or private telecommunications facilities.
Communication software executing on the end stations correlate and manage data communication with other end stations. The stations typically communicate by exchanging discrete packets or frames of data according to predefined protocols. In this context, a protocol consists of a set of rules defining how the stations interact with each other. In addition, network routing software executing on the routers allow expansion of communication to other end stations. Collectively, these hardware and software components comprise a communications network and their interconnections are defined by an underlying architecture.
Modern communications network architectures are typically organized as a series of hardware and software levels or "layers" within each station. These layers interact to format data for transfer between, e.g., a source station and a destination station communicating over the network. Specifically, predetermined services are performed on the data as it passes through each layer and the layers communicate with each other by means of the predefined protocols. The lower layers of these architectures are generally standardized and are typically implemented in hardware and firmware, whereas the higher layers are generally implemented in the form of software running on the stations attached to the network. Examples of such communications architectures include the Systems Network Architecture (SNA) developed by International Business Machines Corporation and the Internet communications architecture.
The Internet architecture is represented by four layers which are termed, in ascending interfacing order, the network interface, internetwork, transport and application layers. These layers are arranged to form a protocol stack in each communicating station of the network. FIG. 1 illustrates a schematic block diagram of prior art Internet protocol stacks 125 and 175 used to transmit data between a source station 110 and a destination station 150, respectively, of a network 100. As can be seen, the stacks 125 and 175 are physically connected through a communications channel 180 at the network interface layers 120 and 160. For ease of description, the protocol stack 125 will be described.
In general, the lower layers of the communications stack provide inter-networking services and the upper layers, which are the users of these services, collectively provide common network application services. The application layer 112 provides services suitable for the different types of applications using the network, while the lower network interface layer 120 of the Internet architecture accepts industry standards defining a flexible network architecture oriented to the implementation of LANs.
Specifically, the network interface layer 120 comprises physical and data link sublayers. The physical layer 126 is concerned with the actual transmission of signals across the communication channel and defines the types of cabling, plugs and connectors used in connection with the channel. The data link layer, on the other hand, is responsible for transmission of data from one station to another and may be further divided into two sublayers: Logical Link Control (LLC 122) and Media Access Control (MAC 124). The MAC sublayer 124 is primarily concerned with controlling access to the transmission medium in an orderly manner and, to that end, defines procedures by which the stations must abide in order to share the medium. The LLC sublayer 122 manages communications between devices over a single link of the network and provides for environments that need connectionless or connection-oriented services at the data link layer.
Connection-oriented services at the data link layer generally involve three distinct phases: connection establishment, data transfer and connection termination. During connection establishment, a single path or connection, e.g., an IEEE 802.2 LLC Type 2 or "Data Link Control" (DLC) connection as referred hereinafter, is established between the source and destination stations. Once the connection has been established, data is transferred sequentially over the path and, when the DLC connection is no longer needed, the path is terminated. The details of such connection establishment and termination are well-known and, thus, will not be described herein.
The transport layer 114 and the internetwork layer 116 are substantially involved in providing predefined sets of services to aid in connecting the source station to the destination station when establishing application-to-application communication sessions. The primary network layer protocol of the Internet architecture is the Internet protocol (IP) contained within the internetwork layer 116. IP is primarily a connectionless network protocol that provides internetwork routing, fragmentation and reassembly of datagrams and that relies on transport protocols for end-to-end reliability. An example of such a transport protocol is the Transmission Control Protocol (TCP) contained within the transport layer 114. Notably, TCP provides connection-oriented services to the upper layer protocols of the Internet architecture. The term TCP/IP is commonly used to refer to the Internet architecture.
Data transmission over the network 100 therefore consists of generating data in, e.g., sending process 104 executing on the source station 110, passing that data to the application layer 112 and down through the layers of the protocol stack 125, where the data are sequentially formatted as a frame for delivery onto the channel 180 as bits. Those frame bits are then transmitted over an established connection of channel 180 to the protocol stack 175 of the destination station 150 where they are passed up that stack to a receiving process 174. Data flow is schematically illustrated by solid arrows.
Although actual data transmission occurs vertically through the stacks, each layer is programmed as though such transmission were horizontal. That is, each layer in the source station 110 is programmed to transmit data to its corresponding layer in the destination station 150, as schematically shown by dotted arrows. To achieve this effect, each layer of the protocol stack 125 in the source station 110 typically adds information (in the form of a header field) to the data frame generated by the sending process as the frame descends the stack. At the destination station 150, the various encapsulated headers are stripped off one-by-one as the frame propagates up the layers of the stack 175 until it arrives at the receiving process.
SNA is a mainframe-oriented network architecture that also uses a layered approach. The services included within this architecture are generally similar to those defined in the Internet communications architecture. In a SNA network, though, applications executing on end stations typically access the network through logical units (LU) of the stations; accordingly, in a typical SNA network, a communication session connects two LUs in a LU-LU session. Activation and deactivation of such a session is addressed by Advanced Peer to Peer Networking (APPN) functions.
The APPN functions generally include session establishment and session routing within an APPN network. FIG. 2 is a schematic block diagram of a prior art APPN network 200 comprising two end stations 202, 212, which are typically configured as end nodes (EN), coupled to token ring (TR) subnetworks 204, 214, respectively. During session establishment, an EN (such as EN 202) requests an optimum route for a session between two LUs; this route is calculated and conveyed to EN 202 by an intermediate station (e.g., station 206) via a LOCATE message exchange through the network 200. Thereafter, a "set-up" or BIND message is forwarded over the route to initiate the session. The BIND includes information pertaining to the partner LU requested for the session.
Intermediate session routing occurs when the intermediate stations 206, 216, configured as APPN network nodes (NN), are present in a session between the two end nodes. As can be seen, the APPN network nodes are further interconnected by a WAN 210 that extends the APPN architecture throughout the network. The APPN network nodes forward packets of an LU-LU session over the calculated route between the two APPN end nodes. An APPN network node is a full-functioning APPN router node having all APPN base service capabilities, including session services functions. An APPN end node, on the other hand, is capable of performing only a subset of the functions provided by an APPN network node. APPN network and end nodes are well-known and are, for example, described in detail in Systems Network Architecture Advanced Peer to Peer Networking Architecture Reference IBM Doc SC30-3422 and APPN Networks by Jesper Nilausen, printed by John Wiley and Sons, 1994, at pgs 11-83.
FIG. 3 is a schematic block diagram of the software architecture of a prior art APPN node 300. As noted, application 302 executing on an APPN end node, such as EN 202 of network 200, communicates with another end node, such as EN 212, through a LU-LU session; LU 304 within each end node functions as both a logical port for the application to the network and as an end point of the communication session. The session generally passes through a path control module 312 and a data link control (DLC) module 316 of the node, the latter of which connects to various network transmission media.
When functioning as an APPN router node, such as NN 206, an intermediate session routing (ISR) module 305 maintains a portion of the session in each "direction" with respect to an adjacent network node, such as NN 216 of network 200. In response to receiving the BIND message during session establishment, path control 312 and ISR 305 are invoked to allocate resources for the session. In particular, each NN 206, 216 allocates a local form session identifier for each direction of the session. Collectively, each of these individually-established "local" sessions form the logical communication session between the LUs 304 of the end nodes 202, 212.
When initiating a session, the application 302 specifies a mode name that is carried within the BIND message and thus distributed to all APPN network nodes; the LU 304 in each node uses the mode name to indicate the set of requored characteristics for the session being established. Specifically, the mode name is used by control point (CP) module 308 of each APPN node 300 to find a corresponding class of service (COS) as defined in a COS table 310. The CP coordinates performance of all APPN functions within the node, including management of the COS table 310. The COS definition in table 310 includes a priority level specified by transmission priority (TP) information 320 for the packets transferred over the session; as a result, each APPN network node is apprised of the priority associated with the packets of a LU-LU session. The SNA architecture specifies four (4) TP levels: network priority, high priority, medium priority and low priority. Path control 312 maintains a plurality of queues 314, one for each TP level, for transmitting packets onto the transmission media via DLC 316.
Data link switching (DLSw) is a forwarding mechanism for the SNA architecture over an IP backbone network, such as the Internet. A heterogeneous DLSw network is formed when two DLSw switches interconnect the end nodes of the APPN network by way of the IP network; the DLSw switches preferably communicate using a switch-to-switch protocol (SSP) that provides packet "bridging" operations at the LLC (i.e., DLC) protocol layer. FIG. 4 is a schematic block diagram of a prior art DLSw network 400 comprising DLSw switches 406, 416 interconnecting ENs 402, 412 via IP network 410. The DLSw forwarding mechanism is also well-known and described in detail in Request for Comment (RFC) 1795 by Wells & Bartky, 1995 at pgs 1-91.
According to the DLSw technique, a lower-layer DLC connection is established between each EN and DLSw switch; however, these connections terminate at the switches 406, 416. In order to provide a complete end-to-end connection between the end nodes, the DLC connections are "disposed" over a reliable, higher-layer transport mechanism, such as TCP sessions. DLSw switches can establish multiple, parallel TCP sessions using well-known port numbers. All packets associated with a particular DLC connection typically follow a single, designated TCP session. Accordingly, SNA data frames originating at a sending EN 402 are transmitted over a particular DLC connection along TR 404 to DLSw switch 406, where they are encapsulated within a designated TCP session as packets and transported over IP network 410. The packets are received by DLSw switch 416, decapsulated to their original frames and transmitted over a corresponding DLC connection of TR 414 to EN 412 in the order received by switch 406 from EN 402.
Typically, all packets transmitted by DLSw switch 406 over a DLC connection/TCP session flow at the same priority level from a single output queue 405 of the switch and, as noted, arrive at an output queue 415 of DLSw switch 416 in the same order in which they are transmitted. When the switches are configured as bridges to forward packets over a TCP session through the IP network, prioritization is straightforward. However, it may be desired to integrate the functions of an APPN network node within switch 406 by overlaying an APPN layer onto a DLSw layer of the switch; the resulting hybrid node may prioritize the packets at the APPN layer in an order governed by the TP information levels.
A problem that arises when deploying a hybrid node in such a heterogeneous network is that the TP priority information is lost when passing the packets between the APPN and DLSw layers, primarily because the TP information is not encapsulated within the packets. That is, the APPN layer has knowledge of the TP levels associated with the packets of a LU-LU session by virtue of the BIND message exchange during session establishment; yet that information is not encapsulated within the associated packets and, thus, is not conveyed beyond the APPN layer.
Specifically, the packets are passed from the APPN layer in priority order and "fimneled" onto the single output queue of the DLSw layer for transmission over the appropriate DLC connections/TCP sessions between the DLSw switches; as noted, the order of these packets is typically preserved from end point to end point over the communication sessions. However, if there is congestion within the IP network, e.g., at intermediate queuing points within intermediate routers, there is no information within the packets to instruct the routers how to sort and arrange the packets by priorities assigned by the hybrid node.
The present invention is directed to solving the problem of prioritizing packets transmitted by a hybrid node within a heterogeneous network, particularly when congestion occurs within the network.

Technique for maintaining prioritization of data transferred among heterogeneous nodes of a computer network


Disclosed are a viscosity index improver which comprises a copolymer (A) consisting essentially of an alkyl methacrylate (a1), and one or more monomers (a2) selected from the group of conjugated dienes, acetylene, substituted acetylene, alkyl vinyl ethers and alkyl allyl ethers; an engine lubricant composition comprising said viscosity index improver and base oil; and a concentrate comprising an increased amount of said viscosity index improver and base oil. The viscosity index improver gives reduced amounts of coked products, while improving the fuel-related performance characteristics of cars that use the engine lubricant composition comprising the improver.

1. Field of the Invention
The present invention relates to a viscosity index improver, an engine lubricant composition, and a concentrate. More precisely, it relates to a viscosity index improver producing reduced amounts of coked products, an engine lubricant composition comprising said viscosity index improver and base oil, and a concentrate comprising an increased amount of said viscosity index improver and base oil.
2. Description of the Prior Art
With the recent tendency toward the global environmental protection, there is being an increased demand for much more improvements in fuel-related performance characteristics of cars (fuel consumption in cars). As one means of improving such fuel-related performance characteristics of cars, so-called multi-grade oil comprising engine oil and a viscosity index improver may be used. At present, about 30% of engine oil to be used in diesel engine cars in Japan will be such multi-grade oil. Multi-grade oil of the type generally contains a viscosity index improver comprising an ethylene-propylene copolymer (hereinafter referred to as "OCP viscosity index improver").
Where further improvements are required in fuel-related performance characteristics of cars in future, engine oil to be used will be required to have a reduced viscosity. In order to satisfy this requirement, engine oil must have a high viscosity index while having a lowered high-temperature high-shear viscosity (that is, a lowered TBS viscosity).
However, engine oil containing such an OCP viscosity index improver added thereto is defective in that its viscosity index is low while its high-temperature high-shear viscosity is high, thereby resulting in that the engine oil containing it is problematic in that its viscosity could not be lowered any more and that fuel-related performance characteristics of cars that use it could not be improved any more.
In order to solve these problems, the addition of a viscosity index improver containing an alkyl methacrylate polymer (hereinafter referred to as "PMA viscosity index improver") to engine oil may be taken into consideration. Since engine oil containing such a PMA viscosity index improver may have a higher viscosity index and a lower TBS viscosity than that containing an OCP viscosity index improver, it is expected that the former may have a lowered viscosity and that fuel-related performance characteristics of cars that use the former could be much more improved.
However, engine oil containing a PMA viscosity index improver is problematic in its practical use in that it gives large amounts of coked products.

Viscosity index improver, engine lubricant composition, and concentrate


An aft suspension system for a pickup truck comprises four corner assemblies, where one corner assembly is located at a suspension position corresponding to each of the wheel corners for the vehicle. An air supply unit includes a reservoir, a compressor, and an ECU is fluidly connected to the corner assemblies. The air supply unit is capable of independently adjusting the corner assemblies from one another. The air suspension system is operable to place the corner assemblies in a unloading position or a trailer, which corresponds to two of the corner assemblies in raised positions and the other of the two corner assemblies located in lowered positions to create a maximum height differential between the front and rear corner assemblies.

Suspension systems for automotive vehicles provide vehicle passengers with a more comfortable ride. Demand from vehicle owners for more controls and options has led to the development of adjustable air suspension systems. Depending on the current driving surface, different suspension operating modes may be selected by the vehicle operator. The suspension operating modes have present suspension parameters to provide the ideal suspension arrangement for various driving situations. Typical operating modes a driver may select include, a standard driving mode, a parking mode, an off-roading mode, etc,
In addition to providing selected operating modes for various driving situations the suspension system may be adjusted when select operating conditions are met. For example the vehicle height may be lowered when operating above a predetermined operating speed to obtain a better aerodynamic profile for the vehicle. Thus, adjustable air suspension systems provide a vehicle operator with a more efficient driving experience.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

System and method of using air suspension to improve vehicle unloading


An optical measurement system configured to determine whether an optical transmitter signal requires calibration is disclosed. In an implementation, the system includes an optical transmitter configured to emit electromagnetic radiation in limited spectrums of wavelengths at amplitudes based upon one or more transmission signals, and an optical sensor configured to detect the electromagnetic radiation in the limited spectrums of wavelengths and to generate a signal in response thereto. The system includes reference current sources configured to generate a respective reference current and a switch configured to transition between a first configuration and a second configuration based upon the transmission signals. The reference currents are configured to subtract from the signal generated by the optical sensor such that a difference remains. A comparison device is configured to compare the difference portion to a reference signal and output a signal indicative of the direction in which an optical transmitter driver signal should be adjusted.

Optical communication networks include optical transmitters configured to emit, or generate, signals representing data to be transmitted. For example, optical transmitters may be utilized within a passive optical network to provide reliable and efficient data transmission of video, audio, images, text multimedia, and so forth, via optical fibers. Data from an optical line terminal is transmitted via an optical fiber and is shared among multiple optical network terminals located proximate to an end-user location.

Direct reference subtraction system for control of optical transmitters


A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator.

In most modern computer systems, a memory system may have a significant impact on the performance of the computer system. A poorly designed memory system may cause a modern computer system with a state of the art processing unit to perform no better than an older computer system with an average processing unit. This may be due to slow access to programs, applications, data, and so forth, stored in the memory system. A poorly designed memory system may significantly delay access to memory and effectively negate performance advantages inherent in the state of the art processing unit. For example, the speed in which the processing unit may process instructions and data may be dependent on the ability of the memory system to provide the instructions and data to the processing unit. A slow memory system may make the processing unit wait unnecessarily.
FIG. 1 is a diagram illustrating a computer system 100. Computer system 100 includes a processing unit 105 and a memory system 110. Memory system 110 may be partitioned into multiple levels, with a first level of memory being registers 115 located in a processing unit, a second level of memory being a cache memory 120, a third level of memory being main memory 125, and a fourth level of memory being mass storage devices 130. In general, the amount of the memory available at each level will increase with level, while the speed will decrease. Generally, the speed of memory at a given level may be an order of magnitude slower than memory at a level immediately higher than it. For example, registers 115 in the first level of memory may amount to only tens or hundreds of bytes, while a mass storage device 130 may be on the order of terabytes in size, but the speed of the registers 115 may be hundreds if not thousands of times faster than the mass storage device 130.
Cache memory 120 is a relatively small but fast memory that may be used to temporarily hold instructions and/or data. Since cache memory 120 is relatively small, it may be unlikely that an entirety of instructions and/or data can be stored in cache memory 120. Rather, the instructions and/or data stored in cache memory 120 may be instructions and/or data that are predicted to be instructions and/or data that will be used by processing unit 105 in a relatively short amount of time. If the instructions and/or data required by processing unit 105 are residing in cache memory 120, then the instructions and/or data may be retrieved from cache memory 120 with relatively small delay. However, if instructions and/or data required are not in cache memory 120, then the instructions and/or data will need to be retrieved from main memory 125 or mass storage device 130 with significant delay.
Cache memory 120 include a cache data memory 135 that may be used to store instructions and/or data, a cache tag memory 140 that may be used to store high order address bits of instructions and/or data stored in cache data memory 135, and a cache controller 145 that may be used to manage the reading and writing of instructions and/or data in cache memory 120, as well as predicting instructions and/or data that will be needed in the future and retrieving them from lower levels of memory.
When a memory address of an instruction or data is presented to cache memory 120, high order bits (the tag) of the memory address may be used to index into cache tag memory 140 to determine if the instruction or data is stored in cache data memory 135. If the tag indicates that the instruction or data is stored in cache data memory 135, then cache controller 145 may be used to retrieve the instruction or data from cache data memory 135. If the tag indicates that the instruction or data is not stored in cache data memory 135, then the instruction or data may be retrieved from main memory 125 or mass storage 130. As the instruction or data is retrieved from main memory 125 or mass storage 130, it may also be stored in cache data memory 135. Storing the instruction or data may force out instructions and/or data already stored in cache data memory 135. Additionally, cache tag memory 140 may also be updated to reflect the newly stored instruction and/or data.
Some computer systems also make use of error correcting codes (ECC) to protect the integrity of instructions and/or data stored in its memory system. The use of an ECC adds additional bits of information to each byte, word, and so on, in the memory system to detect (and in some cases, correct) errors in the instructions and/or data stored in the memory system. The addition of ECC may help to increase the complexity of determining cache memory hits (i.e., the requested instruction or data is stored in the cache memory) or cache memory misses (i.e., the requested instruction or data is not stored in the cache memory), since additional operations may need to be performed to verify that there is an ECC match in addition to memory address match. This may result in slowing down cache memory performance as well as increasing cache memory design complexity.
FIG. 2a is a diagram illustrating a portion of a cache memory 200 wherein cache memory 200 makes use of a prior art technique for determining cache memory hit or miss and wherein the memory system makes use of ECC. Cache memory 200 includes an ECC generator 205 that may be used to generate an ECC from an m bit input CPU-tag data input (i.e., high order bits of a memory address from the processing unit). The ECC, as generated by ECC generator 205, may be provided to cache tag memory 207 (which may be similar to cache tag memory 140, for example), where if the CPU-tag is in cache tag memory 207, the cache-tag associated with the CPU-tag may be retrieved.
The cache-tag and the ECC may then be provided to a single error correction-double error detection (SEC-DED) ECC unit 209 that may be used to correct the cache-tag using the ECC if necessary (and if possible). SEC-DED ECC unit 209 may produce a corrected cache-tag, which may then be compared with the CPU-tag in an equality comparator 211. If the corrected cache-tag and the CPU-tag are equal, then equality comparator 211 may assert that a cache memory hit has occurred. If the corrected cache-tag and the CPU-tag are not equal, then equality comparator 211 may assert that a cache memory miss has occurred.
FIG. 2b is a diagram illustrating a portion of a cache memory 250 wherein cache memory 250 makes use of a prior art technique for determining cache memory hit or miss and wherein the memory system makes use of ECC. Cache memory 250 attempts to shorten delays incurred by the addition of ECC by computing a fast hit value, which may or may not represent an actual cache memory hit. Cache memory 250 includes cache tag memory 207, SEC-DED ECC unit 209, and equality comparator 211 which serve substantially the same purpose in cache memory 250 as they do in cache memory 200, which is determining the occurrence of a cache memory hit or a cache memory miss. The result produced by these units is referred to as being a true hit.
However, to shorten delays due to the inclusion of the ECC, cache memory 250 also computes a fast hit. As discussed above, a fast hit may not accurately represent a cache memory hit. A memory address that results in a fast hit may actually end up being a cache memory miss, so a fast hit is not 100 percent fool proof. Cache memory 250 includes an ECC generator 255. Similar to ECC generator 205, ECC generator 255 generates an ECC from the CPU-tag from the memory address provided by the processing unit. ECC generator 255 outputs an ECC that may be compared with an ECC retrieved from cache tag memory 207. The comparison may be performed by an equality comparator 257. If the two ECCs are equal, then a fast hit is asserted. Since the delay through EEC generator 205 and equality comparator 257 is typically shorter than the delay through cache tag memory 207, SEC-DED ECC unit 209, and equality comparator 211, it will usually complete faster.
FIG. 2c is a diagram illustrating a detailed view of SEC-DED ECC unit 209. SEC-DED ECC unit 209 includes a SEC-DED syndrome unit 265 that may be used to compute an error syndrome from the cache-tag. The error syndrome may be a pattern that is representative of any errors present in the cache-tag. The error syndrome may be provided to an error bit decoder 267 that may be used to determine which bit (or bits) in the cache-tag contains an error. An error bit corrector 269 may then be used to correct the erroneous bit (bits) in the cache-tag.
The error syndrome from SEC-DED syndrome unit 265 may also be provided to a SED/DED decoder 271. SED/DED decoder 271 may determine from the error syndrome provided by SEC-DED syndrome unit 265 if a single error detection (SED) or a double error detection (DED) occurred. If a SED occurred, then error bit corrector 269 may be able to correct the error in the cache-tag. If a DED occurred, then error bit corrector 269 may not be able to correct the error in the cache-tag and a cache memory miss has occurred. The output of error bit corrector 269 may be compared with the CPU-tag in equality comparator 211 to determine if a cache memory hit or a cache memory miss occurred.

System and method for fast cache-hit detection

Taiwan Semiconductor Manufacturing Company, Ltd.


A semiconductor integrated circuit (1) comprises a substrate voltage control circuit (10A), a drain current adjuster (E1), a MOS device characteristic detection circuit (20), and a drain current compensator (E2). The substrate voltage control circuit (10A) has at least one substrate voltage supply MOS device (m1) for controlling the supply of the substrate voltage of the semiconductor integrated circuit (1). The drain current adjuster (E1) adjusts the drain current of the substrate voltage supply MOS device (m1) by controlling the substrate voltage of the substrate voltage supply MOS device (m1). The MOS device characteristic detection circuit (20) has a characteristic detection device (m2) for detecting the characteristics of the substrate voltage supply MOS device (m1). The drain current compensator (E2) corrects the drain current of the substrate voltage supply MOS device (m1) by controlling the substrate voltage of the substrate voltage supply MOS device (m1) according to the characteristics of the substrate voltage supply MOS device (m1) detected by the MOS device characteristic detection circuit (20).

In recent years, it is requested in the field of a semiconductor integrated circuit that the variability of a substrate voltage of the semiconductor integrated circuit resulting from PVT (process, voltage variation, temperature) be reduced based on the control of a substrate voltage of an MOS element for supplying the substrate voltage so as to realize an optimum delay setting and cut down power consumption. In order to realize the request, it is necessary to provide a substrate voltage control circuit for monitoring a characteristic of the MOS element for supplying the substrate voltage and supplying an optimum substrate voltage conformable to an actual delay value to the semiconductor integrated circuit via the MOS element for supplying the substrate voltage. There are two conventional circuits which realized such substrate voltage control.
The first conventional example is a constitution wherein the substrate voltage is supplied to the semiconductor integrated circuit via the MOS element for supplying the substrate voltage so that a saturation current of the MOS element for supplying the substrate voltage can be constant, which is recited in the Non-Patent Document 1. A schematic illustration of the example is shown in FIG. 12.
The second conventional example is a constitution wherein a delay of a replica circuit having the same circuit configuration as that of a circuit to be controlled is monitored, and such a substrate voltage that a delay value thereby obtained can be optimal is supplied to the actual circuit (semiconductor integrated circuit), which is recited in the Non-Patent Document 2.    Non-Patent Document 1: (M. Sumita, S. Sakiyama, M. Kinoshita, Y. Araki, Y. Ikeda, and K. Fukuoka, "MixedBody Bias Techniques with Fixed Vt and Ids Generation Circuits" ISSCC Digest of Technical Papers, pp. 158-159, February 2004)    Non-Patent Document 2: (J. Tschanz, J. Kao, S. Narendra, R. Nair, dantoniadis, A. Chandrakasan, and V. De, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-DieParameter Variation on Microprocessor Frequency and Leakage" ISSCC Digest of Technical Papers, pp. 412-413, February 2002.)


A tensile-testing apparatus (10) comprises a platen (40) for situating a tendon-type support system in manner mimicking its expected installation condition. A force-imposing device (20) imposes installation-expected forces and sensors (61, 71) sense displacement in the force-imposing direction. A station (80) collects force and displacement data and a station (90) outputs the collected data in format allowing system analysis.

A tendon type support system, such as a mechanical rock bolt system, can be used to stabilize rock in a tunnel or mine. Such a bolt system supports the rock that makes up the immediate roof structure by supporting it from a stronger or more stable rock structure that lies above.


An electromagnetic actuating apparatus having an armature unit, which can be moved through a movement distance in an axial direction relative to a stationary core unit and in reaction to an operating current being passed through a coil unit, which armature unit magnetically interacts axially at one end with the core unit over a control range which at least partially overlaps axially along the movement distance, which, as a section of the armature unit, has a first profile section and, as a section of the core unit, has a second profile section, with an air gap formed between them and forms an extent at right angles to the axial direction.

The present invention concerns an electromagnetic actuation device.
Such a device is, for example, of known art from DE 198 48 919 A1 as an electromagnetic valve device. As a reaction to the energisation of a (stationary) coil unit, an armature unit, guided in a radially symmetrical manner in the interior of the coil, moves and opens or closes a valve seat for the fluid that is to be controlled.
Here the armature unit (essentially having a cylindrical armature body) moves along the axial direction relative to a stationary core unit, which is part of the magnetic circuit, and which by means of its configuration influences the movement characteristic, in particular a magnetic armature force of the armature unit. In concrete terms the device cited as prior art features a so-called control cone region (control region) for purposes of influencing the movement characteristic, i.e. the force profile, of the armature movement in the crossover region between the (movable) armature unit and the (stationary) core unit; the said control cone region influences the magnetic flux in the magnetic circuit between armature unit, core unit, and the other magnetic circuit elements that are involved, along the axial direction, in a region of the armature stroke (namely the region immediately after the release of the armature unit from the core unit).
The control cone of known art from DE 198 48 919 A1, here in the form of an annular step, running around the periphery of the armature end face, and flattened outboard, and a corresponding (radial) inner form on the side of the core unit, here effects, for example, an increase of the magnetic force of the armature in the initial stroke region described. As a result of the overlap shown between the armature unit and the core region the necessary magnetomotive force of core and armature reduces as a result of energisation of the coil, relative to that for a so-called flat cone, namely a configuration of the crossover region between armature unit and core unit with no axial overlap, i.e. with no reduction of the working air gap. Accordingly the magnetic field lines of the magnetic flux over the axial overlap are primarily closed, as a consequence of which the magnetic force in this armature initial stroke region is specifically increased.
By means of a suitable configuration of the said control region (control cone region), for example, specification of an effective axial overlap, it is possible to influence specifically the movement characteristic of the armature unit, in particular a profile of the magnetic force along the movement stroke (movement stroke path); to reinforce or weaken, for example, the profile comparatively or point-by-point.
However, the axial overlap of armature unit and control unit in the control region, which is to be taken to be of known art, also brings with it potential disadvantages, in particular in terms of the wear and service life properties of electromagnetic actuation devices configured in this manner. Thus in particular, as a result of the axial overlap of the profile sections on the armature and core forming the control region, in addition to the axial magnetic flux profile that is important for the armature movement, there also arises a radial component (i.e. a component normal to the axial direction) of the magnetic flux profile, across the air gap formed between the facing walls of the profile sections. The said magnetic force component (which is radial in radially symmetrical arrangements) causes disadvantageous transverse forces, which have a disadvantageous effect in practice, i.e. in particular in conjunction with frequent movement cycles, or long operating times. It is true to say that if the armature and core were to be exactly aligned relative to one another, the transverse force generated by the radial magnetic force component would be cancelled out in the centre and thus compensation would be effected. However, this cannot be achieved in practice, either in production, or in operation. Instead the effect can be observed that the armature unit (necessarily mounted with a radial clearance) within a surrounding guide has a tendency to tilt (within the bounds of the clearance that is present), whereby such an effect is, for example, additionally reinforced by compression springs that are not engaging quite centrally with the armature unit, or similar influences; production tolerances and other effects also play a role.
An armature unit of this kind, sitting within the bounds of the clearance fit in an inclined manner in the armature guide (in the form of a diametrical two-point contact on corresponding internal positions of the armature guide) leads firstly to the fact that core unit and armature unit (and consequently the profile sections forming the control region) are no longer exactly aligned, thus large radial air gaps of various sizes (more specifically: sectors of a peripheral air gap) appear around the periphery.
With energisation of the coil unit and the magnetomotive force in the control region thereby caused large magnetic transverse forces of unequal size accordingly arise in the air gap positions of various widths. Small radial air gaps generate relatively high magnetic transverse forces, while large radial air gaps correspondingly generate small magnetic transverse forces. These no longer compensate for each other in the radial direction, so that a resultant (radial) transverse force is formed in the direction of the smallest air gap.
This acts on the armature unit (mounted with clearance) as a normal force and generates static and sliding friction forces in accordance with the frictional values of the tribological system comprising the armature unit (or an armature sliding coating provided on the armature unit) and also the armature guide.
In the first instance these act negatively on the force balance of the magnet and lead to an (unnecessary) increase in the magnetic force requirement, and consequently to a larger magnet installation space.
In electromagnetic switching devices with a high service life requirement (typically more than 100 million switching cycles) the high magnetic transverse forces (normal forces) described also generate a disadvantageously high surface pressure onto the friction partners, and thereby accelerate their tribological wear. This is particularly serious, for example, in the case of pneumatic actuation applications (such as, for example, a pneumatic valve) since here no lubrication or similar can act so as to reduce the wear.
The consequence is premature failure, in particular in the case of systems with a control cone region optimised in terms of build size and energy consumption, in particular if the armature unit, in a manner otherwise of known art, is provided with sliding coatings of PTFE or MoS2 and no sliding film (itself, however, again complex) is used for purposes of guiding the armature.
It is therefore the object of the present invention to improve an electromagnetic actuation device of the generic kind in terms of its operational and wear characteristics, in particular to reduce disadvantageous transverse, i.e. normal forces, which promote tilting of the armature unit, and thus within the context of systems having an axially overlapping control region to combine a beneficial magnetic movement characteristic and energy optimisation with protection against undesirable wear as a result of disadvantageous friction.


In one aspect, an apparatus for setting a dynamic user/issuer pairing is provided, comprising:                at least one processor; and        at least one memory including computer program code;        the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to:        send transaction details and an account identifier to a plurality of issuer servers belonging to a corresponding plurality of issuers, the transaction details relating to a transaction initiated by a user and the account identifier identifying the user;        receive issuer fee bids submitted by one or more issuers who have received the transaction details and the account identifier, the one or more issuers being those available to conduct the transaction; and        analyze the issuer bids based on predetermined criteria associating with the account identifier to present to the user at least one issuer among the one or more issues who have submitted the issuer bids.

With the proliferation of mobile communication devices, such as mobile telephones, financial account holders that have such devices have begun to use them to effect financial transactions.
Recently, there is an increasing and significant number of users effecting financial transactions online e.g., using the Internet or via a mobile device app program. It is known that the customers are limited to use accounts that they have with financial institutions. However, it is impossible to know about the on-going promotions that other financial institutions are holding with an appropriate user/financial institution (e.g., an issuer) match.
For example, user typically browses online, selects the products (e.g., goods and/or services) and makes payment online. This traditional payment mode can have numerous disadvantages including, for example, limited awareness of promotions that other financial institutions are holding or not knowing of other users who have good financial credibility These disadvantages can be even more problematic when user would like to save money on transaction fee or to conduct a transaction that the financial institution with whom he does not have an account.
In the recent time, financial institutions have enhanced the way in which they publicize their promotions and transaction fees. When using such websites, for example, financial institutions can post descriptions of their on-going promotions, which can then be searched by users who access the website. If a user is interested in a posted promotion, the user can contact a financial institution by opening an account with the financial institutions. Thus, these types of websites are still based on the traditional process summarized above, but with the convenience that financial institutions can post their on-going promotions, and users can review on-line available promotion and submit an application for an account using their computer.
While such web sites have provided an improved level of convenience to financial institutions and users relative to other traditional methods, known resources nevertheless suffer from a number of disadvantages and inconveniences associated with the time consuming process of posting on-line promotions, reviewing application forms mailed or submitted by users, deciding which users are good candidates after reviewing application forms, contacting those users, and going through the application process. Further, this traditional process provides limited insight to the financial credibility of a user.
A need therefore exists to provide methods for conducting a user-approved transaction using one of a plurality of accounts that addresses one or more of the above problems.
Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.

Apparatus and method for dynamic user/issuer pairing


A receiving circuit for a radio-wave clock broadcast wave having a frequency converter that converts a received signal of the radio-wave clock broadcast wave into a signal of a frequency in the bandwidth of an AM radio broadcast. The converted-into signal is input to a first high frequency amplifier of an AM radio receiver of a heterodyne type comprising the amplifier, an oscillator, a frequency mixer generating a signal of an intermediate frequency, an intermediate frequency amplifier amplifying the signal of the intermediate frequency, and a detector. Time correction is performed on the basis of a demodulated signal of the radio-wave clock broadcast wave output from the detector.

1. Field of the Invention
The present invention relates to a receiving circuit for a radio-wave clock broadcast wave and particularly to technology for realizing the mechanism of a radio-wave clock to be small in size, easy to mount and inexpensive.
2. Description of the Related Art
These days, many of products such as radios, car audio systems, and home audio systems have a clock function. Most of clock circuits mounted in these products use a crystal oscillator. With the circuits using a crystal oscillator, there is a limit in improving their accuracy because variation of about ±1 to ±5 sec per day and thus variation of about ±30 to ±150 sec per month occur.
One method to improve accuracy is to adopt a radio-wave clock. However, in order to realize a radio-wave clock, a circuit to receive a reference wave of 40 kHz to 80 kHz in frequency is necessary (refer to, for example, Japanese Patent Application Laid-Open Publication No. 2004-80073), and in order to incorporate this in the above products, the tasks of reducing its size and costs need to be achieved.

Receiving circuit for radio-wave clock broadcast wave


A method and system for distributed acoustic sensing using multimode optical fibers.

Fiber-optic sensors are increasingly being used as devices for sensing some quantity, typically temperature or mechanical strain, but sometimes also displacements, vibrations, pressure, acceleration, rotations, or concentrations of chemical species. The general principle of such devices is that light from a laser is sent through an optical fiber and there the light experiences subtle changes and then reaches a detector arrangement which measures these changes.
In particular a growing application field is the use of fiber optic sensing system for acoustic sensing, especially Distributed Acoustic Sensing (DAS). DAS is quickly becoming recognized as a powerful tool for remote downhole sensing. The list of existing and potential applications for this new technology is long and continues to grow. Traditionally, DAS measurements are performed with single mode optical fiber (SMF), and not multimode optical fiber (MMF).
Distributed temperature sensing or DTS is a fairly mature and fairly widely deployed downhole oil and gas sensing technology that usually requires the use of MMF. For this reason, many hydrocarbon wells throughout the world already have MMF installed. The ability of using DAS with MMF can greatly expand the use of DAS in existing wells and will allow both types of measurements to be performed with one type of fiber.

Distributed acoustic sensing with multimode fiber


In a parabolic reflector system for directing or receiving radiation from or to a radiation feed, having a parabolic reflector surface defining a parabolic reflector axis, a parabolic reflector focus and a radiation aperture, wherein the parabolic reflector has a flat plate shroud attached thereto at the aperture thereof and a radome covering the shroud aperture.

This invention relates to reflector type radio frequency (RF) antennas used for communications purposes and more particularly to such antennas having a parabolic shaped reflector, a shroud and a radome.
Parabolic reflector type antennas developed and currently produced for satellite ground applications use are made by forming aluminum sheet on a mandrel by a spinning process. Satellite earth terminal antennas may be forty feet or more in diameter and are fabricated using preformed metal panels or are plastic molded on parabolic forms. The plastic reflectors are metalized to make the surface reflective using any of many well known techniques.
High tolerance parabolic reflectors for high efficiency operation must be very stiff to maintain the manufactured parabolic shape regardless of single or multi-piece construction or size. Reflectors of two or more piece construction of metal or plastic require greater effort and costs than the same size reflector of single piece construction for the same surface precision. However, two or more piece construction of reflectors of diameter larger than about two feet have significant saving in storage and shipping. All must meet the same operating surface tolerances.
One class of parabolic reflector antenna that is known to produce superior radiation performance is the so called "high performance" antenna. This class consists of a parabolic reflector, a reflective cylindrical shroud and a planar radome covering the shroud aperture. Cylindrical shrouds are a development of "tunneling" techniques to reduce unwanted side and back radiation from a transmitting antenna and unwanted side and back radiation reception by a receiving antenna. The shroud as used on high performance parabolic reflector antennas has been a cylinder the same diameter as the reflector to which it attaches at one end and the radome covers the other end of the cylinder.
The radome is a transparent microwave window and may be rigid plastic or a pliable material mated to the cylindrical shroud open aperture by various means.
High performance signifies much reduced side and rear radiation characteristics of the shrouded antenna, as compared with a standard, (average), unshrouded parabolic reflector antenna. Low side and rear radiation performance is required in urban or congested areas to minimize interference with other antennas.
Shrouds of other shapes, such as conical shapes are not as effective as cylindrical shrouds whose reflective surface is parallel to the parabolic reflector axis of the antenna system. Conical shaped shrouds serve as extensions of the parabolic reflector surface and exhibits similar diffraction radiation as simple parabolic apertures.
A shrouded parabolic reflector antenna is relatively more expensive to make than one without a shroud. Typically the shroud is supported by the reflector and adds significant weight and wind force loading to the antenna support, which tends to distort the shape of the parabolic reflector and the reflective shroud, losing some of the surface accuracy produced at the factory. With a cylindrical shroud, radiation to the side and rear can be 20 db or more down as compared to an unshrouded antenna, all else being equal. Thus, the cylindrical shroud does not contribute to structural integrity and does not enhance the parabolic reflector surface accuracy. It is employed when much improved radiation directivity is desired over the performance of an unshrouded parabolic reflector antenna.
For sizes larger than about two feet in diameter, high performance antennas suffer the disadvantage of: greater weight, larger shipping and storage volumes, assembly and installation complexities, and greater cost. As a consequence, high performance antennas have been used only for terrestrial point-to-point microwave communication links.

Antenna system parabolic reflector, flat plate shroud and radome


The present invention is intended to provide a method of fabricating an EEPROM having excellent endurance characteristics. A work obtained by processing a substrate (1) by a wafer processing process including a passivating process and having a tunnel oxide film, an aluminum wiring film and a passivation film is subjected to a low-temperature heat treatment employing a processing temperature of about 250.degree. C. and a processing time on the order of 50 hr in a thermostatic oven (20) in the presence of nitrogen gas. The low-temperature heat treatment reduces trap sites produced in the tunnel oxide film by a plasma CVD process carried out to form the passivation film to repair the tunnel oxide film damaged by the plasma CVD process and to improve the endurance characteristics. The aluminum wiring film is not deteriorated by the low-temperature heat treatment because the low-temperature heat treatment employs a relatively low processing temperature.

1. Field of the Invention
The present invention relates to a method of reducing the trap density of an oxide film formed in a semiconductor device and, more particularly, to a method of reducing the trap density of an oxide film formed in a semiconductor device suitable for application to fabricating a nonvolatile memory cell.
2. Description of the Related Art
An EEPROM of a floating gate construction having a floating gate electrode formed under an insulating layer (oxide film) underlying a control gate electrode is a known nonvolatile memory cell.
This EEPROM has a thin oxide film (tunnel region) between a drain and a floating gate electrode. Electrons are injected through the thin oxide film (tunnel oxide film) into the floating gate or electrons are removed from the floating gate through the thin oxide film to erase or write information.
In writing or erasing information, an electric field of a high intensity is applied to the thin tunnel oxide film to allow electron to tunnel through the thin tunnel oxide film. Therefore, it is essential that the thin tunnel oxide film is capable of withstanding repeated application of a high-intensity electric field thereto to enhance the endurance characteristics (which are represented by the number of possible data rewriting cycles) of the EEPROM.
The endurance characteristics may be improved if the breakdown of the tunnel oxide film attributable to the local concentration of the high-intensity electric field applied to the EEPROM in rewriting data can be prevented and it is considered that the endurance characteristics can be effectively improved by forming the tunnel oxide film in a uniform film quality.
A high-temperature annealing in an N.sub.2 atmosphere at a high temperature on the order of 1000.degree. C. is a means for improving the film quality of an oxide film.
However, it was found through experiments conducted by the inventors of the present invention that the tunnel oxide film is damaged and trap sites are formed by a plasma CVD process for forming a silicon nitride (SiN) film having an excellent hygroscopic property as a passivation film.
Thus, if the tunnel oxide film has trap sites, electrons are liable to be trapped when tunnel current flows through the tunnel oxide film in rewriting data in the EEPROM, the intensity of the internal electric field of the tunnel oxide film increases with the increase of the trapped electrons and, finally, the breakdown of the tunnel oxide film occurs.
Since the tunnel oxide film damaged in forming the passivation film is repaired after an aluminum electrode has been formed, it is impossible to improve the quality of the tunnel oxide film by high-temperature annealing.

Method of reducing the trap density of an oxide film for application to fabricating a nonvolatile memory cell


A method for balancing a rotor of an alternator in a diesel-electric locomotive in which the rotor is drivingly coupled to a power output shaft of a diesel engine. A speed sensor and a vibration sensor are coupled to the rotor for providing output signals representative of instantaneous rotational velocity and instantaneous amplitude of vibrational motion of the rotor, respectively. In the inventive method, the rotor is accelerated to a first preselected rotational velocity and a first rotor unbalance is determined from the velocity and vibration signals. The rotor is then accelerated to a second preselected rotational velocity and a second rotor unbalance is determined. The first and the second rotor unbalance determinations are combined to identify a first correction weight and position thereof for minimizing the first and the second rotor unbalance. The identified weight is installed and the process repeated until the unbalance is corrected such that vibration is less than a preselected maximum value.

The present invention relates to balancing of rotors of large dynamoelectric machines and, more particularly, to in situ balancing of a rotor of an alternator operatively coupled to a shaft of an internal combustion engine and assembled in a locomotive.
Balancing of rotating apparatus, from automobile tires to aircraft gas turbine engines, is a generally known process. Typically, the apparatus is placed on some form of fixture and rotated at preselected speeds. The fixture has built-in electronics for detecting out of balance conditions and indicating to an operator a mass of weight and the location for adding the mass so as to correct the unbalance condition. Some of these balancing machines may provide for gross corrections, such as with tire balancing, while others may provide for very fine balancing, such as is required for gas turbine engines. The first may sense the forces induced in the machine by the rotating apparatus while the latter may use highly expensive, non-contacting vibration sensing equipment, such as dynamic trim balancing analyzers of the type described in U.S. Pat. No. 3,751,987. These latter type machines, while very accurate, are not generally adapted for use in detecting unbalance in large dynamoelectric machines mounted in an operating system. Initial balancing of rotors of large dynamoelectric machines is generally performed in the same manner as with other rotating apparatus, i.e., before installation in an operating system. However, such initial balancing is often not sufficient to meet the requirements for vibration when the rotor is installed in the dynamoelectric machine and further installed in an operating environment. In particular, when the rotor is operatively coupled to a shaft of an internal combustion engine, the additional vibration induced by the engine may be sufficient to excite undesirable vibrations in the dynamoelectric machine and in the equipment in which the machine is installed. Accordingly, it would be advantageous to provide a method and apparatus which can be used in a manufacturing environment to detect and correct unbalance in a large dynamoelectric machine when the machine is installed in an operating locomotive or similar electric traction vehicle.


A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.

1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a semiconductor device having a guard ring.
2. Description of the Background Art
Generally, a power semiconductor requires a high main breakdown voltage retaining capability. For such retention of breakdown voltage, guard ring structures are generally utilized. Basic structures and applied structures thereof are disclosed in, for example, the following document or the like:    B. Jayant Baliga, "Power Semiconductor Devices", the United States, PWS PUBLISHING COMPANY, pp. 98-103
A guard ring structure is provided with an impurity region having a floating potential and surrounding an emitter to alleviate surface electric field and retain breakdown voltage.
If guard rings are provided up to the end of a semiconductor substrate, an electric field peak comes in the semiconductor substrate in the vicinity of its central portion in which an element formation region is provided. Hence, the guard rings are not formed up to the end of the semiconductor substrate.
Intervals between the guard rings are adjusted so that an electric field peak is maximal just below a guard ring electrode attached to an outermost guard ring. Unfortunately, this limits improvement of breakdown voltage just below the guard ring electrode attached to the outermost guard ring.
Also, the guard ring structure unfortunately requires a large area to retain breakdown voltage.


The problem is solved by converting each radio frequency of a plurality of communications systems to tested signals as digital signals via single A/D conversion means; inputting the one A/D-converted tested signal to Fourier transform means 16 for frequency spectrum analysis; converting the other A/D-converted tested signal and a local frequency LO2 via a tested signal converter 13; filtering the converted tested signals S13 to convert them to tested signals S14 containing necessary signal components; and decimating the filtered tested signals S14 and performing frequency spectrum analysis on the decimated tested signals S15 via the Fourier transform means 16.

1. Field of the Invention
The present invention relates to a frequency spectrum analysis method and a frequency spectrum analyzer, and in particular to a frequency spectrum analysis method and a frequency spectrum analyzer in which frequency spectrum analysis is performed via software by using proper tested signals on a per communications system basis.
2. Description of the Related Art
FIG. 2 is a block diagram showing a conventional frequency spectrum analyzer. Two types of communications systems, Communications System A and Communications System B, are treated in this figure.
For Communications System A, tested signals S12A are input to a fast Fourier transformer 16. For Communications System B, tested signals S12B are input to the fast Fourier transformer 16.
Intermediate frequencies IFA, IFB and sampling frequencies SFA, SFB of Communications System A and Communications System B differ from each other; for example, the intermediate frequency IFA of Communications System A is 3.6 MHz and the sampling frequency SFA is 14.4 MHz while the intermediate frequency IFB of Communications System B is 100 kHz and the sampling frequency SFB is 400 kHz.
Communications System A and Communications System B use frequency spectrum resolutions different from each other to perform frequency spectrum analysis.
For example, the frequency spectrum resolution required of Communications System A is approximately 1800 Hz and the frequency spectrum resolution required of Communications System B is approximately 50 Hz. Sampling data count required by the fast Fourier transformer 16 is 8192 (2{circumflex over ( )}13) for both Communications System A and Communications System B.
Communications System A: 14.4 MHz÷8192=1757.8≈1760 Hz
Communications System B: 400 kHz÷8192=48.8≈50 Hz
The following describes a processing procedure to take when Communications System A or Communications System B is selected for frequency spectrum analysis.
In the case of frequency spectrum analysis in Communications System A, system selector switches SW2, SW3 are placed in the P1 position and an output frequency obtained through frequency synthesis of a radio frequency RF and a local frequency LO1A is input to a low-pass filter 11A composed of hardware and converted to an intermediate frequency IFA. The intermediate frequency IFA is input to an A/D converter 12A to obtain tested signals S12A as digital signals. The tested signals S12A are input to the fast Fourier transformer 16 to obtain frequency spectrum analysis results S16.
In the case of frequency spectrum analysis in Communications System B, system selector switches SW2, SW3 are placed in the P2 position and an output frequency obtained through frequency synthesis of a radio frequency RF and a local frequency LO1B is input to a low-pass filter 11B composed of hardware and converted to an intermediate frequency IFB. The intermediate frequency IFB is input to an A/D converter 12B to obtain tested signals S12B as digital signals. The tested signals S12B are input to the fast Fourier transformer 16 to obtain frequency spectrum analysis results S16.
The frequency spectrum analyzer has a problem that new hardware must be implemented for each communications system thus expanding the size of apparatus. In order to solve this problem, a configuration is proposed in which apparatus size is reduced by using the same hardware and realizing through software the difference in hardware design.
FIG. 3 is a block diagram showing a frequency spectrum analyzer with apparatus size reduced. Same as a conventional frequency spectrum analyzer, Two types of communications systems, Communications System A and Communications System B, are treated in this figure.
Apparatus size is reduced by sharing hardware between Communications System A and Communications System B. An intermediate frequency IF and a sampling frequency SF shall satisfy the test conditions of a conventional frequency spectrum analyzer and the IF and the SF shall be the higher of the IF frequencies and SF frequencies of Communications System A and Communications System B, respectively.
For both Communications System A and Communications System B, tested signals S12 are input to the fast Fourier transformer 16. Required frequency spectrum analysis resolution is obtained by changing the sampling data count at fast Fourier transform depending on the communications system employed.
Thus the intermediate frequency IF is 3.6 MHz and the sampling frequency SF is 14.4 MHz. Same as a conventional frequency spectrum analyzer, the frequency spectrum resolution required of Communications System A is approximately 1800 Hz and the frequency spectrum resolution required of Communications System B is approximately 50 Hz. Sampling data count required by the fast Fourier transformer 16 is 8192 (2{circumflex over ( )}13) for Communications System A and 262144 (2{circumflex over ( )}18) for Communications System B.
Communications System A: 14.4 MHz÷8192=1757.8≈1760 Hz
Communications System B: 14.4 MHz÷262144=54.9≈55 Hz
The following describes a processing procedure to take when Communications System A or Communications System B is selected for frequency spectrum analysis.
In the case of frequency spectrum analysis in Communications System A, an output frequency obtained through frequency synthesis of a radio frequency RF and a local frequency LO is input to a low-pass filter 11 composed of hardware and converted to an intermediate frequency IF. The intermediate frequency IF is input to an A/D converter 12 to obtain tested signals S12 as digital signals. The tested signals S12 are input to the fast Fourier transformer 16 to obtain frequency spectrum analysis results S16.
The frequency spectrum analysis in Communications System B is the same as that in Communications System A. However, the sampling data count required by the fast Fourier transformer 16 is a huge 262144. This resents problems that the processing time is extremely long and memory used for operation such as fast Fourier transform is large.
A conventional frequency spectrum analyzer has a problem that the apparatus size is large and a frequency spectrum analyzer with apparatus size reduced has problems that memory usage is large and frequency spectrum analysis takes huge processing time.
For a frequency spectrum analyzer with apparatus size reduced, reduced sampling data count required by the fast Fourier transformer in Communications System B would shorten the processing time and reduce memory usage.
The object of the invention is to provide a frequency spectrum analyzer wherein apparatus size is reduced, processing time is shortened, and memory usage is reduced while the conventional frequency spectrum analysis performance is retained, by adding a signal processor in software which provides an intermediate frequency and a sampling frequency equivalent to those of a conventional frequency spectrum analyzer for each communications system, based on a frequency spectrum analyzer with apparatus size reduced.
The invention solves the aforementioned problems via the following frequency spectrum analysis methods and frequency spectrum analyzers:
1. A frequency spectrum method comprising the steps of:
converting each radio frequency of a plurality of communications systems to tested signals as digital signals via single A/D conversion means,
inputting said one A/D-converted tested signal to Fourier transform means for frequency spectrum analysis,
converting said other A/D-converted tested signal and a local frequency via a tested signal converter,
filtering the converted tested signals to convert them to tested signals containing necessary signal components, and
decimating the filtered tested signals and performing frequency spectrum analysis on the decimated tested signals via the Fourier transform means.
2. A frequency spectrum method comprising the steps of:
synthesizing each of the radio frequencies with local frequencies and filtering the frequency-synthesized tested signals to convert them to tested signals containing necessary signal components, and performing A/D conversion on the tested signals to obtain the digital signals.
3. A frequency spectrum analyzer for performing frequency spectrum analysis comprising:
a tested signal converter for inputting tested signals and outputting converted tested signals,
a low-pass filter for inputting the converted tested signals and outputting filtered tested signals,
a sampling frequency converter for inputting filtered tested signals and outputting tested signals,
system selector switches for switching between communications systems, and
a fast Fourier transformer for inputting tested signals and outputting frequency spectrum analysis results, characterized in that frequency spectrum is analyzed via software by using proper tested signals for each communications system.
4. A frequency spectrum analyzer, characterized in that the tested signal converter performs frequency synthesis of tested signals and local frequencies to convert the tested signals to the tested signals in a proper frequency band.
5. A frequency spectrum analyzer, characterized in that the system selector switches make switching so that one tested signal is input to the fast Fourier transformer and the other tested signal is converted by the tested signal converter, low-pass filter and sampling frequency converter, and the converted signal is input to the fast Fourier transformer.
6. A frequency spectrum analyzer for converting each of radio frequencies of communications systems having different frequencies to digital signals via a single A/D converter and performing frequency spectrum analysis on the digital signals via a frequency spectrum analysis section consisting of a single fast Fourier transformer, the frequency spectrum analysis section comprising:
a tested signal converter for inputting tested signals and outputting converted tested signals,
a low-pass filter for inputting the converted tested signals and outputting filtered tested signals,
a sampling frequency converter for inputting filtered tested signals and outputting tested signals,
system selector switches for switching between communications systems, and
a fast Fourier transformer for performing frequency spectrum analysis on the selectively input tested signals and outputting frequency spectrum results, characterized in that frequency spectrum is analyzed via software by using proper tested signals for each communications system.
7. A frequency spectrum analyzer, characterized in that the single A/D converter comprises:
a low-pass filter for converting to intermediate signals the frequency obtained by synthesizing each of the radio frequencies and a first local frequency and
an A/D converter for A/D-converting the intermediate frequency.
8. A frequency spectrum analyzer, characterized in that the tested signal converter performs frequency synthesis of tested signals and a second local frequency to convert the tested signals to the tested signals in a proper frequency band.
9. A frequency spectrum analyzer, characterized in that the system selector switches make switching so that one digitally converted signal is input to the fast Fourier transformer and the other digitally converted signal is converted by the tested signal converter, low-pass filter and sampling frequency converter, and the converted signal is input to the fast Fourier transformer.

Frequency spectrum method and frequency spectrum analyzer


A digital camera comprising an imaging device, a memory, a monitor, and a monitor controller is provided. The digital camera is used for photographing an optical image of an object as an image of a first rectangle. An aspect ratio of the first rectangle is a first aspect ratio. The imaging device generates an image signal. The monitor is a second rectangle. An aspect ratio of the second rectangle is a second aspect ratio. The second aspect ratio is decided to be lower than the first aspect ratio if the first aspect ratio is higher than one. The second aspect ratio is decided to be higher than the first aspect ratio if the first aspect ratio is lower than one. The monitor controller makes a displayed-image be displayed on the monitor according to a first or a second replay mode.

1. Field of the Invention
The present invention relates to a digital camera that can display a captured image while being rotated according to a position of the digital camera on photographing.
2. Description of the Related Art
In the prior art, the imaging device used for a digital camera is formed to a rectangle, having long and short sides. The imaging device is mounted in the digital camera so that the long sides can be parallel to the horizon when the digital camera is in the regular position. In addition, the digital camera has a rectangular monitor, whose aspect ratio is the same as that of the imaging device. The monitor is usually mounted in the digital camera so that the long sides of the monitor can be parallel to the horizon when the digital camera is in the regular position.
Accordingly, a wide-width-photograph, whose width is greater than the height, is taken when the digital camera is in the regular position. On the other hand, a tall-height-photograph, whose height is greater than the width, is taken when the digital camera is in a vertical position, where the digital camera is rotated around the optical axis by 90 degrees. When the tall-height-photograph is replayed on the monitor, a user should rotate the digital camera by 90 degrees.
As for the above problem, Japanese Patent Publication No. 2002-232753 discloses a digital camera to display the tall-height-photograph automatically rotated by 90 degrees. Then, the tall-height-photograph is displayed on the monitor with a scale-down.


A method and system wherein the coverage area of a plurality of base stations may be evaluated with respect to noise rise and power for assignment of system resources is disclosed. Path loss is measured to determine candidate base stations and at least one timeslot is selected from within the candidate base stations for optimization of the uplink and downlink.

Wireless communication systems may be deployed in a number of ways. For example, cellular type systems are typically deployed using an omni deployment or a sectored deployment. In FIG. 1, an omni deployment 10 is shown. Omni deployments are made up of sites with a base station in each site wherein the base stations use transmission (reception) antenna(s) that radiate (receive) nearly uniformly in all directions in the horizontal plane. Omni deployments are typically used for rural, micro-cellular, and indoor areas.
To increase system capacity in densely populated areas, for example, a sectored deployment may be used. An example of a sectored deployment 50 is shown in FIG. 2. Sectored deployments are also made up of sites (i.e. site 1 and site 2) wherein each site includes a base station. In sectored deployments, however, each site is broken down into a plurality of sectors. To provide coverage to each sector, the base stations include a transceiver and antenna(s) for each of their respective sectors so that the antenna(s) in each sector radiate/receive within a different arc. For example, base station 52 has transceivers 56a, 58a, 60a which each radiate with an arc of 120 degrees for sectors 56b, 58b, 60b. For simplicity, the area covered by a transceiver is hereafter referred to as a cell with the understanding that a cell may correspond to either a sector in a sectorized deployment or an area covered by a site in an omnidirectional deployment.
Referring now to FIG. 3, and continuing with cellular type systems purely by way of example, cellular systems generally divide the time axis into continuing intervals of equal duration called frames. A frame 100 is divided into a finite number (Nt) of intervals of equal duration called timeslots. A particular cell is allowed to use some or all of the timeslots for uplink or downlink transmissions as defined by the cell's timeslot assignment. Within each timeslot, it is possible to assign a finite number of codes (Nc) to different WTRU(s) for transmission/reception of wireless signals using spread spectrum technology. The combination of a code and a timeslot is considered a channel and the allocation of the codes to a set of WTRU(s) is referred to as channel allocation. An optimum allocation will reduce interference and increase capacity of the system.
Typically, when a WTRU requests resources (i.e. a set of channels) from a wireless system the WTRU first chooses the base station from which the WTRU has measured the least amount of path loss. Generally, to measure path loss the WTRU subtracts the measured power at which the beacon signals are received from the known transmission power of those signals. The transmission power of the beacon signals is normally signaled within the beacon as part of the system information. The base station from which the least amount of path loss is measured is referred to as the base station that is closest to the WTRU. Note, however, that this base station may not always be the closest in the geographical sense. Once the closest base station has been selected, resources are then allocated to the WTRU. Typically, the channel that is allocated is within a timeslot where the WTRU will experience the least amount of interference.
Interference may originate from two sources, intra-cell and inter-cell. Intra-cell interference is interference seen by a WTRU due to other WTRUs in the same cell as the WTRU. Inter-cell interference is interference seen by the WTRU from WTRUs in other cells. Some wireless communication systems employ some type of multi-user detection (MUD) that cancels most of the intra-cell interference seen by the WTRU. The TDD modes (3.84 Mcps and 1.28 Mcps) of UTRA are examples of such systems. In these systems, channel allocation is primarily concerned with minimizing the inter-cell interference seen by the WTRU.
With respect to inter-cell interference, neighboring cells are typically timeslot synchronized so that the neighboring cells are using the same timeslots for uplink and downlink transmissions. Assigning resources to a WTRU in one cell may result in a significant increase in inter-cell interference to the neighboring cells. For example, the WTRU may be assigned to a timeslot that, although being the timeslot with the least amount of interference, the addition of the WTRU causes a sudden increase in interference that cannot be compensated by WTRUs operating in the same timeslot in neighboring cells (i.e. WTRUs assigned resources from that timeslot cannot transmit with enough power to maintain a satisfactory signal to interference plus noise ratio (SINR)). The above outage can occur due to the well-known power balancing effect between the WTRU and WTRUs from neighboring cells that are also assigned resources in the same timeslot.
Power balancing is a phenomenon that occurs in various wireless communication systems such as CDMA type systems, for example. In CDMA type systems, since all WTRUs within the system share the frequency spectrum, each WTRU sees the other WTRUs noise/interference. To achieve reliable communication, a SINR ratio must be above a certain ratio. When a new WTRU is added to a system, the interference in the system increases. This causes existing WTRUs within the system to increase their power to maintain the SINR above the certain ratio. The power increase from the existing WTRUs causes an increase in interference to the new WTRU. The new WTRU then increases its power again to maintain the SINR. This pattern continues until the SINR stabilizes. In cases where the SINR does not stabilize, one or more WTRU's will experience outage. In the prior art, there is a mechanism to predict the increase in interference, based on the current level of interference and relative path loss of the new WTRU to the system. This mechanism can be used to choose the timeslot with the lowest predicted increase in interference. However, there may be cases where, although resources within the timeslot in this cell and neighboring cells are not fully used (i.e. the MUD benefits are not fully realized), there is no suitable timeslot within this cell for the new WTRU in this cell. This will lead to a blocked WTRU admission.
It would therefore be desirable to have a method and system for assigning resources in wireless communication systems without such limitations.

Resource allocation in wireless communication systems


A process for producing thin films of superconducting material by bombarding a heated target with radiation from pulsed high energy UV laser to form a plume of target material, and depositing the plume on a substrate is disclosed.

Recent advances in the superconducting transition temperature of various oxide materials has provided the opportunity for applications in radio frequency, microwave and other electronic technologies. Considerable progress has been made in a number of fabrication technologies related to forming these oxide superconductors into various electronic devices.
The technique of laser evaporation for deposition of thin films has been applied to a large class of materials ranging from polymers to semiconductors and dielectrics. For most present electronic device applications such as radio frequency and microwave technology, thin films are proving to be the form of superconducting oxide most useful. As a result, much of the work relating to the use of high temperature superconductors in microelectronic applications has focused on the growth of high quality thin films. Such films can serve as ground planes or can be patterned into a microwave circuit. High quality superconducting films can have significantly lower values of surface resistance than copper or gold films. This low surface resistance is important for making high-performance thin film microwave circuits such as filters, resonators and delay lines.
While various methods are available for producing superconducting thin films, one of the better methods is pulsed laser deposition, described first by D. Dijkkamp at al., Appl. Phys. Lett., 51, 619-621 (1987). This method provides thin films of superconducting material having correct stoichiometry and high superconductivity transition temperature, T.sub.c. In addition to the high deposition rate provided by this method and relatively simple apparatus required, the film can be grown at low substrate temperatures, as discussed in Koren et al., Appl. Phys. Lett., 56, 2144-2146 (1990). A major drawback of this technique is that the deposited film contains a large number of particles, commonly referred to as particulates, typically on the order of 0.5 .mu.m to 2 .mu.m in width and are commonly present in a density of 110-140 particulates per 1000 .mu.m.sup.2. The presence of these particulates limits the use of the film in most applications where microscopic patterns must be printed thereon, e.g., microwave circuits. Koren et al. has speculated that these undesirable particulates may result from loosely connected target flakes, splashing of molten material, or deep target subsurface heating that leads to an explosion of bubbles and condensation in the high density plume that results from the laser ablation of the target.
Several techniques have been devised to reduce the size and/or number of particulates in these films. One described by Koren et al. involves the use of a second laser beam perpendicular to the first to reduce the size of the particulates. Another involves using a target that is moved at a velocity comparable to the fragments in order to eject the particulates, Research Disclosure, 32397, March 1991, page 209.
While these methods have met with some success, they involve more expensive and complex apparatus than conventional laser ablation and do not produce sufficiently particulate-free films for demanding applications. The present invention provides a method for producing films wherein the amount of particulates is reduced by orders of magnitude rendering such films of superior utility as circuit elements.

Process for making oxide superconducting films by pulsed excimer laser ablation


In accordance with preferred embodiments, a fuel injector has a gas accumulator of a volume that is at least ten times the maximum amount of fuel which would have to be injectable thereby, and a solenoid operated poppet valve with an end face that opens into the combustion cylinder and is shaped to deflect a portion of the fuel injected into direct contact with the ignition plug. In a first embodiment, using a variable fuel supply, an electronic control unit (ECU) controls the injection timing to inject the compressed gas into the cylinders as each's piston nears its top dead center (TDC) position to obtain diesel engine-like efficiencies (.eta.=45%) so long as the compressed gas supply pressure is sufficiently high (at least approximately 2,000 psi), and when the compressed gas supply pressure becomes too low for high efficiency operation (i.e., below 2,000 psi), the ECU changes the manner of operation so that fuel is injected into the engine when piston is near its bottom dead center position (BDC) so that it can be premixed with air prior to ignition to produce gasoline engine-like efficiencies (.eta.=35%).

1. Field of the Invention
The present invention relates to fuel injection systems for gaseous fuel engines. In particular, the invention relates to a system by which a compressed natural gas fueled engine can obtain efficiencies at or above those obtained by diesel engines.
2. Description of Related Art
Jensen U.S. Pat. No. 4,865,001 discloses a gaseous fuel injector valve, having a tubular body and stemmed poppet valve, for injection of a mixture of a gaseous and a liquid fuel into a diesel engine. The poppet valve includes a coil compression spring which normally urges the valve stem into a closed position sealing a fuel flow passage into the combustion chamber and has an outwardly opening valve face portion over which the outflowing supply of fuel passes. The injector valve is electronically controlled by a solenoid valve to cause gaseous fuel to be admitted into engine cylinder during the part of the compression stroke after the exhaust valve has closed and prior to rapid increase in the compression pressure that follows. However, this injector is not designed for use in engines that operate solely with gaseous fuels, nor does it deal with the problems associated with engines that are operated solely using gaseous fuels, and particularly, the need to obtained increased efficiency or the difficulties of igniting a gaseous fuel (the liquid fuel serves as a pilot for ignition of the gaseous fuel, being injected after the gaseous fuel).
In U.S. Pat. No. 4,505,249 of Young, a fuel control system for gaseous fueled engines is disclosed wherein a pressure regulator is provided for maintaining a constant pressure from the fuel source. However, Young's system is a carburetion system and is primarily directed to using the gaseous fuel in supplementing the fuel supply of a diesel engine. Thus, the Young patent, also does not deal with the problem increasing the efficiency of an engine fueled solely with compressed gas; carburetor-type compressed gas systems, which work like a conventional gasoline engine, have a lower efficiency than a diesel engine.
Lewis et al. disclose in U.S. Pat. No. 4,430,978, a system for the direct injection of liquid petroleum gas in to an engine. The Lewis et al. system compensates for the effect of variations in fuel pressure and density on the fuel metering accuracy by measuring the pressure differential across the fuel injector and varying the duty cycle (pulse width) of the injector to compensate for supply pressure variations. Furthermore, since the Lewis et al. system injects liquid gas, compensation must be provided for the vaporization of liquid gas fuel in the system upstream of the injector and in the injector itself.
Of course, numerous systems are known by which an engine may be operated solely with compressed gas as a fuel; see, for example, Dolderer U.S. Pat. No. 4,774,909, Reggiani U.S. Pat. No. 4,632,083, and Pagdin U.S. Pat. No. 4,617,904. Dolderer recognizes the problem that gas engines have been unable to match the efficiency of diesel engines and the difficulties that have been encountered in trying to do so, and like the Lewis et al. system, Dolderer injects gas fuel in a liquid state. No prior art device has successfully addressed the problems associated with the injection of gaseous fuels, into an engine, in a gaseous state and as the only fuel, so as to achieve efficiencies at or above those attainable by a conventional diesel engine.

Compressed natural gas injection system for gaseous fueled engines