By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.

1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of source/drain regions of transistors by using an embedded strained semiconductor material to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel, due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. Among others, the development or sophisticated adaptation of enhanced photolithography techniques, implantation processes, deposition techniques, etch processes and many other processes may be necessary with the advance to every new technology node.
Therefore, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to an advanced technology node while avoiding or at least postponing many of the above process developments and adaptations associated with device scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region by, for instance, producing a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for future device generations since, for example, strained silicon may be considered as a "new" type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials and manufacturing techniques.
In one approach, the hole mobility of PMOS transistors is enhanced by forming an embedded strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. To this end, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Although this technique offers significant advantages in view of performance gain of the PMOS transistor and thus of the entire CMOS device, the corresponding process flow for forming the recesses and the respective etch and growth mask for covering the NMOS transistor may comprises a plurality of complex process steps, as will now described in more detail with reference to FIGS. 1a-1d.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a P-channel transistor 150p and an N-channel transistor 150n, which may be formed above a substrate 101 at appropriate substrate areas. In this manufacturing stage, the transistors 150p, 150n may each comprise a gate electrode 105 formed above a semiconductor layer 102 and separated therefrom by a gate insulation layer 104. Moreover, the respective gate electrodes may be covered by a capping layer 109, which is typically comprised of silicon nitride. As previously explained, the transistors 150p, 150n may represent field effect transistors of highly scaled semiconductor devices, wherein a gate length, i.e., the horizontal extension of the gate electrodes 105 in FIG. 1a, may be approximately 100 nm and significantly less. Consequently, in order to obtain an enhanced performance for the P-channel transistor 150p for a given gate length, strain may be created in the respective channel region 103 based on an embedded strained semiconductor layer to be formed adjacent to the gate electrode 105 of the P-channel transistor 150p, as will be described later on.
Typically, the semiconductor device 100 as shown in FIG. 1a may be formed according to the following processes. After forming a dielectric material for the gate insulation layers 104 by oxidation and/or deposition and after the deposition of an appropriate gate electrode material, such as polysilicon, an advanced patterning process on the basis of photolithography and anisotropic etch techniques may be performed to obtain the gate electrodes 105 as shown. In order to provide reliable encapsulation of the gate electrodes 105 during the further processing, an appropriate capping layer is usually deposited prior to the patterning of the gate electrodes 105, wherein a thickness of the corresponding capping layer may be selected such that an appropriate process margin is provided for the subsequent processing, that is, during the subsequent etch and epitaxial growth processes. Consequently, the capping layers 109 are provided on top of the gate electrodes 105 with a thickness corresponding to the process requirements, wherein, however, the thickness of the capping layers 109 may also be selected in accordance with requirements of the preceding patterning process, thereby also restricting the available range of thickness for the capping layers 109.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. A spacer layer stack comprising a silicon dioxide liner 107 and a silicon nitride spacer layer 106 is conformally formed above the first and second transistors 150p, 150n. Moreover, a resist mask 108 is formed above the N-channel transistor 150n, while exposing the P-channel transistor 150p.
The liner 107 and the spacer layer 106 may be formed on the basis of well-established techniques, such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) and the like. During the formation of the liner 107, which will act as an etch stop layer during an anisotropic etch process 110 for patterning the spacer layer 106, an appropriate thickness of the layer 107 is selected with respect to a reliable protection of the capping layers 109 and the semiconductor layer 102 during a respective extended over-etch time of the process 110, which may be required due to pattern dependent etch non-uniformities, which may also be referred to as microloading effects. Consequently, the initial thickness of the silicon dioxide liner 107 is selected in a range of approximately 10-20 nm in order to provide the required protection of the underlying materials during the anisotropic etch process 110. Thereafter, the spacer layer 106, comprised of silicon nitride, may be deposited on the basis of LPCVD and the like, with a thickness required for reliably encapsulating the second transistor 150n during a subsequent selective epitaxial growth process and also to define a specific offset for a cavity etch in the P-channel transistor 150p. Thereafter, the resist layer 108 may be formed on the basis of well-established photolithography techniques. Then, the device 100 is subjected to the anisotropic etch process 110 in order to form respective sidewall spacers on the gate electrode 105 of the P-channel transistor 150p to provide the required encapsulation for the subsequent selective epitaxial growth process. During the etch process 110, using appropriate process parameters, a highly anisotropic behavior of the etch process 110 may be obtained, for instance on the basis of fluorine-containing reactive components in combination with a specific plasma ambient, while a high etch selectivity with respect to the material of the liner 107 is simultaneously achieved. The pronounced selectivity of the etch process 110 may, however, be associated with a certain degree of non-uniformity and sensitivity to pattern density of circuit elements formed across the entire substrate 101, thereby resulting in a moderately non-uniform etch result. Consequently, a certain amount of over-etch time in the process 110 is applied in order to reliably expose the liner 107 across the entire substrate 101. At the same time, exposure of the semiconductor layer 102 and/or the capping layers 109 is to be maintained at a low level in order to not unduly affect the uniformity of the subsequent cavity etch process. Thus, a more or less reduced uniformity of the oxide liner 107 after the completion of the etch process 110 may therefore also affect the finally obtained etch result in the subsequent cavity etch process. Additionally, the characteristics of the respective spacers formed during the anisotropic etch process 110, i.e., their finally obtained width as well as the degree of coverage of the sidewalls of the gate electrode 105, may also be affected by the required over-etch time and thus the thickness of the spacer layer 106 and also the capping layers 109 may not be selected independently from each other, but may have to be selected on the basis of the requirement for efficient protection during the subsequent processing.
FIG. 1c schematically illustrates the semiconductor device 100 after the completion of the above-described process sequence and after a further plasma-based resist strip etch process for removing the resist mask 108. Hence, the device 100 comprises respective spacer elements 106A, including the liner 107 formed on sidewalls of the gate electrode of the P-channel transistor 150p, while the N-channel transistor 150n is still covered by the liner 107 and the spacer layer 106. As explained above, a respective spacer width 106W as well as a residual thickness 107T of the liner 107 after the etch process 110 may depend on the specifics of the etch process and may vary due to the above-explained etch non-uniformities. Thereafter, the device 100 is subjected to a further etch process for removing the exposed portions of the residues of the liner 107, which may have a significantly reduced thickness, i.e., the thickness 107T, compared to the initial thickness, which may be accomplished on the basis of high frequency plasma-based techniques. Thereafter, the device 100 may be subjected to a cleaning process on the basis of an appropriate wet chemical chemistry for efficiently removing any contaminants resulting from the previous process steps. Any contaminants or surface irregularities, caused by the preceding etch processes, may otherwise significantly influence the subsequent cavity etch process, thereby resulting in non-uniformities, which may then also translate into respective non-uniformities during a subsequent selective epitaxial growth process.
FIG. 1d schematically illustrates the device 100 after the completion of the above-described process sequence, wherein here the device 100 is exposed to a further etch process 112 for forming a respective recess or cavity 111 adjacent to the gate electrode 105 on the basis of the sidewall spacers 106A. The etch process 112 may be designed as an isotropic etch process, an anisotropic etch process or as any mixture thereof, depending on the desired size and shape of the recess 111. Due to any process non-uniformities, especially during the etch process 110 for patterning the sidewall spacers 106A, the etch process 112 may also result in corresponding etch non-uniformities, i.e., the depth of the cavity 111 as well as the resulting surface roughness may vary across the substrate 101. Since the etch process 112 and thus the finally obtained depth and shape of the recess 111 may be controlled for a given etch recipe on the basis of the etch time only, any previously produced non-uniformities may significantly determine the finally obtained across-substrate uniformity in addition to any further process non-uniformities of the cavity etch process 112 itself.
After the etch process 112 and after any cleaning processes for removing contaminants from exposed portions of the semiconductor layer 102, a corresponding selective epitaxial growth process may be performed on the basis of established recipes in order to provide a strained semiconductor material in the recess 111, for instance a silicon/germanium layer, thereby providing a desired degree of strain in the adjacent channel region 103. However, any non-uniformities of the respective recesses 111 may thus also translate into respective non-uniformities of the generated strain, since the shape and depth of the recess 111 and thus the amount of strained semiconductor material and its location may be determined by the configuration of the recess 111. As a consequence, a corresponding nonuniformity of transistor characteristics may result. Thus, a plurality of highly complex process steps are required while the requirements for enhanced device performance uniformity may significantly affect process flexibility with respect to the characteristics of the recess 111.
In view of the situation described above, there exists a need for an improved technique for the formation of recesses in advanced transistor elements while avoiding or at least reducing one or more of the problems identified above.

Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process


An LSI design method includes (a) performing an arrangement wiring on a plurality of macro blocks, (b) performing a timing analysis on the plurality of macro blocks based on the result of the arrangement wiring, and (c) designing an inside portion of each of the plurality of macro blocks based on the result of the timing analysis.

1. Field of the Invention
The present invention relates to an LSI design method including a plurality of macro blocks. More particularly, the present invention relates to an LSI design method, which never produces a timing error having influence on an entire specification of an LSI function, after design of a layout and a circuit of detailed portions.
2. Description of the Related Art
A conventional LSI design method including a plurality of macro blocks is described with reference to attached drawings. FIG. 1 is a flowchart showing a flow of the conventional LSI design method.
At first, in an LSI function specification determining step 21, a function specification to be defined as the LSI is determined. Next, the function specification is divided into a plurality of function modules. Then, in a function module designing step 22, all the function modules of the LSI are designed.
Next, in a layout step 23, a mask layout on the entire LSI is performed. Moreover, in a timing analysis step 24, a timing analysis as to whether or not the layout circuit satisfies a desirable timing specification is performed based on the layout result.
As a result of the timing analysis, if the desirable timing is not obtained and a timing error is brought about, the operational flow returns back to any one of the LSI function specification determining step 21, the function module designing step 22 and the layout step 23, on the basis of content of the timing error. Again, the design is tried.
In the above-mentioned conventional LSI design method, the timing analysis 24 between the function modules or a delay analysis can not be performed, unless the layout 23 for the entire LSI is executed after completion of all the function module designs 22. If the timing error occurs at the timing analysis step 24, the operational flow returns back to any one of the LSI function specification determining step 21, the function module designing step 22 and the layout step 23, on the basis of the content of the timing error. Again, the design is tried.
Especially, if the timing error can not be solved only by retrying the layout 23 or the function module design 22 and further the review of the timing of the entire system is required and thereby the LSI function specification determination 21 must be retried, the design must be retried from the original stage, at the final stage of the LSI design. Thus, this results in the large retrial, and also leads to the increase of a design time.
Japanese Laid Open Patent Application (JP-A-Heisei-5-197774) discloses the following method of modifying a circuit. A circuit generator having a high level synthesizer which receives an operational specification and prepares an inner representation based on its specification is provided with an input output interface device, an analysis modification managing device and a synthesis modification executing device. The synthesis modification executing device prepares a floor plan of a circuit based on the input operational specification, and checks it based on a constraint item. If there is a violation, the analysis modification managing device analyzes it, and outputs a modification plan.
Japanese Laid Open Patent Application (JP-A-Heisei 9-153084) discloses the following method of automatically designing LSI. After an input of a net list between function macros, a schematic layout process for the function macro is done based on this net list, and a physical specification of the function macro is determined on the basis of the schematic layout. Then, a logically synthesizing process is done based on the determined physical specification, and the layout is performed on the logic obtained from the logical synthesis, based on the schematic layout of the function macro. Thus, the retrial of the circuit synthesis and the like can be extremely reduced by watching out the layout from a stage of a function design for upper layer in which a gate level is not determined. Hence, it is possible to complete the layout design of LSI, in which a delay time and an area of the LSI are optimal, in a short time.
Japanese Laid Open Patent Application (JP-A-Heisei 10-171857) discloses the following method of designing an integrated circuit. Various modules usable as components of design target are registered as parameterized models. Database is prepared in advance for accumulating therein an instance generation information indicative of a procedure of generating an instance for the various modules and an index calculation information indicative of a manner of calculating a design quality index for each abstract. Then, this database is used to design the orientation of a floor plan. That is, also in a high level of an operational level and an RT level, the design quality indexes of the various modules used for the design are calculated by using the database. Then, they are used to execute the floor plan. In accordance with the execution result, the design quality indexes of a circuit size, a delay time and a consumption power of the design target and the like are calculated to accordingly judge whether or not the change of the design is required (whether or not the design specification is satisfied).
The present invention has been made to solve the above-described problems of the conventional LSI design method. An object of the present invention is to provide an LSI design method of performing a timing analysis at an early stage of LSI design to avoid an occurrence of large retry. Another object of the present invention is to perform a timing analysis on an entire LSI before designing an RT (Register Transfer) level of a function module to avoid the change of the specification, the change of the circuit and the re-layout of the entire LSI resulting from a timing error immediately before the end of the LSI design.
In order to achieve an aspect of the present invention, an LSI design method, includes (a) performing an arrangement wiring on a plurality of macro blocks, (b) performing a timing analysis on the plurality of macro blocks based on the result of the (a) step, and (c) designing an inside portion of each of the plurality of macro blocks based on the result of the (b) step.
In this case, the (b) step includes performing the timing analysis in consideration of a wiring capacitance and a wiring resistor corresponding to the result of the (a) step.
Also in this case, the (c) step includes performing a register transfer level design, a circuit design and a layout design on the inside portions such that the plurality of macro blocks satisfy timing restrictions corresponding to the result of the (b) step, the timing restrictions being given to the plurality of macro blocks.
Further in this case, the (c) step includes performing, after performing the register transfer level design, the circuit design and the layout design on the inside portions as a specific performing, performing a second timing analysis whether the plurality of macro blocks satisfy the timing restrictions based on the result of the specific performing, and performing one of the register transfer level design, the circuit design and the layout design on the inside portions again, when the timing restrictions are not satisfied as the result of the second timing analysis.
In this case, an LSI design method further includes (d) determining a function specification of an LSI, (e) dividing the LSI into the plurality of macro blocks based on the function specification, and (f) determining a size and a shape of each of the plurality of macro blocks to perform a floor plan on an entire portion of the LSI, and wherein the (d), (e), and (f) steps are performed before the (a) step is performed.
Also in this case, when a predetermined timing restriction is not satisfied as the result of the (b) step, at least one of the (d), (e) and (f) steps is performed again.
Further in this case, at least one of the plurality of the macro blocks is a macro block, as a post-designed macro block, of which a design is performed, and the (c) step includes designing the inside portion of one other than the post-designed macro block of the plurality of macro blocks.
In order to achieve another aspect of the present invention, an LSI design method, includes (g) performing a function specification design of an LSI, (h) performing an arrangement wiring on a plurality of macro blocks for the LSI based on the result of (g) step, (i) performing a timing analysis on the plurality of macro blocks based on the result of (h) step, (j) performing a design and a wiring on an inside portion of each of the plurality of macro blocks based on the result of (i) step, (k) performing a arrangement on the plurality of macro blocks for the LSI without performing a wiring on the plurality of macro blocks based on the result of (g) step, (l) performing a design on an inside portion of each of the plurality of macro blocks, (m) performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks after the (k) and (l) steps are performed, wherein the first and second wirings are performed at a same time to each other, and (n) performing a timing analysis on the plurality of macro blocks after the (m) step is performed, and wherein a first LSI design process includes the (h), (i) and (j) steps and a second LSI design process includes the (k), (l), (m) and (n) steps, and one of the first and second design processes is performed selectively.
In this case, the first design process is performed selectively when the LSI is a LSI in which a timing required is more critical than a predetermined value as the result of the (g) step.
Also in this case, the first design process is performed selectively when a circuit size of the LSI is larger than a predetermined size, as the result of the (g) step.
Further in this case, the second design process is performed selectively when a layout density of the LSI is larger than a predetermined density, as the result of the (g) step.
In order achieve still another aspect of the present invention, an LSI design method, includes (o) performing a floor plan on a plurality of macro blocks for an LSI, (p) performing an arrangement on the plurality of macro blocks, (q) performing a wiring on the plurality of macro blocks, (r) performing a timing analysis on the plurality of macro blocks based on the result of the (q) step to perform a design and a wiring on an inside portion of each of the plurality of macro blocks based on the timing analysis when the wiring as the result of the (q) step fits into a predetermined chip size, and (s) removing the wiring as the result of the (q) step and performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks, wherein the first and second wirings are performed at a same time after performing a design of the inside portion of each of the plurality of macro blocks when the wiring as the result of the (q) step does not fit into the predetermined chip size.
In order achieve yet still another aspect of the present invention, an LSI design apparatus, includes a first section performing an arrangement wiring on a plurality of macro blocks, a second section performing a timing analysis on the plurality of macro blocks based on the result of the arrangement wiring, and a third section designing an inside portion of each of the plurality of macro blocks based on the result of the timing analysis.
In this case, the second section performs the timing analysis in consideration of a wiring capacitance and a wiring resistor corresponding to the result of the arrangement wiring.
Also in this case, the third section performs a register transfer level design, a circuit design and a layout design on the inside portions such that the plurality of macro blocks satisfy timing restrictions corresponding to the result of the timing analysis, the timing restrictions being given to the plurality of macro blocks.
Further in this case, the third section performs, after performing the register transfer level design, the circuit design and the layout design on the inside portions as a specific performing, a second timing analysis whether the plurality of macro blocks satisfy the timing restrictions based on the result of the specific performing, and performs one of the register transfer level design, the circuit design and the layout design on the inside portions again, when the timing restrictions are not satisfied as the result of the second timing analysis.
In this case, an LSI design apparatus, further includes a fourth section determines a function specification of an LSI, a fifth section divides the LSI into the plurality of macro blocks based on the function specification, and a sixth section determining a size and a shape of each of the plurality of macro blocks to perform a floor plan on an entire portion of the LSI, and wherein the operations of the fourth, fifth, and sixth sections are performed before the operation of the first section is performed.
Also in this case, when a predetermined timing restriction is not satisfied as the result of the operation of the second section, at least one of the operations of the fourth, fifth and sixth sections is performed again.
Further in this case, at least one of the plurality of the macro blocks is a macro block, as a post-designed macro block, of which a design is performed, and the third section designs the inside portion of one other than the post-designed macro block of the plurality of macro blocks.
In order to achieve another aspect of the present invention, an LSI design apparatus, includes a first unit performing a function specification design of an LSI, a second unit performing an arrangement wiring on a plurality of macro blocks for the LSI based on the result of the operation of the first unit, a third unit performing a timing analysis on the plurality of macro blocks based on the result of the operation of the second unit, a fourth unit performing a design and a wiring on an inside portion of each of the plurality of macro blocks based on the result of the operation of the third unit, a fifth unit performing a arrangement on the plurality of macro blocks for the LSI without performing a wiring on the plurality of macro blocks based on the result of the operation of the first unit, a sixth unit performing a design on an inside portion of each of the plurality of macro blocks, a seventh unit performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks after the operations of the fifth and sixth units are performed, wherein the first and second wirings are performed at a same time to each other, and a eighth unit performing a timing analysis on the plurality of macro blocks after the operation of the seventh unit is performed, and wherein a first LSI design process unit includes the second, third and fourth units and a second LSI design process unit includes the fifth, sixth, seventh and eighth units, and one of the first and second design process units performs selectively.
In order to achieve still another aspect of the present invention, an LSI design apparatus, includes a floor plan unit performing a floor plan on a plurality of macro blocks for an LSI, a arrangement unit performing an arrangement on the plurality of macro blocks, a wiring unit performing a wiring on the plurality of macro blocks, a timing analysis unit performing a timing analysis on the plurality of macro blocks based on the wiring to perform a design and a wiring on an inside portion of each of the plurality of macro blocks based on the timing analysis when the wiring fits into a predetermined chip size, and a removing unit removing the wiring and performing a first wiring between the plurality of macro blocks and a second wiring on the inside portion of each of the plurality of macro blocks, wherein the first and second wirings are performed at a same time after performing a design of the inside portion of each of the plurality of macro blocks when the wiring does not fit into the predetermined chip size.
In order to achieve yet still another aspect of the present invention, a computer readable recording medium for recording a program for a process, includes (t) performing an arrangement wiring on a plurality of macro blocks, (u) performing a timing analysis on the plurality of macro blocks based on the result of the arrangement wiring, and (v) designing an inside portion of each of the plurality of macro blocks based on the result of the timing analysis.
An LSI design method in the present invention, in an LSI design method including a plurality of macro blocks, comprises: a step of performing an arrangement wiring on a plurality of macro blocks; a step of performing a timing analysis between the plurality of macro blocks based on the result of the arrangement wiring; and a step of designing the inside of the macro block based on the result of the timing analysis.
Another LSI design method in the present invention, in an LSI design method including a plurality of macro blocks, selects between a first LSI design method includes: a step of performing an arrangement wiring on a plurality of macro blocks; a step of performing a timing analysis between the plurality of macro blocks based on the result of the arrangement wiring; and a step of wiring the inside of the macro block based on the result of the timing analysis, and a second LSI design method includes: a step of performing only an arrangement without wiring a plurality of macro blocks; a step of designing the inside of the macro block; a step of performing only arrangement on the macro block; a step of designing the inside of the macro block, and a step of simultaneously performing the wiring between the macro blocks and the wiring within the macro block after the above-mentioned steps; and a step of performing a timing analysis after the wiring step, based on a function specification of the LSI.
Still another LSI design method in the present invention, in an LSI design method of performing a layout so that a plurality of macro blocks are mounted in a predetermined chip size, determines a floor plan for each of the plurality of macro blocks, and performs the arrangement between the macro blocks and the wiring between the macro blocks. If the wiring between the macro blocks is accommodated in the predetermined chip size, a timing analysis between the plurality of macro blocks is performed based on the result of the wiring between the macro blocks, and the inner design of the macro block and the inner wiring of the macro block are performed based on the result of the timing analysis. If the wiring between the macro blocks is not accommodated in the predetermined chip size, the wiring between the blocks is stripped off. Then, the wiring between the macro blocks and the inner wiring of the macro block are simultaneously performed after the completion of the inner design of the macro block.

LSI design method which never produces timing error having influence on entire specification of LSI function, after design of layout and circuit of detailed portion


An electronic packaging module for bonding of power semiconductor devices is produced. The semiconductor device is mounted on a base, and enclosed by a frame and lid. The lid is an insulating substrate having a conductive pattern with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the metallization pads of semiconductor devices. The metal protuberances are bonded to the semiconductor device joining it to the lid, and through the conductive pattern of the lid connecting the device to the input/output contacts of the package.

Power semiconductor devices include power field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), power transistors, power diodes, and power gallium arsenide transistors (GAs). In the past the common package for power semiconductor chips was the TO-3 can. The TO-3 package has a number of disadvantages. The wire bonds inside the package and the wires extending through the can have significant impedance the wire bonds have resistance which add to the on-resistance of the device. As chip designs have been improved to lower the resistance of the device, the resistance of the aluminum wires has become a large percentage of the total resistance of the package. The packaging efficiency of the TO-3 can is poor since the package is many times larger in surface area, volume and weight than the semiconductor chip it contains.
In the packages for logic semiconductors, the flip chip or C4 (Controlled Collapse Chip Connection) has achieved the lowest impedance by eliminating wire bonds, and the highest packaging efficiency, up to 90% for a 10 mm.times.10 mm die. The flip chip and C4 packages use specially prepared "bumped" chips with metallization built up on the contact pads to provide bumps for solder connection or connection by solder coated balls to the package.
Many power semiconductor chips come with a solderable back contact and aluminum metallization on the top surface. Solder can't be used on aluminum pads. Power semiconductor chips have been bumped using wire bonding machines to form multiple bumps on aluminum contact pads of the chips. A gold wire ball bond is made on the contact pad, as in conventional wire bonding, but the wire is severed at the ball bond, and the ball remains on the contact pad as a gold bump.
In one proposed package for power semiconductor chips, the chip is bonded to a metallic base; also bonded to the base is a frame which surrounds the chip. An alumina ceramic lid, provided with holes containing copper balls for contact to the chip, is bonded to the frame over the chip. The copper balls are soldered to the gold bumps on the chip and make contact through the lid to copper foils bonded to the outer alumina surface. Since the metallic base is bonded to the bottom of the frame, and the alumina lid is bonded over the top of the frame there is a height tolerance problem, because the height of the frame must compensate for any variation in flatness of the internal components of the package. To overcome this problem it has been proposed to make the alumina lid somewhat smaller than the frame and a ring of free standing copper foil between the frame and the lid would form a somewhat flexible medium to take up variations in the height of the package.
In other proposed packages, a copper foil is bonded to the wire bond gold bumps on the chip and part of the foil is formed into tabs which in one variation are insulated on one side with polyimide and then folded over to make contact with copper balls in the lid. In another variation foil tabs are bought out through the lid of the package, and the package hermetically sealed by soldering the foil tabs to copper foil lands bonded to the lid.
The mismatch of the thermal expansion coefficients of alumina and the copper foil leads to failure mechanisms that affect the adhesion of copper foil to the substrate and the hermetic seal of the package. When the copper foil is joined to the copper balls, the copper foil is deformed, stressed and thinned; it is subject to the further stress of thermal mismatch leading to breaks and stress corrosion.
Miniature flexible circuits have been designed to provide packaging efficiencies similar to the C4 process. The flexible circuits can be used with conventional integrated circuits having perimeter contacts. Gold conductors of the flexible circuit are thermosonically bonded the integrated circuits contacts. The conductors of the flexible circuit don't fan out from the integrated circuit contacts into the area around the chip, instead the conductors fan in underneath the chip terminating in a grid array of metal bumps underneath the chip for interconnection to second level packaging. The flexible circuit is bonded to the chip with an elastomeric adhesive 0.15 mm (6 mil) thick. The organic elastomeric adhesive and flexible circuit materials limit the temperature range in manufacture and use, do not permit good thermal transfer, make the package sensitive to moisture, and prevent use as hermetically sealed packages.


A filtration method, that includes: (A) filtering a liquid having particles with a resin media filter; and (B) applying ultrasonic waves at a frequency of at least 30 kHz to the resin media filter during the filtering (A) or after completion of the filtering (A) to regenerate the resin media filter, where: i) a material of the resin media filter is nylon, polycarbonate, polytetrafluoroethylene (PTFE), polysulfone, polyether sulfone, and/or cellulose, ii) for the regeneration of the resin media filter, the applying results in a filter regeneration ratio of at least 0.40; iii) on a surface of the resin media filter, a support material comprising a mesh resin layer is disposed; and iv) the resin media filter is present in a filter housing having a three-dimensional shape and an ultrasonic vibrator, which generates the ultrasonic waves, is present on a lateral side of said filter housing.

In polishing employing a polishing composition and a polishing pad, demands for a polished surface with high smoothness free from defects is increasingly high year by year. Along with such a tendency, the particle size of abrasive grains contained in a polishing composition becomes smaller. Further, in general, the particle size of abrasive grains is distributed, and if coarse particles which are extremely large relative to the aimed particle size are contained, such coarse particles will lead to surface defects such as scratches, and accordingly they should be removed.
Such coarse particles dispersed in a liquid medium are usually removed by a filter. In order to capture the coarse particles efficiently, it is desired to use a filter having a smaller aperture. However, the smaller the aperture of a filter, the more clogging is likely to occur. If clogging occurs, the efficiency in removal of the coarse particles tends to be deteriorated and finally, the filter will no longer be used. Accordingly, a filtration method with which clogging is less likely to occur, or a method of easily eliminating the clogging if occurred, has been desired.
From such a viewpoint, various filtration methods have been studied. Patent Document 1 discloses a filter for filtration of a fluid with an increased efficiency, by directly applying ultrasonic vibration to suppress an increase in the viscosity of the fluid, or by vibration, and a filter to which back pressure cleaning is easily conducted, if the filter is clogged, by directly applying vibration to the filter thereby to decrease the viscosity of a fluid with which the filter is clogged, or thereby to break the fluid by vibration.
Patent Document 2 discloses a liquid filtration method, which comprises subjecting a liquid to filtration while continuously or intermittently applying ultrasonic waves.
Patent Document 3 discloses a filtration apparatus comprising a filter such as a hollow fiber membrane, a nonwoven fabric, an open cell sponge, fibers or particles contained in a housing, wherein ultrasonic vibrators are respectively provided to two facing edge faces of the housing, at such positions that the phases of ultrasonic waves generated by the vibrators will not coincide with each other.
The above documents disclose to utilize ultrasonic waves for the purpose of improving the filter property, but failed to provide a method effective for a step of removing coarse particles (several hundred to several thousand nm) in polishing composition particles of from several ten to several hundred nm.

Filtration method, method for purifying polishing composition using it, method for regenerating filter to be used for filtration, and filter regenerating apparatus


An image forming apparatus includes an image forming unit, a waste toner accommodating unit, a movement member, and a driving mechanism. The image forming unit forms an image by using a toner. The waste toner accommodating unit accommodates a waste toner after being used in the image forming unit. The movement member is supported so as to move in a direction parallel with a falling direction of the waste toner in a toner falling path, through which the waste toner falls, of a movement path of the waste toner that moves from the image forming unit to the waste toner accommodating unit. The driving mechanism reciprocates the movement member in the direction parallel with the falling direction of the waste toner.

The technology of the present disclosure relates to an electrophotographic image forming apparatus which performs image forming by using a toner.
In general, in an electrophotographic image forming apparatus such as a copy machine, a printer, and a facsimile, an electrostatic latent image formed on an image carrying member such as a photosensitive drum is visualized by a developer (a toner) in a developing device, and the toner image is transferred to a recording medium. At this time, since a toner not transferred to the recording medium remains on the surface of the photosensitive drum, the remaining toner is removed from the surface of the photosensitive drum by a cleaning device. The remaining toner removed from the surface of the photosensitive drum is horizontally conveyed to an end portion in a horizontal direction by a screw as a waste toner, is fallen from the end portion, and is put into and stored in a disposal bottle.
The waste toner that is removed from the surface of the photosensitive drum has a low fluidity due to mechanical stress or mixing of impurities such as paper powder, and is easily solidified. Therefore, there is a case in which the waste toner is solidified and clogged on a conveying path of the waste toner.
Conventionally, there has been known a technology for allowing a leaf spring to intermittently make contact with a toner stirring and conveying blade of a rotating conveying auger of a developing device so as to vibrate the blade, and loosening a toner piled on a falling conveying path, through which a toner is supplied to a developing unit, by using the vibration.


An automatically openable and closeable gate system that will find primary use with the street curb opening to a catch basin or vault of a storm drain system, and for other similar openings, the system having a gate which during dry and low-flow water drainage situations will be in a closed position such that items of trash, debris, litter, leaves and the like will be prevented from entering the basin, vault or system, yet in periods of heavy rainfall or other heavy water run-off situations will automatically open to allow free flow of water into the basis or vault to alleviate water accumulation in the adjacent street and other surrounding areas.

This invention relates generally to a gate system for use with a storm drain of the type typically found in the curb of a street. More particularly, this invention relates to such a system which during periods of low water flow is in a closed position to effectively prevent debris from entering into the storm drain, but which during periods of high water flow opens to allow the maximum amount of water to enter into the drain to alleviate the accumulation of water in the street and the surrounding areas.
What to do with excess runoff rain water has been an issue for urban planners and dwellers for a long time. Even in arid regions, the occasional heavy rainfall will create large volumes of run off that must be channeled effectively or flooding resulting in impassable roads at least or the loss of property and lives at worst may occur. In areas of high annual rainfall, effectively channeling that rainwater away from streets and homes is an absolute must
For this reason, almost every city in the civilized world has an extensive underground storm drain system. And the most common inlet to the entire system is the ubiquitous curbside opening that is built into the sidewalk curb along the street. Those openings typically lead to a rather large underground chamber, often called a vault, at one end of which there is a conduit that leads to the main storm drain pipe that is usually set under the paved road adjacent the vault.
These drain systems have proven very effective in channeling runoff storm water away from the streets and populated areas, and usually into an adjacent river or into the ocean. However, another ubiquitous part of urban life—street debris and litter—also finds its way into the storm drain system. For example, some cigarette smokers seem to believe that their cigarette butts are not litter to be deposited in a trash can, but something that can be thrown on the ground wherever they happen to be when they must discard the cigarette—thrown into the gutter as they walk along the sidewalk, or thrown out of the car as they drive along. These cigarette butts, which are not environmentally friendly and do not naturally degrade easily, invariably end up in the drain system and then into the river or ocean into which it drains. Other trash, from paper cups to hamburger wrappers to envelops, all find there way into the gutters, drain systems and ultimately river and ocean. And this is just the man-made debris. Naturally debris such as leaves and twigs are also commonly found in streets and gutters, and then make their way into the storm drain system when it rains, or when water from some other source makes its way into the street.
It is not just the introduction of these items into the drain system that is a problem. Most storm drain systems ultimately empty directly into a nearly body of water, often a river or the ocean. Also, the systems rarely include any type of intermediate water treatment facility, so what goes into the drain system usually ends up in river, lake or ocean, where it is unsightly and can be toxic.
Because the introduction of trash and other debris into the storm drain system is such a common occurrence, many street side drains are constructed with a sizeable open chamber into which the storm drain opening leads, with the conduit to the under-street pipe located at one end thereof. The purpose of this is to try to trap as much of the debris as possible in the vault, and only allow the water to run-off into the system. This has proven only partially effective. First, so much trash is often introduced into the vault that much of it gets into the system anyway. This is particularly true if there is an accumulation of trash in the vault when there is a heavy rainfall or other heavy flow of water into the vault. Second, this arrangement necessarily requires that the vault be periodically cleaned, and cleaning the vault cannot of course be done by the usual street sweeping equipment, but requires an entirely different piece of equipment with strong suction capability to literally vacuum the trash from the vault. Third, this arrangement is designed to allow the trash to accumulate in the vault in between cleanings, such that in a worst case scenario, the accumulated trash becomes so large that the drain becomes plugged wholly or partially, and flooding in the area occurs when it rains.
In light of these issues, various attempts have been made to prevent trash from getting into drain. For example, in some places, a sizeable plate has been securely attached over the drain opening, leaving only a little space for water to flow. This solution does prevent much of the trash from entering into the drain, but it also prevents much of the water as well, and essentially defeats the purpose of the large drain opening that was intended to prevent flooding during heavy water run off. Therefore, other attempts have been made to design a storm drain gate that would remain closed during periods of low water run off, but which would automatically open in periods of heavy water run off. One recent example is U.S. Pat. No. 6,972,088, to Yehuda, in which a Pivotal Gate For A Catch Basin Of A Storm Drain System is disclosed. That system uses a rather complex system involving a rotatable paddle wheel and interconnected wires that interplay to open the gate when sufficient water begins to flow into the drain. While it appears workable, this system may not be desirable for widespread installation given its complexity, which translates into higher initial cost and higher cost of upkeep. It is a given in any piece of machinery that the more moving and complex the component parts, the more costly to manufacture and install, and the more costly to maintain, and more likely to malfunction. Other prior art devices suffer from one or more of these drawbacks, as the design goals of simplicity, ease of installation, durability, low maintenance, and high effectiveness are difficult to achieve.
Therefore, there exists a need in the art for such a simple, effective gate system.


Exemplary embodiments of the present invention provide an image display device having a functional design and accomplishing high quality and marketability to attract customers' attention. Exemplary embodiments include an independent installation type image display device including a display panel having a transmissive screen, a support frame for inclinedly supporting the display panel so that, when the image display device is erected on a horizontal floor, an angle defined between the display panel and the bottom surface is an acute angle, a projector placed below the display panel to project an image on the screen of the display panel, a storage unit which stores image data of an image to be projected and is mounted to the projector to output the corresponding image data to the projector, and an optical mechanism to direct a projection beam emitted from the projector to the screen from the rear of the display panel to form the image on the screen.

Exemplary embodiments of the present invention relate to an image display device using a projector, which is suitable for displaying an advertisement, guide information, etc. at a store.
In department stores, supermarkets, general merchandise stores, etc., television-type image display devices have been widely used in place of posters, to introduce the stores or supermarkets or provide goods information to customers. Since these devices can repeatedly display various images as compared to the posters, by combining various moving images, an advertisement effect can be markedly enhanced. Therefore, the number of stores which adopt the image display devices gradually increases. These days, a large display device which displays an image on a screen using a liquid crystal projector has been developed. See related art documents Japanese Unexamined Patent Application Publication No. 9-154088 and Japanese Unexamined Patent Application Publication No. 2003-136892.


A baseball glove includes a palm side ply that has an inner face and a palm section, and a back side ply facing the inner face and connected to the palm side ply. A cushion sheet is attached to the inner face of the palm side ply, and has a palm portion substantially corresponding to the palm section, a plurality of finger portions extending upwardly from the palm portion, a plurality of webs each extending between two adjacent ones of the finger portions, a hill portion projecting from the palm portion, and a plurality of curved ribs each disposed along a respective one of the webs. The hill portion and the curved ribs have shock-absorbing foamed materials.

1. Field of the Invention
The invention relates to a glove, more particularly to a baseball or softball glove.
2. Description of the Related Art
Referring to FIGS. 1 and 2, a conventional baseball glove 1 has a glove body 10 including a palm side ply 11 that has a ball-catching region 111, and a back side ply 12 connected to the palm side ply 11 and cooperating with the same to define a hand-receiving chamber. The hand-receiving chamber has an opening 13 for insertion of a player's hand therein, and finger sections 121 for insertion of the player's fingers therein.
A player frequently has to catch high-speed balls either thrown by a teammate or batted by a batter. Further, since a baseball is hard, the baseball glove 1 and the hand of the player must absorb a great impact force during catching of a ball, so that the player's fingers are easily injured.

Baseball glove having a palm section provides with a cushion sheet


A substrate such as a semiconductor wafer is transferred to a plurality of process chambers so as to perform prescribed processes. An inspection chamber is air-tightly connected to each of the process chambers. The inspection chamber is provided with a handler which loads and unloads the substrate. A gate valve is disposed between each process chamber and the inspection chamber. By this gate valve, each chamber is air-tightly closed.

1. Field of the Invention
The present invention relates to a substrate processing apparatus for performing prescribed processes (such as performing a thin film growth process) for a semiconductor substrate used for producing a semiconductor device such as a VLSI. (Very Large Scale Integration) device and a substrate processing method.
2. Description of the Related Art
Thin film growth technologies for growing a thin film on the surface of a semiconductor substrate are one of the key technologies for enhancing the performance of semiconductor devices. In particular, thin film growth technologies using the CVD (Chemical Vapor Deposition) method have been widely employed.
Conventionally, substrate processing apparatuses of this type, such as a thin film growth apparatus, are designed to perform particular processes such as growing a thin film on the surface of a substrate, such as a semiconductor wafer. The thin film which has been formed on the substrate is evaluated by another apparatus in the next process after the substrate on which the thin film was formed on the surface thereof has been unloaded from the thin film forming apparatus (substrate processing apparatus).
Thus, it takes a long time for the result of evaluation of the thin film which has been formed on the substrate to be obtained.
However, in this case, while the substrate is being processed and evaluated, the surface of the thin film may be contaminated or the characteristics of the film may change.
In a single wafer processing apparatus, from the view point of quality assurance of a processed substrate, the evaluation of the process should be performed with a high frequency. Thus, when the substrate is evaluated by another apparatus, much labor and time are consumed. In addition, when the evaluation of the process result takes a long time, unnecessary processes will be continued for a defective substrate.

Substrate processing apparatus and substrate processing method


A released beam structure fabricated in trench and manufacturing method thereof are provided herein. One embodiment of a released beam structure according to the present invention comprises a semiconductor substrate, a trench, a first conducting layer, and a beam. The trench extends into the semiconductor substrate and has walls. The first conducting layer is positioned over the walls of the trench at selected locations. The beam is positioned with the trench and is connected at a first portion thereof to the semiconductor substrate and movable at a second portion thereof. The second portion of the beam is spaced from the walls of the trench by a selected distance. Therefore, the second portion of the beam is free to move in a plane that is perpendicular or parallel to the surface of the substrate, and could be deflected to electrically contact with the walls of the trench in response to a predetermined acceleration force or a predetermined temperature variation applied on the beam structure. Other beam structures such as a beam held at both ends, or a beam held in the middle are also possible. Several beam structures at different angles can be fabricated simultaneously and mechanical etching stops are automatically formed to prevent unwanted overstress conditions when manufacturing several beam structures at the same time. Beam structures can also be manufactured in three orthogonal directions, providing information on acceleration in any direction.

1. Field of the Invention
The present disclosure relates generally to a semiconductor released beam device, and in particular but not exclusively, relates to a semiconductor released beam device fabricated in trenches.
2. Description of the Related Art
Micro-electromechanical systems (MEMS) in semiconductors have arisen for various applications to sense temperature, pressure, strain, acceleration, rotation, chemical properties of liquids and gases, etc. Those MEMS structures are usually combined with other integrated circuits, such as metal oxide semiconductor (MOS) circuits or complimentary metal oxide semiconductor (CMOS) circuits, for analyzing and calculating the parameters sensed by MEMS. Therefore, the MEMS manufacturing processes are required to be compatible with the existing MOS or CMOS manufacturing processes such that the whole system is inexpensive, reliable, and compact.
Different MEMS structures in semiconductors have been proposed and developed for such various sensing purposes. For example, a released beam sensor was proposed in U.S. Pat. No. 5,917,226 for detecting temperature variation and an integrated released beam oscillator was proposed in U.S. Pat. No. 6,278,337. A similar released beam sensor was also proposed in U.S. Pat. No. 6,218,209 ('209 patent) for detecting acceleration and could be applied in airbag, anti-lock braking, or ride suspension systems for automobiles or in-flight aircraft monitoring systems.
The process sequence shown in the '209 patent includes the step of forming a sacrificial layer of material such as silicon dioxide above and in contact with a layer of material that serves as both an etch stop layer and a fixed contact layer, as shown in FIG. 1 of '209 patent. The layer of material that the released beam in formed from is located above and in contact with the sacrificial layer. The removal of the sacrificial layer in selected regions after the released beam material is patterned produced the structures that are used in sensor applications.
However, the released beam structure proposed in '209 patent could only detect the acceleration force in only one direction which is perpendicular to the surface of the substrate. Furthermore, even there is an etch stop layer under the sacrificial layer, there is no etch stop layer around the sides of the sacrificial layer and therefore it is difficult to control the etch process in the lateral direction when there are several released beam structures manufactured at the same time.

Integrated released beam layer structure fabricated in trenches and manufacturing method thereof


A first powerline communication device, associated with a first powerline communication network, determines a plurality of time intervals in a beacon period of the first powerline communication network based, at least in part, on variations in levels of interference from a second powerline communication network which shares a powerline communication medium with the first powerline communication network. The first powerline communication device determines at least one channel adaptation parameter for each of the plurality of time intervals in the beacon period to compensate for effects of the variations in the levels of interference from the second powerline communication network. The first powerline communication device applies the at least one channel adaptation parameter corresponding to one or more of the plurality of time intervals in the beacon period when transmitting data via the powerline communication medium.

Embodiments of the inventive subject matter generally relate to the field of communication networks, and, more particularly, to channel adaptation to compensate for interference from a neighbor powerline communication network on a shared powerline communication medium.
In a powerline communication (PLC) system, two or more PLC networks may utilize a shared PLC medium. For example, in a SoHo (small office/home office) environment, powerline wiring inside a dwelling unit may be shared by two or more PLC networks for providing connectivity between various devices. Multiple PLC networks may share the PLC medium using time division multiple access (TDMA), carrier sense multiple access (CSMA), etc. Such sharing of the PLC medium by multiple PLC networks can reduce the performance of PLC due to interference from neighbor PLC networks. For example, a transmission in a first PLC network may appear as interference to network devices in a second PLC network.

Channel adaptation to compensate for interference from neighbor powerline communication networks


A rack-mount data server includes a housing, a plurality of data server components supported by the housing, the components including at least one peripheral storage device, a logic chassis for the data server, at least one disk drive on which the data server stores files, and at least one power supply, and a plurality of racks coupled with the housing to accommodate the data server components, the racks including a first topmost rack accommodating the at least one peripheral storage device and a second rack accommodating the logic chassis, the housing supporting the second rack underneath the first rack as the second topmost rack. The data server also includes a front door and a top door, the top door and the front door being interlockable with each other such that when the top door and the front door are in their closed positions, one of the top door and the front door locks the other of the top door and the front door in its closed position. A security system monitors the closed and/or locked status of a number of components, including the front door.

1. Field of the Invention
The invention relates to computing devices, and more particularly, to packaging architectures for arranging and enclosing data server components.
2. Description of Related Art
Data servers are well-known in the art for linking computing resources within networks. Data server components, including hard disk drives, peripheral storage devices, power supplies, and logic components, are available in a variety of configurations.
A number of prior art data server configurations waste significant internal space, and thus are unnecessarily large, because the data server components are significantly spaced apart to allow room for repair and replacement tasks. Up to 40% of the internal space in some servers is empty, and thus wasted, for the sake of easy serviceability. Other configurations sacrifice ready access and serviceability for compactness, and are consequently extremely difficult to repair and maintain. Some smaller servers, for example, place peripheral storage devices and a logic chassis at the same level within the server, necessitating disassembly and/or removal of the storage devices to service the logic chassis, and vice versa. Additionally, many internal components of certain data servers can be accessed only from the side of the server for repair and/or maintenance. Accessing these components through the side of the server necessitates a two-to-three foot space between adjacent servers, rolling a server away from an adjacent server, and/or disconnecting a server from its power source. A need has arisen, therefore, for a data server that is both compact and serviceable, and that does not require side access for standard repair and maintenance.
Other typical data server configurations present a significant disadvantage in that the data server components that are accessed and used most often, e.g. peripheral storage devices, are placed at least partially at an operator-inconvenient location. Locating peripheral storage devices at floor level, for example, requires an operator to stoop down to supplement, swap or service the peripheral storage devices. A need has arisen, therefore, for a more user-friendly data server providing easier access to often-used components.
Additionally, many prior art servers are vulnerable to unauthorized access at a number of points, and/or provide inadequate safety/warning devices to indicate that access is being attempted to the interior of the data server which potentially could compromise the integrity of data stored on the server. A need has arisen, therefore, for a data server that minimizes the number of access points while providing effective securement and monitoring of those access points. In this regard, most prior art servers fail to prevent unauthorized removal of the server doors. A need has thus arisen for a server that simply but effectively prevents unauthorized door removal and/or access to the interior of the server.
Finally, a number of prior art servers fail to adequately control airflow through and past essential components of the server, causing heat buildup and thermal-induced failure. Recirculation of warm air through the server, for example, has been problematic in a number of previous devices. A need has arisen, therefore, for a server that provides better air circulation and thus more effectively cools the data server components.

Packaging architecture for a data server


A correlator used for spread spectrum communications which reduces consumed power. A signal extraction circuit (6) is provided for directly extracting phase information from an input signal which expresses two values of code data by each phase of a plurality of cycles. A signal transferring circuit (1) is connected to the signal extraction circuit (6) for transferring the phase information to a multiplying circuit (2) comprised of a plurality of multipliers. Signals in each cell of the signal transferring circuit (1) are multiplied by fixed coefficients within the multiplying circuit (2) and supplied to an adding circuit (3) for determination of a correlation peak value.

1. Field of the Invention
The present invention relates to a correlator which is used in spread spectrum communications, and more particularly, to a correlator with a reduced amount of consumed power (hereinafter referred to as "consumed power") by reducing circuit scale. Still more particularly, the present invention relates to a signal extraction circuit for directly drawing out phase information from an input signal which expresses two values ("1", "0") of code data by each phase of a plurality of cycles and a correlator of spread spectrum communications utilizing circuit.
2. Description of the Related Art
FIG. 18 is a schematic view showing waveforms of signals to be processed on transmitting side in a spread spectrum communications. FIG. 19 is a block diagram showing one example of a conventional correlator.
In spread spectrum communications, original transmitted baseband data D1 are multiplied by code data in PN (pseudo noise) code sequence (hereinafter referred to as "PN code data D2", and where, "0" of transmitted baseband data D1 is assumed to be -1), and multiplication data (transmitted baseband data D1.times.PN code data D2) is BPSK (binary phase shift keying) modulated to transmission signal D3, and is sent out to transmission path on the transmission side as shown in FIG. 18.
The PN code data D2 is "1" of transmitted baseband data D1 converted to, for example, the data of multiple bits (for example, 32 bits) of "1" and "0". "1" or "0" of this PN code data is called "chip" in spread spectrum communications. In BPSK modulation, the phase of the carrier is reversed at the leading edge and the trailing edge of PN code data D2, and "1" or "0" information of PN code data D2 is the transmission signal D3 expressed by the phase. To transmission signal D3, for example, 190 cycles are allocated per 1 chip of PN code data D2. Presently, if the signaling rate of transmitted baseband data D1 is 1 Mbps, chip rate of the PN code data D2 is 13 Mcps, chip length is 11 chips, and carrier frequency of transmission signal D3 is 2.4 GHz band.
On the receiving side, the above-mentioned transmission signal D3 is received, and using a frequency converter (not illustrated) such as down converter, etc., removing components of the carrier frequency and converted into signal corresponding to value of each chip of PN code data D2, and inputted into a correlator of a configuration as shown in FIG. 19 to demodulate and reproduce transmitted baseband data D1.
In the correlator shown in FIG. 19, numeral 1 is a signal transferring means utilizing CCD (charge coupled device), etc., where a signal having the components of the carrier frequency removed from inputted transmission signal D3 is taken in successively as data expressed by two values by clock signal .phi.1 of the frequency same as the chip rate of PN code data D2, and is outputted from each cell 1a while being transferred to each cell 1a of the signal transferring means 1. The two values are positive peak (+1) and negative peak (-1). The data (+1, -1) outputted from each cell 1a is multiplied by coefficient ("1" denoted to +1 and "0" denoted to -1) of the PN code (code corresponding to PN code data D2) previously set to each multiplier 2a.
Consequently, at the timing in which the data on the same list of coefficient of PN code data D2 are outputted from each cell 1a of the signal transferring means 1, multiplication result of each multiplier 2a becomes 1 (=+1.times.+1=-1.times.-1), and adding these by an adding means 3 causes addition output to achieve the peak value (correlation peak). For example, if chip length is 32 chips and number of cells of signal transferring means 1 is 32, the value of the correlation peak is 32.
Now, PN code data D2 corresponding to "0" of transmitted baseband data D1 is each reversed bit of PN code data D2, which corresponds to "1" of transmitted baseband data D1. Consequently, at the timing in which the same data as that of list of PN code data D2 corresponding to "0" of this transmitted baseband data D1 is taken in, multiplication result of each multiplier 2a is -1 (=+1.times.-1) and these are added at adding means 3, then peak value becomes negative. If the number of cells 1a is 32 as with the above-mentioned case, the value of the correlation peak is -32.
The correlation peak obtained from adding means 3, as described above, is identified as "1" when the correlation peak is positive and as "0" when it is negative, and restored and reproduced to the above-mentioned transmitted baseband data D1, and outputted to subsequent stage. As described above, by setting on correlator side a multiplication coefficient corresponding to PN code data D2 on the transmitting side, it is possible to take in transmitted baseband data D1 identified by relevant PN code data D2.
Data showing the correlation peak are inputted to a synchronous signal generator means 5, and clock signal generator means 4 is controlled by synchronous signal obtained in synchronous signal generator means 5, and phase of clock signal .phi.1 is controlled so as to match the phase of transmission signal D3.
By the way, as described above, because modulated transmission signal D3 has an extremely high carrier frequency, if it is inputted as it is into the correlator, clock signal .phi.1 operating the correlator must be matched to the frequency, but this may exceed the operating frequency limit of signal transferring means 1, and in addition, the number of cells 1a of signal transferring means 1 becomes enormous, resulting in extremely large power consumption.
Therefore, hitherto, as described above, transmission signal D3 has components of the carrier frequency removed first and converted to a signal correspond to PN code data by the frequency converter, and then taken in the correlator, but passing the signal to the frequency converter distorts waveforms by intermodulation, generates errors in extracting the transmitted baseband data D1 or requires a frequency converter, causing a problem of increased circuit scale.
Under these circumstances, the principal object of the present invention is to provide a signal extraction circuit which directly takes out phase information from the input signal expressing the two values of code data with the phase of a plurality of cycles and does not require a frequency converter, and a correlator that utilizes such signal extraction circuit. The other object of the present invention is to provide a correlator which does not need a frequency converter and which is designed to reduce consumed power.

Signal extraction circuit and correlator utilizing the circuit


Methods, systems, and computer program products for reducing communication overhead to make remote direct memory access more efficient for smaller data transfers. An upper layer protocol or other software creates a receive buffer and a corresponding lookup key for remotely accessing the receive buffer. In response to receiving a data message, the remote direct memory access protocol places a data portion of the data message into the receive buffer and prevents further changes. The upper layer protocol or software confirms that further changes to the receive buffer have been prevented. A lower layer transport protocol may be used to deliver data received from a remote system to the remote direct memory access protocol. Data transfers may occur through buffer copies with relatively lower overhead but also relatively lower throughput, or may occur through remote direct memory access to offer relatively higher throughput, but also imposing relatively higher overhead.

1. The Field of the Invention
The present invention relates to remote direct memory access. More particularly the present invention relates to methods, systems, and computer program products for reducing communication overhead between protocol layers to make remote direct memory access more efficient.
2. Background and Related Art
In computer systems, data frequently must be copied from one buffer to another. Without direct memory access (DMA), copy operations are performed by a computer system's central processing unit (CPU). While performing a copy operation, the CPU is unavailable for more important and more sophisticated operations. Accordingly, depending on the amount of data to copy, use of a CPU in buffer copy operations may lead to poor resource management and result in slow system performance.
In traditional DMA, the CPU programs a DMA engine to perform the buffer copy, such as by specifying a source address, a destination address, and a length to copy. The DMA engine then moves the data from one buffer to another, without further impact on CPU resources. When the buffer copy is complete, the DMA engine notifies the CPU.
FIG. 1 illustrates a remote DMA between host 100A and host 100B. In order to copy the contents of buffer 120A at host 100A to buffer 120B at host 100B, hosts 100A and 100B program remote network interface cards (RNICs) 110A and 110B to make the transfer, such as by identifying a source address at a particular host, a destination address at a particular host, and a length to copy. This frees, or reduces the utilization of, CPUs 130A and 130B at hosts 100A and 100B, making CPUs 130A and 130B more available for other activities. RNIC 110B receives the data and transfers it to buffer 120B, without using CPU 130B. Thus, RNICs 110A and 110B operate as remote DMA (RDMA) engines, with corresponding RMDA interfaces 112A and 112B. RDMA transfers use zero copy paths 124A and 124B, allowing for data transfer (throughput) at the rate of the network or fabric. As in traditional DMA, the RNICs notify the appropriate CPU when finished making the transfer.
Note that in FIG. 1 two additional paths from the RNICs 110A and 110B to buffers 120A and 120B are illustrated. Buffer copy paths 122A and 122B are directed to buffers 120A and 120B through intermediate private buffer pools 140A and 140B, respectively, whereas zero copy paths 124A and 124B directly connect to buffers 120A and 120B. Buffer copy paths 122A and 122B use CPUs 130A and 130B for copy operations. In other words, buffer copy paths 122A and 122B result in higher CPU utilization, meaning the CPU is less available to perform other operations. It also should be noted here that network throughput (data transfer at network speed) is increasingly likely to exceed the transfer rate available from an RNIC's CPU. Even so, one reason for the two separate paths relates to the communication overhead associated with zero copy paths 124A and 124B. Remote direct memory access using zero copy paths 124A and 124B introduces some amount of overhead to RDMA (e.g., the overhead to program RNICs 110A and 110B for an RDMA transfer). As described in more detail with respect to FIGS. 3A and 3B below, for small data transfers, this overhead may negate the faster data throughput that zero copy RDMA offers. In other words, for small data transfers, it may be faster to use the buffer copy path, and sacrifice CPU utilization at the RNIC, rather than use the zero copy path that RDMA offers.
Conventionally, the zero copy path overhead for RDMA has been relatively significant, requiring transfers on the order of 32 k bytes and above to justify its use. As can be appreciated, many networks frequently have data transfers of less than 32 k bytes, making zero copy RDMA less attractive for certain operations. Accordingly, methods, systems and computer program products are desired to reduce the communication overhead for zero copy paths so the performance benefits of faster data throughput can be used for relatively smaller data transfers.

Remote invalidation of pre-shared RDMA key


A method of making a binder for extruded, pelleted, or agglomerated animal feed. The binder is made by treating biomass such as soybean hull or lemon peels with an aqueous acidic solution for a time, at a temperature, and at a pH sufficient to yield a first mixture containing biomass solids and partially dissolved biomass; and mechanically treating the first mixture of step to yield a first mechanically treated mixture; and then incorporating the first mechanically treated mixture as a binder in an animal feed. Also described are animal feeds made using the binder.

Manufactured animal feeds are a staple product of commerce. A host of natural products, such as wheat gluten, high-gluten wheat flour, and other starch-rich ingredients (rice, sorghum, corn, etc.) are used as binders in animal feeds (e.g., feeds for ungulates and swine, poultry feeds, fish feeds, shrimp feeds, feeds for domestic pets such as cats and dogs, etc.). Modified substances such as carboxymethyl cellulose, alginate, propylene glycol alginate and lignin sulfonate, as well as synthetic binders such as sodium or calcium bentonite, polyvinyl alcohol, and urea formaldehyde have also been used as binders. They vary widely in cost, performance, and beneficial vs. adverse impacts on animal health.
For example, extrusion cooking devices have long been used to make a wide variety of dry animal feeds, such dry dog food, cat food, and poultry feeds. The basic process is very straightforward conceptually, but much more complex in practice. The food material to be processed is passed through a temperature-controlled extruder barrel where it is subjected to increasing levels of temperature, pressure, and shear. As the material emerges from the extruder die, it is fully cooked and shaped. The conventional practice is to subdivide the product into pellets as it exits the extruder using a rotating knife assembly. See, for example. U.S. Pat. No. 10,383,347, issued Aug. 20, 2019, which describes an extruded animal feed that comprises a gelatin binder and a low starch content.
Animal feeds made via extrusion (as well as via other methods) typically include a binder to improve internal cohesive strength of the extruded, pelleted product. The binder provides a host of functional advantages to the final product. Most notably, the binder brings the food portions of the feed ration together so that the final product can be readily ingested by the target animal. At the same time, it makes the pelleted or agglomerated final product less likely to fracture during shipment, storage, and dispensing. This greatly cuts down on the creation of dust and fines, which leads to waste. In the context of extruded feeds, starches and modified starches are widely used as binders because they gelatinize under the conditions typically encountered during extrusion, which helps adhere the food components to one another.
As a general proposition, animal feeds are produced with low-cost, by-product food ingredients that cannot be sold in the human food market. The conventional, low-cost binders, though, do not yield feed pellets that are sufficiently durable. In addition to starch, mentioned above, various protein colloids, carboxylmethyl cellulose, lignosulfonate-starch blends, and urea formaldehyde resins have been used as animal feed binders. U.S. Pat. No. 5,714,184, issued Feb. 3, 1998, even describes a method and composition of matter that uses sodium carbonate pulping liquor (from papermaking) as a pellet binder for animal feed.
See also U.S. Pat. No. 4,996,065, issued Feb. 26, 1991, which describes a molasses-free, chemically reactive binder for animal feed.
U.S. Pat. No. 4,988,520, issued Jan. 29, 1991, describes a binder comprising water-soluble calcium compounds, such as calcium hydroxide, calcium oxide, calcium chloride, and calcium acetate.
U.S. Pat. No. 4,952,415, issued Aug. 28, 1990, describes an animal feed composition that uses a polymer made from carboxylic acid-containing monomers as a binder, for example polymers made from polyacrylic acid, polymaleic acid, and polymethacrylic acid.
U.S. Pat. No. 4,153,735, issued May 8, 1979, describes a binder that contains a salt of a fatty acid, a hydrogenated lipid, and a water-soluble anionic polymer.
While some of these products do provide some improvement in pellet quality, there is much room for improvement.

Animal feed binders derived from pectin- and protein-containing feedstock

The United States of America, as Represented by the Secretary of Agriculture


A method for gaining access to and removing mechanical fasteners such as pedicle screws. A small arthroscopic incision is made over the location of the fastener. A guide wire is then placed into the incision and attached to the fastener. A series of progressively enlarging dilator tubes are slipped into the incision to progressively enlarge its diameter. A screw extractor tube is placed into the incision, over the largest dilator tube. The screw extractor tube is advanced until its lower extreme surrounds the head of the fastener. The dilator tubes are then removed. At this point, the screw extractor tube holds open the incision and provides access to the fastener through its hollow interior. A specially designed extractor tool is inserted into the screw extractor tube. An arthroscope is preferably also inserted through the screw extractor tube so that the surgeon can visualize the process. Jaws on the end of the extractor tool are clamped to the fastener's head. The extractor tool is then rotated to back out the fastener. Once the fastener is freed from its installed position, the extractor tool withdraws it through the screw extractor tube. Other conventional processes—such as debridement—may then be performed through the screw extractor tube. Finally, the surgeon withdraws the screw extractor tube and closes the small incision.

1. Field of the Invention
This invention relates to the field of orthopaedic surgery. More specifically, the invention comprises a process for removing orthopaedic hardware while using only a small incision.
2. Description of the Related Art
The field of orthopaedic medicine involves the application of plates and screws to stabilize compromised articulations in the human body. One typical application is stabilization of the lumbar vertebrae after collapse of one or more intervertebral disks. FIG. 1 is an illustration of two lumbar vertebrae 10. Intervertebral disk 11 lies between the two. In this example, instability of the spine has necessitated the joining of the two vertebrae.
It is well known in the art that vertebrae can be joined by bone grafting. However, it is generally necessary to stabilize the position of the two vertebrae for some period in order to allow the joining to occur. Accordingly, plate 12 is attached to the two vertebrae. Typically two plates 12 would be applied, with one lying on each side of the posterior spinous processes. Each plate 12 is pierced by a set of holes, through which pedicle screws 14 are inserted.
In order to install pedicle screws 14, holes must be drilled through the pedicle portions of the two vertebrae. Pedicle screws 14 are then threaded into these holes and tightened. If all goes well, the two vertebrae will eventually fuse together, thereby eliminating any articulation at the joint. The fusing will ideally render the patient asymptomatic, though obviously somewhat less flexible.
The ideal result is not always achieved, however. Those skilled in the art will know that great variations exist in human anatomy. They will also know that the surgeon is unable to fully visualize the structures involved. These factors may lead to imperfect results.
The reader will observe in FIG. 1 that nerve root 20 exits the foramen between the two vertebrae in a position which is close to the lower pedicle screw 14. A portion of this pedicle screw 14 may protrude beyond the surface of the lower vertebra 10 (As the vertebra comprises a highly irregular shape, the hole drilled therethrough may intersect the outer surface at one or more points. A portion of the threaded pedicle screw shaft may thereby be exposed). This portion may rest against nerve root 20, possibly even compressing nerve root 20. In such an event, the patient may experience common neurological symptoms, such as pain or numbness.
After the joint has stabilized, it may be desirable to remove pedicle screw 14 (as well as possibly plate 12). This operation has typically been performed under general anesthesia. A substantial incision is made through the skin 18, and fascia 16, to reveal the spinal column. The muscles and other structures attached to the posterior spinous processes must then be removed in order to expose pedicle screw 14. A wrench is then used to back pedicle screw 14 out of the bone and remove it through the open incision. It is often difficult to determine whether a particular pedicle screw is the source of the neurological symptoms experienced by the patient. As the patient is asleep during the procedure, there is no way to determine if the removal of the screw altered the symptoms until much later.
FIG. 2 shows another common factor in the placement of such hardware. The reader will observe that pedicle screw 14 is angularly displaced from the axial center of the hole through plate 12. This angular displacement is sometimes necessary in order to accommodate the shape of the vertebra. On other occasions, it is simply a result of the imperfect drilling process. Whatever the cause, the angular displacement may necessitate a larger incision since the socket head of the removing device must be aligned with screw head 22.

Method for removing orthopaedic hardware


A ground termination system may include a backshell for an electrical connector, a grounding insert and a ferrule. The grounding insert includes an outer peripheral edge and a centrally disposed aperture. The outer peripheral edge may be sized to fixedly engage a surrounding portion of the backshell and the centrally disposed aperture may be defined by a plurality of lobes. A first group of the lobes may be sized to receive power conductors of a variable frequency drive power cable. The ferrule may include a crimp barrel and a sleeve. The crimp barrel may receive a ground conductor and be rigidly clamped thereto. The sleeve of the ferrule may fixedly engage one of the lobes in the second group of lobes and anchor the ferrule in the aperture.

Variable frequency drive systems can use power electronics as motor drives. These systems may include a harness that includes primary power conductors run co-linearly with one or more ground conductors. The primary power conductors may include one or more cables, such as copper cables, that are twisted together in a bundle. The ground conductors may be bare wires, such as copper cables. The power and ground conductors may be twisted together in a bundle and sheathed within a shield to minimize cable inductance.

Ground termination system for a variable frequency drive harness


The brushhead includes an outer brushhead which is fixed in operation when the brushhead is attached to a skin brush appliance and an inner brushhead which oscillates in operation. The outer brushhead includes three spaced sections of elastomeric fingers and three spaced sections of tufts positioned, respectively, between the elastomeric finger sections. The inner brushhead includes a plurality of non-circular concentric rows of tufts.

Effective and efficient skin cleansing is important for facial skin health. A wide variety of appliances and brushhead configurations are known which collectively have advantages as well as disadvantages. An important consideration in effective skin cleansing with a power appliance is not only effective cleansing and the overall cleansing experience for the user, but also an effective and efficient flow of cleansing fluid to the active portion of the brushhead and the efficiency of fluid flow with residue away from the active portion of the brushhead. The brushhead disclosed herein has the characteristics of convenience and effectiveness in allowing fluid to flow to the active portion of the brushhead and then away therefrom during operation.

Cleansing brushhead for a facial skin cleansing appliance


The light emitting element lighting device in accordance with the present invention, includes: a light emitting unit including a light emitting element; and a power supply circuit configured to supply a supply voltage to the light emitting unit. The power supply circuit is configured to increase the supply voltage from a first voltage lower than a lighting start voltage of the light emitting element to a second voltage higher than the lighting start voltage to light up the light emitting unit. The power supply circuit is configured to, in a process of increasing the supply voltage from the first voltage to the second voltage, decrease a rate of increase in the supply voltage as the supply voltage gets closer to the second voltage.

Recently, development of an organic EL element which is a thin solid light emitting element has been promoted. For example, a lighting device employing such an organic EL element as its light source has been proposed (e.g., see document 1 [JP 2007-265805 A]).
The lighting device disclosed in document 1 includes a light emitting unit constituted by organic EL elements, and a DC power source configured to supply a desired DC voltage to the light emitting unit. However, the organic EL element has a capacitance component. Therefore, there is a problem that application of a voltage to the organic EL element is likely to cause an excess rush current to flow into the organic EL element.
In consideration of this problem, in the lighting device disclosed in document 1, an inductor which serves as a current limiting device is interposed between the DC power source and the organic EL element to decrease the rush current which flows through the organic EL element when a voltage is applied.
In the aforementioned prior lighting device, suppression of the rush current flowing through the organic EL element is achieved by the inductor connected between the DC power source and the organic EL element. However, connection of the inductor is likely to cause a distortion in a current waveform and an increase in a loss.

Light emitting element lighting device and lighting fixture using same

Panasonic Intellectual Property Management Co., Ltd.