An auto scan horizontal deflection apparatus comprising a voltage detecting circuit as an amplitude detecting winding arranged at a secondary side of a choke transformer and detects amplitude of a flyback pulse. A frequency discriminating circuit (frequency/voltage converting circuit) discriminates frequency of horizontal synchronizing signal, and a control signal generating circuit (adding circuit) generates a control signal controlling the power source voltage of a variable power circuit supplying a power source voltage to a horizontal output circuit through a primary winding of the choke transformer on the basis of the outputs of both circuits. It becomes possible for the apparatus to keep horizontal deflection width constant regardless of the horizontal deflection frequency without using a conventionally-used detection resistance whose electric power loss is large, thereby decreasing electric power loss and keeping the horizontal amplitude almost constant even when the horizontal deflection frequency is changed.

1. Field of the Invention
This invention relates to an auto scan horizontal deflection apparatus cable of obtaining constant, horizontal amplitude even when the horizontal deflection frequency is changed.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional auto scan horizontal deflection apparatus disclosed, for example, in Japanese Utility Model Application Laid-Open No. 63-56865 (1988). In the figure, reference numeral 1 designates a horizontal oscillation driving circuit to which a horizontal synchronizing signal is inputted from an exterior image apparatus through an input terminal IT, and numeral 2 designates a horizontal output circuit (driven by the output of the horizontal oscillation driving circuit 1.
In the horizontal output circuit 2, the symbol Q designates a switching transistor which is switched by the output of the horizontal oscillation driving circuit 1, and D1 designates a damper diode thereof. The symbol L designates a horizontal deflection coil, and C designates a resonance capacitor connected with the horizontal deflection coil L in parallel.
In addition, a plurality of dummy coils Ld, each of which can be short-circuited by a switch S1, are connected in series with the horizontal deflection coil L, and a plurality of dummy capacitors Cd, each of which is grounded at its one end through a switch S2, are connected in parallel with the resonance capacitor C.
Symbol Cs designates an S-form compensation capacitor connected in series with the horizontal deflection coil L, and R designates a detection resistance connected in series with the S-form compensation capacitor Cs in order to detect horizontal deflection current I flowing through the horizontal deflection coil L.
Reference numeral 3 designates a peak rectifier circuit which detects voltage drop between both of the terminals of across the detection resistance R, and 4 designates a variable power circuit in which a source voltage Vcc to be outputted is controlled with the output voltage of the peak rectifier circuit 3 being used as control signal.
Reference numeral 5 is a choke transformer supplying the source voltage Vcc to the horizontal output circuit 2 through a primary winding 5a from the variable power circuit 4, and a high-voltage output is outputted from a secondary winding 5b thereof through a diode Db.
Reference numeral 6 is a deflection mode switching circuit controlling opening/closing of the switches S1 and S2 inside of the horizontal output circuit 2, responsive to the frequency of title inputted horizontal synchronizing signal
Next, an explanation will be given of the operation of the circuit shown in FIG. 1. A plurality of dummy windings Ld which can optionally be short-circuited by the switch S1 are connected in series with the horizontal deflection coil L so that the power voltage Vcc of the horizontal output circuit 2 is not changed greatly when the frequency of the inputted horizontal synchronizing signal is changed.
In addition, at the resonance capacitor C, a plurality of dummy capacitors Cd are connected in parallel, each of whose one end being grounded respectively by the switch S2 so that the ratio Ts/Tr of the horizontal scanning time Ts to the horizontal flyback time Tr may be kept almost constant by changing the horizontal flyback time Tr.
These switches S1, S2 are switched according to frequencies of the inputted horizontal synchronizing signals of a television system (15 to 17 KHz), high density personal computer system (22 to 26 KHz), high density CAPTAIN (Character and pattern telephone access information network:videotex) system (29 to 34 KHz) and so on by the deflection mode switching circuit 6.
By the way, of background horizontal width of an image projected on a picture tube is decided by the horizontal deflection current I when the anode voltage of the picture tube is constant. The relation between the horizontal deflection current I and the source voltage Vcc of the horizontal output circuit 2 is shown in the following equation (1). ##EQU1##
Accordingly, variation of the horizontal width can be limited to a certain extent by changing the net inductance L+Ld including the horizontal deflection coil L at the horizontal scanning time Ts is changed with the horizontal deflection frequency. In order to make the horizontal width constant usually, however, it is required to control the source voltage Vcc by detecting the horizontal deflection current I.
Therefore, the detection resistance R is connected with the S-form compensation capacitor Cs and the voltage drop across this detection resistance R is detected by the peak rectifier circuit 3. The variable voltage circuit 4 is then controlled so that the value of the detected voltage drop may be constant, thereby adjusting the source voltage Vcc outputted therefrom.
In addition, as another prior art, the invention of Japanese Patent Application Laid-Open No. 62-5781 (1987), entitled as "a deflection circuit" has been proposed. The invention of this Japanese Patent Application Laid-Open No. 62-5781 (1987) is so constructed as to carry out almost a constant horizontal deflection by changing the electric source potential of the horizontal output circuit to be saw toothlike responsive to the input frequency of the horizontal synchronizing signal.
As a conventional auto scan horizontal deflection apparatus is so constructed as above-mentioned, in the former, electric power is largely lost according to the detection resistance R, and the deflection current I becomes large especially when a large-sized monitor is used, therefore electric power loss becomes great and cannot be neglected, these facts causing the apparatus to be an impractical one.
The latter arrangement has a possibility that the horizontal scan width changes when the input frequency of the horizontal synchronizing signal changes. Because it does not carry out feedback of the horizontal scan width.

Auto scan horizontal deflection apparatus


To provide an apparatus capable of stably performing a binding process on a sheet bundle which is set from the outside as having a setting portion arranged at an external cover of a sheet storing apparatus. In an apparatus including a setting portion arranged at an external cover as being capable of setting a sheet bundle from the outside, the setting portion includes a opening, a setting face on which sheets inserted through the opening are placed, and an abutting-regulating face which performs positioning of end edges of the sheets inserted, the opening is arranged at an open-close cover of the external cover, and the abutting-regulating face are arranged at an apparatus frame which is located at the inner side of the open-close cover.

1. Field of the Invention
The present invention relates to a sheet storing apparatus which stacks and stores image-formed sheets, and relates to improvement of a manual setting mechanism for performing a binding process on a sheet bundle which is manually inserted from the outside.
2. Description of Related Arts
In general, such an apparatus is arranged at the downstream side of an image forming apparatus. Such an apparatus has been widely used as a sheet storing apparatus which receives image-formed sheets and stacks and stores the sheets on a tray. Further, there has been also known a post-processing apparatus which stores, at a stack tray, sheets received from an image forming apparatus after performing a post-processing thereon such as a binding process, a folding process, and a bookbinding process.
Japanese Patent Application Laid-open No. 2005-096392 discloses a sheet storing apparatus which stacks and stores image-formed sheets as being connected to a sheet discharging port of an image forming apparatus. Here, it is proposed to adopt a mechanism for performing a binding process on a sheet bundle which is prepared offline by an operator while a manual binding portion for performing a binding process on a sheet bundle set from the outside is arranged at an external casing.
Further, Japanese Patent Application Laid-open No. 2010-159144 discloses a post-processing apparatus which performs a binding process on sheets fed from an image forming apparatus after stacking the sheets on a processing tray and stores the sheets on a stack tray at the downstream side.

Sheet storing apparatus and image forming system having the same


A plasma display panel where the address electrodes are designed to have perforated portions in the vicinity of display electrodes to prevent the build up of unwanted wall charges in the vicinity of the display electrodes to thus prevent mis-discharge in the plasma display panel. The perforations can be quadrilateral in shape, and can be made to different sizes depending on the color of the phosphor in the vicinity of the perforation. As a result, drive voltage margin quality between the different colors can be improved to produce a more reliable display.

1. Field of the Invention
The present invention relates to a plasma display panel (or PDP), and more particularly, to an address electrode structure of a plasma display panel.
2. Description of the Related Art
A PDP is typically a display device in which ultraviolet rays generated by the discharge of gas excite phosphors to realize predetermined images. With its ability to realize high-resolution images, the PDP is emerging as one of the most popular flat panel display configurations used for wall-mounted televisions and other similar large-screen applications.
When voltages are applied to the display and the address electrodes in a PDP, a charge and hence a space voltage forms near both the scan electrode and the display electrode on the substrates. An opposite charge is also formed on the lower substrate near the address electrode opposite to the scan electrode. These charges are free to move about and can accumulate about the display electrode. On the upper substrate, this charge that develops about the display electrode is of opposite polarity to the charge built up about the scan electrode and thus this charge built up about the display electrode serves to disturb the magnitude of the wall voltage, thus decreasing the quality of the image displayed. Therefore, what is needed is a design for a PDP that reduces or eliminates this build up of charge on the upper substrate in the vicinity of the display electrode.

Address electrode design in a plasma display panel


A stabilizing method for a current source is provided. The current source is provided a current which increases when temperature rises. An adjustment circuit provides an input current increasing when temperature rises. A rising ratio of the input current with temperature is the same as a rising ratio of the current of the current source with temperature. The current of the current source is subtracted from the input current. After the current of the current source is subtracted from the input current, the current of the current source does not vary when temperature varies.

1. Field of the Invention
The invention relates to a stabilizing method for a current source, and more particularly to a stabilizing method for a current source which provides a current varying with temperature.
2. Description of the Related Art
For integrated circuit design, reference voltages and reference currents are required. Wherein, the reference voltages and the reference currents are usually included in a bias part of the integrated circuit. For general applications, the bias part of an integrated circuit is designed according to operating temperature of the integrated circuit. However, variations in operating temperature are not considered for the design of the bias part.
During the operation of integrated circuits, operating temperature varies according to ambient temperature variation or heat generated by electronic elements within the integrated circuit. Operating temperature variations may affect signal transmitting operations of the integrated circuit, so that the transformed signals have noise resulted from the operation temperature variation. For example, an analog-to-digital converter is affected by temperature noise. Moreover, a microprocessor with a sensor is more sensitive to temperature variations, thus, temperature variations also affects operations of microprocessors with sensors.
In general, bipolar junction transistors (BJTs) are used to design integrated circuits having temperature variation. There is a logarithmic relationship between base-emitter voltage VBE and collector current IC of a BJT and the base-emitter voltage VBE is affected by temperature variation. The relationship between the base-emitter voltage VBE and the temperature variation is represented by the following:VBE(H,IC)=EGE−H(EGE−VBEN)+VTHH log(IC/IN)−ηVTHH log H  (Function 1)
wherein, H=T/TN, and T represents absolute temperature, and TN represents standardized temperature. TN is usually a middle value of an operating temperature range, such as 300K (27°). EEG represents an assumed value of the base-emitter voltage VBE at absolute zero (zero degree Kelvin), or about 1.14V to 1.19 V. VBEN represents a value of the base-emitter voltage VBE when junction temperature of a BJT is equal to the specific value TN and collector current IC is equal to a specific value IN. VTN represents a value of thermal voltage (=kT/q) at the standardized temperature TN. η represents a curve constant, about 2 to 4.
FIG. 1 shows a line diagram of Function 1. Referring to FIG. 1, showing characteristics of BJTs, the base-emitter voltage VBE decreases when temperature rises and increases when collector current IC increases. BJTs are usually applied in circuits, wherein when there is a rise in temperature, current increases, achieving current balance so that the current remains at a constant value.
However, since diodes are required in a BJT circuit, requirement for a BJT circuit increases hardware costs and device/element volume. Thus, it is desired to provide an alternative method for stabilizing a current source.


A storage device that includes: an address table; a cache memory; a flash memory device that is a storage medium for user data; and a control circuit that is in charge of access management for the flash memory device. In the storage device, the control circuit makes access to the user data on the flash memory device via an address table, in the address table, with an index of an address value generated from an initial logical address, location information is acquired for the user data on the flash memory device corresponding to the index, and the address table is segmented in its entirety into a plurality of small address tables for every area of the index, and the small address tables that are segmentation results are stored in the flash memory device, read as required when the user data is accessed, and expanded on the cache memory with entries of the small address tables.

1. Field of the Invention
The present invention relates to a storage device including a nonvolatile memory and a computer system and, more specifically, to a storage device whose main storage medium is a flash memory, a computer system, and a storage device access method.
2. Description of the Related Art
In recent years, flash memories have been receiving attention as a storage medium for use for digital still cameras or mobile computer equipment.
The flash memory is a semiconductor memory for storing therein data. For data storage, by using electron tunneling or acceleration of hot electrons, electrons are injected to a floating gate or a trapping layer after being made to pass through a gate insulation film so that a threshold value of a cell transistor is changed. In such a semiconductor memory, only one transistor of a multilayer gate or MNOS (Metal Nitride Oxide Semiconductor memory) structure can configure a memory cell so that the resulting memory can be inexpensive and large in capacity.
For such a semiconductor memory, a NAND flash memory is typically exemplified.
FIG. 1 is a diagram showing an exemplary internal configuration of a NAND flash memory.
The NAND flash memory of FIG. 1 includes a plurality of memory units 1-1 to 1-n in an array (in length and width directions). The memory units 1-1 to 1-n are connected to bit lines BL1 to BLn, respectively.
For example, a gate of a selection transistor 2 is connected to a selection gate line SL1, and a gate of another selection transistor 3 is connected to a selection gate line SL2. Gates of memory cells N0 to N15 are connected to word lines WL0 to WL15, respectively.
The memory cells N0 to N15 are each of multilayer gate structure and store therein data in accordance with the amount of charge stored for a floating gate. That is, when many electrons are stored in the floating gate, a transistor is increased in threshold value. For an assessment of data, an access circuit 4 including a sense amplifier or others is used to detect whether there is a current flow from the charged bit lines BL1 to BLn to the memory units 1, i.e., 1-1 to 1-n.
Such a NAND flash memory has no need to include an area for every memory cell to come in contact with the bit lines. In this sense, the NAND flash memory is considered suitable for use as a medium of inexpensive large-capacity storage devices.
The issue here is that the flash memory is generally considerably slow in program speed and requires several hundreds of micro (μ) seconds per cell. With the fact that no overwriting of data is possible, there is a need to erase data before running of a program, and this takes several m seconds. To deal with such a problem, many memory cells are subjected to parallel processing.
That is, writing of a memory cell group 5, i.e., a page unit, including cells all connected to the word line WL0 is performed in a batch all at once, and erasing of a cell block 6 configured by page groups each sharing a memory unit is performed in a batch all at once. Through such batch writing and erasing, the program is increased in transfer speed.
More specifically, Non-patent Document 1 (Digest of ISSCC2002, p 106, session 6.4) describes a NAND flash memory of 1 Gb, in which a page size is 2 kbytes, and an erase block size is 128 kB. That is, in a memory array, a memory cell group of 128 kbytes is erased in parallel, and a memory cell is programmed thereto in parallel for every 2 kbytes, thereby realizing the program transfer speed of 10 MB/s.
Also, in the field of NAND flash memory, the memory takes various internal configurations as a result of memory size reduction and a development of multilevel memory. However, accessing the memory is still the same, i.e., using a unit referred to as page for batch writing/reading and a unit referred to as block or erase block for batch erasing, and the block still includes a plurality of pages.
Alternatively, the memory device may include a plurality of flash memory chips and perform parallel writing by putting the chips into operation all at once. With this being the configuration, a group of pages in each of the chips serves as an actual page in the memory device, and the actual page serves as a unit for batch writing for the memory device. In this configuration, a group of erase blocks corresponding to each of the chips also serves as an actual erase block in the memory device, and the actual erase block serves as a unit for batch erasing in the memory device. As such, also in such a memory device, the actual erase block being a unit for batch erasing is configured to include a plurality of actual pages, each being an individual writing unit.
Moreover, with such varying internal configuration as a result of memory size reduction, and with some change observed in writing mechanisms, constraints are imposed on the pages in the blocks for the order of writing. That is, writing to the pages is made in the forward direction from low-order addresses to high-order addresses, and writing in the backward direction is prohibited. For example, once writing is made to some page, no writing is allowed any more to the page no matter if any low-order address in the same block is not yet through with writing.
Note that the pages for the NAND flash memory each generally have a backup area of 64 bytes with respect to an area for storing therein the user data of 2 kbytes, for example. The backup area can store therein various types of management data, e.g., parity bits, on the side of a system using the NAND flash memory. Writing to such a backup area is generally required to be made in one operation with writing to the user data area so that the writing operation is executed always as a set, i.e., executed both to the backup area and the user data area.
With a general file storage, the minimum write unit is a sector of 512B, which is used as a basis for random access. In this case, a command is issued to rewrite only a part of one page area, for example.
If random access as such is made using the above-described flash memory, however, any actual erase block area has to be entirely erased. If the actual erase block area includes any effective file in its not-yet-selected area, the file has to be protected from being lost.
FIG. 2 shows an example for such a data update. The procedure for the data update is as follows.
1. First of all, data of an entire actual erase block area 21 is read from a flash memory 20 to a buffer memory 23.
2. Next, in the buffer memory 23, any corresponding data is updated.
3. The block area 21 on the flash memory is erased.
4. Lastly, from the buffer memory 23, updated block data is entirely written back to the data-erased area 21.
As such, a sequence of operations for rewriting a few sectors requires a huge overhead of reading and writing of data whose amount is about 100 times as large as the amount of data in the sectors and erase blocks. As a result, it takes a longer time to fully seek a hard disk drive.
For a file update, it is actually common to update, at the same time, not only any corresponding file but also a plurality of small areas related to the file, e.g., a management domain or a log description. There may be a case where a file itself is fragmented and scattered in a plurality of small areas. Therefore, if there are constraints as described above, the actual transfer capability will be considerably poor.
For the aim of increasing the efficiency of such a sequence of operations, more flexible memory management using address conversion has been variously proposed. The current most popular management is of performing address conversion on an erase block basis.
FIGS. 3A and 3B are diagrams both showing an exemplary method of performing address conversion on an erase block basis.
FIG. 3A is a diagram showing a storage area of a flash memory, and FIG. 3B is a diagram showing an address table.
An address table 27 can acquire a physical block address (PBA) with an index of a logical block address (LBA). The physical block address is an address on the flash memory for any corresponding erase block.
When a host or an application issues a command of accessing a block address of "0x55", for example, the address is converted into "0x6B" using the address table, whereby access is made to the erase block 21 of the flash memory 20.
Under such memory management, data is updated on the flash memory as below.
1. A data-erased block 25 is prepared in advance for backup use with a physical address of "0xAA".
2. Assuming that a logical block address "0x55" is addressed, a corresponding physical block address "0x6B" is acquired, and thus a page 22 in the block 21 is accessed. With such access, data of the block 21, i.e., a to-be-erased block, of the flash memory 20 is sequentially copied to the backup block 25 via a page buffer 24, which is separately provided.
3. For copying to-be-updated data of the page 22, any desired portion of the data is updated on the page buffer 24 before being copied to a target page 26.
4. After any available data of the page is completely copied, the address of the block 21 is exchanged to the address of the backup block 25 on the address table 27.
5. Lastly, the original block 21 is erased.
After such a procedure, for the logical block address "0x55", an erase block corresponding to the physical block address "0xAA", i.e., backup block 25, will be always accessed so that accessing remains consistent.
After a data update, the block 25 becomes accessible at the time of the above process 4 so that the time to be taken for block erasing can be saved.
If such a backup block is plurally provided and scattered throughout the storage area, intensive copying to any specific block is prevented. Moreover, address conversion as above serves well for the purpose of preventing access making to any defective block.
Patent Document 1 (JP-A-8-328762) describes the details about a management method for use in a WORM (write-once, read-many-times) system using address conversion on a page basis. The page here is a unit for batch writing of the flash memory.
FIGS. 4A and 4B are diagrams both showing a management method in the WORM system.
FIG. 4A is a diagram showing a storage area of a flash memory, and FIG. 4B is a diagram showing an address table.
With such a management method, a physical page address (PPA) can be acquired from an address table 28 with an index of a logical page address (LPA). The physical page address is an address on the flash memory for the corresponding page.
When a host issues a writing command to a logical page address of "0x5502", for example, address conversion is performed using an address table on a page basis so that a physical page address "0x6B05" on the flash memory is acquired. As such, access is made to any corresponding area of the page 22 in the block 21.
For a data update in page 22, a search is made to find any appropriate free page area for direct data writing in the flash memory. As a writing destination considered appropriate, if a head page area 29 of the data-erased block 25 corresponding to a physical block address of "0xAA", is selected only the data of the page 22 is updated via the page buffer 24, and thus updated data is written to the page area 29. At this time, the logical page address "0x5502" is remapped to a physical address "0xAA00" of the page area 29. The old data on the page 22 is left as it is for the time being but is made invalid.
With such memory management, as long as there is any free area in the flash memory, writing of only one-page data is needed for updating the respective page data.
Thus, this leads to data rewriting at high speed. During the data rewriting, there is no need for data erasing so that the rewriting frequency can be considerably reduced for the flash memory, and the useful life of the flash memory also can be increased.
The inventors of the invention have proposed the more advanced management technique utilizing address conversion on a page basis, e.g., JP-A-2005-114711, JP-A-2005-165234, and JP-A-2005-1714.
There is also the technique utilizing address conversion which is an intermediate version between a page-basis and a block-basis. For example, without changing the relationship between the blocks and the page groups in the blocks, the positional relationship between the pages inside of the blocks is remapped. The effects derived thereby for reduction of the overhead are intermediate in level between the above-described two techniques.
As such, by remapping using an address table, user data on the flash memory can be managed in various different manners.
With every such manner, the address table is referred to by using as an index the address value generated from the initial logical address, and information is acquired about the location of the corresponding user data, e.g., physical address on a flash memory. Based on the thus acquired location information, access is made to the data on the flash memory.
Especially, if every page group that is a unit for batch writing is subjected to remapping of changing their relative positions, the access efficiency can be increased with remarkable effects.

Storage device, computer system, and storage device access method


A system including a plurality of remotely configurable telephone network communication terminals (102) is adapted to communicate with a programming terminal (134) over a data network (222) by adding a remote interface means (RIM) (202) for each terminal to convert communications between the terminal to or from a format adapted for transmission over the data network, the programming terminal having a modem emulator (202) having communication and programming capabilities to interface the programming terminal with the network; by converting the programming terminal data to a network compatible format, obtaining an address for the RIM, connecting the programming terminal and the RIM via the data network, connecting the RIM and the communication terminal, transmitting the converted programming terminal data to the RIM, reconstituting the converted data to a format suitable for the communication terminal, and transmitting the reconstituted data to the communication terminal.

Premises alarm systems generally allow technicians and others to use dial up or analog data modems over the PSTN to gain remote access to the equipment in order to modify the configuration and down load new firmware. Such an arrangement is illustrated in FIG. 9 which shows programming terminal 9.34 connected to the PSTN 9.13 via modem 935, and an alarm panel 9.02 connected to the PSTN 9.13 via a second modem 9.04.
A number of problems arise when attempts are made to transmit telephony signalling via a data network.
Some non-digital signalling systems utilize "real-time" or time-dependent information to convey signalling information. For example, in telephone signalling, a pause of a known duration can be used to indicate that the following information is to be interpreted in a different manner from that in which it would normally be interpreted. Similarly, a signalling burst can be "bracketed" between pauses of defined duration. We have found that this time dependent information can be lost or corrupted in transmission across data networks such as packet-switched networks. In particular, this information can be lost in transmission across an IP network.
Recent times have seen the rapid roll out of voice over IP (VoIP) services displacing the PSTN at customer premises. As legacy alarm systems are generally incompatible with VoIP services, new customer terminal equipment has been introduced to convert the signals from the legacy alarm panels' PSTN interface to a form compatible with IP networks used to deliver the VoIP service.
The introduction of customer terminal equipment blocks the path used to remotely down load configuration data and the like into alarm systems. Therefore in order to completely replace the PSTN with if) networks, the customer terminal equipment must provide the ability to remotely (and securely) modify the configuration of the alarm system over IP or cellular networks in a similar manner to the PSTN.
Some attempts have been made to solve this problem by providing VoIP functionality in the customer terminal equipment to support a PSTN like connexion to the premises alarm system so as to provide the communications path to remotely modify the configuration over IP. This approach suffers from a number of limitations, including poor security associated with using VoIP, and unpredictable channel quality. This is due to the fact that VoIP call quality depends on available bandwidth and other factors, such as jitter and packet loss affecting the IP path between the customer premises and the remote site from which the configuration is being carried out. If the bandwidth available over the TP path is low or is available in bursts, then the quality of the communications channel is poor and will not provide a reliable connexion for the analog data modems used to provide the data communications link for remote configuration.
This specification describes an arrangement which allows the secure remote configuration of alarm systems over IP or cellular links in a manner that is far less dependent on the quality of the communications path or the available bandwidth as it only uses the bandwidth specifically required for the data download, which could range from 110 bits per Second up to 33800 bits per Second, but not exceeding 64000 bits per Second.
The invention is also applicable to other legacy systems which have similar requirements.

This patent is subject to a terminal disclaimer.


A method for ICI self-cancellation and ICI reconstruction and cancellation is introduced. The method includes receiving input signals; receiving boundary information regarding a length q of an ISI-free region of the received signals; selecting a plurality of ISI-free signals from the received signals; combining the plurality of ISI-free signals to provide combined signals z(n); performing FFT operations on the combined signals to provide output signals Z(k); reconstructing ICI based on the output signals Z(k) and the length q of the ISI-free region of the input signals r(n) in order to provide an estimated ICI; subtracting the estimated ICI from the output signals Z(k) to provide a cancelled signal W(k); performing a channel estimation for the cancelled signal W(k); equalizing the cancelled signal W(k) to provide an equalized signal; and de-mapping the equalized signal to provide a de-mapped signal d(k).

The invention relates to the transmission of orthogonal frequency division multiplexing (OFDM) signals, and specifically, relates to a method and an apparatus for inter-carrier interference (ICI) self-cancellation and ICI cancellation and reconstruction of OFDM signals.
In wireless communication systems, signals may be transmitted in electromagnetic waves through a physical channel such as air. Due to undesirable channel effects such as, for example, multi-path reflection and multi-path fading, signals may generally be distorted when received. An orthogonal frequency division multiplexing (OFDM) system based on multi-carrier modulation has been developed to address the issue of multi-path reflection. With only one simple one-tap equalizer at the receiver, the OFDM system is able to equalize signals that may have suffered from constructive interference or destructive interference caused by the multi-path effects. Therefore, the OFDM scheme becomes a mainstream scheme in the wired/wireless communications and in the digital terrestrial broadcasting applications. Examples of the OFDM applications may include Asymmetric Digital Subscriber Line (ADSL), Power Line Communication (PLC), and Digital Audio Broadcasting (DAB) systems, and may further include Wireless Local Area Network (IEEE 802.11a/b/g/n), Wi-MAX (IEEE 802.16 series), and Digital Video Broadcasting (DVB) over terrestrial (DVB-T) and over handheld devices (DVB-H) under research and development.
To prevent an OFDM system from the multi-path channel effect, a duplicate of a section of an original useful symbol, called a guard interval (GI), having a length Tg, is cyclically prefixed to the original useful symbol, which has a length Tu with N sampling points, to form a complete OFDM symbol before OFDM signals are transmitted into the channel. When the maximum channel delay, τmax, is shorter than the length of GI, τg, the inter-symbol-interference (ISI) caused by the multi-path channel may be prevented in the OFDM receiver. The receiver then discards the GI sections and retrieves the useful symbols from the received symbols, and compensates for the channel effect by an one-tap equalizer so as to estimate the transmitted data.
In the specifications of some OFDM systems, such as the DVB-H and IEEE 802.16, it is emphasized that receivers have to provide desirable capability of reception when moving at a high speed. However, when a receiver of an OFDM system is not stationary and may be mobile relative to a transmitter at a relatively high speed, the status of the channel within a useful symbol duration may be no more constant. The channel may thus become a time-selective fading channel, which may result in one time of Doppler frequency offset, either positive or negative, in carriers relative to a center carrier frequency, fc. Such a frequency offset is unfavorable to a multi-carrier modulation system such as the OFDM system, and may incur inter-carrier interference (ICI) that destroys the orthogonality of the system, disadvantageously resulting in an "error floor" effect in the bit error rate (BER).
It may be desirable to have an apparatus and a method to address the ICI issue due to the Doppler effect in an OFDM system.

Apparatus and method for inter-carrier interference self-cancellation and inter-carrier interference reconstruction and cancellation

Industrial Technology Research Institute


A station and a method of collecting information corresponding to security. A wireless communicator transmits a request packet to search a wireless network to at least one external device and receives a response packet to the request packet. An authentication method determiner analyzes the response packet to search for at least one wireless network and determines an authentication method supported by each of the searched wireless networks. A storage unit stores the determined authentication method of each of the searched wireless networks. Thus, necessary information corresponding to security during a connection to a wireless network can be searched in advance and provided to a user.

1. Field of the Invention
The present general inventive concept relates to a station and a method of collecting information corresponding to security. Specifically, the present general inventive concept relates to a station and a method of collecting information corresponding to security by which information necessary for security can be searched in advance during a connection to a wireless network to provide the information to a user.
2. Description of the Related Art
Devices supporting wireless communications generally require settings for wireless connections. In a wireless environment in which security is not set, settings for wireless connections may be wirelessly performed using only Service Set Identification (SSID) searched in the network. In a case of a wireless environment in which security is set, the devices require setting of security on a Wired Equivalent Protocol (WEP), Wi-Fi Protected Access-Pre Shared Key (WPA-PSK), or 802.11i level. Accordingly, a user must manually input data necessary for setting security to set security. However, if the user has a limited knowledge of setting security in a wireless network, the user does not know which security setting is necessary for the wireless search.
When a user desires to set a connection to an access point (AP) in which wireless security is set, a conventional device supporting wireless communications does not provide information necessary for wireless setting. Thus, the user has no enough knowledge of wireless security and thus suffers much inconvenience. Also, if wireless setting is wrong in the conventional device, the conventional device does not provide information related to errors to the user. Thus, the user is not able to easily understand what type of security is required for setting wireless environment, and thereby spends a large amount of time for wireless setting.

Station and method of collecting information corresponding to security in a wireless network


A method and apparatus for designing low-order linear-phase IIR filters is disclosed. Given an FIR filter, the method utilizes a new Krylov subspace projection method, called the rational Arnoldi method with adaptive orders, to synthesize an approximated IIR filter with small orders. The method is efficient in terms of computational complexity. The synthesized IIR filter can truly reflect essential dynamical features of the original FIR filter and indeed satisfies the design specifications. In particular, the linear-phase property is stilled remained in the passband.

1. Field of the Invention
The present invention relates to a method of designing digital filters, and more particularly, to a method of designing low-order linear-phase IIR filters for approximating an FIR filter.
2. Description of Related Art
Digital filters for addressing digital signal processing have been applied widely in commercial electronic products, such as compact disk players, television sets and the like. In order to deal with real-time signals, the designs should be considered low computational costs to output signals efficiently. Also, since the distortion-free transmission of-the waveforms in the passband is very important in signal processing, the filters should contain a linear-phase characteristic, i.e., constant group delay.
There are two classes of digital filters. One is a finite-duration impulse response (FIR) filters and the other is an infinite-duration impulse response (IIR) filters. The main advantages of the FIR filters are exactly linear phase and guaranteed stable. However, when the specification being very rigorous, the resulting FIR filter is usually with higher orders, which may require more hardware components and lower the operational speed. Conversely, the IIR filters are useful for large-scale or high-speed designs but they do not have exactly linear phase and can not guarantee to be stable.
One way to synthesize the IIR filters with linear phase in passband is to solve the rational approximation problem directly. These methods, for example, include Pade approximation, linear programming, nonlinear programming, multiple criterion optimization and eigenfilter approach.
Another way is called the indirect approach. It will be composed of three steps, as shown in FIG. 1. Step 1 receives and stores the design specifications of a digital filter.
These specifications are required in the frequency-domain in terms of the desired magnitude and phase response of the filter. Then, a linear-phase FIR filter, which meets design specifications, will be designed in step 2. The order and the coefficients of the FIR filter can be obtained using the conventional methods such as the frequency-sampling design technique, the window design technique and the optimal equiripple design technique. Finally, a lower-order IIR filter will be obtained using filter approximation techniques in step 3. It should be mentioned that the special attentions shall be paid on this indirect approach. The resulting IIR filter must be ensured to capture the linear-phase response of the original FIR filter in the passband.
In recent years, several linear-phase IIR filter design techniques have been emerged for this purpose. Generally speaking, two distinct methods have be proposed: (1) Grammian-Based Methods: including the balanced truncation method and impulse response grammian method and (2) Optimal Approximation Methods: including the least-square approximations and the H2 norm approximation. Although satisfactory results have been reported, computational complexity of these methods are still quite expensive.

Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter


A cost efficient electrical feedthrough is provided for forming a hermetic seal with a container and allowing a desired number of inputs to be connected between varied environmental conditions. The electrical feedthrough can be employed for environmental conditions including high pressures, high temperatures, low temperatures and the presence of corrosive gases. A first wire situated in a first environmental condition and a second wire situated in a second environmental condition are connected via a conducting material. The first environmental condition and the second environmental condition are separated by a divider having an opening for passing therethrough either the first wire or the second wire. A first seal extends from the divider to a material in contact with the conducting material. In an aspect, a second seal forms an enclosed area with the conducting material for surrounding a wire engaging hole and any wire extended therethrough and sealing the first environmental condition from the second environmental condition.

Electrical feedthrough assemblies provide a conductive path extending between the interior of a hermetically sealed container and a point outside the container. Electrical feedthroughs are utilized by many industries for avoiding any leakage of gases or fluids. Industries requiring an electrical feedthrough include the aerospace industry, telecommunication industry, semiconductor industry, medical device industry with respect to implantable devices, and automotive industry for systems including fuel pumps, transmissions, process controls, and marine systems. Scientific instruments of all types also require an electrical feedthrough between varied environmental conditions. As an example, in a laboratory environment, a pressurized chamber is typically used for product evaluation of a pressure sensor for automotive or industrial applications. Since a pressurized chamber is often used to test various parts, numerous connections must be established with a device situated outside the pressurized chamber.
In order to communicate with or power a unit being evaluated, a high pressure feedthrough is often required. With so many applications, a varied number and varied type or size of input/output connections are required. As such, contemporary feedthrough devices are commonly custom made to order and are relatively expensive. Contemporary feedthrough devices for pressurized chambers typically contain about twenty input/output connection wires. As the number of inputs and outputs increase, the costs of the feedthrough devices increase, with a significant cost increase at about one hundred input/output connections. Further, the size limitation of contemporary feedthrough devices can dictate the size and construction design of a pressurized chamber. These limitations place undesirable restrictions on the pressurized chamber design.
Environmental conditions including high temperatures and the presence of a corrosive gas can further limit the design of an electrical feedthrough. Feedthrough corrosion may be, and often is encountered with contemporary devices. The corrosion can ultimately compromise a seal, resulting in leakage between the necessary separate environmental conditions.

Electrical feedthrough for varied environmental conditions


Radial impulse engine, pump, and compressor systems are disclosed herein. In one embodiment of the invention, a radial impulse engine includes first and second movable V-members operably disposed between first and second end wall portions. The first V-member can have a first wall portion with a first distal edge portion and a second wall portion with a first cylindrical surface. The second V-member can have a third wall portion with a second distal edge portion and a fourth wall portion with a second cylindrical surface. In this embodiment, the first distal edge portion of the first wall portion can be configured to slide across the second cylindrical surface of the fourth wall portion, and the second distal edge portion of the third wall portion can be configured to slide across the first cylindrical surface of the second wall portion, when the first V-member pivots about a first pivot axis and the second V-member pivots about a second pivot axis.

The efficiency of internal combustion engines is often expressed in terms of thermal efficiency, which is a measure of an engine's ability to convert fuel energy into mechanical power. Conventional internal combustion engines with reciprocating pistons typically have relatively low thermal efficiencies. Conventional automobile engines, for example, typically have thermal efficiencies of about 0.25, which means that about seventy-five percent of the fuel's energy is wasted during engine operation. More specifically, about forty percent of the fuel's energy flows out the exhaust pipe as lost heat, while another thirty-five percent is absorbed by the cooling system (i.e., coolant, oil, and surrounding air flow). As a result of these losses, only about twenty-five percent of the fuel's energy is converted into usable power for moving the car and operating secondary systems (e.g., charging systems, cooling systems, power-steering systems, etc.).
There are a number of reasons that conventional internal combustion engines are so inefficient. One reason is that the cylinder head and walls of the combustion chamber absorb heat energy from the ignited fuel but do no work. Another reason is that the ignited fuel charge is only partially expanded before being pumped out of the combustion chamber at a relatively high temperature and pressure during the exhaust stroke. An additional reason is that reciprocating piston engines produce very little torque through much of the piston stroke because of the geometric relationship between the reciprocating piston and the rotating crankshaft.
While some advancements have been made in the field of piston engine technology, it appears that the practical limits of piston engine efficiency have been reached. The average fuel economy of new cars, for example, has increased by only 2.3 miles-per-gallon (mpg) in the last 20 years or so. More specifically, the average fuel economy of new cars has increased from 26.6 mpg in 1982 to only 28.9 mpg in 2002.
Although a number of alternatives to the conventional internal combustion engine have been proposed, each offers only marginal improvements. Hybrid vehicles, for example (e.g., the Toyota Prius), and alternative fuel systems (e.g., propane, natural gas, and biofuels) still use conventional reciprocating piston engines with all of their attendant shortcomings. Electric cars, on the other hand, have limited range and are slow to recharge. Hydrogen fuel cells are another alternative, but implementation of this nascent technology is relatively expensive and requires a new fuel distribution infrastructure to replace the existing petroleum-based infrastructure. Accordingly, while each of these technologies may hold promise for the future, they appear to be years away from mass-market acceptance.

Radial impulse engine, pump, and compressor systems, and associated methods of operation


The invention discloses a pharmaceutical hemostatic liquid foam base preparation comprising albumin as foaming agent and a fibrinogen precipitating substance and optionally a coagulation inducing agent, wherein albumin as foaming agent is present in native form; a method for the production of a transient hemostatic liquid foam; the transient hemostatic liquid foam; and a kit for making the foam.

Foams are generally understood to represent materials in which a gas, such as air, is finely dispersed in a liquid in a form that is stable over some time. The liquid is found in the form of thin films between the bubbles. The stabilizing element of such gas dispersions is the surface tension of the liquid phase. The surface tension can be influenced by the presence of surface-active agents in the fluid phase, which help to stabilize the films against collapse. These foams are generally referred to as closed pore foams, as there is no connection between the gas spaces of each individual bubble. If the liquid films are stabilized by other means, e.g. by chemical reactions that transform the liquid phase into a viscoelastic solid, then the formation of open pore foams is possible, in which the fluid bridges are removed in a controlled manner, e.g. by evaporation or other processes. The transformation of the liquid films into a viscoelastic solid material also serves to effectively stabilize the foams against rapid collapse.
It is an object of the present invention to provide improved hemostatic foams which can be safely injected into tissue voids with low visibility and which are effective with no need for approximation. In addition, it is important that such a foam hemostat does not present a risk of obstruction or compression of pressure sensitive organs or tissues due to excessive swelling. Such a foam should be specifically applicable in neuro/spine, laparoscopic and cardiovascular surgery.


A hierarchical tagging system and method are provided. In one embodiment, a software-based customer relationship management system and method may include the hierarchical tagging system.

Customer relationship management (CRM) systems and solutions are well known. For example, typical known CRM systems include Microsoft® CRM, SalesForce, a CRM product provided by SalesForce.com, Netsuite CRM, and SAP Business One CRM. However, conventional CRM systems have significant limitations that include a lack of flexibility, high costs, and a closed-source structure which is embedded into the traditional product offerings. These limitations have led to a failure rate of over 70% with traditional CRM implementations. Thus, it is desirable to provide a customer relationship management system and method that overcomes these limitations of typical CRM systems and it is to this end that the system and method are directed.

Customer relationship management system with hierarchical tagging


A seal apparatus, for sealing around a rotating shaft such as a propeller shaft of a watercraft between the exterior water and an interior lubricant space, includes a multiple seal arrangement with plural seal rings forming seal chambers therebetween, and plural fluid medium lines supplying and/or returning a respective fluid medium to a respective seal chamber. A section of a first medium line is formed as an axial passage through a housing of the apparatus, and a section of a second medium line is formed by a pipe arranged within the axial passage in the housing. A method of making such an apparatus especially by retrofitting an existing seal arrangement involves inserting a pipe into an axial passage in the housing in order to establish two medium lines through the housing where there was previously only one medium line.

Various types and configurations of seal arrangements, bushings, packing boxes, stuffing boxes, glands and the like are known for providing a seal around the rotating shaft that drives a ship's propeller, for example where the shaft penetrates through the stern of the ship from the interior to the exterior of the ship's hull. The seal arrangement must effectively prevent water from the exterior environment, i.e. from the exterior of the hull below the water line, leaking into the interior of the hull where the shaft penetrates through the hull, while still allowing the shaft to rotate. Preferably, the seal arrangement should also dissipate the frictional heat that arises due to rubbing friction of seal elements on the rotating shaft, should allow for the removal of wear particles or other contaminants from the seal arrangement, and further should provide a long operating life and allow easy maintenance.
One known type of seal arrangement uses plural seal rings spaced axially from one another along the propeller shaft in a stern tube, for example, thereby forming successive seal chambers respectively between successive neighboring ones of the seal rings. An outermost chamber can be filled with seawater, an intermediate chamber can be pressurized with a compressed gas such as compressed air, and an inner chamber can be filled with oil. The respective fluid, for example air or oil, can be supplied to and drained from the respective seal chamber through respective medium lines.
A seal arrangement for sealing a ship propeller shaft between the exterior water and the interior lubricant space, of the above described general type is known, for example, from the German patent laying-open document DE 44 34 247. The disclosed arrangement comprises a multiple seal arrangement having two seal rings oriented toward the exterior water and two seal rings oriented toward the lubricant space of the ship propeller shaft. A respective seal chamber is formed respectively between neighboring seal rings. A fluid medium can be supplied into the respective seal chamber via a respective medium supply line, and the fluid can be removed from the chamber via another respective medium return line.
As seen in the direction from the interior lubricant space toward the exterior water, this known seal arrangement has the forwardmost or first seal chamber filled with an oil, the second or middle seal chamber filled with air, and the third or aft seal chamber filled with exterior water. Because the multiple seal arrangement is arranged outside of the ship hull, the respective medium lines conveying the respective medium to and from each chamber must, at least partially sectionwise, pass through a massive housing such as a stern tube section for example, or such as a gondola or pod housing, depending on the particular type of embodiment of the ship drive arrangement. These sections of the fluid supply and return lines guided through the housing are typically individual bored holes, that each respectively correspond to a single fluid supply or return line, and that each require a technically demanding and time intensive boring operation for their formation. This is especially problematic and disadvantageous when a seal arrangement of an existing ship propeller shaft is to be upgraded, retrofitted or supplemented with additional seal chambers and/or additional medium supply and return lines. In such a situation, it becomes necessary to bore additional individual bore holes through the massive housing around the ship propeller shaft, for which the required boring or drilling operations can lead to a long out-of-service time of the ship in a service dock. Such long out-of-service times must absolutely be avoided due to the high costs and accruing losses when the ship is out of service.

Seal apparatus for a ship propeller shaft and method of making the apparatus


A method for forming a semiconductor device having a reduced pitch is provided. The method includes providing a substrate, forming a material layer over the substrate, forming a photoresist layer over the material layer, exposing a top surface of the photoresist layer to radiation, and forming a silylated layer over the photoresist layer. The method further includes removing a portion of the silylated layer to expose the photoresist layer, removing the photoresist layer, removing portions of the material layer using the silylated layer as a mask, and removing another portion of the silylated layer.

1. Field of the Invention
The present invention relates generally to methods for fabricating semiconductor devices and, more particularly, to methods for reducing cell pitch in semiconductor devices.
2. Description of Related Art
The fabrication of semiconductor devices is a complex process, which typically includes a number of photolithography processes. In a typical photolithography process, a photoresist material is deposited over a layer to be patterned and is exposed to a radiation source, such as, for example, ultraviolet radiation, which is projected through a mask that defines the pattern to be formed in the photoresist. The mask only passes radiation to selected regions of the layer to be patterned, resulting in the exposure of the photoresist only at those selected regions. The photoresist is then developed to form a patterned photoresist layer over the underlying layer to be patterned. The portions of the underlying layer left exposed by the photoresist are etched away to define, for example, gate conductors of ensuing transistor devices. The pattern in the photoresist is thus replicated in the underlying layer.
Important advantages are of course achieved by making the semiconductor devices as small as possible. Typical photolithography processes, however, limit the size and density with which semiconductor devices may be fabricated. For example, a minimum resolution capability of a given photolithography process determines the minimum pitch with which features for a patterned layer may be printed using that process. Consequently, the photolithography process limits the minimum achievable widths which can be obtained for those features of such conventional semiconductor devices. It therefore can be difficult to reduce the widths of and distances between, for example, transistor gate conductors that are defined by the photolithography process.
Because of limitations of the photolithography process, the pitch of semiconductor devices, such as for example transistor devices, cannot be easily reduced. The "pitch" is herein defined as the distance between the same points of two adjacent structures of the same type, such as, for example, two adjacent transistor gate conductors. Since the pitch of semiconductor devices cannot be easily reduced, the device density cannot easily be increased to meet the high demand for smaller and faster semiconductor devices. In addition, higher densities translate into lower material costs for the semiconductor devices.
A need thus exists in the prior art to reliably and efficiently reduce the pitch of semiconductor devices. A further need exists to develop methods for fabricating semiconductor devices in which the widths of and distances between adjacent structures of the same type are not limited by the photolithography process.

Methods for using a silylation technique to reduce cell pitch in semiconductor devices


Periods P.sub.k between the one edges of input pulses are measured one after another by a successive period measuring circuit, and at the same time, the time interval between the one edge to the other of each input pulse, that is, a pulse width W.sub.k, is measured by a time interval measuring circuit. The measured periods are sequentially accumulated and each accumulated value is made to correspond to each pulse, as the time at which the measurement of its pulse width was started. In an interpolation part, pulse widths, which are assumed to be obtained at regular time intervals, are computed, by an interpolation method, from the sequence of measured pulse widths and the their measurement starting times. In a Fourier transform part, the pulse width data obtained by the interpolation is subjected to a Fourier transform to obtain the frequency components of a pulse width jitter.

The present invention relates to a jitter analyzer for analyzing what are called jitters of input pulses, such as the pulse width fluctuation and pulse repetition period fluctuation.
It is coded pulse train signals that are reproduced, for example, in a magnetic disk unit for use as an external storage of a personal computer, a digital audio apparatus called a compact disk apparatus, or a video apparatus such as a laser disk apparatus. If a jitter is contained in such a coded pulse train signal, an error is likely to occur during decoding of the signal. The occurrence of an error is not allowed in the case of an external storage of a computer, in particular. In the case of determining if these digital apparatuses are good or defective, it is therefore necessary to measure whether the jitter of the pulse train signal stays within a given limit or not.
In Japanese Patent Application Public Disclosure No. 284268/87 the inventor of this application proposes a pulse width fluctuation analyzer. FIG. 1 shows its basic construction in a simplified form. Input pulses are applied to a time window 2, whereby pulses of a particular pulse width are sequentially extracted or selected from among pulses of various pulse widths which are substantially integral multiples of a unit pulse length, and the selected pulses are converted by a time-to-voltage (hereinafter referred to as T-V) converter 3 to voltages corresponding to the pulse widths. The voltage thus converted for each pulse is provided to an ordinary fast Fourier transform (FFT) analyzer 4, wherein it is subjected to a fast Fourier transform for analysis. In this way, pulse width fluctuations or jitter components of the input pulses can be detected, and in particular, even if the jitters vary with a plurality of periods, components of the respective periods can be detected, which can be used to ascertain the cause for the occurrence of each jitter.
With the T-V converter 12 which simply integrates reference clock pulses for the duration of the input pulse as in the above-mentioned Japanese patent public disclosure, it is impossible to achieve a high precision time-to-voltage conversion, for example, with a resolution of 100 ps. In practice, as proposed by the inventor of this application in Japanese Patent Application Public Disclosure No. 294993/87, for instance, a constant voltage is integrated for a fractional or odd period .DELTA.T.sub.1 from the rise of a certain input pulse to the rise of a clock pulse immediately thereafter and for a fractional or odd period .DELTA.T.sub.2 from the fall of the input pulse to the rise of a clock pulse immediately thereafter to thereby obtain voltages corresponding to odd or fractional components of the clock pulses at the rise and fall of the input pulse, respectively, the voltage at the fall of the input pulse is subtracted from the voltage at the rise thereof to obtain a difference voltage, and the number of rises of the clock pulses, counted from the end of the fractional period .DELTA.T.sub.1 to the end of the fractional period .DELTA.T.sub.2, is converted by a D-A converter to the corresponding voltage. The sum voltage, obtained by adding the difference voltage and the voltage corresponding to the clock count value, is sampled and held, as a voltage corresponding to the width of the input pulse, by a sample-hold circuit and then output therefrom. In this instance, the number of digits for conversion is a predetermined sequence of four digits or so, and in the case of voltage conversion of, for example, a 1.2345 .mu.s pulse width, a voltage corresponding to the value of the low order four digits 2345, the least significant digit of which is 100 ps, is provided, that is, the voltage output is yielded with no information of the most significant digit being taken into account. This does not matter when it is necessary to analyze the pulse width fluctuation, i.e. the frequency component of the jitter and the pulse width of the input pulse is preknown.
Since the magnitude of the jitter relative to the pulse width is often required, it is necessary to measure the pulse width of the input pulse when it is unknown. Moreover, in the case where input pulses of different pulse widths are provided and it is desirable to detect the frequency component of a jitter corresponding to each pulse width or the distribution of frequency of the jitter with respect to the pulse width, it is necessary to measure the pulse width.
To this end, the conventional jitter analyzer shown in FIG. 1 is provided with a pulse width measuring part 5, wherein the width of the output pulse from the time window 2 is measured. The pulse width measuring part 5 can be operated in synchronism with the sample-hold timing of the T-V converter 3, since the timing period with which pulses of a fixed width are extracted is not always constant when the time window 2 is used, the measuring cycle is not constant, in general, that is, the measurement dead time varies. This means that the sample-hold timing in the T-V converter 3 does not become constant, and therefore it is impossible to use, as a sampling clock for fast Fourier transformation, a signal synchronized with the sample-hold in the T-V converter 2. Accordingly, the FFT analyzer 4 has an independent sampling clock of a fixed interval. In other words, the T-V converter 3 and the pulse width measuring part 5 can be operated with the same measuring cycle, but the FFT analyzer 4 needs to be operated with a different measuring cycle. Hence, the jitter analyzer calls for complicated control.
In addition, as mentioned above, the T-V converter 3 includes a D-A converter and a sample-hold circuit, whereas the FFT analyzer 4 includes a sample-hold circuit and an A-D converter. Thus, the prior art analyzer is, in its entirety, wasteful or uneconomical in construction.


A vertical-channel semiconductor device includes an active pillar including a channel region, a gate located at a sidewall of the active pillar, a buried bit-line formed below the active pillar, and an insulation film formed below the buried bit-line. Some parts of the buried bit-line are replaced with an insulation film, such that a bit-line junction leakage is prevented.

Embodiments relate to a semiconductor device including a vertical channel, and more particularly to a vertical-channel semiconductor device in which some parts of a lower portion of a buried gate are replaced with an insulation film so as to prevent a bit-line junction leakage.
Generally, a semiconductor is a material that falls within an intermediate region between a conductor and a nonconductor in terms of electrical conductivity. Although a semiconductor is similar to a nonconductor in a pure state, electrical conductivity of the semiconductor material can be increased by impurity implantation or other manipulation. The semiconductor is used to form a semiconductor device such as a transistor through impurity implantation and conductor connection. A device including a semiconductor element is referred to as a semiconductor device. A representative example of the semiconductor device is a semiconductor memory device.
A semiconductor memory device may include a plurality of transistors. The transistor may have three regions, i.e., a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal (the magnitude of a voltage) input to the gate of the transistor. The charges between the source and the drain move through a channel region in accordance with the properties and operation of the semiconductor device.
Generally, a method for manufacturing the transistor includes forming a gate over a semiconductor substrate, and forming a source and drain by doping impurities over the semiconductor substrate located at both sides of the gate. A region between the source and the drain may be located below a gate, and is used as a channel region of the transistor. A transistor including a horizontal channel region occupies a relatively large area, so that it may be difficult to form a highly-integrated semiconductor device.
In order to address the above-mentioned issues, there is proposed a vertical-channel semiconductor device in which an active region is formed as a pillar shape, and a source and drain region is located above or below the pillar, so that a vertical-shaped channel region is formed.
However, the higher the degree of integration of the semiconductor device, the shorter a physical distance between gate electrodes or bit lines, such that a bridge may occur between the gate electrodes or the bit lines, or parasitic capacitance between the gate electrodes or the bit lines increases. As a result, there is a need for a new structure capable of being highly integrated while also being easily fabricated.

Semiconductor device having vertical channel


A tool and method for switching an electromagnetic relay may be provided, whereby the tool comprises a switching member capable of moving between a first position and a second position along a path oriented to the relay; wherein movement of the switching member from the first position to the second position is capable of switching a switch state of the electromagnetic relay via a magnetic force exerted by the switching member.

Electromagnetic relays are used extensively as electromechanical switches in various applications such as electrical circuit boards, alarms, and sensors etc. Typically, a relay comprises an electromagnet with a soft iron bar, or armature. A movable contact/switch is coupled to the armature such that the contact is held in its normal position by e.g. a return spring. Typically, when the electromagnet is energized, by e.g. a user applying a power source to the relay, a magnetic force overcomes the biasing force provided by the return spring and moves the contact into an alternative position, such that the circuit is either open or connected. When the electromagnet is de-energized, by e.g. a user removing the power source to the relay, the contact returns to and is held in its normal position by the return spring.
In some electromagnetic relays, a lock-down door and test button is provided, where manual or physical manipulation of the relay switch can be provided and the manipulated position of the switch physically retained. The manipulation thus bypasses the effect of the electromagnet within the relay. In other words, some relays are integrated with an assembly which allows for the manual operation of the switch, without having to energize the electromagnet coil. This can allow a user to e.g. debug a system controlled by the relay, without energizing the relay's coil.
However, such integrated lock-down door and test button assemblies are not always present in all electromagnetic relays. Non-provision of such assemblies can be because the presence of such additional assemblies may add to the cost of the electromagnetic relay. Further, such assemblies cannot be easily incorporated in certain types of relays due to size or other constraints defined by industrial standards or user requirements. This is particularly true for a range of relays, typically called slim relays. In relays where the lock-down door and test button assemblies cannot be provided, e.g. in conventional slim relays, there does not exist any means for switching the relay to another state without some form of energizing the coil. This situation is particularly difficult and undesirable given that relays, after manufacturing, are typically encapsulated by a moulding material and the internal components of the relay, such as the coil and armature, are not typically accessible. Furthermore, for debugging purposes, it is also not desired to energize a relay in order to switch its state. For example, relays can be used to control a high-power circuit using a low-power signal, with complete electrical isolation between the control and controlled circuits. During commissioning or debugging of the relay, there are situations where the low power signal supplied to the coil cannot or should not be provided.
Therefore, there exists a need for a tool for switching the state of a relay that seeks to address at least one of the above problems.

Tool and method for switching an electromagnetic relay


The present disclosure relates to a diaphragm that may be used with a mechanical-to-acoustical transducer. The diaphragm may include a layer of optically clear film, a damping layer and another layer of optically clear film. The damping layer may be an adhesive. The diaphragm may also comprise two optically clear films, optionally including a damping layer, wherein the films indicate a desired coefficient of linear thermal expansion in one or both of the machine and transverse directions.

Mechanical-to-acoustical transducers may have an actuator that may be coupled to an edge of a speaker membrane or diaphragm that may then be anchored and spaced from the actuator. Such a system may provide a diaphragm-type speaker where a display may be viewed through the speaker. The actuators may be electromechanical, such as electromagnetic, piezoelectric or electrostatic. Piezo actuators do not create a magnetic field that may then interfere with a display image and may also be well suited to transform the high efficiency short linear travel of the piezo motor into a high excursion, piston-equivalent diaphragm movement.
One example of mechanical-to-acoustical transducer including an actuator that may be coupled to an edge of a diaphragm material is recited in U.S. Pat. No. 7,038,356. The use of a support and actuator that was configured to be responsive to what was identified as surrounding conditions of, e.g., heat and/or humidity, is described in U.S. Publication No. 2006/0269087.

Optically clear diaphragm for an acoustic transducer and method for making same


A normalization system for multi-photodetector single photon counting luminescent measuring systems and a standard for use in the same. The method comprises calculating one or more counting ratios for each photodetector in the single photon counting system and multiplying counts of unknown samples by the inverse of the appropriate counting ratio. A counting ratio for a particular photodetector is calculated by dividing the count of a standard measured by the photodetector by the count of the same standard measured by a reference photodetector. The particular standard developed employs calcium tungstate:lead as a scintillator and tritium or carbon-14 thymidine as a means of exciting the scintillator. This standard has the advantages of providing a good model of typical luminescence chemistry and producing an emission pattern which is susceptible to single photon counting.

With the advent of multiple detector, single-photon counting systems, a need has developed to normalize an array of photodetectors so that the measure of luminescence is independent of which photodetector performs the measurement.
Furthermore, in modelling chemiluminescent and bioluminescent emissions, it is generally desirable to use a standard with a peak wavelength approximately the same as that of the sample which is to be measured. While numerous radiophosphorescent standards have been developed to model low intensity emissions which are typical of chemiluminescent and bioluminescent samples, none have a decay constant long enough for single photon counting systems and a peak wavelength which matches that of the typical luminescence chemistry, e.g., approximately 430 nanometers.

Normalization technique for photon-counting luminometer


The present invention generally relates to methods and apparatuses for ensuring the integrity of probe card assemblies, verifying that probe cards are ready for testing, and allowing analysis of probe card performance characteristics. In one embodiment, an apparatus allows rework of a probe card at an angle from a front position of the apparatus.

1. Field of the Invention
Embodiments of the present invention generally relate to integrated circuit testing, and more particularly, to apparatuses and methods for testing probe cards used to test integrated circuits on a wafer.
2. Description of the Related Art
Probe card test and verification systems are commonly used as production tools for the characterization of probe cards (used in testing integrated circuit devices/substrates) before and after use and to facilitate rework of probe cards that do not conform to predefined standards. Such systems typically consist of a computer, a precision measurement system, a software based vision system, and precision motion control and measurement system. Such equipped systems allow for the measurement and adjustment of probe card planarization, visual X/Y location and adjustment, probe contact resistance, leakage and component measurements.
Electrical parameters including contact resistance and leakage may also be measured against reference values and an indication may be provided as to whether a probe card assembly under test has passed or failed. If a failure is determined, a full report may be printed to accompany the card for rework. Quick verification provided by such systems may validate that a probe card assembly is ready for test or is in need of rework.
Therefore, there is a continuing need to improve such systems to that ensure the integrity of probe card assemblies, verify that probe cards are ready for testing, and allow analysis of probe card performance characteristics.