A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

1. Field of the Invention
The present invention relates to a semiconductor memory and its production process, and more particularly, the invention relates to a semiconductor memory provided with a memory transistor having a charge storage layer and a control gate, and its production process.
2. Description of Related Art
As a memory cell of an EEPROM, is known a device of a MOS transistor structure having a charge storage layer and a control gate in a gate portion, in which an electric charge is injected into and released from the charge storage layer by use of a tunnel current. In this memory cell, data "0" and "1" is stored as changes in a threshold voltage by the state of the charge in the charge storage layer. For example, in the case of an n-channel memory cell using a floating gate as the charge storage layer, when a source/drain diffusion layer and a substrate are grounded and a high positive voltage is applied to the control gate, electrons are injected from the substrate into the floating gate by a tunnel current. This injection of electrons shifts the threshold voltage of the memory cell toward positive. When the control gate is grounded and a high positive voltage is applied to the source/drain diffusion layer or the substrate, electrons are released from the floating gate to the substrate by the tunnel current. This release of electrons shifts the threshold voltage of the memory cell toward negative.
In the above-described operation, a relationship of capacity coupling between the floating gate and the control gate with capacity coupling between the floating agate and the substrate plays an important role in effective injection and release of electrons, i.e., effective writing and erasure. That is, the larger the capacity between the floating gate and the control gate, the more effectively the potential of the control gate can be transmitted to the floating gate and the easier the writing and erasure become.
With recent development in semiconductor technology, especially, in micro-patterning techniques, the size reduction and the capacity increase of memory cells of EEPROM are rapidly progressing. Accordingly, it is an important how large capacity can be ensured between the floating gate and the control gate.
For increasing the capacity between the floating gate and the control gate, it is necessary to thin a gate insulating film therebetween, to increase the dielectric constant of the gate insulating film or to enlarge an area where the floating gate opposes the control gate.
However, the thinning of the gate insulating film is limited in view of reliability of memory cells. For increasing the dielectric constant of the gate insulating film, a silicon nitride film is used as the gate insulating film instead of a silicon oxide film. This is also questionable in view of reliability and is not practical. Therefore, in order to ensure a sufficient capacity between the floating gate and the control gate, it is necessary to set a sufficient overlap area therebetween. This is, however, contradictory to the size reduction of memory cells and the capacity increase of EEPROM.
In an EEPROM disclosed by Japanese Patent No.2877462, memory transistors are formed by use of sidewalls of a plurality of pillar-form semiconductor layers arranged in matrix on a semiconductor substrate, the pillar-form semiconductor layers being separated by trenches in a lattice form. A memory transistor is composed of a drain diffusion layer formed on the top of a pillar-form semiconductor layer, a common source diffusion layer formed at the bottom of the trenches, and a charge storage layer and a control gate which are around all the periphery of the sidewall of the pillar-form semiconductor layer. The control gates are provided continuously for a plurality of pillar-form semiconductor layers lined in one direction so as to form a control gate line, and a bit line is connected to drain diffusion layers of a plurality of memory transistors lined in a direction crossing the control gate line. The charge storage layer and the control gate are formed in a lower part of the pillar-form semiconductor layer. This construction can prevent a problem in a one transistor/one cell structure, that is, if a memory cell is over-erased (a reading potential is 0 V and the threshold is negative), a cell current flows in the memory cell even if it is not selected.
With this construction, a sufficiently large capacity can be ensured between the charge storage layer and the control gate with a small area occupied. The drain regions of the memory cells connected to the bit lines are formed on the top of the pillar-form semiconductor layers and completely insulated from each other by the trenches. A device isolation region can further be decreased and the memory cells are reduced in size. Accordingly, it is possible to obtain a mass-storage EEPROM with memory cells which provide excellent writing and erasing efficiency.
The prior-art EEPROM is explained with reference to figures. FIG. 800 is a plan view of a prior-art EEPROM, and FIGS. 801(a) and 801(b) are sectional views taken on lines A–A′ and B–B′, respectively, in FIG. 800.
In FIG. 800, pillar-form silicon semiconductor layers 2 are columnar, that is, the top thereof is circular. However, the shape of the pillar-form silicon semiconductor layers need not be columnar. In the plan view of FIG. 800, selection gate lines formed by continuing gate electrodes of selection gate transistors are not shown for avoiding complexity of the figure.
In the prior art, is used a P-type silicon substrate 1, on which a plurality of pillar-form P-type silicon layers 2 are arranged in matrix. The pillar-form P-type silicon layers 2 are separated by trenches 3 in a lattice form and functions as memory cell regions. Drain diffusion layers 10 are formed on the top of the silicon layers 2, common source diffusion layers 9 are formed at the bottom of the trenches 3, and oxide films 4 are buried at the bottom of the trenches 3. Floating gates 6 are formed in a lower part of the silicon layers 2 with intervention of tunnel oxide films 5 so as to surround the silicon layers 2. Outside the floating gates 6, control gates 8 are formed with intervention of interlayer insulating films 7. Thus memory transistors are formed. Here, as shown in FIGS. 800 and 801(b), the control gates 8 are provided continuously for a plurality of memory cells in one direction so as to form control gate lines (CG1, CG2, . . . ). Gate electrodes 32 are provided around an upper part of the silicon layers 2 with intervention of gate oxides films 31 to form the selection gate transistors, like the memory transistors. The gate electrodes 32 of the selection gate transistors, like the control gates 8 of the memory cells, are provided continuously in the same direction as that of the control gates 8 of the memory cells so as to form selection gate lines, i.e., word lines WL (WL1, WL2, . . . ).
Thus, the memory transistors and the selection gate transistors are buried in the trenches in a stacked state. The control gate lines leave end portions as contact portions 14 on the surface of silicon layers, and the selection gate lines leaves contact portions 15 on silicon layers on an end opposite to the contact portions 14 of the control gates. Al wires 13 and 16 to be control gate lines CG and the word lines WL, respectively, are contacted to the contact portion 14 and 15, respectively. At the bottom of the trenches 3, common source diffusion layers 9 of the memory cells are formed, and on the top of the silicon layers 2, drain diffusion layers 10 are formed for every memory cell. The resulting substrate with the thus formed memory cells is covered with a CVD oxide film 11, where contact holes are opened. Al wires 12 are provided which are to be bit lines BL which connects the drain diffusion layers 10 of memory cells lined in a direction crossing the word lines WL. When patterning is carried out for the control gate lines, a mask is formed of PEP on pillar-form silicon layers at an end of a cell array to leave, on the surface of the silicon layers, the contact portions 14 of a polysilicon film which connect with the control gate lines. To the contact portions 14, the Al wires 13 which are to be control gate lines are contacted by Al films formed simultaneously with the bit lines BL.
A production process for obtaining the structure shown in FIG. 801(a) is explained with reference to FIGS. 801(a) to 805(g). A P-type silicon layer 2 with a low impurity concentration is epitaxially grown on a P-type silicon substrate 1 with a high impurity concentration to give a wafer. A mask layer 21 is deposited on the wafer and a photoresist pattern 22 is formed by a known PEP process. The mask layer 21 is etched using the photoresist pattern 22 (see FIG. 802(a)).
The silicon layer 2 is etched by a reactive ion etching method using the resulting mask layer 21 to form trenches 3 in a lattice form which reach the substrate. Thereby the silicon layer 21 is separated into a plurality of pillar-form islands. A silicon oxide film 23 is deposited by a CVD method and anisotropically etched to remain on the sidewalls of the pillar-form silicon layers 2. By implantation of N-type impurity ions, drain diffusion layers 10 are formed on the top of the pillar-form silicon layers 2 and common source diffusion layers 9 are formed at the bottom of the trenches (see FIG. 802(b)).
The oxide films 23 around the pillar-form silicon layers 2 are etched away by isotropic etching. Channel ion implantation is carried out on the sidewalls of the pillar-form silicon layers 2 by use of a slant ion implantation as required. Instead of the channel ion implantation, an oxide film containing boron may be deposited by a CVD method with a view to utilizing diffusion of boron from the oxide film. A silicon oxide film 4 is deposited by a CVD method and isotropically etched to be buried at the bottom of trenches 3. Tunnel oxide films 5 are formed to a thickness of about 10 nm around the silicon layers 2 by thermal oxidation. A first-layer polysilicon film 5 is deposited and anisotropically etched to remain on lower sidewalls of the pillar-form silicon layers 2 as floating gates 6 around the silicon layers 2 (see FIG. 803(c)).
Interlayer insulating films 7 are formed on the surface of the floating gates 5 formed around the pillar-form silicon layers 2. The interlayer insulating films 7 are formed of an ONO film, for example. The ONO film is formed by oxidizing the surface of the floating gate 6 by a predetermined thickness, depositing a silicon nitride film by a plasma-CVD method and then thermal-oxidizing the surface of the silicon nitride film. A second-layer polysilicon film is deposited and anisotropically etched to form control gates 8 on lower parts of the pillar-form silicon layers 2 (see FIG. 803(d)). At this time, the control gates 8 are formed as control gate lines continuous in a longitudinal direction in FIG. 800 without need to perform a masking process by previously setting intervals between the pillar-form silicon layers 2 in the longitudinal direction at a predetermined value or less. Unnecessary parts of the interlayer insulating films 7 and underlying tunnel oxide films 2 are etched away. A silicon oxide film 111 is deposited by a CVD method and etched halfway down the trenches 3, that is, to a depth such that the floating gates 6 and control gates 8 of the memory cells are buried and hidden (see FIG. 804(e)).
A gate oxide film 31 is formed to a thickness of about 20 nm on exposed upper parts of the pillar-form silicon layers 2 by thermal oxidation. A third-layer polysilicon film is deposited and anisotropically etched to form gate electrodes 32 of MOS transistors (see FIG. 804(f)). The gate electrodes 32 are patterned to be continuous in the same direction as the control gate lines run, and form selection gate lines. The selection gate lines can be formed continuously in self-alignment, but this is more difficult than the control gates 8 of the memory cells. For, the selection gate transistors are single-layer gates while the memory transistors are two-layered gates, and therefore, the intervals between adjacent selection gates are wider than the intervals between the control gates. Accordingly, in order to ensure that the gate electrodes 32 are continuous, the gate electrodes may be formed in a two-layer polysilicon structure, a first polysilicon film may be patterned to remain only in locations to connect the gate electrodes by use of a masking process, and a second polysilicon film may be left on the sidewalls.
Masks for etching the polysilicon films are so formed that contact portions 14 and 15 of the control gate lines and the selection gate lines are formed on the top of the pillar-form silicon layers at different ends. A silicon oxide film 112 is deposited by a CVD method and, as required, is flattened. Contact holes are opened. An Al film is deposited and patterned to form Al wires 12 to be bit lines BL, Al wires 13 to be control gate lines CG and Al wires 16 to be word lines WL at the same time (see FIG. 805(g)).
FIG. 806(a) schematically shows a sectional structure of a major part of one memory cell of the prior-art EEPROM, and FIG. 806(b) shows an equivalent circuit of the memory cell. The operation of the prior-art EEPROM is briefly explained with reference to FIGS. 806(a) to 806(b).
For writing by use of injection of hot carriers, a sufficiently high positive potential is applied to a selected word line WL, and positive potentials are applied to a selected control gate line CG and a selected bit line BL. Thereby, a positive potential is transmitted to the drain of a memory transistor Qc to let a channel current flow in the memory transistor Qc and inject hot carriers. Thereby, the threshold of the memory cell is shifted toward positive. For erasure, 0 V is applied to a selected control gate CG and high positive potentials are applied to the word line WL and the bit line BL to release electrons from the floating gate to the drain. For erasing all the memory cells, a high positive potential may be applied to the common sources to release electrons to the sources. Thereby, the thresholds of the memory cells are shifted toward negative. For reading, the selection gate transistor is rendered ON by the word line WL and the reading potential is applied to the control gate line CG. The judgement of a "0" or a "1" is made from the presence or absence of a current.
In the case where an FN tunneling is utilized for injecting electrons, high potentials are applied to a selected control gate line CG and a selected word line WL and 0 V is applied to a selected bit line BL to inject electrons from the substrate to the floating gate.
This prior art provides an EEPROM which does not mis-operate even in an over-erased state thanks to the presence of the selection gate transistors.
The prior-art EEPROM does not have diffusion layers between the selection gate transistors Qs and the memory transistors Qc as shown in FIG. 806(a). For, it is hard to form the diffusion layers selectively on the sidewalls of the pillar-form silicon layers. Therefore, in the structure shown in FIGS. 801(a) and 801(b), desirably, separation oxide films between the gates of the memory transistors and the gates of the selection gate transistors are as thin as possible. In the case of utilizing the injection of hot electrons, in particular, the separation oxide films need to be about 30 to 40 nm thick for allowing a sufficient "H" level potential to be transmitted to the drain of a memory transistor. Such fine intervals cannot be practically made only by burying the oxide films by the CVD method as described above in the production process. Accordingly, desirably, the oxide films are buried in such a manner that the floating gates 6 and the control gates 8 are exposed, and thin oxide films are formed on exposed parts of the floating gates 6 and the control gates 8 simultaneously with the formation of the gate oxide films for the selection gate transistors.
Further, according to the prior art, since the pillar-form silicon layers are arranged with the bottom of the lattice-form trenches forming an isolation region and the memory cells are constructed to have the floating gates formed to surround the pillar-form silicon layers, it is possible to obtain a highly integrated EEPROM in which the area occupied by the memory cells are small. Furthermore, although the memory cells occupy a small area, the capacity between the floating gates and the control gates can be ensured to be sufficiently large.
According to the prior art, the control gates of the memory cells are formed to be continuous in one direction without using a mask. This is possible, however, only when the pillar-form silicon layers are arranged at intervals different between a longitudinal direction and a lateral direction. That is, by setting the intervals between adjacent pillar-form silicon layers in a word line direction to be smaller than the intervals between adjacent pillar-form silicon layers in a bit line direction, it is possible to obtain control gate lines that are separated in the bit line direction and are continuous in the word line direction automatically without using a mask.
In contrast, when the pillar-form silicon layers are arranged at the same intervals both in the longitudinal direction and in the lateral direction, a PEP process is required. More particularly, the second-layer polysilicon film is deposited thick, and through the PEP process to form a mask, the second-layer polysilicon film is selectively etched to remain in locations to be continuous as control gate lines. The third-layer polysilicon film is deposited and etched to remain on the sidewalls as described regarding the production process of the prior art. Even in the case where the pillar-form silicon layers are arranged at intervals different between the longitudinal direction and the lateral direction, the continuous control gate lines cannot be automatically formed depending upon the intervals of the pillar-form silicon layers. In this case, the mask process by the PEP process as described above can be used for forming the control gate lines continuous in one direction.
Although the memory cells of the prior art as described above are of a floating gate structure, the charge storage layers do not necessarily have the floating gate structure and may have a structure such that the storage of a charge is realized by a trap in a laminated insulating film, e.g., a MNOS structure.
FIG. 807 is a sectional view of a prior-art memory with memory cells of the MNOS structure, corresponding to FIG. 801(a). A laminated insulating film 24 functioning as the charge storage layer is of a laminated structure of a tunnel oxide film and a silicon nitride film, or of a tunnel oxide film, a silicon nitride film and further an oxide film formed on the silicon nitride film.
FIG. 808 is a sectional view of a prior-art memory in which the memory transistors and the selection gate transistors of the above-described prior art are exchanged, i.e., the selection gate transistors are formed in the lower parts of the pillar-form silicon layers 2 and the memory transistors are formed in the upper parts of the pillar-form silicon layers 2. FIG. 808 corresponds to FIG. 801(a). This structure in which the selection gate transistors are provided on a common source side can apply to the case where the injection of hot electrons is used for writing.
FIG. 809 shows a prior-art memory in which a plurality of memory cells are formed on one pillar-form silicon layer. Like numbers denote like components in the above-described prior-art memories and the explanation thereof is omitted.
In this memory, a selection gate transistor Qs1 is formed in the lowermost part of a pillar-form silicon layer 2, three memory transistors Qc1, Qc2 and Qc3 are laid above the selection gate transistor Qs1, and another selection gate transistor Qs2 is formed above. This structure can be obtained basically by repeating the aforesaid production process.
As described above, the prior-art techniques can provide highly integrated EEPROMs whose control gates and charge storage layers have a sufficient capacity therebetween and whose memory cells occupy a decreased area, by constructing the memory cells using memory transistors having the charge storage layers and the control gates by use of the sidewalls of the pillar-form semiconductor layers separated by the lattice-form trenches.
However, if a plurality of memory cells are connected in series on one pillar-form semiconductor layer and the thresholds of the memory cells are supposed to be the same, significant changes take place in the thresholds of memory cells at both ends of the memory cells connected in series owing to a back-bias effect of the substrate in a reading operation. In the reading operation, the reading potential is applied to the control gate lines CG and the "0" or "1" is judged from the presence of a current. For this reason, the number of memory cells connected in series is limited in view of the performance of memories. Therefore, the production of mass-storage memories is difficult to realize.
The problem that the thresholds of memory cells are changed owing to a back-bias effect is true not only of the case where a plurality of memory cells are connected in series on one pillar-form semiconductor layer but also of the case where one memory cell is formed on one pillar-form semiconductor, depending upon variations in the back-bias effect of the substrate in an inplanar direction.
In the prior art memory, an impurity diffusion layer is not formed between memory cells on the same pillar-form semiconductor layer. However, it is preferable that an impurity diffusion layer is formed therebetween.
Furthermore, in the prior-art memories, the charge storage layers and the control gates are formed in self-alignment with the pillar-form semiconductor layers. Taking mass storage of the cell array into consideration, the pillar-form semiconductor layers are preferably formed at the minimum photoetching dimension.
In the case where the floating gates are used as the charge storage layers, the capacity coupling between the floating gates and the control gates and between the floating gates and the substrate is determined by the area of the outer periphery of the pillar-form semiconductor layers, the area of the outer periphery of the floating gate, the thickness of the tunnel oxide films insulating the floating gates from the pillar-form semiconductor layers and the thickness of the interlayer insulating films insulating the floating gates form the control gates. In the prior-art memories, the charge storage layers and the control gates are formed to surround the pillar-form semiconductor layers by utilizing the sidewalls of the pillar-form semiconductor layers in order that the capacity between the charge storage layers and the control gates is ensured to be sufficiently large. However, in the case where the pillar-form semiconductor layers are formed at the minimum photoetching dimension and the thickness of the tunnel oxide films and that of the interlayer insulating film are fixed, the capacity between the charge storage layers and the control gates is determined simply by the area of the outer periphery of the floating gates, that is, the thickness of the floating gates. Therefore, it is difficult to increase the capacity between the charge storage layers and the control gates without increasing the area occupied by the memory cells. In other words, it is difficult to increase the ratio of the capacity between the floating gates and the control gates to the capacity between the floating gates and the pillar-form semiconductor layers without increasing the area occupied by the memory cells.
Further, if transistors are formed in a direction vertical to the substrate stage by stage, there occur variations in characteristics of the memory cells owing to differences in the properties of the tunnel oxide films and differences in the profile of diffusion layers. Such differences are generated by thermal histories different stage by stage.

Semiconductor memory and its production process


A barn for raising hogs includes walls, a roof, and a floor within the structure for supporting the hogs, the floor being solid such that materials on the floor settle on the floor without passing therethrough and being capable of supporting an animal and the floor including at least one sloped surface and a waste collection area at a lower end of the sloped surface and an animal feeding station adjacent an upper end of the sloped surface. A process is also taught for raising hogs it includes confining hogs on a solid floor, applying compostable, fibrous material to the solid floor, collecting manure-soiled fibrous material from the floor and composting the manure-soiled fibrous material to form a nutrient rich material suitable for use as a compost soil or soil supplement.

The present invention is directed to livestock farming processes and barns and in particular to processes and barns for raising hogs.
In previous hog farming processes, the hogs are raised in barns with slotted floors. The animal waste drops through the slots in the floor and into a pit, which is normally water filled. The pit is emptied into a holding lagoon outside the barn until it is used for spraying on fields. This process has met with public resistance because of the associated odour and appearance of the outside holding lagoon and health concerns over risk of water contamination.
In addition, the hogs were sometimes under stress because of the cold and cramped barn and slotted floors. The slotted floors tend to be damaging to the hogs hoofed feet. In addition, drafts and moisture rise from the manure mixture below. These conditions can require that the hogs be administered antibiotics to maintain them in a healthy, docile state.
A hog farming process and barn have been invented that reduce animal stress and effectively handle manure waste without open lagoons.
In one aspect of the present invention, there is provided a barn for raising hogs, the barn comprising: a structure including walls and a roof, a floor within the structure for supporting the hogs, the floor being solid such that materials can settle on the floor without passing therethrough and capable of supporting an animal and the floor including at least one sloped surface and a waste collection area at a lower end of the sloped surface and an animal feeding station providing access to food and water and positioned adjacent an upper end of the sloped surface.
In one embodiment, the barn includes means for creating a temperature differential between an area adjacent the upper end of the sloped surface and an area adjacent the lower end of the sloped surface. The means for creating a temperature differential can be a heater provided to heat an area of the barn adjacent the upper end of the sloped surface. Alternately or in addition, the means for creating a temperature differential is an air circulation system for creating an air draft above the waste collection area.
The animal feeding station is preferably a feeder that contains water in a liquid collection dish. In addition, on-demand means can be provided in the feeder such that food and/or water is released only upon demand of an animal.
In one embodiment, the barn includes at least two sloped surfaces inclining downwardly towards each other and toward the waste collection area. The waste collection area is preferably substantially flat to facilitate waste pick up. Walls can be arranged over the sloping surfaces and the waste collection area to create pens for containment of animals. In one embodiment, the walls have open areas permitting visual communication between the pens. Preferably, these open areas are adjacent the waste collection area.
In another aspect of the present invention there is provided a process for raising hogs, the process comprising: confining hogs on a solid floor, applying compostable, fibrous material to the solid floor, collecting the manure-soiled fibrous material from the floor and composting the manure-soiled fibrous material to form a nutrient rich material.
The fibrous material can be, for example, finely chopped straw, finely chopped newsprint or sawdust. Sawdust is preferred as it also has a pleasant, wood scent that reduces the manure odor within the barn.
In a preferred process, the hogs are confined on a floor that is sloped toward a waste collection area to promote movement of the manure-soiled fibrous material by gravity toward the waste collection area. The floor can additionally include an area conducive to animal sleeping. The process can further include controlling the environment to enhance defecation in the waste collection area.


A character recognition method which accurately recognizes characters contacting or adjacent to a ruled line. Black runs each having a length greater than a predetermined length are extracted from the original binary image. A ruled line rectangle defined by adjacent black runs is extracted from among the extracted black runs so that the ruled line rectangle completely encircles the adjacent black runs which are within a predetermined short distance from each other. Black pixels contained in the ruled line rectangle are deleted from the original binary image. Then, a recognition is performed for characters contained in the original binary image.

1. Field of the Invention
The present invention generally relates to an image processing method for processing image data obtained from a ruled document and, more particularly, to a method for deleting ruled lines contained in image data obtained by scanning a document and a character recognition method using such a method for accurately recognizing characters surrounded by or adjacent to the ruled lines.
2. Description of the Related Art
Many documents or preformatted sheets are provided with ruled lines or frame lines. In order to read characters within an area defined by the ruled lines or frame lines, it is common to distinguish the characters from the ruled lines or frame lines by providing different colors to the rules lines or frame lines and the characters, as is suggested in Japanese Laid-Open Patent Application No.56-9877. In this method, image information obtained by optically scanning a document having ruled lines or frame lines is classified into each color image information. To use this method, ruled lines or frame lines must be printed with a predetermined specific color by considering the spectral characteristic of scanners to be used. Thus, there is a problem in that cost for preparing or printing a document with colored ruled lines or frame lines must be added to the cost of the blank document. That is, an additional cost is required for printing the ruled lines or frame lines with a specific color. Additionally, it is inconvenient for a user to use a writing tool of a specific color which is different from the color of the ruled lines or frame lines when writing characters within the area defined by the ruled lines or frame lines.
On the other hand, in recent years, it has become common to print the ruled lines or frame lines on a regular print paper by a word processor. Japanese Laid-Open Patent Applications No. 61-196382 and No. 2-7183 suggest methods for separating characters from ruled lines or frame lines. In these methods, a histogram of high-intensity pixels in the image obtained from the document is produced. The ruled lines or frame lines are extracted from a peak of the histogram so as to delete the ruled lines or frame lines prior to performing a recognition process of characters in the area defined by the ruled lines or frame lines.
However, the method suggested in Japanese Laid-Open Patent Application No. 61-196382 has a problem in that an area defined by the ruled lines or frame lines cannot be accurately detected when the document provided with the ruled lines or frame lines is inclined with respect to the scanning direction since positions of the ruled lines or frame lines are detected from the histogram of high-intensity pixels (black pixels). Additionally, the method suggested in Japanese Laid-Open Patent Application No. 2-7183 has a problem in that an area of the ruled lines or frame lines for an unknown document cannot be accurately detected for an unknown document since an area divided by the ruled lines or frame lines cannot be accurately recognized. This is because, in the method suggested in Japanese Laid-Open Patent Application No. 2-7183, extending ranges of the ruled lines or frame lines are detected from projection patterns obtained by dividing the document area along a direction perpendicular to a direction of lines in the document.
When character recognition is performed on a document image including ruled lines or frame lines, the characters should be recognized, in most cases, by an area (hereinafter referred to as a ruled area) encircled by ruled lines or frame lines. In order to achieve this, the ruled lines or frame lines must be detected before the character recognition is performed.
As a method for recognizing the ruled area, it is common to recognize the ruled area as rectangular areas by extracting the vertical and horizontal ruled lines and using coordinate values of the inner sides of the rectangular areas. However, there is a problem in that the ruled area is recognized as an area smaller than the actual ruled area when the scanned image or the document is inclined, as described below.
A description will now be given in more detail, with reference to FIG. 1, of the above-mentioned problem. FIG. 1 shows the ruled area defined by horizontal ruled lines 300 and 301, and vertical ruled lines 303 and 304. If the ruled area is inclined as shown in FIG. 1, a width of each the rectangular areas 300a, 301a, 303a and 304a corresponding to the respective ruled lines 300, 301, 303 and 304 is increased in response to a degree of inclination. In FIG. 1, the ruled area recognized by using coordinate values of the inner sides of the rectangular areas 300a, 301a, 303a and 304a corresponds to the rectangular area defined by points Aa, Ba, Ca and Da. Since the actual ruled area corresponds to a rectangular area defined by points A, B, C and D, the recognized ruled area is smaller than the actual ruled area. Thus, in this method, parts of characters adjacent to the ruled lines may be encompassed within the rectangular areas, resulting in an inaccurate recognition of the characters.
Japanese Laid-Open Patent Application No. 3-172984 suggests a different method. In this method, similarly to the above-mentioned method, rectangular areas corresponding to vertical and horizontal ruled lines are extracted so as to define the ruled area. However, in this method, the ruled area is recognized based on the outer sides of the rectangular areas. That is, in this method, the ruled area is recognized as a rectangular area defined by points Ab, Bb, Cb and Db shown in FIG. 1. This rectangular area recognized as the ruled area is larger than the actual ruled area defined by the points A, B, C and D. In this method, characters are extracted by using the rectangular area defined by the points Ab, Bb, Cb and Db. Thus, the number of characters which are not accurately recognized are decreased.
However, in the method suggested in Japanese Laid-Open Patent Application No. 3-172984, when inclination of the document is large, the black runs corresponding to the characters contacting or adjacent to a ruled line may be combined with the black runs corresponding to that ruled line. As a result, the characters contacting or adjacent to the ruled line may not be accurately recognized. Additionally, there is a problem in that characters outside the ruled area defined by the actual ruled lines may be erroneously recognized as characters included in the ruled area since the assumed ruled area is larger than the actual ruled area.

Character recognition method using a method for deleting ruled lines


Automotive window glass to which a molding for sealing space between a car body and the window glass is to be attached, the window glass including, an attachment starting point mark indicating an attachment starting point of the molding, and at least one of a termination starting point mark and a termination last point mark in a specification range in which a termination of the molding, of which an attachment to the window glass being started from the attachment starting point, is to be placed.

Field of the Invention
This invention relates to automotive window glass with an outer periphery to which a molding for sealing space between a car body and the window glass is to be attached, method for attaching the molding, and method for manufacturing the automotive window glass.
Related Art
A member called a molding is attached to the outer periphery of automotive window glass for sealing space between the window glass and a car body. To determine the position of such a molding easily while the molding is to be fitted to window glass along its outer periphery, markings have been placed on both the window glass and the molding (see Japanese Unexamined Patent Application, Publication No. H06-297942).

Automotive window glass, method for attaching a molding, and method for manufacturing automotive window glass


A method and apparatus for implementing DC mode selection in a data access arrangement (DAA). The present invention overcomes the geographic constraints of the prior art by providing a plurality of selectable DC modes. Each of the selectable DC modes may be designed to meet the DC mask specifications of a desired country or region. The apparatus of the present invention may then be utilized in any of the desired countries or regions by selecting the appropriate DC mode. To accommodate several possible DC mask parameters, embodiments of the present invention include selection between a plurality of DC mode voltage levels, selection between current limiting and non-current limiting DC modes, and selection between a plurality of current limit values. Control elements, such as opto-couplers controlled by a microcontroller, are used to perform the selection by enabling and disabling circuit elements or connections. One embodiment provides for temperature compensation of DC current limiting. A thermistor with a negative temperature coefficient compensates for temperature variance in a feedback transistor to maintain stable current limiting performance over a range of temperatures.

1. Field of the Invention
This invention relates to the field of data communication equipment, and in particular to artificial inductors in data access arrangements.
2. Background Art
Telephone systems were originally designed for simple voice communication. As new technologies have emerged, methods have been devised to provide more advanced voice communication functions, as well as to transmit other types of information over telephone lines. These methods typically require the connection of electronic equipment, other than the voice telephone set, to the telephone line. Examples of such equipment include computer modems, facsimile ("fax") machines, answering machines, voice mail systems, phone patches, automatic number identification (ANI) or "Caller ID" systems, and advanced telephone systems.
The electrical characteristics of signals present within the above equipment often differ from the electrical characteristics permitted on a standard twisted-pair telephone line used to connect the equipment to a central office (CO) of the local telephone service provider. An interface circuit referred to as a data access arrangement (DAA) is utilized to couple the equipment to the telephone line. The data access arrangement typically provides isolation, impedance matching, and sometimes amplification, filtering and control functions.
Unfortunately, the specifications for data access arrangements may differ from region to region or country to country to meet the electrical operating parameters of the respective central office. Therefore, a particular data access arrangement has utility only in those countries where the operating specifications are met. The relationship between the data access arrangement and the central office is more clearly understood with reference to a sample data access arrangement as illustrated in FIG. 1.

Method and apparatus for implementing DC mode selection in a data access arrangement


A sequential catalysis of the ring opening polymerization of cyclic organosiloxanes using a base catalyst that can be neutralized by a subsequent redistribution and condensation catalyst such as a Lewis acid catalyst, preferably a phosphonitrilic compound, permits the rapid synthesis of functionalized and poly-functionalized silicone copolymers such as alkenyl hydride copolymers, a new composition of matter. The instant claims are drawn to branched siloxanes having both Si--H and Si-alkenyl groups.

Polydimethylsiloxane fluids may be conveniently prepared by any of several synthetic methods. A common and widely used industrial process to prepare such fluids involves the hydrolysis of halo-functional silanes followed by condensation. A second process begins with cyclic organosiloxanes utilizing a ring-opening polymerization to produce either a kinetically or equilibrium controlled mixture of linear and cyclic organosiloxane compounds.
Ring-opening polymerization of cyclic organosiloxanes may be accomplished by either acid or base catalysis. The catalysts that have been successfully employed range from very acidic catalysts such as trifluoromethane sulfonic acid to very basic such as potassium hydroxide or potassium silanolate. A wide variety of acid catalysts have been employed to catalyze ring opening polymerization, sulfuric acid, acid washed clays, acidic ion exchange resins and linear phosphonitrilic chlorides (LPNC).
While ring opening polymerization may be accomplished with either an acidic or basic catalyst, the preparative chemistry of hydrogen containing siloxanes (i.e. silyl hydrides) is restricted to the acidic catalysts. When a basic catalyst is used, the ring opening polymerization proceeds, but base catalyzed hydride abstraction produces hydroxy functionalities in place of the hydrogen functionalities and the material condenses through the silanol groups. While this produces a polymer, it produces a cross-linked polymer in contrast to a linear polymer.
Process considerations in the choice of an acidic catalyst for the preparation of hydrogen organosiloxanes tend to require the milder acid catalysts in contrast to sulfuric acid and trifluoromethane sulfonic acid because these acids are very strong and highly corrosive. The use of such strong acids requires the use of special alloys in process vessels to avoid acid induced corrosion and contamination of the resulting product.
Milder acid catalysts such as the acid washed clays and acidic ion exchange resins possess drawbacks that while avoiding the corrosion and contamination problems associated with strong acid attack on metal process vessels, cause other problems. The acidic ion exchange resins do not maintain catalytic activity well for any significant and economically useful period of time, requiring frequent regeneration or refreshment. Acid washed clays are generally used as powders to improve contacting efficiency between the reaction substrate and the catalyst which necessitates a downstream filtration to remove the acid washed clay catalyst fines from the product Further, acid washed clays generally contain residual amounts of water that contributes to a hydride silanol interchange that results in a gradual and undesired condensation polymerization of the hydride product. By comparison to the stronger acid catalysts, these milder acid catalysts suffer from lower reaction rates and thus a lower production of product per unit time at any given temperature.
While the kinetic rate deficiencies of any given catalyst may be offset by an increase in temperature, this solution has at least two serious drawbacks. The first is that as temperature is changed, i.e. increased, the relative proportions of reactants, desired products and undesired by-products change. This change may either benefit the desired process or be a detriment depending on the relative amounts of the desired product as a function of the increased temperature because the equilibrium constant for the reaction is a function of temperature. As the temperature is increased, the amount of energy furnished the reaction to increase the temperature must be increased (for endothermic reactions) and this almost always adversely affects the process economics. There is thus a complex balancing between the desired reaction rate, the desired product mix, catalyst activity and process operating variables.
In contrast to the acid catalysts that must either be neutralized, e.g. sulfuric acid, or separated from the product, e.g. acid washed clays, phosphonitrilic halides, particularly linear phosphonitrilic chlorides (LPNC), have found particular use for the redistribution and condensation of organosiloxane oligomers. These LPNC catalysts may be used at fairly low levels in the reaction being catalyzed, e.g. between 25 and 2,000 ppm. An additional advantage is that the catalyst may be left in the product and thermally deactivated if desired. This procedure usually does not result in any significant contamination of the product.
While the LPNC catalysts have been particularly useful for redistribution and condensation reactions involving silicones and siloxanes, they have not usually been used for ring opening polymerization because of the low rates associated with these catalysts in reactions of this type. While it is possible to achieve acceptable reaction rates in the synthesis of hydride siloxane organosiloxane copolymers when the hydride level is above approximately 1,000 ppm, the rate of ring opening polymerization in the presence of a low hydride level siloxane (.about.300 ppm) is extremely slow requiring a matter of days as opposed to hours. Thus LPNC materials would not be expected to be particularly well suited to catalyze ring opening polymerization in the presence of low hydride content siloxanes to make low hydride content siloxane polymers.

Process for preparing hydrogen siloxane copolymers


A semiconductor memory is provided to which external data can be written during a self-refresh. Data thus written can be read out and examined to measure the oscillation frequency of the internal refresh oscillator There is no need to use special equipment such as a frequency counter for testing the oscillation frequency, and the oscillation frequency can be tested after chip sealing.

1. Field of the Invention
The present invention relates generally, as is indicated, to a semiconductor memory. More particularly, the present invention relates to a dynamic semiconductor memory generally known as a pseudostatic random-access memory (pseudo-SRAM), a form of dynamic random-access memory (DRAM) having a self-refresh function.
2. Description of the Prior Art
DRAMs are extensively used in various fields because they are smaller in size, have a larger capacity, and are cheaper to fabricate as compared with static random-access memories (SRAMs). However, DRAMs have the disadvantage that they need periodic refreshing in order to retain the stored contents. To cope with this disadvantage, it has been known to provide a pseudo-SRAM which is essentially a DRAM but is provided with a self-refresh function to accomplish automatic refreshing within the chip, thus enabling it to be used as if it were a SRAM.
The self-refresh operation of this pseudoSRAM will be described below with reference to FIGS. 5 and 6.
When, as shown in FIG. 6, the refresh control signal RFSH is set active (i,e., to an "L" or digital "low" state) for more than a prescribed period of time during the inactive (i,e., "H" or digital "high" state) period of the chip select signal CE disabling access to the pseudo-SRAM chip, this state is detected by a refresh controller 32 via an AND circuit 31, shown in FIG. 5. This causes a refresh oscillator 33 to generate a clock signal INTOSC having a constant cycle as shown in FIG. 6. Based on this clock signal, a refresh counter 34 sequentially generates row addresses by incrementing the count. Therefore, there is no need to input an external clock signal or address signal for refresh operations, but self-refresh can be automatically performed using the internal refresh oscillator 33 and refresh counter 34, thus enabling the DRAM to be used like an SRAM by just manipulating the refresh control signal RFSH.
Further, while the self-refresh is being performed, since a NAND circuit 36 is masked via a buffer 35 by the chip select signal CE, write to a memory cell array 37 is inhibited regardless of the state of the write enable signal WE. Since a NAND circuit 38 is also masked via the buffer 35, the output enable signal OE is also disregarded.
The refresh oscillator 33 is usually formed from a ring oscillator consisting of an odd number of inverters connected in a loop form. However, with the refresh oscillator 33 of this type, there is a possibility that the oscillation frequency may vary due to variations in the process conditions of semiconductor fabrication. Therefore, in the prior art semiconductor fabrication process, it has been practiced to provide a test pad on the pseudo-SRAM chip, to directly measure the frequency of the refresh oscillator 33 and to correct any improper deviation of the oscillation frequency by a laser blow or other technique.
The refresh oscillator 33 of the above construction has the further problem that the frequency may also vary or the circuit itself may be damaged during the process of sealing the chip with resin molding. However, once the chip has been sealed with resin molding, it is no longer possible to directly measure the frequency via the test pad, and failure detection can only be achieved indirectly by read/write tests or other methods. Another disadvantage in the prior art is that since an ordinary memory tester is not equipped with a frequency counter, extra measuring equipment is required during pseudo-SRAM fabrication, even when testing the oscillation frequency via the test pad before chip sealing.
In view of the above problems, there is a strong need in the art for a semiconductor memory that can permit the writing of external data even at the time of self-refresh and thereby enables the oscillation frequency of the refresh oscillator to be tested even after chip sealing.
The present invention overcomes the aforementioned shortcomings of the above known pseudo-SRAMs. The present invention is summarized and described in detail below.


An apparatus, system, and method are disclosed for on-demand control of a grid system resource on a grid computing system. An on-demand management apparatus includes a user input module, a parameter module, and a reservation module. The user input module is configured to allow a user to input a parameter control request. The parameter control request corresponds to a performance parameter of the grid computing system. The global parameter module is configured to dynamically change the performance parameter, which corresponds to a performance resource, according to the parameter control request. The global reservation module is configured to reserve the performance resource for a grid computing operation. The on-demand management apparatus is also configured to terminate a performance resource reservation when a client reclaims the performance resources from the grid computing system.

1. Field of the Invention
This invention relates to grid computing and more particularly relates to on-demand control of performance resources on a grid computing system.
2. Description of the Related Art
Grid computing is a relatively new technology in the computing industry. Many current grid computing systems are designed to allow multiple interconnected computers, or nodes, to work together on large grid applications, such as computational problems, that would be impossible to do on a single machine. In order to feasibly manage such overwhelming amounts of computational processing, the computational problem may be divided into several smaller, more manageable jobs. This type of shared processing of grid applications is possible in part because of the enforced or incidental idle processor time of many personal and business computers.
Additionally, grid computing systems may allow for shared storage across a plurality of nodes within the system. In this way, data may be stored remotely on the system, in the form of a backup, for example, and allow large amounts of data to be virtually stored by a single node.
One of the major issues in designing and implementing grid computing systems is resource management. Managing the performance resources available to the grid computing system is fundamental to the efficacy of the system. For example, with various disparate storage, memory, and processing resources available from the many nodes in a grid computing system, somehow these performance resources must be utilized within the grid system in an organized and productive manner.
Some grid computing systems are built exclusively for grid computing operations. In this scenario, all of the performance resources of all of the connected nodes are dedicated to the grid computing system. Although the grid system operation must be assigned out to specific node resources, there is very little need, if any, for such a grid computing system to dynamically manage the allocated performance resources because the amount of resources available to the grid is relatively static. Except for the occasional downtime of a failed device, the performance resources within this type of grid computing system remain dedicated to the grid system.
Other grid computing systems rely on nodes that may be available to the grid computing system infrequently or less than on a dedicated basis. For example, some grid computing systems contain software on each node that performs calculations on data received through the grid computing system. Input data may be transferred to the node during a minimal period of connectivity to the grid computing system. The calculations are performed during system idle time of the node, such as during the operation of a screensaver application. The computational results are then transferred back to the grid server during a subsequent period of connectivity to the grid computing system. Alternately, the calculation may be performed as a background application using processing cycles not utilized for local applications on the node.
However, for grid applications that require substantial connectivity to the grid system for large amounts of data transfer, such as data backup applications, the availability (i.e. accessibility, capacity, etc.) of performance resources on a particular node may become more determinative of the efficacy of the grid computing system. It follows that management of the available performance resources is also more important to the operation of the grid computing system. Unfortunately, conventional grid computing systems are generally inadequate to manage the dynamic availability of performance resources made available to the grid computing system on a non-dedicated basis.
Consequently, a need exists for an apparatus, system, and method that facilitate favorable on-demand control of performance resources on a grid computing system. Beneficially, such an apparatus, system, and method would overcome many of the current performance limitations on non-dedicated grid computing systems.

Apparatus, system, and method for on-demand control of grid system resources

International Business Machines Corporation


A regulator circuit that makes it possible to supply a voltage which enables a load circuit to operate normally, even if an external power supply voltage is momentarily interrupted or dropped, includes a ZD/R parallel circuit (a backflow prevention diode and in parallel with a resistor) that is connected between an external power supply voltage terminal and the drain of a MOSFET.

1. Field of the Invention
The present invention relates to a regulator circuit used in a power conversion device such as an internal combustion engine ignition device, and to a semiconductor integrated circuit device forming the regulator circuit. More particularly, the invention relates to a regulator circuit wherein it is possible to output a voltage which enables a load circuit (one or more circuits serving as a load of the regulator circuit) to operate normally despite a momentary interruption or momentary drop of an external power supply voltage, and to a semiconductor integrated circuit device forming the regulator circuit.
2. Description of the Prior Art
FIG. 8 is a main portion circuit diagram of a commonly used regulator circuit 500 which lowers an external power supply voltage VB. With, for example, a band gap reference circuit used as a reference voltage circuit 55, it is possible to make an output voltage VREG of the regulator circuit 500 a stable voltage to which is added a reference voltage VREF division ratio of resistors (a first resistor 65 and second resistor 66) by using a reference voltage, having no temperature dependence (the reference voltage actually has some temperature dependence, but it is taken here that it has no temperature dependence), which is generated from the reference voltage circuit 55. By setting a current flowing through an MOSFET 56 (an enhancement type n-channel type MOSFET) connected to an external power supply voltage terminal VB into which an external power supply voltage is input (a terminal into which is input an external power supply voltage such as a battery voltage) to be equal to or higher than a current flowing through a load circuit 70, it is possible to make the output voltage VREG of the regulator circuit 500 a set voltage VREG0 which is a constant voltage. It is possible to raise the VREG from the low external power supply voltage VB by using a depression type MOSFET as the MOSFET 56.
Of the reference signs in FIG. 8, 52 is a positive terminal of an operational amplifier 51, 53 is a negative terminal of the operational amplifier 51, 54 is an output terminal of the operational amplifier 51, 57 is a drain of the MOSFET 56, 58 is a source of the MOSFET 56, 59 is a gate of the MOSEFT 56, 65 is the first resistor, 66 is the second resistor, 67 is a first connection point, 68 is a second connection point, 69 is an output terminal of the regulator circuit 500, VB is the external power supply voltage, and VDD is a power supply which drives the operational amplifier 51.
FIGS. 9A and 9B are diagrams showing a behavior of the VB when momentarily interrupted in the regulator circuit 500 of FIG. 8, wherein FIG. 9A is a waveform diagram of the VB, while FIG. 9B is a waveform diagram of the VREG. Herein, the VB is substantially equal to the VREG in a range from VB=0V until the VB rises, but when an enhancement type MOSFET is used, there is originally a region in which the VB drops by the amount of the threshold voltage of the enhancement type MOSFET. An operation of a depression type MOSFET is shown for the sake of simplification. When the VB falls below the VREG and drops to, for example, 0V, the VREG also drops to 0V following the VB. In normal operation, an unshown capacitor (which is small in capacitance particularly when the load circuit is configured of a semiconductor integrated circuit) configuring each of the load circuit 70 is in a condition in which it is charged with the VREG. When a momentary interruption occurs in the VREG, electric charge with which the capacitor is charged is discharged via the external power supply voltage terminal (VB terminal) to an external power supply (battery) side, thus reverse charging the unshown external power supply.
When the capacitor is low in capacitance, the discharge is carried out so that the VREG follows the drop of the VB. When the VB drops drastically, the VREG also drops drastically, and a minimum voltage VREG2 of the VREG reaches 0V. When a VREG1 shown by the broken line is set to be a voltage which enables the load circuit 70 to operate normally, it is difficult for the load circuit 70 to operate normally at a point at which VREG2<VREG1. The load circuit 70 has a logic circuit incorporated therein and, for example, a latch circuit configured of the logic circuit cannot maintain a normal state, thus causing malfunction such as latch release.
FIG. 10 is a diagram showing VB dependence of the VREG. This shows VB dependence when the regulator circuit 500 starts operating and stops operating.
The regulator circuit 500 starts operating, and when the VB rises gradually from 0V, the VREG rises following the VB. Because of this, the VB and VREG rise in a relationship of VREG=VB. VREG=VREG0 at a point at which the VB reaches the VREG0, and the VREG is the VREG0 and a constant voltage in a condition in which VB>VREG0. Normally, the regulator circuit 500 operates at the VREG0. Herein, for example, the circle indicates an operating point.
Meanwhile, when the VB drops to 0V from a voltage higher than the VREG0 in a stop and transitional state of the regulator circuit 500, VREG=VREG0 when VB≧VREG0, while VREG=VB in the range of VREG0>VB=0V, and the VREG drops to 0V following the VB.
FIG. 11 is a diagram showing temperature dependence of the VREG. The temperature dependence of the VREG is such that the VREG has no temperature dependence and is flat when using a reference voltage with no temperature dependence, such as of a band gap reference circuit, as previously described. Because of this, the VREG at the operating point coincides with the VREG0, and the VREG is of a constant value without changing with a rise and drop in temperature.
Also, it is disclosed in JP-A-59-96828 (FIG. 2) that, in a parallel redundant system direct current power supply device including a backflow prevention diode on the output side, by adopting a configuration wherein a dummy resistor is used only when necessary, it is possible to reliably carry out the selection of a defective device, and thus possible to contribute to a loss reduction.
Also, the following is disclosed in JP-A-2004-129413 (FIG. 1). A charge pump circuit includes a voltage source, a boosting capacitor, a holding capacitor, and a diode provided so as to prevent a backflow of a discharge current of a capacitor charged by the voltage source, and reduce the output voltage of the charge pump circuit by the amount of forward voltage. The circuit outputs a voltage value greater than that of the output voltage of the voltage source by utilizing the action of charging the capacitors. The circuit also includes a correcting diode provided so as to increase the output voltage of the voltage source by the amount of forward voltage. This configuration prevents the output voltage of the charge pump circuit from being affected by the forward voltage of the diode.
It is disclosed in JP-A-2010-288444 (FIG. 1) to provide a gate drive device, which drives the gate of an active element with high input capacitance, such as an IGBT or MOSFET, including a semiconductor integrated circuit 4 having an internal power supply circuit which forms an internal power source based on an external power source supplied from an external power supply such as a battery. The semiconductor integrated circuit incorporates a voltage drop suppression circuit, and a drop of the internal power supply voltage of the internal power supply circuit to lower than a minimum operating voltage, and a sharp drop of voltage output to the gate, are suppressed by the voltage drop suppression circuit when an input external power supply voltage drops momentarily to lower than a minimum operating voltage. It is disclosed a gate drive device which can thereby suppress a fluctuation in the internal power supply voltage and output voltage while reducing the number of parts by omitting a bypass capacitor connected in parallel to the semiconductor integrated circuit. It is described that a ZD/R parallel circuit wherein a zener diode ZD and resistor R are connected in parallel to the internal power supply circuit is provided in the gate drive circuit. A description is given, in FIGS. 12 to 15, of a case in which the ZD/R parallel circuit is provided in a regulator circuit which lowers the external power supply voltage.
However, with the regulator circuit 500 of FIG. 8, when there is a momentary voltage interruption or momentary voltage drop, the VREG drops to 0V or drops drastically, as shown in FIGS. 9A and 9B. When the VREG drops drastically, the power supply voltage supplied to the load circuit 70 drops drastically, and the minimum value VREG2 of the VREG falls below the minimum voltage (=VREG1) which enables the load circuit 70 to operate normally, thus preventing the load circuit 70 from maintaining the normal operation. For example, the latch circuit malfunctions such as by the latch being released, as previously described. A description will be given of a heretofore known regulator circuit 600 which, in order to prevent this problem, adopts measures to be able to supply a voltage which enables the load circuit 70 to operate normally even when there is a momentary voltage interruption or momentary voltage drop.
FIG. 12 is a main portion circuit diagram of the heretofore known regulator circuit 600 adopting the measures. A ZD/R parallel circuit 60 which is a reverse current limiter circuit wherein a zener diode 61 and resistor 64 are connected in parallel is connected on the output terminal 69 side (downstream side) of the regulator circuit 500 of FIG. 8. The ZD/R parallel circuit 60 is a circuit which, when VB<VREG0, blocks a current Ib flowing from unshown capacitors of the load circuit 70 to the VB terminal via an unshown body diode (parasitic diode) of the MOSFET 56. The zener diode 61 prevents a backflow, but as the resistor 64 causes a reverse current to flow while suppressing it, it is not possible to completely interrupt the reverse current (current Ib).
Also, the resistor 64 is necessary for supplying voltage to the load circuit 70 until a threshold voltage (of on the order of 0.6V) of the zener diode 61 is reached when the VB rises from 0V, as will be described hereafter. Next, a description will be given of an advantageous effect obtained by providing the ZD/R parallel circuit 60. The threshold voltage (=0.6V) of the zener diode 61 is a voltage when a forward voltage rises and a voltage affected by the diffusion potential of a pn junction.
FIGS. 13A and 13B are diagrams of a behavior of the VB when momentarily interrupted in the regulator circuit 600 of FIG. 12, wherein FIG. 13A is a waveform diagram of the VB, while FIG. 13B is a waveform diagram of the VREG. When the external power supply voltage VB is applied to the external power supply voltage terminal (VB terminal), the operational amplifier 51 operates, thereby resulting in that the potential of the negative terminal 53 of the operational amplifier 51, reflecting the voltage of the positive terminal 52, becomes equal to the voltage (VERF) of the positive terminal 52, and the voltage of the second connection point 68 reaches the reference voltage VREF of the operational amplifier 51. By regulating the gate voltage of the MOSFET 56 into which is input an output voltage output from the output terminal 54 of the operational amplifier 51, a current I0 flowing through the second resistor 66 is regulated so that the reference voltage VREF is generated in the second resistor 66. The voltage of the first connection point 67, being ((the resistance value of the first resistor 65+the resistance value of the second resistor 66)/the resistance value of the second resistor 66)×VREF, reaches a set voltage VREG0. Then, VREG=VREG0−Vp, and the VREG is a constant voltage (VREG0−Vp) in the region of VB≧VREG0. The Vp is a voltage drop Vp occurring in the ZD/R parallel circuit 60.
Meanwhile, when the VB is momentarily interrupted, VB<VREG0, and VB=0V in an extreme case. At this time, electric charge within the load circuit 70 is discharged, and a reverse current tends to flow toward the VB terminal via the ZD/R parallel circuit 60 which is a backflow limiter circuit, but is blocked by the zener diode 61, meaning that the reverse current flows via the resistor 64. When the VB voltage<0, the reverse current flows from the GND into the resistor 64 via the body diodes of the series of currents. Consequently, when VB=0V, VREG=VREG2 rather than VREG=0. The VREG2 depends on the current flowing through the resistor 64.
By setting the VREG2 to be equal to or higher than a voltage VREG1) at which the resistor 64 is optimized to enable the load circuit 70 to operate normally, the load circuit 70 can maintain the operation normally even when there is a momentary voltage interruption or momentary voltage drop.
FIG. 14 is a diagram showing VB dependence of the VREG. This shows VB dependence when the regulator circuit 600 starts operating and stops operating.
VREG=VREG0−Vp when VB≧VREG0. Also, VREG=VB−Vp when VB<VREG0. The drop rate of the VREG decreases when the VB is between the threshold voltage (0.6V) of the zener diode 61 and 0V. This is because a voltage (R×Ir1) generated in the resistor 64 is dominant when the Vp is between these voltages. The VREG is supplied to the load circuit 70. The circle in FIG. 14 is an operating point.
FIG. 15 shows temperature dependence of the VREG. Even when the reference voltage VREF has no temperature dependence, the temperature dependence of the voltage drop Vp generated in the ZD/R parallel circuit 60 is reflected in the temperature dependence of the VREG. The temperature dependence of the VREG becomes positive, and the Vp decreases when the temperature rises, while the Vp increases when the temperature drops.
That is, in the regulator circuit 600 shown in FIG. 12, the VREG is a voltage always lower than the VREG0 by the amount of the Vp in the region of VB≧VREG0. Furthermore, as the VREG, reflecting the temperature dependence of the Vp, has the positive temperature dependence, there is a problem that the VREG is not suitable to be used as a power source when it is desired to eliminate temperature dependence in the output characteristics of the load circuit.
Also, in JP-A-59-96828 (FIG. 2) and JP-A-2004-129413 (FIG. 1), a regulator output is stabilized toward a drop in the external power supply voltage to prevent malfunction of the load circuit, thus enabling a circuit operation even at the low external power supply voltage. Furthermore, no description is given of a regulator circuit wherein the VREG has no temperature dependence so that it is possible to supply a voltage which enables the load circuit to operate normally.

Regulator circuit and integrated circuit device forming the regulator circuit


A computer implemented method is for generating a media playlist including a plurality of tracks to be played on a listener's mobile or stationary client device with Internet radio capabilities, the client device intended to be connected to the Internet. The method comprises: obtaining, as a listener's input into the listener's client device, a playlist definition; selecting, from a plurality of tracks, tracks meeting the playlist definition to form the playlist, wherein the playlist is formed by playlist entries that include track identifications referring to selected ones of the plurality of tracks; tracks present in a remote master media inventory, tracks present in an Internet-based cloud memory environment, and tracks present in a local media content inventory of the listener's client device form the plurality of tracks; selecting tracks that meet the playlist definition includes comparing the playlist definition with entries for tracks in a metadata encyclopedia which includes metadata derived from a master metadata encyclopedia referring to the tracks present in the remote master media inventory and the tracks present in the cloud memory environment, and the local media content inventory kept in the local listener's client device; the metadata encyclopedia is kept locally in the client device; and each entry in the local metadata encyclopedia refers to a respective track and includes at least one track descriptor and at least one similarity data descriptor; and providing the playlist to the listener's client device for obtaining the tracks indicated on the playlist for playing the tracks in the playlist in an order defined in the playlist.

Internet radio is an audio service to distribute audio content via the Internet to individual consumers. Today, music is the most popular type of audio content that is distributed. However, news, weather information, audio books, spoken commentaries, e-learning content, or the like are also offered on the Internet to an audience or a community of listeners. This is sometimes referred to as webcasting since it is not transmitted broadly and directly to its listeners through wireless means only.
Similar to traditional radio broadcasting, Internet radio involves streaming media, which is presenting listeners with a continuous stream of audio that cannot be paused or replayed by a listener. In this respect, it is distinct from on-demand file serving. Internet radio is also distinct from podcasting individual content, which involves downloading rather than streaming. Many Internet radio services are associated with a corresponding traditional (terrestrial) radio station or radio network. Internet-only radio stations are independent of such associations.
While Internet radio services are usually accessible from anywhere in the world, some stations and networks restrict listening to within the country. Internet radio services offer news, sports, talk, and various genres of music, such as Blues, Classical, Country, Easy Listening, Electronic, Folk, Jazz, Latin, Metal, Pop, R&B and Urban, Rap, Reggae, Rock, or others, in a similar manner as they are available on traditional radio stations.
Streaming technology is used to distribute audio content that is encoded. Streaming audio coding formats include MP3, Ogg Vorbis, Windows Media Audio, RealAudio, or others. Audio data is continuously transmitted serially (streamed) over the local network or Internet in TCP or UDP packets, then reassembled at the receiver and presented to the listener. Most stations stream their content at data rates between 64 kbit/second and 128 kbit/second, providing near CD quality audio.
Currently known Internet radio stations such as Pandora, geographically restricted to the U.S., rely solely on an analysis of music by musician-analysts that have been listening to music song by song in order to analyze and collect musical details on every track such as melody, harmony, instrumentation, rhythm, vocals, lyrics etc. Based on, e.g., a name of a song, artist or genre entered by a user, the database is scanned to include tracks with musical similarities in a playlist. The tracks of that playlist will then be streamed to the listener's Internet device (desktop, laptop, or tablet computer, smartphone, e-book with Internet access, or the like).
Growing media libraries are more and more difficult to effectively manage. Music playlists are one way to effectively manage and filter certain songs by selecting groupings of songs for ordered playback. While handcrafting a playlist typically involves the tedious process of searching through a list of media to find appropriate songs and selecting the desired songs, music playlists can also be automatically generated based on common music track attributes, such as genre, artist, album, and the like. These automatically generated playlists, while simple and fast to create, usually result in playlists with low acceptance by listeners. Further, such automatic methods assume that all relevant track attributes are available and accurate for each piece of media. One way of generating automatic playlists involves a user to specify search criteria, adds songs matching the search criteria to the playlist, and automatically updates the playlist as songs meet the criteria. However, even these playlists are limited by a user's musical familiarity, library, and skill in crafting an effective playlist.
A main drawback of conventional media playlist generation is determining which media items are similar to one another by one or more aspects. When handcrafting a playlist the user is responsible for drawing similarities between several different media items. Media similarity data and, more specifically, media playlists based on media similarity data are known in the art. Systems using similarity data for this purpose identify characteristics within each track and identify those tracks as being similar. Automated playlist generators rely on criteria such as melody, harmony, instrumentation, rhythm, vocals, lyrics etc. to build playlists, but these criteria are often too broad. Media by the same artist or even of the same type or genre is often not similar enough to generate a desirable playlist, i.e., where the listener's preferences are adequately taken into account. Some playlists try to solve some of these problems based on more detailed characteristics of the media, but they do not account for human preferences that are not easily definable.
As media libraries grow and digital media players are available with ever increasing capacities, these problems with playlists are likely to be exacerbated. Accordingly, what is needed in the art is an improved method of generating similarity data between media files and using such data for creating and managing playlists. However, in the rapidly growing number of Internet radio stations, currently known solutions are found to be inadequate to generate sufficiently attractive playlists of content. Therefore, the reach of each Internet radio station can be quite limited in the future due to its lack of focus on its listener community.

Method and system for preparing a playlist for an internet content provider

Panasonic Automotive Systems Company of America, Division of Panasonic Corporation of North America


Disclosed is an electric conductive gasket including: an electric conductive sheet having a natural pulp base, a soft aluminum foil adhered to a surface of the natural pulp base with an adhesive being interposed therebetween, and a hot melt layer formed on the other surface of the natural pulp base; and a nonconductive elastic member overlapped to be continuously encompassed by the electric conductive sheet, to be adhered by the hot melt layer.

As an electronic communication is developed and an information society is built, modern home appliance, industrial electronic device and information communication equipment are required to have fast processing and low consumption power. According to the above requirements, equipments themselves are miniaturized, and a circuit is integrated to allow many devices to be installed in a small space. Accordingly, the devices are gradually placed in an environment where they tend to be influenced by an electronic wave noise and heat. Various counterplans are set to solve the above problem.
Equipment has a main part such as a connection part of the equipment, a cable, a transparent display plate or a connector connection part or the like where the leakage and the infiltration of an electronic wave are generated. In order to shield the electronic wave of the cable, the cable is shielded or grounded itself and a wire of the cable, that is, a core is used as a twisted core. Further, in order to shield the electronic wave from the transparent display plate, the transparent display plate is manufactured using a transparent insulating material such as acryl, and a metal fabric mesh or a conductive mesh is disposed within the transparent display plate, or a transparent conductive material is vacuum-deposited onto one side surface of the transparent display plate.
Such parts can shield the electronic wave to some degrees, but it is not easy that the connection part of the equipment satisfactorily shields the electronic wave.
The connection part shields the electronic wave to prevent an electronic wave, which is generated at the external of the equipment, from being infiltrated into the equipment via the atmosphere or prevent an electronic wave, which is generated at the internal of the equipment, from being leaked out from the equipment. In order to maximize the shielding of the connection part against the electronic wave, it is optional to design the connection part without seam, but it is impossible that the connection part does not have the seam. Accordingly, the connection part necessarily accompanies the infiltration or the leakage of the electronic wave. An electronic conductive gasket is used to prevent the infiltration or the leakage of the electronic wave. The gasket with a low electric resistance has an excellent electronic wave shielding effect and an excellent grounding effect at a high frequency.
As the electric conductive gasket, there are a finger gasket using beryllium or copper, an electric conductive silicon gasket manufactured by mixing and curing a metal powder with nonconductive silicon, and a knitting gasket having an electric conductive wire knitted on nonconductive urethane or silicon.
However, a most popularized gasket is an electric conductive fabric gasket having a nonconductive urethane sponge encompassed using an electric conductive fabric. A method of manufacturing the electric conductive fabric gasket is described as follows. Nylon or polyester fabric is nonelectrolytic-plated using nickel, copper, silver or aurum to manufacture the electric conductive fabric, and then a nonconductive polymer hot melt is coated on one side surface of the electric conductive fabric. After that, if the result is heated while encompassing a urethane sponge, a hot melt is molten to be in contact with the urethane sponge.
The electric conductive fabric gasket has a drawback in that the nickel, copper, silver or aurum non-electrolytically plated on the nonconductive fabric are expensive, thereby increasing a manufacture cost.
In order to solve the above drawback, a low-priced aluminum can be used for nonelectrolytic-plating. However, aluminum cannot be nonelectrolytically plated since it concurrently has properties of a positive ion and a negative ion. That is, since nickel, copper, silver and aurum are metals with a property of the positive ion, they can be nonelectrolytically plated, but aluminum cannot be nonelectrolytically plated since it is a metal having both properties.
Further, the electric conductive fabric gasket has a drawback in that since a harmful chemical component is generated as a pollution material when the fabric is nonelectrolytic-plated, it is not environment-friendly.
Furthermore, the electric conductive fabric gasket has a drawback in that since cloths are treated in a manufacture process, pollution such as dust is generated to deteriorate a work environment.
Additionally, the electric conductive fabric gasket has a drawback in that when nickel is used as a plating metal, a skin trouble such as allergy is generated, and when copper is used as the plating metal, the copper is discolored.
Further, the electric conductive fabric gasket has a drawback in that since the electric conductive fabric gasket is formed using the fabric, the fabric gets loose at a cut section surface, and since the plating of nickel or copper is performed at a limited thickness to have flexibility, the electric resistance is high and the thermal conductivity is poor.
An object of the present invention is to provide an electric conductive gasket with a low manufacture cost, an excellent electronic-wave shielding characteristic and grounding effect, and an environment-friendship.
Other objects and features of the invention will be more apparently understood in the following described embodiment.