A component built-in module includes an electric insulation layer, first wiring patterns in a plurality of layers that are laminated with the electric insulation layer being interposed therebetween, at least one first inner via electrically connecting the first wiring patterns in different layers with each other, and at least one electronic component that is embedded in the electric insulation layer and is mounted on any one of the first wiring patterns in the plurality of layers, wherein at least one of the first inner vias is present in a range that overlaps a range in which the electronic component is present in a lamination direction in which the first wiring patterns are laminated, and has a height in the lamination direction that is smaller than a height of the electronic component. Since the first inner via has a small height, the via diameter can be decreased. Therefore, it is possible to provide a component built-in module that has high reliability and is suitable for high-density component mounting.

1. Field of the Invention
The present invention relates to a component built-in module in which an electronic component such as a semiconductor and/or a circuit component is provided inside an electric insulation layer, and to a method for manufacturing the same.
2. Related Background Art
Recently, following the tendency of electronic devices toward high performance and compact size, it is increasingly demanded to achieve high density and improved function of circuit components. It also is demanded to provide a circuit-component-mounted module suitable for high density and improved performance. To mount circuit components at a higher density, wiring patterns are complicated increasingly, and hence, there is a tendency of wiring boards toward multi-lamination.
In the case of conventional glass-epoxy substrates, multi-lamination is achieved with a through hole structure that is obtained by drilling. This structure has high reliability, but wiring patterns provided thereon are limited since wiring patterns in different layers are connected using through holes. Furthermore, a semiconductor or a circuit component cannot be mounted at an area on a surface of the wiring board where the through hole is provided, and therefore, it is not suitable for high-density component-mounting.
Therefore, as a method for achieving high densification of circuitry, a multi-layer wiring board utilizing electric connection by inner vias is used also. The inner via connection allows the wiring patterns between large scale integrated circuits (LSIs) and components to be connected over the shortest distances, and also provides only necessary connections between wiring pattern layers, thereby facilitating the circuit component mounting. Furthermore, by incorporating circuit components in a wiring board, the component mounting efficiency is improved further.
However, the incorporation of circuit components and the connection of the same through inner vias may have a problem in reliability. The reliability of the inner via connection is influenced significantly by the ratio of a height of an inner via to a diameter thereof (i.e., aspect ratio=height/diameter). In the case where a circuit component is incorporated in a wiring board, an electric insulation layer having a height greater than a height of the circuit component is required, thereby necessarily causing an inner via to have a greater height. Therefore, to improve the connection reliability, it is necessary to increase the diameter of an inner via. However, an increase in the diameter leads to a decrease in the mounting density.
Therefore, it is an object of the present invention to provide a component built-in module that has high reliability and is suitable for high-density component-mounting, and a method for manufacturing the same.
A first component built-in module of the present invention includes: an electric insulation layer; first wiring patterns in a plurality of layers that are laminated with the electric insulation layer being interposed therebetween; at least one first inner via electrically connecting the first wiring patterns in different layers with each other; and at least one electronic component that is embedded in the electric insulation layer and is mounted on any one of the first wiring patterns in the plurality of layers. Herein, at least one of the first inner vias is present in a range that overlaps a range in which the electronic component is present in a lamination direction in which the first wiring patterns are laminated, and has a height in the lamination direction that is smaller than a height of the electronic component.
Here, in the present invention, xe2x80x9cheight of an electronic componentxe2x80x9d means a distance from an upper surface of a wiring pattern on which the electronic component is mounted to an upper surface of the electronic component. More preferably, it means a thickness of the electronic component itself. Furthermore, the term xe2x80x9coverlapxe2x80x9d herein means that the two concerned ranges overlap each other at least partly, and the ranges do not necessarily coincide with each other completely.
This configuration makes it possible to suppress a height of the first inner via provided substantially opposite to the electronic component in a direction perpendicular to the lamination direction of the first wiring patterns. As a result, even with a decreased diameter of the via, the degradation of reliability resulting from an increase in the aspect ratio is prevented. Therefore, it is possible to provide a component built-in module that has high reliability and is suitable for high-density component-mounting.
The first component built-in module preferably further includes a wiring board including second wiring patterns in at least two layers, and a through hole and/or a second inner via that electrically connects the second wiring patterns in different layers with each other. Here, the wiring board is embedded inside the electric insulation layer, and any one of the first wiring patterns in the plurality of layers and the second wiring pattern are connected electrically through an inner via.
This configuration makes it possible to provide a component built-in module suitable for high-density component-mounting, taking advantage of the high reliability of the wiring board. Further, since a generally used wiring board can be used, this leads to a decrease in production cost.
Next, a second component built-in module of the present invention includes: an electric insulation layer; first wiring patterns in a plurality of layers that are laminated with the electric insulation layer being interposed therebetween; at least one first inner via electrically connecting the first wiring patterns in different layers with each other; a wiring board including second wiring patterns in at least two layers, and a through hole and/or a second inner via that electrically connects the second wiring patterns in different layers with each other; and at least one electronic component that is embedded in the electric insulation layer and is mounted on any one of the second wiring patterns. Here, at least one of the first inner vias is present in a range that overlaps a range in which the electronic component is present in a lamination direction in which the first wiring patterns are laminated, and has a height in the lamination direction that is smaller than a height of the electronic component.
In a component built-in module that utilizes an existing element having an electronic component mounted on a wiring board, and has an electric insulation layer laminated on the electronic component-mounted surface, it is possible to decrease a height of the first inner via provided substantially opposite to the electronic component in a direction perpendicular to the lamination direction of the first wiring pattern. As a result, even with a decreased diameter of the via, the degradation of reliability resulting from an increase in the aspect ratio is prevented. Therefore, it is possible to provide a component built-in module that has high reliability and is suitable for high-density component-mounting.
Each of the first and second component built-in modules preferably further includes at least one electronic component that is mounted on any one of the first wiring patterns in the plurality of layers, and is not embedded in the electric insulation layer. This provides a component built-in module that has high reliability and is suitable for mounting components at a further higher density.
Furthermore, in each of the first and second component built-in modules, the electric insulation layer preferably is made of a mixture of a filler and an insulating resin. By selecting a type of a filler, it is possible to control a heat conductivity, a coefficient of linear expansion, a dielectric constant, etc. of the electric insulation layer.
In this case, the filler preferably contains at least one selected from alumina, magnesia, boron nitride, aluminum nitride, silicon nitride, tetrafluoroethylene, and silica. This makes it possible to provide an electric insulation layer that is excellent in heat dissipation. In the case where alumina is used as a filler, an advantage of low cost is achieved. The use of magnesia as a filler provides an increase in the coefficient of linear expansion of the electric insulation layer. In the case where boron nitride, aluminum nitride, or silicon nitride is used as a filler, it is possible to decrease the coefficient of linear expansion. The use of tetrafluoroethylene or silica as a filler provides an electric insulation layer having a low dielectric constant.
Furthermore, the insulating resin preferably contains at least one selected from an epoxy resin, a phenol resin, a fluorocarbon resin, a cyanate resin, a polytetrafluoroethylene (PTFE) resin, a poly(phenylene oxide)(PPO) resin, and a polyphenylether (PPE) resin. By selecting an appropriate insulating resin material, it is possible to improve a heat resistance, an electric insulation, and high-frequency characteristics.
In each of the first and second component built-in modules, the first wiring patterns preferably are made of at least one selected from a metal foil, a lead frame, and a conductive resin composition. This allows a fine wiring pattern having a low electric resistance to be formed.
In each of the first and second component built-in modules, the electronic component preferably is a semiconductor bare chip. This allows semiconductor elements to be mounted at a higher density, and since the semiconductor is thinner, this allows the electric insulation layer to have a smaller thickness.
In this case, the semiconductor bare chip preferably is mounted by flip chip bonding. This allows the semiconductor elements to be mounted at a high density.
Furthermore, in each of the first and second component built-in modules, the first inner via preferably is made of a via paste containing a conductive powder and a thermosetting resin. This allows the electric insulation layer and the first inner via to be cured simultaneously, thereby decreasing the number of manufacturing steps.
Furthermore, the wiring board preferably is composed of a ceramic substrate, a glass-epoxy substrate, or a multi-layer substrate having an inner via connection. This configuration allows a component built-in module to be formed using a generally used wiring board, thereby reducing the production cost.
Furthermore, in each of the first and second component built-in modules, the electric insulation layer in contact with the electronic component and the electric insulation layer in contact with the first inner via preferably are provided integrally. The phrase xe2x80x9cprovided integrallyxe2x80x9d herein indicates that the two electric insulation layers have a common composition and are continuous seamlessly. This causes these electric insulation layers to be provided continuously without a boundary, thereby improving the reliability.
Furthermore, in each of the first and second component built-in modules, a plurality of the electronic components preferably are disposed opposite in the lamination direction in which the first wiring patterns are laminated. This allows electric components to be mounted at a higher density.
Furthermore, in each of the first and second component built-in modules, the first wiring patterns preferably include a land pattern electrically connected with the first inner via. This increases an area capable of incorporating electronic components, thereby allowing the same to be mounted at a high density.
A first method for manufacturing a component built-in module according to the present invention includes the steps of: forming a first inner via in an electric insulation layer; mounting an electronic component on a first wiring pattern; and laminating the electric insulation layer and another wiring pattern different from said first wiring pattern in this order on a surface of the first wiring pattern on which the electronic component is mounted so that said first wiring pattern and the another wiring pattern, which are provided opposite each other with the electric insulation layer being interposed therebetween, are electrically connected through the first inner via. Here, the electric insulation layer before being laminated has a thickness smaller than a height of the electronic component in a direction of the lamination.
This allows the first component built-in module of the present invention to be manufactured readily.
In the first method, it is preferable that the another wiring pattern is provided on a surface of another electric insulation layer different from said electric insulation layer, and that the another wiring pattern is connected with an inner via formed in the another electric insulation layer. This facilitates the handling of the another wiring pattern, and allows wiring patterns to be laminated in multiple layers through a decreased number of manufacturing steps.
Furthermore, in the first method the another wiring pattern preferably is carried on a carrier, and the method further includes the step of removing the carrier that is carried out after the laminating step. This facilitates the handling of the another wiring pattern.
Furthermore, in the first method, the another wiring pattern preferably is a second wiring pattern exposed on a surface of a wiring board that includes second wiring patterns in at least two layers, including said second wiring pattern, and a through hole and/or a second inner via that electrically connects the second wiring patterns in different layers with each other. This allows a generally used wiring board having high reliability to be incorporated along with the electronic components.
Next, a second method for manufacturing a component built-in module according to the present invention includes the steps of: forming a first inner via in an electric insulation layer; preparing a wiring board including second wiring patterns in at least two layers, and a through hole and/or a second inner via that electrically connects the second wiring patterns in different layers with each other; mounting an electronic component on the second wiring pattern that is exposed on a surface of the wiring board; and laminating the electric insulation layer and a first wiring pattern in this order on the second wiring pattern on which the electronic component is mounted, so that the second wiring pattern and the first wiring pattern, which are provided opposite with the electric insulation layer being interposed therebetween, are electrically connected through the first inner via. Here, the electric insulation layer before being laminated has a thickness smaller than a height of the electronic component in a direction of the lamination.
This allows the second component built-in module of the present invention to be manufactured readily.
In the second method, it is preferable that the first wiring pattern is provided on a surface of another electric insulation layer different from said electric insulation layer, and that the first wiring pattern is connected with an inner via formed in the another electric insulation layer. This facilitates the handling of the first wiring pattern, and allows wiring patterns to be laminated in multiple layers through a decreased number of manufacturing steps.
Furthermore, in the second method, the first wiring pattern preferably is carried on a carrier, and the method further includes the step of removing the carrier that is carried out after the laminating step. This facilitates the handling of the first wiring pattern.
Furthermore, in each of the first and second methods, the electric insulation layer before being laminated has a hole for accepting the electronic component. This suppresses the displacement of the first inner via when the electronic component is embedded.
In each of the first and second methods, at least a part of the electronic component preferably is embedded in the electric insulation layer upon the electric connection. This allows a component built-in module of the present invention to be manufactured readily.
Furthermore, in each of the first and second methods, the electric insulation layer is cured upon making the electric connection. This allows a component built-in module of the present invention to be manufactured through a decreased number of manufacturing steps.
Furthermore, in each of the first and second methods, it is preferable that at least a part of the electronic component is embedded in the electric insulation layer and the electric insulation layer is cured upon the electric connection. This allows a component built-in module of the present invention to be manufactured through a decreased number of manufacturing steps.
Furthermore, in each of the first and second methods, the electric insulation layer before being laminated preferably is in a non-cured state. This allows an electric insulation layer in contact with the electronic component and an electric insulation layer in contact with the first inner via to be provided integrally, thereby producing a component built-in module of the present invention with high reliability.
Furthermore, in each of the first and second methods, it is preferable that the another electric insulation layer has a wiring pattern on the other surface thereof, and the wiring pattern on the other surface is connected with the inner via of the another electric insulation layer. This causes the inner via formed in the another electric insulation layer to be not exposed, thereby facilitating the handling of the another electric insulation layer, and improving the connection reliability of the inner via.

Component built-in module and method of manufacturing the same

Matsushita Electric Industrial Co., Ltd.


A system and method of conducting a continuous performance analysis for a system includes collecting transient performance data for a first parameter of the system and a second parameter of the system. Transfer functions are applied to the transient performance data for at least one of the first and second parameters to thereby generate phase compensated performance data representative of a steady state relationship between the first and second parameter. For each phase compensated performance datum, an estimate of the first parameter is calculated at a predetermined value of the second parameter using the phase compensated performance datum and a previously stored performance characteristic curve representative of the steady state relationship between the first and second parameters in a deterioration model extrapolation method. A very efficient binning method is used for storing phase compensated performance data and converting them into steady state performance characteristic curves of any non-linear shape.

Many systems are subject to some type of performance assessment upon system start-up and initialization to determine the capability of the system to perform various functions without exceeding a limit. For example, gas turbine engines used in aerospace applications, such as helicopters, are often subject to a daily pre-flight power assurance test before beginning a mission. The purpose of the daily power assurance test is to verify the helicopter engine(s) can meet the minimum power requirements needed for its mission without exceeding the power turbine inlet temperature limit.
Typically, the daily helicopter engine power assurance test is conducted while the helicopter is hovered at a relatively low altitude, and after steady-state engine conditions have been substantially achieved. As may be appreciated, in the context of military helicopter operations, this procedure can be potentially dangerous if it is conducted in a hostile military environment, such that the helicopter can be shot down by enemy fire. This procedure may also consume significant amounts of flight time and engine life, and may thus be relatively costly. Moreover, the daily power assurance test result is only provided at the beginning of the first flight of the day. Thus, if engine performance deteriorates during a mission the pilot may not be aware until the next day, when a new daily power assurance test is conducted.
Hence, there is a need for a performance analysis system and method that can provide accurate system performance results continuously during system operation, without having to rely on potentially costly, non-useful system operation and/or placing the system in undesirable tactical situations and/or requiring that steady-state system conditions be established. The present invention addresses at least these needs.

Continuous performance analysis system and method


A memory device is provided which includes a substrate, a common P-well isolated from the substrate, a plurality of sectors, and a common sector selection transistor configured to select one of the sectors for erasure. Each of the sectors share the same common sector select transistor, and the common P-well. The selected sector is configured to be erased by applying appropriate voltages to the selected sector.

Flash memory is a type of electronic memory media that can hold its data in the absence of operating power. Flash memory can be programmed, erased, and reprogrammed during its useful life (which may be up to one million write cycles for typical flash memory devices). Flash memory is becoming increasingly popular as a reliable, compact, and inexpensive nonvolatile memory in a number of consumer, commercial, and other applications. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory cell, such as a flash memory unit.
One conventional flash memory technology is based upon a memory cell that utilizes a charge trapping dielectric cell that is capable of storing two bits of data. One example of this type of non-volatile memory device is known as a dual-bit Flash electrically erasable and programmable read-only memory (EEPROM), which is available under the trademark MIRRORBIT™ from Spansion, Inc., Sunnyvale, Calif. Such dual-bit memory cells utilize a single silicon nitride layer having two separate charge storage regions to store charge within the silicon nitride layer. In such an arrangement, one bit can be stored using a first charge storing region on one side of the silicon nitride layer, while a second bit can be stored using a second charge storing region on the other side of the same silicon nitride layer. For example, a left bit and right bit can be stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell, respectively. In comparison to a conventional EEPROM cell, a dual-bit memory cell can store twice as much information in a memory array of equal size.
FIG. 1 is a cross-sectional view of a conventional dual-bit memory cell 50. The memory cell 50 has a dual-bit (bit1, bit2) architecture that allows twice as much storage capacity as a conventional EEPROM memory device.
The conventional memory cell 50 includes a substrate 54, a first insulator layer 62 disposed over the substrate 54, a nitride charge storage layer 64 disposed over the first insulator layer 62, a second insulator layer 66 disposed over the charge storage layer 64, and a polysilicon control gate 68 disposed over the second insulator layer 66. To produce an operable memory device, a first metal silicide contact (not shown) can be disposed on substrate 54, and the control gate 66 can be capped with a second metal silicide contact (not shown).
In one implementation, the substrate 54 is a P-type semiconductor substrate 54 having a first buried junction region 60 and a second buried junction region 61 formed within substrate 54 in self-alignment with the memory cell 50. First buried junction region 60 and second buried junction region 61 are each formed from an N+ semiconductor material. The first insulator layer 62, the charge storage layer 64, and the second insulator layer 66 can be implemented using an oxide-nitride-oxide (ONO) configuration in which a nitride charge storage layer 64 is sandwiched between two silicon dioxide insulator layers 62, 66. Alternatively, charge storage layer 64 may utilize buried polysilicon islands as a charge trapping layer. The charge storage layer 64 is capable of holding a charge.
Memory cell 50 can store two data bits: a left bit represented by the circle (bit 1); and a right bit represented by the circle (bit 2). In practice, memory cell 50 is generally symmetrical, thus first buried junction region 60 and second buried junction region 61 are interchangeable. In this regard, first buried junction region 60 may serve as the source region with respect to the right bit (bit 2), while second buried junction region 61 may serve as the drain region with respect to the right bit (bit 2). Conversely, second buried junction region 61 may serve as the source region with respect to the left bit (bit 1), while first buried junction region 60 may serve as the drain region with respect to the left bit (bit 1). A threshold voltage exists between the control gate 66 and the substrate 54 to prevent leakage during functioning of the device.
While a single dual-bit memory cell 50 is illustrated in FIG. 1, it will be appreciated that any suitable number of the dual-bit memory cells 50 could be used to form a memory array, as described below with reference to FIG. 2.
FIG. 2 is a simplified diagram of a plurality of dual-bit memory cells arranged in accordance with a conventional array architecture 200 (a practical array architecture can include thousands of dual-bit memory cells 50). Array architecture 200 includes a number of buried bit lines formed in a semiconductor substrate as mentioned above. FIG. 2 depicts three buried bit lines (BLs) 202, 204, and 206, each being capable of functioning as a drain or a source for memory cells in array architecture 200. Array architecture 200 also includes a number of word lines (WLs) correspond to the gate of the memory cells and are utilized to control the gate voltage of the memory cells. FIG. 2 depicts four WLs 208, 210, 212, and 214 that generally form a crisscross pattern with the bit lines. Although not shown in FIG. 2, charge storage layer, such as an ONO stack, resides between the BLs and the WLs. The dashed line circles in FIG. 2 represent two of the dual-bit memory cells in array architecture 200. Notably, BL 204 is shared by the dual-bit memory cells. Array architecture 200 is known as a virtual ground architecture because ground potential can be applied to any selected BL and there need not be any BLs with a fixed ground potential.
Control logic and circuitry (not shown) for array architecture 200 governs the selection of memory cells, the application of voltage to the WLs 208, 210, 212, 214, and the application of voltage to the BLs 202, 204, 206 during conventional flash memory operations, such as: programming; reading; erasing; and soft programming. Voltage is delivered to the BLs 202, 204, 206 using BL contacts 230. FIG. 2 depicts three conductive metal lines 220, 222, and 224 and three BL contacts 230. For a given BL 202, 204, 206, a BL contact is used once every 16 WLs because the resistance of the BLs 202, 204, 206 is very high.
FIG. 3 shows an array 300 of dual-bit memory cells comprising a number of core array sectors 320-350. Each of the core array sectors 320-350 comprises a number of BLs and WLs which form the dual bit memory cells as described in FIG. 2. Each core array sector 320-350 can be erased by selecting that particular sector for erasure, and applying appropriate voltages to a common P-well (not shown) in the substrate, BLs and WLs in the selected sector. To select a particular core array sector 320-350 to be erased, each of the core array sectors 320-350 has its own corresponding sector select transistor 310A-310D.
FIG. 4 shows an array 400 of dual-bit memory cells and the biasing used during a hot hole erase operation to erase a selected sector in the array 400. The array 400 of dual-bit memory cells comprises a plurality of sectors. Each sector comprises a number of WLs 410, 420 and a number of BLs 430, 440. All of the sectors share a common P-well 405.
When a particular sector is selected to be erased via a hot hole erase operation, a sector select transistor for that sector can be used to pass the required BL voltage to that particular sector. The selected core array sector can then be erased by applying a negative bias voltage (−VG), for example minus nine volts, to each of the WLs 410 in the selected sector, applying a positive BL voltage (+VB), for example nine volts, to each of the BLs 430 in the selected sector, grounding each of the WLs 420 and BLs 440 in the unselected sectors 330-350 at zero volts, and grounding the common P-well 405 at zero volts.
In the hot hole erase operation of FIG. 4, individual sector select transistors 310A-310D are required for each core array sector 320-350 to prevent an erase disturbance. Since each sector 320-350 needs a dedicate sector select transistor, valuable die area is consumed. Moreover, the erase disturbance can occur to the unselected sector during a hot hole erase operation of the selected sector because the positive BL voltage (+VB) on the BLs can generate undesired hot holes and can erase of the unselected sectors. Applying a positive BL voltage (+VB) to the selected BLs 430 and grounding the unselected BLs 420 can be achieved by controlling the different sector select transistors 310A and 310B-D between the sectors 320-350 of FIG. 3.

Method and apparatus for sector erase operation in a flash memory array


Disclosed are methods and apparatus for analyzing the quality of overlay targets. In one embodiment, a method of extracting data from an overlay target is disclosed. Initially, image information or one or more intensity signals of the overlay target are provided. An overlay error is obtained from the overlay target by analyzing the image information or the intensity signal(s) of the overlay target. A systematic error metric is also obtained from the overlay target by analyzing the image information or the intensity signal(s) of the overlay target. For example, the systematic error may indicate an asymmetry metric for one or more portions of the overlay target. A noise metric is further obtained from the overlay target by applying a statistical model to the image information or the intensity signal(s) of the overlay target. Noise metric characterizes noise, such as a grainy background, associated with the overlay target. In other embodiments, an overlay and/or stepper analysis procedure is then performed based on the systematic error metric and/or the noise metric, as well as the overlay data.

The present invention relates generally to overlay measurement techniques, which are used in semiconductor manufacturing processes. More specifically, the present invention relates to analyzing overlay marks (also called overlay targets) used for measuring alignment error between different layers or different patterns on the same layer of a semiconductor wafer film stack.
In the process of manufacturing semiconductor integrated circuits, one of the critical metrology steps is overlay or misregistration measurement. The overlay measurement ideally quantifies the lateral displacement between two layers of the integrated circuit from their nominal, perfect alignment. The lateral displacement is called overlay error or misregistration (herein referred to as overlay). This metrology is typically performed by a specialized optical instrument, overlay metrology tool, on test structures located either in the so-called scribe lines on the wafer or within the area of the integrated circuit itself. These test structures are called overlay targets. The overlay metrology tool reports, as the result of each measurement, two numbers, representing the overlay in two orthogonal directions in the plane of the wafer, labeled x and y. The overlay is measured on several locations on a wafer, and on several wafers of each processing lot. The results are used primarily for two purposes. One purpose of the overlay measurements is to facilitate decisions as to whether to pass or fail a given wafer lot (known as lot dispositioning), based on the overlay values or their combinations. Another purpose is to facilitate calculating what part of these errors was due to the non-ideal alignment or other functioning of the lithography stepper or scanner, and feeding this information back to the stepper or scanner to effect corrections (known as process control). This correction is determined using a stepper analysis program, based on stepper models.
Unfortunately, the reported overlay results may not be reliable in certain situations. That is, the measured overlay measurements may be affected by other factors besides misalignment of the target. The overlay measurement may be affected by background noise associated with the measured target. In one example, background may cause an overlay error to be measured when the target is not misaligned. Systematic errors, such as asymmetry may also cause the measured overlay error to be inaccurate. In another example, a target which has significant asymmetries, combined with a significant true overlay error, may result in zero measured overlay error. Thus, the asymmetry error may go unnoticed and steps to correct process problems leading to such asymmetry may go uninitiated and adversely affect yield.
Accordingly, there is a need for improved techniques for analyzing the quality and reliability of overlay targets. There is especially a need for taking into account systematic and noise contributions as they affect the reliability of the overlay measurements.

Use of overlay diagnostics for enhanced automatic process control


A collapsible liner for a bulk container made of a flexible material and having seamless top and bottom walls is provided. The liners are formed from a tubular blank folded to form two gusset panels received inwardly of two overlying flat panels. The blank is severed to form triangular portions adjacent opposed ends of the blank and adjacent sides of adjacent triangular portions are connected together to form a pair of generally opposed and generally rectilinear side walls of the liner. The seamless top and bottom walls are stronger than those portions of the liner with seams and are less likely to rupture or leak.

Previously, many granular products and some liquids have been shipped and stored in large bulk bags which may contain as much as a ton or more of material. Some of these bulk bags are flexible and when empty can be folded to a generally flat condition. One such flexible bag is disclosed and claimed in U.S. Pat. No. 5,104,236.
These flexible bags have generally rectangular ends interconnected by generally rectangular side walls and, when filled, can be stacked one on top of another. For some applications the bags are made of a woven fabric and for other applications a plastic material. For some applications, and particularly for storing liquids or hazardous materials, a bag of a water impervious plastic material is received in and reinforced and protected by a bag of a woven fabric. Usually, these bags have a spout in one or both ends for filling and emptying the bags. Further, for some applications, it is desirable to have a bag of a water impervious plastic material encasing a bag of woven fabric to protect the contents of the inner bag and to contain the contents of the inner bag that leak through the inner bag.
Typically these bags are produced by severing a tubular blank to form triangular portions adjacent opposite ends of the blank. Adjacent sides of adjacent triangular portions are then connected together such as by stitching or heat sealing the edges together to form generally square and spaced apart top and bottom walls of the bag. The connections between adjacent triangular portions of the top and bottom walls of the bags are typically weaker than seamless portions of the bag and are hence subject to rupturing or tearing especially during moving or shipping of filled bags. Further, especially when liquids are being carried by the bulk bag, high stresses can result in the top and bottom of the bags, both when the bags are being lifted such as for loading onto a vehicle for shipping, and also during shipping due to the shifting of the liquid within the bag during shipping.
Thus, current bags have the weakest portion of the bag, where the triangular portions are connected together, in the top and bottom walls of the bag which can experience the highest stresses during use of the bag. Therefore, the bags are subject to rupturing adjacent their top and bottom walls which limits the load bearing capacity of the bags.


A bias generation circuit is between a power voltage node and ground voltage node at a far end from power voltage and ground voltage terminals. Reference voltage nodes are connected to an amplifier circuit block from the far end. The amplifier block is closer to the power supply source, and the bias generation circuit is distant therefrom. Even if the power supply voltage drops due to current constantly flowing in the amplification block and bias generation circuit, the bias generation circuit generates reference voltages at the reference voltage nodes based on the voltage-dropped power supply. Therefore, the voltage in the constant current source MOS transistor of the amplifier block becomes lowest at the amplifier circuit closest to the bias generation circuit. The response speeds of other amplifier circuits do not drop if the circuit is designed based on the amplifier closest to the bias generation circuit.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a circuit configuration that suppresses the influence of the process variation of wire resistance on characteristics of the semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor integrated circuits which can decrease the variation of bias currents among chips to reduce the difference of current consumption among the chips and the difference of device characteristics are known in the art. Japanese Patent Application Laid-Open (Kokai) No. 2000-310981 (paragraph 0089), for example, discloses that the same bias current is supplied to each chip from the outside in order to suppress the current consumption difference and characteristic difference among different chips. The bias current is used to decide a current to flow in amplifiers of each chip. A bias generation circuit, which determines the bias current, is installed outside the chip, so that this circuit supplies the same bias current to each chip.
Japanese Patent Application Laid-Open No. 2000-310981 discloses a technology for installing the bias generation circuit outside the chip, and not for decreasing the variation of bias currents among a plurality of amplifier circuits, and decreasing the difference of current consumption and difference of device characteristics by deciding appropriate positions of the amplifier circuits and the bias generation circuit on a same chip. This Japanese Patent Application Laid-Open No. 2000-310981 does not provide a useful technology for suppressing the influence of process variation of the wiring resistance on characteristics of the products, because chips become long, such as the case of a semiconductor integrated circuit device used for a liquid crystal TFT driver, and power supply and ground wires from the power supply and ground supply terminals to the internal circuits become long.


A vehicle communication system including a communication management unit (CMU) and a data gateway is provided. The CMU is at least in part configured to route first type messages using a first type message communication. The data gateway is configured to communicate second type messages to a remote location. The CMU is configured to route at least some of the first type messages to the data gateway. The data gateway is configured to communicate a pseudo acknowledgment for each message block of each first type message routed to the data gateway back to the CMU indicating the message block was received by a designated remote location. The data gateway is further configured to interface each received first type message into the second type message and communicate each second type message to the designated remote location using a second type of message communication.

Vehicles, such as but not limited to, aircraft may use more than one type of communication system when communicating with remote locations. An example communication system used in an aircraft is an aircraft communication addressing and reporting system (ACARS). ACARS is an aircraft to/from ground system communication system used to communicate relatively short messages between the aircraft and ground end systems via airband radio or satellite such as Very High Frequency (VHF), High Frequency (HF) and Satellite Communications (SATCOM). ACARS is reliable and secure and therefor used for critical messages (safety messages). Safety messages are high design assurance level information that would be used for such things as navigation, systems control, system health, etc. Although ACARS messages are reliable and secure, they are costly and not ideal for sending large messages or large quantities of non-safety messages. Protocol used with ACARS messages only sends one message block at a time where a message may include one to sixteen blocks. Because of this approach, the message is limited by having to wait for each message/message block to be acknowledged (from the peer on the ground for downlink or peer CMU on the aircraft for uplink) before it can send another. This problem of per message block acknowledgement is particularly impactful when using SATCOM (even high bandwidth SATCOM) as the latency on message transmission over geostationary satellites can be relatively high (for example, the latency may be 500 msec or more for the full round trip of the message/acknowledgement).
Other available communications systems used by aircraft may include Wi-Fi, cellular and/or broadband SATCOM that allow internet protocol (IP) broadband links. Communications through these systems, when available, provide higher-bandwidth and are cheaper. However communication signals used in these communication systems are only allowed to communicate low design assurance level information and are not approved to transmit ACARS safety messages.

Vehicle multi-communication message type communication system


A safety release device for a kite line has a first fastening member with an attachment point for a first line portion and a second fastening member with an attachment point for a second line portion. In a fastened position the second fastening member engages through an aperture of the first fastening member. A release member is movably positioned on the first fastening member and is movable between a secured position holding hold the release device in the fastened position and a released position in which a line attached to the release device pulls the second fastening member out of engagement through the aperture. A releasable locking member is provided on the release member for locking the release member in the secured position so as to prevent it being moved to the released position.

1. Field of the Invention
The invention relates to a safety release device for a kite, and in particular to a safety release device for releasably fastening together first and second portions of a kite line.
2. Description of the Prior Art
A user controls the power and direction of a kite by manipulating a control bar connected to the kite lines. In one configuration the control bar is arranged to slide long a center control line having a harness loop for attaching the kite to a harness hook worn by a user.
It is possible to loose control of the kite and be over powered. This can be particularly dangerous during launching when the user is on or near land, solid objects, spectators, and other kites. For this reason it is known to provide a safety release device in the central control line. If the user looses control of the kite or the kite becomes over powered the user lets go of the control bar and it is pulled along the center control line by the kite until it hits the release device. The release device which operates to break the center control line portions de-powering the kite.
However, when performing certain maneuvers the user must remove his or her hands from the control bar. A problem exists because this would result in the safety release device operating to de-power the kite.


An apparatus for transporting clothing comprising a wheeled suitcase and a detachable garment bag. The garment bag is adapted to wrap around outside panels of the suitcase and is held snuggly against the suitcase by a fastener system including connectively interlocking clips or the like. Auxiliary hook and loop strips ensure that the garment bag is securely held on the suitcase. The wheeled suitcase, in its generally upright position, includes an upper end and lower end. The upper end has an opening free of the wrapped garment bag affording ready access. Corners of the suitcase are rounded to facilitate gentle wrapping such that clothing within the garment bag is not subject to folding or wrinkling. The suitcase is slightly smaller than the size limited by airline regulations for carry-on luggage. Thus, when wrapped with the unique garment bag, the combined suitcase and garment bag will not exceed regulations.

This invention relates to luggage both of the wheeled variety and the foldable type adapted to transport relatively large clothing pieces such as suits and dresses with minimal wrinkling.
Luggage for transporting clothing typically takes the form of suitcases of the box or trunk style or the foldable variety known as garment carriers or garment bags. Accommodating the carrying of relatively large garment pieces such as suits, jackets, shirts, blouses, and dresses, while avoiding wrinkles, has been an ongoing problem for travelers everywhere. Traditional luggage, commonly referred to as suitcases cannot accommodate large garments such as suits or dresses without folding them to fit inside. Compression and relative friction brought on by folding and packing result in garment wrinkles and unsightly creases.
As a solution to stuffed suitcases, garment bags were introduced as a means of transporting large garments. Garment bags are widely used despite a number of problems encountered with their use. Usually the user must suffer the strain and awkwardness of reaching backward across a shoulder to grasp a hanger hook from which the unfolded garment bag is suspended. Alternatively, the garment bag may be folded for easier handling, but the clothing held therein will suffer. This is because garment bags along with their contents require doubling or folding to a size that, at most, is half their overall length. The objective is to make garment bags just large enough to accommodate suits and dresses, yet small enough to be carried reasonably conveniently, and to permit them to be brought aboard a commercial flight. Occasionally, airline flight personnel will permit hanging the garment bag during flight, but typically the bag must be folded and stuffed into an overhead compartment, where they often are subjected to crushing pressure from adjacent bags of other passengers. The garment bag suffers similar distress in the trunks of taxicabs or the luggage hold of buses.
Another problem with respect to garment bags is they typically add to the luggage load for a user who already is struggling with lifting and managing a regular suitcase or duffle bag. The added load can be inconvenient, tiring and uncomfortable. Besides that, more than one "carry-on" item often is not permitted onboard an airplane. An undesirable outcome is that the "soft" or delicate garment bag may be relegated to bruising transport within the airplane's luggage hold.
A relatively recent development has been luggage with wheels and retractable handles, of the type exemplified by Rollaboard®. Early wheeled luggage of this type is described in the U.S. Pat. No. 4,995,487 issued to Plath. Rather than having to carry the suitcase, the Plath invention enables a user to pull the suitcase in such a way that the load is carried on small wheels or rollers. This type of suitcase has become extremely popular due to the obvious improvement in comfort and convenience to the user.
The most popular types of rolling suitcases are those sized to meet the carry-on width/length/girth limits imposed by airline regulations. Generally speaking, present standards, dictate that the carry-on suitcase will not exceed 22″×14″×9,″ although such a designated, chosen or dictated dimension can vary slightly from airline to airline and country to country. When it comes to packing and transporting clothing of various shapes and sizes, roller-equipped or wheeled suitcases which, by design, are relatively small, suffer from the same deficiency or inadequacy of larger, non-wheeled suitcases. That is, wheeled suitcases cannot accommodate large garments without considerable folding and compression.
Manufacturers have tried to combine the convenience of the smaller, wheeled and non-wheeled suitcase with the larger clothes-carrying capacity of a garment bag. They accomplish this by incorporating a garment bag within the confines of the suitcase itself. This allows suits and large garments to be inserted inside the suitcase. Luggage of this nature is known in the industry as a suiter. Such a suitcase eliminates the need to carry two separate pieces of luggage; but, the typical suiter is by no means small. In fact it wields a sizable footprint and significant heft. Besides that, the internal garment bag feature consumes valuable packing space. Alas, the so-called suiter suffers the problem common to regular suitcases, garment bags and the smaller wheeled versions: larger articles of clothing must be folded, and often into several folded layers.
In U.S. Pat. No. 6,109,402, Godshaw describes soft-sided luggage with separate compartments in a saddle-bag configuration designed to fit on top of a wheeled type suitcase. An opening in the soft-sided luggage allows it to fit over a handle of wheeled suitcase so as to extend downwardly along the suitcase sides. One embodiment of this design is a garment bag to hold suits. This luggage carries a number of disadvantages.
While the construction contemplated in the Godshaw patent allows clothing to be carried on the outside of wheeled luggage so as to be portably moveable therewith, it faces the same deficiency as previously described luggage because it requires large garments such as suits to be folded to fit into a garment bag portion of the Godshaw luggage. The resultant combination is bulky and heavy, and must be disassembled to afford access the interior of the wheeled suitcase.
In U.S. Pat. No. 5,624,026, Chernoff demonstrates the concept of rolling clothing around a cylinder to reduce wrinkles. This concept of rolling or wrapping large garments for storage, rather than the traditional folding process has been a major step in the right direction since it eliminates many of the problems of folding, thus going a long way in avoidance of wrinkles. However, a garment bag of this type still must be carried since it is in no way associated with wheels.
While the above discussed patent references as well as others of record in the above noted parent application relate to the present invention disclosed and claimed herein, none has the distinguishing features of the present inventive apparatus and method to be discussed below. More specifically, it is believed that prior to this invention there existed no wheeled luggage adapted to carry relatively larger articles of clothing such as suits dresses and the like in such a way that avoids abusive folding required to fit said clothing inside (or to drape it across) wheeled luggage. In other words, none of the prior art includes the novel features of the present inventive and method disclosed and claimed herein.

Wheeled suitcase with detachable garment bag


A compressor (5) of a turbo supercharger (3) is located between an air flow meter (12) and a throttle valve (13). An EGR passage (21) is connected to an intake passage (10) at a joint (22) upstream of the compressor (5). The following relationship (1) is satisfied between an intake passage volume (V1) from the air flow meter (12) to the junction (22), an intake passage volume (V2) from the compressor (5) to the throttle valve (13) and a maximum boost pressure (Pb) under operating conditions in which the introduction of EGR gas is performed, in order to prevent a mixed gas of fresh air and EGR gas from flowing back to the air flow meter (12) even under the maximum boost pressure (Pb).

As disclosed in Patent Document 1, there is known an intake device for an internal combustion engine with a supercharger such as a turbo supercharger in which the intake device has a recirculation valve for releasing a boost pressure from the downstream to the upstream of a compressor of the supercharger when a throttle valve is closed suddenly in a supercharged state. There is also known an exhaust gas recirculation (EGR) device for introduction of EGR gas from the exhaust system into fresh air at the upstream of the compressor as disclosed in Patent Document 1.
The following problem however arises in the case where the supercharger-equipped internal combustion engine uses the recirculation valve through which the boost pressure is released from the downstream to the upstream of the compressor in combination with the exhaust gas recirculation device by which the EGR gas is introduced into the fresh air at the upstream of the compressor. When the recirculation valve is opened under operating conditions in which exhaust gas recirculation is effected, the mixed gas of fresh air and EGR gas flows back to the upstream side of the intake passage through the recirculation valve so that an intake air flow meter gets fouled by EGR gas components.

Intake device for internal combustion engine with supercharger

Abstract: V          1                >                              V            2                    ×                      (                                                            P                  b                                -                                  P                  1                                                            P                1                                      )                    ×                                    (                                                P                  1                                                  P                  b                                            )                                                      κ                -                1                            κ                                                          (        1        )


A method and arrangement in a telecommunication network according to “GSM on the Net” or “IPT” intercepts an incoming call for a user registered at an access node for which an intercept service is active. Depending on the type of called party identifier provided with the incoming call, the call is routed to the Service Node. The service node identifies an alias of the access node and sends the access node alias with called party data to the application node. The application node returns to the service node a divert-to identifier associated with the access node, and the service node delivers the call to a different access node identified by the divert-to identifier.

The introduction of mobile telephones into society has created a number of social problems due to the fact that a person with a mobile telephone can be available any time, anywhere. Annoyances have been most notable in public group settings where group silence is essential to the experience or performance taking place. Examples of such experiences or performances are live performances, movie theatres, classrooms, conferences or even fine restaurants. Most people have today experienced the distraction of a ringing telephone during a crucial climax or punch line. Similar annoyances can be foreseen with the introduction of PC-phone applications into the business place, where PC-phone applications may disturb meetings, conferences or presentations.
There are several solutions presented to the problem situation described above. For mobile phones the most recent solution is the vibrating alert which replaces the normal ringing alert on incoming call. For PC-phones and mobile phones there are supplementary services as well, such as: Call forwarding, call diversion, screening and messaging services. In the very least, the user can simply turn off the mobile terminal or close down the PC-application. A problem with these solutions are that they rely on the called party to actively do something to prevent the telephone from ringing. However, experience has shown that, in this respect, one simply cannot rely on private persons to honour the privacy of the group.

Supplementary call grabber service for mobile networks


A method for detecting radar signal comprises the steps of: receiving a signal by a receiver, wherein the strength of the received signal is controlled within a range; sampling the received signal so as to obtain a plurality of sampling values; dividing the sampling values into a plurality of segments; summing up the absolute values of the sampling values in each segment; and determining that the received signal includes radar signals if at least one summation is greater than a threshold.

1. Field of the Invention
The present invention relates to a radar detection method and apparatus, and more particularly to a radar detection method capable of detecting radar signals during normal operations.
2. Description of the Related Art
There is a widespread development in wireless communication devices using unauthorized frequency. For example, the Federal Communications Commission (FCC) released 255 MHz bandwidth from 5.470 GHz to 5.725GHz in 2003for unlicensed national information infrastructure (U-NII). However, the signals of U-NII devices at about 5GHz are easily interfered with by existing radar signals. FIG. 1 shows a typical U-NII and radar system. The transmitting scope of a U-NII system 11, e.g., a wireless local area network 11 composed of a plurality of U-NII devices 15 and a wireless base station 14, is overlapped with that of radar systems 12, 13 so that their signals conflict with each other. To resolve such a matter, the FCC regulates that all U-NII devices using bandwidth between 5.25GHz and 5.35GHz and between 5.470, GHz and 5.725GHz have to adopt dynamic frequency selection (DFS) technology so as to hop frequency to a conflict-free channel when a frequency conflict occurs. Thus the conflict issue caused by radar signals around 5GHz is resolved.
While DFS solves the problem of frequency conflict, the issue of effectively implementing the detection of conflicting radar signals remains without solution. 802.11h, the specification defined by the Institute of Electrical and Electronics Engineers (IEEE), proposes that the radio local area network (RLAN) around 5GHz should not only adopt DFS technology to avoid conflict with radar signals and to uniformly allocate bandwidth, but also should suspend current signal transmission in order to detect radar signal to reduce possible signal interference. However, the above suggestion will largely decrease throughput of signal transmission and does not meet the user's demand.
M. Wen, L. Hanwen, "Radar detection for 802.11a systems in 5GHz band," International Conference on Wireless Communications, Networking and Mobile Computing, 2005,pp. 512-514presented an algorithm for detecting radar signals. The algorithm detects power variation whose position is close to sampling signals. However, it normally fails when RLAN and radar signals stay in the same power level.
U.S. Pat. No. 6,697,013discloses another algorithm of detecting radar signal, which achieves the detection based on signal correlation, pulse width and zero crossing. However, its hardware complexity is considerable because both real and imaginary parts of the frequency and time domains have to be compared.

Radar detection method and apparatus using the same


A mechanism for removably mounting instruments with a cylindrical outer case to a flat panel over an opening with a peripheral wall extending perpendicularly from the rear side of the panel and two or more gripping assemblies mounted adjacent to the wall. Outwardly extending flange members mounted on the outer case at one end of the instrument are cooperatively and removably engaged within the gripping assemblies. The gripping assemblies in an alternate embodiment are removably mounted through slots in the panel. A user can mount and unmount the instruments from the rear without requiring the use of any tools.

1. Field of the Invention
The present invention relates to a mechanism for mounting instruments, such as meter gauges, to a panel. And more particularly, to the type that removably flush mounts the instruments from the rear side of a panel with corresponding openings, such as a control panel.
2. Description of the Related Art
Applicant believes that the closest reference corresponds to U.S. Pat. No. 789,735 issued to H. T. Hochhausen in 1905. However, it differs from the present invention because flanges D and E and projections F and G of socket A that hold the latter to a plate with projections F and G. This mechanism does not allow for a flush mount on a panel. Also, the patented lamp holder has crevices and openings that make instruments susceptible to the elements.
Other patents describing the closest subject matter provide for a number of more or less complicated features that fail to solve the problem in an efficient and economical way. None of these patents suggest the novel features of the present invention.

Mounting mechanism for instruments having flanges


The present invention relates to a class D audio amplifier comprising a pulse width modulator, an adjustable loop filter and a feedback loop. The pulse width modulator generates a first set of pulse width modulated control signals at an adjustable modulation frequency for respective switch control terminals of a first output driver. A controller of the class D audio amplifier is configured to control frequency response characteristics of the adjustable loop filter based on a frequency setting of the adjustable modulation frequency.

Class D audio amplifiers are a well-known type of audio power amplifier which is generally recognized to provide energy efficient audio drive of a loudspeaker load by switching a pulse width modulated (PWM) or pulse density modulated (PDM) signal across the loudspeaker load. Class D audio amplifiers typically comprises an H-bridge driver with a pair of output terminals coupled to respective sides or terminals of the loudspeaker load to apply an oppositely phased pulse width modulated or pulse density modulated audio signals across the loudspeaker. Several modulation schemes for pulse width modulated audio signals have been utilized in prior art PWM based class D amplifiers. In so-called AD modulation, the pulse width modulated audio signal at each output terminal or node of the H-bridge is switched between, or toggles between, two different levels in opposite phase. The two different levels typically correspond to the upper and lower power supply rails, respectively, such as the positive and negative DC supply rails of the class D amplifier. In so-called BD modulation, the pulse width modulated signal across the loudspeaker load is alternatingly switched between three levels of which two levels correspond to the above-mentioned upper and lower DC power supply rails and the third level is zero level that is obtained by simultaneously pulling both terminals of the loudspeaker load to one of the DC power supply rails. In multi-level PWM modulation as described in the applicant's co-pending patent application PCT/EP2011/068873, a third supply voltage level, often a set to a mid-supply level between the positive and negative DC supply rails, is applied to output node(s) of the output driver such that for example a 3-level or 5-level pulse width modulated signal can be applied across the loudspeaker load by an appropriately configured output driver.
The present inventor has obtained significant performance improvements in Class D amplifiers by adjusting the modulation frequency of the pulse width modulator according to specific characteristics of the audio input signal. The modulation frequency adjustment is beneficial for several reasons such as reduced EMI emission, reduced power loss in output switching devices etc. However, frequency response characteristics of loop filters of class D audio amplifiers are ordinarily designed or selected such that the feedback loop remains just stable, within a required safety margin due to component spread and production spread, at full output power and maximum setting of the modulation frequency. This loop filter design is advantageous in order to suppress distortion and noise generating mechanisms introduced by non-ideal behaviour of circuitry and components of the class D amplifier within the feedback loop. However, the just stable design of the loop filter at the maximum setting of the adjustable modulation implies the feedback loop tends to become unstable if a lower modulation frequency than the maximum frequency setting is chosen. Such a lower modulation frequency would otherwise be advantageous for example to save power as described above. Hence, it is advantageous to tailor or adapt the frequency response characteristics of the adjustable loop filter to a current setting of the modulation frequency, and optionally load power level, to obtain the highest possible loop gain of the feedback loop throughout the audio bandwidth (20 Hz-20 kHz) within loop stability constraints for specific settings of the modulation frequency of the pulse width modulator.
Accordingly, class D audio amplifiers with reduced levels of EMI noise are highly desirable. Likewise, class D amplifiers with improved power efficiency, especially at low or small audio input signals levels, are also highly advantageous. Finally, it is desirable to decrease the size of the external load inductors and load capacitors to provide more compact, power efficient, reliable and less costly Class D amplification solutions for consumer and other types of audio products.

Class D audio amplifier with adjustable loop filter characteristics


An apparatus is provided for applying to a surface of mammalian tissue including soft, living tissue an initially fluent material and then activating the material by exposure to an energy source. The material may be a liquid capable of polymerization to a non-fluent state by exposure to actinic light. The device, and methods that may be practised in association with the device, enable a wide range of medical conditions to be treated including, for example, the application of a barrier to soft tissue to prevent post-surgical adhesions.

A number of photopolymerizable hydrogel polymers that may be applied to mammalian tissue, including soft, living tissue, in order to treat various medical conditions are disclosed in the following U.S. patent applications:
U.S. patent application Ser. No. 843,485 filed Feb. 28, 1992 (Hubbell et al.) and a continuation-in-part thereof, Ser. No. 08/022,687 filed Mar. 1, 1993, PA1 U.S. patent application Ser. No. 07/870,540 filed Feb. 28, 1992 (Hubbell et al.) and a continuation-in-part thereof, Ser. No. 08/024,657 filed Mar. 1, 1993.
The hydrogels disclosed in the foregoing applications may be applied to living tissue, for example, for the prevention of postoperative adhesions, the protection of tissue surfaces, the local application of biologically active species, and the controlled release of biologically active agents to achieve local and systemic effects. They also may be used as temporary or long-term tissue adhesives or as materials for filling voids in biological materials. The materials and conditions of application are selected to enhance desirable properties such as good tissue adherence without adverse tissue reaction, non-toxicity, good biocompatability, biodegradability when desired, and ease of application or handling.
The composition that will form the polymerized hydrogel may include a light sensitive polymerization initiator and is applied to the tissue surface in fluent form, as a liquid. The coated tissue then is exposed to light to polymerize the composition and render it non-fluent, in situ. The light is selected to be of an appropriate wavelength to efficiently initiate or sustain the polymerization and is of an appropriate intensity to achieve the polymerization within the desired time.
Reference is made to the above-identified patent applications for a detailed description of various hydrogels usable in this invention, their compositions, manufacture and general use. The disclosures of the above-identified applications are incorporated by reference as part of the disclosure herein.

Apparatus and method for local application of polymeric material to tissue


The present invention relates to a process for producing N-alkyl-N-trialkylsilylamides from trialkylsilylhalides and N-alkylamides in the presence of a base and in the absence of a solvent.

The N-alkyl-N-trialkylsilylamides are particularly useful as silylating agents in a process for the manufacture of a peptide or peptide analogue. In particular, N-alkyl-N-trialkylsilylamides are useful as silylating agents for amino acids, peptides or peptide analogues in the manufacture of peptides or peptide analogues as e.g. described in EP 2062909 A1 or EP 2060580 A1 or for derivatization of compounds for e.g. gas chromatography as disclosed in U.S. Pat. No. 4,467,037 due to their increased volatility upon silylation.
Different processes for synthesis of N-alkyl-N-trialkylsilylamides are known and summarized e.g. in T. R. Bailey, Science of Synthesis (2005), 21, 811-31. This document discloses the synthesis of 2,2,2-trifluoro-N-methyl-N-(tert-butyldimethylsilyl)acetamide by deprotonating of the amide with NaH at 0° C. followed by treatment with tert-butyldimethylsilyl chloride in a polar aprotic solvent (acetonitrile/benzene 1:1) at 4° C. Further the silylation of N-methylacetamide with trimethylsilyl chloride using triethylamine as nitrogen containing organic base in anhydrous benzene (anhydrous toluene or acetonitrile may be substituted) with the reaction being performed at 0-5° C. is disclosed. The above reactions are explained in more detail in Mahwhinney, T. P.; Madson, M. A., J. Org. Chem., (1982) 47, 3336) and de Benneville, P. L.; Hurwitz, M. J., U.S. Pat. No. 2,876,209, (1959) ; Chem. Abstr., (1959) 53, 67817.
U.S. Pat. No. 4,467,037 relates to the silylation of amino acids for analysis by gas chromatography. One example of this document discloses the reaction of tert-butyldimethylsilyl chloride (1.3 mole) with N-methylacetamide (1 mole) dissolved in triethylamine, which is used as solvent in an amount of about 10 moles. The reaction mixture is stirred for 24 h at room temperature before isolating the end product.
All of these processes of the prior art have in common that solvents are used for dissolving the educts of the reaction, be it for example acetonitrile/benzene 1:1, anhydrous benzene (or anhydrous toluene or acetonitrile) or triethylamine. These solvents have to be removed at some point during the process to isolate the desired product. The use of solvents is always impaired with costs and environmental burden. Furthermore, if the boiling points of the desired product and the employed solvents are not sufficiently distinct a separation by distillation can additionally complicate the isolation of the desired product.
In another approach for the synthesis of N-methyl-N-trimethysilylacetamide EP 0 021 238 directly heats N-methylacetamide with N-trimethylsilylimidazole to boiling at 13 mbar. The temperature of this process is between 120 and 170° C. and the reaction product is continuously removed by distillation over 8 h. The resulting N-methyl-N-trimethylsilylacetamide is subsequently further purified by fractional distillation. This process requires N-trimethylsilylimidazole which is costly, even when imidazole obtained from the process is recovered and the imidazole is again converted into N-trimethylsilylimidazole, for example by means of hexamethyldisilazane. Furthermore, the process requires long reaction times, which is disadvantageous. Besides, it is difficult to carry out a process using such low pressure in an industrial scale and cleaning of the reaction container containing the imidazole obtained from the process is impeded by the high melting point of imidazole (86-90° C.).
There is need for a process for producing N-alkyl-N-trialkylsilylamides which does not have the disadvantages of the prior art. In particular, the process should be economic and environmentally friendly, even on an industrial scale and be able to provide N-alkyl-N-trialkylsilylamides in a good yield and with a sufficient purity using as few steps as possible while keeping low reaction time and low reaction temperatures.
For solving these problems, the present invention provides a process as defined in the claims.

Industrial process for the preparation of N-alkyl-N-trialkylsilylamides


A light assembly comprising: (a) one or more light sources; and (b) one or more reflectors comprising: (i) a first reflector facet that forms a first reflected light by redirecting light from the one or more light sources in a first direction and (ii) a second reflector facet that forms a second directed light by redirecting light from the one or more light sources in a second direction; and wherein the first directed light and the second directed light are configured to extend away from a vehicle housing the light assembly to form a light pattern that demonstrates a location the light assembly is aimed relative to the vehicle.

Headlights in vehicles typically are static in position and once aimed maintain the aim. However, as vehicles move an adjustment of the light may change over time so that the lights are directed outside of a desired location. It also may be difficult for an operator of a vehicle to determine that the lights are misaligned; however, the misalignment may be apparent to or directed toward surrounding vehicles or individuals.
Examples of lights or light systems may be disclosed in U.S. Pat. Nos. 4,236,099; 6,483,441; and 6,040,787 and US Publication Nos. 2002/0130953; 2005/0099821; and 2005/0134482 all of which are expressly incorporated herein by reference for all purposes. Thus, there is a need for a device that assists in aiming light from a light source. It would be desirable to method and device for aiming each individual light individually. There is a need for a device and method of determining a direction a light source is projecting and aligning the light source. It would be desirable to be able to aim each individual light of a vehicle.


4-(pentafluorosulfanyl)benzenediazonium tetrafluoroborate salt was synthesized and isolated. The pentafluorosulfanyl salt was examined in a wide assortment of reactions to form novel SF5-bearing alkenes, alkynes, and biaryl derivatives using Heck-Matsuda, Sonogashira, and Suzuki coupling protocols. Dediazoniation of the salt furnished the corresponding p-SF5—C6H4X,C6H4OS(O)(CF3)═NSO2CF3, and p-SF5—C6H4-NTf2 derivatives. The azide derivative p-SF5—C6H4N3 entered into click chemistry with phenylacetylenes to furnish the corresponding triazoles. Various SF5-bearing alkenes were synthesized by coupling reactions using a metal catalyst. Fluorodediazoniation selectively furnished the fluoro derivative p-SF5—C6H4F. Homolytic dediazoniation gave the unsymmetrical biaryls, thus demonstrating the broad utility of pentafluorosulfanyl diazonium salts as building blocks of SF5-aromatics that are in high demand in many branches of chemistry including biomedicine and materials chemistry.

The presence of the pentafluorosulfanyl (SF5) group imparts a number of favorable physical and chemical characteristics including thermal, hydrolytic, and chemical stability, high density, high electronegativity, and high lipophilicity. These favorable characteristics have prompted a high degree of interest in SF5-organics for potential applications in the biomedical and materials fields (Altomonte & Zanda, J. Fluorine Chem. 2012, 143, 57-93). As such, pentafluorosulfanyl-substituted compounds are undergoing extensive studies for use as high performance polymers, liquid crystals, pharmaceuticals and pesticides (Thayer, Chem. Eng. News 2006, 84:27-32).
As a substituent on an aromatic ring the SF5 group acts as a sterically demanding, strongly electron-withdrawing/deactivating group. A major drawback in the development of synthetic chemistry of SF5-arenes has been the lack of practical methods that avoid the use of exotic/hazardous reagents and harsh conditions. In early pioneering studies Sheppard synthesized the parent (pentafluorosulfanyl)benzene and its p-nitro derivative in modest yields by reacting the corresponding aryl disulfides or aryl sulfur trifluorides with excess AgF2 in chlorofluorocarbon solvent at elevated temperatures in a copper reactor (Sheppard, J. Am. Chem. Soc. 1962, 84, 3064-3072). This method was later employed by Thrasher et al. (Sipyagin, et al., J. Fluorine Chem. 2001, 112, 287-295; Sipyagin, et al., J. Fluorine Chem. 2004, 125, 1305-1316) to prepare various substituted derivatives of PhSF5 in modest overall yields and many side products. Subsequent methods reported from other laboratories involved elemental fluorination starting with the corresponding bisnitrophenyl disulfide, (Bowden, et al., Tetrahedron 2000, 56, 3393-3408; Kirsch & Hahn, Eur. J. Org. Chem. 2005, 3095-3100; Kirsch & Hahn, Eur. J. Org. Chem. 2006, 1125-1131; Kirsch, et al., Angew. Chem. 1999, 111, 2174; Kirsch, et al., Angew. Chem. Int. Ed. 1999, 38, 1989-1992) and high pressure reactions with gaseous SF5 halides (Sergeeva & Dolbier Jr, Org. Lett. 2004, 6, 2417-2419; Winter & Gard, J. Fluorine Chem. 2004, 125, 549-552). The 3-nitro derivative is accessible by direct electrophilic nitration of PhSF5 (Sheppard, J. Am. Chem. Soc. 1962, 84, 3064-3072; Bowden, et al., Tetrahedron 2000, 56, 3393-3408; Kirsch & Hahn, Eur. J. Org. Chem. 2005, 3095-3100; Kirsch & Hahn, Eur. J. Org. Chem. 2006, 1125-1131; Kirsch, et al., Angew. Chem. 1999, 111, 2174; Kirsch, et al., Angew. Chem. Int. Ed. 1999, 38, 1989-1992; Sergeeva & Dolbier Jr, Org. Lett. 2004, 6, 2417-2419). A recent method reported by Umemoto et al. (Umemoto, et al., Beilstein J. Org. Chem. 2012, 8, 461-471) involves synthesis of ArSF4Cl from ArSSAr or ArSH by reaction with Cl2/KF or CsF and subsequent transformation to ArSF5 by ZnF2/heat.
The strongly deactivating effect of SF5 group makes PhSF5 amenable to SNAr chemistry notably with alkoxides and thiolate, (Beier, et al., Org. Lett. 2011, 13, 1466-1469) and by vicarious nucleophilic substitution of hydrogen (Beier, et al., J. Org. Chem. 2011, 76, 4781-4786; Iakobson, et al., Synlett 2013, 24, 855-859; Vida & Beier, J. Fluorine Chem. 2012, 143, 130-134). By contrast, the SEAr chemistry of SF5-aromatics has remained under-developed. In early work by Bowden (Bowden, et al., Tetrahedron 2000, 56, 3393-3408) the 3-iodo and 4-iodo derivatives were synthesized by in-situ diazotization and reaction with KI, and were shown to enter into cross coupling reactions in representative cases. Formation of an SF5-based azo-dye by in-situ diazotization and coupling to PhNMe2 was reported by Kirsch and Hahn (Kirsch & Hahn, Eur. J. Org. Chem. 2006, 1125-1131). However, the F5S—C6H4N2+ salt was never isolated in earlier studies to allow its use as a key building block for the synthesis of other SF5-aromatics using diazonium ion chemistry.
The commercial availability of parent PhSF5 and a few other derivatives, notably the p-Me, the p-NH2, and the m- and p-NO2 derivatives has remedied some of the preparatory problems. However, there are only a few readily available pentafluorosulfanyl compounds, significantly limiting the use of pentafluorosulfanyl-based synthesis. Much of the current technology focuses on synthetic methods that use of exotic and/or hazardous reagents and harsh conditions. As such, what is required is a readily available starting pentafluorosulfanyl-substituted compound for use in pentafluorosulfanyl-based synthesis.

Synthesis of 4-(pentafluorosulfanyl)benzenediazonium tetrafluoroborate and analogs and their application for the preparation of SF


A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

Gather and scatter instructions are types of vector load/store instructions that access multiple memory locations. Gather instructions perform loads, and scatter instructions perform stores. Gather/scatter memory operations, also referred to as indexed memory accesses, appear commonly in modern scientific and data analysis applications that often involve sparse and adaptive data abstractions, such as adaptive meshes, sparse matrices, tensors, and graphs. For any given application context, a gather/scatter operation may involve indirection offsets that are highly random or regular. These applications may exhibit patterns with or without locality, and sequences of such operations may be highly serialized or highly parallel.
Historically, gather/scatter instructions have been supported in the context of vector supercomputers, but until very recently have not been supported by general purpose instruction set architectures. Recently, support for these instructions have appeared in general purpose instruction sets, such as x86 and ARM.

Method and apparatus for back end gather/scatter memory coalescing


A device for widening a hollow body at least partially having elastic regions, which device is connected to the hollow body and widens the hollow body to a desired circumference. At least one elastic device, which can be concertedly widened over its full length by means of force transmitting means, is disposed on the hollow body.

The present invention relates to a device and a method for widening a hollow body having an at least partially elastic region, in which an elastic device is firmly connected to the hollow body to widen the hollow body to a desired circumference.
In certain circumstances, there is a need in medicine to surround with a cover, e.g., to protect against mechanical or chemical influences or for the purpose of locating. Particularly in the field of organology, there is a need in certain cases to protect an organ against exterior chemical or mechanical influences by covering the organ. If these covers fit snugly, e.g. for locating purposes, elastic covers are employed which are widened accordingly before they can be drawn over the organs.
It is known to widen elastic covers from the interior by means of suitable tools or to manually open elastic covers in such a manner that the cover can be slipped over the object to be covered. When the cover slackens and thus contracts, the tools and/or fingers used for widening it reach in between the cover and the object to be covered and are pressed against the object by the contracting force of the cover. Especially if sensitive objects are involved, for example human organs, the contracting force of the cover transmitted through the assisting tools and/or fingers may result in deformations of the organs which can lead to irreversible damage. Moreover, there is also the danger that unevenness or edges of the assisting tools and/or fingers may damage the object to be covered when the contracting pressure is applied.
Once the elastic cover is positioned about the object to be covered in the proper manner and fits, the assisting tools and/or the fingers have to be drawn out from between the cover and the covered object. However, during this drawing out lateral forces act upon the cover and the object. These forces can, on the one hand, cause the object to shift position or the object and the cover to shift position in relation to each other, which on the other hand, may lead to further damage to the cover and to the covered object. The object to be covered is subject to further stress from jolting when the assisting tools and/or the fingers are ultimately withdrawn caused by the elasticity of the cover, i.e., a snapping down effect of the elastic cover against the object to be covered when the assisting tools and/or the fingers are finally fully withdrawn, leading to the brief greater local application of pressure than the static load pressure of the cover on the object. Furthermore, it is extremely difficult, if not impossible, to correct the position by widening the cover again without damaging the cover or the object to be covered, for example a human organ.
In addition to the known manner of slipping an elastic cover over an object to be covered generally described above, it is also known to widen the elastic cover from the exterior using a vacuum and then to slip it over the object. For this purpose the elastic cover is briefly surrounded by a larger, rigid cover and connected to it in an airtight manner, i.e. such that there is a vacuum, which can be adjusted as desired, in the intermediate space between the elastic and the rigid covers. After positioning by slackening, the cover can be mounted over the object to be covered from the exterior by means of suited pressure adjustment without any other external influences.
For this purpose, the opening of the external, rigid cover must possess a width which at least corresponds to the largest expansion of the object to be covered. Therefore, the elastic cover must also be correspondingly widened at this point. However, this expansion cannot be obtained at the point of contact by the developing vacuum, but by mechanical gripping forces.
The elastic cover has to be expanded at the opening of the surrounding rigid cover in a conventional manner so wide that it can be attached at the edges of this opening in a suited manner, for example airtight. The attachment can, for instance, occur by means of a rubber ring. On the other hand, the opening in the rigid cover has to be at least so large that the object to be covered can pass through without using force. In this way, moreover, no complete slackening of the elastic cover is possible simply by reducing the vacuum. Therefore, it is necessary to use, at least at the point of contact, mechanical aids which suitably widen the cover.
In addition to the drawbacks described above, which also occur due to the mechanical widening, there is also the expense of complex instruments. Moreover, it is necessary, depending on the varying sizes of the objects to be covered, to employ exterior covers of varying rigidity. Finally, readjustment is not possible after removal of the exterior, rigid cover from the flexible cover.
An object of the present invention is to provide a device and a method for widening a hollow body at least partially having elastic regions, which device is connected to the hollow body and widens the hollow body to a desired circumference, in such a manner that it is possible to widen the elastic cover without mechanical influence on the interior side of this cover. Another object of the present invention is to avoid foreign bodies remaining between the cover and covered object after contraction of the elastic cover. A further object of the present invention is to provide a device and method in which the entire covering procedure is as gentle as possible for the object to be covered, and which avoids the brief exposure of local influences of force to the object to be covered.
These and other objects have been achieved by providing a device for widening a hollow body having an at least partially elastic region, including at least one elastic device connected to the hollow body, and a force transmitting means configured to stretch the elastic device in order to widen the hollow body.
These and other objects have also been achieved by providing a method of widening a hollow body having an at least partially elastic region, the method comprising the steps of attaching an elastic body to the hollow body, and stretching the elastic body with a force transmitting means in order to widen the hollow body.
The present invention provides and advantageous device and method for widening a hollow body at least partially having elastic regions, which device is connected to the hollow body and widens the hollow body to a desired circumference in such a manner that at least one elastic device which can be concertedly widened over its entire length by a force transmitting means is disposed on the hollow body.
The present invention is based on the idea to tangentially attach an elastic hose which has a closed end and an open end to the elastic hollow body suited for covering sensitive objects. A preferably flexible rod, the length of which is longer than the length of the hose which is disposed on the exterior side of the hollow body is entered into the open end of the hose. If the flexible rod is entered further into the hose than the length of the hose in the slack state permits, the elastic hose stretches over its entire length. The elastic hose is firmly connected to the walls of the hollow body along a generally circumferential course of the hollow body, such that the hollow body expands radially outward as the elastic hose stretches and assumes, in the region of the elastic hose, the widened shape of the flexible rod. The degree of widening is solely limited by the elasticity of the material and the length of the flexible rod.
Using several elastic hoses suitably disposed on or in the walls of the hollow body permits expanding the hollow body over its entire length in such manner that the objects to be protected can be covered.
In order to simplify handling of the invented expanding device for the operator, a suitable stopping and/or locking device may be provided at the open end of the elastic hose as well as at the proximal end of the flexible rod in such a manner that the elastic cover is automatically held open. Contraction of the cover can be precisely controlled by means of suitable end stopping and/or locking devices and controlled retraction of the flexible rod from the elastic hose.
It is also contemplated to expand the elastic hose disposed on the exterior side of the hollow body by concerted introduction of a gas or a liquid into the hose, requiring that the elastic hose can be made gas-tight or liquid-tight.
These and other objects, features and advantages of the present invention will become more readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.

Device and method for widening a hollow body having an at least partially elastic region


A signal generator generates a WiMedia ultra wideband test signal with a user interface for setting test sequences and parameters of the test signal. Parameters are set for Presentation Protocol Data Units associated with Packet Groups of the test signal. A signal processing unit compiles the Groups containing the Presentation Protocol Data units to generate digital data representative of the test signal. A waveform generator receives the digital data and generating a test signal output having Packet Groups containing Presentation Protocol Data Units. A method is describes for setting test sequences and parameters of an ultra wideband test signal test signal with a user interface of the signal generator.

The present invention relates generally to the generation of test signals and more particularly to a signal generator and user interface for setting parameters and test sequences for a test signal generated by the signal generator.
To check the operation of an electrical circuit under test, a test signal is provided to the circuit under test. A signal generator is an apparatus that provides such a test signal for checking the operation of the circuit under test. The signal generator has controls for setting-up the test signal according to user settings. The output signal from the electrical circuit may be observed by a measurement instrument, such as an oscilloscope or the like.
Various manufacturers provide user interfaces for setting-up test signals. One Example is the WinIQSIM™ Simulation Software, manufactured and sold by Rohde & Schwarz. The simulation software provides a user interface for setting-up digitally modulated signals and adding impairments to the signals. The user interface has a multi-carrier block diagram as shown in FIG. 1A having various blocks for defining parameters and setting impairments to the signal. Clicking on one of the blocks, such as the Data Source block, opens a data source dialog window as shown in FIG. 1B where the user can define data parameters or import a data file. Once the user has set the parameters of the data source, the user clicks the OK box and the dialog box closes. Clicking on the Modulation Setting block as shown in FIG. 2A opens a Modulation dialog window as shown in FIG. 2B where the user can set the modulation parameters of the signal. Clicking on the OK box closes the Modulation Setting dialog window. Clicking on the IQ Impairment block as shown in FIG. 3A opens an IQ Impairment dialog window as shown in FIG. 3B where the user can set the IQ Impairments "On" and set IQ impairments for the signal. Clicking on the OK box closes the IQ Impairment dialog window.
A drawback to the above described user interface is that the user has to set signal parameters with the respective dialog windows for each of the blocks in the block diagram. This does not allow the user to view all of the settings for the signal at a glance. Further, the above user interface does not allow the setting of a group of PPDUs (Presentation Protocol Data Units) and the repeating of the group(s). Neither does the above described user interface provide for selective ON/OFF of signal components, such as headers and Physical layer Service Data Unit (PSDU).
What is needed is a user interface for use with a signal generator that allows a user to view the settings of a signal at a glance. The user should be able to set parameters for signal packets and groups of packets. The user interface should allow sequence control of the groups to allow the signal generator to provide various and complicated frame sequences and provide structured test approaches to design development processes.

Signal generator and user interface for setting test sequences and parameters of a test signal