An electro-optical device according to the present invention comprises an electro-optical layer, a pair of electrodes facing each other with the electro-optical layer interposed therebetween, and a metal layer and a plurality of layers laminated on the metal layer which are arrange toward the electro-optical layer on a substrate provided on one side of the electro-optical layer, wherein an outer periphery of the metal layer is covered by a first layer of the plurality of layers which is initially formed.

1. Field of the Invention
The present invention relates to a substrate for an electro-optical device, an electro-optical device and an electronic device, and a method for manufacturing the electronic device, and more specifically, to the construction of an electro-optical device in which a metal layer is provided on a substrate.
2. Description of the Related Art
In general, in various electro-optical devices, such as a liquid crystal display device, an organic electro-luminescent device, and a plasma display device, a pair of electrodes is opposite to each other with an electro-optical layer interposed therebetween, and a substrate is provided on at least one side of the electro-optical layer. A liquid crystal display device, which is an example of an electro-optical device, usually has a panel in which electrodes are formed on the inner surfaces of a pair of substrates, the pair of substrates is bonded to each other by a sealing material, and liquid crystal is injected in a space surrounded by the pair of substrates and the sealing material.
There are two reflecting types of liquid crystal display devices: one is a reflective liquid crystal display device, and the other is a transflective liquid crystal display device, both having a reflective plate or reflective layer. As this type of device, a device in which a reflective layer is disposed on the external side of a substrate is used. However, in this case, since light passes through a substrate two times and is then visually recognized, display quality deteriorates due to parallax caused by the path of light. Therefore, it is common that an internal reflection type device having a reflective layer on the inner surface of the substrate is mainly manufactured.
In the internal reflection type liquid crystal display device, the reflective layer is formed by depositing a metal material, such as aluminum, an aluminum alloy, a silver alloy, or a chromium alloy, on the substrate using an evaporation method or a sputtering method. In the case of color liquid crystal display devices, color filters have a construction in which colored layers are provided on the reflective layer. In this case, there has been known a method of preventing the reflective layer from damaging by covering the reflective layer with the colored layers and by forming the reflective layer within the boundary narrower than that of the colored layers.
An example of the transflective liquid crystal display device will be described with reference to FIG. 16. A liquid crystal display device 200 has a construction in which a liquid crystal layer 235 is provided between a first substrate 210 and a second substrate 220. In the first substrate 210, a transparent base layer 212, a reflective layer 213, colored layers 214F and 214C, a protective layer 215, a transparent electrode 216, and an alignment film 217 are formed in order on a substrate 211. In the second substrate 220, a transparent electrode 222 and an alignment film is formed in order on a substrate 221. An opening 213a is formed corresponding to every pixel P in the reflective layer 213. A light transmission region Pt is formed of the opening 213a, and a light reflection region Pr is formed of regions other than the light transmission region Pt. A light-shielding layer 214 is formed between pixels. According to the liquid crystal display device, it is possible to make the liquid crystal layer 235 thicker in the light transmission region Pt and to make the liquid crystal layer 235 thinner in the light reflection region Pr only by patterning the protective layer 215. Also, according to the conventional embodiment illustrated in FIG. 16, it is possible to reduce the difference of display quality between transmissive display and reflective display by making the optical density of the colored layer 214C in the light transmission region Pt larger and the optical density of the colored layer 214F in the light reflection region Pr smaller.
FIG. 17(a) is an enlarged cross-sectional view illustrating the construction of a part of the peripheral region provided on the outside of a display region in which a pixel P is arranged in the first substrate 210 of the liquid crystal display device 200.
In the peripheral region, a light-shielding layer 214BM is formed by laminating a red colored layer 214R and a blue colored layer 214B in order. The light-shielding layer 214BM is covered with a protective layer, on which a wiring line 218 to be connected to the transparent electrode 216 is arranged. An outer periphery 213e of the reflective layer 213 is provided under the light-shielding layer 214BM.
However, the liquid crystal display device 200 may have a defect in display in that the outer periphery 213e of the reflective layer 213 lifts together with the light-shielding layer 214BM to disconnect the wiring line 218 as illustrated FIG. 17(b) when the reflective layer 213, the colored layers 214B, 214R, and 214G, the protective layer 215, the electrode 216, and the wiring line 218 are formed in this order. Such a defect in display occurs even when the reflective layer is formed to be narrower then the colored layer, resulting in a reduction of yield.
Accordingly, the present invention is designed to solve the above problems, and it is an object of the present invention to provide a substrate for an electro-optical device and the construction of the electro-optical device capable of reducing a defect in display due to the disconnection of wiring lines and of improving the yield of product by preventing the lifting of the outer periphery of metal layer.

Substrate for electro-optical device, electro-optical device, electronic apparatus, and method for manufacturing electro-optical device


A processing device and a machine-implemented method may be provided for sequentially aggregating, or writing, data to a log included in a data store. The log may store multiple log entries. Each of the log entries may include an entry metadata portion, describing a respective log entry, and an entry payload data portion. The entry metadata portion may include a log sequence number, corresponding to a log entry at a particular position in the log. A library of log-related processes may be provided, along with an application program interface to permit a calling application program to call any of the log related processes. The log-related processes may be called during a boot mode, a user mode, and a kernel mode.

Data may reside over a wide range of addressable storage space of a data store. With respect to some data stores, data may only be written incrementally through addressable storage space. With respect to random access data stores, such as, for example, disks and flash-based storage, data may be written in any order to any storage location. Although writing data in any order to any storage location may be convenient, often this approach is not very efficient for writing to the random access data stores. A most efficient approach for writing data to a random access data store is sequential writing of the data.
A random access data store, such as, for example, a modern disk drive, may be capable of moving approximately 700 kilobytes (KB) of data in an amount of time taken for the disk drive to seek an arbitrary location on a disk. As technology advances, disk drives may be capable of moving larger amounts of data during a same time period.
Most data transfers are much smaller than 700 KB. As a result, disk drives may spend a significant amount of time seeking locations on disks during non-idle time periods.


This invention concerns a valve for an underpressure-activated outflow mechanism for a drinking receptacle (2). The valve includes a valve head (34) and a valve seat (44), in which the valve seat (44) is arranged in force-transmitting connection with a membrane (1), whereas the valve head (34) is fixed to the remaining structure via at least one stay (36).

This invention concerns an underpressure-activated valve device for a drinking receptacle. The valve includes a valve head, a valve seat and a flexible membrane. The valve seat is in force-transmitting connection with the flexible membrane, whereas the valve head is fixed to an associated support structure. Particularly, the invention is directed towards a valve design suitable for mould casting and mass production.
The patent literature discloses several devices that utilize underpressure for activating a valve for a drinking receptacle, for example as shown in U.S. Pat. No. 6,290,090 and in Norwegian patent no. 315182. Common to prior art in this area is that the valve seat is fixed to an associated structure, and that only the sealing surface of the valve head can be moved or change shape during activation of the valve. By making the valve seat moveable, however, it is possible to obviate the need for the valve head requiring horizontal sealing surfaces that must be pulled out of the casting mould after moulding, which may inflict damage to such a sealing surface. The sealing surface may also become damaged during assembly, inasmuch as it becomes strongly deformed when forced through a valve opening. Having to inspect the sealing surface by means of known inspection methods provides both an increase in cost and complexity.


A pull tab apparatus may be easily connected to and disconnected from a slide fastener by a user. The pull tab apparatus includes a coil having a first end and a second end. The coil includes a first section and a second section. At least one of the first and second sections includes a plurality of layers and a path exists between the layers. One of the first and second sections includes a circular portion and the other one of the first and second sections includes a plurality of parallel portions coupled to the circular portion. A circular disc is inserted into the circular portion. A portion of the slide fastener is movable along the path from one of the first and second ends where the pull tab apparatus is disconnected from the slide fastener to a predetermined position where the pull tab apparatus is connected to the slide fastener.

1. Field of the Invention
The present invention generally relates to a pull tab apparatus, and more particularly, to a pull tab apparatus that may be easily connected to and disconnected from a slide fastener by a user.
2. Background Information
Slide fasteners often rely on a pull tab apparatus for effective operation. For example, a pull tab apparatus may be manipulated by a user to move a slide fastener such as a zipper in various directions. Pull tab apparatuses and slide fasteners may be used for various articles such as clothing garments, garment bags, backpacks, purses, luggage, camping equipment, vehicle/boat covers, and/or other articles.
With current pull tab apparatuses and slide fasteners, a problem arises when a pull tab apparatus breaks. In particular, when such breakage occurs, a user may be prevented from using the slide fastener. For example, certain slide fasteners such as zippers may include a locking mechanism in the zipper head that must be disengaged before the zipper can be moved in any direction. Accordingly, when a pull tab apparatus breaks with such a zipper, the locking mechanism may remain engaged and thereby prevent the zipper from being used. One solution to the foregoing problem is to replace the entire zipper head. While the cost of replacement parts with this approach may be relatively small, the labor costs can be cost-prohibitive for many users.
Accordingly, there is a need for a pull tab apparatus which avoids the foregoing deficiencies, and can thereby be easily connected to and disconnected from a slide fastener by a user. The present invention addresses these and/or other issues.


A method and apparatus for speech transmission in a telecommunications system in which a speech signal is compressed to a small number of speech coding bits by a speech coding method, and the speech coding bits are subjected to channel coding. Several different speech coding methods, which may all operate at different transmission rates, are involved in the speech transmission. The method is based on the use of two-stage channel coding. The first channel coding is dependent on the speech coding method, and it is performed in connection with the speech coding in such a manner that the total transmission rate provided by the speech coding and the first channel coding is always constant irrespective of the speech coding method. The second channel coding performed thereafter is always exactly the same regardless of the speech coding method and the first channel coding method, and it is used with all speech coding methods. The second channel coding may be, for example, the original channel coding in an existing telecommunications system.

In telecommunications systems transmitting digital speech, a speech signal is usually subjected to two coding operations: speech coding and channel coding.
Speech coding comprises speech encoding performed in the transmitter by a speech encoder and speech decoding performed in the receiver by a speech decoder. The speech encoder in the transmitter compresses a speech signal so that the number of bits used for representing the speech signal per a unit of time is reduced, whereby less transmission capacity is required for transmitting the speech signal. The speech decoder in the receiver performs a reverse operation and synthesizes the speech signal from the bits generated by the speech encoder. However, the speech synthesized in the receiver is not identical with the original speech compressed by the speech encoder; the original speech has changed more or less as a result of the speech coding. In general, the more the speech is compressed in the speech coding, the more its quality deteriorates during the coding. In the pan-European GSM mobile communication system (Global System for Mobile Communication), for example, the speech encoder of a full-rate traffic channel compresses a speech signal to a transmission rate of 13 kbit/s. The speech synthesized by the corresponding speech decoder is clearly of a poorer quality than the speech transmitted by, for instance, a public switched telephone network (PSTN).
Thus, when a speech coding method is selected, a compromise must be made between the quality offered by the method and the transmission capacity required by it. Another factor to be considered in the selection is the complexity of the implementation of the speech coding method: the quality of speech can usually be improved without increasing the transmission rate if higher requirements for the method as regards calculation capacity and thereby also higher costs of the implementation are allowed. On account of the continuous development of speech coding methods and the implementation techniques, more and more advanced methods are available for speech transmission in the existing telecommunications systems. After the development of the method employed in the GSM, speech coding technology has advanced to such an extent that, as compared with the above-mentioned 13 kbit/s speech coding method, a higher quality of speech can now be achieved at a much lower transmission rate, e.g. 8 kbit/s.
Channel coding comprises channel encoding performed in the transmitter by a channel encoder, and channel decoding performed in the receiver by a channel decoder. The purpose of channel coding is to protect speech coding bits to be transmitted against errors occurring in the transmission channel. Channel coding can either be used for merely detecting whether the transmission has caused any errors in the speech coding bits without any possibility of correcting them, or it may be capable of correcting errors caused by the transmission, provided that the number of errors does not exceed a given maximum, which is dependent on the channel coding method.
The selection of the channel coding method employed depends on the quality of the transmission channel. In fixed transmission networks the probability of errors is often very low, wherefore not much channel coding is required, whereas in wireless networks such as mobile telephone networks the probability of errors in the transmission channels is often very high, and the channel coding method employed has a significant effect on the resulting quality of speech. Mobile telephone networks usually employ both error-detecting and error-correcting channel coding methods concurrently.
Channel coding is based on the use of error check bits, also called channel coding bits, added to the speech encoding bits. Bits produced by the speech encoder of the transmitter are supplied to a channel encoder, which adds a number of error check bits to them. In the above-mentioned GSM full-rate transmission channel, for example, error check bits with a transmission rate of 9.8 kbit/s are added to speech coding bits of 13 kbit/s on the transmission channel, whereby the total transmission rate of the speech signal on the channel will be 22.8 kbit/s. The channel decoder decodes the channel encoding in the receiver in such a way that only the 13 kbit/s bit stream produced by the speech encoder is applied to the speech decoder. During channel decoding, the channel decoder detects and/or corrects errors that have occurred on the channel as far as such error correction is possible.
Speech coding and channel coding are closely connected with each other in telecommunications systems transmitting speech. The significance of the bits produced by the speech encoder for the quality of speech generally varies so that in some cases one error in an important bit may cause audible noise in the synthesized voice, whereas a larger number of errors in less important bits may be almost imperceptible. How big the differences between the importance of speech coding bits are depends essentially on the speech coding method employed; however, at least small differences can be found in most methods. When a speech transmission method is developed for a telecommunications system, channel coding is therefore usually designed together with speech coding in such a manner that the bits that are the most important for the quality of speech are protected more carefully than less important bits. On a full-rate channel of the GSM system, for instance, the bits produced by the speech encoder are divided into three different categories according to their importance. The most important category is protected in channel coding with both an error-detecting and an error-correcting code; the second most important category is protected only with an error-detecting code; the least important category is not protected at all in channel coding.
Although the speech coding and channel coding are closely connected, there are often considerable differences in their implementation in digital mobile telephone networks. The GSM system may once again be used as an example. Speech encoding and speech decoding are typically carried out by means of software, using a digital signal processor. This applies both to terminal equipment (telephones) and to network elements. Channel coding may also be performed by means of software, but often a separate integrated circuit is designed for this purpose, especially at the network end. Thus, changing of the speech coding method requires often merely a new signal processing program, whereas changing of the channel coding method may require equipment changes.
In addition to the way they are implemented, these two codings, speech coding and channel coding, may differ in their physical locations at the network end of a mobile telephone system. In the GSM system, for example, channel coding in the network is performed in a base station, while speech coding is performed in a separate transcoder unit, which may be remote from the base station, and even if it is located at the base station, it is a completely separate unit. Because of the separate locations, any changes in the transmission rates of the channel coding and speech coding will also entail changes in the connections between the different network elements.
In view of the different ways in which speech and channel coding are performed and their separate locations, it would be clearly more advantageous if the quality of speech could be improved in an existing system merely by changing the speech coding. As the channel coding is, however, usually designed particularly for the speech coding of the existing system, and as the new speech coding method should use exactly the same transmission rate as the original speech coding method of the system, methods for adapting new speech coding methods for existing telecommunications systems have not been disclosed previously.
FIG. 1A and 1B are block diagrams illustrating a transmitter and a receiver of a prior art telecommunications system. In the transmitter shown in FIG. 1A, a speech signal 100 is supplied to a speech encoder 101, which on the basis of the signal generates compressed speech coding bits having a transmission rate of S kbit/s. These speech coding bits are supplied to a channel encoder 102, where error check bits are added to them, which results in a total transmission rate of S+C kbit/s. This bit stream 103 is transmitted over the transmission channel to the receiver shown in FIG. 1B. In the receiver of FIG. 1B, the bit stream 104 received from the transmitter is at first supplied to a channel decoder 105, which decodes the channel encoding and transmits the speech coding bits thus obtained to a speech decoder 106; the transmission rate of the speech coding bits is again S kbit/s. The speech decoder synthesizes a digital speech signal 107. The telecommunications systems of the prior art thus employ only one speech encoding method and a corresponding channel coding method. Such telecommunications systems include, for example, all the commonest digital mobile telephone systems.
The prior art systems also include systems in which two different speech coding methods are used in such a manner that a separate channel coding method corresponds to each speech coding method, and in which the total transmission rate obtained as a result of the speech and channel coding is different in these two methods. An example of such a system is the GSM mobile telephone system, in which full-rate and half-rate traffic channels are specified.
There are also known solutions in which transmitters and receivers according to FIG. 1A and 1B are connected in parallel so that the system that is formed comprises several different speech encoding methods, each of which has a corresponding channel coding method. The speech coding methods used in such a system can operate at different transmission rates, wherefore the channel coding methods corresponding to them are also mutually independent and operate at different transmission rates.

Method and apparatus for speech transmission in a mobile communications system


A system is described allowing a virtual desktop to be booted directly from a desktop image stored in a backup database without requiring content from the desktop image to be copied into the virtual disk of the virtual machine hosting the virtual desktop. The hosting virtual machine contains a synthetic virtual disk acting as a stub disk by redirecting read requests targeted for the synthetic disk from the guest operating system to corresponding locations of the storage where the desktop image is kept.

Virtual desktops are becoming more and more commonplace in today's work environments. The security of having a remotely stored desktop, ability to access the desktop from any location and on various devices, centralized management, the efficient use of hardware resources, among other benefits made possible by virtual desktop infrastructure (VDI) is a large benefit for many organizations. Hence, the concept of using VDI to provide users with virtual desktops in the cloud is appealing to a growing number of enterprises.
In a conventional VDI environment, each user in an enterprise is provisioned a virtual desktop and is allowed to access their virtual desktop over a remote network connection, such as a WAN connection. The virtual desktops are typically hosted on servers that reside in a data center of the enterprise (or a third party service provider), and each host server may execute multiple virtual desktops. Users can utilize a client device to remotely log into their individual virtual desktop and all of the application execution takes place on the remote host server which is linked to the local client device over a network using a remote display protocol, such as remote desktop protocol (RDP), PC-over-IP protocol (PCoIP), virtual network computing (VNC) protocol, or the like. Using the remote desktop protocol, the user can interact with applications of the virtual desktop, which are running on the remote host server, with only the display, keyboard, and mouse information communicated with the local client device. A common implementation of this approach is to host multiple desktop operating system instances on separate virtual machines deployed on a server hardware platform running a hypervisor.
However, successful deployment of VDI in an enterprise poses several challenges. For example, VDI must provide cost-effective dedicated desktops, in which users still have the diversity and personalization they are used to (e.g. installing custom applications and storing a large number of documents), while reducing the cost of storage and computing resources required for handling the user workloads. One challenge in today's systems is that the underlying storage in VDI must be of large capacity and high performance, as it contains all operating system (OS) files, applications, and user data, and must respond quickly to a massive amount of input and output (JO) requests from various virtual desktops running from the storage.
Also, IT needs to be able to continue supporting users with physical devices, co-existing with the virtual desktops. Furthermore, the system should enable fast transition from the physical desktop to the virtual desktop (e.g. for business continuity in case of disaster). Today, migrating existing full physical desktops into the cloud to enable a virtual desktop is a long and complicated process that requires copying the entire contents of each physical desktop into the corresponding virtual disks, which also consumes a lot of storage space. In addition, maintaining synchronization between the virtual desktop and the physical desktop for when the user returns to using the physical desktop is a significant problem. Further, IT needs to be able to provision and update operating systems, applications, and perform other IT tasks in the same way both for physical and for virtual desktops, ideally without having to duplicate the effort.
Meeting these challenges traditionally required expensive high-end storage devices storing full block-level desktop images and extensive IT involvement. The common approach for meeting these requirements is to dedicate a virtual machine per user, with varying solutions for storing the various desktop image components (the operating system, IT-provisioned applications, user-installed applications, user data, and settings). For example, a simple storage solution that is widely used is to have a "full clone" of a virtual machine disk for every virtual desktop. Each full clone contains an entire block-level desktop image. However, this solution wastes a lot of storage, as the entire operating system and all IT- and user-installed applications are duplicated across many virtual machine disks. Some solutions, such as "linked clones," reduce storage needs to some extent by allowing multiple VMs to share a base or "parent" virtual disk that contains the core operating system (OS), while changes of each VM are written to a separate delta disk for each VM. This enables de-duplicating the core OS files, however, user data, installed applications and customized settings are not de-duplicated. Furthermore, with linked clone technology, each virtual delta disk consumes increasingly more storage over time as blocks are being written to the delta disk, which in turn requires either a periodic "refresh" operation that discards all user-installed apps or a resource-intensive garbage collection operation for reclaiming unused blocks.
A more efficient approach is desirable for managing virtual desktop infrastructure in enterprise network environments.

Provisioning virtual desktops with stub virtual disks


Disclosed is an image synthesizer including an image frames memory which memorizes a plurality of image frames which are produced by continuously taking pictures of a subject, an image synthesizer which synthesizes a plurality of image frames to a summation image, an image brightness adjuster which adjusts brightness of the summation image by synthesizing the image frames with the image synthesizer, and a display which displays the summation image which is being synthesized by the image synthesizing means in the image brightness adjusting processing.

1. Field of the Invention
The present invention relates to an image pickup apparatus or an image synthesizing apparatus which synthesizes a plurality of image frames produced by continuously taking images of a subject to produce a synthesized image.
2. Description of Related Art
A conventional image pickup apparatus such as a digital camera forms an optical image of a subject by means of an optical lens, and converts the optical image into an electric signal by means of an image pickup device such as a CMOS image sensor.
As a method for taking images in a dark place, there is known a method in which images of a subject are continuously taken with exposure time having smaller hand jiggle, the images are added while correcting motion of the plurality of images, thereby producing one image (e.g., see U.S. Pat. No. 7,057,645).
In the case of the patent document 1, however, a predetermined number of images are collectively continuously taken previously and then, the images are synthesized into one image. Therefore, a brightness of the synthesized image might be different from a desired by user.

Image synthesizing apparatus and image pickup apparatus with a brightness adjusting processing


A modular faceplate assembly having a faceplate and at least one modular panel received and supported within a frontal opening in the faceplate and releasably secured to the faceplate by concealed latches hingedly connected to the modular panel rearward of the faceplate for flexure between latching and releasing positions relative to keepers carried by the faceplate and resiliently biased to said latching positions. When the latches are in latching positions latch operators carried by the latches form closures for latch operating apertures opening through the frontal surface of the faceplate assembly. Cam surfaces on the latch operators facilitate operation of the latches to release the panel from the faceplate in response to insertion of an operating tool into the latch operating apertures.

This invention relates in general to wire management devices and deals more particularly with an improved modular faceplate assembly for mounting at a termination point in a wiring system to support one or more electrical or electronic devices such as, for example, electrical outlet receptacles and/or telecommunications jacks, to facilitate interface with the wiring system. A faceplate assembly of the type with which the improvement of the present invention is concerned is adapted for mounting on a device box, surface mounted raceway or other structure which comprises a part of a wiring system and generally includes a frame or faceplate for supporting one or more modular inserts or panels which carry discrete electrical or electronic devices. The panel or panels are releasably secured to the faceplate or other supporting structure by substantially concealed latching elements. Each insert or panel member is supported within and provides a substantial closure for at least a part of a frontal opening in the faceplate and cooperates with the faceplate to conceal the latching element or elements which retain it in assembly with the faceplate. The panel member or members may also conceal other fasteners which retain the faceplate on an associated supporting structure. A faceplate assembly of the aforedescribed type is particularly suitable for use in a premises distribution/communication system to provide a universal quick change interface for voice, data and video applications.
Some means must, of course, be provided to release each panel or insert from its associated faceplate to enable access to electrical terminations therebehind. Heretofore, discrete latch operating apertures have been provided in the frontal surfaces of such faceplate assemblies and in the regions of the retaining latch or latches to enable a tool such as a screwdriver, for example, to be inserted into and through each latch operating aperture to operate an associated latch whereby the insert or insert members which comprise the assembly may be removed from the faceplate. In such prior art faceplate assemblies each latch is often located some distance rearward of an associated insert panel so that the manner in which the panels are secured to the faceplate is not immediately evident. One who is not familiar with the latching system may accidentally scratch, mar or otherwise damage the frontal surface of the faceplate assembly in an attempt to pry or otherwise remove a panel from the faceplate. Further, the latch operating openings in the frontal surfaces of such prior art faceplate assemblies are usually readily visible and tend to detract from the otherwise smooth uninterrupted surface appearance of the assemblies. The present invention is concerned with these problems.
Accordingly, it is the general aim of the present invention to provide an improved modular faceplate assembly of the concealed latch type having latching means which is easy to operate and which provides improved latch concealment for better overall appearance.

Modular faceplate assembly having concealed latching means


Vinyl sulfides bearing protected arlyoxy substituents and a process for their preparation are provided. In the process a vinyl sulfide is formed by coupling a ketone compound and a thioester compound with a low valent titanium reagent to form both carbon-carbon bonds in the same step. The vinyl sulfide compounds are useful as intermediates which are convertible into triggerable sulfur-substituted dioxetanes by addition of oxygen to the double bond. The sulfur-substituted dioxetanes additionally are useful for producing chemiluminescence or for further conversion into triggerable alkoxy, alkenyloxy, alkynloxy, aryloxy, aralkyloxy, or acyloxy-substituted dioxetanes. Triggerable dioxetanes are useful for producing chemiluminescence and in detecting activating agents in assays such as immunoassays and nucleic acid hybridization assays.

(1). Field of the Invention
The present invention relates to a novel process for the preparation of stable chemiluminescent 1,2-dioxetane compounds which can be triggered to generate light. Stable, triggerable dioxetanes prepared by the present process are preferably of the formula: ##STR1## The present invention also relates to novel sulfur-substituted alkenes (vinyl sulfides) preferably of the formula: ##STR2## and stable triggerable sulfur-substituted 1,2-dioxetanes preferably of the formula: ##STR3## a process for their preparation and a process for their use as intermediates for producing stable triggerable 1,2-dioxetanes substituted on the dioxetane ring with alkoxy, alkenyloxy, alkynyloxy, aryloxy, aralkyloxy or acyloxy groups.
(2). Description of Related Art
a. Synthesis of Dioxetanes. The preparation of dioxetanes with alkoxy substituents by addition of singlet oxygen to a vinyl ether is well known in the art. Singlet oxygen is typically produced by irradiation of a photosensitizing dye in the presence of oxygen but can also be generated by thermolysis of triphenylphosphite ozonide. Other methods of preparing dioxetanes with alkoxy substituents from vinyl ethers include electron-transfer oxidation with oxygen and triarylaminium cation radical salts (R. Curci, L. Lopez, L. Troisi, S. M. K. Rashid and A. P. Schaap, Tetrahedron Lett. 28, 5319-22 (1987); L. Lopez, L. Troisi and G. Mele, Tetrahedron Lett. 32, 117-20 (1991)), oxidation by Cr(VI) or Mo(VI) oxide diperoxides (R. Curci, L. Lopez, L. Troisi, S. M. K. Rashid and A. P. Schaap, Tetrahedron Lett. 29, 3145-8 (1988)) and oxidation with triethylsilyl hydrotrioxide (G. H. Posner, K. S. Webb, W. M. Nelson, T. Kishimoto and H. H. Seliger, J. Org. Chem., 54, 3252-4 (1989)). A dioxetane was produced in low yield by reaction of a dioxene compound with oxygen which had been passed through an electric discharge, apparently producing a small amount of singlet oxygen in addition to ozone (T.-S. Fang and W.-P. Mei, Tetrahedron Lett. 28, 329-21 (1987)).
All of these methods for the preparation of alkoxy-substituted dioxetanes require the preparation of the precursor vinyl ether. No reaction involving the direct introduction of alkoxy or aryloxy groups on a pre-formed dioxetane ring has been reported to the best of applicant's knowledge. There is thus a need for a general method for the preparation of a variety of alkoxy-substituted dioxetanes from a common intermediate which does not require the preparation of each individual vinyl ether precursor.
b. Sulfur-Substituted Dioxetanes. 1,2-Dioxetanes with one or more sulfur-containing substituents on the dioxetane ring are known. All known examples are unstable, with most decomposing rapidly at room temperature. (W. Adam, L. A. Arias, D. Scheutzow, Tetrahedron Lett., 23(28), 2835-6 (1982); W. Adam, L. A. Encarnacion, Chem. Ber., 115(7), 2592-605 (1982); W. Ando, K. Watanabe, T. Migita, J. Chem. Soc., Chem. Commun. (24), 961-2 (1975); G. Geller, C. S. Foote, D. B. Pechmann, Tetrahedron Lett. 673-6 (1983); R. S. Handley, A. J. Stern, A. P. Schaap, Tetrahedron Lett. 26, 3183-6 (1985)). The most stable sulfur-substituted dioxetanes, derived from 4,5-dialkyl-2,3-dihydrothiophene decompose with a half-life of a few minutes at room temperature (W. Adam, A. Griesbeck, K. Gollnick, K. Knutzen-Mies, J. Org. Chem., 53, 1492-5 (1988); K. Gollnick, K. Knutzen-Mies, J. Org. Chem., 56, 4027-31 (1991)). Two spiroadamantyl-substituted dioxetanes bearing one and two sulfur substituents, respectively, on the dioxetane ring are known. Both have been reported to rapidly and completely decompose on attempted isolation at room temperature (W. Adam, L. A. Encarnacion, Chem. Ber., 115(7), 2592-605 (1982)).
c. Synthesis of Vinyl Sulfides. Vinyl sulfides containing a carbon-carbon double bond and a sulfur substituent directly attached to one of the double bond carbon atoms can be prepared by various methods known to the skilled synthetic chemist. One of the classical methods for preparation of vinyl sulfides involves the reaction of a ketone and mercaptan with TiCl.sub.4 and an amine base (T. Mukaiyama, K. Saigo, Chem. Lett., 479-82, 1973)). vinyl sulfides have been formed by other methods which utilize titanium reagents. Vinyl sulfones are reduced at the sulfur to vinyl sulfides with LiAlH.sub.4 -TiCl.sub.4 (E. Akgun, K. Mahmood, C. A. Mathis, J. Chem. Soc., Chem. Commun, (6), 761-2 (1994)). .alpha.-Halo-sulfoxides undergo elimination and reduction with Zn-TiCl.sub.4 to form vinyl sulfides (V. Retrakul, P. Poochaivatananon, Tetrahedron Lett., 24(5), 531-4 (1983)). In each of these methods, one or both of the C--C bonds is already formed in the starting material. None of the foregoing methods involves the direct formation of the sulfur-substituted carbon-carbon double bond from two separate carbon atoms. No method of which Applicants are aware is known for creating a vinyl sulfide by coupling two carbonyl-containing compounds, one of which is a thioester, to form a double bond with a sulfur-substituent.
d. Chemically Triagerable Dioxetanes. Chemically triggerable adamantyl-stabilized dioxetanes are disclosed in U.S. Pat. No. 4,857,652 and a paper (A. P. Schaap, T. S. Chen, R. S. Handley, R. DeSilva, and B. P. Giri, Tetrahedron Lett., 1155 (1987)). These dioxetanes exhibit thermal half-lives of years but can be triggered to produce efficient chemiluminescence on demand. Benzofuranyl dioxetanes substituted with trialkylsilyl and acetyl-protected phenolic groups which produce weak chemiluminescence have also been reported (W. Adam, R. Fell, M. H. Schulz, Tetrahedron, 49 (11), 2227-38 (1993) ; W. Adam, M. H. Schulz, Chem. Ber., 125, 2455-61 (1992)). Each of these dioxetanes was prepared by dye-sensitized photooxygenation of a vinyl ether (alkene) precursor.
e. Enzymnatically TPriacrrablp Dioxetanes. Enzymatic triggering of adamantyl-stabilized 1,2-dioxetanes are described in U.S. Pat. No. 4,857,652 and a series of papers (A. P. Schaap, R. S. Handley, and B. P. Gini, Tetrahedron Lett., 935 (1987); A. P. Schaap, M. D. Sandison, and R. S. Handley, Tetrahedron Lett., 1159 (1987) and A. P. Schaap, Photochemn. Photobiol., 47S, 50S (1988)). These dioxetanes bear a protected aryloxide substituent which is triggered to decompose with emission of light by the action of an enzyme in an alkaline aqueous buffer to give an aryloxide intermediate dioxetane which decomposes with emission of light at a greatly increased rate. Chemiluminescence is thereby emitted at a much greater intensity than that resulting from slow thermal decomposition of the protected form of the dioxetane. Further examples of enzymatically triggered dioxetanes are disclosed in U.S. Pat. No. 5,068,339 to Schaap, U.S. Pat. Nos. 5,112,960 and 5,220,005 and a PCT application (88 00695) to Bronstein, U.S. Pat. No. 4,952,707 to Edwards, U.S. Pat. No. 5,132,204 to Urdea, U.S. Pat. No. 5,248,618 to Haces and PCT application WO94/10258 to Wang and in a publication (M. Ryan, J. C. Huang, O. H. Griffith, J. F. Keana, J. J. Volwerk, Anal. Biochem., 214(2), 548-56 (1993)). The enzymatically triggerable dioxetanes are now undergoing widespread use as substrates for marker enzymes in numerous applications including immunoassays, gene expression studies, Western blotting, Southern blotting, DNA sequencing and the identification of nucleic acid segments in infectious agents.
New processes for the-preparation of existing and new triggerable dioxetanes. are desirable -to advance the state of the art. Processes which permit the preparation of dioxetane compounds which are difficult or impossible to prepare by known methods would be particularly desirable. The process of the present invention provides such means.

Vinyl sulfide compounds and a process for their preparation


The invention relates to specific binding members for estradiol and materials and methods relating thereto, in particular antibodies or binding domains thereof which have high affinities (low dissociation constants) for estradiol and low cross-reactivity for other steroids. The invention further provides means to make such binding members, assay methods for the detection and/or quantitation of estradiol, and nucleic acid encoding said binding members, which nucleic acid may be used for their production. Preferred binding members include those with CDR regions of the D12 antibody heavy and light chain domains (SEQ ID NO:2 and SEQ ID NO:12 respectively).

Estradiol is one of a number of physiologically important steroid hormones among which minor differences in structure result in profoundly different biological activities [Cook, B. & Beastall, G. (1989). In "Steroid Hormones: a practical approach." Practical Approach Series (Rickwood, D. & Hames, B. D., eds.), Oxford University Press, Oxford. pp. 1-65.]. Measurement of estradiol levels in body fluids is important in clinical practice, for example to follow the menstrual cycle in women, and to monitor compliance and optimal dosing of estradiol administered as part of hormone replacement therapy in women at menopause. High levels of estradiol in men can be diagnostic of estrogen-secreting tumours such as Leydigs cell tumours, liver disease and hyperthyroidism.
Physiological concentrations of estradiol at particular stages in the menstrual cycle vary between individuals, but typically rise from around 0.18 nM at the lowest point to a peak of 1.5 nM prior to ovulation. These low levels of hormone make quantitative determination of estradiol difficult, placing a premium on the sensitivity and selectivity of assays. Antibody based detection methods are commonly used in diagnostic assays, but in the case of estradiol the antibody itself has proved to be the limiting factor.
Since steroids are not themselves immunogenic, they have to be coupled to a larger molecule in order to elicit an immune response in animals. However, it has been found that the antibodies raised in this way are often unable to recognise important structural differences in that part of the steroid attached to the carrier. The importance of specificity is not only in ensuring that the right hormone is measured, but also in discriminating between the biologically active form and metabolites inactivated by the liver [Cook, B. & Beastall, G. (1989)]. The inability to discriminate between closely related structures is manifested by the antibody having similar affinity for different steroids substituted at particular positions, and is often referred to as a `blind-spot` [Aravelo, J. H., Stura, E. A., Taussig, M. J. & Wilson, I. A. (1993). J. Mol. Biol. 231, 103-118].
Useful polyclonal antisera have nevertheless been obtained [Cook, B. & Beastall, G. (1989)], though affinity and cross-reactivity of sera is highly variable between animals, creating problems in standardizing assays, and many animals need be immunised before an antiserum with the required properties is obtained, limiting the supply of serum. All currently available diagnostic kits use polyclonal, antisera (e.g. Abbott, Amersham etc.) Consequently, many attempts have been made to generate monoclonal antibodies. Although some have had high affinities (typically 50 nM or better), none has had the requisite specificity. The well-characterised mouse monoclonal antibody DB3 [Aravelo, J. H. et al.] binds to progesterone with a dissociation constant of approximately 1 nM. This antibody provides an excellent example of the properties of an antibody raised against a steroid coupled to a protein; although DB3 is specific to the portion of the steroid furthest from the carrier, it shows very little specificity at the end of the steroid that was conjugated to the protein and will bind equally well when even large substituents are present at this site.
Phage display has previously been used to isolate a progesterone-binding antibody from a non immunised murine repertoire [Gram, H., Marconi, L., Barbas, C. F., Collet, T. A., Lerner, R. A. & Kang, A. S. (1992). Proc. Natl. Acad. Sci. (USA) 89, 3576-3580.]. The dissociation constant of the resulting antibody was only micromolar, and cross-reactivity to other steroids was not explored.

Specific binding members for estradiol; materials and methods


A new syringe design is provided with a safety feature that prevents inadvertent or otherwise unintended release of any contents within the syringe. This safety feature is accomplished by way of an automatic (passive) plunger locking mechanism. The new syringe design also providing for automatic (passive) disengagement of the automatic plunger locking mechanism so as to not inhibit the operating use and function of a syringe.

The invention here disclosed relates primarily to syringes and in particular those typically used for medical purposes that allow unintended dispensement of fluid substances from the syringes main staging chamber.
The main purpose of the improvement here disclosed is to provide a reliable, safe, simple and low cost method of passively and automatically locking a syringe from unintended dispensement of its contents when and only when not engaged for its ultimate purpose and allowing for automatic unlocking whenever and however many times a syringe is engaged for its ultimate purpose upon at least two points of contact.
Various attempts to create syringe locks have been made such as the locking mechanism disclosed by Watts (20070049872-A1 US). These attempts allow effective locking control by way of the deliberative action of the user to engage the locking mechanism. Further, the locking mechanism is disclosed as a separate part which will lead to inconsistent use where safety is a factor.
The invention here disclosed provides passive locking and unlocking control of the syringe plunger in its preferred embodiments. Further, the preferred embodiments accomplish the said passive locking control within a simple low cost and easy to manufacture and implement structure.
Passive locking control is necessary to ensure maximum effective use, application safety enhancement and reduced waste including that of sometimes expensive medical supplies.


A headset of the present invention includes: a housing 10 worn on one auricle of a wearer; an arm 41 having a predetermined length, one end side of which is accommodated in the housing and the other end side of which is pulled out of a hole 13a of the housing to the outside, accommodated in the housing by adjusting the length pulled out of the hole 13a of the housing to the outside; and a microphone attached to the arm 41. When the headset is being used, the end of the arm 41 comes close to the wearer's mouth by pulling the arm 41 out of the housing 10. When the microphone need not be used, the arm 41 is stored in the housing 10 so as not to protrude from the housing 10.

As headsets which are worn on users' heads, conventionally there have been various forms of headsets put into practical use. For example, there is a headset having the shape shown in FIG. 1. This headset shown in FIG. 1 is constructed such that a driver unit which outputs a sound according to a provided sound signal is incorporated in both a left housing 1 and a right housing 2, and both the housings 1 and 2 are connected by a band 3 to form headphones. When a user puts on this headset, the housings 1 and 2 are each worn on the user's left and right auricles by hooking auricle holding portions 3a and 3b of the band 3, which are in the vicinity of portions connected to the housings 1 and 2, to be attached to his/her upper auricles.
Hereupon, an arm 4 is attached to the outside of the left housing 1 by means of a supporting member 5 capable of turning freely, and a microphone 6 is attached to the end of the arm 4. With this construction, when this headset is worn and connected to communication equipment such as a mobile-phone unit, sound received by the communication equipment is output from the left and right housings 1 and 2 and sound picked up by the microphone 6 is transmitted from the communication equipment, so that audio transmission and the like can be executed.
Then, the above conventional headset has a construction in which a microphone is added to headphones, and can also be used as headphones. That is, without using the microphone the headset can be used as headphones equipped with speakers. However, there has been a problem in which while the headset is being used as headphones, the microphone is unnecessary and disturbing to the user. In the case of the headset shown in FIG. 1, for example, the arm 4 to which the microphone 6 is attached can freely turn by means of the supporting member 5. Therefore, when the microphone is not being used, it is likely that the arm 4 to which the microphone 6 is attached will be turned and lifted upward as shown in FIG. 2, for example.
Although the microphone will be away from the wearer's mouth by the lift of the microphone, the microphone still remains extending from the housing 1 and stays in a position unpleasant for the wearer, which is a problem. In order to solve this problem, it is assumed that, for example, a headset has a construction in which an arm, to which a microphone is attached, can be detachable from a housing; however, in that case detaching and attaching the detachable arm takes time and effort, and also requires the user's care not to lose the microphone detached from the housing, so that there occurs a problem in which time and effort is required in handling.


An electronic device (100) includes a first processor (802) and a second processor (804) coupled to the first processor. The first processor (802) is to receive image data from a first imaging camera (114, 116) and to determine two-dimensional (2D) spatial feature data representing one or more 2D spatial features identified from the image data. The second processor (804) is to determine three-dimensional (3D) spatial feature data representing one or more 3D spatial features identified based on the 2D spatial feature data. Further, the first processor (802) can initiate detection of one or more 2D spatial features from a portion of an image frame prior to receiving the entire image frame.

Machine vision techniques, such as simultaneous localization and mapping (SLAM), augmented reality (AR), and virtual reality (VR), often rely on the identification of objects within the local environment of a device through the analysis of imagery of the local environment captured by the device. This analysis conventionally is performed by a graphics processing unit (GPU) on a frame-by-frame basis, which can introduce a significant lag between image capture and feature identification, which in turn can severely impact the perceived responsiveness of the device to changes in the position or orientation of the device or to changes in the local environment.

System for 2D/3D spatial feature processing


An improved method and apparatus for rendering curved surfaces in a graphics system. The appearance of a curved surface is created by varying color shades across an object. The graphics systems represents each primary color with fewer than eight bits. The present invention maintains smooth transaction between color shades despite using fewer than eight bits to represent color. An eight bit color shade value is truncated, with the most significant bits being saved and used as a color value. The least significant bits that are truncated are used to determine which of the adjacent color values to use to render pixels. Thus, if five bits are saved and used to represent a color, the three least significant truncated bits are used to determine the appropriate mix of the closest five bit shades. The three truncated bits are used to select an entry from a ramp table and a control signal from a look-up table selects a bit from the selected ramp table entry. The selected bit is used to determine which of the closest five bit shades to use for rendering a pixel. The invention may be implemented in software.

A. Field of the Invention
The present invention relates generally to a graphic system for a personal computer. More particularly, the present invention relates to rendering polygons on a computer screen. Still more particularly, the present invention relates to a technique for dithering polygons to create curved surfaces.
B. Background of the Invention
Before the availability of the personal computer (PC), computer graphics packages were expensive tools primarily reserved for industrial applications. Early microcomputers were only capable of rendering simple line drawings with a low screen resolution (256.times.256, for example). As microcomputers evolved, higher resolution color displays became available, and software applications routinely provided data output in a graphical format. The graphics techniques used were unstructured, with objects defined in terms of absolute coordinates using straight lines. Subsequently, graphics "primitives" were developed, enabling circles, ellipses, rectangles and polygons to be drawn with single software instructions. The use of primitives for drawing shapes increased the speed at which the images can be rendered.
The availability of computer graphics has generated a demand for higher resolutions and three dimensional (3-D) rendering capabilities. Computer animation and games, in particular, have spawned a revolution in computer graphics capabilities. A 3-D image can be represented in a computer system as a collection of graphical objects, such as polygons, lines, and points. A set of vertex points defines a polygon. Associated with each point are certain parameters, such as shading, texturing, color, and the like. Identification of other non-vertex points within the polygon typically is done through the use of linear interpolation. Once interpolated, the polygon can be rendered on a computer monitor by successive scanning of successive rows of the polygon.
Demand for higher performance computer graphics has led to graphics systems capable of much greater speed, resolution, and quality than graphics systems of only a few years ago. Traditionally, graphic systems employed an "8-8-8" standard, and many still do, in which eight bits are used to represent each of the three primary colors red, green, and blue. That is, eight bits are used for red, eight bits for green, and eight bits for blue. In an 8-8-8 system, therefore, twenty-four bits are needed to fully represent the color of a single pixel. Using eight bits for each color allows 256 different shades of each of the three primary colors. To increase the resolution of the color system, each color is represented with an "8.16" interpolator value in which sixteen bits of FRACtional color are included with each eight bit integer shade. With such resolution 8-8-8 graphics systems typically produce very high quality color images.
The down side of an 8-8-8 graphics system is that twenty-four bits are necessary to represent the integer color shade of a single pixel. The number of pixels on a typical computer screen today commonly approaches 1,000,000. With twenty-four bits of color and other parameters associated with each pixel, voluminous bits of information necessarily must be processed, thereby creating a demand for higher memory capacity and faster processing. Semiconductor part manufacturers have responded by developing higher performance graphics hardware. In many graphics applications, however, there is a demand for even higher performance from computer hardware.
Designers of graphics systems, therefore, have developed various techniques to achieve greater performance given the performance limitations of the supporting graphics hardware. For example, other graphics standards exist besides the 8-8-8 standard. One such standard is the "5-6-5" system in which five bits are used to represent shades of red, six bits are used to represent green, and five bits are used for blue. As shown in FIG. 1, in an eight bit system, eight bits are used to represent the color red. In a 5-6-5 system, however, only the upper or most significant five bits, i.e., bits R.sub.3 -R.sub.7, are used for red. The least significant three bits, R.sub.0 -R.sub.2, are simply truncated and not used. For the color green the upper six bits are used, i.e., G.sub.2 -G.sub.7, with bits G.sub.0 and G.sub.1 truncated. An extra bit is used for the color green because most human eyes are more sensitive to the color green and thus, additional resolution or precision for the color green is needed. The sixteen color bits that are used (five each for red and blue and six for green) are packed together for storage and/or processing. Other standards such as the "5-5-5" and "3-3-2" standards are also used.
Using a 5-6-5 system, instead of 8-8-8, advantageously allows the integer portions of the color representation to be stored in sixteen bits (i.e., two bytes) of memory instead of twenty-four bits (three bytes) as necessary for an 8-8-8 system. Moreover, significantly less memory is necessary to store computer images with a 5-6-5 system and more graphics information can be processed faster using existing hardware devices.
As one of ordinary skill in the art will recognize, representing a color shade with eight bits allows 2.sup.8 or 256 different integer shades of that color. Representing a color shade with only five bits, however, allows for just 2.sup.5 or 32 shades of that color and using six bits allows for 64 (26) color shades. Referring now to FIG. 2, a comparison between an eight bit color standard and a five bit standard emphasizes the lower precision of a five bit system. Because the least significant three bits (bits 0-2) are truncated from an eight bit shade to create the five bit shade, eight bit color shades 0000 0000 through 0000 0111 (decimal 0-7) are represented by 00000 in the five bit system. In other words, with only five bits, the five bit representation cannot distinguish between eight bit shades 0-7 (decimal). Similarly, eight bit color shades 0000 1000 through 0000 1111 (decimal 8-15) are represented by 00001 in the five bit standard. This comparison illustrates that for every increment (or decrement) in a five bit color shade, eight eight-bit color shades are skipped. A similar comparison could be made for the six bit representation for the color green highlighting that because only the least significant two bits are truncated, there are four eight-bit green color shades for every six bit shade.
Polygons typically are drawn one row of pixels at a time, rendering pixels individually from one edge of the polygon to the other. To give the appearance of a curved surface to create 3-D images, a graphics system applies varying shades of color to the pixels rendered. For example, a polygon might be rendered with a dull shade of red on the left side of the polygon and bright red on the right side with a transition between the dull and bright shades for the intervening pixels. In an 8-8-8 system, with 256 integer shades each for red, green, and blue and sixteen bits of FRACtional shades, there is sufficient color precision to make the transitions of color across a polygon appear smooth to the human eye.
The attendant lower precision in a 5-6-5 graphics system does not permit color transitions across a polygon that are as smooth as in 8-8-8 systems. This problem is called "banding." Banding is caused by color transitions across polygons that include more pronounced, larger increments in shades of color because there are fewer different shades possible than in an 8-8-8 system. The boundary lines between different shades is more perceptible to the eye. A polygon rendered using the 5-6-5 color standard appears as bands of different shades of color on the computer screen rather than smooth transitions. Transitions in color shades in a 5-6-5 system between bands is noticeable despite the difference between adjacent bands of only a single shade of color.
To minimize the undesirable appearance of an image suffering from banding, the technique of dithering is used. Dithering takes advantage of the insufficient resolving ability of the human eye to distinguish individual pixels from a large group of pixels on a computer screen. Dithering allows the appearance of a color band to be altered to make the color shade of the band appear closer to the shade of an adjacent band, thereby smoothing the sharp transitions between the two bands. Graphics systems implementing known dithering techniques increment by one binary value randomly selected pixels in a band. Thus, some pixels in the dithered band are rendered using one shade of color, while other randomly selected pixels in the band are rendered using the color shade of the pixels in the adjacent band. The appearance of the dithered band thus appears closer to the shade of the adjacent band and the transition in color shades between the two bands is less noticeable to the eye. For the colors red and blue in a 5-6-5 system, incrementing a color shade by one shade level is equivalent to an increment of eight color shades in an eight bit system as demonstrated in FIG. 2. For the color green, a unitary increment equates to an increment of four shades of green in an eight bit system.
Although images using the dithering technique appear to lose the undesirable sharp edges between color bands, the result is still less than completely satisfactory because the dithered image is not an accurate rendition of the desired color transitions across the polygon. Because pixels are rendered randomly using one of two shades of color, the appearance to the eye of the band changes, but the resulting appearance is not necessarily the desired shade. Referring to FIG. 2, for example, if the desired eight bit red color shade in a particular region of a polygon is 0000 0010, commonly known dithering techniques will randomly render the pixels in that region with five bit shades 00000 and 00001. If, however, eight bit shade 0000 0111 were desired, systems implementing dithering will also randomly render the same group of pixels with five bit shades 00000 and 00001. The appearance to the eye will be the same because the same five bit shades (00000 and 00001) would be used in random fashion in both instances.
Thus, it would be desirable to provide a computer graphics system that solves the banding problem associated with graphics systems that represent color with fewer than eight bits of precision. In particular, it would be desirable to provide a graphics system in which fewer than eight bits are used to represent shades of color that can achieve the color precision of eight bit systems. Despite the advantages of such a system, to date, no such system has been developed.

Software-based dithering method and apparatus using ramp probability logic


A lightweight insulated electric wire and an automobile wire harness using the same insulated electric wire where the insulated electric wire has a conductor portion including one or more first wires and one or more second wires, which are stranded together. The first wires are constituted by metal wires made from at least one type of metal selected from copper, copper alloy, aluminum and aluminum alloy. The second wires are constituted by metal wires different from the first wires and have a relative permeability of 4.0 or less.

In general, an automobile is equipped with a wire harness (internal wirings) within the vehicle and the wire harness is used for feeding electricity to electrical equipments within the vehicle, communication and sensing, etc. Such wire harness is generally constituted of electric wires, protective members and terminals such as connectors which are mounted to the end portions of the electric wires. Conventionally, metal wires constituted mainly of copper are employed as the conductors of the electric wires.
In recent years, weight reduction of vehicular components has been advanced due to demands for fuel consumption reduction and a wire harness is no exception. Also, because of the necessity of resources saving and recycles, there is a need for reduction of the amount of copper used for electric wires.
There are two important characteristics required for electric wires. One of them is the electrical conductivity and the other is the tensile strength. Copper, which is often used for the conductors of electric wires of the aforementioned wire harness, is a metal material with a very low electrical resistance. Therefore, the electric wires which have the conductors made of copper can offer sufficient conductivities even when they have relatively small wire diameters. However, in order to maintain a tensile strength required for electric wires, the wire diameters must be made large to some degree. Consequently, there is the necessity of reducing the amount of copper used for electric wires while maintaining the tensile strength.
On the other hand, there are electric-wire conductors made of stainless steel wires with a copper layer on their outer circumferences (refer to, for example, Patent Document 1 and 2). Further, as electric-wire conductors consisting of different types of metal wires stranded together, there are stranded wires consisting of stainless steel wires and copper wires (refer to, for example, Patent Documents 3 and 4).
Patent Document 1: JP-A No. 1-283707
Patent Document 2: JP-B No. 7-31939
Patent Document 3: JP-B No. 63-23015
Patent Document 4: JP-A No. 1-225006

Covered wire and automobile-use wire harness


The present invention is a method and apparatus to reduce latency in accessing a memory from a bus. The apparatus comprises a pre-fetcher and a cache controller. The pre-fetcher pre-fetches a plurality of data from the memory to a cache queue in response to a request. The cache controller is coupled to the cache queue and the pre-fetcher to deliver the pre-fetched data from the cache queue to the bus in a pipeline chain independently of the memory.

1. Field of the Invention
This invention relates to microprocessors. In particular, the invention relates to reducing latency in memory accesses.
2. Description of Related Art
Highly demanding applications such as multimedia and graphics have created a bottleneck in microprocessor systems due to their high bandwidth requirements between the processing devices and the system memory. To provide efficient usage of the system memory, fast peripheral buses have been developed to allow peripheral devices to access the system memory efficiently.
Traditionally, all bus accesses to the system memory are checked against the processor's cache to get the most updated data. This checking on the bus is referred to as bus snooping. The disadvantages of the bus snooping include long initial latencies to access the system memory. Accesses that are initiated on the bus, therefore, still suffer long latencies, especially for read accesses.
Therefore there is a need in the technology to provide a simple and efficient method to reduce latencies for bus accesses to system memory.

Reducing memory access latencies from a bus using pre-fetching and caching


A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be addressed with common addressing signals. The combination volatile and nonvolatile memory integrated circuit further has a memory control circuit in communication with external circuitry to receive address, command, and data signals. The memory control circuit interprets the address, command, and data signals, and for transfer to the volatile memory array and the nonvolatile memory arrays for reading, writing, programming, and erasing the volatile and nonvolatile memory arrays. The volatile memory array is may be a SRAM, a pseudo SRAM, or a DRAM. Any of the nonvolatile memory arrays maybe masked programmed ROM arrays, NAND configured flash memory NAND configured EEPROM.

1. Related Patent Applications
"A Novel Monolithic, Combination Nonvolatile Memory Allowing Byte, Page a Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout ", U.S. patent application Ser. No. 10/223,208, filed Aug. 19, 2002, assigned to the same assignee as the present invention, and herein incorporated by reference.
"A Novel Monolithic, Combination Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout", U.S. patent application Ser. No. 10/351,180, filed Jan. 24, 2003, assigned to the same assignee as the present invention, and herein incorporated by reference.
"A Combination Nonvolatile Memory Using Unified technology with Byte, Page and Block Write and Simultaneous Read and Write Operations", U.S. patent application Ser. No. 10/351,179, filed Jan. 24, 2003, assigned to the same assignee as the present invention, and herein incorporated by reference.
"A Novel Combination Nonvolatile Integrated Memory System Using a Universal Technology Most Suitable for High-Density, High-Flexibility And High-Security Sim-Card, Smart-Card And E-Passport Applications", U.S. patent application Ser. No. 11/025,822, filed Dec. 24, 2004, assigned to the same assignee as the present invention, and herein incorporated by reference.
2. Field of the Invention
This invention relates generally to integrated circuit memory. More particularly this invention relates to combinations of volatile and nonvolatile memory incorporated with an integrated circuit structure. Even more particularly this invention relates to combinations of static random access memory (SRAM), NAND flash electrically erasable programmable read only memory (flash memory), and NAND configured electrically erasable programmable read only memory (EEPROM) on one substrate for incorporation with a system-on-a-chip structure (SOC).
3. Description of Related Art
Volatile memory, as is well known in the art, retains data temporarily such that that any interruption of the power supply voltage source causes a loss of the data. The static random access memory (SRAM) is well known example of a volatile memory and consists of a bistable transistor flip-flop or latching circuit. Referring to FIGS. 1a and 1b, the inverters I1 5 and I2 10 are coupled such that the output of the inverter I1 5 is connected to the input of the inverter I2 10 and the output of the inverters I2 10 is connected to the input of the inverter I1 5 to form the bistable latch. The access transistor Ma1 15 has a first source/drain terminal connected to the input of the inverter I1 5 and the output of the inverter I2 10 and a second source/drain terminal connected to the bit line BL 25. The access transistor Ma2 20 has a first source/drain terminal connected to the input of the inverter I2 10 and the output of the inverter I1 5 and a second source/drain terminal connected to the bit line BL 30. The gates of the access transistors Ma1 15 and Ma2 20 are connected to the word line WL 35 to receive the activation signals for accessing the memory cell.
In operation, the bit lines BL 25 and BL 30 are precharged respectively to the data to be written or read from the memory cell. The word Line WL 35 is set to a voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20 and the digital signal representative of the binary data to be written to or read from the memory cell is transferred to or from the memory cell.
The inverter I1 5 consists of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 configured as the well known CMOS inverter. Similarly the inverter I2 10 consists of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 also configured a CMOS inverter. The gates of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the common drain connection of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 and the gates of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 are connected to the common drain connection of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7. This forms the cross-connection to create the bistable flip-flop. The sources of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the ground reference voltage source and the sources of the p-type MOS transistors Mp1 7 and Mp2 11 are connected to the power supply voltage source VDD.
An alternative to the SRAM is a pseudo-static random access memory (PSRAM). The PSRAM is as is known in the art is formed of a single transistor gating charge representing the digital data to and from a capacitor. The structure is essentially that of a dynamic random access memory with the controls for refresh and timing being internally generated.
The alternative to the volatile memory is the nonvolatile read only memory (ROM). The cell structure and application of the nonvolatile ROM is well known in the art. The nonvolatile ROM has four classifications the masked Programmable Read Only Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Erasable and Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable and Programmable Read Only Memory (Flash).
A masked ROM cell consists of a single transistor. The masked ROM cells are arranged in rows and columns. The gate of each ROM cell is connected to a word line, the drain is connected to a bit line and the source is connected to a source line. The programming or reprogramming of a ROM has to be performed during the integrated circuit fabrication through costly mask changes and a slow throughput of generally approximately one month. In a ROM array configuration, the ROM cells in each column are connected to a common bit line in parallel. Therefore, ROM read access speed is fast. A ROM cell uses a single polycrystalline silicon process on a P-type substrate. The mask programming of the ROM is performed using a post-polycrystalline silicon Boron implant that penetrates through the cell's polycrystalline silicon gate to channel to adjust the threshold voltage VT of the ROM cell.
The cell structure and application of the floating gate nonvolatile memories is well known in the art. The floating gate nonvolatile memory has three classifications the Electrically Programmable Read Only Memory (EPROM), Erasable and Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable and Programmable Read Only Memory (Flash). The EPROM is programmed by electrically forcing charge to the floating gate. Ultra-violet light is employed to eliminate (erase) the electrical charges of the programming from the floating gate of the EPROM. During EPROM program operation, in addition to a low-voltage power supply (VDD), an external high-voltage programming power supply (VPP) of about 12V is used. With a sealed package, UV-light cannot reach floating-gate, thus the erase operation is blocked and the EPROM is considered a One Time Programmable (OTP) EPROM. If the sealed OTP is changed to sealed Flash, then both erase and program operations can be performed electrically and repeatedly in system without the overheads of UV-light exposure and the external VPP programmer due to Flash's on-chip charge pump that can generate high voltage internally.
The sealed Flash is now able to be programmed and erased number times by using the external high-voltage power supplies to eliminate the on-chip charge pumps and state-machine without UV-light exposure to achieve numerous program and erase cycles. In this method, the die size can be drastically reduced for cost reduction. The prior art of the EEPROM and the Flash memories are structurally different at the individual cell as well as in technologies, array organizations and write schemes and conditions. In the prior art, 1-transistor NOR-type Flash, the drains of the cells within a block are connected in parallel to bit lines in cell array to achieve faster read speed. The erase block size is large ranging from 8 KB (64 Kb) to 64 KB (512 Kb) due to the limitation of erase operating voltage condition. The erase voltages have the memory cell's gate set to a voltage of approximately −10V and memory cell's P-Well set to approximately +10V. Having to set the P-Well to approximately +10V forces a requirement that the size of the sub-array or block of memory to be erased to be large to minimize the impact of the size constraints of a P-Well. Due to this operating voltage limitation, currently there is no page erase in unit of single word line size offered with acceptable endurance cycles of more than 100K in market. In the prior art, 1-transistor, NAND-type Flash memory, the drains and sources of cells are connected in series with a disadvantage of slower read speed but an advantage of most compact cell array. Like 1-transistor, NOR Flash, the cells are formed on P-well within deep N-well on top of P-substrate. The erase operation is performed by coupling the gate of the memory cell to the ground reference voltage (0V) and coupling the P-Well to a voltage source of approximately +20V. Having to apply the power supply to P-Well for each memory cell to be erased forces the erase size to be relatively large. The Erase size of the NOR flash memory cannot be performed in a unit of single word line. In prior art, typical 2-transistor EEPROM cell has cell scalability issue and stays at 0.25 μm.
The three nonvolatile memory technologies (EEPROM, NOR-type and NAND-type flash memory) of prior art are process incompatible and were never intended to be manufactured on a single integrated circuit chip. The EEPROM, NOR-type and NAND-type flash memory have the charge transferred to the floating gate for programming by either a channel hot injection (CHE) of the charge or by Fowler-Nordheim Tunneling (FN) through a tunneling oxide. The erasure of the EEPROM and Flash memory is generally by a Fowler-Nordheim Tunneling through the tunneling oxide.
Presently, the key primary applications nonvolatile memory systems and technologies are smart-cards. A smart card is a tiny secure computer processor embedded within a credit card-sized card. Smart cards presently are designed to comply with ISO/IEC 7816, 14443, and 15693 series of standards that define the physical shape of the smart card, the positions and shapes of its electrical connectors (if any), the communications protocols and power voltages to be applied to those connectors, the functionality, and the format of the commands sent to the card and the response returned by the card. Some smart cards may have physical connectors and other structures may have no external connections and communicate by way of radio frequency identification (RFID). Further, the compact nature of the smart card leads to the desirability for the processor, memory function, and support functions to be placed on a single chip.
The smart card is employed in such as applications Subscriber Identity Module (SIM-card) and Electronic Passport (e-passport to store personalized biometric data such as DNA, finger-print, iris and facial picture), to store data of multiple applications and Biometric Information Authentication System (BIAS) programs and to store small data such as telephone numbers and short email messages in same chip. Historically, the permanent program memory such as Basic Input/Output System (BIOS) and applications for the microprocessor was formed of classic mask programmable read only memory (ROM), and later as EPROM. Modifications to the program memory required physically changing the memory.
As the need to update the programs of the microprocessor and applications in system and allow for more than one time became more important, NOR-type flash memory was used. As the demand for serially downloading the audio and video slow-speed data, the high-density NAND-type flash was commonly used for cost reduction. But for those requiring byte-alterable small data memory, EEPROM was replacing flash memory. These three technologies were developed to provide in-system rewriteability. However, processes of EEPROM, NOR-type flash, NAND-type flash memories are not fully compatible in the present technology and are difficult to integrate on the same integrated circuit chip.
As the applications for microprocessors and microcontrollers are becoming more pervasive, the need for storage that is permanent and will not fail or disappear when power is removed is required. In most applications, the program is not modified often. However, the application data is changed relatively frequently. The program memory can be classified as configuration, traceablity, boot program, or main program and application programs. The application data includes information from any external input to the system, e.g., operational, instrument, recorder, or sensor data that is required for historical purposes or to maintain continuity of operation after power down or power loss. Data memory is typically frequently altered over the lifetime of the application, thus demand for much higher program/erase (P/E) cycles of more than 500K.
Recently, there are more and more applications that require addition of more security functions in smart card functions such as e-passport and SIM-card. Most of the security schemes are mandatory asking to store personalized biometric data such as DNA, iris, facial and finger prints. Traditionally, the small NAND-flash cell was not used in low-density card technology, thus the large NOR-type flash cell or the larger EEPROM cell were employed instead to store such biometric data. The effective cell size of 1-transistor NAND is around 4λ square, while 1-transistor NOR-type Flash is around 10λ square and 2-transistor EEPROM cell is about 80λ square. Please, note that λ is a unit of the minimum feature size. That means λ of a 0.13 μm process is 0.13 μm. Obviously, using the big 1-transisitor NOR Flash and the bigger EEPROM cell to store personalized biometric data is wasteful of space. Particularly, in smart card technology, the final die size of a smart card system-on-a-chip that contains all Flash, EEPROM, SRAM, CPU, and Cryptographic processor has to be made within 25 mm square to avoid die cracking. A system-on-a-chip (SOC) integrates all components of a computer system into a single chip. The chip contains an embedded computer processor, program memory, application data memory, and appropriate input/output function. In applications such as cellular telephones and wireless personal digital assistants, a SOC contains digital, analog, mixed-signal, and radio-frequency functions within a single integrated circuit chip
With higher and higher security required for smart card applications, the pressure of more and more personalized data is strongly required in a tiny die area of card. For example, storing ten finger prints is more preferable than to store just one thumbprint from security viewpoint. Having facial picture data from more angles is superior to the data from just one angle. Storing whole finger prints, iris and facial pictures or even DNA in one chip is better than to store part of it from security perspective.
The cells size of the EEPROM and NOR-type Flash memories no longer make these memories a cost effective solution to store personalized biometric data. The smallest cell size of 1-transistor NAND-type flash as noted above is 4λ square and is preferably used for personalized data storage memory.
High-level language software such as Java card system from Sun Microsystems, Inc., Santa Clara, Calif. 95054 provide easy and fast development software processes for creating and integrating software for multiple application down-loadable programs. Therefore, a flexible, easily partitioned small, non-uniform block size NOR-type flash system for multiple function programs is desirable in smart card applications.
The traditional large cell size of EEPROM technology is essentially non-scalable below 0.25 μm and thus it is not suitable for storing memory density higher than 1 Mb (128 KB). The trend is to use low-cost flash technology to replace traditional EEPROM but still retain the features of byte-alterable scheme and high PIE cycles of more than 500K.
The number of times that a nonvolatile memory must be altered determines the endurance requirement of the device. Nonvolatility requires the device to retain data without power applied for the lifetime of the application. The lifetime of the application determines the data retention requirement of the device. Both of the reliability requirements of endurance and data retention have associated failure rates, which must be minimized. Since NOR-type flash memories is employed as the program and application memory, it has the less amount of reprogramming and erasing, therefore, it must have the longest data retention and require the medium endurance (approximately 100,000 program/erase cycles). Conversely, the EEPROM, employed as data memory, must be able to be modified repeatedly and therefore must have higher endurance (more than 1 million program and erase cycles). The NAND-type flash nonvolatile memory preferably used to store personalized data. It does not require too many updates and endurance (approximately 10K program/erase less cycles depending on the applications).
U.S. Pat. Nos. 6,801,458 and 6,370,081 (Sakui, et al.) provide a memory cell array that has a unit memory circuit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data. Sakui, et al. provides essentially 3-transistor EEPROM cell based on the structure of NAND cell. Each block of the EEPROM cells are grouped together in the individual wells such that the bulk of each memory cell of the block is commonly connected.

Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications