Devices, systems and methods for automatically positioning a syringe in a target orientation suitable for withdrawing medication from a container, and for filling the syringe with the medication. The device comprises a syringe conveyor, which is configured to receive the syringe in an initial orientation, and to bring the syringe to a target orientation by being translated and rotated while holding the syringe in a steady orientation relative to the syringe conveyor. The device further comprises a supporting module, configured to support the syringe conveyor while allowing a translation and a rotation thereof. The device comprises a syringe holder configured to hold the syringe, and a gripper coupled to the syringe holder. The gripper is configured to engage the plunger and to enable the automatic displacement.

Automatically filling syringes has many known advantages in the art. For example, US patent application 2009/0198208 to Straysky and Einy discloses a dosage dispenser intended to provide a solution for measuring and dilution of liquid medications and issuing marked and ready for use. The dosage dispenser device carries out actions required for the preparation of a required dose of medication, including identifying ampoules, breaking them, filling a syringe, diluting the medication in a solution, marking the syringe, disposing of waste and documenting the process, all at the patient bedside. The dosage dispenser is aimed at reducing the number of errors in the dosage, which is a problem, menacing medical services throughout the world. The problem is made acute by considerable pressure on the medical teams while carrying out many and complex procedures under pressure in a situation of uncertainty and with variable data.

Devices, systems and methods for filling a syringe with a medication


A mobile transport platform for the handling of aeronautical parts with a frame has an array of telescopic actuators vertically arranged in rows and columns, each telescopic actuator is coupled by one end to the frame, and has a coupled head (2c) at its opposite end; a control system connected to each telescopic actuator for individually controlling the actuation of each telescopic actuator so that the telescopic actuator can adapt a position between that of maximum extension in which the head and at least part of the shaft of the telescopic actuator project from the plane of the load surface, and that of maximum retraction in which at least the shaft of the telescopic actuator does not project from the plane of the load surface.

I. Field of Invention
This invention relates to the field of manufacturing technologies for aeronautical parts and particularly the sector of transportation tools for transporting such parts between manufacturing stations.
II. Prior Art of the Invention
In the manufacture of aeronautical parts, the handling of each of the parts during its manufacturing stages is currently very varied and depends on the specific process of manufacture being used. Among such parts to be found are large size parts such as wings, stabilizers, fuselage panels, rudders, etc., and parts thereof, such as their coverings. In order to handle these parts and their transportation between the various manufacturing stations which they have to pass through, there exists a wide range of tools, trolleys, stocks, etc., for being able to handle the parts depending on the state or phase of manufacture that the parts are to be found in at any moment.
Nowadays, carbon fibre based materials are more and more prevalent than aluminium for aeronautical coverings. Such coverings are typically manufactured as follows.
First, the covering is taped to a tool generally made of Invar. The taping is a process consisting of locating layers of reinforced composite material in the form of strips on a mold in different directions in order to obtain the desired properties. An example of a composite material widely used in the aeronautical industry is preimpregnate, a mixture of fibrous reinforcement and a polymer matrix used for manufacturing composite materials in such a way that it can be stored for later use. In this process, the strips are not placed randomly; instead, they are generally laid or deposited in certain directions, specifically, at 0°, 90°, 45° and −45°. The number of layers (thickness) and the depositing of the strips in certain directions or others is determined according to the nature and magnitude of the stresses which the part is going to withstand at each point.
Following the taping, it is necessary to confer stiffness on the covering, for which a structure of horizontal and vertical stiffeners is used. In order to locate the stiffeners in the right directions in the coverings, certain modules with different geometries are used, arranged matrix-fashion, between which the horizontal and vertical stiffeners are introduced. Initially, the modules are located in a tipping frame and the stiffeners are introduced between them. Afterwards, the frame is rotated, and the entire array (stiffeners and modules) is located on the covering in the proper position; on this array a bag is located with which a vacuum will be created in order to prevent porosities and then the entire array (tool+covering+stiffeners+modules+vacuum bag) is then introduced into an oven, known as an autoclave, in order to provide the part with the desired characteristics. The autoclave is usually a horizontal cylindrical tank in which the parts are introduced, with a door at one of its ends and a fan plus the heating and cooling system at the opposite end. The autoclave is charged with compressed air plus nitrogen up to the required pressure, depending on the curing cycle of the parts, and the mixture (air+N2) is then recirculated inside by the fan in order to heat up the parts, the temperature being reached and maintained with the heating system (an array of resistors) or cooling by means of the cooling system. By this stage, it is possible to cure the parts.
Following the curing, it is necessary to withdraw the vacuum bag and the modules for the covering. The vacuum bag is withdrawn by hand. After that, the mold stripping or withdrawal of the modules located on the covering is carried out. The last two stages consist of edging and ultrasound inspection. Once the edging phase is completed, the part has to be transported to the automatic inspection machine where it is positioned and secured in the right position for carrying out non-destructive inspection of the part. By means of this stage, the intrinsic quality of the element is defined without damaging it, in other words, a definition is made of whether it has any problems regarding later use. For these tests, inspection equipment is used that is capable of detecting any discontinuities that might be present in the material being used (in this case, carbon fibre) and recording them without damaging the part.
As a final stage, if the entire manufacturing process has been passed through correctly (no manufacturing defect has been detected in the part), the part will be taken to the parts dispatch warehouse or, if any defect was detected in the inspection, the part will be taken to the repair zone so that the necessary operations can be carried out there for rectifying the part.
Each of these stages generally use different transport devices, involving not just the cost of purchasing and maintenance of these devices but also the fact that these devices are used sporadically and discontinuously, plus the fact that they generate handling times which increase the work and slow down the manufacturing process.
For that reason, it was desirable to overcome the drawbacks described above and achieve a handling of parts that would permit the manufacturing costs of the aeronautical parts to be reduced by saving handling times which do not add any value to the part. This was particularly desirable in view of the fact that the rate of manufacture of aeronautical parts, which did not usually very high in comparison with other sectors, has now increased notably and the forecast for the coming years is that it is going to increase even further.

Mobile transport platform for the handling of aeronautical parts


A logarithmic attenuator circuit includes a resistive attenuator in which the series resistors are P-channel MOSFETs with gate electrodes connected to V.sub.DD and the parallel resistors are P-channel MOSFETs which also function as switches. A control circuit (8B) produces a plurality of successive control signals (V1,2 . . . 10) on the gate electrodes of the successive MOSFETs which functions as switches in response to a gain control signal (V.sub.GC)

The invention relates to variable gain logarithmic attenuators/amplifiers, and more particularly to such devices which are more precisely linear than those of the prior art, and still more particularly to such devices which are more easily implemented using CMOS technology than the devices of the prior art.
The closest prior art is set forth in U.S. Pat. No. 5,077,541 entitled "VARIABLE-GAIN AMPLIFIER CONTROLLED BY AN ANALOG SIGNAL AND HAVING A LARGE DYNAMIC RANGE", issued Dec. 31, 1991 and U.S. Pat. No. 5,432,478 entitled "LINEAR INTERPOLATION CIRCUIT", issued Jul. 11, 1995, both by Gilbert, and both assigned to Analog Devices, Inc.
The Gilbert '541 patent discloses a variable gain amplifier including, as a feedback network, a ladder attenuator circuit 22 having a number of "tap" points which are applied as inputs to the + inputs of ten "g.sub.m stages" 36, the outputs of which are connected to a differential amplifier 28 to produce an output signal of the variable gain amplifier. A "swept" control signal is applied between conductors 32 and 34 of a gain control circuit 30 that includes ten transistors 40, nine base resistors R.sub.S, and eight constant current sources I. The gain control circuit, in effect, includes ten "segments", each of which supplies a controllable bias current to a corresponding g.sub.m stage. The gain range of the variable gain amplifier can be viewed as being subdivided into successive segments, each segment having its own g.sub.m stage connected to a corresponding node of the attenuation ladder. Applying the V.sub.CONTROL voltage to the gain control circuit 30 activates each segment amplifier in turn, by increasing and then decreasing the transconductance of that stage. The increasing and decreasing and transconductance occurs in the adjacent g.sub.m stages in succession in an overlapping fashion to provide a smooth reduction in overall gain. The effective "tap" point of the attenuator is said to be continuously "interpolated" between the nodes of the latter circuit by the gain control circuit 30.
Gilbert's '478 patent refers to the logarithmic attenuator of his earlier '541 patent as producing a plurality of overlapping, exponentially varying currents as the control signal is swept through its entire range. The non-linearities in the current waveforms produce a non-linear gain in the g.sub.m stags as a function of the control signal. Gilbert acknowledges that in many applications, however, a more linear current waveform than obtained in his earlier circuit is required. Gilbert proposed to solve the linearity problems which he attributes to the interpolation circuit 30 in his '541 patent by providing a significantly different interpolation circuit 16 which included five sections or "legs" and four pairs of parallel-connected pairs of shunting diodes connected between such legs. For example, one leg includes constant current source I1 and diode D1 connected in series, the adjacent leg includes current source I2 and diode D2 connected in series, and the shunting diodes include parallel-connected diodes D21 and D12 connected between conductors 36 and 38. Conductor 36 also is connected to an output transistor Q1 which produces a bias current I.sub.A that, in effect, "enables" a corresponding transconductance amplifier 14A and controls the transconductance thereof. See FIG. 1 of the '478 patent, in which transconductance amplifier 14A is similar to the first transconductance amplifier 36 in FIG. 1 of the '541 patent. The control nodes 28 and 30 of the interpolation circuit 16 of the '478 patent are connected to current sources 32 and 34, respectively, which "demand" complementary currents through the diodes D1-D5, and hence the output currents I.sub.A,B . . . E, to be piece-wise linear functions of the control signal supplied between control nodes 28 and 30 as the control signal is "swept" through its full range. FIGS. 5A-E and 6 of the '478 patent illustrate the piece-wise linear behavior of interpolation circuit 16 which constitutes the improvement over the less linear circuitry of Gilbert's '541 patent.
While the logarithmic amplifiers disclosed in the Gilbert '541 and '478 patents operate acceptably for implementation in bipolar integrated circuit structures, they are not as well suited for implementation by means of CMOS integrated circuit structures. One reason for this is that the logarithmic attenuators disclosed in the Gilbert '541 and '478 patents are located in the feedback loop of an operational amplifier, and if the circuits disclosed by Gilbert were to be implemented in CMOS technology, the bandwidth would be reduced by this configuration.
Furthermore, the attenuator circuits disclosed in the Gilbert '541 and '478 patents apparently can not be used as simple attenuators; that is, they must be utilized as a feedback component of an amplifier.
It would be desirable to provide a logarithmic attenuator circuit which can be utilized as a simple attenuator otherwise than as a feedback component of an amplifier. It also would be desirable to provide a logarithmic attenuator circuit which is more readily implemented in an integrated circuit using CMOS technology than the logarithmic amplifiers disclosed in the Gilbert '541 and '478 patents.

CMOS differential voltage controlled logarithmic attenuator and method


An animal litter is provided that includes a sorbent granule composed of granule particulate that is able to pass −20 screen sieve and a binder such that greater than 90% of said granules have a size of between −5 and +60 screen sieve. The granule has an oil coating thereon. An animal litter is produced by milling sorbent material to a particulate size such that greater than 90% by weight of said particulate is −20 screen sieve size or finer. The sorbent material is then agglomerated to the milled particulate to a granule size of between −5 and +60 screen sieve with a binder. The granule is then coated with an oil. Extrusion represents a preferred mode of agglomeration.

The production of animal litter from various mineral and biomass granular materials that are decorated with urine-activated clumping agents is well known to the art. Representative examples are found in U.S. Pat. Nos. 5,458,091 and 6,053,125. While such animal litter products have generally been effective, the generally modest urine absorption by a base granule has meant that urine entrainment has had to occur through the wetting and activation of the surface decorating clumping agent. This mechanism results in a less efficient use of litter than would otherwise be obtainable provided the base granule was urine absorbent.
Since conventional animal litters are formed from a large granule decorated with clumping agent, granule irregularity in both shape and size tends to create tracking of the resulting litter by an animal after usage in addition to dust formation associated with granule bumping during transport. A still further limitation of conventional animal litter products is that the typical granule size decorated with clumping agent forms a mass that is unsuitable for disposal in most septic systems and therefore must be handled as solid waste. Thus, there exists a need for an animal litter product where the base granule is formed from agglomerated finer particulate in order to overcome the limitations of the prior art, such litter produced by commercially practical methodology.

Agglomerated animal litter and manufacturing process for the same


A YIG device comprises a resonator including a YIG element 16 of a single crystalline yttrium iron garnet having a part of yttrium substituted with gadolinium, which is formed in a spherical shape, and magnetic field applying means 20 for applying a magnetic field to the YIG element 16 to resonate the YIG element, whereby the YIG device can have a small ΔH and a large threshold electric power for generating the resonance saturation.

As oscillators and filters in the microwave frequency band, the YIG (Yttrium Iron Garnet) device is known. The YIG device utilizes the characteristics of yttrium iron garnet, which is a kind of ferrite, where Q values of the ferrimagnetic resonance are very high, which is suitable for use as microwave band variable tuning resonators and variable tuning oscillators.
The YIG device is used in the local oscillators and filters of measuring instruments, such as spectrum analyzers, network analyzer, etc, and is an important constituent part that plays an important role in the performance of these measuring instruments.
The principal element forming the YIG device is a YIG element. YIG crystal made of magnetic garnet material whose basic composition is expressed by the chemical expression Y3Fe5O12 is machined in a spherical shape to form the YIG element.
In the YIG device, it is required as a characteristic of the YIG crystal that the full width at half maximum of the magnetic resonance spectrum (hereinafter called "ΔH") is small. The ΔH of the magnetic garnet material is generally expressed byΔH=ΔHi+ΔHp+ΔHa.Here, ΔHi is an intrinsic ΔH of the material having the same composition. ΔHp is a part contributed by demagnetizing fields around scratches, pores or different phases. ΔHa is a part contributed by internal magnetic fields based on crystalline magnetic anisotropy.
When the YIG crystal has lattice defects, the precession of the spins in the YIG crystal becomes disuniform, which results in RF characteristics degradation, such as decrease of the Q value, occurrence of parasitic resonance, and occurrence of spurious caused by them, etc. Accordingly, in the YIG device requiring the ΔH to be small, it is preferable to use the single crystalline YIG.
Patent Reference 1: Japanese published unexamined patent application No. Hei 09-270605
Patent Reference 2: Japanese published unexamined patent application No. Hei 06-236814
Patent Reference 3: Japanese published unexamined patent application No. Hei 08-165197
Patent Reference 4: Japanese published unexamined patent application No. Hei 10-233308

Single crystalline magnetic garnet and YIG device


The system for packaging a flexible web (2) that is layered in a zigzag loops comprises the following for simplifying the handling and packaging processes: a layering device (1) for forming a tier consisting of a web (2) that is layered in zigzag loops; a transfer device (26) for directly or indirectly transferring the looped web tier to a packaging container; and a memory-programmable control device for components of the system.

1. Technical Field
The invention relates to a system for packaging a flexible web, in particular a textile web, which is positioned in zigzag-form loops, according to the preamble of claim 1.
2. Prior Art
EP 0 062 753 B and EP 0 778 236 A disclose a system of the type mentioned in the introduction in the case of which a flexible web, in particular a textile web, is positioned in zigzag-form loops and an arrangement of web loops is thus formed. The resulting web-loop arrangements are stacked manually and packaged into a packaging container and then processed further in the textile industry. For this purpose, the web-loop arrangements have to be stacked manually in a packing shaft, that is to say they have to be transferred manually into the packaging shaft by operators, and an arrangement of web loops is thus formed, via push-off plates. The operations of determining the number of web loops per arrangement and of separating the web loops in a precise and defined manner between the respectively bottom and top planes are difficult to automate on account of the random positioning of the textile web loops and of the sensitivity of the web-loop arrangements to pressure. Such web-loop arrangements are generally difficult to handle since they are subjected to a high level of internal stressing at the folds and thus tend to deform easily because, at the folds, the web tries to return into the straightened-out position again. The operator thus lines the packing shaft with a paper sheet prior to the first web-loop arrangement being introduced. Once the desired web length has been achieved, in the first instance, the group as a whole has the paper sheet wrapped around it and this paper sheet is fixed with adhesive tape in order that the web-loop arrangements do not come apart. It is only then that the group as a whole can be removed from the packing shaft and deposited in a packaging container.
U.S. Pat. No. 6,321,512 B discloses a system which is intended for packaging a flexible web positioned in zigzag-form loops and in the case of which a vertically fed length of material is cut into individual webs in the first instance, these webs then being positioned together in loops and the web loops being jointly introduced vertically into a container which is fitted over them. No indication is given here of the possibility of using the system to form, on a horizontal bearing panel, a web-loop arrangement of predeterminable magnitude which could then, moreover, be transferred into a packaging container.

System for packaging a flexible web that is layered in zigzag loops, in particular a textile web


A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the surface of the substrate, thereby minimizing damages to the gate region.

The present disclosure relates generally to semiconductor devices, and more particularly to a method for using retrograde well for forming Metal-Oxide-Semiconductor (MOS) transistors.
Typically, integrated circuits (ICs) operate at various operating voltages. Therefore, transistors in these ICs must withstand certain voltage thresholds. For example, transistors with gate lengths of less than 0.25 um typically must operate at less than 2.5 volts, while transistors with a longer gate length (>0.3 um) may operate at well over 3 volts. In certain high voltage applications such as power supplies and hard-disk controllers, even higher operating voltages may be required.
One undesirable effect when applying a high operating voltage to a MOS transistor not designed for such a high voltage is the accumulation of hot electrons at and around the junction of the channel and drain of the transistor. In turn, ionized electrons resulting from the hot electrons move to the drain, thereby causing the drain current to increase. When hot electrons increase to a point where the source/drain junction voltage exceeds a certain level, the source/drain junction of the transistor breaks down, thereby causing damage to the transistor. That certain level of source/drain junction voltage is also known as the breakdown voltage, and must be increased in high voltage environments wherein a high operating voltage is applied to the transistors.
In order to provide a higher breakdown voltage, a double diffused drain (DDD) is typically provided in many MOS transistors that need to operate in the high voltage environment. DDDs help to suppress the hot electron effect, thereby reducing electrical breakdown of the source/drain under high operating voltage.
However, high voltage MOS transistors with DDD are typically formed on a semiconductor wafer that also includes low voltage MOS transistors without DDD. Because the thermal budgets of the processes needed for the formation of high voltage MOS transistors are different from that of low voltage MOS transistors, it is difficult to integrate the manufacturing processes of high voltage MOS transistors to those of low voltage MOS transistors without materially causing permanent change to the physical characteristics of these transistors. As an example, since the drain of a high voltage MOS transistor needs to withstand high breakdown voltages, DDD is formed with a process whereby high temperature and long processing time are required. However, the high temperature and long processing time may drive ions in the doped regions of the low voltage MOS transistors into the silicon substrate beyond a predetermined depth, thereby causing the physical characteristics of the low voltage MOS transistors to become uncontrollable. As such, traditional processing methods are not practical in producing advanced semiconductor technologies that have both high voltage and low voltage MOS transistors because of the increasing uncontrollability.
One solution is to use a drain extended transistor, wherein a very lightly doped extension region adjacent to the drain is used. This extension not only allows voltage to be dropped across the extension region, but also reduces the electric field across any part of the gate oxide, thereby preventing breakdown. However, such extensions consume much wafer space, and are known to be very expensive in advanced technologies where transistor densities are high and wafer real estate commands a significant premium.
Desirable in the art of are additional designs that provide improved high voltage designs for advanced semiconductor technologies that may achieve a high breakdown voltage in the smallest-possible surface area.

Method of forming high voltage devices with retrograde well

Taiwan Semiconductor Manufacturing Co., Ltd.


An image formation device includes a power controller that controls transition to an energy-saving mode to reduce power consumption in a standby state and starts up out of the energy-saving mode and a timer in which a timing schedule that starts up the device out of the energy-saving mode is set. The power controller controls the surface temperature of the fixing roller of the image generator to be a temperature lower than the fixing temperature that enables image formation when the image formation device is started up out of the energy-saving mode according to the timing schedule set in the timer.

1. Field of the Invention
The present invention relates to an image formation device and to a method for starting an image formation device and, more specifically, to an image formation device configured to start automatically out of an energy-saving mode when a timer reaches a set time, and to a method for starting the image formation device.
2. Description of the Related Art
Image formation devices such as multi-functional peripherals (MFPs) that are integrally equipped with a copier, printer, scanner, facsimile and other functions are widespread. Such image formation devices may be equipped with energy-saving modes for reducing power consumed while waiting to operate. In these energy-saving modes, power consumption is reduced while standing by to operate by methods that include turning off the power supplied to unnecessary devices and the like while in standby, halting clocks used for operation, and putting devices that have energy-saving functionality into that state.
Japanese Patent Application Laid-Open Publication No. 2007-274487, for example, describes technology that causes devices to automatically transition to an energy-saving mode and automatically return from the energy-saving mode according to a preset timing schedule. Specifically, this image formation device is equipped with a conduction switching means which switches between whether or not one or a plurality of function blocks that are components or collections of components for image processing are conducting independently of conduction to a communication means, a timing schedule storage means which stores preset timing schedules for conduction control of the function blocks, and a schedule startup control means which, when the function blocks are in a non-conducting state, switches the function blocks to a conducting state by controlling the conduction switching means according to a timing schedule stored in the timing schedule storage means.
In the energy-saving mode described above, power is not supplied to the image generator, either, so the surface of the fixing roller of the image generator is naturally not being warmed. Consequently, when starting up out of the energy-saving mode, it is necessary to raise the surface temperature of the fixing roller of the image generator to the specified temperature and to place the device in a fixing-capable state to be able to form images. At this time, in cases where the device is started up out of the energy-saving mode explicitly by the user pressing an energy-saving cancel button or the like, the possibility of the user being in front of the image formation device and promptly performing image formation processing is considered to be high. It is therefore desirable to rapidly enter a fixing-capable state.
However, it is considered highly unlikely for the user to be in front of the image formation device when it is started up out of an energy-saving mode automatically according to a timing schedule as recited in Japanese Patent Application Laid-Open Publication No. 2007-274487, as opposed to when it is started up out of an energy-saving mode by the user performing an operation. That is, even if the fixing roller is heated and caused to enter into a fixing-capable state while the user is not in front of the image formation device, this only wastefully consumes power by maintaining a heated state and is therefore not desirable.

This patent is subject to a terminal disclaimer.

Image formation device and method for starting image formation device


A method for processing a silver halide color photographic light-sensitive material comprising a support having thereon at least one light-sensitive silver halide emulsion layer, the method comprising the steps of: exposing the light-sensitive material; color developing the light-sensitive material; and desilvering the light-sensitive material, the desilvering step comprising processing the light-sensitive material with a desilvering processing solution containing at least one compound represented by formula (I) or a salt thereof: ##STR1## wherein Z represents --NR.sub.5 (R.sub.6) or --OR.sub.7, R represents an alkylene group, n represents 0 or 1, R.sub.1, R.sub.2, R.sub.3, R.sub.4, R.sub.5 and R.sub.6 each independently represents a hydrogen atom, an aliphatic group or an aromatic group, and R.sub.7 represents an aliphatic group or an aromatic group, provided that any two of R.sub.1, R.sub.2, R.sub.3 and R.sub.4 may be combined with each other to form a ring, that the total carbon number of R.sub.5 and R.sub.6 is from 4 to 20 and that R.sub.5 and R.sub.6 may form a ring.

In general, the processing of a silver halide photographic light-sensitive material, for example, a silver halide color photographic light-sensitive material (hereinafter sometimes referred to as "light-sensitive material"), comprises a color development step and a desilvering step. In the desilvering step, the developed silver produced at the color development step is oxidized (bleached) into silver salt by a bleaching agent having an oxidation action and removed together with unused silver halide from the light-sensitive layer by a fixing agent which forms a soluble silver. As the bleaching agent, a ferric (trivalent) ion complex salt (e.g., aminopolycarboxylic acid iron(III) complex salt) is mainly used, and as the fixing agent, a thiosulfate is usually used.
The bleaching and the fixing may be used individually as a bleaching step and a fixing step or may be conducted simultaneously as a bleach-fixing step. These processing steps are described in detail in James, The Theory of Photographic Process, 4th edition (1977).
The above-described processing is usually conducted in an automatic developing machine. Particularly, in recent years, a small-size developing machine called a mini lab. is installed at a shop and rapid processing service to users is being popularized. In the processing of color paper, as the developing machine is miniaturized and the rapid processing prevails, the bleaching agent and the fixing agent are used in the same bath as a bleach-fixing bath. On the other hand, in the above-described processing, for the purpose of resource saving and environmental conservation, low replenishment of the processing solutions is aggressively recommended. However, if the processing is conducted merely in a low replenishment of the developer, matters dissolved out from the light-sensitive material, particularly, iodine ions or bromine ions as a strong development inhibitor accumulate to reduce the development activity, thereby causing a problem of failure in the rapid processing. In order to reduce the accumulation of iodine ions or bromine ions and to achieve rapid processing, JP-A-58-95345 (the term "JP-A" as used herein means an "unexamined published Japanese patent application") I JP-A-59-2323442, JP-A-61-70552 and WO87-04534 disclose a method of using a silver halide light-sensitive material having a high silver chloride content and this is considered to be an effective technique for achieving rapid processing in a low replenishing system of the developer.
JP-A-4-443 describes the processing of a silver halide light-sensitive material having a high silver chloride content with a color developer containing a hydroxyalkyl-substituted p-phenylenediamine derivative having a specific structure, whereby the dye image can be excellent in the stability and the low replenishment and the ultra-rapid processing can be achieved.
Further, the bleach-fixing is also being demanded to be greatly expedited and improved in the solution stability. However, if a short-time bleach-fixing is conducted after the rapid color development, the developing agent which is conventionally removed in the bleach-fixing step or the sensitizing dye or the dye for preventing halation used in the light-sensitive material cannot be removed sufficiently and as a result, stains on an image after the processing, namely, blurs on the white background of an image are generated to trash the image as cannot endure viewing. Accordingly, a desilvering processing composition and a processing method capable of overcoming the above-described problems have been keenly demanded.
In the processing of a silver halide light-sensitive material containing silver chlorobromide or silver iodobromide, an onium salt represented by a quaternary ammonium salt or an organic base taking a conjugate acid has been conventionally used in the bleaching bath as a bleaching accelerator so as to accelerate the desilvering as described in JP-A-49-84440, JP-A-61-151147, JP-A-62-129854, JP-A-62-135833, JP-A-1-211757 and JP-A-1-213653. As described in JP-A-1-211757, the bleaching accelerator is useful particularly in processing a color reversal light-sensitive material for photographing or color negative light-sensitive material for photographing using a high silver amount emulsion.
However, in these patent publications, a method for rapidly removing or accelerating the removal of a developing agent or a coloring material such as a sensitizing dye or a dyestuff is not known. Further, it has been found that some desilverization accelerators deteriorate the image stability when the water washing or stabilization processing time is reduced and they are unsuitable for the rapid processing including water washing.
JP-A-5-303185 discloses rapid removal of a developing agent or a dye remaining in the light-sensitive material by using a bisguanidine compound. The bisguanidine compound may surely remove a developing agent or a dye remaining in the light-sensitive material to a certain degree, which is, however, not satisfactory, and the compound is still bound to a problem of discoloration generated when the processed light-sensitive material is stored under a high temperature and a high humidity, hence, an improvement is demanded.
In JP-B-49-26140 (the term "JP-B" as used herein means an "examined Japanese patent publication"), JP-B-49-26900, JP-A-55-87145, JP-A-60-260952, JP-A-61-4050, JP-A-61-4054 and JP-A-61-35447, other guanidine compound is added to a developer or a stabilization solution, however, any compound is insufficient in the removal of a developing agent or a dye remaining in the light-sensitive material and bound to a problem of generation of stains, hence, an improvement is demanded.

Processing method of silver halide color photographic light-sensitive material and desilvering processing composition


The present invention relates to a cutting tool, e.g. carbide insert, solid carbide drill or mill or carbide tip, particularly for milling of steels, stainless steel, HRSA, titanium or any alloyed material from any of these groups, comprising a cemented carbide substrate and an aperiodic multilayer coating with:                a substrate of cemented carbide having a composition of from about 8 to about 11 wt-% Co, from about 0.1 to about 0.5 wt-% Cr and balance essentially tungsten carbide        and a coating which is essentially an aperiodic multilayer consisting of layers A+B+A+B+A . . . where the sublayers A and B consist of AlxTi1-xN and TiyAl1-yN respectively. The typical average thickness of each A+B sequence is in the range from about 30 to about 300 nm and the total thickness of the coating in the range from about 0.5 to about 20 μm. The total chemical composition averaged over the whole coating consists of TizAl1-zN where z lies in the range from about 0.40 to about 0.70.

The present invention pertains to a coated cemented carbide insert for machining of steels or stainless steel when a high wear resistance combined with a high edge toughness are required.
In typical milling operations, the thermal load on the insert will vary over time, something that often induces thermal tension and subsequently may generate thermally induced cracks in the coatings. This is especially a concern with cooled/wet operations where the thermal variations are more pronounced than in dry operations.
A common wear mechanism in milling is cracking, followed by chipping or small fragments of the cutting edge loosening from the rest of the substrate. Increasing the edge toughness is thus of great importance to increase tool lifetime. One possible solution to decrease the risk of thermal cracking—as well as cracking for various other reasons—is to use a multilayered coating. The multilayered coating is expected to act as a crack inhibitor as an initial crack going down the coating may be redirected at any sublayer interface. Another benefit of multilayer coatings is expected to show up when hard, wear resistant layers are interlaid with a softer sublayer. The softer layer may be able to absorb shocks and thus inhibit cracks from penetrating the whole coating.
WO 98/48072 relates to a cutting tool comprising a body of sintered cemented carbide, ceramic or high speed steel on which at least on the functional parts of the surface of the body, a thin, adherent, hard and wear resistant coating is applied. The coating comprises a laminar, multilayered structure of refractory compounds in polycrystalline, non-repetitive form MX+NX+MX+NX . . . where the alternating layers MX and NX are composed of metal nitrides or metal carbides. The sequence of individual layer thicknesses is essentially aperiodic throughout the entire multilayered structure.


The present invention provides an efficient method and system for performing data mining on large amounts of data using a multi-threaded Bayesian algorithm. The method for data mining includes receiving data from a database, performing multi-threaded classification on the data using a Naïve Bayes model and performing multi-threaded regression on the data based on a Naïve Bayes model. One of the multi threaded classification and regression steps may include processing the data according to a batch learning system, processing the data according to an incremental learning system, processing the data according to an online learning system, and processing the data according to a distributed learning system. One of the the multi-threaded classification and regression steps may include developing a set of rules from a set of training data. One of the multi-threaded classification and regression steps may comprise arranging the data into a plurality of groups.

As the amount of data expands, the ability to process and comprehend that data becomes more difficult. Patterns and trends are lost in the massive quantities of data stored in databases and data warehouses. As the influx of data increases, the ability to interpret the data also becomes more difficult. Thus, there is a need for a powerful and efficient analytical tool that can process and derive interesting knowledge from the enormous amounts of data available.
Historically, the primary method for analyzing data was to construct well structured hypotheses and test the hypotheses by analyzing data. Today, a method called data mining is one of the new ways of analyzing data. Data mining is an automated process whereby previously unknown relationships among data are discovered. The two main steps of data mining are modeling, and scoring. These two steps are typically performed by a data mining tool.
Generally, modeling is the process of deriving a model or function by analyzing sets of training data. The derived model may be represented in various forms, such as classification rules, decision trees, mathematical formulae, or neural networks. If a model was a rule, for example, the rule could be a set of symptoms that a doctor uses to diagnose a disease. This rule can be derived from a set of patients who had the disease. Once derived, the rule is applied to a larger group of people to assist in determining whether they have that disease. The model that is generated using this training data is then used to make predictions about future patients.
Scoring involves making predictions with the generated model. The score may or may not be augmented with a numerical values that represents the certainty of each prediction. Scores are predictions, and can be present along with associated data, e.g., confidence measures or overall accuracy measures. Currently, there are several methods for scoring with a model. One method of scoring involves using an Open DataBase Connectivity (ODBC) or Structured Query Language (SQL) cursor. The scoring occurs where the model is stored and the scoring results are transmitted from the model's location to the database. In another method, a model may consist of data used by a C, C++ or Java function. The function may be wrapped in an application, which runs against the data stored in the database. However, this option also involves massive data movement and hence, is inefficient.
Performance-wise these are not efficient options because they involve a lot of data movement across the database to the mining tool's location. Further, many models are unusable because the execution time required is too large to process the data. Thus, there is a need for a more efficient data mining system and method.

Multi-threaded Naïve Bayes algorithm for enterprise-server data mining


A power stealing circuit provides operating power for a environmental control such as a thermostatic control while controlling the current in a power supply line to a load in response to the cycling output of the environmental control. A pair of power FETs are connected to the series power terminals, and the gates are controlled by logic and phase timers. FETs are turned off at the end of a phase, while a small amount of power sufficient to operate the control and circuitry is diverted to a power storage circuit, then the FETs are turned back without substantial interruption to the load. A preferred embodiment uses a bi-directional charge pump to transfer power between low- and high-voltage power storage circuits. The circuit can operate with symmetrical or nonsymetrical AC or DC loads.

A conventional environmental control system utilizes various electrically powered devices such as heating, cooling, ventilating, or air conditioning units. Typically, the environmental control system uses a bi-metal thermostat to activate and deactivate the various devices. The conventional bi-metal thermostat directly switches the alternating current which powers the equipment. Since the bi-metal thermostat is a mechanical device, it does not require any external operating power in order to switch the current.
With the advances in semiconductor components and embedded microprocessors, it has become increasingly common to replace the conventional bi-metal thermostat with a sophisticated electronic thermostat which affords a longer life, quieter operation, and greater flexibility. When replacing a mechanical thermostat with an electronic thermostat, additional power must be supplied for circuit operation. Typically, the additional power is provided by an external transformer and an additional power supply line from the transformer to the electronic thermostat. Alternatively, the electronic thermostat may be powered by an internal battery.
There are several disadvantages to providing power to an electronic thermostat by an external transformer. For example, the additional components increase the cost of replacing a mechanical thermostat with an electronic thermostat. In addition, running the conductor from the transformer to the electronic thermostat may be very difficult and costly.
There are also disadvantages to using a battery for providing the operating power. One primary disadvantage is the need to continually check and replace the battery. If the battery is not properly replaced and cannot provide adequate power, the electronic thermostat may fail during a period of extreme environmental conditions.
It would be desirable to provide electronic thermostat switching circuitry with the necessary power for operation by taking, or "stealing" current from the current supply that is being controlled, so that the need for additional wiring or batteries is eliminated.
While it has been shown that FETs have been connected in opposition with common sources for switching alternating current, an overall best scheme for providing the gate control voltages from power derived off the two load control wires for both the OFF and ON states of the control has not been done. Typically, the two gates of the opposing transistors have also been connected together for ON-OFF control without the capability of stealing some of the current for energizing the electronic control circuitry.

Power stealing solid state switch for supplying operating power to an electronic control device


An oil separator provided in combination with a cylinder head cover of an internal combustion engine. The oil separator includes a separator cover fixed to an inner surface of the cylinder head cover defining a space extending in a first direction perpendicular to axis of a camshaft in plan, between the separator cover and the cylinder head cover. The separator cover has an opening through which the space is opened to a valve operating chamber. A partition wall is provided to define in the space an inlet-side separator chamber and an outlet-side separator. The partition wall extends in a second direction parallel with the axis of the camshaft and being formed with a plurality of fine passages. Additionally, a plurality of projection walls project from a part of the inner surface of the cylinder head cover which faces the valve operating chamber through the opening.

This invention relates to improvements in an oil separator provided in combination with a cylinder head cover of an internal combustion engine to separate oil mist in blow-by gas to be discharged out of the engine through the cylinder head cover.
As is well known, in an internal combustion engine of an automotive vehicle, blow-by gas containing unburnt gas component leaked into a crankcase from combustion chambers of the engine is again introduced or recirculated into the combustion chambers through an engine air intake system, together with fresh taken in from the outside of the engine. In such recirculation of blow-by gas, blow-by gas flowing through the crankcase contains oil mist of lubricating oil. In order to prevent oil mist from being carried to the engine intake system, in general, an oil separator is provided in combination of a cylinder head cover as a single unit so that the blow-by gas is taken out from the engine after oil mist is separated from blow-by gas by the oil separator, as disclosed in Japanese Patent Provisional Publication Nos. 2000-45750 and 7-243317. In general, two blow-by gas paths are connected to the cylinder head cover, in which fresh air is introduced through one of the two blow-by gas paths under a normal engine operating condition while blow-by gas flows through both the two blow-by gas paths under a high engine load operating condition. The cylinder head cover is provided with two oil separators which are respectively used for the two blow-by gas paths.
Many oil separators provided in combination with the cylinder head cover have been proposed. In an arrangement of Patent Provisional Publication No. 2000-45750, an inner plate having a plurality of small holes for oil separation is horizontally disposed, in which blow-by gas passed through the small holes strike against projection portions formed at a ceiling surface. Accordingly, oil droplets separated are spread on the upper surface of the inner plate thereby clogging the small holes. This lowers an oil separation performance of the oil separator.
In the arrangement of Patent Provisional Publication No. 7-243317, a cover-like inlet member is disposed at the bottom plane of an inlet opening which is open to the upper side of a camshaft in order to prevent oil droplets raised up by the camshaft from directly entering the inlet opening. This inlet member increases the whole height of the cylinder head cover by an amount corresponding to the inlet member.

Oil separator combined with cylinder head cover


The disclosed methods and apparatuses provide a unique and cost efficient approach to using traffic channels of an optical mesh network, and sometimes optical supervisory channels, for carrying timing information (e.g., BITS timing signals), thus eliminating the need to use external BITS sources at remote add/drop nodes of a network. Planning the distribution of timing in such an optical mesh network includes identifying in the network a source node associated with an external timing source, identifying optical light paths between nodes in the network, and, for nodes other than the source node, selecting optical light paths originating either directly or indirectly from the source node to use to derive timing information.

Networks that transport data may require timing, e.g., digital pulse cycles at precise accuracy. Such timing can be provided by a Building Integrated Timing Supply (BITS) clock. Few network providers, however, are able to provide external BITS clock generators at their traffic add/drop locations to add/drop data traffic synchronously. Prior approaches to this problem include networks based on simplistic ring architectures, which have a natural linearity to optical traffic flow, but mesh optical networks are more complex and mandate the need for advanced tools and apparatuses to implement and validate network timing distribution. Other approaches to distribute timing are based on a singular approach of using an optical channel carrying synchronous network traffic to derive BITS timing at a remote add/drop node and/or using dedicated traffic demands for carrying timing. These approaches are not able to account for network outages due to fiber cuts and their impact on the network timing distribution.

Method and apparatus for distributing network timing in a mesh optical network


The present invention relates to a Lactuca sativa seed designated 79-05 RZ, which may exhibit a combination of traits including resistance against downy mildew strains Bl:1 to Bl:31, CA-I to CA-VIII (Bremia lactucae), currant-lettuce aphid (Nasonovia ribisnigri) biotype Nr:0, and lettuce mosaic virus (LMV), as well as moderately glossy leaves with a medium to dark green leaf color. The present invention also relates to a Lactuca sativa plant produced by growing the 79-05 RZ seed. The invention further relates to methods for producing the lettuce cultivar, represented by lettuce variety 79-05 RZ.

All cultivated forms of lettuce belong to the highly polymorphic species, Lactuca sativa, which is grown for its edible head and leaves. As a crop, lettuces are grown commercially wherever environmental conditions permit the production of an economically viable yield.
Lactuca sativa is in the Cichoreae tribe of the Asteraceae (Compositae) family. Lettuce is related to chicory, sunflower, aster, scorzonera, dandelion, artichoke and chrysanthemum. Sativa is one of about 300 species in the genus Lactuca.
Lettuce cultivars are susceptible to a number of pests and diseases such as downy mildew (Bremia lactucae). Every year this disease leads to millions of dollars of lost lettuce crop throughout the world. Downy mildew (Bremia lactucae) is highly destructive on lettuce grown at relatively low temperature and high humidity. Downy mildew is caused by a fungus, Bremia lactucae, which can be one of the following strains: NL1, NL2, NL4, NL5, NL6, NL7, NL10, NL12, NL13, NL14, NL15, NL16, Bl:17, Bl:18, Bl:20, Bl:21, Bl:22, Bl:23, Bl:24, Bl:25, Bl:26, Bl:27, Bl:28, Bl:29, Bl:30, Bl:31 (Van Ettekoven, K. et al., "Identification and denomination of 'new' races of Bremia lactucae," In: Lebeda, A. and Kristkova, E (eds.), Eucarpia Leafy Vegetables, 1999, Palacky University, Olomouc, Czech Republic, pp. 171-175; Van der Arend et al. "Identification and denomination of "new" races of Bremia lactucae in Europe by IBEB until 2002." In: Van Hintum, Th et al. (eds.), Eucarpia Leafy Vegetables Conference 2003, Centre for Genetic Resources, Wageningen, The Netherlands, p. 151; Plantum NL (Dutch association for breeding, tissue culture, production and trade of seeds and young plants), Van der Arend et al. "Identification and denomination of "new" races of Bremia lactucae in Europe by IBEB until 2002." In: Van Hintum, Th et al. (eds.), Eucarpia Leafy Vegetables Conference 2003, Centre for Genetic Resources, Wageningen, The Netherlands, p. 151; Plantum NL (Dutch association for breeding, tissue culture, production and trade of seeds and young plants); IBEB press release "New race of Bremia lactucae Bl:27 identified and nominated", May 2010; Plantum NL (Dutch association for breeding, tissue culture, production and trade of seeds and young plants), "New race of Bremia lactucae Bl:28 identified and nominated", March 2011; Plantum NL (Dutch association for breeding, tissue culture, production and trade of seeds and young plants), IBEB press release, "New races of Bremia lactucae, Bl:29, Bl:30 and Bl:31 identified and nominated", August 2013), Ca-I, Ca-IIA, Ca-IIB, Ca-III, Ca-IV (Schettini, T. M., Legg, E. J., Michelmore, R. W., 1991. Insensitivity to metalaxyl in California populations of Bremia lactucae and resistance of California lettuce cultivars to downy mildew. Phytopathology 81(1). p. 64-70), and Ca-V, Ca-VI, Ca-VII, Ca-VIII (Michelmore R. & Ochoa. O. "Breeding Crisphead Lettuce." In: California Lettuce Research Board, Annual Report 2005-2006, 2006, Salinas, Calif., pp. 55-68).
Downy mildew causes pale, angular, yellow areas bounded by veins on the upper leaf surfaces. Sporulation occurs on the opposite surface of the leaves. The lesions eventually turn brown, and they may enlarge and coalesce. These symptoms typically occur first on the lower leaves of the lettuce, but under ideal conditions may move into the upper leaves of the head. When the fungus progresses to this degree, the head cannot be harvested. Less severe damage requires the removal of more leaves than usual, especially when the lettuce reaches its final destination.
Of the various species of aphids that feed on lettuce, the currant-lettuce aphid (Nasonovia ribisnigri) is the most destructive species because it feeds both on the leaves of the lettuce as well as the heart of the lettuce, making it difficult to control with conventional insecticides. The lettuce aphid feeds by sucking sap from the lettuce leaves. Although direct damage to the lettuce may be limited, its infestation has serious consequences because the presence of aphids makes lettuce unacceptable to consumers.
Symptoms of LMV vary greatly. Leaves of plants that are infected at a young stage are stunted, deformed and (in some varieties) show a mosaic or mottling pattern. Such plants rarely grow to full size; head lettuce varieties infected early fail to form heads. Plants that are infected later in the growth cycle show a different set of symptoms. These plants may reach full size, but the older outer leaves turn yellow, twisted, and otherwise are deformed. On head lettuce, the wrapper leaves often will curve back away from the head and developing heads may be deformed. In some cases, brown necrotic flecks occur on the wrapper leaves.
Next to the resistances against pathogens that are desired by lettuce growers, lettuce leaves should have an appearance that is appealing to the customer. Since lettuce is increasingly sold as mixes of leaves in a plastic container or bag, glossiness and variation in leaf color are highly desired characteristics that make such a mixture of leaves more appealing to the customers. Dark green varieties have the additional advantage that processed leaf pieces cannot quickly be considered as pale and therefore visually non-fresh.
Dark green lettuce varieties also have the advantage of a higher chlorophyl content, because this is strongly correlated with a higher beta-carotene content and a higher lutein content. Both components are antioxidants. Beta-carotene can be transferred into vitamin A in the human body. Lutein is supposed to have positive effects on human health as well.
Citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention.


A valve is provided for a hydraulic system having a source of pressurized fluid, a fluid actuator, and a proportional pressure compensating valve. The valve has a bore in fluid communication with the source and the fluid actuator. The valve also has a valve element disposed in the bore and movable between a flow blocking position and a flow passing position to selectively fluidly communicate the source with the fluid actuator. The valve also has a valve signal passageway disposed within the valve element and configured to be in fluid communication with a pressurized fluid having a signal pressure indicative of pressure supplied to the fluid actuator. The valve further has first and second orifices disposed within the valve element in fluid communication with the valve signal passageway and the bore. The valve signal passageway is configured to communicate the signal pressure with the first and second orifices. Movement of the valve element from the flow blocking position to the flow passing position fluidly communicates the first orifice with a system signal passageway before the second orifice, and fluidly communicates both the first and second orifices with the system signal passageway when the valve element is in the flow passing position.

Hydraulic circuits are often used to control the operation of hydraulic actuators of work machines. These hydraulic circuits typically include valves that are fluidly connected between a pump and the actuators to control a flow rate and direction of pressurized fluid to and from chambers of the actuator. In some instances, multiple actuators may be connected to a common pump causing undesirable pressure fluctuations within the hydraulic circuits during operation of the actuators. In particular, the pressure of a fluid supplied to one actuator may undesirably fluctuate in response to operation of a different actuator fluidly connected to the same pump. These pressure fluctuations may cause inconsistent and/or unexpected actuator movements. In addition, the pressure fluctuations may be severe enough and/or occur often enough to cause malfunction or premature failure of hydraulic circuit components.
One method of reducing these pressure fluctuations within the fluid supplied to a hydraulic actuator is described in U.S. Pat. No. 5,878,647 ("the '647 patent") issued to Wilke et al. on Mar. 9, 1999. The '647 patent describes a hydraulic circuit having two pairs of solenoid valves, a variable displacement pump, a reservoir tank, and a hydraulic actuator. One pair of the solenoid valves includes a head-end supply valve and a head-end return valve and connects a head end of the hydraulic actuator to either the variable displacement pump or the reservoir tank. The other pair of solenoid valves includes a rod-end supply valve and a rod-end return valve and connects a rod end of the hydraulic actuator to either the variable displacement pump or the reservoir tank. Each of these four solenoid valves is associated with a different pressure compensating check valve. Each pressure compensating check valve is connected between the respective solenoid valve and the actuator to control a pressure of the fluid between the associated valve and the actuator.
Although the multiple pressure compensating valves of the hydraulic circuit described in the '647 patent may reduce pressure fluctuations within the hydraulic circuit, they may increase the cost and complexity of the hydraulic circuit. In addition, the pressure compensating valves of the '647 patent may not control the pressures within the hydraulic circuit precise enough for optimal performance of the associated actuator.
Additionally, hydraulically actuated pressure compensating valves may cause undesirable pressure fluctuations within the hydraulic circuit if biased by significantly low pressure signals. Such pressure signals may communicate significantly low pressure pulses to the pressure compensating valve that could cause rapid movement of the pressure compensating valve element. This rapid movement may result in a pressure surge through the hydraulic circuit and, if communicated to the actuator, may cause undesirable and/or jerky operation of the actuator.
The disclosed valve is directed to overcoming one or more of the problems set forth above.

Valve gradually communicating a pressure signal


Systems and methods that may be implemented to provide on-board trace impedance testing for a system level board of an information handling system. A printed circuit board (PCB) of the system level board may include built-in test trace circuitry that may be used to measure board trace impedance so that the trace impedance of a fully assembled system level board may be tested and verified for compliance with trace impedance specification, and without requiring any disassembly of the board.

As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
PCB trace impedance plays a critical role in the integrity of high-speed electrical signal waveforms on system level boards used in information handling systems. Reflections will occur during system operations if the trace impedance does not match the source impedance and, if the rise time is fast enough, these reflection will affect the signal to noise ratio and cause erroneous results. During conventional PCB manufacture methods, an attempt is made to fabricate conventional system level PCBs to meet a specified stackup. The impedance of various PCB traces is specified in the stackup to be within a certain defined tolerance. However, no cost-effective method exists that may be performed during and post PCB assembly to verify that the trace impedance of individual system level PCBs meets the specified trace impedance tolerance.
Companies that produce system level boards need to verify the trace impedance of PCBs. In an attempt to do so it is common to measure the trace impedance of only a small portion (a few samples) of all manufactured PCBs using an expensive time domain reflectometer (TDR) machine, and to assume that all similar PCBs were manufactured to have the same or similar trace impedance as were the portion of PCBs that were tested. However, TDR machines are expensive and the process of obtaining TDR measurements is typically manual and time-consuming, requiring the PCB traces to have no component present during measurement (i.e., testing must be performed with a bare fab). Moreover, as with any manual process there exists the possibility of human error. There is also a significant risk with this common approach as it only validates a few PCB samples out of an entire batch, and assumes there was no change in the fabrication process from individual PCB to other individual PCBs. But there are many possible fabrication variations that may occur between different PCBs, such as use of different board etching machines for etching different batches of PCBs, use of the wrong material for etching some PCBs, variations in the source of PCB materials (e.g., dielectric, copper, etc.) used to fabricate different PCBs, etc. These fabrication variations can result in manufacture of some PCBs that violate the specified trace impedance tolerance and therefore vary in performance from other similar PCBs.
The root cause of erroneous performance and resulting errors observed during operation of an information handling system must be investigated to eradicate the errors, and time is required to determine the root cause of such problems. Where the root cause of the erroneous system performance is determined to be related to signal integrity, then incorrect trace impedance of a system board is always a possible culprit. However, there is no time and cost-efficient procedure that may be performed to validate the correct trace impedance of an assembled system level board.
During system operation, poorly controlled system board trace impedance is known to cause non-monotonic edges, create overshoot/undershoot, increase jitter, affect pulse width, cause ringing, and other problems. These problems may cause functional failures within the board electrical communication path such as packet drops, CRC or LDPC errors, and at a minimum decrease the board signal performance so that it does not provide the signal performance margin that is required by a given protocol specification. This is a cause for concern regarding the stability and robustness of any given information handling system.
Some integrated circuits (ICs) execute firmware that can be used to change IC termination impedance.

Systems and methods for in-silicon measurement of printed circuit board (PCB) trace impedance


A terminal device, in an information collection system in which the terminal device and an information collection device are connected, which reads question information from a question information storage section storing question information, as questions the responses to which are to be provided to the information collection device, and after power to the terminal device has been turned on, or based on a state of usage, receives the input of response information, as responses corresponding to output question information, and transmits the input response information to the information collection device.

1. Field of the Invention
The present invention relates to an information collection system, information collection device, terminal device management program, information collection management program, information collection management method, and terminal device management method, for transmission from a terminal device to an information collection device of answer information responding to question information, and for collection of information.
Priority is claimed on Japanese Patent Application No. 2004-332897, filed Nov. 17, 2004, the content of which is incorporated herein by reference.
2. Description of Related Art
When conventional personal computers (hereafter "PCs"), printers, and other equipment are sold as products, product marketing is performed, or data for reference in developing new products is obtained, by ascertaining the type of user making a purchase, the purposes for which the purchase was made, and similar.
In such cases, for example, a postcard is inserted in advance into the packaging box of the packed product in order to have the user register and fill out a questionnaire, to obtain information relating to the user who has purchased the product. By having users who have purchased the product return such a postcard, information relating to users is collected.
In the case of the above-described technology, there is the problem that if the user loses the postcard inside the packaging box, information relating to the user cannot be collected. Moreover, there is the problem that, in order to collect information relating to the user, the user must voluntarily send the postcard. With respect to the distribution source, when the product has been sold via a sales agent, it is possible to ascertain which products have been sold in what quantity by the agent, but there is a problem in that it is not possible to ascertain the sales route beyond the agent, that is, to what users the products have been sold. There is a further problem in that, in the cases in which a father buys a product for his child to use, or in the cases in which a product is purchased by a corporation for use by an employee of the corporation, and in other cases in which a representative purchases the product but a family member other than the representative uses the product, even if information regarding the purchaser is obtained, it is not possible to collect information relating to the actual user of the product.
In addition to the above-described method using a postcard, systems have been proposed to collect information relating to users by utilizing the Internet (see for example Japanese Unexamined Patent Application, First Publication No. 2001-250048).
In the related art, when a user has the will to apply for a prize, the network information collection processing system enables collection of information related to a user upon application for the prize; but there is the problem that information relating to users who do not apply for the prize cannot be collected. That is, there is the problem that if a user does not voluntarily apply for a prize, then the entity offering the prize cannot obtain information relating to the user.
Thus in the above-described technology and the related art, there are the problems that the user must voluntarily initiate contact, and that users actually using the product cannot be ascertained.

Information collection system, information collection device, terminal device management program, information collection management program, information collection management method, and terminal device management method


Methods and apparatus, including computer program products, for a supplemental powered information receiver. A system includes a processor linked to a memory, the memory including at least a Global Positioning System (GPS) navigation process, a clock and internal timer linked to the processor, a programmable power source linked to the processor, and an information receiver module linked to the processor, the information receiver module receiving information when programmed to power up into a standby mode.

The present invention relates to a Global Positioning System (GPS) navigation device, and more particularly to a supplemental powered information receiver.
GPS is a "constellation" of twenty-four well-spaced satellites that orbit the Earth and make it possible for people with ground receivers/devices to pinpoint their geographic location. The location accuracy is typically from 100 meters to 1 meter for most GPS devices.
A popular use of GPS devices is trip navigation. More particularly, GPS navigational devices are often used in conjunction with vehicles to map out or route directions between two geographic points for a vehicle operator, i.e. a geographic origin and a geographic destination. Most GPS navigational devices enable a user to enter geographic origin and destination points interactively and provide an ability to store such pairs of points as routes.

Supplemental powered information receiver


The bus switch with back gate control circuit includes: an NMOS transistor coupled between a first port and a second port; a PMOS transistor coupled in parallel with the NMOS transistor; a first blocking device coupled between the first port and a control node of the PMOS transistor; a second blocking device coupled between the second port and the control node of the PMOS transistor; a first pull-down device coupled to a back gate of the NMOS transistor; and a second pull-down device coupled to the back gate of the NMOS transistor, wherein the pull down device is controlled by a power supply node and the control node of the PMOS transistor.

On resistance (Ron) flatness is a concern in analog switches and one way to achieve a flatter Ron is by allowing the back-gate of the NMOS transistor to increase in voltage, producing a stronger transistor with less resistance. To allow the back-gate to rise an NMOS transistor is used as a switch to connect and disconnect the back-gate to its source. The drawback with this is during a power down condition the back-gate will be left floating and will allow higher leakage through the pass transistor.

Bus switch circuit with back-gate control during power down


A system is provided that evaluates an energy state. The system comprises a sensor, bins, and a processor. The sensor is communicatively coupled to at least one cell that is powering an electric load. The sensor is operative to collect samples, each representing a measure of current discharged from the at least one cell during a discharge event. The bins are stored in a memory, and are accessible by the processor. The processor is programmed to sort the collected samples into bins based upon sample value. The processor is also programmed to create a use estimate based upon samples sorted into their corresponding bins. Yet further, the processor is programmed to determine a fractional depletion for each bin, each fractional depletion being a quotient that is computed by dividing an expected value for that bin by the use estimate for that bin.

The present disclosure relates in general to battery management, and in particular, to the evaluation of a battery state based upon a fractional depletion estimation.
Industrial batteries represent a significant operating cost for operators of fleets of industrial vehicles. In this regard, operating cost is realized in both servicing the battery (e.g., recharging the battery, performing maintenance on the battery, etc.) and in replacement of a worn out battery.
Lead-acid batteries represent a predominant type of industrial battery, especially for electrically operated vehicles such as forklift trucks. However, despite over one hundred years of proven reliability in use and relatively low acquisition cost per kilowatt hour, lead-acid batteries, like all batteries still require service and eventual replacement.

Fractional depletion estimation for battery condition metrics


Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.

This invention is in the field of semiconductor integrated circuit manufacturing, and is more specifically directed to the fabrication of metallization conductor layers according to damascene processes.
In the field of integrated circuit manufacturing, a fundamental goal is to design and manufacture integrated circuits that are as small as possible. As is well known in this art, the manufacturing cost of an integrated circuit corresponds strongly to the wafer area occupied by each integrated circuit die or chip. This is because the chip area correlates directly to the number of possible integrated circuits per manufactured wafer, and because the theoretical yield, for a given manufacturing defect density, increases as chip area decreases. In addition, the smaller feature sizes that result in decreasing chip area provide improved device performance and increased functionality per unit area.
An important advance that has reduced the necessary chip area for modern integrated circuits is the technology for forming multiple levels of metal conductors. Increases in the number of available metal levels has provided dramatic reduction in chip area and increased device and functionality density.
Of course, the implementation of multiple metal levels presents many challenges and tradeoffs. The cross-sectional area of each metal conductor is preferably minimized, especially in the lower levels, to permit overlying levels to make connections to lower metal levels and to underlying active devices. These narrower-pitch metal lines require high resolution photolithography. In addition, because current density increases with decreasing conductor cross-sectional area, the vulnerability of the finished conductors to electromigration is increased for these narrow pitch conductors. Another rule pertains to the aspect (height-to-width) ratio between metal layers. These factors affect the selection of materials and fabrication methods for modern integrated circuit metallization.
Copper has become a popular metallization material in modern integrated circuits, replacing aluminum in many instances. Copper is significantly more conductive than aluminum, and is also less vulnerable to electromigration failure than aluminum. In modern processes, because of the difficulty of chemically etching copper metal, damascene processes are often used to form multiple levels of copper conductors. In general, damascene processes refer to the inlaying of a metal into etched grooves or trenches that define the conductor lines. In contrast, traditional metallization is formed by the depositing of a metal layer over insulating films on the wafer surface, followed by the patterned etching of the metal film to define the conductors.
According to conventional "single damascene" processes, vias are etched through an interlevel insulating film at locations at which the conductor is to contact underlying elements, which may be portions of active semiconductor devices or metal conductors in previous levels. The vias are then filled with metal, such as copper, typically by electrochemical deposition (e.g., electroplating). Another conductive material, such as tungsten or aluminum, may also be used to fill the vias. Chemical-mechanical polishing (CMP) is then performed to remove excess copper (or other conductive material) from the surface of the insulator, leaving the conductor inlaid within the vias. An intrametal insulator layer is then deposited over the structure, and trenches are etched through the intrametal insulator layer at those locations at which the conductors are to run laterally along the surface of the device. The trenches are generally etched to expose the top of the filled vias to allow contact to the underlying elements through the vias. Copper metal is then deposited overall, again typically by electroplating. After deposition, the copper is planarized (e.g., by CMP) to leave the conductors in this level inlaid into the intrametal insulating film. The via and trench damascene process may be repeated for additional metal levels in the integrated circuit structure, with as many as eight levels being formed in modern manufacturing processes.
Dual damascene copper metal processes refer to metallization systems in which both the trenches and vias are simultaneously filled with the copper metallization. "Trench first" dual damascene processes refer to those processes in which trenches are etched into the insulator before the vias are etched, while "via first" processes define and etch the vias prior to trench etch. In either case, copper metal is simultaneously deposited into the trenches and vias, typically by electrochemical deposition (e.g., electroplating). The damascene inlay is then completed by CMP of the structure.
In both single and dual damascene processes, the use of a cap layer to overlie the insulating layers is known. These cap layers serve to protect the surface of the insulating layer during via and trench etches. This protection is especially important in those processes in which the interlevel and intrametal insulating layers are formed of low dielectric constant materials, such as organosilicate glass (OSG). In this case, the cap layer remains in place under the patterned photoresist, and protects the OSG film from punchthrough by the etch if the photoresist is partially or fully eroded during the etch, or during subsequent etches such as those used to clear etch-stop layers at via bottoms. This cap layer is also referred to as a hardmask layer, considering that the layer assists in defining the locations of trenches and vias.
By way of further background, silicon nitride is a known cap layer material in damascene processes. Examples of silicon nitride cap layers at various stages of damascene processes are described in U.S. Pat. No. 6,424,044, U.S. Pat. No. 6,127,258, and U.S. Pat. No. 6,465,340.
It has been observed, in connection with this invention, that the use of a silicon nitride cap layer is less than optimal in modern damascene processes, especially in defining extremely small vias. FIGS. 1a through 1c illustrate an example of a conventional via etch, as used in connection with a conventional damascene metal process. In this example, referring first to FIG. 1a, underlying conductor 2 is disposed within an insulating layer 1; for example, conductor 2 may be a copper conductor in a lower damascene metal level, or alternatively may be a semiconductor element such as a diffused region or a transistor gate. In any event, active semiconductor elements, such as transistors and passive components, are present within or beneath insulating layer 1, in the conventional manner. Etch-stop layer 3, typically formed of silicon carbide, is disposed over conductor 2, and low dielectric constant ("low-k", or "ultra-low-k") insulator layer 4 is disposed over etch-stop layer 3. In modern processes, insulator layer 4 is often formed of an OSG material, examples of which include BLACK DIAMOND silicon oxide-based CVD low-k film available from Applied Materials, Inc.; CORAL low-k dielectric film available from Novellus Systems Inc.; and SiLK dielectric material available from Dow Chemical Co. Examples of ultra-low-k materials include ORION 2.2 ultra-low-k dielectric material available from Trikon Technologies, Inc.; BLACK DIAMOND 2 insulator material available from Applied Materials, Inc.; p-SiLK dielectric material available from Dow Chemical Co.; and LKD-5109 low-k dielectric material available from JSR Corporation. Typically, insulator layer 4 is deposited using CVD techniques, although spin-on techniques may also be used. Silicon nitride cap layer 5 overlies insulator layer 4, as shown in FIG. 1a. The photolithographic patterning of the location of a via to be etched through insulator layer 4 is defined by patterned photoresist 6, which is photolithographically exposed and developed in the conventional manner, in combination with bottom antireflective coating (BARC) layer 7, which is disposed under photoresist 6 as shown.
FIG. 1b illustrates the structure of FIG. 1a, following a conventional via etch through low-k insulating layer 4, using photoresist 6 as a mask. This etch is a conventional plasma etch, with active species selected according to the material of insulating layer 4, as known in the art. Residue 6′ remains at the surface, and consists of remaining portions of photoresist 6 and BARC layer 7. Following this etch process, etch-stop layer 3 is exposed at the bottom of the via. Because the material of etch-stop layer 3 (e.g., silicon carbide) is resistant to the via etch, it remains substantially intact at this point. However, as evident from FIG. 1a, silicon nitride cap layer 5 is not completely impervious to the via etch. Rather, cap layer 5 may be etched, or eroded, in a lateral direction due to its lower etch resistance; as a result, the via critical dimension (CD) will widen (increase). This undesirable widening of the via through insulating layer 4 continues with the clearing of etch-stop layer 3 from the bottom of the via; despite the selection of an etchant species and condition that is suitable for etching etch-stop layer 3, silicon nitride cap layer 5 will be further laterally etched, so that it and the underlying portions of insulating layer 4 that are exposed after cap layer 5 pulls back are both etched. The resulting via in FIG. 1c is thus significantly wider than the via dimensions defined by the patterning of photoresist 6 (FIG. 1a). By way of example, this CD increase may be as much as on the order of 30 nm in via width, for a via having a desired width of 140 nm, resulting in a CD increase of on the order of 20%.
This widening of the via dimensions is typically referred to as CD increase, referring to an increase of the critical dimension of the via width. In modern processes, via width is a critical dimension, particularly in repetitive structures such as memory arrays, because the size and spacing of the etched vias largely determine the density of the conductors in the current metal level, and may indirectly also define the density of the underlying structures 2.
However, because the via width is a critical dimension that defines the overall density of conductors and contacts in a given level, the photolithography process used in defining via locations is likely to be pushed to its manufacturable limits. For example, in modern processes, so-called "193 nm" photolithography, using exposure wavelengths at least as short as 193 nm, are used to define via locations. Because the via photolithography process is already at its limits, especially at 193 nm or lower wavelengths, the via pattern cannot be adjusted by undersizing the vias further, to account for the CD increase, during via etch and etch-stop layer etch, using the silicon nitride cap layer. Rather, the integrated circuit design rules must be loosened to allow for the widened vias.
By way of further background, silicon carbide is also a known material for use as the cap layer in damascene processes. An example of this use of a silicon carbide cap layer is described in U.S. Pat. No. 6,472,333. Referring to FIG. 1a, according to this conventional approach, silicon carbide would serve as cap layer 5.
However, it has been observed, in connection with this invention, that the via etch process using silicon carbide as a cap layer is vulnerable to the failure mechanism that is commonly referred to as "resist poisoning". Low-k and ultra-low-k films, such as insulating film 4 in FIG. 1a, are relatively porous materials. Nitrogen-containing materials are typically used in preceding processes, including CMP and surface pretreatment prior to etch-stop layer deposition. This nitrogen, either as an amine or in the form of ammonia, tends to be trapped in residue from the CMP process. These contaminants infiltrate the OSG film and remain within the pores. The slurry used in CMP is especially likely to provide this infiltrating nitrogen, in the form of ammonia or amine. Once the nitrogen contaminant is present in insulating film 4, it has a tendency to outgas from the film in later processes, such as trench or via pattern in a single damascene copper metal process. The deleterious effect of the nitrogen is often seen in photolithography operations that use chemically-amplified positive photoresists, such as is common in the 193 nm photoresists used for critical dimension patterns. Chemically-amplified photoresists, as known in the art, rely upon a photo-acid-based chemical reaction to transfer the exposure pattern through the complete depth of the photoresist layer, from the surface locations that were exposed to the UV light energy. However, at those locations at which nitrogen has outgassed, the acid-based reaction will stop upon reaching the basic (i.e., the amine) contaminant. This incomplete exposure of the photoresist layer at these locations, which will be at the vias in via patterning, will cause a killing physical defect, namely a missing via. It has been observed, in connection with this invention, that silicon carbide is a poor barrier to the outgassed nitrogen or ammonia, leaving the via process vulnerable to this failure mechanism.

Dual cap layer in damascene interconnection processes


A data management and storage (DMS) cluster of peer DMS nodes manages resources of a multi-tenant environment. The DMS cluster provides an authorization framework that provides user access which is scoped to the resources within a tenant organization and the privileges of the user within the organization. To authorize an action on a resource by a user, the DMS cluster determines determine user authorizations associated with the user defining privileges of the user on the resources of the multi-tenant environment, and organization authorizations associated defining resources of the multi-tenant environment that belong to the organization. The DMS cluster authorizes the action when the user authorizations and organizations authorized indicate that the action on the resource is authorized.

The amount and type of data that is collected, analyzed and stored is increasing rapidly over time. The compute infrastructure used to handle this data is also becoming more complex, with more processing power and more portability. As a result, data management and storage is increasingly important. One aspect of this is reliable data backup and storage, and fast data recovery in cases of failure. Another aspect is data portability across locations and platforms.
At the same time, virtualization allows virtual machines to be created and decoupled from the underlying physical hardware. For example, a hypervisor running on a physical host machine or server may be used to create one or more virtual machines that may each run the same or different operating systems, applications and corresponding data. In these cases, management of the compute infrastructure typically includes backup and retrieval of the virtual machines, in addition to just the application data. However, various different platforms are offered for virtualization, including VMware, Microsoft Hyper-V, Microsoft Azure, GCP (Google Cloud Platform), Nutanix AHV, Linux KVM (Kernel-based Virtual Machine), and Xen. While users may desire to have their applications and data be machine-agnostic, it typically is not easy to port applications and data between different platforms.
In addition, there often are economies of scale to operating larger compute infrastructures. However, the capacity of the infrastructure may be too large to be consumed by just one organization. Thus, it may be advantageous for multiple organizations, each with many users, to share a compute infrastructure. In such a situation, it is important that the different tenants are isolated from each other. Even though they are sharing a common compute infrastructure, users from one tenant typically do not have rights to access the resources of another tenant. Users that do not belong to any of the organizations may also require access to certain resources, for example to maintain the compute infrastructure.
Thus, there is a need for better approaches to managing and storing data, particularly across different virtual machine platforms and for multi-tenant situations.

Multi-tenant authorization framework in a data management and storage cluster