A UV irradiation apparatus, which includes a UV lamp installed in a chamber for generating UV rays; a vacuum chuck installed below the UV lamp for supporting and moving a wafer; and, a reflector surrounding the UV lamp for concentrating UV rays on the vacuum chuck. The apparatus further includes heating blocks for controlling the temperature at both sides of the vacuum chuck. Thus, it is possible to maintain an essentially constant temperature around the wafer supported by the vacuum chuck. As a result of the temperature control, when a protection tape attached to the front side of the wafer is irradiated with UV rays, an adhesive of the protective tape can be effectively degraded by a chemically reaction under optimum conditions, to thereby easily detach the protection tape from the wafer.

The present invention relates to an ultraviolet (UV) irradiation apparatus which may be used in a process for manufacturing a semiconductor device, and more particularly, to a UV irradiation apparatus adapted to facilitate detaching a protective tape from the front side of a back-ground wafer.
In general, a semiconductor device is manufactured on a wafer which is subject to many processes. Good products are selected out of the manufactured semiconductor device by measuring their electrical characteristics, and the selected semiconductor devices are then packaged. In the present process, the wafer is formed to be thin and results in at least one semiconductor device which has been processed to be thin. A method of back-grinding a wafer is widely used as a means to thin the wafer for the semiconductor device after the process of manufacturing it is completed. The process of back-grinding is performed by the steps of: attaching a protection tape to the front side of the wafer in order to protect the semiconductor device; thinning the wafer by back-grinding while the protection tape is attached, by back-grinding; and eliminating the protection tape attached to the front side of the back-ground wafer. In the subsequent process step to eliminate the protective tape backing, a UV irradiation apparatus is widely used. The protective backing has an adhesive coated on one side of the protection tape to cause the tape to adhere to the wafer, and this adhesive coating can be caused to lose its adhesive property via a chemical reaction when exposed to UV. Accordingly, the wafer with the protective tape adhered thereon is usually transferred to the UV irradiation apparatus in order that the upper portion of the tape can be irradiated. Therefore, the UV rays cause the adhesive property to be lost so that the protection tape can be removed from the wafer. Such chemical reaction of the adhesive is affected by both the temperature and the distribution of the UV irradiation on the adhesive.
The conventional UV irradiation apparatus consists of a UV lamp for generating UV rays which is fixed in a chamber, a wafer transferor installed under the UV lamp for transferring the wafer, and a reflector adapted to surround the UV lamp in order to concentrate UV on the wafer and wafer transferor. In such a process step, a vacuum chuck or a roller is widely used as the wafer transferor.
In general, the transferring method is by a vacuum chuck which rotates and at the same time, horizontally transfers the wafer lying thereon to the UV irradiation apparatus, or only horizontally transfers it. In such a process, when the vacuum chuck rotates the wafer, the wafer thereon is rotated on its center axis. Accordingly, this results in the central portion of the wafer being concentratedly irradiated with more UV rays than that of the peripheral portion thereof. Likewise in the wafer transfer method which utilizes a roller, the wafer is horizontally moved according to a rotating movement of a plurality of rollers upon which the wafer lies. A desired uniform smooth transfer movement is difficult to obtain in such a process. Since each of the rollers can neither rotate at a uniform speed nor transfer a uniform force to the wafer, a smooth movement of the wafer is prevented. As the result it is difficult to automate such a step without jamming occurring, which presents manufacturing problems. If a successive wafer is prevented from proceeding to or from the UV irradiation apparatus, it results in a halt to the desired UV irradiation process step which cannot be performed. Another difficulty in the irradiation process is caused by the UV lamp, which usually generates not only the desired UV rays but also undesired infrared and visible rays. Thus, the wafer is also irradiated with the undesired infrared rays and visible rays. This usually leads to an increase in the temperature of the wafer and thereby causing the wafer to suddenly cool down to room temperature after completing the UV irradiation. Thus, the undesired quick-cooling problem prevents the adhesive from completely losing its adhesive property before cooling.
In the conventional UV irradiation apparatus, the UV lamp is fixed in a chamber so that it is impossible to freely control a distance between the UV lamp and a wafer. Accordingly, since the amount of UV irradiated on the wafer cannot be appropriately controlled, it is difficult to maximize a chemical reaction within the adhesive to cause it to release the wafer. The temperature around the wafer is a result of the heat generated only by the UV lamp and it is difficult to freely provide an optimum temperature where the adhesive can lose its adhesive property.
As pointed out above, in the conventional UV irradiation apparatus where a wafer is transferred by rollers, the horizontal movement of wafer is not smooth. Therefore, when the wafer after UV irradiation is loaded on a carrier, the wafer can be damaged or broken due to colliding with the carrier.
By the conventional UV irradiation apparatus as described above, the whole surface of the wafer cannot be uniformly irradiated with UV rays, which makes it difficult to freely control the quantity of UV irradiation on the wafer and the temperature of the wafer. The temperature of the wafer can be also increased by the UV irradiation apparatus lamp. Such a UV lamp also results in irradiation of infrared rays which generate heat, and further the heated wafer suddenly cools to a room temperature after that the UV irradiation on the adhesive on the wafer surface sometimes does not lose its adhesive property. In such a case, it is difficult to easily eliminate the protective tape from the wafer surface.


A semiconductor device includes a semiconductor substrate, a first electrode that is formed over said semiconductor substrate, a capacitive insulating film that is formed on the first electrode and is made of a metal oxide ferroelectric, a second electrode that is formed on the capacitive insulating film, an insulating film that has a first opening exposing a portion of an upper side of the second electrode and is formed so that it covers the first electrode, the capacitive insulating film, and the second electrode, a first barrier film having an amorphous structure which is formed inside the first opening and on the insulating film, and a wiring film that is formed over the first barrier film.

1. Field of the Invention
The present invention relates to a semiconductor device with a wiring structure having good electrical properties in a connection with a capacitor that uses a metal-oxide dielectric.
A ferroelectric random access memory (FeRAM) is a high-speed nonvolatile memory using the hysteresis property of a ferroelectric material. A FeRAM has excellent features, such as high-speed read/write operations that are as fast as a dynamic random access memory (DRAM) and lower power consumption, for instance.
When a capacitor is formed with a ferroelectric material of a metal oxide, an annealing treatment in an oxygen atmosphere at a high temperature (600-800 degrees Celsius) is required to recover the properties of the ferroelectric material after sintering or etching. Because of this, precious metal such as platinum (Pt) or iridium (Ir) having excellent oxidization resistance properties is used for the upper and lower electrodes adjacent to a ferroelectric. Especially, Pt is best used for the electrodes in consideration of process-stability and workability.
Japanese Patent Publication JP-A-10-256503 (especially pages 5-8 and FIG. 1) shows a semiconductor device with a ferroelectric capacitor. In this semiconductor device, aluminum (Al) and Pt are used for the main wiring material and the main electrode material, respectively. In general, it is known that Al and Pt excessively yield chemical reactions. A void is formed in an Al wiring in these chemical reactions. Also, if much chemical reactions are provoked, the Al wiring pattern will be separated. Therefore, an anti-reaction layer is formed on a capacitor electrode in order to prevent chemical reactions between Al and Pt.
2. Background Information
As described above, Pt, which is used for an electrode material of a ferroelectric capacitor, chemically reacts with Al, which is a general wiring material, and an Al2Pt compound is produced. As a result, a void is formed in Al wiring. Also, if a large number of chemical reactions are provoked, the Al wiring pattern will separate. Therefore, it is common to form a barrier film such as titanium nitride (TiN) between a Pt electrode and the Al wiring. However, the crystal structure of TiN is a columnar crystal structure. Therefore, Al atoms can easily spread through the crystal grains of TiN to a surface of the Pt electrode. One of the countermeasures for this could be to improve the barrier properties by lengthening the diffusion path of Al by forming a thick TiN film. However, if a thick TiN film is formed with a method such as sputtering, an overhang growth of TiN will be enhanced on a contact hole used to connect a capacitor electrode with wiring. Also, Al, a wiring material, cannot be implanted into a contact hole sufficiently. Therefore, deterioration of the electrical properties will be provoked. Thus, a sufficient barrier effect cannot be obtained just by forming a TiN barrier film on an interface between a Pt electrode and Al wiring.
The semiconductor device described in Japanese Patent Publication JP-A-10-256503 includes an anti-reaction layer between the Pt electrode and the Al wiring of a capacitor. In other words, it includes a barrier layer, a stopper layer, and an adhesion layer. However, this anti-reaction layer is formed on a capacitor electrode, and integrated with a capacitor electrode. Therefore, the thickness of the electrode itself can be increased, and eventually the thickness of the whole semiconductor device structure can be increased. Also, in this semiconductor device, a contact hole used to connect a capacitor electrode with wiring is etched after the anti-reaction layer is formed. However, the dielectric film is damaged in this etching process. Therefore, an anneal in an oxygen atmosphere at a high temperature is normally conducted to recover the properties of the dielectric film, although this is not described in Japanese Patent Publication JP-A-10-256503. However, there is a possibility that the anti-reaction layer already formed will be oxidized, its electrical properties will be reduced, and the anti-reaction layer will be separated in this anneal treatment. Also, in this semiconductor device, a stacked capacitor structure is employed, and an anti-reaction layer is formed only on an upper electrode of a capacitor. If a contact needs to be formed upward from both upper and lower electrodes of a capacitor, an anti-reaction layer needs to be formed for a lower electrode. However, forming an anti-reaction layer for a lower electrode is not described in this patent publication.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method for manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Ferroelectric type semiconductor device having a barrier TiO and TiON type dielectric film


The present invention discloses a method and a system for transmitting an uplink signal between a plurality of carriers, user equipment, and a base station, so that channel reciprocity can be effectively utilized. The method in embodiments of the present invention includes: receiving indication signaling sent by a base station; and transmitting an uplink signal in a target subframe of a corresponding target carrier based on the indication signaling.

In a Long Term Evolution (LTE) system, channel estimation is required. Channel estimation is a process of estimating a model parameter of an assumed channel model when receiving data.
Currently, for a carrier that supports both uplink transmission and downlink transmission, it is beneficial to perform channel estimation by using sounding reference information (or Sounding Reference Signal, SRS) and channel reciprocity.
However, user equipment (UE) generally can aggregate a larger quantity of downlink carriers than a quantity of uplink carriers. As a result, when uplink transmission resources are in shortage, some downlink carriers with downlink transmission cannot be used for uplink transmission, for example, transmission of an uplink SRS signal. Obviously, for these downlink carriers, channel reciprocity cannot be effectively utilized.

Methods and apparatus for communication an uplink signaling in a target subframe


An insulating cover for covering an opening in a torpedo car is disclosed. The insulating cover includes an upper and lower wire mesh layer and an insulating layer positioned between the wire mesh layers. Tie devices secure the wire mesh layers together and hold the insulating layer in position. At least one ferromagnetic plate is provided, whereby each ferromagnetic plate provides a lift point for lifting the insulating cover, such as with an electromagnet or the like.

1. Field of the Invention
The present invention relates to heat retention within torpedo cars, more specifically toward insulating covers which are configured for easy and safe positioning on torpedo cars.
2. Background Information
Torpedo cars, also referred to as ladle cars, are employed for carrying molten metal from one location to another. Typically, the hot metal is transported between the blast furnace and the melt facility by a torpedo car. After molten metal is poured from a torpedo car, it is desirable to retain the temperature within the container as high as possible between emptying and subsequent refilling of the torpedo car. The temperature retention is desired to minimize the molten metal temperature loss occurring during the next refilling.
It is well known to form a shield or insulating cover to cover the opening of a torpedo car such as a wire mesh enclosed refractory containing sheet. Examples of such insulating covers can be found in U.S. Pat. Nos. 4,381,855; 4,390,170; 4,424,956 and 4,424,957. These prior art insulating covers have several disadvantages including difficulty in manually engaging and positioning these covers on the torpedo car opening with hooks or the like.
It is the object of the present invention to overcome the drawbacks of these aforementioned prior art insulating covers by providing an easily manufactured insulating cover which is configured for easy placement and removal, if necessary, on the opening of a torpedo car.


The invention provides to the user a way of ascertaining the estimated delay through a circuit, by back-annotating the estimated delay through an instantiated macro into the HDL circuit description. Reported delays may include maximum delay, typical delay, and/or minimum delay on the critical path. Using well-known techniques for responding to textual keywords, a software procedure call is initiated whenever an HDL library macro instantiation is detected. The procedure looks up the associated timing data for the macro in a macro or device speeds file and back-annotates the data into the HDL circuit description, preferably as a comment directly following the macro instantiation. In another embodiment, the delay information is added when the file is saved. In yet another embodiment, the delay information is not added to the HDL file, but is written to a report file or displayed on the screen.

1. Field of the Invention
The invention relates to design entry of electronic circuits. More particularly, the invention relates to a method for annotating timing into an HDL description of a circuit.
2. Description of the Background Art
As the electronics industry evolves, the typical operating speed of integrated circuits (ICs) changes frequently. Therefore, it is important for an IC designer to be able to rapidly determine the speed at which a signal will traverse a path through a proposed circuit in the IC. If the signal cannot traverse the path within the desired time period, the circuit may have to be modified or replaced. If the signal will predictably traverse the path in less than the available amount of time, some of the extra time may be used to perform other logical functions. Therefore, it is important to IC designers to be able to predict, with at least some degree of accuracy, the speed at which various portions of their circuits will operate. One field in which this requirement is particularly important is that of Field Programmable Gate Arrays (FPGAs), where a circuit may have different delays when implemented in different speed grades or in different FPGAs, and an FPGA may be selected for use in a system based primarily on the speed of the circuit as implemented in that particular FPGA.
One method for estimating circuit operating speed in an FPGA is a manual estimation technique that involves tracing each delay in the circuit manually and looking up delay values in tables provided by the FPGA manufacturer. One source for such information is "The Programmable Logic Data Book" (hereinafter referred to as "The Xilinx 1996 Data Book"), published in September, 1996 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Suppose, for example, that an FPGA user wishes to predict the delay through a simple circuit such as a 2-input exclusive-OR (XOR2) gate, in an XC4003E FPGA device in the -2 speed grade. (Each Xilinx FPGA is assigned, after testing, a number preceded by a dash to indicate to which of several "speed grades" a particular packaged device is assigned. Each speed grade is guaranteed to meet a specific set of corresponding timing requirements.) The FPGA user must first be familiar enough with the architecture of the XC4003E device to realize that the XOR2 circuit can be implemented in a single function generator. The FPGA user can then predict the corresponding delay by consulting page 4-85 of the Xilinx 1996 Data Book, which is incorporated herein by reference, and a portion of which is reproduced in FIG. 1. Consulting this page, which is devoted to "XC4000E CLB Switching Characteristic Guidelines", the FPGA user looks under the heading "Combinatorial Delays" and identifies the symbol "TILO" as representing the delay through a single function generator. "TILO" for the -2 speed grade is 1.6 ns, therefore the delay for an XOR2-gate in an XC4003E-2 device is 1.6 ns. However, this estimated delay does not take into account such factors as net delay in reaching the inputs of the gate, nor a net delay on the gate output. In this case, the FPGA user might estimate a net delay of 0.5 ns, for a total delay through the XOR2-gate of 2.1 ns (1.6 ns block delay +0.5 ns net delay). For some circuits, these net delays can be larger than the delay through the function generator.
As a second example, consider a binary 8-bit counter such as the one shown in FIG. 2. This 8-bit counter comprises eight flip-flops (200-207). Each flip-flop corresponds to one bit of the counter, with flip-flop 200 generating bit Q0 (the least significant bit), flip-flop 201 generating bit Q1, and so forth up to flip-flop 207 generating bit Q7 (the most significant bit). Each flip-flop is reset by signal CLR. The data input D of flip-flop 200 is driven by bit Q0, inverted by inverter 210. Therefore, bit 0 toggles with every active edge on clock CK. The data inputs D of flip-flops 201-207 are driven by XOR2-gates 211-217, respectively. XOR2-gate 211 has as inputs Q1 (the related counter bit) and carry-in signal CIN1 (which could equally correctly have been labeled Q0 or as carry-out signal COUT0). Carry-in signal CIN1 and bit Q1 are also ANDed together in AND2-gate 221 to generate carry-out signal COUT1 (which is labeled CIN2, since it also forms the carry-in signal for the next bit). The other XOR2-gates 212-217 and AND2-gates 222-226 are similarly connected to the outputs Q2-Q7 of their corresponding flip-flops 202-207.
To manually estimate the delay through the counter the FPGA user must understand how the logic will be mapped into FPGA configurable logic blocks (CLBs) and function generators in the target FPGA device. When the counter shown in FIG. 2 is mapped into an XC4003E device, two bits of the counter will be placed in each CLB, as shown in FIG. 3. FIG. 3 indicates (by way of boxes 330, 332, 334, 336) the mapping of the logic in the counter into four CLBs. The maximum operating speed of this counter is determined by the settling time of the carry chain from least significant to most significant bit. The critical path (the path determining the maximum operating speed of the circuit) therefore comprises the path from clock CK, through flip-flop 200 to output Q0), then along the carry chain through AND2-gates 221, 222, 223, 224, 225, and 226, through XOR2-gate 217, and a setup time at flip-flop 207. Net delays from flip-flop output Q0 to the input of AND2-gate 221, and from each AND2-gate to the succeeding AND2-gate, must be added as well. The FPGA user can therefore calculate the estimated speed of the counter by summing: 1) clock-to-out for flip-flop 200; 2) six times the estimated average net delay from a flip-flop or AND2-gate output to an AND2-gate input; 3) five times the delay through an AND2-gate (one function generator delay each); 4) the delay through AND2-gate 226 and XOR2-gate 217 (one function generator delay for both); and 5) the setup time on input D of flip-flop 207. Consulting the data book information in FIG. 1, and estimating the average net delay based on previous experience with FPGAs, the estimated delay through the critical path for the counter of FIGS. 2 and 3 can be calculated: ##EQU1##
However, to provide a third example of manual delay estimation, XC4000E CLBs also offer special fast carry logic, and library macros (schematic or HDL circuit descriptions or symbols representing commonly used circuits, such as counters) that use this special logic are provided to XC4000E users. Speed estimation methods for counters and adders that use the fast carry logic are explained in Xilinx Application Note XAPP018 (Version 2.0), entitled "Estimating the Performance of XC4000E Adders and Counters", published Jul. 4, 1996 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which is incorporated herein by reference. Briefly, the propagation delay of an 8-bit counter using fast carry logic comprises the following delays: 1) the delay in getting onto the carry chain in the first CLB, corresponding to CLB 330; 2) two times the delay on the carry chain through a single CLB (two CLBs of two bits each, corresponding to CLBs 332 and 334); and 3) the delay in getting off the carry chain in the fourth CLB, corresponding to CLB 336. The delay can therefore be calculated using the formula: EQU Delay=TOPCY+(2*TBYP)+TSUM
Consulting the data book information in FIG. 1, the estimated delay of this counter in an XC4003E device with a -2 speed grade is found to be: EQU Delay=2.1 ns+(2*0.6 ns)+2.6 ns=5.9 ns.
Therefore, it is seen that the delay of even a simple circuit such as a counter may be heavily dependent on the particular implementation used in the macro, and the manual estimation method may be relatively involved.
A more automated method currently used for estimating the speed of an FPGA circuit involves mapping, placing, and routing the design, and writing out a netlist description of the completed design. (A "netlist" is a description of a circuit comprising a list of low-level circuit elements or gates and the connections (nets) between the outputs and inputs thereof. A netlist is typically stored as one or more computer files.) The next step is to run a software tool that inserts delays into the netlist corresponding to the delays that will be incurred by a signal traversing each element in the netlist. These delays are typically read from a file called a device speeds file. (A device speeds file may include delays for one or more different FPGAs or other programmable ICs, or may include delays for one or more elements in a standard cell library that may be used for designing custom ICs.) The device speeds file may be encrypted. A given FPGA device speeds file is typically specific to a particular FPGA device, and may include information for several different speed grades of the device. After inserting timing delays into the netlist, the software tool produces a report on the overall speed of the resulting design, or it can be directed to report the delay associated with a particular path through the design. One such software tool is the XDelay software from Xilinx, Inc. A step-by-step description of how to use the XDelay software to report path delays in a mapped, placed, and routed FPGA design is included in pages 15-39 through 15-43 of the "XACT Viewlogic Interface User Guide", published April, 1994, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which are incorporated herein by reference. These methods typically produce relatively accurate reports of timing delays to be expected from the circuit when programmed into an FPGA.
One automated method for displaying timing for an FPGA circuit is described by Lawman and Wells in U.S. Pat. No. 5,673,198, "Concurrent Electronic Circuit Design and Implementation", which is incorporated herein by reference and title to which is held by the assignee hereof. However, this method requires software post-processing to map, place, and route the circuit before a timing estimate can be provided. This post-processing is often time-consuming.
FIG. 4 shows a schematic for an XOR2-gate that is used when designing circuits for Xilinx FPGAs using the Workview schematic entry environment from Viewlogic Systems, Inc. The XOR2-gate is an element in a library of macros provided by Xilinx or by Viewlogic Systems, Inc. to their customers. This XOR2-gate schematic is also a simulation model used to perform logic and timing simulations of the XOR2-gate and of higher-level schematics incorporating this gate. The schematic includes timing information for the gate. As shown in FIG. 4, the schematic comprises two buffer symbols 401, 402 and one symbol 403 representing the exclusive-OR function. Each of symbols 401, 402, 403 has two associated timing variables. For example, symbol 403 has the notation "TPLH=@ODLY1", which means that the Timing Period on the Low to High transition when passing through this logic is represented by a variable "ODLY1". Similarly, the notation "TPHL=@ODLY0" on symbol 403 means that the Timing Period on the High to Low transition is represented by a variable "ODLY0".
FIG. 5 shows the Workview XOR2 schematic symbol that corresponds to the XOR2 schematic of FIG. 4. (Timing attributes have been made visible using the Workview "Change Attributes Visible" command. Attributes other than timing variables are not shown in FIG. 5.) The timing variables from the schematic of FIG. 4 are also present in the schematic symbol of FIG. 5, and in FIG. 5 they are assigned default values. For example, the notation "@ODLY1=" means that the default delay for the low to high transition on symbol 403 is 1 timing unit, or 0.1 ns. (The basic time unit for Workview is 0.1 nanoseconds, or 100 picoseconds.) The notation "@IODLY0=0" in FIG. 5 means that the default delay for the high to low transition of symbol 402 is 0 ns. These attributes on the symbol are the Workview software's method of passing the timing information from the simulation model (shown in FIG. 4) to the Workview simulator. This timing information is nominal and does not reflect the performance of the circuit in a mapped, placed, and routed design. Therefore, it has no value for delay estimation purposes.
When the XOR2-gate of FIGS. 4 and 5 is converted to a Viewsim.TM. simulation netlist, the simulation netlist is written as appears in FIG. 6. (Viewsim is the Workview simulation software tool. Viewsim is a trademark of Viewlogic Systems, Inc.) The netlist description of FIG. 6 provides an example of how timing delays can be incorporated into a netlist. In this example, each symbol is represented by a single line of text. For example, symbol 403 is represented by line 600. FIG. 7 shows another type of netlist showing incorporation of the default delays. The netlist of FIG. 7 is in Xilinx. Netlist Format (XNF). In this netlist, symbol 403 is represented by lines 12 through 16 (labeled 700). To obtain a netlist having actual delays rather than the default values for TPHL and TPLH, the circuit must be mapped, placed, and routed, and the resulting netlist must be back-annotated with delays using the XDelay program.
An advantage to this automated method is that it is no more difficult for a user to obtain the delay through a large, complicated circuit than it is through a simple circuit such as an XOR2-gate, although it may take longer because of increased software execution time. A disadvantage of this method for estimating FPGA circuit delays is that the circuit must be implemented (mapped, placed, and routed) before the user can receive any information about the speed of the circuit. If design changes are made as a result of the timing information, the circuit must be reimplemented to assess the results of the changes. Further, in order to implement the circuit, the circuit must be transformed into a complete FPGA design, i.e., input/output pads must be added, and each circuit output must either drive some destination circuitry or be marked so the software will retain what appears to be unused logic. This process can therefore be time-consuming. Some FPGA users prefer to make one or more iterations of the design process based on a manual estimation of the delay through the circuit, before proceeding to the accurate estimations produced by the above method.
Another common method of describing a circuit, other than with a schematic, is by textual description in a Hardware Description Language (HDL). There are several standard HDL languages; two commonly used HDL languages are Verilog and VHDL. In addition, there are a number of distinct coding styles for entering a circuit description in an HDL, including behavioral, dataflow, and structural descriptions. These languages and coding styles are well known in the HDL art and are not discussed in detail herein. Exemplary circuit descriptions herein are written in the Verilog language.
A common technique used in HDL circuit descriptions is the instantiation (essentially the inclusion of a copy by reference) of a previously implemented macro. The following Verilog code fragment shows the instantiation of an exemplary macro:
CPU.sub.-- core U1 (Addr, Data, CS, CE, RD.sub.-- WR.sub.-- n, INT, Clk); PA1 DMA.sub.-- core U2 (Addr, Data, CS2!, CE2!, RD.sub.-- WR.sub.-- n, INT1!, Clk);
In this example the macro is named `CPU.sub.-- core`. This particular instance (instantiation) has a unique instance reference name U1. The list of signal names (in parentheses) is called a port list. In this example, the port list shows that the CPU.sub.-- core macro has connections to an address bus (Addr), a databus (Data), and numerous control signals (signal lines or buses) such as CS (Chip Select), CE (Chip Enable), and so forth. The port list is used to connect the macro to other portions of the design, which often includes other such instantiations. For example, in addition to instance U1 above, a design may contain an instantiated DMA core such as the following:
In this example, the two macros are connected by way of the commonly labeled signals through the macro ports in the port list. For example, the CS2! entry in the DMA core's port list indicates that the DMA is connected to bit 2 of the CPU core's CS bus, while the two macros share clock signal "Clk".
In Verilog, the port names in the instantiation port list may or may not be the same names as those used for the same ports within the library macro. However, instantiation port names are assigned to the macro ports based on the order in which they appear in the port list (as in the examples above), or alternatively can be connected in the instantiation port list using notation such as ".macro.sub.-- internal.sub.-- port.sub.-- name(instantiation.sub.-- name)".
An HDL description (which may optionally contain one or more macro instantiations) typically describes in text form the desired structure or behavior of a circuit, and the HDL description is then compiled or synthesized by HDL synthesis software to produce a netlist. This netlist may be substantially similar to a netlist produced from a schematic. The delay through an HDL circuit can therefore be estimated using the same methods used for schematic circuits, i.e., by manually estimating the delay through each element and adding the delays, or by mapping, placing, and routing the circuit and running timing estimation software such as the XDelay software from Xilinx, Inc. The manual estimation method may be more difficult with an HDL description than with a schematic description, because it is not always apparent from the HDL description (particularly a behavioral description) what circuit elements will be used to implement the circuit.
It is desirable to have a way of estimating the delay through an FPGA circuit from either a schematic description or an HDL circuit description, without consulting a data book, without manually adding together many small delays, and without mapping, placing and routing the circuit.


A mounting apparatus includes a fixed mounting structure that includes a first fixed fitting including a plurality of first flanges and a second fixed fitting. A rotatable mounting structure has a swivel fitting configured to engage and swivel with respect to the first fixed fitting. The swivel fitting includes a plurality of second flanges, one of which is configured to rest on one of the plurality of first flanges when the swivel fitting and first fixed fitting are engaged. The rotatable mounting structure also has a slide fitting configured to slide with respect to the second fixed fitting based on the swivel fitting being engaged with the first fixed fitting. An adjustment assembly is arranged at an interface between the second fixed fitting and the slide fitting. The adjustment assembly is configured to adjust an angular position of the slide fitting relative to the swivel fitting.

The subject matter disclosed herein relates to a mount for a vehicle wing, and in particular to an adjustable mount and method of adjusting the mount.
Conventional aircraft bore sight mounts include screws that extend from an object to be mounted and are affixed to the bore sight mount with a nut. Adjusting the nut adjusts the position of the mounted object. Typically, each end of the object includes multiple screws to permit three-dimensional adjustment of the object.


The present inventive concept provides a moisture prevention film including: a first moisture prevention film; a second moisture prevention film formed on the first moisture prevention film; and a third moisture prevention film formed on the second moisture prevention film, wherein a concentration of oxygen (O) of the second moisture prevention film is higher than a concentration of oxygen of each of the first moisture prevention film and the third moisture prevention film, a method of manufacturing the moisture prevention film, and an organic light emitting device including the moisture prevention film.

Organic light emitting devices are devices which have a structure where a light emitting layer is provided between a cathode injecting an electron and an anode injecting a hole and in which when the electron supplied from the cathode and the hole supplied from the anode are injected into the light emitting layer, the electron and the hole are combined to generate an exciton, and the generated exciton is shifted from an excited state to a ground state to emit light.
In the organic light emitting devices, if moisture penetrates into the light emitting layer, the light emitting layer is easily deteriorated, and for this reason, a device characteristic is reduced, and lifetime is shortened. Therefore, a moisture prevention film for preventing moisture from penetrating into the light emitting layer is provided on a top of each of the organic light emitting devices.
Hereinafter, a related art organic light emitting device will be described with reference to the drawing.
FIG. 1 is a schematic cross-sectional view of a related art organic light emitting device.
As seen in FIG. 1, the related art organic light emitting device includes a substrate 1, a light emitting part 2, and a moisture prevention film 3.
The light emitting part 2 is provided on the substrate 1. The light emitting part 2 includes an anode, a cathode, and an organic light emitting layer provided between the anode and the cathode.
The moisture prevention film 3 is provided on the light emitting part 2 to prevent moisture from penetrating into the light emitting part 2.
The related art organic light emitting device uses an inorganic insulating material as a material of the moisture prevention film 3, but since there is a limitation in a process of forming the moisture prevention film 3, a moisture prevention effect is reduced.
The inorganic insulating material is formed through a chemical vapor deposition (CVD) process. However, when a defect such a pin hole occurs in a thin film in the deposition process, the thin film grows, and for this reason, the defect such as the pin hole grows together. That is, since the defect such as the pin hole is continuously formed from a lower portion to an upper portion of the moisture prevention film 3, external moisture can easily penetrate into the light emitting part 2 through an area where the defect occurs, causing a problem where the light emitting part 2 is easily deteriorated.
Moreover, in a case where the inorganic insulating material is deposited through an atomic layer deposition (ALD) process, a moisture anti-penetration effect is enhanced, but a deposition rate is reduced, causing a reduction in productivity.

Film for preventing humidity from percolation and method for manufacturing the same


Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

The present invention is related generally to computer processors and more specifically to computer processor enhancements suitable for virtual machines.
The notion of a virtual machine has been a topic of academic research for many years. However, the idea has been popularized by Sun Microsystems, Inc. with its Java programming language and runtime environment. The Java virtual machine is software that acts as an interface between compiled Java binary code (known as bytecode) and the underlying hardware platform (e.g., a microprocessor) that actually implements the bytecodes. Once a Java virtual machine has been provided for a platform, any Java program can run on that platform.
As the name implies, a virtual machine is an abstraction (a virtual representation) of a physical processor and typically comprises virtual counterparts of a conventional processor. For example, the Java virtual machine specifies elements such as an instruction set, a set of registers, a stack, a "garbage heap," and a method area. The real implementation of this abstract or logically defined processor is the native machine code executed by the real processor or be built into the microchip processor itself (so-called microcode).
An area in which the virtual machine is finding application is in the use of smartcards. Typically, a smartcard is a card that is embedded with either a microprocessor and a memory chip or only a memory chip with non-programmable logic. A microprocessor-based smartcard can add, delete, and otherwise manipulate information on the card, and is readily adaptable to many functions. For example, the national health card of Taiwan is a general-purpose smartcard which can store multiple programs downloaded from multiple vendors. Other examples include a credit card which can hold multiple "loyalty" applications to reward the user for multiple purchases from a single vendor, and which can also function as an employee ID card. Java Card is based on the underlying technology of the Java programming language. The Java virtual machine specification and the language definition have been accommodated to make Java technology available in a smartcard.
The present invention is motivated in part by the potential benefits of virtual machine based smartcards and, in general, by the use of virtual machine technology in resource-limited environments such as the smartcard.
For example, a smartcard typically uses three kinds of memory: ROM (read-only memory), RAM (random-access memory), and EEPROM (electrically erasable programmable read-only memory). A programming language (e.g., Java) used in a virtual machine is an abstract language and typically uses a memory model that does not recognize different kinds of memory. The translation from the abstract memory space of the virtual machine environment to the physical memory contained in or connected to the smartcard is performed by the virtual machine.
Java is an object oriented language, and thus relies heavily on the creation and destruction of objects. In an object oriented language, there are no facilities for supporting procedures (i.e., functions without an associated object), so it is not possible to do procedural programming. Therefore, it is necessary to create, destroy, and call objects to perform a given task.
Typically, smartcards have very limited RAM capacity; 2K (bytes) to 4K is common. If the programming objects are created in the limited RAM, then it becomes very difficult to perform complex tasks because the amount of memory available for object creation is very limited. A smartcard typically has much more EEPROM capacity than RAM, usually on the order of 32K to 96K of EEPROM as compared to the 2K-4K of RAM. Consequently, the virtual machine uses EEPROM for instantiation of object instance data, and uses RAM only for the Java stack and "transient RAM arrays."
The allocation of EEPROM memory for object instance data permits the creation of large programs because there is much more EEPROM capacity than RAM capacity. However, there is a substantial cost for this extra capacity. RAM typically requires one clock cycle to read or write data. EEPROM reads, likewise, typically are performed in one clock. EEPROM write operations, on the other hand, typically require about 4 mS to complete, or about 14,289 clock cycles running at 3.57 MHz! Object creation involves initialization of the data comprising the object, which require writes to the EEPROM. It can be appreciated therefore that object creation and object instance data updates is a very, very slow process.
Similarly, the virtual machine heap is allocated from EEPROM. The heap is a dynamic data structure which is constantly read and, more significantly, written. Thus, writing to dynamically allocated memory is a very slow process. Generally, any variable not on the stack will be allocated from the EEPROM heap, and so writes to non-stack variables will be very slow.
Another area of concern is in the area of providing adequate memory management. In the context of a smartcard environment, and other similarly constrained operating environments, system memory capacity is a very limited resource. Historically, limited memory capacity has always been a problem in processors, especially on multitasking systems where multiple users can run different programs simultaneously as if each user were the only person on the system. The earliest multitasking systems supported a method of multitasking memory called "swapping." This system saves the entire executing state of a low priority program to a disk, thus freeing up memory to allow another, higher priority program to execute. Swapping can also take place when a program is idle, waiting for data transfer with a slow I/O device (e.g., tape drive) to complete.
Though swapping is effective in providing access to memory, the performance is less than optimal because the entire address space of the program must be swapped to and from the disk. The idea of swapping out entire programs evolved into the notion of "paging" where the address space of a program was divided into some number of fixed-size pages. Each of these pages could then be swapped out to disk and back, as required by the system, without having to swap out the entire program thus improving system performance.
Memory protection mechanism are needed when multiple programs are executing on the processor. Memory protection via hardware instructions has traditionally been implemented in one or two different ways: The first method was via extra data bits added to each machine word. This method required special hardware and was incompatible with industry standards, and was soon discontinued in favor of memory management logic. This method relies upon a component called a memory management unit (MMU) to implement memory protection. The MMU approach provides page-level granularity, usually on the order of 4 Kbytes and higher.
Another memory management technique concerns memory access speed. The "cache" is a high-speed memory and was originally envisioned as a slave to a slower core memory in such a way that in practical cases the effective access time is nearer that of the fast memory than that of the slow memory. Caches have traditionally been used to decrease the average access time of slower RAM memory, and have also been used in mechanical storage media such as disk drives.
There is a need to provide a suitable operating environment for operating a virtual machine in a smartcard environment and in general in any similar resource-limited environment other than in a smartcard application.

Processor for virtual machines and method therefor


A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.

1. Technical Field
The present invention relates to memory circuits and more particularly to a memory circuit and method having/using a level shifter for controlling cell voltages during memory operations.
2. Description of the Related Art
Static Random Access Memory (SRAM) is one of the key components in semiconductor processors and computer systems. As technology advances and printed features in semiconductor chips become smaller, SRAM design is facing a difficult problem which arises from the statistical variation of process parameters in each SRAM cell. Traditionally, SRAM design depends on the symmetric nature of an SRAM cell. When the symmetry is broken due to local variation of process parameters, SRAM designs become susceptible to stability issues where an SRAM cell is so unbalanced and, as a result, it is no longer correctly functional for either read or write operations.
Another challenge in SRAM design is keeping up with ever increasing operating frequency. As technology advances, the devices in an SRAM cell become smaller than those in previous technologies. Since the newer process technologies face tougher problems, device performance may no longer scale at a same rate as feature scaling. As a result, the SRAM cell current in a newer process technology tends to be weaker than previous technologies. This means that SRAM performance may not fare as well compared with the previous technologies.
One of the techniques employed is separating power supplies to SRAM arrays and possibly SRAM array peripherals and boosting one power supply to a higher value than the rest of chip. In this way, the SRAM stability issue decreases, and the SRAM design can gain speed at the same time. However, issues with introducing separate power supplies with different potentials arise. When the difference in potential is small enough, the issue may be negligible. However, when the potential difference becomes large enough, the circuit at the boundary of the two supplies may malfunction or may experience issues such as excessive leakage.

Level shifter for boosting wordline voltage and memory cell performance

International Business Machines Corporation


A method of controlling a packet flow in a distributed network system comprising a plurality of network nodes having the same destination address is disclosed. Network nodes each having an application running that waits for connections on a given destination port are registered in a flow table. This registration information is distributed to each of the plurality of network nodes. When a packet indicating an initiation of a connection is received and it is determined that the received packet indicates the initiation of the connection on the given destination port, a network node is selected from the network nodes registered in the flow table, to which the received packet is to be forwarded. The received packet is forwarded to the selected network node and a corresponding entry is inserted into the flow table. This entry information is distributed to each of the plurality of network nodes.

TCP/IP (Transport Control Protocol/Internet Protocol) is a commonly used protocol for applications to set up reliable end-to-end connections in the networking world. The BSD (Berkeley Domain Sockets) socket interface is a popular network-programming interface for users to implement TCP/UDP (User Datagram Protocol) based applications. The TCP protocol has the concept of a 'listener', which signifies a server software that waits for connections on a given TCP port.
With systems becoming more complex, the significance of distributed systems is increasing.
If the TCP protocol stack is distributed (i.e. if there are multiple instances of TCP protocol stack and sockets running) on various nodes in a distributed system, the external world still looks at the whole system as a single IP-endpoint. Due to this, the incoming TCP connection requests have the same destination-port. If there are multiple applications running on multiple nodes listening to different ports, there is a need to create a mechanism to send incoming SYN requests and further TCP segments to the appropriate listener.
The problem is more complex when multiple applications on multiple cards that listen to the same TCP port have to be supported.
Existing implementations have a centralized listener which receives packets and applications take care of distributing messages to other nodes if required.

Listener mechanism in a distributed network system


A process is disclosed for enriching the amount of CFC-114 relative to the amount of CFC-114a from an initial mixture containing both isomers, by contacting said initial mixture with hydrogen chloride in the vapor phase at an elevated temperature in the presence of a catalyst to produce a product mixture containing C.sub.2 Cl.sub.2 F.sub.3 and chlorination products of CCl.sub.2 FCF.sub.3 wherein the weight ratio of CClF.sub.2 CClF.sub.2 to the total C.sub.2 Cl.sub.2 F.sub.4 is higher than the weight ratio of CClF.sub.2 CClF.sub.2 to the total C.sub.2 Cl.sub.2 F.sub.4 in the initial mixture. The chlorination products of CFC-114a (e.g., CCl.sub.3 CF.sub.3) in the product mixture may then be separated from the C.sub.2 Cl.sub.2 F.sub.4 therein (e.g., by distillation).

Products containing isomers of C.sub.2 Cl.sub.2 F.sub.4 are produced in various degrees of isomer purity. For example, C.sub.2 Cl.sub.2 F.sub.4 can be produced by the chlorofluorination of perchloroethylene, and the product typically consists of a mixture of the isomers, CClF.sub.2 CClF.sub.2 and CCl.sub.2 FCF.sub.3 (see e.g., U.S. Pat. No. 4,605,798). If the C.sub.2 Cl.sub.2 F.sub.4 isomer mixture is then used to produce CHClFCF.sub.3 (HCFC-124), CHF.sub.2 CClF.sub.2 (HCFC-124a), CHF.sub.2 CHF.sub.2 (HFC-134) and/or CH.sub.2 FCF.sub.3 (HFC-134a) by hydrodehalogenation, the products often consist of a mixture of C.sub.2 HClF.sub.4 isomers and C.sub.2 H.sub.2 F.sub.4 isomers. GB 1,578,933 illustrates that mixtures of C.sub.2 Cl.sub.2 F.sub.4 isomers in ratios of CFC-114 to CFC-114a of about 28:1 to 1:1 can be hydrogenolyzed over a palladium on carbon catalyst to mixtures of C.sub.2 H.sub.2 F.sub.4 isomers in ratios of HFC-134 to HFC-134a of from less than 0.01:1 to about 4:1, depending on reaction conditions. Over a palladium on alumina catalyst mixtures having CFC-114 to CFC-114a ratios of about 3:1 to 1:1 are essentially completely hydrogenolyzed to HFC-134a. PCT International Application No. 9218446 discloses that mixtures of C.sub.2 Cl.sub.2 F.sub.4 isomers can be converted to mixtures of C.sub.2 H.sub.2 F.sub.4 isomers with the product containing essentially the same distribution of fluorine atoms as the starting materials.
C.sub.2 HClF.sub.4 isomers and C.sub.2 H.sub.2 F.sub.4 isomers are used as refrigeration fluids for a number of applications. C.sub.2 HClF.sub.4 isomers, like C.sub.2 Cl.sub.2 F.sub.4 isomers, are also valuable raw material feeds for a number of other commercial processes. It has been found that for many of these applications, the presence of the unwanted isomer of an isomer pair can alter the physical properties of the desired product. As a result, there have been continually increasing market and process demands for high isomer purity materials. Identification of methods for enriching a composition's content of one isomer over another represents a significant aspect of preparing products for specific applications.
Purification of fluorocarbon products has been the subject of considerable research. Of particular interest are the challenges presented in separating fluorocarbon products from materials such as impurities in the starting materials used to produce the fluorocarbon products; and in separating excess reactants, and reaction co-products and by-products which are difficult to remove by standard separation methods such as distillation. Enrichment of CFC-114 in the presence of its isomer, CFC-114a, by distillation is not considered practical since their boiling points are close; the boiling point of CFC-114 is 3.6.degree. C., and the boiling point of CFC-114a is 3.3.degree. C.

Process for enriching 1,2-dichloro-1,1,2,2-tetrafluoroethane from a mixture of dichlorotetrafluoroethane isomers


A method, system, and medium of modeling and/or for controlling a manufacturing process is disclosed. The method includes the steps of identifying one or more input parameters that cause a change in output characteristics, defining global nodes using estimated maximum and minimum values of the input parameters, and defining a mathematical equation that calculates a predicted output characteristic for each node. The method also includes the steps of receiving at least one empirical data point having one or more input parameter values and at least one empirical output value and adjusting the predicted output values at the nodes based on a difference between the at least one empirical output value and the predicted output characteristic calculated using the mathematical equation based on the one or more input parameter values.

In manufacturing devices that include precision discrete devices (e.g., manufacturing microelectronic chips on silicon substrates), there is an ever growing need to improve manufacturing processes. Improving manufacturing processes may require, among other things, monitoring the characteristics of manufactured devices and adjusting input parameters (e.g., equipment controlling parameters) that influence the characteristics of the manufactured devices. A mechanism used for automatically monitoring information relating to the processing of manufactured devices and estimating the characteristics of these manufactured devices based on the adjustments to input parameters is called a process model. In turn, an automated system that makes adjustments to the input parameters as estimated by the process model and uses the adjusted input parameters to control the manufacturing processes is called a control system (or a process control system).
A conventional process model for one or more pieces of manufacturing equipment to be used in manufacturing processes is referred as a predictive model, which attempts to predict the characteristics of manufactured devices based on the input parameters. One example implementation of a conventional predictive model may use a lookup table, without using a mathematical model, to determine the best combination of input parameters to control the characteristics of manufactured devices. This technique however often requires collecting and storing an enormous corpus of experimental data obtained from numerous real-time trials. These drawbacks make this example technique a complicated, time-consuming and costly procedure.
Another conventional process model is a mathematical or formula based optimization method. This model uses numerical analyses to solve equations. More specifically, using a mathematical formula, an equation or a set of equations is used to calculate output values and arrive at the minimum of an objective function. The minimum represents an optimal solution of the objective function. More often than not, the formula is of a complex structure which may be difficult to solve. The above-described formula technique, which uses equations built on the basis of a limited number of empirical data points, can be rapid and compact. However, it is not configured to store and take into account the "history" of collected empirical data points. For example if empirical data points are collected within a small part of the total area over which monitoring and potential adjustment may be desired, the resulting correction provides a case of close fit only for the small part of the total area from which the empirical data points were collected, but when this correction is extrapolated over the total area as is widely practiced today, the resulting predictions can become inaccurate.

Method, system and medium for controlling manufacturing process using adaptive models based on empirical data


A method for producing an optoelectronic assembly having a first and at least a second optoelectronic components may include forming a first electrically conductive layer on a substrate, forming a second electrically conductive layer on the first electrically conductive layer, applying an insulator material on the second electrically conductive layer and the substrate, such that at least a first insulator region, which insulates a first component region from a second component region, a second insulator region, which insulates the second component region from a first contact region, a third insulator region arranged on a side of the first component region, and a fourth insulator region arranged between the first and second insulator regions on a side of the second component region are formed by the insulator material, forming a first and second optically functional layers in the first and second component regions, respectively, and applying an electrically conductive electrode layer.

In optoelectronic components such as organic light-emitting diodes, insulators are used inter alia to separate two electrode regions from one another and/or electrically insulate them from one another.
Suitable insulators, for example photosensitive resists, are usually very expensive and difficult to apply, for example in a photolithographic process. For example, the resists are applied without a structure flat onto metal layers subsequently to be etched, and are exposed with the aid of a mask. Depending on the resist used, the exposed or unexposed regions can then be removed, so that the resist layer is structured. During the subsequent etching process, the remaining resist structures protect the underlying metal layer or the underlying metal layers.

Method for producing an optoelectronic assembly, and optoelectronic assembly


The hand tool has a pair of hand tool elements pivotally joined at one distal end thereof. Each hand tool element has an elongated configuration having a handle portion, a tool portion extending distally away from the handle portion, and a concave blade extending sidewardly and oppositely inwardly relative to one another along each tool portion. Furthermore, each hand tool element has a cutting edge along at least one portion of each concave blade, and at least one avocado seed engaging portion located along, and protruding substantially radially distally away from, each concave blade.

There are numerous examples of kitchen hand tools on the market usable for cutting in two and\or coring avocados. Some of these commercially available hand tools typically comprise a handle portion and a tool portion extending from one end of the handle portion, with the tool portion being adapted for either cutting the skin and flesh of an avocado, or removing the seed, or coring, the avocado. Other examples of such kitchen hand tools comprise a handle portion, and both a tool for cutting the skin and flesh of an avocado, such as a blade extending from one end of the handle portion, and a coring tool typically at an opposite end of the handle portion or, alternatively, located adjacent the cutting tool.
Invariably, the cutting and coring tools of these hand tools are two distinct portions thereof. Consequently, a user must use in alternance each one of these distinct portions of the hand tool, with each requiring their respective manipulations, for cutting than removing the seed of an avocado.
These manipulations applied in alternance can become a painful strain on the hands of the user when a series of avocados must be cut and cored using these kitchen hand tools.
Thus, there is a need on the market for an improved hand tool for cutting and coring an avocado that avoids the aforementioned disadvantages.
In a broad aspect, the present invention provides such an improved hand tool, and a method of using same.

Hand tool for cutting and coring an avocado and a method of using same


According to one embodiment, a tracking apparatus includes a spherical body, 1st to 3rd gimbals, a movable body, three or more spherical driving units, a hold unit, a target position identifying unit, 1st to 4th angle sensors, a rotation spring driving unit, a moving unit, a transmission unit, and a control unit. The rotation spring driving unit returns the third gimbal to a center of a rotation range of the third gimbal. The moving unit moves a movable lens to set a distance between a fixed lens and the movable lens. The control unit causes the spherical driving units to swing the movable body based on the position data and the 1st to 4th angles, reorients the movable body to point in a desired direction, and controls the distance.

In recent years, systems for tracking an object using, for example, an Industrial television camera, to realize continued monitoring or acquire detailed information have been produced on a commercial basis for protective service equipment employed in large-scale facilities such as airports and manufacturing plants, lifeline facilities such as electric power plants and water networks, and traffic information support systems such as Intelligent Transport Systems. These systems include not only ground equipment type systems, but also compact ones installed in vehicles, ships or airplanes and having a vibration-proof structure. In the systems, it has come to be important to enhance their whirling speed to make them quickly point a plurality of targets and sequentially track the targets.
In such a conventional moving object image tracking system as the above, to track a target that moves in all directions, a gimbal structure is often employed. The gimbal structure needs to have at least two axes. In such biaxial gimbals, when a target passes the zenith or a position near the same, it is necessary to instantly rotate the AZ axis thereof through 180 degrees. Actually, however, this quick rotation is hard to execute since the motor torque is limited, and hence the phenomenon, called gimbal lock, which makes it impossible to continuously track an object will occur. Therefore, the biaxial gimbal structure cannot be oriented to the zenith and its vicinity, which makes it difficult to realize omnidirectional tracking.
In light of the above, in some conventional image tracking systems, a triaxial gimbal structure is employed to enhance the degree of freedom in tracking, and is attempted to be used to continuously track a target in all directions, with its azimuth axis (Az axis) and cross elevation axis (xEL axis) controlled so as not to excessively increase the angular velocity to thereby avoid gimbal lock and make the movement of the gimbal fall within an allowable range.
Further, as a conventional technique that does not employ a gimbal structure, a mechanism has been proposed in which a spherical casing is rotated in all directions by a friction rolling mechanism.
Yet further, as a mechanism for rotating a spherical movable body utilizing friction, a conveyor apparatus capable of moving by rolling a spherical rotary hollow body with its surface formed of an elastic member has been proposed.
The above conventional techniques have a problem that downsizing is hard to realize and a control law for tracking a target is complex. For instance, in the triaxial gimbal structure, the number of driving means, such as motors, is increased, which makes it difficult to reduce the size and manufacturing cost. Also, since a camera, for example, is installed, the inertia load of the xEL axis is inevitably increased, which may cause interference between the Az axis and the xEL axis. Thus, problems peculiar to the triaxial gimbal structure may well occur. In addition, although it is possible to reduce the angular velocity of the Az axis utilizing a redundant axis, the angular velocity required for the Az axis is still greater than that of any other axis, whereby the driving torque needed for the Az axis is inevitably increased.
Furthermore, a system utilizing no conventional gimbal structure is free from a problem such as gimbal lock. In this case, however, it is difficult to automate the system. For instance, it is necessary to drive a spherical body by artificial remote control until a target enters the screen of a camera. In addition to this, since there is no element for acquiring information indicating the orientation of the camera, it is difficult to automatically track the target using information acquired from an image thereof. Also, since the camera, for example, in the spherical casing is accessed by radio, the timing of moving the camera is limited.
Moreover, it is difficult to apply the conventional mechanism for driving a spherical body to a moving object image tracking system, although this mechanism is applicable to, for example, a moving apparatus. For instance, it is difficult to reorient the camera to point in a desired direction, because the spherical body is driven so that a table moves with its attitude kept horizontal.


An electrophotographic belt which enables the suppression of bleeding of an electrolyte while minimizing influence on its surface smoothness. The electrophotographic belt showing electroconductivity resulting from dissociation of an electrolyte is made of a resin composition containing a crystalline resin as a binder resin, an oil-soluble dye and an electrolyte.

1. Field of the Invention
The present invention relates to an electrophotographic belt used as an intermediate transfer belt or the like of an electrophotographic image forming apparatus, and also relates to an electrophotographic image forming apparatus.
2. Description of the Related Art
An electrophotographic image forming apparatus uses, for example, an intermediate transfer belt which is used for carrying, on a surface thereof, toner images having been primarily transferred from electrophotographic photoconductive members and transporting the toner images to a secondary transfer region where the toner images are transferred to a transfer medium such as paper, or a transfer-transport belt which is used for carrying, on a surface thereof, a transfer medium such as paper, onto which a toner image is transferred and transporting the transfer medium. An electrophotographic belt used as such members is required to have electroconductivity according to the use of the electrophotographic belt. For the purpose, an electrophotographic belt to which electroconductivity is provided by producing the belt in such a manner that an electrolyte is dispersed in a binder resin has been proposed and utilized. In the electrophotographic belt to which electroconductivity is provided by incorporation of an electrolyte, however, the electrolyte or ions generated by dissociation of the electrolyte may gradually migrate toward the surface of the belt (this phenomenon is hereinafter referred to as "bleeding") as a result of applying a DC bias to the belt within the electrophotographic image forming apparatus (herein, an electrolyte and ions generated by dissociation of the electrolyte may be collectively referred to as "electrolyte").
The bleeding of the electrolyte may cause the electroconductivity of the electrophotographic belt to change with time. If the electrophotographic belt is used as an intermediate transfer belt, the electrolyte deposited on the surface as a result of the bleeding may affect the efficiencies of the primary transfer and the secondary transfer of toner images. Accordingly, Japanese Patent Application Laid-open No. 2010-139650 has proposed that hydrotalcite is added as a filler for suppressing the bleeding of an electrolyte.

Electrophotographic belt and electrophotographic image forming apparatus


A manufacturing method for a semiconductor device formed in a device region composed of a plurality of semiconductor layers on a substrate, the method including a trench forming step of forming a trench on the substrate around the device region and a semiconductor growth step of growing the semiconductor layer in the device region.

(1) Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device, in particular to a manufacturing method for a III group nitride semiconductor device having heterojunction, such as a light emitting diode (hereafter referred to as LED) in a visible range to an ultraviolet range, a semiconductor laser in a visible range to an ultraviolet range, or a high-speed transistor, and relates to a semiconductor device and a semiconductor wafer manufactured by the III group nitride semiconductor having the heterojunction.
(2) Description of the Related Art
The III group nitride semiconductor made of GaN, InN, AlN or an alloy composed predominantly of these materials is a semiconductor material that can form a hetero-structure of a wide band-gap having an energy gap corresponding to a wave range from a visible light to an ultraviolet radiation. Therefore, it is a preferred material for a LED, a semiconductor laser, a high-speed transistor which can operate in a high temperature environment, and the like.
The III group nitride semiconductor using such as GaN is often grown on a substrate made of different materials such as sapphire and SiC. Therefore, a distortion is generated when it grows because of differences of a grating constant and a thermal expansion coefficient between the substrate and a III group nitride growth layer. Or, when the hetero-structure made of AlGaN or InGaN is formed on GaN, the grating constant and the thermal expansion coefficient are different among GaN, AlGaN and InGaN so that a distortion is generated at the time of the growth. When such distortion is deposited and a limit is reached, a crack is generated on the growth layer. Accordingly, various counter-measurements are taken.
For example, Japanese Laid-Open Patent Publication application No. H11-74621 (related art 1) discloses a technology of moderating a distortion using InGaN for one of the layers which forms a light confinement hetero-structure. The other, Japanese Laid-Open Patent Publication application No. 2002-9341 (related art 2) discloses a technology of moderating a distortion by forming a III group nitride layer on a p-GaN having concavo-convexes.
According to the method, it is possible to thicken a thickness of the growth layer by moderating the distortion and to grow a growth layer which even has a large compositional difference with the base without generating a crack.
However, with the conventional structure, the distortion can be reduced but the crack is propagated to a semiconductor device and a semiconductor substrate when the growth layer grows as much as causing a distortion larger than a destruction limit. Also, there is a limitation for a combination of the base and the growth layer.
Furthermore, in the case where a semiconductor material with a film hetero-structure using InGaN is applied to a light-emitting device with a short wavelength such as a purple light to an ultraviolet radiation, an InGaN layer works as a light absorption layer so that a light-emitting efficiency remarkably declines and an high-efficient semiconductor device cannot be acquired. Further, by a method of forming concavo-convexes on p-GaN which has a base structure, the p-GaN which has an electrical conductivity is used for a base layer so that, when the method is applied to a high-speed transistor, a maximum operation frequency is declined.

Manufacturing method for semiconductor device, semiconductor device and semiconductor wafer

Matsushita Electric Industrial Co., Ltd.


Methods of generating nanoparticles are described that comprises feeding nebulized droplets into a radio frequency plasma torch to generate nanoparticles, wherein the majority of the nanoparticles generated have a diameter of less than about 50 nm. These methods are useful for synthesizing nanoparticles of metals, semiconductors, ceramics or any other material class where the precursors are either in liquid form or can be dissolved or suspended in a suitable liquid. Methods of feeding nebulized droplets and central gas into a radio frequency plasma torch and apparatus for generating nanoparticles are also described.

1. Field of the Invention
The present disclosure relates to a method of generating nanoparticles using a radio frequency plasma torch and a nebulizer.
2. Description of the Related Art
Over the last few decades, many different techniques have been utilized for the production of fine particles of a variety of materials. Mechanical attrition, wet chemical synthesis routes and aerosol/vapor based syntheses are the most commonly cited processes for this purpose. There are several advantages in using aerosol/vapor based processes like flame spray pyrolysis [1], combustion synthesis [2] and thermal plasma synthesis [3-8]. For example, they allow easy control of morphology and a relatively large production capacity. In addition, unique material phases can sometimes be obtained due to the non-equilibrium nature of these processes. Among aerosol/vapor phase processes, radio frequency (RF) plasma techniques (alternatively, inductively coupled or induction plasma) are especially valuable. RF plasma techniques offer various advantages such as large plasma volume, low gas velocity, and the capability for axial injection of the feedstock. Because the RF plasma techniques are inherently electrodeless, they also serve to minimize contamination during particle synthesis. Examples of RF plasma techniques include spray-inductively couple plasma synthesis (SICP) [9, 10], suspension plasma spraying (SPS, see U.S. Pat. Nos. 5,609,921 and 6,994,837, and U.S. Patent Publication No. 2007/0029291), and precursor plasma spraying (PPS) [7]. These techniques are useful in the synthesis of various metal, ceramic and semiconductor powders.
In the SICP process, particles of various materials are produced using a RF plasma by feeding pre-atomized solution/suspension droplets into the plasma region via a thin cooled probe inserted directly into the plasma [10, 11]. Since the probe diameter is severely constricted (less than about 1/10 of the diameter of the central core region of the plasma torch), the probability for the pre-atomized droplets to coalesce and form larger droplets is high. This can lead to the formation of large particles along with smaller ones, which not only broadens the particle size distribution, but also increases the total number of the particles having larger diameters.
The SPS (and the similar PPS) process for producing films or particles takes advantage of a high-pressure water-cooled two-fluid type probe atomizer that is inserted directly into the plasma torch [12-14]. This atomizer arrangement is not capable of producing small enough droplets. The size range of the droplets produced by the atomizer in the SPS process as stated in the specifications from manufacturer is 20-120 μm or larger depending on operating conditions. Furthermore, the arrangement of having the probe inserted directly into the plasma makes it impossible to attach a scavenging mechanism for removing large droplets. As a result, particles with a wide size range ranging from a few tens of nanometers to larger than 10 μm are produced. This is easily appreciated by perusing the size distribution data provided in references [8] and [14]. Although the current state-of-the-art RF plasma-based techniques can produce particles in the sub-100 nm range of diameters, they are inherently incapable of producing a plurality of nanoparticles with a majority of the volume concentrated in sub-100 nm particles. From the point of view of industrial production, it is important to have the ability to produce a large volume fraction carried by sub-100 nm particles. A large fraction of the mass of particles produced by current industrial processes now would have diameters larger than 100 nm, which would have to be rejected in nanoparticle production.
Various embodiments described herein address the need for a technique to successfully control the particle size distribution below the 100 nm threshold by using RF plasma processing of atomized solvent/suspension precursors. Furthermore, this technique can also be applied to other processes like flame spray synthesis, combustion synthesis or any system where an aerosolized form of the precursor needs to be injected into a reaction zone for particle synthesis.

Method and apparatus of producing nanoparticles using nebulized droplet


The present invention provides the use of a composition comprising a block polymer as a support matrix in the manipulation, processing or analysis of particles, such as cells and fluorescent beads. In a preferred embodiment, the composition exhibits gel-sol thermoreversibility, micelle formation under gelling conditions, optically compatible, controllable surfactant properties, molecular sieving properties and biocompatibility. Further aspects of the invention provide (a) a support matrix composition comprising a block polymer, fluorescent beads and/or a dye for use in the manipulation, processing or analysis of particles, (b) a multichamber plate coated in a support matrix composition and (c) kits for producing the same.

There exists a need to make biological assays faster and simpler to perform with an overriding drive to make the processes cheaper yet maintain accuracy and reproducibility. This is due to a rapid increase in the number of research and diagnostic molecular probes available (e.g. new fluorescent reporter molecules) and the advantages in terms of information content of multiplexing such assays across a range of instruments. Increasingly there is a need for cell-, particle- and bead-based (and a combination of these units) assays in which the presence, for example, of cells with certain features indicates disease processes. Similarly, the demand and evolution of rational approaches in the search for bioactive molecules for new medicines has resulted in a need for low cost high-through-put screening (HTS) and the development of cell- and molecule-based assays, tools and arrays within the field of functional analysis.
Such assays require or are enhanced by the availability of methodologies for:    i) the manipulation of cells/particles, analytes and reagents in liquid and gel phases for processing purposes,    ii) the controlled delivery of fluorescent/bioluminescent molecules to cells/particles or the retention of the fluorescent/bioluminescent-associated properties of said particle/cells.    iii) the controllable immobilisation of said cells/particles for the purpose of analysis involving light collection    iv) the retention of cell viability and cell function for periods of time sufficient for the purposes of an analysis.
The present invention seeks to provide means for use in such methodologies.
A variety of hydrogels based upon thermoreversible polymers (in liquid form at elevated temperatures but in gel form at lower temperatures) are known, including natural gel-forming materials such as agarose, agar, furcellaran, beta-carrageenan, beta-1,3-glucans such as curdlan, gelatin, or polyoxyalkylene containing compounds.
The present invention exploits to the distinct advantages and properties of block polymer-based gels, such as polyoxypropylene-polyoxyethylene block polymer gels (PBP), which unusually undergo transition to liquid form upon temperature reduction. This property can be described as 'reversed thermosetting'.
Selected properties of the PBP preparations, such as detergent properties and the mechanical and thermoreversible properties of hydrogels in general, have been documented and exploited in the art.
For example, reported uses and properties of PBP preparations include the following:
Surfactant Properties
Polyoxypropylene-polyoxyethylene block polymer (PBP) has been used as a non-ionic surfactant for detergents, dispersants, binders, stabilisers, defoaming agents, emulsifying agents to name but a few. At high aqueous PBP concentrations, beyond a transition temperature, a gel can form comprising amphiphilic block copolymer micelles. A commercial Pluronic® preparation F-127 (PEO99-PPO69-PEO99, with E and P being polyoxyethylene and polyoxypropylene, respectively) has been used in gel form for pharmaceutical preparations.
Reverse Agar and Biofilms
Gel-forming formulations of PBP have been described as 'reverse agar' in their use. The low temperature gelling formulation has been used to support the limited growth of micro-organisms in conventional microbiology applications. Such Pluronic®-based hydrogels have been used extensively to assay biocide treatments. Gel-trapped micro-organism populations mimic the localized high cell densities observed in biofilms and are subject to the similar nutrient and chemical gradients found within natural biofilms. Such prior art uses with respect to micro-organisms has revealed that PBP should have low toxicity in the stable gel form.
Molecular Sieve Properties
PBP gel form has the potential to form ordered micellar structures and has been used as a separation media for nucleic acids, indicating the coherent movement of molecules through the gel upon the passage of a continuous or pulsed electrical current. Microdevices have also been designed with sieving gels within the same device to perform separations involving both single- and double-stranded DNA over distances on the order of 1 cm. Extensive comparisons have been made to compare different gel matrices on the basis of gel casting ease, reusability, and overall separation performance using for example a 100 base pair double-stranded DNA ladder as a standard sample.
Hydropads
Miniature size and high sensitivity of biochips is sought in diagnostics, testing, and research in medicine, veterinary science and applications, agriculture, toxicology, environmental monitoring, forensics etc. Three dimensional biochips comprising non-thermoreversible gels (hydropads) have been developed consisting of an array of three-dimensional gel elements on the hydrophobic surface of a microscope slide. For example, a gel-based biochip project was initiated in Engelhardt Institute of Molecular Biology of the Russian Academy of Science (EIMB) in 1989 resulting in the development of the 'Immobilized Micro Array of Gel Elements' on chip (or IMAGE chip), which can bear oligonucleotides, DNA, proteins, small compounds or cells fixed within semi spherical hydrogel pads. A simple two-step procedure has been developed for the large-scale manufacture of such chips. The gel pads can serve both as support for immobilisation and as individual nanoliter test tubes to carry out various specific interactions, chemical or enzymatic reactions. Chips have been produced that contain immobilized antibodies, antigens, enzymes, receptors, and different ligands.
Cell Encapsulation
Polymeric gels have also been explored as cell encapsulation materials for tissue engineering. Isolated mammalian cells and tissues have countless applications in medicine and biotechnology, yet protecting and nourishing cells either in vitro or in vivo while harvesting the desired products has proven difficult.
Drug and Dye Delivery
Previous clinical applications have revealed the use of hydrogels for the purpose of local delivery of pharmacologically active agents to tissues. In contrast, previous work on the "liquid less" cell staining by dye diffusion from gels (polyacrylamide or gelatin) has been restricted to the use of gel systems lacking the unique thermoreversible properties of PBP-based gels. Such studies have been described by Smolweski et al., 2001, Cytometry 44(4):355-60. Dye delivery to cells was observed but required a 2- to 4-fold increase in normal staining concentration of DNA dyes.

Analyzing cells immobilized in block copolymers


A telecommunication station having the capability to both block selected incoming calls and transfer other selected incoming calls. The station further has the capability to provide user messages to the blocked calls and thereafter, if desired, further divert the blocked calls to another selected station.

The invention relates to a telecommunication station comprising reproducing means and blocking means for blocking incoming calls.
Such a telecommunication station is, for example, the SOPHO-SET S375(D) business telephone by Philips. This telephone has various facilities for blocking calls and diverting calls, as required, such as "follow me" and "do not disturb" facilities. These facilities are described on pages 48 and 49 of the Sopho-Set S375(D) User Guide, published by Philips Communication Systems, Hilversum, The Netherlands, November 1990. "Follow me" is a facility by which the user can block and divert all incoming calls to a number to be indicated by him. "Do not disturb" is a facility by which the user simply blocks all incoming calls.
The "do not disturb" and "follow me" facilities do not enable the user to block specific incoming calls and not to block others.

Telecommunication station with call blocking and call transferring capabilities


The tungsten nitride film containing fluorine is used as a barrier metal in the contact hole or via hole of the semiconductor device. The tungsten nitride film formed contains 1% to 20% fluorine at atomic density. With this structure, it is possible to obtain a WNF film having a good step coverage for a fine hole.

The present invention relates to a semiconductor device having a tungsten nitride film containing fluorine (WNF film).
Recently, there is a great demand for a highly reliable multilayer wiring technique capable of forming via holes, contact holes or fine wires, which have high aspect ratios, so as to achieve a high integration of LSI. For example, conventionally, chemical vapor deposition methods have been proposed as a technique for burying a wire having a high aspect ratio, a typical one of which is blanket W-CVD using tungsten hexafluoride (WF.sub.6) and hydrogen (H.sub.2).
However, with the blanket W-CVD, a good adhesion with respect to the underlayer of Si or oxide film, cannot be obtained, and therefore it is required to provide a metal adhesion layer such as of titanium nitride, tantalum nitride (TaN), tungsten titanium or tungsten nitride, between the underlayer and W. Conventionally, such a metal adhesion layer is formed by the sputtering or reactive sputtering technique; however it is preferable that a CVD method having a high step coverage should be employed when applied to fine via holes or contact holes.
Further, conventionally, for wires made of low-resistance materials such as Al and Cu, a metal adhesion layer made of, typically, TiN is used as a diffusion barrier; however recently there is an increasing demand for a CVD method having a high step coverage, as the size of the wiring portion becomes finer.
In the case where a TiN film is formed by the CVD method, the film is formed with use of titanium chloride (TiCl.sub.4) and ammonium (NH.sub.3); however these materials cannot be used after the formation of the aluminum wire since the temperature for the formation of the film is as high as 600.degree. C. or higher. Further, chlorine remains as residue in the film, and therefore the corrosion of the wire easily occurs. Furthermore, the formation of a TiN film with use of a Ti-based organic metal gas and ammonium is presently studied; however it entails the problem of an increase in resistance, caused by impurities or moisture absorption, and therefore has not yet been established as a film forming method.
As described, the formation of a TiN, TaN or TiW film with use of the CVD method, entails a number of drawbacks to be solved.
In the meantime, the formation of tungsten nitride film containing fluorine (WNF film), using material gases of WF.sub.6 and NH.sub.3, is also studied. The WNF film is thermally stable, and it can be formed at a low substrate temperature of 600.degree. C. or less by a vacuum CVD method. Therefore, the use of the film as an adhesion layer for Mo, or a barrier layer for an Al or Cu wire is studied.
However, the WNF film made by the conventional vacuum CVD method using WF.sub.6 and NH.sub.3, entails the problems of a poor step coverage and a high film stress. One of the factors which create such problems is considered that the content of fluorine in the WNF film is low. Therefore, the WNF film made by the conventional vacuum CVD method using WF.sub.6 and NH.sub.3, should not be appropriate as an adhesion layer, barrier layer or the like, in a fine hole.

Semiconductor device having WNF film and method of manufacturing such a device


A global navigation satellite system (“GNSS”) positioning method is provided, based upon a GNSS radio signal that includes a navigation message transmitted as a sequence of frames, each frame being composed of a plurality of subframes, each of which contains a first set of ephemeris and clock correction data (DECH) sufficient for computing a satellite position and a satellite clock error. Each subframe furthermore contains a second set of DECH, more compact than the first set of DECH, but sufficient for computing satellite position and satellite clock error to a lesser degree of accuracy, at least two copies of the second set of DECH being present in each subframe, such that the timing difference between two consecutive copies does not exceed 70% of the subframe duration.

GNSS signals (the "Signal-in-Space" segment) are the main interface between a GNSS ("Global Navigation Satellite System") spatial infrastructure and the various user segments thereof. In this respect, it plays a major part in the performance which will be available to a user in a given environment and use context. This is because performance is the result of the receiving algorithms used (a function of the use context) and of the quality of the signal which reaches the user (affected by propagation conditions).
The spectral and temporal characteristics of the signal, such as carrier frequency, power or modulation (PRN, BPSK, BOC rate) parameters, substantially determine performance in terms of interoperability, tracking and interference and multipath robustness, etc.
The navigation message itself is also a predominant factor in performance. It determines the services in terms of content, but also, by means of its structure, in terms of availability (robustness) and latency (or responsiveness). The navigation message contains, inter alia, a set of ephemeris and clock correction data ("DECH") from the transmitting satellite. The set of DECH is taken to mean a set of data sufficient to permit the receiver to compute the satellite position and the satellite clock error. The navigation message makes a significant contribution to acquisition performance, in particular to acquisition time (also known as "Time To First Fix").
However, the design of a GNSS signal and its navigation message are also the result of a compromise between the various intended service requirements and content (for example and for Galileo: Open Service (OS), Safety of Life (SoL), Search And Rescue Return Link Message (SAR RLM), etc.), sometimes conflicting performance objectives (responsiveness and robustness), and operational or technological constraints (interoperability, mass/consumption/volume of the satellites, etc.).
The Galileo E1 OS and GPS L1C signals thus incorporate numerous changes in comparison with the GPS C/A signal: new navigation message structure, PRN code, optimized modulation schemes, etc. Both signals are directed inter alia towards open service, essentially intended for consumer receivers, and often operate in a difficult environment (urban canyon, for example). However, these two signals differ significantly in their design: the L1C GPS signal is solely directed towards open service, whereas the Galileo OS signal was designed both to handle open service and to supply real-time integrity data (SoL) and the SAR return link channel (SAR RLM). As a consequence, the Galileo message does not solely contain items of ephemeris and time (clock correction) data, but also additional items of data.

GNSS radio signal with an improved navigation message