An integrated circuit is provided for sourcing a mirrored current into a high impedance output node. A load may be coupled to the output node, and the mirrored current may be derived proportional to or substantially equal to current forwarded from a reference current source. The integrated circuit, or current mirror, includes a pair of series-connected output transistors coupled between the output node and a reference terminal. One of the output transistors is dimensioned with a channel that is short enough to ensure the threshold voltage of that transistor is smaller than the threshold voltage of the other transistor having a longer channel. Thus, one transistor utilizes the benefits of high density integrated circuit manufacture and, more specifically, short channel effects arising from channel length less than, e.g., 1.0 microns. The difference in threshold voltages between the pair of output transistors, and mutually connecting gates of those transistors helps maximize the output impedance and voltage swing from the output node of the current mirror while minimizing voltage needed to operate the current mirror.

1. Field of the Invention
This invention relates to an integrated circuit and, more particularly, to a metal oxide semiconductor ("MOS") circuit or method for providing current from a self cascode transistor arrangement having differing gate lengths to maximize output impedance and voltage swing from the circuit while minimizing voltage needed to operate the circuit.
2. Description of the Related Art
There are many techniques used to provide regulated current to a load circuit. One technique involves a current mirror. A conventional current mirror provides output current proportional to an input current. Separation between the input and output current ensures the output current can drive high impedance loads. Conventional current mirror designs have been implemented in both bipolar and MOS technology. MOS devices with short channel lengths and therefore faster operation have provided an impetus toward current mirrors based on MOS technology.
An important aspect in designing an MOS current mirror is to achieve optimum matching between the input (or "bias") current and the output current. Typically, the output current is designed to traverse a load placed across output terminals of the current mirror. The bias current is generally derived from a current source linked to a bias transistor. The bias transistor receives the bias current and produces a proportional bias voltage. The bias voltage is then placed on an output transistor configured to replicate (or "mirror") the bias current. Properly mirrored output current assumes the bias transistor and output transistor are fabricated with similar traits. For this reason, most modern day current mirrors are fabricated on a monolithic substrate as part of an integrated circuit.
FIG. 1 is a conventional current mirror 10 shown in simplistic form. A pair of MOS transistors Q1 and Q2 are shown having their gate terminals mutually connected, along with mutually connected source terminals. Since both transistors are fabricated on a monolithic substrate consistent with one another, the transistors operate in similar fashion. That is, transistors Q1 and Q2 can be n-type transistors or p-type transistors. Transistor Q1 is connected as a diode, whereby the gate terminal is shorted to the drain terminal.
The threshold voltage (Vt) of transistor Q1 is designed to be substantially the same as transistor Q2. Likewise, the voltage across the source and drain terminals (Von) of transistor Q1 when that transistor is in saturation is similar to Von across the source and drain terminals of transistor Q2. The bias current (Ibias) applied to transistor Q1 generates a bias voltage (Vbias) at the gate terminal of transistor Q1. Vbias is substantially equal to the threshold voltage (Vt) of transistor Q1, along with additional turn-on voltage (Von) required for current flow of Ibias. The relation between Von and Ibias is described in the following equations, and is sometimes referred to as the MOS square law relationship: EQU Ibias =K * W/L*(Vgs-Vt).sup.2,
where K is the MOS gain factor, W is the channel width, L is the channel length and Vgs is the gate-to-source voltage, and where EQU Von=Vgs-Vt,
which reduces to EQU Von=(Ibias/(K*W/L)).sup.1/2
Von is generally referred to as the saturation voltage of the transistor. If the drain-to-source voltage (Vds) of the transistor is larger than voltage Von, the transistor will operate in the "saturation"region. On the contrary, if Vds is lower than Von, the transistor will enter the "linear"region which, when entered, significantly degrades the gain and output impedance properties of the transistor.
In the instance shown, the diode-connection of transistor Q1 forces Vds of that transistor to be Vt+Von, which is larger than Von such that transistor Q1 is automatically placed in saturation. Whether transistor Q2 is in saturation or not depends on the drain voltage of node 12. The threshold voltage Vt of transistor Q1 is designed to be substantially the same as transistor Q2. Likewise, the Von of transistor Q1 is similar to Von of transistor Q2.
If transistors Q1 and Q2 in FIG. 1 have matched parameters (channel width, channel length, threshold voltage, etc.) current Ibias will be reproduced or mirrored through transistor Q2 as Iout. Furthermore, the mirrored current Iout will flow through whatever circuit is connected to output node 12. A circuit connected to output node 12 (interchangeably referred to as "Vout") is referred to as the load of the current mirror 10.
Proper design of a current mirror must take into account at least three important characteristics involved in all current mirrors. First, the output impedance as measured upon the output node must be as large as possible. If the output impedance between node 12 and a reference supply applied to node 14 is quite large, then changes in Vout will not substantially effect Iout. Thus, output impedance is often used to evaluate the stability of the current mirror. In the example shown in FIG. 1, output impedance is equal to the impedance across transistor Q2 and is inversely proportional to a channel length modulation factor .lambda. of that transistor, as follows: EQU Rout=R.sub.Q2 =1/(.lambda.*Iout)
A second parameter used in evaluating current mirrors is the output swing, or range, of Vout. At times when the load of the current mirror operates linearly the output swing measured at node 12 should be as high as possible to add to the robustness at which a load circuit can operate when connected to Vout. One edge of the output swing is limited by the saturation voltage (i.e., voltage to maintain saturation) of the load and/or transistor Q2. As defined above, the saturation voltage of transistor Q2 between the source and drain terminals is Von. The smaller the value of Von, the higher the output swing available to a load connected at node 12. In the example provided in FIG. 1, the saturation voltage of the load is equal to the saturation voltage Von of transistor Q2. It is desirable to minimize the saturation voltage Von of the output transistor Q2, and therefore to maximize the output swing available to a load device.
A third criteria involves the voltage required to operate the current mirror. This voltage is often referred to as the minimum operating voltage. The extent at which the operating voltage can be minimized is limited by the voltage required to bias the output transistor. Thus, in many cases, the minimum operating voltage is equal to Vbias. In the example of FIG. 1, the minimum operating voltage is Vt+Von. The three characteristics of a current mirror attributed to the exemplary circuit of FIG. 1 is shown below in reference Table I:
TABLE I ______________________________________ Output Impedance R.sub.Q2 Saturation Voltage Von Bias Voltage Vt + Von ______________________________________
The main disadvantage of current mirror 10 shown in FIG. 1 is the dependence between the output impedance and the channel length modulation factor .lambda. of transistor Q2. The channel length modulation factor will increase with shorter channel lengths. This means that the output impedance R.sub.Q2 will decrease with shorter channel lengths. As the densities of modern day integrated circuits increase, the channel lengths will decrease. Unfortunately, the trend toward higher density circuit devices will decrease the output impedance of current mirrors formed therefrom. In modern sub-micron processes, the effect of channel length modulation becomes significant. A single output transistor Q2 employed within a current mirror and having a channel length less than, e.g., 1.0 .mu.m will increase the output impedance to such an extent that the current mirror may be rendered useless in many applications. For example, if the output impedance is too small, DC gain will be deleteriously small if the current mirror is used as the load of an opamp.
In an effort to maintain high output impedance in submicron fabrication processes, many modern current mirrors employ a cascode arrangement. FIG. 2 illustrates a conventional cascode current mirror 18 having a cascode transistor Q4 inserted in series with transistor Q2, and cascode transistor Q3 added in series with transistor Q1. Transistor Q3 generates the bias voltage from Ibias necessary to replicate or mirror Ibias into the load device. Current mirror 18 has many features similar to current mirror 10, and therefore the similar features (i.e., output node 12 and reference voltage terminal 14, etc.) are identically numbered.
The cascode arrangement shown in FIG. 2 allows the voltage on the drain of transistor Q2 to be shielded from variations in Vout at node 12. Thus, the output impedance Rout of the load is increased by the gain of transistor Q4 as follows: EQU Rout=R.sub.Q2 (gm.sub.Q4 *R.sub.Q4)
Where gm.sub.Q4 and R.sub.Q4 represents the transconductance and output impedance, respectively, of transistor Q4. Since the product of gm.sub.Q4 and R.sub.Q4 is generally much larger than 1.0, the output impedance provided by circuit 18 is much greater than that provided by circuit 10. The disadvantage of a cascode current mirror is the reduced output swing and headroom due to the insertion of cascode transistors Q3 and Q4.
If Vt and Von of transistors Q3 and Q4 are identical, Vbias will be 2Vt+2Von, and the minimum Vout at node 12 will become Vt+2Von. The increased minimum Vout and Vbias makes the conventional cascode arrangement less desirable to low voltage circuits, or circuits which mandate minimal power consumption. Low voltage application implies the voltage swing of a load connected to node 12 must be maintained as large as possible. Consumption of that output swing and available headroom with an increase in the saturation voltage will prove detrimental to low voltage and/or power applications. Performance of cascode current mirror 18 is summarized in Table II as follows:
TABLE II ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage Vt + 2Von Bias Voltage 2Vt + 2Von ______________________________________
There have been numerous enhancements proposed to overcome the shortcomings of circuits 10 and 18. Specifically, those enhancements are derived in current mirrors having as high an output impedance as possible yet with minimal saturation and bias voltages. One example of a cascode current mirror with sufficiently high output impedance yet having minimal saturation voltage is illustrated in FIG. 3. Instead of using a single input current source and a pair of cascode bias transistors coupled to that single source, current mirror 22 of FIG. 3 uses two separate bias circuits. The separate bias transistors Q1 and Q3 are each coupled to receive current from a respective current source.
To more fully understand the differences between current mirrors 18 and 22, it is important to note how the gate and/or bias voltages upon output transistors Q2 and Q4 are derived. In circuit 18 shown in FIG. 2, the cascode-connected, bias transistors Ql and Q3 force the drain voltage of transistor Q3 to be at Vt+Von instead of Von. Thus, the drain terminal of transistor Q2 receives an extra threshold voltage V.sub.t necessary to maintain saturation of transistor Q2. Since saturation of transistor Q4 of circuit 18 requires the gate terminal to be above the source terminal by Vt and Von, the bias voltage at the gate terminal of transistor gate 4 is equal to (Vt+Von)+(Vt+Von)=2Vt+2Von. By employing an individual bias circuit for transistor Q4 in FIG. 3, the extra Vt at the drain of transistor Q2 can be omitted. If the channel width-to-channel length ratio (i.e., the "W/L" ratio) of transistor Q3 is 1/4 the W/L ratio of transistor Q1, then with the same Ibias current applied to both transistors Q1 and Q3, Vbias at the gate terminal of Q4 will be Vt+2Von. Since the drain voltage of transistor Q2 will be a sum of Vt and Von less than the bias voltage, the drain of transistor Q2 of circuit 22 will be merely Von. This will make the saturation voltage of circuit 22 at node 12 to be 2Von. This condition is usually referred to as the "high-swing condition". Note that the saturation voltage across the source and drain terminals of transistor Q4 remains as Von. If the drain voltage of transistor Q2 is merely Von, then the output voltage Vout is simply 2Von in circuit 22, rather than Vt+2Von in circuit 18.
Employing a lower Vout saturation voltage of 2Von in circuit 22 will afford a greater voltage swing of the load at node 12. Unfortunately, using two bias circuits and two separate current sources substantially increases the power dissipation within circuit 22, relative to a single bias cascode circuit 18. Accordingly, circuit 22 is not appropriate for low power applications. The following Table III summarizes the performance of circuit 22:
TABLE III ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage 2Von Bias Voltage Vt + 2Von ______________________________________
A circuit which avoids using separate bias circuits and high power consumption therewith is set forth in FIG. 4. Circuit 26 shown in FIG. 4 essentially divides a bias transistor Q3 into separate bias transistors Q3a and Q3b. Transistors Q3a and Q3b generate an intermediate voltage (bias voltage) at the source/drain connection point, that intermediate voltage being Vt+2Von. If the W/L ratios of transistors Q3b and Q3a are, for example, 1:1/3, then the gate voltage of transistor Q3b will be approximately 2Vt+3Von. Accordingly, intermediate voltage Vbias will become Vt+2Von which biases the load in a high swing condition. Transistor Q5 is inserted in the diode connection of transistor Q1 to equalize the drain voltage to transistor Q2 in order to achieve a more accurate current mirror. The disadvantage of circuit 26 is the rather large operating voltage input to transistors Q3a and Q3b, represented as 2Vt+3Von. The rather large bias voltage is not appropriate for low voltage applications. The performance parameters of circuit 26 is summarized in Table IV as follows:
TABLE IV ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage 2Von Bias Voltage 2Vt + 3Von ______________________________________
A current mirror which has a relatively high output voltage swing (small saturation voltage), but which uses only one current path or bias circuit is generally referred to as a "self cascode" current mirror. Current mirror 26 shown in FIG. 4 employs this self cascode arrangement, as does current mirror 30 shown in FIG. 5. Current mirror 30 is a somewhat simplified version of current mirror 26. Instead of bifurcating bias transistor Q3 into transistors Q3a and Q3b, a resistor 32 is provided. The resistance value of resistor 32 is chosen so that a voltage of Von across resistor 32 will occur. Von across resistor 32 will be added to Vt+Von generated by the gate of transistor Q1. Thus, the voltage applied to bias transistor Q4 will be approximately Von above Vt+Von. Circuit 30 can therefore achieve an output swing similar to circuit 22 without having to add an extra biasing circuit. The disadvantage of circuit 30 is that process variations will cause the resistance of resistor 32 to fluctuate. Any fluctuation whatsoever will replicate back to and be applied upon, the gate conductor of transistor Q4. Accordingly, both the saturation voltage and the bias voltage of circuit 30 are susceptible to variations in the semiconductor fabrication process. Performance parameters resulting from circuit 30 are listed in Table V as follows:
TABLE V ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage 2Von Bias Voltage Vt + 2Von ______________________________________
Circuit 34, shown in FIG. 6, presents an effort to produce a current mirror circuit which is less susceptible to semiconductor fabrication process variations, does not require a separate bias circuit, and maintains maximum output impedance. Current mirror circuit 34, similar to circuit 30, includes an output node 12 and a reference supply terminal 14. However, the transistors Q1, Q2, Q3 and Q4 are of either dissimilar type or have dissimilar thresholds. For example, transistors Q1 and Q2 can be enhancement-mode transistors, while transistors Q3 and Q4 are depletion-mode transistors. This implies that transistors Q3 and Q4 operate at negative thresholds. Alternatively, transistors Q3 and Q4 can be enhancement-mode transistors, yet operate at a lesser, albeit positive, threshold from that of transistors Q1 and Q2. The lower thresholds of enhancement-mode transistors Q3 and Q4 (e.g., 200 mv rather than, e.g., 400 mv), or the negative thresholds of depletion-mode transistors proves beneficial in a conventional setting. However, a description of depletion-mode operation in general is necessary to understand why depletion transistors have negative thresholds.
Opposite enhancement transistors, depletion transistors are normally "on" unless a gate-to-source voltage exceeding Vt occurs. In other words, a bias voltage on the gate electrode of depletion transistors is needed to deplete the channel region of majority carriers, and thus turn those transistors off. NMOS depletion-mode transistors require a negative gate voltage to be turned off while corresponding PMOS transistors require a positive gate voltage to be turned off.
An additional (or dissimilar) ion implantation step may be used to modify the threshold of one transistor from that of another, or to fabricate a depletion-mode transistor separate from enhancement-mode transistors. For example, in order for the required negative threshold voltage for a depletion-mode n-type MOS device to be produced, n-type impurities are implanted between the source and drain regions to form a built-in channel. The channel remains until the threshold voltage is exceeded in absolute value, thereby depleting a channel and terminating the saturation condition. Alternatively, to form a lower threshold transistor separate from, for example, a medium threshold transistor, the channel of a lower threshold transistor must be doped lighter than the medium threshold transistor, or a counter doping must be used. Ion implant is but one way to change thresholds among transistors, another way being, e.g., a change in gate oxide thickness or doping the gate conductor by a compensating amount.
Depletion transistors are said to have a threshold voltage Vt less than zero, and lower threshold transistors have a threshold voltage Vt less than medium threshold transistors. Accordingly, the depletion transistors or lower threshold transistors Q3 and Q4 are henceforth referred to as Vt2, whereas the threshold voltages of the medium threshold transistors Q1 and Q2 are henceforth referred to as Vt1. When transistors are "on", the saturation voltage across those transistors are equal and represented as Von. If all gates are tied together, as shown in FIG. 6, the saturation voltage seen at output node 12 will be Vt1-Vt2+Von, and the minimum operating voltage (bias voltage) is Vt1+Von. If Vt1 -Vt2=Von, the saturation voltage will become 2Von. Circuit 34 achieves lowest operating voltage equal to the single MOS current mirror of FIG. 1. Moreover, the saturation voltage produced at output node 12 of circuit 34 is comparably low, at least as small as many of the other conventional circuits described above. A summary of performance parameters for circuit 34 are listed in Table VI as follows:
TABLE VI ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage Vt1 - Vt2 + Von Bias Voltage Vt1 + Von ______________________________________
Unfortunately, circuit 34 requires additional processing steps to implement, e.g., the implant procedures needed to produce dissimilar threshold transistors or the depletion-mode transistors separate from the enhancement-mode transistors. For example, the depletion-mode transistors require a well region in which the respective depletion-mode transistor channels are formed separate from the channels of enhancement-mode transistors. Those well regions must be implanted or doped separate from dopants placed in the enhancement-mode transistor channels. Alternatively, a threshold adjust implant may be used to lessen (or enhance) threshold of one enhancement-mode transistor from that of another. In either instance, change in threshold or transistor type requires additional fabrication steps. If the additional implantation procedure is not carefully followed, contaminants will selectively arise in transistors employing the additional steps causing a skew in their performance relative to the transistors not having such steps. This skew may cause Von to differ from transistor to transistor. Moreover, contaminants or implant skewing may vary between transistors of dissimilar mode or threshold, causing a possible shift from a desired threshold performance.
It is imperative that the parameters used in producing transistors of a current mirror be carefully matched. Not only must the sizes of the bias and output transistors be controlled, but also the processing parameters used in forming the transistors must be consistent across the monolithic substrate. Implementing additional well regions, implant steps and photolithography sequences into the overall fabrication process may jeopardize the consistent performance needed to ensure accurate mirroring of the input bias current to a high impedance output current.


A method of forming a barrier layer is disclosed. The barrier layer is formed on the upper surface of the tungsten plug. The method of forming the barrier layer is mainly a nitridation reaction. The nitridation reaction makes use of NH.sub.3 plasma, N.sub.2 plasma and N.sup.+ implantation.

1. Field of the Invention
The invention relates in general to the fabrication of a barrier layre, and more particularly to the fabrication of a barrier layer corresponding with a nitridation reaction.
2. Description of the Related Art
The increasing of the integrity of the integrated circuited (IC) causes the insufficiency of the chip surface for formation of interconnection. To satisfy the requirement of more wiring lines as the device size is shrinking, a design of multi-level interconnection is needed for IC fabrication. The multi-level interconnection is a three-dimensional wiring line structure . To form a multi-level interconnection structure, the first or lower layer of the metal wiring line is first formed, connecting with the source/drain region of the metal-oxide semiconductor transistor (MOS) on a substrate and the second layer of the metal wiring line is then formed, connecting with the first metal wiring line. The metal wiring lines can either be made from metal or any conductive material such as polysilicon. More than two layers of metal wiring lines can be formed if necessary.
Aluminum and tungsten are both widely used metal for metallization process of ICs. Aluminum is mainly used as wiring lines between devices due to its low resistivity and aluminum is mostly formed by magnetron DC sputtering. Tungsten is widely used for forming a plug to connect different layers of metal since it can be formed by chemical vapor deposition (CVD), easy to form fluoride compound with high volatility and without etching difficulties. However, spiking tends to occur at the junction of the aluminum and silicon. The solution of spiking is to form a barrier layer made from a conductive material between the aluminum layer and silicon. By forming the barrier layer, the adhesion force of tungsten to other material can be also improved. The barrier layer can be formed from TiN or TiW.
On the other hand, copper has been intensively studied as a new candidate for metal interconnects because of its lower electrical resistivity and better electromigration resistance than aluminum. However, for the successful application of copper metallization, fast diffusivity and high oxidation of copper must be solved. Although several metal nitirides and metal oxides have been investigated to improve these problems, they also increase the complex of metallization process and sheet resistance of copper interconnection line; thus, a stable copper metallization system was not easy to obtain.
Referring to FIG. 1A.about.1C, a conventional process for forming a barrier layer is shown. As shown in FIG. 1A, a semiconductor device 11 is first formed. Then, referring to FIG. 1B, an oxide layer 12 is deposited to cover the semiconductor device 11 by CVD. Then, by performing a photolithography process, an opening 13 is etched to formed at the oxide layer 12.
Next, referring to FIG. 1C, a barrier layer 14 is deposited to cover the periphery and the bottom of the opening 13. The material of the barrier layer 14 can be TiN. Next, a tungsten plug layer 15 is deposited by CVD to fill the opening 13 and to cover the barrier layer 14. A chemical mechanical polishing (CMP) process is then performed to polish the tungsten plug layer 15 until the surface of the oxide layer 12 is exposed and the upper surface of the tungsten plug is about at the same level as the upper surface of the oxide layer 12.


The present invention relates to a film for blocking ultraviolet rays that has excellent light resistance, thus exhibiting stable UV blocking performance for a long time, and has a low haze value, and thus is suitable for protecting an organic light emitting device and the like from the external light source.

Among solar rays, ultraviolet rays corresponding to the region of about 10 to 400 nm has higher energy than visible rays or infrared rays, and thus has an energy level capable of exciting or cutting the molecular bond of organic compounds and the like.
Particularly, an organic light emitting device (OLED) has recently been widely used as a material for displays, and if it is exposed to ultraviolet rays and blue light of 405 nm or less, damage to organic compounds such as blue light emitting materials existing in the organic material layer, and shrinkage of pixel diaphragm or outgassing, and ultimately loss of the function of a device, may occur.
Thus, in order to protect OLED devices from ultraviolet rays, a technology of introducing a coating layer including organic dyes capable of absorbing UV on the OLED devices has been suggested. However, the organic dyes, if exposed to UV for a long time, may be degraded and gradually lose the UV absorbing property, and thus cannot maintain the initial UV blocking performance, and ultimately may cause deterioration of the life cycle characteristic of OLED products.
Therefore, there is a demand for the development of a film for blocking ultraviolet rays having excellent light resistance that can effectively protect an OLED device from external light.


The invention provides an aqueous formulation comprising a pharmaceutically active agent present within vesicles suspended in an aqueous carrier. The invention resides in the finding that improved therapeutic efficacy can be achieved by providing the active agent both in the vesicles themselves and in the aqueous carrier vehicle. The invention provides a formulation which comprises: an aqueous vehicle; vesicles suspended in the aqueous vehicle; and a pharmaceutically active agent comprised within both the vesicles and the aqueous vehicle.

The first line drugs currently used for the treatment of visceral leishmaniasis are pentavalent antimony compounds such as sodium stibogluconate and meglumine antimoniate. These drugs due to their polar nature are inactive by the oral route and undergo rapid renal excretion following dosing by the parenteral route, which necessitates a multiple dosing regime. Compliance with such a regimen is difficult to achieve in remote areas such as the Sudan where visceral leishmaniasis is endemic and has reached epidemic proportions. Development of a vesicular formulation of such antimonial drugs could increase their efficacy, allowing both the number of doses and dose size to be lowered.
The constituents of a vesicular formulation can influence vesicle characteristics (e.g. stability, size, charge) and hence its suitability as a drug carrier system and depending on the intended usage the requirements of the formulation can be drug specific. In our previous studies using a murine model of visceral leishmaniasis we have shown that vesicle size is important since elimination of Leishmania parasites from deeper sites such as the spleen required the use of small, drug loaded vesicles. Incomplete removal of parasites from these sites results in relapse and probably underlies the 2-8% relapse rate reported after antimonial therapy.
Diverse non-ionic surfactants can be used to form vesicles with potential therapeutic applications such as drug delivery (Ozer et al., 1991) and immunological adjuvants (Brewer and Alexander, 1993). We have already demonstrated (Carter et al., 1989a,b) that stibogluconate loaded non-ionic surfactant vesicles are as effective as drug loaded liposomes for improving the treatment of experimental visceral leishmaniasis.
It is an object of the present invention to provide such a vesicle formulation of improved efficacy. This and other objects of the present invention will become apparent from the following description and examples.


An inkjet recording apparatus which discharges ink onto a recording medium in response to an image signal. The above inkjet recording apparatus has an ink accommodating portion which has a plurality of ink chambers each of which accommodates ink therein and is integrally formed, thereby the ink pressurization characteristics between the ink chambers is uniform.

1. Field of the Invention
The present invention relates to an inkjet recording apparatus that prints onto a recording medium such as copying paper by discharging ink in response to an image signal.
2. Description of the Related Art
Conventionally, an inkjet recording apparatus that prints onto a recording medium such as copying paper by discharging ink which fills up an ink chamber in response to an image signal has been proposed. In this type of recording apparatus for example, the inkjet head 90 as disclosed in U.S. Pat. No. 5,471,232 has been used as an ink discharge means.
FIG. 1 shows the above-mentioned inkjet head 90. This inkjet head 90 is comprised by spacers 94 fixed to a nozzle plate 92 where a plurality of nozzle holes 91 are formed. Said spacers 94 divide the chamber to form the ink chambers 93 which correspond to each nozzle hole 91. A vibration plate 95 is fixed to the lower portion of the spacers 94. Island portions 96 formed on the lower surface of this vibration plate 95 by means of electroforming are fixed to the top surface of a piezoelectric member 97.
In an inkjet head 90 comprising the above-mentioned construction, the piezoelectric member is made to expand and contract by applying a voltage to the piezoelectric member 97. Then, the deformation of the piezoelectric member 97 is efficiently transferred through the island portions 96 to the vibration plate 95 to either expand or contract the vibration plate. Thereby, ink inside the ink chambers 93 is pressurized by means of the vibration plate 95 after which ink droplets are discharged from the nozzle holes 91.
However, because there are a large number of members and assemblies used to form the ink chambers 93 for said inkjet head 90, irregularity in the dimensions and assembly precision of each ink chamber 93 easily occurred. As a result there are other problems such as changes in the ink pressurization characteristics due to the vibration plate and uneven diameter of the ink droplets to be discharged occurring between the ink chambers 93. Furthermore, in a type of inkjet head that pressurizes the ink chambers 93 by means of the vibration plate 95, the vibration of the piezoelectric member 97 for one ink chamber 93 is transferred to the ink housed inside the adjacent ink chambers 93 through the vibration plate 95 making the surface tension of the ink unstable. Thereby, a problem occurs in which ink leaks from the ink chamber that should not discharge ink.

Ink jet head and recording apparatus having concave portions


A modular cart that includes a main cart, a first modular cart frame, and a second modular cart frame is described. The main cart further includes a handle end with a first base component that is mechanically coupled to at least one caster. The main cart also includes a first bar disposed on a distal end of the first base component that extends to a second base component, in which the first bar is orthogonal to the second base component and the first base component. A first bay perimeter is bounded by the first base component, the first bar and the second base component. The main cart further includes a second bay perimeter is bounded by a second base component, a second bar and a third base component.

Carts come in different shapes and sizes such as platform trucks, utility carts, two-shelf carts or the like. Carts are generally designed for a particular purpose, and that purpose is relatively limited, so multiple carts are purchased at a great expense. For example, carts are used for transporting a variety of materials in a wide variety of environments such as warehousing, maintenance, housekeeping, and construction.
A first illustrative cart is the laundry carts that may include an attached fabric linen bag for stowing dirty towels and bed sheets. The laundry cart may be a dedicated cart that is just used to capture dirty linens.
Another illustrative cart is the utility cart. This type of cart includes at least one shelf and a handle at one or both ends for pushing or pulling the cart. In addition to transporting material, the top shelf of the cart may be used as a work surface.
Yet another illustrative cart is the housekeeping or "maid" cart that is constructed for room make-up and linen changes. The maid cart may include linen bags that are suspended within the handles of the carts, in which the housekeeper can place dirty linens. In addition to the linen bag, the housekeeping cart may include supplies that are used to clean multiple rooms, as well as clean towels, clean linens, amenities such as soaps and shampoos, and a trash bag used to collect waste from the waste baskets. The fully loaded housekeeping cart is then pushed by the housekeeper along a predetermined route.


The identification tag is provided in a general horseshoe shape with resilient prongs engageable to a shaft such as a shaft of a pulley-mounted hook at a beginning of a processing line. The identification tag can be used to track a product throughout the processing line.

Although many forms of identification tags existed, there remained unaddressed needs. For instance, many slaughterhouses have a processing line where the carcasses are carried by a pulley-mounted hook across various transformation steps to turn them into animal product, often including harsh environments such as flames used to burn the carcasses' hair, very cold temperature to quickly freeze the animals, agents to clean the hooks, etc. While various forms of identification tags existed for tracking the identity (provenance, etc.) of the live animal, there was a need to continue to track the carcass or meat as it was carried across various transformation steps in the slaughterhouse to ensure that the animal product resulting therefrom is associated with the right animal when they exit the slaughterhouse. Other types of production lines where products are suspended from pulleys had similar needs in terms of tracking the conveyed products. Such similar tracking needs may occur in the pulp and paper industry or metallic component production, for instance.

Identification tag adapted to be clipped to a shaft


Methods and apparatus for positioning a non-expandable liner hanger in a wellbore. A liner is coupled to the liner hanger, wherein the liner hanger comprises: a conduit body; and a reactive metal sealing element disposed on the conduit body, wherein the reactive metal sealing element comprises a reactive metal having a first volume. An example method includes contacting the reactive metal with a fluid that reacts with the reactive metal to produce a reaction product having a second volume greater than the first volume; and contacting a surface adjacent to the reactive metal sealing element with the reaction product to form a seal against the surface and to anchor the liner hanger from the surface, wherein anchoring the liner hanger to the surface suspends the liner in the wellbore.

In some wellbore operations, a liner may be suspended from a casing string or set cement layer with a liner hanger. The liner hanger anchors to the interior of the casing string or set cement layer and suspends the liner below the casing string or set cement layer. The suspended liner and the liner hanger do not extend to the surface as a casing string or set cement layer may. A liner hanger forms a seal with the casing string or set cement layer to prevent fluid flow therein from outside of the suspended liner. The fluid flow may be directed through the liner instead.
Sealing elements may be used for a variety of wellbore applications including forming annular seals in and around liner hangers and anchoring liner hangers to suspend the liner. The annular seal may restrict all or a portion of fluid and/or pressure communication at the seal interface. These sealing elements may seal and anchor the liner hangers to the adjacent surface such as the casing string or set cement layer. Some species of sealing elements comprise swellable materials that may swell if contacted with a specific swell-inducing fluid.
Many species of the aforementioned swellable materials comprise elastomers. Elastomers, such as rubber, swell when contacted with a swell-inducing fluid. The swell-inducing fluid may diffuse into the elastomer where a portion of the fluid may be retained within the internal structure of the elastomer. Swellable materials such as elastomers may be limited to use in specific wellbore environments (e.g., those without high salinity and/or high temperatures). The present disclosure provides improved apparatus and methods for sealing around and anchoring liner hangers in wellbore applications.
The illustrated figures are only exemplary and are not intended to assert or imply any limitation with regard to the environment, architecture, design, or process in which different examples may be implemented.


An array substrate, a display panel and a display device are provided. The array substrate includes a base substrate including a display region and a peripheral region, the peripheral region including a gate driving circuit region, a driving bonding region and a first communication region; a first common electrode line, located in the first communication region; a second common electrode line, located on a side of the gate driving circuit region away from the display region; and a third common electrode line, located in the gate driving circuit region. The second common electrode line is electrically connected to the first common electrode line, the third common electrode line includes a first end close to the driving bonding region and a second end close to the first communication region, the second end of the third common electrode line is insulated from the first common electrode line.

At present, display panels have been more and more widely used in the market. For example, thin film transistor liquid crystal display (TFT-LCD), organic light emitting diode display (OLED), etc., have been widely used in terminal devices such as televisions, laptops, and mobile phones. With the rise of narrow-frame terminals and the advantages of low cost of twisted nematic (TN) type TFT-LCDs, etc., narrow-frame TN-type TFT-LCDs have gained more development.

Array substrate, display panel and display device

BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.


A substantially planar shipping container blank is configured for planar stacking to permit compact packaging but simplifies the ease of assembly into a triangular shipping container. The container blank is foldably divided into a rectangular longitudinal section, two end sections, and a closure tab. The interior surfaces of certain portions of the end sections are pre-mounted to the interior surface of the longitudinal section. By folding the longitudinal section of the blank along two pre-pressed longitudinal fold lines, the end sections of the blank automatically fold along pre-pressed angular fold lines to form a triangular shipping container. The container can thereafter be fastened shut by folding the closure tab along a third pre-pressed longitudinal fold line and affixing the tab to the exterior of the container.

1. Field of the Invention
This invention relates generally to the field of shipping containers and relates more particularly to a shipping container blank that is configured for easy assembly into a triangular shipping container and a method for preparing the same.
2. Description of the Related Art
Triangular containers for shipping and storing various items are well known in the art. To conserve space and simplify handling, such containers are themselves typically shipped and stored in the form of unassembled planar blanks that must be folded and glued, taped, and/or stapled to produce complete, assembled containers. Assembly of a container often requires numerous portions of a blank to be folded and fastened together, which can be time consuming and labor intensive. This folding and fastening of the prior art blanks is ordinarily entirely performed immediately before the object to be shipped is placed in them by the user. If the blanks were folded by their manufacturer before being packaged and shipped to the user, the blanks become bulky and therefore inefficient and more expensive to package, inventory and ship.
It would therefore be desirable to have a shipping container blank that is substantially planar so it can be compactly and efficiently packaged and stored before use but additionally is constructed in a way that reduces the amount of folding and fastening manipulations that the user must perform in order to assemble it into a triangular shipping container.


A system and method is provided that displays graphical symbology that enables a pilot to rapidly discern (1) that a neighboring aircraft is a rotorcraft, and (2) whether the rotorcraft is hovering. The provided system and method enables a user to define hovering, by editing a position change (distance) within a predetermined time.

In addition to maintaining an active out-the-window scanning activity, pilots rely on various tools and displays to provide necessary information for maintaining situational awareness. Information about neighboring aircraft traffic may be visually presented on one or more onboard displays including, but not limited to, a primary flight display, a multifunction display, and/or navigation display in a top-down, moving map format. Applications such as CDTI (Cockpit Display of Traffic Information) and ACAS (Airborne Collision Avoidance System) provide the onboard display with the visual information. A source of aircraft surveillance technology such as Automatic Dependent Surveillance-Broadcast (ADS-B) typically provides the traffic information to be displayed via a moving map display, CDTI or ACAS.
In the course of maintaining an active out-the-window scanning activity, pilots may have extended periods of time during which they are only periodically paying attention to the moving map display. Therefore, the graphic display of information on the moving map display should be such as to clearly present the information in a manner that promotes at-a-glance situational awareness.
Rotorcraft are a unique category of aircraft traffic in that a rotorcraft's status may be "hovering" or "not hovering." Human eyes have limitations in spotting motionless objects, and discerning whether a traffic object is a rotorcraft and whether it is or is not hovering is difficult and the time consumed thereby is excessive. Therefore, it is important to the operation and safety of both fixed wing and rotary wing aircraft to be aware of hovering rotorcraft.
Accordingly, a system and method that displays graphical symbology that enables a pilot to rapidly discern that (1) a neighboring aircraft is a rotorcraft, and (2) whether the rotorcraft is hovering, is desirable. It would also be desirable to provide a system and method that enables a user to define hovering, by editing a position change (distance) within a predetermined time.

System and method for graphically displaying neighboring rotorcraft


A rotatable hydraulic grapple apparatus comprises a yoke assembly having attached to it a hydraulic motor and having within it a channel. A housing is rotatably connected to the yoke assembly and is capable of being rotated by movement of the hydraulic motor. The housing is centered along the longitudinal axis of the yoke assembly such that the longitudinal axes of both the yoke assembly and the housing are collinear. The channel in the yoke assembly communicates with a manifold in the housing. The housing has rigidly attached to it a plurality of chambers, each chamber containing an hydraulic actuator rigidly attached within the chamber. Attached to each hydraulic actuator is a grapple tine. A pressurized fluid supply provides fluid to the yoke assembly channel which communicates the fluid to the housing manifold. The fluid is then communicated from the manifold to each actuator for movement of the actuator which in turn moves the grapple tines. The housing and chambers completely enclose the actuators and the fluid supply to the actuators so that no cavities or fluid lines are exposed to the operating environment of the grapple. The walls of the housing are interconnected in a way which provides greater rigidity to the structure over the prior art.

The invention relates to a rotatable hydraulic grapple suitable for use in retrieving, lifting, transporting, and unloading materials of various shapes, sizes, and compositions. Various forms of hydraulic grapples exist in the prior art. These prior art designs have certain limiting attributes which this invention overcomes. These limitations include: exposed hydraulic lines or hoses which are susceptible to tearing and other damage because of the environment in which grapples are used; exposed and open cavities among and between the various structural parts of the grapple which tend to get clogged with material and debris thereby inhibiting the effective performance of the grapple; non-rotatable grapples which restrict the grapple user from choosing more preferable and useful orientations of the grapple during its use. The existence of external hoses and lines also restricts the rotatable movement even of those grapples which are rotatable because the distance of rotation is restricted by the length of the lines.
An object of the present invention is to overcome these limitations.


The present disclosure includes a method for manufacturing a pressure transmitter system, comprising steps as follows: providing a capillary adapter and a pressure transmitter, which has at least one diaphragm platform and an isolating diaphragm, which is connected along at least one edge gas-tightly with the diaphragm platform to form a pressure chamber between the isolating diaphragm and the diaphragm platform; welding the capillary adapter to the pressure transmitter; arranging the capillary tube and a capillary tube interface of the capillary adapter relative to one another; welding the capillary tube to the capillary adapter; and plugging a protective hose onto a protective hose seat of the capillary adapter.

Pressure transmitter systems for transferring a media pressure usually comprise a body of the pressure transmitter, i.e. a diaphragm platform with a media facing surface, and an isolating diaphragm, which is connected along at least one edge gas-tightly with the body of the pressure transmitter to form a pressure chamber between the isolating diaphragm and the body of the pressure transmitter, wherein a duct extends through the body of the pressure transmitter to the pressure chamber, and the pressure chamber and the duct are filled with a pressure transfer liquid, in order to transfer to a pressure receiver a media pressure acting on the isolating diaphragm. Such pressure transmitter systems further comprise a capillary tube and a capillary adapter, wherein the capillary tube is connected via the capillary adapter to the body of the pressure transmitter, i.e. diaphragm platform, in order to transfer the media pressure to the pressure receiver.
In order to manufacture such a pressure transmitter system, a complicated and expensive manufacturing process is needed. In such case, first, the capillary tube is inserted into a traversing bore of the capillary adapter, until the tube has traveled to become essentially flush with an end face of the capillary adapter. At this end face, then the capillary tube is welded to the capillary adapter, before the adapter with the capillary tube is affixed to the body of the pressure transmitter. The affixing of the capillary adapter with the capillary tube to the body of the pressure transmitter occurs then and requires due to the welded attachment of the capillary tube a manual adjusting the capillary tube during the welding.
In the next step, a protective hose is drawn over the capillary tube and led at one end into a bore of the capillary adapter, the bore extending to a defined depth in the longitudinal direction of the capillary adapter and communicating with the traversing bore. The protective hose so introduced into the bore is then affixed to the capillary adapter. This manufacturing process has, such as just indicated, the disadvantage that it is relatively complicated and, thus, also expensive.
Furthermore, pressure transmitter systems manufactured in such a manner have a poor durability in the presence of corrosion promoting environmental conditions, since the weld seam between capillary adapter and capillary tube is not accessible for subsequent treatment and therefore often becomes corroded. This leads, in turn, to the fact that, in the end, oil escapes at the corroded location.
A further disadvantageous aspect of pressure transmitters manufactured in such a manner is that the bore of the capillary adapter, into which the protective hose is inserted, can collect liquids, for example, rain water, which leads, in turn, to increased corrosion in the transition between the bore and the traversing bore.

Method for manufacturing a pressure transmitter system


The present invention relates to a polygonal rib structure having ribs directed orthogonal to one plane and intersecting each other to form polygonal shapes. More particularly, to a shock absorbing polygonal rib structure. In a polygonal rib structure having ribs directed orthogonal to one plane and intersecting each other to form polygonal shapes, a thickened central portion located at a substantially central portion in the longitudinal direction of each side of the polygonal rib is bisected. The opposed parting surfaces formed upon the bisection are spaced from each other to form an opening portion, and each side of the polygonal rib is so shaped that the cross-sectional area of the opening portion is reduced as one goes from the opening end toward the depth. Thus, an opened polygonal rib structure is formed.

A honeycomb structure having a hexagonal cross-sectional shape is disclosed in Japanese Patent Laid-Open No. Hei 9-105013.
The honeycomb structure disclosed in Japanese Patent Laid-Open No. Hei 9-105013 has a structure in which a surface formed by connecting end edges of ribs arranged in a honeycomb shape is a curved surface, and it has been attempted to apply the honeycomb structure to a shock absorbing member for helmets.
In manufacturing this honeycomb structure, as shown in FIGS. 20 and 21 of the drawings, a band-like blank material 01 that is directed rectilinearly in one direction and has a rectangular cross-sectional shape is fed between a pair of truncated conical rolls 02, and is rolled to have an elongate trapezoidal cross-sectional shape as shown in FIG. 21. Thus, a band-like blank material 01A is obtained in which the band-like blank material 01 directed rectilinearly in one direction is spirally wound.
The band-like blank material 01A that is spirally wound is divided into a plurality of portions, for example, three portions evenly over the winding direction, as shown in FIG. 23. The surface of the arcuate band-like blank material 01B is divided at regular angular intervals from the spiral center O into sections (X1, X2, X3, X2) (X1, X2, X3, X2) . . . , as shown in FIG. 22. In the surface of one of the adjacent arcuate band-like blank materials 01B, an adhesive is applied to the sections X1 intermediated by the three sections X2, X3, X2. In the surface of the other of the adjacent arcuate band-like blank materials 01A, an adhesive is applied to the central section X3 located at an intermediate position between the adhesive-coated sections X1. After curing of the adhesives, both upper and lower end portions of the band-like blank materials 01B that are divided into arcuate forms are broadened from each other as shown in FIG. 24, whereby a honeycomb structure as shown in FIG. 14 can be manufactured.
In order to manufacture the honeycomb structure disclosed in Japanese Patent Laid-Open No. Hei 9-105013, a process is used in which the rectangular band-like blank material 01 having a cross-sectional shape with a fixed thickness over the longitudinal direction is formed into the band-like blank material 01A having an elongate trapezoidal cross-sectional shape. It is necessary to prepare a band-like blank material 01 which is free of dispersions in the width direction and in the thickness over the longitudinal direction thereof. At the same time, it is necessary that the accuracy of the outer peripheral surfaces of the pair of truncated conical rolls 02 and the accuracy of the parallelism and size between the roll axes should be high. Moreover, a large number of working steps is required. As a result, productivity is low, and it is impossible to obviate a high cost.
In addition, it has been difficult to apply the structure disclosed in Japanese Patent Laid-Open No. Hei 9-105013 to polygonal rib structures other than the honeycomb structure.

Openinged polygonal rib structure and polygonal rib structure


A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

Accompanying the miniaturization and performance enhancement of electronic equipment in recent years, the number of pins in a semiconductor element included in the electronic equipment increases and various types of electronic components constituting the electronic equipment become smaller. Accordingly, there has been a dramatic increase in the number and density of wirings in a printed board on which they are mounted. In particular, the number of leads led out from the semiconductor element (semiconductor chip) and the number of terminals have increased rapidly, so that the printed board (wiring board) becomes increasingly finer. Consequently, fine pitch connection techniques are gaining greater importance.
The fine pitch connection techniques can be divided broadly into a wire bonding (WB) method, a flip chip bonding (FC) method, and a tape automated bonding (TAB) method, each of which will be described briefly in the following.
According to the wire bonding (WB) method, electrodes of a semiconductor chip and electrodes of a lead frame are connected to each other mainly using gold wires (diameter: 20 to 25 μm). The connection is achieved through solid phase diffusion caused by applying heat or ultrasonic waves to the gold wires and the electrodes of both the semiconductor chip and the lead frame. The WB method is disclosed in Patent Document 1, for example. According to the flip chip bonding (FC) method, bumps (protruding electrodes) are formed on a semiconductor chip, and these bumps are connected to electrodes on a wiring board. The FC method is characterized in that it provides a configuration in which a surface on which the electrodes are formed (hereinafter, referred to simply as an "electrode-formed surface") of the semiconductor chip and an electrode-formed surface of the wiring board face each other. The FC method is disclosed in Patent Document 2, for example. According to the TAB method, semiconductor chips first are connected to a long tape provided with lead wirings. The chip provided with the lead then is punched out from the tape, and the lead is connected to a substrate. Basically, the TAB method is carried out automatically through a reel-to-reel process. The TAB method is disclosed in Patent Document 3, for example.
Patent Document 1: JP 4(1992)-286134 A
Patent Document 2: JP 2000-36504 A
Patent Document 3: JP 8(1996)-88245 A
The WB method disclosed in Patent Document 1 will be described with reference to FIGS. 21A and 21B. FIG. 21A is a top view showing the wire-bonded state, and FIG. 21B is a cross-sectional view taken along a line I-I in FIG. 21A.
According to the WB method, a semiconductor chip 501 is die-bonded to a portion (a die pad) of a lead frame 504, and then wire bonding pads 502 of the semiconductor chip 501 and external terminals 505 (inner lead portions) of the lead frame 504 are wire-bonded using bonding wires 503. Thereafter, a region including the semiconductor chip 501 and the inner lead portions of the external terminals 505 is encapsulated with an encapsulation resin 506, whereby, for example, a resin-encapsulated body (a semiconductor module) 500 as shown in FIG. 22 is obtained. The external terminals 505 exposed from the encapsulation resin 506 are connected to a wiring board (not shown), whereby the semiconductor chip 501 is connected electrically to the wiring board.
However, the WB method has the following problems. First, there is a problem in that a mounting area of a semiconductor element component (here, this refers to the module 500 including the semiconductor chip 501) is large. That is, in the WB method, since the semiconductor chip 501 is not mounted on the wiring board directly but is connected to the external terminals 505 of the lead frame 504 via the bonding wires 503, it is inevitable that the size of the semiconductor module 500 (the element size or the component side) becomes larger than that of the semiconductor chip 501. Consequently, the mounting area of the semiconductor module 500 becomes large.
Furthermore, since the wire bonding pads 502 of the semiconductor chip 501 and the external terminals 505 of the lead frame 504 are connected to each other one by one with the bonding wires 503, there is a problem in that, as the number of the terminals increases, the time and effort required for the operation increase. Moreover, the pitch of the external terminals 505 on the lead frame 504 defines the pitch of the semiconductor element 500, thus imposing limitations on the narrowing of the pitch.
Next, the FC method disclosed in Patent Document 2 will be described with reference to FIG. 23. FIG. 23 shows a cross-sectional configuration of a semiconductor device 600 mounted by the FC method.
According to the FC method, electrodes 604 of a semiconductor chip 605 are connected to wiring patterns 602 provided on a substrate 601 via bumps 603. More specifically the electrodes 604 of the semiconductor chip 605 that has a sensitive area 606 in which a transistor etc. are formed are connected to the predetermined wiring patterns 602 provided on the substrate 601 via the bumps 603, whereby the semiconductor chip 605 is mounted on the substrate 601 with a space being formed therebetween. Thereafter, an encapsulation resin 607 is formed by inserting resin into the space between the substrate 601 and the semiconductor chip 605 so as to embed the wiring patterns 602, the bumps 603, and the electrodes 604 in the resin. The semiconductor device 600 for which the FC method is employed is configured as above.
However, the FC method has the following problems. First, there is a problem in that aligning the semiconductor chip 605 is difficult. According to the FC method, since the semiconductor chip 605 is mounted on the substrate 601 with its electrode-formed surface facing downward, the bumps 603 of the semiconductor chip 605 cannot be seen directly from the outside. This makes the alignment very difficult. Moreover, the pitch of the electrodes 604 of the semiconductor chip 605 when the FC method is employed is narrower than the pitch of the external terminals 505 when the WB method is employed. This factor also makes the alignment difficult.
Also, there is a problem in that the substrate 601 is liable to be expensive. The reason for this is that, according to the FC method, the substrate 601 is required to have the wiring patterns 602 that are fine patterns corresponding to the pitch of the electrodes 604 of the semiconductor chip 605. Another reason is that, when the electrodes 604 of the semiconductor chip 605 are arranged in an area array form, the substrate 601 is liable to have a multilayer structure. Moreover, when the FC method is employed, the semiconductor chip 605 is connected to the substrate 601 via the bumps 603. Thus, unless the coefficient of linear expansion of the semiconductor chip 605 is made as close as possible to the coefficient of linear expansion of the substrate 601, a stress is applied to the bumps 603 etc. Therefore, it is necessary to match the coefficients of linear expansion of both the semiconductor chip 605 and the substrate 601, and the matching of the coefficients of linear expansion needs to be performed strictly. In this respect, the cost of the substrate 601 increases.
Moreover since the semiconductor chip 605 is connected to the substrate 601 via the bumps 603, the heat dissipation is deteriorated. More specifically, since the semiconductor chip 605 is disposed on the substrate 601 with points thereof being in contact with the substrate 601 rather than the surface thereof being in contact with the substrate as in the case of the WB method, the heat dissipation is deteriorated. Also, in the first place, forming the bumps 603 takes time and effort.
Next, the TAB method disclosed in Patent Document 3 will be described with reference to FIGS. 24 and 25. FIG. 24 shows a cross-sectional configuration of a semiconductor device 700 for which the TAB method is employed, and FIG. 25 shows a configuration in which this semiconductor device 700 is mounted on a mounting board 709.
The semiconductor device 700 shown in FIG. 24 includes a base film 702 of a film carrier tape and a semiconductor IC chip 701 arranged in a device hole 702b provided in the base film 702. Copper foil wirings 703 are formed on the base film 702, and electrodes 701a of the semiconductor IC chip 701 are connected to inner leads 703a provided in inner end portions of the copper foil wirings 703. Lands 703b for external connection are provided at portions of the copper foil wirings 703 on the outer side relative to the inner leads 703a, and solder bumps 706 are formed on the lands 703b. Through holes 702a are provided in the base film 702. At the center of each of the lands 703b, a pore 703c is provided. A cover resist 704 is formed on the film carrier tape excluding the portions where the lands 703b are formed. An encapsulation resin 705 for protecting the semiconductor IC chip 701 is provided in the device hole 702b.
In this semiconductor device 700, the solder bumps 706 serve as outer leads, and as shown in FIG. 25, the solder bumps 706 are connected to pads 709a on the mounting board 709. The semiconductor device 700 for which the TAB method is employed is mounted on the mounting board 709 by a mass reflow process.
However, the TAB method has the following problems. First, since an inner lead bonding (ILB) step and an outer lead bonding (OLB) step are separate steps, it takes time and effort to perform the TAB method. More specifically, in the example shown in FIG. 24, the step of connecting the inner leads 703a to the electrodes 701a of the semiconductor IC chip 701 and the step of forming the solder bumps 706 at the lands 703b are different types of steps, which complicates the operation. Furthermore, it is also necessary to encapsulate the semiconductor IC chip 701 arranged in the device hole 702b with the encapsulation resin 705, which also takes time and effort. In addition, there is a different type of problem in that, because the base film 702 having a larger area than the semiconductor IC chip 701 is used, the mounting area increases.

Mounted body and method for manufacturing the same


The present disclosure provides a method of user clustering, and the method includes: acquiring a clustering condition for a predetermined user group, wherein the clustering condition includes a time selecting condition and an event selecting condition; determining at least one target time period for each user behavior data in a user behavior database based on the time selecting condition; determining association data indicating a relationship between the each user behavior data and each target time period based on the each user behavior data and the each target time period; and selecting target association data for a time period to be monitored based on the time period to be monitored and the event selecting condition, so as to determine a target user belonging to the predetermined user group according to the target association data. The present disclosure also provides an apparatus of user clustering, a computer device and a non-transitory medium.

User clustering refers to a process of selecting users according to needs of business scenarios, and selecting target user groups that meet predetermined clustering conditions. Results of user clustering may be used in an analysis process of website or application about user behaviors of user groups. Generally, users may be clustered according to user data, and the user data may include user attribute data and user behavior data. In a scheme of user clustering based on the user behavior data, related art needs to routine a query and storage logic for a user behavior database once for each predetermined time period, which results in occupying a large amount of computing resources and storage space, and has a poor flexibility.

Method and apparatus of user clustering, computer device and medium

BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.


An ultrasonic fluid-gauging probe has a still well and two or more piezoelectric transducer elements mounted at its lower end. A drive and processor unit may separately energize each element and provide a separate output indicative of fluid height so as to provide redundancy. Alternatively, one element may be energized and the other used to receive the reflected signal in normal use but, when a fault is detected, one element may be used to both transmit and receive. The elements may be mounted side-by-side, such as on a common substrate, or one above the other in a stack.

This invention relates to fluid-gauging probes.
Ultrasonic fluid-gauging probes, such as for measuring the height of fuel in an aircraft fuel tank, are now well established and examples of systems employing such probes can be seen in U.S. Pat. No. 5,670,710, GB2380795, GB2379744, GB2376073, U.S. Pat. No. 6,598,473 and U.S. Pat. No. 6,332,358. The probe usually has a tube or still well extending vertically in the fuel tank and a piezoelectric ultrasonic transducer mounted at its lower end. When the transducer is electrically energized it generates a burst of ultrasonic energy and transmits this up the still well, through the fuel, until it meets the fuel surface. A part of the burst of energy is then reflected down back to the same transducer. By measuring the time between transmission of the burst of energy and reception of its reflection, the height of fuel in the still well can be calculated.
Because the probe only has one transducer, failure or partial failure of the transducer or its associated electrodes or electrical circuit results in a complete loss of information from the probe. In order to provide sufficient reliability and redundancy in, for example, aircraft applications, it is usual to provide additional probes so that sufficient information can be provided in the event of probe failure. This leads to extra cost and weight.


The present invention provides a method of joining members to be joined by use of an Au—Sn brazing material, in which joining is performed by adjusting the composition and thickness of the Au—Sn brazing material so that the Sn content of the joint after joining is from 20.65 to 23.5 wt %. The invention has been completed on the basis of the discovery that the true eutectic point of this alloy system corresponds to 20.65 wt % Sn. In the invention, as means for adjusting the composition of a resulting joint, it is necessary to appropriately adjust the composition and thickness of a brazing material according to the thickness of a gold plating. In the invention, the relationship between the brazing material thickness and the gold plating thickness is shown when the brazing material to be used has an Sn content of 21 wt % to 25 wt %.

1. Field of the Invention
The present invention relates to a method of joining by use of an Au—Sn brazing material, for example, in joining a lead pin to a circuit terminal or sealing a semiconductor package.
2. Description of the Related Art
Au—Sn brazing materials are brazing materials in which eutectic structures of Au—Sn alloys are used, and have relatively low melting points (about 280° C.). In addition, Au—Sn brazing materials are excellent in corrosion resistance and have the advantage that they do not contain harmful substances such as Pb unlike solders (Sn-37 wt % Pb) that have thitherto been used. Au—Sn brazing materials are widely used in the field of electrical and electronic equipment and have been field proven, for example, as sealing materials for the hermetic sealing of electronic part packages and joining materials for joining lead pins to circuit terminals.
Although basically a joint formed by an Au—Sn brazing material has an Au—Sn eutectic structure, an Au—Sn alloy phase having a high Au content (hereinafter referred to as an Au rich phase) may sometimes occur partially. This Au rich phase, which is a kind of intermetallic compound, is hard and has a higher melting point than the surrounding Au—Sn eutectic phase. Therefore, this Au rich phase does not dissolve at the melting points of brazing materials and remains as a solid phase. And because the Au rich phase is diverse in size, variations may sometimes be produced in the thickness of a joint. In particular, in a joining method using Au—Sn brazing materials, joining is often performed by plating parts to be joined with gold in order to improve wettability. Owing to the diffusion of gold from this gold plating, the gold content in a joint rises and an Au rich phase becomes apt to occur. Also, in the composition range in which this Au rich phase occurs, the crystal structure becomes coarsened and the solder flow becomes worse, thus posing a problem.
The present applicant has so far disclosed a sealing method and a joining method that are effective in the above-described uses (Japanese Patent No. 3086086, Japanese Patent Laid-Open No. 2001-176999). In these methods, compared to Au—Sn brazing materials of Au-20 wt % Sn that have hitherto been used, there are used brazing materials having a composition slightly displaced from a eutectic point, in which the gold content is lowered and the Sn content is raised to 20.5 through 21.5%. In these methods, by using a brazing material of low gold content, the composition of the brazing material is prevented from deviating from a eutectic point to the gold side even when the gold content in the brazing material rises during joining due to the diffusion of gold from outside and the occurrence of a gold rich phase is suppressed. A joint formed by these methods has a complete eutectic structure or a eutectic structure containing a small amount of Sn rich phase. Compared to an Au rich phase, an Sn rich phase has a low melting point, exerts a small effect and suppresses the coarsening of a structure by suppressing the occurrence of an Au rich phase. Therefore, by causing a joint having such a structure like an Sn rich phase to be formed, it becomes possible to perform joining in a stable manner.
The methods disclosed by the present applicant can efficiently form good joints although the methods are simple ones that involve slightly changing the composition of a brazing material to be used. However, according to examinations by the present inventor, although in most cases good joints are obtained by using this brazing material the composition of which is adjusted, in some cases an Au rich phase occurs and satisfactory joints may not be formed. Although the fraction defective itself on that occasion is not high, from the standpoint of ensuring product yield and effective utilization of resources, it is desirable to cause the fraction defective to approach zero as far as possible if this is possible.
The present invention has been made against the above-described background and has as its object the provision of a joining method using an Au—Sn brazing material that completely suppresses the occurrence of an Au rich phase and can form a homogeneous joint with higher probability.

Joining method by Au-Sn brazing material


A bending machine, capable of accurately bending a workpiece to a desired angle while protecting the workpiece from damage, comprises an upper die fastened to a ram, which is movable vertically and acts in cooperation with a stationary table to fix a workpiece to be bent, a bending blade selection arm which can be vertically swung by a bending blade selection cylinder and to which a downward bending beam and an upward bending beam are fastened in such a manner that the downward bending beam and the upward bending beam are able to swing while being vertically separated from each other, a downward bending blade for bending the workpiece downwardly when the downward bending beam is swung by a downward blade swing cylinder, and an upward bending blade for bending the workpiece upwardly when the upward bending beam is swung by an upward bending blade swing cylinder. Therefore, the upward and the downward bending blades do not rub the workpiece.

1. Field of the Invention
The present invention relates to a bending machine capable of bending a plate-like workpiece while protecting it from damage.
2. Related Art
In a case where a plate-like workpiece is bent, so-called "spring back" takes place, which is a phenomenon causing the bent workpiece to be slightly deformed from the desired shape due to an elastic restoration of the bent workpiece.
Hitherto, a workpiece has been bent by a surplus amount to take the aforesaid "spring back" into account so as to obtain the desired shape. In order to bend the workpiece as described above, it has been known, for example, Japanese Published Unexamined Utility Model Application No. (U) 61-152325, to adapt a bending machine in such a manner that a bending blade is disposed at the leading portion of a rocker arm to be rotated in a vertical direction by a double action actuator so as to bend the workpiece by the bending blade which is moved by the vertical movement of the rocker arm, and an eccentric member for supporting the base portion of the rocker arm is rotated so as to horizontally displace the overall body of the rocker arm, so that the amount of the "spring back" is corrected.
However, a problem arises in that the quality of the product deteriorates in a case where a workpiece, the surface of which has been treated with a surface treatment such as a coating or zinc plating, is bent because the aforesaid bending machine performs the bending operation in a state where the bending blade rubs the workpiece, and therefore the surface of the workpiece is damaged. What is worse, the cost of a control system cannot be reduced because complicated control must be performed to obtain a desired bending angle.
In a case where a panel arranged as shown in FIG. 19 is formed from a plate-like workpiece a, a shorter side edge b of the workpiece a is bent first, then the workpiece a is rotated by 90.degree. so that a clamping die or an upper die is adjusted to the width to be bent which is aligned to the inside of the bent portion of the shorter side edge b, and then a longer side c is bent.
In a bending operation of the aforesaid type, the upper die for bending the longer side edge c must have a length obtained by subtracting thickness corresponding to those of two workpieces a from the length of the longer side because the bent shorter side edge b has been raised. In addition, the die must be separated after it has bent the longer side edge c in such a manner that the die cannot be caught by the shorter side edge b. Technology capable of achieving the aforesaid requirement has been disclosed in Japanese Patent Publication No. 1-16568 in which the interference is prevented by arranging the structure in such a manner that an opening die, which can be rotated by a pin or a link, is disposed on a corner of the upper die.
However, each of the aforesaid opening dies is structured in such a manner that it is rotated by the dead weight thereof to prevent the interference. Therefore, when the ram starts moving upwardly at the time of separating the die, the opening die moves to prevent the interference while being in contact with the upper surface of the workpiece which has been molded. Also at the time of the bending operation, the opening die, which has been moved to a position at which the interference can be prevented with the downward movement of the ram, moves to the position at which molding is performed while being in contact with the upper surface of the workpiece. Therefore, a problem arises in that the quality of the product deteriorates excessively due to damage caused from rubbing in a case where the workpiece is made of colored iron plate or which has been coated with paint.


Aluminum alloys having an improved combination of properties are provided. In one aspect, a method for producing the alloy includes preparing an aluminum alloy for artificial aging and artificially aging the alloy. In one embodiment, the artificially aging step includes aging the aluminum alloy at a temperature of at least about 250° F., and final aging the aluminum alloy at a temperature of not greater than about 225° F. and for at least about 20 hours.

For aluminum alloys, it is generally accepted that fatigue crack growth resistance under spectrum loading generally decreases as strength increases, and vice-versa. See, e.g., Wanhill et al., "Flight simulation and constant amplitude fatigue crack growth in aluminum-lithium sheet and plate", International Congress on Aeronautical Fatigue, Tokyo, Japan, 1991. Additionally, some 7xxx alloys, such as AA7150 or AA7055, realize higher strengths than 2xxx alloys, such as AA2024, AA2026 and AA2099, but also realize significantly lower fatigue crack growth resistance.

Aging of aluminum alloys for improved combination of fatigue performance and strength


A double heterojunction bipolar transistor includes diamond as the semiconductor material for the collector and emitter, while silicon carbide provides the base. Accordingly, the diamond is readily and reproducibly p-doped, and the silicon carbide may be fabricated by a solid state reaction to form an n-type intrinsic semiconductor. The base is preferably not so thick as to greatly increase transit time, yet sufficiently thick to prevent tunneling. In one embodiment single crystal diamond and single crystal silicon carbide are used in direct contact with each other. In another embodiment of the transistor, polycrystalline diamond is used, and a layer of insulating diamond is positioned between each face of the silicon carbide layer and the diamond layers. A method for fabricating the transistor includes depositing silicon on the diamond and annealing same so as to produce silicon carbide by a solid state reaction. The silicon carbide so produced is intrinsically n-type. Alternately, the silicon carbide may be directly deposited.

Bipolar transistors fabricated using conventional semiconductor materials, such as silicon, are widely used. Bipolar transistors offer short electron transit times, thereby offering high cutoff frequencies without particularly stringent demands on lithography as is typically required with Field Effect Transistors (FET's). In addition, the entire emitter area of a bipolar transistor conducts current, unlike a FET in which only a thin surface channel conducts current. Accordingly, a bipolar transistor may provide high current output per unit of chip area, while permitting and maintaining high circuit density.
Continuous progress has been made in building upon the advantages of bipolar transistors while minimizing their shortcomings. The use of heterojunctions, that is, junctions formed of two different semiconductor materials, has added a new degree of freedom in transistor design and enabled higher operating speeds. Considerable improvement in transistor performance may be obtained by intentionally changing the semiconductor material composition of a heterojunction bipolar transistor (HBT) to produce a bandgap that is wider in the emitter, for example. Moreover, appropriate combinations of electric fields and bandgap variations permit the forces on holes and electrons to be established separately. See, for example, Chapter 6 "Bipolar Transistors", by Asbeck in High-Speed Semiconductor Devices, edited by Sze, pp. 358-391 (1990).
As discussed in High-Speed Semiconductor Devices, HBT's have been explored using conventional semiconductor materials having matching lattice constants, such as including GaAlAs/GaAs and InGaAs/InAlAs/InP. U.S. Pat. No. 5,089,428 to Verret et al. entitled Method for Forming a Germanium Layer and a Heterojunction Bipolar Transistor discloses an HBT having an N-Ge.sub.x Si.sub.1-x layer deposited onto an N-Si substrate. The substrate having these layers formed thereon is heated in an oxidizing ambient which causes the p-Ge.sub.x Si.sub.1-x layer to transform into a pure Ge layer.
U.S. Pat. No. 5,117,267 to Kimotor et al. entitled Semiconductor Heterojunction Structure suggests that an HBT may be formed using n-type cubic boron nitride (c-BN) with p-type diamond. Diamond is a preferred material for semiconductor devices because it has semiconductor properties that are better than silicon, germanium or gallium arsenide. Diamond provides a higher energy bandgap, a higher breakdown voltage and a higher saturation velocity than these traditional semiconductor materials.
These properties of diamond yield a substantial increase in projected cutoff frequency and maximum operating voltage compared to devices fabricated using silicon, germanium or gallium arsenide. Silicon is typically not used at temperatures higher than about 200.degree. C. and gallium arsenide is not typically used above 300.degree. C. These temperature limitations are caused, in part, because of the relatively small energy band gaps for silicon (1.12 eV at ambient temperature) and gallium arsenide (1.42 eV at ambient temperature). Diamond, in contrast, has a large band gap of 5.47 eV at ambient temperature, and is thermally stable up to about 1400.degree. C.
Diamond also has the highest thermal conductivity of any solid at room temperature and exhibits good thermal conductivity over a wide temperature range. The high thermal conductivity of diamond may be advantageously used to remove waste heat from an integrated circuit, particularly as integration densities increase. In addition, diamond has a smaller neutron cross-section which reduces its degradation in radioactive environments, that is, diamond is a "radiation-hard" material. Because of the advantages of diamond as a material for semiconductor devices, there is at present an interest in the growth and use of diamond for high temperature and radiation-hardened electronic devices, especially transistors.
A diamond bipolar transistor is disclosed in Bipolar Transistor Action in Ion Implanted Diamond, by Prins, Applied Physic Letters, 41(10), pp. 950-952, Nov. 15, 1992. Prins discloses a p-type base region formed in a single crystal of natural Boron-doped IIb diamond by ion implanting n-type emitter and collector regions, while the p-type base region is masked by a thin tungsten wire. The ion implantation is intended to produce "radiation damaged" n-type collector and emitter regions from the natural diamond.
A diamond bipolar transistor would offer high temperature performance, as well as other advantages of diamond as a semiconductor material. Unfortunately, reproducible n-type behavior in diamond is difficult to achieve in practice.
An article entitled Material-Based Comparison for Power Heterojunction Bipolar Transistors, IEEE Transactions on Electron Devices, Vol. 18, No. 11, November 1991, by Gao and Morkoc discusses a figure of merit based upon material parameters for various HBT's. The article discloses a number of combinations of semiconductor materials for the proposed devices. The article suggests that a wide bandgap material, such as AlGaAs, InP, SiC, GaN or diamond can be used for the base of an HBT. However, as noted in the article, while wide bandgap materials appear to offer an improvement in the figure of merit for an HBT, realization of such devices awaits technological breakthroughs.

Diamond and silicon carbide heterojunction bipolar transistor


A product for electronic transmission of handwritten information, a user unit for recording and sending the information, and a computer program for controlling a user unit are disclosed. The product may include at least one writing area for the handwritten information and an address area indicating an address to which the handwritten information is to be sent. A position-coding pattern in the form of a plurality of symbols may be reproduced in the writing area, an arbitrary position area of a predetermined size of the position-coding pattern unambiguously defining a position on the product. The address area may include an address-coding pattern with a plurality of symbols, an arbitrary address portion of a predetermined size of the address-coding pattern unambiguously defining part of the address.

The amount of information transmitted electronically has increased in recent years. Most of the information transmitted electronically has been generated by means of a computer. There is, however, a great need for electronically transmitting information that has been generated in some other way than by means of computers. For instance, there is a need for transmitting handwritten information in connection with the filling-in of a form. A further example when there is a need for transmitting handwritten information involves advertisements in newspapers. Advertisements in newspapers sometimes have a writing area for handwritten information and a fax number to which the advertisement can be sent.
For a long time the only possibility of sending handwritten information was to use a fax machine. An alternative is to use a scanner for converting the information to a digital image, which can then be transmitted via a computer communication link or via the telephone network. U.S. Pat. No. 5,852,434 discloses a method for entering handwritten information by means of a pen and a base with a coordinate pattern. When writing on the base, the pen records the movement and stores it as positions.
Independently of how the information is entered, a manual step is necessary when transmitting the information.
There is thus a need for an alternative method and a device for more easily transmitting handwritten information such as handwritten text.


The present application provides a microchannel coil manifold system. The microchannel coil manifold system may include a number of assembly inlet manifold sections that terminate in a first stub tube, a number of assembly outlet manifold sections that terminate in a second stub tube, and one or more microchannel coils. Each pair of assembly inlet and outlet manifold sections may be in communication with the one or more microchannel coils.

Modern air conditioning and refrigeration systems provide cooling, ventilation, and humidity control for all or part of an enclosure such as a building, a cooler, and the like. Generally described, the refrigeration cycle includes four basic stages to provide cooling. First, a vapor refrigerant is compressed within a compressor at high pressure and heated to a high temperature. Second, the compressed vapor is cooled within a condenser by heat exchange with ambient air drawn or blown across a condenser coil by a fan and the like. Third, the liquid refrigerant is passed through an expansion device that reduces both the pressure and the temperature of the liquid refrigerant. The liquid refrigerant is then pumped within the enclosure to an evaporator. The liquid refrigerant absorbs heat from the surroundings in an evaporator coil as the liquid refrigerant evaporates to a vapor. Finally, the vapor is returned to the compressor and the cycle repeats. Various alternatives on this basic refrigeration cycle are known and also may be used herein.
Traditionally, the heat exchangers used within the condenser and the evaporator have been common copper tube and fin designs. These heat exchanger designs often were simply increased in size as cooling demands increased. Changes in the nature of the refrigerants permitted to be used, however, have resulted in refrigerants with distinct and sometimes insufficient heat transfer characteristics. As a result, further increases in the size and weight of traditional heat exchangers also have been limited within reasonable cost ranges.
As opposed to copper tube and fin designs, recent heat exchanger designs have focused on the use of aluminum microchannel coils. Microchannel coils generally include multiple flat tubes with small channels therein for the flow of refrigerant. Heat transfer is then maximized by the insertion of angled and/or louvered fins in between the flat tubes. The flat tubes are then joined with a number of manifolds. Compared to known copper tube and fin designs, the air passing over the microchannel coil designs has a longer dwell time so as to increase the efficiency and the rate of heat transfer. The increase in heat exchanger effectiveness also allows the microchannel heat exchangers to be smaller while having the same or improved performance and the same volume as a conventional heat exchanger. Microchannel coils thus provide improved heat transfer properties with a smaller size and weight, provide improved durability and serviceability, improved corrosion protection, and also may reduce the required refrigerant charge by up to about fifty percent (50%).
Microchannel coils generally are connected to the refrigeration system as a whole via an assembly or a refrigerant inlet manifold on one side of the coil and an assembly or a refrigerant outlet manifold on the other side. The microchannel coils may be connected in series, in parallel, or combinations thereof. The refrigerant inlet and outlet manifolds, however, should be able to accommodate these various configurations while permitting ease of installation, access, repair, removal, and/or reconfiguration and the like.
There is a desire therefore for an improved microchannel coil manifold system. Such an improved system should accommodate as many microchannel coils in as many different configurations as may be desired. Preferably, the manifold system may allow the easy reconfiguration of the microchannel coils in the field as well as in the factory.


A multi-function electronic fishing float having an identification number automatically generates radio frequency (RF) signals, if a fish takes bait or is hooked. The generated RF signal is sent to a receiver, and an angler can clearly identify a sign of a fish's bite or hooking through sound, vibration, or light generated by the receiver, without checking the float with eyes.

1. Field of the Invention
The present invention relates to a fishing float and, more particularly, to a multi-function electronic fishing float having an identification number and enabling easy identification of a fish's bite by utilizing radio frequency (RF) communication and signals (sound, vibration, or light).
The multi-function electronic fishing float automatically generates RF signals, and the generated RF signals are sent to a receiver, when a fish takes bait or is hooked.
Additionally, a multi-function electronic fishing float according to the present invention helps an angler clearly identify a bite or hooking of a fish with signals of light, vibration, or sounds (voice or various sounds of music) output from the receiver, even without watching the fishing float continuously.
Additionally, the present invention relates to a multi-function electronic fishing float that minimizes changes of an angler's location when the fishing float is used in flowing water by forming rotating blades at the submerged part of the electronic fishing float.
2. Description of the Prior Art
Generally, basic fishing tackles such as a fishing rod, line, hook, float, and bait are required for fishing.
Presently, various types of fishing floats are being used. The fishing floats are generally formed of materials such as rigid synthetic resin or wood, having an air pocket formed therein to provide buoyancy.
Among such fishing tackles, the fishing float is used to identify a bite or hooking of a fish in water and, particularly, a proper fishing float is used according to the depth of the water.
The fishing float maintains a state that its upper part comes up above the water surface, and moves upwards/downwards in response to the fish's bite. Accordingly, an angler may consider a correct time of pulling a fishing rod and decide whether to pull the fishing rod or not.
However, in the case of fishing with a conventional fishing float, the fishing float with its upper part coming up above the water surface easily moves due to waves generated by wind or flowing water. Therefore, an angler faces difficulties in identifying whether the movement of the float is caused by the fish's bite or by the waves.
Accordingly, there may be a problem of missing a fish, because a fishing rod is not pulled at a correct time in response to the fish's bite, and pulling the fishing rod is not instantly performed.
Additionally, an angler has to watch the float continuously during the fishing. If the fishing is continued for a long time, the angler may face problems of feeling stress and fatigue due to strain in eyes, bloodshot eyes, or losing its eyesight in the worst case.

Abstract: A transmitter sending RF signals corresponding to the fish's bite or hooking is installed in the electronic fishing float that partially comes up above the water surface by buoyancy, and the transmitted RF signals are received by the receiver outputting sound, vibration, and light as information on the fish's bite or hooking.