A thin profile laser pointer assembly includes a thin profile laser head, a constant voltage laser diode driver circuit, and a coin cell power source all packaged within a thin-profile rectangular housing having a thickness between about 2.0 mm and about 6.0 mm. The laser head includes a thin, rectangular heat sink and a laser diode mounted on a recessed shelf on a front edge of the heat sink. The laser head is slidably received in a mounting channel in a front portion of the housing. The arrangement of the laser head and mounting channel rigidly fixes the laser diode in the X and Z axes while permitting sliding linear movement of the laser diode along a "Y" axis, which defines the optical axis of the laser diode. A lens is mounted in the mounting channel along the optical axis, and a projecting aperture is formed in the front edge of the housing in front of the lens for allowing the laser beam to exit through the front of the housing. The laser beam is focused by sliding the laser head within the channel. The laser diode driver circuit and a contact switch are mounted on a circuit board received and secured over the housing. Contact pads on the circuit board engage corresponding contacts on the battery and laser head assembly to complete the circuit. The constant voltage power regulating circuit utilizes a simple shunt regulator circuit which monitors voltage drain as the battery decays and draws appropriate current levels to provide constant power to the laser diode.

The instant invention relates to laser pointer devices, and more particularly to a laser pointer assembly having a thin profile laser head and housing structure.
Laser pointing devices are generally well known in the prior art. In this regard, the U.S. Patents to Lo U.S. Pat. No. 5,268,829; Jehn U.S. Pat. No. 5,307,253; Huang U.S. Pat. No. 5,335,150; Knowles U.S. Pat. No. 5,473,464; and Jehn U.S. Pat. No. 5,446,635 are representative of the current state of the art. As will be apparent from a review of the above-noted laser pointer devices, it is a common design feature that the laser pointer devices are packaged in cylindrical housings. The reason for this common feature is the fact that many commercially available laser diodes are pre-packaged in a cylindrical can assembly such as that generally indicated at 10 in FIG. 1. Referring to FIG. 1, the prior art laser head 10 include a cylindrical mounting head 12 having an integral heat sink 14, a laser diode 16 mounted on the heat sink 14, and a window 18 supported in front of the laser diode 16 by a protective housing 20, or "can" as commonly referred to in the art. The can 20 provides a protective enclosure around the laser diode 16 and the wire bond connection 22 to prevent physical harm to the laser diode 16 and wire bond 22 during manufacture and use. These types of laser heads also typically include a photodiode sensor 24 for monitoring light levels emitted from the laser diode. While these type of laser head assemblies 10 are highly effective and reliable, the physical characteristics of the cylindrical mounting head 12 limit the housing configurations to generally cylindrical constructions as shown in the above-noted patents, or alternatively to other housing structures having a minimum thickness which is limited by the outer diameter of the mounting head 12 plus the dimensions of any modular housing in which the laser head 10 is mounted. The laser head assemblies 10, which are typically referred to as transistor outline packages, are commercially sold in 2 standard sizes, namely 5.6 mm and 9 mm. Referring to FIG. 1A (prior art), a typical laser module of the prior art is illustrated and generally indicated at 26. The module assembly 26 comprises a laser head assembly 10, a mounting body 28, a collimating lens 30, and lens cap 32. Taking into account the smallest diameter of the transistor outline package 5.6 mm, and the necessary module housing in which it is mounted, a conventional laser module cannot be constructed any smaller than about 7.0 mm in diameter, or thickness. The laser module 26 is usually then mounted in another housing which in turn adds another 2-3 mm in diameter or thickness to the device, making the total diameter or thickness, no smaller than 9-10 mm. Accordingly, it is impossible to design a truly thin housing package from this type of laser head. As stated previously, while the existing laser head assemblies are highly effective, there is nevertheless a perceived industry need and consumer desire for laser mounting heads which have flatter packaging configurations than those currently available.
Accordingly, the instant invention provides a thin profile laser pointer assembly which incorporates a thin profile laser head, a simple constant voltage laser diode driver circuit, and a coin cell power source, all packaged into a thin profile housing which has a thickness of between about 2.0 and 6.0 mm.
The laser head comprises a thin, rectangular heat sink having parallel side edges, and further includes a laser diode mounted on a recessed shelf on a front edge of the heat sink. More specifically, the heat sink includes a recessed shelf at the inner end of an outwardly diverging slot formed in the front edge of the heat sink. The recessed shelf extends inwardly from the lower surface approximately half-way between the upper and lower surfaces of the heat sink, and the laser diode is mounted on the forward edge of the shelf. The wire bond from the laser diode passes through an aperture located next to the shelf to a contact pad on the upper surface of the heat sink body. The recessed shelf and slot protect the laser diode and wire bond from physical damage during handling and manufacturing thereof The housing comprises a thin rectangular body having a bottom wall and upwardly extending side walls. The rectangular heat sink is slidably received in an elongate rectangular mounting channel formed in a front portion of the housing. The mating parallel sides of the heat sink and mounting channel rigidly fix the laser diode in X and Z axes of a 90.degree. angle reference system while also permitting sliding linear movement of the laser diode along a "Y" axis, which defines the optical axis of the laser head assembly. The heat sink and mounting channel also positively fix rotation .theta..sub.x, .theta..sub.y, and .theta..sub.z of the laser diode around the X, Y and Z axes. A collimating lens is mounted at the front of the channel along the optical axis, and a projecting aperture is formed in the front wall of the housing in front of the lens for allowing the laser beam to exit through the front wall of the housing. The laser beam is focused through the lens by sliding the laser head assembly forwardly or rearwardly within the mounting channel to the proper longitudinal position. The laser head assembly is secured in focused position in the channel by an adhesive.
The battery is received in a circular recess formed in the rear portion of the housing. A hinged door is formed in the bottom wall of the housing for access to the battery after assembly.
The laser diode driver circuit and a switch are mounted on a two-sided circuit board which is received and secured over the open top of the shallow housing to form the top wall of the housing. Selectively placed contact pads on the circuit board engage corresponding electrical contact surfaces on the battery and laser head to complete the electrical circuit. The diode driver circuit utilizes a simple shunt voltage regulator which monitors laser voltage as the battery decays and adjusts current flow to provide constant voltage to the laser diode. More specifically, an operating circuit voltage is compared to the internal reference voltage of the shunt regulator. If the two values are the same, nothing happens. But, if the operating circuit voltage is higher than the reference, then the amplifier of the shunt regulator will draw more current from the battery reducing the overall voltage level to the diode.
A protective overlay sheet is mounted onto the upper surface of the circuit board to complete assembly of the laser pointer device. The overlay sheet protects and hides the electronic surface of the circuit board and can be provided with custom logo imprints for customized marketing of the laser pointer.
Accordingly, among the objects of the instant invention are: the provision of a laser pointer assembly having a thin profile housing with a thickness between about 2.0 mm and about 6.0 mm, and most preferably about 3.5 mm; the provision of a laser pointer assembly including a thin profile laser head; the provision of a laser pointer assembly wherein the thin profile laser head is slidably mounted in an elongate mounting channel; the provision of such a laser pointer assembly wherein the laser head and the mounting channel rigidly fix the laser diode in X and Z axes of a 90.degree. angle reference system, while also permitting linear sliding movement in the Y axis; the provision of such a laser pointer assembly wherein the laser head and mounting channel further fix rotation .theta..sub.x, .theta..sub.y, and .theta..sub.z of the laser diode around the X, Y, and Z axes; the provision of such a laser pointer assembly wherein a collimating lens is mounted at the forward end of the mounting channel and focusing of the laser beam is accomplished by sliding the laser head forward and backward within the mounting channel; the provision of thin profile laser head wherein the laser diode is mounted on a recessed shelf of a heat sink body to protect the laser diode and wire bond from harm during handling and manufacturing; the provision of a laser pointer assembly including a power regulator circuit which operates on constant voltage rather than constant current; the provision of a laser pointer assembly having a power regulator circuit which has no photodiode feedback loop; the provision of a laser pointer assembly having a power regulator circuit which uses a shunt-type voltage regulator; and the provision of a laser pointer assembly having a power regulator circuit with a shunt-type voltage regulator that uses the internal resistance of the battery to limit current to the shunt regulator.
Other objects, features and advantages of the invention shall become apparent as the description thereof proceeds when considered in connection with the accompanying illustrative drawings.


Provided is a storage controller that will not impair the operation of a storage control system even when a new storage area is added to a pool corresponding to an AOU volume. This storage controller includes a logical volume accessible by a host system; a pool associated with the logical volume and including one or more physical storage areas configuring a storage area of the logical volume; and a memory for storing attribute information showing an attribute of a physical storage area included in the pool; wherein the controller is configured to add a new physical storage area to the pool based on the attribute information.

The present invention generally relates to a storage controller, and in particular relates to a storage controller that gives consideration to the performance or reliability of a physical volume upon adding a physical volume, which is allocated to a logical volume, to a logical volume.
As background art relating to this kind of storage controller, for instance, the storage control system described in Japanese Patent Laid-Open Publication No. 2004-13547 is known. This storage control system aims to improve the access performance to data and secure the reliability thereof in technology of allocating data to a data storage area of a plurality of storages, and has a computer, a plurality of storage apparatuses for storing data to be used by a program of the computer, and an allocation device for allocating data to a prescribed storage area for storing such data, wherein the allocation device decides the position of the storage area to be allocated based on characteristic information of the storage apparatus and volume requirement information showing the type or usage of data.
Further, Japanese Patent Laid-Open Publication No. 2003-15915 describes an automatic expansion method of capacity in a storage apparatus. With this method, the storage area of a storage apparatus is not decided uniquely, but is rather decided dynamically. The storage controller monitors the logical block address of the read or write I/O to be access from a host to a logical volume of the storage apparatus. The storage controller dynamically extends the storage area of the logical volume based on the acquired logical block address. Moreover, the storage controller reduces/expands the storage area of the logical volume based on the capacity reduction/expansion command of the logical volume from a command unit of the host to a volume server.


A high-brightness polarizing plate of the present invention comprises a polarizing plate that comprises a polarizer and a protective film prepared on one or both sides of the polarizer, a brightness enhancement film and an adhesive layer through which the polarizing plate and the brightness enhancement film are laminated with the protective film interposed between them, wherein the protective film has an in-plane retardation Re of 0 to 10 nm and a thickness-direction retardation Rth of −30 to 10 nm, wherein Re=(nx−ny)d and Rth={(nx+ny)/(2−nz)}d. The high-brightness polarizing plate has a small color shift, and can be applied to various image displays such as liquid crystal displays.

In a conventional technique, natural light emitted from a backlight enters liquid crystal cells as it is. Recently, upsizing and high definition of liquid crystal displays have required an increase in backlight brightness. In addition, a number of techniques are beginning to be used for polarization of light from backlights.
In a backside of a liquid crystal cell, for example, the high-brightness polarizing plate with which a polarizing plate and a brightness enhancement film are adhered together is prepared. A brightness enhancement film shows a characteristic that reflects linearly polarized light with a predetermined polarization axis, or circularly polarized light with a predetermined direction, and that transmits other light, when natural light by back lights of a liquid crystal display or by reflection from a back-side etc., comes in. The polarizing plate, which is obtained by laminating a brightness enhancement film to a polarizing plate, thus does not transmit light without the predetermined polarization state and reflects it, while obtaining transmitted light with the predetermined polarization state by accepting a light from light sources, such as a backlight. This polarizing plate makes the light reflected by the brightness enhancement film further reversed through the reflective layer prepared in the backside and forces the light re-enter into the brightness enhancement film, and increases the quantity of the transmitted light through the brightness enhancement film by transmitting a part or all of the light as light with the predetermined polarization state. The polarizing plate simultaneously supplies polarized light that is difficult to be absorbed in a polarizer, and increases the quantity of the light usable for a liquid crystal picture display etc., and as a result luminosity may be improved. That is, in the case where the light enters through a polarizer from backside of a liquid crystal cell by the back light etc. without using a brightness enhancement film, most of the light, with a polarization direction different from the polarization axis of a polarizer, is absorbed by the polarizer, and does not transmit through the polarizer. This means that although influenced with the characteristics of the polarizer used, about 50 percent of light is absorbed by the polarizer, the quantity of the light usable for a liquid crystal picture display etc. decreases so much, and a resulting picture displayed becomes dark. A brightness enhancement film does not enter the light with the polarizing direction absorbed by the polarizer into the polarizer but reflects the light once by the brightness enhancement film, and further makes the light reversed through the reflective layer etc. prepared in the backside to re-enter the light into the brightness enhancement film. By this above-mentioned repeated operation, only when the polarization direction of the light reflected and reversed between the both becomes to have the polarization direction which may pass a polarizer, the brightness enhancement film transmits the light to supply it to the polarizer. As a result, the light from a backlight may be efficiently used for the display of the picture of a liquid crystal display to obtain a bright screen.
The suitable films are used as the above-mentioned brightness enhancement film. Namely, multilayer thin film of a dielectric substance; a laminated film that has the characteristics of transmitting a linearly polarized light with a predetermined polarizing axis, and of reflecting other light, such as the multilayer laminated film of the thin film having a different refractive-index anisotropy; an aligned film of cholesteric liquid-crystal polymer; a film that has the characteristics of reflecting a circularly polarized light with either left-handed or right-handed rotation and transmitting other light, such as a film on which the aligned cholesteric liquid crystal layer is supported etc. may be mentioned.
Therefore, in the brightness enhancement film of a type that transmits a linearly polarized light having the above-mentioned predetermined polarization axis, by arranging the polarization axis of the transmitted light and entering the light into a polarizing plate as it is, the absorption loss by the polarizing plate is controlled and the polarized light can be transmitted efficiently. On the other hand, in the brightness enhancement film of a type that transmits a circularly polarized light as a cholesteric liquid-crystal layer, the light may be entered into a polarizer as it is, but it is desirable to enter the light into a polarizer after changing the circularly polarized light to a linearly polarized light through a retardation plate, taking control an absorption loss into consideration. In addition, a circularly polarized light is convertible into a linearly polarized light using a quarter wavelength plate as the retardation plate.
If the light guide plate itself has a prism structure and a prism-type condensing sheet or the like is used together, polarized light can be emitted from a backlight, through it is slight. In such a case, the polarization performance can be 5% or more, preferably 10% or more, further preferably 15% or more, and a direction of the emitted light does not have to be in the normal direction of the backlight face. The polarization performance is represented by the formula: polarization performance=(maximum brightness−minimum brightness)/(maximum brightness+minimum brightness). The polarization performance is determined by measuring, through a Glan-Thomson prism, changes in brightness (maximum brightness and minimum brightness) of the emitted light from the backlight in the direction of the polarization axis.
In the case that such brightness enhancement films are used, there has been a problem of the amount of color shift. A various kinds of methods have been proposed to reduce the amount of color shift (for example, see Japanese Patent Application Laid-Open (JP-A) Nos. 11-248941, 11-248942, 11-64840, and 11-64841). In these literatures, a reduction in the amount of color shift in the whole of a liquid crystal display is investigated. In JP-A Nos. 11-248941 and 11-248942, a reduction in the amount of color shift of a brightness enhancement film is investigated. In JP-A Nos. 11-64840 and 11-64841, a combination of a brightness enhancement film and a liquid crystal panel is investigated to reduce the amount of color shift. Conventionally, however, the amount of color shift is not sufficiently reduced in the high-brightness polarizing plate that is a laminate of a polarizing plate and a brightness enhancement film.
It is also known that a composite film of an interference multilayer laminate and a stretched polyvinyl alcohol-based film is impregnated with iodine to form a high-brightness polarizing plate of a composite of a brightness enhancement film and a polarizer (for example, see, Japanese Patent Application National Publication (Laid-Open) No. 09-507308, page 12). Such the high-brightness polarizing plate can reduce the amount of color shift to some extent but can have serious unevenness in dyeing of the polarizer, therefore it cannot be applied to image viewing displays such as liquid crystal displays. The polyvinyl alcohol-based film is stretched to 3 times or more (4 times or more or 5 times or more) and controlled to have a water content of 10% or less. In the process of impregnating the resulting film with iodine, the speed of iodine dyeing can vary with variations in the alignment state of the polyvinyl alcohol-based film in the width and variations in the thickness directions and variations in the degree of crystallinity in the width direction, so that thick parts can significantly tend to be deeply dyed and thin parts less deeply dyed. Thus, uneven dyeing can occur in the polarizer, and in-plane unevenness can lead to an insufficient reduction in brightness when black viewing is displayed. It is practically difficult to apply such a composite film to liquid crystal displays or the like.

High luminance polarizing plate, and liquid crystal panel and image display using same


The present invention relates to a novel polycyclic aromatic organic semiconductor compound having a polycyclic aromatic core, a method for preparing the same, and electronic, optical or electro-optical devices such as an organic semiconductor composition, organic semiconductor thin film, organic field effect transistor and solar cell containing the compound. The novel organic semiconductor compound according to the present invention has high crystallinity and control capability, and facilitates control of doping conditions in the manufacture of organic semiconductor element so that it can be used for diverse applications. The compound can be mass-produced at low cost and has high solubility in organic solvents so that a liquid phase process can be applied to the manufacture of semiconductor elements and the like, thus enabling the mass-production of semiconductor elements and solar cells at low cost.

The introduction of an organic semiconductor makes it possible to realize a flexible display that can be manufactured on a flexible plastic substrate. Since a result of research showing that polyacetylene as a simple conjugate polymer has semiconductor properties and if polyacetylene is doped, it may have electrical conductivity of metal was reported, research and development on organic semiconductor materials, especially organic light emitting diodes, has been in progress and various mobile electronic devices employing organic light emitting diodes have been commonly used. Further, it has been tried to manufacture a driving mechanism for such organic light emitting diodes with organic materials, and, thus, technology development on organic thin film transistors has been in progress.
A configuration and a principle of operation of the organic thin film transistors are basically the same as those of metal oxide semiconductor field effect transistors (MOSFET) using amorphous silicon or polycrystalline silicon. However, the biggest difference between the organic thin film transistor and the MOSFET is using an organic semiconductor as a semiconductor material instead of using silicon. Even a few years ago, an organic thin film transistor using an organic semiconductor as an active layer semiconductor material, a glass substrate or a silicon wafer, having very low, electrical resistance as a substrate, and metal and an inorganic oxide film as an electrode and an insulating layer, respectively, has been researched. However, recently, research on an organic thin film transistor (TFT) using polymer materials for a substrate, an insulating layer and an electrode has been in progress, and, thus, a public use of a flexible display has been accelerated.
In addition to this, development of an organic semiconductor is important in developing organic solar cells. Solar cells mainly feature p-n junction solar cells using silicon, but improvement in a performance and price competitiveness of the solar cells may reach the limit. Therefore, development of new solar cells which can overcome limitations of conventional solar cells is needed. There have been suggested various solar cells over silicon solar cells, and an organic solar cell capable of remarkably improving an economic feasibility of a silicon solar cell has been regarded as having greatest potential. The most important thing in developing organic solar cells is development of a light absorbing layer that absorbs lights and development of an n-type semiconductor layer and a p-type semiconductor layer that receive electron holes and electrons generated when the light absorbing layer absorbs lights. Various organic polymer have been developed as a p-type semiconductor, and, thus, it is possible to make a selection in various ways, but there has not been suggested a particular system having a distinctively excellence as an n-type semiconductor. In a dye-sensitized solar cell, TiO2 has been used to form an n-type semiconductor and a light sensitizer using ruthenium organic metal compound has been used. However, such a technology has been technically protected and is expensive. Eventually, the development of the organic semiconductor is most important in developing organic solar cells having high efficiency and price competitiveness.
It is possible to reduce manufacturing cost with a semiconductor device and a solar cell using an organic semiconductor as compared with a conventional semiconductor device using an inorganic semiconductor such as Si, and the semiconductor device and solar cell using the organic semiconductor have been expected to have flexibility. Various organic semiconductor compositions such as polythiophene and rubrene have been researched, and it has been reported that a transistor including a channel forming area formed of such organic semiconductor compositions has mobility equal to or similar to mobility of a transistor including a channel forming area formed of amorphous silicon (see, for example, APL Vol. 80, No. 6, 1088-1090 (2002)).
A number of organic semiconductor compositions such as pentacene or conductive polymers having high mobility of electron holes have been known as p-type organic semiconductors used for organic TFTs, organic light emitting diodes, solar cells and the like.
However, if a channel forming area is formed of these organic semiconductor compositions, the organic semiconductor compositions are very slightly soluble in organic solvents and it is difficult to apply a coating process to these compositions, and, thus, a film is formed by vacuum deposition. These organic semiconductor compositions may have affinity with organic solvents by introducing alkyl chains or other substituents, so that these organic semiconductor compositions can be dissolved in the organic solvents. To be specific, it has been reported that poly-3-hexylthiophene (P3HT) formed by introducing a hexyl group to polythiophene is dissolved in organic solvents such as chloroform or toluene and a channel forming area is formed through a coating process such as a spin coating process (see, for example, APL 69(26) 4108-4100 (1996)).
Meanwhile, a polyacene compound as a condensed polycyclic compound is a molecule having a n-electron conjugated system in the same manner as polyacetylene or polyphenylene, and theoretically, the polyacene compound has a small band gap and has been expected to serve as an organic semiconductor composition having outstanding functions as compared with polyacetylene. A substituent introduced to the polyacene compound can be used for molecular binding or binding with a functional group of an insulating film surface and can be used to control a distance, a position and arrangement of an acene structure or can be used for patterning. The polyacene compound has benzene rings linearly connected to each other, and the polyacene compound which does not contain a substituent has a property of being slightly soluble in organic solvents as the number of benzene rings increases. Particularly, a polyacene compound having five or more linearly-fused benzene rings, such as pentacene, is not dissolved in most organic solvents and it is very difficult to form a uniform film through a spin coating process, and even if possible, an organic solvent and a temperature are very limited (for example, trichlorobenzene, 60° C.-180° C.).
Further, it has been widely known that as the number of benzene rings increases, the polyacene compound has low stability and particularly, pentacene has low resistance to oxidation and can be oxidized by oxygen in the air. As an example of introducing a substituent to a polyacene compound, 2,3,9,10-tetramethyl pentacene has been reported (see Wudl and Bao, Adv. Mater. Vol. 15, No. 3(1090-1093), 2003). However, 2,3,9,10-tetramethyl pentacene can be slightly dissolved in slightly heated o-dichlorobenzene and in reality, a channel forming area constituting a field effect transistor is formed by vacuum deposition.
It is also described in Japanese Patent Laid-open Publication No. 2004-256532 that 2,3,9,10-tetramethyl pentacene or 2,3-dimethyl pentacene is dissolved in o-dichlorobenzene. However, they are dissolved at temperature of 120° C. and it is not described that they can be dissolved at room temperature.
That is, a polyacene organic semiconductor compound such as pentacene needs a high production cost and can be sublimated under a depressurized atmosphere at 300° C. and decomposed in the air at a temperature higher than 300° C., and also, the polyacene organic semiconductor compound has low solubility to aqueous solvents and organic solvents, so that it is difficult to apply a liquid phase process to the polyacene organic semiconductor compound and instead, a gas phase process is applied to the polyacene organic semiconductor compound. Accordingly, a new organic semiconductor compound capable of solving the above-described problems has been demanded.

Organic semiconductor compound, method for preparing the same, and organic semiconductor composition, and organic semiconductor thin film and element containing the same


When correcting for velocity aberration in satellite imagery, a closed-form error covariance propagation model can produce more easily calculable error terms than a corresponding Monte Carlo analysis. The closed-form error covariance propagation model is symbolic, rather than numeric. The symbolic error covariance propagation model relates input parameters to one another pairwise and in closed form. For a particular image, the symbolic error covariance propagation model receives an input measurement value and an input error value for each input parameter. The symbolic error covariance propagation model operates on the input values to produce a set of output correction values, which correct for velocity aberration. The output correction values can be used to convert apparent coordinate values to corrected coordinate values. The symbolic error covariance matrix operates on the input error values to produce a set of output error values, which identify a reliability of the corrected coordinate values.

There are several near earth orbiting commercial satellites that can provide images of structures or targets on the ground. For applications that rely on these images, it is important to accurately register the images to respective coordinates on the ground.
For satellite-generated images of earth-based targets, one known source of misregistration is referred to as velocity aberration. Velocity aberration can arise in an optical system with a sufficiently large velocity relative to the point being imaged. A typical velocity of a near earth orbiting commercial satellite can be on the order of 7.5 kilometers per second, with respect to a location on the earth directly beneath the satellite. This velocity is large enough to produce a registration error of several detector pixels at the satellite-based camera.
The correction for velocity aberration is generally well-known. However, it is generally challenging to calculate error terms associated with the correction. These error terms estimate the confidence level, or reliability, of the velocity aberration correction.
Historically, error calculation for velocity aberration correction has been treated statistically with a Monte Carlo analysis. In general, these Monte Carlo analyses can be time-consuming and computationally expensive. In order to produce statistically significant results, a Monte Carlo analysis can require that a large number of simulated cases be executed and analyzed, which can be difficult or impossible due to the limitations of computational resources and processing time requirements. As a result, error estimation for velocity aberration correction can be lacking.

Calculation of numeric output error values for velocity aberration correction of an image


A brake system for a ram air turbine (RAT) causes the RAT to slow or lock if the RAT achieves an over-speed condition with a centrifugal force operated trigger system that actuates a compression type brake pack to slow or lock the turbine hub.

A ram air turbine (RAT) is a device for generating emergency supplemental power in a wide variety of aircraft. A RAT may generate hydraulic power, electric power or both. A RAT incorporates a turbine that extracts power from an air stream proximate the aircraft in flight. A typical RAT in current use is described in U.S. Pat. No. 4,743,163 to Markunas et al., owned by the assignee of this application, and incorporated herein by reference. The turbine is coupled to suitable power generating equipment, such as a hydraulic pump for hydraulic power and an electric generator for electric power, or both in the case of a hybrid RAT.
As described in Markunas et al., the turbine includes a speed governor that changes the turbine blade position to maintain a relatively constant shaft speed to the power generating equipment. Failure of the turbine speed governor can cause an over-speed condition that may ultimately cause the release of a turbine blade at very high speed. Due to the high speed, the wayward blade has very high energy as well. The most common cause of governor failure is due to seizure of the bearing between the turbine shaft and the governor yoke plate that controls the pitch of the turbine blades.
The potential release of a high-energy blade proximate the aircraft is a concern for both commercial and military RAT applications. Should the wayward blade strike the aircraft fuselage, it may penetrate the skin and cause damage to electric or hydraulic power equipment or control systems. It may also injure passengers or crew. If one of the propulsion engines ingests the wayward blade, the engine may suffer severe damage that results in loss of thrust.
Current methods to minimise hazards caused by turbine over-speed-induced release of a turbine blade have involved strategic placement of key elements or shields to prevent penetration. These methods no longer satisfy increasingly stringent certification and safety requirements promoted by airworthiness authorities.


An electronic device including a peripheral device connection unit configured to connect to a peripheral device and to receive identification data for the peripheral device, and a controller. The controller is configured to determine configuration information, wherein the configuration information is based at least on one of the identification data for the peripheral device or geographic location data for the electronic device, obtain a user interface selected from a plurality of user interfaces based at least partly on the configuration information, and automatically configure the electronic device based on the obtained user interface.

Conventionally, a television was configured to connect to a set top box or an antenna. In such a case, the television was able to receive a cable feed or over the air content. However, the television may be unable to receive other content. To allow the television to receive the other content, the television manufacturer may have to produce a set top box to be connected to the television. However, the cost of manufacturing, distributing, and maintaining a set top box may be cost prohibitive. For example, the set top box may not contain all of the features that the manufacturer wants for a particular television, especially since each manufacturer may have numerous models of televisions.

Method and apparatus for configuring an electronic device


A magnetic valve and a fluid supply system using the same are provided. The fluid supply system includes a flow channel and the magnetic valve. The magnetic valve penetrates through a pipe wall of the flow channel, and includes a driving unit, a first magnet and a second magnet, a cover plate, a first and second spools. A first leaning portion of the first spool is disposed at one end of a first sheath portion. The first sheath portion has a first outlet opening. The second magnet is disposed on a surface of the first leaning portion facing to the cover plate. The second spool sleeves the first spool and has a second outlet opening. The first spool rotates relative to the second spool through a magnetic force to control an overlapping area of the first and second outlet openings, so as to control a flow rate.

1. Field of the Invention
The invention relates to a valve and a fluid supply system. Particularly, the invention relates to a magnetic valve and a fluid supply system using the magnetic valve.
2. Description of Related Art
A valve is a device used for controlling a flow rate. In a commonly used apparatus, if a flow rate of a fluid in a flow channel is required to be controlled, the valve is generally installed in the flow channel to control the flow rate of the fluid. For example, a simple valve is used in intravenous drip to control a flow speed and flow rate of medicament, so as to inject the medicament according to an individual status of a patient. Alternatively, some fluid-related experiments are carried on in laboratory researches, and the valve is generally used to change or control the flow rate of the fluid that serves as a variable to obtain experiment results. Alternatively, in a portrait-type server rack, since a fluid is used to serve as a cooling medium, and the fluid has different potential energy at different heights that may influence the flow rate, in the cooling fluid loop, the valve is used to control the fluid of different heights to achieve the same flow rate.
Taking the valve used in a mechanical equipment (for example, a fluid experiment equipment or a server rack) as an example, two hollow spools are sleeved to each other, and one of the spools is connected to a motor, and another spool is fixed on the flow channel, and when the motor drives the spool to rotate, the spool connected to the motor is rotated relative to the spool fixed on the flow channel, so that an overlapping area of outlet openings of the two spools is varied to determine the flow rate of the fluid.
It should be noticed that in order to prevent the fluid leaking out from a space between the two spools, an O-ring is generally disposed between the two spools. However, configuration of the O-ring increases difficulty in relative rotation of the two spools. If a good sealing effect is achieved to prevent the fluid leakage, an extremely large force has to be used to implement the relative rotation between the two spools. Alternatively, if the relative rotation between the two spools is smoothly achieved, the contact between two spools and the O-ring cannot be too tight, which influences the sealing effect.

Magnetic valve and fluid supply system using the same


A seat cushion is provided with seat belt strap engaging arms operable to engage and spread the lap belt and shoulder belt straps, if present, of a seat belt structure away from the center of the stroller or other seat to provide easier access to place a user of the seat in the seat. Installation of the cushion is facilitated in one embodiment by adapting the arms to be detachably coupled to seat belt and shoulder belt straps. As a result, the cushion can be placed in the seat and the arms coupled to the straps without the need to undo the straps of the seat belt structure before use of the cushion.

It can be difficult to position individuals, especially toddlers, in a car seat or stroller that has a seat belt structure. That is, a person while holding the child, must often move seat belt straps out of the way using one hand in order to create space to position the child in the seat without the child sitting on seat belts. This task is even more difficult with modern seat belt structures that have both lap belts and shoulder straps that are designed to be buckled together over the stomach area of the child.


A packaged microelectronic element includes connection component incorporating a dielectric layer (22) carrying traces (58) remote from an outer surface (26), posts (48) extending from the traces and projecting beyond the outer surface of the dielectric, and pads (30) exposed at the outer surface of the dielectric layer, the pads being connected to the posts by the traces. The dielectric element overlies the front surface of a microelectronic element, and contacts (74) exposed on the front surface of the microelectronic element are connected to the pads by elongated leads (76) such as wire bonds. Methods of making the connection component are also disclosed.

The present invention relates to components and assemblies useful in microelectronic assemblies, to assemblies incorporating such components and to methods of making such components.
Microelectronic elements such as semiconductor chips typically are provided in packages which protect the semiconductor chip itself from the external environment and which facilitate mounting the chip on a circuit board. For example, some microelectronic packages include a connection component incorporating a dielectric element such as a board or sheet having top and bottom surfaces and having electrically conductive terminals exposed at the bottom surface. The chip is mounted to the top surface and connected to the terminals by various arrangements such as electrically conductive traces extending on a surface of the dielectric element, or within the dielectric element. The chip typically has a front surface with small contacts thereon and an oppositely-facing rear surface. The chip may be mounted in a face-down arrangement, so that the front surface of the chip confronts the top surface of the dielectric element and the rear surface of the chip faces upwardly, away from the dielectric element. In other cases, the chip may be mounted in a face-up arrangement, with the rear surface of the chip facing downwardly toward the top surface of the dielectric element. The contacts on the front face of the chip typically are connected to the traces on the dielectric element either by direct bonds between the contacts and leads formed integrally with the traces, or by wire bonds. As disclosed, for example, in U.S. Pat. No. 6,177,636, the disclosure of which is incorporated by reference herein, similar chip packages can be made with terminals in the form of posts projecting from the bottom surface of the dielectric element. The posts can be fabricated using an etching process. As disclosed in commonly assigned, co-pending U.S. Provisional Patent Applications 60/533,210; 60/533,393; and 60/533,437, all filed Dec. 30, 2003, the disclosures of which are incorporated by reference herein, packages utilizing posts can provide numerous advantageous features. For example, the posts and the dielectric layer or layers can be configured to promote tilting of the posts when the tips of the posts are engaged with a test socket, to facilitate effected contact between the tips of the posts and the contacts of the test socket.
Efforts have been made to fabricate electronic connection structures such as individual layers for multi-layer circuit boards using a metallic post structure. In one process, disclosed by the North Corporation of Tokyo, Japan, a metallic plate is etched to form numerous metallic posts projecting from the plate. A dielectric layer is applied to this plate so that the posts project through the dielectric layer. An inner or upper side of the dielectric layer faces upwardly toward the metallic plate, whereas the outer or lower side of the dielectric layer faces downwardly towards the tip of the posts. The dielectric layer may be fabricated by coating a dielectric such as polyimide onto the plate around the posts or, more typically, by forcibly engaging the posts with the dielectric sheet so that the posts penetrate through the sheet. Once the sheet is in place, the metallic plate is etched to form individual traces on the inner side of the dielectric layer extending to the bases of the various posts.
The components made by this process suffer from certain drawbacks for use as connection components in certain types of semiconductor chip packages. For example, it is often desirable to mount a chip in a face-down orientation and connect the contacts on the chip to the traces of the connection component using wire bonds which extend from the chip through a large opening or slot in the dielectric element, or around the edges of the dielectric element, and approach the outer or bottom surface of the dielectric element. Such a wire bond can be formed in a simple, one-step bonding operation. However, in the aforementioned process, the traces are formed on the inner or upper side of the dielectric element. Therefore, the traces are not exposed for making such a simple, one-step wire bond connection to the contacts on the chip.
One solution to this problem is to use a two-step wire-bonding procedure, in which the bonding wires are connected to the traces before the chip is placed on the component, leaving free ends of the wires projecting across the slot or beyond the edges of the dielectric element. After placing the chip on the connection component, the free ends of the wires remain accessible so that the free ends of the wires can be bonded to the contacts of the chip in a second bonding step. The two-step bonding process, however, adds to the cost and complexity of the assembly procedure, and creates the risk of defects such as adhesive contamination of the chip contacts or bonding wires during the chip mounting step and misalignment of the free ends of the bonding wires with the chip contacts.
As disclosed in certain embodiments of co-pending, commonly assigned U.S. Provisional Patent Application 60/508,970, filed Oct. 6, 2003, the disclosure of which is hereby incorporated by reference herein, a connection component including posts can be provided with pads exposed at the bottom or outer surface of the dielectric. The component can be fabricated by uniting a metallic sheet having posts thereon with a dielectric layer as discussed above, so that the metallic sheet is disposed on the top or inner surface of the dielectric layer and the posts project through the dielectric layer and project beyond the bottom surface of the dielectric layer. Some of the posts are crushed, abraded or otherwise treated so as to convert these posts to pads which project only slightly from the outer or bottom surface of the dielectric. The metallic sheet is etched to form traces which connect the pads to the posts. The pads may be formed adjacent edges of the dielectric, or adjacent slots in the dielectric. Such a component may be assembled with a chip in face-down orientation, with the contacts of the chip disposed outside of the edges of the dielectric or in alignment with the slots in the dielectric. The pads, and hence the traces and posts, can be connected to the contacts on the chip by a simple, one-step wire-bonding procedure.

Method of making a connection component with posts and pads


The cutting apparatus includes an ultrasound cutting element associated with a drive mechanism which enables the rate of advance of the cutting element through the product being cut to be varied selectively and locally. The preferred application is for cutting layered food products.

1. Field of the Invention
The present invention relates to a method and an apparatus for cutting food products comprising zones, generally layers, having different cutting characteristics.
2. Description of Related Art
Apparatus of this type is known, for example, from EP-A-0 614 733. This prior art document describes the presence of a pair of cutting devices (ultrasound blades) driven by a rod and crank mechanism on a member which can travel in synchronism with, and so as to follow food products which advance on a conveyor.
This solution constitutes an example of the many conventional solutions used for cutting food products in industrial plants for the manufacture of such products. The operating criteria and types of such apparatus are in fact extremely varied.
The automatic cutting of food products in such a context must take account of a series of factors which are becoming ever more important as conditions.
In the first place, the productional capacities of such plants, and hence the rate at which it is necessary to carry out the cutting, tend to increase continuously.
In the second place, the products treated are often delicate and cannot withstand very violent handling which could damage the product and/or cause the breaking away of fragments, crumbs and particles which can soil the plant itself.
Yet again, many food products have an intrinsically non-homogeneous character in the sense that they are not constituted by a single food substance but rather by a combination of food substances which may be very different from each other: it suffices to think, for example, of filled and/or layered products.

Apparatus and method for cutting food products


A semiconductor memory device is provided which comprises: a plurality of memory cell transistors each having a tunnel oxide film formed on a semiconductor substrate of a first conductivity type, a floating gate formed on the tunnel oxide film, a control gate overlaid on the floating gate with intervention of an insulating film, source/drain regions of a second conductivity type formed in the semiconductor substrate, and a high-concentration impurity layer of the first conductivity type formed in a portion adjacent to the drain region below the floating gate by oblique ion implantation employing an implantation angle .theta. with respect to a normal line to the semiconductor substrate; the plurality of memory cell transistors each sharing a source region with a memory cell transistor disposed adjacent thereto on one side thereof and a drain region with a memory cell transistor disposed adjacent thereto on the other side thereof; the implantation angle .theta. being defined by the following expression:. 0<tan.sup.-1 (Ld/Hg)<.theta.<tan.sup.-1 (Ls/Hg)<.pi./2. wherein Ls is a distance between gates of the adjacent transistors sharing the source region, Ld is a distance between gates of the adjacent transistors sharing the drain region, and Hg is a total height of the floating gate, the insulating film and the control gate on the tunnel oxide film.

1. Field of the Invention
The present invention relates to a semiconductor memory device and a fabrication process therefor. More particularly, the invention relates to a semiconductor memory device including a NOR-type flash EEPROM in which the impurity concentration in a portion of a channel region adjacent to source/drain regions is different from that in the other portion of the channel region, and to a fabrication process therefor.
2. Description of Related Art
Flash EEPROMs of one-transistor-per-cell structure are conventionally used as nonvolatile memory devices which are capable of electrically writing and erasing data.
A memory cell transistor in such a flash EEPROM includes, as shown in FIG. 10, a floating gate 23 of a polysilicon film formed on a semiconductor substrate 21 with intervention of a gate insulating film 22, an ONO insulating film 24, and a control gate 27 comprised of a polysilicon film 25 and a tungsten silicide film 26 and also serving as a word line. Source/drain regions 28 and 29 are formed on opposite sides of the floating gate 23 and the control gate 27, and the source region 28 has a low-concentration impurity layer 28a in its peripheral portion.
A fabrication process for a memory cell transistor as described above will hereinafter be described.
As shown in FIG. 8, P-type ions are implanted into a device formation region of a P-type semiconductor substrate 21 having a device isolation film (not shown) to control the impurity concentration in a channel region, and then a silicon oxide film 22 is formed on the semiconductor substrate 21.
In turn, as shown in FIG. 9, a floating gate 23, an insulating film 24 and a control gate 27 comprised of a polysilicon film 25 and a tungsten silicide film 26 are formed on the resulting substrate. A resist pattern 30 having an opening only on a source formation region is formed on the resulting substrate by a photolithographic and etching process. Then, a low-concentration impurity layer 28a is formed by implanting N-type ions (N.sup.+) in a low concentration into the resulting substrate with use of the floating gate 23, the control gate 27 and the resist pattern 30 as a mask.
Subsequently, the resist pattern 30 is removed, and N-type ions (N.sup.++) are implanted in a high concentration into the resulting semiconductor substrate 21 including the floating gate 23 and the control gate 27 to form source/drain regions 28 and 29.
To write data to the memory cell transistor shown in FIG. 10, a high voltage of about 12 V is applied to the control gate with the source grounded, and a voltage of about 7 V is applied to the drain. At this time, a large current flows between the drain and the source, whereby hot electrons of a high energy generated around the drain junction are injected into the floating gate and accumulated in the floating gate. The memory cell transistor to which data is written has a high threshold voltage, thereby storing therein data "0", for example.
To erase data stored in the memory cell transistor, on the other hand, a high voltage of about 12 V is applied to the source with the control gate (positive gate type) grounded. At this time, a high-intensity electric field is generated between the floating gate and the source, and the electrons accumulated in the floating gate are drawn through the thin silicon oxide film by a tunnel current. Therefore, the threshold of the memory cell transistor is reduced, so that the data stored therein is erased.
In the memory cell transistor of FIG. 10, the data writing is performed on the drain junction side, and the data erasing is performed on the source junction side. In a device design, the junction profile is optimized in accordance with the operations on the drain junction side and the source junction side. More specifically, an electric-field-concentration type profile involving an abrupt change in the impurity concentration is employed on the drain junction side to increase the writing efficiency, while an electric-field-dispersion type profile involving a stepwise change in the impurity concentration is employed on the source junction side to allow the application of a high-intensity electric field for data erasing. Therefore, the construction is asymmetrical on the drain junction side and on the source junction side.
In a method for reducing a voltage to be applied to the source for data erasing, a negative voltage is applied to the control gate (negative gate type).
In the memory cell transistor of FIG. 10, the ion concentration around a channel inversion layer is rendered substantially uniform by implanting ions of the same conductivity type as that of the semiconductor substrate 21 before the formation of the floating gate 23. If the impurity concentration in the channel inversion layer is uniformly increased along the length of the channel, the efficiency of hot electron injection into the floating gate for data writing is increased, that is, the time required for the data writing can be shortened. When electrons are drawn out of the floating gate to the source for data erasing, however, a band-to-band tunneling current increases causing increase in current consumption. In addition, hot holes thereby generated migrate into the tunnel oxide film, so that hot hole behavior becomes less reliable for channel operation.
On the other hand, if the impurity concentration in the channel inversion layer is uniformly reduced along the length of the channel, the band-to-band tunneling current can be reduced, but the efficiency of data writing is reduced. Therefore, a tradeoff between the writing characteristics and the erasing characteristics is a critical problem.
To solve this problem, a memory cell transistor is proposed in which the impurity concentrations in a portion adjacent to a source region and in a portion adjacent to a drain region are independently optimized by implanting ions of the same conductivity type as that of a semiconductor substrate only into the portion adjacent to the drain region after the aforesaid process steps for memory cell transistor fabrication are performed.
However, the fabrication process for such a memory cell transistor requires an additional mask for ion implantation for the optimization of the impurity concentration in the portion adjacent to the drain region. In addition, the fabrication process requires a resist application step, an exposure step, a developing step, a removal step and an impurity-diffusion-layer formation step. Thus, the process is complicated, resulting in a reduced throughput.
One exemplary fabrication process for a memory cell transistor having source/drain regions of an asymmetrical structure is disclosed in Japanese Unexamined Patent Publication No. 4-329632 (1992). As shown in FIG. 11, gate electrodes 33 formed on a first region A of a semiconductor substrate 31 are spaced from each other a predetermined distance, and gate electrodes 33 on a second region B of the semiconductor substrate 31 are spaced from each other a distance smaller than that in the first region A. Ions are implanted into the first and second regions A and B at an ion implantation angle .theta..sub.1 (0.degree.<.theta..sub.1 <90.degree.) with respect to a normal line to the semiconductor substrate 31 by oblique rotation ion implantation to form source/drain regions 34A in the first region A and source/drain regions 34B in the second region B respectively having different ion concentrations.
Another exemplary fabrication process is disclosed in Japanese Unexamined Patent Publication No. 6-21476 (1994). As shown in FIGS. 12(a) to 12(d), P-type ions are implanted from the side of a drain (FIG. 12(b)) and N-type ions are implanted from the side of a source (FIG. 12(c)) at an ion implantation angle .theta..sub.2 (0.degree.<.theta..sub.2 <90.degree.).
However, the aforesaid ion implantation methods cannot be applied to a NOR-type flash EEPROM such as of FIG. 10 having a common source region shared with adjacent memory cells, because ions to be selectively implanted into the drain region are also implanted into the source region, making it impossible to form a desired flash EEPROM of the asymmetrical structure.

Method of fabricating EEPROM using oblique implantation


Aspects of the present invention include a methodology for the general timing-driven iterative refinement-based approach, a timing-driven optimization (TDO) method that optimizes the circuit depth after the area oriented logic optimization, and a layout-driven synthesis flow that integrates performance-driven technology mapping and clustering with TDO to account for the effect of mapping and clustering during the timing optimization procedure of TDO. The delay reduction process recursively reduces the delay of critical fanins of a selected. Furthermore, in one embodiment, the fanins of the selected node are sorted according to their slack values.

1. Field of the Invention
Aspects of the present invention generally relate to computer aided engineering of logic circuits. More particularly, embodiments of the present invention relate to timing optimization of logic circuits.
2. Description of the Related Technology
In general, logic optimization is classified into two categories, two-level logic optimization and multi-level logic optimization.
Two-level optimization deals with the optimization of combinational logic circuits, modeled by two-level "sum of products" expression forms, or equivalently by tabular forms such as implicant tables. Two-level logic optimization has a direct impact on programmable logic arrays (PLAs) and macro-cell based programmable logic devices (CPLDs).
Combinational logic circuits are very often implemented as multi-level networks of logic gates. The fine granularity of multi-level networks provides several degrees of freedom in logic design that may be exploited in optimizing area and delay as well as in satisfying specific constraints, such as different timing requirements on different input/output paths. Thus, multi-level networks are very often preferred to two-level logic implementations such as PLAs. The unfortunate drawback of the flexibility in implementing combinational functions as multi-level networks is the difficulty of modeling and optimizing the networks themselves. The need of practical synthesis and optimization algorithms for multi-level circuits has made this topic of high importance in VLSI CAD.
Multi-level logic optimization is frequently partitioned into two steps. In the first step, a logic network is optimized while neglecting the implementation constraints on the logic gates and assuming rough models for their area and performance. This procedure is usually referred to as technology independent logic optimization. In the second step, one takes into consideration the constraints on the available gates (e.g., K-LUTs in FPGAs) as well as the detailed area and delay models of these gates. This step is the so-called technology dependent logic optimization or technology mapping. The discussion hereinbelow addresses the technology independent logic optimization problem, and, in particular, the timing-driven logic resynthesis problem.
Several common operations that are used during the area-oriented multi-level optimization are as follows:
1. Common Sub-Expression Extraction
By extracting common sub-expressions from a number of functions, the circuit area is reduced. However, the better the area saving, the more places the sub-expression fans out to, which could degrade the circuit performance.
2. Resubstitution
Resubstitution is similar to common sub-expression extraction and involves expressing a node in terms of another, if possible.
3. Elimination
Elimination involves removing, from the multi-level network, all occurrences of variables that represent the nodes which are eliminated. When all the internal nodes are eliminated, the operation is called collapsing.
4. Decomposition
The decomposition of an internal node function in a multi-level network replaces the node by two (or more) nodes that form a subnetwork equivalent to the original node. Decomposition is often performed on a node to split a complex function into two (or more) simpler functions. Small-sized expressions are more likely to be divisors of other expressions and may enhance the ability of the resubstitution algorithm to reduce the size of the network.
5. Simplification Using Don't Care Conditions
Simplification is used to find a compact representation for the Boolean function at every node. By removing the redundancies from a representation of a function, both the size and the depth can be reduced. In a multi-level network, the simplification at a node needs to consider the structure of the logic around it. This gives rise to don't care conditions that can be exploited during node simplification.
From the description of these operations, one can see the complex interaction between the circuit area and delay. In addition, the delay impact of a particular transformation applied on the same network often depends on the delay data (the arrival and required times). Since the delay data is imprecise at the technology independent stage, it is difficult to adapt the strategies used for area optimization to address the performance optimization issue. Because of this difficulty, many of the techniques developed to reduce the circuit delay use local transformations to make incremental changes to the logic.
Timing optimization will now be discussed. One significant issue in restructuring a circuit is determining circuit regions that should be transformed. The most critical outputs and their transitive fanins are a natural choice. However, one problem with this approach is that after the most critical outputs have been optimized, outputs that were close to being critical before could become critical after optimization of the original critical paths. Moreover, optimizing only the most critical outputs by more than the needed amount can also result in an unnecessary area penalty. Thus, some techniques optimize close-to-critical nodes along with the most critical nodes.
Several conventional algorithms use an iterative refinement-based approach, where, in each iteration, a set of critical paths is identified and then the delays of a set of nodes are reduced so that the overall circuit performance is improved. These algorithms are differentiated in (i) how to determine in each iteration the set of nodes to apply the local transformation for delay reduction and (ii) the local transformation method itself.
Another conventional attempt at timing optimization takes a different approach based on clustering, partial collapsing and subsequent timing optimization. This approach is based on the premise that at a technology-independent level, in the absence of the target technology information and wiring delays, any delay model is inaccurate. Therefore, it assigns a zero delay to all the gates, thus treating all the input-to-output paths uniformly. However, whenever a signal crosses cluster boundaries, a delay of one unit is incurred.
Another existing approach first performs area optimization on a circuit to achieve to reduce the size of the circuit layout, and then incremental changes are made to the circuit to reduce its delay. This approach is particularly useful for layout-driven logic resynthesis, wherein the timing correction step is performed incrementally to ensure the convergence of the iteration between the layout design and the circuit resynthesis.
A significant aim of the restructuring approaches discussed above is to generate a good multi-level structure of the circuit that will subsequently be mapped into a small delay implementation. These conventional approaches generally use simple, weak models to predict the circuit delay. As a result, the savings observed at the technology independent stage may not be evident after technology mapping of the optimized circuit.
To alleviate this problem, researchers have extended the basic ideas of the technology independent optimizations to work on mapped circuits. Heuristics have been used to address the optimization of mapped circuits while taking into account the characteristics of the cell library.
The Timing-Driven Logic Optimization section discussion below describes the performance optimization at the technology independent level and how this optimization impacts the subsequent technology mapping and physical design.
With the rapid scaling of transistor feature sizes, integrated circuit performance is increasingly determined by interconnects instead of devices. Interconnect delays are even more significant in PLD designs due to the extensive use of programmable switches. As a result, the delay between two logic blocks is highly dependent on their placement on the chip and the routing resources used to connect them. PLDs, such as those from Altera, include several types of interconnects, including local, row and column interconnects. Local interconnects refer to the connections between logic elements (LEs) in the same logic array block (LAB). Row interconnects refer to the connections between LEs in the same row, but in different LABs. Column interconnects refer to the connections between LEs in different rows. The delay attributed to interconnects can be many times that of the logic element delay. Given such a high variation of different types of interconnect delays, it would be almost impossible to perform accurate timing optimization during synthesis without proper consideration of the layout result. That is why layout-driven synthesis is considered to be an important problem area in high-performance PLD designs.
The layout-driven synthesis problem has proved to be difficult to solve due to the mutual dependency nature of the logic synthesis and layout design. In general, there are two approaches to integrate logic and layout synthesis. One approach is to employ a highly iterative design flow. It follows the design steps in the traditional design flow, but feeds the layout result in the current iteration back to the logic synthesis tools for improving the synthesis results in the next iteration. To make such a "construct-by-correction" approach effective, the correction step needs to be done incrementally with respect to the information fed back by layout. However, a different approach completely remaps the entire circuit based on the information fed back from the layout design, making it difficult to guarantee any convergence when performing the iteration between layout and synthesis.
Another conventional approach is to use a concurrent design flow, which performs logic synthesis/technology mapping and placement/routing concurrently. However, the optimality of such an approach usually holds for very special circuit structures (such as trees) and the main difficulty associated with this approach is its high computational complexity.
Clearly, a better technique is needed for an effective and efficient layout-driven synthesis flow. Such a technique should consider layout information during synthesis and design planning, such as by combining logic partitioning with retiming and proper consideration of global and local interconnect delays, or by exploiting fast interconnects available in many PLD architectures during technology mapping.
As the capacity of PLD devices increases, hierarchical architectures are being more widely used, where basic programmable logic blocks, such as look-up tables (LUTs) or macrocells, are grouped into a logic cluster and connected by local programmable interconnects inside the cluster. There are basically two types of clusters, hard-wired connection-based clusters (HCC) and programmable interconnect-based clusters (PIC). The layout-driven synthesis flow described below is mainly targeted for the PIC-based FPGA architectures, although, in other embodiments, other architectures are targeted.
In a PIC, a group of basic logic blocks are connected by a local programmable interconnection array that usually provides full connectivity and is much faster than global or semi-global programmable interconnects. A number of commercial PLDs use the PIC architecture, such as the logic array block (LAB) in Altera FLEX 10K and APEX 20K devices, and the MegaLAB in APEX 20K devices. For example, in FLEX 10K devices, each LAB consists of eight 4-LUTs connected by the local interconnect array. Multi-level hierarchy can be formed easily using PICs, in which a group of small (lower-level) PICs may be connected through a programmable interconnect array at this level to form a larger (higher-level) PIC. For example, in Altera APEX 20K FPGAs, each LAB consists of ten 4-LUTs connected by local interconnects, which forms the first-level PIC. Then, 16 such LABs, together with one embedded system block and another level of programmable interconnects, form a second level PIC, called MegaLAB. Finally, global interconnects are used to route between MegaLAB structures and to I/O pins.
Conventional PLD synthesis algorithms often transform a given design into a flat netlist of basic programmable logic blocks (such as LUTs or macrocells) without consideration of the device hierarchy. Therefore, a substantial challenge in this area is to be able to synthesize a given design directly into a multi-level hierarchical architecture, with consideration of different interconnect delays and clustering constraints at each level.

Methodology and applications of timing-driven logic resynthesis for VLSI circuits


A pipe supporting device is shown of the type used to support an exposed pipe of a roof. The device includes a base having a flat bottom for resting on the roof, an upright member of a length which is connectable to the base and a receiving portion which is connectable to the upright member for receiving and supporting the exposed pipe. The length of the upright member can be altered by a user at a job site to thereby provide a device having a desired overall height.

1. Field of the Invention
The present invention relates generally to improvements in support arrangements for exposed pipes and, more specifically, to a support device for an exposed pipe on a building roof.
2. Description of the Prior Art
A variety of devices have been used in the prior art in order to support exposed pipe. Support devices are necessary for a number of reasons, such as to prevent undue strain being placed upon a pipe or coupling. In some cases, it is necessary to support the pipe at a slope with respect to an adjacent support area, such as in the case of condensate drain lines from air conditioning/heating systems, or in the case of sewer pipes and lines.
Commercial buildings often have various types of pipes which are exposed and run along the rooftops of such buildings. For example, it is quite common for air conditioning units to be mounted on a building roof of a commercial building, the air conditioning units having condensate drain pipes which slope from the unit toward an exit point on the rooftop. Other service units are commonly mounted on building roofs which utilize pipes which must be supported, often at a slope with respect to the surrounding rooftop.
At the present time, most mechanical and heating/ventilation contractors hand saw pieces of wood of the desired height to support air conditioner condensate drain pipes. This procedure is time consuming and labor intensive. An adjustable, ready-made device would save time and money.
While various devices are shown in the prior art for supporting pipes, shortcomings continue to exist. For example, U.S. Pat. No. 4,513,934, to Pruyne, issued Apr. 30, 1985, shows a pipe supporting device adapted to receive and support an exposed pipe on a building roof. The device has a base with a substantially flat bottom for resting on the roof and an upwardly tapered structure secured on and rising from the base to provide upwardly divergent, V-shaped recesses for receiving the pipe and supporting it above the base. One problem with the device shown in the '934 patent is that the upright portion of the device is not adjustable in length. As a result, it is not possible to vary the overall height of the device except by stacking multiple devices, one upon the other, thereby adding to the cost of the installation. Of course individual devices of the type shown in the '934 patent could be manufactured of different overall heights, however this would lead to additional expense in manufacture and require that the user maintain an inventory of different height devices in order to provide the slope required at the particular job site.
The present invention has as its object to provide a pipe supporting device which is simple in design and economical to manufacture and which can support an exposed pipe at a desired slope with respect to a surrounding support surface, such as a building roof.
Another object of the invention is to provide such a pipe supporting device which has an upright member which is easily adjustable in length in order to provide a pipe supporting device of a selected overall height at the job site.
Another object of the invention is to provide such a pipe supporting device of standard components which can be mass produced at an economical price but which include height adjustment features to allow the standard device to be adjusted an overall height to fit the installation location at hand.


A hydraulic control device for an automatic transmission comprises a shift valve and a control valve which are coaxially aligned in a valve chamber. The shift and control valves of a spool type control connecting states of first and second clutches of the automatic transmission, respectively. The shift and control valves are separated by a retainer having a through-hole through which a part of the control valve pushes the control valve so as to change the operating state of the control valve. The shift valve takes one of a first state where a hydraulic chamber of a first clutch is communicated with a drain port and a second state where the first clutch hydraulic chamber is communicated with a line pressure. In the first state of the shift valve, the control valve is set to control the line pressure and communicate a hydraulic chamber of a second clutch and the controlled line pressure. In the second state of the shift valve, the control valve is pushed by the shift valve and is set to communicate the second clutch hydraulic chamber and a drain port.

1. Field of the Invention
The present invention relates to improvements in an hydraulic control device for an automatic transmission of a vehicle.
2. Description of the Prior Art
It is well known that a shift change of an automatic transmission in an automotive vehicle is usually carried out by changing a connecting state of two clutches. For example, 2nd speed is produced by engagement of a first clutch and release of a second clutch, and 3rd speed is produced by release of the first clutch and engagement of the second clutch. When a drive position of the automatic transmission is changed from 2nd speed to 3rd speed, a shift valve in a control system is changed from a first state that a hydraulic chamber of the first clutch is communicated with a line pressure to a second state that a hydraulic chamber of the second clutch is communicated with the line pressure. Such an automatic transmission is disclosed in a full range electronic control type automatic transmission (5E-AT) Service Manual (Type RE5R01A). In this transmission, to control the increase of the torque power which is caused by directly applying a line pressure to the second clutch, a pressure control valve is installed between the shift valve and the second clutch. Accordingly, the line pressure from the shift valve is properly controlled and supplied to the second clutch.
However, difficulties have been encountered with the above conventional arrangement, in which it is necessary to use a relatively large space for the installation thereof. That is, since the shift valve has to change the connecting conditions of the first and second clutches, the shift valve needs to have at least five ports. This increases the axial length of the shift valve. Furthermore, since it is necessary to provide a pressure control valve in addition to the above-mentioned shift valve, another valve chamber for the pressure control valve is required to this arrangement.

Hydraulic control device for an automatic transmission having a shift valve and a control valve coaxially aligned in a valve chamber


A negative hinge offset rotor head for a coaxial helicopter, the rotor head having two or more flapping rotor blades having outer and inner tips, the inner tips rotatably attached to a hinge attachment rotated by a driveshaft where the driveshaft is positioned between the rotor blades and the rotor blades' respective hinge attachment.

It is known to those skilled in the art that conventional helicopters of all types can benefit from the use of flapping hinges. Flapping hinges allow the rotor blades to flap up and down as the rotor disk rotates, eliminating the bending stresses in the blade that would otherwise occur if no hinge was fitted. An example of the placement of the flapping hinges on a conventional prior art coaxial helicopter with 2 blades per rotor is shown in FIG. 1.
In this example, the hinges are fitted close to the axis of rotation of the rotor but are offset away from the axis of rotation of the driveshaft in the direction of the rotor blade a distance denoted by dimension E. The flapping hinge offset provides the same benefits to helicopters with more than two blades per rotor, but for simplicity only helicopters with two blades per rotor will be discussed here.
The flapping hinge offset is almost always positive, that is, in the direction of the rotor blade, because this results in an improvement in pitch and roll control as described herein. The only exception is in the case of a teetering rotor system, wherein the flapping hinge axis intersects the driveshaft axis. In this case, distance E would be zero. This layout does not provide the benefits that a positive value of E provides.
It is known to those skilled in the art that a conventional helicopter with flapping hinges, coaxial or otherwise, derives its pitch and roll control by using cyclic pitch control to tilt the rotor disk in the direction of desired movement. In the example shown in FIG. 1, the rotor disks have been tilted forward an angle of θ. This creates a nose-down pitching moment from two effects. The first effect is the offset of the thrust vector of the rotor disks to behind the center of gravity of the aircraft, which in this case results in a pitching moment that acts to pitch the aircraft nose-down. This effect is well known to those skilled in the art.
In the example shown in FIG. 1, additional forward pitching moment is obtained from the positive hinge offset distance E. As the rotor disk tilts forward in this case, the Tip Path Plane (plane about which the rotor blade tips, T, travel as the revolve, denoted as TPP in this example) also tilts forward by an angle that is approximately the same as the disk tilt angle θ. Shown in the diagram are the centripetal force vectors of the rotor blades, denoted by forces Fc in this example. It is known to those skilled in the art that centripetal force vectors act through the center of gravity of the rotor blades, denoted by CG in this example. The act largely radially outwards of the rotor disk, and parallel to tip path plane TPP as shown. Due to the flapping hinge offset E, the CG of the rear rotor blade is further away from the TPP than the CG of the front rotor blade as shown. Due to this, the centripetal force vectors from the front and rear rotor blades do not intersect, but are offset from each other by a distance denoted by D, resulting in a nose-down pitching moment from each rotor disk denoted by M. For helicopters having two rotor blades fitted per rotor, this pitching moment is not constant, rather, it can vary sinusoidally with rotation of the rotor disk. The pitching moment can be at a maximum when the rotor blades are positioned as shown in the example and can be at a minimum when the rotor blades are rotated 90 degrees from that shown. For helicopters having 3 or more rotor blades per rotor, the pitching moment can be constant.
It is known to those skilled in the art the pitching moments M that results from the flapping hinge offset E shown in FIG. 1 assists the pitching moment that results from the offset thrust vector from disk tilt described previously. This is known to improve pitch and roll response, which is highly desirable from a control perspective, however, it also results in limiting the top speed that the conventional helicopter can achieve. In a conventional helicopter with cyclic pitch and flapping hinges, the flapping hinges are not necessarily the limiting factor of top speed, however this can be the case where the hinge offset is relatively large
It is, therefore, desirable to provide a system and method that counters the aforementioned pitching moment and, thereby, increases the top speed a helicopter can travel at.

Negative hinge offset rotor head for a helicopter


A method includes storing architectural state data associated with a processing unit in a cache memory using an allocate without fill mode. A system includes a processing unit, a cache memory, and a cache controller. The cache controller is to receive architectural state data associated with the processing unit and store at least a first portion of the architectural state data in the cache memory using a first fill mode responsive to a first value of a fill mode flag and store at least a second portion of the architectural state data in the cache memory using a second fill mode responsive to a second value of a fill mode flag, wherein the first fill mode differs from the second fill mode with respect to whether previous values of the architectural state data are retrieved prior to storing the first or second portions in the cache memory.

1. Field of the Disclosure
The disclosed subject matter relates generally to electronic devices having multiple power states and, more particularly, to a method and apparatus for storing an architectural state of a processor in cache memory.
2. Description of the Related Art
Some processors may include multiple central processing unit (CPU) cores and one or more secondary processor cores, such as a graphics processing unit (GPU) cores. To save system power, one or more of these cores can be powered off when not being utilized. For example, a processor core may be powered down when the processing load is light. When the load subsequently increases and the system again requires the use of that processor core, it will power up the processor core and resume executing instructions on that processor core. When a processor core is powered off, the architectural state of that processor core is lost. When the processor core is powered up again, it will require that architectural state be re-established to continue executing instructions. To avoid running lengthy boot code to restore the processor core back to an initialized state, a processor core may save its architectural state before being powered off and then restore that architectural state when being powered up. The processor core stores the architectural state in a location that will retain power across the processor core powered-down period.
This process of saving and restoring architectural state is time-critical for the system. Any time wasted before going into the powered-down state is time that the core could have been already powered down. Reducing the time required for an architectural state save results in increased power savings. Also, any time wasted while restoring the architectural state on power-up adds to the latency in re-establishing the operational state of the processor core, thereby reducing system performance.
The memory location where the architectural state is saved while the processor core is in a low power state must be secure. If a hardware or software entity could maliciously corrupt this architectural state when the processor core is in a low power state, the processor core would restore a corrupted state and could be exposed to a security risk. Conventional processors save the architectural state to various locations to facilitate a lower power state. For example, the processor may save the architectural state to a dedicated static random access memory ("SRAM") array or to the system memory ((e.g., dynamic random access memory ("DRAM")). The use of dedicated SRAM allows faster save and restore times and improved security, but requires additional hardware, resulting in increased cost. Saving the architectural state to system memory uses existing memory infrastructure, but increases save and restore times and decreases security as compared to the use of dedicated SRAM.
The use of the same reference symbols in different drawings indicates similar or identical items.

Method and apparatus for storing a processor architectural state in cache memory


A series of guanine analogs and physiological salts thereof, which are useful as virus inhibitors and as antiviral agents in the treatment of viral disease, having the basic structures of: ##STR1## wherein B is H, CH.sub.3 or NH.sub.2 ; C is NH.sub.2 or SCH.sub.3 ; D is N or CH; E is O, S or Se; and G is selected from a group consisting of alkanes, alkenes, ethers, esters, hydrocarbons, amines and heterocyclic compounds, is herein disclosed. In I and III, A is O, S or Se while in II, A is NH.sub.2, OH, NHOH, OCH.sub.3 or SCH.sub.3. In I and II, F is 0, S or Se, while in III, F is F is 0, S, Se or NH. These compounds may be formulated with a physiological carrier, and used either alone or in combination with, for example, acyclovir or ganciclovir or another therapeutic agent, for the treatment of conditions resulting from viral infections.

The past two decades has seen the emergence of acyclic derivatives of guanine as drugs of choice for the treatment of certain viral caused conditions. The three most recognized of these acyclic derivatives are acyclovir [9-(2-hydroxyethoxymethyl)guanine], HBG [9-(4-hydroxybutyl)guanine], and ganciclovir [9-(1-hydroxymethyl-2-hydroxyethoxymethyl)guanine]. Acyclovir is the current drug of choice for the treatment of herpes simplex virus (HSV) infections; whereas, ganciclovir is the standard against which other drugs are measured for their effect against human cytomegalovirus (HCMV). The diversity of like structures which have been synthesized and evaluated for their antiviral efficacy has been the subject of recent review articles.sup.1,2. These structures are related to each other in two ways: (1) They contain some portion of the glycosyl moiety of natural nucleosides and are collectively termed acyclic nucleosides and (2) the more active compounds all contain the aglycon guanine.
A recent perspective.sup.3 reviewed the immunomodulatory properties of many 8-substituted guanosine derivatives and analogs. One of the more studied guanosine analogs with demonstrated immunomodulatory activity is 5-amino-3-(.beta.-D-ribofuranosylthiazolo[4,5-d]pyrimidine-2,7(3H, 6H)-dione (7-thia-8-oxoguanosine).sup.3-7. This nucleoside shows a broad spectrum of antiviral activity in the host animal but is virtually inactive in vitro.sup.3. Additionally, certain alkyl guanine analogs and derivatives were found to have similar activity profiles.sup.8-9. This latter work showed that neither the ribose moiety nor a portion thereof was required for immunomodulatory activity. Active guanine analogs were prepared by appending acyclic hydrocarbons of 4-6 carbon atoms in length.sup.8 to the heterocycle.
Two patents.sup.4,5 have issued which cover certain glycosyl derivatives of the thiazolo[4,5-d]pyrimidine moiety. Additionally, two journal publications.sup.6,7 describe the synthesis of glycosides of this heterocycle. Further publications.sup.10,11 have described the synthesis of aryl derivatives of thiazolo[4,5-d]pyrimidines as antimicrobials. The original syntheses of the parent heterocycles were disclosed in 1969.sup.12 and 1970.sup.13.
A number of ribonucleosides bearing a 2'-fluoro substituent in the "up" (arabino) configuration has provided a host of potent agents against several DNA viruses.sup.14-17. The best known examples are 1-(2-deoxy-2-fluoro-.beta.-D-arabinofuranosyl)thymine (FMAU) and 1-(2-deoxy-2-fluoro-.beta.-D-arabinofuranosyl)-5-iodouracil (FIAU).
The concept of primary alkyl derivatives of guanine and guanine-like heterocycles as immunomodulators has been disclosed.sup.8,9. There are also a fair number of recent publications.sup.18-29 dealing with synthesis and biological evaluation of similar heterocyclic molecules substituted with alkenes, alkynes and allenes. However, with only one exception.sup.29 these substitutions terminate with either a phosphonate or moieties which can be phosphorylated (kinased) and thus, are designed to operate by alternate mechanisms of action when compared to the compounds of the present invention.
The present invention describes a new set of novel derivatives of thiazolo [4,5-d]pyrimidine and related heterocycles. These analogs uniquely demonstrate in vitro activity against viral infections.


A method for dynamically scaling scanned images is disclosed. For example, the method is executed by a processor and includes receiving a scanned image, determining that the scanned image is larger than a previously scanned image, adjusting the previously scanned image to be smaller than the scanned image, generating an adjusted previously scanned image, and causing a display to show the scanned image and the adjusted previously scanned image.

Physical documents can be scanned to generate electronic files of the physical documents. Physical documents can be scanned on a multi-function device (MFD). The physical documents can be fed into the MFD. Each page may be positioned on a platen glass that has an optical scanner on the opposite side. The MFD may use an optical scanner to capture an image of the physical document and convert the image into a page of the electronic file. The process may be repeated for each page of the physical document.


A memory storage system includes multiple flash memory storage devices, multiple transmission interfaces and a central control device. The central control device has a cache and respectively coupled to the flash memory storage devices through the transmission interfaces. The central control device is for maintaining a block map table (BMT) to record a mapping relationship between multiple logical blocks and the physical blocks of the flash memory storage devices and the BMT is temporarily stored in the cache. In addition, the central control device uses the communication commands to access the physical blocks of the flash memory storage devices, in which the communication commands are transmitted to multiple controllers in the flash memory storage devices through the transmission interfaces and the controllers access the physical blocks according to communication commands. In this way, the system can effectively manage multiple flash memory storage devices.

1. Field of the Invention
The disclosure relates to a memory storage system and a central control device, a management method and a power-failure recovery method.
2. Description of the Related Art
The flash memory is a non-volatile storage device. The data stored in a flash memory would not disappear during power-off and the flash memory is able to provide fast reading efficiency. In more details, although the access speed of a flash memory is not so fast as a dynamic random-access memory (DRAM), but it is low noise, small volume and fast access. In electronic communication products, the flash memory thereby has been broadly applied in commodity such as camera, mobile phone, flash drive and notebook computer.
A flash memory has unique characteristic. For example, data can not be directly repeatedly written into the same physical address; instead, the data only can be rewritten after performing an erasing operation. In addition, a flash memory has a plurality of physical blocks and each physical block has a plurality of physical pages, in which the minimum erasing unit is one physical block (also termed as erase unit (EU)) and the minimum writing unit is a page. Each physical page includes a data-area and a spare-area, in which the data-area is used for storing general data and the spare-area is used for storing metadata corresponding to the general data. The metadata includes, for example, logic address which the general data belong to and error correction code corresponding to the general data. Moreover, each physical block has an upper limit of erasing number of times, for example, 10-100 thousands. When the erasing number of times of a physical block reaches the upper limit, the physical block may be damaged and unable to write date into. Further, to write data into each physical block, the data must be written following the sequence of the physical pages.
Due to the above-mentioned access limit of a flash memory, in general speaking, a flash memory storage system would employ a flash translation layer (FTL) therein to conduct a translation management between logic positions and physical positions, where a mapping relationship between logic positions and physical positions is stored through maintaining a block map table (BMT).
Based on the above mentioned description, in a large server, if the system employs flash memories serving as storage units, many problems must be confronted. For example, a plurality of flash memory storage devices must be managed simultaneously, so that the translation management between logical positions and physical positions becomes more complex. Since during the operation of the flash memory storage system, the BMT must be temporally stored in a volatile memory for updating convenience, hence, once abnormal shutdown occurs, the BMT would be lost. When that is the case, although the BMT can be rebuilt by scanning the spare-areas of the physical pages of all the physical blocks in all the flash memory storage devices during rebooting, but it definitely consumes much time. In this regard, how to effectively manage a large memory storage system with multiple flash memory storage devices and deal with and respond abnormal shutdown of the large memory storage system has become a critical issue to be solved by the relevant developers.

Power-failure recovery device and method for flash memory

Industrial Technology Research Institute