A method is disclosed for generating a ceramic coating on a superalloy substrate. A first constituent of the coating and a second constituent of the coating are provided separate from one another, and preferably within a sealed chamber that has been evacuated. The first constituent and the second constituent are heated and evaporated to generate a first evaporant and a second evaporant, and form a vapor flux. The flux is then condensed on the article to generate the coating.

Electron beam physical vapor deposition (EB-PVD) is one method for coating substrates or other components with thin layers of columnar grain coatings, and is typically performed within a sealed chamber that is maintained at a low gas pressure. The application of ceramic TBCs to substrates fabricated from superalloys is known, for example from U.S. Pat. No. 4,321,311 to Strangman, which discloses columnar grain ceramic thermal barrier coatings; U.S. Pat. No. 4,405,659 to Strangman, which discloses a method for producing columnar grain ceramic TBCs; U.S. Pat. No. 4,405,660 to Ulion et al, which discloses a method for producing metallic articles having durable ceramic TBCs; and U.S. Pat. No. 5,087,477 to Giggins, Jr. et al., which discloses an EB-PVD method for applying ceramic coatings.
During EB-PVD, an electron beam impinges upon a coating target provided in solid form, e.g., as a stick or rod of material. The target is held in a cooled crucible, generally in the shape of a hollow cylinder. The beam heats the exposed end of the target, thereby forming a molten pool of target material. The material vaporizes, and the vapor or evaporant fills the chamber and condenses upon the surface of the substrate to form the coating. One such target/coating material is yttria stabilized zirconia (YSZ), which is characterized by constituents having similar vapor pressures. Accordingly, the constituents tend to vaporize at similar rates, and the composition of the resultant TBC corresponds to the composition of the target.
The general purpose of TBCs is, of course, to reduce heat flow into the component, thereby protecting the substrate. In aircraft applications, and particularly with respect to the first several turbine stages, turbine blades and vanes are subjected to gas temperatures of up to 2500-3000.degree. F., which are well above the melting point of the underlying substrate. The TBC therefore must have a low thermal conductivity and usually the component must also be cooled. However, providing cooling to the component reduces the operating efficiency of the turbine. YSZ has a thermal conductivity of about 20 Btu-in./(hr-ft.sup.2 -.degree. F.) or 2.3 W/(m-.degree. C.). While YSZ has served as a satisfactory TBC for a number of years, lower thermal conductivity TBCs are desired.
One known target/coating material is yttria stabilized zirconia (YSZ), which is characterized by constituents having similar vapor pressures. Accordingly, the constituents tend to vaporize at similar rates, and the composition of the resultant coating corresponds to the composition of the target. YSZ has a thermal conductivity of about 20 Btu-in./(hr-ft.sup.2 -.degree. F.) or 2.3 W/(m-.degree. C.). While YSZ has served as a satisfactory TBC for a number or years, lower thermal conductivity TBCs are desired.
A TBC having lower thermal conductivity offers several advantages for aircraft and other gas turbine applications. Given a constant TBC thickness and gas temperature, blade/vane temperatures are lowered thereby extending blade/vane life. Given a constant coating thickness and metal temperature, higher gas temperatures are possible thereby improving efficiency. Given a constant gas temperature and constant metal temperature, thinner coatings may be utilized, which greatly reduces the pull exerted by a rotating blade and enables use of smaller, lighter disks and/or increased creep life. Moreover, thinner coatings are expected to be more durable than thinner coatings, to the extent that thermal stresses in the thicker coatings are believed to contribute to TBC failure. Variations of the above, e.g., application of a somewhat thinner TBC and operation at a somewhat higher gas temperature, may also be desirable.
In an effort to generate TBCs having improved characteristics such as reduced thermal conductivity, other combinations of constituents have been utilized. U.S. Pat. No. 5,334,462 to Vine et al. discloses a ceramic insulating material and insulating coating made thereof. The coating material is a yttria strengthened ceria. The addition of a small amount of yttria, e.g., 0.5 w/o (0.5 percent by weight) significantly hardens the ceria, and provides a material which is useful as a TBC. It was suggested that the above-noted beneficial effects of yttria strengthened ceria apply up to, or even above, the solid solubility limit of yttria in ceria, which is about 12 w/o yttria.
Test applications of this material applied by EB-PVD, in which a unitary, solid source of yttria and ceria target material is employed, indicate that EB-PVD does not provide TBCs with a percentage of yttria comparable to the target. It is believed that since the ceria has a significantly higher vapor pressure than yttria, the resulting TBC necessarily has a significantly lower weight percentage of yttria than does the target. As noted in Vine et al., a target having 9 w/o yttria results in a TBC having only 0.5 w/o yttria using the above-described EB-PVD techniques. Moreover, solid single source targets of constituents which are not miscible, tend to crack during heating due to the thermal gradients that are generated between the two distinct constituents.
In addition, it is preferable that TBCs also exhibit erosion resistance.
It is a general object of the present invention to provide a method for producing vapor fluxes of two or more evaporants to form TBCs.
It is a more specific object of the invention to provide a method in which the amounts of the constituents in the flux are adjustable, thereby enabling adjustment of the composition of the resultant TBC.
It is another object of the invention to provide a method for generating TBCs from constituents having significantly different vapor pressures, such as yttria and ceria


In a heating device, a material is heated by heat from a hydration reaction with an exothermic material and water. A container for the material heated is provided above a container for the exothermic material and has a number of apertures at a bottom wall of the portion for containing the material to be heated. The apertures spout vapor of a high temperature generated by the heat of hydration reaction with the exothermic material and water to the inside of the container for the material to be heated so that the vapor of high temperature is added to the material to be heated from right below the material to be heated in addition to conductive heat transferred through a wall of the portion for containing the material to be heated.

As a heating device for easily heating drinks such as coffee, tea and so forth or cooked foods, there have been provided heating devices which use by heat of hydration reaction between an exothermic material and water.
However, in these conventional heating devices, as seen in, for example, Japanese patent publication (kokai) No. 62-16371 and 61-259974, and Japanese utility model publication (kaukoku) No. 62-32500, European patent publication No. 3231513, Japanese utility model publication (koukai) No. 61-35, a portion for containing a material to be heated and a exothermic part are parted by a partion wall or walls of container and the material to be heated is heated only by conductive heat transferred therethrough. As a result, therefore, a part of the material to be heated contacting with the wall is heated to a high temperature, while other parts distant from tile wall can not be heated until they reach a sufficient temperature. Especially, in the case when a material to be heated is a solid, this tendency becomes remarkable; that is, the part in contact with the wall is scorched but an inner temperature is not raised sufficiently.
The heating devices, described in Japanese utility model publication (koukai) Nos. 62-123742 and 61-137318, have an aperture at a bottom wall. The vapor produced by heat of hydration reaction can heat the materials to be heated without causing uneveness of temperature, as described above.
In the heating devices described in Japanese utility publication (koukai) Nos. 62-123742 and 61-137318, it is a problem that small pieces of the exothermic material may be attached to the material to be heated together with the vapor of high temperature through apertures of the portion for containing the material to be heated.
The object of the present invention is to provide heating device in which small pieces of the exothermic materials spattered by reaction of the exothermic material and water does not tend to attach to the material to be heated.
Then, the heating device described above is one in which the exothermic material and water after hydration reaction are mounted with unremoved off, as disclosed in Japanese patent publication (koukai) No. 62-16371, and one in which exothermic materials or a bag containing the exothermic materials is directly included, as Japanese utility model (koukai) No. 61-137318, the device, after having made hydration reaction of the exothermic materials could not be re-used.
The other object of the present invention is to provide a cartridge-type heating device comprising portion a for containing the exothermic materials, which is applied to different styles of the heat devices, and also the heating devices are reusable.


The present invention relates an RF tuner module that comprises one or more standard RF connectors. As, relative big, standard RF connectors are widely in use but at the same time there is a pressure to make products smaller an RF tuner module design is size constrained. The invention describes a measure to make an RF tuner module, with a standard RF-connector, smaller by extending one of the shielding sides of the RF tuner in order to facilitate a proper mounting of the RF connector to the RF tuner module.

In the field of consumer electronic products, such as an LCD TV, Set-Top-Box, a cable modem, a move towards slim designs and smaller components is required. This includes the requirement for a smaller (low-profile) RF (Radio Frequency) tuner module. However, the requirement of the use of standard RF connectors such as IEC and F-type connectors (which typically can be found as part of a RF tuner module) creates a restriction to the design of a low-profile RF tuner module.
A prior art, high vertical profile, RF tuner module typically comprises a metal-stamped frame, which houses an internal electrical circuit. It has both a top and bottom metal cover that closes the frame for shielding purposes. The module also may comprise one or more standard RF connectors, I/O (Input/Output) pins and mounting tags on the frame. Such as module can be applicated by, e.g., inserting its signal pins and mounting tags onto, e.g., a chassis PCB with a matching footprint. An RF signal is fed into the tuner module via an RF coaxial cable with a matching RF connector at its end.
Another prior art low-profile design RF tuner module does not comprise a standard RF connector. The RF input is fed instead to the module via one or more signal pins through its cover. Such a module can also be applicated by, e.g., inserting its signal pins (including an RF-in signal pin) and mounting tags onto, e.g., a chassis PCB with a matching footprint. The RF-in pin is connected to a separate RF connector via copper track on the chassis PCB. This affects the RF signal coming into the tuner module due to signal disturbances though the copper track connections, and also poor matching of the input impedance via the pin connector, resulting in bad performance of the RF tuner module.

Flat turner module with a standard connector


To produce substances of vegetable origin, a vegetable organ is implanted in a culture medium and is kept under hypoxia by immersion beneath a layer of oil and the substances produced are extracted from the organ, the medium and/or the oil.

This invention relates to a process for the production of substances of vegetable origin by "in vitro" culture.
Numerous substances of vegetable origin have a certain economic value for such industries as the pharmaceutical industry (active principles of medicaments), the cosmetics industry (perfume) and the food industry (flavourings and additives). The substances in question are generally produced by extraction from collected or cultivated plants. However, this method has many disadvantages, particularly in regard to restocking of the vegetable starting material (periodicity, stability, quality, etc.).
Various substitute processes have been investigated with a view to obviating these disadvantages. They include the "in vitro" process for culturing undifferentiated tissues or cells of productive species. Reference is made in this regard to Japanese patent JP 57-39778, which relates to the culture of calluses in an agitated liquid medium containing cellulose to extract the active principles therefrom with paraffin oil and/or fats, and to the Article by Bisson et al (Journal of Medicinal Plant Research, 1983, 47, 164) which relates to the extraction of essential oils from a culture of undifferentiated cells of camomile by addition to the nutrient medium of droplets of a fatty phase in which the oils are to accumulate. However, because they use undifferentiated cells, these techniques are limited to the preparation of well-defined products.

Process for the production of substances of vegetable origin


A circuit arrangement for controlling a system, and a system having a circuit arrangement, both suitable for use with a lumbar support with at least two air cushions, may include actuators, voltage supply paths, and electronic switching elements.

Systems called lumbar support, which can especially be pneumatically adjusted and integrated into a seat such as a car seat, are used to increase seating comfort. To adjust the backrest of the seat, the system comprises several air cushions filled with air that can be deflated once again in order to change the contour of the seat or backrest. To inflate or deflate them, the air cushions are typically connected to a pneumatic pump via supply lines and to the ambient atmosphere, in which case valves are arranged in the supply lines for opening and closing. The valves themselves are in each case adjusted by actuators for which generally electromagnets are used.
Furthermore, actuators based on wires made of SMA (shape memory alloys) elements are used in which a positioning element of the actuator is activated when current is supplied to the SMA element. If a supply voltage is fed to an actuator or its SMA element, power is supplied to it and the actuator is activated. In this case, the power supplied must be maintained within a very narrowly defined range to ensure the reliable activation of the actuator and nonetheless prevent a thermal overload, which would damage the SMA element permanently. However, in practical use, this is often problematic, as the supply voltage is subject to large fluctuations, especially when used in the automotive sector, and when excessive current is fed to the SMA elements with direct contact. Moreover, the power supplied should typically be varied depending on the surrounding temperature, so that less power is supplied with a higher surrounding temperature than with a lower surrounding temperature in order not to overload the SMA element once again.
To ensure a reliable functionality of the SMA elements and actuators, it is known for example to integrate the actuators into a circuit arrangement with a control unit that takes over the most varied tasks, especially a measurement of the supply voltage and the surrounding temperature by means of the temperature sensors integrated into the control unit. Here, the SMA elements are controlled via pulse width modulation, wherein depending on the measured supply voltage and temperature of the duty cycle of the pulse width modulation, hence the ratio of pulse width to period duration, is adjusted. Another option consists of using a power source controlled by a control unit to adjust the current flowing through the SMA elements or using temperature-dependent power sources, wherein one power source must be available for each actuator.
Therefore, the known circuit arrangements or methods are elaborate and expensive because of the components needed, e.g. control unit, temperature sensors or power sources. In addition, many components are necessary, such as one power source for every actuator. Furthermore, due to the power loss occurring in the power sources, which must necessarily be dissipated to the surroundings in order to prevent the circuit and its components from overheating, no compact design is possible, although desirable, especially when used in a car seat.

Circuit arrangement to control system and system with circuit arrangement


An electronic device includes a display portion with a monitor, an operating portion, a button portion and an illuminant. The operating portion is pivotally connected to the display portion, and includes a casing and a touch unit located inside the casing. The button portion is located in the casing and facing to the touch unit. There is no through seam provided between the button portion and the casing. At least one part of the button portion is pervious to light. The illuminant is installed in the casing and near the button portion.

1. Field of Invention
The invention relates to an electronic device and, in particular, to an electronic device comprising a light pervious button portion and the illuminant.
2. Related Art
As the coming of the electronic age, people demand for and depend on the electronic products more. Taking notebooks for example, since the notebooks possesses the popular utility, they become more and more common. In this consumer-oriented era, not only the competitive price of the good products, but the quality and the utility are also concerned by the consumers. Therefore, the manufacturers are trying to make better product to meet consumer's needs.
To make the invention easier to be illustrated, a notebook is taken for example hereinafter. A conventional notebook 1 includes a display portion 11 and an operation portion 12. The display portion 11 includes a display 111. The operation portion 12 is pivoted to the display portion 11 and includes a casing 121, a button unit 122 and a switch unit 123. The button unit 122 includes a button portion 1221, a connecting-arm 1222 and a fixing portion 1223. The fixing portion 1223 is connected to the casing 121, and the button portion 1221 is connected to the fixing portion 1223 with the springy connecting-arm 1222. The fixing portion 1223 can be fixed on the casing 121 by the way of thermal fusing. Surely, the fixing portion 1223 can also be screwed on the casing 121 with screws (not shown).
Referring to FIG. 2, when the button portion 1221 is pressed to move toward a first direction d1, since the connecting-arm is springy and the fixing portion 1223 is fixed on the casing 121, a rebound is produced to make the button portion 1221 move toward a second direction d2 as the pressing force is released. In this case, the second direction d2 is reverse to the first direction d1.
The switch unit 123 is disposed in the casing 121 and is positioned under the button portion 1221. The switch portion 123 includes a switch 1231 and a circuit board 1232. When the button portion 1221 is pressed to move toward the first direction d1, the button potion 1221 contacts with the switch 1231, so as to act the switch 1231 to create electronic connection with the circuit board 1232.
Since the button unit 122 and the casing 121 are separated and assembled together, the bad assembling problem may happen during manufacturing, which reduces the production yield and increases the producing cost. Moreover, a through seam 3 is needed between the casing 121 and the button unit(s) 122 to avoid getting stuck. However, it is thus easy to accumulate dust in the trough seam 3 that causes the inconvenience for cleaning. Besides, when the environment light is insufficient, the users may not tell the right position of the buttons correctly, resulting in inconvenience of operations.
It is therefore a subjective to solve the above-mentioned problems.

Electronic device with illuminant portion


A vehicular active vibratory noise control apparatus includes an adaptive notch filter (second control signal generating unit) for generating a corrected error signal representative of a road noise only by removing the component of a rotational frequency (the component of an engine muffled sound) from an error signal, generates a first control signal from the corrected error signal and a reference signal, and reduces the component of the rotational frequency (engine muffled sound) at a position where a microphone is located (evaluating point).

1. Field of the Invention
The present invention relates to a vehicular active vibratory noise control apparatus for canceling a road noise by causing a canceling sound that is in opposite phase with the road noise to interfere with the road noise.
2. Description of the Related Art
Heretofore, there has been proposed in the art an active noise control (ANC) apparatus for canceling a road noise (also called "drumming noise") in the passenger's compartment of a vehicle with a canceling sound that is in opposite phase with the road noise at an evaluating point (hearing point) where a microphone is located (see Japanese Laid-Open Patent Publication No. 2000-280831). The road noise is based on the vibrations of vehicle wheels which are caused by the road when the vehicle is running on the road, transferred through the suspensions to the vehicle body, and particularly excited by the acoustic resonant characteristics of the closed room such as a passenger's compartment. The road noise has a peak level at a frequency of about 40 [Hz] and has a frequency bandwidth in the range from 20 to 150 [Hz].
The vehicle has various rotating components including an engine crankshaft, a transmission main shaft, a transmission countershaft, a propeller shaft, etc. which rotate when the engine on the vehicle operates. The rotational frequency of these rotating components varies depending on the speed of the vehicle, etc. When these rotating components rotate, they produce a noise (hereinafter referred to as "engine muffled sound" to be distinguished from the road noise) in the passenger's compartment based on the rotational frequency.
It has been found that when the active noise control apparatus for canceling the road noise is turned on in a frequency range wherein the rotational frequency of the rotating components in the passenger's compartment overlaps the frequency of the road noise, the engine muffled sound caused by the rotation of the rotating components does not change per se, but tends to increase at the evaluating point.
For example, FIG. 12 of the accompanying drawings shows a graph of sound pressures (represented by the vertical axis) measured in the position (evaluating point) of the ears of the driver of a vehicle at different frequencies (represented by the horizontal axis). As shown in FIG. 12, a characteristic curve 2 indicated by the dotted lines is plotted when the road-noise ANC apparatus on the vehicle is turned off, and a characteristic curve 4 indicated by the dot-and-dash lines is plotted when the road-noise ANC apparatus on the vehicle is turned on. As indicated by the characteristic curves 2, 4, at the frequency of 42 [Hz] at which the sound pressure of the road noise is maximum, the sound pressure is lower by 10 [dB] or more when the road-noise ANC apparatus is turned on than when the road-noise ANC apparatus is turned off. However, at the frequency of 65 [Hz] which corresponds to the rotational frequency, the sound pressure is higher by about 5 [dB] when the road-noise ANC apparatus is turned on than when the road-noise ANC apparatus is turned off. The road-noise ANC apparatus is disadvantageous in that while it can reduce the road noise, it tends to increase the engine muffled sound at the frequency of 65 [Hz].
Furthermore, as shown in FIG. 13 of the accompanying drawings, if the rotational frequency is of about 45 [Hz], then a characteristic curve 6 indicated by the dotted lines is plotted when the road-noise ANC apparatus is turned off, and a characteristic curve 8 indicated by the dot-and-dash lines is plotted when the road-noise ANC apparatus is turned on. The comparison of these characteristic curves 6, 8 shows that the road-noise ANC apparatus is not effective to lower the sound pressure at the rotational frequency of about 45 [Hz].

Vehicular active vibratory noise control apparatus


The disclosure relates to support frames for prosthetic implantable valves. The support frames may include a plurality of symmetrically arrayed interconnected U-shaped member structures. Preferred support frames are tubular structures enclosing a longitudinal axis and including a plurality of U-shaped member structures facing a distal or a proximal end of the support frame. Each U-shaped member structure may be connected to a single longitudinally adjacent U-shaped member facing in an opposite longitudinal direction, as well as two laterally adjacent U-shaped members.

Intraluminally implantable frames may be implanted to treat a variety of conditions in a variety of fields. Frames implanted in vessels, ducts or channels of the human body can form part of a valve to regulate fluid flow within a body lumen or as scaffolding to maintain the patency of the vessel, duct or channel lumen. Implantable frames can also support a valve or valve leaflets for regulating fluid flow within a body lumen or for dilating a body lumen. One or more flexible valve leaflets can be attached to an implantable frame to form a medical device useful as an artificial valve. A variety of other implantable prostheses, such as stents, grafts and the like, also comprise an implantable frame placed within the body to improve the function of a body lumen.
The venous system includes a series of valves that function to assist the flow of blood returning to the heart. These natural valves are particularly important in the lower extremities to prevent blood from pooling in the lower legs and feet during situations, such as standing or sitting, when the weight of the column of blood in the vein can act to prevent positive blood flow toward the heart. This condition, commonly known as chronic venous insufficiency, is primarily found in individuals in which gradual dilation of the veins, thrombotic events, or other conditions prevent the leaflets of the native valves from closing properly. The failure of native valves to properly close can worsen, leading to significant leakage of retrograde flow such that the valve can become incompetent. Chronic venous insufficiency is a condition in which the symptoms can progress from painful edema to skin ulcerations. Elevation of the feet and compression stocking can relieve symptoms, but do not treat the underlying disease. Untreated, the disease can impact the ability of individuals to perform in the workplace or maintain their normal lifestyle.
One promising approach to treating venous valve insufficiency includes the implantation of self-expanding or radially-expandable artificial valves that can be placed using minimally invasive techniques. Recently, the development of artificial and biological valves has been employed to provide additional regulation of blood flow within blood vessels, such as veins. There are a variety of these valves described in the art, which are generally designed to allow normal flow of blood back to the heart, while preventing retrograde flow. However, dynamic fluctuations in the shape of the vein pose challenges to the design of implantable devices that conform to the interior shape of the vein. The shape of a lumen of a vein can undergo dramatic dynamic change as a result of varying blood flow velocities, pressures, and volumes therethrough. Implantable intraluminal prosthetic valves should be compliant enough to conform to the changing shape of the vein lumen and prevent irritation of the wall of the vein contacting the valve, but rigid enough to maintain vein patency and/or valve function within the vein. Blood flow within a vein is intermittent and bidirectional, subject to constant fluctuation in pressure and volume. These conditions may present challenges to designing an implantable frame suitable for placement inside the vein. An implantable frame lacking sufficient radial strength may collapse and/or fracture under the repeated fluctuations of vein diameter, while an implantable frame with undesirably high levels of radial strength may lack flexibility and may damage the vein by failing to compress in response to normal fluctuations in the vein diameter. Likewise, an implantable frame with a high surface area contacting the interior wall of a vein may induce inflammation or trauma in the vein wall, while an implantable frame with an insufficient surface area may lack sufficient durability.
What is needed is an intraluminally-placed medical device, such as a support frame, that provides structure for an artificial valve and is configured to distribute stress and strain forces within the frame during dynamic movement of a body vessel and intermittent fluid flow within the body vessel. In addition, medical devices are needed that provide sufficient radial strength to maintain vessel patency while being configured to prevent migration within the body vessel and minimize irritation of the body vessel. There also remains a need for a support frame configured with a radial strength to maintain patency of a body vessel while supporting a means for regulating fluid within the body vessel and minimizing irritation to the body vessel after implantation and/or extensive wear to the prosthetic valve leaflets during leaflet motion.


A vaginal speculum having a universal connection between the handle and each of a plurality of blades, for selectively detaching and attaching one or more of the blades at any one of a plurality of angles between the handle axis and the blade axis. Preferably, the vaginal speculum is part of a kit having a plurality of elongated blades adapted to penetrate and fully enter a vagina while providing surgical access, each being interchangeably connectable to the handle, thereby providing a variety of options for blade length, blade width, or blade contour to better fit the vaginal structure of a particular patient. Each blade is made of a rigid or semi-rigid plastic, that is disposable after each use. The handle is preferably made of heavy metal, with a permanent plastic sheath or coating.

The present invention relates to a weighted vaginal speculum of the type comprising an elongated blade having a contour adapted to penetrate and fully enter a vagina while providing surgical access, and an elongated, weighted handle connected to the blade, for initially manipulating the blade and providing a counter weight to the blade during surgery.
A variety of vaginal specula have been used or described in printed publications, for maintaining access to a female vagina while the surgeon inserts various instruments along or through the blade to perform the necessary procedures within the vagina. Such specula have been adapted for use in conjunction with particular instruments, such as fiber optic cables, and other unique forms of diagnostic, monitoring and incision related equipment. In general these specula have been designed for compatibility with the type of diagnostic or surgical procedure, and in particular for unique instruments and equipment, rather than for the particular characteristics of the patient's anatomy.
From patient to patient, the vagina can vary as to length, width, taper angle, and angle of the vaginal centerline relative to the surface of a surgery table on which the patient lies. In typical vaginal diagnostic or surgical procedures, the doctor or surgeon must adapt the positioning and support of the speculum to the particular characteristics of the patient's vagina. This adaptation is either very time consuming, for example, by selecting one of a plurality of available specula and trying one after the other until a good fit is obtained, or else using a standardized speculum that must be supported in an awkward or less than ideal orientation. Moreover, if multiple specula are tried before the "best fit" is identified, this requires that for each operation multiple specula be available, and multiple specula will require autoclave treatment before reuse.


The present invention relates to a high-power semiconductor laser having low divergence and low astigmatism, this laser being including, in an active layer, a first part in the form of a narrow monomode stripe with transverse index guiding terminating in a second part flaring out from the first part, also with transverse index guiding.

Semiconductor lasers with a power of greater than 1 watt are generally lasers of the broad stripe type and, depending on the required emission power, may be unitary lasers or lasers arranged in parallel to form arrays. The main drawback of such lasers is that the amplitude distribution of their emitted beam in a plane perpendicular to their emission face is highly divergent (with a divergence of around 15° in a plane parallel to the active layers) and very inhomogeneous. This results in a reduction in the efficiency of coupling to an optical fiber. The cause of this is the existence of parasitic modes in the laser cavity and the presence of "filamentation" defects (the electron current within the semiconductor does not pass through the entire active section of the semiconductor, but inhomogeneously).
To improve the homogeneity of the near field of the emission face of such lasers, a monomode narrow stripe laser (acting as a filter), extended by a flared part acting as an amplifier, is integrated on the same chip. Power levels substantially above 1 watt can then be emitted, while maintaining a monomode transverse beam. The known lasers have been produced in the following two configurations. The first consists in etching, in active layers, a narrow monomode stripe with transverse index guiding followed by a flared part, which also has transverse index guiding, where "transverse index guiding" means that the lateral confinement of the optical field is achieved by differentiation of the refractive index between the narrow stripe zone and the zones bordering the stripe. The second configuration also includes a narrow monomode stripe with transverse index guiding, but followed by a flared part with transverse gain guiding. Hitherto, no other configuration has been proposed, as it was considered that only the two aforementioned configurations allow the quality of the laser beam emitted to be easily controlled. However, these known structures are relatively complex to produce and their dissipated heat is not easy to extract. For example, patent US 2004/125846 discloses a laser of the narrow stripe type, said stripe being extended by a flared part, but this laser is complex to produce (it includes etching and regrowth steps).

Power semiconductor laser with low divergence and low astigmatism, and method for the production thereof


An LED light source includes a sub-circuit (24) that is connectable via terminals (12,13) to an electronic transformer and to a powered circuit including at least one LED (4). The sub-circuit (24) includes a sub-circuit rectifier (1a, 1b, 1c, 1d) that is connectable to the transformer (25), and a constant current regulator (7) and a sub-circuit capacitor (6) that are connected parallel to the sub-circuit rectifier (1a, 1b, 1c, 1d).

LED light sources are often used to replace low voltage (12V) halogen lamps in order to save energy, but problems may occur when LED light sources replace halogen lamps and are connected to existing electronic transformers.
Electronic transformers contain a high-frequency oscillator feeding an isolation transformer which powers a connected load, such as a halogen lamp or an LED light source. The load needs to draw sufficient power from the electronic transformer in order for the transformer to turn on and supply power, i.e. the transformer needs to be sufficiently loaded. Typically, electronic transformers for 12V halogen lamps are rated to operate with loads of 20-70 W and the halogen lamps are typically supplied with 20 W or 50 W power ratings. However, LED light sources that replace halogens typically draw far less power than 20 W, with the result that the transformers are under loaded.
Electronic transformers cease to supply power if the connected load is below a minimum level. When connected to an electronic transformer, LED light sources initially present the transformer with a sufficient load to turn the transformer on. However, following an initial inrush power, the LED light source draws less power than the minimum requirements of the electronic transformer (i.e. presents a low load) and hence the transformer turns off and ceases to supply power.
Depending on the particular electronic transformer, it may or may not turn on (re-ignite) again to supply power, with the result that the LED either receives no power (i.e. malfunctions completely) or the cycle described above is repeated and the LED flickers.
Most attempts to address the problem with under-loaded transformers are based on booster circuits followed by buck regulators. These booster circuits lower the impedance presented to the transformer. These circuits contain inductors, switches and some logic circuits like PWM generators, which cause the circuits to be costly and bulky. Further, the high switching causes EMI related problems. U.S. 20110115400 A1 discloses an example of such a booster circuit.
Other solutions attempt to ignite transformers by feeding pulsed currents back into the transformer in order to re-ignite the transformer. These solution also require logic circuitry and bulky capacitors in order to feed high enough current back to the transformer in order to re-ignite such transformer. EMI issues could occur as high current re-ignition pulses flow between LED light and transformer. U.S. Pat. No. 6,433,493 discloses an example of feed back to re-ignite a transformer.
The present invention seeks to keep electronic transformers functioning under low load conditions, to provide power to LED light sources, while avoiding shortfalls such as visible flickering, high costs, and bulk.

Circuit to keep electronic transformers working while under-loaded


A low-cost hot water use warning device, having the shape of an aerator housing, including a metallic housing inner core (2) with threads configured for attachment to a faucet and a ridged indented channel for accommodating a thermochromic belt (6) or band that may constitute several layers including an outer thermochromic layer (10) capable of changing its color at a certain temperature, a second high thermal conductivity layer (11) made of copper for evening out temperature gradients and a third low heat conducting polymeric layer (12) for imposing a controlled delay. At each vertical side of the thermochromic belt are flanking wedge-shaped isolation grooves (7). The device operates as an awareness indicator for informing a faucet user of excessive temperature and duration of hot water use.

The present invention relates to water- and energy-efficiency solutions for faucets. More particularly, the invention relates to a low-cost visual metering device for informing a faucet user of excessive temperature and duration of hot water use, ultimately leading to a reduction of hot water use due to a change in user behavior.
A number of important technological solutions that saves water and hot water for faucets have become widely adopted by the market during the last decades. Perhaps the most revolutionary example is the mixing of air with the water flow through the use of aerators. Other examples include single-lever mixers, cold-start mixers, constant flow regulators, temperature limiters and thermostats. However, none of these technologies primarily targets bad user behavior leading to water waste, a reason to why many households report water and energy usage considerably higher than others of the same size, even when accounting for factors such as the number of faucets, showers and whether there is a dishwashing machine installed or not.
As building regulations continually impose rising demands on higher energy-efficiency and rational use of natural resources, the use of hot water has come to play an increasingly pivotal role in lowering the building total energy demand. In newly renovated or constructed multi-dwelling buildings for example, having already implemented solutions such as an energy-efficient building envelope and HVAC-system, hot water use alone can account for over 50% of the building total energy use. Hot water use further tends to be split evenly between faucets and showers. However, where for instance shower timers and flow-meters are offered and readily available on the market, few sensible solutions for raising user awareness are available for faucets. Most faucets cannot bear the same costs and apparatus size as the technology for a shower system is allowed to have. A number of prior art temperature indicators for faucets address the issue of conveying water temperature information in a fast and convenient way for e.g. anti-scalding purposes, as can be seen in US2013269799A1, US2002083520A1, U.S. Pat. Nos. 5,265,959A and 4,773,767A. Prior art even also suggests the use of thermochromic pigments for this purpose. However, for addressing primarily bad user behavior leading water waste, it would be a risky approach to implement only instantaneous or almost instantaneous water temperature measurement, as that may in a behavioral context lead to more hot water use—not less. Prior art can in general, and in particular for all of the above listed documents, be said to deal with means for "hot water warning", while the present invention's objective is rather to provide means for "hot water use warning", i.e. a device incorporating some kind of use metering functionality (not only temperature) for primarily water- and energy saving purposes. Therefore, there exists a need for a device such as the one disclosed by the present invention.

Hot water use warning device for faucets


Notification systems and methods are provided for identifying utility theft for an entity associated with a premise under a Continuous Service Agreement with at least one utility service provider, where utility service is never turned off such that the entity may legally use utility services while a premise is vacant.

Millions of multifamily apartment complexes and other rental units exist in the United States. For such units, it is a common practice for the property owner/manager to enter into agreements with the utility companies to keep electricity and/or gas always turned on at the unit, even while the unit is vacant, to eliminate inconveniences and/or the service fees utility companies may charge to turn-on and shut-off service to individual units. Additionally, property owners/managers often need utility services to remain on in vacant units, for example, to perform maintenance and to keep the HVAC system running to prevent un-desirable situations such as frozen pipes in the winter, or the build-up of mold or odor in the summer. To permit always-on or continuous service, agreements between the utility company and the property owner/manager, commonly referred to as Continuous Service Agreements (CSAs), are used to authorize the transfer of payment responsibility from owners to tenants who move-in, or to transfer payment responsibility back to the owner when tenants move-out. In most cases, the tenants of the units are responsible for establishing utility services with local utility companies as required in their lease agreements, which often require that a tenant contact their local utility prior to move-in to sign up for services and to keep that service on for the duration of their lease.
Under CSAs, until a tenant contacts a utility company and establishes service in their name, the owners will typically be responsible for payment of those utility services—even though the tenant still occupies the unit. Also, later when a tenant contacts a utility company with a false move-out date prior to vacating a unit, the owners again will be responsible for payment of those utility services under the CSA. Because the average turnover for tenants in multifamily units is high, the use of a CSA exposes property owners to a significant amount of utility-related expenses when a tenant reports a false move-out or fails to take responsibility for utility charges after move-in. Although this problem applies to many multifamily units, the problem also exists for any leased space where arrangements such as CSAs exists and a non-owner tenant is responsible for utility service charges. Currently, when a multifamily unit tenant fails to apply for a utility service under their name, the property manager or owner will receive the utility bills for the occupied units, and it may take 45 days or longer before the owner becomes aware that the tenant has not established service in their name. The property manager or owner must then go through the tedious and complex task of matching bills for occupied units with tenants, which requires the correct information to permit a property manager to identify the tenants that owe money for utilities. This task of cost recovery based on utility bills is made even more difficult due to unit turnover because utility bills often apply to utility service consumed months earlier, and tenants within a particular unit may have already moved out. Often the situation goes un-noticed for months and results in loss of income for owners and property managers. Furthermore, in the event that tenants call their local utility company and ask for a disconnection or shut off of service under their name before moving out, owners can become prematurely responsible for utility expenses that should be paid by the tenant.
In recent years some multifamily owners have outsourced the identification of utility recovery to third party service companies that match utility bills with tenant data received from property owners and provide multifamily tenants with a recovery bill. This type of service is known as Vacant Cost Recovery (VCR). VCR bills are typically available 45 or more days after the usage service period, and the utility recovery process is generally only available for those tenants who fail to enroll for service at the time of move-in. When tenants report a false move-out date to the utility within 45 days of their actual move-out, the utility bills for units may go un-recovered because the bills are not received until after the tenant has vacated the unit. As such, these utility recovery processes lack the ability to identify potential cost recovery opportunities on the back end or at the time of move out. In addition, standard utility recovery methods report move-in violations approximately 45 days or longer after the violation, putting pressure on multifamily owner's cash flow since utility bills are paid to utility companies before utility recoveries are collected from tenants. Therefore, a system and method is needed to quickly identify utility theft by tenants who are or who will be receiving services for which the owner may incur costs.

This patent is subject to a terminal disclaimer.

Systems and methods for the prevention of extended utility theft


In a case where a conversion result image corresponding to a former image has been stored in a memory, control is performed to transmit this conversion result image without performing any image conversion process on the former image.

1. Field of the Invention
The present invention relates to an image communication apparatus, an image processing apparatus, an image communication method and an image processing method which perform a predetermined conversion process to an input image and then output the conversion-processed image, and to programs which execute those methods.
2. Related Background Art
In recent years, an image processing apparatus which has various image input/output functions such as a scanner function, a printer function, a copying function, a fax function and the like is known. Moreover, an image processing system in which such an image processing apparatus, an image processing apparatus of another kind, and a host computer such as a PC (personal computer) or the like are connected to others through a network is known. In such an image processing system, an image input by the image input function of one image processing apparatus can be output to another apparatus on this system. Further, when the image is output, the image to be output is subjected to an image conversion process by using an image conversion function provided in the image processing apparatus, and then the image obtained by the image conversion process can be output.
As an example of the image processing apparatus, a digital multifunctional device (simply called a "multifunctional device" hereinafter) is given. Here, the multifunctional device has a function to transmit or print an image obtained by reading an original with a scanner or an image externally received. When the multifunctional device executes this function, the original image is subjected to the conversion process by using the image conversion function, and then the image obtained by the conversion process can be transmitted or printed.
The above operation is controlled by a controller of the multifunctional device. For example, when the above image transmission is performed, a CPU (central processing unit) provided in the controller executes a transmission application. Further, when the above printing is performed, the CPU executes a copying (printing) application.
Moreover, when a document read by the scanner is transmitted, the CPU performs a conversion process concerning the number of pixels, resolution, a direction and the like on the read document, whereby the image suitable for a transmission destination can be transmitted. At this time, the CPU executes the transmission application and controls the scanner, a hard disk, a transmission I/F (interface) and the like. Meanwhile, the CPU controls the conversion process by using image processing hardware, a memory and the like. This conversion process is performed with respect to each page, and the image of the page which has been transmitted and is thus no longer necessary is cancelled from the disk.
In recent years, a digital multifunctional device which includes plural transmission applications has been proposed. In this digital multifunctional device, each transmission application performs an image conversion process, with respect to each page, on an image to be transmitted, and then performs the transmission of the processed image. For example, one transmission application may perform the image transmission by electronic mail, and another transmission application may perform file transfer on the basis of the standard file transfer protocol (FTP).
However, when one image is transmitted by using plural transmission applications, there is a case where an identical image conversion process is to be performed on the one image and the processed image is transmitted in accordance with a combination of these transmission applications, for example, a case where the identical former image is transmitted to plural destinations respectively by using several different transmission applications. Here, each transmission application performs the image conversion process, the transmission of the converted image, and the cancellation of the unnecessary image independently of the other transmission applications. For this reason, even if the identical former image is transmitted to plural destinations by means of plural transmission applications, each transmission application performs the same image conversion on all the pages of the identical former image. This means that the same image conversion process is redundantly performed plural times, resulting in the wasteful use of CPU resources.

Image communication and processing with common performance of processing of a file preparatory to further processing by different applications


A semiconductor integrated circuit device includes a pair of complementary signal lines, a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being coupled to one of the pair of the complementary signal lines, and a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of the first transistor, one of a source and a drain of the second transistor coupled to an other of the source and the drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to the other of the pair of the complementary signal lines. A direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor.

The present invention concerns a semiconductor integrated circuit device and it particularly relates to a semiconductor integrated circuit device having a plurality of transistors formed over one identical diffusion layer.
In the semiconductor integrated circuit device, reduction in the circuit area directly leads to reduction in the manufacturing cost. Particularly, in a case of semiconductor memory devices, etc., when the area of a circuit portion that is used repetitively in an identical layout pattern can be reduced even at the slightest, a significant effect of decreasing the cost can be obtained.
A sense amplifier circuit is used repetitively as a circuit portion in a dynamic semiconductor memory device. In the dynamic semiconductor memory device, a plurality of sense amplifier circuits are coupled to a memory cell array in which memory cells are arranged in a matrix. FIG. 1 is a circuit diagram showing the configuration of one sense amplifier circuit in a general dynamic semiconductor memory device.
Referring to the constitutional elements of the sense amplifier circuit in FIG. 1, the sense amplifier circuit includes a first bit line BLT, a second bit line BLN, a sense amplifier SA, a precharge/balance device Q, an equalize signal input portion EQ, and a half power source voltage input portion HVC. The precharge/balance device Q includes a first transistor Q1 as a balance device, a second transistor Q2 as a first precharge device, and a third transistor Q3 as a second precharge device. As the most general sense amplifier SA, a simple flip-flop circuit is used.
The coupling relation for the constitutional elements in the sense amplifier circuit in FIG. 1 is to be described. One end of the sense amplifier SA is coupled to a first bit line BLT. The other end of the sense amplifier SA is coupled the second bit line BLN. One of the source and the drain of the first transistor Q1 is coupled to the first bit line BLT. The other of the source and the drain of the first transistor Q1 is coupled to the second bit line BLN. Gates of the respective first to third transistors Q1 to Q3 are coupled in common to the equalize signal input portion EQ. One of the source and the drain of the second transistor Q2 is coupled to the first bit line BLT. One of the source and the drain of the third transistor Q3 is coupled to the second bit line BLN. The other of the source and the drain of the respective second and third transistors Q2 and Q3 are coupled to the half power source voltage input portion HVC.
The operation of the sense amplifier circuit shown in FIG. 1 is to be described briefly. At first, the potential difference between the first and second bit lines BLT and BLN is decided depending on the state of a memory cell coupled to one of the bit lines thereof and selected by a word line.
The half power source voltage input portion HVC supplies a half power source voltage as one-half of a power source voltage VCC to the source-drain coupling portion of the second and third transistors Q2 and Q3. As a result, the second and third transistors Q2 and Q3 precharge the half power source voltage to the first and the second bit lines BLT and BLN. Since the second and third transistors Q2 and Q3 operate as two precharge devices, they are generally designed with an identical size of the gate width and in a symmetrical layout.
Finally, the sense amplifier SA amplifies the voltages of the first and second bit lines BLT and BLN to complementary potentials in accordance with the difference between the potentials and the half power source voltage respectively.
Then, the gates of the first, second, and third transistors Q1, Q2, and Q3 are provided an equalize signal from the equalize signal input portion, respectively. As a result, the source and the drain are conducted in each of the first, second, and third transistors Q1, Q2, and Q3, and the voltages of the first and second bit lines BLT and BLN become identical. While the same effect can be obtained only by the second and third transistors Q2 and Q3, if the first transistor is added, a potential is supplied to the first and second bit lines BLT and BLN and the potentials of the BLT and BLN can be equalized at a higher speed by the first transistor when it is intended to equalize the voltages between them. As described above, since the first transistor Q1 operates as a balance device, the gate width is generally designed to be longer than the gate width of the second or third transistor Q2 or Q3 so that a larger current flows at once.
FIG. 2A is a plan view showing a layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device Q shown in FIG. 1. FIG. 2B is a plan view showing another layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device Q in FIG. 1.
Each of the semiconductor integrated circuit portions in FIG. 2A and FIG. 2B includes first to third transistors Q1 to Q3 in the same manner as the precharge/balance device Q in FIG. 1. In the layout of FIG. 2A and FIG. 2B, the first bit line BLT, the second bit line BLN, the equalize signal input portion EQ, and the half power source voltage input portion HVC are drawn as contacts that can be coupled to respective wirings.
In the layout of FIG. 2A, the first, second, and third transistors Q1, Q2, and Q3 are formed over one identical diffusion layer 11. The first, second, and third transistors Q1, Q2, and Q3 have a gate in common, and the gate is coupled to the contact for the equalize signal input portion EQ. The first and second transistors Q1 and Q2 also have the source or the drain in common, and the source or the drain is coupled to the contact for first bit lines BLT. The first and third transistor Q1 and Q3 also have the source or the drain in common and the source or the drain is coupled to the contact for the second bit lines BLN. The second and third transistors Q2 and Q3 also have the source or the drain in common and the source or the drain is coupled to the contact for the half power source voltage input portion HVC. The second and third transistors Q2 and Q3 are arranged such that the directions of the respective gate width are arranged on one extension line. Further, the first transistor Q1 is arranged such that the direction of the gate width is different from the direction of the gate width of the second or third transistor Q2 or Q3.
In the layout of FIG. 2B, the layout of FIG. 2A is rotated by 90° and, further, the position of the contact for the equalize signal input portion EQ is changed to the top of the gate protrusion portion of the first transistor Q1. Either the layout of FIG. 2A or FIG. 2B has been generally used so far.
In connection with the above technique, Japanese Patent No. 3787500 contains disclosure regarding a write/read circuit. The write/read circuit evaluates at least one of bit lines (BL, BBL) in a DRAM memory. The write/read circuit includes at least two transistor pairs (T1/T2, T4/T5) and two transistors (T3/T6) for evaluation. The two transistor pairs (T1/T2, T4/T5) for evaluation have transistors of an identical channel type respectively. The two transistors (T3/T6) apply voltages (VDD; GND) to the transistor pairs (T1/T2, T4/T5). The transistors used in the transistor pairs (T1/T2, T4/T5) are vertical MOS transistors (T1, T2, T4, and T5). The vertical MOS transistors (T1, T2, T4, and T4) in each of the transistors pairs (T1/T2, T4/T5) and the transistors (T3, T6) used for applying the voltage (VDD; GND) have respective common source/drain regions (59, 63).
Further, Japanese Unexamined Patent Publication No. 2004-87074 discloses a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a sense amplifier, a first precharge MOSFET, a selection switch MOSFET, a second precharge MOSFET, and a dynamic memory cell. The sense amplifier includes a CMOS latch circuit for amplifying and holding a pair of input/output node signals corresponding to an operation timing signal. The first precharge MOSFET includes a pair of transistors disposed to input/output nodes, put to an on-state in a precharge period, and supplying a precharge voltage to respective complementary bit line pairs of the input/output nodes. The selection switch MOSFET couples the input/output node and the complementary bit line pair corresponding to a selection signal. The second precharge MOSFET is disposed between the pair of complementary bit lines for short circuiting the same. The dynamic memory cell is disposed between one of the pair of complementary bit lines and a word line crossing the same and includes an address selection MOSFET and a memory capacitor. The semiconductor integrated circuit device has a feature of including a memory circuit in which the gate insulation film of the second precharge MOSFET is formed to a smaller thickness than that of the gate insulation film of the selection MOSFET.
Further, Japanese Unexamined Patent Publication No. 2005-340367 discloses a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a sense amplifier, precharge MOSFETs including paired transistors, a selection switch MOSFET, a first equalize MOSFET, and a dynamic memory cell. The sense amplifier includes a CMOS latch circuits for amplifying and holding signals of a pair of input/output node signals corresponding to an operation timing signal. The paired precharge MOSFET are disposed to the pair of input/output nodes, put to an on state during a precharge period and supplies a precharge voltage to each of the input/output nodes. The selection switch MOSFET couples the pair of input/output nodes and the complementary bit line pair corresponding to a selection signal. The first equalize MOSFET is disposed between the pair of complementary bit lines for short circuiting the same during a precharge period. The dynamic memory cell is disposed between one of the pair of complementary bit lines and a word line crossing the same, and includes an address selection MOSFET and a memory capacitor. The gate insulation film of the selection switch MOSFET and the first equalize MOSFET is formed with a gate insulation film of a first thickness. The gate insulation film of the precharge MOSFET is formed with a gate insulation film of a second thickness which is smaller than the first thickness. A precharge signal corresponding to a power source voltage is supplied to the precharge MOSFET. The first equalize MOSFET and the selection switch MOSFET include a memory circuit which is supplied with an equalize signal corresponding to an elevated voltage defined to higher than the power source voltage and a selection signal.


A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching of mask data on a rising edge of CAS so that new mask data can be entered in Page Mode.

1. Field of the Invention
This invention relates to circuitry for controlling semiconductor devices. More specifically it relates to memory addressing systems for semiconductor memory arrays. It is particularly directed to providing address read/write enablement for semiconductors. The address enablement is used in addressing different semiconductor memory chips in a memory array which is connected to a computer CPU (central processing unit) through a multi-line bus.
2. Description of the Related Art
This invention is intended for use in controlling semiconductor devices, where each semiconductor device has an array of addressable circuits thereon. Such arrays are found on memory circuits, typical memory circuits being dynamic random access memories (DRAMs).
The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". The invention refers to a method of controlling addressed devices, and is not restricted to implementations which involve memory devices or semiconductor devices.
Computer systems, whether general purpose, desktop, work stations, or imbedded controllers (e.g., small computers used to control tools, instruments, or appliances), all include some form of read/write memory. At the present time, the most popular form of read/write memory is the semiconductor DRAM (or Dynamic Random Access Memory) The DRAM is so popular because it offers the best available combination of performance, density, and price; but it does have some disadvantages. Since its memory is based on the storage of an electrical charge on a small capacitor, the charge on the capacitor must be periodically renewed to prevent it from "forgetting" (this process of renewing the charge is called refresh). Internally, the memory cells are organized into a rectangular array where each cell is addressed as being in a particular row, and at a particular column location within the row.
The most common DRAMs minimize the package size by using the same input pins to select the row and the column, i.e., multiplexing the addresses. To read (or write) to a particular cell, the row address is presented on the address pins and a control signal (called RAS) is taken low; then the column address is presented on the same address pins and while RAS is kept low, another control signal (called CAS) is taken low. When RAS first goes low, sensing circuits within the memory device measure the charge on the capacitors for every cell that is a part of the specified row. When CAS goes low, the resulting data from the cells within that row as specified by the column address is transferred to the output pin(s). The time from RAS going low until data is available at the output (for a read operation) is called the "row access time" and is typically 100-120 ns. The time from CAS going low until data is available is approximately half of the row access time and is called the "column access time" (some DRAM manufacturers measure column access time from the time the column address is put onto the address pins instead of when CAS goes low).
The maximum operating speed of a computer device depends on two things: how fast the processor can execute instructions, and how long it has to wait for instructions or data. The maximum operating rate will occur when the read/write memory is sufficiently fast so that the processor never has to wait for instructions or data. This is referred to as "operating with zero wait states". Since many of the most common processors require memory accesses of under 100 ns (commonly 50-60 ns), using a DRAM memory with full RAS/CAS cycles would require slowing down the processor by adding "wait states". To operate without wait states either requires a faster read/write memory device or some means must be found to speed up the DRAM memory. One memory device that can be used is the SRAM (Static Random Access Memory), which has access times as quick as one-tenth that of a DRAM. However, that faster access time comes at the expense of a more complex device which means that it costs more and is less dense than the DRAM.
Several different modifications to the DRAM have been devised to reduce the access time. The most common modification for general read/write applications is the "page mode". In the page mode, once RAS has been taken low (which effectively remembers the row address), any cell on that row (referred to as that "page") can be accessed by presenting its column address and taking CAS low. If RAS is kept low, CAS can be taken high, another column address presented and CAS taken low again to access another cell within the page. This process of presenting a new column address and taking CAS low can be repeated several times; and in each case the access time from the new column address to data is now the column access time instead of the longer row access time and is typically less than 60 ns.
The logic required to use the DRAM parts in this manner is fairly complex. There is a limit to how long RAS can be held low without taking it back high. Also, DRAMs need to be refreshed at regular intervals, so the page mode may need to be interrupted to perform a refresh cycle. For the second, and following page mode cycles, it is necessary to compare the current row address with the previous address to determine if it is the same; if not, then a penalty is imposed because RAS has to be taken high for a specified period of time (about 100 ns) before the new row address can be input. After RAS goes back low, then the column address can be presented and CAS taken low just as previously described for a normal access. That means that if the new request is in a different row, that access will actually be slower than for a standard DRAM access. Therefore, an optimal controller for page mode operation of main DRAM memory would include some means of automatically switching between page mode and non-page mode of DRAM operation depending on some prediction of whether the next access will be on the same page or on another page.
A DRAM controller can operate DRAMs in a page mode of operation by holding RAS low. As mentioned, this reduces access time for successive memory accesses, but only if those accesses are, in fact, addressed on the same page of the DRAM. If the access time in normal mode is 120 ns, then page mode access time would be in the range of approximately 50 or 60 ns. If the address turns out to be on a different page, then RAS must be sequenced, followed by CAS, which is now delayed. Consequently, a "miss", where a sequential memory address is not in the same row, results in increased access time, which would be, for example, in the range of 220 ns. For this reason, it is advantageous for a page mode controller to be "clairvoyant" in predicting when sequential addresses will be on the same page of a DRAM.
Computers have been designed with architectures which permit a central processor to respond to an initial set of instructions, called BIOS, followed by Instructions from an operating program (operating system software), followed by further programming information embodied by the particular program being run. Various forms of memory are addressed through this architecture.
Most computers divide their memory into blocks. Thus, an initial block, such as 512 bytes, can have one set of control parameters, and further blocks can have different control parameters. Typically, an initial block, such as the above mentioned 512 bytes, will have faster response times. This initial block is sometimes SRAM, with the remaining memory being DRAM.
Blocks of memory are often divided into byte multiples of chip sizes. For example, 4 Meg chips are grouped together in groups of 9 to provide 4 megabytes of 9 bit bytes.
Parity bits are commonly used with some computer protocols, and are found on most DOS compatible computers. The parity bit is added to 8 bit bytes as a ninth bit. The byte is able to contain 8 bits of program data, but, with the parity bit, requires 9 bits of memory per byte. 16 and 32 bit computer memory in a similarly structured system therefore require 18 and 36 bits, respectively. A computer could also be configured to use one parity per 16 and 32 bits of computer memory, so that such a 16 or 32 bit system would require 17 and 33 bits, respectively.
Smaller blocks of memory often use "by-four" chips, such as 1 Meg "by-four" chips. These are 4 Meg chips which are configured to behave as four 1 Meg chips. Odd bits (such as ninth parity bits) use a "by-one" 1 Meg chip, which is an ordinary 1 Meg chip configured to behave as a single 1 Meg chip. Thus, two generations of chips are blocked together.
For example, in one configuration, four 64K "by-four" chips are grouped together, along with two 64K "by-one" chips. The 64K "by-four" chips are essentially 256K chips, so that four of these are grouped with the two 64K chips. This gives a number of nine bit bytes of memory equal to twice the bit size of one of the sectors, or 128K, because there are eighteen sectors in that configuration.
In one configuration, shown in FIG. 4, eight "by-four" chips 41 are grouped together on a memory module, along with four "by-one" chips 43. The module may then be addressed as four 9 bit bytes, two 18 bit words, or one 36 bit word. The four parity bits are each used to check parity in each of the eight bit bytes. Of course, the total memory on the module is equal to the total number of bits divided by the number of bits per byte.
Certain chip configurations, such as a 256K.times.36 module, are organized into multiple blocks of memory. It is desired to implement parity memory, but byte addressability with parity becomes difficult where multiple parity bits are to be simultaneously addressed from the same chip.
In order to implement parity memory on a 256K.times.36 module, a processor should be able to only change some combination of blocks within the 36 bit word. This feature is called "byte addressability".
In order to provide "byte addressability" with parity, it is necessary to use two 256K.times.4 DRAMs and one 256K.times.1 DRAM to make up each of the 9 bit wide blocks. So the complete module tales eight 256K.times.4's and four 256K.times.1's. There are many disadvantages to using "mixed densities" of DRAMs to build this module. Some of these are: the speed differences, the module's requirement of continued availability of older DRAMs, and the profuse number of parts.
The parity bits were not all put into one 256K.times.4 part because there must be individual write control on each of the four bits. Individual write control on each of the four bits is not possible when all four bits reside inside one "normal" DRAM.
In normal Mask Write cycles, the mask data is latched on the falling edge of RAS and cannot be changed in a Page Mode cycle. It would be desirable to have a method of latching mask data on the rising edge of CAS so that new mask data can be entered in Page Mode.
Standardized operating programs, such as MS DOS or OS 2 (trademarks of Microsoft Corporation), permit computers from different manufacturers to behave similarly, a fact that is not lost to software developers who design their programs to operate from the operating system ("DOS") instead of directly from the computer's BIOS. These circumstances provide what is often referred to as DOS compatible computers. These are colloquially referred to as IBM compatible computers, even though specific architectures of the computers differ.
Most DOS compatible computers use the same set of bus addresses for addressing similar memory locations. This enables software developers to write programs which function on different computers.
While DOS compatible computers have used eight bit bytes (nine with parity), never generations of computers are using more bits per bytes, such as 32 bits (36 with parity). The never generations of computers often must accept parity in memory for the larger (32 bit) bytes and for each of the smaller (eight bit) bytes if the computer is to be able to divide memory into the smaller bytes.
A video RAM (VRAM), sometimes called dual-port RAN, is a DRAM (dynamic random access memory) with a serial access memory. The serial access memory permits a block of stored data to be rapidly accessed, while the normal access function of the DRAM is also occurring. The information in the serial access memory is normally obtained from, or input into, a primary memory on the VRAM. The primary memory is configured as a DRAM and is accessed according to DRAM protocols.
It is further desired to enhance the address ability of VRAM devices in order to facilitate computer access to the VRAM with a reduced number of address lines.
A common feature that has recently been added to the x4 and x8 organizations of both DRAMs and VRAMs is the Mask Write (or write-per-bit) function. For many common operations, especially in the area of graphics, a CPU needs to change some subset of the bits within a 4 or 8 (or 16 or 32 . . . ) bit word.
It is possible to use a Mask Write function by using separate CAS lines. This would permit one to build memory modules for a computer, such as an IBM (TM) PS/2 that uses only nine x4 DRAMs and takes advantage of some signals on a 72 pin bus to do a Mask Write to a DRAM selected to be a parity DRAM.
This arrangement has the advantage of implementing the parity bits on a single chip rather than mixing the DRAM densities. This requires a separate CAS line for each of the four DQ planes, for the parity information. One would simply drop CAS for the parity bits one wishes to change and leave CAS high for the bits which are not accessed. The advantages to this method are (1) that it works for Page Mode, and (2) makes the decode logic simple. The disadvantage is that it requires a "custom" DRAM with three more pins on it.
Before the Mask Write function was developed, it was necessary for the processor to do a Read-Modify-Write cycle to change individual bits in a x4 or x8 DRAM. The processor must first read all four or eight of the bits from that address location (since it does not know what is stored there) then Modify the bits it wanted to change, and then Write the information back into the memory location.
The Mask Write function speeds up this operation by providing a way to "mask off" the bits that processor does not want to change. The mask data acts as an individual input enable for each of the DQ pins.
In normal Mask Write (also called write-per-bit) cycles the mask data is latched on the falling edge of RAS and cannot be changed in a Page Mode cycle. This invention is a method of latching mask data on the rising edge of CAS so new mask data can be entered in Page Mode.
In the prior art, mask data has always been latched at the falling edge of RAS. This means that the system must exit the Page Mode access cycle in order to enter new mask data, showing the system timing. By latching mask data at the rising edge of CAS, new mask data can be entered without having to exit Page Mode.

Mask write enablement for memory devices which permits selective masked enablement of plural segments


An apparatus and method for delivering electrical shock therapy in order to treat atrial tachyarrhythmias such as atrial fibrillation is presented. The ventricular rhythm of certain patients during an episode of atrial fibrillation may be such that shockable R—R intervals are infrequent or do not occur at all. Continuous electrical stimulation of the atria after detection of an atrial tachyarrhythmia may be utilized to modify the ventricular rhythm in such patients to increase the frequency of shockable R—R intervals.

Tachyarrhythmias are abnormal heart rhythms characterized by a rapid heart rate, typically expressed in units of beats per minute (bpm). They can occur in either chamber of the heart (i.e., ventricles or atria) or both. Examples of tachyarrhythmias include ventricular tachycardia, ventricular fibrillation, atrial tachycardia, and atrial fibrillation. Tachycardia is characterized by a rapid rate, either due to an ectopic excitatory focus or abnormal excitation by normal pacemaker tissue. Fibrillation occurs when the chamber depolarizes in a chaotic fashion with abnormal depolarization waveforms as reflected by an EKG.
An electrical shock applied to a heart chamber (i.e., defibrillation or cardioversion) can be used to terminate most tachyarrhythmias by depolarizing excitable myocardium, which thereby prolongs refractoriness, interrupts reentrant circuits, and discharges excitatory foci. Cardioversion refers to a shock delivered synchronously with a ventricular beat, while defibrillation refers to an asynchronously delivered shock. Implantable cardioverter/defibrillators (ICDs) provide this kind of therapy by delivering a shock pulse to the heart when fibrillation is detected by the device. An ICD is an electronic device containing a pulse generator that is usually implanted into the chest or abdominal wall. Electrodes connected by leads to the ICD are placed on the heart, or passed transvenously into the heart, to sense cardiac activity and to conduct the shock pulses from the pulse generator. ICDs can be designed to treat either atrial or ventricular tachyarrhythmias, or both, and may also incorporate cardiac pacing functionality.
The most dangerous tachyarrhythmias are ventricular tachycardia and ventricular fibrillation, and ICDs have most commonly been applied in the treatment of those conditions. Ventricular fibrillation is treated by the immediate delivery of a defibrillation shock, while ventricular tachycardia can be treated with either a defibrillation or a cardioversion shock. ICDs are also capable, however, of detecting atrial tachyarrhythmias, such as atrial fibrillation and atrial flutter, and delivering a shock pulse to the atria in order to terminate the arrhythmia. Although not immediately life-threatening, it is important to treat atrial fibrillation for several reasons. First, atrial fibrillation is associated with a loss of atrio-ventricular synchrony which can be hemodynamically compromising and cause such symptoms as dyspnea, fatigue, vertigo, and angina. Atrial fibrillation can also predispose to strokes resulting from emboli forming in the left atrium. Although drug therapy and/or in-hospital cardioversion are acceptable treatment modalities for atrial fibrillation, ICDs configured to treat atrial fibrillation offer a number of advantages to certain patients, including convenience and greater efficacy.
As aforesaid, an ICD terminates atrial fibrillation by delivering a shock pulse to electrodes disposed in or near the atria. The resulting depolarization also spreads to the ventricles, however, and there is a risk that such an atrial shock pulse can actually induce ventricular fibrillation, a condition much worse than atrial fibrillation. To lessen this risk, the ICD delivers a cardioversion shock synchronously with a sensed ventricular depolarization (i.e., an R wave) and delays delivering the shock until the intrinsic ventricular rhythm is below a specified maximum rate. That is, an R—R interval, which is the time between a presently sensed R wave and the preceding R wave, is measured. If the R—R interval is above a specified minimum value, the interval is considered shockable and the atrial cardioversion shock pulse is delivered.
If the ventricular rhythm does not slow to a safe rate in a short time, however, the delay in delivering atrial cardioversion therapy may be deleterious to the patient. In addition, a particular subset of patients have spontaneous ventricular rhythms during atrial tachyarrhythmias that may remain too rapid to ever safely deliver an atrial cardioversion shock, and these patients may not be suitable candidates for ICD therapy. What is needed in the art is a system which addresses these and other problems.

Method and apparatus for atrial tachyarrhythmia cardioversion


Convertible fiber optic panel/module assemblies for optical fiber connectivity, including for wall and floor-mounted connectivity applications are disclosed. The convertible fiber optic assemblies are configured to be convertible between a fiber optic panel assembly and a fiber optic module assembly, as desired. According to an exemplary embodiment, the convertible fiber optic panel/module assembly comprises a fiber optic panel to provide a fiber optic panel assembly. One or more fiber optic adapters are disposed through the fiber optic panel to provide fiber optic connectivity. If it is desired to convert the fiber optic panel assembly to a fiber optic module assembly, the fiber optic panel assembly is additionally fitted with a module housing having at least one rear fiber optic adapter disposed therein and a fiber optic cable harness connecting the at least one rear fiber optic adapter to the fiber optic adapters disposed in the fiber optic panel.

Benefits of optical fiber include extremely wide bandwidth and low noise operation. Because of these advantages, optical fiber is increasingly being used for a variety of applications, including but not limited to broadband voice, video, and data transmission. Fiber optic networks employing optical fiber are being developed and used to deliver voice, video, and data transmissions to subscribers over both private and public networks. These fiber optic networks often include separated connection points linking optical fibers to provide "live fiber" from one connection point to another connection point. In this regard, fiber optic equipment is located in data distribution centers or central offices to support interconnections.
Fiber optic cables can also be extended from the fiber optic equipment to end point devices to provide fiber optic network connectivity to the end point devices. For example, an end point device may be a network card in an office computer in an office environment. In this regard, wall- and/or floor-mounted fiber optic junction boxes may be provided in a building to house a fiber optic panel to provide connectivity points between a fiber optic cable run through the interior walls or floors of a building and end point devices in the building. FIG. 1 illustrates an example of a floor-mounted junction box 10 that includes a cavity 12 for disposing a floor-mounted fiber optic panel 14 in a floor. For example, the fiber optic panel 14 illustrated in FIG. 1 contains six (6) duplex LC fiber optic adapters 16(1) -16(6) extending through a panel 18. Thus in this example, six (6) duplex connectorized legs of a fiber optic cable (not shown) can be brought into a rear side of the floor-mounted junction box 10 and connected to the backside of the duplex LC fiber optic adapters 16(1)-16(6) in the floor-mounted fiber optic panel 14. Last run fiber optic jumper cables (not shown) can be connected to the front side of the duplex LC fiber optic adapters 16(1)-16(6) extending out from the fiber optic panel 14 and to end point devices to provide optical fiber connectivity between the end point devices and the fiber optic cable. Thus, in this example, the six (6) duplex LC fiber optic adapters 16(1)-16(6) can support duplex fiber optic connectivity to up to six (6) end point devices.
Thus in summary, the paths or conduits in the interior walls and/or floors of a building to support runs of the fiber optic cable have to be large enough in diameter to support break out of multiple legs each having end fiber optic connectors. Larger diameter pull paths can be more difficult to install. It would be advantageous if fiber optic connectivity could be provided to the end point devices in a manner that would reduce or minimize the pulling path size of the fiber optic cable and provide for the desired fiber optic connectivity to end point devices.
No admission is made that any reference cited herein constitutes prior art. Applicant expressly reserves the right to challenge the accuracy and pertinency of any cited documents.


A method and computer readable medium for generating a graph which displays amounts of access to computer files, such as URL""s on the world wide web, over a period of time. Time is mapped along a central axis, and a plurality of file identifiers is mapped radially about the radial axis as lines having varying distances from the radial axis. The lines may be arranged at angles of rotation about the radial axis and are colored to represent the lexicographical similarity of the nodes. Alpha bending is utilized to reveal lines having an angle of rotations near 0 degrees that would otherwise be concealed by neighboring lines. In an alternative embodiment, a two dimensional graph displays instantaneous access information for a plurality of file identifiers, where angular rotation and color may also be used to represent the grouping of the nodes, and distances of radial lines from an origin represent access values to respective files. The present invention may be used to represent traffic patterns across nodes in a network, database queries, or any other application where visualization of numerical values associated with discrete entities is desired.

1. Field of the Invention
The present invention relates generally to analyzing computer network activity. More particularly, the present invention relates to visualizing traffic patterns over a computer network that correlates related documents and their associated usage data.
2. Background of the Invention
A global computer network exists as a collection of smaller networks interconnected to allow them to function as a single virtual network. One such global computer network is the World Wide Web (xe2x80x9cthe Webxe2x80x9d). Users of the Web access nodes or websites stored on connected servers all over the world. A website is a file stored at a physical location on a server that contains content an entity wishes to share with the rest of the users on the Web. The popularity of the Web has made websites effective marketing tools through which businesses may advertise products and services, news services provide news on a broad range of topics, and libraries provide online volumes of all types of information.
Web browsers allow individual users to search the Web for a particular topic, and return the websites address conforming to a universal resource language (URL), which allows the user to immediately access desired website. Large websites will often maintain enormous numbers of files with large storage and processing requirements. Commercial Web servers maintain many websites. Because Web traffic patterns shift dramatically based on the time of day, the day of the week, and sporadic events, it is important to be able to monitor the traffic patterns so that resources such as bandwidth and storage space may be allocated accordingly.
For example, objective information such as which websites are being accessed, how often they have been accessed, and which files are being downloaded is very valuable information both to the entity responsible for the content on the website as well as the entity managing the server which hosts the website. Based on web traffic information, an individual site may be edited for content based on usage, with more emphasis placed on areas that receive high traffic, and areas that are rarely visited may be removed. For marketing purposes, a company that posts product information on a website may use traffic information to gauge the popularity or potential success of a new product or service.
Conventional attempts to quantify Web traffic have focused on the use of log files, which list websites and numbers of hits or accesses. However, for a large number of websites, or for a large number of files within a given website, it is difficult to convey traffic information effectively. One visualization method, described as Interactive Visualization of Serial Periodic Data, and published in the Proceedings of the ACM Symposium on User Interface Software and Technology, November, 1998, describes a method of displaying data that is serial along a spiral axis and periodic along the radii from the axis. However, this visualization technique does not avoid the extreme aspect ratio of plotting a large number of URLs, such that widely varying values are difficult to visualize. It also conceals information within the image.
Thus, there is a need for a method and apparatus to visualize computer network traffic in a manner that is meaningful to a viewer.
The present invention allows the generation of a three-dimensional chart having a radial layout which displays network traffic across selected nodes on a network over a period of time. Graph 100 may be shown in a window displayed as a three-dimensional window 101. Graph 100 shows 30 days of Web traffic from approximately 5000 URLs that are sorted lexicographically. Time is mapped along the x-axis 102. The URLs are mapped radially about the axis 102. As shown, the mapping is only displayed across an angle span of 180 degrees because in the preferred embodiment there is no relationship between the first and last URL. However, larger angle spans may be used. Usage or access to computer files corresponding to the individual URLs is mapped to the distance from axis 102.
In one aspect, the present invention provides a method for visualizing relationships between files stored on a computer network and usage data associated with the files, the method comprising the steps of: (a) obtaining information containing at least one identifier identifying a node in a network and the number of user accesses to the node over a period of time; and (b) creating a graph wherein the information is displayed in a three dimensional line chart with a radial layout, where a first distance between a line and a radial axis represents number of accesses to the node, time is mapped to the radial axis, and nodes having similar identifiers are represented by lines having similar angles of rotation about the radial axis.
In another aspect, the present invention provides a computer readable medium for use with computer apparatus, the medium including computer instructions which, when executed by the computer apparatus: (a) obtain information containing at least one node identifier identifying a node and a number of user accesses to the node over a period of time; and (b) create a graph wherein the information is displayed in a three dimensional line chart with a radial layout, where a first distance between a line and a radial axis represents number of accesses to the node, time is mapped to the radial axis, and nodes having similar identifiers are represented by lines having similar angles of rotation about the radial axis.
In another aspect, the present invention provides a method for visualizing relationships between nodes stored on a computer network and usage data associated with the nodes, the method comprising the steps of: (a) obtaining information containing at least one node identifier identifying a node and the number of user accesses to the node at a specified time; and (b) creating a graph wherein the information is displayed in a two dimensional line chart having a radial layout about a point in a single dimension, where a line having an angle of rotation about the point and extending from the point represents number of accesses to the node, and nodes having similar identifiers are represented by lines having similar angles of rotation about the point.

Bristlelines: a visualization for discovery relationships between sorted web documents and their usage data


A system is disclosed for eliminating cell loss through the use of flow control of both allocated and dynamic bandwidth. When output buffers in the switch become filled to a predetermined threshold level a feedback message is provided to input buffers to prevent transmission of cells from the input buffers to the output buffers. In order to provide connection and traffic type isolation the buffers are grouped into queues and flow control may be implemented on a per queue basis. The feedback message is a digital signal including an ACCEPT/REJECT message and a NO-OP/XOFF message. An XOFF message can be received while transmitting via allocated bandwidth or dynamic bandwidth. In particular, an XOFF (allocated) message may be received with regard to allocated bandwidth and an XOFF (dynamic) message may be received with regard to dynamic bandwidth. When ACCEPT is received by the requesting input queue the cell is transferred to the output queue. When REJECT is received by the requesting queue the cell is not transferred. When XOFF (dynamic) is received by the requesting input queue further requests to transfer to that output queue by the requesting input queue using dynamic bandwidth are halted until receipt of an XON message from that output queue. When XOFF (allocated) is received by the requesting input queue further requests to transfer to that output queue by the requesting input queue using allocated bandwidth are halted until receipt of an XON message from that output queue.

Networks such as asynchronous transfer mode ("ATM") networks are used for transfer of audio, video and other data. ATM networks deliver data by routing data units such as ATM cells from source to destination through switches. Switches include input/output ("I/O") ports through which ATM cells are received and transmitted. The appropriate output port for transmission of the cell is determined based on the cell header.
One problem associated with ATM networks is loss of cells. Cells are buffered within each switch before being routed and transmitted from the switch. More particularly, switches typically have buffers at either the inputs or outputs of the switch for temporarily storing cells prior to transmission. As network traffic increases, there is an increasing possibility that buffer space may be inadequate and data lost. If the buffer size is insufficient, cells are lost. Cell loss causes undesirable interruptions in audio and video data transmissions, and may cause more serious damage to other types of data transmissions. Avoidance of cell loss is therefore desirable.

Allocated and dynamic switch flow control