The invention is a luminescence energy transfer based bioaffinity assay comprising a first group labeled with an energy donating compound (donor) and a second group labeled with an energy accepting compound (acceptor), wherein the donor is a luminescent lanthanide chelate having a long excited state lifetime and the acceptor is either a luminescent compound having a short excited state lifetime or a nonluminescent compound. The increase or decrease, respectively, in the energy transfer from the donor to the acceptor resulting from shortening or lengthening, respectively, of the distance between the said groups, is measured. Characteristic for the invention is that the lanthanide energy emission and the acceptor energy absorption do not essentially or not at all overlap each other.

The publications and other materials are used herein to illuminate the background of the invention, and in particular, cases to provide additional details respecting the practice, are incorporated by reference.
A great variety of assays based on bioaffinity or enzymatically catalyzed reactions have been developed in order to analyze biologically important compounds from various biological samples (such as serum, blood, plasma, saliva, urine, feces, seminal plasma, sweat, liquor, amniotic fluid, tissue homogenate, ascites, etc.), samples in environmental studies (natural, raw and waste water, soil samples) industrial processes (process solutions, products and side products) and compound libraries (screening libraries which may comprise organic compounds, inorganic compounds, natural products, extracts of biological sources, biological proteins, peptides, or nucleotides, and so on). These association assays rely on specific bioaffinity recognition reactions, in which natural biological binding components form the specific binding assay (using biological binding components such as antibodies, natural hormone binding proteins, lectins, enzymes, receptors, DNA, RNA or peptide nucleic acids (PNA)) or artificially produced binding compounds like genetically or chemically engineered antibodies, molded plastic imprint (molecular imprinting) and so on. Such assays generally rely on a label to quantitate the formed complexes after recognition and binding reactions and suitable separation. To achieve efficient separation of bound reagents from unbound components separations such as precipitation and centrifugation, filtration, affinity collection (to e.g. plastic surfaces of tubes, slides or microbeads), solvent extraction, gel filtration or other chromatographic systems are used. The quantitation of the label in free or bound fraction enables the calculation of the analyte in the sample directly or indirectly, generally through use of a set of standards to which unknown samples are compared.
Dissociation assays are assays where, for example specific enzymes catalyze a biological reaction such as hydrolyzing a substrate, transferring a functional group, adding or cleaving a substituent and so on. On the contrary to binding assays some of those assays follow the hydrolysis of a labeled product, e.g. enzyme substrate. According to assay design, a wide variety of different labeling technologies are applied. These assays can utilize a simple labeled substrate, which facilitates the measurement of either substrate or end product, or it may be defined in a way to give direct information of hydrolysis (e.g. internal quenching or energy transfer).
The separation and washing needed in most of these assays make them labor intensive, slow and difficult to automate. Furthermore end point measurement does not allow gathering of kinetic information (e.g. association/dissociation rates). In cases of low affinity bindings, the affinity may be so low that no physical separation can be applied without destroying the binding (e.g. low affinity receptors). Particularly in areas, like screenings (e.g. high throughput screening) there is a constant demand for simpler assays, simplified protocols, which would make automation easier and increase the throughput.
This can be accomplished with homogeneous or nonseparation assays. Homogeneous biomedical assays are defined as assays taking place in one homogeneous phase. It means that no separate phases (such as solid phase catching reagents), and no separation is used prior to measurement. This requires a signal production system that responds to the binding in a way making its direct monitoring possible. Systems known to prior art are e.g. fluorescence polarization assays applied for small molecular compounds, enzyme-monitored immunoassays (Syva Co.), various fluorescence quenching or enhancing assays (for an review see e.g. Hemmila, Applications of Fluorescence in Immunoassays, Wiley, N.Y., 1991). Another category of simplified assay technologies is the nonseparation assays, which, similarly to homogenous assays, avoid separation and washing steps. A good example of such a technology is the scintillation proximity principle marketed by Amersham, which is based on short distance penetration of radiation particles in assay medium and a solid scintillator coated with catching reagents (Udenfriend et al, (1985) Proc Natl Acad Sci, 82, 8672 and Anal Biochem, (1987) 161, 494).
Regardless of a great number of homogeneous assay designs published to day, there are no assays, where the versatility and sensitivity would match those of a good separation assay. The reason to that is manifold relating to e.g. the different way a homogeneous, versus heterogeneous, assay has to be optimized, the control of low affinity nonspecific bindings, and the limitations of applicability of most of the existing homogenous assay techniques. In addition, the conventional homogeneous fluorometric assays are very vulnerable to background interferences derived from various components in the samples. Fluorescence polarizations assays are interfered by low affinity nonspecific bindings (e.g. probe binding to albumin) and autofluorescence of samples.
Energy transfer is a widely used technology to measure and monitor biological reactions. Fluorescence resonance energy transfer (FRET) has been applied e.g. as a spectroscopic ruler in structural studies to measure distances within a macromolecule (Stryer and Haugland (1967) Proc Natl Acad Sci. USA, 58; 719). In addition to resonance energy, transfer, there are other energy transfer reactions, like simple radiative energy transfer (where acceptor absorbs the light emitted by donor), collisional energy transfer, exchange mechanism (Dexter (1953) J Chem Physics, 21, 836), exciton migration (in crystals) and long range electron transfer (Matko et al. 1995, Cytometry 19, 191). In addition, donor emission can be quenched by numerous ways with a number of unrelated compounds having a deactivating effect on some of the donor's energy levels.

Homogeneous luminescence assay method based on energy transfer


A flight planning system for providing a flight planning tool on a client device includes a flight planning module, a weather module, and an airport module. A flight planning API is configured to communicate with the modules and client device, and receive, via client device hardware, a request for information associated with a selection of one of a plurality of tools corresponding to one of the modules. Accessing the flight planning system includes identifying a user and authorizing access to the flight planning system. The flight planning module is configured to: retrieve, based on the tool selection, information responsive to the request from at least one of a third-party device or another of the plurality of modules; generate an aviation flight plan based on the information responsive to the request; and transmit the flight plan to the client device for display via the client device.

Modern flight planning has continued to evolve from early individual web-based applications that separately supplied a general aviation pilot with flight information, such as weather, aircraft performance information, airport directories, and fundamental route planning to more all-in-one-solutions. For example, mobile, in-cockpit Electronic Flight Bags (EFBs) provide some information relevant to a flight, such as real-time weather and traffic information via wireless access to remote devices. But while current systems like EFBs may provide mobile access to some available information, there is a need for a single, customized source for all critical and pertinent information necessary for a pilot to plan and execute a flight, as well as to integrate the information across other available platforms. Further, there is a need for information to be readily available to a pilot before, during, and after an aviation flight.
In addition, the prevalence of devices that use mobile applications (e.g., smartphones, tablets, etc.) provides an avenue for a comprehensive flight planning tool to be provided in manner that allows the information to be readily accessible to a user, even in an on-the-go situation. Thus, there is a need for a mobile application that provides the above advantages.

Comprehensive flight planning tool for a mobile device


A camera lens holder configured to hold a camera lens when the lens is not attached to a camera body. The camera lens holder includes a back plate and an adapter plate associated with the back plate. The back plate and adapter plate may be movably connected with a hinge. The lens holder also includes a lens mount configured to engage with a camera lens associated with the adapter plate. The camera lens holder may include a lens release mechanism to selectively prohibit or allow the removal of a camera lens which has been engaged with the lens mount. Also disclosed is a lens holding system and a method of holding a spare camera lens.

A professional or advanced amateur photographer will typically own and use several camera lenses for each camera body he or she uses. The various camera lenses may have different focal lengths, selected focal ratios or other differing optical characteristics. One of the photographer's various lenses may then be selectively attached to a camera body and used to compose and take a desired film or digital photograph.
Each camera lens will have a lens mount including tabs or other structures that have been machined or formed into the necessary shape or structure to mate with a specific camera body type. The corresponding camera body will have an appropriately machined mounting socket or receptacle configured to receive the camera lens. Typically, the camera lens mounting structure and the corresponding structure associated with the camera body will allow a lens to be quickly inserted into the camera mount and locked into place with a short twist of the lens with respect to the camera body. The camera body or lens will generally include a locking mechanism that engages automatically when the lens is twisted into place, preventing the lens from disengaging accidentally. Thus, when it is desired to remove the lens from the camera body, a button, lever or other release mechanism is activated, allowing the lens to be rotated in the reverse direction and quickly disengaged from the camera body. Camera lens mounting systems as described above are commonly known as camera lens "bayonets" on the lens side and "bayonet mounts" on the camera side.
Only one lens may be attached to the camera body at a given time. Many photographers, including but not limited to wedding photographers, sports photographers, nature photographers, advanced amateur photographers and others will desire to carry multiple lenses with them and quickly but safely interchange lenses as needed to achieve specific photographic goals. Lenses not attached to the camera body are often carried in the padded compartments of a photographer's bag or in special pockets associated with a photographer's vest.
It may be noted that the rear optical elements of a camera lens are relatively protected from dust when the camera lens is attached to a camera body. These rear optical elements, along with the front optical elements, are exposed however if the camera lens is removed from the camera body. Accordingly, a photographer will usually cover the front and rear portions of a camera lens with specially fitted lens caps when a camera lens is removed from the camera body and placed into a vest or bag.
In view of the foregoing, it is readily apparent that some time and effort is necessary for a photographer to safely exchange one camera lens for another in the field. Initially, the first camera lens must be removed from the camera body. Then a dust cap must be found in the photographer's bag and attached to the front and rear surfaces of the first camera lens. Attaching a dust cap is a relatively simple operation; however cap attachment does generally require that the photographer use both hands. Once the dust cap(s) are attached the photographer may secure the first lens in a padded compartment of his photographer's bag. The photographer may then select a replacement lens from his or her bag or vest and remove the dust cap(s) from the second lens. This is also typically a two-handed operation. Once the dust cap(s) have been removed, the photographer may attach the second lens to the camera body.
Although each of the steps associated with exchanging a camera lens stored in a conventional photographer's bag or vest is relatively simple, the process does take two hands and some time and care is necessary to avoid damage to the rear optical surfaces of the respective lenses. It is common for photographers of fast-paced subjects such as wildlife, sports action or weddings to either miss desired photographic opportunities or use a less than ideal lens because of the time and effort necessary to quickly exchange camera lenses.
The embodiments disclosed herein are directed towards overcoming one or more of the problems discussed above.


A combination inductive coil and integrated circuit semiconductor chip is provided in a single lead frame package. The lead frame is preferably made of a copper alloy and has a flat configuration. The chip is electrically connected to end portions of the inductive coil thus permitting the inductive coil to function as an antenna for the chip.

In the past, passive devices such as inductors, capacitors and resistors were combined with active devices such as diodes and transistors on a printed circuit board to manufacture electronic circuits and/or electronic systems.
As the technology developed, active devices of various types such as bipolar and MOS (or unipolar) devices became integrated into a single semiconductor chip. Integration of these active devices and also passive devices such as resistors and capacitors into a single semiconductor chip led to the formation of electrical circuits in a single semiconductor chip which became known as an integrated circuit semiconductor chip.
Packaging of such integrated circuit semiconductor chips became very important. As a result, integrated circuit semiconductor chip manufacturers have sought for ways to inexpensively and reliably package integrated circuit semiconductor chips.
One early packaging technique was to provide hybrid packages which usually incorporated integrated circuit semiconductor chips with passive devices such as capacitors and resistors on a ceramic substrate surface of a ceramic package which would have metal pins to permit the ceramic package to be inserted into via holes in a printed circuit board containing a number of such ceramic packages interconnected to provide either an electronic circuit or electronic system. Ceramic packages were very costly resulting in higher costs for a printed circuit board using multiple ceramic packages.
In an effort to significantly reduce manufacturing costs, lead frame packages were developed to protectively house integrated circuit semiconductor chips. A lead frame package generally comprised a metal lead frame member that would carry an integrated circuit semiconductor chip on a portion thereof. Wirebonding techniques were used to electrically connect terminal portions or pads of the integrated circuit semiconductor chip to fingers of the lead frame structure. Subsequently, the integrated circuit semiconductor chip on the lead frame structure with its wirebond connections thereto was encapsulated with plastic to provide a plastic encapsulated lead frame package. From a manufacturing cost point of view, plastic encapsulated lead frame packages were very inexpensive as compared to, for example, ceramic type packages.
A need existed to develop electronic type products that would be relatively inexpensive to make and that would take advantage of the lead frame manufacturing technology. Specifically, a need existed for improved lead frame type products that could perform functions that were not provided by the available lead frame products.

Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor


A continuous selection graph can be displayed as a graphical user interface, where the continuous selection graph includes a similarity continuum to indicate media content that is progressively similar, and includes an axis of identifying criteria for the media content. The axis of identifying criteria for the media content associates the media content along the similarity continuum, where the axis of identifying criteria is displayed perpendicular to the similarity continuum.

Viewers have an ever-increasing selection of television programming to choose from, and may want to locate programming choices that are of interest to them. In addition to scheduled television program broadcasts, television viewing options also include on-demand choices which enable a viewer to search for and request media content for viewing when convenient rather than at a scheduled broadcast time. Typically, a viewer can initiate a search for a list of television programming choices and on-demand viewing choices in a program guide (also commonly referred to as an electronic program guide or "EPG"). The program descriptions shown in a program guide, however, are displayed in a single dimension and rarely provide enough information for a viewer to decide whether a program or movie will be of interest to them.
In other television programming and/or menu search systems, a viewer may select a genre or program category by which to locate particular types of programs and movies that may be of interest to them. Alternatively, a viewer may designate a particular actor as a basis to locate television programs and/or movies in which the actor appears. However, these types of program category search systems also initiate a search for programs of interest and return viewing options in a single dimension.

This patent is subject to a terminal disclaimer.


An air circuit breaker bell alarm accessory interacts with the circuit breaker contact position indicator to provide local and remote indication of the occurrence of a circuit interruption. A drive pin extending from the bottom of the accessory interacts with a slot on the contact position indicator lever to prevent release of the circuit breaker closing spring until the bell alarm accessory is manually reset.

Air circuit breakers as described within U.S. Pat. No. 3,095,489 entitled "Manual Charging Means for Stored Energy Closing Mechanisms of Electric Circuit Breakers" and U.S. Pat. No. 3,084,238 entitled "Ratchet Mechanism for Charging a Closing Spring in an Electric Circuit Breaker" include operating mechanisms that are mainly exposed to the environment. Since the air circuit breakers are rated to carry several thousand amperes of current continuously, the exposure to convection cooling air assists in keeping the operating components within reasonable temperature limits.
U.S. patent application Ser. No. 08/878,598 entitled "Contact Position Indicator for an Industrial-Rated Circuit Breaker", filed concurrently herewith, describes the use of a target device to indicate the condition of the circuit breaker contacts as well as an interlock arrangement for preventing false indication thereof.
Various accessory devices are used with such air circuit breakers to provide auxiliary function along with overcurrent protection. One such accessory is the bell alarm accessory that provides local and remote indication as to the occurrence of circuit interruption. U.S. Pat. No. 5,502,286 entitled "Bell Alarm and Lock-Out for High Ampere-Rated Circuit Breakers" describes a bell alarm accessory used with so-called "insulated case" circuit breakers wherein the circuit breaker interrupting components are completely enclosed within an insulating plastic enclosure. This patent describes one such bell alarm accessory that interacts with the circuit breaker operating mechanism to activate the bell alarm upon circuit interruption and to prevent the closing of the circuit breaker contacts until the accessory is manually reset.
It would be beneficial to provide a similar bell alarm with air circuit breakers to indicate the occurrence of a circuit interruption and to prevent the closing of the circuit breaker contacts until the accessory is manually reset.
One purpose of the instant invention is to provide a bell alarm accessory that provides local as well as remote indication of such circuit interruption as well as preventing circuit breaker contact closure until and unless the accessory has become manually reset.

Circuit breaker bell alarm accessory with lock-out


The invention provides a packing article where a packing cost and a transportation fee can be kept low and a buffering function is further enhanced. The invention provides a packing article including: a packing box; a lower-side buffering member to provide packing including a concave portion, which is located at the lower side of the packing box, and which locates an item to be packed in the center; an item to be packed, located in the concave portion of the lower-side buffering member to provide packing; and a partition member located on the upper side of the item to be packed and a storing member, which is located between the partition member and the upper surface of the packing box, and which stores an attached part and/or an instruction manual. The partition member includes an outside partition member, including an upper surface member and an outside skirt portion connected to the upper surface member, and an inside partition member, including a lower surface member and an inside skirt portion connected to the lower surface member.

1. Field of Invention
The present invention relates to a packing article where an item to be packed, such as an electronic device, is packed in a packing box, a method of packing an item to be packed, such as an electronic device, in a packing box, and a partition member which is preferably used for the above packing article.
2. Description of Related Art
In the related art, an electronic device or a precise instrument, such as a computer, a printer and/or a projector, can be stored in a packing box with a pair of upper and lower buffering members of packing, which is made of foaming plastic or pulp mold material. The related art also includes a packing article or a method of packing where a buffer member to provide packing, which is made of relatively expensive bubble resin material, is only used for buffering on a lower side and a tray for attached parts, and a box to store attached parts of a product is used to provide buffering on the upper side. This approach can reduce packing cost since the numbers of buffer members to provide packing is reduced to be half other techniques, and can reduce shipping cost since the size of a packing article is small.
FIG. 11 to FIG. 16 show a related art packing article and a method of packing. FIG. 11 is a cross-sectional view of a related art packing article where a box for attached parts is used for a buffer member on the upper side. As shown in FIG. 11, a related art packing article 700 includes a packing box 10, a lower pad 20 located on the bottom of a packing box 10, a lower-side buffering member to provide packing 30 having a concave portion in the center located on the upper surface of the lower pad 20, an item to be packed P located in the concave portion of the lower-side buffering member for packing 30, a box for attached parts 50 made of a corrugated cardboard and located on the upper side of the item to be packed P.
In a packing box 10, a handling opening 10C, to enhance gripping with a user's hand at the time of carrying the packing box, and a throwing opening 10D to enable passage therethrough of an additional part P2 or an additional instruction manual M2 therein in a shipped area (such as a foreign country), are installed.
FIG. 12 is a schematic that shows a packing method of the related art packing article shown in FIG. 11. The related art packing article 700 is packed as follows. Firstly, the lower pad 20 is located on the lower surface of the packing box 10 The lower-side buffering member 30 having a concave portion in its center is located on the upper surface of the lower pad 20 thereafter. The item to be packed P is located in the concave portion of the lower-side buffering member for packing 30 thereafter. A box for attached parts 50, which is made of a corrugated cardboard and stored attached parts and instruction manuals in advance, is located on the upper surface of this item to be packed P. A lid of the packing box is closed, thereby forming the packing article 700.
Therefore, in the related art packing article, the box for attached parts 50 made of a corrugated cardboard is located on the upper side of the item to be packed P so that shockproof is secured by buffer function between the lower-side buffering member for packing 30 and the box for attached parts 50 and the packing article is shipped to the destination safely, even if this article is dropped on the way.
FIG. 13 is a cross-sectional view of a related art packing article where a tray for attached parts is used as a buffering member at upper side. As shown in FIG. 13, a related art article 800 includes a packing box 10, a lower pad 20 located in the bottom of the packing box 10, a lower-side buffering member 30 having a concave portion in the center located on the upper surface of the lower pad 20, the item to be packed P located in the concave portion of the lower-side buffering member 30, a tray for attached parts 52 made of a corrugated cardboard and located on the upper side of the item to be packed P. An attached part P1 and an instruction manual M1 are stored in the inside of the tray 52.
In the packing box 10, a handle opening 10C, to enhance gripping with a user's hand at the time of carrying the packing box, and a throwing opening 10D, to enable passage therethrough of an additional part P2 or an additional instruction manual M2 therein at a shipped area (such as a foreign country), are installed.
FIG. 14 is a schematic of a packing method of a related art packing article shown in FIG. 13. The related art packing article 800 is packed as follows. Firstly, the lower pad 20 is located on the lower surface of the packing box 10. The lower-side buffering member to provide packing 30 having a concave portion in its center is located on the upper surface of the lower pad 20 thereafter. The item to be packed P is located in the concave portion of the lower-side buffering member 30 thereafter. A tray for attached parts 52, made of a corrugated cardboard and stored attached parts and instruction manuals in advance, is located on the upper surface of this item to be packed P. The lids of the packing box are closed, thereby forming the packing article 800.
Thus, in the related art packing article, the tray for attached parts 52 made of a corrugated cardboard and located on the upper side of the item to be packed P so that shockproof is secured by buffer function between the lower-side buffering member 30 and the box for attached parts 50 and the packing article is shipped to the destination safely, even if this article is dropped on the way.
FIG. 15 is a cross-sectional view of a related art packing article where a partition plate is installed. As shown in FIG. 15, a related art article 900 includes the packing box 10, a reinforcing spacer 22 located on the bottom of a packing box 10, the lower-side buffering member to provide 32 having a concave portion in the center located on the upper surface of the reinforcing spacer 22, the item to be packed P located in the concave portion of the a lower-side buffering member for packing 30, a partition member 40 including a partition plate 42 (see FIG. 16) and a skirt portion 44 (see FIG. 16) and a box 50 for attached parts, which is made of a corrugated cardboard and located at the upper side of the partition member 40. An attached part P1 and an instruction manual M1 are stored in the inside of the box 50 for attached parts.
In the packing box 10, the handling opening 10C, to enhance gripping with a user's hand at the time of carrying the packing box, and the throwing opening 10D, to enable passage therethrough of an additional part P2 or an additional instruction manual M2 therein at a shipped area (such as a foreign country), are installed.
FIG. 16 is a schematic of a packing method of a related art packing article shown in FIG. 15. The related art packing article 900 is packed as follows. Firstly, the reinforcing spacer 22 is inserted under the lower side of the lower-side buffering member to provide 32 having a concave portion in the center. This lower-side buffering member 32 with the inserted reinforcing spacer 22 is located on the bottom of the packing box 10. The item to be packed P is located in the concave portion of the lower-side buffering member 32 thereafter. The partition member 40 including the partition plate 42 and the skirt portion 44 connected to the partition plate 42 is located on the upper side of the item to be packed P thereafter. A box for attached parts 50, made of a corrugated cardboard and stored attached parts and instruction manuals in advance, is located on the upper surface of this partition member 40. The lids of the packing box are closed, thereby forming the packing article 900.
Thus, in the related art packing article, the box for attached parts 50, which is made of a corrugated cardboard, works as the upper buffer member and is located on the upper surface of the item to be packed P so that shockproof is highly secured by buffering function of the lower-side buffering member for packing 32 and the box for attached parts 50 and the packing article is shipped safely, even if the packing article is dropped on the way. Further, in this related art packing article, the partition member 40 is located between the item to be packed P and the box for attached parts 50 so that this item to be packed P contacts with the box for attached parts 50 via this partition member, even if the item to be packed P is thick. Hence, shockproofing is provided by the buffering function of this partition member, and the packing article is shipped safely, even if the packing article is dropped on the way. Further, the shock to the packing article P, caused by the weight of the box for attached parts 50, can be softened because of the existence of the partition member 40.
A box for attached parts and a tray for attached parts made of corrugated cardboard and used in the related art packing article are subject to the problem that these elements are still hard, and thus somewhat insufficient to achieve a buffering function. Further, the partition member is also still hard, and thus somewhat insufficient to achieve a buffering function, even if installing the partition member enhances the buffering function.

Packing article, a method of packing and a partition member


A tool cabinet has a plurality of vertically-oriented drawers, each slidably supported at its upper and lower ends by upper and lower drawer slide assemblies, wherein each slide assembly is coupled between facing support surfaces on the drawer and the cabinet frame, which surfaces are inclined to both the horizontal and vertical in use. The cabinet also includes horizontal drawers and an access door. Each vertical drawer has a pegboard-type panel on which associated tools or articles may be hung.

The present invention relates to storage cabinets for articles such as tools and, in particular, to vertically-oriented drawers or like storage units for such cabinets.
Typical tool chests or cabinets are provided with horizontally arranged shelves, drawers, trays and the like for containing or supporting tools or other items. Since horizontal drawers can sometimes make it difficult for the user, such as an automotive mechanic or the like, to readily see or gain access to the contents of a drawer, tool cabinets or storage devices have also been provided with upstanding support panels or pallets or the like on which tools can be clipped or hung for better display to the user. Such upright arrangements may, for example, include wall cabinets, with a tool-support wall arranged vertically in use, and tool chests with pop-up tool pallets, which can be raised from a horizontal position to an upstanding position for better display and access. However, wall cabinets and tool chests with pop-up pallets have only a single pallet or tool-support wall.
In other applications, it has been known to provide cabinets with vertically-arranged drawers or storage units which can be slidably moved between closed positions within the cabinet and open positions extending from the cabinet, and on which items may be hung or clipped. In prior drawer cabinets, the drawers, whether vertical or horizontal, are typically supported on drawer slide assemblies, which commonly include two or three interfitted slide members or rails slidably movable relative to each other, usually with the aid of a friction-reducing arrangement, such as the use of low-friction materials, ball races and the like. The rails or tracks of these drawer slide assemblies are commonly channel-shaped, having a width substantially greater than the depth, the assemblies typically being mounted with the channel width oriented vertically in use. Thus, when the drawer is pulled out to its open position, the drawer slide assembly has uneven rigidity in horizontal and vertical directions.

Inclined slide assemblies for vertical drawers


The present invention provides a method, a system, and a device for a hash generation and network traffic detection. It uses a method of storing intermediate calculation results to perform hash calculation for streaming data, and uses a matrix multiplication operation as a strong hash algorithm to reduce memory occupation. The present invention can generate hash in real time in the case of streaming data comprising defects, unordered, and overlapping, which is suitable for detecting files from network traffic, and is applicable to virus detection, intrusion detection, data anti-leakage, network content review, digital forensics, digital rights protection, and other fields.

With the ever-increasing network traffic, identifying traffic data for the data leakage prevention (Data Leakage Protection, DLP), network defense and other security requirements increasingly important. For example, Trojans, viruses, porn videos, and internal files are identified from network traffic. If they can be identified during transmission, they can be examined and disposed of at an early stage.
To identify data in traffic, the general approach is to generate a summary of the data in the network. The current methods for generating summaries for data fall into two main categories:
The first type, cryptographic hash algorithms, such as MD5, SHA256 algorithms, etc. Due to the avalanche effect when the data changes, minor modifications to the file will cause the hash values to change greatly, so it cannot be used for identifying similar files.
The second type, context-triggered piecewise hashing, such as ssdeep, sdhash, tlsh, Nilsimsa, mrsh-v2, and so on. Among them, ssdeep, also known as fuzzy hash, is the most widely adopted context-triggered piecewise hashing algorithm, which is used by institutions such as the National Institute of Standards and Technology, VirusTotal, and others.
Fuzzy hashing algorithm is based on hash slicing, with a weak hash function (rolling hash, referred rh) calculating a length of a continuous byte hash value (calculation length referred to as slice calculation window).
When the weak hash value rh satisfies the slicing condition (Equation 2), the data is sliced at this position.
The slicing conditions determine the average number of slices, the method of calculating the initial block size binit as shown in Equation 1, the slicing condition is shown in Equation 2:
                     b      init          =                  b       min                         2               ⌊                           log          2                  (                   n                     Sb           min                            )                ⌋                                     Eqn     .                   (      1      )                                    rh                     mod                     blocksize          =           blocksize      -      1                        Eqn     .                   (      2      )
wherein bmin, a constant, is the minimum slice value; ssdeep is set to be 3 in the algorithm; n is the length of the input file; S, a constant, is the length of the expected hash string; ssdeep is set to be 64 in the algorithm, mod is modulo operation; the blocksize initial value is binit.
Subsequently, a low collision rate hash function (called strong hashing in ssdeep, using FNV algorithm) is used to calculate a hash value for each slice, such that local file changes only affects one or two slices, and do not cause the hash values the entire file to change completely. In practice, the similarity between two files is measured by using the edit distance between the fuzzy hash values of the two files.
The byte streams of the files/data transmitted in the network traffic can be obtained by traffic capture, protocol parsing, and decompression. However, there are a large number of complex processing situations in network traffic based on application protocol, such as online video playback, network disk file downloading, etc. Such type of data has a lot of unordered and incomplete capture situations.
Therefore, the traditional fuzzy hash algorithm is suitable for the processing of offline data (identifying almost identical files using context triggered piecewise hashing, 2006), but the presently transmitted streaming data have encountered the following problems:
1) Data arriving out of order: due to transmission technologies such as multi-thread transmission, the byte stream of a file may be unordered, that is, the data located at the front of the file arrives later, while the data at the back of the file arrives first. The traditional solution for the out-of-order problem is to cache data, but this will undoubtedly increase memory overhead.
2) Missing initial length: some network transport protocols, such as HTTP 1.1, allow the total length of the file not to be declared before the file transfer begins. The existing fuzzy hash algorithm requires a total file length before the calculation to set a fuzzy hash trigger condition. Thus, files that are being transmitted in the network without an initial length cannot be calculated.
3) File defect: deep packet inspection systems, such as Data Leak Prevention System (DLP) and Network Intrusion Detection System (NIDS), have the ability to restore files from network traffic, but because of many scenarios, such as DDOS attacks, sudden traffic surges, the files captured may be incomplete. Existing hash algorithms cannot summarize such files.
4) Streaming processing: the traditional fuzzy hashing algorithms need to read the files multiple times, and constantly adjust the slicing triggering condition to generate a hash value of appropriate length. This is not a problem for the file stored on the disk. But in dealing with a huge network traffic, there is only one processing opportunity, this method cannot be applied to streaming data being transmitted.

Method, system, and apparatus for monitoring network traffic and generating summary

INSTITUTE OF INFORMATION ENGINEERING, CHINESE ACADEMY OF SCIENCES


Disclosed is a semiconductor device comprising a substrate (10); at least one semiconducting layer (12) comprising a nitride of a group 13 element on said substrate; and an ohmic contact (20) on the at least one semiconducting layer, said ohmic contact comprising a silicon-comprising portion (22) on the at least one semiconducting layer and a metal portion (24) adjacent to and extending over said silicon-comprising portion, the metal portion comprising titanium and a further metal. A method of manufacturing such a semiconductor device is also disclosed.

Over the last few years, semiconductor devices based on group 13 nitrides such as GaN have drawn considerable interest because of their promise in high-temperature and high-power applications, e.g. power and microwave amplification, RF signal processing and sensor applications.
A unique feature of group 13-nitrides like AlN, GaN and InN is the large difference in electronegativity. Nitrogen is the most electronegative group V element. This results in spontaneous polarization in the group 13 nitrides. In addition, strain in the crystal structure of these materials enhances the polarization effect. In GaN/AlGaN heterostructures, this additional piezoelectric polarization due to the differences in crystal lattice parameters gives rise to a two-dimensional electron gas formed at the heterojunction between these two layers. This two-dimensional electron gas forms the conducting channel between the source and drain of a normally-on high electron mobility transistor (HEMT).
It is important to create a low-ohmic contact to the two-dimensional electron gas in order to successfully utilize these devices in high-performance application domains. Most ohmic contacts on GaN/AlGaN heterostructures are based on Ti/Al-based metallization schemes. Titanium creates nitrogen vacancies by forming TiN, which enables electrons to tunnel to the two-dimensional electron gas underneath the AlGaN. Aluminium is present to react with Ti to prevent oxidation of the titanium.
Typically, gold is used as the bulk metal on top of the aluminium, and is separated from the aluminium by one or more diffusion barriers. Most frequently reported metallization schemes include Ti/Al/Ti/Au, Ti/Al/Ni/Au and Ti/Al/Pt/Au.
However, the use of gold adds significant cost to the manufacturing process of such semiconductor devices, not in the least because gold is not commonly used in existing manufacturing processes such as a CMOS process. This therefore requires significant redesign of the manufacturing process, which is undesirable from a cost perspective.
To be able to process group 13 nitride semiconductor devices such as GaN/AlGaN high-electron mobility transistors (HEMTs) on silicon substrates in a main-stream semiconductor fab, such as a silicon-based fab, gold has to be eliminated from the manufacturing process. It is however far from trivial to make this elimination without suffering an increase in the contact resistance of the ohmic contacts, thereby compromising the performance of the semiconductor device.
F. M. Mohammed et al. In Electr. Letters, 41 (17), 2005, pages 984-985, disclose a Ti/Si/Al/Si/Mo/Au layer stack as an ohmic contact for a AlGaN/GaN HEMT. Upon annealing such a contact at 850° C. for 30 seconds, it was found that the incorporation of the silicon layers in this stack caused the formation of silicided inter-metallics as well as the unintentional doping of the AlGaN/GaN heterostructures with silicon, which lead to a contact resistivity of 0.16 Ω·mm and a specific contact resistivity of 6.77×10−7 Ω·cm2.
However, this ohmic contact still relies on gold as the bulk metal, which is undesirable as previously explained. Moreover, it has been experimentally found, e.g. by the present inventors, that the presence of the Si layer in the complete bulk contact causes problems in terms of reproducibility of the quality of the contact in industry-scale manufacturing processes.

Group 13 nitride semiconductor device and method of its manufacture


A cylinder head arrangement for a multiple valve internal combustion engine including an arrangement for cooling the flow passages and also the valve guides which extends longitudinally of the cylinder head so as to promote cooling and the extraction of vapor and air from the engine cooling jacket.

This invention relates to an internal combustion engine and more particularly to an improved cooling arrangement for the cylinder head of such engine.
In overhead valve engines, the intake and/or exhaust passages are formed directly in the cylinder head. Where the engine or cylinder head is liquid cooled, the cylinder head is formed with an internal cooling jacket and the intake and/or exhaust passages are formed by internal walls in the cylinder head around which the cooling jacket extends. However, there are portions of the wall that define the passages which may have larger wall thicknesses, for example, in the area where the valve stems are supported. These thicker wall sections reduce the amount of cooling that is possible for the flow passage.
Where multiple passages are employed for either the intake and/or the exhaust function, it is generally the practice to have the passages formed by a common wall. These common walls provide a substantially greater thickness and thus provide a mass in the interior of the cylinder head which may not be adequately cooled.
In addition, these complex type of internal walls can give rise to pockets where pockets may form, such as either water vapor and/or air, and the cooling of the cylinder head is further deteriorated.
It is, therefore, a principle object of this invention to provide an improved cylinder head cooling arrangement wherein the cooling of the passages in the cylinder head is ensured.
It is a further object of this invention to provide an improved cylinder head arrangement for an internal combustion engine wherein the wall forming the flow passage of the cylinder head is formed with a coolant passage for permitting not only coolant flow but for purging air or water vapor from the cooling jacket and avoiding the formation of pockets that are not filled with liquid coolant.

Engine cylinder head cooling arrangement


A computer implemented method and system is used for evaluating an intensive EEG or an EEG during anaesthesia. Time domain and/or frequency range parameters are determined from the EEG graphs. The determined parameters are used in multivariate classification functions and the intensive EEG or EEG during anaesthesia are automatically divided into stages. The EEG graphs are also analysed for interfering signal components from the quantity of biosignals of graphs characteristic of intensive EEGs or EEGs which are not performed during anaesthesia. If interfering signal components are identified, the existence of biosignals of graphs characteristic of intensive EEGs or EEGs which are not performed during anaesthesia is verified by artifact analysis in the absence of artifacts, and is not verified if artifacts are identified.

EP 0 856 181 B1 has disclosed a method and a device for evaluating an anesthesia EEG or intensive-care EEG. The anesthesia EEG or intensive-care EEG is classified from EEG curves by means of mathematical-statistical methods. Moreover, artifacts are registered and taken into account for correcting or suppressing classifications.
EP 1 795 122 A1 has disclosed the practice of registering EEG signals and bio-impedance signals. Instances where a bio-impedance threshold is exceeded or the similarity between the signals in the EEG signal and in the bio-impedance signal is/are used for artifact recognition. The bio-impedance analysis can be used to discard EEG signal sections that are subjected to artifacts, or the classification as "awake" can be supported, for example if blinking eyes are identified. This document predominantly relates to artifacts in the facial region.
U.S. Pat. No. 6,731,975 A has disclosed a method for determining the cerebral status of a patient, for example after an anesthetic is administered. To this end, the entropy in the EEG signal and in the combined EEG-EMG signal, and a pure EMG index, are calculated.
It was found that there are a number of triggers for bio-signals, which can modify EEG curves and interfere with a classification of the anesthesia EEG or intensive-care EEG. Volatile anesthetics on the basis of flurane, in particular sevoflurane, should be highlighted since these can trigger seizure potentials with increasing dosage.

Method and device for evaluating an intensive EEG or an EEG during anaesthesia


The present invention relates to adenosine A3 receptor ligands of the general formula (I), within those preferably antagonists, as well as their salts, solvates and isomers, and the pharmaceutical compositions containing them, to the use of the compounds of the general formula (I), as well as their salts, solvates and isomers, to the preparation of the compounds of the general formula (I) and their salts, solvates and isomers, furthermore to the new intermediates of the general formulae (II) and to the preparation thereof.

Adenosine is a well-known component of several endogenous molecules (ATP, NAD+, nucleic acids). Besides, it plays an important regulatory role in many physiological processes. The effect of adenosine on heart function was discovered already in 1929 (Drury and Szentgyörgyi, J Physiol 68:213, 1929). The identification of an increasing number of physiological functions mediated by adenosine and the discovery of new adenosine receptor subtypes give possibilities for therapeutic application of specific ligands (Poulse, S. A. and Quinn, R. J. Bioorganic and Medicinal Chemistry 6:619, 1998).
To date, the receptors for adenosine have been classified into three main classes: A1, A2 and A3. The A1 subtype is partly responsible for inhibiting the adenylate cyclase by coupling to Gi membrane protein, partly influences other second messenger systems. The A2 receptor subtype can be subdivided into two further subtypes—A2a and A2b—, which receptors stimulate the adenylate cyclase activity. The sequence of adenosine A3 receptors has been recently identified from rat testis cDNA library. Later it was proved that it corresponds to a novel, functional adenosine receptor. The activation of the A3 receptors is connected also with several second-messenger systems: e.g. inhibiting of adenylate cyclase, and stimulating of phospholipase C and D.
The adenosine receptors are found in several organs and regulate their functions. Both A1 and A2a receptors play important roles in the central nervous system and cardiovascular system. In the CNS, the adenosine inhibits the release of synaptic transmitters which effect is mediated by A1 receptors. In the heart, also the A1 receptors mediate the negative inotropic, chronotropic and dromotropic effects of adenosine. The adenosine A2a receptors located relatively in a higher amount in the striatum, display a functional interaction with dopamine receptors in regulating the synaptic transmission. The A2a adenosine receptors on endothelial and smooth muscle cells are responsible for adenosine-induced vasodilation.
On the basis of mRNA identification, the A2b adenosine receptors are widely distributed in different tissues. They have been identified almost in every cell type, but its expression is the highest in the intestine and the bladder. This subtype probably also has important regulatory function in the regulation of the vascular tone and plays a role in the function of mast cells.
Contrary to A1 and A2a receptors, where the tissue distribution was detected on the protein level, the presence of A2b and A3 receptors was detected on the basis of their mRNA level. Expression levels for A3 adenosine receptors are rather low comparing to other subtypes and highly species dependent. A3 adenosine receptors are expressed primarily in the central nervous system, testis, immune system and appear to be involved in the modulation of mediator release from mast cells in immediate hypersensitivity reaction.
The A3 antagonists published so far in the literature belong to the groups of flavonoides, 1,4-dihydropyridine derivatives, triazoloquinazolines, thiazolonaphthyridines and thiazolopyrimidines. The present invention relates to a novel type of effective A3 antagonists, which have the triazolo-quinolin structure.
For therapeutic use it is essential to ensure that the molecule does not bind, or bind only in the case of very high concentration to the A1, A2a and A2b sub-types of the adenosine receptor. Our present invention relates to the compounds of the general formula (I) as well as their salts, solvates and isomers which have great selectivity for the A3 sub-type of the adenosine receptor.
Our aim was to prepare A3 ligands first of all with triazolo-quinolin structure, and within those preferably antagonists, which have strong antagonistic effect and show high selectivity for the A3 receptor, i.e. they inhibit the A3 receptor in much lower concentration than they inhibit the A1, A2a and A2b receptors. Further aims were to have stability, bioavailability, therapeutic index and toxicity data which make possible to develop the new compounds into drug substances and that due to their favourable enteral absorbtion the compounds can be applied orally.

Triazolo-quinolin derivatives useful as adenosine receptor ligands


A brevity signaling module for a digital television (DTV) receiver enables the reception of emergency broadcast messages. The overlay signal received at the receiver front end is squared in a squaring loop, producing spectral lines at DC and twice the overlay signal frequency, or 2xcfx89, where xcfx89=2xcfx80f and f is the center frequency of the overlay signal. The squared signal is passed through a narrow band filter having a bandwidth sufficient to pass a spectrum containing a plurality of tones 2xcfx89, 2xcfx891, 2xcfx892, . . . , 2xcfx89n, where 2xcfx891, 22, . . . , 2xcfx89n are different frequency tones assigned to different auxiliary functions. The detected tone is used by a control module to determine whether normal multipath processing should be performed or whether this processing should be suppressed and auxiliary functions performed, including turning on the DTV receiver power in order that an emergency broadcast message might be conveyed to persons in the vicinity of the DTV receiver.

1. Technical Field
This invention relates to digital televison (DTV) and, more particularly, to use of an overlay signal in the DTV transmission for brevity signaling for public safety.
2. Background Art
High definition television (HDTV) is an emerging technology that is capable of providing service either in analog or digital format. In the United States, research on HDTV has focused on digital, rather than analog, technology. While digital HDTV is not currently available, Japanese companies have developed an HDTV system based on analog technology (known as Hivision) that has been in use since 1991. Because of the potential advantages of digital HDTV and many technical problems shared by both types of systems, research in digital HDTV has also been active in Japan. See, for example, David K. Kahaner in xe2x80x9cHDTV Research in Japanxe2x80x9d, IEEE Micro, Oct. 1993, pp. 49-53.
One of the most important prevalent problems in DTV is that of multipath. In fact, it is useful to think of the DTV channel as multipath limited and not power limited. Multipath may arise from fixed structures acting as reflectors in the transmission channel, such as building walls. Moving objects, such as airplanes, may also cause a multipath condition. Even microreflections in cabling can cause multipath. See, for example, P. T. Marhiopoulos and M. Sablatash, xe2x80x9cDesign of a Ghost Canceling Reference Signal for Television Systems in North Americaxe2x80x9d, Proceedings of Canadian Conference on Electrical and Computer Engineering, Vancouver, BC, Canada, Sep. 14-17 1993, pp. 660-663.
It has been proposed, as described in commonly assigned copending patent application Ser. No. 09/201,376, filed Nov. 30, 1998, that the DTV transmitter overlay a wideband signal in order to provide a way to characterize the multipath limited channel in order to mitigate multipath effects. This signal would be processed by receivers equipped to do so, but would not adversely affect the picture produced by receivers not so equipped; that is, the technique is backward compatible.
The Emergency Alert System (EAS) is a valuable government service that provides timely and crucial warning to customers of public broadcast media. As recently as 1997, the new EAS system replaced the older Emergency Broadcast System (EBS). The upgraded system allows for less obtrusive testing and converts many of the its messages into digital formats. As digital television (DTV) matures, it will provide a challenge to make better use of the publicly owned spectrum to better serve the public. One important way to do this is to upgrade communications for public safety and the commonweal to even higher levels.
A brevity signaling module for a digital television (DTV) receiver enables reception of emergency broadcast messages. The overlay signal received at the receiver is squared, producing spectral lines at DC and twice the overlay signal frequency, or 2xcfx89, where xcfx89=2xcfx80f and f is the center frequency of the overlay signal. The squared signal is analyzed to determine which of different frequency tones, 2xcfx89, 2xcfx891, 2xcfx892, . . . , 2xcfx89n, is present, where the different frequency tones 2xcfx891, 2xcfx892, . . . , 2xcfx89n are assigned to different functions. The detected tone is used by a control module to determine whether normal multipath processing should be performed or whether this processing should be suppressed and auxiliary functions performed, including turning on the DTV receiver power in order that an emergency broadcast message might be conveyed to persons in the vicinity of the DTV receiver.

Use of wideband DTV overlay signals for brevity signaling and public safety


A lottery gaming system and method providing a lottery ticket with a pre-draw cash-in amount based on the player symbols of the lottery ticket.

The present disclosure relates to lottery gaming systems, tickets, and methods, and more particularly to lottery gaming systems, tickets, and methods that enable the play of lottery games. Certain lottery gaming systems may enable a player to select one or more numbers for a lottery ticket, randomly select winning draw numbers, and if the winning draw numbers match the player-selected numbers, provide the player an award.

Lottery gaming system, ticket, and method


The present invention relates to a flexible sensing material made from (a) at least one flexible polymeric layer and (b) at least one conductive, curable coating layer containing about 0.01 wt. % to about 5 wt. % of multi-walled carbon nanotubes having a diameter of greater than about 4 nm, about 10 wt. % to about 99 wt. % of an aliphatic urethane acrylate and about 0.1 wt. % to about 15 wt. % of a photoinitiator, wherein the weight percentages are based on the weight of the formulation, wherein the coating layer is curable by exposure to radiation and wherein the cured coating layer has a surface resistivity of about 102Ω/□ to about 1010Ω/□. The inventive sensing material may prove useful for sensing one or more of pressure, temperature and moisture and find use in a wide variety of applications.

Since the discovery of carbon nanotubes in 1991 by Iijima, Nature, 354, pp. 56-58 (1991), extensive research has been carried out involving the synthesis, chemistry, and manipulation of these materials. Carbon nanotubes are electrically conductive along their length, chemically stable, and capable, individually, of having a very small diameter (much less than 100 nanometers) and large aspect ratios (length/diameter).
Force sensors made of resistive inks or materials that can measure applied force by changes in resistance have been known in the art since around 1968 as evidenced by U.S. Pat. No. 3,806,471, issued to Mitchell. Mitchell used a volumetric dispersion of at least partially conductive particles such as molybdenum disulfide in a compressible insulating elastomeric material such as RTV silicon rubber. When a force is applied to compress the material the particles touch and increase the number of conductive paths through the bulk material thereby decreasing the resistance of the material. When the force is removed the material conforms to its original shape and returns to its original resistance. The change in resistance is a bulk material effect and not a surface effect, and as such does not work well in thin film applications. Additionally, the high loadings of conductive particles in the elastomeric material will reduce the elastomeric properties of the bulk material.
U.S. Pat. Nos. 4,489,302 and 4,314,227, both issued to Eventoff, disclose an improved force sensor based on the pressure dependent contact area between a conducting surface and a semiconducting surface having a multiplicity of microprotrusions of the semiconducting material. In one embodiment, the loading of the semiconducting molybdenum disulfide material in the resin surface is between 46% and 63%. Such high loadings of filler will reduce the physical properties of the resin binder, such as flexibility. Eventoff teaches in some of embodiments that the flexible film used as the substrate is MYLAR. The substrate films in Eventoff can conform to a two dimensional surface but cannot conform to a three dimensional surface well without creasing.
Maness et al., in U.S. Pat. No. 4,734,034, disclose a flexible force sensing pad suitable for measuring dental occlusions. Maness et al. teach a flexible high spatial resolution force sensor pad can be fabricated using a matrix of force sensor cells. The force sensor cells are composed of a plurality of flexible parallel electrodes supported by a thin flexible film substrate to provide a set of row electrodes; a second plurality of flexible parallel electrodes supported by a second thin flexible film substrate to provide a set of column electrodes. At least one of the two sets of electrodes is coated with a thin film resistive material, preferably an insulating vinyl ester binder with titanium dioxide filler and butyl cellosolve acetate solvent with a conductive ink containing graphite, vinyl resin, and butyl cellosolve acetate; and oriented such that the two electrode sets face each other to form a matrix of rows and columns that defines a measuring space suitable for measuring dental occlusions. The two sets of electrodes are separated by a resistive layer such as talcum powder to prevent contact until there is an applied force. The response of the force sensor cells as taught by Maness et al. is of a binary nature which either senses an applied force or no applied force but cannot discriminate between small changes in applied force. Maness et al. teach in the preferred embodiment of the invention, the thin film used as the flexible substrate is polyester film such as MYLAR, or similar films such as KAPTON, manufactured by DuPont. The substrate films of Maness et al. can conform to a two dimensional surface but cannot conform to a three dimensional surface well without creasing.
U.S. Pat. No. 4,856,993 also issued to Maness et al., is said to provide an improvement on U.S. Pat. No. 4,734,034, wherein part of the resistive coating between the conductive plurality of flexible parallel electrodes in rows and columns is composed of a graphite-molybdenum disulfide based ink in an acrylic binder. The separating resistive layer (talcum) between the two sets of electrodes is also eliminated. Maness et al. teach the thin film used as the flexible substrate is polyester film such as MYLAR, or similar films such as KAPTON. The substrate films of Maness et al. can conform to a two dimensional surface but cannot conform to a three dimensional surface well without creasing. The pressure sensing resistive layer is composed of high levels of graphite and molybdenum disulfide that reduces the flexibility and mechanical properties of the layer.
U.S. Pat. No. 5,296,837 issued to Yaniger, discloses a pressure transducer based on at least one three-dimensional stannous oxide textured resistive layer juxtaposed to at least one of two conductive layers containing a circuit to measure the resistance between the two conductive layers. The measured resistance is a function of the resistance layers contact area or pressure perpendicular to the resistive layers. In one embodiment, the pressure transducer resistance is dependent on the area of contact between the two juxtaposed resistive layers. At low pressure, just the peaks of the stannous oxide particles of the textured surfaces are in contact giving a high resistance. As the pressure increases, the two resistive layers bend to conform to the valleys between the stannous oxide particles and increase the contact area between the resistive layers. One advantage to this form of pressure transducer is it relies on a surface effect and not a bulk effect and thus may be well suited to thin film applications. However, in the preferred embodiment of Yaniger, the levels of stannous oxide filler can range from 16% to 80% of the conductive resin layer which would have a considerable effect on the physical properties of a thin film, such as flexibility. Yaniger teaches the thin film suitable as the flexible substrate is a polyester film such as MYLAR. Similarly to other referenced patents herein, the substrate films of Yaniger can conform to a two dimensional surface but cannot conform to a three dimensional surface well without creasing.
U.S. Pat. Nos. 6,964,205 and 7,258,026, both issued to Papakostas et al., disclose a method for fabricating a plurality of sensor cells to measure a parameter applied to a surface. Papakostas et al. try to address the shortcomings in the above-referenced patents on flexibility in the film substrates and flexibility in the resistive measuring layer. Papakostas et al. teach that flexibility and mechanical isolation between cells can be achieved by using spiral-like conductive traces which wrap around at least a portion of the sensor element to interconnect the sensor elements. Papakostas et al. further teach slits or cut-outs in the substrate between the sensor elements will allow sensor elements to move independently of one another. Cut slits in the film will improve the overall flexibility of the film and independent movement of the individual sensor elements, but the sections of the film and sensor cells will still be subject to stress cracking in areas of high flexing loads.
It is known to those skilled in the art that non elastomeric films or substrates in applications that involve extensive flexing will undergo stress cracking over time. The use of sensor pads or films in applications such as shoes, wheelchairs, hospital beds, and car scats has thus been limited due to the robustness of the materials of construction.
Therefore, a need continues to exist in the art for improved materials for sensing one or more parameters such as pressure, temperature and moisture. A need also exists for a highly flexible force sensing cell and sensor array on a highly flexible and elastomeric film substrate. The sensing material should preferably be flexible to permit its use in a wide variety of applications.

Flexible sensing material containing carbon nanotubes


An image sensor including a photoelectric converter, a charge-voltage converter, a transfer transistor to transfer a charge from the photoelectric converter to the charge-voltage converter whereby potential of the charge-voltage converter changes to a first direction, an amplifier transistor to output a signal corresponding to potential of the charge-voltage converter to a column signal line, the amplifier transistor sequentially outputting, to the column signal line, noise level and light signal level, a capacitance between a control signal line and the charge-voltage converter, and a control unit to change a potential of the control signal line so that the potential of the charge-voltage converter changes to a second direction opposite to the first direction in a period in which the charge-voltage converter is in floating and which is prior to outputting the noise level.

Field of the Invention
The present invention relates to a solid-state image sensor and a camera.
Description of the Related Art
A solid-state image sensor including a plurality of two-dimensionally arrayed photoelectric converters is mounted in a digital camera, a digital camcorder, or the like. In the solid-state image sensor, a transfer transistor transfers charges accumulated in the photoelectric converters to a floating diffusion (to be referred to as an FD hereinafter). The FD functions as a charge-voltage converter which converts a charge quantity into a voltage. The gate of an amplifier transistor is connected to the FD. The amplifier transistor outputs, to a column signal line, a signal corresponding to the charge quantity (the potential of the FD) transferred to the FD. The charge quantity that can be transferred to the FD depends on the potential of the FD. Japanese Patent Laid-Open No. 2012-010106 describes that when the FD is in a floating state, the potential of the FD is increased by increasing the potential of the gate of a reset transistor within a range where the reset transistor is not turned on. Increasing the potential of the FD makes it possible to increase the charge quantity that can be transferred to the FD and widen a dynamic range. Note that if the potential of the gate of the reset transistor is increased until the reset transistor is turned on, the reset transistor drives the FD at a predetermined potential. In this state, therefore, it is impossible to read out signals corresponding to the charges of the photoelectric converters even if the charges are transferred to the FD.
As described above, the solid-state image sensor described in Japanese Patent Laid-Open No. 2012-010106 can increase the potential of the gate of the reset transistor only within the range where the reset transistor is not turned on. Therefore, the charge quantity that can be transferred to the FD serving as the charge-voltage converter is limited to be in the range where the reset transistor is not turned on.

Solid-state image sensor and camera with charge-voltage converter


An apparatus, system, and method are provided for automatically minimizing Real-Time (RT) task latency and maximizing Non-Real Time (NRT) task throughput. The apparatus may include a task manager, a determination module, and optionally a tracking module. The task manager may execute a NRT task configured to obtain exclusive access to a resource within a multi-processor environment. The determination module identifies a RT task within the multi-processor environment that shares exclusive access to the resource with the NRT task. Optionally, the tracking module selectively executes or bypasses a preemption point associated with the NRT task in response to the RT task becoming runnable. Alternatively, the NRT task selectively executes or bypasses a predefined preemption point in response to the RT task becoming runnable. In this manner, RT tasks on any processor of the multi-processor environment meet minimum latency thresholds and NRT tasks automatically provide maximum throughput in the multi-processor environment.

1. Field of the Invention
The invention relates to multi-processor computing. Specifically, the invention relates to apparatus, systems, and methods for automatically minimizing real-time task latency and maximizing non-real time task throughput.
2. Description of the Related Art
Mainstream computer systems are currently moving from conventional single processor architectures, also known as Uniprocessor (UP), to multi-processor architectures. In particular, Symmetric Multi-Processor (SMP) architectures or environments are becoming more widely used in various fields. In an SMP environment, typically, hardware computing resources such as memory, communications bus, I/O devices, and the Operating System (OS) are shared by two or more processors. The multiple processors cooperate as peers each having an equal ability to service tasks assigned by the OS.
A multi-processor environment or SMP system can be implemented with multiple physical processors connected to a common bus. Alternatively, due to advances in processor technology a single physical processor may be used but treated as multiple logical processors by the OS and all other computer system components. One example of this technology is hyperthreading. As used herein, references to SMP system(s) and multi-processor environment(s) refers to any computer system that includes a plurality of physical and/or logical processors. Similarly, references to "processor" include both physical processors and logical processors.
SMP systems are being used both for general purpose computing such as desktop PCs and for more specialized applications such as embedded computing systems. Operating systems for the general purpose and embedded computing systems are adapting to most efficiently service both general desktop computing needs and specialized embedded computing needs. One example of this adaptation is the ability of a single SMP OS to properly manage both Non-Real Time (NRT) tasks and Real-Time (RT) tasks. As used herein, the term "task" refers to the smallest portion of a software program that the OS can switch between a waiting or blocked state and a running state in which the task executes on a particular processor. Tasks can come from a single software program or a plurality of software programs and typically include portions of the OS.
As used herein, a NRT task refers to software code that does not have explicit time constraints for when computing services are to be provided to the task. Conversely, RT tasks are tasks for which the task has a predefined maximum threshold for delay between requesting a service from the computer system and having the request fulfilled. Failure to service the RT task within the threshold can cause serious failure of the task and/or systems managed by the RT task. Furthermore, RT tasks include both hard real time tasks and soft real time tasks. Hard real time tasks require an absolute guarantee of response time below the maximum threshold. Soft real time tasks require a very high probability that the response time is below the maximum threshold, but not an absolute guarantee.
Where the threshold is set to define a NRT task or a RT task depends on the context. For a mission critical task, such as respiratory oxygen content in a hospital patient, the threshold could be measured in tens of microseconds. Such a critical task is one example of a hard real time task. For other RT tasks, soft real time tasks, the threshold could be measured in minutes, such as a weather station temperature sampling task. Another soft real time task example is a real time video or audio processing task. Failure to meet the maximum threshold for response time may result in detectable "skips" or degradation in quality, but not critical failures such as possible death.
Typically, NRT tasks are tasks that involve user interaction where long delays in response to user inputs results in a poor user experience but no loss of data, functionality, or a critical failure. However, because classifying a task depends so much on the context, NRT tasks and RT tasks are typically classified as such for the OS by the software developer. Generally, RT tasks have a very low service threshold and NRT tasks have a comparatively high service threshold.
The delay between when a task requests a service from the OS and when the service is provided is referred to as latency. Typically, the requested service is the assignment of a processor to execute the task. The service threshold defines a maximum tolerable latency for the task. As used herein, the term "latency" or "task latency" refers to the time between when the task requests a service from the OS and when the service is provided. The service may include assignment of a processor for task execution, exclusive access to a resource, and the like. Task latency typically includes other more specific latencies well known to those of skill in the art such as scheduling latency, task switching latency, and the like.
Multiple factors affect task latency. It is well known that modern OSs constantly change the task assigned to a particular processor in order to provide multitasking functionality. Consequently, the number of tasks managed by the OS can lengthen the task latency due to the increased overhead in handling each additional task. However, due to the critical nature of RT tasks, general purpose OSs have been modified to service the task latency requirements of the most demanding RT tasks in order to handle a worst-case scenario and ensure that the worst-case task latency still meets the RT task requirements.
In certain cases, real-time specific OSs (RTOSs) have been developed. Unfortunately, the RTOSs favor the RT tasks over the NRT tasks. Consequently, a NRT task may experience poor responsiveness on an RTOS system. Often, if the RTOS support NRT tasks, the NRT task is so delayed in responding to user inputs that the user notices a delay in response to a user-initiated action. The responsiveness of a NRT task in an OS is referred to herein as task throughput. Task throughput represents how quickly a task is able to complete a command and provide a response to the user. Task throughput also includes the number of units of work a task can complete in a given time period.
If NRT tasks and RT tasks are run together on the same computer system, the optimizations for servicing RT tasks adversely affect NRT task throughput. In certain cases, the NRT task throughput is affected regardless of whether any RT tasks are running on the system. Similarly, conventional optimizations to improve NRT throughput can adversely affect RT task latency. Consequently, the industry has experienced a trade-off in OSs attempting to service both RT tasks and NRT tasks. Until the present invention, the industry has been unable to satisfactorily minimize RT task latency and maximize NRT task throughput automatically.
Typically, NRT task throughput is sacrificed in favor of RT task latency. Currently, the OS scheduling algorithm is optimized such that RT tasks, if present, are assigned a processor ahead of NRT tasks. Consequently, in a typical Uniprocessor (UP) system, NRT tasks are generally preempted if a RT task becomes runnable. Preemption means the task currently executing on the processor is halted before the task has reached a natural termination point. The task is forced to wait while a higher priority task, such as a RT task, is assigned a processor. However, as noted above, under this approach, as the number of RT tasks increases the NRT task throughput decreases. Examples of these scheduling optimizations include a Priority Level Scheduler (PLS) and Multi-queue Scheduler (MQS).
The problem of optimizing the OS to minimize RT task latency and maximize NRT throughput is even more difficult in an SMP system. In a UP system, RT tasks can simply be tracked and provided priority over runnable NRT tasks. However, in SMP systems, there is currently no efficient way to determine whether a RT task exists on a processor other than the processor executing a NRT task.
In addition, in an SMP system the concurrent nature of multiple processors (each executing a different task) sharing resources such as data structures, memory, devices, and the like requires that access to the shared resources be controlled. The access to the resources is controlled such that only one processor and its currently executing task, are permitted to access the resource at a given time. This process of controlling access is referred to as serialization.
Serialization is particularly desirable to preserve data integrity when multiple tasks/processors can modify data in a shared resource. Preempting a task while writing to a shared resource can corrupt the data. Consequently, serialization should provide exclusive access for the task requesting the shared resource and exclude preemption. If one task has access to the resource, all other tasks are excluded from con accessing the resource until the one task has finished. Exclusive access is provided atomically meaning a task executes a single command to obtain access and is either successful or not, there is no opportunity to preempt the task while requesting the exclusive access.
Generally, serialization of SMP tasks to shared resources is controlled by locks. If a task desires exclusive access to a resource, the task requests the lock. If the lock is not held by any other task, the lock is atomically provided to the requesting task. If the lock is held by another task, the requesting task often enters a loop in which the task continually requests the lock until the lock becomes free. Once a task holds a lock, the task modifies or otherwise uses the shared resource in some manner and then releases the lock. Typically, a lock is implemented using a boolean value, False if the lock is available and True if the lock is being held.
FIG. 1 illustrates a conventional multi-processor environment 100 with NRT tasks 102 and RT tasks 104 that share exclusive access to a common resource 106. The environment 100 includes a memory 108, a plurality of processors 110, also referred to as Central Processing Units (CPUs) 110, and a communications bus 112. The memory 108, CPUs 110, and communications bus 112 are well known. The CPUs 110 are identified by subscripts 1, 2, . . . n. Those of skill in the art will recognize various different hardware configurations for a multi-processor environment 100.
The memory 108 includes a set of executable code that includes a multi-processor operating system 114 such as an SMP OS 114 and a data section 116. The SMP OS 114 includes a task manager 118 also referred to as a scheduler 118 and a runqueue 120 associated with each CPU 110. The runqueue 120 include subscripts 1, 2, . . . n corresponding to the associated CPU 110. The data section 116 includes task-specific data as well as data structures shared by the tasks. Certain exclusive access data structures are controlled by locks 122. Different locks 122 are represented using alphabetic identifiers and an arrow 124 to the associated resource 106, such as a data structure.
By way of example, in the current multi-processor environment 100, CPU1 110 is executing a NRT task 102 that has acquired the lock A 122a for resource 106. At substantially the same time, a RT task 104 on CPUn 110 has become runnable and begins to run on CPUn. Furthermore, one of the first instructions executed by RT task 104 is to acquire lock A 122b.
This presents a problem. The task latency will be increased because the NRT task 102 is holding lock A 122a which the RT task 104 needs and the NRT task 102 is not preemptable. Furthermore, depending on which type of lock 122 NRT task 102 is holding interrupts could be disabled. This means that the RT task 104 must wait for the NRT task 102 to release the lock before the RT task 104 can perform its work. In addition, if interrupts are enabled, an interrupt arrive while the NRT task 102 holds the lock. The interrupt may be long-running such that the interrupt also delays the release of the lock by NRT task 102. The delays caused by the NRT task 102 and/or interrupts are generally unacceptable and the RT task latency maximum threshold is consequently exceeded.
In a conventional multi-processor environment 100, the solution is to defer to the needs of the RT task 104. One proposed solution is to include multiple preemption points 126 in the code of the NRT task 102. Alternatively, if the NRT task 102 is executing object code in the kernel of the OS, the preemption points 126 are in the kernel. The preemption point 126 is executed indiscriminately. There is currently no way for a NRT task 102 to avoid the preemption point 126 and its associated delay.
A preemption point 126 is a predefined point in the object code when a developer has determined that the NRT task 102 can voluntarily give up ownership of the CPU1 110. Generally, as part of executing the preemption point 1126 the NRT task 102 will also release any locks 122 being held. Typically, the preemption points 126 are in the kernel object code and the NRT task 102 is forced to give up the CPU1 110.
Preemption points 126 ensure that the most time added to the RT task latency is the time between preemption points 126. RT tasks 104 are not delayed by a NRT task 102 holding a lock 122 too long. Preemption points 126 also introduce overhead as the NRT task 102 performs steps to preserve its state, release any locks 122, sleep, and then resume operations after the preemption point 126.
Unfortunately, indiscriminate execution of preemption points 126 incurs this overhead delay even if there are no RT tasks 104 in the environment 100. The overhead delays caused by mandatory preemption points 126 unnecessarily reduce the NRT task throughput.
From the foregoing discussion, it should be apparent that a need exists for an apparatus, system, and method for automatically minimizing RT task latency and maximizing NRT task throughput in a multi-processor environment. Beneficially, such an apparatus, system, and method would conditionally execute preemption points in response to the presence or absence of a runnable RT task in the multi-processor environment. In addition, the apparatus, system, and method would automatically and optimally handle both RT tasks and NRT tasks, incur minimal processing overhead, and prevent shared resource contention between NRT tasks and RT tasks.

Apparatus, system, and method for automatically minimizing real-time task latency and maximizing non-real time task throughput

International Business Machines Corporation


A concave portion having a V-shaped cross section is dug in a semiconductor region of a chip, and a surface of the semiconductor region inclusive of the concave portion is covered with an insulation film. A wiring film connected to an integrated circuit device is disposed on the insulation film. A protection film covering the surface of the chip is provided with a window to expose the concave portion and a portion of the wiring film. The window is covered with a thin metal subbing film connected to the wiring film. A metal protrusion for a bump electrode is provided by an electroplating process so as to protrude from the concave portion.

1. Field of the Invention
The present invention relates to a bump electrode structure and more particularly to a small bump electrode or protruded electrode provided on a semiconductor chip for connecting the integrated circuit device to the outside. The present invention also relates to a semiconductor chip having such a bump electrode structure.
2. Description of the Prior Art
Recent development of high integration techniques for fabricating semiconductor integrated circuit devices has naturally led to requirement for rationalization of forms in which the semiconductor integrated circuit devices are-mounted in electronic circuits or electronic devices, particularly reduction in time and effort, as well as spaces required for mounting. As is well known, it is more advantageous to mount chips of integrated circuit devices as they are, i.e., in the form of chips themselves, than mount them after they are contained in plastic packages or the like. Hence, so-called flip chips, which are mass-produced electronic devices having protruding bump electrodes have been adopted widely.
Referring to FIG. 1, a typical example of construction of a conventional bump electrode will be explained below. FIG. 1 is a cross sectional view showing a portion of a semiconductor integrated circuit device chip. As shown in FIG. 1, a bump electrode 20 made of a solder is mounted on a semiconductor region 10 of a semiconductor integrated circuit device chip 1. An insulator film 22 such as silica film covers a surface of the semiconductor region 10. An aluminum wiring 23 connected to the integrated circuit in the semiconductor region 10 is arranged on the insulation film 22. An end of the aluminum wiring 23 is covered with a protective film 24 made of silicon nitride or the like, which is formed with a window for forming the bump electrode 20 by removing the protective film 24 to expose the aluminum film 23. The exposed aluminum film area or the window area is covered with a thin subbing layer 25 made of a metal such as titanium or copper. Then, a metal protrusion 26 made of a solder is grown to a predetermined height by an electroplating method. In the case shown in FIG. 1, the metal protrusion 26 is heated for a short time to melt the solder, thereby forming the bump electrode 20 rounded on its top.
The mounting of a flip chip having such a bump electrode as mentioned above can be performed, for example, by placing the chip on a device on which the chip is to be mounted in such a manner that the tip of the bump electrode contacts a conductor of the other device, that is, upside down in FIG. 1, and heating in this state to melt the solder to thereby solder the metal protrusion 26 to the conductor. This ensures both fixation and connection of the flip chip to the other device on which it is to be mounted simultaneously, resulting in reduction in the labor of mounting and minimization of spaces required for the mounting.
The development of high integration of circuits on the other hand has led to reduction in size of chips of semiconductor integrated circuit devices and increase in the number of circuits integrated in a single chip, and hence there is a tendency that the number of connections connected to the outside increases. In the case of certain integrated circuit devices, for example, it is required to arrange several hundreds bump electrodes on a surface of a chip of within several millimeter square. This means the size of the bump electrode must be reduced from about 100 .mu.m in diameter or square as had by conventional bump electrodes, to below 30 .mu.m. However, miniaturization or reduction in size causes a new problem of weakened attachment or junction of the bump electrodes to the root of the chip
More specifically, reduction in the diameter of a bump electrode from 100 .mu.m to 30 .mu.m results in reduction in the area of the root portion the bump electrode to about 1/10, and this alone leads to reduction in junction strength by one order of magnitude. In addition, reliability of adhesion among the films provided between the metal protrusion 26 and the semiconductor region 10, i.e., the insulation film 22, aluminum wiring film 23, the protection film 24 and the subbing film 25 shown in FIG. 1 also reduces so that decrease in the junction strength is further aggravated to such an extent that a small outer force urged upon the mounting could readily cause the films to peel one from another.

Bump electrode structure and semiconductor chip having the same


There is provided a combination treatment for slowing or arresting the progression and/or effecting the regression of atherosclerotic plaque deposits in a mammalian patient, said combination treatment including the administration to the patient of a cholesterol lowering drug such as a statin, and the administration to the patient of an aliquot of a patient's own blood which has been treated ex vivo with one or more stressors selected from an oxidative environment, thermal stress and UV light.

Hyperlipidemias such as hypercholesterolemia and elevated serum triglyceride levels are among the most potent risk factors in the causation of atherosclerosis, which is the build-up of fatty plaque deposits within the walls of blood vessels. For example, high levels of serum cholesterol bound to low density lipoprotein (LDL), intermediate density lipoprotein (IDL) or very low density lipoprotein (VLDL) are known to correlate strongly with the occurrence of atherosclerosis in humans. In particular, it is known that the higher the circulating levels of cholesterol in the form of LDL, IDL and VLDL cholesterol, and the higher the circulating levels of other lipids such as triglycerides, the more likely it is that cholesterol and lipids will be deposited within the blood vessel wall and cause or contribute to atherosclerosis.
In hypercholesterolemia, for example, the increase in the blood cholesterol level is associated mainly with a rise in the concentration of LDL, IDL and VLDL cholesterol. However, the specific causes of hypercholesterolemia are complicated and varied. At least one kind of hypercholesterolemia, known as familial hypercholesterolemia, is caused by a mutation in the gene for the LDL receptor that moves cholesterol out of the blood, primarily in the liver. Much more commonly, hypercholesterolemia has been associated with genetic factors and high dietary intake of saturated fatty acids and cholesterol, resulting in elevated blood cholesterol levels. High serum triglyceride levels have also been associated with high dietary intake of fatty acids.
Reduction of hyperlipidemia, including hypercholesterolemia, results in a delayed onset of atherosclerosis and a decrease in the progression of atherosclerosis, thus reducing the risk of coronary heart disease. Atherosclerosis, the major cause of most cardiovascular disorders, is a complex process involving the blood vessel wall, many different blood elements and the immune system. Recent evidence indicates that immune-related inflammation of the Th1 type is a major factor in the initiation, progression and manifestations of the disease. Down-regulation of the Th1 type immune response has been shown experimentally to prevent the development of, and/or cause regression of, atherosclerosis.
Some forms of hyperlipidemia, including hypercholesterolemia, are potentially partially reversible with current techniques of preventive management. Taking cholesterol-lowering drugs can result in a reduction in serum cholesterol, and other drugs may lower serum triglyceride levels. Dietary therapy is usually recommended for all patients with hyperlipidemia but the effect is often not sufficient to reduce risk optimally.

Combined therapies for atherosclerosis treatment


An electrostatic discharge (ESD) circuit (12) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a parasitic bipolar transistor (202). The parasitic bipolar device is triggered by a combination of a MOSFET (204) and a string of diodes (200). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. A feedback circuit (602) ensures that MOSFET (204) is in a conductive state independent of the voltage state of the voltage supply, VDD, during an ESD event.

In the semiconductor industry, the use of electrostatic discharge protection (ESD) circuits is known. ESD circuits ensure that integrated semiconductor devices are not destroyed by static electricity during routine post-manufacture processes. However, current and foreseeable trends in the semiconductor industry are adversely impacting the effectiveness of known ESD circuits.
For instance, the use of heavily doped epitaxial (epi) substrates prevents metal oxide semiconductor (MOS) field effect transistors (FETs) and thick field oxide (TFO) devices from acting as current shunting devices. In normal, use, a heavily doped substrate is desirable. Such a substrate reduces the undesirable occurrence of "latch-up." During latch-up, two parasitic bipolar transistors formed by two complimentary MOSFETs create a feedback loop. In the feedback loop, the base of the first parasitic bipolar device is also the collector of the second device. Conversely, the base of the second device is the collector of the first device. When both of these transistors are conducting, large amounts of current can flow between two power supplies. A high current event applied to one of the terminals of the two transistors can cause the two parasitic transistors to conduct. A heavily doped epitaxial substrate acts to break the feedback loop by grounding the substrate and.sub.9 hence, the base of one device and the collector of the other.
The use of salicide bonding layers to reduce sheet resistivity (rho) also decreases the effectiveness of known ESD circuits. Here, several MOSFETs or several fingers forming a single MOSFET act as a parasitic bipolar device to provide ESD protection. Such an ESD device relies upon the "snap-back" current-voltage characteristics of a parasitic bipolar transistor. There, a current begins to flow through a bipolar transistor at a certain collector-to-emitter voltage, V.sub.tl. Thereafter, the collector-to-emitter voltage decreases as the current increases, "snapping-back" from V.sub.tl. Later, the trend reverses, causing the collector-to-emitter voltage to rise as the current also rises. Eventually, the bipolar transistor fails at another particular collector-to-emitter voltage, V.sub.t2. The low resistance of the salicide layer can cause the ultimate breakdown voltage, V.sub.t2 to be lower than the initial voltage, V.sub.tl. Such a relationship causes the first MOSFET or first finger of the MOSFET to breakdown at a voltage less than the voltage at which the second MOSFET turns on. Consequently, the protection provided by the group of MOSFETs is no greater than the protection provided by a single MOSFET.
Some known ESD circuits rely on the inherent capacitance between the voltage rails of a integrated circuit to shunt excess energy applied to one voltage rail to the other. This strategy minimizes the total number of devices necessary to provide protection. However, this strategy also fails as the capacitance of the integrated circuit drops. Consequently, one ESD circuit designed for a particular integrated circuit may not be sufficient for another circuit.
Die reduction is one of the overriding trends in the semiconductor industry. As integrated circuits shrink, the area allocated to ESD circuits shrinks. Typically, an ESD circuit is placed below an input, output, or I/O pin which the circuit protects. This area is rapidly becoming inadequate to host such circuits.
Other known ESD circuits rely on diode strings to shunt power. Unfortunately, these diode strings leak current at elevated temperatures. Furthermore, each diode's leakage increases with its temperature. Another trend in the semiconductor industry is to design and manufacture integrated circuits that consume as little current as possible and that are suitable for wide usage. Both of these goals is adversely impacted by leaky designs that are limited by environmental concerns.

Circuit for electrostatic discharge (ESD) protection