Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

A prefix search is used in networking to route and classify packets. The route to be used for a packet and its classification are determined by finding the longest matching prefix in a set. For example a packet using IPv6 (internet protocol version 6) has a 128-bit destination address. A router determines the output port over which such a packet should be routed by searching a set of variable-length binary strings to find the longest string that matches a prefix of the destination address. For classification purposes, other fields of the header, such as the port number, may also be included in the string to be matched.
To illustrate the problem of prefix search, consider the list of prefix character strings shown in FIG. 1 in alphabetical order. The principle is the same with binary strings. Given a search string, such as "cacea", the goal is to find the longest stored string that exactly matches a prefix of this string. Although a simple linear search of the list finds that this string falls between "cab" and "cad", one must scan several strings backward from this point to find that the longest matching prefix is "ca" In actual routing tables, which may contain hundreds of thousands of entries, the matching prefix may be far from the point where the linear search fails. An optimized data structure is needed to efficiently find the matching prefix.
A prior method for performing longest prefix matching employs a data structure called a trie. A trie for the prefix list of FIG. 1 is shown in FIG. 2. As shown, the trie is a tree structure in which each node of the tree resolves one character of the string being matched. Each internal node consists of a list of characters. Associated with each character is an outgoing link either to another internal node, a rectangle in the figure, or to a leaf node, a circle in the figure. A slash at the start of a node indicates that a prefix leading to that node with no additional characters is part of the list. Each leaf node holds the result data associated with the prefix leading to that leaf node, and in the figure, the leaf nodes are labeled with these prefixes. The result data might, for example, be the output port associated with a data packet and a flow-identifier.
To search the trie, one starts at the root node, node 1 in the figure, and traverses the tree by following the outgoing link at each node corresponding to the next character in the string to be matched. When no matching outgoing link can be found, the longest matching prefix has been found. For example, given the string "cacea" we start at node 51. The "c" directs us to node 54. The "a" directs us to node 58. As we cannot find a match for the next character, "c", at node 58, we follow the link associated with the slash to the leaf node associated with the longest matching prefix, "ca". Note that if prefix "ca" were not in the list, we would need to backtrack at this point to node 54 for prefix "c".
Another prior method for prefix matching is to perform binary search on a table. However, as described by Radia Perlman, Interconnections, Bridges and Routers, Addison Wesley, 1992, pages 233-239, and shown in FIG. 3, since binary search will find the closest matching string, rather than the longest matching prefix, we must make two modifications to the list to apply this technique. First, we insert two entries for every entry in the list that encloses other entries, that is, that would serve as a longest matching prefix for another prefix in the list but for the other prefix itself being in the list. One of those entries is terminated by the symbol 0, which comes alphabetically before all characters, and one by the symbol 1, which comes alphabetically after all characters. These two entries act as parentheses enclosing all entries that contain the prefix. Second, we attach to each entry in the list not ending in a 0 a pointer to the nearest enclosing entry. FIG. 3 shows the list of FIG. 1 augmented in this manner. Note that the prefix "ca" has been replaced by the two entries "ca0" and "ca1" that bracket all entries containing the prefix "ca" and that all of these entries have a pointer back to "ca0".
To search the augmented list of FIG. 3 for the longest matching prefix, one searches for a string equal to a prefix of the target or the alphabetically closest pair of strings. Strings ending in "0" or "1" never exactly match a prefix of the target string because "0" and "1" do not match any character of the target string. If the search finds an exact prefix of the target string, the result data associated with the string is retrieved. Otherwise, the search found the closest pair of stored strings, Sa and Sb. In this case there are three possibilities:
1. If Sa ends in a "0" symbol, then the longest matching prefix is this string with the "0" removed.
2. If Sb ends in a "1" symbol, then the longest matching prefix is this string with the "1" removed.
3. Otherwise, an enclosing pointer from Sa is followed to find a string ending in a "0" symbol which encloses Sa and the nearest match is that string with the "0" symbol removed. For example, a search for "cacea" will end between "cab" and "cad". Since this is not an exact match, "cab" does not end in "0", and "cad" does not end in "1", the pointer from "cab" is followed back to "ca0" giving the longest matching prefix, "ca". Similarly a search for "cb" will end between "ca1" and "cc" and follow the pointer from "ca1" back to the common prefix, "c".


It has been shown that the formulation of phosphonic compound (ethephon) with sulfuric acid increases the efficacy and efficiency of ethephon and the speed of the effect of the ethephon. It was theorized that the effect that is shown by the mixture of ethephon and sulfuric acid could be achieved using another acid. The effect was demonstrated using muratic acid. All acids that reduce the pH of the spray carrier are claimed in this patent as synergist for phosphonic acid compounds such as ethephon.

Phosphonic compounds (ethephon) have been used for years as plant growth regulators, harvest aids and defoliation products. Atwater et.al has shown that when ethephon is formulated in sulfuric acid and adduct the Plant Growth Regulated (PGR) effects are increased. The present invention shows that the increased in the PGR effect shown by Atwater occurs with other acids as well as with the sulfuric acid combinations claimed in the Atwater patent(s).

Compositions comprising a phosphonic compound, and acids as methods for plant growth and regulatory effects


An auger stabilizer includes a rigid elongated body having a first end and a second end. The length of the body is adjustable between a retracted transport position and an extended drilling position. A pair of spaced apart wheels are attached at the second end of the body. A split body with two halves connected by fasteners is used to pivotally attach the first end of the body to a handle of an auger. When the body is in the extended drilling position, the pair of spaced apart wheels roll along a ground surface away from the auger as the handle of the auger descends and the pair of spaced apart wheels act to stabilize the handle of the auger against reactive torque.

Augers are commonly used to dig holes, such as for posts. These augers have a gas powered engine that drives a depending auger screw. Handles are provided to allow either one or two people to operate it. A problem often encountered is reactive torque. U.S. Pat. No. 5,007,492 teaches a safety stabilizer to help counteract the twisting motion on the handles caused by reactive torque.

This patent is subject to a terminal disclaimer.


A pressure sensor apparatus is disclosed. The pressure sensor apparatus includes a bulk acoustic wave (BAW) die having a die interface side and a pressure contact side, a sensor BAW resonator and a reference BAW resonator disposed on the die interface side of the BAW die, a control circuit die coupled to the die interface side of the BAW die via an attachment layer, and an extended opening on the pressure contact side that extends into a depth of the BAW die and is generally aligned with the sensor BAW resonator, the extended opening being configured to translate an external pressure on the pressure contact side onto the sensor BAW resonator.

A bulk acoustic wave (BAW) resonator device includes a piezoelectric material sandwiched between two electrodes and acoustically isolated from the surrounding medium. Common materials used for the piezoelectric material are aluminum nitride and zinc oxide. A typical BAW resonator device resonates in the frequency range of roughly 100 MHz to 10 GHz. BAW resonator devices can be used for sensor applications because when a BAW resonator device is put under mechanical pressure, its resonance frequency will shift. Applying a voltage or temperature change to a BAW resonator will also result in a shift of its characteristic frequency.


Performing power control by determining a maximum required signal-to-interference plus noise ratio for a nominal packet size of a received data signal, wherein the maximum required signal-to-interference plus noise ratio corresponds to a quantity of physical resource blocks used for the nominal packet size of the data signal. A received signal-to-interference plus noise ratio of the received data signal is compared with the maximum required signal-to-interference plus noise ratio. In response to the received signal-to-interference plus noise ratio exceeding the maximum required signal-to-interference plus noise ratio, power control is performed for the data signal to reduce the received signal-to-interference plus noise ratio.

The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
3GPP third generation partnership project
AWGN additive white Gaussian noise
BLER block error rate
C/I carrier-to-interference ratio
DL downlink
ECP extended cyclic prefix
E-UTRA evolved universal terrestrial radio access
eNB or eNodeB evolved node B/base station in an E-UTRAN system
E-UTRAN evolved UTRAN (LTE)
GBR guaranteed bit-rate
ID identification, identifier
IP internet protocol
LTE long term evolution
LTE-A long term evolution advanced
MCS modulation and coding scheme
PC power control
PHR power headroom report
PRB physical resource block
PUSCH Physical Uplink Shared Channel
QAM quadrature amplitude modulation
RF radio frequency
RSSI received signal strength indicator
SINR signal-to-interference plus noise ratio
TPC transmitter power control
TBS transport block size
UE user equipment (e.g. mobile terminal)
UL uplink
UMTS universal mobile telecommunications system
UTRAN universal terrestrial radio access network
VoIP voice over IP
In Release 10 of the Third Generation Partnership Project (3GPP), physical uplink shared channel (PUSCH) transmit power for a user equipment (UE) in a subframe i for a serving cell c is defined by the following formula (see 3GPP TS 36.213 V10.3.0 (2011-09), Section 18.104.22.168):
                              (      1      )                                    P                      PUSCH            ,            c                                            (          i          )                    =              min                          {                                                                                P                                              CMAX                        ,                        c                                                                                (                      i                      )                                                        ,                                                                                10                                                                                log                        10                                                                                (                                                                              M                                                          PUSCH                              ,                              c                                                                                (                            i                            )                                                                          )                                                                              +                                                            P                                              O_PUSCH                        ,                        c                                                                                (                      j                      )                                                        +                                                                                α                        c                                                                                (                        j                        )                                                              ·                                          PL                      c                                                        +                                                            Δ                                              TF                        ,                        c                                                                                (                      i                      )                                                        +                                                            f                      c                                                                                (                      i                      )                                                                                }                      ,
where PCMAX,c(i) denotes a maximum transmission power according to a UE power class in subframe i, and MPUSCH,c(i) is the bandwidth of the PUSCH resource assignment expressed as a number of resource blocks valid for subframe i and serving cell c. The transmission power of the UE increases in proportion to MPUSCH,c(i). PLc is the downlink path loss estimate calculated in the UE for serving cell c in dB and α(j) denotes a scaling factor, which is determined at higher layers in consideration of a difference between uplink and downlink channels established by a cell formation.
PO—PUSCH,c(j) is a parameter composed of the sum of a component PO—NOMINAL—PUSCH,c(j) provided from higher layers for j=0 and 1 and a component PO—UE—PUSCH,c(j) provided by higher layers for j=0 and 1 for serving cell c. A Modulation and Coding Scheme (MCS) or Transport Format (TF) compensation parameter ΔTF,c(i) can be defined as follows:ΔTF,c(i)=10 log10((2BPRE·K,−1)·βoffsetPUSCH)  (2),
where KS is a cell-specific parameter.
Power control based on Ks=1.25 attempts to limit the received carrier-to-interference (C/I) ratio in such a way that the C/I received at the eNB is specific to the particular MCS in use. However, power control based on Ks=1.25 has not proved to be very popular and is not even supported by all UEs. Thus it is not a complete commercial solution to the problem of limiting the interference in the system for small packet users (such as VoIP users) or other users with known packet sizes.

Performing power control based on nominal packet size


A secondary pool of VMs is used to run secondary services or jobs, which may be evicted upon failure of a corresponding primary VM. Upon detection of a failure of a primary resource, the secondary services or jobs are evicted from secondary pool resources, and the secondary pool resources can be automatically allocated to the jobs of the failed primary resource. In this regard, a secondary job may be thought of as a preemptible job and comprises services or jobs that are lower priority than the service or job on the primary resource. By using computing resources in the secondary pool to run secondary or preemptible jobs, this technology makes use of what would be otherwise idle resources. This beneficially avoids having to allocate additional and separate computing resources for secondary jobs, leads to more efficient use of network resources, and reduces costs.

Multi-single-tenant (MST) services run individual service instances in an isolated environment, such as in a separate virtual machine (VM). Cloud SQL is an example of such a service. Since individual service instances run on a single VM, the failure of the VM will result in unavailability of the service instance. Failures may be planned or unplanned, but either requires the VM to be taken down. An example of a planned failure is VM updates, such as critical security patches to the kernel. A control plane of the service may be able to detect VM failures, and failover to a newly created VM. For planned failovers, the unavailability time for the VM may be reduced by re-creating the new VM before taking down the old one. However, both approaches are prone to VM stockouts, where users are unable to create VMs due to lack of capacity of the requested type of machine in the target zone. This is unacceptable as it renders customer's existing service instances unavailable for an indefinite period of time.

Cost-efficient high-availability multi-single-tenant services


To provide an electron source including: a wiring board having: a substrate provided with a groove on its surface; a first conductive member which is arranged along the groove in the groove; and a second conductive member which is arranged above the first conductive member crossing the first conductive member; and an electron-emitting device which is arranged on the wiring board and is electrically connected to the first conductive member and the second conductive member; wherein a particle is arranged between the first conductive member and an inner wall of the groove.

1. Field of the Invention
The present invention relates to an electron source, an image display apparatus, an image reproducing apparatus, a wiring board, and an electronic device.
2. Description of the Related Art
A flat panel display such as an LCD and a PDP is a display apparatus having a plurality of pixels arranged in a planar state. By selectively applying a voltage to an electron-emitting device located on each cross portion of a plurality of wirings (matrix wirings) arranged in a matrix or in the vicinity of each cross portion thereof, a flat panel display using an electron-emitting device controls emission of the electron from each electron-emitting device and displays an image.
The matrix wiring is formed by a scan line to which a scan signal is applied and a signal line to which a modulation signal is applied. In recent years, there is a great demand for a display which can display a high-resolution image. Therefore, it is necessary for the wiring to be made narrower, and on the other hand, it is necessary for the film of the wiring to be thick in order to prevent increase of resistance of the wiring due to narrowing of the wiring. In addition, a display which can be made more simply has been required.
As one of solutions for such a request, it is disclosed in Japanese Patent Application Laid-Open No. 2005-216639 and Japanese Patent Application Laid-Open No. 2004-342547 to put a metal wire having a large cross section and a low resistance which has been prepared in advance in a groove disposed on the surface of a substrate and use this for the wiring.

Electron source, image display apparatus, image reproducing apparatus, wiring board, and electronic device


A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

The present invention relates generally to the field of computer processors and more specifically to increasing throughput in simultaneously multi-threaded processors.
A computer processor is the heart of any computer system. They are responsible for processing the instructions that make all of the functions of the computer possible. Computer processors are also called central processing units (CPU's) and microprocessors. A pipelined computer processor has multiple stages that each instruction must traverse during the processing phase. An exemplary five stage pipelined processor contains the following stages: fetch, decode, memory access, execute and write-back. During the fetch stage, an instruction is fetched from a register, or buffer. The instruction is decoded in the decode stage to determine the type of operation to be conducted, and what operand(s) are needed to complete the operation. The required operands are retrieved during the memory access stage and execution of the instruction occurs during the execute phase. The result of the executed instruction is then written back to memory during the write-back stage. Many processors have more than five stages and some processors have more than one pipeline. However, some features of pipelined processors are the same for all pipelines. Specifically, once an instruction enters a pipeline any stall caused by the instruction will cause the entire pipeline to stall. When the pipeline is stalled, no output is produced and performance drops. Thus, preventing pipeline stalls is an important factor in achieving optimal performance in microprocessors.
Microprocessors run on a timing schedule that is coordinated by a clock. The clock provides timing signals referred to as cycles. Movement of instructions, operands and results are preferably completed upon each clock cycle. A given stage within a pipeline, such as the execute stage, may take more than one clock cycle to complete. However, the execute stage is preferably broken into multiple sub-stages so that at the end of each clock cycle some output is produced and allowed to enter the next stage. In this way, the microprocessor produces some output at the end of each clock cycle. Both clock cycle and clock frequency can be used to describe the speed of the processor. A computer with a short clock cycle will have a high clock frequency. Generally, the higher the clock frequency the faster the computer, or more accurately, the faster the computer is able to process instructions.
A thread is a line, or stream, of computer instructions that when processed achieves some objective of the computer or the computer user. Simultaneously multithreaded processors allow for the execution of two or more potentially independent instruction streams concurrently. While only one instruction can occupy any one stage of a pipeline at a time, having instructions from other threads ready for processing increases system performance. To make most efficient use of the available hardware and avoid duplication of function, some pipeline resources are shared among all threads. For a given thread to occupy a shared resource, its instruction stream must at some point be merged with the instruction streams of the other threads. For the purpose of this application, the act of an instruction from any given thread merging into a shared pipeline resource is defined as "issue". After an instruction issues, a data dependency could cause it to stall in a shared resource until the dependency is resolved, stalling all threads which require the same resource. The impact of this problem is magnified in high frequency designs because the pipeline depth requires that the decision to issue a particular instruction be made one or more cycles before operand availability is known. This increases the chance of a dependent instruction stalling in a shared resource awaiting required operands. If instead, issue was delayed until operand availability was known, overall system performance would be negatively affected in cases where the operands would have been ready at the time the dependent instruction required them. Single threaded performance would also suffer due to the increased latency, while multithreaded performance and/or efficiency would suffer due to not utilizing every possible opportunity to issue an instruction from a given thread.
Prior attempts to remedy this problem involved blocking a thread with the dependency from issuing until its operand data is ready for forwarding. This was a suitable solution for lower frequency designs, but is not optimal for high frequency designs which must make the issue decision one or more cycles before operand availability is known due to the pipeline depth. Using this prior method in processors with a high clock frequency introduces penalty cycles to a specific thread's overall latency each time a dependency is encountered, since operand data can not be used as soon as it becomes available.

Speculative instruction issue in a simultaneously multithreaded processor

International Business Machines Corporation


A non-volatile semiconductor memory device comprises an area in which only one rewriting is possible and an area in which rewriting is possible repeatedly. A control circuit generates a high voltage from a boosting circuit and operates a writing circuit to write data in the rewritable area whose address designated by an address register/decoder. The control circuit allows writing of data into the area in which only one rewriting is possible by the writing circuit in response to an external signal. Therefore, even if the writing mode is set influenced by the unstable state of the power supply, destruction of the data in the area in which only one rewriting is possible can be prevented.

1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices and, more specifically, to a non-volatile semiconductor memory device having an electrically rewritable non-volatile semiconductor as a memory element.
2. Description of the Background Art
In an EEPROM as an electrically rewritable non-volatile semiconductor memory device, a high voltage of 20V is applied to a memory cell corresponding to a binary information in accordance with a writing mode signal applied from a controller, and threshold value of the memory cell is changed to receive charges, whereby the information is written. Methods for applying high voltage to the memory cell comprise a method of applying the voltage from a voltage source directly to an external terminal provided in each memory cell, and a method of applying a normal voltage 5V which is boosted by a boosting circuit provided in an IC to apply the boosted voltage. One example of the latter method is disclosed in Japanese Patent Laying-Open No. 63-7599.
FIG. 5 is a block diagram showing a whole structure of a conventional EEPROM. Referring to FIG. 5, a clock pulse is applied to an input register 101 and data and address are serially inputted thereto. The input register 101 serially reads the data and the address in response to the clock pulse, loads the data in a data register 103 and loads the address to an address register/decoder 104. The clock pulse is also applied to a timing generation circuit 102, which generates timing signals in response to the clock pulse to apply the same to a mode register 105. The mode register 105 is provided for loading a writing mode signal or an erasing mode signal. The writing mode signal or the erasing mode signal loaded in the mode register 105 is applied to a control circuit 1.
The data loaded in the data register 103 and the address signals loaded in the address register/decoder 104 are applied to a memory cell 100. A writing mode signal or an erasing mode signal is applied from the control circuit 1 to the memory cell 100. The writing mode signal is also applied to a boosting circuit 2 and a writing circuit 111. The boosting circuit 2 boosts a supply voltage of +5V to a high voltage of 20V in response to the writing mode signal or the erasing mode signal to apply the same to the memory cell 100 through the writing circuit 111. When the high voltage is applied to a cell of the designated address, the memory cell 100 writes the information in the cell. A sensing circuit 101 amplifies the information read from the memory cell 100 to apply the same to an output circuit 109.
FIG. 6 is a specific block diagram of the memory cell portion shown in FIG. 5, FIG. 7 is a specific electric circuit diagram of the boosting circuit shown in FIG. 6, and FIG. 8 is a specific electric circuit diagram of a high voltage switch.
Referring to FIGS. 6 to 8, the portions near the memory cell will be described in more detail. FIG. 6 shows an example of a memory matrix MA in which memory cells M11 . . . M1n+1, M21 . . . M2n+1, M31 . . . M3n+1, M41 . . . M4n+1 arranged in a matrix of two columns x 2 rows for rewriting n bit data at one time. The memory cell M11 comprises a selective transistor and a memory transistor. Other memory cells have the same structure. The selective transistor of each of the memory cells M11 . . . M1n+1, M21 . . . M2n+1, M31 . . . M3n+1, M41 . . . M4n+1 is connected to each other in the row direction by the word lines W1, W2 and in the column direction by digit lines D11 . . . 1n, D21 . . . D2n+1. High voltage switches 71 and 72 are connected to the word lines W1 and W2, high voltage switches 52 . . . 5n+1 are connected to the digit lines D11 . . ., D1n+1 and high voltage switches 62 . . . 6n+1 are connected to the digit lines D21 . . . D2n+1. Transistors 81 and 82 transmit high voltage on a control gate line CG1 to the control gate of the memory cells M11 . . . M1n+1, M21 . . . M2n+1 and transistors 83 and 84 transmit high voltage on a control gate line CG2 to the control gates of the memory cells M31 . . . M3n+1, M41 . . . M4n+1. Drains of the transistors 81 and 82 are connected to the high voltage switch 51, and the drains of the transistors 83 and 84 are connected to the high voltage switch 61.
The control circuit 1 applies a controlling signal for generating a high voltage from the boosting circuit 2 in the writing mode and in the erasing mode to the boosting circuit 2. The boosting circuit 2 comprises an oscillator 21 as shown in FIG. 7. The oscillator 21 starts the oscillating operation in response to the controlling signal from the control circuit 1. The boosting circuit 2 comprises n channel transistors 23 connected in series with the gates and drains connected to each other and capacitors 24 connected between the source of each of the transistors 23 and the output of the oscillator 21 or an output of an inverter 22 inverting the output from the oscillator 21. The boosting circuit 2 is generally called a charge pump, which boosts the output from the oscillator 21 by the combination of the N channel transistors 23 and the capacitors 24 to apply a high voltage to the high voltage switches 51, 52 . . . 5n+1, 61, 62 . . . 6n+1, 71 and 72.
The control circuit 1 applies a control signal in the writing mode and in the erasing mode to one input end of each of the AND gates 31 and 41. An address signal Y1 is applied to the other input end of the AND gate 31, and an address signal Y2 is applied to the other input end of the AND gate 41. Data D1 . . . Dn are applied to one input end of the AND gates 32 . . . 3n+1, respectively, and the address signal Y1 is applied to the other input end. The data D1 . . . Dn are applied to one input end of the AND gates 42 . . . 4n+1, respectively, and the address signal Y2 is applied to the other input end. Address signals X1 and X2 are applied to the high voltage switches 71 and 72.
Referring to FIG. 8, the structure of the high voltage switch 50 will be described in the following. An output from any one of the AND gates 31, 32 . . . 3n+1, 41, 42 . . . 4n+1 and X1, X2 shown in FIG. 6 is applied to the inverter 501. The output from the inverter 501 is applied to the gate of N channel transistor 502 which has its source connected to the ground and its drain connected to the drain of an N channel transistor 503 and to the gate of an N channel transistor 504. The gate and the source of the N channel transistor 503 are connected to one end of a capacitor 505 and to the source of the N channel transistor 504. A high voltage is applied from the boosting circuit 2 to the drain of the N channel transistor 504, while the oscillation output from the oscillator 21 is applied to the other end of the capacitor 505. A high voltage is outputted from the drain of the N channel transistor 502.
Operation of a conventional EEPROM will be described in the following. The high voltage switch 50 is a switching element for switching a high voltage (about 20V) for writing into the EEPROM by peripheral 5V signals. When a "H" level (5V) signal is inputted to the gate of the N channel transistor 502, the N channel transistor 502 is turned on and a "L" level signal is outputted from the drain thereof. When a "L" level (0V) signal is inputted to the gate of the N channel transistor 502, the N channel transistor 502 is turned off, and the capacitor 505, and N channel transistors 503 and 504 function as a last stage of the boosting circuit 2 to output a high voltage.
The operation of erasing and writing data in the memory cell M11 which is at the first row and first column of the 2.times.2 memory cell array MA shown in FIG. 6 will be described in the following as an example. The EEPROM has two modes, that is, the erasing mode and the writing mode. At first, the erasing mode will be described. The erasing of data is carried out by applying a high voltage of about 20V to the gate (generally called a control gate) of a memory transistor of the memory cell M11. A control signal for starting oscillation is applied from the control circuit 1 to the oscillator 21 of the boosting circuit 2. The oscillator 21 starts oscillation in response to the control signal and the boosting circuit 2 generates a high voltage. On this occasion, the control signal E outputted from the control circuit 1 is set to the "H" level, and the data D1 to Dn are set to the "L" level. Now, the information in the memory cell D11 at the first row and first column is to be erased, so that the address signal X1 is set to the "H" level, X2 is set to the "L" level, Y1 is set to the "H" level and Y2 is set to the "L" level. Consequently, the AND gate 31 conducts, the high voltage switch 51 sets the control gate signal CG1 at 20V and the high voltage switch 71 sets the word signal W1 at 20V. Consequently, the transistor 81 is rendered conductive, a high voltage is applied to the control gate of the memory cell M11, whereby the data is erased.
Writing of the data is carried out by applying a high voltage of 20V to the drain of a memory transistor in the memory cell. Namely, in the writing mode, the control signal E is set to the "L" level and the data D1 to Dn are set at respective values. The address signals X1, X2, Y1 and Y2 are set in the same manner as in the erasing mode. When the control gate signal CG1 is kept at the "L" level and the data D1 to Dn are at the "L" level, the high voltage is not transmitted to the digit signal D11, so that writing of data to the memory cell is not carried out. When the data D1, for example, is set at the "H" level, the high voltage is transmitted to the digit signal D11, so that writing of data to the memory cell M11 is carried out.
When the EEPROM shown in FIG. 6 is used as a memory element, there is a possibility of the data stored in the EEPROM being destroyed when the power supply is turned on/off or the applied voltage is stopped for an instant. More specifically, the power is supplied through an external terminal to the boosting circuit 2. When the high voltage is applied to the memory cell and the signal outputted from the controller becomes unstable due to the turning on/off the power supply or the instant stoppage, the memory device may be erroneously set to the writing mode. When a boosting circuit 2 such as shown in FIG. 7 is provided in the memory device and the signal outputted from the controller becomes unstable due to the turning on/off of the power supply or the instant stoppage, the writing mode may be erroneously set.
Electrical rewriting of data is possible in an EEPROM. However, in most cases, they are used as ROMs, that is, only a portion is used for writing data and other regions are used only for reading with the data once written being maintained as they are. Therefore, various measurements have been proposed in order to prevent fatal damage of the system derived from the destruction of the written data by the above described causes.
For example, measurements such as providing pull up and pull down resistances to an input terminal, provision of a power supply detecting circuit inside or outside of the IC so as to turn off the main power supply after the external signal lines are established, and so on have been proposed. However, these measurements are not enough to prevent erroneous writing.

Non-volatile semiconductor memory device having an area responsive to writing allowance signal


A method for producing optoelectronic components including A) providing a growth substrate with a semiconductor layer arranged thereon that produces a zone which is active during operation, B) applying separating structures on the semiconductor layer, C) applying a multiplicity of copper layers on the semiconductor layer in regions delimited by the separating structures, D) removing the separating structures, E) applying, a protective layer at least on lateral areas of copper layers, F) applying an auxiliary substrate on the copper layers, G) removing the growth substrate, H) singulating a composite assembly comprising the semiconductor layer, the copper layers and the auxiliary substrate to form components which are separated from one another.

It has been observed that, in the production of optoelectronic components comprising a copper substrate (which serves, in particular, as a heat sink and for mechanical stabilization), a very high number of rejects in respect of non-functional components, are produced, particularly if the optoelectronic components are light emitting diodes or laser-diodes.
Therefore, it could be helpful to provide a method with which a smaller number of rejects in respect of non-functional optoelectronic components are obtained.

Method for producing an optoelectronic component, optoelectronic component, and component arrangement having a plurality of optoelectronic components


This invention relates to an apparatus for causing a pool cue ball to jump and thereby avoid an opponent's safety blocking ball utilizing a cue stick of approximately one half of the standard length, and having a plurality of apertures within a carrier in a radial slot in the handle end of the stick wherein selected weights may be secured to adjust the weight of the stick for different shooting styles and for different weights of cue balls.

Numerous designs for pool cues and billiard cues are well known in the art. These designs include the metallic billiard cue of Lindley, U.S. Pat. No. 1,609,026; the weighted billiard cue of Waldo, U.S. Pat. No. 3,342,489; the billiard cue having an adjustable center of gravity of Molis, U.S. Pat. No. 3,372,932; and the weighted billiard cue of Johnson, U.S. Pat. No. 3,468,538. These references, however, teach variations of the standard cue stick and do not meet the unique requirements of a cue stick to be used for jump shots. This is of course due to the fact that jump shots have not traditionally been used in billiards and pool. However, the use of blocking shots in safety play has become more popular recently, with a resulting increase in the use of jump shots to defeat the block.


A moisture sensing system for a refrigerant flow of a heating, ventilation and air conditioning (HVAC) system includes a moisture sensor including a color change material sample located in a refrigerant flow of the HVAC system. The color change material sample configured to change color as an indication of a moisture level of the refrigerant flow. A color sensor is in optical communication with the moisture sensor and is configured to sense a color of the color change material and communicate the sensed color to an HVAC system controller. A method of operating an HVAC system includes exposing a condensing a color change material sample to a flow of refrigerant and sensing a color of the color change material via a color sensor. The color is indicative of a moisture level of the flow of refrigerant. The sensed color is communicated to an HVAC system controller.

The subject matter disclosed herein relates to heating, ventilation and air conditioning (HVAC) systems. More specifically, the subject matter disclosed herein relates to chillers.
As regulatory & industry trends continue to drive towards replacement of conventional HFC's like R134a, of particular interest are the class of "low pressure refrigerants", i.e. refrigerants that are near, or below atmospheric pressure at the boiling temperatures in a chiller. One example of a "low pressure refrigerants" is R1233zd. Numerous other low pressure refrigerants are known to those of ordinary skill in the art. While low pressure refrigerants have numerous known advantages, they, however, also tend to absorb moisture, which can inhibit chiller performance.
Because the low pressure chiller system operates at below atmospheric pressure, ambient air can intrude into the chiller and, with it, bring moisture, which is absorbed by the refrigerant, thereby degrading chiller performance and potentially causing other problems. The chiller system is typically monitored for moisture level in the refrigerant, and moisture is periodically dried or purged from the chiller system. Chiller systems typically employ a sight glass with a color change material exposed to the refrigerant stream, with the color indicating a moisture level of the refrigerant. This sight glass indicator requires operators of the chiller periodically physically check the sight glass for moisture content of the refrigerant.

Moisture sensing system for heating, ventilation and air conditioning systems


A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

1. Field of the Invention
This invention relates to ADCs and more specifically to a clock-to-clock auto-ranging ADC that operates directly on the IF band.
2. Description of the Related Art
Known ADCs are used to convert a baseband analog signal (0-500 KHz) into an equivalent digital signal by sampling the baseband signal at at least twice the signal frequency to satisfy the Nyquist criterion and then quantizing the sampled values with a fixed number of bits. The baseband signal may be oversampled 16 to 128 times to achieve a processing gain and to ease the tolerances on filters and amplifiers that are used in conjunction with the ADC.
Known communications systems modulate different high frequency sinusoidal carrier signals with respective baseband signals, broadcast them over the communications channel, and demodulate them at the receiver. This reduces the required size of the transmitter and receiver antennas and allows simultaneous transmission of multiple baseband signals. At the transmitter, the baseband signals are modulated up to the different IF bands, upconverted to the different RF channels, and transmitted over the channel. At the receiver, multiple mixdown stages are used in conjunction with narrow band filters to downconvert the RF signal to, for example, 71 MHz, 10.7 MHz and then to baseband and to select a particular baseband signal. The baseband signal is then input to the ADC, which produces the equivalent digital signal.
As a result of the transmission medium, the received signal level may vary over a relatively wide amplitude range. For example, the signal may vary by 30 dB within its 90 dB range during a data burst. If this signal were input directly to a fixed-range ADC, as the signal moved over the 90 dB range the ADC would at times saturate and clip the signal and at other times only coarsely resolve the signal. Thus, some known ADCs employ tracking circuitry that gains/attenuates the signal prior to digitizing such that the dynamic range of the signal approximately matches that of the fixed-range ADC. However, the tracking circuitry exhibits a time delay such that the signal may clip or be coarsely resolved for a period of time before the gain/attenuation can be adjusted. Furthermore, after the gain/attenuation is adjusted the signal must settle for some period of time. This will introduce distortion and a loss of signal sensitivity.
A well known approach is to pass the baseband signal through multiple gain paths in which each gain path has a different gain/attenuation buffer and its own fixed-range "flash" ADC. The DSP looks at the digital signal coming out of the highest gain channel. If the digital signal is saturated, the DSP steps down to the next highest gain channel and so forth until it identifies an unsaturated signal. This causes a time delay of several clock cycles before the proper gain/attenuation level is attained, during which the digital signal is saturated and information may be lost. Furthermore, the signals gain paths cannot be changed during the burst because the equalization would be severely compromised due to phase and gain differences between gain paths. As a result, the receiver is very hardware intensive.
Iwamatsu, U.S. Pat. No. 4,851,842, discloses an ADC that detects the level of the baseband input signal and uses the detected level to adjust the gain of its variable gain amplifier. As shown in FIG. 2 and described in col. 3, lines 22-27, when the detected level crosses one of the preset levels there is a delay of several cycles of the baseband input signal before the gain of the amplifier is adjusted and the signal has settled. Iwamatsu calls this delay the "insensitive region," in which the signal could saturate the ADC thereby clipping the signal or underrange the ADC thereby providing only coarse resolution.
As shown, the insensitive region includes approximately eight baseband cycles. Since the ADC's sampling rate must satisfy the Nyquist criterion, the insensitive region corresponds to a minimum of sixteen cycles of the digital output signal, and potentially many more if the ADC oversamples the baseband signal. Thus, every time the gain level is adjusted, there is a lag of at least sixteen clock cycles in the digital signal before the appropriate gain level is applied and the analog signal settles, during which the digital signal can either saturate or only coarsely resolve the baseband analog signal.
Another drawback of Iwamatsu is that the level detection circuit adjusts the resistance value of the feedback circuitry around the amplifier to set its gain. As a result, the bandwidth and phase of the resulting digital signal may be a function of the selected gain level. Thus, as before, equalization may be compromised.

Intermediate frequency (IF) sampling clock-to-clock auto-ranging analog-to-digital converter (ADC) and method


A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A multiway cache includes a single array partitioned into a plurality of cache slots and a directory, both directory and cache slots connected to the same data bus. A first cache slot is selected and accessed; and then corresponding data is accessed from alternate slots while searching said directory, thereby reducing the latency penalty for cache access.

1. Technical Field of the Invention
This invention generally relates to set associative caches for computer systems, and more particularly to reducing the latency penalty for cache access.
2. Background Art
The use of caches for performance improvements in computing systems is well known and extensively used. See, for example, U.S. Pat. No. 5,418,922 by L. Liu for "History Table for Set Prediction for Accessing a Set Associative Cache", and U.S. Pat. No. 5,392,410 by L. Liu for "History Table for Prediction of Virtual Address Translation for Cache Access", the teachings of both of which are incorporated herein by reference.
A cache is a high speed buffer which holds recently used memory data. Due to the locality of references nature for programs, most of the access of data may be accomplished in a cache, in which case slower accessing to bulk memory can be avoided.
In typical high performance processor designs, the cache access path forms a critical path. That is, the cycle time of the processor is affected by how fast cache accessing can be carried out.
In order to achieve increased performance, microprocessors are being designed with ever-faster clock rates. Keeping the microprocessor supplied with instructions and data from memory becomes more difficult as processor speeds increase, and it is becoming more common to implement Level 2 (L2) caches using SRAMS operatively coupled to the microprocessor. The least expensive SRAMS are the industry-standard, commodity-priced modules which are typically 64K.times.18-bit or 256K.times.18-bit devices. Several of these SRAMs are usually used in parallel to create an external L2 cache. An example of a pipelined SRAM is the IBM 32K.times.36 & 64K.times.18 SRAM 03H9040, described in IBM publication SA 14-4659-03, revised 7/96 at page 3 of 21.
Until now, the vast majority of these L2 caches have been direct-mapped, or 1-way associative, due to the simplicity of such a design, and more importantly, due to the fact that the limited number of signal pins on a typical microprocessor makes it difficult to implement a multi-way associative cache using standard SRAMS. There is, therefore, a need in the art for a circuit design which enables a multiway off-chip cache to be implemented with standard SRAMS.
There are two common ways to implement a multiway cache.
The first way is to implement the cache as a set of caches operating in parallel, with the desired data being obtained from one of the caches based on information obtained from a directory which is usually accessed at the same time as the cache. A two-way cache, for example, would be implemented-with two parallel arrays, and the output of one array would be selected based on matching an entry in one of the directories associated with the cache. This method usually results in the best performance, because the cache and directory accesses are done at the same time, resulting in the minimum latency for obtaining the desired data. The major disadvantage, especially as it relates to microprocessor external caches, is that a data bus from each array must be connected to the microprocessor, unless some sort of external multiplexer (which increases latency and adds cost) is used.
A second approach for implementing a multiway cache is to use a single array, and partition it to contain the various cache sets, or slots as they are sometimes called. However, this usually means that the directory must be searched before the array access can begin, because the slot must be known in order to generate the array address bit(s) which correspond(s) to the desired cache slot. The advantage of this method is that only one data bus need be connected to the SRAMs to access data. The disadvantage is that access latency is increased because the directory must be searched before beginning the cache access.
It is, therefore, an object of the invention to avoid increased access latency in multi-way cache accessing due to the need to search a directory before beginning the cache access.

Multiway associative external microprocessor cache

International Business Machines Corporation


The invention relates to a device for cooling a housing of a gas turbine and/or of a combustion chamber, in particular of a gas turbine, comprising: a cooling gas supply device with a cooling gas outlet, out of which a cooling gas stream flows when the cooling gas supply device is in operation, and with a cooling gas inlet, via which the cooling gas stream flows back to the cooling gas supply device when the cooling gas supply device is in operation; and a cooling gas path which is led through the housing in the circumferential direction of the latter and which connects a first housing connection to a second housing connection. So that a circumferential temperature difference of the housing can be set independently of an average temperature of the housing, the cooling device is equipped with a switching device for reversing the flow direction.

The housing of a gas turbine or of a gas turbine combustion chamber has to be cooled when the gas turbine is in operation. For this purpose, it is customary to lead a cooling gas path through the housing in the circumferential direction of the latter. Such a cooling gas path in this case connects a first housing connection, which serves, for example, as a cooling gas inlet, to a second housing connection, which serves, for example, as a cooling gas outlet. The cooling gas, when flowing through the cooling gas path, heats up. The housing correspondingly possesses a lower temperature at the cooling gas inlet than at the cooling gas outlet. This means that a circumferential temperature difference occurs in the circumferential direction of the housing. This circumferential temperature difference should not overshoot a predetermined maximum value when the gas turbine is in operation, in order to avoid damage to the housing due to thermal stresses. Furthermore, an average temperature of the housing also should not overshoot a predetermined maximum value, in order to avoid damage to the housing.
It has been shown, however, that, in conventional housing cooling, there is an interaction between the average temperature and the circumferential temperature difference of the housing. When the average temperature is reduced, for example by the lowering of the cooling gas temperature at the cooling gas inlet, this automatically leads to an increase in the circumferential temperature difference. Conversely, a raising of the average temperature, for example by an increase in the cooling gas inlet temperature, automatically leads to a reduction in the circumferential temperature difference. In conventional housing cooling, therefore, the setting of the circumferential temperature difference and the setting of the average temperature are always a compromise between a comparatively high circumferential temperature difference and a comparatively high average temperature.

Device and method for cooling a housing of a gas turbine or a combustion chamber


A method for treating peripheral neuropathy, particularly ischemic peripheral neuropathy, is provided. The method involves administering to subjects in need of such treatment an effective amount of an angiogenic growth factor to alleviate a symptom of the neuropathy.

Peripheral neuropathy generally refers to a disorder that affects the peripheral nerves, most often manifested as one or a combination of motor, sensory, sensorimotor, or autonomic neural dysfunction. Peripheral neuropathies can be genetically acquired, can be induced by a toxic agent, or can result from peripheral ischemia or from a systemic disease. Genetically-acquired peripheral neuropathies include Refsum's disease, Abetalipoproteinemia, Tangier disease, Krabbe's disease, Metachromatic leukodystrophy, Fabry's disease, Dejerine-Sottas syndrome, Charcot-Marie Tooth Disease (also known as Peroneal Muscular Atrophy, or Hereditary Motor Sensory Neuropathy) and others. Exemplary toxic agents which cause neurotoxicities include therapeutic drugs such as antineoplastic agents, contaminants in foods, and environmental and industrial pollutants. Ischemic peripheral neuropathies include, but are not limited to, diabetic polyneuropathy. Peripheral neuropathies associated with a systemic condition include uremia and alcoholic polyneuropathy among other disorders.
Ischemic peripheral neuropathy, particularly when it develops in the absence of diabetes, has received limited study, despite the fact that it may be a prominent feature of patients with peripheral vascular disease. Among diabetics, peripheral neuropathy is common and ultimately accounts for significant morbidity. Typically, symptoms are dominated by sensory defects. (Tomlinson DR, et al. Diabetes 1997;46:S43–S49). The ultimate consequence of such sensory deficits involving the lower extremities may be foot ulceration initiated by traumatic injury that is inapparent to the patient. Indeed, it has been reported that 20% of all hospital admissions among diabetic patients in the United States are for foot problems. (Reiber G E, et al., in Harris M I, et al, (eds): Diabetes in America. Washington, National Institute of Diabetes and Digestive and Kidney Diseases, 1995, pp 409–427). That such ulcerations may lead to lower extremity amputation (Parkhouse N, et al., N Engl J Med 1988;318:1306–1309) is borne out by the fact that the rate of lower limb amputation is fifteen times higher in diabetic versus non-diabetic patients (Veves A, et al., Diabetes 1998;47:457–463). Even with intensive insulin therapy, as reported in the Diabetes Control and Complications Trial (DCCT), the incidence of new clinically detected neuropathy per patient per year was 3.1% in the non-retinopathy group and 7.0% in the group with baseline retinopathy; with conventional therapy, the incidence of neuropathy increased to 9.8% and 16.1% with and without retinopathy (The Diabetes Control and Complications Trial Research Group, N Engl J Med 1993;329:977–988). When loss of sensation is compounded by loss of control over blood flow due to autonomic neuropathy and lower extremity vascular obstruction, the threat of limb loss is exacerbated. In the case of peripheral artery disease, hospital mortality, length of hospitalization, and complications resulting from surgery are all increased in the presence of diabetes (Currie C J, et al., Diabetes Care 1998;21:42–48).
In view of the foregoing, a need still exists to better understand the molecular processes underlying peripheral neuropathy, and to develop improved drug therapies to replace or supplement the existing methods for treating peripheral neuropathies, particularly ischemic peripheral neuropathy. Preferably, such drug therapies would be designed to reduce or prevent nerve damage at its earliest stages and to enhance peripheral nerve repair following diagnosis and treatment.

Angiogenic growth factors for treatment of peripheral neuropathy

St. Elizabeth's Medical Center of Boston, Inc.


A system and method for an adaptive network of network access nodes comprises a global network operations center (GNOC) receiving operator inputs and generating a global policy according to the operator inputs. The GNOC and/or a distributed network gateway (GW) generate configuration commands for configurations for at least one of the network access nodes based on the global policy, transmit the configuration commands to at least one of the network access nodes, and receive telemetry from at least one of the network access nodes. The distributed network GW transmits a summary of key performance indicators (KPIs) to the GNOC and the GNOC revises the global policy according to the summary of KPIs.

Currently, configurations (e.g., payload configurations) of satellite networks are changed manually according to changing user demand for satellite resources (e.g., loading patterns), ambient environmental conditions, and/or system performance (e.g., including failures). In particular, a satellite's payload configuration is changed by a ground station manually generating and sending payload configuration command signals to the satellite. This conventionally used, manual procedure is very tedious and time consuming for the satellite operator. In addition, since this conventional procedure is manually-driven and does not incorporate closed-loop feedback, there is no self-organization and self-optimization capability.
In light of the foregoing, there is a need for an improved technology for adapting configurations to adapt the network to changes in user mobility and capacity demands.

Adaptive self-optimizing network using closed-loop feedback


A system for locating inflamed plaque in an artery of a patient includes a catheter with an expander mounted at a catheter distal end. An infrared carrier, e.g., an optical fiber is mounted on the catheter with a carrier distal end attached to the expander. A sensor is connected to a carrier proximal end to measure infrared radiation transmitted through the carrier from the carrier distal end. In use, the expander is operable to selectively move the carrier distal end into contact with the arterial wall. Infrared radiation can then be measured to determine the temperature at the arterial wall. Temperatures at various locations can be taken, with elevated temperatures being indicative of inflamed plaque.

Plaque can develop in different locations in a patient's cardiovascular system. The plaque can vary in size and shape. For example, the plaque can be quite extensive and occlude a substantial length of the vessel. Alternately, the plaque can be quite short and small.
Further, the condition of the plaque can vary. For example, the plaque can be inflamed and unstable, or the plaque can be quite stable. It is important to recognize that, inflamed and unstable plaque is subject to rupture, erosion or ulceration which can cause the patient to experience a myocardial infarction.
Presently, a number of procedures are available for locating plaque in an artery. One commonly performed procedure is angiography, which involves taking x-ray pictures of vessels after injecting a radiopaque substance into the vessels. While this procedure is quite effective for locating large plaque in arteries, this procedure is unable to evaluate whether the plaque is inflamed and unstable. Therefore, there is a need of a device and procedure for precisely and accurately locating the position of unstable, inflamed plaque.
In light of the above, it is an object of the present invention to provide a device and method for locating unstable, inflamed plaque in an artery. Another object of the present invention is to provide a system for determining the size of the unstable, inflamed plaque in the artery. Another object of the present invention is to provide a device and method for locating inflamed plaque which is relatively easy and inexpensive to manufacture and relatively easy to operate.

Device and method for locating inflamed plaque in an artery


A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.

1. Field of the Invention
The subject matter of the present invention is a multilayer structure, comprising a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon and having a lattice constant which differs from a lattice constant of the substrate. Silicon which is deposited on a SiGe layer of this type is biaxially strained. Since the mobility of charge carriers in strained silicon is higher than in unstrained silicon, electronic components which make use of strained silicon to increase the switching speed are receiving more and more interest.
2. Description of the Related Art
In particular an SiGe layer, which consists of a mixture of silicon and germanium with a germanium content of from 20 to 50% and is as far as possible completely relaxed, is suitable for the deposition of strained silicon. Since the lattice constant of the SiGe layer is greater than that of silicon, the silicon lattice which is deposited on a layer of this type is widened, producing a layer of strained silicon.
In general, silicon is also used as a substrate for the relaxed SiGe layer to be deposited on. On account of the different lattice constants, a heteroepitaxial layer which grows is initially strained itself. The strain disappears beyond a critical layer thickness, forming dislocations. Misfit dislocations tend to continue in a plane along the direction of growth of the growing layer. However, threading dislocations are also formed as extensions of misfit dislocations. These threading dislocations extend in the direction of growth of the SiGe layer and reach as far as the surface of this layer. This occurs to an increased extent if the deposited SiGe layer is relaxed during a simple heat treatment (anneal). Threading dislocations should be avoided wherever possible, since they usually continue in layers which are deposited on the SiGe layer and disrupt the functioning of electronic components which are integrated in layers of this type. Pile-ups of threading dislocations are particularly harmful. Another important parameter for the quality of the SiGe layer is the roughness of the surface, which should be as low as possible. Misfit dislocations produce stress fields and lead to local differences in the growth rate during the growth of the SiGe layer, and ultimately to a surface topography, known as "cross-hatch" topography, which is likewise transferred to layers deposited on the SiGe layer. A measure of this cross-hatch is the RMS roughness of the surface, measured for example by AFM (Atomic Force Microscopy).
Strategies have already been developed for reducing the density of threading dislocations. One possible option is to increase the concentration of germanium in the SiGe layer in steps or continuously. Another approach pursues the objective of depositing the SiGe layer on a layer which has a high concentration of point defects. Misfit dislocations then tend to form closed dislocation loops, which lead through the area with the high concentration of point defects, rather than to lengthen into threading dislocations directed toward the surface of the SiGe layer. The density of the threading dislocations which still reach the surface of the substrate is of the order of magnitude of at least 1·107 threading dislocations/cm2 and is therefore still far too high for the material to be suitable for the fabrication of electronic components. US2004/0067644 A1 has described a process which allows the density of threading dislocations to be reduced to below 1·105 threading dislocations/cm2. The process substantially comprises etching the surface of the SiGe layer at the same time as the heat treatment which relaxes the SiGe layer (etch anneal process). An advantageous side-effect of so doing is that the surface roughness also decreases.

Multilayer structure comprising a substrate and a layer of silicon and germanium deposited heteroepitaxially thereon, and a process for producing it


This is a domestic rolling machine for homemade pasta with the surface of the rolling rollers formed by anodizing metal to provide a micro-rough surface that considerably increases adherence thus reducing the number of passes for the sheet of pasta to reduce the thickness of the sheet of pasta from the initial to the final thickness.

We all know how homemade pasta is made.
The dough that is made from durum or bread wheat flour, eggs and water is prepared for processing with the domestic machines formed of a pair of smooth rollers and a pair of cutting rollers.
The longest rolling phase comes after the mixing phase.
After taking pieces of dough and patting them by hand into flat, thick and even sheets, they are introduced between the pair of smooth rollers in the domestic machine, with the maximum opening between the rollers.
To get the right thickness, the opening between the two rollers is reduced with each successive pass of the dough.
The reduction between one pass and the next to reduce the thickness of the pastry, is limited by the adherence of the roller surfaces which must drag the pasta sheet to press it.
Current domestic pasta machines which have been on the market for years now, have steel rolling rollers with a nickel-plated surface.
Nickel plating has a dual purpose, it protects the steel rollers and gives a longer lasting attractive appearance.
The problem with a nickel-plated surface is that it is smooth and compact and offers little adherence.
This means that numerous different passes are needed between the original thickness of the pasta sheet to the final required thickness.
This poor adherence is worsened further when dry flour has to be sprinkled over the pasta if it is too damp.
This means that the shiny nickel-plated surfaces offer no adherence whatever, and the pasta has to be pushed by hand into the two rollers.
The idea had been considered to roughen the nickel-plated surface to make it more adherent, by satinizing for example, but, as food products are involved, this is not possible because too much nickel would be given off into the pastry, which, being a heavy metal, is considered as harmful.
The aim of the patent is to overcome these problems by improving surface adherence of the rollers without any release of metal particles.
This aim has been reached by using aluminum rollers with anodized surfaces, exploiting the microporous feature of the surface which increases adherence and hardens the surface of the aluminum, which by nature is soft, and creates very long-lasting surfaces.
In fact the feature of this patent is the excellent surface adherence given by the microporous surface layer, in the form of evenly distributed microscopic raisings and grooves.
The anodizing process improves the microporosity without reducing the hardness and resistance to wear.
In detail, the surface layer of the anodized rollers is formed of a porous layer of aluminum oxide being in crystalline alumina (Al2O3) form and being an amorphous metal which is extremely hard and wear resistant with a microporous surface that creates micro-roughness without releasing any metal particles.
The inventiveness in this patent lies in using the collateral feature of anodizing aluminum which ensures hardness and resistance to wear and creates the surface micro-roughness which improves adherence of the rolling rollers on the pasta machines.
The hardness and wear resistance properties in this specific patent are also very advantageous, because the aluminum used for anodizing the rollers is of moderate hardness and is not easy to dent and the wear resistance of the surface reduces to virtually zero the release of particles from the surface layer, and even in the event any particles were released, being alumina they are not considered harmful in food preparations.
As previously stated, the anodized alumina used improves adherence on the surface of the processing rollers (rollers and cutters) in aluminum or aluminum alloys, but as alumina is by nature abrasive, it presents a problem for the scraping blades.
The function of the scraper blades is to avoid any pasta remaining on the rollers, and when the metal blades come into contact with the surface of the rollers they create friction.
As we said above, the surface of the rollers is abrasive and tends to wear the edges where the blades come into contact.
As the blades must be flexible to function, either stainless steel or nickel-plated steel are preferably used because they are hard wearing.
As we know, with wear the material begins to detach and this metal material would enter the pasta that is being processed.
Therefore as the surface of the rollers is alumina (hard and abrasive), the answer to avoid the metal particles detaching from the scraper blades is to coat them with a resin film for food use, to clean the rollers removing any pasta deposits and able to gently resist the roughness of the roller surface for a long time.


Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.

The following relates generally to memory devices, and more specifically to a hybrid memory including a ferroelectric random access memory (FeRAM) array and a dynamic random access memory (DRAM) array.
Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic "1" or a logic "0." In other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored state in the memory device. To store information, the electronic device may write, or program, the state in the memory device.
Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), DRAM, synchronous dynamic RAM (SDRAM), FeRAM, magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., flash memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. A binary memory device may, for example, include a charged or discharged capacitor. A charged capacitor may become discharged over time through leakage currents, resulting in the loss of the stored information. Certain aspects of volatile memory may offer performance advantages, such as faster read or write speeds, while aspects of non-volatile, such as the ability to store data without periodic refreshing, may be advantageous.
In some cases, a FeRAM may be operated at a speed and with a nonvolatile property similar to that of a DRAM. In these cases, however, the ferroelectric capacitors used in the memory cells of the FeRAM may suffer from fatigue as a result of repeated polarizations and inversions of the ferroelectric materials within the ferroelectric capacitors, resulting in a reduction of residual polarization. Also, when writing operations are continuously carried out in the same polarization direction, a shift in the hysteresis characteristic of a memory cell, referred to as an "in-print," may cause subsequent degradation in the rewriting characteristic of the memory cell. Compared to a DRAM, a FeRAM may therefore support fewer read-out and writing operations over its lifetime.
On the other hand, the ferroelectric capacitor of a FeRAM has a characteristic in which the ferroelectric characteristic by a residual polarization component and the paraelectric characteristic by a normal capacitor component are combined with each other, and by using only the paraelectric characteristic, without carrying out polarization inversion, the FeRAM may be operated similarly to a DRAM.


A transmitter with data stream transformation circuitry is described. The transmitter has a first driver and a second driver. Each driver has an output for a respective analog signal. A summation circuit combines respective analog signals from the first driver and the second driver. A data selection circuit processes at least two data streams. Each data stream corresponds to a time sequence of digital data symbols. The data selection circuit selectively couples at least one of the data streams to at least one of the drivers during each time interval of a sequence of time intervals, thereby applying a linear transformation to the data streams. A finite state machine controls the data selection circuit during each time interval of the sequence of time intervals.

Communications systems, such as multi-tone links, often perform signal processing operations on data based on a communications technique being used and/or one or more characteristics of a communications channel. For example, communication systems may code and/or frequency band limit the data using a transformation, such as a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). Filters, such a finite impulse response (FIR) filter or a polyphase filter, may equalize and/or shape a spectral content of the data in at least a band of frequencies corresponding to at least one communications channel. And depending on the characteristics of the communications channel, the filters and/or a modulation code used to modulate the data may also be adapted.
In some communications systems it is advantageous to implement many of these signal processing operations in a transmitter. However, supporting a wide variety of operations in the transmitter, especially in those systems that include adaptive signal processing and/or adaptive modulation coding, may increase complexity and/or expense. There is a need, therefore, for an improved digital transmitter in communication systems.
Like reference numerals refer to corresponding parts throughout the drawings.

Digital transmitter with data stream transformation circuitry

The Board of Trustees of the Leland Stanford Junior University


A resonator mounting mechanism includes a stand having a groove in the head of the stand. A cap, which also has a groove, fits over the top of the stand to hold a resonator in place. The stand has two slots formed between lugs, which receive arms on the cap. The sidewalls of the lugs forming the slots and the arms on the cap are tapered so that there is an interference fit between the cap and the stand. The interference fit between the slots and arms holds the cap, stand, and resonator in a fixed position. The bottom of the stand includes structure for attaching the stand to a wall of a resonator cavity, or the like.

Numerous types of resonant structures, often used in electromagnetic filters, are known in the prior art. For most applications, a conductor and/or dielectric material must be held in a fixed position with respect to a wall, such as the cavity wall of a filter housing. In some resonant structures, conductors are held between slabs of dielectric material which are forced together using screws, springs or adhesive. In many applications, however, it is desirable that a resonator have little physical contact with other objects. Small screws or bolts may be placed through an opening in a resonator such as a dielectric puck, in order to attach the resonator to another structure with minimal physical contact. Although some degradation in performance of the resonator may undoubtedly be attributed to such mounting structures, that degradation is generally small in comparison to other losses which affect the overall quality of the resonator.
The introduction of superconducting materials into resonant structures has significantly decreased the surface resistance of those structures, thereby raising the quality factor "Q" of the filtering devices utilizing the resonant structures. Losses due to mounting, which were previously insignificant, have now become an important limiting factor in the quality of a filter. Prior structures, such as providing a threaded opening or the like in a resonator, may no longer be desirable, because they interfere with the electromagnetic fields at the surface of the resonator. In general, the greater the size of a mounting mechanism or the more contact it has with the resonator, the more likely it will interfere with the electromagnetic properties of the resonator or resonant cavity in which it is used. The desire for reduced size in mounting mechanisms is at odds with the need to hold the resonator at a precise location with minimal chance for mounting failure. In the case of filters using superconductors, the structural demands on the mounting mechanism are increased, since that mechanism will be subjected to temperatures ranging from room temperature to hundreds of degrees below 0.degree. C.
In U.S. Pat. No. 5,604,472, the disclosure of which is incorporated herein by reference, the assignee of the present application used a resonator mounting device having a stand with a groove in the head of the stand surrounded by two wings. A cap with a groove and two wings fit over the head and was attached to the stand by rings. While such a device operates satisfactorily, assembly of the rings onto the wings can be difficult. In certain positions of the stand, it might also be cumbersome to hold the cap to the stand while the rings were applied. In addition, tolerances of the grooves had to be relatively precise or the cap would not hold the resonator to the stand in a fixed position. It is also possible for the resonator to vary in cross-section, resulting in the rings fitting too tightly for assembly or too loosely to clamp effectively once assembled.


A zoom lens comprises, in order from the image magnifying side to the image reducing side, a negative power first lens group which is moved axially for focusing a lens system of the zoom lens and fixed during zooming the lens system, a positive power second lens group, a positive power third lens group and a negative power fourth lens group which are moved axially relative to each other and relative to the first lens group and a fifth lens group which has a positive power and remains fixed during focusing and zooming the lens system, the zoom lens satisfying the following conditions: EQU -2.0<F1/F<-0.9 EQU 0.9<F2/F<1.5 EQU 1.5<F3/F<5.0 EQU 0.8<F5/F<1.5. where F is the overall focal length of the zoom lens at the wide angle end, and F1, F2, F3 and F5 are the focal lengths of the first, second, third and fifth lens groups, respectively.

1. Field of the Invention
This invention relates to a zoom lens system for use with imaging device, such as a charge coupled device (CCD) and an image pick-up tube, a photographic camera using a silver film, and a projection type television set.
2. Description of Related Art
There have been known zoom lens systems of the type including a negative power first lens group, a positive power second lens group, a negative power third lens group and a positive power fourth lens group. The first lens group is movable axially for focusing the zoom lens system and, however, remains fixed during zooming the zoom lens system. The fourth lens group is stationary. During zooming the zoom lens system, the second and third lens groups are moved axially relative to each other and relative to the first and fourth. One of such zoom lens systems known from, for example, Japanese Unexamined Patent Publication No. 5-297276 has been designed for the purpose of forming an image on a small size of imaging device such as a CCD.
In recent years, projection type television sets with liquid crystal display means installed therein have received much attention. If the zoom lens described above is used as a projection lens of such a projection type television set, the zoom lens does indeed become bulky with an increase in image size, which is always undesirable in view of strong demands for miniaturization of the projection type television set. Further, if a zoom lens is used as a projection lens, it is generally hard for the zoom lens to sufficiently reduce aggravation of distortion. In particular, if a zoom projection lens is applied to the projection type television set, from the standpoint of preventing aggravation of occurrence of irregular color and a quantitative light loss which are caused depending upon lighting systems, the zoom projection lens is desired to be of a telecentric type which makes a principal ray parallel to its optical axis at a side on which an image is reduced. The prior art zoom lens is not of the telecentric type. Further, the prior zoom lens has only a back focal length too short to admit a color separation optical element in an appropriate axial position.


The present solution ensures that the UEs are able to make use of all the available reference signals that can be used in a cell for performing UE measurements, estimations or demodulations. That is achieved by indicating on a downlink common or shared channel, the MIMO mode settings associated with a specific network node. The indicated MIMO mode settings explicitly or implicitly indicate available common reference signals and/or dedicated reference signals to be used for said UE measurements, estimations or demodulations, which implies that measurements, estimations or demodulations can be performed based on said received indication.

UTRAN (Universal Terrestrial Radio Access Network) is a term identifying the radio access network of a UMTS (Universal Mobile Telecommunications System), wherein the UTRAN consists of Radio Network Controllers (RNCs) and NodeBs i.e. radio base stations. The NodeBs communicate wirelessly with mobile user equipments (UEs) and the RNCs control the NodeBs. The RNCs are further connected to the Core Network (CN). Evolved UTRAN (E-UTRAN) is an evolution of the UTRAN towards a high-data rate, low-latency and packet-optimised radio access network. Further as illustrated in FIG. 1, the E-UTRAN consists of radio base stations (eNBs) 12, and the eNBs are interconnected and further connected to the Evolved Packet Core network (EPC) 14. E-UTRAN is also being referred to as Long Term Evolution (LTE) and is standardized within the 3rd Generation Partnership Project (3GPP). FIG. 1 also shows UEs 10 in communication with the eNBs 12.
E-UTRAN is a pure packet data designed cellular system, in which transmissions of user data in uplink and downlink always take place via shared channels. Orthogonal Frequency Division Multiplexing (OFDM) technology is used in the downlink, whereas DFT (Discrete Fourier Transform) based pre-coded OFDM is used in uplink. As similar to HSPA (High Speed Packet Access) in the UTRAN, the UE monitors physical downlink control channels (PDCCH) in order to access UE dedicated user data on the physical downlink shared channel (PDSCH) and the network assigns uplink scheduling grants to the UE on demand basis for uplink transmission via the physical uplink control channel (PUCCH) and the physical uplink shared channel (PUSCH). Error detection is provided on transport blocks and control payloads through CRC, and HARQ operations ensure efficient re-transmissions.
FIG. 2 illustrates mapping of downlink common reference signals for one, two and four antenna ports.
OFDM is a modulation scheme in which the data to be transmitted is split into several sub-streams, where each sub-stream is modulated on a separate sub-carrier. Hence, in OFDMA based systems, the available bandwidth is subdivided into several resource blocks prior to being transmitted. A resource block is used both for uplink and downlink and is defined in both the time and the frequency domain. According to the E-UTRAN standard, a resource block size is 180 KHz (comprising of 12 sub-carriers each with 15 KHz carrier spacing) and 0.5 ms (time slot) in frequency and time domains, respectively. The transmission time interval (TTI) comprises of 2 time slots, which correspond to 1 ms length in time. The radio frame is 10 ms long. The overall uplink and downlink transmission bandwidth can be as small as 1.4 MHz and as large as 20 MHz.
Each time slot comprises of N number of OFDM symbols as illustrated in FIG. 2 and a cyclic prefix (CP) is appended to each OFDM symbol to enable the mitigation of inter-symbol interference. The number of OFDM symbols 'N' per slot depends upon the cyclic prefix in use. In small cells typically normal CP (around 5 μs) is used whereas in larger cells extended CP (around 17 μs) is used. Therefore When normal CP is used more OFDM symbols can be used in a slot.
Each element in the time frequency resource grid for antenna port p is called a resource element 20, which is uniquely identified by the index pair (k,l) in a slot represented; kth sub-carrier and lth OFDM symbol as shown in FIGS. 1 and 2.
FIG. 2 further illustrates the resource elements 24 used for downlink common reference signal transmission for extended CP as specified in E-UTRA technical specification 36.211. The notation Rp is used to denote a resource element used for common reference signal transmission on antenna port p. The common reference signals are also referred to as cell specific reference signal as opposed to UE specific reference signals which are also referred to as dedicated reference signals. As indicated in FIG. 2, some resource elements 20 denoted by crosses are not used for transmission on a specific antenna port.
Reference signals or pilot signals or pilot sequences or training sequences have similar meaning and are interchangeably used in literature. It is standardized set of signal sequences which are transmitted by the transmitter and are known a priori to the receiver. Their main objective is to assist the receiver to estimate the characteristics of radio channel, which especially varies over time due to user mobility.
The terms reference signal or reference symbol are also interchangeably used but they have similar meaning.
E-UTRAN utilizes multiple antennas techniques referred to as MIMO (Multiple Input Multiple Output) modes. Examples of such MIMO modes are precoding mode and beamforming mode. Precoding mode works with codebook-based transmission weights and utilizes common reference signal for channel estimation. A UE can determine a codebook index from the channel estimates and feed it back to the evolved NodeB (eNodeB). Beamforming mode works however with non-codebook based transmission weights, which requires in the downlink a dedicated reference signal that is precoded with the same transmission weights as the data and can be operated without any feedback of a codebook index. UE measurements for radio resource management, such as mobility management, are performed based on the common reference signals.
Regarding the dedicated reference signal patient design for the beamforming mode, in one scenario where all the users in one cell are configured for beamforming mode, the shared channel is demodulated based on the dedicated reference signal. On the other hand, common channels such as broadcast channel or other common control channels such as PDCCH, which may be transmitted to all or a group of UEs, are typically sent over the entire cell. In other words they are not beamformed towards a particular UE. Hence, the UE needs to use common reference signals to demodulate all common channels. This means that the network has to transmit both dedicated and common reference signals in a cell supporting beamforming. The transmission of dedicated reference signals in addition to the common reference signals results in that the overall overhead of reference signals becomes quite high.
It is therefore desired to reduce this overhead when dedicated reference signals are transmitted to support beamforming in a cell. One way is to reduce the common reference signal density, e.g. to only keep the common reference signals in the same OFDM symbols as the common control channel while still keeping the common control channel demodulation performance good enough. In other scenarios where there are users configured for the preceding mode within one cell, common reference signals are required for both common control channel demodulation and the shared channel demodulation. Then it is preferred that the common reference signal is spread among the whole subframe, i.e. higher density.
The common reference signals are also used by the UE to perform neighbour cell measurements, which are used for taking mobility decisions such as cell reselection and handover. The neighbour cell measurements include, e.g. reference signal received power (RSRP) and reference signal received quality (RSRQ). However, the number of available reference signals is reduced if e.g. beamforming is used. An insufficient number of reference signals may adversely impact the neighbour cell measurement performance.
Moreover, LTE supports MBSFN (Multicast Broadcast Single Frequency Network) operation on the same carrier as unicast traffic. This means that a subset of the subframes is allocated to MBSFN transmission from multiple cells. In such subframes the common reference signal transmission is reduced and the common reference signals available for measurements are only transmitted in the first symbol of each subframe. In other normal unicast subframes, the reference signals from antenna port 0 and 1 for mobility measurements are transmitted in four different separated subframes.
In the current LTE it is desired to use as many reference signals as possible for neighbour cell measurements in order to achieve a good mobility management. For this purpose the serving cell can provide neighbour cell configuration indicators to the UE on a dedicated channel. These indicators can be used to indicate whether or not the neighbour cells have the same configuration as the serving cell and whether there are any MBSFN subframes at all. In this way the terminal will be able to use as many common reference signals as possible when performing the measurements.

Method and apparatus for communicating to UE an indication of available RS, based on MIMO mode settings


The present invention relates to a method for regulating a predetermined modifiable brake pressure in the wheel brakes of a brake system, wherein input quantities determining the brake pressure in the individual wheel brakes are evaluated and correcting variables of hydraulic valves are defined in a control and/or data processing system. To obviate the need for additional pressure sensors which register the pressure in the wheel brakes, it is arranged for by the invention that a characteristic curve is stored in the control or data processing system, said curve correlating the valve characteristics of the hydraulic valve with a pressure difference of the hydraulic valve, and the correcting variable of the hydraulic valve is defined according to the characteristic curve.

Vacuum brake boosters require a vacuum supplied by the engine for boosting the pedal force to be generated by the driver. Depending on the engine, even relatively low pedal forces allow reaching a condition where further increase of the force applied to the actuating unit is possible only by an increase in the pedal force because the vacuum brake booster has reached the maximum possible boosting force. This condition is referred to as the point of maximum boosting of the booster. Braking operations that take place in excess of the point of maximum boosting of the vacuum brake booster place high demands on the driver in terms of the pedal force to be generated. For this reason, brake systems (OHB-V) are employed at an increasing rate supporting the driver by means of an active hydraulic brake pressure build-up. Brake systems of this type generally include a motor-and-pump assembly and a hydraulic unit being controlled by an electronic control such as ESP, ABS, TCS, and similar systems, to comply with the desired brake force boosting.
When pressure is built up in the wheel brakes by means of hydraulic boosting beyond the point of maximum boosting of the vacuum brake booster, the (analogized) separating valves are closed, and the hydraulic pump delivers brake fluid from the tandem master cylinder (TMC) into the wheel brakes. In the pressure reduction phase, it is required to discharge the additionally generated pressure into the tandem master cylinder by way of the separating valves in a manner comfortable with respect to pedal feeling and braking effect. This action usually requires two additional pressure sensors at the wheel brakes, one per brake circuit, in order to determine the wheel pressure. The result is a higher requirement of components causing an increase in the system's costs.

Method for regulating a predetermined modifiable brake pressure