Embodiments of the present disclosure provide a charging control method, a charging control device and a device to be charged. The method includes: in a charging process, performing K constant current charging stages on a battery in the device to be charged, where K is a positive integer greater than or equal to 1; in each constant current charging stage, performing constant current charging on the battery with a preset current corresponding to the constant current charging stage until the battery is charged to a preset voltage corresponding to the constant current charging stage, wherein the preset voltage corresponding to the Kth constant current charging stage is a charging cut-off voltage greater than a rated voltage of the battery; and when the voltage of the battery reaches the charging cut-off voltage in the Kth constant current charging stage, stopping charging the battery.

At present, a charging process of an electronic device can be divided into a trickle current charging stage, a constant current charging stage and a constant voltage charging stage. In the existing charging process, after detecting that a voltage of a battery reaches a constant current charging voltage point, a constant voltage charging is performed, and the process is remained in the constant voltage charging stage until a charging cut-off condition is satisfied, and then the process is ended. Moreover, the charging voltage in the entire constant voltage charging stage does not exceed a rated voltage of the battery. Thus, since the constant voltage charging duration is long, the entire charging duration is long, which wastes time and also reduces the charging speed.

Charging control method, charging control device and device to be charged

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


A hair roller heating apparatus for heating hair rollers, has a base and a plurality of heating rods of sufficient length to simultaneously hold and heat a plurality of hair rollers. The heating rods further have a distal portion and a proximal portion, the proximal portion attached to the base and the distal portion free for receiving hair rollers. The heating rods also have an outer casing and heating elements placed within the outer casing. An electrical cord provides electricity from an electrical source to the heating elements, Therefore, the heating rods impart sufficient heat to the hair rollers to heat the rollers to a desired temperature. In a preferred embodiment the heating rods are at least 10 inches in length.

The use of hair rollers for hair styling is well known. There are many commercially available hair roller heater roller sets for home use. Currently, heating apparatuses for heating hair rollers include a plurality of heating rods with each heating rod capable of heating only one hair roller. Consequently, in order to accommodate many rollers, the overall dimension of the apparatus is quite large and takes much needed counter space during use, as well as storage space during periods of non-use. Additionally, because of space restraints and in order to hold as many hair rollers as possible, the available hair roller heaters are designed for hair rollers that have an outer diameter of less than 2 inches. Consequently, hot hair rollers are available only for those who wish to curl their hair. Those individuals who wish to straighten their hair, which is accomplished by hair rollers that are more than 2 inches in diameter, have to do so using other means. Clearly, a compact apparatus for heating hair rollers is desirable. Further, it is desirable to have a hair roller heating apparatus for heating hair rollers with an outer diameter of at least 2 inches.

Heating apparatus for vertically stacked hair rollers


The present invention provides a poisoning-resistant catalyst for combustion of CO and inflammable gases which comprises an inorganic carrier, a noble metal active ingredient supported on said inorganic carrier, and silica supported on said noble metal active ingredient, said noble metal active ingredient comprising at least one member selected from the group consisting of Pt, Rh and Pd, the surface of said catalyst being richer in silica and the inner part of said catalyst becoming richer in said noble metal active ingredient the deeper from the surface said inner part becomes; and a catalytic combustion apparatus for burning inflammable gases in a starting gas by the use of said catalyst. Said catalyst has a high resistance to poisoning and has a high level of activity at a low temperature of 200.degree. C. or lower.

1. Field of the Invention
The present invention relates to a catalyst for combustion of inflammable gases, and it relates to, in particular, a poisoning-resistant catalyst used for purifying a desired gas by removing inflammable impurities (e.g. CO, H.sub.2, hydrocarbons, etc.) in a starting gas by a catalytic combustion method, and a process for producing this catalyst.
2. Description of Related Art
For production of semiconductor devices, various gases are used. In recent years, there has been a growing demand for an ultrahigh-purity gas with an enhancement of the degrees of integration and fineness of semiconductor devices, for the purpose of improving the yield of a product. In particular, nitrogen gas used as a carrier gas or a gas for conditioning an atmosphere has also come to be increasingly required to have an ultrahigh purity, and the permissible content of impurities in the nitrogen gas decreases at an increasing tempo.
In general, high-purity nitrogen gas is collected by separating nitrogen gas from air by subzero fractionation, but a slight amount of CO contained in the starting air cannot be removed by the subzero fractionation because its boiling point is near that of nitrogen. Therefore, CO is burned by the use of a catalyst before the subzero fractionation, and then separated and removed.
Processes for purifying a desired gas by removing such an inflammable gas in a starting gas by a catalytic combustion method have been disclosed, for example, in Japanese Patent Application Kokoku No. 3-7603 and Kokai No, 61-225568 and Japanese Utility Model Kokai No. 61-123389. They comprise converting CO or H.sub.2, i.e., an inflammable gas contained in a starting gas, into CO.sub.2 or H.sub.2 O, respectively, by catalytic combustion, separating the CO.sub.2 or H.sub.2 O by means of an adsorption separator provided in the downstream side of the catalytic combustor, eliminating the same from the system, separating the starting air freed of CO or H.sub.2, by a subzero fractionation apparatus, and thereby producing a desired high-purity gas.
As a catalyst used in the above catalytic combustion method, there are generally used noble metal catalysts such as Pt and Pd which have a high activity in a low temperature range. However, when a component poisonous to the catalyst (e.g. SO.sub.2 or H.sub.2 S) is contained in the starting gas, the catalyst is poisoned to be decreased in activity. The decrease of the activity results in a lowered removal rate of the inflammable gas in the starting gas, so that the purity of the gas produced by means of the subzero fractionation apparatus is lowered.
As a means for solving this problem, there is a method in which poisoning of the catalyst is prevented by providing a means for removing the poisonous component, on the inlet side of a catalyst tank. For example, a method for removing SO.sub.2 gas, a main component poisonous to the catalyst, has been proposed (Japanese Patent Application Kokai No. 2-119921). However, the provision of a means for removing such a component poisonous to the catalyst increases the cost of production of a catalytic combustion apparatus.
As a method for preventing the catalyst from being poisoned, employment of a high reaction temperature in a catalyst tank is known. In detail, as compared with catalytic combustion at a low temperature, catalytic combustion at a high temperature makes difficult the adsorption of a component poisonous to the catalyst and hence permits suppression of the decrease of activity of the catalyst. However, the employment of the high reaction temperature requires preheating of the starting gas or the catalyst as much, resulting in an increased running cost.

Poisoning-resistant catalyst, process for production thereof, and process for using said catalyst


A blood vessel entry indicator device is provided which includes a colored flexible membrane disposed within the transparent body of a hypodermic needle that is stretched over the proximal end of the needle cannula. As the needle reaches the inside of the blood vessel, pressure within the vessel is transferred through the cannula to the membrane which moves or inflates indicating that entry has been achieved. A stopper is provided for arterial use. Because it is pressure sensitive, the invention provides a positive indication of blood vessel entry, avoiding double puncture of the same blood vessel.

The present invention relates to a device for detecting when an intravenous or arterial cannula enters a vein or artery, and more particularly to a visually observable membrane which inflates or moves when the cannula comes into contact with the pressure of blood within a vein or artery.
Present intravenous and arterial cannulas depend upon a visual observance of blood itself in the hub of the cannula after the blood has flowed through the length of the cannula in order to indicate that the cannula needle has entered the vessel. Often, a cannula may puncture a blood vessel through both walls. When this happens using present cannulas, any back flow of blood may not be observed and the double puncture is undetected. This may result in improper administration of medication, hemorrhaging, collapse of the vein or artery, or other similar complications.
One method of addressing this situation is disclosed in U.S Pat. No. 5,030,207 to Mersch, et al. The Mersch device provides a fiber optic mounted around the cannula of the needle that is conformed to the distal end of the needle, so that as the distal end comes into contact with the blood at the interior of the vein or artery, that color is transmitted along the fiber optic to a magnifying system. However, the Mersch invention is complicated to manufacture, requires a certain amount of light to work properly, and may still allow the needle to puncture both walls of the vein or artery without being readily detected. The present is more reliable because it is activated by the pressure of the blood within the vessel.

Entry indicator device for arterial or intravenous needle


An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.

Virtual ground EPROM arrays are known in the art. Also known are alternating metal virtual ground EPROM arrays, described in U.S. Pat. Nos. 5,151,375 and 5,204,835, assigned to the common assignees of the present invention.
In the Background of the '375 and '835 patents, it is noted that the general trend in the EPROM industry is to reduce the size of each EPROM cell in the array. This has been done in a number of ways: by reducing the "design rule", (i.e. the minimum width of features on the lithographic masks used to produce the shapes of the integrated circuit elements) and by changing the architecture to one which utilizes less space. The design rule is determined by the capabilities of the lithographic processes with which the EPROM array is produced.
In general, an architecture usually can only be produced in a few different size design rules. For each architecture, there is usually one or two design rules any smaller than which the EPROM array cannot economically be produced, either due to poor resulting yields or to manufacturing expense.
The ideal architecture would be one all of whose elements are dependent only on the design rule. Such an architecture would reduce in size as the design rule decreases in size, without approaching a limit. One version of the ideal architecture is known as a "poly pitch limited" architecture whose size is a function of the pitch of lines of polycrystalline silicon (polysilicon or "poly") used to create an EPROM cell. The basic EPROM cell is detailed in FIG. 1, to which reference is now made.
An EPROM array 10 comprises two polysilicon layers, called "poly 1" and "poly 2". The polysilicon layers are produced on a semiconductor substrate (not shown) in a grid having intersecting lines 30 of poly 1 and lines 32 of poly 2. Parallel, spaced apart doped regions 34, known as diffusion bit lines, are formed in the silicon substrate between and in alignment with the poly 1 lines 30.
The area around an "intersection" of a poly 1 line 30 and a poly 2 line 32 is an EPROM transistor or cell 12, wherein the portion of the poly 1 line 30 beneath the poly 2 line 32 is a floating gate of the EPROM transistor 12.
In an ideal cell 12, the width of each poly 1 and poly 2 line is L, where L is the design rule, and the space between the lines is D. A typical value for L in a 0.8 .mu.m technology is 0.8 .mu.m. The area of the EPROM cells 12 is then (L+D).sup.2 where L+D is known as the "pitch" of each line. If L and D are equal, which is the ideal, then the area is 4 L.sup.2. A cell 12 having an area of 4 L.sup.2 is "poly pitch limited" in that it depends only on the pitch of the poly lines 30 and 32.
The alternating metal virtual ground EPROM array described in U.S. Pat. Nos. 5,151,375 and 5,204,835 is generally, though not completely, a poly pitch limited architecture. The teachings of U.S. Pat. Nos. 5,151,375 and 5,204,835 are incorporated herein by reference. With reference to FIG. 2, the following is a brief discussion of the alternating metal virtual ground architecture and operation.
The EPROM array of U.S. Pat. Nos. 5,151,375 and 5,204,835 comprises an EPROM area 10 comprising a plurality of EPROM transistors 12, or cells, surrounded by two "control areas" 14 comprising control elements, detailed hereinbelow.
In the EPROM area 10, each cell 12 comprises a gate 16, a source 18 and a drain 20. The sources 18 of a column of EPROM cells 12 together form non-metal-strapped, segmented diffusion bit lines, labeled S-1, S and S+1. The drains 20 of a column of EPROM cells 12 together form metal-strapped, continuous diffusion bit lines labeled M-1, M and M+1. Segmented bit lines S-1, S and S+1 typically connect together N EPROM cells 12, where N is typically 64. The gates 16 of a row of cells are connected to one word line WLi.
Each control area 14 comprises select transistors 22, contacts 26 and select lines SELn and SEL(n+1). Select transistors 22 are typically stacked gate transistors but can also be n-channel devices. One contact 26 is connected to each bit line M-1, M or M+1 in each control area 14.
A pair of select transistors 22 from two neighboring control areas 14 are operative, when activated by the appropriate select lines SELn or SEL(n+1), to connect one segmented diffusion bit line S-1, S or S+1 to a neighboring continuous diffusion bit line M-1, M or M+1.
In order to access the EPROM cell labeled 12a, the following lines are activated: word line WL1, select lines SEL(n+1) and bit lines M and M-1. Bit line M receives the drain voltage and bit line M-1 receives the source voltage. The select transistors 22 which are activated by select lines SEL(n+1) transfer the source voltage from bit line M-1 to the segment S-1. Word line WL1 activates a row of EPROM cells and bit lines M and M-1 activate a column of cells, thereby activating only EPROM cell 12a, which sits at the intersection of the activated row and column. The output of the EPROM cell 12a is provided through the contact 26 which is connected to the appropriate bit line.
In order to ensure that the current only flows between the strapped and non-strapped bit lines M and S-1, respectively, through selected EPROM cell 12a, neighboring select transistors 22 are isolated from each other. This is illustrated in FIG. 2 by spaces 24 which, in reality, are field oxide isolation units 24 (shown in FIG. 3A). Units 24 isolate the select transistors 22 from each other such that no current flows between them.
Unfortunately, the isolation units 24 are not poly pitch limited, as shown in FIGS. 3A and 3B to which reference is now made. FIGS. 3A and 3B are schematic cross-sectional views of one area 14 having a few isolation units 24 and select transistors 22.
The transistors 22 and isolation units 24 have very similar structures. Each comprise a strip 40 of poly 1, of width L, covered by a strip of poly 2, labeled 42. They each also typically comprise sandwich layers 41, located between the two poly layers, and side oxides 43. Each sandwich layer 41 comprises a poly-poly dielectric formed of an oxide-nitride-oxide (ONO) dielectric layer capped by a polysilicon and a nitride layer.
In the select transistors 22, the poly 1 strip 40 lies on a thin, gate oxide strip 44 laid on top of a semiconductor substrate 46 (the "wafer") formed of silicon. When the select transistor 22 is active, current flows through an area 45 under the gate oxide strip 44, known as the "channel".
In the isolation units 24, the poly 1 strip lies on top of a very thick, field oxide element 48, typically of a thickness of 5000 .ANG. or greater. This thickness is large enough to ensure that the isolation unit 24 generally does not leak current.
As can be seen, each field oxide element 48 is not completely coincident with its corresponding strip 40 of poly 1. In fact, the field oxide elements 48 extend beyond the poly 1 strips 40. These extensions are known as "oxide beaks", labeled 50, and their size varies with manufacturing variations. The oxide beaks 50 extend into the area of the bit lines and reduce their width. The remaining portions of diffusion bit lines are labeled 52.
The isolation units 24 are not poly pitch limited for at least two reasons, as described hereinbelow.
Firstly, in order to ensure complete isolation, the minimum feature width Q of the field oxide element layer 48 is typically wider than the poly width L. Additionally, the oxide beaks 50 extend beyond the minimum feature width Q, by an imprecisely controllable distance.
Secondly, the mask used to produce the poly 1 strips 40 is often misaligned with the mask used to produce the field oxide elements 48, causing the poly 1 strips 40 to be misplaced vis-a-vis the field oxide elements 48. The resultant cross-section is illustrated in FIG. 3B, wherein a poly 1 strip 40a is too close to a field oxide element 48a.
If poly 1 strip 40a is very close to field oxide element 48a, the material (typically arsenic) used to implant the bit line diffusions 52 will not reach the silicon of the wafer 46 and the bit line diffusion 52, in the area of the field oxide element 48a, will have a discontinuity. Therefore, no bit line diffusion 52 is shown between strip 40a and field oxide element 48a. The resultant select transistor 22 fails to electrically connect the metal-strapped bit line (M) to its neighboring segmented bit line (S).
If the space between poly 1 strip 40a and field oxide element 48a is such that some arsenic, but not enough, succeeds in implanting, the bit line diffusion 52 will be too narrow and will have a high resistance. The signal from a select transistor 22 having such a bit line will be weak during reading and the rate of programming will be slow.
Therefore, in the prior art, when determining a distance J between strips 40 of poly 1, the following was considered: a minimal spacing SPACE between the field oxide element 48 and the adjacent poly 1 strip 40 necessary to ensure successful implantation of the bit line diffusion 52, the expected size BEAK of the oxide beak, the expected variation OXIDE in the size of the oxide beak 50, the expected extent MISALIGN of the misalignment, and the expected variation ETCH in the width of the poly 1 caused by the poly 1 etch. The distance J is given as: EQU J>SPACE+BEAK+sqrt(OXIDE.sup.2 +MISALIGN.sup.2 +ETCH.sup.2) (1)
where "sqrt" indicates the square root function. Table 1 lists the variables of equation for the 0.8 .mu.m process such as is described in U.S. Pat. No. 5,151,375 and for a smaller 0.5 .mu.m process. The value of J provided is the minimal value of J.
TABLE 1 ______________________________________ VALUES FOR VARIABLES OF EQUATION 1 (in .mu.m) 0.8 .mu.m 0.5 .mu.m Variable process process ______________________________________ SPACE 0.35 0.3 BEAK 0.35 0.25 OXIDE 0.1 0.05 MISALIGN 0.3 0.2 ETCH 0.1 0.05 Minimum J 1.03 0.76 Ideal Cell Size 2.56 1.0 Actual Width Between 1.0 0.6 Cells Actual Cell Size 3.25 1.39 Percentage Increase 27% 39% Between Ideal and Actual Pitch ______________________________________
For an 0.8 .mu.m process, a J of 1.03 .mu.m is only 27% larger than the desired poly pitch of 0.8 .mu.m. However, for a 0.5 .mu.m process, a J of 0.76 .mu.m is an unacceptable increase of 39%. For the 0.5 .mu.m process, J is still large because, although the design rule for lithographic processes is less, the values for BEAK, OXIDE, MISALIGN and ETCH are not reduced accordingly. As can be seen, the variables BEAK, OXIDE, MISALIGN and ETCH limit the extent to which any design can truly become poly pitch limited.
It will be appreciated that the pitch of the cell along a row (the X pitch) is the same as the size required for the control area 14. Thus, the cell ceases to be poly pitch limited.


An intake manifold with a swirl system for an internal combustion engine having a number of cylinders; the intake manifold has, for each cylinder, an intake conduit connecting the intake manifold to the cylinder and in turn having two parallel channels; the swirl system has, for each intake conduit, a throttle valve housed inside a channel of the intake conduit to vary the air flow section of the channel, and which has a throttle mounted to rotate about an axis of rotation.

An internal combustion engine has a number of cylinders, each connected to an intake manifold via at least one intake valve, and to an exhaust manifold via at least one exhaust valve. The intake manifold receives fresh air (i.e. outside air) along a feed conduit regulated by a throttle valve, and is connected to the cylinders by respective intake conduits, each regulated by at least one intake valve.
A swirl system has recently been proposed to vary the cross section of the intake conduits when the engine is running and as a function of engine speed (i.e. drive shaft rotation speed). At low engine speed, the air flow section of the intake conduits is reduced to produce swirl in the air intake to improve the air-fuel mixture in the cylinders. By swirl-enhancing the mixture, all the injected fuel is burnt, thus reducing combustion-generated pollutant emissions. At high engine speed, the air flow section of the intake conduits is maximized to completely fill the cylinders and so generate the maximum possible power.
To vary the air flow section of the intake conduits, each intake conduit has two parallel channels, only one of which can be completely closed by a throttle valve. At low engine speed, the throttle valves are closed to reduce the air flow section of the intake conduits; and, at high engine speed, the throttle valves are opened to maximize the air flow section of the intake conduits.
Various design solutions for swirl system intake manifolds of the type described have been proposed, but comprise a large number of component parts and are complicated to assemble.

Swirl system intake manifold for an internal combustion engine


A load driving circuit that generates a desired voltage waveform to drive a load includes a target voltage waveform output section that outputs a target voltage waveform to be applied to the load. Power supply sections generate electrical power with voltage values different from each other. Negative feedback control sections between the power supply sections and the load supply electrical power from the corresponding power supply sections to the load and execute negative feedback control of a value of a voltage applied to the load for matching the voltage value and the target voltage waveform. A power supply connection section selects one of the power supply sections based on the value of the voltage applied to the load or the voltage value of the target voltage waveform and connects the selected power supply section to the load and disconnects the rest of the power supply sections from the load.

1. Technical Field
The present invention relates to a technology for generating a predetermined voltage waveform, thereby driving a load.
2. Related Art
Today, quite a number of devices use electricity as energy sources, and have various types of components operating with electricity incorporated therein. Although most of the components incorporated in the devices are arranged to exert predetermined functions only by supplying standardized electrical power, on the other hand, there are many components (components operating in an analog manner) which require power supply with a precisely controlled voltage value or voltage waveform in order for exerting predetermined functions. Further, the devices incorporating such components operating in an analog manner also incorporate dedicated circuits (driving circuits) for generating electric power with target voltage values or voltage waveforms to drive such analog-like components. It should be noted that the component driven by the driving circuit may sometimes be called a load of the driving circuit (or simply a load).
In such driving circuits, it is required to supply electrical power with the most accurate possible voltage value or voltage waveform. Therefore, the voltage supplied to the load may sometimes be detected to perform negative feedback control (feedback control) so that the voltage becomes a target voltage. Further, there is proposed a technology, in the case of driving a plurality of loads, attempting to use counter-electromotive force generated in one load for driving of another load in order for reducing power consumption (e.g., JP-A-9-23643, JP-A-2002-281770).
However, since these proposed technologies are not applicable unless a plurality of loads are driven and the loads are types of load generating counter electromotive force, there arises a problem that the scope of application is significantly limited.

Load driving circuit and load driving method


A system and method for facilitating a user defined virtual space is disclosed. One or more virtual space locations and/or activities may be correlated with user specified geolocations. In some implementations, the user specified geolocations may be verified against one or more spatial requirements prior to recording the user selected space-geolocation correlations. A user request to initiate an action or activity in the virtual space may be received. Prior to executing the requested action or activity in the virtual space, the user current geolocation may be verified against that specified in a space-geolocation correlation corresponding to a virtual space location or activity indicated in the user request.

Systems that reward users with virtual items for completion of activities in real world locations are known. For example, some systems unlock a virtual item in user inventory upon user's completion of real world location based activity such as checking into a restaurant or coffee shop. In another example, some systems generate offers of rare virtual items to incentivize users to go to real world locations or introduce friends to real world locations.
Systems that use real world locations to establish game rules are also known. Some systems of those systems use real world locations as positions on a game board/map. For example, users are required to capture real world locations specified on the game board/map by sending text messages from the real world locations to a game server.

This patent is subject to a terminal disclaimer.

System and method for facilitating user defined virtual space


A multi-window display control system includes a display area setting device for setting a first display area in the display area on a physical screen and setting a second display area in another area, different than the first display area. A display controller controls display of an active window or windows selected as application software and all the other inactive windows in the second display area so as not to overlap each other.

1. Field of the Invention
The present invention relates to a multi-window display control system and, more particularly, to a multi-window control system for displaying a plurality of independent logical windows on a physical screen of, for example, a CRT (cathode ray tube) and a LCD (liquid crystal display).
2. Description of Related Art
Recently, a system capable of displaying a plurality of independent windows simultaneously on a CRT screen connected to a personal computer, a work station, or the like, has become popular. Such a system is called a multi-window system. The use of such a system permits the user to operate different application software at the same time and hence permits the user to edit information displayed on one window while seeing information displayed on another window. Thus, the user's efficiency in performing operations has been improved to a remarkable extent.
In the multi-window control system, however, there sometimes occurs a case where too many windows are displayed on the CRT screen. For example, when plural windows are to be displayed in the multi-window system, a newly selected window is put on a window that has already been selected, with the result that plural windows are displayed on the CRT screen in a stacked state. This state is closely similar to a scattered state of many documents on a desk. In this state, the user has difficulty in seeing each window, so that the operability and the working efficiency are deteriorated.


Techniques are disclosed relating to reducing drag on cables towed behind a vessel in a body of water. In one embodiment, an apparatus includes a signal source coupled to a survey vessel via a source cable, and the source cable includes a plurality of floats along its length. The floats may in some embodiments allow the source cable to be lifted partially, substantially, or entirely above the surface of the water. Lifting the cable above the surface of the water may in turn decrease the amount of hydrodynamic drag on the cable, reducing the force necessary (e.g., from lateral deflectors on the cable or at the signal source) to tow the source and/or the force necessary to attain a desired lateral position for the signal source. The disclosed techniques may in some embodiments be used to tow such sources at relatively wide lateral separations.

1. Technical Field
The disclosure relates generally to the field of marine geophysical surveying. More particularly, this disclosure relates to systems and methods for reducing drag on cables used in marine geophysical surveying.
2. Description of the Related Art
Marine geophysical surveying systems, such as seismic acquisition systems and electromagnetic survey systems, are used to acquire geophysical data from formations disposed below the bottom of a body of water, such as a lake or the ocean. One type of survey, a marine seismic survey, is based on the use of sound waves. In such a survey, a vessel may tow one or more acoustic sources (e.g., an air gun) and a plurality of streamers along which a number of sensors (e.g., hydrophones) are located. Sound waves generated by the source may then be transmitted to the earth's crust and then reflected back by various strata and detected at the sensors. Sound waves received during a marine seismic survey may be analyzed to locate hydrocarbon-bearing geological structures, and thus determine where deposits of oil and natural gas may be located. In a similar fashion, marine electromagnetic (EM) surveys may be conducted using EM signals transmitted by, for example, a submerged antenna and detected by EM receivers.
In the example of marine seismic surveying, the surveying systems typically include a seismic survey vessel having onboard navigation, seismic signal source control, and geophysical data recording equipment. The seismic survey vessel is typically configured to tow one or more (typically a plurality of) laterally spaced sensor streamers through the water. At selected times, the seismic signal source control equipment causes one or more seismic signal sources (which may be towed in the water by the seismic vessel or by another vessel) to actuate. Signals generated by various sensors on the one or more streamers in response to detected seismic energy are ultimately conducted to the recording equipment. A record is made in the recording system of the signals generated by each sensor (or groups of such sensors). The recorded signals may be interpreted to infer the structure and composition of the formations below the bottom of the body of water. Corresponding components for inducing electromagnetic fields and detecting electromagnetic phenomena originating in the subsurface in response to such imparted fields may also be used in marine electromagnetic geophysical survey systems.
In some embodiments, it may be advantageous for the geophysical survey sources to be towed at relatively wide lateral separations (e.g. relatively wide separations from other survey sources, or relatively wide separations from a central axis of the survey vessel). Certain marine geophysical surveying systems and a discussion of some advantages of wide source tow are provided in U.S. Patent Application Publication No. 2012/0257474, which is incorporated by reference herein. Reducing hydrodynamic drag on sources and source cables may be advantageous in attaining relatively wide tow of such sources. Further, even in embodiments that do not involve wide tow of sources (e.g., sources directly behind a survey vessel, or sources at relatively small lateral separations from a central axis thereof), it may be desirable to reduce the hydrodynamic drag acting on the sources and/or source cables.

Reduced-drag towing of geophysical equipment


The present invention relates to an insulated take home food container. In particular, the present invention relates to a laminate of metallic or non-metallic heat reflective film, either flat or in a manner to create air pockets, utilized to increase the holding time a food stays warm in the container. The container can have flat surface or dividing walls depending on the use of the box.

1. Field of the Invention
The present invention relates to a container for keeping food warm, moist and fresh. In particular, the present invention relates to an insulated food container designed to keep hot food warmer, more moist, and fresher for longer periods of time.
2. Description of Related Art
Food delivery or takeout food, e.g. fast food, has long been a mainstay within the United States. While most fast food or regular restaurants serve food within their restaurants, a great majority of them offer food to go or delivery of food. Since most fast food is a hot product, best served fresh out of the oven, keeping food warm and moist during delivery or on the drive home has been a difficult problem for decades.
For home delivery, ovens and reusable heavily insulated containers have frequently been utilized. However, for take home use, the container must be of a disposable kind and expensive products are clearly unsuitable. Typically, food is placed in a corrugated cardboard (e.g. as used in pizza boxes), Styrofoam, or other inexpensive material container. While the containers are very inexpensive and do a reasonable job handling moisture collection from hot food, it is not very good at retaining heat and moisture for a very long period of time. The corrugated cardboard or Styrofoam box does a good job in absorbing the moisture, however, it tends to dry out the food and makes it harder.
Several attempts to make a container that insulates better have been made, but mostly expensive solutions have been developed. Since the container must be included in the price of the food, anything that is difficult to make and/or uses expensive materials is unsuitable for a disposable container. Examples of unsuitable boxes include laminated multiple polymers, dual layers of corrugated cardboard with an insulating material certain types. These triple laminates, while an improvement in the heat retention, are too expensive to manufacture when compared to the single layer cardboard container which can be cut out of a flat sheet or stamped to a shape.
It is a need within the industry to have a container which holds heat longer than 10 minutes or so, and keeps the food moist and fresh, yet is inexpensive to manufacture and uses inexpensive materials. Since many companies that deliver food offer 30 minute hot delivery, attempting to keep a food warm for that period without a separate heat source or expensive reusable container would be desirable, but to date has not been achieved.


Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad; a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion; a chip disposed on the die pad and electrically connected to the leads; a molding compound encapsulating the chip, the inner lead portions and the trace portion, where the outer lead portions and a first surface of the trace portion are exposed from the molding compound; and an insulating layer covering the first surface of the trace portion.

A QFN package is a type of semiconductor device package having short signal traces. The short signal traces may allow for fast signal transmission speeds. Therefore, QFN packages are suitable for chip packages with high frequency transmission (e.g. high frequency transmission through the RF bandwidth). An improved QFN semiconductor package is described in this disclosure.

Semiconductor packages and related manufacturing methods

ADVANCED SEMICONDUCTOR ENGINEERING, INC.


A method for fabricating a thin film transistor is provided. A conductive layer is formed on a substrate. A patterned mask is formed on the conductive layer to cover a predetermined thin film transistor (TFT) area, and at least one portion of the conductive layer exposed by the patterned mask are removed. A laser is applied to form a laser hole in the patterned mask to expose a portion of the conductive layer and the laser hole substantially corresponds to a channel region of the predetermined TFT area. The exposed conductive layer is etched to form source and drain electrodes on opposite sides of the channel region.

1. Field of the Invention
The present invention relates to a fabrication method for a thin film transistor, and more particularly to a fabrication method utilizing laser ablation technology to simplify the manufacturing of thin film transistors.
2. Description of the Related Art
FIG. 1a to FIG. 1e illustrate a conventional process for manufacturing a thin film transistor in liquid crystal display using five photomasks. In FIG. 1a, a first conductive layer is formed on a substrate 100 by sputtering. Then, the first conductive layer is patterned to form a gate electrode 120 on the substrate 100 by a first photolithography and etching process beyond a predetermined thin film transistor area T.
In FIG. 1b, an insulating film 140, a semiconductor film 160, and an ohmic contact layer 180 are sequentially formed on the gate electrode 120. The semiconductor layer 160 and the ohmic contact layer 180 are patterned by a second photolithography and etching process to remove portions beyond the predetermined thin film transistor area T.
In FIG. 1c, a second conductive layer is formed on the substrate 100 by sputtering. The second conductive layer and the ohmic contact layer 180 underlying the second conductive layer are patterned by a third photolithography and etching process to form a drain electrode 200a and a source electrode 200b on the predetermined TFT area T. A portion of the semiconductor layer 160 exposed by an opening serves as a channel region. More specifically, the semiconductor layer 160 is exposed by an opening located between the drain electrode 200a and source electrode 200b.
In FIG. 1d, a passivation layer 220 covers the substrate 100 and the island shaped structure on the thin film transistor area T. The passivation layer 220 is then patterned by a fourth photolithography and etching process to form a contact hole 240 therein, thereby exposing a portion of the source electrode 200b.
In FIG. 1e, a pixel electrode 260 is formed on a portion of the passivation layer 220 and patterned by a fifth photolithography and etching process. The pixel electrode 260 is electrically connected to the source electrode 200b through the connect hole 240.
As mentioned above, the process for manufacturing the thin film transistor typically requires the use of five photomasks. Since manufacturing costs are greatly dependent upon the total number of photomasks used, it is a general object in the art to save the manufacturing costs by reducing the number of photomasks. It has been proposed in other fields, to use a laser ablation process to eliminate the need for photomasks to simplify the manufacturing steps. For example, in U.S. Patent Publication No. 20050064648, irradiation of the laser beam is performed on a photothermal converting layer to transfer heat and therefore sublimate a portion of a sublimation layer thereon. U.S. Patent Publication No. 20050258478 uses laser ablation to form a groove pattern in a semiconductor film.

Method of fabricating thin film transistor


Disclosed are system and method for distributing antivirus records to user devices. An exemplary method includes collecting, by a server, statistics on the use of antivirus records; calculating a coefficient of effectiveness of each antivirus record based on the statistics; identifying one or more most effective antivirus records whose coefficients of effectiveness exceed a predetermined effectiveness threshold; identifying one or more less effective antivirus records whose coefficients of effectiveness do not exceed the predetermined effectiveness threshold; transmitting identified most effective antivirus records to a plurality of user devices for storage in antivirus databases of the user devices; receiving, from the user devices, one or more less effective antivirus records removed from the antivirus databases of the user devices; and storing the received less effective antivirus records in an antivirus database of the server if said antivirus records were not in the antivirus database of the server.

Among the multitude of applications there is a group of malicious programs which are able to cause harm to the user device or the data of the user, such as: Internet worms, key loggers and computer viruses. There have been developed many different technologies for providing computer security, such as antivirus software, which is designed to detect malicious programs on the user device and to block their operating ability (e.g., placing them in quarantine or removing them from the user device).
The antivirus software may use a number of different methods of detecting malicious software, malicious processes, other malicious objects of the operating system (OS) and links to them, such as the URI (Universal Resource Identifier, such as file://***.exe). The most popular malware detection methods are signature analysis (a technology for finding correspondences between a particular segment of code of the program being analyzed and a known code, or signature, in a database of signatures of malicious programs), heuristic analysis (a technology involving emulating the working of a program being analyzed, creating an API (Application Programming Interface) function call log, and finding correspondences between the data of the created API function call log and the data in a database of emulations of malicious programs), and proactive analysis (a technology involving intercepting API function calls launched in the system of the program being analyzed, creating an API function call log, and finding correspondences between the data of the created log and the data in a database of calls for API functions of malicious programs).
In operation, each of the aforementioned methods requires data to be used for the detection of malicious objects, for example, in the case of signature analysis, such data might be signatures, for heuristic analysis, such the data might be heuristic rules. Despite the fact that, for example, when a single signature is used, the antivirus software may detect a whole array of malicious objects similar in their structure or in the harm caused. Therefore, the ever increasing number of malicious objects which can cause harm to the user's data or to his computer requires a corresponding increase in the volume of data used for detecting malicious objects. In the majority of cases, said data is stored on the user's computer as part of antivirus libraries—a component of the antivirus software. Thus, increasing the volume of data used for the detection, may result in the decrease of available space on the hard drive of the user device.
Although there are known approaches aimed at optimizing (reducing) the space on a hard drive occupied by data used for the detection of malicious objects, they are not able to solve the problem of distributing the data used for detecting malicious objects between a remote server and a local hard drive or they do not solve it effectively enough. Therefore, there is a need for a more effective solution of the problem of distributing to user devices the data used for detecting malicious objects.

System and method for distributing antivirus records to user devices


A method for distinguishing speakers in a conference call of a plurality of participants, in which method speech frames of the conference call are received in a receiving unit, which speech frames include encoded speech parameters. At least one parameter of the received speech frames is examined in an audio codec of the receiving unit, and the speech frames are classified to belong to one of the participants, the classification being carried out according to differences in the examined at least one speech parameter. These functions may be carried out in a speaker identification block, which is applicable in various positions of a teleconferencing processing chain. Finally, a spatialization effect is created in a terminal reproducing the audio signal according to notified differences by placing the participants at distinct positions in an acoustical space of the audio signal.

Various audio and video conferencing services have been available for a long time, particularly in circuit-switched telecommunications networks. Teleconferencing systems can be divided into distributed and centralized systems, of which the latter ones have turned out to be more advantageous in providing teleconferencing services, considering the service providers and the implementation of terminals.
FIG. 1 illustrates a prior art design for implementing a centralized audio conference service. The teleconferencing system comprises a conference bridge CB and several terminals UE that communicate with it. Each terminal UE receives the terminal user's speech by a microphone and encodes the speech signal with a speech codec known per se. The encoded speech is transmitted to the conference bridge CB, which decodes the speech signal from the received signal. The conference bridge CB combines the speech signals received from different terminals in an audio processing unit APU using a prior art processing method, after which the combined signal comprising several speech signals is encoded by a speech codec known per se and transmitted back to the terminals UE, which decode the combined speech signal from the received signal. An audible audio signal is produced from the combined speech signal by loudspeakers or headphones. To avoid harmful echo phenomena, the audio signal transmitted to the conference bridge by a terminal is typically removed from the combined audio signal to be transmitted to that terminal.
The combined signal is produced in the conference bridge typically as a single-channel (monophonic) audio signal or as a two-channel (stereophonic) audio signal. In the conference bridge, a spatial effect, known as spatialization, can be created artificially in a two-channel audio signal. In that case the audio signal is processed to give the listeners the impression that the conference call participants are at different locations in the conference room. In that case the audio signals to be reproduced on different audio channels differ from one another. When a single-channel audio signal is used, all speech signals (i.e. the combined signal) are reproduced as mixed on the same audio channel.
The spatialization, if properly implemented, improves the speech intelligibility of the conference call participants, since the listener is able sense the speech of each participant coming from a different direction. Accordingly, the spatialization is a desired feature in conference call systems. Prior art teleconferencing systems including spatialization are described e.g. in WO 99/53673, U.S. Pat. No. 6,125,115 and U.S. Pat. No. 5,991,385.
However, these prior art arrangements have remarkable disadvantages. To create a spatialization effect the receiving terminal requires information as to which participant is speaking at each moment. In most cases, the teleconference bridge is capable of defining the information, but it has to be included in the output signal of the teleconference bridge to be transmitted to each participating terminal. There is no standardized way to include this additional information in the signal to be transmitted. Besides, the inclusion of this additional information results in increase of the bandwidth used in data transmission, which is a further disadvantage.
An alternative prior known method for creating a spatialization effect is to provide a spatialization unit within the conference bridge. All input channels are spatialized in the spatialization unit and the spatialized signal is transmitted to each participating terminal. This, in turn, increases the complexity of the conference bridge. The signal including the spatialization information requires also a greater bandwidth.
Furthermore, in certain cases even the teleconference bridge is not capable of defining which participant is speaking at each moment. For example, it is possible to use the teleconference bridge as a gateway between a monophonic conference network and a 3D-capable (stereo/n-phonic) conference network. In such a situation, the gateway teleconference bridge receives, from a teleconference bridge of the monophonic conference network, a combined signal comprising all speech signals of the participants of the monophonic conference network. Again, additional information defining which participant is speaking at each moment should be included in the combined signal in order to enable the gateway teleconference bridge to separate the speakers from each other for further spatialization processing.

Spatialization arrangement for conference call


A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write back and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

This invention relates to semiconductor electrically erasable programmable read only memories (EEPROM) and specifically to a controller cache system for removable memory cards using EEPROM or other, similar memories.
Flash EEPROM systems are being applied to a number of applications, particularly when packaged in an enclosed card that is removably connected with a host system. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. One supplier of these cards is SanDisk Corporation, assignee of this application. Host systems with which such cards are used include personal computers, notebook computers, hand held computing devices, cameras, audio reproducing devices, and the like. Flash EEPROM systems are also utilized as bulk mass storage embedded in host systems.
Such non-volatile memory systems include an array of floating-gate memory cells and a system controller. The controller manages communication with the host system and operation of the memory cell array to store and retrieve user data. The memory cells are grouped together into blocks of cells, a block of cells being the smallest grouping of cells that are simultaneously erasable. Prior to writing data into one or more blocks of cells, those blocks of cells are erased. User data are typically transferred between the host and memory array in sectors. A sector of user data can be any amount that is convenient to handle, preferably less than the capacity of the memory block, often being equal to the standard disk drive sector size, 512 bytes. In one commercial architecture, the memory system block is sized to store one sector of user data plus overhead data, the overhead data including information such as an error correction code (ECC) for the user data stored in the block, a history of use of the block, defects and other physical information of the memory cell block. Various implementations of this type of non-volatile memory system are described in the following United States patents and pending applications assigned to SanDisk Corporation, each of which is incorporated herein in its entirety by this reference: U.S. Pat. Nos. 5,172,338, 5,602,987, 5,315,541, 5,200,959, 5,270,979, 5,428,621, 5,663,901, 5,532,962, 5,430,859 and 5,712,180, 6,222,762 and 6,151,248. Another type of non-volative memory system utilizes a larger memory cell block size that stores multiple sectors of user data.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell.
In order to increase the degree of parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips.
One architecture of the memory cell array conveniently forms a block from one or two rows of memory cells that are within a sub-array or other unit of cells and which share a common erase gate. Although it is currently common to store one bit of data in each floating gate cell by defining only two programmed threshold levels, the trend is to store more than one bit of data in each cell by establishing more than two floating-gate transistor threshold ranges. A memory system that stores two bits of data per floating gate (four threshold level ranges or states) is currently available. Of course, the number of memory cells required to store a sector of data goes down as the number of bits stored in each cell goes up. This trend, combined with a scaling of the array resulting from improvements in cell structure and general semiconductor processing, makes it practical to form a memory cell block in a segmented portion of a row of cells. The block structure can also be formed to enable selection of operation of each of the memory cells in two states (one data bit per cell) or in some multiple such as four states (two data bits per cell).
Since the programming of data into floating-gate memory cells can take significant amounts of time, a large number of memory cells in a row are typically programmed at the same time. But increases in this parallelism cause increased power requirements and potential disturbances of charges of adjacent cells or interaction between them. U.S. Pat. No. 5,890,192 of SanDisk Corporation, which is incorporated herein in its entirety, describes a system that minimizes these effects by simultaneously programming multiple chunks of data into different blocks of cells located in different operational memory cell units (sub-arrays).
To further efficiently manage the memory, blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each plane. Use of the metablock is described in international patent application publication No. WO 02/058074, which is incorporated herein in its entirety. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all blocks of a metablock are erased together. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within the blocks are typically identified by offsets within the block address. A metapage is a unit of programming of data in a metablock. A metapage is comprised of one page from each of the blocks of the metablock.
Due to the difference in size between a sector (512 bytes) and an erase block or metablock (sometimes more than 128 sectors), it is sometimes necessary to copy from one erase block, or metablock, to another. Such an operation is referred to as garbage collection. Garbage collection operations reduce the write performance of a memory system. For example, where some sectors in a metablock are updated, but other sectors in the metablock are not, the updated sectors may be written to a new metablock. The sectors that are not updated may be copied to the new metablock, either immediately or at some later time as part of garbage collection.
In some memory systems, the physical memory cells are also grouped into two or more zones. A zone may be any partitioned subset of the physical memory or memory system into which a specified range of logical block addresses is mapped. For example, a memory system capable of storing 64 Megabytes of data may be partitioned into four zones that store 16 Megabytes of data per zone. The range of logical block addresses is then also divided into four groups, one group being assigned to the physical blocks of each of the four zones. Logical block addresses are constrained, in a typical implementation, such that the data of each are never written outside of a single physical zone into which the logical block addresses are mapped. In a memory cell array divided into planes (sub-arrays), which each have their own addressing, programming and reading circuits, each zone preferably includes blocks from multiple planes, typically the same number of blocks from each of the planes. Zones are primarily used to simplify address management such as logical to physical translation, resulting in smaller translation tables, less RAM memory needed to hold these tables, and faster access times to address the currently active region of memory, but because of their restrictive nature can result in less than optimum wear leveling.
A memory array generally has circuitry connected to the array for reading data from and writing data to the memory array. As part of this circuitry, a data cache may be connected to the memory array. A data cache may simply be a row of registers that may be used to transfer data to and from the memory array. A data cache may hold as much data as a row of the memory array. Typically, a data cache is formed on the same chip as the memory array.
A controller may have several components including a central processing unit (CPU), a buffer cache (buffer RAM) and a CPU RAM. Both buffer RAM and CPU RAM may be SRAM memories. These components may be on the same chip or on separate chips. The CPU is a microprocessor that runs software (firmware) to carry out operations including transferring data to and from the memory array. The buffer cache may be used to hold data prior to writing to the memory array or prior to sending the data to the host. Thus, the buffer cache is a dual access memory that can simultaneously service the flash and host operations. The CPU RAM may be used to store data needed by the CPU such as instructions or addresses of data in the buffer cache or in the memory array. In one example shown in U.S. Pat. No. 5,297,148, which is incorporated herein in its entirety, a buffer cache may be used as a write cache to reduce wear on a flash EEPROM that is used as non-volatile memory.
FIG. 1 shows a buffer cache interposed between a host and a non-volatile memory (NVM) in a removable memory card. The buffer cache is connected to the host by a host bus. The buffer cache is connected to the NVM by an NVM bus. The bandwith of the host bus is greater than that of the NVM bus so that the NVM bus becomes a bottleneck for data being transferred between the host and the NVM. Also, programming within the NVM may become a bottleneck, especially when the host writes single sectors of data. After a single-sector write, the controller waits for the NVM to complete the write operation before accepting another sector from the host. Write or read operations involving small numbers of sectors may be inefficient where parallelism allows greater numbers of sectors to be handled. Where a host executes multiple threads, multiple data streams are generated that may be handled sequentially by a memory card controller.
Thus, a memory controller is needed that improves efficiency of read and write operations involving small amounts of data in an NVM.


Medical device components and processes are disclosed. For example, tube-shaped catheter components and processes of making tube-shaped catheter components are disclosed. Devices and systems, including medical devices and systems, such as catheters, containing tube-shaped catheter components are also disclosed.

Medical device components (e.g., tube-shaped catheter components) are used in a variety of systems.
For example, tube-shaped catheter components can be used in balloon catheters. Balloon catheters are commonly used in medical procedures. As an example, in some procedures a balloon catheter is used to open an occluded lumen, as in angioplasty. As another example, a balloon catheter can be used to selectively block a passageway. In additional examples, a balloon catheter is used in various combinations of these procedures. Typically, the procedures include positioning a balloon catheter within a blood vessel at a location of treatment, and inflating the balloon portion of the catheter with an inflation fluid. The balloon is then deflated and the catheter is withdrawn from the body.
As another example, tube-shaped catheter components can be used in systems for delivering medical devices, such as stents or grafts. The medical devices can be balloon-expandable or self-expanding.


A sliding rail assembly for wire baskets is provided. The rail of the sliding rail assembly has an enlarged opening in the front so that a wire basket could be guided into the rail quickly and easily. A number of wheel members are installed along the bottom of the rail to provide both support and sliding functions to the wire basket, and much less abrasion and squeaking noise is generated when the wire basket is pushed or pulled along the rail. Specially designed blocking members are installed along the rail so as to prevent the wire basket from being pulled entirely out of the rail, or being pushed too far into the rail.

(a) Technical Field of the Invention
The present invention generally relates to storage devices, and more specifically to a sliding rail assembly for supporting wire baskets in a closet.
(b) Description of the Prior Art
Wire baskets are commonly found under kitchen units and in storage and tool closets for the organization of various items. As shown in FIG. 8, the top rim A11 of a conventional wire basket A1 is engaged by sliding on a supporting rail A21 or within a sliding rail of a rail frame A2.
Usually the supporting rail A21 and the sliding rail of the rail frame A2 are designed simply to support the wire basket A1 and often found to have the following shortcomings. First, the top rim A11 of the wire basket A1, the supporting rail A21, and the sliding rail of the rail frame A2 are quickly abraded from the constant sliding movement of the wire basket A1. In addition, there are usually unpleasant loud squeaking noises when the wire basket A1 is slid.
Secondly, when the wire basket A1 is loaded with heavy items, the sliding movement of the wire basket A1 becomes more difficult from the increased friction. The heavy weight would also cause even more severe abrasion.
Thirdly, as there is no positioning mechanism in the design of the conventional wire basket A1, the supporting rail A21, and the rail frame A2, the wire basket A1 could be pulled entirely out or pushed too far into the rail, increasing its difficulty of use. Further more, if the wire basket A1 is filled with sharp knives or heavy tools, pulling out the entire wire basket A1 could pose a security hazard to the users, especially children.


Electrical devices, particularly circuit protection devices, contain conductive polymer elements whose edges are formed by breaking the conductive polymer element, along a desired path, without the introduction of any solid body into the element. The resulting cohesive failure of the conductive polymer produces a distinctive fractured surface. One method of preparing such devices involves etching fracture channels in the electrodes of a plaque containing a PTC conductive polymer element sandwiched between metal foil electrodes, and then snapping the plaque along the fracture channels to form individual devices.

This application is related to copending, commonly assigned U.S. application Ser. No. 08/121,717, filed Sept. 15, 1993, by Siden, Thompson, Zhang and Fang (Docket No. MP1490-US1), now abandoned, to copending, commonly assigned U.S. application Ser. No. 07/910,950, filed Jul. 9, 1992, by Graves, Zhang, Chandler, Chan and Fang, now abandoned, and the corresponding PCT Application US93/06480, filed Jul. 8, 1993 (Docket No. MP1454), and to the copending, commonly assigned U.S. application Ser. No. 08/242,916 filed by Zhang and Fang on May 16, 1994 (Docket No. MP1509-US1) now abandoned. The entire disclosure of each of those US and PCT applications is incorporated herein by reference for all purposes.

Electrical devices containing a conductive polymer element having a fractured surface