Viewing of web pages is improved by prioritizing image rendering based on positioning of images within a web page. For example, for images that are likely to be initially viewable upon presentation of the web page (i.e., prior to scrolling), compressed proxy versions are made available so that the images can be transferred and rendered more quickly. These compressed proxy images are later replaced with better quality renderings of the same images. Fetching of images that are not initially visible can be deferred until after other, more important page resources are loaded. Prioritization of page loading in this manner helps to ensure that the page becomes operational earlier, resulting in improved perceived speed and responsiveness, and greater ease of navigation.

Conventionally, in client-server network systems, such as the Internet, HTTP clients such as web browsers render HTTP responses including HTML content, such as web pages received from web servers. Typically, the client requests the HTML content from the web server, and then renders and displays the content for the user. Such content can include, for example, text, images, interactive content, and the like, and/or any combination thereof.
Because of transfer speed, bandwidth restrictions, latency, and/or rendering speed, it can take some time for content to appear on the user's screen. Images often take longer than other forms of content, because they involve relatively large amounts of data that must be transferred to the client, and because there may be limitations on the rendering speed because of the available processing power of the client machine. Accordingly, users of browser software often experience a lag time between the moment when a web page is requested (for example by clicking on a link or entering a URL) and the time when the complete web page, including its images, is presented on the screen for the user to see.
It is known to store images according to a progressive compression mechanism. For example, the progressive JPEG format compresses the image data in multiple passes of successively higher levels of detail. When an image in progressive JPEG format is rendered at a browser, a lower level of detail can be initially displayed. As more data is received at the client, the lower-resolution version of the image can be replaced by successively higher resolution versions. In this manner, the user can see an initial version of the image more quickly than if the browser waited until the full-resolution image were received and rendered.
Web pages often extend beyond the area that is initially viewable on a window of the user's display screen. Typically, an initial portion of the web page is shown (occupying either the full display screen or a window on the display screen; this display area is referred to herein as a "viewport"), and the user can scroll down to see the remainder of the web page. Web page authors often take into account which areas of the web page are likely to be initially viewable upon presentation of the web page. However, such areas differ from client to client, depending on various factors such as screen size, screen resolution, browser settings, user-specified preferences, and the like. Tools such as Google Browser Size, available from Google Inc. of Mountain View, Calif., provide web page authors with guidance as to which areas of the web page are likely to be initially viewable by what percentage of users.
Existing image optimization methods do not adequately take into account which areas of a web page are likely to be initially viewable upon presentation of the web page. Rather, such existing techniques generally make no distinction between those images that are likely to be initially viewable and those that are not.

System and method for presenting content in a client/server environment


Disclosed herein is an electronic component package including: a connection member provided on at least one surface of a substrate; an active element coupled to the substrate by the connection member; a molding part covering an exposed surface of the active element; and an additional layer formed on an exposed surface of the molding part to decrease a warpage phenomenon. In the electronic component package, the warpage phenomenon may be decreased as compared with the related art.

1. Technical Field
The present invention relates to an electronic component package.
2. Description of the Related Art
Recently, miniaturization and lightness of a portable electronic product such as a smart phone have been continuously conducted. Therefore, miniaturization and lightness of electronic components mounted in the portable electronic product have also been conducted.
Meanwhile, as a function of each of the electronic components has been improved and a size thereof has continuously decreased, the case of packaging the electronic component in order to protect the electronic component and increase efficiency of a manufacturing process has been increased.
As an example, in Patent Documents 1, 2, or the like, a technology related to a package on package (POP) has been introduced. Particularly, in Patent Document 1, the case of implementing a molding part using an epoxy molding compound (EMC) has been introduced.
Meanwhile, in accordance with the trend toward slimness of various electronic devices, thicknesses of a substrate, a molding part, and the like, have been continuously decreased. However, in the case of implementing the molding part using the EMC as in Patent Document 1, as an electronic component package is slimmed, a warpage phenomenon in a high temperature environment is intensified.
This warpage phenomenon causes serious problems such as deterioration of connectivity, generation of a crack at a contact portion, and the like, when an electronic component package is connected to other devices.


An optical receiver includes a light receiving element configured to convert an input light signal into an electric current, a current mirror circuit including a reference current side transistor and a mirror current side transistor, the transistor being connected to the light receiving element, a current-voltage conversion circuit configured to convert an output current from the transistor into a voltage and output the voltage as a light reception level monitor voltage of the light receiving element, and a current sink circuit connected to the transistor and configured to feed an electric current to the transistor.

As a system for realizing a public line network using an optical fiber, an access system optical communication system of point-to-multipoint called PON (Passive Optical Network) system has been widely used.
The PON system includes one OLT (Optical Line Terminal), which is a station-side device, and a plurality of ONUs (Optical Network Units), which are subscriber terminal devices, connected to the OLT via an optical star coupler. The PON system has advantages that economization of operation costs can be expected because the OLT and the most part of optical fibers, which are transmission lines, can be shared among a large number of ONUs, the optical star coupler, which is a passive component, does not require power supply and is easily set outdoors, and the reliability is high. Therefore, the PON system has been actively introduced in recent years as a trump card for realizing a broadband network.
For example, in a 10G-EPON (10 Gigabit-Ethernet (registered trademark) Passive Optical Network) which is capable of performing communication at transmission speed of 10 Gbit/s standardized by IEEE (Institute of Electrical and Electronic Engineers) 802.3av, a broadcast communication system by a 1.58 μm band is used in downward communication from the OLT to the ONUs. The ONUs divide transmission speed using WDM (Wavelength Division Multiplexing) filters for performing wavelength division multiplexing and extract only data addressed to the own stations in time slots allocated to the ONUs. On the other hand, in upward communication from the ONUs to the OLT, an optical wavelength 1.27 μm band is used and a time division multiplex communication system for controlling transmission timing is used to prevent data from the ONUs from colliding with one another.
In the upward communication of the PON system explained above, a light receiving unit of the OLT receives burst light signals. In the OLT, by detecting the light reception level of each of the burst light signals, there is an effect that it is possible to improve the quality of the upward communication of the PON such as communication state monitoring and presence or absence of the burst light signal. Therefore, it is necessary to detect the light reception level of each of the burst light signals. For example, Patent Literature 1 and Patent Literature 2 propose a technology for detecting a light reception level in a point-to-point system.

Optical receiver, station-side optical network unit, and light reception level monitoring method


A method for providing wireless connection capability for a telematics unit including determining a connection failure between the telematics unit and a call center, providing the telematics unit with an alternative cellular identifier pair at the telematics unit based on the determination and attempting to establish a connection between the telematics unit and the call center using the alternative cellular identifier pair.

The opportunity to personalize features in a mobile vehicle is ever increasing as the automobile is being transformed into a communications and entertainment platform as well as a transportation platform. Many new cars will be installed with some type of telematics unit to provide wireless communication and location-based services. These services may be accessed through interfaces such as voice-recognition computer applications, touch-screen computer displays, computer keyboards, or a series of buttons on the dashboard or console of a vehicle.
Currently, telematics service call centers establish a voice or data communication channel between a telematics unit and the call center to provide various types of location services, including sending emergency help to a vehicle when air bags deploy, stolen vehicle tracking, traffic information, weather reports, road condition information, accident updates, street routing, and business finders.
When a user attempts to establish a non-emergency communication channel between the telematics unit and the call center, the service provider opens the communication channel after the transmitted mobile identification number (MIN) and electronic serial number (ESN) are recognized as an authorized MIN/ESN pair. The initial call attempts to establish a data connection from the telematics unit to the call center, sending information such as the location of the vehicle and vehicle identification. If the attempt to open the communication channel fails the telematics unit automatically makes one or more attempts to open the non-emergency communication channel over normal cellular communication channels using the same MIN/ESN pair. If one or more additional attempts fail, the telematics unit informs the user that the call attempt has failed. An additional attempt is made using a voice only connection rather than a data connection. However, even the voice connection is subject to some failures.
The telematics unit continues indefinitely to establish an emergency communication channel between the telematics unit and the call center. In this case, additional call attempts are made followed by a non-authenticated voice call attempt. Non-authenticated voice calls, also known in the art as cleared calls, are comprised of predetermined phone numbers that are not checked by the carrier or network for validity. All the attempts to place the call are made over normal cellular communication channels using the same MIN/ESN pair.
It is desirable to reprogram the network access device to use additional technologies and previously assigned and/or alternative cellular parameters to establish the communication channel between the telematics unit and the call center in the event that an attempt to establish a communication channel between the telematics unit and the call center fails.

Dynamic connection retry strategy for telematics unit


The present invention is directed to a bearing surface on a slider having a center split pressurization feature which minimizes the effects of altitude or change in ambient air pressure on the flying characteristics of the slider. After a cavity dam and a subambient pressurization cavity is the center split feature. The center split feature is located proximate the centroid of the slider body and the bearing surface. The center split feature has, at least, three levels including a first center split level a second center split level and a third center split level. The first center split level is at the same level as the bearing surface level and is located closest to the centroid. The second center split level is located forward of, in the direction of air flow, the first center split level. The second center split level is also recessed from the first center split level to the same level as the first recessed level. The third center split level is located forward of the second center split level and is recessed from the second center split level.

Disc drives of the "Winchester" and optical types are well-known in the industry. Such drives use rigid discs, which are coated with magnetizable medium for storage of digital information in a plurality of circular, concentric data tracks. The discs are mounted on a spindle motor, which causes the discs to spin and the surface of each disc to pass under a hydrodynamic bearing disc head slider. The slider typically carries a transducer, which writes information to and reads information from the disc surface. Typically, a single disc surface will have one disc head slider passing over the surface.
In a conventional disc drive, multiple discs are coupled to and rotate about a spindle. Each of the discs has two substantially flat surfaces that are capable of storing data. Typically these discs are stacked in a parallel relationship with each other. The sliders are designed to move within the space between the adjacent discs while flying in close proximity the disc surface. The slider is coupled to the distal end of a thin, arm-like structure called a head suspension assembly (HSA), which is inserted within the space between two adjacent discs.
The track accessing arm moves a slider or group of sliders from track to track across the surfaces of the disc. The track accessing arm typically includes a head gimbal assembly, a load beam, an actuation component to move the track accessing arm, and a read/write head and slider supported by the head gimbal assembly. The load beam provides a load force which encourages the slider towards the disc surface. A gimbal is positioned between the slider and the load beam, or is integrated into the load beam, and provides a resilient connection that allows the slider to pitch and roll while following the typography of the disc.
The slider typically includes a bearing surface which faces the disc surface. As the disc rotates, air is drug underneath the slider by the disc and along the bearing surface in a direction approximately parallel to the tangential velocity of the disc. As the air passes beneath the bearing surface, air compression along the air flow path causes the air pressure between the disc and the bearing surface to increase, which creates a hydrodynamic lifting force which counteracts the load force and causes the slider to lift or "fly" above or in close proximity to the disc surface.
One type of slider is a "self-loading" air-bearing slider, which includes a leading taper, a pair of raised side-rails, a cavity dam and a subambient pressurization cavity. The leading taper is typically lapped or etched onto the end of the slider that is opposite the read/write head. The leading taper pressurizes the air as the air is dragged under the slider by the disc surface. An additional effect of the leading taper is that the pressure distribution under the slider has a first peak near the tapered end or "leading edge" due to high compression angle of the taper step, and a second peak near the read/write head or "trailing edge" due to a low bearing clearance necessary for efficient magnet recording. This dual peak pressure distribution results in a bearing with a relatively high pitch stiffness.
The bearing clearance between the slider and the disc surface at the read/write head is an important parameter to disc drive performance. As average flying heights continue to be reduced, altitude induced and manufacturing variation induced fly height loss are an increasing source of head contact and modulation that lead to read/write failures. In addition, variation in slider shape (i.e. crown and cross curvature) also lead to unwanted head/disc contact.
Further, there is a tendency for the slider to change both its pitch angle and its fly height as the ambient air pressure around the disc surface changes as a result of altitude changes to the drive. This change in flying characteristics of the slider can result in the head crashing into the surface of the disc, causing damage to the information contained on the data surface. Prior art sliders have used lap pads or diamond-like carbon (DLC) pads to account for this change in fly height as well as to reduce the stiction force associated with the slider contacting the disc surface. A typical slider without pads is typically designed to fly at a pitch angle of approximately 160 micro radians. When the slider is fitted with pads, the slope of the pitch angle is increased to approximately 220 micro radians. This increased slope created by the pads results in a high pitch offset and an increased sensitivity to ambient pressure changes.
The flying characteristics of the slider are typically controlled by variations in the pressurization over the surface of the slider. A slider typically experiences areas of positive pressure and areas of negative pressure. The areas of positive pressure tend to cause the slider to rise above the surface of the disc. Whereas, areas of negative pressure tend to cause the slider to move towards the surface of the disc. By balancing these pressurization areas a slider designer is able to control the flying characteristics of the slider. Typically, disc sliders have a positive pressure area at the leading edge and at the trailing edge or near these regions. Some sliders also have a positive pressure area along the side edges. Sliders commonly have a cavity dam after the leading edge pressurization feature which creates an area negative pressure to help offset the positive pressure force generated by the leading edge feature, and to encourage the slider towards the disc surface while maintaining the designed pitch angle. However, when the altitude of a slider is increased, for example, by taking the drive up in an airplane, the pressure differential generated by these two areas of pressure is often not enough to maintain the designed flying characteristics. Therefore, a slider design is desired which minimizes the sensitivity of the slider to altitude.
Embodiments of the present invention provide solutions to these and other problems, and offer other advantages over the prior art.

Center split feature and pressurization for altitude insensitivity, high pitch torque and high preload sensitivity air bearing slider


The invention provides improvements in reconstructive imaging of the type in which a volume is reconstructed from a series of measured projection images (or other two-dimensional representations) generated by projection of a point x-ray source (or other radiation source), positioned at a distinct focus, through the volume to a plane at which the respective projection image is acquired (“detector plane”). In one aspect, the improvements are with respect to back-projecting a two-dimensional representation lying in the detector plane (representing, for example, a difference between an originally-acquired measured projection image and a subsequently-generated estimate thereof) to generate three-dimensional representation (which can be used, for example, to update an estimate of the volume). According to this aspect, for each of one or more slices of the 3D representation parallel to the projection plane and for each distinct focus at which a projection is generated, the following steps are performed in connection with the back-projection: (i) warping the first 2D representation to generate a second 2D representation by applying to the first 2D representation a selected linear mapping, where that selected linear mapping would map, in order to match dimensions of the respective slice within the 3D representation, a region defined by projection, at the respective focus, of corners of that slice onto the detector plane, and (ii) incrementing values of each of one or more voxels of the respective slice by an amount that is a function of a value of a correspondingly indexed pixel of the second 2D representation. A related aspect provides improvements with respect to forward-projecting, as well as in iterative (and non-iterative) methodologies that incorporate both back-projection and forward-projection.

The invention relates to digital data processing and, particularly, to novel methods and apparatus for forward-projection and back-projection for use, e.g., in reconstructive imaging. The invention has application in health care and, specifically, medical imaging—as well as in a host of other areas, such as manufacturing, security, research, and defense.
A forward-projection is an operation for estimating the (two-dimensional) transmission or emission shadow that would result from illumination of a (three-dimensional) object by a point source which emits radiation that partially passes through the object. By way of example, a forward-projection could be performed in order to provide an estimate of what an x-ray image of a human might look like. The term forward-projection also refers to the estimate that is determined from executing a forward-projection operation.
A back-projection is an operation for generating a simple estimate of the structure of a (three-dimensional) object that could produce a given (two-dimensional) transmission or emission shadow, if that object was illuminated by a point source which emits radiation that at least partially passes through the object. To continue the example, a back-projection could be performed in order to generate a simple estimate of the body structures the imaging of which resulted in a particular x-ray image. As above, the term back-projection also refers to the estimate that is determined from executing such a back-projection operation.
Reconstructive imaging is a procedure for constructing a three dimensional (3D) model of a subject from a series of two-dimensional (2D) projection images. These projection images are typically generated by exposing the subject to a x-ray (or other radiation) point source that is positioned on one side of the subject and measuring the transmitted (or non-absorbed) radiation with a 2D detector that is positioned on the opposite side of the subject. A series of these projections is created by repeatedly measuring the transmitted radiation as the point source and/or the detector are moved differing locations relative to the subject.
For example, computed axial tomography (CAT) is a reconstructive imaging technique in which a three-dimensional model of the internals of an object—typically, some portion of the human body—is constructed from a series of two-dimensional x-ray projections taken at evenly spaced angles that surround the object. With the aid of a computer, the series of acquired 2D projection images are computationally projected backwards to estimate the relative density of the internal structures of the object (e.g., in the case of a head, the skull, gray matter and other resolvable structures). While no one of these back-projections is, by itself, sufficient to identify those structures, the computational combination of all of the back-projections typically produces a reasonable 3D representation of the object. Because this typically involves performing back-projections on hundreds, if not thousands, of projected images, reconstruction systems typically incorporate special-purpose hardware in order to provide timely results. Though prior art solutions have proven effective in this regard, they are typically quite expensive.
Moreover, those prior art solutions for determining back-projections have limited applicability to a new class of imaging, referred to as tomosynthesis, in which a relatively small number of projection images are acquired from only a limited number of x-ray source positions (or foci). Typically, these foci are distributed across a limited arc. For this type of imaging, the requisite reconstruction requires an iterative approach. In these systems, the computations include not only back-projections, but also forward-projections, in which estimates of the volume being reconstructed are projected "forward" to generate hypothetical projection images for computational comparison with actual measured projection images acquired by the imaging equipment. By comparing the hypothetical forward projection of the current 3D model to the measured projection images, a correction image can be calculated and used to update (modify) the current 3D model.
CAT scanners and tomosynthesis systems are not the only medical imaging equipment that use forward-projections and/or back-projections. Forward-projection and back-projection operations also form the basis of a broader class of computer-based imaging techniques, referred to as computed tomography (CT), as well positron emission tomography (PET), single photon emission computed tomography (SPECT), to name but a few. In addition, back-projection and forward-projection are used outside the medical field, for example, in manufacturing (e.g., to inspect articles for defects), security (such as baggage scanning) in research, defense and so forth.
An object of the invention is to provide improved digital data processing apparatus and methods. Another object is to provide such apparatus and methods as can be applied in reconstructive imaging applications, e.g., of the types referred to above (by way of non-limiting example).
Related objects of the invention are to provide such apparatus and methods as can be performed more rapidly and with fewer computational resources. A related object of the invention is to provide such methods and apparatus as can be performed with less expensive equipment, off-the-shelf or otherwise.

Methods and apparatus for back-projection and forward-projection


An acoustic attenuator includes a housing having an inner side surface which defines an interior chamber and at least one dampening member both physically and acoustically coupled to the housing and projecting into the interior chamber. Acoustic energy propagating within the housing is deflected into the dampening members for acoustically dispersal within the interior chamber. In various aspects thereof, the dampening members may include one or a group of two or more generally cylindrical sleeves having one end both physically and acoustically coupled to the housing and a second end projecting into the interior chamber. Preferably, when a group of two or more cylindrical sleeves are employed, the sleeves are nested within one another. The dampening members may further include a second, oppositely disposed, group of two or more acoustic attenuators nested within one another and interdigitated with the first group of cylindrical sleeves.

1. Technical Field
The present disclosure relates to an acoustic attenuator for use in downhole applications. More particularly, the present disclosure relates to a low frequency downhole acoustic attenuator configured to attenuate acoustic signals at frequencies below 5 kHz and preferably in a low frequency bandwidth extending from about 300 Hz to about 2 kHz.
2. Description of Related Art
Geologists and geophysicists are often interested in the characteristics of subsurface earth formations encountered by a drill bit as it drills a well for the production of hydrocarbons from the earth. Such information is useful in determining the correctness of the geophysical data used to choose the drilling location and in choosing subsequent drilling locations. In horizontal drilling, such information can also be useful in determining the location of the drill bit and the direction that drilling should follow. It should be readily appreciated by those skilled in the art that the foregoing is but a rudimentary description of some of the ways in which information regarding the characteristics of a subsurface earth formation would be useful to geologists, geophysicists and/or others involved in the exploration of the subsurface earth formation. It is, however, a sufficiently detailed description for the purposes disclosed herein.
Information related to the characteristics of a subsurface earth formation can be derived in a number of ways. For example, cuttings from the mud returned from the drill bit location can be analyzed or a core can be bored along the entire length of the borehole. Alternatively, the drill bit can be withdrawn from the borehole and a wireline logging tool can be lowered into the borehole to take measurements. Other approaches, commonly referred to as either measurement-while-drilling (MWD) or logging-while-drilling (LWD) techniques, involve the use of tools which make measurements in the borehole while the drill bit is working. Of the aforementioned techniques, MWD and LWD are generally preferred because, by employing such techniques, information related to the subsurface earth formation may be acquired quicker and at lower cost. Currently, however, the bandwidth available for downhole telemetry systems, for example, mud pulse or electromagnetic (EM) telemetry systems, is insufficient for transmitting essential MWD or LWD data in real time. As a result, data acquired by a MWD or LWD tool is often stored in a local memory in the tool and not retrieved from the local memory until after the tool has been removed from the borehole. As a result, data acquired by a MWD or LWD tool is not always available for analysis in real time.
The transmission of acoustic telemetry data through the drill pipe itself has been periodically contemplated. Acoustic telemetry systems which transmit acoustic data through a drill pipe have been able to transmit data at rates exceeding 50 bits-per-second (bps). A problematic issue related to the transmission of acoustic data through a drill pipe while drilling operations are being conducted is that on-going drilling operations tend to generate wide bandwidth noise which contaminates the acoustic data transmission channel through which acoustic data is being transferred. One source of such noise is the drill bit typically located at the end of the drill pipe. Another is the top drive or other mechanical equipment located at the surface and coupled to the drill pipe. Regardless of the source thereof, such noise tends to reduce the signal-to-noise (SNR) ratio within the acoustic data transmission channel. As a result, the rate at which acoustic data may be transmitted through the acoustic data transmission channel is reduced.
It should be appreciated that, by incorporating one or more devices capable of absorbing low frequency acoustical energy into a drill string, the amount of noise entering an acoustic data transmission channel of the drill string would be reduced. As a result, data acquired by a downhole data transceiver and transmitted to the surface via the acoustic data transmission channel is less likely to be contaminated by extraneous noise.

Low frequency acoustic attenuator for use in downhole applications


A notch alignment apparatus has a unit body (15), which can advance into a carrier (3) through a bottom opening (4) of the carrier (3), for aligning notches (2) formed in the peripheral edges of semiconductor wafers (1), which are contained in the carrier (3) and arrayed in a facing state. The unit body (15) is provided with a rotationally driving shaft (25) having a cylindrical shape, for coming into contact with the peripheral edges of the wafers (1) from below and driving the wafers (1) to rotate all together. A plurality of idle pulleys (26) independent of each other are arranged on one side of the driving shaft (25), for coming into contact with the peripheral edges of the wafers (1) from below. The idle pulleys (26) are supported by a common pulley shaft (27) to be independently and freely rotatable. A stopper or wafer guide (28) is arranged on the other side of the driving shaft (25), for stopping rotation of the wafers (1) by means of contact with the peripheral edges of the wafers (1). The stopper (28) is arranged such that the peripheral edge of each wafer (1) comes into contact with the stopper (28) when that the wafer (1) engages with the driving shaft (25) by its notch (2) and inclines. The driving shaft (25) and the pulley shaft (27) are driven to rotate along with each other in the same direction.

The present invention relates to a notch alignment apparatus for aligning the notches of target objects, such as semiconductor wafers, contained in a container and arrayed in a facing state, and an adjustment jig for the notch alignment apparatus.
In manufacturing semiconductor devices, a container, which is also referred to as a carrier or cassette, is used for containing a plurality of target objects, i.e., semiconductor wafers, in a facing state when the wafers are transferred among processing steps. Semiconductor wafers are provided with orientation flats or notches, i.e., cut-out portions, respectively, at their peripheral edges to easily judge and align their crystal orientations.
Jpn. Pat. Appln. KOKAI Publication Nos. 6-345028 discloses a notch alignment apparatus for aligning the notches n of a plurality of semiconductor wafers W, contained in a container C and arrayed in a facing state. The apparatus have an alignment unit. The alignment unit has a driving shaft for coming into contact with the peripheral edges of the wafers from below to drive the wafers to rotate all together; a plurality of idle pulleys 20 independent of each other and arranged on one side of the driving shaft, for coming into contact with the peripheral edges of the wafers from below; and a stopper 30 arranged on the other side of the driving shaft, for stopping rotation of the wafers by means of contact with the peripheral edges of the wafers.
In this apparatus, each wafer W is essentially supported by the driving shaft and the corresponding idle pulley 20 while the wafer is rotated by the driving shaft. When the notch n of the wafer engages with the driving shaft and the wafer leans the peripheral edge of the wafer comes into contact with the stopper 30, thereby causing the wafer to stop its rotation. In this way, the notches of the wafers are aligned in the axial direction of the driving shaft.
Jpn. Pat. Appln. KOKAI Publication No. 7-235587 discloses a notch alignment apparatus for aligning the notches 2 of a plurality of semiconductor wafers 3, contained in a container 4 and arrayed in a facing state. The apparatus has an alignment unit 7 which is capable of moving up and down so that it can advance into the container through the bottom opening of the containers. The alignment unit has a driving shaft 11 (12) for coming into contact with the peripheral edges of the wafers from below to drive the wafers to rotate all together; a plurality of idle pulleys 43 independent of each other and arranged on one said of the driving shaft, for coming into contact with the peripheral edges of the wafers from below; and a stopper 28 arranged on the other side of the driving shaft, for stopping rotation of the wafers by means of contact with the peripheral edges of the wafers.
In this apparatus each wafer W is essentially supported by the driving shaft 11 and the corresponding idle pulley 43 while the wafer is rotated by the driving shaft. When the notch 2 of the wafer engages with the driving shaft and the wafer inclines, the peripheral edge of the wafer comes into contact with the stopper 28, thereby causing the wafer to stop its rotation. In this way, the notches of the wafers are aligned in the axial direction of the driving shaft.
In this type apparatus, however, alignment of the notches can not be correctly performed on occasion, because slip is caused between the driving shaft and the wafers, or the notches pass over the driving shaft, depending on the state of the wafers, for example, a state brought about after film formation. More specifically, the driving shaft is generally coated with a fluoro-resin to enhance its physical and chemical withstand capability, which in return results in a low frictional resistance. On the other hand, the peripheral edges of the wafers also have a low friction resistance, and much less especially after a film formation process, depending on the film material. Further, each notch generally has an opening width smaller than the diameter of the driving shaft. In addition, after a film formation process, the size of each notch becomes slightly smaller. As a result, the notches become apt to pass over the driving shaft. In this respect, the driving shaft may be coated with silicone rubber to improve the rotational driving capability of the driving shaft, but the silicone rubber is easily worn out.
On the other hand, such a notch alignment apparatus is known that has an optical sensor for confirming alignment of the notches. See U.S. Pat. No. 5,533,243. The sensor senses alignment of the notches in a state where the wafers are supported by and in a container after a notch alignment operation is finished and an alignment unit is moved down. By using the optical sensor, it is possible to raise an alarm or to repeat the notch alignment operation, if the notch alignment has not been correctly performed.
However, in the apparatus of this type, the notches and the optical axis of the optical sensor are not lined up on occasion due to a deformation or dimensional error of the container, thereby bringing about a sensing error. Further, the sensing accuracy of the optical sensor depends on its arranged state. Since the notch alignment apparatus is periodically disassembled, cleaned, and reassembled, it becomes more important to assemble it with high precision.

Notch alignment apparatus and adjustment jig for the same


The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

The transistor is the fundamental building block for electronic circuit design. Performance metrics, like speed, power consumption and the number of transistors used are directly related to the choice of transistor technology that is used for the implementation. The selected technology may hence strongly influence the circuit performance.
The main factors that define a field-effect transistor (FET) are the type of carriers used (n or p) and the threshold voltage. The type of carriers determines the response of an input voltage to the gate on the output current at the drain terminal. For a n-type device the on-current is increased as the gate voltage is increased, while for a p-type device the on-current is decreased as the gate voltage is increased. The type of conduction is set by the doping of the material. The threshold voltage determines the voltage level at which the transistor goes from the off-state to the on-state. In a planar technology the threshold voltage is given by the geometry of the device. Normally-on (or depletion mode) DFETs often have advantageous high-frequency performance as compared to normally-off (or enhancement mode) EFETs, since the channel in DFETs remains open on the source and drain side of the gate, which reduces the access resistance. EFETs often suffer from high access resistance as the external part of the channel remains partially depleted which adds resistance. It is hence well known in the field that it is difficult to design and fabricate good enhancement mode devices.
While circuits may be designed with one type of transistors only, it is often favorably to combine different types of transistors. For instance, in the complementary-metal-oxide-semiconductor technology (CMOS) n- and p-type metal-oxide-semiconductor field-effect transistors MOSFETs, are combined primarily to reduce the power consumption in logic elements. Notably, the CMOS does only consume negligible static power while the dynamic power consumption is dominating. The price to pay for this implementation is that the speed is set by the comparably slower PMOS transistors.
The main advantage of using semiconductors commonly referred to as III/V semiconductors is the carrier transport properties. n-type devices are typically considered mainly due to the substantially higher mobility for the electrons than for the holes. In III/V-design, where there is a lack of CMOS technology, design with DFETs only may be considered and has been demonstrated for instance in the unbuffered FET logic circuits and in Schottky diode FET logic circuits. These circuits, however, require level shifters for the switching between negative and positive biases and may even require two levels of signals in the circuit. This adds complexity to the circuit and increases the power consumption. Design with EFETs only is more advantageous, since the fact that the transistor is normally off reduces the static power consumption as compared to the DFET design. The drawback lies in the comparably lower speed of the EFET. In many applications, it is, however, desired to utilize both EFETs and DFETs and use the alternating threshold voltage to switch the conductivity between a pair of transistors, as employed in the directly coupled field effect logic (DCFL) circuits. These circuits have demonstrated record low-power and high-speed operation. The limitations in the planar technology are related to the mentioned difficulties in making EFETs with low access resistance, the difficulty to control the threshold voltage in the post-growth process, the presence of short-channel effects as the planar gate length is reduced, and the lack of suitable substrate and lattice-matched heterostructure material for the narrow band gap technologies.

Assembly of nanoscaled field effect transistors


A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.

1. Technical Field
The present invention relates generally to semiconductor technology, and more specifically to semiconductor research and development.
2. Background Art
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in a wide variety of products, such as televisions, telephones, and appliances.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each worth hundreds or thousands of dollars.
The ideal would be to have every one of the integrated circuits on a wafer functional and within specifications, but because of the sheer numbers of processes and minute variations in the processes, this rarely occurs. "Yield" is the measure of how many "good" integrated circuits there are on a wafer divided by the maximum number of possible good integrated circuits on the wafer. A 100% yield is extremely difficult to obtain because minor variations, due to such factors as timing, temperature, and materials, substantially affect a process. Further, one process often affects a number of other processes, often in unpredictable ways.
In a manufacturing environment, the primary purpose of experimentation is to increase the yield. Experiments are performed in-line and at the end of the production line with both production wafers and experimental wafers. However, yield enhancement methodologies in the manufacturing environment produce an abundance of very detailed data for a large number of wafers in processes subject only to minor variations. Major variations in the processes are not possible because of the time and cost of using production equipment and production wafers. Setup times for equipment and processing time can range from weeks to months, and processed wafers can each contain hundreds of thousands of dollars worth of integrated circuits.
The learning cycle for the improvement of systems and processes requires coming up with an idea, formulating a test(s) of the idea, testing the idea to obtain data, studying the data to determine the correctness of the idea, and developing new ideas based on the correctness of the first idea. The faster the correctness of ideas can be determined, the faster new ideas can be developed. Unfortunately, the manufacturing environment provides a slow learning cycle because of manufacturing time and cost.
Recently, the great increase in the complexity of integrated circuit manufacturing processes and the decrease in time between new product conception and market introduction have both created the need for speeding up the learning cycle.
This has been accomplished in part by the unique development of the integrated circuit research and development environment. In this environment, the learning cycle has been greatly speeded up and innovative techniques have been developed that have been extrapolated to high volume manufacturing facilities.
To speed up the learning cycle, processes are speeded up and major variations are made to many processes. To reduce costs, only a few wafers are actually processed for each cycle. This research and development environment has resulted in the generation of tremendous amounts of data and analysis for all the different processes and variations. This, in turn, has required a large number of engineers to do the analysis. With more data, the answer always has been to hire more engineers.
However, this is not an acceptable solution for major problems. A continuing need persists, for example, for faster, more efficient, and more economical methods and systems for testing flash memory integrated circuits in the course of their manufacture. Flash memory devices, for example, are tested at various stages for various performance characteristics. One important test is to check the integrity of the tunnel oxide ("TOX") layer of the flash memory cells. Currently, TOX weakness is only detected at final electrical testing of the completed flash memory devices, that is, at the very end of the manufacturing process. A much earlier, in-line test is needed, particularly since TOX formation is one of the earliest steps in flash memory manufacturing.
In view of the considerable processing that happens before TOX weakness is identified under conventional fabrication procedures, it would be very beneficial to be able to pre-screen flash memory devices for TOX weakness at a much earlier production stage. Such earlier detection would enable much earlier process adjustments, would avoid financial losses from needlessly completing wafers that were destined to fail, would thereby significantly improve production efficiencies, would improve overall testing time, and would shorten development cycle times. Ideally, such earlier detection would be performed by a quick, in-line pre-screen method that requires minimal intervention and processing to detect such TOX weakness.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development


When a buyer's debt to a seller cannot be paid using an account issued to the buyer by an issuer within a payment processing system, then either or both the seller and the buyer are solicited to conduct future transactions payable on the account. If the debt can be paid using the account, then a sub-account is created unique to the seller and buyer. Transactions between the buyer and seller can be processed using the sub-account including the option of aggregating the debts prior to the processing. The credit limit of the sub-account can be set to match the amount of the aggregated debts.

Businesses often process their transactions with other businesses through various means of payment types, such as by a credit account, a checking account, or an Automated Clearing House (ACH) credit transfer. For example, a buyer may have a purchase order (PO) for a seller disclosing the goods the buyer wishes to purchase. The PO may have several payment types associated with it depending on such factors as contractual obligations or credit limits. Consequently, the buyer may pay for certain goods using a check while paying for other goods with a credit card. Similarly, multiple POs may have multiple payment types.
Typically, PO or invoice payments are processed manually. The buyer may look through an accounts payable file and, based on the payment type, write checks to a seller, request the seller to charge a credit card, or prepare a money order for the seller, for example.
The process of manually determining the payment type for a payment, choosing between different systems that process the payment type, and disseminating the payment request through the different systems can become cumbersome to track, reconcile, and control. For example, each PO may be processed separately, resulting in inefficiencies as multiple payments are made to the same buyer during a window of time.
Some organizations utilize an Enterprise Resource Planning (ERP) system which typically integrates data into a single unified system within the organization, such as by storing the accounts payables of the organization into a single database. The ERP system can assist in organizing the accounts payables of the buyer or the accounts receivables of the seller; however, the ERP system does not automatically process each payment type through the different systems nor does the ERP automatically reconcile remitted payments to the corresponding invoices and/or POs.
Moreover, certain payment types may have advantages that may be underutilized when buyers or sellers process their accounts payables or accounts receivables in-house. For example, an account such as a credit account, within a payment processing system may have remittance guarantees or conditional incentives that may be beneficial to the business owner. The seller may prefer payments made on an account within the payment processing system because the payment processing system may facilitate remittance of the payment within a period of time or provide promotions options that increase the sales of the seller. The buyer may prefer payments made on the account because the account may be part of a loyalty program such that the buyer can receive a benefit by utilizing the account when conducting transactions. In a business-to-business transaction, the loyalty program may include cash back, insurance coverage for goods purchased, or frequently flyer miles, for examples. These benefits may be underutilized because the buyer or the seller engaged in trade may not be aware of the capability of the other to process the transaction on the account or the buyer or the seller may not know of the other's preference.
There is a need for a system in which the processing of payment obligations from the buyer to the seller can be automated. This and other problems, individually and collectively, are addressed herein.

Payment processing system debt conversion notification


A surgical patient support includes a foundation frame, a support top, and a brake system. The foundation frame includes a first column and a second column. The support top is coupled to the first column and the second column for rotation about a top axis extending along the length of the support top. A single-handle unlock for the support top is also provided.

The present disclosure relates to patient support apparatuses such as are used to support a patient in different positions. More particularly, the present disclosure relates to surgical tables used during surgery to support a patient in a predetermined position or number of positions. However, the present disclosure may also be applicable to other types of patient support apparatuses such as hospital beds, home care beds, x-ray tables, therapy supports, wheel chairs, and the like.
Sometimes, surgical tables allow adjustment of the table prior to surgery so that patients can be properly supported or held in place for a particular surgical operation. Also, some surgical tables allow adjustment during surgery so that a patient is moved to different positions during an operation. Many such surgical tables are difficult to adjust prior to and/or during surgery.

Bracket attachment apparatus for dual column surgical table


The present invention discloses a plasma etching apparatus which can protect the surface of the wafer from a damage due to collisions among the etching ions and can also process a plurality of wafers only by one-time plasma generation. In the etching apparatus of the present invention, a plurality of wafers are loaded in the chamber by a plurality of wafer support members which are located vertically round the gas dispersion tube used as a cathode electrode, and magnetic field formation means are provided to form a magnetic field around each wafer.

1. Field of the Invention
The present invention relates to a plasma etching apparatus, and more particularly to a plasma etching apparatus which can prevent the surface of the wafer from damage due to collisions of the etching ions and can also process a plurality of wafers simultaneously.
2. Description of the Prior Art
Generally, an etching process which is one of the manufacture processes of the semiconductor device is classified into a wet etching and a dry etching methods depending on the etching method. The wet etching for an isotropic etching uses chemicals, and the dry etching is mainly used for an anisotropic etching. The dry etching is usually called a plasma etching since it uses a reaction in the plasma state. The general plasma etching apparatus for a plasma etching process will be explained below by reference to FIG. 1.
As shown in FIG. 1, a chamber 1 which is a component of the plasma etching apparatus has a space in which an etching process of a wafer is performed by means of a generated plasma, an etching gas supplying tube 2 for supplying an etching gas into the chamber 1 is connected to an upper side of the chamber 1. The chamber 1 and the etching gas supplying tube 2 are electrically isolated each other by an insulator 8, and an end of the etching gas supplying tube 2, which is located at an internal space of the chamber 1, is connected to a dispersion plate 3 for dispersing evenly the etching gas into the internal space of the chamber 1. The dispersion plate 3 is also used as a cathode electrode to which a RF power generated in a RF power generator 4 is applied when a plasma is formed. Meanwhile, a wafer support member 5 for supporting a wafer 6 is provided at a bottom of the internal space of the chamber 1. The wafer support member 5 is electrically grounded and is used as an anode electrode when a plasma is formed. A vacuum supplying tube 7 for supplying a vacuum pressure so as to maintain the interior of the chamber 1 at a vacuum state is connected to one side of the chamber 1, the vacuum supplying tube 7 is connected to an external vacuum outlet pump (not shown).
Now, the etching process which is performed in a conventional plasma etching apparatus constructed as described above will be explained as follows.
First, after a wafer 6 on which an etching mask is formed is loaded to the wafer support member 5, an etching gas is supplied into the internal space of the chamber 1 through the etching gas supplying tube 2. When the etching gas is dispersed into the internal space of the chamber 1 through the dispersion plate 1, the RF power generator 4 is activated to apply a RF power to the dispersion plate 3. Accordingly, an electric field is formed between the dispersion plate 3 used as a cathode electrode and the wafer support member 5 used as an anode electrode. The etching gas is plasmarized by means of the electric field, and then etching radicals are formed.
At this time, the movement of etching ions to the wafer 6 is accelerated by a sheath potential of a plasma, and the accelerated etching ions are collided physically with the surface of the wafer 6, an etching of the wafer 6 is performed. However, as the etching ions are collided with the surface of the wafer in the state in which etching ions have a rapid acceleration, the surface of the wafer 6 will be damaged, therefore, a reliability of the device is degraded due to this damaged surface of the wafer 6. In addition, in the conventional plasma etching apparatus, as the wafer 6 is loaded on the wafer support member 5 in parallel to the dispersion plate 3, particles generated from the cathode electrode and the plasma are directly adsorbed to the wafer 6, therefore, these particles affect reliability of the device. Also, since only one wafer 6 is loaded on the wafer support member 5 in the etching apparatus, a plasma is generated repeatedly so as to perform an etching process for a plurality of wafers. Due to this fact, as the process conditions for performing a process for each wafer, for example the amount of the etching gas supplied, are different, the etching uniformities among the wafers are different each other.

Hyundai Electronics Industries Co., Ltd.


The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate, and an etch is performed so as to form trenches within the semiconductor substrate. An anti-reflective film is deposited such that it extends within the trench. A dielectric film is deposited over the anti-reflective film such that it fills the trench. A heating process step is then performed to anneal the substrate, rounding the corners of the trench. A chemical mechanical polishing process is performed to remove those portions of the anti-reflective film and the dielectric film that overlie the hard mask. The hard mask is then removed, producing a shallow trench isolation structure that prevents lifting and notching in subsequent fabrication steps.

Shallow trench isolation structures are used in semiconductor device fabrication to isolate active areas of the semiconductor substrate. Typically, shallow trench isolation structures are formed by etching the top surface of the semiconductor substrate so as to form trenches that extend into the semiconductor substrate. These trenches surround areas of the semiconductor substrate that are commonly referred to as "active areas." A layer of oxide is then deposited to fill up the trenches, electrically isolating active areas from each other.
Conventional shallow trench isolation structures usually include trenches that have a flat horizontal bottom and that have vertical sidewalls. The sharply angled bottom corners of conventional shallow trench isolation structures result in thermal-mechanical stress buildup concentrated at the bottom corners. This corner stress buildup can result in localized stress-related defects. In severe cases, stresses from subsequent process steps and from thermal cycling can cause dislocation and cracking. This can cause device failure, resulting in reduced manufacturing yield and increased manufacturing costs.
Another problem that can arise with respect to conventional shallow trench isolation structures is electrical field buildup enhancement at top corners of the active area. The sharper the corner is, the greater enhancement of the field buildup will be. As a result, the corner portion of the transistor will have lower threshold voltage than the the main channel portion of the transistor. This phenomenon, commonly referred as "kink effect," can produce early turn-on of transistors and undesired cross-talk between adjacent devices.
One method for reducing stress buildup and kink effect is to form an oxide liner by performing an oxidation step prior to filling the trench. However, conventional processes for forming oxide trench liners use high temperature processes (often at temperatures of greater than 1,100 degrees centigrade), which stress the substrate, resulting in undesired stress buildup.
After the formation of conventional shallow trench isolation structures, implantation steps are performed so as to form various doped regions. During these subsequent implant steps, resist masks are exposed and developed to define the areas that are to be doped. However, when the resist thickness is not sufficient to block incoming light, some of the light passes through the resist and into the trenches. This light reflects off of the sidewalls of the trench so as to cause resist notching and lifting. Resist notching exposes areas of the active areas that are supposed to be covered by resist, causing undesired implantation. Lifting results in resist covering areas that were supposed to be exposed, preventing the implantation of desired impurities.
One method for preventing this problem is to increase the resist thickness during implant process steps. However, this can result in bridging and may not be practical when features less than 0.13 micron must be formed.
Accordingly there is a need for a shallow trench isolation structure and a method for forming a shallow trench isolation structure that reduces localized stress-related defects and "kink effect." Also, there is a need for a shallow trench isolation structure and a method for forming a shallow trench isolation structure that will reduce or eliminate notching and lifting in subsequently formed resist masks. The present invention meets the above needs.

Method for forming shallow trench isolation structure with anti-reflective liner


A load control system may include a load control device for providing power to an electrical load and a control device that may send instructions to the load control device for providing the power to the electrical load. The control device may communicate with the load control device using a link address assigned to the load control device. The load control device may provide power to the electrical load in a manner that causes the electrical load to indicate the link address assigned to the load control device. The link address may be identified by a user or a user device. The identified link address may be associated with a load control device identifier that may identify a physical location of a load control device that is assigned the link address. A user may control a load control device at a physical location by sending instructions via the link address.

Lighting systems may include a lighting load, an electrical ballast for controlling electrical power to the lighting load, and/or a ballast control device capable of sending instructions to the ballast for controlling the electrical power provided to the lighting load. Typically, after the lighting system is installed in a location, such as a residence, an office, or the like, the ballast control device may assign a link address to each ballast that it controls. The link address may be used for sending instructions to the ballast. This assignment may be done at random. For example, a ballast control device may be capable of controlling 64 ballasts and may randomly assign each ballast a link address (e.g., 1-64).
However, it is difficult to determine what ballast address was assigned to a ballast at a specific location. For example, a floor plan may indicate each ballast and its corresponding location in a room or building, and the ballast control device may have a list of the assigned link addresses. However, the installer, at the location of a particular ballast, cannot readily identify that particular ballast's address. Similarly, the installer, with a particular link address, cannot readily identify the corresponding location of the ballast with that link address.
FIG. 1 shows a prior art example used for determining a link address assigned to a ballast in a lighting system. As shown in FIG. 1, each of rooms 102, 104, and 106 may be in the same building and may be installed with one or more lighting loads. Rooms 102 and 104 may be on the same floor of the building, while rooms 102 and 106 may be on different floors. Each lighting load may be controlled via a ballast. Each ballast may be randomly assigned a unique identifier by the ballast control device 112 for sending instructions to the ballast for controlling the lighting load.
To determine the link address associated with each of the ballasts, a user 116 may select a link address that the user 116 wishes to identify at the computer 114 and the computer 114 may send instructions to the ballast to instruct the ballast that has been assigned the link address to flash its lighting load for identification. For example, the user 116 may select a unique identifier that has been assigned to ballast 110 and may send instructions which may cause the lighting load 108 that is controlled by ballast 110 to flash on and off.
As the ballast control device 112 may be capable of controlling up to at least 64 ballasts, and the ballast 110 may be installed in multiple rooms throughout a building, the user 116 may instruct the ballast 110 to identify itself via the lighting load 108, while user 118 searches multiple rooms (e.g., rooms 102, 104, and/or 108) throughout the building to find the flashing lighting load 108. Once the lighting load 108 is identified, the user 118 may communicate the ballast identity of the ballast 110 to the user 116 and the user 116 may associate the ballast identity (e.g., indicating the ballast location) with the selected link address. This association may be stored in the computer 114 such that the user 116 can properly identify the ballast 110 and configure the lighting system by sending instructions to the ballast 110 using the link address assigned to the ballast 110.
FIG. 2A depicts example prior art floor plan displays 202, 204, and 206 that may be used to identify the installed ballasts. The floor plan displays 202, 204, and 206 may be displayed on the computer 114 and/or may illustrate the layout of the ballasts in rooms 102, 104, and 106, respectively. A user 116 may instruct the ballast assigned a first link address Addr1 to identify itself. Using the floor plan displays 202, 204, and 206, the user 118 may identify the ballast 110 as corresponding to ballast B9 in the floor plan display 202. Once the ballast 110 is identified, the user 118 may communicate the identified ballast to user 116 and user 116 may associate the ballast 110 with link address Addr1 in an association table, such as the association table 210 shown in FIG. 2B for example. The association table 210 may then be used for looking up the link address associated with the ballast 110 when the lighting system is being configured.
As shown in FIG. 2B, the association table 210 may be included in a graphical user interface (GUI) 208 that may be displayed on the computer 114 and used to associate the installed ballasts with their link addresses. After the user 116 completes the association of the ballast 110 with its link address, the user 116 can flash the lighting load of the ballast associated with the next link address by selecting the button 212. The users 116 and 118 may perform the same process described above for each ballast in the lighting system. This process of address assignment may be time consuming and costly, particularly when the lighting system is installed in a large building having many different rooms controlled by one or more ballast control devices. In fact, this form of address identification may account for about 20% of a company's post-installation commissioning costs.


A calibration apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when a bias signal is applied to it is disclosed. The apparatus includes a test magnetic field generator (MFG) to generate magnetic fields of known magnitude, and further includes a processor to control the MFG to generate a known magnetic field, control the sensor to generate a test output signal when the MFG generates the known magnetic field and a known bias signal is applied to the sensor, and determine how to change the bias signal based on a deviation of the measured test output signal from an expected output signal. Using a test MFG that produces known magnetic fields when known bias signals are applied to sensors allows evaluating and compensating for changes in sensitivity of the sensors by accordingly changing bias signals applied to the sensors.

Magnetic sensors, such as magnetoresistive (MR) sensors, can be used for magnetic field sensing in a wide range of industrial, automotive, and healthcare applications. For example, magnetic sensors can be configured in a Wheatstone bridge and the output voltage of the sensors can be proportional to an external magnetic field sensed with respect to the internal magnetization of the sensors. In certain instances, such sensors may have a signal-to-noise ratio (SNR) close to 100 dB making them attractive for high-precision applications, and for low-power and size-limited applications.
One example application of magnetic sensors is for current measurement apparatuses where magnetic sensors may be used to perform measurement of currents through conductor wires without coming into contact or breaking the wires (i.e., in a contactless manner). Such contactless current measurement may be useful for diagnostic, operational, and protection purposes in many settings, such as residential, industrial, and automotive.
One of the challenges with using conventional magnetic sensors for magnetic field sensing is the variation of sensitivity of the sensors with external magnetic field and/or temperature. Another challenge is that conventional housing structures in which magnetic sensors are typically provided may not always fit inside tight places or other constrained areas where measurements may need to be carried out. Improvements on one or more of these challenges would be desirable.


A binary to unary decoder for a video digital to analog converter is cascadeable in both a horizontal and a vertical direction. Video data is transmitted from a video data source and received by a plurality of unary decoders which convert the video data to a corresponding number of unary digits having comparable value. The unary decoders are arranged in a number of cascaded levels. A plurality of cascaded unary block drivers receive the unary digits and transit unary output digits to a video data bus. The plurality of unary block drivers are arranged in a number of tiers having a predetermined number of individual unary block drivers. The predetermined number of cascaded unary block drivers are enabled based upon the numerical value of the video data.

The present invention relates to a binary to unary decoder and, more particularly, to a binary to unary decoder for a video digital to analog converter which is cascadeable in both a horizontal and a vertical direction.
In a typical graphics display system for a personal computer, a digital video signal is retrieved from a memory array and converted into an analog video signal by a digital to analog converter which is then displayed on a video screen. In order to achieve an adequate number of color intensity levels, typically 8 bits of data are associated with each pixel on the screen which allows for up to 256 different colors. Eight bits of data originating from either bit plane registers or directly from RAM contained within the system are transmitted to a color look-up table. The color look-up table recognized the 8 bits of data as an 8-bit address which is used to select 1 of 256 24-bit color values. Each 24-bit color value comprises three 8-bit binary values which are converted to red, green and blue analog signals respectively which are then output to video display devices.
Many prior art video digital-to-analog converter (DACs) use a binary weighted decode scheme. A plurality of analog current generators are implemented, the size of which are proportional to the significance of the bits of the color value the generator represents. Preferably, 8 analog generators are required for each DAC. However, there is a problem with the binary weighted decode schemes in that there is sometimes a time discrepancy between when a certain color bit turns off and the next color bit turns on. Overlaps of color bits can cause a glitch in the video display which is apparent to the human eye. For example, if the color bit scheme is 100 and then the next color bit scheme is 011, sometimes the decoder mistakenly identifies the signal as 111. If a number of glitches are apparent on the video display, it produces an unpleasant visual appearance.
These disadvantages can be overcome by first converting the 8-bit binary color value to a unary value which is then converted to an analog signal. The analog signal is used to drive a plurality of analog generators which are each equal in size, thereby, eliminating the need for weighted generators. A binary to unary decoder receives a binary input value which represents a particular color value and which is converted into a unary output value which is then transmitted to the video DAC for conversion to an analog signal. In general, in an n-bit binary to unary decoder, there are 2.sup.n-1 unary outputs. The number of active unary outputs is equal to the binary input value. In the preferred embodiment, each color binary input value comprises 8 bits. Therefore in an 8-bit binary to unary decoder, there are 2.sup.8-1 or 256 unary outputs. If the binary input value equals 00000011, then there are 3 active unary outputs. The number of bits which are enabled by the unary decoder determines the number of active analog current generators and therefore the intensity of each color produced on the video display.

Binary to unary decoder for a video digital to analog converter


Methods for updating presence information between a first user equipment (UE) and a second UE over a communications network are presented including: on an INVITE message delivery failure to the second UE from the first UE, sending a first PUBLISH message on behalf of the second UE to a presence server by a communications server; sending a NOTIFY message to the first UE by the presence server; and setting a current presence status of the second UE to UNAVAILABLE. In some embodiments, methods further include: if an immediately previous presence status of the second UE is set to AVAILABLE, sending a NOTIFY message to all watchers of the second UE to indicate the current presence status of the second UE. In some embodiments, the first PUBLISH message utilizes a user-agent header to indicate that the communications server originated the first PUBLISH message.

Presence is a service that allows communicating devices to publish their current presence information and fetch the presence information of other users connected with a communication network. Presence information is exchanged using IETF simple based PUBLISH, SUBSCRIBE, and NOTIFY messages in a communication network. These messages are periodically sent between subscribed user equipment (UE) and a server to keep presence information up-to-date. The frequency of these messages is an engineering compromise (typically 1 hour) between network traffic and the validity of presence information.
In conventional examples, users may travel into and out of a network coverage area and may become temporarily or permanently inaccessible. When a user becomes inaccessible, presence information about that user may remain incorrectly published due to delays in updating presence information on a communication network. Thus, a user may appear "available," but a call cannot be established because the user is, in fact, "unavailable." This disparity may contribute to a perception that all presence information is unreliable. One way to address this problem is to increase the frequency of presence updates. However, this is an obvious but expensive solution to the problem.
At least two message delivery failure situations are possible candidates for a proactive presence update from the server itself. These situations and some corresponding strategies for achieving more accurate presence information are presented herein. Utilizing embodiments describe herein may not only improve user confidence in presence information but also optimize message traffic in a communication network. In addition, changes proposed in embodiments herein, are within the existing OMA-based presence framework. As such, methods for managing presence information in a real-time communications network are presented herein.
Presence specifications, standards and requirements are discussed in greater detail in the following technical specifications from Open Mobile Alliance (OMA), which are hereby incorporated by reference in their entirety:
OMA Presence SIMPLE specification, Candidate Version 1.0-10 Jan. 2006; and
OMA PoC Control Plane, Candidate Version 1.0-27 Jan. 2006.
Other references pertinent to this patent application are also the following specifications from the Internet Engineering Task Force (IETF), which are hereby incorporated by reference in their entirety:
IETF RFC 3863 PIDF—Presence Information Data Format; and
IETF RFC 3903 Session Initiation Protocol (SIP) Extension for Event State Publication.
PTT System Overview
FIG. 1 is an illustrative prior art representation of a PoC System Architecture in accordance with OMA PoC/PAG version 1 specifications. An OMA PoC system architecture 100 includes User Equipment (UE) 102 and a set of network components. As illustrated, UE 102 contains the necessary pieces to interface the user acting as participant in a PoC session under the OMA version 1 specifications. UE 102 can either be a mobile terminal, a PC or any other device connected to the access network. Device Management (DM) client 104 inside UE 102 is used to bootstrap UE 102 with necessary configuration data from a DM server 116. An XML Document Management Client (XDMC) 110 is used to download and update by request any relevant contact lists stored in Shared XML Document Management Server (XDMS) 122. An Aggregation Proxy 124 may be configured to perform the authentication of any such requests. Similarly, the XDMC 110 is also configured to communicate via Aggregation Proxy 124 with PoC-specific XDMS (PoC XDMS) 126 for the purpose of managing group policies and authorization lists. UE 102 further includes Presence Source 106 and Presence Watcher 108. Presence Source 106 may be configured to publish a UE's availability status to other users. Presence Watcher 108 may be configured to retrieve availability status of others (e.g. other UEs and contacts). Both UE presence entities communicate with Presence Server 120 via a SIP/IP Core 118. In an OMA PoC system built on top of a GPRS radio network, a SIP/IP Core is often a IP Multimedia Subsystem (IMS) as standardized by the 3rd Generation Partnership Project (3GPP).
A PoC client's main responsibilities are: session management, SIP registration, TBCP request-response management, media transmission, and media reception. Under existing standards, session management, SIP registration may be accomplished over POC-1 and POC-2 interfaces 132 and 136 respectively. Furthermore, TBCP request-response management, media transmission, and media may be accomplished over POC-3 interface 134. PoC server 128 is responsible for application level network functionality including PoC session establishment, termination, handling of TBCP messages and media switching between the participating clients.

Methods for managing presence information in a real-time communications network


An LED light engine includes a flexible electrical cable and a plurality of LEDs. The flexible electrical cable includes first, second and third electrical conductors and an electrically insulating covering for the electrical conductors. The conductors are arranged substantially parallel with one another having an insulating material therebetween. A first LED including a first lead electrically connects to the first electrical conductor and a second lead of the first LED electrically connects to the second conductor. A second LED includes a first lead electrically connected to the second electrical conductor and a second lead electrically connected to the third electrical conductor. A third LED includes first and second leads electrically connected to the second conductor. The third LED is interposed between the first LED and the second LED.

Light emitting diodes ("LEDs") are employed as a basic lighting structure in a variety of forms, such as outdoor signage and decorative lighting. LED-based light strings have been used in channel lettering systems, architectural border tube applications, under cabinet lighting applications and for general illumination. A known spoolable LED light string arranges the LEDs in parallel circuitry. This parallel arrangement requires a very low voltage output power supply (Vout approximately 2.0 to 4.5 VDC) and a large amount of drive current capability. The large currents that must be delivered severely limits the distance that the power supply can be spaced from the LED strip as well as the length of the LED strip that can be driven by the power supply.
Known LED string lights also use parallel/series combinations of LEDs. These known systems require that the LEDs mount to a printed circuit board as well as some sort of current limiting device. These known systems require the printed circuit board to be environmentally isolated, which is expensive. Furthermore, the printed circuit board based systems are also difficult to spool, to mount and to cut to length in addition to requiring the expense of the printed circuit board itself.
Other known LED light strings employ a plurality of LEDs wired in a series/parallel block that are run directly off AC power. These known systems require complicated designs to account for the alternating current.
The present LED light engine contemplates an improved apparatus and method that overcomes the above-mentioned limitations and others.


A multi-dimensional blockchain protocol designed to self-fork into multiple chains, scale infinitely, achieve zero cost transactions, sub-second finality and open new markets for sharders, blobbers, developers, and content publishers, while managing a low inflation rate.

Internet is a global computer network providing a variety of information and communication facilities, consisting of interconnected networks using standardized communication protocols. Internet is not owned by a single entity and it operates without a central governing body. The same principles of distributed governance were applied to digital currencies by providing ability to perform digital transactions that existed without support from any underlying institution. The digital ledger that records the transactions in a chain using a mathematical hierarchy is called a blockchain.
Conventional blockchain technology do not scale and have a high cost of consensus which makes it difficult to use with IoT devices and for micro-transactions. IoT devices typically send a lot of data and so, cumulative costs for such transactions would be too high for a business to be able to use such data. Additionally, daily high-frequency micro-transactions accumulate high fees over time relative to the total amount transacted.
Conventional blockchain technology such as Bitcoin and its derivatives are heavily oriented toward miner incentives to build consensus. These older technologies use work oriented schemes (Proof-of-work) which waste energy resources, and are becoming more centralized mining pools, because of expensive specialized computing power required to achieve consensus, which defeats the original purpose of decentralization. Bitcoin's altcoins are cheaper and more decentralized in comparison, but as they grow, they will suffer the same consequences.
A rather recent blockchain technology, Ethereum, have incorporated scripts or coded transactions which use computing, memory, storage, and bandwidth resources. While the flexibility of a code enables new applications, it complicates the mining process and puts a strain on the resources. This led to charging of fees to properly incentivize contract writers and miners to include a transaction in a mined block. Thus, during high demand events, such as an ICO (initial coin offering), where there is a strong demand to get in the first block mined, a lot of transactions do not go through because the network is overwhelmed and only those that pay a high fee gets their transactions recorded in a block.
Several prominent blockchains (Bitcoin, Ethereum) have gone through the forking process and this period is destabilizing because of uncertainties over the integrity of the forked chain, miner incentives, and user demand. Forks happen because of the need to change the code that cannot be done with a minor upgrade, and is necessary to meet certain application requirements that were not thought of in the initial design. An additional reason for a fork is to reverse a large malicious transaction that has taken place because of an implementation flaw (Ethereum).
Both Bitcoin and Ethereum have a very high inflation rate of mining which reduces over time. Bitcoin started out with 100% before it reduced to its current 4% rate. Ethereum's current inflation rate is 14% but is expected to change after a hard fork in future.

Systems and methods of self-forking blockchain protocol


A handheld apparatus for tracking, recording and retrieving time by account, task and date. The device permits entry of one or more account numbers and one or more tasks associated with each account number. When working on an activity for a selected account and task, a "timer" can be started for that account's activity and the device will keep track of total accumulated time. Recorded data can be retrieved on the internal display or transferred to a computer for processing.

1. Field of the Invention
This invention pertains generally to time keeping devices, and more particularly to an apparatus for logging, tracking and processing the amount of time spent on projects.
2. Description of the Background Art
Clocks, watches and other timekeeping devices are well known and widely used. Further, many individuals and businesses determine how much to charge their clients or customers based on the amount of time spent on a particular project. This often requires the recording of start and stop times during periods of activity, computation of elapsed time during each period of activity or a total elapsed time for all periods of activity, and application of a billing rate or other billing factor to the total elapsed time. As an alternative to recording start and stop times and computing an elapsed time from that information, it is also known to use timers or other devices to record and display total elapsed time. Further, it is known to record, track and process the information either manually or by using electronic data processors.
Examples of devices which have been previously developed for timekeeping purposes include those found in U.S. Pat. No. 4,164,038, which discloses a hand held calculator with memory designed to store time to keep accounting of billable hours; U.S. Pat. Nos. 4,905,186; 4,115,870 and 5,007,015 which disclose portable data terminals that can store data for later downloading; U.S. Pat. No. 5,068,787 which discloses a portable device for tracking elapsed time by job, department or account number, and which provides for downloading the data; U.S. Pat. No. 4,195,220 which discloses a device which permits the recording of elapsed time associated with a number of tasks, and provides information for billing; and U.S. Pat. No. 4,164,038 which discloses a combination calculator/time recording device and teaches that elapsed time may be determined by using a counter or subtracting start and stop times to obtain a difference signal.
The foregoing patents reflect the state of the art of which the applicant is aware and are tendered with the view toward discharging applicant's acknowledged duty of candor in disclosing information which may be pertinent in the examination of this application. It is respectfully stipulated, however, that none of these patents teach or render obvious, singly or when considered in combination, applicant's claimed invention.


A layered flame retardant system and method is disclosed comprising a first flame retardant stable layer for covering a solid combustible material and a second moisture protecting polyolefin stretch film layer. The polyolefin stretch film layer further compactly affixes the first flame retardant stable layer to the solid combustible material. Some embodiments incorporate a five layer flame retardant polyolefin stretch film with flame retardant additives primarily in the inner layers. Another embodiment incorporates thermal insulating material.

A flame retardant wrap is used to protect flammable material. A flame retardant wrap may be used to cover a palate of flammable solid material, or just an individual item, for example a paper roll. A stretch film composite with a flame retardant component has been suggested for such use. The stretch film lends itself to easy coverage, the stretch film clings to the flammable material being covered and the stretch film provides a moisture barrier. However, it has been found that stretch films with flame retardant components fail to pass flame tests, for example large scale NFPA 701 testing (National Fire Protection Association).
When exposed to flame or heat, stretch film tends to melt and shrink away from the solid material intended to be protected. This causes the protected material to become uncovered by the shrink film and fully exposed to the flame. Once the flame retardant film loses its coverage dimension, the flame is no longer inhibited.
U.S. Pat. No. 6,264,031 to Pienta et. al. discloses a packaging method for combustible paper rolls comprising inner and outer stretch film layers with an intermediate Kraft paper layer. Although, mentioned as being fire resistant the Pienta invention does not pass NFPA 701 fire tests.
U.S. Pat. No. 6,265,082 to Dunham et. al. discloses a fire retardant composition that is a cured film that contains a curable resin and a fire retardant. The film is adhered to a flexible substrate in a manner to not substantially alter the hand of the flexible substrate. The fire retardant film is adhesively applied to some flexible substrate, typically a cloth fabric. Unless pre-applied at a processing site, adhesively attaching a fire retardant film requires manual intervention. A flame retardant material could be attached directly without the need of a surface film. Further the substrate is not flame retardant.
It is desirable to provide a method of completely covering a solid flammable material with a flame retardant and moisture resistant material that is snuggly attached to the flammable material without increasing the risk of spreading a fire and . It would be further desirable if the flame retardant system had a relatively low installation cost while passing large scale NFPA 701 flame test.


Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also includes selecting flip-flops for each port if the slack does not exceed a slack threshold. Further, the method includes integrating a wrapper cell to each port for which the slack exceeds the slack threshold. Moreover, the method includes coupling integrated wrapper cells and selected flip-flops corresponding to the input ports to form at least one input scan chain for the core, and corresponding to the output ports to form at least one output scan chain for the core. The method also includes testing the SoC using the at least one input scan chain and the at least one output scan chain of each core.

Various testing techniques are used to test multiple cores of a system-on-chip (SoC) and to test interfaces between the cores. It is desired to reduce test time of the SoC with minimal effect on functional timing of the SoC. Currently used test techniques make use of scan chains, for example a natural bounding chain and a wrapper scan chain, for isolating the cores of the SoC and enabling testing. However, the wrapper scan chain increases area of the integrated circuit by adding a flip-flop and a multiplexer along a functional path, and also impacts the functional timing. The natural bounding chain is formed by stitching core flip-flops that meet certain criteria. If the core is poorly registered, then the number of flip-flops forming the natural bounding chain is high and hence the test time is also high.
In light of the foregoing discussion there is a need for an efficient method and system for testing the SoC that overcomes one or more of the above-mentioned issues.