A vacuum capacitor including an insulating cylinder having first and second ends which are opposite to each other. A stationary-side flange is installed to the first end of the insulating cylinder. A stationary electrode supporting plate is installed to an inner surface side of the stationary-side flange. A movable-side flange is installed to the second end of the insulating cylinder. A movable electrode supporting plate is installed to an inner surface side of the movable-side flange through an electrostatic capacity adjusting screw and movable relative to the stationary electrode supporting plate by turning of the electrostatic capacity adjusting screw. Additionally, a diaphragm is sealingly connected between the movable-side flange and the movable electrode supporting plate, the diaphragm having corrugation and defining a vacuum side and an atmospheric side in the vacuum capacitor.

This invention relates to a vacuum capacitor to be used in an oscillator circuit of a supper power oscillator, a high frequency power circuit for a semiconductor producing apparatus, a tank circuit of an induction heating apparatus, or the like.
Vacuum capacitors are roughly structurally classified into a vacuum fixed capacitor whose electrostatic capacity value is fixed and a vacuum variable capacitor whose electrostatic capacity value is variable. An earlier technology vacuum variable capacitor is shown in FIG. 6 as a vertical sectional view. The vacuum variable capacitor includes an insulating cylinder 1 formed of ceramic or the like. The insulating cylinder 1 has one end to which a stationary-side flange 2 is installed, and the other end to which a movable-side flange 4 is installed through a sealing metal fitting 3, so that a vacuum container 5 is formed. The reference numerals 2a, 4a designate respectively female thread portions through which outside connection conductors are to be installed to the flanges 2, 4.
A plurality of cylindrical electrode plates which have respectively different diameters are coaxially disposed standing on the inner surface of the stationary electrode supporting plate 2 in such a manner as to be spaced a certain distance from each other, thereby forming a stationary electrode 6. Additionally, a center pin 8 formed of an insulating material is disposed standing at the central portion of the inner surface of the stationary-side flange 2 through a stationary guide 7. A cylindrical movable lead 9 is slidably fitted on the center pin 8. A movable electrode supporting plate 10 is installed to the movable lead 9. A plurality of cylindrical electrode plates having different diameters are coaxially disposed standing on the movable electrode supporting plates 10. Each cylindrical electrode plate is insertable into and withdrawable from a space between the adjacent cylindrical electrode plates of the stationary electrode 6 without contacting with the cylindrical electrodes of the stationary electrode, thereby forming a movable electrode 11. Additionally, a movable lead bolt section 9a is fixedly connected to the lower end of the movable lead 9 as a single member.
The movable-side flange 4 is formed at its central portion with a hole 4b defined by an inner peripheral portion of the flange 4. A cylindrical heat pipe 12 is disposed standing at the inner peripheral portion of the movable-side flange 4. A nut receiving section 13 is installed to the inner peripheral portion of the heat pipe 12. An adjusting nut 15 is rotatably installed through a bearing 14 to the nut receiving section 13. The adjusting nut 15 is formed at its inner peripheral portion with a female thread portion 15a which is engageable with the male thread portion 9b of the movable lead bolt 9a. The adjusting nut 15 is formed with a large-diameter hole section 15c which is contiguous with the female thread portion 15a through a step portion 15b. The movable lead bolt 9a is formed at its lower end portion with an axially extending female thread portion 9c with which an adjusting screw 16 is engaged, in which the a head portion 16a of the adjusting screw 16 is brought into engagement with the step portion 15b of the adjusting nut 15. The reference numeral 17 designates a bellows which is extensible conductor and define a vacuum side and an atmospheric side. The one end of the bellows 17 is attached to the movable electrode supporting plate 10 while the other end is attached to the movable-side flange 4.
With the above arrangement, in order to adjust the maximum electrostatic capacity value of the vacuum capacitor, first the adjusting nut 15 is slightly turned to the right to move the movable lead 9 downward from a position corresponding to the maximum electrostatic capacity value at which position the tip end of the movable lead bolt 9a is brought into contact with the tip end of the center pin 8, thereby adjusting the defined maximum electrostatic capacity value. Subsequently, the adjusting screw 16 is screwed into the female thread portion 9c until the head portion 16a of the adjusting screw 16 is brought into contact with the step portion 15b. Then, the adjusting screw 16 is fixed to the female thread portion 9c of the movable lead bolt 9a with an adhesive or the like. As a result, if the adjusting nut 15 is intended to be turned to the left from the position corresponding to the maximum electrostatic capacity value, it cannot be turned to the left since the head portion 16a of the adjusting screw is brought into contact with the step portion 15b.
Adjustment of the electrostatic capacity of the vacuum capacitor is carried out as follows: The movable lead bolt 9a moves downward when the adjusting nut 15 is turned to the right, and moves upward when the adjusting nut 15 is turned to the left. This moves the movable electrode 11 upward and downward to vary the total facing area between the movable electrode 11 and the stationary electrode 6, thereby adjusting the electrostatic capacity.
The movable lead 9 receives a force for pushing it up under the pressure differential between a vacuum on the vacuum side and an atmospheric pressure on the atmospheric side. The adjusting nut 15 also receives the same force so as to generate a surface pressure at the nut receiving section 13, so that a large rotational torque is required to turn the adjusting nut 15. However, since the bearing 14 is provided between the nut receiving section 13 and the adjusting nut 15, turning of the adjusting nut is easy. Additionally, since the heat pipe 12 is provided, heat generated in the bellows 17 upon current-flowing is absorbed and radiated through the heat pipe 12, the movable-side flange 4 and the outside connection conductor, thereby prolonging the life of the bellows 17 and other members.
An earlier technology vacuum fixed capacitor is shown in FIG. 7 in the form of a vertical sectional view. The vacuum fixed capacitor includes an insulating cylinder 18 formed of ceramic or the like. Flanges 19, 20 formed of cupper are respectively provided at the opposite end sides of the insulating cylinder 18. The flange 19 is provided at its outer peripheral part with cylindrical peripheral section 19a installed to one end of the insulating cylinder 18, while the flange 20 is provided at its outer peripheral part with a cylindrical peripheral section 20a installed to the other end of the insulating cylinder 18. Thus, a vacuum container 24 is constituted by the insulating cylinder 18 and the flanges 19, 20.
Each of the flanges 19, 20 is provided with a projection 19a, 20b located at the central portion of the inner surface side thereof. A positioning pin fitting hole 19c, 20c is formed at the tip face of the projection 19a, 20b. A female thread portion 19d, 20d for installation of an outside connection conductor is formed at the central portion of the outer surface side of the flange 19, 20. A locating pin 21 formed of ceramic is provided between the projections 19b, 20b in such a manner that the opposite end sections of the pin 21 are fitted respectively in the fitting holes 19c, 20c of the projections 19b, 20b.
A plurality of cylindrical electrode plates which have respectively different diameters are coaxially disposed standing on the inner surface of the flange 19 in such a manner as to be spaced a certain distance from each other, thereby forming a stationary electrode 22. Additionally, a plurality of cylindrical electrode plates having different diameters are coaxially disposed standing on the inner surface of the flange 20. Each cylindrical electrode plate is insertable into and withdrawable from a space between the adjacent cylindrical electrode plates of the stationary electrode 22 without contacting with the cylindrical electrode plates of the stationary electrode 22, thereby forming a stationary electrode 23. Thus, since the locating pin 21 is provided, the radial and axial distances between the stationary electrodes 22, 23 are made uniform.
In the vacuum capacitors shown in FIGS. 6 and 7, each of the stationary electrode 6, 22, 23 and the movable electrode 11 includes a plurality of thin and coaxial cylindrical electrode plates, in which the total of the electrostatic capacities each of which is produced by the facing cylindrical electrode plates corresponds to the electrostatic capacity of the whole vacuum capacitor. Here, the electrostatic capacity C per unit length L, of infinite coaxial cylindrical electrodes is represented by an equation (1) which can be applied to finite coaxial cylindrical electrodes.C=2πε0L/log (b/a)  (1)
where a is the radius of an inner cylindrical electrode plate, b is the radius of an outer cylindrical electrode plate, ε0 is the vacuum dielectric constant, and L is the length of the cylindrical electrode plates. In case that the electrode 6, 11, 22, 23 is constituted of a plurality of cylindrical electrode plates, the electrostatic capacity of the vacuum capacitor is calculated by totaling the values C each of which is obtained by the above equation (1), in which the voltage proof characteristics at this time is decided by the difference between the radius a of the inner cylindrical electrode plate and the radius b of the outer cylindrical electrode plate.
Prior art documents related to the invention of this application are Japanese Patent Provisional Publication Nos. 6-204082, 7-211588 and 8-97088.


An electrical outlet faceplate. The electrical outlet faceplate comprises a plate, an alternating current to direct current (AC/DC) converter mechanically coupled to the plate, and a wireless beacon mechanically coupled to the plate and electrically coupled to the AC/DC converter. The wireless beacon is a radio transmitter that transmits an identification in a radio frequency signal that has an effective range of less than 20 meters. The electrical outlet face plate further comprises a wire electrically connected to the AC/DC converter at a first end of the wire, whereby, when a second end of the wire is electrically connected to a powered electrical outlet, the wire provides alternating current power to the AC/DC converter.

Mobile communication devices are providing more and more advanced functionality as the processing power of the devices increases. Applications or computer programs may be loaded onto the devices and executed to provide specialized functionality to the users of the devices. Some of the applications rely upon wireless communication to server computers that provide some of the information processing. The server computer may then transmit results or intermediate results to the device via a wireless communication link. The application on the device may then provide the results to the user or may complete the processing of the intermediate results received from the server computer. Wireless beacons can transmit an identity that may be used by a mobile communication device, in combination with a registry service, to discover and access services provided by server computers via wireless communication links.

Wireless beacon for embedding in building infrastructure


Strobe stand on which strobe device is mounted is provided. Strobe device includes strobe body and light-emitting housing coupled to strobe body. The strobe stand includes the following elements: base plate having leg; attachment section provided on one surface of base plate for receiving strobe device; and suction pad provided on leg on the other surface of base plate. With this configuration, the bounce angle of light-emitting housing of strobe device can be positioned accurately.

In order to expand photographic uses, a conventional, simple strobe stand for wireless use is disclosed (see Patent Literature 1, for example).
The strobe stand disclosed in Patent Literature 1 is formed of one planar plate member that has three support-leg parts. The top surface of the plate member is provided with a strobe device attachment section. Three support legs are disposed in the positions of the vertexes (tips) of the three support-leg parts that form an equilateral triangle on the bottom surface of the plate member. Rubber non-slip members are fixed to the bottom surfaces of the support legs, allowing the strobe stand to be installed on a supporting surface.
However, the strobe stand disclosed in Patent Literature 1 cannot adhere closely to the supporting surface for fixation thereto. Thus, when the light-emitting part of the strobe device is rotated for bounce illumination, the strobe stand can be displaced from the intended installation position.
Generally, in the strobe device mounted on the strobe stand, the illumination angle can be changed to a desired angle for bounce illumination, according to the intension of a photographer. However, the bounce position is manually set, and thus when the photographing timing is bad, the photographer can miss a photo opportunity. The effect of vibrations and swings may cause the strobe device mounted on the strobe stand to move from the installation position. Thus, stable light distribution characteristics of the strobe device cannot be obtained.

Stand for strobe and illumination device equipped with same

Panasonic Intellectual Property Management Co., Ltd.


A semiconductor device includes a first power supply terminal, a second power supply terminal, a comparison circuit coupled to the first power supply terminal and the second power supply terminal to produce at an output node thereof a signal responsive to a difference between a potential of the first power supply terminal and a potential of the second power supply terminal, and a core circuit coupled to the output node of the comparison circuit to perform a test operation in response to the signal.

1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device equipped with a test function and a method of setting a test mode in a semiconductor device.
2. Description of the Related Art
Semiconductor device manufacturers need to test the manufactured semiconductor devices prior to shipment from the factory in order to check whether they operate properly. Semiconductor devices are provided not only with a normal operation mode for exerting the functions that are originally intended for these semiconductor devices, but also with a test mode for performing special functions for test purposes. At the test prior to shipment from the factory, semiconductor devices are controlled to enter such a test mode so as to perform test operations that are different from the normal operations. This serves to check the semiconductor devices.
In the case of a microcontroller implemented as a single chip including a CPU, ROM, RAM, and so on, there is a need to lead some signals to an exterior of the chip for inspection in the test mode while these signals are only transmitted between internal modules such as the CPU, ROM, RAM, and so on during the normal operation mode. In such a microcontroller, an entry into a test mode allows the circuit inside the chip for controlling test operations to operate, and allows the signals transmitted between the internal modules to be transmitted to the exterior from the external terminals of the chip.
FIG. 1 is a drawing showing a mechanism for indicating an entry into a test mode in a semiconductor device having a related-art test mode. A semiconductor device 10 shown in FIG. 1 includes a power supply terminal 11, a power supply terminal 12, a test-purpose signal terminal 13, user terminals 14 through 17, and a power supply terminal 18. The power supply terminals 11 and 12 serve to supply power supply voltages VDD and AVDD, respectively, to the core circuit of the semiconductor device 10. The ground terminal 18 serve to set a ground voltage VSS of the core circuit of the semiconductor device 10 to the same potential as the ground voltage of the external circuit. The user terminals 14 through 17 serve to input/output control signals, data signals, etc., with respect to the core circuit of the semiconductor device 10.
The test-purpose signal terminal 13 is configured to receive a test signal indicative of an entry into a test mode. When the test signal applied from the exterior to the test-purpose signal terminal 13 is set to HIGH, for example, the semiconductor device 10 enters the test mode, thereby performing test operations.
Such a test-purpose signal terminal is only used during the test performed prior to the shipment from the factory by the manufacture of the semiconductor device. After the shipment of the semiconductor device, no user uses this terminal. Namely, the test-purpose signal terminal is a terminal of no use for users.
In respect of a semiconductor device chip, generally, as an attempt is made to increase the number of functions incorporated in the chip, the number of necessary input/output signals increases, resulting in an increase in the number of terminals. Further, as the chip size decreases in response to an increase in the circuit density of a semiconductor device, the size and pitches of the terminals need to be reduced in proportion to the reduction of the chip size. Accordingly, as the function of the semiconductor device becomes sophisticated, and as the circuit density increases, space for arranging the terminals decreases. This results in an increase in the demand that unnecessary terminals should be removed as many as possible.
Moreover, it is desirable to hide the method of entering a test mode from general users, thereby preventing the users having purchased the semiconductor device from using the test mode unpurposely. Further, it is preferable that there is some devised mechanism that avoids an inadvertent entry into a test mode so as to prevent the semiconductor device from entering the test mode by accident.
Patent Document 1 discloses a semiconductor integrated circuit having two power supply systems, which includes a first power supply for use in the core circuit and input buffers and a second power supply for use in the output buffers. After the power-on of the first power supply, a predetermined sequence is given to the second power supply, thereby entering a test mode. Patent Document 2 discloses a semiconductor integrated circuit which enters a test mode based on the result of comparison, which is made between the voltage applied from the exterior to an output terminal electrically coupled to an output of the output driver circuit and either one of the higher power supply voltage or the lower power supply voltage. Patent Document 3 discloses a configuration that generates a test signal for setting the test mode in response to the detection of a specific waveform inside the integrated circuit where a power supply voltage waveform applied in the test mode is controlled.
[Patent Document 1] Japanese Patent Application Publication No. 9-105771
[Patent Document 2] Japanese Patent Application Publication No. 2001-53232
[Patent Document 3] Japanese Patent Application Publication No. 6-309475
Accordingly, there is a need for a semiconductor device that can enter a test mode without requiring the use of an unnecessary terminal.

Semiconductor device and entry into test mode without use of unnecessary terminal


A system and method for controlling an interactive playground in which aspects of the playground are dynamically varied based on input signals from sensors in the playground. The system includes a system supervisor unit that utilizes a rule file, a scene file and a MIDI file in conjunction with a variety of sensor input to create an appropriate system response. Output control signals generated by the system supervisor unit are transmitted to other coupled computers to effectuate audio, visual and other effects in an interactive playground environment. The system supervisor has the desirable ability to load different scene, rule and MIDI files to create different system behavior in response to sensor stimuli, thereby creating a more adaptive behavioral based environment.

Environments whose purpose is to entertain, educate or otherwise hold the attention of its participants risk becoming boring when each response is tied to a single input stimulus and the result is invariably the same. In such a system the amount of interaction is low and the result highly predictable. Presently, this is the condition of so-called interactive playgrounds. Present interactive playgrounds respond in the same way to a stimulus without significant variation over time. As these environments become predictable to the participants they correspondingly run the risk of becoming boring to those participants. Eventually, bored participants will choose to avoid such an environment. Thus, whether or not a particular environment becomes boring will often have economic and other consequences for the owners of such an environment. The degree of interaction and the predictability of the environment's response are two important factors in determining whether an environment becomes boring or not.
Presently, interactive playground environments utilize strict rule based systems to control their response. A strict rule based system always responds to stimuli according to one rule. The control is of a top-down type variety in the sense that there is a static set of rules that mediates the output response in a deterministic way.
FIG. 1 illustrates such a rule based system. In FIG. 1, outputs from sensors 10 are transmitted to a computer executing a set of rules 12. The set of rules 12 determine what response 14 is appropriate based on the sensor output 10. The set of rules 12 does not change.
In FIG. 2 the set of rules block 12 in FIG. 1 is expanded to show typical functional sub-systems within the rules block 12 to better illustrate the strict rule based system. The sequential nature of a strictly rule based system requires a perception unit 16 to process information from the sensors 10. The system 12 then updates its current information from the environment in the mapping unit 18. A planning unit 20 and an execution unit 22 then derive and transmit the response 14. These units individually do not have the ability to respond as a system, nor is every unit capable of creating any type of observable behavior in the output. Thus, the strictly rule based system takes an input and operates on that input to produce a result. For the same input, the same result is produced every time. This is often referred to in the art as "hit and run" animation. The designer of this type of system assumes a static problem domain, i.e. the response is static. Ultimately, participants in the strict rule based interactive playground discover the playground is too predictable, then those participants lose interest and avoid it.
In order to keep the participants' attention and reduce the risk of boredom, it would be desirable to have an interactive playground that is less predictable. Furthermore, it would be desirable for an interactive playground to promote higher levels of interaction with its participants.

Behaviorally based environmental system and method for an interactive playground


A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k-1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1, . . . , Ok-2, and Ok-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok-1=I2k-1 if Ok-2=I2k-1, and Ok-1=I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.

Rapid development of electronic information leads to an increasingly higher usage rate of electronic chips. However, during use of an electronic chip, a soft error or a hard error may occur.
The soft error may be construed as a logic error of an electron tube. For example, 0 becomes 1, or 1 becomes 0.
The hard error may be construed as a permanent logic error of an electron tube.
However, some fields have a strict requirement on precision of the electronic chip, such as the aerospace and aviation field, the medical field, and the precision instrument field. No matter if it is the soft error or the hard error that occurs in the electronic chip, a serious result may always be caused.
Currently, a fault-tolerant technique widely used in the prior art is triple modular redundancy (TMR).
Referring to FIG. 1, the figure is a schematic diagram of fault-tolerance of triple modular redundancy in the prior art.
Three functions simultaneously execute a same operation. Output of the three functions serves as input of a voter; and the voter takes the same output that is in the majority as correct output of a voting system, which is usually called two out of three.
As long as two same errors do not occur in the three functions simultaneously, an error of a faulty function may be concealed, so that correct system output is ensured. Because the three functions are independent of each other, a case where two functions have errors simultaneously is of an extremely small probability, so that system reliability may be greatly increased.
However, hardware complexity caused by the triple modular redundancy is at least greater than more than twice the complexity of an original function. Further, when there is an error in a triple modular redundancy module itself, an output frame error rate may rise significantly, and a strong error-correction capability is not provided.
Therefore, a person skilled in the art needs to provide a universal error-correction circuit with fault-tolerant nature and a decoder that applies it, which are provided with general commonality and are provided with an extremely strong fault-tolerance and error-correction capability.

Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it


A secure system for authenticating the identity of ADS-B systems, including: an authenticator, including a unique id generator and a transmitter transmitting the unique id to one or more ADS-B transmitters; one or more ADS-B transmitters, including a receiver receiving the unique id, one or more secure processing stages merging the unique id with the ADS-B transmitter's identification, data and secret key and generating a secure code identification and a transmitter transmitting a response containing the secure code and ADSB transmitter's data to the authenticator; the authenticator including means for independently determining each ADS-B transmitter's secret key, a receiver receiving each ADS-B transmitter's response, one or more secure processing stages merging the unique id, ADS-B transmitter's identification and data and generating a secure code, and comparison processing comparing the authenticator-generated secure code and the ADS-B transmitter-generated secure code and providing an authentication signal based on the comparison result.

ADS-B is a technology that is being developed and deployed around the world to enhance aviation safety by allowing aircraft to make accurate and timely reports of their position, velocity, identification, capability, and intentions. The current ADS-B message protocol lacks any identity authentication scheme and ADS-B data is currently broadcast without encryption or other security measures. In addition, the current direction in air traffic control is to rely on the ADS-B message data for the control and management of air traffic. This leaves the current ATC system vulnerable to broadcast of false identification data.
What is needed is a method of authenticating an aircraft's identity, thereby making it more difficult for unauthorized third parties to enter a given air traffic control region by broadcasting false identification data for an aircraft, without adversely affecting the data throughput of the air traffic control system.
This invention addresses these problems by employing cryptographic techniques as part of an authentication scheme to enhance the security of the ADS-B system.

Secure ADS-B authentication system and method


A character recognition system wherein the flexibility of the recognition task is expanded for orientation independence, position independence, and orientation and position independence. The system also provides a technique for implementing concurrency in the processing to achieve high speed without sacrificing performance. The system is readily implemented on conventional machine vision computing systems.

1. Technical Field
This invention relates to image analysis systems, and more particularly to automated optical character recognition systems.
2. Discussion
Over the last few years, applications of machine vision to the areas of automated inspection and manufacturing have been increasing considerably. Among the areas of machine vision most pursued by various industries are: optical character recognition, defect inspection, gauging and, product counting. Of all these applications, optical character recognition ("OCR") has been of great importance to many industries, such as, pharmaceutical and packaging industries for a variety of reasons. Some of these reasons are:
(1) better quality of products, PA1 (2) cost effectiveness of products, PA1 (3) consistency of product quality, PA1 (4) proper documentation of errors and PA1 (5) better productivity. PA1 (1) recognition irrespective of orientation of characters, PA1 (2) recognition irrespective of position of characters, PA1 (3) very high speed recognition of characters, PA1 (4) recognition irrespective of position and orientation of characters, PA1 (5) recognition of degraded or poor quality characters, PA1 (6) accurate recognition, and PA1 (7) recognition of symbols, as well as, characters. PA1 (1) image acquisition with a TV camera, PA1 (2) segmentation of the acquired image to extract the character image, PA1 (3) processing of the character image by vector correlation technique to extract data pertaining to individual characters, PA1 (4) analysis of the vector correlation data to recognize the characters and, PA1 (5) display the recognized character data. PA1 (1) perform image processing pertaining to orientation independence to extract a blob image, PA1 (2) compute the orientation of the character string by computing the orientation of the principal axis of the blob and, PA1 (3) rotate the characters about an axis to orient it horizontally across the image for recognition. PA1 (1) locate a mark or "fiducial" in the entire image, PA1 (2) compute the displacement of this mark from its "nominal" position and, PA1 (3) move the character image by this displacement to place it at its "nominal" position. PA1 (1) perform image processing pertaining to orientation independence to extract a blob image, PA1 (2) compute the orientation of the principal axis of the blob from horizontal. PA1 (3) rotate the character image about an axis to orient it horizontally across the image, PA1 (4) locate a mark or "fiducial" in the entire image, PA1 (5) compute the displacement of the "fiducial" from its "nominal" position, PA1 (6) move the character image by this displacement to place it at its "nominal" position.
In today's high speed manufacturing processes, it is important to maintain the quality of products without affecting the rate of productivity. Everyday stricter conditions are laid down for better product quality, particularly for the pharmaceutical industry. In this manufacturing environment, it is important to have correct labels and numbering on parts manufactured by an industry. Also, it is increasingly difficult for human inspectors to keep up with the speed of the manufacturing processes. With machine vision application of OCR technology, the speed of a manufacturing process can be maintained without relying on human inspectors. This requires less inspectors and a more cost effective manufacturing. Further, a machine vision system generates results in a consistent way and all errors are automatically documented for future processing.
Many different types of OCR equipment have been installed in different types of industrial environments over the past several years. This equipment includes optical sensing devices, such as television (TV) cameras, image processing units, display monitors for training and viewing and, other peripheral devices. The cameras are mounted in a given orientation to view the manufactured parts and then read characters from these parts in a fixed orientation. Also, character recognition on these parts is performed at a fixed location in the manufacturing line. This constrains the manufacturers to place the characters in a given orientation and at a very precise location on the parts.
These two constraints may not be achievable in many manufacturing scenarios. One example of such a scenario is the task of reading characters from bottle caps as these bottles come down a manufacturing line. The bottles rotate continuously as they move down this line. Thus the character set printed on the caps, which is to be recognized by the machine vision unit, also rotates continuously down the line. There is no guarantee that the character set will be presented at a fixed orientation in front of the camera. We can also have many situations where a character set is not printed at the same precise location on a part. An example of this would be characters stamped on a part by a stamping machine. Errors in the motion of the stamping machine or non-uniform movement of the part along the line, may cause the characters to be printed at different positions of the part at different times. Thus if the TV camera points to a fixed position on the part, it may not find the entire set of characters on the part even though all the characters are present on the part.
In order to overcome most (if not all) of the drawbacks of present OCR technology, it would be desirable to have an image analysis system which is capable of orientation and/or position independent character recognition.

Rotation and position invariant optical character recognition


Pallet stops are provided for blades of a forklift truck. The pallet stops have elongated bodies of a predetermined length, and are easily placed on or removed from forklift blades in predetermined locations. For retrofitting existing forklift blades, the elongated bodies include magnets for removably securing the pallet stops to the blades, while for new forklift blades, the blades may have threaded openings formed in predetermined locations, and elongated pins may be selectively inserted into one of the threaded openings on each blade.

1. Field of the Invention
This invention relates generally to forklift trucks, and more particularly, to a forklift pallet stop for use on a forklift blade to aid in accurately aligning a load, and to prevent damage to adjacent pallets and materials by forklift blades.
2. Description of Related Art
Forklift trucks for moving pallets and goods thereon are widely used. Because of the different materials and pallets which may be moved by known forklifts, adapters, alignment devices, covers, protectors, and other means have been developed therefor. Examples of such known means for forklifts are shown by U.S. Pat. Nos. 4,102,464, 4,239,446, 4,395,190, 4,669,949, 4,747,610, 4,802,813 4,919,465, 5,174,710, 5,208,753 and 5,221,176. However, these known devices and means do not provide for the exact positioning of the blades of a forklift, under a pallet, to prevent damage to adjacent pallets when a series of pallets is to be moved from or lowered into position.
Furthermore, it is known to provide elements or plates for posts and/or pallets to protect such pallets when used with forklifts. Examples of pallet protectors are shown in U.S. Pat. Nos. 4,113,110, 4,292,899 and 5,076,175.
After numerous attempts to solve the problems which occur because of the length of forklift blades extending from under a pallet, and the damage caused thereby, the need for a simple, low-cost, easy-to-manufacture pallet stop which may be mounted on either or both of the blades of a forklift vehicle, to aid in accurately aligning a load, and to prevent damage by the blades, and which pallet stop has a long life, is simple and comparatively low in cost to manufacture, and is not easily lost or detached from the forklift or blade on which it is used, still exists.


An n-type drain diffusion layer, an n-type source diffusion layer and an n-type control gate diffusion layer are formed on the surface of a p-type semiconductor substrate. Furthermore, an n-type well is connected to the control gate diffusion layer. A control gate electrode of aluminum is connected to the well. An isolation oxide layer is formed between the control gate electrode and the control gate diffusion layer. A first insulation layer is formed on the drain diffusion layer, the source diffusion layer and the control gate diffusion layer. A floating gate is formed on the first insulation layer. The upper portion and the side portion of the floating gate are covered with a second insulation layer. The floating gate is completely covered with a protective gate through the second insulation layer. The end edge of the protective gate opposes the well through the isolation oxide layer. The drain diffusion layer and the protective gate are connected to each other to have the same potential.

1. Field of the Invention
The present invention relates to a read-only semiconductor memory device to be used as a memory device of a computer or the like. More specifically, the invention relates to a nonvolatile read-only semiconductor memory device having a floating gate, whose surface is not covered with a control gate.
2. Description of the Prior Art
Conventionally, there is a structure for a nonvolatile semiconductor device, in which two layers of gates, i.e. a floating gate and a control gate, are provided. However, such semiconductor device requires large number of fabrication process for formation of two layers of gates. Therefore, there has been proposed a nonvolatile semiconductor memory device which has a structure with only one layer of gate (Japanese Unexamined Patent Publication No. Hei 7-288291). FIG. 1A is a diagrammatic plan view of a conventional semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. Hei 7-288291, and FIG. 1B is a section taken along line A--A in FIG. 1A. It should be noted that an interlayer insulation layer and an isolation oxide layer are neglected from illustration in FIG. 1A. In the shown semiconductor memory device, an n-type drain diffusion layer 111, an n-type source diffusion layer 112 and an n-type control gate diffusion layer are stacked on the surface of a p-type semiconductor substrate 110 of single crystalline silicon. Also, a p-type channel region 125 is formed between the drain diffusion layer 111 and source diffusion layer 112. An isolation oxide layer 117 is formed between the respective diffusion layers except for the channel region 125. A tunnel insulation layer 119a covering a part of the drain diffusion layer 111, a part of the source diffusion layer 112 and the channel region 125 and a tunnel insulation layer 119b covering a part of the control gate diffusion layer 114 are formed. The tunnel insulation layers 119a and 119b are integrated with each other. Also, a floating gate 113 of polycrystalline silicon is formed on the tunnel insulation layers 119a and 119b.
Also, a protective layer 118 of polycrystalline silicon is formed via an insulation layer 120 above a part of the floating gate 113. Then, the respective elements formed on or above the surface of the p-type semiconductor substrate 110 are covered with an interlayer insulation layer 126. Also, contact holes 121 to 124 are provided through the interlayer insulation later 126. Then, the drain diffusion layer 111 is connected to a drain electrode 211 of aluminum via the contact hole 121. The source diffusion layer 112 is connected to a source electrode 212 of aluminum via the contact hole 122. Also, the control gate diffusion layer 114 is connected to a control gate electrode 214 of aluminum via the contact hole 123. The protective layer 118 is connected to a protective gate electrode 218 of aluminum via the contact hole 124. The protective gate electrode 218 and the drain electrode 211 are connected to each other.
Next, operation of the foregoing semiconductor device will be discussed. FIG. 2 is a diagrammatic illustration showing an equivalent circuit of the memory cell. Some parasitic capacitance is present between the floating gate 113 and the drain diffusion layer 111, between the floating gate 113 and the source diffusion layer 112, between the floating gate 113 and the p-type semiconductor substrate 110 and between the floating gate 113 and the control gate diffusion layer 114, respectively. Each parasitic capacitance is respectively assumed as C.sub.FD, C.sub.FS, C.sub.FB and C.sub.CF in sequential order. Also, a large parasitic capacitance is present between the floating gate 113 and the protective gate 118. Since the protective gate 118 is connected to the drain electrode 211, this parasitic capacitance is included in C.sub.FD. At this time, an expression of C.sub.FD >>C.sub.FS, C.sub.FB and C.sub.CF exists.
The following table 1 shows potential to be applied to the memory cell upon writing or erasing.
TABLE 1 ______________________________________ DRAIN SOURCE CONTROL GATE ______________________________________ WRITING GROUND -- V.sub.PP ERASING V.sub.PP -- GROUND ______________________________________
Upon writing, as shown in the foregoing table 1, the drain electrode 211 is biased to the grounding potential, the control gate electrode 214 is biased to high potential V.sub.PP for programming, and no potential is applied to the source electrode 212. At this time, since the expression of C.sub.FD >>C.sub.FS, C.sub.FB and C.sub.CF exists, the potential of the floating gate 113 is biased substantially to the grounding potential as the same potential as the drain diffusion layer 111. Therefore, a potential difference between the floating gate 113 and the control gate diffusion layer 114 becomes substantially equal to V.sub.PP to cause movement of electron from the floating gate 113 to the control gate diffusion layer 114 by tunnel effect. Thus, the threshold voltage (hereinafter referred to as V.sub.tm) of the memory cell is shifted to low voltage to memorize "1", for example.
On the other hand, upon erasing, as shown in the table 1, the drain electrode 211 is biased to the high potential V.sub.PP, the control gate electrode 214 is biased to the grounding potential. Then, no potential is applied to the source electrode 212. At this time, since the expression of C.sub.FD >>C.sub.FS, C.sub.CB and C.sub.CF exists, the potential of the floating gate 113 is biased substantially to V.sub.PP. On the other hand, the control gate electrode 214 is biased to the grounding potential. Therefore, the potential difference between the floating gate 113 and the control gate diffusion layer 114 becomes substantially equal to V.sub.PP to cause movement of electron from the control gate diffusion layer 114 to the floating gate 113 conversely to the case of writing by the tunnel effect. Therefore, the threshold voltage V.sub.tm is shifted to high voltage to memorize "0", for example.
However, since the floating gate 113 is not completely covered with the protective gate 118 in such a semiconductor memory device, if a quite large amount of mobile ion, such as Na ion or the like, penetrates into the chip, some mobile ion may reach the floating gate 113. Therefore, electron stored up in the floating gate 113 is electrically neutralized to destroy the memorized data.
When a structure to completely cover the floating gate 113 with a protective layer is taken in order to prevent the mobile ion from penetrating, another problem should be encountered. For example, when the floating gate 113 is completely covered with the protective gate 118a and 118b as shown with chain lines in FIGS. 1A and 1B, if the insulation layer 120 is formed thinner, coupling capacitance between the protective gate 118, 118a and 180b and the floating gate 113 becomes larger. At this time, since the drain electrode 211 and the protective gate electrode 218 are connected to each other, the potential of the drain diffusion layer 111 and the potential of the floating gate 113 become substantially equal to each other. Thus, it appears that the potential difference between the control gate diffusion layer 114 and the floating gate 113 becomes closer to V.sub.PP upon writing and erasing to improve efficiency of writing and erasing. However, since the protective gate 118b and the control gate diffusion layer 114 are located adjacently, transfer of electron is caused even between the protective gate 118b and the control gate diffusion layer 114 by the tunnel effect. This transfer of electron does not contribute for writing and erasing, and the efficiency of writing and erasing is lowered practically.
On the other hand, when the insulation layer 120 is formed thicker, the coupling capacitance between the protective gates 118, 118a and 180b and the floating gate 113 becomes smaller. Therefore, the potential difference between the floating gate 113 and the control gate diffusion layer 114 becomes smaller than V.sub.PP to lower the efficiency of writing and erasing.
On the other hand, there has been proposed a nonvolatile semiconductor memory device, in which the tunnel effect between the protective gate and the control diffusion layer is prevented (Japanese Unexamined Patent Publication No. Hei 2-2684). FIG. 3A is a diagrammatic plan view of a conventional semiconductor memory device disclosed in the foregoing publication, and FIG. 3B is a section taken along line B--B in FIG. 3A. It should be noted that the interlayer insulation layer and the isolation oxide layer are ommitted from FIG. 3A. In the shown semiconductor memory device, an n-type drain diffusion layer 131, an n-type source diffusion layer 132 and an n-type control gate diffusion layer 134 are stacked on the surface of the p-type semiconductor substrate 130. Also, a p-type channel region 145 is formed between the drain diffusion layer 131 and the source diffusion layer 132. An isolation oxide layer 137 is formed between the respective diffusion layers except for the channel region 145. A tunnel insulation layer 139a covering a part of the drain diffusion layer 131, a part of the source diffusion layer 132 and the channel region 145 and a tunnel insulation layer 139b covering the control gate diffusion layer 134 and a part of the isolation layer 137 formed on both sides of the control gate diffusion layer 134 are formed. The tunnel insulation layers 139a and 139b are integrated with each other. Also, a floating gate 133 of polycrystalline silicon is formed on the tunnel insulation layers 139a and 139b. A distance between the floating gate 133 and a portion of the drain diffusion layer 131 is narrower than a distance between the floating gate 133 and the source diffusion layer 132.
Also, the floating gate 133 is completely covered with a protective gate 138 of polycrystalline silicon via an insulation layer 140. The respective elements formed on or above the surface of the p-type semiconductor substrate 130 are covered with the interlayer insulation layer 146. Contact holes 141, 142 and 144 are provided through the interlayer insulation layer 146. The drain diffusion layer 131 is connected to a drain electrode 231 of aluminum via the contact hole 141, and the source diffusion layer 132 is connected to a source electrode 232 of aluminum via the contact hole 142. Also, the protective gate 138 is connected to a protective gate electrode 238 of aluminum via the contact hole 144. Then, the control gate diffusion layer 134 per se serves as the electrode 234 for the control gate.
Next, operation of the foregoing semiconductor device will be discussed. FIG. 4 is a diagrammatic illustration of an equivalent circuit of the memory cell. Some parasitic capacitance is present between the floating gate 133 and the drain diffusion layer 131, between the floating gate and the source diffusion layer 132, between the floating gate 133 and the p-type semiconductor substrate 130, between the floating gate 133 and the control gate diffusion layer 134 and between the floating gate 133 and the protective gate 138, respectively. Each parasitic capacitance is respectively assumed as C.sub.FD, C.sub.FS, C.sub.FB, C.sub.CF and C.sub.FG in sequential order. At this time an expression of C.sub.CF >>C.sub.FD, C.sub.FS, C.sub.FB and C.sub.FG exists.
The following table 2 shows potential to be applied to the memory cell upon writing or erasing.
TABLE 2 ______________________________________ DRAIN SOURCE CONTROL GATE ______________________________________ WRITING V.sub.PP -- GROUND ERASING GROUND -- V.sub.PP ______________________________________
Upon writing, as shown in the foregoing table 2, the drain electrode 231 is biased to high potential V.sub.PP for programming, and the control gate 234 is biased to the grounding potential. Then, no potential is applied to the source electrode 232. At this time, the potential V.sub.FGw of the floating gate 133 upon writing is expressed as the following equation (1): EQU V.sub.FGw =(C.sub.FD /(C.sub.FD +C.sub.FS +C.sub.FB +C.sub.FG +C.sub.CF)).times.V.sub.PP ( 1)
Then, since the expression of C.sub.CF >>C.sub.FD, C.sub.FS, C.sub.FB and C.sub.FG exists, upon writing, V.sub.FGw becomes substantially equal to 0 V. Therefore, a potential difference between the floating gate 133 and the drain diffusion layer 131 becomes substantially equal to V.sub.PP to cause movement of electron from the floating gate 133 to the drain diffusion layer 131 by the tunnel effect. Thus, the threshold voltage V.sub.tm is shifted to low voltage to memorize "1", for example.
On the other hand, upon erasing, as shown in the foregoing table 2, the drain electrode 231 is biased to the grounding potential, and the control gate electrode 243 is biased to the high potential V.sub.PP for programming. Then, no potential is applied to the source electrode 232. At this time, the potential V.sub.FGe of floating gate 133 upon erasing is expressed as the following equation (2): EQU V.sub.FGe =(C.sub.CF /(C.sub.FD +C.sub.FS +C.sub.FB +C.sub.FG +C.sub.CF)).times.V.sub.PP ( 2)
Then, the expression of C.sub.CF >>C.sub.FD, C.sub.FS, C.sub.FB and C.sub.FG exists, upon erasing, V.sub.FGe becomes substantially equal to V.sub.PP. Therefore, a potential difference between the floating gate 133 and the drain diffusion layer 131 becomes close to V.sub.PP. Conversely to the case of writing, electron moves from the drain diffusion layer 131 to the floating gate 133. Thus, the threshold voltage V.sub.tm is shifted to high voltage to memorize "0", for example.
However, in the shown semiconductor device, the protective gate 138 is biased to the grounding potential and parasitic capacitance C.sub.FG is present. Therefore, upon erasing, the potential of the floating gate 133 becomes much lower than V.sub.PP to lower the efficiency of erasing.
On the other hand, there has also been proposed a nonvolatile semiconductor device having a non-transparent material, such as aluminum, in order to avoid influence of light to a charge stored up in a floating gate (Japanese Unexamined Patent Publication No. Sho 63-157480). FIG. 5A is a diagrammatic plan view of a conventional semiconductor memory device disclosed in the foregoing publication, and FIG. 5B is a section taken along line C--C in FIG. 5A. It should be noted that the interlayer insulation layer and the isolation oxide layer are neglected from illustration in FIG. 5A. In the shown semiconductor memory device, an n-type drain diffusion layer 151, an n-type source diffusion layer 152 and mutually adjacent an n-type control gate diffusion layer 154 and a p-type control gate diffusion layer 155 are stacked on the surface of the p-type semiconductor substrate 150. Also, a p-type channel region 165 is formed between the drain diffusion layer 151 and the source diffusion layer 152. Also, a p-type diffusion layer 158 surrounding the foregoing elements is formed. An n-type diffusion layer 157a is formed outside of the p-type diffusion layer 158 with respect to the drain diffusion layer 151. An n-type diffusion layer 157b is formed outside of the p-type diffusion layer 158 with respect to the source diffusion layer 152. An n-type diffusion layer 157c is formed outside of the p-type diffusion layer 158 with respect to the control gate diffusion layers 154 and 155. Also, an isolation oxide layer 159 is formed between the respective diffusion layers except for the channel region 165. Then, a tunnel insulation layer 160 covering a part of the drain diffusion layer 151, a part of the source diffusion layer 152 and a part of the control gate diffusion layers 154 and 155 is formed. Furthermore, a floating gate 153 formed of polycrystalline silicon is provided on the tunnel insulation layer 160.
Also, the respective elements formed on or above the surface of the p-type semiconductor substrate 150 are covered with an interlayer insulation layer 166. Contact holes 161 to 164 reaching the n-type diffusion layers 157a, 157b or 157c or the p-type diffusion layer 158 are provided through the interlayer insulation layer 166. Furthermore, an n-type well 156a extending from the n-type diffusion layer 157a to the drain diffusion layer 151 through a portion of the p-type semiconductor substrate 150 is formed. An n-type well 156b extending from the n-type diffusion layer 157b to the source diffusion layer 152 through a portion of the p-type semiconductor substrate 150 is formed. An n-type well 156c extending from the n-type diffusion layer 157c to the control gate diffusion layers 154 and 155 through a portion of the p-type semiconductor substrate 150 and completely surrounding the control gate diffusion layers 154 and 155 is formed. The drain diffusion layer 151 is connected to a drain electrode 251 via the n-type well 156a, the n-type diffusion layer 157a and the contact hole 161. The source diffusion layer 152 is connected to a source electrode 252 via the n-type well 156b, the n-type diffusion layer 157b and the contact hole 162. Also, the control gate diffusion layers 154 and 155 are connected to a control gate electrode 254 via the n-type well 156c, the n-type diffusion layer 157c and the contact hole 163.
Then, a non-transparent material 170, such as aluminum or the like, is buried in the contact hole 164 reaching the p-type diffusion layer 158. Also, the non-transparent material 170 is stacked on the upper surface of the interlayer insulation layer 166 surrounded by the contact hole 164 to be integrated with the non-transparent material 170 buried in the contact hole 164.
Next, operation of the foregoing semiconductor device will be discussed. The following table 3 shows potential to be applied to the memory cell upon writing.
TABLE 3 ______________________________________ DRAIN SOURCE CONTROL GATE ______________________________________ WRITING HV GROUND V.sub.PP ______________________________________
Upon writing, as shown in the foregoing table 3, the drain electrode 251 is biased to high potential HV for programming, the source electrode is biased to the grounding potential and the control gate electrode 254 is biased to V.sub.PP. For example, HV is equal to 6V and V.sub.PP is equal to 12.5V. At this time, a current flows from the drain electrode 251 to the source electrode 252 to induce hot electron in the vicinity of the drain diffusion layer 151. The hot electron is injected into the floating gate 153 to shift the threshold voltage V.sub.tm to high voltage to memorize "0", for example.
On the other hand, upon erasing, irradiating ultraviolet ray to the memory cell is performed, and whereby electron stored up in the floating gate 153 is eliminated. However, since the semiconductor device is covered with the non-transparent material 170, erasing cannot be performed in the shown structure.
In this semiconductor device, the non-transparent material 170 is connected to the semiconductor substrate 150 via the p-type diffusion layer 158 and the n-type diffusion layers 156a, 156b and 156c. Since the semiconductor substrate 150 is biased to the grounding potential, the non-transparent material 170 is also connected to the grounding potential. Thus, parasitic capacitance is present between the non-transparent material 170 and the floating gate 153 to lower the potential of the floating gate 153 upon writing. Therefore, writing efficiency may be lowered.


In one embodiment, a microprocessor, comprising: first logic configured to dynamically adjust a maximum prefetch count based on a total count of predicted taken branches over a predetermined quantity of cache lines; and second logic configured to prefetch instructions based on the adjusted maximum prefetch count.

When a microprocessor executes program instructions, the microprocessor fetches the instructions from memory into the microprocessor using a processor bus. The time required to fetch instructions from memory may consume many clock cycles (e.g., hundreds of clock cycles). To reduce this problem, microprocessors include cache memory. The cache memory—typically much smaller than the system memory—is a memory internal to the microprocessor (or processor core) that stores a subset of the instructions located in the system memory. Though prefetching is important for both instructions and data, emphasis herein is placed on the instruction cache. When the microprocessor fetches an instruction, the microprocessor checks to see if the instruction is present in the cache and is valid. If so, the instruction can be executed more quickly than if the instruction had to be retrieved from system memory. That is, the microprocessor does not have to wait while the instruction is fetched from the memory into the cache using the processor bus. The condition where the microprocessor detects that the instruction is present in the cache and valid is commonly referred to as a cache hit. The condition where the referenced instruction is not present in the cache is commonly referred to as a cache miss. When the referenced instruction is already in the cache memory, significant time savings are realized, by avoiding the extra clock cycles required to retrieve the instruction from external memory.
Cache prefetching is a technique used by microprocessors to further boost execution performance by fetching instructions from external memory into a cache memory, before the instructions are actually needed by the microprocessor. Instruction cache fetches typically look ahead sequentially a predefined number of cache lines (e.g., fetch ahead ten (10) cache lines, or four (4) cache lines, etc.). Successfully prefetching instructions avoids the latency that is encountered when having to retrieve instructions from external memory (avoid consuming bus bandwidth or the bandwidth to other caches, as explained below).
There is a basic tradeoff in prefetching. As noted above, prefetching can improve performance by reducing latency (by already fetching the instructions into the cache memory, before it is actually needed). On the other hand, if too much information (e.g., too many cache lines) is prefetched, then the efficiency of the prefetcher may be reduced, and other system resources and bandwidth may be overtaxed. Furthermore, if a cache is full, then prefetching a new cache line into that cache may result in eviction from the cache of another cache line. Thus, a line in the cache that was in the cache because it was previously needed might be evicted by a line that only might be needed in the future.
In some microprocessors, the cache is actually made up of multiple caches. The multiple caches are arranged in a hierarchy of multiple levels. For example, a microprocessor may have two caches, referred to as a lower, first-level (L1) cache and a higher, second-level (L2) cache. The L1 cache is closer to the computation elements of the microprocessor than the L2 cache. That is, the L1 cache is capable of providing instructions to the computation elements faster than the L2 cache. The L2 cache is commonly larger than the L1 cache, although not necessarily so. Some microprocessors may have a third cache (L3), which may be larger than the L2 cache. Fetch times increase as fetches go from L1, L2, L3 caches, and system memory based on a cache miss (e.g., 10-20 clock cycles from L2, 20-30 clock cycles from L3 for illustration), and so it is desirable from a latency standpoint to intelligently store instructions in the L1 cache.
A microprocessor uses a variety of instruction types, including branch instructions, or simply branches, which include unconditional branches (e.g., branches that are always taken) and conditional branches (e.g., taken or not taken depending on evaluation of a specified condition). A prefetching scheme should take into account these various types of instructions to ensure efficiency of pipeline operations and more particularly, reduction in wasted cycles consumed in fetching instructions.


A system and method are provided for automatically notifying a user of an awaiting message. A wireless communication system including an identification system is utilized. The identification means identifies a registered user of the wireless communication system. A mail notification system is used for notifying the registered user of an awaiting message. A communication system checks for awaiting messages for the identified registered user. If an awaiting message is present, the communication system triggers the mail notification system.

1. Field of the Invention
The invention relates to connecting a messaging system with a wireless communication system, and more particularly to a system and a method for automatically notifying a user of an awaiting message in a wireless communication environment.
2. Description of the Related Art
Messaging systems are common in both public and private areas. For example, voice mail messaging systems are located in almost every office environment and in many private homes. Public and private wireless systems which include cellular telephones are also common. When a cellular telephone user subscribes to a messaging system, such as voice mail, from their cellular carrier, the user must periodically check for messages in that user's message mailbox. This checking is done manually by placing telephone calls. Similarly, a user who is away from the office and/or home and awaiting some message(s) must periodically check for messages in the office and/or home message mailbox(es). This is usually done by calling the office voice mail system or the home voice mail system. An office voice mail system may be connected to a PBX (private branch exchange), and a home voice mail system may be connected to a central office. Thus, both of these systems can be accessed with a telephone call from a user. In these situations, the messaging systems rely on users to remember to check their message mailbox(es).
Outcalling is available in some voice mail systems. Systems with outcalling can be programmed to call a given number when a message is received, but this is not helpful in a wireless communication environment because the cellular telephone can be out of range or turned off.
Enhanced one-number services are available to allow a single cellular telephone to operate with multiple systems. In this arrangement, all telephone calls are transferred to (or follow) a single cellular telephone. While enhanced one-number services transfer calls to a single cellular telephone, they do not transfer awaiting messages.
In public wireless systems, it is desirable to reduce air time usage, and therefore reduce air time charges, and in private wireless systems, it is desirable to reduce congestion on an internal network and to improve usability. Finally, a system which provides simplified mobile message notification and reception is desirable.

System and method for providing automated message notification in a wireless communication system

Siemens Information and Communication Networks, Inc.


A modular propellant charge (10) composed of N propellant charge modules (1; 11-16) each having a length Lo. In order to obtain an economical, durable, easily released connection between the propellant charge modules (1; 11-16), a displaceable sleeve (6; 17-22) of a length L is axially slidably arranged on the exterior of each propellant charge module (1; 11-16) with the relationship ##EQU1## applying for the length L. The displaceable sleeves are utilized to interconnect adjacent modules.

The present invention relates to a modular propellant charge composed of a number of similar propellant charge modules.
Propellant charges composed of several identical modules are required primarily for larger caliber weapons systems (for example, for howitzers, etc.). The individual modules generally have the shape of a cylinder and frequently have a length to diameter ratio of about one. An axial opening is provided to enable the charge to fire through upon ignition.
Such a modular propellant charge is disclosed, for example, in German Utility Model Patent 70/00,615. Here the individual propellant charge modules have unilaterally arranged sleeve-like extensions into which the respective next module can be plugged to form the modular propellant charge. The drawback of such arrangements is primarily the large volume required due to the projecting sleeves and the necessarily directional loading of the propellant charge magazine.
German Patent 3,034,360.A1 discloses a modular propellant charge in which the individual modules are connected with one another via a bayonet closure. For this purpose, the modules are provided with two tubular extensions, with the one tubular extension being provided with bores and the second tubular extension with a corresponding number of outwardly projecting radial pins. This arrangement is also relatively voluminous and requires directional loading of the magazines.
Finally, German Patent 3,737,704.A1 discloses a modular propellant charge in which the individual propellant charge modules are of symmetrical construction. On its two sides facing the adjacent modules, each propellant charge module is provided with constrictions that are connected with one another by means of a separate plug-in ring. The drawback of this arrangement is the relatively complicated manipulation and the additional space required for the plug-in rings.


A fault protection device tests a distribution for persistence of a fault using a selectable first fault testing procedure and a second fault testing procedure.

Power distribution systems typically include distribution feeders (ranging from approximately 4 KV to 69 KV) originating in power distribution substations and leading to the source of supply for end customers of an electrical supply utility or agency. Regulatory service provision requirements, cost and competitive pressures create requirements for lower cost, modular, standardized equipment, which can be installed, operated and maintained with minimal labor and human supervision.
Failures of the distribution feeder (faults) occur due to downed power lines, excavation of underground cable or other causes and are typically detectable by sensing excess (short circuit/overcurrent) current, and occasionally by detecting loss of voltage. In distribution systems, it is sometimes the case that a loss of voltage complaint by the customer is the means by which the utility senses the outage in order to respond by dispatching a crew to isolate the fault and reconfigure the distribution system. The typical devices for isolating these faults are circuit breakers located primarily in distribution substations and fuses located on tap lines or at customer transformers. The substation breakers are generally provided with reclosing relays that cause the breaker to close several times after the breaker has detected an overcurrent condition and tripped open. If during any of these "reclosures", the fault becomes undetectable, service is restored and no extended outage occurs. Particularly on overhead distribution lines, temporary arcing due to wind, lightening, etc causes many faults. Thus, the majority of faults are cleared when the breaker opens and service is restored on the automatic reclose. Alternatively, after some number of reclosure attempts, if the overcurrent condition continues to be present, the recloser goes into a "lockout" state which prevents further attempts to restore service.
Although utility acceptance of more sophisticated automation solutions to fault isolation and reconfiguration has been limited but continues to increase, many methods have been developed and marketed. The most primitive methods have typically involved placing control equipment and switchgear at strategic points in the power distribution grid and coordinating their operation entirely with the use of circuit parameters sensed and operated on locally and independently at each point. More sophisticated methods have been developed for isolating/reconfiguring these circuits by communicating information sensed locally at the strategic points to a designated, higher level control entity(s). Utilizing intelligent, distributed control methodologies, several methods have been developed to isolate/reconfigure distribution circuits without the need for the higher-level control entity(s). In systems implementing these methods, information is sensed and processed locally, acted on as much as possible locally, and then shared with other cooperating devices to either direct or enhance their ability to take action. Examples of these methods include versions of the IntelliTEAM® product available from S & C Electric Company, Chicago, Ill.
Systems, such as the IntelliTEAM® products and the systems described in commonly assigned U.S. Pat. No. 6,697,240, the disclosure of which is hereby expressly incorporated herein by reference, provide methodologies and related system apparatus for using and coordinating the use of information conveyed over communications to dynamically modify the protection characteristics of distribution devices (including but not limited to substation breakers, reclosing substation breakers, and line reclosers). In this way, overall protection and reconfigurability of the distribution system or "team" is greatly enhanced. Devices within the system recognize the existence of cooperating devices outside of the team's domain of direct control, managing information from these devices such that more intelligent local decision making and inter-team coordination can be performed. This information may include logical status indications, control requests, analog values or other data.
Still, when restoration systems reconfigure distribution feeders, for the purpose of fault isolation and/or load restoration, the coordination between fault protection devices, such as interrupters, used to segment the feeder, can be destroyed. Thus, an automated method to reconfigure the protection settings to maintained coordination is desired. Further, benefits may be obtained where the fault protection devices are set so they coordinate with other devices that may or may not automatically set, for example, boundary devices such as circuit breakers that protect the distribution feeder and fuses that protect loads that are tapped off the feeder.
In some instances, where a fault current exceeds a melting current of a fuse protected distribution line, fault interruption followed by automated restoration may lead to service restoration if the fault is transient; however, service disruptions followed by inevitable service loss with the fuse melting may be the result for persistent faults or sufficiently high current faults. This may be particularly true for loads extending from the distribution line between the fuse and the fault protection device.

Fault testing fault protection device and method


A heating element assembly for use in a rapid prototype modeling machine is described. The heating element of the hot melt assembly and an associated product container deliver hot melt product to the jets of the rapid prototype modeling machine.

1. Description of the Art Practices
It is known that materials may be melted and re-solidified in order to form solid objects, such as in the field of rapid prototype modeling. The present invention deals with rapid prototype modeling and, in particular, with an efficient manner for melting materials.
2. Background of the Invention
It is known in rapid prototype modeling that the hot-melt material suffers from the difficulty of uneven melting. The hot-melt product must melt in sufficient time to be utilized with a jet for application of the hot-melt material to a substrate. The heating of the hot-melt product should be accomplished at as low an energy cost as possible.
It is desirable to use a solid slug of a hot-melt material in a rapid prototype-modeling machine. However, the use of a solid slug is difficult if the solid slug melts unevenly in the heating mechanism.
The present invention is directed to the use of slugs of a hot-melt material, and in particular a slug from a container which may remain in place during melting of the slug. The hot-melt heating element assembly of the present invention is uniquely adapted to the use of maintaining a container in place as the slug of material is melted.


A free-standing bulk depositor includes wheels or other mechanical contrivances that enable the unit to be moved from place to place, for example to different tables on the floor of a casino, and includes various currency and/or document processing devices, including a transport mechanism that feeds a stack of documents past at least one sensing/imaging device, a logic unit that sends the documents to appropriate cassettes or drop boxes depending on the type of document and whether the document can be authenticated, and an escrow spool that holds suspect documents while images of the suspect documents are being reviewed in case the logic unit cannot determine whether a document is authentic. The documents may be banknotes, tickets, vouchers, coupons, or other documents having an identifiable value.

1. Field of the Invention
This invention relates to a device arranged to receive and validate currency and other items of value, including tickets, vouchers, coupons, markers, scrip, match play documents, and so forth. The device is suitable for use in environments where large numbers of the printed items of value are exchanged in a short interval of time. By way of example and not limitation, the device may be used at a gaming table of a casino.
Unlike previous bill acceptors designed for use in gaming environments, the device of the invention is mobile and free-standing, thereby enabling the device to easily be move to wherever needed, and to be removed and replaced for service or maintenance.
Furthermore, instead of simply rejecting items that cannot be internally validated, the device of the invention includes an escrow feature that enables remote validation of suspect notes while other notes are being processed, thereby enabling play to continue with minimal inconvenience to the dealer and legitimate players.
2. Description of Related Art
Traditionally, when a dealer at a casino receives a stack of cash from a player for the purpose of purchasing chips, the dealer simply drops the cash through a slot in the table into a secure capture drop box. The slot is positioned to enable the dealers to conduct transactions without taking their eyes off the table, and without placing their hands or any media out of the view of the security camera system that monitors the table. Secure capture drop boxes may be used in connection with a variety of table games, such as black jack, craps, roulette, and baccarat.
A problem with the traditional system is that it is difficult to count stacks of notes while game play is proceeding, and virtually impossible to validate or authenticate the notes until the capture box has been physically removed from the table and taken into soft count to be verified. This has long been viewed as a security risk to both the casino and gaming commissions, and therefore there has been a long felt need for ways to automate note (i.e., cash or other items or documents of value) acceptance and validation, in order to more efficiently count and validate notes as they are received at the table, thereby reducing the risk of employee theft and increasing the casino's protection against counterfeit activity.
In the casino environment, there are several requirements for automated note acceptors. First, the device should be at least as fast and easy for the dealer to use as the conventional slot and drop box, so that use of the device does not slow down a game in progress. Second, all transactions and handling of notes or other documents of value must be within full view of the casino security cameras. Third, the device should be able to accept a variety of notes, including tickets, vouchers, and the like, as well as currency of a variety of different denominations. Fourth, the device should be reliable with a minimal number of jams and easy removal of the jams, and the ability to handle notes of poor quality. Fifth, the device should not be tied to a particular table but rather should be able to be positioned wherever needed, and in particular should be easily removed and replaced if repair is necessary. Sixth, the system should have the ability to retain suspected counterfeit notes for further investigation and to prevent re-use.
This problem has been addressed in a series of patents and publications owned by JCM American Corporation (the JCM patents and publications). These patents and publications, including U.S. Pat. Nos. 6,745,887, 6,889,849, and 6,968,787, and U.S. Patent Publication Nos. 2005/0121286, 2005/0126880, and 2005/0126881, disclose automatic bill acceptors that are specifically designed for use at gaming tables, and that are designed to enable a dealer to insert stacks of bills, tickets, or other notes given to the dealer in exchange for gaming chips, and to validate the notes before game play proceeds to ensure that the notes are not counterfeit. However, there are at least two disadvantages to the bill acceptor designs disclosed in the JCM patents and publications.
The first disadvantage is that JCM takes the approach of mounting the bill acceptors directly to the gaming table, in a manner similar to the standard secure drop box. As a result, the table must be shut down whenever repair or maintenance is required, the repair or maintenance must be carried out on the casino floor in view of casino patrons (casinos never close), and a bill acceptor must be provided for every gaming table even though not all tables will necessarily be in use at any given time.
The second disadvantage is that the JCM table system rejects any notes that cannot be automatically validated, irrespective of the reason that the bill cannot be validated, resulting in a relatively high number of game interruptions and embarrassment or inconvenience to persons presenting notes that cannot be automatically validated for reasons other than inauthenticity.
Other patents that are of background interest because they disclose gaming or wagering systems other than gaming table bulk depositors, or subsystems that might possibly be used in or that are related to bill acceptors, include U.S. Pat. No. 5,826,680, which describes a bill handling system for accepting bills taken in game play media lending machines and for transporting the bills to a cash box, as well as a system of secure bill receiving cassettes; U.S. Pat. No. 5,957,776, which describes an electronic monitoring system for a gaming table integrated with a casino central management system, in which information is tracked regarding operations of the gaming table, the dealer, the floor manager or player in a pit, and a cash box system that provides bill denomination signals to a host control system; U.S. Pat. No. 6,460,848, which discloses a system for automatically monitoring playing and wagering of a game, in particular a chip and card tracking system and table monitoring logic verifying game play, cash box processing, player analysis and employee analysis; U.S. Pat. No. 6,595,857, which discloses a system for tracking playing cards at a gaming table; U.S. Pat. No. 6,579,180, which discloses a casino gaming table monitoring system including a card deck reader, chip tray reader, currency authenticator including bill imaging; and U.S. Pat. No. 6,663,490, which discloses an electronic gaming table monitor similar to that described in U.S. Pat. No. 6,460,848; U.S. Pat. No. 6,676,517, which discloses an electronic gaming table monitor system including position data; cards; dice; roulette wheels and other data; wager data; payout system; electronic paddle used in a drop slot of the table; and communication with a central server; U.S. Pat. No. 6,688,979, which discloses game table play tracking, a chip reader, card reader, and table image, with play tracking and communication with a central server; U.S. Patent Publication No. 2004/0002386, which describes an electronic casino information management system that enables conducting casino business at any location within the casino based on the use of a handheld computing device, and U.S. Patent Publication No. 2004/0033832, which describes a closed system for counting monetary instruments from a plurality of games within a casino, a bill validator that receives, validates and counts monetary instruments and transmits data to a central processor.
Also of background interest are U.S. Pat. No. 4,755,941, which describes a chip tray monitoring system; U.S. Patent Publication No. 2003/0155209, which describes a portable safe arrangement for currency transport system associated with a game card vending machine; U.S. Pat. No. 5,676,231, which describes a secure cash box system for currency accepting machines; U.S. Pat. No. 5,890,440, which describes a cash box arrangement for a gaming table; U.S. Pat. No. 6,641,483, which describes a security cabinet arrangement for electronic casino game controllers; and U.S. Pat. No. 6,845,905, which describes a casino cash transporter with a secure cash box.


This invention relates to the fabrication of lenses which can focus a light beam to a spot size which is smaller than that allowed by diffraction theory. A composite lens function is constructed using a strong centered lens function and several additional lens functions having different weights, different separation distances from the center, and different phases. The focused spot consists of the vector sum of these differently weighted electric fields from the separate lens functions. By varying the separation distances, the weights, and the phases of the additional lens functions, the vector sum of the electric fields from the lens functions produces a focused spot whose width is less than the diffracted limited spot size. Such composite lens functions can be produced, for example, using diffractive optics techniques or by programming the lens function onto a spatial light modulator.

Optical lenses are used to focus a beam of light. However the size of the focused spot is limited from diffraction theory. One such equation, which is discussed by E. Hecht in "Optics", (Addison-Wesley, Mass., 1988), gives the diameter d of the focused spot by the equation ##EQU1## where .lambda. is the wavelength of the light, and f is the focal length of the lens. Here D usually represents the diameter of the lens assuming that the lens is completely illuminated. Otherwise it represents the diameter of the optical beam if it is smaller than the lens. FIG. 1A shows the formation of a diffraction limited spot by a lens.
There are many applications in which a very small focused spot size is desired such as in photolithography, in making high density computer memory chips, in laser machining where high energy densities are desired, and in the reading and writing of compact discs where smaller spot sizes mean longer playing times and higher memory content. According to Eq. (1), three ways of decreasing the spot size are to use shorter wavelengths, shorter focal lengths, or larger diameters. However diffraction theory places a limit on that size.
In order to focus the light, the phase of the incident optical beam .phi.(x,y) must be altered as a function of x and y. This phase function is discussed by A. Yariv in "Introduction to Optical Electronics", (Holt, Rinehart, and Winston, N.Y., 1991) and is given, using small angle approximation theory, by ##EQU2## where f is the focal length of the lens and k=2.pi./.lambda..
More complicated aspheric phase functions are required to obtain the diffraction limited size for the focused spot size as known to those skilled in the art. Some of these are discussed by Kedmi et. al. in U.S. Pat. No. 5,073,007 titled "Diffractive optical element". Lens functions can operate either in transmission as with conventional glass lenses, or in reflection as in the case of focusing mirrors.
For purposes of this Specification, the term "lens function" is defined as a phase and/or amplitude function and which operates either in a reflection or transmission mode.
The phase shift of light traveling through a medium of thickness d is related to ##EQU3## where n is the index of refraction of the medium. This phase can be encoded by varying the index of refraction or the thickness of the material.
The phase function can be encoded to form a lens using several techniques as known to those skilled in the art. The first is refraction and involves the bending of light as it passes through an interface between two different materials such as glass and air. By making a curved glass element as shown in FIG. 1A, different rays of light will be bent by different amounts as they pass through the lens. The phase function is controlled by varying the thickness of the glass lens. By making the glass surfaces with the correct shapes, diffraction limited lenses can be manufactured. These lenses are called refractive optical elements and are the most common lenses available.
A second technique known in the prior art involves diffraction. This approach uses the well known diffraction formula m.lambda.=psin.theta. where m is the order, .lambda. is the wavelength, p is the grating spacing and .theta. is the angle from normal to the grating. If the grating spacing p varies with distance r from the axis in the correct manner as discussed by E. Hecht in "Optics", (Addison-Wesley, Mass., 1988), then the diffraction angle will vary also as shown in FIG. 1B, again forming a focused spot. These lenses are called diffractive optical elements. Examples of such lenses are Fresnel lenses, binary optical elements, and holographic optical elements.
In making Fresnel lenses, the phase function forming the diffraction grating can be encoded using a variety of techniques. A discussion of these techniques can be found in several articles in "Proceedings of SPIE", Volume 1052, (1989).
These encoding techniques can be understood using the Euler relation where .phi.(x,y) is given by Eq. (2), as EQU e.sup.i.phi.(x,y) =cos(.phi.(x,y))+i sin(.phi.(x,y)) (4)
Here the real part is given by cos(.phi.(x,y)) and the imaginary part by sin(.phi.(x,y)). The phase function can be encoded by examining the entire phase function, or only its real or imaginary part.
Some representative phase encoding techniques for making diffractive optical elements or binary optical elements include:
1. Making the grating with adjacent transparent and opaque circular regions. This pattern can be described as a zone plate with alternating transparent regions as discussed by M. V. Klein in "Optics" (J. Wiley and Sons, New York, 1970). In this approach, the phase function is made using a computer program. In one example the phase function is made equal to +1 whenever the Real part of the complex function shown in Eq. (4) is positive. When the Real part of the complex function shown in Eq. (4) is negative or zero, the phase function is made equal to 0.
2. Making the grating with adjacent regions in which the phase of the transmission differs by .pi. radians from one region to another. This pattern is referred to as a binary phase-only filter (BPOF). In this approach, the phase function is made using a computer program as discussed by D. Psaltis et. al. in "Optical image correlation with a binary spatial light modulator" published in Optical Engineering, vol 23, p 698-704, Nov/Dec. (1984). In one example whenever the Real part of the complex function shown in Eq. (4) is positive, the phase function is made equal to +1. When the Real part of the complex function shown in Eq. (4) is negative or zero, the phase function is made equal to -1.
3. Using holographic techniques to encode the phase function as discussed by M. Feldman and C. Guest in the article titled "Computer generated holographic optical elements for optical interconnection of very large scale integrated circuits" published in Applied Optics, vol 26, p 4377-4384, (1987).
4. Using photolithography or a ultraviolet laser writer combined with reactive ion etching to selectively vary the thickness of the optical element to encode the required phase function as discussed by Y. Carts in the article titled "Microelectronic methods push binary optics frontiers" published in Laser Focus World, p. 87-95, February (1992).
5. Using direct e-beam writing to selectively vary the thickness of the optical element to encode the required phase function as discussed by Y. Carts in the article titled "Microelectronic methods push binary optics frontiers" published in Laser Focus World, p. 87-95, February (1992).
6. Using diamond turning to selectively cut the surface of the optical element to encode the required phase function as discussed by Y. Carts in the article titled "Microelectronic methods push binary optics frontiers" published in Laser Focus World, p. 87-95, February (1992).
7. Using an ion exchange process to selectively vary the phase profile of a material by varying the index of refraction of the material as a function of position as discussed by H. Bolstad et. al. in the article titled "Optimization of phase-only computer generated holograms using an ion-exchange process" published in Optical Engineering, vol 31, p. 1259-1263, (1992).
8. Using replication techniques in which a master surface-engineered diffractive optical element is first produced using techniques such as discussed above. Then replica copies can be made by impressing the surface relief pattern onto another material including a variety of plastic materials as discussed by Y. Carts in the article titled "Microelectronic methods push binary optics frontiers" published in Laser Focus World, p. 87-95, February (1992).
Optical elements can also be made using a combination of refractive and diffractive techniques. This approach offers several advantages including correction of chromatic aberrations as discussed by T. Stone et. al. in the article titled "Hybrid diffractive-refractive lenses and achromats" and published in Applied Optics, vol 27, p 2960-2971, (1988).
Finally, optical elements can be made encoding the desired phase function onto programmable recording media including spatial light modulators (SLMs). Some of the devices which are well known to those in the field include the magneto-optic spatial light modulator (MOSLM), liquid crystal light valve (LCLV), liquid crystal television (LCTV), and deformable mirror device (DMD). These modulators can allow encoding of pure amplitude information, a binary phase pattern, a pure phase-only function, or combinations of amplitude and phase information. FIG. 1C shows the formation of a focused spot by diffractive optical elements which has been encoded onto a SLM.
Diffractive optical elements can offer more design freedom than refractive optical elements since the phase distribution can be varied more easily allowing the construction of more complicated optical elements.
Nevertheless, despite the longstanding goal of obtaining a subdiffraction limited focused beam, the problem remains unsolved.


A device for measuring an electric current flowing in a cable, including a flexible Rogowski coil, secured to actuating means for moving the coil to an open position for engagement around a cable, and a closed position to surround the cable, a magnetic circuit, with a winding around the magnetic circuit, for closing around the cable when the coil is in the closed position. The coil in the closed position, may have a non-wound area of predefined length with an overwinding at each opening end of the coil.

The invention relates to the field of measurement of an electric current flowing in a cable.
The object of the invention is more particularly to provide a device for measuring an electric current flowing in a cable, comprising means for securing a flexible Rogowski core able to occupy an open position enabling engagement around the cable and a closed position designed to surround the cable.
It also relates to an assembly for measuring this current comprising at least one measuring device, and to a device for measuring power and energy comprising at least one such measurement sensor.

Device for measuring an electric current in a cable