A semiconductor memory device is tested in a bit-compressed test mode wherein a plurality of banks of memory cells, which are disposed in association with respective I/O pins, are tested through one of the I/O pins. During the bit-compressed test mode, a check mode is additionally entered to examine whether the memory device actually stays in the bit-compressed test mode. The result of check by the check mode is supplied through the one of the I/Os pin delegating the plurality of I/O pins. The bit-compressed test mode is effected with accuracy.

(a) Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device capable of being tested with a correct test mode.
(b) Description of the Related Art
DRAM (dynamic random access memory) increases its storage capacity four fold with each new generation. Then, it follows that if the number of I/O (input/output) units remains unchanged, the time length required to access all the memory cells in the memory device also increases by factor of four at each generation change. To avoid the delay for the access time, a x16 product is developed and commercially available which has 16 I/O pins to be accessed at one time for read/write operation compared to four I/O pins in the conventional x4 products. This permits the access time for all the memory cells to be unchanged between the x4 products and the x16 products. This also allows a screening test time for the memory products to be substantially reduced by a quadrature factor for x16 products than for x4 products having the same storage capacity.
However, in consideration that the memory tester generally has a number of read-out comparators depending on the number of products which can be simultaneously tested, if a x16 product tester contains the same number of comparators as for a x4 product tester, it follows that the number of memory devices which can be tested simultaneously is reduced by a factor of four for the x16 products than for the x4 products, thereby degrading the efficiency in the product screening test.
A bit-compressed test mode is recently proposed which prevents such degradation in the screening test by using a single I/O pin in read-write operation of data for four I/O pins among sixteen I/O pins, for example. An example of conventional circuit arrangements of semiconductor memory device operating in such a bit-compressed test mode is shown in FIG. 1.
In FIG. 1, it is to be noted that the arrangement of data-in buffers DIB1-DIB4 and data-out buffers DOB1-DOB4 which are associated with I/O pins IO1-IO4 have different configurations: the arrangement of data-in buffer DIB2 and data-out buffer DOB2 for IO2 pin is different from the arrangement for the remainder of data-in buffers DIB1, DIB3 and DIB4 and data-out buffer DOB1, DOB3 and DOB4, respectively, for I/O pins IO1, IO3 and IO4. In addition, NAND gates NA901-NA903 are provided for four banks of memory cells in the memory device to provide test result signal TFAILB through IO2 pin.
FIGS. 2 to 5 show circuit configurations of data-out buffers DOB1, DOB3 and DOB4, data-out buffer DOB2, data-in buffers DIB1, DIB3 and DIB4, and data-in buffer DIB2, respectively. In these drawings, as in the rest of the drawings, characters INV, NA, QN, QP, TG, NO and N attached to numerals show that those elements are inverter, NAND gate, N-ch MOSFET, P-ch MOSFET, transfer gate, NOR gate and signal node, respectively.
Referring to FIG. 2, each of data-out buffers DOB1, DOB3 and DOB4 has an inverter INV201 receiving TEST signal for effecting a bit-compressed test mode, a NAND gate NA201 receiving an output from INV201, data from bus RWBSTi (I=1,3 or 4) and output-enable signal OE, a NAND gate NA202 receiving an output from INV201, data from bus RWBSNi (1=1, 3 or 4) and output enable signal OE, inverters INV202 and INV203 receiving outputs from NA201 and NA202, respectively, and a pair of serial N-ch MOSFETs QN201 and QN202 receiving outputs from INV202 and INV203, respectively, at respective gates thereof, for supplying output signal to IOi pin (I=1, 3 or 4) through the node connecting the MOSFETs QN201 and QN202.
Referring to FIG. 3, data-out buffer DOB2 in FIG. 1 is similar to data-out buffers DOB1, DOB3 and DOB4 shown in FIG. 2 except that a test result signal TFAILB showing the occurrence of a failure in the read out data is used instead of TEST signal, and data from bus pair RWBST2 and RWBSN2 are used instead of data from bus pair RWBSTi and RWBSNi (I=1, 3 or 4), respectively.
Referring to FIGS. 4 and 5, data from Ioi pin (i=1 to 4) is supplied to respective data bus pairs RWBSTi/RWBSNi, as will be detailed below.
FIG. 6 shows a timing chart during a bit-compressed test mode in the memory device of FIG. 1. To enter a bit-compressed test mode from a mode, other than a test mode, which enables a normal write/read operation, a WCBR (WEB CASB Before RASB) cycle, which was standardized from 4 Mbit DRAMs, is effected while simultaneously supplying a predetermined specific key input to address key-input pins (A3, A4 and A5 pins in FIG. 1). At this time, no super-voltage (for example, 10 volts) which exceeds a normal voltage of 5 volts is applied to SVT (super-voltage pin, A0 in FIG. 1).
FIG. 6 illustrates write/read cycles during the bit-compressed test mode. Initially, RASB (row address strobe) is made low to accept a row address, and then CASB (column address strobe) is made low to accept a column address. WEB (write enable) is also made low, allowing W0 signal to turn from low to high to provide a single shot of W0 signal, whereby the first stage of IOi (where i=1 to 4) is enabled to accept write-in data or data to be written.
In the bit-compressed test mode, four I/O pins IO1 to IO4 are delegated by a single I/O pin (IO2, in this example) to achieve a bit-compressed test mode. Accordingly, it is only necessary that IO2 pin accepts data to be written, and it does not matter if other IOi pins (where i=1, 3 and 4) stay at a high impedance state (Hi-Z).
Referring to FIG. 4 which shows the circuit arrangement of data-in buffers DIB1, DBI3 and DIB4, even if W0 turns high to enable NAND gate NA403 to pass data from Ioi pin, transfer gate TG402 remains off because TEST signal remains high (and therefore an output from NOR gate N0401 is low ). Thus, written-in data which is fed from IOi pin (where i=1, 3 or 4) is not accepted. Instead, The inverted signal of data DIN2N, which is accepted by transfer gate 501 in data-in buffer DIB2 shown in FIG. 5 associated with IO2 pin, is fed through transfer gate TG401 in data-in buffer DIBi in FIG. 4 which is turned on by TEST signal.
Subsequently, W1 signal turns from low to high, whereby transfer gate TG501 (see FIG. 5) in data-in buffer DIB2 is turned off, allowing the accepted data to be latched by a flipflop formed by inverters INV504 and INV505. Thereafter, W2 signal turns from low to high, whereupon read/write bus pairs RWBSNi/RWBSTi for data-in buffer DIBi (where i=1, 3 and 4) shown in FIG. 4 and read/write bus pair RWBSN2/RWBST2 for data-in buffer DIB2 in FIG. 5 are driven in accordance with the same write-in data fed from IO2 pin. Accordingly, write amplifiers 105 shown in FIG. 1 drives data line pairs IOTi/IONi (where i=1, 2, 3 and 4) for writing the same data into respective memory cells in the four banks.
Now, the read cycle of the bit-compressed test mode will be described. As in the write cycle, RASB assumes low and then CASB assumes low to allow read-out addresses to be accepted. Data stored in memory cells at these addresses for four I/O pins are read out onto data line pairs IONi/IOTi (where i=1, 2, 3 and 4), whereby data amplifiers 104 drive respective bus pairs RWBSNi/RWBSTi (where i=1, 2, 3 and 4).
During the bit-compressed test mode of this example, a read/write operation occurs with the same data for four I/O pins, and hence data read out onto bus pairs RWBSTi/RWBSNi (where i=1, 2, 3 and 4) are equal to each other.
In FIG. 1, when data, all of which are equal to each other, are read out, either output from NAND gate NA901 or NA902 is low independently of whether the data read out are equal to 0 or 1, and hence the test result signal TFAILB from NAND gate NA903 remains high. In this case, it is known from the high level of TFAILB signal that equal data is read out for four IO pins. Referring to FIG. 3 which shows the circuit arrangement of data-out buffer DOB2 associated with pin IO2, data on bus pair RWBST2/RWBSN2 delegates the four data, and if output enable OEB is low and signal OE which is a complimentary signal of OEB is high, read-out data is delivered to IO2 pin. Specifically, in FIG. 3, when TFAILB signal assumes high and OE signal assumes high, NAND gate NA1001/NA1002 delivers an inverted signal of the complimentary signal from bus pair RWBST2/RWBSN2, which is again inverted in an inverter INV1001/INV1002 to feed N-ch transistor QN1001/QN1002, thereby delivering a voltage equivalent to the logic value of RWBST2 from IO2 pin.
In the data-out buffer DOBi for the remaining IOi (where I=1, 3 or 4) shown in FIG. 2, because TEST signal is high, an output from NAND gate NA201/NA202 which receives TEST and OE signals and data from corresponding bus pair RWBSTi/RWBSNi assumes a high level even if the signal OE is high. Accordingly, an output from inverter INV202/INV203 assumes a low level. In this state, N-ch transistors QN201 and QN202 are both turned off, and an output at IOi pin (i=1, 3 or 4) remains at its high impedance state(Hi-Z).
On the other hand, if one of data read out from bus pairs RWBSTi/RWBSNi (where i=1 to 4) is different from other data, TFAILB signal assumes low. Thus, as understood from FIG. 3, an output from NAND gate NA1001/NA1002 which receives TEST and OE signals and data from RWBST2/RWBSN2 assumes a high level, and N-ch transistors QN1001 and QN1002 are both turned off, resulting in an output of Hi-Z through IO2 pin, indicating the occurrence of a failure.
In the event that although the outputs for all the I/O pins (IO1 to IO4) are equal, and yet the data itself is wrong, a failure is detected by the fact that data delivered from IO2 pin is different from an expected value.
In the manner as described above, a read/write operation of data for four I/O pins IO1 to IO4 which are compressed into a single I/O pin is performed.
In the conventional semiconductor memory device described above, it is generally considered sufficient that attention be paid only to IO2 pin during the bit-compressed test mode. However, if the screening test is effected by paying attention only to IO2 pin, a product or products maybe erroneously determined as acceptable in the event that they pass a test effected for IO2 pin even if the product or products to be screened are involved with some defect in the memory device or other reason which prevents them from entering the bit-compressed test mode. Thus, a problem occurs that bank for the IO1, IO3 and IO4 pins may not be properly tested.

Semiconductor memory device having a bit compressed test mode and a check mode selecting section


An MF connector module is provided that positions the fiber end portions relative to respective V-grooves of the module in such a way that the fiber end portions can be bent, and thereby loaded, by a predetermined amount when the fiber end portions are being installed in the respective V-grooves. The bending of the fiber end portions ensures that the optical axes of at least the tips of the fiber end portions are parallel to the optical axes of the respective V-grooves. The loading of the fiber end portions caused by the bending ensures that significant lengths of the fiber end portions are tangent to and in contact with the inner walls of the respective V-grooves. This tangential contact between the fiber end portions and the inner walls of the V-grooves causes the fiber end faces to be precisely aligned with the respective optical axes of the MF connector module.

Multi-optical fiber (MF) connector modules are used to mechanically couple the ends of a plurality of optical fibers to a parallel optical communications module that has a plurality of optical channels. The parallel optical communications module may be a parallel optical transceiver module having both transmit and receive optical channels, a parallel optical transmitter module having only transmit optical channels, or a parallel optical receiver module having only receive optical channels. A typical MF connector module includes an optics system that couples light between the ends of the optical fibers held in the MF connector module and the parallel optical communications module. Within the parallel optical communications module, an optics system couples light between the MF connector module and a plurality of optoelectronic devices disposed inside of the parallel optical communications module. For transmit optical channels, the optoelectronic devices are electrical-to-optical converters such as laser diodes or light-emitting diodes (LEDs). For receive optical channels, the optoelectronic devices are optical-to-electrical converters such as P-intrinsic-N (PIN) photodiodes.
The MF connector modules and the parallel optical communications modules typically have mating features on them that allow them to be fixedly or removably mechanically coupled (i.e., mated) with one another. A variety of MF connector modules and parallel optical communications modules exist in the market today that are designed to mate with one another in a way that optically aligns the optical pathways between the ends of the optical fibers and the respective optoelectronic devices to enable optical data signals to be efficiently optically coupled between ends of the optical fibers and the respective optoelectronic devices. In designing and manufacturing the MF connector modules and the corresponding parallel optical communications modules, great care is taken to ensure that once the modules are mated together, very precise optical alignment exists along the optical pathways.
Inside of the MF connector module, the ends of the optical fibers are typically held in alignment with respective lenses of the optics system of the MF connector module. The lenses of the connector module couple light between the ends of the optical fibers and the optics system of the parallel optical communications module, which often folds the optical pathways by some angle (e.g., 90°). However, the folding of the optical pathways is sometimes performed by the optics system of the MF connector module, or folding may be performed by each of the optics systems.
The alignment of the optical pathways that extend between the ends of the optical fibers, the optics system of the MF connector module, the optics system of the parallel optical communications module, and the optoelectronic devices of the parallel optical communications module should be very precise in order to ensure good optical coupling efficiency and good performance. A variety of configurations exist for holding the ends of the fibers in fixed, aligned positions within the MF connector module. It is well known to use a V-groove configuration in the MF connector module for holding the ends of the optical fibers in fixed, aligned positions within the MF connector module. The ends of the optical fibers are positioned in respective V-grooves and then a refractive index matching epoxy is used to fix the ends in position within the respective V-grooves. A cover is sometimes placed over the V-grooves to protect the fiber ends and to help hold them in position.
One potential problem with such V-groove configurations is that the V-grooves do not always perfectly align the ends of the respective fibers with the lenses of the MF module. This is because the optical fibers do not always conform to the V-grooves. The optical fibers tend to act like rigid rods in the V-grooves in that misalignment of the fiber at the back of the V-groove will result in misalignment of the fiber at the front of the V-groove. For example, if the fiber has ridden up the edge of the respective V-groove at the back of the V-groove, it will usually also ride up the edge of the V-groove in the front of the V-groove. In addition, optical fibers of an optical fiber ribbon cable are not always parallel to one another in all planes once the fibers have been freed from the cable and stripped of their jackets. Fibers in a ribbon cable have a "set," which means that when freed from the cable and stripped of their jackets, they curl in multiple directions and are not all parallel in all planes. The fiber "set" makes it difficult to achieve the needed micron-level alignment accuracy of the fiber ends with their respective lenses.
Moreover, if the V-grooves are formed in plastic, the V-grooves may deform in the areas where a load is applied when the fibers are pressed into them. This can cause the front portion of the fiber end (end portion nearest to the lenses) to lift upwards away from the V-groove, even if the deformation is within the elastic stress range of the plastic. This upward lifting of the fiber end in combination with the "set" problem can mean that a different force is acting on each fiber due to its unique set, which can cause the V-grooves to deform by unique amounts for each fiber. This, in turn, can result in a unique alignment error for each fiber.
A need exists for an MF connector module and methods that enable ends of optical fibers to be installed and held in an MF connector module in precise alignment with respective optical axes of the module.

Precision alignment of optical fiber ends along respective optical pathways in a multi-optical fiber connector module, and methods

Avago Technologies General IP (Singapore) Pte. Ltd.


An input buffer circuit includes a voltage limiting circuit and a protection circuit coupled between a pull-up component and a pull-down component of a level detecting circuit. The voltage limiting circuit receives an input signal at a first voltage range and limits the input signal to a safe voltage range, the first voltage range being between an electrical ground and a first supply voltage level, and the safe voltage range being between the electrical ground and a second supply voltage level. The level detecting circuit has a pull-up component receiving the input signal directly from the input terminal and a pull-down component receiving the safe voltage range from the voltage limiting circuit. The level detecting circuit transitions the input signal from the first voltage range to the input signal at the second voltage range. The protection circuit is coupled in series between the pull-up component and the pull-down component so as to protect the level detecting circuit from gate oxide overstress.

Input buffer circuits are commonly used in Input/Output (I/O) units of Integrated Circuit (IC) devices for receiving data input signals from external systems. When the received data input signals have a voltage level that is greater than the supply voltage of the integrated circuit device, the input buffer transitions the received data input signals to the supply voltage level of the integrated circuit device. With the ever increasing speed requirements of conventional integrated circuit devices, there has been a corresponding need for high-speed input buffers. In order to increase the speed of input buffer circuits and to lower power consumption IC manufacturers have moved to thin gate oxide fabrication processes. However, the high voltage of the input signal can cause breakdown of the gate oxide. In addition, these input buffer circuits can suffer from duty cycle distortion.
In order to solve these problems, one prior art input buffer uses a NMOS transistor in series with the input terminal to limit the voltage swing at the gate oxide of an input inverter, thus protecting the thin gate oxide of the NMOS pull-down transistor and the PMOS pull-up transistor. To reduce the supply current when the input is high, a pull-up circuit (e.g. PMOS transistor gated by the output) is used to pull up the input of the inverter when the input signal is substantially more than the trigger voltage of the inverter. However, the problem of duty cycle distortion exists in this type of input buffer circuit because the voltage at the node of the pull-up circuit and the input of the inverter is time dependent. In other words, the voltage at the input of the prior art inverter depends on its previous value when the input signal changed states. Furthermore, this type of prior art input buffer circuit may have unwanted DC current flow in to the input terminal when the input signal is transitioning from high to low
Thus, there is a need for a high speed input buffer circuit that can tolerate high voltage input signals. Moreover, there is a need for an input buffer that has low power consumption and that does not have duty cycle distortion. The present invention meets the above needs.


Coordinated Multipoint (CoMP) involves multiple transmission points or cells coordinating their individual transmissions so that a target user equipment (UE) experiences enhanced signal reception and/or reduced interference. In order to optimally implement downlink CoMP, a serving cell needs to obtain channel state information (CSI) for the downlink channels from the multiple transmission points to the UE. This disclosure deals with radio resource control (RRC) signaling for configuring the UE to obtain and report CSI for those downlink channels.

A major feature of LTE-Advanced (Long Term Evolution-Advanced or LTE-A), as part of Release 10 of the LTE specification by the 3rd Generation Partnership Project (3GPP), is increased support for Coordinated Multi-Point (CoMP). In CoMP for the downlink, multiple cells each having a transmission point (TP) coordinate with one other in transmitting to mobile devices or terminals, referred to as user equipments (UEs) in LTE, so as to result in reduced interference and/or enhanced signal strength. In order for a set of cooperating cells to employ CoMP in transmitting to a particular target UE, knowledge of the downlink channels that exist between the TPs of the cells and the target UE needs to be obtained. Configuring the UE to deliver this information is the primary concern of the present disclosure.

Reference signal configuration for coordinated multipoint


Disclosed is a radio paging receiver wherein changes from the synchronous state to the asynchronous state and vice versa of a radio receiver are detected, the period of time that the receiver is in the asynchronous state is measured by a timing means and recorded, and the recorded period of time is displayed.

1. Field of the Invention
The present invention relates to a paging receiver with a display for displaying the state of reception, and, in particular, to a paging receiver for displaying an asynchronous or unlock state of the paging receiver when the receiver is outside a selective calling area.
2. Description of the Prior Art
When a synchronous state changes to an asynchronous state in a conventional paging receiver, a mark which indicates the asynchronous state is shown on a liquid crystal display (LCD), and an alarm tone is generated from a speaker during a specified time interval.
An example of such a conventional paging receiver is to be found in U.S. Pat. No. 4,928,086, entitled "Pager receiver having a common timer circuit for both sequential lock-out and out-of-range."
This type of conventional paging receiver indicates an asynchronous state but does not inform the user of an asynchronous period during which the receiver is outside the service area, so the problem remains that the asynchronous state cannot be accurately known later. In other words, the user cannot confirm later whether the data was transmitted or not or whether the receiver was outside the service area.

Paging receiver with display for displaying reception state


According to one embodiment, a memory system includes a nonvolatile semiconductor storage able to hold data, a temperature measurement section configured to measure the temperature of the semiconductor storage, a temperature varying section configured to change the temperature of the semiconductor storage, and a control circuit including a transmitter configured such that data received from a host is transferred to the semiconductor storage, and a temperature storage configured to store temperature information received from the temperature measurement section.

In a flash memory, by passing charges through a tunnel insulating film, charges are injected from a semiconductor substrate into a charge accumulating layer or charges are held near the boundary between the charge accumulating film and tunnel insulating film.
However, moving charges in a tunnel insulating film lead to the problem that the tunnel insulating film may deteriorate (i.e., charges trapped in the insulating film increase), resulting in degradation of data holding characteristics. As described above, conventionally, it has been difficult to achieve a nonvolatile semiconductor device that has a high quality memory cell.


The invention relates to a method of installing a bouquet of digital broadcast programmes on the basis of transponders of different minimum symbol frequencies. The frequency band is traversed using a quantization interval corresponding to the minimum symbol frequency of a transponder of a first type (MCPC). If a transponder of the said first type is found, the characteristics of the various transponders of first or of second type which are referenced in the said signaling table are extracted from its signaling table and the services associated with the various transponders are installed. If no transponder of the said first type is found, the said frequency band is traversed using a quantization interval corresponding to the minimum symbol frequency of a transponder of a second type so as to search for at least one transponder of the said second type and the services of each transponder of the said second type are installed.

The invention relates more especially to the field of audio and/or video digital reception systems complying with the DVB standard (the acronym standing for "Digital Video Broadcast").
The DVB standard is based on the audio and video MPEG-2 standard (the acronym standing for "Motion Picture Expert Group") and relates more especially to the transmission of MPEG-2 signals by satellite, by cable or by a terrestrial route.
The transponders used may be of the MCPC type (the acronym standing for "Multiple Channel Per Carrier") or of the SCPC type (the acronym standing for "Single Channel Per Carrier").
Transmission in MCPC mode allows the broadcasting of several audio and/or video channels on a single frequency by occupying the whole bandwidth of a transponder. In a transmission in SCPC mode, each programme uses a distinct frequency, the transponder being able to contain several frequencies.
The programme broadcasters can use various transponders to build their bouquet of programmes. Specifically, for cost reasons, certain broadcasters who do not have their own network, hire or purchase portions of frequency bands in order to build their bouquet of programmes. Certain programme bouquets therefore contain SCPC transponders and also MCPC transponders. For example, in the case of satellite reception, the band available thereon may be shared by several customers.
Various types of installation of programme bouquets exist. The installation which is simplest for a user is the blind scanning installation. This type of installation allows the user to disregard the signalling parameters which are necessary relative to more sophisticated installation processes. The time to install, under blind scanning, a bouquet on a reception apparatus, such as a set top box or a digital television, is inversely proportional to the sought-after data rate. In the case of the MCPC mode the data rates are of the order of from 15 to 40 Mbaud (mega baud) per second. The data rates in SCPC mode run between 2 and 15 Mbaud per second.
This explains why if an identical installation procedure is used, the time required for installation will be larger under SCPC than under MCPC.
The installation of a bouquet using MCPC and also SCPC transponders under blind scanning is very lengthy since it is necessary to traverse the entire frequency band using a frequency increment which corresponds to the capture span of the components effecting this installation. The latter being calculated on the basis of the smallest symbol data rate sought therefore corresponds within the framework of a mixed multiplex to an SCPC symbol data rate.
The installation of the various programme bouquets using SCPC and also MCPC transponders is therefore much more lengthy than the installation of programme bouquets comprising MCPC transponders only.
The invention therefore proposes to reduce the installation time for programme bouquets using SCPC and MCPC transponders.

Process and device for installing broadcast programs


A medicated module (100) is attachable to a drug delivery device (102). The medicated module (100) includes a housing (104) having a proximal end and a distal end, the proximal end has a connector (110) configured for attachment to a drug delivery device (102). The distal end contains a shuttle (112). A first needle (114) is fixed in the housing (104) and a second needle (116) is fixed in the shuttle (112). The medicated module (100) also includes a reservoir (118) in the housing (104) comprising a medicament (12). Further, the medicated module (100) includes a guard assembly (122) positioned in the housing (104) and configured to move in an axial direction during application to an injection site. Preferably, the medicated module (100) is locked out after at least two injections of the medicament (105) contained in the drug delivery device (102).

Certain disease states require treatment using one or more different medicaments. Some drug compounds need to be delivered in a specific relationship with each other in order to deliver the optimum therapeutic dose. Here, combination therapy may be desirable, but not possible in a single formulation for reasons such as, but not limited to, stability, compromised therapeutic performance and toxicology.
For example, in some cases it might be beneficial to treat a person suffering from diabetes with a combination of a long acting insulin along with a glucagon-like peptide-1 (GLP-1). This GLP-1 is derived from the transcription product of the proglucagon gene. GLP-1 is found in the body and is secreted by the intestinal L cell as a gut hormone. GLP-1 possesses several physiological properties that make it (and its analogs) a subject of intensive investigation as a potential treatment of diabetes mellitus.
A number of potential problems can arise when delivering two active medicaments or "agents" simultaneously. As just one example, the two active agents may interact with each other during the long-term, shelf life storage of the formulation. Therefore, there are certain advantages to storing the active components separately and combine them at the point of delivery, e.g. injection, needle-less injection, pumps, or inhalation. However, the process for combining the two agents needs to be simple and convenient for the user to perform reliably, repeatedly and safely.
One further concern is that the quantities and/or proportions of each active agent making up the potential combination dose or therapy may need to be varied for each user or at different stages of their therapy. Again, as just one example, one or more active agents may require a titration period to gradually introduce a patient to a "maintenance" dose. A further example would be if one active agent requires a non-adjustable fixed dose while the other is varied in response to a patient's symptoms or physical condition. This problem means that pre-mixed formulations of multiple active agents may not be suitable as these pre-mixed formulations would have a fixed ratio of the active components, which could not be varied by the healthcare professional or user.
Additional concerns arise where a multi-drug compound therapy is required, because certain users cannot cope with having to use more than one drug delivery system or make the necessary accurate calculation of the required dose combination. This is especially true for users with dexterity or computational difficulties.
Other problems could arise where a user may attempt to re-use a non-sterile needle after a certain dose combination has been delivered. Using such a non-sterile needle may lead to the transmission of certain diseases (septicaemia) and therefore there exists a need for a medicated module that prevents needle re-use. There is a further concern of inadvertent needle sticks with certain needle assemblies where the injection needle is not concealed or covered, especially after use when a needle may be contaminated with blood. As such, there is also a general need to reduce certain patient's needle anxiety that may heighten a patient's fear or phobia of exposed needles.
Accordingly, there exists a strong need to provide devices and methods for the delivery of two or more medicaments in a single injection or delivery step that is simple and safe for the user to perform and that also tends to reduce a patient's anxiety towards injections or needles.

Medicated module having a double needle guard


The inventive self-leveling wheelbarrows include novel locking mechanisms for maintaining the wheelbarrow at a horizontally level position relative to the underlying terrain.

The present invention is directed to improvements of a product innovation referred to as a "self-leveling wheelbarrow," and which are also described in the inventors' pending patent application, U.S. Ser. Nos. 10/769,989 and 60/443,961. The wheelbarrow incorporates self-adjusting legs which conform to the terrain and lock into place when at rest on the ground. The self-leveling feature offers added stability and provides a significant advantage over conventional wheelbarrows when used on sloping or uneven terrain.
Conventional wheelbarrows are well suited for use on smooth, level surfaces. Their ease of use, excellent mobility, and low cost have made them the material handling equipment of choice for moving small loads in the construction and landscaping industries. As a result of the great success of the conventional wheelbarrow, their basic design has remained essentially unchanged for many years.
However, due to its high center of gravity, fixed leg assembly, and the inherent instability of a tripod-style base, the use of a conventional wheelbarrow on uneven or sloped terrain is somewhat restricted. These factors result in a tendency to overturn if the legs are not resting on a level surface. When level ground cannot be found in close proximity to the working area the worker may be forced to park the wheelbarrow some distance away. The additional walking between the wheelbarrow and the working area during loading or unloading reduces worker productivity. When parked on uneven or sloping terrain, extra care must be taken to avoid overturning and potential injury to the user. Often a wedge or block is placed beneath one leg in order to provide additional stability and prevent overturning. These common problems associated with conventional wheelbarrows are illustrated in FIG. 1.
A simple solution has been devised which greatly improves the stability of a wheelbarrow on sloping or uneven ground and eliminates its tendency to overturn. A self-adjusting mechanism has been added to the leg assembly, allowing the legs to conform to the terrain as the wheelbarrow is lowered and locked into position when both legs are in contact with the resting surface. The self-leveling action increases stability and maintains the wheelbarrow in a level position. The center of gravity remains very nearly centered above the midpoint of the legs, thus the weight is more evenly distributed between the legs, and the tendency to overturn is diminished.
The present invention is directed to a self-leveling wheelbarrow comprising (a) a basin having a front end, a rear end, a left side and a right side; (b) a wheel disposed beneath the basin near said front end; (c) a handle assembly secured to the basin; and (d) a rear mounting bracket secured near the rear end of the basin, the mounting bracket having a top end secured beneath the basin. In certain aspects, the present invention further includes (a) a leg assembly comprising a pair of legs secured to one another by a centrally disposed plate, such that one of the pair of legs is positioned beneath the right side of the basin and the other one of the pair of legs is positioned beneath the left side of the basin, the plate further having a centrally disposed, arcuate top edge and a set of teeth arranged along the top edge; (b) a means for movably securing the leg assembly plate to the rear mounting bracket, such that the leg assembly may rotate in a counterclockwise or clockwise direction and in a vertical direction relative to the rear mounting bracket; and (c) a locking component secured beneath the basin and positioned above the top edge of the leg assembly plate, wherein the locking component is a C-channel member having a pair of adjacent side walls extending downward, each of the side walls further having a tapered edge; and whereby as the leg assembly contacts the underlying ground as the wheelbarrow is parked, the leg assembly rotates about the rear mounting bracket to accommodate the contour angle of the ground, sliding the top edge of the plate within the locking component to thereby engage the tapered edges of said locking component within adjacent teeth of the top edge of the leg assembly plate, thereby further locking the plate therein to prevent the leg assembly from rotating further, either in a clockwise direction of travel or a counterclockwise direction of travel. In certain embodiments, the locking component may be secured to the rear mounting bracket. In addition, each of the side walls of the locking component may include a notch, each notch further including the tapered edge for engagement between adjacent teeth of the top edge of the leg assembly plate when the locking component is engaged with the top edge of the leg assembly plate.
In addition to the basin, wheel, handle assembly, rear mounting bracket, and means for movably securing the leg assembly plate to the rear mounting bracket described above, other aspects of the present invention include (a) a first locking component secured to the leg assembly, the first locking component comprising an elongated inverted U-shaped member having two opposing ends, each of the ends secured to one of the rear legs, and a central portion disposed between the opposing ends; and (b) a second locking component secured beneath the basin and above the central portion of the first locking member, the second locking component comprising a first bar having a slot configured to engage therein the central portion of the first locking component. In operation, as the leg assembly contacts the underlying ground as the wheelbarrow is parked, the leg assembly rotates about the rear mounting bracket to accommodate the contour angle of the ground, sliding the central portion of the first locking component within the slot of the second locking component, thereby locking the central portion of the first locking component therein to prevent the leg assembly from rotating further, either in a clockwise direction of travel or a counterclockwise direction of travel. In other aspects of this embodiment, the second locking component may further include a second bar adjacent the first bar, the second bar having a slot configured to engage therein the central portion of the first locking component, with the slots of the first and second bars being in registration with one another. In addition, the second locking component may secured to the rear mounting bracket.
In addition to the basin, wheel, handle assembly, rear mounting bracket, and means for movably securing the leg assembly plate to the rear mounting bracket described above, other aspects of the present invention also include (a) a first locking component secured to the leg assembly, the first locking component comprising an inverted elongated U-shaped member having two opposing ends, each of the ends secured to one of the rear legs, and a central portion disposed between the opposing ends, the first locking component further including a series of holes penetrating through the first locking component; and (b) a second locking component secured beneath the basin above the first locking component, the second locking component comprising a locking pin configured for engagement within one of the holes of the first locking component. In operation, as the leg assembly contacts the underlying ground as the wheelbarrow is parked, the leg assembly rotates against the rear mounting bracket to accommodate the contour angle of the ground, sliding the central portion of the first locking component upwards for engagement of the locking pin within one of the holes, thereby locking the central portion of the first locking component therein to prevent the leg assembly from rotating, either in a clockwise direction of travel or a counterclockwise direction of travel. In other aspects of the present invention, the holes of the first locking component may be a series of rectangular shaped notches penetrating an outer edge of the first locking component, and wherein the locking pin is a rectangular tab configured for locking engagement within one of the notches. In this embodiment, as in the embodiments described above, the second locking component may be secured to the rear mounting bracket.
The means for movably securing the leg assembly plate to the rear mounting bracket may include a vertical slot provided in the rear mounting bracket and a pin extending from the leg assembly plate, the pin slidably engaged within the vertical slot to allow the leg assembly to move vertically within the slot and to rotate in a clockwise and counterclockwise direction about the pin. Alternatively, the means for movably securing the leg assembly plate to the rear mounting bracket may include a vertical slot provided in the leg assembly plate and a pin extending from the rear mounting bracket, the pin also engaged within the vertical slot of the leg assembly plate to allow for similar vertical and rotational movement of the leg assembly plate against the rear mounting bracket.


A photomultiplier tube 1 is an electron tube comprising an envelope 5 including a frame 3b having at least one end part formed with an opening and an upper substrate 2 airtightly joined to the opening, and a photocathode 6 contained within the envelope 5, the photocathode 6 emitting a photoelectron into the envelope 5 in response to light incident thereon from the outside; wherein multilayer metal films 10b, 10a each constituted by a metal film made of titanium, a metal film made of platinum, and a metal film made of gold laminated in this order are formed at the opening and the joint part between the upper substrate 2 and opening; and wherein the frame 3b and upper side substrate 2 are joined to each other by holding a joint layer 14 containing indium between the respective multilayer metal films 10b, 10a.

Electron tubes such as phototubes and photomultiplier tubes (PMT) have conventionally been known as photosensors. These electron tubes are constructed such that a photocathode which converts light into an electron and an anode are provided within a vacuum container. An example of such electron tubes is a photomultiplier tube in which a component having an inner face formed with a photocathode, a component formed with a photomultiplier part, and a component having an inner face formed with an anode are joined together (see the following Patent Document 1).
Meanwhile, as photosensors have recently been becoming versatile, the demand for reducing the size of electron tubes has been growing. On the other hand, a micropackage structure made by providing a silicon substrate and a glass sheet with respective bonding layers and joining the bonding layers to each other by a solder layer has been known as an example of microdevices having an optical function (see the following Patent Document 2).
Patent Document 1: U.S. Pat. No. 5,568,013
Patent Document 2: Japanese Patent Application Laid-Open No. 2003-175500

Electron tube and method for manufacturing electron tube


An assembled battery voltage detecting apparatus includes a sampling switch section which samples a voltage of each of single batteries, capacitors charged with voltages of single batteries, a transfer switch section to transfer a charge voltage charged in each of the capacitors, a ground potential setting switch section which, in the case of reading the voltage charged in the capacitor, connects a reference electric potential of the capacitor to a grounding terminal of a voltage detecting apparatus, and a voltage detecting circuit which controls a switching timing of each of the above switches, and then reads a voltage of each capacitor.

1. Field of the Invention
The present invention relates to an apparatus and method for detecting a voltage of an assembled battery, and particularly to an apparatus and method for detecting voltages of single batteries in an assembled battery, the apparatus and method being capable of detecting a charge state of a number of single batteries.
2. Description of the Related Art
In an electric vehicle or in a hybrid electric vehicle (HEV), a motor is used as a driving power source. As an electric power source of such a motor, there are used an assembled battery made by serially connecting single batteries such as lithium secondary batteries, fuel batteries or the like.
In particular, the lithium secondary batteries are vulnerable to overcharging or over-discharging. If the batteries are not used at a voltage within a predetermined use range, there is a danger that they cannot be used because a material decomposes, a capacity is significantly lowered, and abnormal heating occurs.
Therefore, in the case where the lithium secondary batteries are used to form an assembled battery, it is required to sufficiently restrict and precisely detect dispersion in voltages of single batteries so as not to occur overcharging or over-discharging in single batteries that configure the assembled battery.
In addition, in the case of fuel batteries which do not require charging as well, it is required to precisely detect output voltages of all single batteries, prevent pole transfer, and prevent shutdown due to an excessive load in order to continuously and efficiently maintain electric power generation. In addition, it is also required to precisely detect output voltages of the fuel batteries in order to detect and control fuel jamming for continuously and efficiently maintaining electric power generation.
In the case of conventional lead batteries using a water soluble electrolyte or an assembled battery composed of single batteries such as nickel batteries, these batteries have properties that dispersion between single batteries is eliminated (uniformly charged) to a certain extent. Thus, over-discharging or overcharging of single batteries have been successfully prevented by monitoring a voltage across a certain single battery and controlling charging and discharging so that the monitored voltage is maintained in a predetermined voltage range.
However, in an assembled battery using lithium batteries as single batteries, the assembled battery being composed by using an organic electrolyte, uniform charging is not carried out under such a control. Thus, it is known that dispersion between single batteries expands, and overcharging or over-discharging of single batteries proceeds, causing performance deterioration such that an unusable state occurs.
Therefore, in a conventional assembled battery using lithium batteries as single batteries, there is provided a charge state detecting apparatus for detecting whether or not a charge state of each of the single batteries as shown in FIG. 8 is controlled to be charged or discharged within a predetermined set voltage range, i.e., abnormal overcharging or over-discharging that exceeds the predetermined set voltage range (for example, refer to FIG. 1 and page 1 of Jpn. Pat. Appln. KOKAI Publication No. 2003-32907).
This charge state detecting apparatus is comprised of; a voltage detecting circuit 15a for detecting overcharging or over-discharging of single batteries in an assembled battery 11 made of a number of single batteries Ba1 to Ban; and an overcharging or over-discharging judging circuit 15b equipped with a logic circuit for judging overcharging or over-discharging from an output of the detecting circuit.
In addition, in the voltage detecting circuit 15a, there are provided, by number of single batteries, resistors RUa and RUb of a voltage dividing circuit for supplying a voltage to judge overcharging by single batteries; resistors RLa and RLb of a voltage dividing circuit for supplying a voltage to judge over-discharging; a constant voltage circuit Er for setting a comparator voltage to judge overcharging or over-discharging; a differential amplifier COU for detecting overcharging from the voltages supplied from these voltage dividing circuits and the comparator voltage set by the constant voltage circuit Er; and a differential amplifier COL for detecting over-discharging.
Further, each one of the differential amplifier COU and the differential amplifier COL is placed at an electric potential with respect to the ground potential, which differs from single battery to battery. Thus, offset voltages of the differential amplifiers COU and COL themselves and an effect of a voltage error of the respective constant voltage circuits Er for setting a reference voltage to be compared cannot be ignored, and there is a problem that the adjustment for controlling the voltage error becomes complicated. Thus, a configuration of this charge state detecting apparatus becomes complicated and expensive, and the detecting apparatus has been unsuitable for voltage detection of an assembled battery made of a number of single batteries.
In contrast with such a charge state detector section for an assembled battery, there is provided a voltage detecting apparatus for an assembled battery having a configuration, called a flying capacitor system, such that reference electric potentials of single batteries Ba1 to Ban, are fixed to a ground potential so as not to be affected by the different reference voltages and such that the number of differential amplifier circuits COU, differential amplifier circuits COL, and voltage setting parts is reduced for judging the above-described overcharging or over-discharging (for example, refer to FIG. 1 and page 1 in Jpn. Pat. Appln. KOKAI Publication No. 2001-201522).
This flying capacitor system is featured by reducing an effect of a parasitic capacitance of a sampling switch section 22 made of a plurality of switches for changing a connection destination of a capacitor for charging each of the single batteries Ba1 to Ban and detecting a voltage of each of the single batteries with high precision.
This voltage detecting apparatus is configured as shown in FIG. 9, and comprises a sampling switch section 22 for sampling voltages of the single batteries Ba1 to Ban of an assembled battery 11 at a capacitor C; a transfer switch section 24 for transferring each of the single battery voltages charged in the capacitor C; a voltage detecting circuit 25 for detecting a charge voltage of the capacitor C; and a controller 26 for controlling a switching timing of each switch of the sampling switch section 22 and the transfer switch section 24 so as to reduce an effect of the parasitic capacitance, and then, detecting abnormal over-discharging or overcharging from an output of one voltage detecting circuit 25.
In this system, in the case of measuring a voltage of the single battery Ban of the assembled battery 11, for example, a sampling switch S22nL and a sampling switch S22nH are first closed at the same time, and the capacitor C is sampled and held or charged with the voltage of the single battery Ban.
Next, the sampling switch S22nL and the sampling switch S22nH are opened at the same time. Then, a ground potential setting switch S24L is closed. After the lower side of the capacitor C has been transferred to the ground potential, the switch S24H is closed with a slight delay. At this time, a charge voltage of the capacitor C is detected by means of the voltage detecting circuit 25, and the switch S24L and switch S24H are opened at the same time.
Then, this operation is sequentially made with respect to all of the single batteries Ban−1 to Ba1 one by one so as to detect the presence or absence of overcharging or over-discharging with respect to each of the single batteries.
However, in the case of a charge voltage detecting apparatus shown in FIG. 9, the voltages of the single batteries Ba1 to Ban are sequentially charged and detected with respect to one capacitor C. That is, the capacitor C is charged while sampling switches S221L to S22nH are sequentially switched, and a voltage of the charged capacitor C is read out, thereby obtaining the voltages of the single batteries Ba1 to Ban. However, in such a flying capacitor system, in the case where a load current of the assembled battery fluctuates while detection of charge voltages is carried out with respect to all the single batteries, there is a problem that dispersion in individual voltages cannot be precisely obtained.
That is, in the voltage detecting circuit, it is important to precisely obtain dispersion in voltages of the single batteries Ba1 to Ban. However, a sampling time is different from another one, in the case where a load current has changed, the voltages of the single batteries Ba1 to Ban having different internal resistances change, thus making it impossible to correctly obtain a difference in relative voltages of the single batteries Ba1 to Ban.

Apparatus and method for detecting voltage of assembled battery


A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.

In failure localization of semiconductor devices, bitmapping is an efficient method to isolate embedded memory defects. However, the process of enabling bitmapping is time consuming and resource consuming. Bitmapping is available on high volume products where return on investment is high. Moreover, memory failure defect localization without the use of bitmapping suffers low success rate using conventional static failure analysis approaches Electrically-enhanced laser-assisted device alteration (EeLADA) is a feasible alternative method. However, the current state-of-art in failing bit-cell isolation is inconsistent and limited to a few tens of microns which is not desirable for subsequent physical failure analysis to reveal the defect.
A need therefore exists for a system and method for improved defect localization with EeLADA for isolating bit-cell defects.


Circuits and methods for generating an oscillator output. The circuit generally includes a ring oscillator, with a series of inverters connected in series and an LC resonator tank (or a variable resistance) coupled to the input and output of the inverter series. The method generally includes the steps of applying an operating voltage to such a circuit and generating an oscillator signal. The circuits and methods may be employed as a VCO component of a phase-locked loop. The upper limit of the oscillator signal frequency may be configured by altering or controlling the variable resistance and/or one or more parameters of the LC resonator tank. The circuit design demonstrates a high tolerance to variations in circuit or circuit component values.

A ring oscillator typically comprises a number of inverters connected in series as a ring. The inherent delays within each inverter cause the ring oscillator to oscillate in proportion to the total gate delay of the inverters in the ring.
FIG. 1 shows a typical ring oscillator 100 comprising an odd number of inverters 110. A tunable current source 101 may be provided to adjust the delay within each inverter 110, generally varying the oscillation frequency. One feature inherent in ring oscillator designs is that multiple phases of oscillation may be obtained at outputs 102-104 of inverters 110. Each of the inverters in FIGS. 1 and 2 are typically formed of CMOS transistors.
Existing voltage controlled oscillators (VCOs) use a variable capacitor or a current controlled source to control, adjust or influence the delay. The delay of each inverter is generally dependent upon the control input voltage in addition to the current provided by current source 101. Existing VCOs therefore generally require exacting attention to operating conditions and/or startup circuits.
VCOs with low gain tend to be more stable than VCOs with high gain. At high gain the voltage potential of the oscillation signal may reach levels that can introduce non-linearities to one or more components of the system. High gain VCOs therefore generally must adjust for process parameters to retain a nearly linear gain slope in the frequency vs. voltage curve (MHz/V). This can be challenging to implement. Therefore it is generally desirable to limit the gain of the oscillator.
Furthermore, in phase-locked loop (PLL) applications, it is useful to limit the frequency of oscillation and to keep the circuit within the capabilities of the phase detector/phase frequency detector (PD/PFD) and the locking circuitry. Also, in some cases limiting the maximum frequency can help to prevent runaway (i.e., a condition where the loop cannot lock and the frequency continually increases until the system fails.)
Thus it is desirable to have a relatively stable voltage controlled oscillator that demonstrates a high tolerance to variable and/or varying component values (e.g., process corners), and which imposes an upper bound on the output frequency.

Circuits and methods for a ring oscillator with adjustable delay and/or resonator tank stage


The invention relates to a veneer joining machine comprising a contact pressure pad having arranged therein a counterpressure roll having an outer tube which is held relative to an inner drive shaft at a variable distance as a jacket whose surface is even with a surface of said contact pressure pad or is slightly projecting with respect thereto. This arrangement offers the advantage that the contact pressure pad sensitively responds to the surface of the adjacent veneers so as to press the same and to activate the gluing thereof for butt gluing.

1. Field of the Invention
The present invention relates to a veneer joining machine comprising transporting means supported in a machine frame, as well as a contact pressure pad which is used for butt joining end edges of adjacent veneers and is displaceably arranged in a direction perpendicular thereto and which includes heating means.
2. Description of the Prior Art
With joining machines of this type it is known that the feed rolls by which the incoming veneers are pressed into the machine and then against the rear edge of a preceding veneer sheet are rotatably supported on a lower stationary table. It is also known that a counterpressure roll, or the like, is arranged in the upper part of the machine to ensure a sufficient advance of the incoming veneer.
As for the conventional rigid supporting of the upper counterpressure roll, the inaccurate adaptation of the distance of the two opposite rolls within the thickness tolerances of the veneers is disadvantageous. As a result, the veneers are often conveyed in an incomplete and irregular way or are even damaged.


The apparatus provides a locking mechanism for an armrest of an automobile or similar motor vehicle to a structural pin or post. The mechanism includes a cap with a lateral slit into which a button and spring are assembled. The spring outwardly biases the button which is limited in its outward travel by a detent arrangement which maintains the outer portion of the button flush with the cap. In this arrangement; the spring further engages a circumferential slot on the structural pin or post thereby locking the armrest to the structural pin or post. However, in order to remove the armrest from the structural pin or post, the user pushes the button inwardly, thereby compressing the spring and moving the spring out of the circumferential notch thereby unlocking the armrest from the structural pin or post and allowing the free removal thereof.

1. Field of the Invention
The present invention relates to a locking armrest support assembly for an automobile or similar motor vehicle. More specifically, the invention relates to a locking armrest support assembly with a sleeve which sliding accommodates a rod of the armrest and a cap at the upper end thereof including a locking device which engages with notches in the rod of the armrest to lock the armrest in position. A button is provided, however, in the cap to compress the spring and to unlock the armrest easily when desired.
2. Description of the Prior Art
In the prior art, the installation and subsequent removal of an armrest in an automobile or similar motor vehicle has been a somewhat involved, time-consuming process. This is particularly true in view of the high number of automobiles or similar vehicles produced and subsequently serviced. While some solutions are available which would make the armrest simple to install and to remove, these solutions would not be satisfactory in that the armrest would not be adequately installed to the vehicle and may become unfastened at undesired times.
A locking headrest support assembly using a locking spring is disclosed in U.S. patent application Ser. No. 08/580,755, filed Dec. 29, 1995, assigned to the present assignee.


Embodiments are directed to implementing a dynamically changeable system model that is customizable per version, programmatically generating system models at runtime and to extending a programmatically generated system model. In an embodiment, a computer system determines that a dynamically changeable system model corresponds to a managed system. The dynamically changeable system model includes various managed system objects. The computer system indicates for the dynamically changeable system model which managed system objects are available in each version of the managed system. The available managed system objects are stored in a data store of the dynamically changeable system model. The computer system requests the managed system to provide current managed system information including at least a version identifier and, based on the managed system information indicated by the managed system, provides to the dynamically changeable system model those managed system objects that are provided by the indicated version of the managed system.

Computers have become highly integrated in the workforce, in the home, in mobile devices, and many other places. Computers can process massive amounts of information quickly and efficiently. Software applications designed to run on computer systems allow users to perform a wide variety of functions including business applications, schoolwork, entertainment and more. Software applications are often designed to perform specific tasks, such as word processor applications for drafting documents, or email programs for sending, receiving and organizing email.
In many cases, software applications are designed to interact with other software applications or other computer systems. For example, client computer systems may be configured to request and receive services or software applications hosted by a back-end server. In some cases, the back-end server's services may have various different service operations. These service operations are typically tied to model objects and will only work with those specific model objects. Moreover, object properties are typically converted between models each time a different back-end version is used.


In one embodiment, a system and method pertain to identifying an output signal having indeterminate timing, creating an expectation for a signal change associated with the output signal, and adding the expectation to an ordered list of expectations for the output signal. In another embodiment, a system and method pertain to detecting a signal change, identifying a vector associated with the signal in which the change occurred, examining pending expectations of the vector until a mature expectation is identified, comparing an expected value contained in the mature expectation with the detected signal change, and reporting an error if the expected value does not match the detected signal change.

Computer processor design is an extremely complex and lengthy process. The design process includes a range of tasks from high-level tasks such as specifying the architecture down to low-level tasks such as determining the physical placement of transistors on a silicon substrate. Each stage of the design process also involves extensive testing and verification of the design through that stage. One typical stage of processor design is to program the desired architecture for the processor using a register transfer language (RTL). The desired architecture is represented by an RTL specification that describes the behavior of the processor in terms of step-wise register contents. The RTL specification models what the processor does without describing the physical circuit details. Thus, the processor architecture can be verified at a high level with reference to the RTL specification, independent of implementation details such as circuit design and transistor layout. The RTL specification also facilitates later hardware design of the processor.
Manually verifying the RTL specification of the processor architecture is prohibitively complex during the design of a modern microprocessor. Therefore, multiple test cases are typically generated to test the design. Each test case contains input instructions and may also contain the desired results or outputs. Once created, the test cases may be executed on a simulation of the RTL specification (often compiled to increase speed) and the results analyzed. Through that analysis, errors in the RTL specification, and potentially the processor architecture design, may be identified.
Many processors use multiple processor cores that execute instructions during processor operation. Cores of such processors are connected by an interface, such as a point-to-point (P2P) interface or a front side bus (FSB) interface, typically on a single chip. With such a configuration, the processor may be operated in a "lockstep" mode in which two or more of the processor cores (a master core and one or more slave cores) execute the same instruction stream each clock cycle. Given that the behavior of the cores is deterministic, the same output should result from each processor core operating in lockstep mode. One advantage of operating in lockstep mode is that if one of the cores experiences an error (e.g., a manufacturing defect, a stuck-at fault, a soft error from an alpha particle, a transient electrical failure, etc.), the other core(s), at least in theory, can continue to execute so that the processor can continue to operate. Assuming that the core that experienced the error has not failed completely, the operating system may be able to resynchronize that core so as to resume normal lockstep operation.
A "lockstep block" may be provided within the verification system that logically resides between the modeled processor cores and their interfaces. In such a case, the lockstep block can monitor outputs of the cores (e.g., data and/or error signals) such that the lockstep block can identify when core errors occur. If a self-detected (i.e., core-reported) error occurs, the lockstep block can shut down the failing core to avoid the output of erroneous signals to the remainder of the verification system. If a data mismatch as between the cores occurs (i.e., core divergence), the lockstep block can signal a system-wide alert to prevent system data corruption in that it is not known which of the cores is failing and which is operating correctly.
Within the verification system, some signals output from the lockstep block propagate to chip pads (or pins). Due to the fact that such signals may traverse circuitous paths through various different clock domains, the time at which such a signal will reach the pad is indeterminate, i.e., the arrival time cannot be determined with certainty at the time the signal is output. Given that it is important that the correct signal changes occur at the chip pads, it is desirable to confirm that those changes in fact occur. Unfortunately, however, the indeterminate nature of the signal timing renders it difficult to make that confirmation.

This patent is subject to a terminal disclaimer.

Systems and methods for conducting future signal checks

Hewlett-Packard Development Company, L.P.


A lure has an opening part at a front end of a main body. A water resistance part and a connecting part are provided in the opening part. The main body is made from a pair of shell members combined together. Each shell member has a recess part for forming the opening part, an inclined face for forming the water resistance part disposed below the recess part, another recess part for forming a hollow part within the main body, a wall for dividing the opening part and the hollow part and a slotted hole which is provided at a front side of the wall and which communicates with the opening part. The slotted hole is so formed as to be located at the position of a gill in an appearance. Each shell also has the connecting part below the opening part in the main body. Accordingly, it is possible to provide a lure in which the reality of the lure to fish, a living bit or the like is improved without deteriorating an activity or moving ability of the lure.

The present invention relates to a lure employed for fishing.
Conventional lures have been generally formed by imitating fishes and other living things in their shape and color.
A lure disclosed in Japanese Examined Utility Model Publication No. 2-42131 has a shape similar to that of a fish, but its connecting part to which a fishing line is connected, its lip for applying an action to the lure or the like are provided outside the lure. Therefore, the lure fails to have actuality as a fish because of the existence of the connecting part and the lip.
Japanese Unexamined Utility Model Publication No. 54-145688, discloses another lure which has an opening part provided at an end of a main body of lure, and holes provided at both sides thereof, the holes being communicating with the opening part. However, the lure is a smell generating type lure and not one adapted to float and move in water.
U.S. Pat. Nos. 2,229,369, 2,878,611 and 4,102,075 also disclose conventional lures of the type in which the passage of water is provided in a body. However, these conventional lures also fails to have reality as of a fish or living bit.
As mentioned above, even if the conventional lure is manufactured by imitating fishes or other living things, they have no actuality or reality of the fishes, because various members to generate action of a lure are protruded outside the main body of lure. Further, in the conventional lure having the water passage, there is no particular attention to provide the lure with reality in respect of a discharge port, which is an end of the passage.


The disclosure relates to a nozzle device for emitting at least one emission medium onto a component, preferably onto a fold, an edge or a transition joint of the component. The nozzle device comprises at least two nozzle plates arranged adjoining one another, wherein a first nozzle plate comprises at least one opening for emitting at least one emission jet and a second nozzle plate comprises at least two openings for emitting at least two emission jets.

The disclosure relates to a nozzle device for emitting a, for example, viscous, in particular highly viscous, emission medium onto a component, preferably for emitting the emission medium onto a fold (e.g. a standing seam), an edge or a transition joint of the component. The component is preferably a motor vehicle component (e.g. a vehicle bodywork component), although it can also be, for example, a component of a commercial vehicle (e.g. a commercial vehicle bodywork component), a component of an aircraft, a window (e.g. a window pane) or a facade component.
With regard to the general prior art, reference is made firstly to DE 10 2013 217 686 A1.
Making reference to FIG. 14, according to the prior art, in particular, standing seams (e.g. component edges) as occur for example in the door sill region or on side rails of a motor vehicle, are sealed by way of conventional, robot-guided flat jet nozzles (also known as flat stream nozzles) made of hard metal. In this method, the standing seam is sealed from at least one side and possibly also from both sides with PVC (polyvinylchloride). So that the underside of the standing seam can be sealed reliably, a robot program is usually created so that the lower edge of the spray jet delivered from the nozzle is applied a few millimetres below the standing seam and is therefore applied past ("overshooting") the standing seam. The PVC material that is applied on one side of the standing seam becomes partially applied round the seam edge and so seals the lower corrosion-susceptible side of the standing seam.
The requirements for a conventional PVC seam are typically 15 mm to 25 mm seam width and 1.5 mm to 2.5 mm seam height. So that this can be realized with a structurally limited nozzle, the slit opening of the conventional flat jet nozzle is configured convex so that the jet width of the spray jet enlarges toward the standing seam and thus toward the emission side.
A disadvantage of the prior art described above is, in particular, that, as a result of the process, a part of the PVC material is delivered "overshot" at the standing seam. This has the result that the robot guiding the flat jet nozzle and/or the application cell in which the method is carried out is soiled and therefore a greater cleaning effort is incurred. Due to the structural tolerances that are typically present in motor vehicle bodywork, the application usually cannot be set differently. The component tolerances also have the result that application to the standing seam must be made from both sides. Joined sheet metal edges differ, for example in their length, from one bodywork to the next.
An additional disadvantage of the prior art described above is the lack of flexibility. Therefore, dependent upon different quality requirements or dependent upon different configurations of the motor vehicle component to be provided with the emission medium, different nozzles must be used. However, nozzle changing processes are time-consuming and disrupt the actual application process.

Nozzle device having at least two nozzle plates and at least three openings


Phosphonate surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirror devices. The surfactants are adsorbed from vapor or solution to form self-assembled monolayers at the device surface. The higher binding energy of the phosphonate end groups (as compared to carboxylate surfactants) improves the thermal stability of the resulting layer.

MicroElectro Mechanical Systems (MEMS) are semiconductor chips that support a top layer of small mechanical devices, such as fluid sensors or mirrors. These devices are built onto chips through growth and etching processes similar to those used to define the topography of an integrated circuit. These processes are capable of creating devices with micron dimensions. The MEMS itself typically packs multiple elements on a single chip.
A MEMS device, specifically a Digital Micromirror Device (DMD), is the basis for Digital Light Processing™ technology. The DMD microchip functions as a fast, reflective digital light switch. The switching is accomplished through the rotation of multiple small mirrors in response to an electric potential. In a mirror's "on" state of rotation, light from a projection source is directed to the pupil of a projection lens and a bright pixel appears on the projection screen. In the "off" state, light is directed out of the pupil and the pixel appears dark. Thus the DMD provides a digital basis for constructing a projected image. Digital Light Processing™ has been employed commercially in televisions, cinemagraphic projection systems, and business-related projectors.
In a typical DMD design, metal, e.g., aluminum, is deposited to form support posts, a hinge, the mirror itself, and structures (such as yokes or landing tips) to contain its rotation. The processes used to define these structures on a DMD (or any other MEMS device) are known in the art and are not the subject of this invention. These processes may include growth of a passivation layer on the mechanical device.
Passivation layers are added to address several problems with device operation. One such problem is static friction (stiction), the static adhesion force between resting bodies in contact (such as two surfaces of a DMD pixel). Another problem is dynamic friction, which arises from the contact of moving elements in the device. Effective passivation layers reduce stiction and friction by reducing the surface energy of the device. For rotating devices (such as the hinge in a DMD), repeated movement and deformation displace molecules and permanently bias the zero state of the rotation. Passivation layers may reduce this hinge memory accumulation by stabilizing certain states of the surface.
Passivation layers are typically formed from surfactants. Effective surfactants are believed to function by forming self-assembled monolayers at the device surface. These monolayers are ordered molecular assemblies formed by the adsorption of a surfactant on a solid surface. Zhu, et. al., "Self-Assembled Monolayer used in Micro-motors," report the use of such monolayers, formed from an octadecyltrichlorosilane precursor, as a passivation layer for a silicon micromotor. Hornbeck, "Low Surface Energy Passivation Layer for Micromechanical Devices" (U.S. Pat. No. 5,602,671) has described the use of self-assembled monolayers as passivation for MEMS devices including DMDs. Suitable self-assembling carboxylates may be introduced as a vapor under conditions designed to facilitate the growth of self-assembled monolayers, as disclosed by Robbins, "Surface Treatment Material Deposition and Recapture," (U.S. Pat. No. 6,365,229).
Self-assembled monolayers have been studied outside the device context. Much of the early research in this field concerned the interaction of surfactants with gold surfaces; but work has been published relating to other metals (and metalloids), including silicon and aluminum. Work pertaining to phosphonate/phosphonic acid surfactants includes: Gawalt, et. al, "Self-Assembly and Bonding of Alkanephosphonic Acids on the Native Oxide Surface of Titanium," Langmuir 2001, 17, 5736-38; Hanson, et. al, "Bonding Self-Assembled, Compact Organophosphonate Monolayers to the Native oxide Surface of Silicon," J. Am. Chem. Soc. 2003, 125, 16074-80; and Nitowski, G., "Topographic and Surface Chemical Aspects of the Adhesion of Structural Epoxy Resins to Phosphorus Oxo Acid Treated Aluminum Adherents."
Within the device context, the passivation layer should be stable under the intended operating conditions of the MEMS. While carboxylate surfactants have functioned adequately in commercial DMD products, the resulting monolayers may thermally desorb under foreseeable conditions of operation. Such desorption, and the resulting increase in stiction, friction, and hinge memory accumulation, would adversely impact the operation of the device. It is therefore desirable to form passivation layers from surfactants that bind more tightly with the surface of interest. That is one objective of the present invention. In addition, because of their reduced acidity (as compared to some commonly employed carboxylates), phosphonic acid surfactants may provide compatibility advantages with common packaging materials, such as Kovar.

MEMS passivation with phosphonate surfactants


An efficient and highly scalable method of sorting an input file in a processing system by using only a limited amount (i.e., a portion) of memory in the processing system, where that amount of memory is substantially smaller than the input file, is disclosed. The input file can be, for example, a fingerprint database for use in deduplication, and the processing system can be, for example, a network storage server. The merge phase is broken down into sub-phases, where each sub-phase takes a predetermined number of subsets of a fingerprint file to merge and writes them back as a sorted, merged group. The number of threads used to process these groups can depend on the number of central processing units (CPUs) present in the system and can be dynamically tuned to achieve desired level of performance.

Network storage is a common approach for making large amounts of data accessible to many users and/or for backing up data. In a network storage environment, a storage server makes data available to client systems by presenting or exporting to the clients one or more logical containers of data. There are various known forms of network storage, including network attached storage (NAS) and storage area networks (SANs). In a NAS context, a storage server services file-level requests from clients, whereas in a SAN context a storage server services block-level requests. Some storage servers are capable of servicing both file-level requests and block-level requests.
In a large-scale storage system, such as an enterprise storage network, it is common for some data to be duplicated and stored in multiple places in the system. Sometimes data duplication is intentional and desirable, as in the case of data mirroring, for example. Often, however, data duplication is an incidental byproduct of normal operation of the storage system. For example, a given sequence of data may be part of two or more different files, LUNS, etc. Consequently, it is frequently the case that two or more segments of data stored at different locations in a storage server are identical. Unintentional data duplication generally is not desirable because storage of the same data in multiple places consumes additional storage space, which is a limited resource.
Consequently, in many large-scale storage systems, storage servers have the ability to "deduplicate" data. Deduplication is a well-known method for increasing the capacity of a storage device or system by replacing multiple copies of identical sequences of data with a single copy, together with a much smaller amount of metadata that allows the reconstruction on demand of the original duplicate data. Techniques for deduplicating data within a network storage server are known and in commercial use today.
Deduplication tends to be a very resource-intensive process, especially when the amount of data to be deduplicated is large. To understand why this is so, first consider how deduplication is commonly performed. Initially, duplicate data segments are identified; this phase is called duplicate detection. A conventional method involves using a hash function, such as SHA-1, to compute an integer, called a "fingerprint", from each data segment, such that different data segments are extremely unlikely to produce the same fingerprint. The fingerprints are stored in one or more fingerprint files, e.g., one fingerprint file for each data volume maintained by the system.
The stored fingerprints are subsequently used to detect potential duplicate data segments. Duplicate detection may be done, for example, when a new data segment is about to be written, or it may be done as a background process. If two data segments have the same fingerprint, there is a high probability they are identical. Accordingly, when two data fingerprints are determined to be identical, the underlying data segments are compared byte by byte to determine if they are in fact identical. If the data segments are identical, deduplication is performed on them.
When the amount of data maintained by the storage system is large, such as in an enterprise-scale network storage system, even the fingerprint files can become extremely large, e.g., potentially hundreds of gigabytes each. Consequently, locating fingerprints in these files for purposes of duplicate detection and removal would be very inefficient and take a long time unless the fingerprint files are first sorted. With current techniques, however, the sorting process itself is extremely memory-intensive; yet often only a small portion of working memory of the system is made available for deduplication, since it is usually desirable to keep most space in memory available for servicing user requests. Also, a fingerprint file is typically much larger than the amount of available working memory in the system. Consequently, each fingerprint file is broken up into smaller chunks that are sorted separately, one at a time, and then merged back together. This process can take an inordinately long time, especially if there are multiple fingerprint files to be sorted; with conventional techniques the sorting process alone can take hours for an enterprise-scale storage system. The overall performance of the deduplication process therefore drops drastically as the amount of data to be deduplicated (and hence the size and number of fingerprint files) increases.
As a result, in conventional network storage systems the fingerprint sorting process (and therefore the overall deduplication process) is not very scalable relative to the amount of data maintained by the storage system. This problem hinders the goal of supporting customers' demands for storage servers that can handle and efficiently deduplicate data sets of ever-increasing sizes.

Sorting a data set by using a limited amount of memory in a processing system


Disclosed are techniques for the automated discovery and extraction of discourse phrases, or in other words terms that representative of a topic or concept communicated via a plurality of electronic documents, to facilitate the generation of a language model that is applicable to interpreting commands for invoking application-based actions via a digital assistant device. An electronic document corpus can be generated having a plurality of electronic documents that are clustered based on entropy, among other things. The clusters can be associated with a corresponding plurality of cluster attractors that are generally representative of a context of the documents included therein. The clusters can be grouped based on determined relationships, such that the groups can be further analyzed and terms or phrases representative of a discourse associated with the grouped documents can be determined. The various groups and clusters of documents can be saved and indexed, among other things, to facilitate more efficient searching of the electronic document corpus to interpret received inputs, such as commands received via a digital assistant device.

Digital assistants have become ubiquitous in a variety of consumer electronic devices. Modern day digital assistants employ speech recognition technologies to provide a conversational interface between users and electronic devices. These digital assistants can employ various algorithms, such as natural language processing, to improve the interpretation of commands (e.g., requests for specific actions to be performed and/or for specific information to be provided) received from a user. Consumers have expressed various frustrations with conventional digital assistants due to, for instance, frequent misinterpretations of spoken commands, unavailability of services due to weak signals or a lack of signal, privacy concerns, and the general requirement that the consumer must structure their spoken commands in a language and/or parlance that is uncomfortable or unnatural for them. Further, the actions resulting from these commands in existing digital assistants typically do not execute within applications selectively installed on users' mobile devices, which often is what users would like, particularly when they are on the move.
Moreover, as the general pace of society continues to accelerate, so do users' desires to consume readily-available information. Digital assistants can enable a seamless interface between users and their devices, and can provide a much faster means for the exchange of input and output information. One digital assistant, particularly the "Q" digital assistant developed by Aiqudo Inc., headquartered in San Jose, Calif., provides such a seamless interface. In other words, the "Q" digital assistant can, among many other things, perform a series of custom or predefined tasks (e.g., each series of tasks or computer operations representing an "action") based on a received command to accomplish a desired result.

Automated discourse phrase discovery for generating an improved language model of a digital assistant


A method for providing actuation thrust to a projectile. The method including: providing two or more individual actuators movably disposed in a stack housing, each of the two or more individual actuators being separated by a separation layer; accelerating exhaust from the two or more individual actuators with an accelerating nozzle having at least a convergent section terminating at a throat; and maintaining a constant volume in the accelerating nozzle after actuation of each of the two or more individual actuators.

1. Field of the Invention
The present invention relates generally to actuators, and more particularly to actuators for gun-fired projectiles and mortars.
2. Prior Art
Since the introduction of 155 mm guided artillery projectiles in the 1980's, numerous methods and devices have been developed for the guidance and control of subsonic and supersonic gun launched projectiles. The majority of these devices have been developed based on missile and aircraft technologies, which are in many cases difficult or impractical to implement on gun-fired projectiles and mortars. This is particularly true in the case of actuation devices, where electric motors of various designs have dominated the guidance and control of most guided weaponry.
In almost all guided weaponry, such as rockets, actuation devices and batteries used to power the same, occupy a considerable amount of the weaponry's internal volume. In recent years, alternative methods of actuation for flight trajectory correction have been explored, some using smart (active) materials such as piezoelectric ceramics, active polymers, electrostrictive materials, magnetostrictive materials or shape memory alloys, and others using various devices developed based on microelectromechanical (MEMS) and fluidics technologies.
In general, the available smart (active) materials such as piezoelectric ceramics, electrostrictive materials and magnetostrictive materials need to increase their strain capability by at least an order of magnitude in order to become potential candidates for actuator applications for guidance and control, particularly for gun-fired munitions and mortars. In addition, even if the strain rate problems of currently available active materials are solved, their application to gun-fired projectiles and mortars will be very limited due to their very high electrical energy requirements and the volume of the required electrical and electronics gear. Shape memory alloys have good strain characteristics but their dynamic response characteristics (bandwidth) and constitutive behaviour need significant improvement before becoming a viable candidate for actuation devices in general and for munitions in particular.
The currently available and the recently developed novel methods and devices or those known to be under development for guidance and control of airborne vehicles such as missiles, have not been shown to be suitable for gun-fired projectiles and mortars. In fact, none have not been successfully demonstrated for gun-fired guided munitions, including gun-fired and mortar rounds. This has generally been the case since almost all the available guidance and control devices and methodologies suffer from one or more of the following major shortcomings for application in gun-fired projectiles and mortars:
1. A limited control authority and dynamic response characteristics considering the dynamics characteristics of gun-fired projectiles and mortars.
2. Reliance on battery-based power for actuation in most available technologies.
3. The relatively large volume requirement for the actuators, batteries and their power electronics.
4. Survivability of many of the existing devices at high-g firing accelerations and reliability of operation post firing.
5. Expensive and complicated.
A need therefore exists for actuation technologies that address these restrictions in a manner that leaves sufficient volume onboard munitions for sensors, guidance and control and communications electronics and fuzing as well as the explosive payload to satisfy lethality requirements.
Such actuation devices must consider the relatively short flight duration for many of the gun-fired projectiles and mortar rounds, which leaves a very short time period within which trajectory correction has to be executed. Such actuation devices must also consider problems related to hardening components for survivability at high firing accelerations and the harsh environment of firing. Reliability is also of much concern since the rounds need to have a shelf life of up to 20 years and could generally be stored at temperatures in the range of −65 to 165 degrees F.
In addition, for years, munitions developers have struggled with placement of components, such as sensors, processors, actuation devices, communications elements and the like within a munitions housing and providing physical interconnections between these components. This task has become even more prohibitive considering the current requirements of making gun-fired munitions and mortars smarter and capable of being guided to their stationary and moving targets, therefore requiring high power consuming and relatively large electrical motors and batteries. It is, therefore, important for all guidance and control actuation devices, their electronics and power sources not to significantly add to the existing problems of integration into the limited projectile volume.

Actuators for gun-fired projectiles and mortars


A tow cable mounting structure for an agricultural tractor that includes a pin-connection feature for a tow cable so that an easily accessible tow connection anchored to the tractor frame can be provided on the tractor. The mounting structure includes a contoured end portion and a bracing structure to manage stress distribution in the mounting structure and the tractor chassis thereby enabling the attachment mount to be added to a tractor with minimal alteration of the chassis.

The present invention relates to a tow hook for a tractor and, more particularly to an attachment mount for a tow cable used on, but not limited to, an agricultural tractor.
Tow cables are often offered on tractors used in applications where the likelihood of becoming stuck is great. One typical application is the use of four-wheel drive (4WD) agricultural tractors to pull earth scraper pans. Extracting a stuck tractor and scraper pan subjects the tractor to large pulling forces as sometimes multiple tractors are used to extricate the stuck tractor and its connected implement. For convenience, many tractors of this type incorporate a length of tow cable which provides a convenient connection point on the stuck tractor. Such tow cables are anchored to a structurally robust portion of the tractor, generally on inaccessible lower portions of the tractor frame, and provide an easily accessible tow connection point near the front of the tractor. Due to the magnitude of the pulling forces required, a suitable attachment mount for the towing cable must be provided that is capable of withstanding the large forces and that transfers the pulling forces into a suitable frame structure on the tractor.
Ideally, a tow cable attachment point is provided proximate to the forward end of the drawbar so that pulling forces are generally directed through the portion of the tractor frame designed specifically for pulling loads. In this manner, pulling forces from the second tractor are directed to the drawbar of the first tractor which avoids using other portions of the tractor frame to transfer these forces. The STX and TJ series four-wheel drive tractors manufactured by Case New Holland are typical examples of tractors including this feature. Changes in the design of the drawbars used on the Case New Holland STX and TJ series tractors have rendered the previous tow cable attachment point unsuitable. Additionally, earlier tow cable attachment point designs connected directly to the drawbar subjected the drawbar attachment pin to reverse bending stresses which increases the likelihood of failure of the attachment pin.
In today's competitive market, functional performance using designs that are simple in construction is paramount. It would, therefore, be a great advantage to provide an improved attachment mount for a tractor tow cable that is durable when subjected to the towing forces, offers a generally direct load path between towing tractors and the draft load line of the stuck tractor implement combination, and relies on, to the extent practicable, existing structural framework on the tractor to overcome the above problems and disadvantages. Still more advantages would be realized if the attachment mount required no chassis design alterations and little or no modification of the tractor chassis.

Attachment mount for a tow cable on an agricultural tractor