Polyhydroxyalkanoate compositions including hot melt adhesive compositions, biodegradable wax compositions, and protective coating compositions are provided and include a low molecular weight polyhydroxyalkanoate, a terminally-modified polyhydroxyalkanoate, or both. The compositions are biodegradable and environmentally friendly. Methods of protecting an article, such as a food product like cheese, are also provided and include coating or encapsulating the article with a composition containing a low molecular weight polyhydroxyalkanoate, a terminally-modified polyhydroxyalkanoate, or both.

The present invention relates to hot melt adhesive compositions, wax compositions, and coating compositions, and methods of using the same.
With a view to the environment, a serious need has arisen for biologically degradable products. Various plastic and wax materials, such as hot melt adhesives and protective coatings, are so often used and in such great volume that these products have a significant impact on the environment. A need exists for biodegradable hot melt adhesive and protective coating materials.
Hot melt adhesives are used in a great number of applications and are particularly employed in packaging materials for all sorts of goods. Unfortunately, most conventional hot melt adhesives are non-biodegradable, thus adversely affecting the environment. Those products that claim to be biodegradable are typically based on water sensitive polymers or additives and hence the degradation process is through dissolution rather than biodegradation. A need exists for a biodegradable hydrophobic hot melt adhesive composition that will provide sufficient adhesion for its intended use yet degrade years later and, thus, be environmentally friendly.
Many non-stable products, particularly food products such as cheese, are coated with a synthetic, non-biologically degradable plastic rind to improve product maturation and shelf-life. The plastic of such a rind cannot be recovered or recycled and thus presents a problem for the environment. Furthermore, such a coating must fulfill a large number of functions and a large number of requirements. The coating material must serve to prevent mechanical damage and attack by molds. The coating must offer both mechanical and hygienic protection, and it must be easy to apply, for example, by an immersion coating technique or by coating with a sponge or brush.
Cheese coatings should advantageously affect the luster and rind formation and must adhere well to the wet surface of the cheese. In addition, after drying, the coating must not crack or stick, for example, to cutting boards or other cheeses. The coating should also be semi-impermeable since CO2 and certain flavoring components must be able to diffuse through the coating in order not to adversely affect maturing of the cheese. Water vapor must also be allowed to pass through in a controlled manner so that natural maturing can occur without any question of excessive weight loss. Also, components must not diffuse into the cheese from the coating. Furthermore, the coating must keep well during prolonged storage. Any paraffinic wax layer that is subsequently applied to the latex coating must not peel off after vacuum packaging. In addition, machines used to apply the coating must be easy to clean.
Although biologically degradable and compostable coatings exist, they are generally water-soluble polymers which are consequently water-sensitive. Examples of these are polyvinyl alcohol, polyethylene oxide, and also proteins such as gelatin, casein, and the like. In the past, it has not been possible to use polyhydroxyalkanoate films as coatings in the foodstuffs industry because of the use of organic solvents and because of the need to heat the polyhydroxyalkanoates to the melting point thereof, which could unnecessarily damage the product. A need exists for a polyhydroxyalkanoate protective coating, layer or film that can be used as a protective coating for articles such as food products, in particular, cheese products, and that can be processed at relatively low temperatures and does not require the use of non-consumable organic solvents.
Surface active agents and solvents are also commonly used in a vast variety of industrial products and processes. Because of the large volume of surface active agents and solvents used worldwide in the many industrial product and process applications, a need exists for a new class of surface active agents and a new class of solvents that are biodegradable. Current biodegradable surfactant systems either do not meet required technical specifications or have a significant price disadvantage that make them uncompetitive with synthetic based systems.

Compositions comprising low molecular weight polyhydroxyalkanoates and methods employing same


An input is disclosed that includes a zoom apparatus for increasing or decreasing the size of an image rendered on a display screen. The zoom apparatus has an actuator that is movable in a first direction to induce the image to zoom in. The actuator is also movable in a second direction to induce the image to zoom out. The zoom apparatus may include a sensor for detecting movement of the actuator in the first direction and movement of the actuator in the second direction. The input device may be a keyboard, for example, that includes a plurality of keys for inputting alphanumeric data, with the sensor also detecting actuation of the keys.

1. Field of the Invention
The present invention relates to input devices for computer operating environments. The invention concerns, more particularly, an input device that incorporates a zoom apparatus for increasing or decreasing the size of an image rendered on a display screen. Concepts related to the input device and zoom apparatus have application to a variety of input devices, including a keyboard.
2. Description of Background Art
A variety of data entry techniques have been developed to enhance usability and to make computers more versatile throughout the evolution of the field of computer science. For example, a typical computer system, especially a computer system using graphical user interfaces for user interaction, may be optimized for accepting input from one or more discrete input devices. Thus, an individual may enter text with a keyboard, and control the position of a pointer image on a display screen with a pointing device, such as a mouse, having one or more buttons for activating selections associated with the location of the pointer. Some computing systems even include a pen-like stylus.
The viewable contents of a computer file, such as a text document, spreadsheet, digital photograph, Web page, or other image rendered on a conventional display screen, may possess a size exceeding the viewable boundaries of the display screen. In other words, the display screen may only render a portion of the viewable contents of the computer file. Similarly, the viewable contents of a computer file may be rendered at a resolution that is less than the resolution of the computer file, thereby limiting the degree to which an individual may view details of the computer file. To address this issue, many operating systems or other software applications permit individuals to selectively modify the relative size of the viewable contents of the computer file, as rendered on the display screen. That is, many conventional computer operating environments incorporate a zoom feature that resizes the viewable contents of the computer file that are rendered on the display screen.
As utilized in the present document, the term "zoom" is intended to denote a change in the scale (i.e., relative size) at which the viewable contents of the computer file are rendered on the display screen. Accordingly, the zoom feature of conventional computer operating environments permits an individual to selectively modify the relative size of the viewable contents of the computer file. For example, the individual may "zoom in" on the viewable contents of the computer file in order to increase the relative size of the rendered image. Given the size constraints of the display screen, zooming in may decrease the percentage of the viewable contents of the computer file that are rendered on the display screen. Similarly, the individual may "zoom out" on the viewable contents in order to decrease the relative size of the rendered image. Based upon the resolution constraints of the display screen, zooming out may decrease the resolution of the viewable contents of the computer file that are rendered on the display screen, thereby limiting detail in the rendered image.
One conventional manner of incorporating a zoom feature into a conventional computer operating environment involves the use of a pointing device, such as a mouse, to navigate through menus that are rendered on the display screen. In many circumstances, multiple movements of the pointing device and actuations of buttons for activating selections associated with zooming are required in order to utilize the zoom feature. Accordingly, the various steps necessary for utilizing conventional zoom features may be relatively inefficient.


An integrated circuit memory system having memory cells capable of storing multiple bits per memory cell is described. The memory system has a restoring operation in which a memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge within the predetermined levels. The memory system also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erased memory cells for increasing the spread, and safety margins, between the predetermined levels.

Semiconductor memory integrated circuits, such as EEPROM, EPROM, FLASH and DRAM, have traditionally been used to store a single digital bit per memory cell, which is termed hereafter as single bit storage. Memories capable of storing more than one bit of digital data per memory cell and their benefits have been described previously. Such multiple bit per cell memories are called multilevel memories because they require more than the conventional two (conducting vs. non-conducting) cell threshold voltage, V.sub.T, levels that are used for single bit storage techniques.
Each level in a multilevel memory cell represents a specific range of electrical charge stored in each memory cell and, in the case of nonvolatile memories, i.e., EEPROM, EPROM, and FLASH memories, represents a specific range of cell V.sub.T values. To store N bits per memory cell requires the cell's V.sub.T range, and the amount of stored charge, to be divided into 2.sup.N levels. Each level corresponds to a unique binary data pattern for all N bits. The cell is erased or programmed to store charge such that the cell's V.sub.T is set within one of these 2.sup.N levels. Sensing circuits determine which level the storage cell's V.sub.T is in and read out the corresponding binary data pattern stored for the N bits. Digital information can thus be stored at a significantly lower cost per bit since N times the number of bits can be stored in the same memory cell array area previously storing just a single bit per cell.
In the following description for nonvolatile memory, a "level" is referred to as a range of V.sub.T values and not as a single voltage value. Furthermore, the term, cell V.sub.T, is not used in the strictest sense defined by solid state device physics, but rather in terms of how the sensing circuits determine the conductivity state of the memory cell. The conductivity is related to the V.sub.T of the cell. Similarly, a DRAM level represents a range of stored charge and not a single charge value.
The operation of sensing individual levels is performed by comparing the conductivity (or stored charge) of the memory cell in terms of sensing voltage or current with respect to multiple reference voltages or currents. The present invention is described in terms of voltage sensing since currents can easily be converted to voltages via load circuits by those practiced in the art of sensing schemes.
There are many problems associated with multilevel memories. Typically 2.sup.N -1 or 2.sup.N reference voltage values, V.sub.RI, where I=1, 2, . . . , 2.sup.N -1, or 2.sup.N, have been proposed to store N bits per memory cell to separate the 2.sup.N levels from each another, with V.sub.R1 <V.sub.R2 < . . . <V.sub.R(2.sup.N.sub.). It should be noted that a V.sub.RI is sometimes referred to as simply V.sub.R for brevity. The relationship between reference voltage values and cell V.sub.T are illustrated in FIGS. 1A-1C, which show the multilevel sensing reference voltages and cell V.sub.T distributions for a whole memory chip for single, two, and four bits stored per cell respectively.
An undesirable condition occurs when a memory cell V.sub.T is close to one of the V.sub.R voltages. The determination of the cell V.sub.T becomes ambiguous. Practical sensing circuits that determine cell V.sub.T are limited by circuit stability and speed, and by voltage and current variations caused by digital switching noise and other variations in power supply voltage, temperature, and silicon processing. Unlike analog signal storage, which does not require discrete multiple levels nor multiple reference voltages, digital memory storage techniques require the level to be unambiguously determined and requires such discrete reference voltages. If the level in a cell is incorrectly sensed, the digital memory malfunctions and up to N bits per cell may be lost.
To avoid the problems of sensing cell V.sub.T values close to, or equal to, one of the V.sub.R voltages, a margin voltage range, V.sub.MPI (see FIG. 2), to separate the cell's V.sub.T in one level from other adjacent levels has been proposed. This separation is performed at the time the cell is erased and programmed. However, both ends of each V.sub.MPI range are not defined. Rather, this proposed technique uses statistical control over the silicon process in conjunction with a lengthy programming algorithm to create adequate V.sub.MPI for storing a single bit, and possibly two bits, per cell. Additionally, no mechanism exists to determine if a cell V.sub.T overshoots the desired range. However, the technique is reliable only when two conditions are met. First, the separation between V.sub.R values must be large enough to provide adequate margin for unambiguous sensing. Secondly, the cell's V.sub.T must remain stable within the desired level and for as long as the data is to remain valid. This period may be as long as the lifetime of the memory chip.
However, a problem all multilevel storage techniques must overcome is the control of the V.sub.T of the memory cell within a very narrow range for each level. This V.sub.T control problem applies to all operational modes of the memory, including programming, erasing and reading the memory cells. The severity of the V.sub.T control problem increases geometrically as the number of bits stored per memory cell increases since 2.sup.N levels per cell are required to store N bits per cell. The range of V.sub.T values within a single level, V.sub.L, and the margin range separating the cell V.sub.T in different levels, V.sub.M (see FIGS. 3A-C), narrows as the number of levels increase within a fixed range of all useful cell V.sub.T values, V.sub.F. In this invention we sometimes refer to a V.sub.LI (where I is one of the 2.sup.N levels) as simply V.sub.L, for brevity's sake.
V.sub.F is usually fixed since it is limited by the voltage range that can be applied to the terminals of the memory cell during the program, erase, and sensing operations. V.sub.F is constrained by circuit speed, complexity and data storage reliability. For many previously proposed nonvolatile memory technologies, V.sub.F is roughly equal to the power supply voltage for read operation, V.sub.CC.
For the extremely simple case where the V.sub.L range for all levels are defined to be the same and there is zero margin between levels, V.sub.L =V.sub.F /2.sup.N. For example, the V.sub.L range for a single bit storage technique operating from a 5 volt V.sub.CC is 5/2=2.5V, while the V.sub.L range for a 4-bit per cell multilevel memory operating from 3V reduces to 3/16=187.5 mV. If a margin voltage range, V.sub.M, is added between each level, V.sub.F =V.sub.L1 +V.sub.M1 +V.sub.L2 +V.sub.M2 + . . . +V.sub.M(2.sup.N.sub.-1) +V.sub.L(2.sup.N.sub.). Continuing with the previous simple case and assuming all V.sub.M ranges are also equal, the level range now reduces to V.sub.L =V.sub.F -(2.sup.N -1).times.V.sub.M !/2.sup.N. With the introduction of a V.sub.M equal to 0.1V, the V.sub.L in the previous 4-bit, 3-volt V.sub.CC example is now reduced to 3-(15.times.0.1)!/16=93.8 mV.
Adding to the V.sub.T control problem is the procedure for erasing memory cells. In practical embodiments of memory arrays, the erasure of cells is accomplished in blocks containing many cells so the V.sub.T distribution of the fully erased cells is wider than the other levels that are programmed more selectively. The wider V.sub.L level used to define the fully erased cells, V.sub.LERASE, reduces the V.sub.L range for the programmed levels even further. FIGS. 3A through 3C graphically illustrate this problem for the same technologies shown in FIGS. 1A-1C.
It should be noted that FIGS. 1A, 1B, 1C, 2, 3A, 3B, and 3C are examples of technologies where programming increases the cell V.sub.T. The previous statements apply analogously for technologies that decrease the cell V.sub.T during programming. In this case these drawings would show the wider erased level at the high end of cell V.sub.T, instead of the low end.
Thus, V.sub.T control is much more important in multilevel than in single bit storage systems since the range of V.sub.T in each level is geometrically reduced as the number of bits per cell increases.
Furthermore, there are various mechanisms which can cause the cell's V.sub.T to drift away from its initially programmed value. Many of these mechanisms are caused by the application of voltage stresses to the cell subsequent to its original programming. These conditions are called "disturbs" and are unavoidable when the cell is grouped within an array of other similar cells to make a useful memory system. Program and erase disturbs are present for the shortest cumulative time but are important causes of V.sub.T drift due to the high voltages used during these operations. For example, disturb data is routinely reported in the technical literature describing new FLASH memory technology.
Other sources of V.sub.T drift are due to the effects of changes in the numbers or positions of trapped charges around the floating gate or between the floating gate and substrate of the memory cell. Trapped charges may be due to defects or the cumulative effects of high electric fields applied over time, such as during repeated program/erase (P/E) cycles. The more erase or programming currents are driven through a gate dielectric, the more trapped charges accumulate. This leads eventually to the retardation of those operations and a malfunction of the part.
Trapped charge may also occur in an unrepeatable fashion with P/E cycling. This has been attributed to the so called "rogue bit" effect. A rogue bit exhibits a shift in programming or erase ability on one cycle and reverts back to normal on another cycle. The rate of V.sub.T drift may not be constant over time and may not be the same from cell to cell due to the statistical variations of the defects present. Each cell in a memory cell array experiences its own unique combination of disturb and charge stress conditions since different rows and columns, within which the cells are interconnected, are accessed in various orders. The drift effects caused by random voltage stresses are added to the drift effects caused by the random defects. These effects are cumulative on the cell's V.sub.T drift.
Nonvolatile cells eventually loose endurance with repeated P/E cycles, that is, they program or erase too slowly for the time allowed for these operations and eventually fail. Some previous programming techniques count the number of times a particular section of memory cell array has been cycled. Such cycling data is then used, in one example, to prevent further P/E cycling of that overused section of memory cell array based on a predetermined conservative maximum number of cycles. This programming technique may thus act to reduce the functionality of the memory before being necessary.
Finally, all the V.sub.T disturb and drift mechanism problems described above worsen due to the increasing electric fields in the cell as the physical sizes of memory cells are reduced. These problems are known impediments to the scaling of cells and barriers to more economical memory chips. Cell V.sub.T drift problems become even more severe as the V.sub.L range is narrowed when storing multiple bits per cell or lower power supply voltages are used, for example.
The present invention solves or substantially mitigates these problems. A memory according to the present invention directly measures the stability, programmability, and erasability of each nonvolatile memory cell over the life of the part.

Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell


A switched mode power supply includes a communication interface and an address terminal for setting a communication address for the power supply using the resistance of an external resistor when the external resistor is coupled to the address terminal. The power supply is configured to determine a first resistance value for the external resistor using a first technique, determine a second resistance value for the external resistor using a second technique, set the communication address of the power supply using the first resistance value if the first resistance value is greater than a threshold value, and set the communication address of the power supply using the second resistance value if the first resistance value is less than the threshold value. Other example switched mode power supplies, power systems including one or more power supplies, and methods for setting a communication address of a power supply are also disclosed.

This section provides background information related to the present disclosure which is not necessarily prior art.
Some power supply modules include unique communication addresses for communicating with an external controller. This may allow each power supply module to communicate (e.g., via a Power Management Bus (PMBus) protocol, etc.) with the external controller and other power supply modules. Each power supply module may use a resistor and a particular address-setting technique to set its unique communication address. The address-setting technique may be a constant current technique in which the power supply module calculates the value of the resistor based on a constant current provided to the resistor and sets the communication address based on the calculated resistor value. Alternatively, the address-setting technique may be a voltage divider technique in which the power supply module calculates the value of the resistor using a voltage divider circuit and sets the communication address based on the calculated resistor value.

Switched mode power supplies with configurable communication addresses


An AC voltage detecting circuit comprises: a first capacitor including a first electrode configured to connect to one end of an AC power supply, and a second electrode; a second capacitor including a first electrode configured to connect to the other end of the AC power supply, and a second electrode; a current-to-voltage converting circuit, which is connected in series between the second electrode of the first capacitor and the second electrode of the second capacitor, and which is connected to a reference potential, wherein the current-to-voltage converting circuit causes the AC current to pass through the current-to-voltage converting circuit when the AC current returns to the AC power supply, and converts an AC current output from the AC power supply into an detection AC voltage; and a voltage detecting unit, which detects an AC input voltage of the AC power supply, based on the detection AC voltage.

As a technology for detecting an AC input voltage, there has been known a technology a technology for detecting an AC input voltage using a photocoupler, for example.
However, in a method of detecting an AC input voltage using a photocoupler, it is possible to appropriately detect an AC input voltage, but the power consumption of a light emitting diode of the photocoupler is not negligible. Accordingly, a technology for detecting an AC input voltage that can save electric power has been eagerly desired.

AC voltage detecting circuit and image forming apparatus having the same


The present disclosure describes micromechanical devices and methods for using such devices for characterizing a material's strength. The micromechanical devices include an anchor pad, a top shuttle platform, a nanoindenter in movable contact with the top shuttle platform and at least two sample stage shuttles. The nanoindenter applies a compression force to the top shuttle platform, and the at least two sample stage shuttles move apart in response to the compression force. Each of the at least two sample stage shuttles is connected to the top shuttle platform and to the anchor pad by at least one inclined beam. Methods for using the devices include connecting a sample between the at least two sample stage shuttles and applying a compression force to the top shuttle platform. Application of the compression force to the top shuttle platform results in a tensile force being applied to the sample. Measuring a tip displacement of the nanoindenter is correlated with the sample's strength. Illustrative materials that can be studied using the micromechanical devices include, for example, nanotubes, nanowires, nanorings, nanocomposites and protein fibrils.

The mechanical and electrical properties of nanomaterials such as, for example, nanotubes, nanowires and nanorings, have led to intense interest in these materials. Potential applications for these nanomaterials include miniaturized electronic, optical, thermal and electromechanical systems. Many of these nanomaterial applications further rely upon the superior strength of the nanomaterials. Deformation and failure of nanomaterials under mechanical load is of particular importance in structural applications such as, for example, composite systems and load carrying components in electromechanical systems. Therefore, a thorough understanding of the mechanical properties of individual nanomaterials is desirable, since there may be property differences observed for individual nanomaterials compared those observed in a bulk sample.
Many methods for mechanical characterization of individual nanomaterials are presently known in the art. The majority of these techniques employ electro-mechanical or thermo-mechanical coupling. Testing methods for real-time observation of individual nanomaterials under stress include, for example, resonance-based methods, microelectromechanical systems (MEMS)-based tensile testing using electrostatically- and thermally-actuated platforms, atomic force microscope (AFM)-assisted bending, and compression and tension tests. A number of the aforementioned techniques are either indirect (e.g., resonance based testing) or direct but qualitative (e.g., AFM-assisted bending). Furthermore, a significant drawback of known direct measurement techniques is that sample load and deformation cannot be simultaneously and independently measured in a quantitative manner. Electrostatically- and thermally-actuated platforms have been able to overcome some of the aforementioned limitations, but their implementation is both expensive and challenging.
In view of the foregoing, new devices and methods for direct measurement of the mechanical properties of nanomaterials would be of considerable benefit in the art. In particular, such new devices and methods would desirably incorporate capabilities for simultaneous observation and mechanical testing of the nanomaterials under load.

Micromechanical devices for materials characterization


The thin film transistor is fabricated by etching a semiconductor layer, n.sup.+ semiconductor layer, etch stopper layer, and metal layer with single etching process to decrease the number of masks. By controlling the thickness of the semiconductor layer or the etching selection ratio of the etch stopper layer, an etch stopper thin film transistor or back channel etched thin film transistor can be fabricated.

The present invention relates to liquid crystal display devices, and more particularly to a simplified method for fabricating liquid crystal displays in which an organic or inorganic insulating layer can be applied as a passivation layer according to the thickness of a semiconductor layer or etching selection ratio of the etch stopper layer.
An important display device, the cathode ray tube(CRT) display device has a large screen area. However, since the screen on which the luminescence material is coated must be separated from the electron gun a distance greater than that prescribed for the large screen area, a CRT display device has a large volume. Therefore, CRT devices cannot be used in a low power consumption portable television, small notebook computers or the like.
Among the various flat panel display devices characterized by low power consumption and small size, such as LCD(liquid crystal display), PDP(plasma display panel), VFD(vacuum florescent display), and ELD(electromagnetic display), the LCD has emerged because of its capability for high resolution.
FIG. 1 is a partial plan view of an AMLCD. This LCD is a TFT(thin film transistor) LCD. In this figure, a plurality of pixels are formed in a matrix shape by a plurality of gate bus lines 1 and data bus lines 7 which extend in the horizontal and vertical directions. For explanatory purposes, only one pixel is described. In the pixel, pixel electrode 9 is formed and TFT 2 is formed at the intersection of gate bus line 1 and data bus line 7. A gate electrode 11 and source/drain electrode 17 of TFT 2 are connected to gate bus line 1 and data bus line 7, respectively. When a voltage is applied to gate bus line 1 from the gate driver circuit(not shown) TFT 2 is turned on, and at the same time, the signal is applied to the pixel electrode 9 from a data driver circuit(not shown) through TFT 2.
There are two types of inverted stagger structure TFTs. One is ES TFT(etch stopper TFT) and the other is BCE TFT(back channel etched TFT). In the ES TFT, the ES layer is formed over the semiconductor layer to prevent the channel region of the semiconductor layer from being etched when the semiconductor layer and the source/drain electrodes are etched. In the BCE TFT, since there is no insulating layer on the semiconductor layer, the process is simpler, although the semiconductor layer in the channel region is etched during the process.
FIGS. 2a-2f illustrate various steps of the conventional process for fabricating a TFT with inverted stagger structure. As shown in FIG. 2a, metal is first deposited on to a transparent glass substrate 10 and etched to form a gate electrode 11. Over the substrate 10 and gate electrode 11, as shown in FIG. 2b, gate insulating layer 13, amorphous silicon(a-Si) layer 14a, and insulating layer 15a are successively deposited. The insulating layer 15a is etched to form and ES layer 15, as shown in FIG. 2c.
As shown in FIGS. 2d and 2e, n.sup.+ a-Si layer 16a and metal layer 17a are deposited after a-Si layer 14a is etched to form a semiconductor layer 14. To form ohmic contact layer 16 and the source/drain electrodes 17, the n.sup.+ a-Si layer 16 and metal layer 17a are etched. As a result, a portion of ES layer 15 overlaps n.sup.+ layer 16 and another portion is exposed. On source/drain electrodes 17 and ES layer 15, the passivation layer(not shown) is deposited. A contact hole is formed in the passivation layer and the pixel electrode 9 covers pixel region to connect it to source/drain electrodes 17.
In this process, since ES layer 15 covers the channel region of semiconductor layer 14, the channel region is non affected during the etching of the a-Si 14a and the n.sup.+ a-Si 16a layers. As shown in the figures, however, six masks are needed to fabricate the TFT of the LCD; that is, masks for forming the gate electrodes, ES layer, semiconductor layer, source/drain electrodes and n.sup.+ layer, contact hole, and pixel electrode. The resulting process is complex and costly.

Method for fabricating thin film transistor


In a color-image pickup device, light is decomposed by R filters, G filters, B filters, and an infrared blocking film into R, G, and B components, and photoelectric conversion elements arranged in a light-reception area receive the R, G, and B components, and output R, G, and B picture signals. The relative reduction in the intensity of the R picture signal, which increases with the incident angle of the R component, is compensated for by relatively increasing the transmittance of the R component or the gain of the R picture signal, or setting light-reception efficiencies at the respective photoelectric conversion elements so as to relatively increase the light-reception efficiency of the R component, with an increase in the distance from the center of the light-reception area.

1. Field of the Invention
The present invention relates to a color-image pickup device which decomposes an optical image of an object with color filters, picks up the optical image with photoelectric conversion elements, and obtains a color-picture signal. In addition, the present invention also relates to an electronic color camera which contains the above color-image pickup device.
2. Description of the Related Art
The following document (1) discloses information related to the present invention.
(1) Japanese Unexamined Patent Publication No. 5-207350
In recent years, video cameras and electronic cameras have come into widespread use. Currently, the technology of advanced color-image pickup devices for use in the video cameras and electronic cameras is rapidly developing. Normally, CCD type or CMOS type image pickup elements are used in the color-image pickup devices. In order to obtain a color-picture signal, the image pickup elements are used in combination with on-chip type or field-sequential type color filters. In the on-chip type color filters, very small color filter elements are used in combination. In the field-sequential type color filters, color filter elements are sequentially arranged in a time-sharing manner. Further, the color filters may be RGB filters, YCyMg filters, or the like. The RGB filters are realized by R filters transmitting light in a red wavelength range, G filters transmitting light in a green wavelength range, and B filters transmitting light in a blue wavelength range. The YCyMg filters are realized by Y filters transmitting light in a yellow (red+green) wavelength range, Cy filters transmitting light in a cyan (green+blue) wavelength range, and Mg filters transmitting light in a magenta (red+blue) wavelength range.
Although it is often explained that the color filters are constituted by a plurality of optical filters each transmitting light in a predetermined wavelength range as indicated above, the color filters actually have a different structure. For example, since the image pickup devices such as CCDs have substantial sensitivity to infrared rays, it is necessary to provide an infrared-cutoff filter which cuts off the infrared rays.
Hereinbelow, the detailed structure of an example of an actual color filter will be described. In this example, the color filter is a primary-color filter. FIG. 12 shows transmission wavelength ranges of four optical filters (a B filter, a G filter, an R filter, and an infrared-cutoff filter) used in the primary-color filter. As shown in FIG. 12, the B filter transmits light in the wavelength range from about 400 to 450 nm, and determines a blue wavelength range, the G filter transmits light in the wavelength range from about 500 to 550 nm, and determines a green wavelength range, the R filter transmits light having wavelengths equal to or longer than 600 nm, and determines the lower limit of the red wavelength range, and the infrared-cutoff filter determines the higher limit of the red wavelength range. Since neither the B filter nor the G filter can cut off the infrared rays, in many color filters, the infrared-cutoff filter is superimposed on each of the R, G, and B filters, and normally a discrete infrared-cutoff filter such as a colored glass plate is inserted into the optical system.
Further, with the recent development in the miniaturization of color-image pickup devices, there is great demand for the miniaturization of optical elements. Therefore, currently, the miniaturization of image pickup lens systems is being pursued. In addition, in some proposed devices, as disclosed in the aforementioned document (1), a dielectric multilayer film for infrared blocking is formed by vapor deposition on an optical element such as a lens or cover glass, instead of the insertion of the discrete infrared-cutoff filter.
Increase in the angular aperture on the image side (i.e., increase in the angle between the optical axis and the principal ray corresponding to the maximum image height) is effective to miniaturize the image pickup lens systems. However, when the angular aperture on the image side is great, the light incident angle at each photoelectric conversion element in each image pickup device increases as the distance from the center of the light-reception area of the image pickup device to the photoelectric conversion element increases. On the other hand, as illustrated in FIG. 13, the transmission wavelength range of the dielectric multilayer film for infrared blocking has a dependence on the incident angle, and the red wavelength range moves to the shorter-wavelength side as the incident angle increases. Therefore, the upper-wavelength side of the red wavelength range is cut off, and the width of the red wavelength range is reduced.
Thus, the ratio of the signal intensity in the red wavelength range to the signal intensity in the green or blue wavelength range at each photoelectric conversion element in each image pickup device decreases as the distance from the center of the light-reception area of the image pickup device to the photoelectric conversion element increases. Therefore, colors represented by the color signal obtained from the above image pickup device are different from actual colors, i.e., color shading occurs.

Color-image pickup device in which an R picture signal is relatively enhanced with distance from center of light-reception area


The invention relates to heat-exchanger tubes structured on both inner and outer sides with excellent heat-transfer characteristics, which have recesses on the outside and ribs with specific dimensions on the inside. The structuring tools utilized for the various method modifications are adjusted in such a manner that they are not only able to create aligned, continuous grooves and non-aligned, spaced apart recesses but also secondary structures. The heat-exchanger tubes provided preferably with smooth end sections and smooth intermediate sections are utilized in particular in shell and tube heat-exchangers.

The invention relates to a heat-exchanger tube with optionally smooth ends, at least one structured section on the outside and inside of the tube and optionally smooth intermediate sections, whereby the outside diameter of the structured area is no greater than the outside diameter of the smooth ends or of the smooth intermediate areas.
This type of tube is usually identified as xe2x80x9cdouble-enhanced tubesxe2x80x9d.
Heat-exchanger tubes of the mentioned type are usually used in shell and tube heat-exchangers (see FIG. 1, Source: TEMA, Standards of Tubular Exchanger Manufacturers Association, New York, 1968). These heat exchangers are characterized by a plurality of tubes 30, which are arranged parallel to one another, and which at their ends are tightly connected to the tube sheets 31. Depending on the operating conditions and tube length, the tubes are supported by means of baffles 32. These baffles 32 are also utilized to direct the shellside fluid flow in specific directions. For example, water or a mixture of water and glycol flows in the tubes 30, whereby the flowing medium along the inside of the tubes is heated or cooled off.
In order to increase the heat-transfer performance of such heat exchangers, finned or structured tubes instead of smooth surfaced ones are utilized. It is hereby intended to enlarge the surface which is available for the heat transfer and to furthermore utilize effects of the surface tension. FIG. 2 illustrates schematically a structured heat-exchanger tube 30. It has several structured sections 2, which are confined by smooth, unstructured end sections 1a and smooth unstructured intermediate sections 1b .The tube 30 is usually tightly connected at the smooth end sections 1a to the tube sheets 31 through a rolling process. The tube 30 rests at the smooth intermediate sections 1b in the bores of the baffles 32. In order for the tube to be able to be moved into the tube sheets 31 and baffles 32 and to be able to be tightly connected to the tube sheets 31 or not to have too much clearance in the bores of the baffles 32, the outer diameter of the structured sections 2 may not be greater than the outer diameter of the smooth sections 1a and 1b .On the other hand, the inside diameter of the tube 30 should be as large as possible in the structured sections 2 in order to keep the pressure drop of the tubeside flowing medium as low as possible. The outside and inside diameter of the tube 30 are at a given structure type in relation to one another in the structured section 2 so that also the outside diameter of the tube 30 should be as large as possible in the structured section 2. Thus, it is advantageous to choose the outside diameter in the structured section 2 to be almost equal to the outside diameter of the smooth tube sections 1a and 1b.
In order to lower the material costs of such tubes, the specific tube weight (i.e. tube weight per unit of length) of the tubes must be reduced at a specified tube diameter. Since the minimum wall thickness is limited by safety requirements, a reduction in the specific tube weight can only be achieved through a reduction of the weight of the structure. An increase of the heat-transfer surface through structuring with a simultaneous minimizing of the structure weight requires a very fine, slim structure.
The use of double enhanced tubes is state of the art in some parts of the industry (for example, in chillers for air conditioners). Many of these tubes are based on finned tubes, whereby the fin tips were modified through notching and flattening. Such tubes are usually manufactured using a rolling process: Rolling disks with a specific profile shape are set up with an increasing diameter on one or more tool shafts. These tool shafts are arranged evenly around the periphery of the tube to be worked. When the inclined positioned, rotating tool shafts are moved towards the smooth tube, the rotating rolling disks penetrate into the wall of the tube, rotate the tube, advance it corresponding to their inclined position in axial direction to form radially outwardly extending helical fins out of the wall of the tube. This operation is similar to a thread rolling operation. Examples for this technology are illustrated in U.S. Pat. Nos. 2,868,046, 3,327,512, 3,383,893 and 3,481,394.
The tube is during the rolling process supported by a mandrel lying in the tube, which mandrel absorbs the radial forces. In order to produce an inner structure, profiled mandrels are provided with helical grooves (DE 23 03 172 C2). Since the inner structure of the tube is determined by the profile shape of the mandrel, it can be shaped essentially independent from the geometry of the outer fin structure. Thus, it is possible to optimally adapt the outer and inner structure independent from one another to accommodate various operating conditions. The mandrel must rotate at a certain speed in order to unscrew itself from the inner structure of the tube. This produces high friction forces between the mandrel and the tube, which must be applied by the rolling disks in order to cause the advance of the tube in the axial direction. A considerable portion of these friction forces is directed parallel with respect to the tube axis 33 and thus also almost parallel with respect to the axis of the rolling disks.
It is known that it is advantageous for certain applications (for example, refrigerant evaporators and condensers) to use structures with small fin pitches in order to achieve an increase in the heat-transfer performance. In the past, fin pitches of 1.35 mm (19 fins per inch) have been used. Today finned tubes having fin pitches of approximately 0.40 mm are commercially available (U.S. Pat. No. 5,697,430 and DE-19757 526). EP-0 701 100 A1 shows that the trend is going to yet smaller pitches (0.25 mm).
Smaller fin pitches demand thinner rolling disks, which causes an increased danger regarding breakage due to the above mentioned friction forces and a greater susceptibility to wear of the tool. The tool life thus becomes more critical and repeated production interruptions because of tool exchange are the consequence. Furthermore the production speed of the rolling machines decreases with decreasing fin pitch. At the same time, because of worldwide competition, the production costs become a decisive factor for the economical success of the manufacture of structured tubes.
Therefore the basic purpose of the invention is to manufacture a delicately structured tube which has both on the outside and also on the inside a large increase in surface area and has a low structure weight. The geometries of outer and inner structures are adaptable independent from one another. The tube must be able to be manufactured at a high speed, with simple tools and low tool wear. Smooth end sections and intermediate sections are manufactured without extra expense.
The purpose is attained according to the invention by creating recesses with certain dimensions on the outside and ribs with certain dimensions on the inside of the tube. The recesses and ribs are formed by pressing rotating roll-forming tools into the tube wall and by the displaced material of the tube wall being pressed inwardly onto a profile mandrel lying in the tube. The utilized structuring tools can be adjusted in such a manner that they create both aligned, continuous grooves and also non-aligned, spaced-apart recesses.
By using additional tools, it is possible to modify the recesses so that secondary structures are created at the flanks or at the base of the recesses or at the ribs between the recesses. Depending on the use, these secondary structures can significantly increase the thermal performance of tubes. This occurs essentially by utilizing surface-tension effects.
It is advantageous for condenser tubes to create structures which have convex edges and channels extending essentially in peripheral direction. These channels enable the discharge of condensate, which is generated on the tube itself or on the tubes of the tube bundle being arranged thereabove.
It is advantageous for tubes, which are utilized in flooded evaporators or spray evaporators, to produce structures with cavities by partially closing off the upper areas of the recesses. This is achieved according to the invention by additional flattening tools which are arranged downstream of the primary structuring tool on the tool shaft.

Heat-exchanger tube structured on both sides and a method for its manufacture


A reversible thermosensitive recording material composed of a support, an undercoat layer formed on the support, and a reversible thermosensitive recording layer formed on the undercoat layer, capable of reversibly assuming a transparent state and a white opaque state depending on the temperature thereof, the undercoat layer having at least one colored portion and at least one light reflecting portion.

1. Field of the Invention
The present invention relates to a reversible thermosensitive recording material capable of recording and erasing images repeatedly by utilizing the property of reversibly changing the transparency from a transparent state to an opaque state depending upon the temperature thereof.
2. Discussion of Background
Recently attention has been paid to a reversible thermosensitive recording material capable of temporarily recording images thereon and erasing the same therefrom when such images become unnecessary. For example, as disclosed in Japanese Laid-Open Patent Applications 54-119377 and 55-154198, there are conventionally known reversible thermosensitive recording materials in which an organic low-molecular-weight material such as a higher fatty acid is dispersed in matrix resin such as a vinyl chloride resin. These according materials reversibly assume a transparent state and a white opaque state, so that an image formed in the recording materials can usually be recognized as a reflected one by providing a colored material on the reverse side of the recording material. However, the image contrast is insufficient merely by providing the colored material on the reverse side of the recording material. Therefore, the formation of a light reflection layer on the reverse side of the recording material is proposed, as disclosed in Japanese Laid-Open Patent Application 1-14079. However, in the case where the light reflection layer is provided on the reverse side of the recording material, images are not always legible depending on the light reflection directions when the images are seen with the naked eyes even though the contrast is remarkably improved in terms of the density and the reflectance thereof measured by a measuring instrument such as a reflection-type densitometer.
When a colored material is provided on the reverse side of the recording material, there is the shortcoming that the image contrast measured by the aforementioned measuring instrument is degraded although images can visually be recognized to some extent regardless of the light reflection directions.

Reversible thermosensitive recording material


A polycarbonate composition comprises an elastomer-modified graft copolymer prepared by an emulsion polymerization process in which an elastomer phase is polymerized or copolymerized in the presence of an electrolyte to obtain latex particles that is then grafted with a monomer mixture comprising a monovinylaromatic monomer.

Polycarbonate/acrylonitrile-butadiene-styrene (PC/ABS) blends, products commercially available from SABIC Innovative Plastics, are an important class of polymeric materials for reasons of their excellent balance of properties such as low-temperature ductility, heat resistance, and outstanding aesthetics combined with ease of processing.
The polycarbonate portion of such a blend, however, is susceptible to degradation by acids and bases, especially under conditions of high heat and humidity. Degradation can cause undesirable color formation, loss of molecular weight, reduced chemical resistance or inferior mechanical properties, and generation of volatiles that can cause defects in surface appearance, for example, splay in molded parts.
These problems can be exacerbated by the addition of elastomeric impact modifiers that are commonly used to improve the toughness of polycarbonate compositions. In particular, an elastomer-containing impact modifier prepared by emulsion polymerization can decrease the stability of a polycarbonate. Specifically, compounds employed as aids in the emulsion polymerization of the impact modifier, during its preparation, can remain as residues within the impact modifier and can, thereby, promote transesterification or degradation of a polycarbonate. For example, U.S. Pat. No. 7,393,896 discloses that alkali metal salts of fatty acid emulsifiers, used during emulsion polymerization of an impact modifier to stabilize the emulsion, can later catalyze transesterification or degradation of a polycarbonate composition containing that impact modifier. In turn, the residual amount of emulsifiers remaining in the impact modifier can cause adverse effects, including inconsistent thermal stability of the polycarbonate composition. This can lead to problems during the molding of the polycarbonate composition, due to the variability in viscosity resulting from the catalytic transesterification or degradation of the polycarbonate component.
In view of the above, the use of emulsion-prepared elastomer-modified graft copolymers in polycarbonate compositions has been avoided, in some cases, in favor of bulk polymerized elastomer-modified graft copolymers, particularly when a stringent requirement for hydrostability exists such as exists with respect to molded parts used in the automotive industry. Bulk polymerized acrylonitrile-butadiene-styrene ("bulk ABS") is essentially free of any surfactant. Accordingly, when higher hydrostability is desired, bulk ABS has been used in admixture with a small amount of sulfonate-based MBS to improve the impact resistance of a polycarbonate composition, as disclosed in EP 0900827 and U.S. Pat. No. 7,393,896 assigned to Sabic Innovative Plastics.
Because of the relatively lower elastomer content in bulk ABS, however, it usually cannot be used (or used alone) when higher impact resistance is desired, such as could otherwise be obtained by an emulsion-prepared ABS. An emulsion-prepared ABS can have elastomer levels as high as 60 wt. % or more.
As indicated above, replacing alkali metal carboxylate based surfactants, previously used in preparing elastomer-modified graft copolymers, with a sulfonate surfactant can improve the stability of a polycarbonate/ABS blend, as disclosed by U.S. Pat. No. 7,393,896. However, further improvement is still desired to meet stringent demands for stability required for certain molded parts.
In view of the above, an object of the present invention is to provide an impact-modified polycarbonate composition having improved resistance to polymer degradation, even under strenuous conditions. In particular, an improved balance of high impact resistance and excellent hydrostability and thermal stability is desired.

Polycarbonate compositions comprising elastomer-modified graft copolymer prepared by emulsion polymerization


Methods of using glucokinase (GK) activators are generally disclosed herein, particularly in combination with insulin or insulin analogs. In certain aspects, the disclosure provides methods of treating type 1 diabetes that include administering a GK activator in combination with insulin or insulin analogs. Uses of GK activators as a medicament are also disclosed herein, as well as the manufacture of a medicament for such uses.

Diabetes mellitus type 1 (type 1 diabetes) is a chronic condition that results from the autoimmune destruction of the insulin-producing beta cells in the pancreas. As a result, persons suffering from type 1 diabetes cannot produce sufficient insulin to permit them to regulate blood-glucose levels properly. Thus, without treatment, they would likely suffer from acute conditions resulting from extremely high blood-glucose. But, even with treatment, persons suffering from type 1 diabetes can still experience fluctuations in blood-glucose levels that result in acute conditions (such as hyperglycemia and hypoglycemia) and that can eventually increase risk of chronic conditions, such as heart disease, stroke, blindness (due to diabetic retinopathy), kidney failure, and poor blood circulation to the limbs (which can result in the need to amputate limbs that no longer benefit from sufficient circulation).
Type 1 diabetes can generally only be managed through the administration of insulin or insulin analogs. Recent decades have witnessed an expansion in the different kinds of insulin that is available, including rapid-acting insulin, short-acting insulin, intermediate-acting insulin, and long-acting insulin. Further, devices have recently come to market that offer continuous glucose monitoring, coupled with a pump for making real-time adjustments to insulin dosing. Many pharmaceutical drug therapies useful for treating non-insulin dependent diabetes have shown low or no effectiveness at treating type 1 diabetes. That is because many pharmaceutical drug therapies rely on the body's ability to make endogenous insulin. Thus, such therapies are of little use in treating type 1 diabetes, because type 1 diabetics have little or no ability to make and secrete endogenous insulin.
Thus, there is a continuing need to develop effective pharmaceutical compounds that can assist in the management of type 1 diabetes without relying on the production of endogenous insulin.

Therapeutic uses of glucokinase activators in combination with insulin or insulin analogs


A styrylcoumarin compound jointing a styryl group by--(C.dbd.C)n--portion and having --NR.sub.1 R.sub.2 group, wherein n is an integer of 2 to 4, and each R is a proton or an alkyl group having 1 to 10 carbon atoms. A photopolymerizable composition comprises the styrylcoumarin compound as a photosensitizer, a polymerization initiator and a polymerizable compound. A photocrosslinking composition comprises the styrylcoumarin compound as a photosensitizer, a crosslinking agent and a polymerizable compound. A volume phase hologram recording medium which comprises the styrylcoumarin compound, a crosslinking agent and a polymer comprising a carbazole.

1. Field of the Invention
The present invention relates to a novel styrylcoumarin derivative, and more specifically, it relates to a photosensitizer comprising a styrylaminocoumarin derivative which functions as a photosensitizer (a sensitizing dye) for a polymerization initiator and/or a crosslinking agent, a photopolymerizable and/or photocrosslinkable photosensitive composition using the photosensitizer, and a hologram recording medium containing the photosensitive composition as a main component.
2. Related Background Art
With the development of triplet sensitizers and dye lasers, various novel coumarin compounds have been synthesized. Above all, ketocoumarins have absorption maximum ranging from 330 nm to 470 nm and so they have been developed as effective triplet sensitizers Tetrahedron, 38, p. 1211 (1982)!.
In consequence, nowadays, the coumarin compounds have been widely used as the photosensitizers for polymerization initiators such as diphenyliodonium salts, triazine, peroxides and halogen compounds. Above all, compounds represented by the formulae (1) to (3) are known as preferable photosensitizers in a photosensitive system using an argon laser at 488 nm. ##STR1##
However, these dyes have absorption maximums in a wavelength region shorter than 488 nm, and a wavelength of 514.5 nm for the argon laser is their absorption edges. Therefore, it is necessary to enhance their sensitivity. In order to enhance the sensitivity of a photosensitive material, an absorbance of the photosensitive material is required to be increased, and as a conventional technique for increasing the absorbance, there has been only one method of increasing the amount of a dye.
In recent years, for the purpose of solving these problems, it has been suggested to use a styrylcoumarin compound represented by the following structural formula (4) as a photosensitizer (a sensitizing dye) Polymer Engineering And Science, 23, p. 1022 (1983)!. However, the suggested photosensitizer is not sufficiently suitable for exposure at 514.5 nm by the argon laser. ##STR2##

Styrylcoumarin compound, photosensitive resin composition, and hologram recording medium


A first processor that executes at least one application or process includes a first interface module that interfaces the first processor to a second processor and that includes N interfaces. N is an integer greater than 1. The first processor also includes a first communication control module (CCM) that selects M of the N interfaces based on bandwidth requested by the at least one application to transmit data generated by the at least one application to the second processor.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a device 10 may execute applications that process large amounts of data. For example only, the device 10 may comprise a personal digital assistant (PDA), a wireless network device, or a cellular phone. Additionally, the device 10 may transmit and receive large amounts of data to and from other devices. Accordingly, the device 10 may comprise an application processor (AP) 12 and a communication processor (CP) 14. The AP 12 may execute the applications that process the data. The CP 14 may communicate with the AP 12, transmit data received from the AP 12 to other devices, and provide data received from other devices to the AP 12.
The AP 12 and the CP 14 may comprise one or more hardware interfaces I/F1, I/F2, . . . , and I/Fn, where n is an integer greater than 1. The hardware interfaces I/F1, I/F2, . . . , and I/Fn may include universal asynchronous receiver/transmitters (UARTs), universal synchronous bus (USB) interfaces, secure digital input/output (SDIO) interfaces, and/or serial peripheral interfaces (SPIs) and/or other types of interfaces. The AP 12 and the CP 14 may communicate with each other via the hardware interfaces I/F1, I/F2, . . . , and I/Fn.

Bandwidth control and power saving by interface aggregation


An apparatus for guiding, treating, or advancing at least one yarn (1), comprising a delivery roll (2) and a companion roll (3) cooperating with the delivery roll so that the yarn repeatedly loops the delivery roll (2) and the companion roll (3). The delivery roll and the companion roll are driven by associated electric motors (7, 8), which are controlled via control lines (9) at a desired frequency by a controller (10). To enable an equalization of the circumferential speeds of the delivery roll (2) and the companion roll (3), the electric motor of the companion roll is an asynchronous motor that is controlled by the desired frequency and has a motor slip.

The present invention relates to an apparatus for guiding, treating, or advancing at least one yarn, of the type commonly used in a melt spinning process. In such process, it is known to use apparatus of the type which comprise a delivery roll and a companion roll associated therewith for enabling a repeated looping of the yarn. In this arrangement, the delivery roll is driven, whereas the companion roll may be constructed with or without a drive unit, as is disclosed, for example, in EP 1 001 521 A2.
According to EP 1 001 521 A2, the delivery roll and the companion roll can each be driven by an electric motor, which is a synchronous motor. By means of a controller the electric motors are controlled at a desired frequency for driving the delivery roll and the companion roll at the same circumferential speed. The layout of the drive units is based on the fact that for maintaining a yarn speed as constant as possible, the circumferential speed of the delivery roll and the circumferential speed of the companion roll must be kept constant. In practice, however, even slight inaccuracies in the casing of the delivery roll or in the casing of the companion roll lead to deviations in the casing diameters, which directly effect a change in the circumferential speeds. This effect results in that on the circumference of the companion roll, the yarn is either decelerated or advanced with overfeed. Interactions of this kind, however, lead to an unsteady advance of the yarn, which has a negative effect in particular when a plurality of yarns advance parallel in side-by-side relationship.
It is therefore an object of the invention to provide an apparatus of the initially described type wherein the yarn can be guided on the circumference of the delivery roll and on the circumference of the companion roll at a substantially constant speed.

Apparatus for guiding, treating, or conveying at least one yarn


A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying various loads to the matchline and/or the discharge line, the match detection circuit demonstrates whether it can overcome the applied loads.

A content addressable memory (CAM) is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., random access memory (RAM), dynamic RAM (DRAM), etc.). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and reads into or gets back the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every location has a pair of status bits that keep track of whether the location is storing valid information in it or is empty and available for writing.
Once information is stored in a memory location, it is found by comparing every bit in memory with data in the comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, the local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, a local match detection circuit returns a match indication. If one or more local match detection circuits return a match indication, the CAM device returns a "match" indication. Otherwise, the CAM device returns a "no-match" indication. In addition, the CAM may return the identification of the address location in which the matched data is stored or one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back the address if there is a match found in memory.
Locally, CAMs may perform match detection using an exclusive-NOR (XNOR) function, so that a match is indicated only if both the stored bit and the corresponding input bit are the same state. CAMs are designed so that any number of stored bits may be simultaneously detected for a match with the input bits in the match detection circuit. One way in which this is achieved is by coupling a plurality of storage devices and logic circuits to a common matchline, as depicted in FIG. 1.
Turning to FIG. 1, a schematic diagram of a conventional match detection circuit 100 is depicted. A first source/drain terminal of a precharge transistor 102 is coupled to a positive voltage source (e.g., VDD). The gate of transistor 102 is coupled to a signal line 138 for receiving a precharge signal. A second source/drain terminal of transistor 102 is coupled to a matchline 140 for precharging the matchline 140 to a predetermined voltage level (e.g., VDD).
The match detection circuit 100 includes several CAM cells 191, which are used to store data. CAM cells 191 also compare the stored data to comparand data to determine if the stored data and the comparand data are substantially the same. Each CAM cell 191 is coupled to matchline 140 through lines 120, 122. Each CAM cell 191 is coupled to discharge line 142 through lines 128, 130. The discharge line 142 is electrically coupled to a ground potential through line 190.
Also coupled to the matchline 140 is a buffer 136 for buffering the matchline 140 voltage and for outputting a match signal. Typically, a logic high (e.g., VDD) match signal indicates that an exact match was detected between the input comparand bits and the stored bits. A logic low (e.g., Ground) match signal represents that at least one bit of the stored data did not match its corresponding input bit.
FIG. 2 shows a portion of the FIG. 1 circuit in greater detail. The CAM cell 191 of FIG. 2 is representational of any of the CAM cells 191 of FIG. 1. The CAM cell 191 includes a storage element 104 and transistors 110, 112, 106, 108, 162, 164. The storage element 104 is used to store a data bit and the complement of the data bit. The output Q0 of storage element 104, which is to be compared with the complement input bit B0*, is coupled to the gate of transistor 106. The first source/drain terminal of transistor 106 is coupled to the matchline 140 (FIG. 1) through line 120. The second source/drain terminal of transistor 106 is coupled to transistor 110. The second source/drain terminal of transistor 110 is coupled to discharge line 142 (FIG. 1) through line 128. The gate of transistor 110 is coupled to complement input bit B0*.
Input bit B0, used to store information in the storage element, is also coupled to the first source/drain terminal of transistor 162 through line 150. The second source/drain terminal of transistor 162 is coupled to an input of storage element 104. The gate of transistor 162 is coupled to wordline 144.
Further, the complement output Q0* of storage element 104, which is to be compared with the input bit B0, is coupled to the gate of transistor 108. First source/drain terminal of transistor 108 is coupled to the matchline 140 (FIG. 1) through line 122. The second source/drain terminal of transistor 108 is coupled to transistor 112. The second source/drain terminal of transistor 112 is coupled to discharge line 142 (FIG. 1) through line 130. The gate of transistor 112 is coupled to the input bit B0.
Complement input bit B0* is also coupled to the first source/drain terminal of transistors 164 through line 152. The second source/drain terminal of transistor 164 is coupled to an input of storage element 104. The gate of transistor 164 is coupled to a wordline 144.
To write to or to read from the storage element 104, the wordline 144 is set to a logic high then to a logic low, which temporarily activates transistors 162, 164 and couples the storage element 104, to input bit B0 and the complement input bit B0*.
Referring to FIGS. 1 and 2, during operation of the match detection circuit 100, the precharge signal goes logic low then logic high in order to precharge the matchline 140 to VDD. The states of a bit stored by storage element 104 and the complement of the stored bit are respectively coupled to the gates of transistors 106, 108 via outputs Q0, Q0*. Consequently, depending upon the states at their respective gates, the transistors 106, 108 may become active.
Similarly, the states of the input bit B0 and its complement B0* are coupled to the gates of transistors 112, 110. Consequently, depending upon the states at their respective gates, the transistors 112, 110 may be active. Consequently, input bit B0 and its complement B0* serve two functions: they function to read and write information to the storage element 104 and they also function to carry the information stored in the comparand for comparison with information stored in the storage element 104.
As seen in FIG. 2, when a match is detected, at least one transistor of each serially connected pair of transistors (e.g., 106 and 110, 108 and 112) is inactive and not conducting. Therefore, when the matchline 140 remains logic high, this signifies to the outside world that a match has been detected and potentially enables any other functions desired when a match is detected (e.g., provide the user with the address of the memory location where the match was found, forward the data to another location, etc.).
However, when a mismatch is detected, as is most often the case during a search for a particular bit pattern, at least one pair of serially connected transistors (e.g., 106 and 108, 110 and 112) is active and conducting and the matchline 140 is coupled to the ground potential. When the matchline 140 is coupled to the ground potential, the match signal goes logic low, which signifies to the outside world that a mismatch has been detected for this storage element 104. Although match circuit 100 of FIG. 1 is shown with two CAM cells 191, any number of CAM cells may be utilized.
In the above-identified search process, the searched data (i.e., the input bits from the comparand) is simultaneously compared with every data word in the match detection circuit 100 in order to find a match between the stored data and the input data.
Conventional testing of the match detection circuit 100 begins by precharging the matchline 140 to a predetermined voltage, e.g., VDD, so that the matchline 140 floats (assuming no significant leakage otherwise exists in the circuit). Stored data in the match detection circuit 100 is then compared to comparand data. Using predetermined comparand and stored data, the expected results (e.g., match or mismatch) are easily determined. The actual results of the test are compared with the expected results to determine the reliability of the match detection circuit 100.
Because of the architecture of the match detection circuit 100, it is possible that, due to defects during design or manufacturing, the circuits within the match detection circuit 100 will cause an erroneous match or mismatch signal to be generated. Further, elements of an array containing match detection circuits 100 may pass conventional tests, but they may be "weak" or marginally acceptable.
Therefore, it is desirable to test the margin of the match detection circuit 100 to determine its reliability.

Circuit and method for configuring CAM array margin test and operation


A PLL circuit produces first to n-th (n being an integer equal to or greater than 2) reference signals. A first variable frequency divider divides the frequency of an output of a voltage-controlled oscillator to produce a first feedback signal. A second variable frequency divider divides the output of the voltage-controlled oscillator to produce second to n-th feedback signals. A phase comparator compares the phases of the first to the n-th reference signals with the phases of the first to the n-th feedback signals to produce first to n-th error signals. A controller produces a control signal from the error signals. The PLL circuit synchronizes the first reference signal with the first feedback signal in phase after the phase difference between at least one of the first to n-th reference signals and a corresponding feedback signal becomes smaller than a predetermined value. The frequency-division ratio of the second variable frequency divider is 1/n that of the first variable frequency divider.

The present invention relates to a PLL circuit.
A PLL apparatus which generates, from a reference signal having a certain frequency, signals having various frequencies that are in synchronization with this reference signal is known as illustrated in xe2x80x9cSANYO TECHNICAL REVIEWxe2x80x9d VOL.10, NO.1, page 32, February 1978, for example. This PLL apparatus includes a reference oscillator generating a reference signal RF, a voltage-controlled oscillator generating an output signal OF having a frequency responsive to a control voltage CV, a variable frequency divider dividing the output signal OF to produce a feedback signal FV, a single phase comparator comparing the phase of the feedback signal FV with the phase of the reference signal to produce an error signal ER, and a low-path filter producing the control voltage CV in response to the error signal ER.
This PLL circuit has the disadvantage of having a long lock-up time (the time until synchronization between the output signal and the reference signal is reached), since it has a single-stage phase comparator and therefore, phase comparison is performed only once during one period of the reference signal.
Japanese Unexamined Patent Publication No. 10-135822 discloses a PLL circuit which can get rid of such disadvantage. The PLL circuit disclosed in this publication includes means for generating a plurality of reference signals having different phases, a plurality of (four, for example) frequency dividers for dividing the frequency of the output signal of the voltage-controlled oscillator, and a plurality of phase comparators for comparing the phase of each of the frequency dividers with the phase of a corresponding one of the reference signals in order to perform phase comparisons several times during one period of the reference signals.
However, the PLL circuit disclosed in this publication consumes electric power in large quantity since it has four frequency-dividers. Especially the consumption is large during an early stage when all the four phase comparators are operated for performing phase comparisons four times during one period of the reference signals. Furthermore, since the PLL circuit has the plurality of the phase comparators which require a relatively large layout space, there is a problem that it is difficult to implement the PLL circuit in an LSI.
Besides, the PLL circuit disclosed in the publication has the plurality of the phase comparators for comparing, with the outputs of the plurality of the frequency dividers that individually divide the frequency of the output of the voltage-controlled oscillator, the plurality of the reference signals having the frequency of 2.6 MHz and different phases which are produced by a delay circuit that delays an output of a fixed frequency divider having a frequency-division ratio of 5 for dividing by 5 the frequency of the output signal having the frequency of 13 MHz output from the reference oscillator.
In the PLL circuit of this type, the frequency of the plurality of the reference signals divided by the number of the reference signals has to match a channel spacing frequency, or a spacing in frequency of signals to be produced by the PLL circuit. However, in the PLL circuit disclosed in the publication, the number of the phase comparators in use, that is the number of the reference signals is an exponentiation of 2. For example, when the channel spacing frequency is required to be 200 kHz, if the number of 16 is selected as the exponentiation of 2, (the frequency of the reference signals)/(the number of the reference signals) is equal to 1300 kHz/5/16=162.5 kHz, and does not match the channel spacing frequency of 200 kHz.
When making (the frequency of the reference signals)/(the number of the reference signals) match a required channel spacing frequency is not possible, the frequency-division ratio of the frequency divider that divides the frequency of the output of the voltage-controlled oscillator may have to be of a value including not only an integer but also a fraction. In that case, however, C/N (Carrier to Noise Ratio) will be degraded since it is impossible to perform phase comparisons with high precision.
An object of the present invention is to provide a PLL circuit which has a short lock-up time and a low power consumption, and is easy to implement in an LSI for reducing the cost of manufacturing.
Another object of the present invention is to provide a PLL circuit which has a short lock-up time, and is capable of complying with any channel spacing frequency.
Another object of the present invention is to provide a PLL circuit which can perform phase comparisons with high precision even when its frequency divider has a frequency-division ratio of a value that includes not only an integer but also a fraction by which the output of its voltage-controlled oscillator is divided.
The PLL circuit according to the first embodiment of the invention comprises a PLL frequency synthesizer (13) including a first variable frequency-dividing means (8), and a second frequency-dividing means (9), a plurality of phase comparison signals (ER1 to ER13) being produced from outputs of the first and the second variable frequency-dividing means, at least one of the outputs of these variable frequency-dividing means being locked in phase accurately.
The second variable frequency-dividing means (9) may be formed from a variable frequency divider (10) and/or a counter (11).
The PLL circuit according to the first embodiment may include a producing means (2) for producing a plurality of reference signals (FR1 to FR13) having different phases, a voltage-controlled oscillator (6) and phase comparators (A1 to A13, B1 to B13), the first and the second variable frequency-dividing means (8, 9) dividing the frequency of the output signal of the voltage-controlled oscillator (6) to produce a plurality of feedback signal (FP1 to FP13), the phase comparators comparing the phases of the feedback signals with the phases of the reference signals to output the plurality of the phase comparison signals (ER1 to ER13)
It is possible that all of the phase comparison signals are output at the start, and a specific one of the phase comparison signals is output after near lock.
It is possible to cause the first and the second variable frequency-dividing means (8, 9) to operate at the start, and cause only the first variable frequency-dividing means (8) to continue to operate after near lock.
The PLL circuit according to the second embodiment of the invention comprises a producing means (2) including a reference oscillator (3) for producing a plurality of reference signal (FR1 to FR13) having different phases, a variable frequency-dividing means (8, 9) for dividing the frequency of an output signal of a voltage-controlled oscillator (6) to output a plurality of feedback signals (FP1 to FP13), and phase comparators (A1 to A13) for comparing the phases of the plurality of the reference signals with the phases of the plurality of the feedback signals, the number of the reference signals is set such that a quotient of (an oscillation frequency of the reference oscillator)/(a desired channel spacing frequency) is equal to the number of the reference signals.
A fixed frequency divider (4) may be provided between the reference oscillator (3) and the phase comparators (A1 to A13) so that the number of the reference signals can be set to a value (an integer) equal to the quotient divided by a frequency-division ratio of the fixed frequency divider.
The number of the phase comparators (A1 to A13) may be set to be equal to the above-described quotient or the above-described value.
By selecting one reference signal from among the plurality of the reference signals (FR1 to FR13) in succession, selecting one feedback signal from among the plurality of the feedback signals (FP1 to FP13) in succession, and comparing the phases of the selected signals, it is possible form the phase comparators as a single phase comparator.
The PLL circuit according to the third embodiment of the invention comprises a producing means (32) for producing a plurality of reference signals (FR1 to FR13) having different phases, a variable frequency-divider (59) for dividing the frequency of an output of a voltage-controlled oscillator (50) to produce feedback signals (FP1 to FP13), and phase comparators (37, 38) for comparing phases of the feedback signals with phases of the reference signals respectively to produce n (n being an integer equal to or larger than 2) phase comparison signals (U1 to U13, D1 to D13), the variable frequency-divider being supplied with frequency-division data according to n.
The variable frequency divider (59) may be constituted by a first variable frequency divider (51) and a second variable frequency divider (55), a PLL frequency synthesizer (45) including the first frequency divider may be provided, the first variable frequency divider may be supplied with frequency-division data N, and the second variable frequency divider may be supplied with frequency-division data N/n.
By outputting the plurality of the feedback signals (FP2 to FP13) from the second variable frequency divider (55) one by one in succession, outputting the plurality of the reference signals (FR2 to FR13) one by one in succession, and comparing the phases of the output signals, it is possible to deliver the plurality of the phase comparison signals (U2 to U13, D2 toD13).
The first variable frequency divider (51) and/or the second variable frequency divider (55) may be comprised of a pulse swallow counter (53, 57).
The PLL circuit according to the fourth embodiment of the invention comprises a producing means (62) for producing reference signals (FR1 to FR5), a variable frequency divider (71, 72) for dividing the frequency of an output of a voltage-controlled oscillator (70) by a frequency-division ratio of N+B/C (where N, B and C are integers, and Bxe2x89xa6C) to output feedback signals (FP1 to FP5), and phase comparators (65, 67) for comparing phases of the reference signals with phases of the feedback signals, phase comparisons being performed accurately one time out of C.
The variant of the fourth embodiment comprises a producing means (62) for producing a plurality of reference signals (FR1 to FR5) having different phases, a variable frequency divider (71, 72) for dividing the frequency of an output of a voltage-controlled oscillator (70) by a frequency-division ratio of N+B/C (where N, B and C are integers and Bxe2x89xa6C) to output a plurality of feedback signals (FP1 to FP5), phase comparators (65, 67) for comparing phases of the reference signals with phases of the feedback signals to output a plurality of phase comparison signals (U1 to U5, D1 to D5), phase comparisons being performed accurately one time out of C.
All the phase comparison signals (U1 to U5, D1 to D5) may be output at the start, and only the phase comparison signal (U1, D1) resulting from the accurate phase comparison may be output after near lock or after lock-up.
The frequency of the reference signal (FR1 to FR5) may be the same as the channel spacing frequency multiplied by C.

Precise phase comparison even with fractional frequency division ratio


An apparatus for making a brush broom includes a lever-operated holder for enclosing and precompressing the gathered cut ends of a bunch of branches for a broom. The lever is pressed downwardly against the enclosed branch ends and held by the user until a U-shaped tie wire surrounding the branches and extending upwardly through a slot in the lever arm is twisted around the branches. The broom handle is driven into the center of the bound branch ends to complete the broom.

The present invention pertains to the manufacture of brooms and, more particularly, to an apparatus useful in making a brush broom.
Brush brooms of the type made by attaching the cut ends of a gathered bunch of branches to the end of a broom handle are very old and well known in the art. Although such brooms are not as common today, due to the advent of straw brooms and brooms made with synthetic bristles, brush brooms are still known to be effective and very efficient to use. The branches used may be from any tree or bush that provides a very twiggy branch which when gathered in the broom, provides a flared sweeping end with densely packed twig ends. The most important aspect in making such a broom is providing a tight and permanent attachment of the cut ends of the branches which are eventually attached to the end of the broom handle.


An air spring apparatus with an internal height sensor is provided. The air spring includes an end cap member, a piston member and a flexible annular sleeve connected therebetween forming a sealed air chamber. The height sensor includes a sensing element and an indicating element and is mounted within the air chamber. The sensing element is mounted to one of the end cap member and piston member. The indicating element has a first portion connected to the end cap member, a second portion connected to the piston member, and an elastic member connected therebetween. The length of the elastic member defines an indicating level sensible by the sensing element such that movement of the end cap member relative to the piston member produces a much smaller proportional movement of the indicating level relative to the sensing element. This proportion reduction of movement allows a smaller sensor to measure a relatively large change in height.

Air springs, also known as pneumatic springs, have been used in the suspension systems of motor vehicles, industrial machinery, and buildings for a number of years. An air spring comprises first and second end members, at least one of which is typically shaped like a piston, with an intervening flexible annular sleeve forming a sealed air chamber or cavity therebetween.
When compressive loads are applied to the end members, air pressure within the air chamber provides an opposing force which cushions rapid inward movements and supports steady loads. The annular sleeve typically deforms during movement in a manner guided by the piston-shaped end member(s). An air passage is usually provided between the interior and exterior of the air chamber for selectively adding or releasing air from the air chamber.
Air springs positioned between movable parts of the suspension system of a vehicle can serve to cushion shock loads impressed on the vehicle's suspension by road irregularities, thus improving the ride of the vehicle and reducing vibrational stresses on the vehicle structure, its passengers, and cargo.
Air springs can also serve as load leveling devices to maintain the proper body height and attitude of a vehicle subjected to various loading conditions. Proper vehicle body height can be important both when the vehicle is moving, e.g., to maintain bumper height, rear vision, and fender clearances, and when the vehicle is stationary, e.g., to maintain position at a loading dock during loading or unloading. One conventional measure of vehicle body height is the axle-to-body distance, i.e., the distance from the axle to a fixed reference point on the body. This measure must usually be kept within a permissible range of values to assure proper vehicle operation.
To manually control axle-to-body distance, it is known to provide an air source connected to the air chamber of the air spring and a valve which allows a user to selectively add or release air from the air chamber as desired to increase or decrease, respectively, the axle-to-body distance. Manual height control systems are relatively simple to implement, however, they cannot assure that a given axle-to-body height is maintained under service conditions of changing load, leaking air lines, etc.
To automatically maintain axle-to-body distance within a permissible range of values, a position sensor or height sensor is needed to monitor the positional relationship of a reference point on the frame with respect to the axle. The output of the height sensor is typically connected (possibly by means of a control circuit) to an air source valve to automatically add or release air to insure that the desired axle-to-body height is maintained.
It is known that a height sensor for use with an air spring can be located either externally or internally with respect to the sealed air chamber of the air spring itself. Locating the height sensor externally exposes the sensor to damage, corrosion and contamination from the external environment. Locating the height sensor inside the air cavity of an air spring protects the sensor from damage or contaminants from the external environment. However, the air cavity within an air spring has a limited amount of open space, is frequently occupied by moving structures such as bumpers, and the air itself may be a source of contaminants. These factors can complicate the internal use of conventional height sensors such as those utilizing mechanical, magnetic, or optical properties, to measure axle-to-body height in an air spring. U.S. Pat. No. 5,337,137 describes and air spring apparatus incorporating an optical path height sensor located within the air cavity. This height sensor is provided with a signal processor circuit which comprises a logarithmic converter circuit, a filter, and a rectifier circuit to overcome the undesirable effects of the contamination of the reflective surfaces within the air cavity. Although such a system may allow the use of an optical height sensor within the air cavity of an air spring, the complexity of the control system can make it more difficult and costly to integrate such a sensor into a given control system.
A need therefore exists, for a height sensor which can be incorporated into the air cavity of an air spring, yet which is simple to adapt into existing control systems. A need also exists, for an air spring incorporating a height sensor inside the air cavity, which height sensor being durable and simple to adapt into existing control systems.

Height sensor and air spring apparatus incorporating the same in the air chamber