An in plane switching (IPS) mode liquid crystal display (LCD) panel is fabricated with a reduced number of mask processes and includes a thin film transistor (TFT) array substrate with a TFT provided at a crossing of gate and data lines, a protective film protecting the TFT, a pixel electrode connected to the TFT, a common line substantially parallel to the pixel electrode, a common electrode connected to the common line to generate a horizontal electric field with the pixel electrode, and a pad including a transparent conductive material and connected to the gate line, the data line and/or the common line. A color filter array substrate is joined to, and overlaps a portion of, the TFT array substrate. Portions of the protective film where the color filter array substrate which do not overlap the TFT array substrate are removed to expose the transparent conductive material included in the pad.

1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices. More particularly, the present invention relates to an in plane switching (IPS) mode LCD panel and a method of fabricating the same using a reduced number of mask processes.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices express pictures by selectively altering light transmittance characteristics of liquid crystal material sandwiched between upper and lower substrates. The light transmittance characteristics can be selectively altered by applying an electric field through the liquid crystal material (i.e., driving the liquid crystal material). Depending upon the orientation of the electric field applied through the liquid crystal material, LCD devices may be broadly classified as either a vertical-electric-field-type or a horizontal-electric-field-type LCD device.
LCD devices that drive liquid crystal material using vertically oriented electric fields (e.g., twisted nematic (TN) mode LCD devices) generate electric fields between a pixel electrode formed on the lower substrate and a common electrode formed on the upper substrate. Such LCD devices beneficially have large aperture ratios but display pictures over an undesirably narrow viewing angle of about 90°.
LCD devices that drive liquid crystal material using horizontally oriented electric fields (i.e., in-plane switching (IPS) mode LCD devices) generate electric fields between a pixel electrode and a common electrode formed parallel to each other on the lower substrate. Such IPS mode LCD devices beneficially display pictures over a wide viewing angle of about 160°. Accordingly, a typical IPS mode LCD device includes a lower substrate (i.e., a thin film transistor (TFT) array substrate); an upper substrate (i.e., a color filter array substrate) coupled to, and separated from, the TFT array substrate to form a cell gap; spacers distributed within the cell gap for uniformly maintaining the distance between the TFT and color filter array substrates; and liquid crystal material arranged within the cell gap.
The TFT array substrate includes a plurality of signal wirings for generating a horizontally oriented electric field for each pixel, a plurality of TFTs, and an alignment film coated thereon to impart an alignment to molecules of the liquid crystal material. The color filter array substrate includes a color filter for selectively transmitting light having predetermined ranges of wavelengths, a black matrix for preventing a light from being transmitted in regions outside the pixels, and an alignment film coated thereon to impart an alignment to molecules of the liquid crystal material.
The process used to fabricate the TFT array substrate described above is complicated and relatively expensive because it involves a number of semiconductor processing techniques that require a plurality of mask processes. It is generally known that a single mask process requires many sub-processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection, etc. To reduce the complexity and cost associated with fabricating TFT array substrates, procedures have been developed to minimize the number of masking processes required. Accordingly, a four-mask process has been developed that removes the necessity of a mask process from then standard five-mask process.
FIG. 1 illustrates a plan view of a TFT array substrate of an IPS mode LCD device fabricated using a related art four-mask process. FIG. 2 illustrates a sectional view of the TFT array substrate taken along the I-I′ line shown in FIG. 1.
Referring to FIGS. 1 and 2, the TFT array substrate includes gate lines 2 and data lines 4 formed so as to cross each other on a lower substrate 1 to define a plurality of pixel areas, a TFT 30 provided at each crossing of the gate and data lines 2 and 4, a pixel electrode 22 and a common electrode 84 provided at each pixel area to generate a horizontally oriented electric field, and a common line 86 connected to the common electrode 84. The TFT array substrate further includes a storage capacitor 40 provided at a region where the pixel electrode 22 and the common line 86 overlap, a gate pad 50 connected to each gate line 2, a data pad 60 connected to each data line 4, and a common pad 80 connected to each common line 86.
Each gate line 2 applies a gate signal to a gate electrode 6 of a corresponding TFT 30. Each data line 4 applies a pixel signal to a corresponding pixel electrode 22 via a drain electrode 10 of a corresponding TFT 30. The common lines 86 are oriented parallel to the gate lines 2 and supply a reference voltage to the common electrode 84, enabling the liquid crystal material to be driven.
In response to a gate signal applied from a gate line 2, a TFT 30 charges and maintains a pixel signal, applied to a corresponding data line 4, in the pixel electrode 22. Accordingly, each TFT 30 includes a gate electrode 6 connected to a corresponding gate line 2, a source electrode 8 connected to a corresponding data line 4, and a drain electrode 10 connected to a corresponding pixel electrode 22.
Further, each TFT 30 includes an active layer 14 overlapping the gate electrode 6 and is insulated therefrom by a gate insulating pattern 12. Accordingly, a channel is formed in a portion of the active layer 14 between the source and drain electrodes 8 and 10. An ohmic contact layer 16 is formed on the active layer 14 and ohmically contacts the overlapping data line 4, the source electrode 8, and the drain electrode 10 in addition to an overlaying lower data pad electrode 62 and storage electrode 28.
Each pixel electrode 22 is connected to the drain electrode 10 of a corresponding TFT 30 via a first contact hole 32 formed through a protective film 18. Specifically, the pixel electrode 22 includes a first horizontal part 22a oriented parallel to gate lines 2 and connected to the drain electrode 10, a second horizontal part 22b overlapping the common line 86, and a plurality of finger parts 22c oriented parallel to the common electrode 84 between the first and second horizontal parts 22a and 22b.
Each common electrode 84 is connected to a corresponding common line 86 and is oriented parallel to the plurality of finger parts 22c.
Each storage capacitor 40 consists of the common line 86 and the portion of the storage electrode 28 overlapping the common line 86, wherein the two conductors are separated by the gate insulating film 12, the active layer 14, and the ohmic contact layer 16 therebetween. The pixel electrode 22 is connected to the storage electrode 28 via a second contact hole 26 formed through the protective film 18. Constructed as described above, the storage capacitor 40 allows pixel signals charged at the pixel electrode 22 to be uniformly maintained until a next pixel signal is charged at the pixel electrode 22.
Each gate line 2 is connected to a gate driver (not shown) via a corresponding gate pad 50. Accordingly, the gate pad 50 consists of a lower gate pad electrode 52 and an upper gate pad electrode 58. The lower gate pad electrode 52 is an extension of gate line 2 and is connected to the upper gate pad electrode 58 via a third contact hole 54 formed through the gate insulating film 12 and the protective film 18.
Each data line 4 is connected to a data driver (not shown) via a corresponding data pad 60. Accordingly, the data pad 60 consists of a lower data pad electrode 62 and an upper data pad electrode 68. The lower data pad electrode 62 is an extension of the data line 4 and is connected to the upper data pad electrode 68 via a fourth contact hole 64 formed through the protective film 18.
Each common line 86 is connected to an external reference voltage source (not shown) via the common pad 80 to receive a reference voltage. Accordingly, the common pad 80 consists of a lower common pad electrode 82 and an upper common pad electrode 88. The lower common pad electrode 82 is an extension of the common line 86 and is connected to the upper common pad electrode 88 via a fifth contact hole 74 formed through the gate insulating film 12 and the protective film 18.
Generally, a horizontal electric field is generated between the pixel and common electrodes 22 and 84 when a pixel signal is applied from a TFT 30 to a pixel electrode 22 and when a reference voltage is applied from the common line 86 to the common electrode 84. Specifically, the horizontal electric field is formed between the plurality of finger parts 22c of the pixel electrode 22 and the common electrode 84. The liquid crystal molecules have a particular dielectric anisotropy. Therefore, in the presence of the electric field, liquid crystal molecules rotate to align themselves horizontally between the TFT and color filter array substrates and the color filter array substrate. The magnitude of the applied electric field determines the extent of rotation of the liquid crystal molecules. Accordingly, gray scale levels may be displayed by a pixel area by varying the magnitude of the applied electric field.
Having described the TFT array substrate above, a method of fabricating the TFT array substrate according to the related art four-mask process will now be described in greater detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a first conductive pattern group, including the gate line 2, the gate electrode 6, the lower gate pad electrode 52, the common line 86, the common electrode 84, and the lower common pad electrode 82, is formed on the lower substrate 1 in a first mask process.
Specifically, a gate metal layer is formed over the entire surface of the lower substrate 1 in a deposition technique such as sputtering. The gate metal layer typically includes an aluminum-group metal. The gate metal layer is then patterned using photolithography and etching techniques in conjunction with an overlaying first mask pattern to provide the aforementioned first conductive pattern group.
Referring next to FIG. 3B, the gate insulating film 12 is coated over the entire surface of the lower substrate 1 and on the first conductive pattern group. In a second mask process, semiconductor patterns, including the active layer 14 and the ohmic contact layer 16, and a second conductive pattern group, including the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62, and the storage electrode 28, are provided on the gate insulating film 12.
Specifically, the gate insulating film 12, first and second semiconductor layers, and a data metal layer are sequentially formed over the surface of the lower substrate 1 and on the first conductive pattern group by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering. The gate insulating film 12 typically includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The active layer 14 is formed from the first semiconductor layer and typically includes undoped amorphous silicon. The ohmic contact layer is formed from the second semiconductor layer and typically includes N- or P-doped amorphous silicon. The data metal layer typically includes molybdenum (Mo), titanium (Ti), tantalum (Ta).
A photo-resist film is then formed over the data metal layer and is photolithographically patterned using a second mask pattern. Specifically, the second mask pattern is provided as a diffractive exposure mask having a diffractive exposure region corresponding to a channel portion of a subsequently formed TFT. Upon exposure through the second mask pattern and development, a photo-resist pattern is created wherein a portion of the photo-resist film remaining in a region corresponding to the channel portion has a lower height than portions of the photo-resist film remaining in regions outside the channel portion.
Subsequently, the photo-resist pattern is used as a mask to pattern the data metal layer in a wet etching process and form the aforementioned second conductive pattern group (i.e., the data line 4, the source electrode 8, the drain electrode 10, and the storage electrode 28), wherein the source and drain electrodes 8 and 10 are connected to each other in a region corresponding to the channel portion. Next, the photo-resist pattern is used as a mask to sequentially pattern the first and second semiconductor layers in a dry etching process and form the active layer 14 and the ohmic contact layer 16.
After the active and ohmic contact layers 14 and 16 are formed, the portion of the photo-resist having the relatively lower height is removed from the region corresponding to the channel portion in an ashing process. Upon performing the ashing process, the relatively thicker portions of the photo-resist in regions outside the channel portion are thinned but, nevertheless, remain. Using the photo-resist pattern as a mask, the portion of the second conductive pattern group and the ohmic contact layer 16 arranged in the region corresponding to the channel portion are then etched in a dry etching process. As a result, the active layer 14 within the channel portion is exposed, the source electrode 8 is disconnected from the drain electrode 10, and the remaining photo-resist pattern is removed in a stripping process.
Referring next to FIG. 3C, the protective film 18 is coated over the entire surface of the lower substrate, on the gate insulting film 12, the second conductive pattern group, and the active layer 14. In a third mask process, the first to fifth contact holes 32, 26, 54, 64, and 74, respectively, are formed through the protective film 18.
Specifically, the protective film 18 is formed over the surface of the lower substrate, and on the gate insulting film 12, the second conductive pattern group, and the active layer 14 by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). The protective film 18 typically includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane). A third mask pattern is then arranged over the protective film 18 and the protective film 18 is then patterned by using photolithography and etching processes to thereby define the first to fifth contact holes 32, 26, 54, 64, and 74. The first contact hole 32 is formed through the protective film 18 to expose the drain electrode 10, the second contact hole 26 is formed through the protective film 18 to expose the storage electrode 28, the third contact hole 54 is formed through the protective film 18 and the gate insulating film 12 to expose the lower gate pad electrode 52, the fourth contact hole 64 is formed through the protective film 18 to expose the lower data pad electrode 62, and the fifth contact hole 74 is formed through the protective film 18 and the gate insulating film 12 to expose the lower common pad electrode 82.
Referring next to FIG. 3D, a third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 58, the upper data pad electrode 68, and the upper common pad electrode 88 are formed on the protective film 18 in a fourth mask process.
Specifically, a transparent conductive material is coated over the entire surface of the protective film 18 and in the first to fifth contact holes 32, 26, 54, 64, and 74 by a deposition technique such as sputtering. The transparent conductive material typically includes indium-tin-oxide (ITO), tin-oxide (TO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO). In a fourth mask process, the transparent conductive material is patterned using photolithographic and etching techniques to thereby form the aforementioned third conductive pattern group (i.e., the pixel electrode 22, the upper gate pad electrode 58, the upper data pad electrode 68, and the upper common pad electrode 88).
Accordingly, the pixel electrode 22 is electrically connected to the drain electrode 10 via the first contact hole 32 while also being electrically connected to the storage electrode 28, via the second contact hole 26. The upper gate pad electrode 58 is electrically connected to the lower gate pad electrode 52 via the third contact hole 54, the upper data pad electrode 68 is electrically connected to the lower data pad electrode 62 via the fourth contact hole 64, and the upper common pad electrode 88 is electrically connected to the lower common pad electrode 82 via the fifth contact hole 74.
While the TFT array substrate described above may be formed using a four-mask process that is advantageous over previously known five-mask processes, the four-mask process can still be undesirably complicated and, therefore, costly. Accordingly, it would be beneficial to fabricate a TFT array substrate according to a less complex, and therefore less costly, process.

Liquid crystal display panel of horizontal electronic field applying type and fabricating method thereof


An imaging control terminal includes a wireless communication interface configured to wirelessly communicate with an imaging terminal, an imaging module configured to generate imaging data, a display interface configured to display an image corresponding to the imaging data generated by the imaging module, an operation interface configured to receive an operation of an operator designating an imaging area or an imaging target to be imaged by the imaging terminal for the image, an information generation unit configured to generate imaging area information representing the imaging area or imaging target information representing the imaging target, and a communication control unit configured to cause the wireless communication interface to wirelessly transmit the imaging area information or the imaging target information to the imaging terminal.

Field of the Invention
The present invention relates to technology for remotely controlling an imaging terminal.
Priority is claimed on Japanese Patent Application No. 2013-108222, filed May 22, 2013, the content of which is incorporated herein by reference.
Description of the Related Art
There is an imaging system which includes an imaging terminal (digital camera or the like) having a wireless connection function and an imaging control terminal (portable terminal or the like) and in which the imaging control terminal wirelessly remotely operates the imaging terminal to control an imaging operation of the imaging terminal. For example, an example of a portable terminal which wirelessly remotely operates a digital camera is disclosed in Japanese Unexamined Patent Application, First Publication No. 2012-186698. Specifically, imaging data is transmitted from the digital camera to the portable terminal after the portable terminal has been wirelessly connected to the digital camera and an image captured by the digital camera is displayed on a display unit of the portable terminal receiving the imaging data. In addition, if a user performs a zoom operation on a display screen of the portable terminal when the image captured by the digital camera is displayed on the display unit of the portable terminal, the zoom setting of the digital camera is changed.

Imaging control terminal, imaging system, imaging method, and program device


A valve assembly (100) is provided. The valve assembly (100) comprises a housing (101) with a plurality of fluid ports (102-105d). The housing (101) includes an actuator chamber (107) configured to receive a fluid. The housing (101) also includes a valve chamber (108) configured to receive the fluid after flowing through the actuator chamber (107). The valve assembly (100) further includes one or more shape memory alloy elements (109a-109d) located within the actuator chamber (108). One or more valve seals (220a-220d) located within the valve chamber (108) are provided. The shape memory alloy elements (109) are coupled to each of the valve seals (220a-220d) to selectively move the valve seals (220a-220d) between a first position and a second position upon heating the corresponding shape memory alloy element (109a-109d) above a transformation temperature.

Fluid handling devices are well known. One type of fluid handling device is an electrically-actuated valve. Electrically-actuated valves are used in a variety of situations to control various types of fluids. Often, electrically-actuated valves are implemented where relatively fast response times are desired or where a fluid-actuated valve cannot be implemented or is not desired. In order for an electrically-actuated valve to be effective and efficient, it should consume minimal power, operate with low noise, and be cost effective to manufacture. In many applications, it is also important that the electrically-actuated valve provide an accurate and consistent fluid distribution.
One type of an electrically-actuated valve that attempts to meet the above criteria is a solenoid valve. Solenoid valves however, are typically limited in size, and in order to obtain adequate performance, a solenoid valve typically consumes a substantial amount of power. The power consumption of a solenoid valve, in some circumstances, is unacceptable. Furthermore, in some applications, it may be desirable to retain the valve in a specific open or mid-point position. If this position requires continuous actuation of the solenoid, the valve will likely consume a substantial amount of power thereby increasing the cost associated with operating the valve. In addition, solenoid valves are often expensive, large, and sometimes create an audible clicking noise as they are actuated that may be undesirable. Furthermore, the electromagnetic field generated by the solenoid valve can present problems in certain environments.
Another solution has been the use of shape memory alloys that transform shape and/or size when heated. Shape memory alloy actuated valves provide an advantage over the previously mentioned prior art solution as they can typically be manufactured smaller and generally consume less power. However, the valves have suffered in certain high temperature environments in the prior art due to a slower response time. For example, in a plunger type valve, the shape memory alloy element may be heated above its transformation temperature by passing an electrical current through the shape memory alloy element to raise the plunger against the force of a spring. In order for the plunger to return to its previous position, the shape memory alloy element must cool below its transformation temperature to allow the spring to once again seat the plunger. Because the valve cannot return to its original position until after the shape memory alloy element has cooled, shape memory alloy actuated valves have been limited in the environments they are suitable to be used. For example, until now, the valves could not be used in heated environments or be used to control heated fluids, i.e., fluids at a temperature near or above the transformation temperature. The heat from the fluid did not allow the shape memory alloy elements to cool below the transformation temperature within an acceptable time.
In an effort to overcome this problem, prior art solutions have attempted to cool the shape memory alloy elements using a cooling fluid. For example, U.S. Pat. No. 6,691,977 and U.S. Pat. No. 7,657,965 disclose shape memory alloy actuated valves that flow the fluid being controlled past the shape memory alloy elements as the fluid flows through the valve. However, both of these approaches are implemented in environments where the fluid being controlled is relatively cold, i.e., well below the shape memory alloy element's transformation temperature, to provide sufficient cooling to the shape memory alloy element. In addition, each approach provides a single inlet with a single outlet. In other words, the approaches do not allow for multiple outlets that can be coupled to various components.
Due to the above-mentioned problems, there exist certain applications that shape memory alloy actuated valves have been avoided due to the heat of the fluid being controlled. One example is in coffee machines that dispense hot water, steam, etc. In these applications, the heat of the water or steam is well above the shape memory alloy's transformation temperature. Therefore, shape memory alloy actuated valves were avoided in such situations because the temperature of the water prevented the elements from cooling below the transformation temperature at a sufficient speed.
The embodiments described below have overcome these and other problems and an advance in the art is achieved. The embodiments provide a shape memory alloy actuated valve that is cooled by the fluid being controlled. In some embodiments, the valve is cooled by the fluid prior to heating the fluid. Therefore, in this embodiment, the fluid being controlled flows by the shape memory alloy elements at a first temperature, is heated, and flows through the valve at a second temperature, which is higher than the first temperature. Therefore, the presently described embodiments cool the shape memory alloy elements even when the valve is used to control a heated fluid.

Fluid cooled shape memory alloy actuated valve


The present invention is an in-train information display apparatus that displays, to a passenger, advertisement content delivered from an advertisement-content delivering apparatus, and includes a display unit configured to display the advertisement content, a display monitoring unit configured to photograph a video screen displayed on the display unit, and a display-result determining unit configured to calculate color-related information, which is information concerning a color of the video screen, based on an image photographed by the display monitoring unit, determine, based on the calculated color-related information and reference information for display result determination, which is information concerning a color of the advertisement content normally displayed on the display unit, whether the display of the advertisement content is normally performed, and transmit, as information for display achievement calculation, a result of the determination to the advertisement-content delivering apparatus having a totalizing function.

In railway systems in recent years, a service for providing passengers with advertisement information including moving images and the like (hereinafter described as advertisement content) using display apparatuses set in cars of a train has been generally adopted.
In reproducing the advertisement content, a railway company performs the reproduction according to, for example, contents of an agreement with an advertiser. The agreement contents include, for example, a period and a time frame for providing passengers with the advertisement content and a total reproduction time and the number of times of reproduction of the advertisement content.
Taking into account the purpose of a company or the like to be an advertiser, i.e., the fact that the company or the like becomes the advertiser for the purpose of realizing profit improvement such as sales promotion of products of the company or the like, in order to accurately learn cost effectiveness of advertisement content provision to train passengers, it is desirable that achievement result such as date and time when the advertisement content is reproduced and the number of times of the reproduction is provided from the railway company to the advertiser. This is because, although the advertisement content is provided, when an expected effect is not obtained or when an effect fades in, the advertiser considers it necessary to take measures for, for example, changing details of the advertisement content or reviewing the agreement contents to change the time frame for reproducing the content and the number of times of the reproduction, a counter value to be paid, and the like.
Patent Literature 1 describes a technology for realizing effective commercial (advertisement content) broadcasting. According to the technology described in Patent Literature 1, a company charges an advertiser for broadcasting according to broadcasting achievement data of a broadcasted CM. Therefore, the advertiser can pay only a counter value for the actual broadcasting of a commercial and reduce useless expenditure.

In-train information display apparatus, in-train information display system, and advertisement display result determining method


Vehicle structures for dissipating and distributing energy associated with a collision are described herein. In one embodiment, a vehicle includes a side support extending in a vehicle longitudinal direction, a rocker support extending in the vehicle longitudinal direction, where the rocker support is positioned outboard of the side support in a vehicle lateral direction, a torque box extending in the vehicle lateral direction, a dash panel coupled to the torque box, where the dash panel comprises an engine room barrier portion extending upward from the torque box and a floor attachment portion extending downward from the torque box, and a reinforcement member positioned between the side support and the rocker support, where the reinforcement member is spaced apart from the side support and the rocker support, and where the reinforcement member is coupled to the engine room barrier portion and the floor attachment portion of the dash panel.

Vehicles may be equipped with bumper systems and crash protection structures that elastically and plastically deform to absorb energy in the event of a collision.
In one example, a substantial portion of energy from an impact with a small front bumper overlap may be directed outboard of many of the energy absorbing structures of the vehicle and may be directed into a front wheel, which causes the front wheel to be directed in a generally rearward direction. Because a substantial portion of the energy from the impact is directed into the bumper assembly at a position that is outboard of many of the energy absorbing structures of the vehicle, the energy from the impact may not be absorbed or may only be partially absorbed by those energy absorbing structures of the vehicle. The unabsorbed energy may be directed into a front wheel and transferred rearward along the vehicle as the front wheel contacts vehicle structures proximate to a passenger cabin of the vehicle.
Accordingly, a need exists for alternative structures for transferring energy and absorbing energy from a small front bumper overlap collision.

Vehicles having a dash panel reinforcement member

Toyota Motor Engineering & Manufacturing North America, Inc.


The present invention relates to an end cap for terminating a transmission cable containing at least one transmission line, the end cap comprising at least one lead-through opening for guiding the at least one line from a rear side to a front side of the end cap. Further, the invention relates to a terminating arrangement terminating a transmission cable containing at least one transmission line. Moreover, the invention relates to a kit for a terminating arrangement for terminating a transmission cable. In order to facilitate the termination of a transmission cable, the present invention provides that a passage extending from the rear side to the front side is formed at the end cap, the passage being adapted for accommodating a central strength member of the cable.

The present invention relates to a terminating arrangement for terminating a transmission cable containing at least one transmission line.
Terminating arrangements are known from the prior art. The end caps constitute terminating members which facilitate the affixing of an end section of a cable, e.g. in an enclosure, and the guiding of at least one line so that it may be handled and e.g. provided with an optical fibre connector.
For example, the cable may be an optical fibre cable and the transmission line may be an optical fibre. Optical fibres may come as units comprising a fibre element with several individual fibres. The fibres may be bundled to bundles comprising several fibres. Such a bundle or several bundles may be accommodated within a cable. As the fibres themselves are rather long and thin and therefore prone to damage, e.g. by snapping and cracking, it is desired to provide a strain relief in order to eliminate any stresses which could act on the fibres themselves.
According to the prior art, strain relief is commonly achieved in that the layer of Kevlar surrounding each line, e.g. fibre or bundle of fibres, is affixed to the end cap or terminating member. Alternatively, cables with a central strength member in the form of a rod running centrally through the cable may be used. Then, instead of the layer of Kevlar, the strength member is fixed to a terminating member or enclosure. Additionally, the line has to be affixed within the enclosure, e.g. with the help of additional means such as adapters. In other words, two separate actions are necessary for terminating the cable according to the prior art. Hence, both when using the Kevlar layer surrounding the line or optical fibres and the central rod as strength members, terminating the cable so that strain relief is achieved is cumbersome and time-consuming.
In view of the disadvantages arising from the possibilities for terminating an optical fibre cable according to the prior art as mentioned above, it is an object of the present invention to facilitate and expedite the procedure of terminating an optical fibre cable while providing strain relief.
This object is achieved according to the invention for the initially mentioned end cap in that the end cap is provided with a passage extending from the rear side to the front side, the passage being adapted for accommodating a central strength member of the cable. In other words, the end cap may constitute a terminating member or a terminating member may be formed as an end cap, wherein the passage provides a channel which is offset at least in a radial direction of the end cap with respect to the lead-through opening.
For the initially mentioned terminating arrangement, the object is achieved in that at least one end cap according to the present invention is applied to the cable, wherein the at least one line extends through the lead-through opening and the strength member of the cable extends through the passage of the end cap.
For a kit mentioned in the beginning of the description, the object is achieved in that the kit comprises at least one end cap according to the present invention.
These solutions have the decisive advantage over the prior art that, on the one hand, the end cap may accommodate and protect an end section of the cable as well as the line and, on the other hand, may accommodate the strength member so that strain relief is provided. The end cap may be easily applied to the cable and the strength member by sliding the end cap over the cable while leading the line and the strength member through the through-opening and the passage, respectively. Then, the end cap may be fixed to an enclosure, thus serving as an adapter for mounting the strength member and the line to the enclosure in a single step.
Further, by the inventive solution to the object, any additional cable jackets and overmoulds for securing as well as protecting the end section of the cable may be omitted. Retention forces for securing the end cap and providing strain relief may be transferred from the section of the strength member protruding from the front side via the end cap to the outer circumference of the cable arranged at the rear side. Hence, the retention forces of the strength member are transferred to the outside of the cable at a position where normally a cable jacket is fixed. This enables the solution according to the present invention to be applied also to standard cable glands which are commonly used in field install kits.
The above-mentioned solutions according to the present invention may be combined in any way with any one of the following advantageous embodiments of the present invention respectively and thus further improved.

Arrangement for terminating a transmission cable


A back scratching device is disclosed including a frame body and a back scratching pad. The frame body is operable to be removeably mounted to a wall surface and includes a base having a first end and a second end, a first flex mechanism attached to the first end of the base, the first flex mechanism operable to be flexed outward from the first end of the base from a resting position to a wall clearing position, and a second flex mechanism attached to the second end of the base, the second flex mechanism operable to be flexed outward from the second end of the base from a resting position to a wall clearing position. The first and second flex mechanisms are each operable to move from the wall clearing position to a clutching position for mounting the frame body to the wall surface. The back scratching pad is attached to the base of the frame body and includes an abrasive contact surface.

A variety of back scratching devices have been known in the art. Many back scratching devices are hand-held and have long handles that enable a user to scratch hard to reach areas of their backs. Alternatively, some back scratching devices are attached to wall surfaces using various attachment mechanisms such as screws, adhesive strips, and suction cups. However, more permanent fasteners such as screws and adhesive strips can cause damage to the wall surface and are not easily portable and unable to be used in a variety of locations around the house. Further, back scratching devices using suction cups are generally only able to be used in bathrooms where the wall surface is very smooth (e.g., glass or tile), and the device is generally ineffective as it is easily removed from the wall surface during use. What is needed is a hands free back scratching device that is easily and securely mounted to a wall surface without causing damage to the wall surface.


A coated paper sheet provided with a coating layer formed on a paper sheet substrate and containing a pigment and a binder and optionally a pre-coated polyacrylamide-containing anionic acrylic resin layer formed between the substrate and coating layer, and having a 75° specular gloss of 70% or more, an air permeability of 4000 seconds or less, a Clark stiffness, in terms of critical strength L, of 12 cm or more in a cross direction and an internal bond strength of 200 mJ or more, exhibits high resistance to blistering, excellent printer-passing property, and high quality image-recording property and useful for both of offset printing and electrophotographic duplicating or printing.

(1) Field of the Invention
The present invention relates to a coated paper sheet. More preferably, the present invention relates to a coated paper sheet having a high gloss, a high Clark stiffness determined in a cross direction (CD) of the sheet and being free from generation of blistering on the sheet when subjected to offset printing or full color printing by, for example, an electrophotographic printing system, and thus exhibiting an excellent passing property through the printing system and a superior capability of being printed with printed images having high quality, namely high clarity and sharpness.
(2) Description of the Related Art
Currently, due to a strong demand of full color printing, high speed printing and high image quality printing, a large amount of coated paper sheets are consumed in the printing and publishing business. Particularly, in the field of on-demand-printing, there is a significant trend of preparing various publications, which have been prepared by the conventional printing method, by a color copying machine or a color printer which can relatively easily respond to a small order. Also, application of coated paper sheets having a high white gloss, in place of conventional paper sheets for plain paper copiers (PPC) and for printers, to electrophotographic copiers and printers, are now increasing.
To respond to the above-mentioned trend, the coated paper sheets for the on-demand publishing must provide sufficient aptitude both for off-set press and for electrophotographic copying machine and printers. For the off-set press, the recording sheets must have a high surface strength (toughness) and a high blister resistance. Also, for electrophotographic full color copying machine and printers, the recording sheet must have a high stiffness and a high blister resistance. Further, to prepare high grade printing, the recording paper sheet is required to have an improved stiffness, because conventional coated paper sheets having a high white gloss are unsatisfactory for high grade printing.
Generally, the coated paper sheet having a high white gloss are produced by coating a substrate paper sheet with a coating containing a white pigment having an average particle size of 2 μm or less, in a dry solid amount of 10 g/m2 or more per surface of the sheet, and smoothing the coating layer surface by calendering. In this case, it is known that the coated paper sheets having a high white gloss is compressed by the calendering and thus the stiffness of the coated paper sheets decreases.
Further, in view of various social requirements due to developments in movements for conservation of natural resources and protection of natural environment and other requirements to decrease a load of consumers on transportation of the prints, and to scale-down of the space for storing the prints in home and library, it is expected that the mass of the recording paper sheets will be further decreased. However, generally speaking, the decrease in mass of the paper sheets causes the thickness and stiffness of the paper sheets to be decreased and thus a problem, that the printed products appear to be a low grade and a difficulty in turning over the leaves of printed products and in reading the printed products increases, occurs.
In the offset sheet press or the electrophotographic copying machine or printer, the stiffness of the paper sheets greatly influences on the passing property of the paper sheets through the printer, and thus it is severly controlled as an important quality item. Especially, in the electrophotographic copying machine and printer, when a paper sheets having a low stiffness are employed, the paper sheets may sometimes be fed irregularly into the printer, are not smoothly passed through the printer and may block the delivery from the printer.
As one way of enhancing the stiffness of the coated paper sheet, the substrate paper sheet is produced from a mechanical pulp which contributes to enhancing the stiffness of the substrate paper sheet and thus of the resultant coated paper sheet. However, the use of the mechanical pulp causes the resultant coated paper sheet to exhibit a low smoothness and a reduced whiteness and it appears to be a low grade. Also, when a chemical pulp produced mainly from soft woods, for example, NBKP is used in a major proportion to produce the paper sheet substrate, the resultant paper sheet exhibits a high stiffness. However, the air permeance of the resultant paper sheet is undesirably increased.
It has been attempted to increase the stiffness of the paper sheet by make the paper sheet bulky. The bulkiness of the paper sheet can be increased by increasing the freeness of the pulp, by reducing the pressure of a wet press or by reducing the pressure of calendering. However, while the increase in bulkiness contributes to enhancing the stiffness of the resultant paper sheet, the resultant paper sheet has a porous inside structure and a low smoothness. When the porous paper sheet is coated with a pigment-containing coating liquid, a great portion of the coating liquid permeates inside the porous paper sheet, and thus the coverage of the coating liquid over the surface of the porous paper sheet decreases. Therefore, after drying, the resultant coated paper sheet is unsatisfactory due to a low gloss and a low uniformity of the gloss. The coated paper sheet having an insufficient gloss must be smoothed by calendering under increased pressure. Thus, the resultant calendered paper sheet exhibits an increased compressive modulus and a greatly decreased stiffness.
Generally, it is known that when an attempt is made to improve the quality of printed images by enhancing the gloss of the paper sheet, the resultant paper sheet has a low stiffness and thus exhibits a poor passing property through the printer. To solve this problem, Japanese Unexamined Patent Publication No. 5-341,553 discloses an attempt to solve the problem of the poor passing property of the paper sheet by controlling a basis mass of the paper mass in the range of from 75 to 95 g/m2.
Further, in the production of a coated paper sheet having a high white gloss, an application of a calendering treatment causes the paper sheet substrate and the coating layer of the calendered coated paper sheet to respectively exhibit increased densities and the resultant coated paper sheet to exhibit a significantly decreased air permeance. In the case where the coated paper sheet having the low air permeance is subjected to a printing procedure using an offset press or an electrophotographic copying machine or printer, a problem such that when the printed ink images are dried or the toner images are heat-fixed, blisters are generated in the coated paper sheet, occurs. The bisters generated in the coated paper sheet are classified into macro-blisters and micro blisters. The macro-blisters are generated by deforming the substrate and the coating layer due to expansion of water contained in the substrate. The macro-blisters are formed in the image-printed portions of the coated paper sheet. The micro-blisters are fine bisters generated in the image-printed portions of the coated paper sheet due to expansion of water vapor generated between the coating layer and the ink or toner images printed on the coating layer. The micro-blisters cause a decrease in gloss of the printed coated paper sheet.
As a general countermeasure to macro-bister generation, there is a method of preventing the breakage of the paper sheet substrate by enhancing the internal bond strength of the substrate. As a method of enhancing the internal bond strength of the substrate, an employment of pulp fibers prepared under an intensified beating condition and having a high bonding strength to each other to form the paper sheet substrate, a coating or impregnating of the paper sheet substrate with a resin and a mixing of a paper strength-enhancing agent into the paper sheet for the substrate, are effectively utilized. However, the use of the pulp fibers produced under a intensified beating condition and the impregnation or coating with a resin contribute to enhancing the internal bond strength of the paper sheet substrate, but cause the air permeance of the paper sheet substrate to decrease. Therefore, these measures can control only the generation of macro-blisters but not of micro-blisters. As a measure of mixing the paper strength-enhancing agent into the paper-forming pulp slurry, Japanese Unexamined Patent Publication No. 3-227,491 discloses mixing a polyacrylamide-compound-containing paper strength-enhancing agent into a paper-forming pulp slurry. In this case, however, when the paper strength-enhancing agent is mixed in too large an amount, flocks are generated in the pulp slurry. Therefore, in order to maintain the process conditions and the uniformity of the resultant paper sheet at high level, the paper strength-enhancing agent must be employed in a limited amount.
Thus, it is difficult to obtain a satisfactory effect on the prevention of the generation of blisters by the use of a paper strength-enhancing agent.
To prevent the generation of the micro-blisters, an increase in the air permeance of the coating layer is considered effective. However, in the coating layer, the higher the air permeance, the lower the white gloss. Accordingly, the conventional coated paper sheet having a high white gloss exhibits an insufficient resistance to micro-blister generation.
As Japanese Unexamined Patent Publication No. 11-174,713 discloses, it is known that, when coated paper sheets having a high white gloss are printed by an offset sheet press or electrophotographic copying machine or printer, particularly in high humid circumstances and, for example, in a rainy season, a closed package of the coated paper sheets is opened and the coated paper sheets are subjected to printing, immediately after the start of printing, misfeeding of a plurality of superposed paper sheets, or blocking of the paper sheet delivery, often occur. The reason of the above-mentioned problem is assumed to be that the coated paper sheets with a high white gloss have a high smoothness and thus are easily adhered to one another, and the surface tension and hydrogen bond of water absorbed in the coating layers of the coated paper sheets cause the coated paper sheets to be adhered one another, and the increased static friction coefficient between the coated paper sheets adjacent to each other, which friction prevents the smooth passing of the coated paper sheets through the printer, increases.
As stated above, when subjected to an offset printing procedure or an electrophotographic full color copying machine, the coated paper sheet having a high 75 degrees specular gloss of 70% or more and a basis mass of, for example, 70 to 90 g/m2 and further exhibiting both a high resistance to blistering and an excellent passing property through the printer or copying machine during the printing procedure have not yet been provided, in practice.


Systems for providing driving voltage of display panels. An exemplary system comprises a data driving circuit with a plurality of driving units generating analog voltage to drive corresponding pixels according to digital data signals from a data bus, each comprising a temporary storage unit storing N digital data in sequence according to N control signals in a first period and outputting the N digital data in sequence according to M switching signals in a second period; a digital-to-analog (DA) conversion unit converting the N digital data to N analog voltages in sequence; an analog buffering unit buffering the N analog voltages from the DA conversion unit; and a de-multiplexer outputting the N analog voltages to the corresponding pixels selectively according to an enabling signal.

1. Field of the Invention
The invention relates to display panels.
2. Description of the Related Art
Liquid crystal displays (LCDs) are used in a variety of applications, including calculators, watches, color televisions, computer monitors, and many other electronic devices. Active-matrix LCDs are a well known type of LCDs. In a conventional active matrix LCD, each picture element (or pixel) is addressed using a matrix of thin film transistors (TFTs) and one or more capacitors. The pixels are arranged and wired in an array having a plurality of rows and columns.
To address a particular pixel, the switching TFTs of a specific row are switched "on" (i.e., charged with a voltage), and then data voltage is sent to the corresponding column. Since other intersecting rows are turned off, only the capacitor at the specific pixel receives the data voltage charge. In response to the applied voltage, the liquid crystal cell of the pixel changes its polarization, and thus, the amount of light reflected from or passing through the pixel changes. In liquid crystal cells of a pixel, the magnitude of the applied voltage determines the amount of light reflected from or passing through the pixel.
Further, "System-on-glass" LCDs that allow integration of various LCD driving circuits and functions require no external integrated circuits (ICs), providing low cost, compact and highly reliable displays. The integrated driving circuits of such an LCD comprise a vertical driving circuit selecting a row of pixels and a horizontal driving circuit writing display data into each pixel in the selected row.
As shown in FIG. 1A, because of design-rule limitations in low temperature polysilicon (LTPS) processes, conventionally double RGB pixel pitch (2PP) is required to contain a set of RGB analog buffers and RGB digital to analog converters (DACs) for each RGB pixel. For example, the sampling latches may sample the data signals from the digital data bus DDB according to the control signal provided by a horizontal shift register, and the sampled data in the sampling latches is output to corresponding holding latches according the enabling signal OE. The held data signal in the holding latches are converted to RGB analog signals and output to a corresponding pixel through corresponding RGB analog buffers. Thus, a display panel requires two horizontal driving circuits disposed on the upper and lower area of the frame area respectively, as shown in FIG. 1B. However, this occupies a lot of layout area, such that panel frame size is enlarged. Moreover, in order to divide data signals from the host system for the two horizontal driving circuits, a data processing circuit 33 is further required, as shown in FIG. 1B.
As shown in FIG. 2A, another horizontal driving circuit reduces required area, with the operation timing chart thereof shown in FIG. 2B. As shown, the sampling latches sample the RGB data signals from the digital data bus DDB according to the control signal provided by the horizontal shift register, and the sampled data in the sampling latches output to corresponding holding latches according to enabling signal OE. According to the data enabling signal DE and the de-multiplexers, R data signals, G data signals, and B data signals held in the holding latches are converted to RGB analog signals by one DA converter in sequence and output to corresponding RGB pixels through one analog buffer. Namely, one DA converter and one analog buffer are shared for RGB pixels, thereby reducing required layout area for horizontal driving circuits. However, this also requires double RGB pixel pitch (2PP) for each RGB pixel driving circuit, because the sampling and holding latches dominate the width of layout of the RGB pixel driving circuit.

Systems and methods for providing driving voltages to a display panel


A data recording and reproducing apparatus for recording and reproducing video signals in a plurality of formats with different rates to/from a record medium is disclosed. In the data recording and reproducing apparatus, a video signal in a selected format is converted into video data packets and audio data packets whose lengths are optimally designated corresponding to the selected format. With a video data packet and an audio data packet, a video sync block and an audio sync block whose lengths are different are formed, respectively. The video sync block and the audio sync block are encoded with respective error correction codes. The resultant data is recorded as record data to a record medium.

1. Field of the Invention
The present invention relates to a data recording apparatus, a data recording method, a data recording and reproducing apparatus, a data recording and reproducing method, a data reproducing apparatus, a data reproducing method, a data record medium, a digital data reproducing apparatus, a digital data reproducing method, a synchronization detecting apparatus, and a synchronization detecting method that are used for recording and/or reproducing a digital video signal and a digital audio signal.
2. Description of the Related Art
A data recording and reproducing apparatus that records a digital video signal and a digital audio signal to a record medium and that reproduces a digital video signal and a digital audio signal therefrom is known. A typical example of such an apparatus is a digital VTR (Video Tape Recorder). In a record processing portion of a digital video signal recording apparatus, digital video data and digital audio data are placed packets with a fixed length. ID information is added to each packet. The packetized data is encoded with an error correction code. A synchronous pattern and ID information are added to packetized data, an error correction code parity, and so forth so as to form a sync block. A plurality of sync blocks are grouped as a sector corresponding to each data type. Each sector as serial data is recorded on a magnetic tape by a rotating head. The length of each sync block in the same sector is the same. The sync blocks are successively assigned unique ID numbers. The ID information has the same value. A product code is used as an error correction code. In other words, a two-dimensional array of data symbols is encoded with an outer code in the vertical direction and an inner code in the horizontal direction. Thus, each symbol is dually encoded. One minimum data encoding/decoding unit of the product code is referred to as ECC block.
On the reproducing side, the start position of each sync block is detected with a synchronous signal. Packets in each sync block are rearranged corresponding to ID numbers and ID information. Since a unique synchronous pattern is added at the start position of each sync block, using the bit sequence of the synchronous pattern, the pattern occurrence interval, successive ID numbers in the same sector, and the same ID information, the phase of a synchronous block can be detected. In other words, when the conditions that the bit sequence of a synchronous pattern matches a fixed pattern, that the same pattern is detected at a position delayed by the block length, and that the block ID is proper are satisfied, the phase of the synchronous block is detected. In the format of such a conventional digital VTR, to easily perform the synchronization detecting process, the length of each synchronous block is fixed (to one type) regardless of the data type.
To record and reproduce video data, a compression encoding process is performed. When video data corresponding to MPEG (Moving Picture Experts Group) standard is compression-compressed, coefficient data generated by DCT (Discrete Cosine Transform) process is encoded with a variable length code. When the amount of data that is recorded per track or every a predetermined number of tracks is fixed, the data amount of the variable length code that is generated in a predetermined time period is limited to a predetermined value. Variable length code encoded data (namely, variable length data) is packed in data areas of a plurality of sync blocks corresponding to a predetermined time period.
The data amount of a digital audio signal is not so large in comparison with that of a digital video signal. To prevent the audio quality from deteriorating in the compressing process and to prevent a complicated process because the data access unit of an MPEG audio signal does not match a video frame and a video signal and an audio signal are switched, non-compressed audio data (linear PCM) is recorded and/or reproduced.
There are as many as 18 types of digital television broadcasting formats in the United States. In such an environment, a digital VTR that can record and reproduce video data in a plurality of formats is desired. When the length of each sync block is fixed to one type regardless of data types as with the conventional digital VTR, although synchronization is easily detected, it is difficult to record data in various formats. Next, this point will be described.
Next, an example of the conventional digital VTR will be described. The VTR records video data and audio data on a tape in a tape format as shown in FIG. 1A. As shown in FIG. 1A, data of six tracks is recorded per frame. One segment is composed of two tracks with different azimuths. In other words, six tracks are composed of three segments. A pair of tracks that compose one segment are assigned track numbers [0] and [1] corresponding to the azimuths. Video sectors are formed on both edges of each track. Video data is recorded on the video sectors. An audio sector is formed between the two video sectors. Audio data is recorded on the audio sector.
In the track format shown in FIG. 1A, audio data of four channels can be handled. Referring to FIG. 1A, A1 to A4 represent sectors of channels 1 to 4 of audio data, respectively. The video data is shuffled (interleaved) and recorded on sectors on the upper side and the lower side. A system area (sys) is formed at a predetermined position of each video sector on the lower side. In FIG. 1A, SAT1(Tr) and SAT2 (Tm) are areas in which a servo lock signal is recorded. In addition, gaps (Vg1, Sg1, Ag, Sg2, Sg3, and Vg2) with predetermined sizes are formed between individual record areas.
As shown in FIG. 1B, data recorded on the tape is composed of a plurality of blocks that are equally divided (these blocks are referred to as sync blocks). FIG. 1C shows an outlined structure of one sync block. One sync block is composed of an ID (that identifies the current sync block), a DID (that represents the contents of data that follows), a data packet, and an error correction inner code parity. Data is recorded and reproduced as sync blocks (the minimum data recording/reproducing unit is one sync block). For example, a video sector is composed of many sync blocks that are arranged.
One sync block is composed of a synchronous signal, an ID, a data packet, and an inner code parity. Now, one sync block is denoted by                sync block: sync pattern+sync id+data packet        +inner parity.        Design condition: The length of one data packet of video data is the same as the length of one data packet of audio data.
Next, as an example of the recording process of video data, the following video data and conditions are considered.                Video data (4:2:2)        Design conditions: Data compression ratio=2 or more (the data amount after data compressing process is ½ or less of the data amount before data compressing process).        10 DCT blocks are packed to two sync blocks.        6 tracks per field.        [525 lines/60 fields] format video signal
Amount of video data per field:                512×720×(8+4+4) bits/8/2=368640 bytes
Number of DCT blocks per field:                512×720/8/8=5760
10 blocks/2 syncs/→1152 sync blocksLength of data packet>368640×(1/2)/1152=160   (1)                [625 lines/60 fields] format video signal
Amount of video data per field:                608×720×(8+4+4) bits/8/2=437760 bytes
Number of DCT blocks per field:                608×720/8/8=6840
10 blocks/2 syncs/→1368 sync blocksLength of data packet>437760×(1/2)/1368=160   (2)
An example of the recording process for audio data is as follows:                Audio data (24 bits, 48 kHz sampled)        Design condition: Non-compression        AUX data: 6 bytes per field
Number of samples per field in [525/60] format:                48 k/59.94 Hz×24 bits/8=2402.4 bytes                    (5 field sequence)                        AUX data of 12 bytes→2415 bytes (total data amount)        Number of samples per field in [625/50] format:                    48 k/50 Hz×24 bits/8=2880 bytes                        AUX data of 12 bytes→2892 bytes (total data amount)
To determine the optimum sync block length of audio data, the products of data packet lengths (162 and 163) and the numbers of sync blocks are obtained as follows.
15161718161:2415257627372898162:2430259227542916
Now, it is defined that the video compression rate is the ratio of the data amount of video data that has been compressed and the data amount of original video data. The data packet length is selected so that the video compression rate becomes 2 or more. The data packet length of which the excessive record area of audio data in both the [525] format and [625] format is 161. However, since each audio sample is composed of 24 bites (3 bytes), the data packet length should be a multiple of 3. Thus, the data packet length should be 162. Consequently, in the digital VTR format, the data amounts are defined as follows.                [525/60] format video data: 162×1152=186624 bytes                    audio data: 162×15=2430 bytes                        [625/50] format video data: 162×1368=221616 bytes                    audio data: 162×18=2916 bytes
Error correction outer code parity data is added to each of video data and audio data. The number of outer code parities added to video data is 10% thereof. The number of outer code parities added to audio data is 100% thereof. (In other words, the number of audio symbols is the same as the number of parities.) Since the circuit scale largely depends on the number of parities, the maximum number of parities is limited to 14. In addition, the number of tracks per field is 6. Thus, the sum of the number of data blocks and the number of outer code parities should be divided by 6. In the case of video data, two ECC blocks are formed on one track.
[525/60] format video data                1152=(96×2)×6→Number of outer code parities                    =10                        2 ECC blocks per track        Number of data blocks per track+number of outer code                    parities=(96+10)×2=212
[625/50] format video data                1368=(114×2)×6→Number of outer code parities                    =12                        2 ECC blocks per track        Number of data blocks per track+number of outer code                    parities=(114+10)×2=248
In the case of audio data, one ECC block is formed in one field.
[525/60] format audio data
15=(5×3)→Number of outer code parities=5
3 ECC blocks per field                Number of data blocks per track+number of outer code                    parities=(15+15)/6=5.                        Number of bytes in unnecessary record area per CH                    =21 bytes/field
[625/50] format audio data                18=(9×2)→Number of outer code parities=9        2 ECC blocks per field        Number of data blocks per track+number of outer code                    parities=(18+18)/6=6                        Number of bytes in unnecessary record area per CH                    =30 bytes/field
An ID (2 bytes), a block synchronous signal (sync pattern) (2 bytes), and an inner code parity (14 bytes) are added to each data packet and thereby a sync block (180 bytes each) is formed as record data. Thus, video data and audio data are recorded as sync blocks on a tape. The decoder detects the beginning of each sync block with the synchronous signal, corrects an error thereof with an inner code, separates each sync block into a video sync block or an audio sync block with a video/audio data identification flag recorded in the ID, corrects an error of each of a video sync block and an audio sync block with an outer code, and decodes the video sync block and audio sync block to video data and audio data.
Each sync block of video data and each sync block of audio data are structured so that the length of the former is the same as that of the latter. Thus, the beginning of each sync block can be easily detected. FIGS. 2A and 2B show ECC block structures of a conventional digital VTR. FIG. 2C shows the structure of one sync block. FIG. 2A shows the structure of a video ECC block. FIG. 2B shows the structure of an audio ECC block. As shown in FIG. 2C, the length of each video sync block is 180 bytes. The length of each audio sync block is 180 bytes. Thus, the length of each video sync block is the same as the length of each audio sync block. In the [625/50] format and [525/60] format, one video ECC block (FIG. 2A) is structured in such conditions that the number of blocks per frame is 12, that the number of heads is 4, and that the number of tracks per frame is 6. In the [625/50] format, one audio ECC block (FIG. 2B) is structured in such conditions that the number of blocks per frame is 1, that the number of heads is 4, and that the number of tracks per frame is 6. In the [525/60] format, one audio ECC block is structured in such conditions that the number of blocks per frame is 1, that the number of heads is 4, and that the number of tracks per frame is 6.
FIGS. 3 and 4 show the relation between an audio ECC block and audio samples. FIG. 3 shows the arrangement of samples in the case that the field frequency is 50 Hz. FIG. 4 shows the arrangement of samples in the case that the field frequency is 59.94 Hz. In FIGS. 3 and 4, audio sample numbers starts from the beginning of the current field. AUX is system data that represents the contents of audio data. The arrangement of samples and the structure of one ECC block in the [525/60] format (FIG. 3) are different from those in the [625/50] format (FIG. 4). Thus, the audio encoder and the audio decoder each require a circuit that changes a process corresponding to a selected mode.
Next, a multi-rate format will be considered. In the format that the video rate of the conventional VTR format is decreased by 3, in formulas (1) and (2), when ½ is substituted with ⅓, the length of each data packet becomes 107. On the other hand, when the length of each audio data packet is the same as the length of each video data packet, since the length of each video data packet should be a multiple of the number of audio samples (3 bytes), the length of each video data packet becomes 108.
The data amount of audio data per field is 2415 bytes in the [525/60] format and 2892 bytes in the [625/50] format. Thus, in the [525/60] format, the data amount of audio data per field becomes 108×3=2484 bytes. In the [625/50] format, the data amount of audio data per field becomes 108×27=2916 bytes.
Combinations of the data packet length (108 bytes) and the number of sync blocks (the product thereof represents the total data amount) are for example:
22232425262728108:2376248425922700280829163024
Next, the structure of each ECC block will be considered. In the case of video data, two ECC blocks are formed per track.
[525/60] format video data                1152=(96×3)×4→Number of outer code parities                    =10                        3 ECC blocks per track        Number of data blocks per track+number of outer code                    parities=(96+10)×3=318
[625/50] format video data                1368=(114×3)×4→Number of outer code parities                    =12                        3 ECC blocks per track        Number of data blocks per track+number of outer code                    parities=(114+12)×3=378
In the case of audio data, it is assumed that one ECC block is formed in one field. In this case, the number of tracks per field is 4.
[525/60] format audio data                23=23×1→Number of outer code parities=23        1 ECC block per field        Number of data blocks per track+Number of outer                    code parities=(23+23)/4=11.5
[625/50] format audio data                27=(9×3)→Number of outer code parities=9        3 ECC blocks per field        Number of data blocks per track+Number of outer                    code parities=(27+27)/4=13.5
In this case, in the NTSC system, the number of outer code parities is too large. Moreover, in both the cases, the number of blocks per track is not an integer. In other words, an ECC block cannot be formed. Thus, in the [525/60] format, 108×24=2592 bytes is selected; and in the [625/50] format, 108×28=3024 bytes is selected.
[525/60] format audio data                24=(8×3)→Number of outer code parities=8        3 ECC blocks per field        Number of data blocks per track+Number of outer code                    parities=(24+24)/4=12                        Number of bytes in unnecessary record area per CH=                    183 bytes/field
[625/50] format audio data                28=(7×4)→Number of outer code parities=7        4 ECC blocks per field        Number of data blocks per track+Number of outer code                    parities=(28+28)/4=14                        Number of bytes in unnecessary record area per CH                    136 bytes/field
In this example, in the [525/60] format, a loss record area of 138 bytes×4 ch per field (equivalent to 0.35 M bps) takes place. Thus, the record efficiency deteriorates. The loss area is proportional to the number of audio channels.
FIG. 5A shows the structure of a video ECC block whose video rate is changed from ½ to ⅓. FIG. 5B shows the structure of an audio ECC block whose audio rate is changed from ½ to ⅓. FIG. 5C shows the structure of a sync block in the case that the length of one video sync block is the same as the length of one audio sync block. In the [625/50] format and [525/60] format, one video ECC block (see FIG. 5A) is structured in such conditions that the number of blocks per field is 18, that the number of heads is 4, and that the number of tracks per field is 4. In the [625/50] format, one audio ECC block (see FIG. 5B) is structured in such conditions that the number of blocks per field is 4, that the number of heads is 4, and that the number of tracks per field is 4. In the [525/60] format, one audio ECC block is structured in such conditions that the number of blocks per field is 3, that the number of heads is 4, and that the number of tracks per field is 4.
FIG. 6 shows the relation between an audio ECC block and audio samples. FIG. 6 shows the arrangement of samples with a field frequency of 50 Hz. The arrangement of samples shown in FIG. 6 is largely different from that of original samples shown in FIGS. 3 and 4. The multi-rate type VTR should also record and reproduce the original format data, it should process data of all different arrangements. Thus, the multi-rate type VTR requires signal processing circuits corresponding to all formats of various video data rates and various frame frequencies. Thus, the circuit scale of the multi-rate type VTR becomes large (because of a rise of the IC cost).
Actually, as shown in FIG. 7, 14 formats are considered as combinations of video data rates (25 M bps to 600 M bps), video scan modes (interlace and progressive), and frame frequencies (59.94 Hz, 50 Hz, 29.97 Hz, 25 Hz, and 23.976 Hz). In FIG. 7, an NTSC picture frame is composed of 720×480 and a PAL picture frame is composed of 720×576. The interlace mode and progressive mode as video scan modes are denoted by i and p, respectively.
It is necessary to define the lengths of sync blocks for all the formats shown in FIG. 7. The length of each sync block closely relates to the frame frequency, the data amount of video data, the data amount of audio data, and so forth. Thus, when the length of each video sync block is the same as the length of each audio sync block, it is very difficult to select the length (data packet length) that is optimum and common in all the formats. In addition, since the structure of audio data is largely affected by the video rate, circuits corresponding to all video rates should be disposed. If the processes performed by the multi-rate type encoder and decoder are different in the individual formats, the circuit scale becomes huge. Thus, the IC cost rises.
In the conventional digital VTR, one packet of variable length data is placed in one sync block. Thus, in the multi-rate format, the packet rate is proportional to the bit rate. However, since a sync pattern, an ID, and so forth that are added to each sync block have fixed lengths, the size of these data becomes large in the entire size of one sync block. In other words, the redundance of data becomes high.
In addition, since the synchronization detecting circuit of the conventional VTR reproducing system has only one synchronous pattern detecting portion, if input data has a plurality of types of sync blocks with different lengths, the circuit cannot correctly detect a sync pattern.

Data recording and reproducing method and apparatus for adding synchronization data during recording and detecting synchronization data during reproduction

Abstract: Corresponding to the data rate of the video signal, at least one data packet is placed in one video sync block.

Abstract: A synchronization detecting apparatus automatically and accurately detects sync blocks with different lengths from a data sequence of record data reproduced from a record medium. The synchronization detecting apparatus separates the detected sync blocks into video sync blocks and audio sync blocks. The video sync blocks and the audio sync blocks are decoded with respective error correction codes. As a result, video data and audio data are restored.


A system for processing audio and video components of a television signal provides for automatic control of closed caption signal display in response to the status of an audio muting feature. The system includes an operating mode in which enabling audio muting also enables the closed caption display and disabling muting disables generation of the closed caption display.

The video signal processing section of a television system may include provisions for decoding and displaying auxiliary video information such as closed caption data. Closed caption data includes ASCII digital data representing text corresponding the spoken audio information contained in a television signal. The closed caption data is displayed on the screen of the television system and is intended to provide a visible representation of the spoken portion of a television program as an aid to hearing impaired television viewers. In the United States, the closed captioning standard is set forth in Federal Communications Commission (FCC) regulations (see e.g., 47 CFR .sctn..sctn. 15.119 and 73.682). FCC regulations specify that digital closed caption data is to be transmitted in line 21 of field 1 in the video signal. Data representative of two ASCII characters is transmitted in each occurrence of line 21 of field 1. Future modifications to the standard may provide for closed caption data to select be located in other lines, e.g., line 21 of every field.
Closed caption data is obtained from the video signal by a decoder. The decoded signal is coupled to the video display when the closed captioning function is enabled by a hearing impaired viewer. A hearing impaired viewer may enable the closed captioning function by activating a switch (e.g., located on a remote control unit or on a control panel on the housing of the television system itself) or by selecting the closed captioning function from a menu displayed on the video screen during a control mode of operation. Once activated, closed captioning remains enabled until disabled by the viewer. A viewer that is not hearing impaired would tend to disable closed captioning function to avoid having the closed caption display interfere with the displayed video program.
A television system may also include an audio muting arrangement in the audio signal processing section. Activating the audio muting function causes the audio output from the television system to be disabled. The volume control setting is not affected so that when audio muting function is disabled, the normal audio output is reestablished without adjustment of the volume. Audio muting may be activated, for example, via a remote control unit.
Audio muting is useful in a variety of circumstances. For example, a user may wish to disable the audio output (i.e., enable muting) when answering the telephone or during a conversation. Although audio muting is useful under these circumstances, a viewer may undesirably miss important spoken information of the television program being viewed while the audio is muted.

Automatic display of closed caption information during audio muting


A pixel cell in which a capacitance is coupled between a storage node and a row select transistor. The pixel cell utilizes a readout timing sequence between operation of a reset transistor and a row select transistor to boost a reset voltage.

Various imager circuits have been proposed such as charge coupled device (CCD) arrays, complementary metal oxide semiconductor (CMOS) arrays, arrays combining both CCD and CMOS features, as well as hybrid infrared focal-plane arrays (IR-FPAs). Conventional arrays have light-sensing elements, typically referred to as "pixels" and readout circuitry that outputs signals indicative of the light sensed by the pixels.
A CMOS imager, for example, includes a focal plane array of pixel cells; each cell includes a photodetector (e.g., a photogate, photoconductor or a photodiode) overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a storage region, connected to the gate of the source follower transistor. Charge generated by the photodetector is sent to the storage region. The imager may also include a transistor for transferring charge from the photodetector to the storage region and another transistor for resetting the storage region to a predetermined charge level prior to charge transference.
FIG. 1 illustrates a block diagram of a CMOS imager device 908 having a pixel array 200 with each pixel cell being constructed as described above, or as other known pixel cell circuits. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 200. The row lines are selectively activated in sequence by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated in sequence for each row activation by a column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel.
The CMOS imager 908 is operated by a control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. Control circuit 250 also controls the row and column driver circuitry 210, 260 so that they apply driving voltages to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal Vrst taken off of the storage region when it is reset by the reset transistor and a pixel image signal Vsig, which is taken off the storage region after photo-generated charges are transferred to it. The Vrst and Vsig signals are read by a sample and hold circuit 265 and are subtracted by a differential amplifier 267, to produce a differential signal Vrst−Vsig for each pixel. Vrst−Vsig represents the amount of light impinging on the pixels. This difference signal is digitized by an analog-to-digital converter 275. The digitized pixel signals are fed to an image processor 280 to form a digital image output. The digitizing and image processing can be located on or off the imager chip. In some arrangements the differential signal Vrst−Vsig can be amplified as a differential signal and directly digitized by a differential analog to digital converter.
FIG. 2 illustrates a four transistor (4T) CMOS imager pixel cell 100. Pixel cell 100 includes a photodiode 102 connected to a transfer transistor 104. The transfer transistor 104 is also connected to storage region 108. A reset transistor 106, a capacitor 107 and a gate of a source follower transistor 110 are connected to storage region 108. A row select transistor 112 is connected to source follower transistor 110. The active elements of pixel cell 100 perform the functions of (1) photon to charge conversion by photodiode 102; (2) resetting the storage region to a known state before the transfer of charge to it by reset transistor 106; (3) transfer of charge to the storage region 108 by the transfer transistor 104; (4) selection of the cell 100 for readout by row select transistor 112; and (5) output and amplification of a signal representing a reset voltage (i.e., Vrst) and a pixel signal voltage (i.e., Vsig) based on the charges present on storage region 108 by source follower transistor 110. Capacitor 107 is utilized because charges produced during an integration period by photodiode 102 may be greater than the capacity of storage region 108. Accordingly, capacitor 107 provides additional charge storage capacity. The pixel cell 100 of FIG. 2 is formed on a semiconductor substrate as part of an imager device pixel array (e.g., array 200 of FIG. 1).
FIG. 3 illustrates a timing diagram for the FIG. 2 circuit 300 during pixel readout. Initially, the storage regions 108 of all pixels in an imager array 200 (FIG. 1) are set to a predetermined voltage to ensure that all source follower transistors 110 remain turned off. The ROW signal of the pixel intended to be read is pulsed high at time t1 providing an operating voltage across source follower transistor 110. The storage region 108 of the pixel intended to be sampled is then reset at time t2 by briefly turning on reset transistor 106, which is supplied with operating voltage VCC plus a Vt threshold voltage of the reset transistor 106 when signal RST goes high, thereby resetting storage region 108 to a predetermined voltage. The reset voltage level on the storage region 108 is then applied to the gate of source follower transistor 110, which converts it to a reset output voltage Vrst on a column output line. The output signal is subsequently sampled at time t3, for example by a sample and hold circuit 265 (FIG. 1), where a high pulse SHR is used to sample and hold the reset output voltage Vrst onto a first sample and hold capacitor.
Charge stored in photodiode 102 from an integration period is subsequently transferred to storage region 108 by signal TX going high at time t4 thereby, turning on transfer transistor 104. The transferred charge lowers the voltage on the storage region 108 to a pixel output signal level, which is applied to the gate of source follower transistor 110. Source follower transistor 110, which is supplied with operating voltage VCC, converts the signal voltage level to a signal output voltage Vsig on the column output line. Sample and hold circuit 265 (FIG. 1) in response to a sample/hold pulse SHS at time t5 causes the pixel's signal output voltage Vsig on the column line to be stored in a second sample and hold capacitor. After Vsig is sampled, the ROW signal is set to a low voltage and the pixel circuit is ready for a next image capture.
Since transfer transistor 104 is positioned between photodiode 102 and storage region 108, the storage region 108 can be reset prior to transferring electrons. This permits a correlated double sampling operation resulting in reduced kTC noise and image noise.
With the pixel circuit configuration of FIG. 2 during reset, in order to obtain a maximum voltage swing at storage region 108, the reset transistor gate voltage is boosted to VCC+Vt (a threshold voltage of reset transistor 106). By adding voltage Vt to the reset voltage, the storage region 108 can be reset to VCC allowing a greater output signal swing from the source follower transistor 110 in response to charges transferred to the storage region 108 from photodiode 102. This technique requires additional supply voltage boost circuits to boost the reset voltage which increases the size, power consumption, design complexity and costs of the pixel and associated circuit.

This patent is subject to a terminal disclaimer.


A turbine blade includes an airfoil, platform, shank, and dovetail. The platform includes a first side disposed along the pressure side of the airfoil, and an opposite second side disposed along the airfoil suction side. The platform second side includes an integral damper keeper disposed below the midchord of the airfoil, and is locally thinner at the forward and aft ends of the platform second side for reducing blade weight.

The present invention relates generally to gas turbine engines, and, more specifically, to turbine blades therein.
In a gas turbine engine air is pressurized in a compressor and mixed with fuel in a combustor for generating hot combustion gases. Turbine stages extract energy from the combustion gases for powering the compressor and producing useful work.
A high pressure turbine (HPT) immediately follows the combustor and includes one or more rows of turbine rotor blades which extract energy from the gases for powering the compressor.
A multistage low pressure turbine (LPT) follows the HPT and includes additional rotor blades which also extract energy from the combustion gases for typically powering an upstream fan in a turbofan aircraft engine application.
In yet another configuration, an intermediate pressure turbine (IPT) is disposed between the HPT and the LPT and includes additional turbine stages which also extract energy from the combustion gases for producing additional work. In this configuration, the IPT may be joined to a low pressure or booster compressor disposed upstream from the high pressure compressor for providing power thereto. And, the LPT powers an external drive shaft which may be used for powering an electrical generator in a typical industrial gas turbine engine application.
Since the rotor blades of the HPT are subject to the hottest temperatures of the combustion gases and rotate at high speed they are subject to considerable thermal and centrifugal stresses during operation. In order to improve their life and durability, the HPT turbine blades are typically formed of superalloys, such as nickel-based metal, for their enhanced strength at elevated temperature.
The turbine blades typically include hollow airfoils having cooling circuits therein through which is circulated cooling air bled from the compressor during operation. The blades also include an integral platform which defines the inner boundary for the hot combustion gases, with an integral supporting dovetail being disposed therebelow.
The blade dovetail includes one or more pairs of dovetail tangs or lobes which are mounted in corresponding dovetail slots in the perimeter of the supporting turbine rotor disk. Axial-entry dovetails are common and extend through axial dovetail slots disposed around the perimeter of the rotor disk.
Centrifugal loads generated during operation of the rotating blades are carried radially inwardly through the dovetail lobes into the corresponding disk posts which define the dovetail slots around the perimeter of the rotor disk Since the blade airfoil, platform, and dovetail are specifically configured for different purposes they experience different thermal and centrifugal loads during operation which must be suitably limited for ensuring a long useful life of the turbine stage.
Correspondingly, the supporting rotor disks must also be suitably configured for carrying the centrifugal loads from the row of rotor blades with limited stress for ensuring the long useful life of the disk as well.
Turbine efficiency is affected by many interrelated parameters. Fundamentally, turbine efficiency may be increased as combustion gas temperature increases, but hotter combustion gases increase the heat loads on the turbine components which must be suitably cooled. Bleeding cooling air from the compressor in turn reduces efficiency of the engine since the bleed air is not used in the combustion process.
Furthermore, the aerodynamic profiles of the turbine blades themselves affect engine efficiency, and the airfoil configuration also affects thermal and centrifugal loads and stresses not only in the airfoils themselves but also in the supporting platforms, dovetails, and rotor disk posts.
In a recent development of a three-spool industrial gas turbine engine having an HPT, IPT, and LPT for driving an electrical generator, engine efficiency is being increased by improving the 3-D aerodynamic configuration of the turbine airfoils in the second stage of the HPT, for example. Modern analysis tools are being used to refine the 3-D configuration of the second stage airfoil for improving the efficiency thereof, which blades experience a larger twist relative to the axial dovetails then conventionally found. Such axial dovetails have proven durability in conventional turbines and permit corresponding long life of the supporting rotor disk.
The increased twist or turning of the airfoil root or hub at the inner platform correspondingly changes the load paths to the axial dovetail which is not similarly twisted or turned about the radial axis.
The airfoil hub turning requires suitably inclined or angled axial splitlines between the adjacent platforms in the row of turbine blades. The blade platforms therefore are twisted relative to the supporting axial dovetail and affect the centrifugal load path therethrough as well as the collective configuration thereof.
Each platform includes two slash faces which define the corresponding axial split lines between adjacent platforms when mounted in a full row around the perimeter of the rotor disk. Twisting of the platform then causes corresponding corners thereof at the forward and aft ends of the platform to overhang the underlying axial dovetail in a cantilever fashion.
The overhanging corners of the platform are therefore relatively long as compared with the midchord region of the platform at which the twisting direction changes, with the opposite corners of the platforms being offset back or recessed behind the corresponding edges of the axial dovetail.
The twisted platform can add significant weight to the entire blade because the platform is typically configured relatively thick at its aft and forward ends to define corresponding damper keepers. In one conventional configuration, the two damper keepers are located on the suction-side slash face of the platform at the junction with the corresponding radially extending skirts which support conventional angel wing seals.
The pressure-side slash face is relatively thin and includes a shelf therebelow for mounting an elongate damper therein. The damper is trapped axially, radially, and circumferentially between adjoining platforms when assembled along the perimeter of the rotor disk, and includes a planar flat face which circumferentially abuts the suction-side slash face, including the two damper keepers integral therewith.
In this way, the enlarged damper keepers maintain the radial orientation of the dampers during operation for maximizing their damping performance as they vibrate between the platforms during operation for frictionally damping vibratory motion of the blades.
Since the two damper keepers are located at the forward and aft ends of the platform in the overhang regions thereof, they add considerable weight to the turbine blades, which correspondingly increases the centrifugal force which must be carried through the dovetails and into the rotor disk, and correspondingly increase stress therefrom.
Furthermore, additional weight is introduced in the turbine blade by the need for providing therein a pair of reference planes or datum pads. A typical turbine blade is initially cast, and then undergoes subsequent machining as required for finishing the blade, such as by drilling many film cooling holes through the airfoil thereof.
In one conventional turbine blade, four supporting lugs extend outwardly from the blade shank above the dovetail on opposite sides of the blade, and support a discrete seal body thereon during operation. Two of the supporting lugs have recessed datum pads on the inboard sides thereof which pads are locally thick regions of the blade shank that rise in elevation to form a common reference plane for subsequent machining operations. Those two datum pads add weight to the blade.
Yet further, individual blades typically include a corresponding serial number therefor. The serial number is typically formed on a corresponding flat pad formed on the pressure side of the blade shank between the other two supporting lugs. That pad is a flat land elevated from the changing contour of the shank, and adds additional weight to the turbine blade.
The entire weight of the turbine blade must be carried through its dovetail into the disk posts of the turbine rotor and creates corresponding centrifugal force and stress which must be carried by the common supporting disk.
In order to ensure the durability and long life of the turbine disk which supports a full row of turbine blades, the disk is typically formed of a superalloy material, nickel based for example, which enjoys high strength in the hot environment of the turbine. Disk strength may be further increased by using state-of-the-art manufacturing processes such as powder metallurgy to form the disk in a correspondingly expensive manufacturing process. Powder-formed turbine rotor disks enjoy increased strength over conventional forged disks, but at a correspondingly higher manufacturing cost.
Accordingly, it is desired to provide an improved turbine blade having selective weight reduction for decreasing centrifugal loads during operation, and permitting the use of a less expensive supporting rotor disk for achieving comparable durability and life.