Modems, methods, and computer program products for recovering from errors during a tone reversal sequence between a modem pair detect a false tone reversal during a tone reversal sequence at a first modem. If a false tone reversal is detected, then the first modem requests that a second modem restart the tone reversal sequence. Tone reversal sequences are used, for example, in the startup protocols of both the V.34 and V.90 standards to calculate the round trip delay between two modems. Neither standard provides for any recovery procedure, however, should the tone reversal sequence fail. The modems, methods, and computer program products can allow errors in a tone reversal sequence to be addressed immediately rather than proceeding to later phases in the communication protocol where the errors may ultimately cause the communication session to breakdown.

The present invention relates generally to the field of modems, and, more particularly, to error recovery in a modem during a startup protocol.
The demand for remote access to information sources and data retrieval, as evidenced by the success of services such as the World Wide Web, is a driving force for high-speed network access technologies. Today""s telephone network offers standard voice services over a 4 kHz bandwidth. Traditional analog modem standards generally assume that both ends of a modem communication session have an analog connection to the public switched telephone network (PSTN). Because data signals are typically converted from digital to analog when transmitted towards the PSTN and then from analog to digital when received from the PSTN, data rates may be limited to 33.6 kbps as defined in the V.34 transmission recommendation developed by the International Telecommunications Union (ITU).
The need for an analog modem can be eliminated, however, by using the basic rate interface (BRI) of the Integrated Services Digital Network (ISDN). A BRI offers end-to-end digital connectivity at an aggregate data rate of 160 kbps, which is comprised of two 64 kbps B channels, a 16 kbps D channel, and a separate maintenance channel. The ISDN offers comfortable data rates for Internet access, telecommuting, remote education services, and some forms of video conferencing. ISDN deployment, however, has been very slow due to the substantial investment required of network providers for new equipment. Because the ISDN is not very pervasive in the PSTN, the network providers have typically tarriffed ISDN services at relatively high rates, which may be ultimately passed on to the ISDN subscribers. In addition to the high service costs, subscribers must generally purchase or lease network termination equipment to access the ISDN.
While most subscribers do not enjoy end-to-end digital connectivity through the PSTN, the PSTN is nevertheless mostly digital. Typically, the only analog portion of the PSTN is the phone line or local loop that connects a subscriber or client modem (e.g., an individual subscriber in a home, office, or hotel) to the telephone company""s central office (CO). In recent years, local telephone companies have been replacing portions of their original analog networks with digital switching equipment. Nevertheless, the connection between the home and the CO has been the slowest to change to digital as discussed in the foregoing with respect to ISDN BRI service. A recent data transmission recommendation issued by the ITU, known as V.90, takes advantage of the digital conversions that have been made in the PSTN. By viewing the PSTN as a digital network, V.90 technology is able to accelerate data downstream from the Internet or other information source to a subscriber""s computer at data rates of up to 56 kbps, even when the subscriber is connected to the PSTN via an analog local loop.
To understand how the V.90 recommendation achieves this higher data rate, it may be helpful to briefly review the operation of V.34 analog modems. V.34 modems are optimized for the situation where both ends of a communication session are connected to the PSTN by analog lines. Even though most of the PSTN is digital, V.34 modems treat the network as if it were entirely analog. Moreover, the V.34 recommendation assumes that both ends of the communication session suffer impairment due to quantization noise introduced by analog-to-digital converters. That is, the analog signals transmitted from the V.34 modems are sampled at 8000 times per second by a codec upon reaching the PSTN with each sample being represented or quantized by an eight-bit pulse code modulation (PCM) codeword. The codec uses 256, non-uniformly spaced, PCM quantization levels defined according to either the xcexc-law or A-law companding standard.
Because the analog waveforms are continuous and the binary PCM codewords are discrete, the digits that are sent across the PSTN can only approximate the original analog waveform. The difference between the original analog waveform and the reconstructed quantized waveform is called quantization noise, which limits the modem data rate.
While quantization noise may limit a V.34 communication session to 33.6 kbps, it nevertheless affects only analog-to-digital conversions. The V.90 standard relies on the lack of analog-to-digital conversions outside of the conversion made at the subscriber""s modem to enable transmission at 56 kbps.
The general environment for which the V.90 standard was developed is depicted in FIG. 1. An Internet Service Provider (ISP) 22 is connected to a subscriber""s computer 24 via a V.90 digital server modem 26, through the PSTN 28 via digital trunks (e.g., Ti, El, or ISDN Primary Rate Interface (PRI) connections), through a central office switch 32, and finally through an analog loop to the client""s modem 34. The central office switch 32 is drawn outside of the PSTN 28 to better illustrate the connection of the subscriber""s computer 24 and modem 34 into the PSTN 28. It should be understood that the central office 32 is, in fact, a part of the PSTN 28. The operation of a communication session between the subscriber 24 and an ISP 22 is best described with reference to the more detailed block diagram of FIG. 2.
Transmission from the server modem 26 to the client modem 34 will be described first. The information to be transmitted is first encoded using only the 256 PCM codewords used by the digital switching and transmission equipment in the PSTN 28. The PCM codewords are modulated using a technique known as pulse amplitude modulation (PAM) in which discrete analog voltage levels are used to represent each of the 256 PCM codewords. These PAM signals are transmitted towards the PSTN by the PAM transmitter 36 where they are received by a network codec. No information is lost in converting the PAM signals back to PCM because the codec is designed to interpret the various voltage levels as corresponding to particular PCM codewords without sampling the PAM signals. The PCM data is then transmitted through the PSTN 28 until reaching the central office 32 to which the client modem 34 is connected. Before transmitting the PCM data to the client modem 34, the data is converted from its current form as either xcexc-law or A-law companded PCM codewords to PAM voltages by the codec expander (digital-to-analog (D/A) converter) 38. These PAM voltages are processed by a central office hybrid 42 where the unidirectional signal received from the codec expander 38 is transmitted towards the client modem 34 as part of a bidirectional signal. A second hybrid 44 at the subscriber""s analog telephone connection converts the bidirectional signal back into a pair of unidirectional signals. Finally, the analog signal from the hybrid 44 is converted into digital PAM samples by an analog-to-digital (A/D) converter 46, which are received and decoded by the PAM receiver 48. Note that for transmission to succeed effectively at 56 kbps, there must be only a single digital-to-analog conversion and subsequent analog-to-digital conversion between the server modem 26 and the client modem 34. Recall that analog-to-digital conversions in the PSTN 28 can introduce quantization noise, which may limit the data rate as discussed hereinbefore. Moreover, the PAM receiver 48 needs to be in synchronization with the 8 kHz network clock to properly decode the digital PAM samples.
Transmission from the client modem 34 to the server modem 26 follows the V.34 data transmission standard. That is, the client modem 34 includes a V.34 transmitter 52 and a D/A converter 54 that encode and modulate the digital data to be sent using techniques such as quadrature amplitude modulation (QAM). The hybrid 44 converts the unidirectional signal from the digital-to-analog converter 54 into a bidirectional signal that is transmitted to the central office 32. Once the signal is received at the central office 32, the central office hybrid 42 converts the bidirectional signal into a unidirectional signal that is provided to the central office codec. This unidirectional, analog signal is converted into either xcexc-law or A-law companded PCM codewords by the codec compressor (A/D converter) 56, which are then transmitted through the PSTN 28 until reaching the server modem 26. The server modem 26 includes a conventional V.34 receiver 58 for demodulating and decoding the data sent by the V.34 transmitter 52 in the client modem 34. Thus, data is transferred from the client modem 34 to the server modem 26 at data rates of up to 33.6 kbps as provided for in the V.34 standard.
The V.90 standard only offers increased data rates (e.g., data rates up to 56 kbps) in the downstream direction from a server to a subscriber or client. Upstream communication still takes place at conventional data rates as provided for in the V.34 standard. Nevertheless, this asymmetry is particularly well suited for Internet access. For example, when accessing the Internet, high bandwidth is most useful when downloading large text, video, and audio files to a subscriber""s computer. Using V.90, these data transfers can be made at up to 56 kbps. On the other hand, traffic flow from the subscriber to an ISP consists of mainly keystroke and mouse commands, which are readily handled by the conventional rates provided by V.34.
As described above, the digital portion of the PSTN 28 transmits information using eight-bit PCM codewords at a frequency of 8000 Hz. Thus, it would appear that downstream transmission should take place at 64 kbps rather than 56 kbps as defined by the V.90 standard. While 64 kbps is a theoretical maximum, several factors prevent actual transmission rates from reaching this ideal rate. First, even though the problem of quantization error has been substantially eliminated by using PCM encoding and PAM for transmission, additional noise in the network or at the subscriber premises, such as non-linear distortion and crosstalk, limit the maximum data rate. Furthermore, the xcexc-law or A-law companding techniques do not use uniform PAM voltage levels for defining the PCM codewords. The PCM codewords representing very low levels of sound have PAM voltage levels spaced close together. Noisy transmission facilities can prevent these PAM voltage levels from being distinguished from one another thereby causing loss of data. Accordingly, to provide greater separation between the PAM voltages used for transmission, not all of the 256 PCM codewords are used.
It is generally known that, assuming a convolutional coding scheme, such as trellis coding, is not used, the number of symbols required to transmit a certain data rate is given by Equation 1:
bps=Rslog2N2xe2x80x83xe2x80x83EQ. 1
where bps is the data rate in bits per second, Rs is the symbol rate, and Ns is the number of symbols in the signaling alphabet or constellation. To transmit at 56 kbps using a symbol rate of 8000, Equation 1 can be rewritten to solve for the number of symbols required as set forth below in Equation 2:
Ns=256000/8000=128xe2x80x83xe2x80x83EQ. 2
Thus, the 128 most robust codewords of the 256 available PCM codewords are chosen for transmission as part of the V.90 standard.
The V.90 standard, therefore, provides a framework for transmitting data at rates up to 56 kbps provided the network is capable of supporting the higher rates. The most notable requirement is that there can be at most one digital-to-analog conversion and subsequent analog-to-digital conversion in the path. Nevertheless, other digital impairments, such as robbed bit signaling (RBS) and digital mapping through packet assemblers/disassemblers (PADS), which results in attenuated signals, can also inhibit transmission at V.90 rates. Communication channels exhibiting non-linear frequency response characteristics are yet another impediment to transmission at the V.90 rates. Moreover, these other factors may limit conventional V.90 performance to less than the 56 kbps theoretical data rate.
U.S. Patents Nos. 5,801,695 and 5,809,075 to Townshend appear to disclose a modem for data transmission over existing telephone lines at data rates higher than conventional analog modems.
Articles such as Humblet et al., xe2x80x9cThe Information Driveway,xe2x80x9d IEEE Communications Magazine, December 1996, pp. 64-68, Kalet et al., xe2x80x9cThe Capacity of PCM Voiceband Channels,xe2x80x9d IEEE International Conference on Communications ""93, May 23-26, 1993, Geneva, Switzerland, pp. 507-511, Fischer et al., xe2x80x9cSignal Mapping for PCM Modems,xe2x80x9d V-pcm Rapporteur Meeting, Sunriver, Oreg., USA, Sep.4-12, 1997, and Proakis, xe2x80x9cDigital Signaling Over a Channel with Intersymbol Interference,xe2x80x9d Digital Communications, McGraw-Hill Book Company, 1983, pp. 373, 381, provide general background information on digital communication systems.
Nevertheless, there exists a need for improvements in V.90 modem technology to allow V.90 modems to achieve more closely the theoretical 56 kbps maximum data rate.
Certain objects, advantages, and features of the invention will be set forth in the description that follows and will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention.
It is an object of the present invention to provide improved modems having a more robust startup protocol.
It is a further object of the present invention to enable a modem pair to recover from errors in a tone reversal sequence during, for example, a startup protocol.
These and other objects, advantages, and features of the present invention are provided by modems, methods, and computer program products for recovering from errors during a tone reversal sequence between a modem pair. In accordance with an aspect of the invention, a false tone reversal during a tone reversal sequence is detected at a first modem. If a false tone reversal is detected, then the first modem requests that a second modem restart the tone reversal sequence.
Tone reversal sequences are used, for example, in the startup protocols of both the V.34 and V.90 standards to calculate the round trip delay between two modems. Neither standard provides for any recovery procedure, however, should the tone reversal sequence fail. The present invention allows errors in a tone reversal sequence to be addressed immediately rather than proceeding to later phases in the communication protocol where the errors may ultimately cause the communication session to breakdown.
In accordance with another aspect of the invention, errors can be detected in the tone reversal sequence at the a modem, which is typically the server modem in a v.90 communication session or the client modem in a V.34 communication session, by obtaining the duration between successive phase reversals of a tone and then determining if the duration is less than a threshold value.
In accordance with yet another aspect of the invention, the first modem can request that the second modem restart the tone reversal sequence by preventing the first modem from acknowledging the receipt of the second reversal in phase of the tone to the second modem.
In accordance with still another aspect of the invention, errors can be detected in the tone reversal sequence at a first modem, which is typically the client modem in a V.90 communication session or the server modem in a V.34 communication session, by obtaining the duration between receiving a tone and detecting a phase reversal of the tone and then determining if the duration is less than a threshold value.
In accordance with another aspect of the invention, the first modem can request that the second modem restart the tone reversal sequence by preventing the first modem from acknowledging the receipt of the phase reversal of the tone to the second modem.
The present invention can therefore be used to reliably calculate the round trip delay from either end of both a V.34 communication session and a V.90 communication session.

Modems, methods, and computer program products for recovering from errors in a tone reversal sequence between two modems

International Business Machines Corporation


This invention relates to a novel microorganism-derived enzyme having an activity to cut disaccharide glycosides (particularly, β-primeveroside and/or analogous disaccharide glycosides) in disaccharide unit, a method for producing the enzyme, a gene which encodes the enzyme and use of the enzyme. Various components can be formed by the action of this enzyme upon disaccharide glycosides.

Alcoholic aromas such as geraniol, linalool, benzyl alcohol, 2-phenyl alcohol and C13-norterpenoid alcohol as plant aroma components take an important role in the aroma formation of, for example, flowers, tea, fruits and wine.
Among these aroma components, monosaccharide glycosides such as β-D-glucopyranoside have been isolated and identified as aroma precursors of benzyl alcohol and (Z)-3-hexenol.
Recently, the presence of a disaccharide glycoside β-primeveroside (6-O-β-D-xylopyranosyl-β-D-glucopyranoside) or its analogs has been confirmed as precursors of fragrant alcohols such as geraniol and linalool, which seem to be taking an important role regarding the aroma of flowers. The presence of the disaccharide glycoside β-primeveroside and its analogs has also been revealed as precursors of other alcoholic aroma components described above.
In addition to such aromas, the presence of the disaccharide glycoside β-primeveroside or its analogs has also been found in certain physiologically active substances such as pigments and pharmacological components. For example, it is known that macrozamin in a cycad, etc. is cut by β-primeverosidase in disaccharide unit to form a toxin.
On the other hand, such an enzyme having a function to cleave precursors of these aroma components and physiologically active components in disaccharide unit has been confirmed only in a small amount in, for example, tea leaves (JP-A-8-140675; the term "JP-A" as used herein means an "unexamined published Japanese patent application"), and almost no study on its application has been carried out. Recently, it became apparent that the aglycon cannot be sufficiently released from these disaccahride glycoside and analogues thereof by the action of the known glucosidase. In consequence, great concern has been directed toward the development of a method by which such an enzyme can be produced on an industrial scale at low cost without depending on the prior art supply sources such as tea leaves.

Diglycosidase isolated from microorganisms


The present invention relates to a process for the preparation of a hydroxy-amino polymer, comprising the steps: a) reacting an H-functional starter compound carrying at least one Zerewitinoff-active H atom with an unsaturated cyclic carboxylic acid anhydride to give a carboxyl-group-carrying prepolymer, b) reacting the carboxyl-group-carrying prepolymer with at least one epoxide compound to give a hydroxyl-group-carrying prepolymer, c) adding a primary amine and/or ammonia to the double bond of the hydroxyl-group-carrying prepolymer obtained according to step b) to give the hydroxy-amino polymer, wherein the ratio of the amount of carboxylic acid anhydride to the number of Zerewitinoff-active H atoms of the H-functional starter compound is so chosen that almost all the Zerewitinoff-active H atoms of the H-functional starter compound are reacted. The invention relates additionally to a hydroxy-amino polymer obtainable by the above-mentioned process, wherein the ratio of the amount of unsaturated cyclic carboxylic acid anhydride to the number of Zerewitinoff-active H atoms of the H-functional starter compound is at least approximately 0.9:1, and further to the use of this hydroxy-amino polymer in the preparation of a polyurethane urea polymer.

Polymers which are both amine-functional and carry hydroxyl groups (so-called hydroxy-amino polymers) are increasingly of interest in some fields of application, especially in the field of the polyurethane industry. The reason for this is that the presence of two different types of functional groups, namely the amine functionalities and the hydroxyl groups, enables novel property and processing profiles to be achieved. For example, combining the amino groups, which are significantly more reactive towards isocyanate groups, with the less reactive hydroxyl groups gives rise to the possibility of influencing the progress of curing processes over time in a desirable manner, which has hitherto not been possible or has been possible to only a limited extent in the presence of only one type of the above-mentioned isocyanate-reactive functional groups.
In general, the amino functionality of hydroxy-amino polymers can be introduced into macromolecules by the addition of primary amines or ammonia to low-electron double bonds, for example of the (meth)acrylate type. The addition of amines to (meth)acrylate-group-containing polymers, inter alia to (meth)acrylate-group-containing polyethers, is known per se; for example, such processes are mentioned in U.S. Pat. No. 5,739,192 A1, U.S. Pat. No. 5,597,390 A1, US 2005/0171002 A1, DE 196 16 984 A1, DE 195 08 308 A1, WO 2010/090345 A1, JP 2009/22753 A1 and JP 04089860 A1.
By contrast, the obtainment of the precursor compounds comprising the low-electron double bonds in the prior art is either not described or takes place via condensation reactions that proceed according to the laws of statistics, for example by the esterification of acrylic acid with difunctional polyethers or the reaction of acryloyl chloride with dysfunctional polyethers.
A common feature of all the described processes is that the introduction of double bonds into the precursor compounds of the hydroxy-amino polymers takes place at the expense of the number of hydroxy functions. Accordingly, these processes do not allow the original hydroxy functionality, which in the case of polyether molecules is generally given by the functionality of the starter molecules used to prepare the polyethers, to be retained during the introduction of the amino fractions.
U.S. Pat. No. 4,874,837 A1 discloses a process in which first diethylene glycol or a mixture of diethylene glycol and a low molecular weight polyether polyol having a molecular weight of from 100 to 600 g/mol is reacted with maleic anhydride or a mixture of maleic anhydride and a further anhydride, maleic anhydride and diethylene glycol being used approximately in a stoichiometric molar ratio. The resulting acid group of the semiester is then converted back into a hydroxy group by reaction with an epoxide, before the amino group is finally introduced by Michael addition of diethanolamine, or a mixture of diethanolamine and further amino alcohols containing primary or secondary amino groups, or diamines containing primary or secondary amino groups to the reactive double bond of the hydroxy maleate.
In the case of the process described in U.S. Pat. No. 4,874,837 A1 it is in some cases perceived to be a disadvantage that the process is limited structurally to the use of diethylene glycol or a mixture of diethylene glycol and a low molecular weight polyether polyol as precursor. A possible reason for this is possibly the falling reactivity of the OH groups of the polyether polyol, in relation to the reaction carried out here, as the chain length increases. Moreover, in each case only approximately one hydroxy group of this precursor is reacted with the anhydride. Furthermore, the Michael addition to the reactive double bond is limited to diethanolamine or a mixture of diethanolamine and further amines reactive with isocyanates.
Accordingly, the object of the present invention was to provide a process for the preparation of hydroxy-amino polymers which is more universally usable, it being possible in particular also to produce hydroxy-amino polymers from polyether polyols with a greater chain length. At the same time, the process is to be simple to carry out and is to suppress the formation of secondary products, such, as, for example, transesterification products, as far as possible, so that working up of the process products is generally not necessary.

Hydroxylamino polymer and method for the production thereof


A valve timing adjusting apparatus includes a driving-side rotor, a driven-side rotor, and a bias mechanism. The bias mechanism includes a projection portion that is rotatable synchronously with the one of the driving-side and driven-side rotors and that contacts a contact part of the other one of the driving-side and driven-side rotors. The contact part includes a receiver part that is configured to increase the restoring force of the resilient member when the other one of the driving-side and driven-side rotors is rotated relative to the one of the driving-side and driven-side rotors in the advance direction or in the retard direction.

1. Field of the Invention
The present invention relates to a valve timing adjusting apparatus for adjusting timing (valve timing) of opening and closing one of an intake valve and an exhaust valve of an internal combustion engine.
2. Description of Related Art
A conventional valve timing adjusting apparatus is known to include a housing serving as a driving-side rotor rotatable synchronously with a crankshaft and a vane rotor serving as a driven-side rotor rotatable synchronously with a camshaft. In the above valve timing adjusting apparatus, the housing includes shoes and the vane rotor includes vanes, and an advance chamber and a retard chamber are defined between the shoe and the vane arranged one after another in a rotational direction. By supplying working fluid to the advance chamber or the retard chamber, the vane rotor is rotated relative to the housing in an advance direction or a retard direction. As a result, a phase (engine phase) of the camshaft with respect to the crankshaft used for determining valve timing is adjusted (for example, JP-A-2002-357105 corresponding to U.S. Pat. No. 6,779,499).
In a valve timing adjusting apparatus described in JP-A-2002-357105, by engaging the vane rotor with the housing at the event of stopping and starting the internal combustion engine, the engine phase is held at an intermediate phase defined between a full advance phase and a full retard phase. Due to the above technique, even when the camshaft applies variable torque that attempts to rotate the vane rotor relative to the housing in the advance direction and the retard direction alternately, the engine phase is mechanically held at the intermediate phase at the event of stopping and starting the internal combustion engine, during which pressure of working fluid is relatively low.
The variable torque (torque reversal) is generated periodically such that the variable torque attempts to advance or retard the camshaft in accordance with the rotation of the internal combustion engine. For example, variable torque is caused by a spring reaction force of a valve spring of the valve that is opened and closed by the camshaft. Also, variable torque may be caused by drive reaction force from a mechanical pump in a case, where the mechanical pump is operated by the camshaft.
Also, in the valve timing adjusting apparatus described in JP-A-H10-252420 corresponding to U.S. Pat. No. 5,775,279, a torsion spring has one end connected with the driven-side rotor and has the other end connected with the driving-side rotor. More specifically, in the apparatus of JP-A-2002-357105, when the one end of the torsion spring is twisted relatively in the retard direction by the rotational force of the driven-side rotor, a restoring force in the advance direction is generated and applied to the driven-side rotor. As a result, the restoring force of the torsion spring quickly rotates the driven-side rotor relative to the driving-side rotor in the advance direction, and thereby responsibility is improved. Also, when supply of fluid is stopped, the restoring force of the torsion spring biases the driven-side rotor in the advance direction relative to the driving-side rotor. Therefore, even in a case, where variable torque from the camshaft is applied to the driven-side rotor, "fluctuation of the cam phase" that may cause noise is successfully suppressed, and thereby the engine phase is capable of being held at a full advance phase.
In JP-A-2002-357105, when the internal combustion engine is stopped, for example, the rotations of the vane rotor relative to housing in the advance and retard directions are limited by different limitation mechanisms, respectively, in order to reliably hold the engine phase at the intermediate phase, and in order to adjust the engine phase or valve timing suitable for the operational state of the internal combustion engine. Each of the limitation mechanisms includes a control pin that is actuated by fluid, and the control pin is assembled into the vane rotor. Because the control pin of each of the limitation mechanisms is actuated independently, a flow channel structure is complicated accordingly.
In contrast, the restoring force of the torsion spring is caused by torsional torque in the apparatus of JP-A-H10-252420. When rotational force in the advance direction twists the connection end portion of the torsion spring, which is connected with the driven-side rotor, the restoring force outputted to the driven-side rotor against relative rotational force is increased. Restoring force of the above torsion spring provides torque that attempts to hold the engine phase at an intermediate phase. However, it is difficult to keep the engine phase at the intermediate phase by using the restoring force of the torsion spring.
Also, even in a case, where the restoring force of the torsion spring is used to bias the engine phase to the intermediate phase in the event of starting the internal combustion engine or in the later event of stopping the supply of working fluid, the restoring force is required to be set at a magnitude equal to or greater than certain torque such that the restoring force advances or retards the engine phase against the average torque of variable torque. The restoring force characteristic of the torsion spring for ensuring the above certain torque causes an increase of torsional torque per unit change of the phase. As a result, when a tracking control for causing the engine phase to follow the target phase or another control for limiting the engine phase within the intermediate phase region is executed, the change amount of the torsional torque required to reduces the gap between the engine phase and the target phase (intermediate phase) is substantially large. Therefore, controlability may deteriorate, and thereby it may become difficult to accurately adjust the engine phase to the target phase.


A method and apparatus for recording time information for received digital data streams are provided. The method includes recording first time information and second time information on a recording medium. The first time information is part of management data for managing presentation data and the second time information is time information of the presentation data. The format of the first time information coincides with the format of the second time information.

1. Field of the Invention
The present invention relates to a method and apparatus for creating and recording time information for searching digital data streams to be recorded on a recording medium and a method and apparatus for searching for requested data using the created time information.
2. Description of the Related Art
In the conventional analog television broadcast, video signals are transmitted over the air or through cables after being AM or FM modulated. With the recent advance of digital technologies such as digital image compression or digital modulation/demodulation, standardization for digital television broadcast is in rapid progress. Based upon the Moving Picture Experts Group (MPEG) format, satellite and cable broadcast industry also moves towards the digital broadcast.
The digital broadcast offers several advantages that its analog counterpart cannot provide. For example, the digital broadcast is capable of providing services with far more improved video/audio quality, transmitting several different programs within a fixed bandwidth, and offering enhanced compatibility with digital communication media or digital storage media.
In the digital broadcast, a plurality of programs encoded based upon the MPEG format are multiplexed into a single transport stream before transmitted. The transmitted transport stream is received by a set top box at the receiver and demultiplexed into original programs. If a program is chosen from among the demultiplexed programs, the chosen program is decoded by a decoder in the set top box and original audio and video signals are retrieved. The retrieved audio and video signals can be presented by an A/V output apparatus such as a TV.
It is also possible to record the received digital broadcast signals on a storage medium instead of directly outputting the received broadcast signals to A/V output devices. The stored digital broadcast signals can be edited and retrieved afterwards. For example, a digital data stream received by the set top box can be transmitted to a streamer such as a digital video disk (DVD) recording apparatus through communication interfaces like an IEEE-1394 serial bus and stored on a recording medium by the streamer. The recorded digital data stream can be edited and transmitted back to the set top box so that the digital audio and video data can be presented.
When recording the digital data stream of a single program on a recording medium in a streamer, the basic recording unit is a stream object (SOB) comprising a series of stream object units (SOBUs). To record received digital data streams on a recording medium and to reproduce the recorded data afterwards, it is necessary to explore how to group and record stream objects (SOBs) and stream object units (SOBUs) and how to create search information for managing and searching for the recorded stream objects (SOBs) and stream object units (SOBUs). Also, it is required to investigate how to search a specific data stream corresponding to a search time requested by a user.
A conventional method for recording digital data streams and creating and recording navigation information will now be explained with reference to the accompanying drawings.
FIG. 1 depicts a block diagram of an apparatus in which the conventional method for creating and recording the navigation information for recorded digital data streams can be employed. FIG. 2 depicts the process of recording digital data streams and creating the navigation information in the system shown in FIG. 1. The system comprises a set top box 100, a communication interface (IEEE-1394), and a streamer 200. The set top box 100 receives transport streams encoded by system encoders and broadcast by a plurality of broadcast stations and demultiplexes the received transport streams. After a decoder 120 decodes the transport stream of a program tuned by a tuning unit 110, a control unit 140 outputs the decoded transport stream to an A/V output apparatus or to the streamer 200 through the IEEE-1394 communication interface 130 and 210 so that the transmitted program can be recorded on a recording medium 230 by the streamer 200, depending upon a user's choice. When requested by a user, the streamer 200 retrieves the recorded program and transmits the retrieved program through the IEEE-1394 communication interface back to the set top box 100. In the set top box 100, the received program is decoded by the decoder 120 and then outputted to an A/V output apparatus so that the recorded program can be presented.
A control unit 250 of the streamer 200 controls a stream recording unit 220 to record the data stream transmitted from the set top box 100 on the recording medium 230, as shown in FIG. 2. The received data stream composed of transport stream packets is recorded on the recording medium along with the packet arrival time (PAT) of each transport stream packet. The transport stream packets with packet arrival times are organized in sectors on the recording medium, with each sector having a predetermined size. A predetermined number of sectors, for example 32 sectors, are grouped into a stream object unit (SOBU). If the recording process is stopped or suspended by a user, the recorded stream object units (SOBUs) are grouped into a stream object (SOB). Additionally, navigation data such as the stream start application packet arrival time (S_S_APAT) and incremental application packet arrival time (IAPAT) for managing and searching for the stream object (SOB) and stream object units (SOBUs) is recorded together with the transport stream packets on the recording medium. A stream reproducing unit 240 reproduces the data recorder with recording medium 230.
FIG. 3 shows the way the received digital data stream is recorded on the recording medium 230. An application packet and its packet arrival time (PAT or time stamp) constitute a transport stream packet (TSP). A plurality of transport stream packets (TSPs) and header information are organized into a sector and a predetermined number of sectors, for example 32 sectors, constitute a stream object unit (SOBU). A series of stream object units (SOBUs) constitutes a stream object (SOB). Meanwhile, the stream object information (SOBI), which is the navigation data for managing and searching the recorded stream object (SOB), comprises stream object general information (SOB_GI) and a mapping list (MAPL) for managing stream object units (SOBUs) contained in the stream object (SOB), as shown in FIGS. 4 and 5. The stream object general information (SOB_GI) includes the stream start application packet arrival time (S_S_APAT) indicative of the start time of the associated stream object (SOB). As shown in FIG. 2, the incremental application packet arrival time (IAPAT), which is a count value counted at constant time intervals (x) between two consecutive stream object units (SOBUs), is included in the mapping list (MAPL) and used as information for searching for the associated stream object units (SOBUs).
The stream start application packet arrival time (S_S_APAT) contained in the stream object general information (SOB_GI) is recorded as a 6-byte packet arrival time (PAT) comprising a 9-bit packet arrival time extension (PAT_ext) and a 39-bit packet arrival time base (PAT_base), as shown in FIG. 6(a). The packet arrival time extension (PAT_ext) is a modulo-300 counter that is incremented at a rate of 27 MHz, whereas the packet arrival time base (PAT_base) is incremented at a rate of 90 kHz. Unlike the stream start application packet arrival time (S_S_APAT), the time stamp recorded along with the application packet shown in FIG. 3 is recorded as a 4-byte packet arrival time (PAT) as shown in FIG. 6(b) that is incremented at a rate of 27 MHz and thus can represent from 0 s up to 159 s (=232/27 MHz). As discussed above, the PAT of the transport stream packet as shown in FIG. 6(b) is a time stamp recorded along with an application packet, and is part of a SOB as shown in FIG. 3 where the SOB is part of user data (actual presentation data) recorded on the recording medium 230.
The method for searching for a transport stream packet corresponding to requested search time using the navigation and time information regarding the stream object (SOB), stream object units (SOBUs) will be explained in detail with reference to an example.
Suppose that the position (s) of a transport stream packet corresponding to the search time (ST) requested by a user is to be searched for, as shown in FIG. 2. First, the stream start application packet arrival time (S_S_APAT) contained in the stream object general information (SOB_GI) of each stream object (SOB) is compared with the requested search time (ST) and a stream start application packet arrival time (S_S_APAT) that is closest to but does not exceed the request search time (ST) is detected. Referring to the mapping list (MAPL) of the stream object SOB #1 containing the detected stream start application packet arrival time (S_S_APAT), the incremental application packet arrival time (IAPAT 1˜4) contained in the mapping list (MAPL) are summed up. The sum value is multiplied by the unit time (x) and added to the detected stream start application packet arrival time (S_S_APAT). The procedure is repeated until the calculated value (S_S_APAT+x×ΣIAPAT) approaches the requested search time (ST) without exceeding it. In FIG. 2, the summation and multiplication is repeated to include IAPAT 4 because the calculated value exceeds the search time (ST) if the calculation continues to IAPAT5. Then, the entry in the mapping list (MAPL) corresponding to the calculated time (S_S_APAT+x×ΣIAPAT) is located and the index of the entry is multiplied by the number of sectors constituting a stream object unit (for example, 32 sectors) to locate the desired stream object unit SOBU 5.
From the start position A′ of the searched stream object SOBU 5, the 4-byte packet arrival time (PAT), which is the time stamp of the transport stream packet, is detected. Recall that the stream start application packet arrival time (S_S_APAT) and the packet arrival time (PAT) of a transport stream packet have different formats and therefore the two values cannot be directly compared. For this reason, the difference between the detected packet arrival time (PAT) and the packet arrival time of the first transport stream packet of the stream object unit SOBU 5 is compared with the difference between the requested search time (ST) and the calculated value (S_S_APAT+x×ΣIAPAT) for fine search of the transport stream packet corresponding to the requested search time (ST).
The position A searched based upon the time information (S_S_APAT+x×ΣIAPAT) calculated using the incremental application packet arrival times (IAPATs), however, does not coincide with the actual start position A′ of the stream object unit SOBU 5, as shown in FIG. 2. Therefore, the offset between the transport stream packet position A detected by the fine search operation and the actual position A′ results in a delay in the search operation.
As a result, additional information indicative of the offset value between A′ and A (Offset_SZ in FIG. 2) is necessary for precisely searching for the position (s) of the transport stream packet corresponding to the requested search time (ST). It is not desirable, however, to add the additional information to every stream object unit (SOBU), which dramatically lowers the recording efficiency of the recording medium.

This patent is subject to a terminal disclaimer.

Method, apparatus and recording medium for recording time information for digital data streams


An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

This application claims the priority of Korean Patent Application No. 2003-33346, filed on May 26, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Technical Field
The present disclosure relates to a nonvolatile memory device and a method of fabricating same. More particularly, the present invention relates to a one-time programmable (OTP) memory device and a method of fabricating the OTP memory device.
2. Discussion of the Related Art
Nonvolatile memory devices are devices from which data is not erased even with discontinued power and which are used to selectively program data according to the needs of a user. OTP memory devices are used for programming data only one time without erasing or adding data. Demand for OTP memory devices has been increasing.
A cell area of an OTP memory device may have a layout as shown in FIG. 1. FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III′ of FIG. 1. The cell structure of a conventional OTP memory device and a method of fabricating same will be described with reference to FIGS. 1 through 3.
As shown in FIGS. 2 and 3, the cell of the OTP memory device includes a tunnel oxide layer 15, a floating gate 20, a dielectric layer 40, and a control gate 50 in a stacked structure. The tunnel oxide layer 15 is formed on a substrate 1 on which an isolation layer 5 is formed. A source region 60 and a drain region 65 are formed in the substrate 1 under and adjacent both sides of the control gate 50. In the OTP memory device having the above-described stacked structure, as electrons are induced by a strong electric field and move through the tunnel oxide layer 15 with a thickness of about 100 Å, a threshold voltage of the cell area varies. As a result, the OTP memory device can perform a programming function. The tunnel oxide layer 15 is used as a gate oxide layer of the OTP memory device. The label tunnel oxide layer 15 derives from the fact that the electrons move inside the tunnel oxide layer 15.
Such an OTP memory device may be used to assist with functions of various types of semiconductor products. For example, an OTP memory device may be embedded in a liquid crystal display driver integrated circuit (LDI) so as to write various kinds of information. The process required to embed a cell of an OTP memory device within the stack structure shown in FIGS. 1 through 3 in an existing integrated circuit (IC) is complicated. When using an OTP memory device having the stacked structure, the number of processes for completing the IC increases and the cost of fabricating the IC increases.
The OTP memory device may be integrated with metal-oxide-semiconductor (MOS) transistors into one circuit on a semiconductor substrate. In order to fabricate the semiconductor IC, a thick oxide layer, for example, a gate oxide layer of the MOS transistor, is first formed on the substrate 1. Next, using a photolithographic process, the entire thick oxide layer or a portion thereof is removed from an area where the OTP memory device is to be formed. Thereafter, the thin tunnel oxide layer 15 is formed in the area. Materials for forming the floating gate 20, the dielectric layer 40, and the control gate 50 are subsequently deposited and patterned. Next, ions are implanted into an active area 10 to form the source region 60 and the drain region 65.
During removal of the entire thick gate oxide layer or a portion thereof using the photolithographic process, and the formation of the thin tunnel oxide layer 15, the gate oxide layer may be exposed to chemicals during formation and removal of a photoresist. Thus, the reliability of the MOS transistor may deteriorate. In particular, gate oxide layers of the MOS transistors may have different thicknesses so that the MOS transistors are used as high and low voltage transistors.

Programmable memory device, integrated circuit including the programmable memory device, and method of fabricating same


A system and a method for scheduling an emergency procedure in response to detecting that a patient has a high probability of acute myocardial infarction. The system is able to identify patients that are suspected of having acute myocardial infarction (or acute ischemia). The system uses one or more expert software tools or algorithms to analyze received ECG records. Each software tool has logic (e.g., thresholds and/or settings) for automatic routing which is configurable by the customer via a graphical user interface. If any sufficient condition for automatic routing is satisfied, the system routes the data (including the underlying ECG record) and an alert to an electronic device which is accessible by the cardiologist “on call” via a bidirectional pager. If the cardiologist decides that the requested emergency treatment or procedure should be performed, the system accesses the schedules of all associated catheterization labs across multiple hospitals to identify a lab having optimum time-to-treatment. Then the system automatically contacts the selected catheterization lab via a network to schedule the PTCA procedure.

In hospitals or other health-care settings, it is frequently necessary to observe critical physiological conditions of a patient, including cardiovascular conditions. Cardiovascular condition data is obtained from sensors applied to a patient, or by imaging and sensing devices. Further, cardiovascular data may be data reported by a cardiologist based on review of a patient or a patient's monitor or image data. Hospitals or health-care centers often have hundreds or even thousands of sensor and metering devices and hundreds or even thousands of cardiac patients that require monitoring periodically over a lifetime. This data may be stored in a database for archival functions and later retrieval.
A known ECG management system, the MUSE® (Marquette Universal System for Electrocardiography) system of GE Marquette Medical Systems, Inc., is a software-based product that runs on off-the-shelf hardware. In particular, this ECG management system comprises a database of ECGs plus applications software. The MUSE® system receives ECG data from a multiplicity of instruments via a plurality of networks, analyzes that ECG data using various programs such as a serial comparison program, generates reports containing the results of the analysis, and then routes those reports to various systems and peripheral devices. In particular, the MUSE® system has automatic report routing which can send reports to multiple devices, including a facsimile machine as well as a digital pager.
In the known system, each ECG received by the MUSE® system has been analyzed by the instrument which acquired the ECG. Each instrument incorporates ECG analysis programs such as 12SL® from GE Marquette Medical Systems, Inc., which is a computer program for analyzing simultaneously acquired 12-lead ECGs. The 12SL® program makes precise measurements of recorded cardiac signals, and then provides an interpretation of the ECG waveforms using ECG interpretation criteria for both rhythm and morphology. This generates diagnostic statements. The ECG information stored by MUSE® system contains waveforms, measurements and diagnostic statement. The serial comparison program uses all of these. It can also re-measure the waveforms and recalculate measurements and criteria. The serial comparison program can do this on both the current and previous ECG.
Another known expert software tool used in cardiology is the ACI-TIPI (Acute Cardiac Ischemia Time-Insensitive Predictive Instrument), which uses a logistic regression-based equation for computing the probability that the patient is experiencing ischemia.
The accuracy of any one of the foregoing expert software tools is directly dependent upon the quality of the signal it acquires. In 1979, Marquette introduced an electrocardiograph that simultaneously acquired all of the leads from the 12-lead electrocardiogram. Prior to this time, all commercially available electrocardiographs could only acquire 3 leads at a time. Simultaneous recording was adopted so that the computer could use all signals from all 12 leads to properly detect and classify each QRS complex. The program also applies digital filters which remove power line noise and baseline sway.
Computer measurement of features within the QRS complex is very susceptible to artifact. In addition to filtering, there is another method of eliminating noise from the QRS complex: signal averaging. Instead of analyzing a single QRS complex, the Marquette 12SL® program generates a median complex. That is, it aligns in time, all of the QRS complexes of the same shape; it then generates a representative complex from the median voltages that are found at each successive sample time. This is more complicated than an average, but the method results in a cleaner signal since it disregards outliers.
All ECG computer programs are composed of two parts: one which measures the waveforms, the other which does the interpretation based on these measurements. The main task of the measurement section is to find the location of the major reference points (that is, the onsets and offsets of the P, QRS and T complexes). Consistent with the signal processing portion of the 12SL® program, the onsets and offsets of the major waves are delineated by an analysis of the slopes in all 12 simultaneous leads. That is, QRS duration is measured from the earliest onset in any lead to the latest deflection in any lead. Similarly, the QT interval is measured from the earliest detection of depolarization in any lead to the latest detection of re-polarization in any lead.
After the onsets and offsets of the P, QRS, and T complexes have been demarcated, the waves within each complex are measured according to published standards. These amplitudes and durations result in a measurement matrix containing more than 1600 values. This is then passed to the criteria portion of the 12SL® program so that it can generate an interpretation, including diagnostic statements referenced via a statement library.
The MUSE® system stores ECGs in such a fashion that they can be re-analyzed by the 12SL® program or other expert software tool. That is, the fidelity of the stored ECG is such that it can be used as if it were freshly acquired from the patient.
Computerized electrocardiography has resulted in two practical advantages for the overreading physician. First, the computer serves as an additional expert opinion. Second, it is possible for cardiologists to overread computer-analyzed tracings in half the time required for conventional, non-analyzed ECGs. Therefore, the computer is not only used to efficiently record, store, transmit, and present the ECG—it is also used to assist the physician in overreading the ECG.
Marquette's serial comparison program helps reduce the number of unnecessary admissions to coronary care units (CCUs) by speeding the evaluation of "questionable" or "borderline" ECGs. The program, which runs on the MUSE® system, compares a patient's current ECG with previous ECGs. The technique of comparing the current ECG to the previous ECG of a patient is termed serial electrocardiography. Serial electrocardiography is used to identify changes in the patient's electrocardiogram. The Marquette serial comparison program was developed to use statements, ECG measurements and waveform comparison techniques to maximize performance and accuracy in the detection of clinically significant changes in rhythm, P, QRS, ST and T waves. The Marquette MUSED system, which stores ECGs with physician-edited interpretations to both individual ECGs and serial comparisons, in tandem with the serial comparison program, allows for accurate and expedient processing of a patient's ECG data. It completes the comparison within minutes, and returns the report while the patient is still in the emergency room. Serial comparison saves time and money by promptly providing diagnostically useful information that helps reduce unneeded CCU admissions.
Serial comparison can provide a quick evaluation of many difficult-to-interpret ECG features, including the borderline Q waves of possible myocardial infarction, the mild ST segment elevation of possible myocardial injury and moderate ST segment elevation with Q-wave evidence of myocardial infarction, which may be persistent change resulting from old infarction. The precise, computerized comparison helps the physician to determine whether the patient has experienced an infarction, whether it is old or new, or whether the ECG reflects a variation that is normal for that patient.
Serial comparison is extremely quick and easy to use. The ECG in question is transmitted from the acquiring electrocardiograph to the MUSE® system using an automatic request for serial comparison of the patient's current and past ECGs. (The MUSE® system automatically stores a patient's successive ECGs.) Within minutes, the physician receives a serial comparison report, including previous ECGs, so that the physician can make his/her own visual comparisons.
It is normal to have significant day-to-day variation in the ECG waveform, and an ECG management system must be able to discriminate between normal and clinically significant variations. Certain clinical conditions can only be reliably detected via a serial analysis. The serial comparison program can detect a new left bundle branch block (LBBB) in an ECG series. It does this based on the ECG interpretation as well as direct comparison of the waveforms.
Acute myocardial infarction (a heart attack) is the leading cause of death in the United States of America. Acute myocardial infarction is often detected through serial change. The pertinent clinical changes in the ECG waveform include a small change in the so-called ST segment and a small new Q wave. These changes in the ECG waveform are typical of the evolution of acute myocardial infarction and must be detected in the face of normal variation.
The 12SL® ECG analysis program (and the other expert software tools discussed above) is able to identify those patients who have a high probability of acute coronary syndrome, i.e., unstable angina/acute myocardial infarction. These patients are candidates for an emergency procedure known as percutaneous transluminal coronary angioplasty (PTCA), which is performed in a catheterization lab at a hospital or health care facility. Time-to-treatment is critical for this procedure. In-hospital patient mortality for primary PTCA has been shown to vary from 2% to 22%, a tenfold difference. Delay in getting the patient into the catheterization lab has been found to be the most important variable for reducing mortality and improving overall outcome. The time-to-treatment for the PTCA procedure often exceeds the recommended guideline (i.e., 90 minutes) by 48-108%. This is because once a high-risk patient has been identified in the emergency department, several subsequent manual steps must be taken to get the patient to the catheterization lab, including locating the cardiologist on call, manually calling or paging the cardiologist, waiting for the called cardiologist to arrive, looking at the ECG upon arrival and then making a decision, manually calling the catheterization lab to schedule the procedure, and so forth.
There is a need for a system and a method for providing expedited scheduling of an emergency procedure in the catheterization lab, thereby reducing the time to treatment for a patient newly classified to have a high probability of acute myocardial infarction.

Automated scheduling of emergency procedure based on identification of high-risk patient

GE Medical Systems Information Technologies, Inc.


For migrating a work flow in a workflow management system having at least one process instance executing an original process definition, each process instance is checked during the execution of the original process definition whether the process instance meets the migration condition. If the migration condition is met, the corresponding process instance is migrated to a modified process definition while executing the original definition.

This invention relates to a method for migrating a process instance executing as per an original process definition in a workflow management system, to continue to execute as per a changed process definition.
Workflow is usually applied in high-volume applications with well-defined business rules. Examples are the treatment of insurance claims or tax-forms filed by public. Workflow is also applicable in organizations wherein primary task of work flow is a consistent application of a process across a wide customer base. Workflow is also applied to execute highly structured internal processes like travel approvals, check requests and marketing material developments.
In a workflow world, there are process definitions and actual instances of these definitions called process instances or simply processes. These instances may be 'enacted' by a Process Engine (PE) which is part of any workflow management system (WFMS). A process definition may include a number of steps called work nodes, some decision making nodes (or route nodes) and loops called reset arcs. Activities may be initiated in work nodes and executed by participants which are also known as Business Objects (BOs). These BOs can be human and/or IT resources.
However, the method for executing a process instance according to the current state of the art essentially remains static. A Process definition describing the business process has to be highly accurate and perfect from the beginning.
In the following scenarios, disadvantages and problems of the state of the art are described.
It is often not possible or not desirable to describe a business process so formalised and detailed enough so as to obtain a process definition from which process instances can be instantiated. Reasons for this may be lack of detailed knowledge about the process or the business problem or even unavailability of the required resources to perform a proper analysis and design of a process. Other difficulties may simply be due to time or economical constraints.
Furthermore, considering and implementing all potential exceptions within a business process might not be technically feasible. Also, this may lead to a very complex process definition. This may also prevents the creation of a precise enough process definition to be used by the workflow manager.
Many organisations do also not take enough time to document their processes and therefore have no ability to translate a process into automation. Others are in volatile business situation, in which no process can be followed. Problems also arise for organisations that have some process orientation but do not apply this process orientation consistently.
Moreover, with the current state of art, if flaws are detected in a business process definition while running its instances, it is complicated or even not possible to realise changes in the execution path of the instances when the original definition is changed.

Migration of a workflow system to changed process definitions

Hewlett-Packard Development Company, L.P.


An initial setup method (100) stores recovery tools (400) and a further setup script (402) on a computer (1000) which has an operating system (302) that need not have any recovery capabilities. At the user site, a further setup method (700, 800) reserves (706) a container space (500) in the file system space (304), creates (716) an image (1008) of the main partition (300), and stores (720) the image in the container. If the partition is corrupted later, the computer can still be booted using virtual boot tools (602), the image can be retrieved (914) from the container even though the partition around it was lost, and the image can then be deployed onto disk (200) over the corrupted partition, thereby restoring a working partition to the computer. This can be done without secondary media such as a recovery CD or floppy, and without a network connection.

U.S. patent application Ser. No. 09/532,223 filed Mar. 22, 2000, which is assigned to PowerQuest Corporation and incorporated herein by reference, describes tools and techniques for storing and recovering images in a computer partition, and more particularly tools and techniques for placing and extracting disk partition images to and from the same partition that is imaged. However, preferred embodiments of the present invention operate to permit image recovery using an image stored in what was once a partition even when a working partition is no longer present, e.g., when the partition table has been overwritten or corrupted. Thus, although an embodiment of the present invention may comprise technology claimed in application Ser. No. 09/532,223, the present invention goes substantially beyond the teachings of that previous application.
U.S. patent application Ser. No. 09/788,191 filed Feb. 17, 2001, which is assigned to PowerQuest Corporation and incorporated herein by reference, describes tools and techniques for running pre-boot code on a computer from a file stored in a file system on the computer; the pre-boot code may be obtained by redirecting floppy drive I/O. It discusses a "virtual floppy" technology which can be used to provide a virtual boot environment for the present invention. However, preferred embodiments of the present invention restore or install a disk image by pulling it out of a container on disk and then installing the image on the disk that held the image container. The nature of the images involved in the two patent applications also differs somewhat, since the virtual floppy image does not necessarily contain a working partition with an installed standard operating system, whereas the present invention's recovery image typically does. Some preferred embodiments of the present invention also lock the container on disk to prevent it from being inadvertently moved, deleted, or modified, a feature which is not required by the virtual floppy technology. Although the virtual floppy image may be loaded from the hard disk, the virtual floppy technology also contemplates routinely loading the image off a CD or other secondary medium instead of the disk, whereas the present invention preferably requires no secondary medium apart from the computer's hard disk(s). Thus, although for one or more of these reasons an embodiment of the present invention may comprise technology claimed in application Ser. No. 09/788,191, the present invention also goes substantially beyond the teachings of that previous application.
PowerQuest Corporation designs, implements, and commercially provides software for computer storage imaging, such as the PowerQuest DRIVE IMAGE® and V2I products. V2I is a mark, and DRIVE IMAGE is a registered mark, of PowerQuest Corporation. Imaging is also discussed in U.S. Pat. Nos. 6,253,300 and 6,108,697, which are assigned to PowerQuest. Propagation of computer storage images to multiple computers is sometimes referred to as "deployment" but in the present application deployment implies installation of an image onto one or more computers, which differs from merely placing an image file or container on a machine without installing the image there.
Gateway 2000, Inc. is assignee of U.S. Pat. No. 5,966,732, which discusses a method for expanding the reserve area of a disk drive to allow computer system manufacturers to change the storage capacity of the reserve area. The computer system manufacturer can add critical data and critical program instructions to the expanded or new reserve area. The computer manufacturer may decide to store a portion of a virus scan program in the expanded reserve area, or store a portion of the basic input output system (BIOS) so that a smaller BIOS read only memory (ROM) can be used for the computer system, or the computer manufacturer can store emergency boot up instructions in the reserve area in the event there is damage to the disk. A disk image for recovering a disk's partition(s) according to the present invention could be stored in such a reserve area on the disk, but a keyword search of U.S. Pat. No. 5,966,732 disclosed no uses of "image", "imaging", "recovery", or "recovering".
Phoenix Technologies, Inc. has disclosed a Boot Engineering Extension Record (BEER) proposal, which is discussed in document T13/D98128RO available under specified conditions from Technical Committee T13 of the InterNational Committee on Information Technology Standards (INCITS); see www.t13.org. The stated goals of the BEER proposal are to "1. Enable BIOS, Option ROM, and OS software to provide the user with a simple, consistent way of addressing all of the storage devices on a PC. 2. Provide a mechanism for the user to select any bootable device. In the case of a mass storage device, the user should be able to pick any bootable partition. 3. The mechanisms in this proposal are designed to last 20 years or more." Some preferred embodiments of the present invention comprise selecting a virtual boot option. Unlike the BEER proposal, however, preferred recovery solutions of the present invention operate on standard hardware and firmware, such as industry standard ATA IDE or SCSI hard drive systems commonly sold in the retail market, without additional modification beyond the software that is documented here.
During "proof of concept" testing of aspects of the present invention, inventor Jared Gaunt created a main partition and a secondary partition on a disk, placed a disk image into the secondary partition, and then merged the secondary partition into the main partition. This provided a single partition having a file containing an image which could then be brought into memory piece-by-piece and laid over the disk, overwriting the main partition. A preliminary name for the present invention was "single disk single partition recovery". U.S. Pat. No. 6,185,666, which is assigned to PowerQuest Corporation, describes tools and techniques for merging computer disk partitions. However, an advantage of some preferred embodiments of the present invention is that no working partition is required.

Computer imaging recovery without a working partition or a secondary medium


A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry. A transistor having a large channel resistance, however, is placed within a feedback path of the latch. Therefore, after the latch is set, if the antifuse cell is blown, the high resistance transistor provides a resistive current path from the V.sub.CC to ground.

Typical integrated memory circuits include arrays of memory cells arranged in rows and columns. In most memory arrays, several redundant rows and columns are provided, which substitute for defective memory cells. When testing circuitry that tests the array identifies a defective memory cell, rather than treating the entire array as defective, a redundant row or column is substituted for the row or columns having the defective memory cell (i.e., for the "defective" row or column). This substitution is performed by assigning the address of the defective row or column to the redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make substitution of the redundant row or column substantially transparent to a system employing the memory circuit, the memory circuit includes an address detection circuit. The address detection circuit monitors the row and column addresses received from the system employing the memory circuit. When the address detection circuit receives the address of a defective row or column, it enables the redundant row or column instead
One type of address detection circuit is a fuse-bank address detection circuit. Fuse-bank address detection circuits employ a bank of sense lines where each sense line corresponds to a bit of an address word. The sense lines are programmed by blowing fuses in the sense lines in a pattern corresponding to the address word of the defective row or column. The programmed addresses are then detected by first applying a test voltage across the bank of sense lines. Then, bits of an external address are applied to the sense lines. If the pattern of blown fuses corresponds exactly to the pattern of external address bits, the sense lines all block current and the voltage across the bank remains high. Otherwise, at least one sense line conducts and the voltage falls. A high voltage thus indicates the programmed address matches the external address. A low voltage indicates a different external address has been applied.
Typically, the fuses are blown by cutting the fuse conductors with a laser to remove the conductive paths through the fuses. One problem with such an approach is that laser cutting of the fuses is time consuming, difficult, and imprecise. As a consequence, the cost and reliability of memory devices employing fuse bank circuits can be less than satisfactory.
To eliminate the cost, difficulty, and expense of laser cutting, memory devices have recently been developed that employ anfifuses in place of conventional fuses. Antifuses are capacitive-type structures that, in their unblown states, form open circuits. Antifuses may be "blown" by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, blown antifuses conduct and unblown antifuses do not conduct.
FIG. 1 shows a typical prior art antifuse circuit 46 from an antifuse bank in greater detail. As noted above, each redundant row and column is addressable by a single programmed address. Therefore, each antifuse bank must correspond to one redundant row or column. If a given memory cell is addressable by an eight bit address word, then eight of such antifuse circuits 46 will together form an antifuse bank. Typically, each antifuse bank will contain an array of antifuses for a redundant row, and an array of antifuses for a redundant column. The antifuse circuit 46 of FIG. 1 shows only one of several antifuse circuits within an antifuse bank that store addresses for both a redundant row and a redundant column. Each of the antifuse circuits 46 in an antifuse bank therefore is identical except for the blown or unblown state of row and column antifuses 48R and 48C, respectively, in each. Consequently, the following description applies equally to all of the antifuse circuits 46 in the antifuse bank.
The antifuse circuit 46 receives three principal input signals: an initiation signal T(RAS), a device enable signal DVC2E, and a reset signal RST. The T(RAS) signal is a delayed version of the row address select signal RAS, which is a common on-chip signal in many memory devices. Like the row address select signal RAS, the T(RAS) signal is a low-true signal. The device enable signal DVC2E is a conventional, on-chip signal at approximately half of the supply voltage V.sub.CC, while the reset signal RST is an externally generated signal that resets the antifuse circuit 46 to the appropriate initial conditions.
In addition to the input signals T(RAS), DVC2E and RST, the antifuse circuit 46 also receives a switchable signal CGND at a switchable node 50. During normal operation, the switchable signal CGND is set to ground to provide a reference for checking the state of the antifuses 48R and 48C. For blowing the antifuses 48R, 48C, the switchable signal CGND is a high voltage, typically greater than 10 volts.
The antifuse circuit 46 includes four principal portions, a row output latch 52R, a row latch control circuit 53, a column output latch 52C and a column latch control circuit 53C. In general, elements in FIG. 1 having a "R" designation following the reference numeral indicates a circuit element for the row portion of the antifuse bank, while a "C" following the reference numeral corresponds to the column portion. While only the row output latch 52R and row latch control circuit 53R are described, such description applies equally to the operation of the column output latch 52C and the column latch control circuit 53C.
The row latch 52R is formed from three PMOS transistors 56R, 58R, 60R and an inverter 62R. The first and second transistors 56R, 58R are coupled in parallel with their sources coupled to the supply voltage V.sub.CC and their drains coupled at a node 64R. The gate of the first transistor 56R is controlled by the T(RAS) signal and the gate of the second transistor 58R is controlled by the output of the inverter 62R, which is also inverted again by an inverter 63R to become the output signal FR of the antifuse circuit 46. In this configuration, if either the T(RAS) signal or the output of the inverter 62R is low, the node 64R will be coupled to the supply voltage V.sub.CC through the first or second transistor 56R, 58R, respectively. The third transistor's gate is grounded so that the third transistor 60R is always on. Therefore, the third transistor 60R couples the node 64R to the inverter input. The third transistor 60R has a high channel length-to-width ratio so that it has a high charnel resistance, typically about 300 k.OMEGA. or more. The third transistor 60R thus forms a constant, high resistance path between the node 64R and the input to the inverter 62R.
Ignoring the effect of the latch control section 53R, operation of the latch 52R is controlled by the T(RAS) signal. Initially, the output signal FR from the row latch 52R is low. Consequently, the gate of the second transistor 58R will be high such that the second transistor 58R is off. Initially, the T(RAS) signal is also high, so the first transistor 56R is off, isolating the node 64R from the supply voltage V.sub.CC. The voltage at the node 64R will be low, because the latch control section 53R forms a path for current to bleed to ground, as described below. The third transistor 60R couples the voltage at node 64R to the inverter 62R so that the input voltage of the inverter is low. The inverter 62R thus continues to supply a high voltage to the gate of the second transistor 58R. keeping the second transistor off and maintaining the initial conditions.
After the initial conditions are established, the T(RAS) signal goes low, turning on the first transistor 56R. In response, supply voltage V.sub.CC pulis the voltage at node 64TR high, through the first transistor 56R. The third transistor 60R transmits the high voltage at node 64R to the input of the inverter 62R. In response, the inverters 62R, 63R set the output signal FR high, thereby turning on the second transistor 58R. At this point, both the first and second transistors 56R, 58R are on.
Later (after address detection is complete), the T(RAS) signal returns high, turning off the first transistor 56R. However, the voltage at node 64R remains high, because the second transistor 58R is latched on through the inverter 62R since the input voltage to the inverter 62R is high and the inverter 62R keeps the second transistor 58R on. The output signal FR thus remains high, even after the T(RAS) signal returns high.
The row latch control circuit 53R is formed from a control transistor 66R and three current legs, all joined at a control node 68R. During normal operation, the control transistor 66R is turned on by the device enable signal DVC2E to couple the control node 68R to the input of the inverter 62R. The inverter's input voltage can therefore be controlled by a control voltage at the control node 68R.
The control voltage is controlled by one or more of the three current legs. The first or reset leg establishes the initial conditions of the row latch 52R. The reset leg is formed from an NMOS reset transistor 76R coupled between the control node 68R and ground. The reset signal RST drives the gate of the reset transistor 76R, such that when the reset signal RST is high, the reset transistor connects the control node 68R to ground. When the reset leg pulls the inverter input low, it forces the output sigmal FR to go low. This turns off the second transistor 58R. The T(RAS) signal is also high, because the initial conditions are established when address detection is inactive. Therefore, the first transistor 56R is also off. With both the first and second transistors 56R, 58R off, the voltage at the node 64R is pulled low. The row latch 52R is thus forced into the stable state described above with the output signal FR low, and the row latch remains) set even after the reset signal RST is removed.
The second or reference leg forms a self-decoupling current path for blowing the antifuse 48R. The reference leg includes a pass NMOS transistor 78R and a decoupling NMOS transistor 80, serially coupled between the control node 68 and ground. The pass transistor 78R is controlled by a row address signal RAx which represents a bit of an address. The address signal RAx is active when the T(RAS) signal is active, such that the pass transistor 78R conducts when RAx is high (inactive) and blocks current when RAx is low (active). If the address signal RAx is low, the pass transistor 78R deactivates the reference leg so that it does not affect the response of the row latch 52R.
The decoupling transistor 80 is controlled by an antifuse programrmng signal FAMx that represents one bit of an address to be programmed into the bank of antifuses. The decoupling transistor 80 (and the pass transistor 76R) couple the control node 68R to ground only when the particular bit for the programmed address is high (i.e., FAMx is high). When the control node 68R is coupled to ground through the decoupling transistor 80, a high voltage can be applied as the CGND signal to the switchable node 50 during programming to program the antifuse 48R.
The third or antifuse sense leg includes an NMOS drop transistor 82R serially connected with the antifuse 48R between the control node 68R and the switchable node 50. The gate of the drop transistor 82R is directly coupled to the supply voltage V.sub.CC (or a higher voltage V.sub.CCp) so that the arop transistor is always on. The drop transistor 82R therefore acts as a resistive element between the control node 68R and the antifuse 48R. Also, the drop transistor 82R limits the maximum voltage applied to the control node 68 during programming of the antifuse 48R to the supply voltage V.sub.CC minus the threshold voltage V.sub.T of the drop transistor. Consequently, the drop transistor 82R limits the drair-to-gate voltages of the transistors 76R, 78R and the source-to-gate voltage of the control transistor 60R to limit breakdown of the gate oxide.
When the antifuse 48R is unblown, the antifuse 48 forms an open circuit, and thus does not affect the voltage at node 68R and does not affect the latch 52. When the antifuse 48R is blown, however, the antifuse 48 has an impedance of approximately 5 k.OMEGA.. The blown antifuse 48R and drop transistor 82R form a conductive path between the control node 68R and the switchable node 50, allowing the switchable signal CGND to affect the voltage at control node. During address detection, the switchable signal CGND is coupled to ground, pulling down the voltage at the control node 68R, which causes the input of the inverter 62R to go low, tripping the latch 52R. The output signal FR then goes low, indicating that the antifuse 48R is blown. The output signal FR remains low even when the T(RAS) signal goes high, because the control transistor 66R, the drop transistor 82R and the blown antifuse 48R draw sufficient current to overpower the third transistor 60R. Thus, when the antifuse 48R is blown, the output signal FR goes low and stays low.
As noted above, for an eight bit address word, eight of such antifuse circuits 46 are required to address a redundant row and a redundant column. If a memory device employs eight redundant rows and eight redundant columns, sixty-four of such antifuse circuits 46 (for eight antifuse banks) are required. Sixty-four of such antifuse circuits 46 adds to the complexity of the memory device, which can increase the probability of defects, and possibly increase the number of manufacturing/processing steps.
Additionally, sixty-four of such antifuse circuits 46 consume substrate area on a die onto which the memory device is formed. Furthermore, certain transistors in each of the anrifuse circuits 46 must be able to withstand high voltages during programming of the antifuses (e.g., transistors 60R, 60C, 78R, 78C, 80, 82R, and 82C). These high voltage transistors also require increased substrate area over typical transistors. Semiconductor circuit designers always desire to reduce substrate area to allow additional functionality to be added to a given device, allow for improved manufacturing tolerances, etc. Therefore, it would be desirable to reduce the number of antifuse circuits 46.
An additional shortcoming of the prior antifuse circuits relates to the lengthy time required to latch a signal in the row/column latch 52R, 52C. As noted above, the third transistor 60R (and 60C) has a high channel resistance. Since the row latch 52R unnecessarily has an inherent RC time constant required to latch a signal therein, an increased resistance caused by the transistor 60R therefore increases the RC time constant. As a result, the row latch 52R (and the column latch 52C) is slower to latch the output signal FR therein, than if the transistor 60R had a low channel resistance. As the speed of memory devices increases, there is increasing need for faster circuitry employed therein, including antifuse bank circuitry, which must be accessed during each read/write operation. The third transistor 60R provides a high resistance path from V.sub.CC to ground if the antifuse 48R (or 48C) is blown (i.e., the path through the transistors 56R, 60R, 66R, and 82R). Without such a high resistance path, high current flow through this path could damage the antifuse circuit 46. Consequently, the high resistance element cannot be removed from the path to speed up the response time of the antifuse circuit 46.

Shared pull-up and selection circuitry for programmable cells such as antifuse cells


Embodiments of this application disclose a precoding matrix determining method and apparatus, to determine a stage-1 precoding matrix based on indication information that is of a spatial correlation matrix and that is fed back by a terminal, thereby implementing three-dimensional precoding based on a channel state and increasing a channel capacity. The method includes: sending, by a base station, a plurality of groups of first reference signals, where the plurality of groups of first reference signals are in a one-to-one correspondence with a plurality of dimensions of an antenna array, and each of the plurality of groups of first reference signals is used by a terminal to estimate spatial correlation matrix information in a corresponding dimension; receiving the spatial correlation matrix information fed back by the terminal based on the plurality of groups of first reference signals; and determining a stage-1 precoding matrix based on the spatial correlation matrix information.

Massive multiple-input multiple-output (Massive MIMO) is a well-known key technology of the 5th generation mobile communication (5G) in the industry. In a massive MIMO system, massive antenna arrays are used to significantly improve spectral efficiency. As a quantity of antennas increases, a large quantity of ports are required for measuring channel state information (CSI), and pilot overheads are high.
In the Long Term Evolution (LTE) Release 13 (R13), a two-stage precoding structure may be supported. In two-stage precoding, spatial dimension reduction is implemented by performing stage-1 precoding at an intermediate radio frequency to reduce complexity and costs, and by performing stage-2 precoding on a baseband to suppress multi-user interference.
However, in an existing two-stage precoding structure, stage-1 precoding is fixed vertical precoding, and an antenna downtilt is adjusted by simulating beamforming. As a result, a beam changes only in a vertical direction. In this method, a channel state cannot be accurately matched based on a spatial feature of a user channel, and consequently, a channel capacity is also not optimal. Therefore, a technology needs to be provided, so that a stage-1 precoding matrix can be determined based on the channel state, thereby implementing three-dimensional precoding and increasing the channel capacity.

Precoding matrix determining method and apparatus


A method and apparatus for controlling uplink transmission power in a mobile communication system are provided. In the method, an Advanced Mobile Station (AMS) determines uplink transmission power based on a measured path loss, an uplink noise and interference level received from an Advanced Base Station (ABS), a target Signal-to-Noise and Interference Ratio (SINR), and an offset. An initial offset value is determined based on a number of retransmissions of an initial ranging code performed until an initial ranging process is completed, a transmission power unit used for retransmission of the initial ranging code, and a power correction value received from the ABS upon completion of the initial ranging process with the ABS.

1. Field of the Invention
The present invention relates to an apparatus and method for controlling uplink transmission power in a mobile communication system. More particularly, the present invention relates to controlling uplink transmission power by compensating for the difference between a downlink path loss and an uplink path loss in a mobile communication system.
2. Description of the Related Art
To increase system capacity and improve service quality, a mobile communication system adopts downlink and uplink transmission power control schemes. However, the uplink transmission power control scheme of current mobile communication systems was designed with no regard to the disparity between a downlink path loss and an uplink path loss. This means that the conventional uplink transmission power control scheme is based on the premise of the same downlink and uplink path loss.
A mobile communication system such as a Frequency Division Duplexing (FDD) communication system may operate in different operation frequency bands, or a downlink gain may be different from an uplink gain in an area managed by a repeater. The FDD communication system may be, for example, an Institute of Electrical and Electronics Engineers (IEEE) 802.16m communication system based on Orthogonal Frequency Division Multiple Access (OFDMA).
Despite the possibility of different downlink and uplink path losses in case of different operation frequency bands or in case of different downlink and uplink gains, the conventional uplink transmission power control scheme was designed on the assumption that the downlink path loss is equal to the uplink path loss. Accordingly, if the downlink path loss is different from the uplink path loss, uplink transmission power control is not effective.

Apparatus and method for controlling uplink transmission power in a mobile communication system


An improved flush system as described herein may comprise a reservoir with a drain opening for egress of liquids disposed in the reservoir into a surrounding toilet tank. A lock mechanism is slidably received by the reservoir so that the lock mechanism is translatable between one or more fixed positions on the reservoir. In turn, translating the lock mechanism into the reservoir at increasing depths causes a size of the drain opening to be reduced and therefore adjusted.

The present disclosure relates to toilet flush valves configured to impart multiple flush types (e.g. dual flush) from a toilet tank into a toilet bowl. For purposes of discussion, a toilet tank typically has a flush valve system that is forced opened and remains opened until a predetermined volume of liquid flows from the tank into the toilet bowl through the flush valve system. Liquid is supplied to the toilet tank through a fill valve from a liquid supply line to the toilet tank. In practice, the fill valve opens when the fluid level in the tank falls below a predetermined liquid level.
Flush valve assemblies typically include a flush valve, a float and an actuation mechanism. The actuation mechanism causes the flush valve to open and release liquids stored in tank into the toilet bowl and close when the float reaches a predetermined liquid level in the tank. For a dual flush valve, the toilet bowl may be refilled with liquids during the time the fill valve fills the toilet tank. The predetermined volume of liquid that refills the toilet bowl is sufficient to seal off the trap way of the bowl. In practice this predetermined volume amount may be defined as ratio of the total liquid volume supplied by the fill valve during a particular flush cycle. The fill valve feeds the liquids and feeds them to the tank bowl.
Toilets that can impart dual flushes have been found to be particularly advantageous in several situations. Specifically, prior to initiating a flush, a user may choose between a large flush water volume for solid waste (e.g. a full flush) or a smaller flush water volume for liquid waste (e.g. a partial flush). This may be done via a switch, button or the like on the actuation mechanism.
In general, dual flush valves (shown in FIG. 2) may be equipped with a flush volume controlling device associated with a flush volume, a drain opening lock, and full and partial flush control devices in order to maximize the volume of respective full and partial flushes. Full and partial flush control devices are typically adjustable to maximize respective flush volumes. Typically, a drain opening controls water inside of the reservoir that holds the full flush float. The size of the reservoir drain opening is controlled by the window lock that ultimately determines the full flush volume. In practice, OEM toilet manufacturers may preset the window lock position for their respective toilet models to comply with code such as watersense.
However, if the end user is able to alter the window lock setting, such alteration may violate the code due to the approved flush volume change. Accordingly, there is a need to resolve this problem so that end users are prevented from altering window lock settings.


A filter cartridge for operatively coupling to an appliance interface to treat a fluid, such as water, being supplied to the appliance. The interface comprises a bypass valve for actuating the interface between a bypass mode in which the fluid flowing through the interface does not flow through the filter cartridge and a treatment mode in which the fluid flowing through the interface is directed through the filter cartridge for treatment by the filter cartridge. The filter cartridge comprises a cartridge housing having a first end and a second end and extending along a housing longitudinal axis through the first end and the second end. A filter media is contained within the cartridge housing between the first end and the second end. The filter cartridge also has a first end cap on the first end of the cartridge housing and a second end cap on the second end of the cartridge housing. A bypass valve actuator is attached to the cartridge housing and extends distally to an actuator distal end. The bypass valve actuator is configured such that the actuator distal end actuates the bypass valve of the interface as the filter cartridge is coupled to interface.

The field of the invention generally relates to fluid treatment cartridges, and more particularly, to a removable filter cartridge for an appliance, such as a refrigerator.
Removable water filter cartridges have previously been disclosed for use in appliances which utilize water, especially where the water is for human consumption. For example, water filter cartridges have been used in refrigerators to filter the water to supply the ice maker used to supply an automatic ice maker and/or a water dispenser built into the refrigerator. A water supply line is connected to the refrigerator to supply the water to the refrigerator, and the water is routed through tubing in the refrigerator to the water filter cartridge and then to the ice maker and/or water dispenser. Several examples of refrigerators having water filter cartridges are disclosed in U.S. Pat. Nos. 6,120,685, 6,337,105, 7,000,894 and 7,147,773.
Because the water filter cartridges eventually become ineffective and need to be changed, a water filter cartridge and an appliance interface to which the water filter cartridge is connected are configured to allow the water filter cartridge to be removed and replaced with a new water filter cartridge. The water filter cartridge has a cartridge inlet, a cartridge outlet, and a filter in fluid communication with the cartridge inlet and cartridge outlet. The interface, also referred to herein as a head assembly, includes an inlet port which connects to the cartridge inlet and an outlet port which connects to the cartridge outlet. The interface also has a supply inlet connected to the water supply and a supply outlet which supplies the water to the ice maker and/or water dispenser.
In order to facilitate the replacement of the water filter cartridge, i.e. the removal of a used cartridge and installation of a new cartridge, some previous appliance interfaces have valves which are actuated by the water filter cartridge, such as upon installing and removing the water filter cartridge to the appliance interface. Some interfaces also include a bypass valve which is opened when a water filter cartridge is not installed in order to allow water to flow to the ice maker and/or water dispenser even without a water filter cartridge. Thus, the water filter cartridge may also actuate the bypass valve such that installing the water filter cartridge closes the bypass valve, and removing the water filter cartridge opens the bypass valve. Examples of filter cartridges which actuate an inlet and outlet valve and/or a bypass valve are disclosed in U.S. Pat. Nos. 7,000,894, 7,147,773, and 5,256,285.