A programmable logic device (PLD) includes dynamic lookup table (LUT) circuits, an interconnect structure implemented in either dynamic or static logic, and optional static logic circuits. Each dynamic LUT circuit has paired true and complement input terminals and provides to the interconnect structure both true and complement output signals pre-charged to a first known value. In some embodiments, the LUT circuits are self-resetting circuits that detect when the paired input signals are valid and evaluate the LUT output values at that time. Once a valid LUT output value has been produced, the LUT resets itself in anticipation of the next valid input condition. In some embodiments, the LUT circuits are implemented using clocked dynamic logic. Routing multiplexers in the interconnect structure can be static or dynamic logic, optionally skewed. Clocked LUTs and routing multiplexers use either of two clock phases under the control of configuration memory cells of the PLD.

Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more "function blocks" connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms "PLD" and "programmable logic device" include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
FIG. 1 is a simplified illustration of an exemplary FPGA. The FPGA of FIG. 1 includes an array of configurable logic blocks (LBs 101a–101i) and programmable input/output blocks (I/Os 102a–102d). The LBs and I/O blocks are interconnected by a programmable interconnect structure that includes a large number of interconnect lines 103 interconnected by programmable interconnect points (PIPs 104, shown as small circles in FIG. 1). PIPs are often coupled into groups (e.g., group 105) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. Some FPGAs also include additional logic blocks with special purposes (not shown), e.g., DLLs, RAM, and so forth.
FIG. 2 illustrates in simplified form a configurable logic element (CLE) for an FPGA. CLE 200 of FIG. 2 includes four similar slices SLICE_0–SLICE_3. Each slice includes two lookup tables (LUTs) 201 and 202, a write control circuit 205, two multiplexers MUX1 and MUX2, and two output memory elements 203 and 204. The lookup tables, write control circuit, multiplexers, and output memory elements are all controlled by configuration memory cells M1–M7. Note that at least some of configuration memory cells M1–M7 represent more than one memory cell. Additional configuration memory cells and logic elements are omitted from FIG. 2, for clarity.
Each LUT 201, 202 can function in any of several modes. When in lookup table mode, each LUT has four data input signals IN1–IN4 that are supplied by the FPGA interconnect structure (not shown) via input multiplexers (not shown). (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) When in RAM mode, input data is supplied by an input terminal RAM_DI_1, RAM_DI_2 to the DI terminal of the associated LUT. RAM write operations in both LUTs are controlled by write control circuit 205, which supplies one or more write control signals W to both LUTs based on RAM control signals provided by the interconnect structure.
Each LUT 201, 202 provides a LUT output signal to an associated multiplexer MUX1, MUX2, which selects between the LUT output signal and an associated register direct input signal Reg_DI_1, Reg_DI_2 from the interconnect structure. Thus, each LUT can be optionally bypassed. The output of each multiplexer MUX1, MUX2 is provided to the data input terminal D of an associated output memory element (203, 204 respectively). Memory elements 203 and 204 are clocked by a clock signal CK (e.g., provided by a global clock network) and controlled by various other register control signals (e.g., from the interconnect structure or provided by configuration memory cells of the FPGA). Each memory element 203, 204 provides a registered output signal Q1, Q2. The output of each LUT 201, 202 is also provided to an output terminal OUT1, OUT2 of the CLE. Thus, each output memory element can be optionally bypassed. The slice also includes output multiplexers (not shown) that select from among the various output signals of the slice and provide the selected signals to the FPGA interconnect structure. These output multiplexers are also controlled by configuration memory cells (not shown).
One programmable element commonly found in FPGA logic blocks is the lookup table, or LUT. A LUT is a memory array (e.g., a 16×1 array) addressable by a number of input signals (e.g., four input signals). By programming predetermined values into the memory array, the LUT can implement any function of the input variables. While 4-input LUTs are common, LUTs having more or fewer input signals can also be implemented that will accommodate larger or smaller logic functions.
FIG. 3 illustrates in simplified form a well known 4-input lookup table (LUT) for a PLD. The lookup table is implemented as a four-stage 16-to-1 multiplexer. The four input signals A1–A4 together select one of 16 values stored in memory cells MC-0 through MC-15. Thus, the lookup table can implement any function of up to four input signals.
The four input signals A1–A4 are independent signals, each driving one stage of the multiplexer. Inverted versions A1B–A4B of signals A1–A4 are generated by inverters 401–404, respectively. Sixteen configuration memory cells MC-0 through MC-15 drive sixteen corresponding inverters 310–325, each of which drives a corresponding CMOS pass gate 330–345. In a first stage of the multiplexer, paired pass gates 330–331 form a 2-to-1 multiplexer controlled by signals A1 and A1B, which multiplexer drives a CMOS pass gate 346. Pass gates 332–345 are also paired in a similar fashion to form similar 2-to-1 multiplexers driving associated pass gates 347–353. In a second stage of the multiplexer, paired pass gates 346–347 form a 2-to-1 multiplexer controlled by signals A2 and A2B, which multiplexer drives an inverter 305. Similarly, pass gates 348–353 are paired to form similar 2-to-1 multiplexers driving associated inverters 306–308.
In a third stage of the multiplexer, driven by inverters 305–308, pass gates 354–355 are paired to form a 2-to-1 multiplexer controlled by signals A3 and A3B and driving a CMOS pass gate 358. Similarly, pass gates 356–357 are paired to form a similar 2-to-1 multiplexer driving a CMOS pass gate 359. In a fourth stage of the multiplexer, pass gates 358–359 are paired to form a 2-to-1 multiplexer controlled by signals A4 and A4B and driving an inverter 309. Inverter 309 provides the LUT output signal OUT.
FIG. 4 illustrates a known configuration memory cell and pass gates controlled by the configuration memory cell. A configuration memory cell typically includes two cross-coupled logic gates, such as the two inverters formed by P-channel transistor 401 and N-channel transistor 403, and by P-channel transistor 402 and N-channel transistor 404. The output nodes of the two cross-coupled logic gates are referred to herein as "storage nodes". The storage node of the first inverter is node Q. In FIG. 4, node Q drives pass gates 407. Pass gates 407 can be, for example, part of a routing multiplexer, lookup table, user storage element (e.g., block RAM or any other type of memory available for the storage of user data), or other configurable logic element. In some configuration memory cells, node QB, the storage node of the second inverter, drives the pass gates. In some configuration memory cells, both storage nodes Q and QB are used to drive logic external to the cell.
An N-channel transistor 405 is coupled between node Q and a first bit line BIT, and gated by a word line WORD. Another N-channel transistor 406 is coupled between node QB and a second bit line BITB, which carries an inverse value from the first bit line. Transistor 406 is also gated by word line WORD. Bit lines BIT and BITB are used to carry values written to the configuration memory cell, and also to read values from the configuration memory cell, e.g., during a configuration readback procedure. Variations on the circuit of FIG. 4 are also well known, e.g., two word lines can be provided, or only one bit line can be included. The circuit of FIG. 4 is a representative example of the various well-known memory cell configurations.
A PLD interconnect structure can be complex and highly flexible. For example, Young et al. describe the interconnect structure of an exemplary FPGA in U.S. Pat. No. 5,914,616, issued Jun. 22, 1999 and entitled "FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines", which is incorporated herein by reference in its entirety.
As described above, programmable interconnect points (PIPs) are often coupled into groups (e.g., group 105 of FIG. 1) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. A routing multiplexer can be implemented, for example, as shown in FIG. 5. The illustrated circuit selects one of several different input signals and passes the selected signal to an output terminal. Note that FIG. 5 illustrates a routing multiplexer with eight inputs, but PLD routing multiplexers typically have many more inputs, e.g., 28, 30, or 32. However, FIG. 5 illustrates a smaller circuit, for clarity.
The circuit of FIG. 5 includes eight input terminals IN0—IN7 and ten pass gates 500–509. Pass gates 500–503 selectively pass input signals IN0—IN3, respectively, to a first internal node INT1. Each pass gate 500–503 has a gate terminal driven by a configuration memory cell M12–M15, respectively. Similarly, pass gates 504–507 selectively pass input signals IN4—IN7, respectively, to a second internal node INT2. Each pass gate 504–507 has a gate terminal driven by one of the same configuration memory cells M12–M15, respectively. From internal nodes INT1, INT2, pass gates 508, 509 are controlled by configuration memory cells M10, M11, respectively, to selectively pass at most one signal to a third internal node INT3.
The signal on internal node INT3 is buffered by buffer BUF to provide output signal ROUT. Buffer BUF includes two inverters 511, 512 coupled in series, and a pullup (e.g., a P-channel transistor 513 to power high VDD) on internal node INT3 and driven by the node between the two inverters.
Values stored in configuration memory cells M10–M15 select at most one of the input signals IN0–IN7 to be passed to internal node INT3, and hence to output node ROUT. If none of the input signals is selected, output signal ROUT is held at its initial high value by pullup 513.
Clearly, a circuit implemented in flexible programmable logic such as that shown in FIGS. 1–5 can potentially be slower than circuitry implemented using dedicated logic (i.e., logic designed for a specific purpose). For example, a circuit implemented using LUTs and flip-flops might need to traverse a succession of LUTs and interconnections between each pair of successive flip-flops, as shown in FIG. 6. The exemplary signal path illustrated in FIG. 6 connects an output terminal of flip-flop 601 with an input terminal of flip-flop 609, and sequentially traverses interconnect 602, LUT 603, interconnect 604, LUT 605, interconnect 606, interconnect 607, and LUT 608. The path delay includes one clock-to-out delay for flip-flop 601, four interconnect delays, three LUT delays, and one setup time for flip-flop 609. The total of these delays determines the minimum clock period for the illustrated signal path.
In non-programmable circuits, one known method of increasing circuit performance is the use of dynamic logic. In dynamic circuitry, many or all nodes (e.g., all output nodes) are pre-charged to a first known value. This state is referred to herein as the "pre-charge state". At a later time the circuit enters the "evaluation state", in which the pre-charge is released and some of the pre-charged nodes change to a second known value, as determined by the logic. In clocked dynamic logic, for example, all nodes can be pulled high at a falling edge of a clock, and then some of the nodes are selectively pulled low at the rising edge of the clock. Therefore, whenever the clock is low the circuit is in the pre-charge state, and whenever the clock is high the circuit is in the evaluation state. (Clearly, dynamic circuits also can be designed to operate in the opposite fashion, i.e., to be in the pre-charge state whenever the clock is high, and in the evaluation state whenever the clock is low.) Thus, only the falling edge on the pre-charged nodes is speed-critical, and circuitry can be skewed for a fast falling edge and a slow rising edge on these nodes. Another type of known dynamic logic uses a self-resetting technique, in which the output node is pre-charged during the pre-charge state, then is conditionally discharged (evaluated) whenever an input node of the circuit changes state. Thus, a low pulse might or might not appear at the output node, based on the values of the various input signals.
The application of dynamic logic principles to PLDs is not straightforward. For example, if dynamic logic is applied to the LUT of FIG. 3, the circuit will not work, because the LUT output signals are non-monotonic. In other words, a LUT output signal can go either high or low (i.e., change state in either direction) depending on the contents of the memory cells, the values of the various input signals, and the relative timing of the input signals. However, LUTs and interconnect are widely used in FPGAs and can consume the largest percentage of the available cycle time in critical timing paths. Therefore, it is desirable to provide LUTs and interconnect circuits that enable the use of dynamic circuitry in PLDs.

High performance programmable logic devices utilizing dynamic circuitry


The present invention relates to polynucleotide and polypeptide molecules for PAR4, a novel member of the protease-activated receptor family. The polypeptides, and polynucleotides encoding them, mediate biological responses and/or cellular signaling in response to proteases. Protease cleavage of PAR4 exposes a PAR4 extracellular amino terminal portion that serves as a ligand for the PAR4 receptor. PAR4 may be used as a target in drug screening, and further used to identify proteinaceous or non-proteinaceous PAR4 agonists and antagonists. The present invention also includes antibodies to the PAR4 polypeptides.

An intriguing question in cell biology relates to the mechanism(s) by which proteases activate cells. In recent years, a subfamily of G protein-coupled receptors capable of mediating cellular signaling in response to proteases has been identified (T. K. H. Vu et al, Cell 64:1057–68, 1991; U. B. Rasmussen et al. FEBS Lett. 288:123–28, 1991; S. Nystedt et al., Proc. Natl. Acad. Sci. USA 91:9208–12, 1994; H. Ishihara et al., Nature 353:674–77, 1997). Members of this unique G protein-coupled receptor family include protease-activated receptors PAR1, PAR2 and PAR3. These receptors are characterized by a tethered peptide ligand at the extracellular amino terminus that is generated by minor proteolysis.
The first identified member of this family was the thrombin receptor presently designated protease-activated receptor 1 (PAR1). Thrombin cleaves an amino-terminal extracellular extension of PAR1 to create a new amino terminus that functions as a tethered ligand and intramolecularly activates the receptor (T. K. H. Vu et al, Cell 64:1057–68, 1991). PAR2 mediates signaling following minor proteolysis by trypsin or tryptase, but not thrombin (S. Nystedt et al., Proc. Natl. Acad. Sci. USA 91:9208–12, 1994). Knockout of the gene coding for PAR1 provided definitive evidence for a second thrombin receptor in mouse platelets and for tissue-specific roles for different thrombin receptors (A. Connolly et al., Nature 381:516–19, 1996). PAR3 was identified recently as a second thrombin receptor mediates phophatidyl inositol 4,5 diphosphate hydrolysis, and was found to be expressed in a variety of tissues (H. Ishihara et al., Nature 353:674–77, 1997). Many other proteases (such as factor VIIa, factor Xa, factor XIIa, protein C, neutrophil cathepsin G, mast cell tryptase, and plasmin) display cellular effects. Therefore, additional members of the PAR family are expected to exist (S. R. Coughlin, Proc. Natl. Acad. Sci. USA 91:9200–02, 1994; M. Molino et al., J. Biol. Chem. 272:11133–41, 1997).
The present invention provides an additional member of the PAR family, a novel human protease-activated receptor designated PAR4 (alternatively designated ZCHEMR2). The PAR4 polypeptide is an appropriate target for drug screening, and has other uses that should be apparent to those skilled in the art from the teachings herein.

Protease-activated receptor PAR4 (ZCHEMR2)


An exercise machine comprising a weighted spool assembly having a shaft that freely rotates upon bearings. To accelerate the weighted spool assembly, a user applies a pulling force to a strap assembly. With the strap assembly in a coiled position, the user applies the pulling force causing the weighted spool assembly to rotate in a first direction, uncoiling the strap assembly, until the length of the strap assembly is exhausted. Once exhausted, the weighted spool assembly continues to rotate in the first direction causing the strap assembly to coil upon it. While the strap assembly is coiling and to decelerate, the user then applies a resistance force. Once the strap assembly is coiled again, the user reapplies the pulling force causing the weighted spool assembly to rotate in a second direction, uncoiling the strap assembly, until the length of the strap assembly is again exhausted.

1. Field of the Invention
The present invention relates to exercise equipment, and more particularly, to exercise machines having a weighted spool assembly.
2. Description of the Related Art
Several designs for exercise machines have been designed in the past. None of them, however, includes a weighted spool assembly having a shaft that freely rotates upon bearings. Whereby, to accelerate the weighted spool assembly, a user applies a pulling force to a strap assembly that is fixed at a distal end to the weighted spool assembly. With the strap assembly in a coiled position, the user applies the pulling force causing the weighted spool assembly to rotate in a first direction, uncoiling the strap assembly, until the length of the strap assembly is exhausted. Once exhausted, the weighted spool assembly continues to rotate in the first direction causing the strap assembly to coil upon it. While the strap assembly is coiling and to decelerate, the user then applies a resistance force. Once the strap assembly is coiled again, the user reapplies the pulling force causing the weighted spool assembly to rotate in a second direction, uncoiling the strap assembly, until the length of the strap assembly is again exhausted.
Applicant believes that the closest reference corresponds to U.S. Pat. No. 6,761,670 issued to Liou for Exerciser having an improved resistive device, on Jul. 13, 2004. However, it differs from the present invention because Liou teaches an exerciser including a wheel and a housing rotatably engaged on a shaft, a bearing disposed between the wheel and the housing for allowing the wheel to be rotated in an active direction by the housing and to be prevented from rotating in a reverse direction by the housing. A strap may be used to rotate the housing in the active direction. A spring may bias the housing to rotate in the reverse direction, and will not bias the wheel when the spring biases the housing to rotate backward in the reverse direction, such that the spring will not be damaged by the wheel.
Applicant believes that another close reference corresponds to U.S. Pat. No. 5,645,514 issued to Chen for Pulling type exerciser, on Jul. 8, 1997. However, it differs from the present invention because Chen teaches an exerciser including a base tube and an extension slidably engaged in the base tube. The extension includes a front end movable outward of the base tube. A frame is secured to the front end of the extension for supporting a shaft and a pulley. One or more wheels are secured on the shaft for facilitating the movement of the extension relative to the base tube. A resilient hand is received in the base tube and the extension and has a front end engaged over the pulley. A handle is secured to the front end of the resilient band for exercising the upper muscle.
Applicant believes that another close reference corresponds to U.S. Pat. No. 4,880,224 issued to Jonas, et al. for Rowing machine, on Nov. 14, 1989. However, it differs from the present invention because Jonas, et al. teaches a frame member having a seat mounted thereon, the seat being movable therealong. The frame member also carries feet rests. A shaft is mounted across the frame member at one end thereof, and a flywheel is mounted on the shaft. A planetary gear system having a rotatable carrier, pinion gears mounted in the carrier, a stationary ring gear and a central gear is mounted on the shaft for rotatably driving the flywheel. The central gear is mounted on the shaft for rotation therewith. A spool is mounted on the carrier for rotation therewith. A cable is wound around the spool for providing rotary motion to the spool when the cable is pulled by an exerciser during the rowing stroke. Thus, the rotary motion of the spool is transferred to the flywheel through the planetary gear system and the shaft in a speed increasing mode.
Other patents describing the closest subject matter provide for a number of more or less complicated features that fail to solve the problem in an efficient and economical way. None of these patents suggest the novel features of the present invention.


A light emitting structure includes lower and upper semiconductor layers having different conductive types, and an active layer disposed between the lower and upper semiconductor layers. The light emitting structure is provided on the substrate. A first electrode layer provided on the upper semiconductor layer includes a first adhesive layer and a first bonding layer overlapping each other. A reflective layer is not provided between the first adhesive layer and the first bonding layer.

1. Field
Embodiments relate to a light emitting device and a light emitting device array including the same.
2. Background
Red, green and blue light emitting diodes (LEDs) exhibiting high luminance and enabling rendering of white light were developed based on the growth of metal organic chemical vapor deposition and molecular beam epitaxy of gallium nitride (GaN).
Such a light emitting diode (LED) has superior eco-friendliness because it does not contain environmentally harmful substances such as mercury (Hg) used in conventional lighting apparatuses such as incandescent lamps or fluorescent lamps, and serves as an alternative to conventional light sources due to advantages of long lifespan and low power consumption. The key factors in competitiveness of such LEDs are to realize high luminance, based on high-efficiency high-power chips and packaging technologies.
In order to realize high luminance, increase in light extraction efficiency is important. A variety of methods using flip-chip structures, surface texturing, patterned sapphire substrates (PSSs), photonic crystal techniques, anti-reflective layer structures and the like are being researched in order to increase light extraction efficiency.
In general, a light emitting device may include a light emitting structure including a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a first electrode to supply a first power to the first conductive type semiconductor layer and a second electrode to supply a second power to the second conductive type semiconductor layer which are disposed on the substrate.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.

Light emitting device and light emitting device array


A cordless device for dispensing a viscous material including housing components for a product cartridge, a DC motor, an air pump, and a rechargeable battery. The device has a pressure limiting switch that maintains a pre-determined pressure of compressed air in a gas enclosure. A manually actuated trigger, when depressed, is adapted to open a flow valve allowing the device to forcefully dispense the viscous material from the product cartridge.

In general, many portable pressure driven viscous product dispensing devices receive an input of relatively high pressure gas which is used to output a viscous product at a relatively low pressure. The dispensing devices typically regulate the high pressure gas using a pressure regulator. In this way, a source of high pressure gas can be used to drive devices that require only a fraction of the high pressure to operate properly. Exemplary sources of high pressure gas include, for example, tanks of compressed air, aerosol containers and commercially available CO2 gas cartridges.
Unfortunately, pressurized containers such as CO2 gas cartridges cannot be shipped via standard air shipment, therefore complete product packages cannot be easily shipped from the manufacturer for retail sales. Moreover, the cost of pressure regulators and replacement pressurized gas sources can become significant in relation to the overall cost of the device into which it is incorporated. This can be true, for example, in relation to dispensing devices for dispensing a viscous product from a viscous product cartridge. Such viscous product cartridges are commonly used in association with adhesives, caulks and other sealants. During extended periods of use, construction workers and other professionals may often require many replacement pressurized gas containers to complete their work. Thus, it has been discovered that a low cost, reliable pressurizing system is desirable to provide a potentially unlimited supply of pressurized gas; particularly for use in cordless dispensing devices for dispensing a viscous product from a viscous product cartridge.


Provided herein is a microwave device using a magnetic material nano wire array and a manufacturing method thereof, the device including a template having a nano hole array filled with a metal magnetic material.

1. Field of Invention
Various embodiments of the present invention relate to a microwave device and a manufacturing method thereof, and more particularly to a circulator puck using a magnetic material nano wire array and a manufacturing method thereof.
2. Description of Related Art
In microwave communication, a circulator is a device that that can be directly connected to an antenna. Connected to the antenna, the circulator plays the role of changing the connection state to and from transmission and reception. An isolator is a device that has a function of proceeding microwaves in only one direction just as a diode of in a semiconductor device.
FIG. 1 is a view for explaining operation principles of a circulator. As illustrated in FIG. 1, the circulator adjusts the direction of progress of a microwave using changes in the phase velocity of the microwave due to changes in the permeability of a magnetic material regarding the microwave. Such operations of the circulator are based on the principle of the magnetic material making precession motions as the magnetic moment is aligned (magnetization) when an external static magnetic field is applied.
In general, when a linear polarized microwave enters a magnetic material, the linear polarized microwave may be decomposed into two circular polarized microwaves. That is, the linear polarized microwave may be divided into a left-circular polarized light and a right-circular polarized light, and the permeability, that is the reaction of ferrite due to the magnetic field of each of the left-circular polarized light and the right-circular light will be different from each other. In other words, due to the difference of phase velocity between the permeability (μ′+) of the light polarized in the same direction as the precession and the permeability (μ′−) of the light polarized in the opposite direction, the direction of progress will rotate as illustrated in the enlarged part (p) of FIG. 1.
Therefore, in order to rotate the direction of progress of such a wave by a certain angle, the magnetic moment of the ferrite puck must be aligned in a certain direction, and in order to do this, a conventional circulator is manufactured to include a permanent magnet for applying a magnetic field.
Conventional circulators mostly have a waveguide structure illustrated in FIG. 2a or a microstrip structure illustrated in FIG. 2b. They may also be configured in other various structures such as a stripline structure or a lumped element structure. Waveguide type circulators include a waveguide 3, and microstrip structure circulators include a metal stripline 4.
Such a conventional circulator is fitted with a magnetic material ferrite puck and a permanent magnet. More particularly, a conventional circulator includes a ferrite puck 1 of a soft magnetic material and a permanent magnet 2 for applying a magnetic field to the ferrite puck.
The permanent magnet that accounts for a significant portion of a circulator increases the cost of the circulator, and further, it is difficult to integrate the circulator with a substrate.
Not only that, for a conventional circulator, an insulating ferrite puck has to be used to minimize the loss of microwaves, and such insulating characteristics of the ferrite cannot easily release the heat energy that is generated when high power microwaves are applied, causing nonlinear characteristics and consequently deteriorating the efficiency of the circulator.
The need to use a permanent magnet can be resolved by developing a puck that can operate even when an external magnetic field is not applied by using hard magnetic (permanent magnet) materials such as Sr (strontium) ferrite or Ba (barium) ferrite, but these materials have their unique magnetic characteristics and thus cause the problem of having to operate at high frequencies only. Therefore, there still remains the problem that such a circulator cannot be used in various frequencies, and also the problem of relatively high magnetic loss.

Microwave device using magnetic material nano wire array and manufacturing method thereof

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


Two threshold parameters are used to identify the intensity modulation peaks corresponding to the interfaces of the two sides of a thin film with the adjacent media. The first parameter is used to distinguish modulation data from noise and is set on the basis of actual background noise data measured during the interferometric scan. The second parameter is used to separate actual contrast data from signals of relatively high modulation that satisfy the first parameter but do not in fact result from interference fringes. Data that satisfy both parameters are considered valid modulation data and the peak of each modulation envelope is then calculated using conventional means. The thickness of the film at each pixel is obtained by dividing the scanning distance corresponding to the two peaks by the group index of refraction of the film material.

1. Field of the Invention
This invention relates to the general field of film characterization and, in particular, to a technique for improving the process of identifying the boundary and thickness of a thin film by interferometric profilometry.
2. Description of the Prior Art
It is well known that light is reflected at the interface between two media with different indices of refraction. By interfering the light reflected from the interface of the two media with a reference beam in a scanning interferometer, an interferogram is generated with maximum contrast at a scanning position corresponding to the interface. Thus, the precise location of the interface along the scanning direction may be identified by determining the peak of the modulation envelope of the interferometric output beam generated by the scan. As is well understood in the art, this may be achieved using one of several techniques as may be most appropriate depending on the wavelength of the light, the bandwidth of the light, the data acquisition scheme, and other factors relevant to the particular interferometric system in use.
When a transparent film is present in a structure, its thickness produces two interfaces with respective reflections of an incident beam. If both reflected beams are interfered with a reference beam in a scanning interferometer, the resulting interferogram will contain two peaks of maximum contrast, each corresponding to the location of the interface between the film and the abutting material. Based on the scanning position corresponding to each contrast peak, the relative optical-length distance between interfaces may be calculated in conventional manner. The film thickness is then derived directly by dividing the optical distance by the group index of refraction of the film material.
Based on these well-known principles, it has been a practice to calculate the thickness of a film by acquiring interferometric light-intensity data during a scan to produce an interferogram from which the two peaks corresponding to the film's interfaces are identified. A light of appropriate bandwidth is used to ensure sufficient coherence length to produce interference at the scanning positions corresponding to both sides of the film and to generate identifiably separate modulation envelopes. Accordingly, a light-intensity threshold is typically used to separate intensity data corresponding to interferometric fringes from noise and constant (DC) signal components.
According to the most general prior-art approach, illustrated in FIG. 1, only data above or below (or both) predetermined thresholds T′ and T″ around the DC component are used to isolate noise and to identify the intensity measurements corresponding to the two regions of significant contrast R1, R2. Modulation envelopes are then derived from these data and used to find the peaks P1,P2 of the regions and the corresponding scanning positions Z1,Z2. Finally, the difference between the peak positions (Z2-Z1) is divided by the group index of refraction to obtain the film thickness at the location corresponding to the pixel associated with the acquired interferogram. FIG. 2 shows interference fringes corresponding to the intensity data of FIG. 1 which illustrate the progressively higher contrast seen in the vicinity of the peaks P1, P2.
In practice, it is more convenient to work with modulation data, rather than intensities. In its simplest form, modulation may be defined as the absolute value of the difference in light intensity recorded between two consecutive data-acquisition frames during a scan (alternatively, the square of the intensity difference is also used). Accordingly, as illustrated in FIGS. 3 and 4 for a single correlogram with peak P1, the modulation M (FIG. 4) of the output of the interferometer (FIG. 3) may be calculated at each scanning step and compared to a first threshold value T to eliminate data that do not reflect the presence of fringes. Since modulation increases materially at scanning positions corresponding to the vicinity of an interface (as seen in FIG. 2), the threshold T is judiciously selected to eliminate data that correspond to noise.
While this approach is theoretically sound and relatively easy to implement, in practice it is often difficult to set the threshold T at the appropriate level. If it is set too high, it becomes difficult to identify peaks characterized by relatively low maximum contrast (such as P2 in FIG. 1). If it is set too low, regions of particularly great noise may be mistakenly identified as regions of contrast and the analysis produces erroneous film-thickness results. This balance is particularly critical when measuring very thin films because the separation between the interfaces of the film sides and the adjacent media may not be sufficient to provide distinct contrast regions. That is, the signals produced by the two interfaces may overlap and yield artifacts that mask the true modulation data produced at each interface. In addition, even when the modulation envelopes are conveniently separated and the threshold parameter is set to clearly distinguish the regions of contrast from noise, different threshold parameters may be needed for materials with different indices of refraction or scattering properties in the film. Therefore, it is typically not possible to utilize this prior-art interferometric approach to characterize multiple film layers.
The present invention is based on the realization that the shortcomings of the prior-art approach may be overcome by relatively simple modifications that produce an optimal threshold level regardless of the film material and system noise. As a result, this disclosure also enables the characterization of single- as well as multi-layer film structures.

Film thickness and boundary characterization by interferometric profilometry


The present invention provides a deactivation method of multimedia broadcast multicast service for wireless communication system, comprising steps of: in SGSN, completing the context deactivation of user equipment of broadcast multicast service; in the user equipment, completing the context deactivation of user equipment of multimedia broadcast multicast service; in GGSN, completing the context deactivation of user equipment of multimedia broadcast multicast service; characterized by further comprising steps of: in SGSN, after completing the context deactivation of user equipment of multimedia broadcast multicast service, completing the context deactivation of user equipment of multimedia broadcast multicast service in a radio network controller of a radio access network. According to the method of the present invention, the context of user equipment of multimedia broadcast multicast service in the radio network controller is deleted, so that the waste of radio resources is prevented, the hidden troubles induced by the inconsistency of data among the network elements is removed, and a foundation for the correct realization of future products is laid.

MBMS is a point-to-multipoint service carrying capacity introduced by 3GPP in Release 6. Through network resource sharing, including core network and access network resource sharing, air interface resource sharing in particular, MBMS achieves transmission of point-to-multipoint service in which data is transmitted from a single data source to multiple users, so as to enhance the utilization rate of network bandwidth, especially that of air interface resources. MBMS defined by 3GPP can achieve not only multicast and broadcast of the message type in text and at a low rate but also multicast and broadcast of multimedia services at a high rate. Undoubtedly, this conforms to the trend of the development of mobile data in future.
FIG. 1 is an architectural schematic view of WCDMA communication systems providing MBMS. As shown in FIG. 1, the WCDMA MBMS network architecture realizes sharing of air interface resources based on a WCDMA/GPRS packet network and through incorporating into core network 1 new function entities, e.g. broadcast multicast service center (BM-SC) 105, adding the MBMS function to existing packet domain function entities, such as UE 101, a radio network controller (RNC not shown) located inside radio access network (RAN) 102, serving GPRS support node (SGSN) 103 and gateway GPRS support node (GGSN) 104, and defining new logic shared channels. The BM-SC 105, which is connected with multicast broadcast source 106 in public data network 2, is used for authorizing and initiating MBMS services in a mobile network and controlling the transfer of MBMS contents; the SGSN 103 and the GGSN 104, which are located in the core network 1, form a transmission network within the core network in MBMS systems to provide routing for the transfer of packet data, in which the SGSN 103 performs network control for users and the GGSN 104 establishes or releases user interface carrying for the transfer of MBMS service data; and the RAN 102 provides radio resources for MBMS services via an air interface and is responsible for the valid distribution of MBMS service data to service areas of MBMS services.
To support such a new capacity introduced into 3GPP Release 6, there is a need to define in the WCDMA network a series of MBMS service procedures, which are as follows:
MBMS Multicast Service Activation Procedure;
MBMS Session Start Procedure;
MBMS Registration Procedure;
MBMS Session Stop Procedure;
MBMS De-Registration Procedure;
MBMS Multicast Service Deactivation Procedure;
MBMS Broadcast Service Activation;
MBMS Broadcast Service De-Activation Procedure;
MBMS Broadcast Session Start Procedure.
Among them, the MBMS Multicast Service Deactivation Procedure defines signaling interaction and operation to be implemented between the UE 101 and a network when the user equipment UE 101 wishes to cancel a certain activated multicast service. Usually initiated by the UE 101, this procedure aims to remind the network that the UE 101 does not desire data service of the certain MBMS service. Through this deactivation procedure, UE context corresponding to the MBMS service (hereinafter referred to as MBMS UE context) stored in both the UE 101 and the network is deleted. The context is directly related to accurate distribution and transmission of MBMS data.
FIG. 2 is a schematic view of the prior MBMS Multicast Service Deactivation procedure. For the detailed description of the prior MBMS Multicast Service Deactivation procedure, please see 3GPP protocol (TS 23.246 V6.3.0 2004-06). The procedure illustrated in FIG. 2 takes into consideration only the removal of MBMS UE context in the UE 101, the SGSN 103 and the GGSN 104 and does not consider the removal of MBMS UE context stored in the RNC. After the MBMS Multicast Service Deactivation procedure, information on the multicast service which the UE 101 wishes to cancel is no longer on either the UE side or the core network side. That is to say, after the procedure, there will be no other trigger condition for the removal of corresponding MBMS UE Context from the RNC. Then, after the procedure in which the UE 101 cancels a certain multicast service, the corresponding MBMS UE Context is still retained in the RNC. This might result in the fact that, in the subsequent distribution procedure of the MBMS Multicast Service data, even though the UE 101 has performed deactivation on a certain MBMS service and there is no other UE that has subscribed to this MBMS service in the cell where UE 101 is located, the RNC still allots it system resources and sends corresponding service data to the cell where the UE 101 is located. Such a result not only deviates from the object of cancellation of the MBMS service the UE 101 wishes to achieve through the deactivation procedure, but also is a waste of radio resources. Moreover, MBMS UE Context stored in each network element (UE, RNC, SGSN, GGSN) is inconsistent, while the RNC will keep the information which is virtually worthless, hence a waste of the RNC's storage space. Consequently, this might lead to hidden troubles and impair correct implementation of future products.

Deactivation method of multimedia broadcast multicast service and related device


A modular drive apparatus includes a gear box (16) with a rotatable internal transmission gear (60). The gear box includes a plurality of body openings (44). The openings may be selectively closed by the installation of cover plates (52, 54). With a cover plate removed, a drive coupler (32, 34, 58, 148) may be extended in the respective opening and mounted in operative connection with the gear box. In the mounted position of the drive coupler, an idler gear (72, 172) engages the ring gear of the gear box. Rotatable power devices such as pumps, motors and generators may be operatively rotatably engaged with the drive coupler.

Power transmission systems are used to selectively deliver rotational power from a driver such as an internal combustion engine, electric motor or other source of rotational power, to one or more driven devices. Driven devices commonly include such things as pumps, electric generators, rotating machinery, the tires of a vehicle or a propeller of a water craft. Drive systems are used to selectively deliver power from the driver to the driven device.
Drive systems may have numerous different configurations. It is also not uncommon to have a need to make changes to the configuration of a drive system. Such changes may include the need to incorporate new devices and components. The configuration of drive systems sometimes make the systems difficult to reconfigure or make implementing changes difficult.
Drive systems may benefit from improvements.


A method for reactivating and recovering electrolyte cells by drilling a hole through the battery case and injecting a volume of electrolyte liquid into the case for absorption into the cell separator material. The battery is subjected to multiple charge/discharge cycles while the cell opening remains unsealed, and is subjected to a final charge prior to sealing the drilled hole through the cell outer case.

The present invention relates to a process for recovering the recharge life cycle of sealed liquid electrolyte batteries. In particular, the invention relates to a method for recovering nickel-cadmium (Ni-Cd) cells which have degraded to the point where they no longer accept or are capable of holding a voltage charge. The preferred embodiment of the invention is directed to Ni-Cd batteries, but the principles of the invention are equally applicable to other sealed liquid electrolyte rechargeable batteries, such as nickel-metal-hydride, or rechargeable alkaline batteries.
All batteries contain an electrolyte of one form or another. The purpose is to provide a medium in which ions move freely from one electrode to another, thereby allowing current flow. Both the volume and strength of the electrolyte are important to the proper operation of the battery. As long as the electrolyte parameters stay within fairly wide limits, operation is not impaired, but if either the volume or strength of the electrolyte move outside of these fairly wide limits, the battery operation degrades. In a Ni-Cd battery and many other batteries, this electrolyte takes the form of a liquid solution of potassium hydroxide (KOH) which is soaked into the insulating material and in contact with the battery electrodes.
The invention is primarily concerned with rechargeable batteries of the general type which may be discharged at peak current drains up to 10-20 amps (A) but typically operate between 0.05 and 10 ampere hour (Ah) capacities. The charging of such batteries is typically accomplished at a charge rate of 0.1-1 amps. The charge and discharge rate of batteries is frequently referred to as the "C-rate," which is defined as the current flow out of or into a cell numerically equal to the cells rated capacity. For example, the C-rate of a 1-Ah cell is 1 A; the C-rate of a 2.5-Ah cell is 2.5 A. The C-rate concept is useful to enable a comparison of different size cells on the basis of a scaling of charge and discharge rates, for different cells behave similarly in terms of their voltage and operation time when they are charged or discharged at the same C-rate. The Ni-Cd batteries can operate with discharge rates up to 20 C, and are typically recharged at rates of 0.02 C-0.3 C.
A Ni-Cd battery is typically constructed of a tightly wrapped coil of materials consisting of a cadmium plate, a nickel plate and a porous insulating material separating the plates, which material is impregnated with an electrolyte solution such as KOH. The electrochemistry of a Ni-Cd cell determines its nominal operating voltage; for a Ni-Cd battery this nominal operating voltage is 1.2 volts. The cell chemistry causes the nominal voltage to "droop" during discharge, although the discharge voltage characteristics are quite flat over an extended operating time, and the "droop" becomes sudden and quite drastic after a predetermined operating time interval. After a Ni-Cd battery has been recharged, the voltage operating characteristic returns to its initial 1.2 volt nominal voltage, and the voltage operating curve is repeatable over many subsequent charge and recharge cycles. Commercially available Ni-Cd batteries are typically advertised to have an operating life of 300-500 recharge cycles.
It has long been suspected that the failure of such batteries is caused by a drying action, whereby the separator between the electrodes becomes dry as a result of loss of electrolyte. The mechanisms which cause such electrolyte loss are not as well known, although several theories have been urged to explain such loss. One such theory contends that the positive electrodes thicken with charging and recharging cycling, and positive active material moves toward the electrode plate surface and, in so doing, greatly reduces the pore size at the surface where contact is made with the separators. The capillary action of the exposed pores is thus increased, causing electrolyte to be drawn out of the separator more strongly than when the cell was new. At the same time, the expansion of the positive-plate electrode provides more void volume inside the plates where the absorbed electrolyte is trapped so that it cannot be recirculated.
Another theory holds that a certain volume of air or other gas is always included in the pores of the electrode plates when the cells are assembled, and, the volume occupied by the nitrogen in this air will eventually become occupied with electrolyte. Some fraction of this electrolyte is likely to come from the separator, thereby drying the separator material to the extent that this migration occurs.
Another and perhaps a better theory is that the charging and recharging of the battery results in the buildup of internal heat, depending to a large extent upon the magnitude of current passing between the electrodes. As the battery internal heat builds up, it increases the internal battery pressure, and this pressure exerts an outward force along all battery seals and, in particular, can be released by an internal pressure valve mechanism which is designed into the battery for that purpose. If the internal valve mechanism permits the release of gas under excess pressure, it will also permit the release of some electrolyte or electrolyte chemicals. Over a period of extended use, this amounts to a gradual reduction in the total electrolyte remaining inside the cell, which causes the drying of the separator material.
It may also be that the continued charging and discharging of the battery, and the heat and high internal pressures associated therewith, results in a buildup of gases along the interface between the battery plates and the separator material and into the surface of the battery plates, and this gaseous buildup reduces the efficiency of transfer of ions between the plates and the electrolyte-filled separator material. Under this scenario, the gaseous buildup may not necessarily be of sufficiently high pressure so as to release the internal battery pressure valve mechanism, but the accumulation may be sufficient to reduce the charging/discharging efficiency of the battery over time. As a gaseous buildup accumulates over time, the overall battery efficiency may degrade to the point where the battery is deemed to be no longer capable of accepting the charge, and is therefore discarded.
The battery recharge cycle is a particularly important factor in battery life, as the battery recharge current may cause a buildup of internal heat in the battery. Minimum commercial battery recharge rates are about C/20, i.e., requiring 20 hours to recharge a battery to its rated capacity. However, since the battery charging efficiency is under 100 percent, it is more typical to require 36-48 hours for recharging a battery to its rated capacity. Recharging efficiency decreases as the battery nears its full recharge. As the battery is recharged to within its final few percentage points of full capacity, the cell approaches an overcharge condition, and in this condition the cell generates gaseous oxygen O.sub.2. If the recharge current rate is low, a continuous overcharge does not damage the battery since the cell can electrochemically recombine the total oxygen volume. However, if the current recharge rate is high, and particularly over the recommended recharge limits, the internally-generated O.sub.2 is expelled from the battery through the internal pressure valve mechanism. Repeated occurrences of this type causes water to dry from the electrolyte, thereby reducing the overall life expectancy of the battery. Market conditions encourage battery manufacturers to recommend faster recharge rates for their Ni-Cd batteries, and it is not uncommon for a manufacturer to recommend a "standard" charging rate of 0.2 C (16-20 hours), but also to provide recommendations for a "fast" charging rate of 1.0 C or higher, which may cause venting of internally-generated O.sub.2. It is believed that commercially-available battery cells can sustain a continuous overcharge at up to about 0.33 C and still internally recombine 100 percent of the O.sub.2 generated at this recharging rate.
A commercially-available Ni-Cd battery pack typically is an assembly of a multiplicity of Ni-Cd cells, usually connected electrically in series. This provides a predetermined battery-pack output voltage which is determined by the number of series-connected cells, and the battery capacity is determined by the respective sizes of each of the cells. However, cells of the same size and manufacture do exhibit actual capacities that differ, up to .+-.10%, from a mean value. When such cells are connected into a multi-cell capacity, these variations can cause some cells to give up the last of their usable capacity and other cells to retain a certain capacity upon discharge of the battery pack. If the extent of battery-pack discharge is deep enough, one or more cells may be brought to zero voltage, which can cause the condition known as cell reversal.
When cell reversal occurs the energy of the cell is expended to the point where any further current drain is into the cell rather than from the cell, and therefore the external circuits drive the cell instead of the reverse action. During cell reversal, the cell voltage can drop as low as -1.4 volts, which generates gaseous hydrogen (H.sub.2), which does not recombine within the cell and must be vented through the cell internal pressure valve mechanism. This condition further contributes to the loss of water from the cell, and the ultimate drying of the electrolyte within the cell.
Ni-Cd batteries can further experience actual electrolyte leakage under certain conditions, particularly conditions wherein the battery is connected into a circuit where there is a very small amount of current drain over an extended period of time. For example, in a Ni-Cd battery connected into a radio which retains some small amount of current drain even when not being operated, a small amount of electrolyte may leak from the seals of the cell in an extended time period of from one week to several months. This is known as "creep" leakage, and usually can be identified upon inspection, as a white fuzz appearing around the top seal of the cell. Such a battery can usually be recharged, although the condition does contribute to the overall shortening of the battery life cycle.
Another factor which shortens the overall life of a Ni-Cd battery is the operating environment temperature. In general, for every 10.degree. C. increase in the average temperature of operation of a Ni-Cd battery, the cell life is cut in half. This is thought to be caused by a loss of electrolyte in the cell, combined with the breakdown of the separator material which absorbs the electrolyte liquid, or an accumulation of gases which interferes with the charge/discharge process.
The foregoing and other causes eventually lead to spent batteries, wherein the batteries are no longer able to accept a recharge, and the spent batteries must then be disposed of in a suitable manner. This presents a particular problem for Ni-Cd batteries, because cadmium is considered to be a hazardous waste and, therefore, such batteries cannot be lawfully disposed of in the usual municipal waste stream. The batteries must, therefore, be recycled in a manner which permits the recovery of the cadmium, which can then be disposed of according to the rules for disposing hazardous wastes. Approximately, 300,000,000 nickel cadmium cells are purchased in the United States each year, with the number increasing each year, and therefore, the disposal of such cells presents a real and significant problem. It, therefore, would be highly advantageous if such cells could be recycled in a manner which regenerates the cell charge-accepting capacity, and permits the cell to be reused for a significant number of additional charge/discharge operating cycles.

Process for the reactivating sealed liquid electrolyte batteries


Various embodiments relate to a converter controller configured to control a resonant converter, including: an integrator configured to receive a current measurement signal from a current measurement circuit in the resonant converter and to produce a capacitor voltage signal indicative of the voltage at the resonant capacitor; a control logic configured to produce a high side driver signal, a low side driver signal, a symmetry error signal based upon the capacitor voltage signal and the current measurement signal; and a symmetry controller configured to produce a symmetry correction signal based upon the symmetry error signal, wherein the symmetry error signal is input into the integrator to control the duty cycle of the high side driver signal and the low side driver signal, wherein the high side driver signal and the low side driver signal control the operation of the resonant converter.

Resonant converters are widely used to convert a DC voltage into an AC voltage. An LLC (two inductors and one capacitor) converter is a commonly used type of resonant converter. A control method of an resonant power converter may make use of the voltage across the resonant capacitor. Furthermore, the half bridge or full bridge current is measured, such that the converter can operate near a capacitive mode or so that the current in the converter may be limited.

Combined current sense and capacitor voltage sense for control of a resonant converter


A leveling roof platform support having a base strip removably mounted on a roof. A support strip is hingedly connected to the upper end of the base strip. A pivot brace is attached between the base strip and the support strip. With a jack assembly, including a ball nut, rotatably coupled to the pivot brace for selectively pivoting the support strip with respect to the base strip and roof surface such that the support strip provides a horizontally oriented support surface upon a sloped roof.

1. Field of the Invention
The present invention relates to roof platforms and more particularly pertains to a new leveling roof platform support for maintaining a roof platform horizontally oriented.
2. Description of the Prior Art
The use of roof platforms is known in the prior art. More specifically, roof platforms heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art roof platforms include U.S. Pat. No. 5,409,266; U.S. Pat. No. 4,221,363; U.S. Pat. No. 5,113,971; U.S. Pat. No. 4,340,205; U.S. Pat. No. 5,312,088; and U.S. Pat. No. Des. 349,801.
In these respects, the leveling roof platform support according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of maintaining a roof platform horizontally oriented.


In a transmission device with switchable gear ratios, a driving gear is disposed onto an output shaft of a motor, a rocker arm is pivoted on the output shaft through an electromagnetic clutch, a rocker arm gear mounted on the rocker arm is driven by the driving gear, a first gear set is driven by the rocker arm gear when the rocker arm is at a first position, a second gear set is driven by the rocker arm gear when the rocker arm is at a second position, and the first gear set and the second gear set have different output rotating speeds. In addition, a first magnetic element attracts the rocker arm at the first position, and a second magnetic element attracts the rocker arm at the second position. Thus, the gear ratio may be switched according to interactions between the electromagnetic clutch and the magnetic elements.

1. Field of the Invention
The invention relates to a transmission device with switchable gear ratios, and more particularly to a transmission device applicable to a scanning apparatus and using magnetic elements in conjunction with a planet gear mechanism to switch the gear ratio.
2. Description of the Related Art
In a conventional flatbed scanning device, a driving device moves a scanning module back and forth. Usually, the moving speed of the scanning module is slower when a document is being scanned, and the moving speed of the scanning module is higher after the document is scanned and the scanning module has to be moved back to the original position in order to shorten the time of the overall scanning process. In addition, the moving speeds of the scanning module for scanning with a high resolution and a low resolution are also different. Thus, it is preferred that the output speed of the driving device may be changed.
In the conventional scanning device, an additional motor or an additional driving device is utilized to switch the gear ratios of power transmitting elements, such as gears in a gear set, so that the output speed may be changed. However, the added motor or driving device occupies extra space in the scanning device, which is disadvantageous to the miniaturization of the scanning device.

Transmission device with switchable gear ratios


A process for fabricating a semiconductor device, the process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.

This invention relates generally to a process for fabricating a semiconductor device having an oxide-nitride-oxide layer and, more particularly, to a process for removing a portion of the oxide-nitride-oxide layer using an isotropic etch.
Semiconductor devices are currently in widespread use in a variety of electronic devices, such as computers, stereos, telephones, cameras, engine control units, and the like. Semiconductor devices include, but are not limited to, central processing units, non-volatile memory devices, and digital signal processors. One type of semiconductor device, non-volatile memory devices, are currently in use in electronic devices that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells within these memory device can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of large blocks of memory cells using a single electrical current pulse.
Product development efforts in non-volatile memory device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many of the foregoing research goals can be addressed through development of materials and processes for the fabrication of the floating-gate electrode. Recently, development efforts have focused on dielectric materials for fabrication of the floating-gate electrode.
One important dielectric material for the fabrication of a flash EEPROM device is an oxide-nitride-oxide (ONO) layer. The ONO layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The ONO layer may serve as either a charge storage layer or an insulating layer in the flash EEPROM device. In one example, the ONO layer serves as a charge storage layer. During programming, electrical charge is transferred from the substrate to the nitride layer in the ONO layer. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the first oxide layer and become trapped in the nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the nitride layer near the source region. Because the nitride layer is not electrically conductive, the charge introduced into the nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in regions within a single continuous nitride layer. In one example, the ONO layer serves as an insulating layer for a floating gate structure within a flash EEPROM device.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory devices that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
In addition to non-volatile memory, such as a flash EEPROM, other semiconductor devices may include ONO layers as well. ONO layers can serve many different purposes, such as, for example an insulator or as a charge storage layer in a semiconductor device. While the recent advances in semiconductor fabrication technology have enabled semiconductor device designers to create much smaller semiconductor devices, numerous challenges exist in the fabrication of material layers within these devices. In particular, fabricating an ONO layer within a semiconductor device presents several challenges. As the size of features within semiconductor devices has decreased, so has the thickness of the ONO layers. Selective removal of a thin ONO layer, that is an ONO layer of less than 1000 angstroms in thickness, has becomes increasingly difficult with conventional etching techniques, such as anisotropic etching.
As illustrated in FIG. 12, anisotropic etching requires the use of an anisotropic etch chamber 60. A semiconductor device 18 is placed upon a negative plate 66 within the anisotropic etch chamber 60 between a positive plate 64 and the negative plate 66. The negative plate 66 is grounded. An RF voltage V+ is applied to the positive plate 64 to excite gases within the anisotropic etch chamber 60 and convert the gases into high energy plasma 62. Because the semiconductor device 18 is placed on the negative plate 66, the semiconductor device 18 experiences a DC bias voltage of V+, which is typically in the range of 100 to 1000 volts. The high energy plasma 62, created by the DC bias voltage of V+ is accelerated from the positive plate 64 to the negative plate 66 and into the semiconductor device 18 at a relatively high rate of speed. Anisotropic etching can typically penetrate as much as 100 angstroms or more into the semiconductor device, and in particular into an ONO layer within a semiconductor device. If the ONO layer within a semiconductor device is thin, that is less than 1000 angstroms, anisotropic etching can cause damage to the semiconductor substrate beneath the ONO layer. Accordingly, advances in processes for fabricating a semiconductor device having an oxide-nitride-oxide layer and, more particularly, in processes for removing a portion of the oxide-nitride-oxide layer, are necessary.
According to a first aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.
According to another aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing a wet etch on the second oxide layer, wherein the wet etch is highly selective to oxides, and performing an isotropic etch on the nitride layer.
According to another aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing a first isotropic etch on the second oxide layer, and performing a second isotropic etch on the nitride layer.
According to another aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes performing an isotropic etch on the nitride layer.

Method for selective removal of ONO layer


A compensated via structure is utilized in a multi-layer printed circuit board (PCB) stackup to improve the radio frequency (RF) transmission performance of the PCB. The compensated via structure includes a compensating structure and a central via surrounded by multiple grounding posts, wherein both ends of the central via are connected to the input and the output transmission lines through pads. The compensating structure is within a ground plane located in between of the two layers within which the input and output transmission lines are. The increased coupling between the central via and the grounding posts and between the compensating structure and the ground plane results in reductions in both return and insertion losses and contributes to the improved RF transmission performance.

PCB transmission lines are widely used in high-speed and high-frequency signal transmission. Vias, i.e. vertical interconnect accesses, are conductors running through multiple PCB layers and electrically connected to PCB transmission lines. A via has a cylindrical-like structure, including a via barrel that is a conductive tube, via pads that connect both ends of the via barrel to other components, i.e. PCB transmission lines, and via antipad (or clearance) that is the clearance hole between the via barrel and the ground plane to which it is not supposed to be connected. At low frequencies, vias have minimal effects on signal transmission. At high frequencies, for example, at Ka band of satellite communication from 20 GHz to 40 GHz, signal loss becomes a considerable problem to overcome for PCB design. Vias not only create impedance discontinuity causing signal reflections, but transmission loss causing signal deterioration.
The transmission loss includes conduction loss and dielectric loss. The conduction loss is primarily due to the resistance in the conduction layer and leakage of charge through the dielectric. The dielectric loss is from the heat dissipation due to the polarization of dipole moments in the dielectric layer subject to the alternating electric field. Both the thickness of the dielectric layer and the length of the vias have an effect on the transmission loss. A thick dielectric layer is helpful for reducing transmission loss, but it also increases the length of via, especially in a multilayer PCB stackup with more than one dielectric layer, which in turn results in increased transmission loss. Thus, a new PCB design is required to offset the elongated effect of vias when thick dielectric layers are employed.

Printed circuit via for KA satcom circuit boards


An extruder drivable for displacement by moving devices is provided for sewer pipe reconstruction and has a radial nozzle applying by extrusion a thermoplastic tube to the inside wall of a sewer pipe to be reconstructed. The thermoplastic tube is pressed against the inside wall by pressurized air and cooled down to form a lining pipe.

The public sewerage system is out of repair and leaking to a considerable extent, namely of approximately 15 to 20 per cent. This causes considerable pollution, in particular of ground water and drinking water. Repair of these damages requires great efforts.
The book of Stein and Niederehe, "Instandhaltung von Kanalisationen" (Sewerage System Maintenance), Ernst & Sohn Verlag, Berlin 1987, pages 308 to 317, discloses numerous methods of repairing or reconstructing damaged sewer pipes that consist in sealing the sewer pipes located in the ground.
The so-called injection method consists in sealing leaking pipe connections by an injection of acrylic resins into the pipe. In another sealing method gaskets are manually inserted into the sewer pipe and pressed against the inside wall of the sewer pipe by means of steel pressing rings. A relining method consists in that a defined annular space is produced with the aid of reusable tube formwork provided with spacers and in that cement mortar is pressed into this space. In a further lining method cement mortar is placed between a pressure piston and a displacement body. When this device is pulled through the sewer pipe, the mortar is pressed against the pipe wall by the displacement body. In a further relining method the relining material is centrifuged towards the inside wall of the sewer pipe by a centrifugal head rotating at high speed.
So-called pipe-line relining consists in a plastic pipe being introduced into the sewer pipe to be reconstructed, which reduces the pipe cross-section considerably. The remaining annular space is filled. Excavations are necessary where break-throughs have to be produced in the continuous plastic pipe for house or street connections.
In the method of so-called short-pipe lining short single pipes are individually entered via an inspection pit into a sewer pipe to be repaired. This also reduces the sewer cross-section. The remaining annular space is filled as a rule. Excavations are necessary to produce house or street connections.
In the so-called wrapped-tube relining method wrapped tubes produced at site from plastic profile strips are entered into the sewer pipe to be repaired. The annular space is filled as a rule.
The so-called hose relining consists in that a prefabricated felt hose soaked with synthetic resin is introduced into the sewer line to be repaired and is pressed to the inside wall of the sewer pipe by internal pressure. Curing is effected in situ by heat supply. House and street connections must be cleared by milling.

Apparatus for lining an inside wall of a sewer pipe


Enough room is provided in a transmitted frame to receive a plurality (n) of useful information blocks, thereby making it possible to catch up any excessive lateness (r) which may arise due to successive repeats. The decoder (2) provides a confidence flag (3) to the controlling microprocessor (5). The command block (COM) from the decoder includes an indication of the number of useful blocks that are transmitted in the frame. This block is advantageously applied to an HDLC component (8).

Three strategies are in common use for reducing the error rate of a digital transmission.
The first consists in an error correcting code without a return path (sometimes called forward error control or FEC). A defect of this error correcting strategy is that it is poorly adaptable and this may be objectionable for certain types of channel (tropospheric channels, or channels being jammed). For example in a tropospheric channel, various channel parameters such as mean signal to noise ratio, coherence band, or coherence time, remain fixed on a small scale only. If these parameters are observed over several hours, several days, or several months, it can be seen that they are subject to non-negligible fluctuations. Thus, a code designed to operate ideally under given parameters will probably be ineffective at certain times of day or at certain times of the year. This strategy has the advantage of ensuring a transmission delay which is fixed. However it is ineffective against bursts of errors unless it is associated with interlacing which suffers from the drawback of increasing transmission delay.
A second strategy is the automatic repeat request (ARQ) strategy which requires the use of a return path, with this strategy being based on detecting errors and on requesting repeats when necessary. It may be defined as follows:
data is sent in packets, and not continuously;
each packet contains data symbols accompanied by check symbols; and
the receiver makes use of the check symbols to detect whether an error has occurred in transmission. It then either accepts the block of data in the packet or it requests retransmission. Thus the ARQ strategy uses an error detecting code whereas the FEC strategy uses an error correcting code. An error detecting code is generally simpler to decode than is an error correcting code.
This strategy gives rise to additional redundancy constituted by retransmission. Thus although the redundancy specific to the coding scheme is fixed (and specified in terms of a code ratio), retransmission redundancy is a random variable. Total mean redundancy is specified in terms of an effective code ratio. The main drawback of this strategy arises when transmission conditions are bad (a very noisy channel) so that the error detecting code is quickly swamped and the number of repeats is very high, thereby increasing transmission delay. To mitigate this problem, it is present practice to associate ARQ strategy with an error correcting code, thereby providing the third strategy.
The third strategy is referred to as a "hybrid" strategy since it combines error correcting code and the ARQ procedure. The code used no longer serves merely to detect errors but also to correct them within the limit of the code's error-correcting capacity. The strategy is then as follows:
an encoded sequence is transmitted;
the receiver has a decoder which attempts to decode the sequence as received. A definite criterion is used for measuring the confidence that may be had in the decision of the decoder;
if the criterion is satisfied, then the decoded sequence is assumed to correspond to the sequence as transmitted, otherwise the receiver requests a repeat.
This hybrid ARQ strategy is described in various publications which make use either of block codes or of convolution codes decoded by the Viterbi algorithm. However, with such codes, it is not possible to obtain an arbitrarily small error rate while keeping the code ratio fixed. It is then possible to use a convolution code which is decoded by a sequential decoding algorithm. The best is doubtless the stack algorithm which, in addition, is capable of providing an indication concerning the reliability of decoding.
One of the drawbacks of strategies that automatically request repeats (the second and third above-mentioned strategies) is the ever increasing delay in data transmission due to successive repeats, thus requiring the transmitter to possess buffer memories of very large size, with data being lost if the memories overflow. This increasing delay means that these methods are unsuitable, in particular, for use in transmitting telephone calls.

Method and apparatus for digital data transmission with automatic repeat request

Alcatel Transmission Par Faisceaux Hertziens A.T.F.H.


A confectionery compressed tablet designed to dissolve in the oral cavity and containing a flavor ingredient intimately bound with a bioadhesive is disclosed. The flavor and bioadhesive composition provide a unique mouthfeel so that as the confection dissolves in the oral cavity, a coating of flavor adheres to the moist areas of the oral cavity. There is also provided a confectionery compressed tablet characterized by a single product body with discrete phases contained therein which act to provide timed release of at least one flavor ingredient sequentially. A flavor and bioadhesive mixture can be prepared with a hydrophilic delivery system providing rapid initial delivery of the flavor and unique mouthfeel or as a part of a hydrophobic delivery system providing extended periods of flavor delivery and unique mouthfeel. There is also provided a process for preparing confectionery compressed tablets containing the unique flavor delivery system and mouthfeel.

The present invention relates to confections which are intended to reside in the oral cavity for a period of time while being consumed. In particular, the present invention provides among other things, confectionery tablets with both instant and timed delivery to the oral cavity of taste-affecting ingredients such as flavors, sweeteners, and mixtures thereof in compressed tablets.
Flavor delivery systems are well known in the art and may be divided into various classes based upon their physical characteristics, namely, liquid, emulsion, paste, or solid. Not only are these characteristics different, but also the potential uses for each type of flavor and method of manufacture differ as well.
In the past, considerable effort has been directed toward the preparation of flavoring materials. Specifically, flavor materials have been sought to provide greater intensity coupled with sustained flavor release for long periods of time.
To overcome difficulty with flavor oils in particular, various attempts have been made to encapsulate flavor oils or use dried ingredients to prolong the delivery of the flavors. Further, considerable effort has been directed to the development of delayed-release agents which will delay release of the flavor and permit uniform-release of the flavor over an extended period of time.
Spray drying is one of the most widely used techniques for encapsulating or fixing a flavor and such are well in the art. Flavor fixation has also been obtained by the extrusion method wherein the flavor oil is co-extruded with a water-soluble sugar or sugar mixture, dried and ground for use. These products find application in dry mixes for the instant release of the flavor upon contact with water. Such products generally contain 10% to 15% by weight of flavor oil. An extensive discussion of the prior art with respect to the extension of flavor is found in commonly/-assigned co-pending U.S. patent application having Ser. No. 07/463050, and U.S. patent application having Ser. No. 07/450756, both of which are incorporated by reference herein. These commonly assigned applications disclose methods and compositions for providing confectionery compressed tablets having both rapid initial delivery of a flavor ingredient and timed delivery of the same or of a second flavor ingredient over a period of time. The use of these flavor delivery systems provide improved confections capable of delivering both an initial rapid delivery as well as prolonged delivery of a flavor ingredient. While the aforementioned flavor delivery systems represent a dramatic improvement in flavor delivery, the present invention provides an alternative solution to the problem of flavor delivery.
In recent years, the adhesive properties of water soluble polymers have been explored as delivery systems for bio-effecting agents. Polymers, such as polyacrylic acid and hydroxypropylmethyl cellulose, for example, have been explored to provide delivery systems adhering to buccal, cervical, gastrointestinal, nasal and ocular mucosa as an administration route. The polymers are engineered to provide predetermined amounts of bio-effecting agents while at the same time anchor the dosage form on a selected mucous membrane.
The buccal route, which relies upon the mucous membranes of the oral cavity, has often been relied upon for administration of bio-effecting agents which are susceptible to inactivation by gastrointestinal enzymes and/or the hepatic "first pass" effect, i.e., inactivation of drugs during the first passage through the liver. Buccal administration is also useful for delivery of bio-effecting agents such as nitroglycerin which has a short duration of bioactivity.
It is, therefore, an object of the present invention to provide a multiple phase compressed tablet providing both a rapid initial delivery as well as timed delivery of flavor ingredients to the oral cavity.
It is another object of the present invention to provide a compressed tablet which has a bioadhesive contained therein to assist in delivery of flavor ingredients to the oral cavity.
It is a further object of the present invention to provide a compressed tablet which can be used to provide heightened as well as varied organoleptic responses which are pleasing to the consumer.
It is a still further object of the present invention to provide a compressed tablet containing flavor ingredients therein and which adheres to the oral mucosa while in the oral cavity.

Encapsulated flavor with bioadhesive character in pressed mints and confections


According to one embodiment, a resistance change type memory includes a memory cell including a first resistance change element as a memory element; a reference cell including a second resistance change element and a first element having a resistance value which is not higher than a resistance range of the first and second resistance change elements; and a read circuit including a first input terminal connected to the memory cell, and a second input terminal connected to the reference cell.

Attention has been paid to resistance change type memories such as a magnetoresistive random access memory (MRAM), a resistive RAM (ReRAM) and a phase change RAM (PCRAM), as next-generation semiconductor memories. Since the resistance change type memories enable relatively easy microfabrication of elements, an increase in storage density and a decrease in power consumption can be realized.
As regards the resistance change type memories, there has been a demand for reliability in data write and data read.


A seal device for a hydroforming press includes a housing having a bore and a seal carrier slidable within the housing bore. The seal carrier has a bore which fits closely outside of the end of tube to be hydroformed. A V-shaped locator rigidly mounted relative to the housing aligns the end of the tube placed thereon with the carrier bore. A carrier actuator is operable to move the seal carrier between a retracted position away from the end of the tube to an extended position over the end of the tube. A resilient elastomeric annular seal carried by the seal carrier encircles the outer surface of the tube. A seal actuator carried on the seal carrier compresses the seal upon relative movement between the seal actuator and the seal carrier. A stop is engaged by the seal actuator as the seal carrier approaches the extended position so that subsequent further movement of the seal carrier compresses the seal against the tube. The locator and a tube backup fixed to an upper bed of the press encircle the tube when the press is closed, reacting against the tube when it is pressurized. A travel limit block provides a reaction member against which the locator reacts to prevent relative movement between the seal device and the press during forming.

It is well known, in the prior art, that a tube may be hydroformed to a desired complex tubular shape. The tube is placed between a pair of dies having cavities which define the desired resultant shape of the tube. The ends of the tube are accessible through the die and a seal is connected to the ends of the tube so that pressurized fluid injected into the tube forces the tube to expand and conform to the shape defined by the die cavity. It is also known to mount the dies in a press so that a lower die is stationary on the lower bed of the press and the upper die moves up and down with the upper bed of the press to permit loading and unloading of the tubes from the die.
U.S. Pat. No. 5,233,054, assigned to the assignee of this invention, provides improvements in the press apparatus and in the mounting of a seal unit or seal device on the press. U.S. Pat. No. 5,233,856, assigned to the assignee of this invention, provides an improved seal device for sealing engagement on the outer surface of the tube end in a hydroforming process.
U.S. patent application Ser. No. 08/071,411, filed Jun. 4, 1993, assigned to the assignee of this invention, entitled "External Seal Device for Hydroforming" also discloses a similar seal device having an actuator with a removable end facilitating seal replacement.
The present invention provides a new and improved seal device having locator means for aligning the tube end with the seal device.

External seal device for tube hydroforming


Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

With the significant growth in the amount of data being stored in data storage systems, the transfer rates of this large amount of data between the data storage systems and the computing systems hosting these data storage systems need to be significantly increased in order to satisfy the performance expectations of the users and/or customers of the data storage system manufacturers.
However, increasing transfer rates of data to and from the data storage systems generates data and signal integrity issues. Additionally, increasing transfer rates and/or number of non-volatile memory interface modules within a data storage system significantly increases design and manufacturing costs of the data storage systems.

This patent is subject to a terminal disclaimer.

Data storage system for improving data throughput and decode capabilities