A PLL comprising a VCO, a phase comparator, a frequency comparator and a filter realizes an enlarged pull-in frequency range and increased operating frequency. The VCO generates a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. An input data signal is inputted to the phase comparator and the frequency comparator. The first clock signal is supplied to the phase comparator and the frequency comparator, and the second clock signal is supplied to the frequency comparator. The phase comparator executes phase comparison between the first clock signal and the input data signal, and outputs the result of the phase comparison. The frequency comparator which is composed of digital components executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates a control signal for controlling the oscillation frequency of the voltage controlled oscillator.

The present invention relates to a phase locked loop, and in particular, to a phase locked loop having the capability of high speed operation.
Clock recovery circuits employing PLLs (Phase Locked Loops) have become very important in the field of data communication especially for miniaturizing devices, and a variety of PLLs have been proposed and reported. Among such techniques concerning PLLs, a PLL which is provided with a frequency comparator so as to enlarge the pull-in range (pull-in frequency range) has been disclosed in a paper: xe2x80x9cA PLL-Based 2.5-Gb/s GaAs Clock and Data Regenerator ICxe2x80x9d, IEEE Journal of Solid-State Circuit, vol.26, No.10, pages 1345-1353 (October 1991).
FIG. 1 is a circuit diagram showing a conventional PLL which is disclosed in the above document. The PLL shown in FIG. 1 comprises a D-FF 70, a delay circuit 71, an EXOR circuit 72, a first phase comparator 73, a second phase comparator 74, a VCO (Voltage Controlled Oscillator) 75, a differential circuit 76, a lowpass filter 77 and a mixer 78.
An input signal is delayed by the delay circuit 71 by half the clock cycle, and the delayed input signal is supplied to the EXOR circuit 72. Meanwhile, the input signal is also supplied to the EXOR circuit 72 directly. Thereby a pulse signal is generated by the EXOR circuit 72 when data change occurs in the input signal. The pulse signal is supplied to the first phase comparator 73 and the second phase comparator 74, which compare the phase of the pulse signal with the phase of a clock signal which is generated by the VCO 75. For the comparison, the clock signal having a phase 0xc2x0 is supplied to the first phase comparator 73, and the clock signal having a phase 90xc2x0 is supplied to the second phase comparator 74. The output of the first phase comparator 73 is inputted to the differential circuit 76, and thereby a differentiated signal is supplied to the mixer 78. Meanwhile, the output of the second phase comparator 74 is directly inputted to the mixer 78. The mixer 78 multiplies the differentiated signal supplied from the differential circuit 76 and the output of the second phase comparator 74 together. The output of the mixer 78 is returned to the VCO 75 via the lowpass filter 77.
The output of the lowpass filter 77 becomes a DC voltage which is proportional to the frequency difference between the input signal and the clock signal. Therefore, a PLL provided with a frequency comparator is formed by the circuit of FIG. 1 and thereby a PLL having a wide pull-in range is realized.
If we describe the clock signal having the phase 0xc2x0 and the clock signal having the phase 90xc2x0 as A sin ((xcfx89t) and A cos ((xcfx89t) respectively, the output of the first phase comparator 73 can be described as:
B sin(dxcfx89t+dxcex8)xe2x80x83xe2x80x83(1)
and the output of the second phase comparator 74 can be described as:
B cos(dxcfx89t+dxcex8)xe2x80x83xe2x80x83(2)
where dxcfx89 is the frequency difference (angular velocity difference) between the input signal and the clock signal, and dxcex8 is the phase difference between the input signal and the clock signal.
Since the output of the first phase comparator 73 is inputted to the differential circuit 76, the output of the differential circuit 76 becomes:
dxcfx89B cos(dxcfx89t+dxcex8)xe2x80x83xe2x80x83(3).
The signals of the expressions (2) and (3) are multiplied together by the mixer 78, therefore, the output of the mixer 78 becomes:
dxcfx89B2/2xc3x97(1+cos(2(dxcfx89t+dxcex8)))xe2x80x83xe2x80x83(4).
The signal (4) can be divided into a DC component which is proportional to the frequency difference and an AC component whose frequency is twice the frequency difference between the input signal and the clock signal. Therefore, by removing the AC component by the lowpass filter 77, a VCO control voltage which is proportional to the frequency difference can be obtained. By the capability of detecting the frequency difference, a PLL which is capable of enlarging the pull-in range up to the capture range of the VCO regardless of the time constant of the lowpass filter 77 and capable of operating stably is realized.
However, the conventional PLL described above requires precision of each block or component of the PLL since the frequency difference between the clock signal and the input data signal is detected in an analog manner. For example, in cases where the precision of the differential circuit 76 is deteriorated for some reason and the 90xc2x0 phase shift is not executed by the differential circuit 76 precisely, an offset voltage occurs in the output of the mixer 78. For the offset voltage, an offset compensation has to be done from outside the PLL. Further, such a high precision circuit becomes more and more harder to manufacture as the operating frequency of the PLL becomes high, and thus stable operation of the PLL in higher frequency becomes very difficult. Therefore, a PLL having wide pull-in range and capability of high speed operation is being required today.
Further, even if the pull-in could be done against the input data signal, phase difference tends to occur between the clock signal generated by the VCO and the input data signal as the bit rate of the input data signal becomes higher. In a clock recovery circuit employing a decision circuit for executing data recognition/regeneration and outputting the recognized/regenerated data, such phase difference between the clock signal and the input data signal supplied to the decision circuit has to be eliminated, that is, phase adjustment has to be executed to the clock signal which is inputted to the decision circuit so that edges (rising edges or falling edges) of the clock signal to be used for the data recognition/regeneration by the decision circuit will come to the optimum decision point (i.e. the midpoint of each time slot of the input data signal).
Such phase adjustment used to be executed by inserting a delay circuit etc. in front of the decision circuit. However, techniques for eliminating the need of the phase adjustment have been proposed these days. Such an example of a PLL has been disclosed in a paper: xe2x80x9cA Self Correcting Clock Recovery Circuitxe2x80x9d, IEEE Journal of Lightwave Technology, vol.LT-3, No. 6, pages 1312-1314 (December 1983).
FIG. 2 is a circuit diagram showing the conventional PLL (clock recovery circuit) which is disclosed in the above document. The PLL of FIG. 2 is composed of a phase comparator 80, a filter 81 and a VCO 82. In the phase comparator 80, a first D-FF 83 and a second D-FF 84 are connected in series. The input data signal is supplied to the data input terminal D of the first D-FF 83. The output terminal Q of the first D-FF 83 is connected to the data input terminal D of the second D-FF 84, and thereby recognized/regenerated input data is outputted from the output terminal Q of the second D-FF 84. The clock terminal C of the first D-FF 83 is supplied with the clock signal from the VCO 82, and the clock terminal C of the second D-FF 84 is supplied with an inverted clock signal which is generated by inverting the clock signal from the VCO 82 by an inverter 85. The data input terminal D and the output terminal Q of the first D-FF 83 are connected to a first EXOR circuit 86, and the data input terminal D and the output terminal Q of the second D-FF 84 are connected to a second EXOR circuit 87. The outputs of the first and the second EXOR circuits 86 and 87 are supplied to an adder 88, in which the output of the first EXOR circuit 86 is inputted to the adder 88 so as to be added and the output of the second EXOR circuit 87 is inputted to the adder 88 so as to be subtracted. The output of the adder 88 is supplied to the filter 81, and the output of the filter 81 is returned to the VCO 82 as a control signal.
The PLL of FIG. 2 operates as follows. FIGS. 3 and 4 are timing charts showing the operation of the phase comparator 80 of the conventional PLL of FIG. 2, in which FIG. 3 shows a case where the phase of the clock signal (VCO OUTPUT) is behind the phase of the input data signal and FIG. 4 shows a case where the phase of the clock signal (VCO OUTPUT) is ahead of the phase of the input data signal. Incidentally, the expressions xe2x80x9cbehindxe2x80x9d and xe2x80x9cahead ofxe2x80x9d are used with respect to falling edges of the clock signal. As shown in FIG. 3(e) and FIG. 4(e), the output of the first EXOR circuit 86 becomes pulses each of which has a pulse width determined by time difference between a changing point of the input data signal (FIG. 3(a) and FIG. 4(a)) and a changing point of the clock signal (VCO OUTPUT) (FIG. 3(b) and FIG. 4(b)). Meanwhile, as shown in FIG. 3(f) and FIG. 4(f), the output of the second EXOR circuit 87 becomes pulses each of which has a pulse width of half the cycle of the clock signal.
In the case where the phase of the clock signal is behind the phase of the input data signal, the output pulse width of the first EXOR circuit 86 (FIG. 3(e)) becomes wider than that of the second EXOR circuit 87 (FIG. 3(f)), and thereby the average of the output signal of the adder 88 (FIG. 3(g)) via the filter 81 becomes a positive voltage.
On the other hand, in the case where the phase of the clock signal is ahead of the phase of the input data signal, the output pulse width of the first EXOR circuit 86 (FIG. 4(e)) becomes narrower than that of the second EXOR circuit 87 (FIG. 4(f)), and thereby the average of the output signal of the adder 88 (FIG. 4(g)) via the filter 81 becomes a negative voltage.
As described above, the average output voltage of the phase comparator 80 changes depending on the phase difference between the clock signal and the input data signal, therefore, the phase comparator 80 can correctly operate as a phase comparator. The PLL phase-locks when the average output voltage of the phase comparator 80 becomes 0, that is, when the output pulse width of the first EXOR circuit 86 becomes equal to that of the second EXOR circuit 87. At such a moment, the phase (of rising edges) of the clock signal comes to the midpoint of each time slot of the input data signal. The first D-FF 83 and the second D-FF 84 also have a function of a decision circuit. Therefore, by the above composition of the PLL, a clock recovery circuit capable of executing data recognition/regeneration at the optimum decision point of the decision circuit without phase adjustment can be realized.
However, in such a clock recovery circuit employing the conventional PLL, when the phase of the clock signal is ahead of the phase of the input data signal and the phase difference is large, the output pulse width of the first EXOR circuit 86 becomes very narrow. Therefore, the EXOR circuits 86 and 87 are required the capability of high speed operation. Generally, an EXOR circuit can output pulses of enough height and width when the output pulse width is wide enough, however, when the output pulse width becomes narrower, the output pulse amplitude tends to become smaller (depending on the operating speed of the EXOR circuit), and thereby detection of the phase difference becomes impossible. Especially, for Gb/s class signals, the phase comparator employing an IC becomes difficult, since the EXOR circuit is required operating speed of 2 to 3 times the bit rate of the signal.
It is therefore the primary object of the present invention to provide a phase locked loop having a wide pull-in frequency range and the capability of high speed operation.
Another object of the present invention is to provide a phase locked loop by which need for the phase adjustment of the clock signal in high speed operation and the effect of variations in quality of device elements are eliminated and thereby stable high speed operation is realized.
In accordance with a first aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a phase comparator, a frequency comparator and a filter. The voltage controlled oscillator, whose oscillation frequency is controlled by a control signal, generates and outputs a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. The phase comparator executes phase comparison between the first clock signal and the input data signal, and outputs the result of the phase comparison. The frequency comparator executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a second aspect of the present invention, in the first aspect, the frequency comparator is composed of digital components.
In accordance with a third aspect of the present invention, in the first aspect, the frequency comparator includes a cycle slip detection circuit and an UP/DOWN signal generation circuit. The cycle slip detection circuit samples the first clock signal in sync with changing points of the input data signal, detects change of the value of the sampled first clock signal, and outputs a detection signal when the change of the sampled first clock signal is detected. The UP/DOWN signal generation circuit judges whether the frequency of the clock signal is higher or lower than the frequency of the input data signal when the cycle slip detection circuit outputted the detection signal based on a sampled data of the second clock signal which is obtained by sampling the second clock signal in sync with a changing point of the input data signal, outputs a DOWN signal for decreasing the oscillation frequency of the voltage controlled oscillator when the frequency of the clock signal is judged to be higher than that of the input data signal, and outputs an UP signal for increasing the oscillation frequency of the voltage controlled oscillator when the frequency of the clock signal is judged to be lower than that of the input data signal.
In accordance with a fourth aspect of the present invention, in the third aspect, the cycle slip detection circuit includes a first sample hold circuit whose clock terminal is supplied with the input data signal and whose data input terminal is supplied with the first clock signal, a second sample hold circuit whose clock terminal is supplied with the input data signal and whose data input terminal is supplied with the output of the first sample hold circuit, and an EXOR circuit which is supplied with the outputs of the first sample hold circuit and the second sample hold circuit.
In accordance with a fifth aspect of the present invention, in the fourth aspect, the UP/DOWN signal generation circuit includes a third sample hold circuit whose data input terminal is supplied with the second clock signal and whose clock terminal is supplied with the input data signal, a first AND circuit which is supplied with the outputs of the first sample hold circuit and the third sample hold circuit, a second AND circuit which is supplied with the outputs of the second sample hold circuit and the third sample hold circuit, a first D-FF whose data input terminal is supplied with the output of the first AND circuit and whose clock terminal is supplied with the output of the EXOR circuit, and a second D-FF whose data input terminal is supplied with the output of the second AND circuit and whose clock terminal is supplied with the output of the EXOR circuit. Thereby the DOWN signal is outputted by the first D-FF and the UP signal is outputted by the second D-FF.
In accordance with a sixth aspect of the present invention, in the fourth aspect, the UP/DOWN signal generation circuit includes a third sample hold circuit whose data input terminal is supplied with the second clock signal and whose clock terminal is supplied with the input data signal, a first AND circuit which is supplied with the outputs of the first sample hold circuit and a second D-FF, a second AND circuit which is supplied with the outputs of the second sample hold circuit and a first D-FF, a third AND circuit which is supplied with the outputs of the EXOR circuit and the third sample hold circuit, the first D-FF whose data input terminal is supplied with the output of the first AND circuit and whose clock terminal is supplied with the output of the third AND circuit, and the second D-FF whose data input terminal is supplied with the output of the second AND circuit and whose clock terminal is supplied with the output of the third AND circuit. Thereby the DOWN signal is outputted by the first D-FF and the UP signal is outputted by the second D-FF.
In accordance with a seventh aspect of the present invention, in the fourth aspect, each sample hold circuit of the cycle slip detection circuit includes a first latch, a second latch and a selector. The data input terminal of the first latch is connected with the data input terminal of the sample hold circuit, and the clock terminal of the first latch is connected with the clock terminal of the sample hold circuit. The first latch holds data at its data input terminal from the moment when a rising edge is supplied to its clock terminal till the moment when a falling edge is supplied to the clock terminal. The data input terminal of the second latch is connected with the data input terminal of the sample hold circuit, and the inverted clock terminal of the second latch is connected with the clock terminal of the sample hold circuit. The second latch holds data at its data input terminal from the moment when a falling edge is supplied to its inverted clock terminal till the moment when a rising edge is supplied to the inverted clock terminal. The input terminals of the selector are supplied with the outputs of the first latch and the second latch, and the selection control terminal of the selector is supplied with the input data signal which is supplied to the clock terminal of the sample hold circuit. The selector selects and outputs the output of the first latch or the output of the second latch depending on the logical value of the input data signal which is supplied to the selection control terminal.
In accordance with an eighth aspect of the present invention, in the seventh aspect, the selector selects and outputs the output of the first latch when the logical value of the selection control terminal is xe2x80x9c1xe2x80x9d, and selects and outputs the output of the second latch when the logical value of the selection control terminal is xe2x80x9c0xe2x80x9d.
In accordance with a ninth aspect of the present invention, in the fourth aspect, each sample hold circuit of the cycle slip detection circuit includes a D-FF whose data input terminal is connected with the data input terminal of the sample hold circuit and whose clock terminal is connected with the clock terminal of the sample hold circuit.
In accordance with a tenth aspect of the present invention, in the first aspect, the filter includes a first filter which is provided corresponding to the phase comparator so as to remove high frequency components of the output of the phase comparator, a second filter which is provided corresponding to the frequency comparator so as to remove high frequency components of the output of the frequency comparator, and an adder for adding the outputs of the first filter and the second filter together.
In accordance with an eleventh aspect of the present invention, in the third aspect, the filter includes a first filter which is provided corresponding to the phase comparator so as to remove high frequency components of the output of the phase comparator, a second filter which is provided corresponding to the frequency comparator so as to remove high frequency components of the output of the frequency comparator, and an adder for adding the outputs of the first filter and the second filter together. The second filter generates a voltage for increasing the oscillation frequency of the voltage controlled oscillator when the UP signal is supplied from the frequency comparator, and generates a voltage for decreasing the oscillation frequency of the voltage controlled oscillator when the DOWN signal is supplied from the frequency comparator.
In accordance with a twelfth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator and a filter. The voltage controlled oscillator generates and outputs a clock signal. The oscillation frequency of the voltage controlled oscillator is controlled by a control signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with rising edges of the clock signal. The phase comparator executes phase comparison between the clock signal and the input data signal by sampling the input data signal in sync with falling edges of the clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The filter removes high frequency components from the output of the phase comparator and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a thirteenth aspect of the present invention, in the twelfth aspect, the phase comparator is composed of digital components.
In accordance with a fourteenth aspect of the present invention, in the twelfth aspect, the phase comparator includes a first inverter, a D-FF, a second inverter, a third inverter, a first latch, a second latch and a selector. The first inverter inverts the clock signal which is outputted by the voltage controlled oscillator. The D-FF samples the input data signal in sync with rising edges of the clock signal which has been inverted by the first inverter and outputs the sampled data. The second inverter inverts the output of the D-FF. The third inverter inverts the output of the decision circuit. The first latch samples the output of the D-FF in sync with rising edges of the output of the decision circuit, and holds the sampled data while the output of the decision circuit remains xe2x80x9c1xe2x80x9d. The second latch samples the output of the D-FF which has been inverted by the second inverter in sync with rising edges of the output of the decision circuit which has been inverted by the third inverter, and holds the sampled data while the output of the decision circuit which has been inverted by the third inverter remains xe2x80x9c1xe2x80x9d. The selector selects and outputs the output of the first latch when the output of the decision circuit is xe2x80x9c1xe2x80x9d, and selects and outputs the output of the second latch when the output of the decision circuit is xe2x80x9c0xe2x80x9d.
In accordance with a fifteenth aspect of the present invention, in the twelfth aspect, the decision circuit and the phase comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.
In accordance with a sixteenth aspect of the present invention, in the twelfth aspect, the phase comparator includes a first inverter, a first D-FF and a second D-FF. The first inverter inverts the clock signal which is outputted by the voltage controlled oscillator. The first D-FF samples the input data signal in sync with rising edges of the clock signal which has been inverted by the first inverter and outputs the sampled data. The second D-FF samples the output of the first D-FF in sync with rising edges of the output of the decision circuit, and thereby executes phase comparison between the clock signal and the input data signal.
In accordance with a seventeenth aspect of the present invention, in the sixteenth aspect, the second D-FF is supplied with the output of the first D-FF to its data input terminal via a second inverter, and is supplied with the output of the decision circuit to its clock terminal via a third inverter.
In accordance with an eighteenth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator and a filter. The voltage controlled oscillator generates and outputs a clock signal. The oscillation frequency of the voltage controlled oscillator is controlled by a control signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with falling edges of the clock signal. The phase comparator executes phase comparison between the clock signal and the input data signal by sampling the input data signal in sync with rising edges of the clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The filter removes high frequency components from the output of the phase comparator and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a nineteenth aspect of the present invention, in the eighteenth aspect, the phase comparator is composed of digital components.
In accordance with a twentieth aspect of the present invention, in the eighteenth aspect, the phase comparator includes a first inverter, a D-FF, a first inverter, a second inverter, a first latch, a second latch and a selector. The first inverter inverts the clock signal which is outputted by the voltage controlled oscillator. The D-FF samples the input data signal in sync with rising edges of the clock signal and outputs the sampled data. The first inverter inverts the output of the D-FF. The second inverter inverts the output of the decision circuit. The first latch samples the output of the D-FF in sync with rising edges of the output of the decision circuit, and holds the sampled data while the output of the decision circuit remains xe2x80x9c1xe2x80x9d. The second latch samples the output of the D-FF which has been inverted by the first inverter in sync with rising edges of the output of the decision circuit which has been inverted by the second inverter, and holds the sampled data while the output of the decision circuit which has been inverted by the third inverter remains xe2x80x9c1xe2x80x9d. The selector selects and outputs the output of the first latch when the output of the decision circuit is xe2x80x9c1xe2x80x9d, and selects and outputs the output of the second latch when the output of the decision circuit is xe2x80x9c0xe2x80x9d.
In accordance with a twenty-first aspect of the present invention, in the eighteenth aspect, the decision circuit and the phase comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.
In accordance with a twenty-second aspect of the present invention, in the eighteenth aspect, the phase comparator includes a first D-FF and a second D-FF. The first D-FF samples the input data signal in sync with rising edges of the clock signal and outputs the sampled data. The second D-FF samples the output of the first D-FF in sync with rising edges of the output of the decision circuit, and thereby executes phase comparison between the clock signal and the input data signal.
In accordance with a twenty-third aspect of the present invention, in the twenty-second aspect, the second D-FF is supplied with the output of the first D-FF to its data input terminal via a first inverter, and is supplied with the output of the decision circuit to its clock terminal via a second inverter.
In accordance with a twenty-fourth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator, a frequency comparator and a filter. The voltage controlled oscillator, whose oscillation frequency is controlled by a control signal, generates and outputs a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with rising edges of the first clock signal. The phase comparator executes phase comparison between the first clock signal and the input data signal by sampling the input data signal in sync with falling edges of the first clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The frequency comparator executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a twenty-fifth aspect of the present invention, in the twenty-fourth aspect, the decision circuit, the phase comparator and the frequency comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.
In accordance with a twenty-sixth aspect of the present invention, there is provided a phase locked loop comprising a voltage controlled oscillator, a decision circuit, a phase comparator, a frequency comparator and a filter. The voltage controlled oscillator, whose oscillation frequency is controlled by a control signal, generates and outputs a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. The decision circuit executes data recognition/regeneration of an input data signal in sync with falling edges of the first clock signal. The phase comparator executes phase comparison between the first clock signal and the input data signal by sampling the input data signal in sync with rising edges of the first clock signal and sampling the sampled input data signal in sync with changing points of the output of the decision circuit, and outputs the result of the phase comparison. The frequency comparator executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates the control signal for controlling the oscillation frequency of the voltage controlled oscillator.
In accordance with a twenty-seventh aspect of the present invention, in the twenty-sixth aspect, the decision circuit, the phase comparator and the frequency comparator are supplied with the input data signal via a duty adjustment circuit which adjusts the duty rate of the input data signal to approximately 50%.


In an imaging apparatus, a method of correcting image data, or a storage medium storing a program, a target is imaged in a plurality of imaging regions and image data is output from each of the plurality of imaging regions; based on the image data captured in a first imaging operation, an imbalance in output levels of image data respectively output from the plurality of imaging regions in a second imaging operation is corrected; and an imaging condition in the first imaging operation is controlled in accordance with an imaging condition in the second imaging operation. Accordingly, an imbalance in a plurality of image data simultaneously output from a plurality of output terminals of an imaging device is automatically corrected appropriately even if an imaging condition changes.

1. Field of the Invention
The present invention relates to a method of correcting an imbalance in an imaging device used in a digital camera or the like. More specifically, the present invention relates to a method of correcting an imbalance in an imaging device having a plurality of output terminals from which data is simultaneously read, by averaging output levels of image data respectively output from the plurality of output terminals, so that a seam will not be apparent in an image formed by combining the output data.
2. Description of the Related Art
In order to improve the ability of sequence shooting in a conventional digital camera system on the order of ten frames per second, it is required that the overall system be improved. That is, there must be an improvement of the speed of reading from the imaging device and of the speed of writing data from the imaging device to a frame memory.
FIG. 1 schematically shows the construction of an imaging device, more specifically a CCD with two horizontal CCD sections and two outputs, which is an example of improvement of conventional technology.
In the CCD shown in FIG. 1, charges generated by photodiodes 9 at respective pixels are simultaneously transferred to vertical CCD segments 10 at a predetermined timing, and the charges transferred to the vertical CCD segments 10 are transferred, line by line, to horizontal CCD segments 7 and 8 at a subsequent timing.
The horizontal CCD segments 7 transfer the charges that have been transferred thereto to a left amp 5 in synchronization with a transfer clock, whereas the horizontal CCD segments 8 transfer the charges that have been transferred thereto to a right amp 4 in synchronization with the transfer clock. Thus, image data captured by the CCD is read as left and right segments separated along a center of the screen.
The left and right parts of the image data captured by the CCD are respectively input to CDS/AGC circuits 3 and 6, which are grounded via resistors 1 and 2, respectively, and A/D conversion circuits 116 and 117 (shown in FIG. 2), and then stored in frame memories 126 and 127 (shown in FIG. 3) after being converted into digital data. These digital image data for the left part and for the right part are imbalanced mainly due to a difference in gain between the CDS/AGC circuits 3 and 6, particularly with regard to the offset component and the gain component. In order to correct the imbalance, calibration imaging is performed in addition to main imaging.
In an imaging apparatus such as a digital camera, in a proposed method, calibration imaging for calculating a correction coefficient for correcting an imbalance among a plurality of outputs is performed before or after the main imaging, and an imbalance among a plurality of outputs in an image obtained by main imaging is corrected using the correction coefficient. In another proposed method, the imbalance is corrected by the correlation of a plurality of outputs after converting a plurality of output signals into digital image data by an analog/digital converter.
However, some high-specification digital cameras, for example, of the single lens reflex type, allow various settings of imaging conditions, such as speed setting equivalent to ISO 100 to ISO 6400 or long-time imaging exceeding ten seconds. Thus, the correction methods described above are not sufficient for all these imaging conditions, resulting in inaccurate or unstable correction.

Imaging apparatus that corrects an imbalance in output levels of image data


There are provided a series inductor array implemented as a single winding capable of decreasing a layout area for providing a plurality of inductors, and a filter including the same, the series inductor array including a winding structure having both ends, and one or more terminal parts electrically connected to a region between the both ends of the winding structure to form an external electrical connection, wherein the winding structure has a structure in which a plurality of inductors having inductance formed in regions of the winding structure disposed between the both ends thereof and the terminal parts or between the terminal parts are connected in series.

1. Field of the Invention
The present invention relates to a series inductor array used in a high frequency circuit, or the like, and a filter including the same, and more particularly, to a series inductor array implemented as a single winding capable of decreasing a layout area for providing a plurality of inductors, and a filter including the same.
2. Description of the Related Art
Generally, in a high frequency circuit, various electrical and electronic devices for a high frequency are used, and an inductor, a capacitor, or the like, may be used for matching levels of the electrical and electronic devices with each other.
For example, a low pass filter type matching circuit is used in an output terminal of a power amplifier in the high frequency circuit in order to remove a harmonic component generated in the power amplifier simultaneously with maximizing an output of the power amplifier or implementing 50Ω matching. In this low pass filter type matching circuit, two series inductors connected to a signal line in series and a capacitor connected to a connection node of the two series inductors by a shunt are used. In addition, an additional inductor for removing the harmonic component may be connected between the two series inductors and the shunt capacitor in series.
According to the related art, two series inductors used in the matching circuit are implemented as respective windings. Therefore, in implementing the two series inductors in a physical structure, since each of the inductors is implemented as a single winding, two winding structures should be implemented in a circuit layout. Further, in order to implement an overall matching circuit, three inductors should be formed in a winding structure in the layout, and additionally, a capacitor and a ground pattern should be implemented.
That is, according to the related art, the higher the number of inductors, the larger the layout area of the circuit for actually containing the inductors needs to be, thereby having a negative influence on slimness and lightness of electrical and electronic products using the corresponding circuit.
Therefore, new technology for decreasing a layout area required for implementing a circuit using a plurality of inductors to contribute to miniaturization and slimness of products has been demanded in the art.

Series inductor array implemented as a single winding and filter including the same


When an RF coil in a magnetic resonance imaging system includes a plurality of conductive members and circuit elements connected to the conductive members, at least part of each of the conductive members is formed to a thickness so as to dissipate heat generated from the circuit elements. Moreover, the magnetic resonance imaging system is configured to include a cooling unit that circulates cooling air over the surfaces of the circuit elements provided in the RF coil.

1. Field of the Invention
The present invention relates to a magnetic resonance imaging system and a Radio Frequency (RF) coil. Particularly, the present invention relates to a magnetic resonance imaging system and an RF coil that can suppress heat generated around the RF coil.
2. Description of the Related Art
A magnetic resonance imaging system applies a high-frequency magnetic field over a subject placed in a static magnetic field, detects a nuclear magnetic resonance signal emitted from the subject with the high-frequency magnetic field, and reconstructs an image. Such magnetic resonance imaging system includes an RF coil that applies the high-frequency magnetic field over the subject, and detects a magnetic resonance signal emitted from the subject. The RF coil can be a single coil for both transmitting and receiving that performs application of a high-frequency magnetic field and detection of a magnetic resonance signal, or separate coils for transmitting and receiving to perform respective operations.
Generally, an RF coil is formed by using thin conductive members, such as copper foil, and the conductive members are connected to certain circuit elements for controlling operation of the RF coil. For example, a capacitor included in a resonant circuit for resonating the frequency of a high-frequency magnetic field with a resonance frequency, and/or a P-Intrinsic-N (PIN) diode configured to be a switch for switching the operation mode between transmitting and receiving when the RF coil is configured to be used for both transmitting and receiving, are connected to the RF coil.
Such circuit elements generate heat when a current is supplied. Consequently, when the magnetic resonance imaging system is operated, heat is generated around the RF coil. The heat can be conducted to the subject. For this reason, during operation of the magnetic resonance imaging system, the heat generated around the RF coil needs to be appropriately cooled. To solve the problem, a technology is contrived for cooling heat generated in a magnetic resonance imaging system by providing a cooling device in the magnetic resonance imaging system, and feeding cooling air to a portion that may generate heat, such as an area around an RF coil by using the cooling device (for example, see JP-A H8-322815 (KOKAI)).
However, heat is locally generated due to heat generation by various circuit elements around an RE coil, so that sometimes heat generation cannot be efficiently suppressed in some cases only by simply feeding cooling air to the RF coil as conventionally performed. Such phenomenon is often observed when a large current needs to be supplied to the RF coil, for example, when scanning a heavy subject.

MRI system and RF coil with enhanced cooling in vicinty of included circuit elements


A temperature monitoring and display system for use in data centers includes a magnetic layer that attaches to a server cabinet of a data center, and a flexible printed circuit board (FPCB). A plurality of lighting units and temperature sensors are mounted to the FPCB. An integrated controller of the temperature monitoring and display system receives temperature signals from the temperature sensors and, based on those signals, controls the lighting units to output predetermined colors.

1. Field of the Invention
The invention relates generally to data centers and, more particularly, to systems for monitoring and presenting information concerning the temperature in data centers.
2. Background Information
Organizations, such as companies, educational institutions, and others, often install numerous pieces of computing equipment in centralized locations known as data centers. A data center, which may be located in a building, typically includes a large number of information technology (IT) and/or computing equipment, such as servers, switches, routers, storage systems, etc. The equipment is often rack-mounted within server cabinets located in the data center. As a result of the dense packing of the IT equipment in the server cabinets and in the data center, significant heat is generated within the data center. To prevent premature failure of the IT equipment, which might otherwise occur due to the excessive heat generated within the data center, cooling equipment, such as computer room air conditioning units (CRACs), is often installed to cool the data center and the IT equipment located therein. Nonetheless, localized "hot" spots may occur in the data center due, e.g., to different IT equipment loadings in the server cabinets, different operating characteristics of the equipment, different placement of the server cabinets within the data center, air flow patterns, etc. Significant time and resources are spent by managers of data centers identifying such "hot" spots, and taking corrective action.

Temperature monitoring and display system for data centers


The invention relates to sensor chips with multiple layers of polysiloxane with improve homogeneity.

In recent years, there have been developed numerous solid phase systems based on self-assembled monolayers (i.e., SAMs) from bi-functional molecules (i.e., "linkers") that have gained ever more significance in analytical micro technology, wherein specific probe molecules are coupled, or, as the case may be, conjugated, onto the surface of a solid carrier, which can be confirmed with the help of suitable marking (for example, radio active, colored, or fluorescent marking).
For such systems, in analogy to electronic microchips, the term sensor chips has been adopted. In the case of the conjugation of biological molecules (so called "bioconjugation") in such sensor chips, for example, with oligonucleotides or antibodies, one speaks of "Bio Chips." Coupling on the surface of the carrier can be accomplished directly or indirectly. An example of indirect coupling is the coupling of a nucleic acid sequence to be tested by means of hybridisation onto an immobilized, complementary oligonucleotide used as a probe. In this case, the use of the probe has the additional advantage of the natural specificity of the interaction of biological macromolecules.
Typically, for the manufacture of sensor chips, surfaces of metal oxides, or, as the case may be, metalloid oxides, as, for example, aluminumoxide, quartz-glass, glass, are dipped in a solution of bi-functional molecules (so called "linkers"), which comprise, for example, a halosilane-(for example, chlorosilane-) or alkoxy silane group for coupling to the carrier surface so that a self-organized monolayer (SAM) forms. In this case, this SAM comprises a thickness of a few Ångstrom. The coupling of the linkers to the sample or probe molecules takes place by means of suitable further functional groups, for example, an amino or epoxy group. Suitable bi-functional linkers for coupling of a multitude of sample or probe molecules, particularly also those of biological origin, on a multitude of carrier surfaces, are known to one of ordinary skill in the art, see, for example, "Bioconjugate Techniques", GT Hermanson, Academic Press, 1996.
A homogenious and chemically resistant layer can be obtained by this method only with much difficulty. Monofunctional silanes, which are suitable for solid carriers with metal oxide or metalloid oxide surfaces, for example, monochlorosilanes such as aminopropyl monochlorosilane, while they achieve real monolayers, can be split off from the surface merely by means of hot water. Trifunctional silanes, such as, for example, aminopropyltriethoxysilane, form cross-links in solution, which can lead to an inhomogeneous layer of silanes on the carrier surface. Homogeneous layering is not thereby achieved, which results in a loss in quality. In addition, there are also changes in character within a chip series.
A further disadvantage of this process in its practical application is the relatively long incubation time of silane solutions. For an efficient layering, silation times of about two hours are often necessary.
An object of the present invention is, departing from this state of the art, to fabricate a sensor chip with homogeneous layering based on a silane linker, as well as a process which makes such a layer quickly and reproducibly.

Sensor chips with multiple layers of polysiloxane


A microlens substrate will warp when an oxide film is formed and annealed before forming a mask in order to adjust the etching rate of wet etching. Accordingly, a film exerting a stress that cancels out this warping is formed upon a microlens. This film functions as an optical path length adjusting layer.

1. Technical Field
The present invention relates to fabrication methods for microlens array substrates.
2. Related Art
Various types of electronic elements, including various types of wires such as data lines, scanning lines, and capacitance lines as well as thin-film transistors ("TFTs" hereinafter) are built into image display regions of electro-optical apparatuses such as liquid-crystal apparatuses. Accordingly, of the total amount of parallel light incident upon such an electro-optical apparatus, it is only possible to utilize an amount of light allowed by the numerical aperture of the pixels, unless some kind of measures are taken.
As one such measure, a microlens array containing microlenses corresponding to respective pixels has in the past been embedded into an opposing substrate, a microlens array substrate has been affixed to an opposing substrate, and so on. Doing so takes light that originally travels toward non-aperture regions outside the aperture regions of the respective pixels and focuses the light on a pixel-by-pixel basis so as to conduct the light to the aperture regions of the pixels. The electro-optical apparatus can produce a bright display as a result.
A high lens efficiency is a basic requirement in such microlenses. As such, methods for fabricating microlenses having aspheric surfaces have been proposed.
For example, JP-A-2004-70283 discloses a method for fabricating a microlens that includes forming on a substrate a first film that has an etching rate higher than the substrate, forming on the first film a mask in which a hole is provided at a position corresponding to a center of the microlens to be formed, and forming in the substrate an aspheric recess that defines a curved surface of the microlens by wet-etching the first film over the mask.
According to JP-A-2004-70283, after being formed on the substrate, the first film is subjected to annealing at a predetermined temperature so as to bake the first film and control the etching rate thereof. However, the inventors of this invention discovered that the annealing in this method causes the substrate to warp, causing problems in the subsequent steps of forming films and the like. A large warp in the substrate makes it difficult to position the element substrate and the opposing substrate when affixing the substrates to each other, making it generally difficult to affix the element substrate and the opposing substrate to each other. A large warp in the substrate can also make it impossible to carry out vacuum suction during the substrate transportation, resulting in errors, and can furthermore result in localized forces being applied when polishing the substrate surface during a smoothing process, which can cause the film to peel off.

Fabrication method for microlens array substrate


Circuitry formed of a two-dimensional regular array of capacitive elements 2 is coupled to decoding circuitry in the form of column decoder 8 and a row decoder 6. The decoders 8, 6 are used to select a start point and an end point within a sequence of selected capacitive elements to be connected in parallel following a horizontal raster scan arrangement. The selected capacitive elements may be used to generate an output voltage with a magnitude corresponding to the number of selected capacitive elements.

1. Field of the Invention
This invention relates to the field of circuitry for connecting capacitive elements in parallel.
2. Description of the Prior Art
It is known to provide circuitry for connecting particular combinations of capacitive elements in parallel so as to provide a desired overall capacitance, or a signal derived as a consequence of that overall capacitance. Such circuits typically incur an undesired overhead in signal routing and selection circuitry complexity.

Multi-dimensional array of impedance elements

The Regents of the University of Michigan


Various solutions for supporting out-of-order hybrid automatic repeat request (HARQ) feedback with respect to user equipment and network apparatus in mobile communications are described. An apparatus may construct a first HARQ-ACK codebook corresponding to a first physical downlink shared channel (PDSCH) and construct a second HARQ-ACK codebook corresponding to a second PDSCH received later than the first PDSCH. The apparatus may activating an out-of-order HARQ transmission to transmit the first HARQ-ACK codebook and the second HARQ-ACK codebook in an event that the priorities associated with the codebooks are different.

Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted as prior art by inclusion in this section.
In Long-Term Evolution (LTE) or New Radio (NR), hybrid automatic repeat request-acknowledgement (HARQ-ACK) information transmission is introduced to improve transmission reliability and robustness. The user equipment (UE) needs to report HARQ-ACK information for corresponding downlink receptions in a HARQ-ACK codebook. The HARQ-ACK codebook should be transmitted in a slot indicated by a value of a HARQ feedback timing indicator field in a corresponding downlink control information (DCI) format. The DCI format should also indicate the physical uplink control channel (PUCCH) resource scheduled for the HARQ-ACK information transmission. HARQ-ACK multiplexing can be used to facilitate HARQ-ACK information transmission.
In NR Release-15, there is a restriction on the order between the scheduled PDSCHs and their corresponding HARQ feedback. Such restriction could be described as "in a given scheduled cell, the UE is not expected to receive a first PDSCH in slot i, with the corresponding HARQ-ACK assigned to be transmitted in slot j, and a second PDSCH starting later than the first PDSCH with its corresponding HARQ-ACK assigned to be transmitted in a slot before slot j". Thus, in NR Release-15, out-of-order HARQ feedback is not supported. This restriction could be reasonable when a single service type is deployed.
However, the current framework of transmission of HARQ feedback bits is not suitable for ultra-reliable and low latency communications (URLLC). URLLC is introduced for emerging applications that demands high requirements on end-to-end latency and reliability. Different reliability aspects required for different service types are also variant. In spectral efficiency, URLLC HARQ feedback may require more physical resource block (PRB) allocation for reliability whereas Enhanced Mobile Broadband (eMBB) HARQ feedback is likely to require narrower frequency-domain allocation. Therefore, the out-of-order HARQ restriction is not suitable when different service types are deployed simultaneously.
Accordingly, how to design a new HARQ feedback mechanism to satisfy different performance requirements for different service types is an important issue in the newly developed wireless communication network. Therefore, there is a need to provide proper HARQ feedback design to support out-of-order HARQ feedback for better performance when different service types are supported.

Method and apparatus for out-of-order hybrid automatic repeat request feedback in mobile communications


The present invention provides peptides and peptide analogs that have tissue protective activities while having little or no potentially undesirable hematopoetic effects. The peptides and peptide analogs are useful in preventing and treating a variety of diseases and disorders associated with tissue damage.

Tissue damage can be caused by a substantive loss of tissue due to ischemic, traumatic, toxic, or inflammatory injuries in which cells within the tissue are destroyed by apoptosis or necrosis. Tissue damage can occur in a number of acute and chronic diseases and conditions. The degree to which tissue damage occurs is mediated by many factors, including the type of disease or injury, the level of or severity of inflammation or trauma associated with the disease or injury, the location of the tissue damage, and the vascular sufficiency of the tissue.
Recent evidence suggests that erythropoietin (EPO), a member of the Type-1 cytokine family, commonly associated with the maintenance of hematocrit may also play an important role in attenuating tissue damage through the interaction with its receptor, EPOR (Brines et al., 2004, Proc. Natl. Acad. Sci. USA, 101(41):14907-12). Although it is hypothesized that EPO may provide compensatory responses that serve to improve hypoxic cellular environment and modulate programmed cell death caused by metabolic stress, the underlying molecular mechanism is yet to be clearly understood.
Based upon this observation, investigators have explored the use of EPO in various indications. As an example, investigators have explored the use of EPO as a potential treatment for cancers based upon the observation that EPO used to treat anemia in oncology patients not only rectified the anemia but resulted in an enhancement of the well-being of the oncology patient as well. (see U.S. Pat. No. 6,579,525 and Blau C. A., 2007, Stem Cells 25(8):2094-7). U.S. Pat. No. 6,579,525 to Haran-Ghera et al. relates to the use of recombinant EPO for the treatment of multiple myelomas and hypothesizes that EPO induces an immune response to the tumor. Additionally, U.S. patent application Ser. No. 11/093,177, publication no. US 2005/0267027, discloses the use of EPO to inhibit angiogenesis in tumors by reducing HIF-1α and/or VEGF expression in the tumors.
However, EPO as a potential tissue protective agent suffers from serious disadvantages due to its erythropoietic effect. In particular with chronic dosing, such as would be envisioned in indications such as cancer and inflammation, the frequent applications of therapeutic doses of EPO may significantly increase a subject's hematocrit, which may lead to hypertension, seizures, and vascular thrombosis.
Further, with regard to cancer, the potential of EPO as a therapeutic has not been realized. It has been determined that several types of cancer, such as breast cancers, express, and tend to over-express, erythropoietin receptors. This has led to concerns that the therapeutic use of EPO to treat cancer would lead to further growth of the tumor as opposed to a regression of the tumor's development (see Blau, 2007, supra, and U.S. patent application Ser. No. 10/432,899, published as US 2005/0260580). This concern has been borne out in the clinic as several trials of EPO within various cancer indications have been halted due to an increase in mortality due to tumor growth (Blau). In light of these adverse clinical outcomes the FDA has attached a Black Box warning on approved EPO products cautioning against their use in unapproved cancer indications.
Additionally, mature human EPO protein is a 165 amino acid protein having a molecular weight of about 30.4 kDa measured by mass spectroscopy. The recombinant protein can be produced in Chinese hamster ovary cells in an expensive and labor intensive process that is highly regulated. Further, EPO must be stored under stringent conditions to maintain its activity. Given these limitations EPO is not an ideal candidate to address public emergencies, such as the release of a toxic agent such as radiation or a chemical agent, either through an industrial accident or act of terrorism or war that would require the rapid mass production of the therapeutic for wide distribution.
Accordingly, there is a need for tissue protective treatments that have little or no potentially detrimental effects and can be made readily available to the public.

Tissue protective peptides and peptide analogs for preventing and treating diseases and disorders associated with tissue damage


Micro-conduit with enhanced wetting characteristics for use in providing a blood heat exchanger apparatus with improved heat exchange capability. The micro-conduit comprises a plurality of elongated fibers, which may be made of a hydrophobic material such as polypropylene or polyethylene. Each fiber is open at two opposing ends, and has an inner surface between the open ends. The inner surface is coated with a wetting agent, such as phosphatidyl choline or another ampiphilic material with a hydrophilic end and a hydrophobic end. The fibers may have a shape and size that without presence of the wetting agent, would otherwise substantially impair free passage of water. The micro-conduit may be provided as a heat exchanger micro-conduit wrapping material, wherein micro-conduit fibers are attached to a thin flexible interconnect, such as woven netting, to maintain the fibers at predetermined spacings in substantially parallel alignment with each other. The wrapping material is wrapped about an elongated spindle to provide a generally cylindrical heat exchange core. Opposing first and second seals are created by applying potting compound between fibers proximate the spindle's first end and proximate the spindle's second end. After ends of the fibers are trimmed and sealed, a shell is placed around the core.

1. Field of the Invention
The present invention generally relates to heat exchangers for use in regulating the temperature of a patient's blood during surgery. More particularly, the invention concerns micro-conduit with enhanced wetting characteristics for use in the heat exchanger portion of a blood oxygenator.
2. Description of the Related Art
"Heart-lung" machines are known in the medical field. One component of these machines is a blood oxygenator. Blood oxygenators arc typically disposable and serve to oxygenate a patient's blood during medical procedures such as heart surgery. Most blood oxygenators employ a gas transfer membrane, which comprises thousands of tiny hollow fibers having microscopic pores. Blood flows around the outside surfaces of these fibers while a controlled oxygen-rich gas mixture flows through the fibers. Also, due to the relatively high concentration of carbon dioxide in the blood arriving from the patient, carbon dioxide in the blood diffuses through the fibers' microscopic pores and into the gas mixture. Due to the relatively low concentration of oxygen in the blood arriving, from the patient, oxygen from the gas mixture diffuses into the blood through the fibers' microscopic pores.
Most blood oxygenators also employ a heat exchanger to precisely regulate the temperature of a patient's blood. The heat exchanger usually includes one or more conduits housed in a vessel. The patient's blood is continuously pumped through the conduits, while a heat exchange medium such as water flows through the vessel around the conduits, or vice versa. The heat exchange medium is either heated or cooled to maintain the patient's blood at a desired temperature.
One example of a commercially successful blood oxygenator is sold under the designation MAXIMA.RTM. by Medtronic Corp. In the MAXIMA blood oxygenator, the heat exchange medium (water) blood flows inside relatively large diameter metal tubes while blood flows on the outside of the tubes within the vessel. The TERUMO brand oxygenator uses a different configuration, where blood flows inside relatively large, diameter metal tubes. In the BARD WILLIAM HARVEY HF-5700 blood oxygenators the blood flows outside plastic tubes that contain a flow of temperature-regulated water.
Known heat exchangers, such as those described above, have benefited the purposes of doctors and patients alike in many different applications. However, in their quest to continually update these products, design engineers are always seeking improvements. In this regard, some applications may benefit from heat exchangers with improved heat exchange characteristics. One sure way to increase the heat exchange rate is to increase the area of contact between the blood and heat exchange medium. Enlarging the heat exchanger, however, is undesirable because of the greater bulk, the increased weight, and the enlarged blood volume required to fill the vessel.
A different way to improve the heat exchange efficiency is to increase the number of heat exchanger tubes while decreasing their size. Furthermore, by running, blood inside these smaller tubes, the blood is more thoroughly and evenly exposed to the heat exchange medium. This approach can be problematic because priming small diameter tubes can be difficult or impossible. When "priming" the heat exchanger tubes, typically an aqueous solution is pumped through the tubes to displace the ambient air. Then, blood is pumped into the tubes following the aqueous solution. Priming small plastic tubes is problematic because the tubes tend to act as capillary tubes, which are associated with certain undesirable properties. In particular, the use of a large number of tubes has the effect of reducing the pressure drop across the tubes. Therefore, if a few tubes become plugged with bubbles of air or water, the aqueous priming solution easily finds a path through other unplugged tubes. Consequently, the trapped bubbles reluctantly remain in the plugged tubes. There can be dangerous consequences if an air bubble somehow releases and subsequently passes into the patient's bloodstream. Therefore, lack of reliable priming can be a significant problem in heat exchangers with a large number of small diameter heat exchanger tubes.
Another problem with the above approach is finding an appropriate material for manufacturing the heat exchanger tubes. Many materials are not suitable for this application due to the obviously low tolerance to contamination and toxicity. Although metals have been successfully used in past blood heat exchangers, metals present a number of difficulties. First, since tubes of small diameter must be manufactured more precisely, they are more expensive than larger tubes. Furthermore, this expense is compounded due to the increased number of heat exchanger tubes required in this design.
Unlike metals, plastics are typically inexpensive. However, many desirable plastics have relatively low critical surface tension, and thus do not "wet" easily with water or other aqueous priming solutions. This aggravates the priming problems resulting from the capillary effect in small diameter tubes, as discussed above. Furthermore, plastics have poor heat transfer characteristics and therefore their use necessitates an even greater surface area to efficiently achieve the desired heat exchange.

Blood heat exchange system employing micro-conduit


A net includes lower fixed and upper vertically adjustable parts. The net parts extend across a playing area. Ends of the net parts are fastened to posts at sides of the playing area. The lower net part is fixedly mounted at a lower post part. The upper net part is doubly folded along a line along a longitudinal direction, forming a fold along the line. The upper net part exhibits a downwardly-hanging portion on each side of the fold. The ends of the upper net part are fastened to a vertically adjustable upper post part. The fold of the upper net part is arranged across the lower net part in a longitudinal direction with a portion hanging down on each side of the lower net part, so that the upper net part at least between a lower part of the hanging portions encloses an upper part of the lower net part.

As from the year 2012, new rules for tennis games for young participants are being internationally introduced. Thus, in connection with training and playing, the young participants will be divided into different age groups, 5-8 years, 8-10 years, 9-10 years and those above the age of 11. These new rules imply, for example, that the different age groups will play under different conditions with regard to: the size of the racket, the hardness and hence speed of the ball, the size of the court and the height of the net.
In these contexts, the arrangement of the height of the net for different age groups is a factor that is difficult or laborious. At one and the same court, it may occur that young participants of various age groups and also senior players alternate with each other and have different playing-times. This may require a complicated adjustment of the height of the net which for the moment is to be adapted to the relevant category of players. One way of arranging this is to replace a net for the last playing category of players with a net adapted to the players that will use the court during the next period of time. Another way of achieving the height adjustment is to quite simply vary the height of the upper net edge above the ground by moving the whole net upwards or downwards by using existing hoisting and tensioning devices which are arranged at the posts which stretch the net at the ends thereof. A disadvantage of varying the height of the net in the last-mentioned way is that a traditional net in the raised position may let through balls below the net, since the net does not reach down to the ground in the raised position.
U.S. Pat. No. 4,852,876 discloses a solution for arranging a net with a vertically adjustable (i.e. raisable and lowerable) upper edge in a net for a tennis court. According to this solution, an upper auxiliary net is arranged. This auxiliary net has an upper longitudinal edge and a lower longitudinal edge, where the upper and lower longitudinal edges are fixed to auxiliary posts which may be hoisted, in the vertical direction, along fixed posts for the net at the two opposite sides of the court. Between the fixed poles, a lower fixed net is placed and stretched. The upper auxiliary net is arranged such that, when hoisted upwards or downwards, it runs parallel to the fixed net along one side thereof. By hoisting it upwards or downwards, the upper auxiliary net may be arranged with the upper longitudinal edge to a desired total height for the whole net. A disadvantage of this arrangement is that balls that are captured by the upper auxiliary net have a tendency to fall down between the upper auxiliary net and the lower fixed net, where these two parts of the net overlap.
No international standard regulating the arrangement of a vertically adjustable net has as yet been adopted.

Net with a vertically adjustable upper edge for a playing area and a method for adjusting the height of the upper edge


A computer-implemented method for contact photoplethysmography, abbreviated contact PPG, comprises obtaining during a time interval plural PPG signals for sub-regions of a lens or video frame; and combining the plural PPG signals to thereby obtain a multi-region PPG signal.

Photoplethysmography or PPG is an optical technique that allows to monitor one or more physiological parameters by detecting blood volume changes in peripheral circulation. PPG makes use of light absorption by blood to track these volumetric changes. When a light source illuminates the skin, the reflected light varies as blood flows. A light sensor then converts these variations in light reflection into a digital signal, the so called PPG signal. PPG signals are typically recorded using a pulse oximeter or photodetectors, for instance the camera integrated in an electronic device like a person's smartphone or other smart wearable or non-wearable device.
PPG can be used, among other applications, to monitor cardiovascular and hemodynamic parameters such as heartrate, heartrate variability, blood pressure, or to monitor other physiological variables such as stress, respiration or autonomic functions. One key part of an accurate monitoring with PPG is to obtain a high-quality, artefact-free signal, as PPG can be affected by various sources of noise.
International patent application WO 2014/024104, entitled "Device and Method for Extracting Physiological Information" and filed by Koninklijke Philips N. V., describes a method to improve the accuracy of remote PPG or non-contact-PPG, which is typically used to track a larger region of interest (e.g. a face) in daily applications like fitness. The method divides the region of interest in spatial sub-regions and partitions the PPG signal in signal subsets representing the respective sub-regions. The signal subsets are processed separately. The processing may involve a quality estimation. Thereafter, the signal subsets are combined into an enhanced signal. Distorted sub-signals can be attenuated or eliminated from the combined signal.
Also United States Patent Application US 2013/0272393 A1, entitled "Video Coding and Decoding Devices and Methods Preserving PPG Relevant Information" and filed by Koninklijke Philips N. V., concerns remote PPG.
Although remote PPG is non-obtrusive for the monitored person, it poses major challenges to signal detection and signal processing. As a consequence, the use of remote PPG remains limited to everyday applications like leisure or fitness as its accuracy and reliability are insufficient for medical applications.
As opposed to remote PPG, the present invention concerns contact PPG or contact PPG, wherein the measurement components are in direct contact with the skin in order to obtain a more reliable, more accurate PPG signal that facilitates medical diagnosis.
In applications where a contact PPG signal is processed to determine the heartrate variability, inaccuracies can result from a low signal quality. While a partially good quality signal gives sufficient information to make a reliable analysis, the presence of artefacts can severely affect the quality and can lead to misleading results. Consequently, there is a need to have a contact PPG signal as clean as possible, and to identify and remove bad quality portions to keep only the good quality ones for further analysis.
Artefacts include motion, bad positioning of the skin with respect to the light sensor or ambient light interference. The article "A new look at the essence of the imaging photoplethysmography" from the authors Alexei A. Kamshilin et al. also reports another artifact frequently observed in PPG signals: PPG waveform inversion. This phenomenon is manifested by a signal, or a part of the signal, being inverted in comparison with the usual orientation of the signal. This phenomenon has been observed in adjacent areas of the skin, one area presenting a signal in the usual orientation and the adjacent area presenting a signal in the opposite orientation. This leads to a quality loss of the PPG signal when these two areas are used to extract the signal. Explanations for this phenomenon are still to be validated.
In order to improve the quality of contact PPG signals recorded by means of a camera, it has been suggested to divide the image pixels into a matrix of sub-regions, or quadrants, and to apply a selection algorithm that determines the optimal sub-image, i.e. the quadrant whose PPG signal has the best quality, called the optimal region of interest.
The article "Investigation of Five Algorithms for Selection of the Optimal Region of Interest in Smartphone Photoplethysmography" from authors Rong-Chao Peng et al. describes five algorithms to select the optimal region of interest:                the Variance (VAR) algorithm selects the quadrant whose PPG waveform has the highest variance, i.e. the highest signal power, as optimal region of interest;        the Spectral Energy Ratio (SER) algorithm selects the quadrant whose PPG signal has the highest spectral energy ratio, i.e. which indicates the highest proportion for cardiac activity, as optimal region of interest;        the Template Matching (TM) algorithm selects the quadrant whose PPG signal has the highest similarity with a template waveform as optimal region of interest;        the Temporal Difference (TD) algorithm selects the quadrant whose PPG signal has the highest average intensity variation for pixels between adjacent frames as the optimal region of interest; and        the Gradient (GRAD) algorithm selects the quadrant whose PPG signal has the greatest average light intensity gradient as the optimal region of interest.
The article of Peng et al. concludes that the TM and TD algorithms outperform the others in selecting the optimal region of interest and consequently in selecting the PPG signal that enables to estimate physiological parameters with improved accuracy.
The article "Detection of the Optimal Region of Interest for Camera Oximetry" from authors Walter Karlen et al. describes yet another algorithm to determine the preferred quadrant or optimal region of interest. The proposed algorithm considers only blue channels and extracts beats or pulses from the PPG signal through mean pixel intensity calculation and the incremental-merge segmentation (IMS) algorithm. In other words, the selected optimal region of interest has the PPG signal with the highest pulses. Karlen et al. further also teach to select the incandescent white balance mode as preferable setting for PPG on the Samsung Galaxy Ace mobile phone.
In addition to selecting a subset of pixels, the so called optimal region of interest, it has been suggested to generate a PPG signal by choosing a specific color channel. The article "Comparison between red, green and blue light reflection photoplethysmography for heart rate monitoring . . . " from Jihyoung Lee et al. for instance suggests that green light is more suitable for monitoring heartrate.
United States Patent Application US 2011/0077484 A1, entitled "Systems and Methods for Identifying Non-Corrupted Signal Segments for Use in Determining Physiological Parameters" and filed by Assignee Nellcor Puritan Bennett Ireland, teaches to analyse the quality of contact PPG signal segments by processing the wavelet transform of PPG signals with a trained neural network. This results in corrupted and non-corrupted PPG signal segments being identified. Corrupted signal segments are removed or replaced by earlier received, non-corrupted PPG signal segments.
The known solutions rely on the selection of a single region of interest and extract the PPG signal from this selected region of interest. However, the selected region of interest is static, i.e. the optimal region is a single sub-region of pixels that is considered to be the same for the whole measurement. Useful information in other sub-regions is not used. This can lead to unsatisfying results when the optimal sub-region to extract the PPG signal varies across the measurement. The extracted PPG signal may then contain inversions and/or bad quality sections that reduce the accuracy of physiological parameter estimation, e.g. the accuracy of heart rate variability, and consequently the accuracy of any disease diagnosis, for instance AF diagnosis, built thereon.
Likewise, the color selection in known systems for contact PPG signal extraction is made beforehand and the same color is statically used for every analysis.
Furthermore, none of the prior art solutions aimed at improving signal quality target the camera settings that may negatively influence the contact PPG signal quality across various vendors and types of smart devices.
It is therefore an objective of the present invention to disclose a computer-implemented method for contact PPG that resolves one or more of the above-identified shortcomings of existing solutions. More particularly, it is an objective to disclose a method for contact PPG with improved accuracy and reliability.

Computer-implemented method and system for contact photoplethysmography (PPG)


Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.

By definition, an overmolded microelectronic package contains a base flange and a package body, which is molded over and bonded to the base flange during package fabrication. An overmolded microelectronic package may be produced via the injection of a selected mold compound, heated to a flowable state, into a tool cavity defining the shape of the molded package body and into which a base flange has been pre-inserted. The heated mold compound flows onto surfaces of the base flange and, upon cooling, forms a solidified package body. In certain instances, one or more microelectronic devices may be pre-mounted to the base flange prior to the overmolding process, in which case the molded package body may be formed as an essentially solid block of material encapsulating the microelectronic devices. Alternatively, the molded package body may be produced prior to microelectronic device attachment and formed to include an open cavity through which the frontside of the base flange is partially exposed. After formation of the package body, one or more microelectronic devices may be positioned in the open cavity, attached to the exposed portion of the flange frontside, and interconnected with the package leads. A lid or cover may then be positioned over and bonded to an upper peripheral edge of the package body to sealingly enclose the package cavity and the microelectronic devices contained therein.
Relative to other types of microelectronic packages, such as packages containing window frames, overmolded microelectronic packages can typically be produced at greater efficiencies and reduced manufacturing costs. These advantages notwithstanding, overmolded microelectronic packages remain limited in certain respects. As a primary limitation, separation or "mold-flange delamination" can occur at the interfaces between the overmolded package body and the base flange. Mold-flange delamination may be problematic in high temperature applications, particularly when the microelectronic package contains one or more semiconductor die composed of a high stiffness material, such as gallium nitride. To reduce the likelihood of mold-flange delamination, certain base flanges are now fabricated to include so-called "mold lock features" in the form of relatively large dove tail or half dove tail grooves. Such mold lock features are generally characterized by an overhang or "tail" feature, which partially encloses a peripheral groove formed around the flange frontside. During overmolding, the heated mold compound directed onto the flange frontside flows into the peripheral groove and beneath the overhang feature, thereby forming a relatively robust mechanical bond with the base flange upon cooling of the mold compound and formation of the molded package body.

Overmolded microelectronic packages containing knurled flanges and methods for the production thereof


A projectile and a projectile mount having a central bore into which the projectile is mounted and includes rotational formations functionally engaging between the projectile and the projectile mount which in use provides rotational motion to the projectile around an axis of rotation by the propulsion of the projectile along the axis of rotation.

Technical Field
The present invention relates to a projectile and in particular to a projectile that is fired from a chamber such as a bullet.
The invention has been developed primarily for use in a gun or rifle without the need of an elongated barrel mount and will be described hereinafter with reference to this application. However, it will be appreciated that the invention is not limited to this particular field of use and in particular could relate to projectiles in medical fields or other engineering fields.
Description of the Related Art
It is known that elongated projectiles generally need a spin in order to stabilize the projectile in flight and to impart a degree of accuracy in the direction of the flight. A primary mechanism for achieving this has been the creation of a rifling barrel in which the inside of the barrel is shaped with an inwardly extending helical curve coaxial with the axis of the barrel. The bullet is sized to match the bore diameter of the barrel so that when the bullet is propelled down the barrel, the inwardly extending helical curve of the barrel provides a frictional force on the travelling bullet sufficient by the end of the barrel to impart rotational spin to the bullet around its longitudinal axis.
A substantial problem with this process is the loss of energy by the frictional force and blow by leakage gases. Although there is the benefit of bullets being mass produced to generally fit the barrel, the bullet has to be sufficiently malleable relative to the inwardly extending helical curve of the barrel. This results in the bullet receiving rifling marks caused by deformations and stripping of material from the bullet, as well as loss of energy by frictional heat. A substantial increase of projectile energy is needed to compensate for the losses, and choices and costs of material substantially hinder ready construction.
The present disclosure seeks to provide a projectile that will overcome or substantially ameliorate at least one or more of the deficiencies of the prior art, or to at least provide an alternative.
It is to be understood that, if any prior art information is referred to herein, such reference does not constitute an admission that the information forms part of the common general knowledge in the art, in Australia or any other country.

Projectile system including a projectile mount and a projectile


A charger includes a control circuit (308) for determining the charge rate and charge capacity of a battery (312). Control circuit (308) switches the rate at which battery (312) is being charged from a first charge rate such as a rapid charge rate (206) to a charge rate which is increasing in charge over time (208). Once battery (312) becomes fully charged, control circuit (308) then charges battery (312) at a third charge rate such as a trickle rate (214).

Conventional battery chargers used to charge rechargeable batteries such as Nickel-Cadmium (NiCd) or Nickel Metal Hydride (NiMH) batteries in a rapid fashion typically drop the rate at which the battery is being charged once the battery begins to increase in temperature. For example, a typical rapid charger used to charge two-way radio batteries begins to charge the battery at a charge rate approximating the capacity of the battery in one hour (charge rate of "C"/hr where "C" is the capacity of the battery), the battery charger then drops the charge current to a trickle rate (e.g., C/20 or less) once the battery starts to increase in temperature by a certain amount over time (reaches a certain .DELTA.T/.DELTA.t). Usually the battery is between 88% and 93% charged at the time the charger switches to the trickle charge. At the trickle charge rate, the battery becomes fully charged after 10 or more hours in the battery charger.
The main reason for dropping the charge rate from a rapid rate to a trickle charge rate is to avoid excessive heating of the battery cells, since the charge efficiency of the battery cells decreases as the battery temperature increases. However, although reducing the charge rate protects the battery from thermal damage, the trickle charge rate requires 10 hours or more to fully charge the battery. A need thus exists for a method and apparatus which can fully charge a rechargeable battery faster but yet protect the battery cells from excessive heating.

Method and apparatus for charging a battery


A motor having enhanced transient characteristics during the acceleration time of the motor in a disk unit. The motor includes a motor controller having a phase-locked loop (PLL) or frequency-locked loop (FLL) for controlling the speed of a spindle motor in a disk drive. The PLL or FLL is coupled to a digital filter. The difference between a phase or frequency synchronized with the rotational speed of the motor and a target value is received by the digital filter. The digital filter output is added to the target value. The sum of the filter output and the target value is set in the PLL or FLL as an adjusted target value to perform PLL control or FLL control. With this arrangement, the time to shift from a low-speed rotation state to a high-speed rotation state can be shortened.

1. Field of the Invention
the present invention relates to a motor controller and a disk drive unit, and more particularly to a disk drive unit having accurate control of the rotational speed of a motor, such as a hard-disk drive.
2. Description of Related Art
Conventional disk drives typically use a spindle motor to rotate the disk or disks in the disk drive. The high-speed rotation (e.g., 5400 rpm) of a disk is achieved by fixing a hub, which integrally holds the disk, to the spindle motor and by transmitting the rotation of the spindle motor to the hub. A head typically flys above the disk at a predetermined fly height providing a gap between the head and the disk. When the head is positioned over the desired track, data may be read from or written to that track. When the motor does not accurately rotate the disk, it is difficult for the head to follow the track often leading to data errors when writing to or reading from the disk. Therefore, the disk drive is required to prevent these types of data errors to maintain stable high-speed rotation of the disks.
One method of controlling the rotational speed of a motor used in a disk drive is to compare a target frequency or a target phase with the frequency or the phase in synchronization with the actually measured rotational speed of the motor. The driving current of the motor is controlled by this difference. Such methods of controlling the motor speed is often referred to as the phase-locked loop (PLL) or frequency-locked loop (FLL) control methods. FIG. 1 illustrates a block diagram of a conventional FLL used for motor control.
According to FIG. 1, a target frequency and a measured frequency are provided to a frequency comparator 12 at inputs 10a and 10b, respectively. The target frequency represents the frequency of the input signal into the FLL circuit 10 and the measured frequency represents the feedback signal of the FLL circuit 10. The output of the frequency comparator 12 is coupled to a charge pump 14. The difference between the two input frequencies of the charge pump 14 control the amount of current generated and output by the charge pump 14. The output of the charge pump 14 is provided to the loop filter 16 for shaping the waveform. The loop filter 16 output is provided to a drive circuit 18. The drive circuit 18 generates and outputs a motor driving current. By controlling the driving current in this manner, a motor 20 is rotated. The rotational velocity of the motor 20 is converted to a frequency by a velocity/frequency (V/F) converter 22 and is provided to frequency comparator 12 as the measured frequency at input 10b. FIG. 2 illustrates the gain of the elements in the FLL circuit 10.
A drawback of the conventional motor speed controller using FLL or PLL control methods, such as FLL circuit 10 shown in FIG. 1, is that it is difficult to obtain a high-speed transient response. In other words, the time it takes to get the disk or disks into uniform motion is relatively slow. This results from a relatively large time constant of the loop filter in the PLL or FLL circuits. When there is an attempt to achieve high-speed and high-precision rotation of disk(s) in a disk drive, the impact of high frequency noise must be minimized. In order to filter out the impact of noise, there is the need to limit the gain, and consequently, the time constant cannot be reduced. Therefore, it is difficult to achieve a high-speed transient response with the conventional FLL or PLL circuits.
In the latest disk drives, particularly those used in personal computers, when the disk is not accessed within a predetermined amount of time, the current supply to the spindle motor is reduced or stopped in order to reduce dissipation power. Accordingly, the spindle motor is stopped or operates with reduced speed. In a power-saving disk drive such as this, if there is a request to access a disk during the time the disk is in its stopped state or being rotated at low speeds (i.e., the low power state), the rotational speed of the disk must be increased to a predetermined rotational speed. Data may be accessed from the disk once the rotation of the disk has been returned to the rotational speed at which data can be written to or read from the disk. Thus, the performance of the disk drive may be enhanced by how quickly the disk is returned to a predetermined rotational speed.

International Business Machines Corporation


A method and apparatus that detects a multiplicity of normal data sets, each of which includes values of n parameters, for each of the operation modes of an object having a plurality of operation modes. Self-organizing maps are provided for each operation mode using the normal data sets. Abnormal data sets representing virtual abnormal states are created by modifying the values of the n parameters of each of the multiple normal data sets so that as many abnormal data sets as the number of deviation vectors are created for each of the multiple normal data sets. Abnormal operation mode proportion vectors are then created by selecting a self-organizing map from the above noted self-organizing maps which has the highest similarity degree to each of the abnormal data sets.

Conventional machine maintenance adapts corrective maintenance in which a machine is repaired after it breaks down, or uniform preventive maintenance which is performed at predetermined intervals. Corrective maintenance entails a lot of time and cost for repair. Preventive maintenance generates unnecessary part and oil waste due to its uniformity and thereby imposes greater costs on customers. Further preventive maintenance is expensive because of the intensive labor required. There is a requirement for a departure from such conventional maintenance manners and for conversion to predictive maintenance in the future.
In predictive maintenance, the degree of soundness is diagnosed by understanding data of load and environment during operation, a database of past maintenance history, physical failure and others, and further deterioration and remaining life are predicted in order to find a defect on a machine at an early stage and to provide a safe operation environment.
For example, patent reference 1 relates to an abnormality diagnosis apparatus for a working vehicle such as a construction machine; a pressure sensor for detecting discharge pressure from a hydraulic pump, an engine speed sensor for detecting engine speed, an oil temperature sensor for detecting the oil temperature in a hydraulic circuit and a communication device for radio transmitting detection data by these sensors to a network management center (a network station) are installed in a vehicle body of a working machine (a hydraulic excavator), and a monitoring station (e.g., an office of the manager of the working machine) obtains the detection data of the working machine from the network management station through the Internet and diagnoses any abnormalities of the working machine based on the detection data.
Further, patent reference 2 relates to an abnormality detection apparatus for a fixed machinery facility such as a batch plant or a continuous plant; normal data when the object plant is in a normal state is previously collected, on the basis of the normal data, characteristics of the normal data are extracted using a Self-Organizing Map; on the basis of the characteristics, a characteristic map indicating distance relationships between outputting units is created and stored as a normal state model, and an abnormality of the object plant is detected based on the normal state model and input data (input vectors). Here, the normal state model is formed by converting multi-dimensional data into a visualized two-dimensional map as shown in FIG. 20 (in which the multi-dimensional data is classified into five clusters expressed by regions with symbols R1-R5), and if input data has a characteristic identical to the normal state model, the input data is judged to be normal data. The technique of patent reference 2 can totally detect an abnormality of multi-dimensional input data in real time.
Patent reference 1: Japanese Patent Application Laid-Open (KOKAI) Publication No. 2002-323013
Patent reference 2: Japanese Patent Application Laid-Open (KOKAI) Publication No. HEI 11-338848

Diagnosis of abnormal operation modes of a machine utilizing self organizing map