A down hole flow control device used in a well bore includes a central mandrel and a packer ring disposed thereon. The packer ring is compressible along a longitudinal axis of the central mandrel to form a seal between the central mandrel and the well bore. Upper and lower slip rings are disposed on the central mandrel and include a plurality of slip segments joined together by fracture regions to form the slip rings. The fracture regions are configured to facilitate longitudinal fractures to break the slip rings into the plurality of slip segments that secure the down hole flow control device in the well bore. The upper and lower slip rings have different fracture regions from one another to induce sequential fracturing with respect to the upper and lower slip rings when an axial load is applied to both the upper slip ring and the lower slip ring.

1. Field of the Invention
This invention relates generally to down hole tools for use in oil and gas wells, and more particularly to down hole tools having drillable materials and metallic slips.
2. Related Art
Down hole tools, such as well packers, bridge plugs, fracture ("frac") plugs, cement retainers, and the like, are commonly used in oil or gas wells for fluid control in both completion and production efficiency applications. For example, such down hole tools are often placed in the bore of a well to form a seal between the well tubing and casing in order to isolate one or more vertical portions of the well. A tool can also be placed inside the casing to isolate one elevation from another during formation fracturing and treatment operations.
Down hole tools often have central mandrel with lower slip elements adjacent a lower slip wedge and upper slip elements adjacent an upper slip wedge. The slip elements are often made of a cast iron material, composite material or the like, so as to facilitate drill out when removal of the down hole tool is desired. Additionally, a compressible packer is disposed between the upper and lower slip elements. The compressible packer is often made of an elastomeric material such as rubber so that the compressible packer can conform to the shape of the surrounding well bore and down hole tool in order to form a seal between the well bore wall or casing and the central mandrel.
In use, the down hole tool is positioned in the well bore at a desired depth and an axial force is applied to the upper and lower slip segments such that the upper and lower slip segments are moved closer together along the longitudinal axis of the central mandrel so as to compress the compressible packer. As the compressible packer is compressed, the packer bulges radially outward to form a seal between the central mandrel and the well bore wall or casing. Additionally, the upper and lower wedges are forced under the upper and lower slip elements, respectively, to force the slip elements radially outward away from the mandrel toward the well bore wall or casing in order to set the tool in the well bore by engaging the well bore wall or casing.
Because down hole tools are used in a wide range of well bore environments, they must be able to withstand extremes of high temperature and pressure as well as corrosive fluids, such as acid or brine solutions, superheated water, steam, and other natural formation fluids, as well as fluids used in oil or gas well operations. During normal well completion operations, the down hole tools must be removed to allow the installation of tubing to the bottom of the well to begin the recovery of oil and gas. In order to facilitate removal of these tools, the components are usually made of easily drillable materials, such as cast iron, fibrous composite materials, and the like.
Unfortunately, the down hole tools described above have some problems For example, the slip elements are often made of a cast iron ring with stress risers spaced about the ring. The stress risers are configured to fracture the ring into separable slip elements when the slip wedges apply radial forces on the cast iron ring. Unfortunately, the rings sometimes do not fracture along the stress risers, or the stress risers do not fracture uniformly so that the separable slip elements are not evenly formed. When this happens one of the separable slip elements may be larger than another so that when the slip elements engage the well bore wall or casing an uneven loading is applied around the central mandrel. This uneven loading can result in movement of the down hole tool over time as it is used in the well bore and which results in an loss of seal or damage to other well components.
Another problem of the down hole tools described above is that the cast iron rings that separate into the slip segments often fracture into the separable segments at nearly the same time. This can result in setting of the tool in the well bore before the compressible packer is sufficiently compressed to form an optimal seal between the central mandrel and the well bore wall or case.
Still another problem of the down hole tools described above is that the compressible packer is often exposed to a wide range of temperatures. Sometimes the temperatures can soften or melt the polymer of the compressible packer such that the packer material can flow under pressure around the slip wedge and through the gaps between the separated slip elements such that the integrity of the seal can be compromised. Alternately, the packer material can flow into the gap between the conical wedge outer diameter and the casing inside diameter.


Methods, systems and computer programs for distributing a computing operation among a plurality of processes and for gathering results of the computing operation from the plurality of processes are described. An exemplary method includes the operations of pairing a plurality of processes such that each process has a maximum of one interaction partner, selecting half of the data located at a process, dividing the selected half of the data into a plurality of data segments, transmitting a first data segment resulting from the dividing operation from the process to the interaction partner of the process, receiving a second data segment at the process from the interaction partner, concurrently with the transferring and receiving operations, performing a computing operation on a third data segment previously received from a previous interaction partner and a fourth data segment from the data segments, and iterating over the transmitting, receiving and computing operations until all the data segments have been exchanged.

Parallel completing is the distribution of a computing operation among a plurality of processors and/or a plurality of computing systems. Parallel computing is advantageous because a computationally expensive processing task may take less time to complete if more processors are used. For example, scientific and technological research frequently comprises computational tasks which, due to their complexity, require years to complete on a single processor. However, such tasks can frequently be completed in a manageable amount of time if divided among a large number of processors. Weather forecasting and computerized simulations of real-world phenomena also frequently comprise complex computational tasks which may benefit from parallel computing. Parallel computing is particularly advantageous for high performance computing, a term used in the art to denote computing tasks requiring very large amounts of computational resources.
Historically, computationally expensive computing tasks have been executed by supercomputers, specialized systems having very fast processors. However, a parallel computing system may solve such tasks in a more cost-effective manner than a supercomputer. A primary reason is because adding additional processors through parallel computing may improve performance more effectively and/or at a lower cost than increasing computing power by increasing the speed of an individual processor. This is because there are diminishing returns to increasing the speed and performance of a single processor. By contrast, there is often virtually no limit to the number of processors which may contribute to a computing task. The overhead required to couple together multiple processors is a far lass significant factor than the diminishing returns of increasing the speed of a single processor. Moreover, parallel computing may beneficially reduce the power consumption required to complete a computing task. This is because performance derived from parallel execution is generally more power efficient than performance derived from increased processing speed.
One of the operations in parallel computing is the global reduce operation. In a global reduce operation, a plurality of processes collaborate to complete a computing operation. The processes are located at different processors and/or different computing systems. Each process initially has a quantity of data known in the art as an input vector. The global reduce operation combine all the input vectors using a specified computing operation or set of computing alterations. When the vectors are large, this may be achieved by each processor performing the computing operations or set of computing operations on a subset of the vector. It is emphasized that a wide variety of computing operations known in the art may be applied in conjunction With global reduce. The performance of the global reduce operation is essential to many high performance parallel applications.
For parallel computing to succeed, it is important for the processes sharing responsibility for a computing task to interact effectively with each other. It is highly advantageous for the computing task to be divided among the participating processes in predefined ways. To achieve this goal, the processes should ideally communicate with each other according to predefined communication protocols. The Message Passing Interface, or MPI, is a protocol known in the art for facilitating communication between a plurality of processors cooperating on a computing task. MPI defines semantics of various types of communications.
To facilitate communication, MPI defines a plurality of primitives. Some MPI primitives perform point-to-point communication. Among these primitives are a one-way sending operation and a one-way receiving operation. Other MPI primitives facilitate collective communication. These primitives include MPI_BARRIER and MPI_BCAST. A subset of the collective communication primitives are noteworthy because they distribute a computing operation across multiple processes. Specifically, the primitives combine both communication and computing within the same operation. This subset comprises the primitives MPI_REDUCE and MPI_ALLREDUCE, both of which perform a global reduce operation.
In an MPI_REDUCE operation, each process has an input vector. The output of the MPI_REDUCE operation is the result of applying the global combining or reducing operation on ail the input vectors. Certain core computing operations, including summation and determining a minimum or maximum value, are defined, by MPI. Additionally, customized computing operations not envisioned by MPI may be implemented. Where the reduction is complete, the result of the reduce operation is available at a single process, known as the root. It is possible to specify which process shall serve as the root.
The input acid output of an MPI_ALLREDUCE operation is similar to a MPI_REDUCE operation. However, at the conclusion of an MPI_ALLREDUCE operation, the combined result of the reduce operation across all processors is available at each processor.
The performance of the MPI_REDUCE and MPI_ALLREDUCE primitives are important for the performance of parallel computing applications based on the MPI. One long term profiling determined that for parallel computing applications using the Message Processing Interface, the amount of time spent within MPI_REDUCE and MPI_ALLREDUCE accounted for more than 40% of the total time spent by the profiled applications in any MPI function. See Rolf Rabenseifner, Optimization of Collective Reduction Operations, International Conference on Computational Science 2004, Lecture Notes In Computer Science {LNCS}, Volume, 3036/2004, Springer.
The computational cost of MPI_REDUCE or MPI_ALLREDUCE is at least (N−1)Lγ, where N is the number of processes, L is the length of the vector in bytes and γ is the reduce operation cost per byte. If distributed evenly across the processes, the computational cost at any particular process is at least
            (              N        -        1            )        N      L                  γ    .
The interconnection means of computing systems may include Remote Direct Memory Access (RDMA) capability. RDMA is a method by which data in memory belonging to one computer system can be transmitted to memory belonging to another computer system concurrently with processors of both systems performing distinct operations and without interfering with those operations. Techniques exist in the prior art for using RDMA to improve the performance of MPI_REDUCE and MPI_ALLREDUCE for large messages. Specifically, the overlapping of processing with data transfer provided by RDMA can foe combined with the pipelining provided by MPI_REDUCE and MPI_ALLREDUCE. This prior art technique will be referred to herein as the Pipelined RDMA (PRT) algorithm.
For MPI_REDUCE, the PRT algorithm splits each input vector into q slices and pipelines the handling of those slices. Communications are organized along edges connecting nodes of a process tree. Nodes of the tree represent the participating processes, and the root of the tree is the root of the MPI_REDUCE operation. Each process requires q steps of communication and computation. At step i, a process first waits for all of its child processes to deliver slice i of their vectors via RDMA. The parent process then combines the received slices with slice i of its own input vector. The reduce operation performed on slice i at the process is overlapped with the receiving of slice (i+1) from its child processes. This is possible because the reduce operation is performed by the processor while data transfer is handled by an RDMA adapter. Finally, the parent process sends the combining result to its parent. Here again, the sending of slice i can be overlapped with the reduce operation on slice (i+1).
While the PRT algorithm offers improved performance compared to non-RDMA implementations of the MPI_REDUCE and MPI_ALLREDUCE primitives, it is nonetheless suboptimal. For example, consider that either the computational cost to reduce a single byte is greater than or equal to the communication cost to transmit a single byte, or the computational cost to reduce a single byte is less than the communication cost to transmit a single byte. This follows directly from the mathematical truism that for two defined numbers, the first number must be either greater than, equal to or less than the second number.
If the reduction cost is greater than or equal to the communication cost, most of the communication cost is overlapped by computation. In this case, the computational cost of PRT algorithm when implemented using binary trees is approximately
      (          2      +              2                                                    log                                            (                N                )                                      -            1                    q                      )      L                  γ    .  This is more than double the lower bound of the distributed computational cost inherently required by MPI_REDUCE and MPI_ALLREDUCE. Implementing the PRT algorithm with other process tree structures would result in an even higher cost.If instead the reduction cost is less than the communication cost, the communication cost then becomes the predominant factor in the total cost required to apply the PRT algorithm. The communication cost can be approximated by
            (              1        +                                            log                                            (                N                )                                      -            1                    q                    )            L                          β    ,where β is the communication cost to transmit a single byte. The total amount of data communicated by each process which is neither a leaf note nor a root node is 3 L. This is because each such process receives a vector L bytes in length from each of two child processes and sends a vector L bytes in length to its parent process. Although RDMA removes the serialization bottleneck at the processor and memory for transferring this data, the adapter bandwidth requirement is significantly increased. This disadvantage is especially pronounced when, implementing the MPI_ALLREDUCE primitive, because each process which is neither a leaf nor the root mist transfer 6 L bytes of data.

Iteratively processing data segments by concurrently transmitting to, processing by, and receiving from partnered process

International Business Machines Corporation


A method and an apparatus to divide image blocks to improve the quality of intermediate images by splitting each macro image block (macro block) in left-eye and right-eye views into sub image blocks (sub blocks) according to quadtree disparity estimation, and then splitting each sub block into smaller sub blocks. The method includes setting a plurality of splitting threshold values for a macro block in an image frame and determining whether to split the macro block into sub blocks, and setting a plurality of splitting threshold values for each sub block and determining whether to split each sub block into smaller sub blocks.

1. Field of the Invention
The present invention relates to a method and apparatus to divide image blocks, and more particularly, to a method and apparatus to improve the quality of intermediate images. To achieve such improvements, this invention proposes a new standard to divide image blocks that can prevent flickering in synthesized intermediate images when splitting image blocks using quadtree disparity estimation. The image block splitting is followed by disparity estimation required for synthesis of intermediate views used to represent a three dimensional (3D) image.
2. Description of the Related Art
To realize an imaging and communication system that provides a high degree of realism and naturalness, it is necessary to develop 3D image processing technology that can naturally represent images according to human visual characteristics. 3D image processing employs binocular parallax, which is a difference in depth of an object perceived by left and right eyes. Processing and transmission of binocular images is of great concern in the field of next generation visual communication.
However, one significant problem associated with such image processing and transmission is a large amount of information contained in stereoscopic images, considering the fact that most images are color or moving images as well as transmission rate over a transmission line and processing rate of a transmission (or image processing) system. To overcome this problem, it is necessary to research a technique to efficiently and easily compress a large amount of information while maintaining the quality of a stereoscopic image.
Research is being conducted to develop a method that involves estimating variation in objects within an image using the fact that left and right views have high correlation, instead of independently encoding the two views, transmitting the variation information and either the left or right view, and compensating and restoring the transmitted view to binocular images at a receiving terminal.
Further, when the viewpoint of an observer moves or there are several observers, multi-view images are needed to create a natural stereoscopic image. However, since independent transmission of all multi-view images excessively increases the amount of information, reconstruction of multi-view images from binocular images restored at the receiving terminal of a binocular image transmission system, often called intermediate view reconstruction (IVR) or intermediate view synthesis, is used. In this case, reconstruction can be performed using intermediate view interpolation or extrapolation by obtaining variation information related to intermediate views from information on variation between the binocular images.
3D images are compressed and decompressed using an MPEG technique applied to two dimensional (2D) images. In particular, compression, transmission, and decompression of 3D images for digital broadcasting are performed using MPEG-2, which is a standard for digital broadcasting.
As is widely known in the art, MPEG-2 uses block-based compression schemes to compress 2D images. Currently, these schemes are also applied to compression of 3D images and are known as the most efficient method of 3D image compression.
Block-based compression is performed in blocks of a fixed size (for example, 16×16 pixels), each of which is called a macro block. Compression is achieved by motion estimation in units of a macro block and calculating a motion vector, which is the resulting value of estimation, and prediction error. When macro blocks of a fixed size are used in synthesizing intermediate views from binocular images, as in 2D images for stereoscopic depth perception by a viewer of 3D images as mentioned above, degradation in the quality of intermediate views may occur. In particular, quality degradation due to blurring of the edges of an image becomes a significant problem.
To overcome this problem, various quadtree disparity estimation approaches that can prevent quality degradation by splitting a macro block of a fixed size into smaller sub blocks near the edge of an image have been proposed (1998 SPIE Paper: Anthony Mancini and Janusz Konrad, "Robust Quadtree-based Disparity Estimation for the Reconstruction of Intermediate Stereoscopic Images", and IEEE 0-7803-6685-9/01 Paper: D. R. Clewer, "Efficient Multiview Image Compression Using Quadtree Disparity Estimation").
According to a quadtree disparity estimation approach, a block matching technique is used to calculate a mean absolute difference (MAD) of each macro block in left-eye and right-eye views and MADs of four sub blocks into which the macro block is divided. Then, if a ratio Rmadsub1 of the maximum sub block MAD to the minimum sub block MAD within a macro block is less than a predetermined threshold, disparity between binocular images is estimated in units of macro blocks. Conversely, if Rmadsub1 is greater than the threshold, disparity is re-estimated for each sub block. Since a method of calculating MADs is described in detail in literature including the above-cited references, a detailed description will be omitted.
FIG. 1A shows a conventional block splitting algorithm using quadtree disparity estimation. As mentioned above, a quadtree disparity estimation approach involves splitting an N×N macro block into four (N/2)×(N/2) sub blocks and estimating disparity in units of sub blocks when the ratio of the maximum sub block MAD to the minimum sub block MAD within the macro block is greater than a predetermined threshold. The conventional block splitting process using the quadtree disparity estimation approach will now be described in detail with reference to FIG. 1A.
If an N×N macro block that is the highest level block in disparity estimation (hereinafter called "Large Macro block (LMB)") is input (operation S10), block matching between binocular images is implemented to estimate disparity between the binocular images and verifies if the resulting estimate is correct. The adequacy and correctness of estimation is determined by Rmadsub1, which denotes the ratio of the maximum MAD of any sub block (lower level block) within a macro block (higher level block) to the minimum MAD of any sub block within the same macro block. As Rmadsub1 becomes greater, the disparity difference between regions in a block becomes greater, and thus this estimation becomes less accurate. If the resulting estimate is verified as the most ideal one, which means there is little disparity difference between regions within the block, Rmadsub1 approximates 1, which is the minimum value.
Next, in operation S11, it is determined whether to split the LMB. This is done by determining whether Rmadsub1 is greater than a first threshold value Rth1, which is the reference value used to judge whether to split the LMB. Rth1 is decided by experiment.
If Rmadsub1 is less than Rth1, which means disparity present between binocular images is low, LMB is not split (operation S111) and disparity is estimated in units of LMBs (operation S16). Then, in operation S17 it is decided whether to split the next LMB.
If Rmadsub1 is greater than Rth1, the LMB is split into four (N/2)×(N/2) sub blocks (hereinafter called "Middle Sub Blocks (MSBs)") (operation S12), and it is determined whether to split each MSB (operation S13). For this determination, the MAD of each (N/4)×(N/4) sub block (hereinafter called "Small Sub Block (SSB)") within an MSB is calculated. Then, Rmadsub2, the ratio of the maximum SSB MAD to the minimum SSB MAD within an MSB, is calculated and compared to a second threshold value Rth2, which is a reference value to determine whether to split the MSB. Like Rth1, Rth2 is decided by experiment.
If Rmadsub2 is less than Rth2, the MSB is not split (operation S14) and disparity is estimated in units of MSBs (operation S16). Then, in step S17 it is determined whether to split the next LMB.
If Rmadsub2 is greater than Rth2, the MSB is split into four (N/4)×(N/4) SSBs (operation S15). Then, in operation S17 it is determined whether to split the next LMB.
FIG. 1B shows image blocks produced in a block splitting procedure using a quadtree disparity estimation approach. Each block is contained in a 720×288 image frame. A block splitting technique proposed by the present invention is applied to the image blocks shown in FIG. 1B. For an image created by interlaced scanning, in particular, this splitting may be performed in frames or fields. As mentioned above, the conventional block splitting algorithm splits a higher level block into four lower level blocks in order to re-estimate disparity when the maximum to minimum MAD ratio of the lower level blocks exceeds a single threshold, thus obtaining more detailed intermediate views.
However, a little change can occur in disparity due to shaking of the camera, changes in lighting conditions, and noise components such as dust, even in a still image or low complexity image (with less motion). Since blocks in this kind of image may have MAD ratios near a threshold, the determination of whether these blocks are split is highly dependant on such changes in disparity. Thus, disparity estimates suffer from a significant change when synthesizing intermediate views for such an image block. In this case, since the conventional block splitting algorithm applies each single threshold when splitting an LMB into four MSBs and an MSB into four SSBs, flickering can occur in synthesized intermediate views.
Furthermore, the conventional block splitting algorithm in the quadtree disparity estimation approach cannot prevent degradation in quality of intermediate views, in particular, flickering near edges, by adopting a single threshold.

Method and an apparatus to divide image blocks


A capsule making machine includes a pin bar having a set of passageways disposed so as to allow free passage of fluid through a base. In another aspect of the present invention, a hood having a substantially triangular side view shape is disposed within the capsule hardening station for dispersing fluid upon the pin bars to promote hardening of the capsules. Another aspect of the present invention provides specific heating temperature ranges within predetermined section of the capsule hardening station. Methods of constructing a pin bar and for operating a capsule making machine are also provided within the present invention.

This invention relates generally to medicinal capsule making machines and specifically to a capsule making machine employing improved pin bars and air flow characteristics.
It is well known to provide a gelatin, hard shell capsule making machine employing pin bars which sequentially move from a preheating station, to a greasing station, dipping/spinning/front elevator station, upper deck heating kiln, rear elevator, lower deck heating kiln, and finally to an automatics section. One such device is disclosed within U.S. Pat. No. 1,787,777 entitled "Capsule Machine" which issued to Colton on Jan. 6, 1931, and is incorporated by reference herewithin.
Most conventional capsule making machines employ pin bars consisting of an elongated base and a plurality of depending pins. The pins are dipped into a liquid gelatin capsule solution at the dipping station. The gelatin capsule solution adheres to the pins and is subsequently dried and hardened within a heated kiln. The hardened capsules are then cut and removed within the automatics station. Thereafter, the automatics station temporarily joins the cap portion of the capsule with the body portion of the capsule. Cellulose capsule making machines are somewhat similar to the gelatin capsule making machines except that cooled pin bars are placed within a relatively hot gelatin capsule solution and then subsequently hardened by cooling in cooling chambers in place of the kilns.
Conventional pin bars have a rectangular cross sectional shape. The pins are typically inserted into a set of openings centrally located within the otherwise solid and unpierced base. This set of openings are longitudinally aligned and adapted to receive a constricted portion of the pins. Such exemplary pins and pin bars are disclosed within U.S. Pat. Nos.: 4,758,149 entitled "Capsule Forming Pin Having a Burnish-Hardened Surface" which issued to Sauter on Jul. 19, 1988; 5,032,074 entitled "Apparatus for Manufacturing Hard Capsules for Medicament Use" which issued to Muto et al. on Jul. 16, 1991; 4,997,359 entitled "Multi-Well Dish for Capsule Making" which issued to Lebrun on Mar. 5, 1991; 4,627,808 entitled "Apparatus for Making Capsule having Plural Chambers" which issued to Hughes on Dec. 9, 1986; and 3,399,803 entitled "Self-Locking Medicament Capsule" which issued to Oglevee et al. on Sep. 3, 1968. The preceding patents are all incorporated by reference herewithin. Solid pin bars are also disclosed within WIPO Patent Publication No. WO 92/21311 entitled "Method and Apparatus for the Manufacture of Pharmaceutical Cellulose Capsules", published on Dec. 10, 1992, and Canadian Patent No. 1 151 823 entitled "Hard Shell Gelatin Capsule Dipping Apparatus and Method" which issued on Aug. 16, 1983.
These traditional solid pin bars retard desired air flow within the drying kilns since hundreds of these pin bars are closely juxtapositioned within the upper deck kiln and the lower deck kiln. Therefore, essentially no heated air can pass through the bases of the pin bars and extremely little heated air can pass between the tightly packed bases. This is schematically shown in FIG. 1 which illustrates one side of a traditional machine. In this figure, heated air is blown from a hood 21 and directed downward upon the upstanding pins 23. This air stream is then deflected to the side of the kiln by the bases of the pin bars such that the air flow is then received by an outlet 25 alongside the kiln. Thus, these solid pin bars do not allow for uniform air flow to the innermost rows of the pins thereby allowing undesired irregularities in the final capsule wall thickness and the like. This leads to inefficient heating, costly scrappage of parts and a less than optimum process control.
A variety of drying duct formations have also been employed with traditional capsule making machines. For example, reference should be made to U.S. Pat. Nos. 1,978,829 entitled "Method and Apparatus for Drying Capsules" which issued to Wilkie on Oct. 30, 1934 and 1,114,325 entitled "Capsule Machine" which issued to Winchester on Oct. 20, 1914. These conventional ducts are often cumbersome and difficult to package within modern capsule making machines. Accordingly, it would be desirable to provide improved pin bars which enhance uniform air flow and heating characteristics. It would also be desirable to employ more easily packaged hoods.

Capsule making machine having improved pin bars and air flow characteristics


Provided are formulations of a stable paroxetine hydrochloride tablet comprising paroxetine hydrochloride, povidone or copovidone as a binder, and an HCl free/non-hygroscopic filler, prepared by the wet granulation method. Preferably, the paroxetine hydrochloride is paroxetine hydrochloride hemihydrate.

Paroxetine, (−)-trans-3-[(1,3-benzodioxol-5-yloxy)methyl]-4-(4-fluorophenyl) piperidine; (3S, 4R)-3-[5-(1,3-dioxaindanyl)oxymethyl]-4-(p-fluorophenyl)piperidine, is a 5-hydroxytryptamine (5-HT, serotonin) re-uptake inhibitor having the formula:

Paroxetine, disclosed in U.S. Pat. No. 4,007,196 (incorporated herein by reference), is prescribed for the treatment of psychiatric problems including depression, Parkinson's disease, anxiety disorders, obsessive-compulsive disorders, panic disorder and post-traumatic stress disorder. Other syndromes such as pre-menstrual syndrome (PMS) and male sexual dysfunction can also be treated with paroxetine.
Paroxetine is marketed as Paxil® in the U.S. and as Seroxat® in other countries by GlaxoSmithKline. Paxil® is prescribed as oral dosage tablets containing 10 mg, 20 mg, 30 mg and 40 mg of the base equivalent of paroxetine hydrochloride. Paxil® tablets include dibasic calcium phosphate dihydrate, hydroxypropyl methylcellulose, magnesium stearate, polyethylene glycols, polysorbate 80, sodium starch glycolate, titanium dioxide and one or more of the following: D&C Red No. 30, D&C Yellow No. 10, FD&C Blue No. 2, FD&C Yellow No. 6.
Paxil® is also available as an oral suspension with a dosage of 10 mg of the base equivalent of paroxetine hydrochloride in a 5 mL suspension containing polacrilin potassium, microcrystalline cellulose, propylene glycol, glycerin, sorbitol, methyl paraben, propyl paraben, sodium citrate dihydrate, citric acid anhydrous, sodium saccharin, flavorings, FD&C Yellow No. 6 and simethicone emulsion, USP.
Commercial paroxetine tablets, such as Paxil® and Seroxat® contain paroxetine as paroxetine hydrochloride (HCl) hemihydrate. Although Paxil® and Seroxat® contain HPMC, it is believed that HPMC is a component of the coating in these tablets, which are probably manufactured by a direct compression method. It is believed that these tablets do not contain a binder.
Many problems are associated with paroxetine hydrochloride tablets. See e.g. WO 00/32593, incorporated herein by reference. One such problem is the susceptibility to changes in mechanical properties, particularly hardness. Paroxetine hydrochloride tablets are particularly susceptible to becoming soft during storage, especially under accelerated aging conditions. In tests performed under accelerated aging conditions, tablets of Seroxat® and those containing HPMC as a binder and microcrystalline cellulose as a filler lost a substantial amount of their hardness, more than about 40%. Thus, there is a continuing need to improve the preparation and formulations of paroxetine hydrochloride oral dosage forms, particularly tablets.

This patent is subject to a terminal disclaimer.

Stable pharmaceutical formulation of paroxetine hydrochloride and a process for preparation thereof


The present application relates to a method of manufacturing a heat sink from a plurality of extruded lamellas, each lamella including a base portion having a top surface, a bottom surface, and two side surfaces, each lamella further including a fin portion extending from the top surface of the base portion, wherein the base portion is wider than the fin portion. The method includes aligning the base portions of the plurality of lamellas with the fin portion of each lamella extending in the same direction and the side surfaces of adjacent base portions facing each other; pressing the base portions of adjacent lamellas into contact with each other by applying a force to the side surface of at least one of the base portions; and welding the bottom surfaces of adjacent base portions together. A heat sink and a lamella for use in manufacturing a heat sink are also disclosed.

In order to cool the temperature of electronic components, aluminum heat sinks are often used. Aluminum and/or aluminum alloys are often utilized to form heat sinks due to their high thermal performance characteristics, ability to be extruded and availability in the marketplace. A cost efficient way of manufacturing an aluminum heat sink is extruding the metal in a fin and base configuration as shown in FIGS. 1a-1d.
In the embodiment shown in FIG. 1 and disclosed in U.S. Pat. No. 6,637,109 B2, the heat sink has base portions 15 and 17 that act as a mounting surface for the heat generating components, and the fins therebetween form a fin portion which adds a surface area, which is critical for maximizing heat dissipation from attached heat-generating components. Heat that is generated by the components is initially transferred through conduction to the base portions 15 and 17 (top and bottom portions) of the heat sink and subsequently into the fins where the heat is dissipated to the surroundings via radiation, forced convection, and/or natural convection. Because there is a direct correlation between the amount of surface area and total heat transfer, it is advantageous to maximize fin height and density, which minimizes the gap/space therein between fins, particularly when dealing with forced convection applications.
Aspect ratio is a relationship for characterizing heat sinks, where the ratio is mathematically defined as fin height divided by the gap between fins. Current extrusion technology limits the ratios achievable because as the aspect ratio increases, the extrusion die becomes weaker when extruding such heat sinks as a one-piece profile. To decrease the probability of die failure, the extrusion process speed is usually decreased, reducing overall productivity of the extrusion press. Heat sinks with higher ratio fins manufactured as one-piece by the aluminum alloy extrusion method also incur larger scrap rates.
One method of addressing issues related to manufacturing of high-aspect ratio heat sinks from single extruded profiles is joining them together by Friction Stir Welding (FSW) as disclosed in U.S. Pat. No. 6,637,109 B2. The method includes extruding or bending of an extruded profile which is cut in a plurality of pieces of the appropriate length. The single profile cross-section includes a first end portion, a second end portion, and a connecting web portion, where the first and second base portions are thicker than the web portion. The pieces of extruded profiles are then aligned and joined together by friction stir welding along their contacting surfaces. In cases where heat generating components are placed on both the top surface of the base portion 15 and the bottom surface of the base portion 17, this can be a cost effective solution that overcomes the problem of extruding a single piece as noted above.
A drawback of this method is that it cannot be utilized to form a heat sink having a base plate for mounting the element to be cooled on only one side. This problem occurs when such a "one-sided" heat sink with very dense fins is needed. It is not possible to extrude a one-sided heat sink with dense fins as a single-piece unit due to previously mentioned limitations surrounding the aluminum extrusion process.
Thermal performance of heat sinks generally increases as the ratio of fin height to fin gap increases. As a result, bonded heat sinks are used when high heat load dissipation is required. Bonding techniques for making bonded heat sinks include brazing, epoxy bonding, mechanical (press-fit or snap), and friction stir welding. However, while high fin density heat sinks can be made by brazing and epoxy bonding, a filler material has to be used to facilitate the bond, which creates some degree of thermal resistance at the joint, which has a negative effect on overall thermal performance. Additionally, these methods are labor intensive, which causes their manufacturing costs to be quite high. Furthermore, it is known that epoxy joints can weaken over time, reducing the mechanical strength of the bond and inhibiting heat transfer.
Mechanical joining includes making heat sinks from extrusions, profiles, called lamellar, or other segments having a number of fins and interconnected by press and/or snap fitting. However, while this method is cost-efficient, it suffers from a few disadvantages. The disadvantages of mechanical joining include a mediocre bonding strength, which is not suitable for all applications. This can cause reliability issues during exploitation of such a heat sink. Additionally, air gaps can exist around mechanical joints, which can cause high spreading thermal resistance. Furthermore, machining and drilling processes, which are required for heat pipe integration and/or heat generating component attachment, may loosen the adjacent mechanical joints of two neighboring extrusions or profiles.
Friction stir welding has also been utilized as a bonding method to join aligned extrusions or lamellar segments. Friction stir welding for joining parts made of aluminum alloy typically utilizes a non-consumable rotating tool including a shoulder and a pin, which often includes specially configured surfaces for increasing friction when the tool is in contact with the metal. The rotating friction stir welding tool usually also moves linearly along the adjacently aligned edges of two workpieces to be joined together. The friction generated by this rotation heats and plasticizes the material at the weld zone. The plasticized material of two joining adjacent parts is fused together and thus creates a weld seam along their edges. As the tool rotates, a downward force is applied on the workpiece to sufficiently fuse the two pieces together. Deformation might occur when the rotating tool traverses abutting edges of lamellar segments or profiles since there is no support or joint underneath for the one-sided heat sink embodiment to counteract the previously mentioned down force. Therefore, the workpieces usually require a support from the side opposite the welding where the force is applied, a rear or down side, as, for example, is shown in FIG. 1a. Alternatively, the workpieces have a shape allowing the other, down or opposite part of the work piece to serve as a support to compensate for the rather substantial vertical forces applied during friction stir welding. It is known in the art to use friction stir welding for joining of two metal or plastic work pieces.
FSW is the most efficient bonding method providing high tensile strength of the joined parts while maintaining high thermal conductivity at the joint. However, when forming heat sink segments from lamellar or extruded profiles, the segments are typically arranged only by clamping. When the segment is formed by, for example, a press-fit connection, where a neighboring extrusions or profiles have interacting extensions on one side and grooves receiving those extensions on the other side, significant air gaps might exist between lamellar segments in those press-fit connections around extensions spaced within the grooves in non-weld areas, especially for a large scale heat sink. Such gaps can result in high spreading thermal resistance. Additionally, if these air gaps occur in the weld zone, they can create a defective weld that will contain voids. In addition, I-, U-, and S-shaped cross-sections, such as those shown in FIGS. 1b, 1c and 1d, need to include two end portions, which limits the variations of shapes of the final product and increases the weight of the heat sink.


Systems and methods for estimating engine faults are described. In one embodiment, the method includes the steps of obtaining measured engine quantities at a first operating condition, obtaining measured engine quantities at a second operating condition, and generating an estimated fault vector y based on the measured engine quantities obtained at the first and second operating conditions. Model-based values can also be obtained at the first and second operating conditions and used in connection with generating vector y.

The present invention relates generally to gas turbine engines, and more specifically, to estimating faults in such engines.
Gas turbine engines are used in aeronautical, marine, and industrial applications. Gradual wear resulting from repetitive cycles over the life of an engine, as well as assembly errors and incidental damage to hardware components, can cause faults in such engines. Hardware component damage may occur, for example, due to foreign object damage and extreme operating conditions. Engine efficiency and life are improved by detecting faults as quickly as possible and then performing needed repairs. Quickly detecting faults and performing needed repairs also facilitates avoiding cascading damage.
In aeronautical applications, gas path or performance related faults are typically detected using flight-to-flight trending of a few key parameters such as exhaust gas temperature. Changes in sensed parameters are identified between a current flight and a previous flight. If multiple parameters are trended, then the pattern in the changes may be sufficiently distinct to allow classification (i.e., diagnosis) as a specific fault. With flight-to-flight trending, data scatter may occur, and such data scatter may be of a same order of magnitude as the fault effects to be identified. Also, while sudden changes in a trended parameter indicate possible faults, such trending does not necessarily assist in identifying, or isolating, the fault.
Methods and systems for estimating engine faults are described. In one embodiment, the method includes the steps of obtaining measured engine quantities at a first operating condition, obtaining measured engine quantities at a second operating condition, and generating an estimated fault vector y based on the measured engine quantities obtained at the first and second operating conditions. Model-based values can also be obtained at the first and second operating conditions and used in connection with generating vector y.
The first and second operating conditions, in an exemplary embodiment, are similar. For example, and with a gas turbine engine used in an aeronautical application, the operating conditions are two cruise points in a single flight. Alternatively, the operating conditions are takeoff points in two separate flights. In another exemplary embodiment, the operating conditions are different. For example, the first operating condition is a takeoff point and the second operating condition is a cruise point.
The estimated fault vector y is generated in accordance with:
y=xR
where, x is a vector of size n where n is a number of sensors and model values, and R is a regressor matrix. The regressor matrix R is generated by simulating engines with no faults with random variations in engine quality, deterioration, sensor bias levels, and operating condition to obtain a first set of sensor readings, and simulating engines with several faults of random magnitude within pre-defined magnitude limits with random variations in engine quality, deterioration, sensor bias levels, and operating condition to obtain a second set of sensor readings.
The fault estimation systems and methods provide the advantage that by using inputs acquired during a single or two consecutive flights or cycles, a fault can be detected during the cycle in which it occurs, or a few cycles later.


A parallel processor is provided with a plurality of independently operable command units and a plurality of function units each connected to the command unit. A data unit, a register file, and a carry bit are shared such that the command and function units operate in parallel without any conflict. A priority scoreboard is provided to control the register file so that the command units operate independently according to the parallelism of a program, and detect and avoid a contention for a register according to the order of priority, making simultaneous execution of a plurality of commands possible, resulting in the increased process speed.

1. Field of the Invention
The present invention relates to parallel processing method and apparatus for use in processing information at high speeds.
2. Description of the Prior Art
A conventional parallel processor of this type, such as described by Carl Dobbs, Paul Reed, and Tommy Ng in "Supercomputing on Chip," VLSI SYSTEMS DESIGN, Vol. IX, No. 5, May 1988, pp. 24-33, is shown in FIG. 13. The parallel processor consists of an integer unit 501 for performing addition and subtraction of integers and a bit field process; a floating point unit 502 for multiplication of floating point numbers or integers; a floating point unit 503 for performing other floating point arithmetic operations and division of integers; an optional special function unit 504; a data unit 505 for reading and writing data in a memory; a register file 506 used by the above function units to perform an arithmetic operation; a scoreboard 507 for performing detection and avoidance of a contention for a register; a command unit 508 for fetching, decoding, and transferring a command to a function unit; a bus 509 for interconnecting the respective units to the register file; and a program counter 510 for controlling an address of the next command to be executed.
In operation, the command unit 508, which is divided into three pipelined stages; namely, fetch, decode, and transfer stages, completes a fetch in a clock cycle and passes the fetched command to the decode stage. The decode stage decodes part of the command and requests the scoreboard 507 to prefetch the necessary operand from the register file 506 for the function unit corresponding to the command. The scoreboard 507 has scoreboard bits corresponding to respective registers of the register file 506. The scoreboard bit is set while the register is installed or during data operation and is cleared when the data operation is completed. In response to a request, the scoreboard 507 checks the scoreboard bit and, if a scoreboard bit is set, waits until the scoreboard bit is cleared. Then, it issues a use permit to the command unit 508. When the operand necessary for execution of the command is fetched, the command is transferred to the function unit. Each function unit has several stages to execute the command using the prefetched operand.
In the above conventional parallel processor, however, only one command can be decoded in a clock cycle so that no more than one operation result can be obtained, resulting in the limited processing speed.

Parallel processing method and apparatus


A method and apparatus for routing and forwarding between virtual routers is described. A method in a single network element comprises peering a first virtual router to a second virtual router, wherein the first and second virtual routers have separate address spaces and separate routing tables, distributing a set of one or more routes from the first virtual router to the second virtual router, wherein a first of the set of routes identifies the first virtual as a next hop of the first route, said first route including a destination, and downloading to a set of one or more forwarding tables, the destination and the next hop.

1. Field of the Invention
The invention relates to the field of communication. More specifically, the invention relates to communication networks.
2. Description of Prior Art
The development of virtual routers within a single network element provided certain benefits and functionality unavailable with legacy routers. For example, a single network element with virtual routers could service multiple Internet Service Providers and/or corporations with the single network element.
FIG. 1 (Prior Art) is a diagram of a single network element with virtual routers. In FIG. 1, a network element 101 includes virtual routers VR-A 111, VR-B 113, and VR-C 115. Each of the virtual routers 111, 113, and 115 respectively receive traffic from ingress ports 103A-103C and respectively transmit traffic out of the egress ports 151A-151C as illustrated in FIG. 1. The virtual router VR-A 111 receives traffic 109A from the ingress port 103A and transmits the traffic 109A out of the egress port 151A. The virtual router VR-B 113 receives traffic 109B from the ingress port 103B and transmits the traffic 109B out of the egress port 151B. The virtual router VR-C 115 receives traffic 109C from the ingress port 103C and transmits the traffic 109C out of the egress port 151C.
Network elements that support virtual routers, performed inter-VR forwarding based on the forwarding scheme described (i.e., with standard interfaces). If VR-A 111 received a packet for transmission to VR-B 113, then the VR-A 111 looked up the next hop in its routing table, found an interface that was associated with the ingress port 103B, and forwarded the packet based on that interface.
Despite the advantage offered by virtual routers and the capability of a single network element to behave as multiple routers, the virtual routers within a single network element do not communicate routing and/or forwarding information as if separate routers.

Method and apparatus for routing and forwarding between virtual routers within a single network element


The present disclosure relates to a method, device and computer program product for executing a job in an application system. Here, the application system comprises a first processing device and a second processing device, and a first response speed of the first processing device being lower than a second response speed of the second processing device. In a method, a job request is received from a user of the application system, the job request specifying that the job is to be executed in the application system; a job type of the job is determined, the job type describing a requirement of the user on a response speed for executing the job; a target processing device is selected from the first processing device and the second processing device in accordance with determining that the job type relates to a high response speed; and the job is assigned to the selected target processing device, so that the job is executed by the target processing device. By means of the above method, a processing device for processing a job is selected based on the type of the job, and further processing devices in the application system may be dispatched more effectively. Furthermore, there is provided a corresponding device and computer program product.

With the development of application systems, various types of application systems have emerged. A user of an application system may perform various types of tasks in the application system. For example, regarding an application system for backup, a user of the application system may back up his/her own user application at different time points. Subsequently, in a backup job submitted to the application system, a backup copy may be transmitted to the application system. In another example, the user may further submit a recovery job to the application system, so that data that has been backed up may be retrieved from the application system for recovering the user system to the retrieved data.
Technical solutions have been proposed to deploy a dedicated processing device in an application system for assisting a general-purpose processing device and further increasing a speed of job execution. However, a workload of the dedicated processing device may not be stable, and sometimes may result in larger latency and further lead to processing inefficiency of the application system. Therefore, how to more effectively execute various jobs from users has become a focus of research.

Method, device, and computer program product for executing a job in an application system


A distraction frame for use with a surgical table, wherein the surgical table includes a base for positioning on a floor, the distraction frame including a table mount for fixation to the base of the surgical table; at least one horizontal strut mounted to the table mount; at least one vertical strut mounted to the at least one horizontal strut; and at least one distraction mechanism mounted to the at least one vertical strut, wherein the at least one distraction mechanism may be connected to a limb of a patient for applying a distraction force to the limb of the patient; wherein the table mount may transfer to the floor a force moment imposed on the table mount when the at least one distraction mechanism applies a distraction force to a limb of a patient.

When performing surgical procedures on the hip joint, it is common to distract the hip joint prior to the surgery in order to provide additional room within the hip joint during the surgery and in order to better present selected anatomy to the surgeon. This hip distraction is commonly achieved by applying a distraction force to the distal end of the leg of the patient. Currently, a surgical boot is placed on the foot and lower leg of the patient, the surgical boot is connected to a distraction frame, and then the distraction frame is used to apply a distraction force to the surgical boot, whereby to apply a distraction force to the leg of the patient, whereby to distract and position the hip joint.
The present invention is intended to provide a new and improved distraction frame for applying a distraction force to the leg of the patient so as to effect hip distraction and to allow for leg positioning.

Distraction frame for effecting hip distraction


In non-volatile semiconductor memory erasing method and device, in an erasing operation, a negative potential is applied to the gate of each memory cell (MC00 to MCmn), a positive potential which is equal or above a supply voltage Vcc from the external is applied to the channel of each memory cell, and the source and drain of each memory cell are connected to the ground potential through a high-resistant current path by a cell voltage control circuit, thereby obtaining a stable erasing characteristic in the erasing operation.

1. Field of the Invention
The present invention relates to an erasing method and an erasing device for a non-volatile semiconductor memory on the basis of a channel erasing system.
2. Description of the Prior Art
A gate/source erasing system and a channel erasing system are known erasing systems for a non-volatile semiconductor memory. The gate/source erasing system is disclosed in, for example, U.S. Pat. No. 5,077,691,. Briefly, according to the gate/source erasing system, an erasing operation is performed by applying a negative voltage to the gate of a memory cell while applying a positive voltage to the source of the memory cell and keeping the drain of the memory cell opened at the erasing time.
FIG. 13 shows the structure of a memory cell which is suitable for the gate/source erasing system. As shown in FIG. 13, drain D is formed on a P-type substrate P-sub on the basis of an N.sup.+ -diffusion layer, and source S is formed on the P-type substrate on the basis of an N.sup.- diffusion layer and an N.sup.+ diffusion layer. Floating gate FG and control gate CG are formed on this substrate. In the gate/source erasing type memory cell as mentioned above, an interband tunnel current flows from the source S to the substrate P-sub, and thus the current consumption is large. Further, a high withstanding voltage structure is indispensable to the source S, so that a special manufacturing step of forming the junction of the source diffusion layer deeply is necessary, and a restriction is imposed on minimum gate size.
The channel erasing system can solve the aforementioned problem of the gate/source erasing system, and FIG. 14 shows the structure of the memory cell which is suitable for the channel erasing system. In this memory, drain D based on an N.sup.+ diffusion layer and source S based on a N.sup.+ diffusion layer are formed on a P-type substrate P-sub. On the substrate are formed floating gate FG and control gate CG. In such a channel erasing type memory cell, no high electric field is applied to the source S, and thus the source S may be designed in the same structure as the drain D. Further, when the effective channel length Leff is set to the same as shown in FIG. 13, the dimension of each gate can be reduced, and thus this is effective to reduce the size of the memory cell.
Next, the channel erasing system will be briefly explained with reference to FIGS. 15 and 16.
FIG. 15 shows a system (hereinafter referred to as "first system") in which the drain and source of the memory cell are kept open and a negative voltage of -13 (V) is applied to the gate of the memory cell while a positive voltage of 5(V) is applied to the substrate portion. Such a system is disclosed in "A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode" of IEEE JOURNAL OF SOLID-STATE CIRCUITS, pp1547-1554 VOL. 27. NO. 11 NOVEMBER 1992.
FIG. 16 shows a system (hereinafter referred to as "second system") in which a positive voltage of 3(V) is applied to the drain and source of the memory cell, a negative voltage of -15(V) is applied to the gate of the memory cell and a positive voltage of 3(V) is applied to the substrate portion. Such a system is disclosed in "Low Voltage NVGTM: A New High Performance 3V/5V Flash Technology for Portable Computing and Telecommunications Applications" of IEEE TRANSACTION ON ELECTRON DEVICES, pp1510-1517, VOL. 43. NO.9 SEPTEMBER 1996.
In the first system, the problem of the gate/source erasing system is avoided, however, it has an unstable erasing characteristic because the source/drain of the memory cell is kept open and thus the source/drain may be set to a higher voltage than the substrate of the memory cell due to the fluctuation of a power source or the like.
On the other hand, in the second system, the problems of the gate/source erasing system and the first system are avoided. However, circuits for applying a voltage to the source and drain of the memory cell respectively are needed, and particularly the circuit for applying the voltage to the drain has a large overhead.

Erasing method and erasing device for non-volatile semiconductor memory


An apparatus measures the flow rate of a fluid. The apparatus comprises a fluidic oscillator provided with an elongate slot in a direction Oz and suitable for forming a jet of fluid that oscillates in a plane Oxy perpendicular to the Oz direction, and an obstacle located upstream from the slot to modify the distribution of speeds in the flow. The obstacle is in the flow at least in the central portion thereof and is implemented in the form of a substantially plane plate.

It has been known for many years that a fluidic oscillator can be used to measure the flow rate of a flowing fluid.
Document FR 2 663 417 discloses apparatus for measuring the flow rate of a fluid by making use of a fluidic oscillator. The apparatus described therein comprises, from an upstream end to a downstream end: a metal screen for modifying the speed distribution of the fluid flow; and a slot that is elongate in an Oz direction and suitable for forming a fluid jet that oscillates in an Oxy plane perpendicular to said direction and within an oscillation chamber.
The oscillation chamber has a plurality of obstacles including one situated facing the slot and two lateral obstacles serving to define recirculation flows centered on said obstacles and enabling the fluid jet to be switched from one lateral obstacle to the other. The fluid jet thus adopts "oscillating" motion which takes place at a frequency that is representative of the flow rate of the fluid.
The oscillation frequency of the jet is detected, for example, by means of pressure pickups situated at the extreme points of the sweep of the jet of fluid, and connected to known electronic systems.
The oscillation frequency of the jet is associated with the flow rate of the fluid by prior calibration.
The measurement apparatus presents curves of error as a function of flow rate that are acceptable, given the intended applications.
Nevertheless, the Assignee has observed that in the presence of fluids, such as gases, conveying impurities (particles, dust, . . . ), the impurities can accumulate in the openings of the metal screen, thereby disturbing the distribution of speeds in the flow between said screen and the slot of the fluidic oscillator.
That phenomenon therefore runs the risk of degrading the performance of the measurement apparatus quite quickly, and after the apparatus has been in operation for a few years the openings can become completely obstructed, thus making any flow rate measurement impracticable.
The above contamination phenomena are made worse when the fluid concerned is hot water.

Apparatus for measuring a fluid flow rate, the apparatus including at least one element for modifying the speed profile of said fluid flow


A medical device having a drug-eluting coating that includes a pharmaceutical compound or, more generally, a therapeutic material housed within pores of a zeolite carrier. The zeolite carrier has an open porous structure with reservoirs for holding the therapeutic material. The therapeutic material loaded zeolites may be suspended or dispersed within a bioerodible polymer matrix to provide controlled delivery of the therapeutic material. Zeolite drug carriers may have enhanced or optimally engineered pore sizes for a particular therapeutic material and release profile. Along with a therapeutic material, reservoirs of a zeolite drug delivery system may include a release agent. The release agent may be used to entrap the therapeutic material until such time as a triggering condition is met that prompts the release agent to activate and thereby release the therapeutic material from the zeolite reservoir.

Prosthetic devices, such as stents or grafts, may be implanted during interventional procedures such as balloon angioplasty to reduce the incidence of vessel restenosis. To improve device effectiveness, implantable medical devices may be coated with one or more therapeutic agents providing a mode of localized drug delivery. The therapeutic agents are typically intended to limit or prevent restenosis. For example, anti-thrombogenic agents such as heparin or clotting cascade IIb/IIIa inhibitors (e.g., abciximab and eptifibatide) may be coated on the stent, thereby diminishing thrombus formation. Such agents may effectively limit clot formation at or near the implanted device. Some anti-thrombogenic agents, however, may not be effective against intimal hyperplasia. Therefore, the implantable medical device may also be coated with anti-proliferative agents or other compounds to reduce excessive endothelial re-growth. Therapeutic agents provided as coating layers on implantable medical devices may effectively limit restenosis and reduce the need for repeated treatments. Therapeutic agents that provide other benefits, such as anti-plaque agents, e.g., naproxen and ibuprofen, also be may desirably coated onto an implantable medical device.
Several strategies have been developed for coating one or more therapeutic agents onto the surface of an implantable medical devices. Standard methods may include dip coating, spray coating, and chemical bonding. The therapeutic agent coating may be applied as a mixture, solution, or suspension of polymeric material and/or drugs dispersed in an organic vehicle or a solution or partial solution. However, the creation of an implantable medical device coating such that a drug may be delivered in a reliable but controlled manner presents many challenges, particularly the need to dissolve the drug inside the polymer carrier. Such drug dissolution often requires the use of solvents to dissolve the drug, and further solvents or co-solvents to dissolve the polymer. As such, finding the right solvents with the right polymer to deliver the right drug can be difficult to achieve. What is needed is a drug-eluting polymeric coating for an implantable medical device that does not require the use of co-solvents between the drug and the polymer carrier.
Hydrophilic polymeric coatings containing antibiotic zeolites known in the art may provide one solution to this problem. The antibiotic zeolites are created by an ion-exchange process wherein antibiotic metal ions; such as, silver, copper or zinc ions, are retained on zeolite particles through an ion exchange reaction. The antibiotic zeolites are dispersed in a hydrophilic polymer, for example, by high shear mixing, and the hydrophilic polymer is then dissolved in an organic solvent to provide a coating solution for a medical article. Such an antibiotic hydrophilic polymer coating is disclosed in U.S. Pat. No. 6,436,422 to Trogolo et al., which is incorporated by reference herein in its entirety. However, a need still exists for a drug-eluting polymeric coating for an implantable medical device with a controlled dosing profile that can be used to deliver a greater variety of therapeutic agents and that does not require the use of co-solvents between the therapeutic agent and the polymer carrier.

Medical device having coating with zeolite drug reservoirs


Powdered ferrous metal compositions are disclosed which provide for increased corrosion resistance through the admixing of powder aluminum containing compositions with standard ferrous metal compositions prior to forming the powder metal parts. In a preferred embodiment, the aluminum ranges is admixed as an FeAl alloy powder with the standard ferrous metal composition. The present invention further includes a powder metal ferrous part formed from the composition produced by a method including the steps of (i) providing a ferrous powder metal composition, (ii) admixing a powder aluminum containing composition with the ferrous composition to form a blended mixture, and (iii) forming a powder metal part from at least a portion of the blended mixture. In accordance with the present invention, the admixing of powder aluminum with powder steels increases the corrosion resistance of the resulting part formed from the mixture and allows the use in applications in which the parts are exposed to more aggressive corrosive environments than possible in prior art compositions.

The present invention relates to processes for producing ferrous metal compositions having increased corrosion resistance and the compositions and parts made therefrom. More particularly, the invention relates to the discovery that the introduction of powdered aluminum containing compositions into powder standard ferrous metal compositions results in modified compositions that have increased corrosion resistance.
Iron-chromium-nickel and iron-chromium alloys, specifically in the form of stainless steels, have found widespread use in industry due to the highly desirable mechanical and corrosion properties of stainless steels in comparison with conventional low alloy steels. The addition of substantial quantities of chromium to steels results in the formation of a highly protective chromium oxide layer on the surface of the steel that generally protects the underlying metal from corrosion and also provides an excellent surface finish. The addition of nickel enhances the mechanical properties of stainless steels by promoting an austenitic structure in the alloy.
There are, however, a number of problems associated with the use of chromium and nickel. One problem is that nickel is an expensive alloy element that greatly increases the cost of the steel. Another problem is that the majority of the world production of chromium comes from a small number of foreign sources, which means that the supply of chromium is subject to the uncertainties of foreign markets. Therefore, it would be beneficial to reduce the amount of chromium and nickel used in steels.
The protective chromium oxide layer on stainless steels substantially improves the corrosion resistance of the steels to attack by chloride ions compared to low alloy steels. Because of the low resistance of low alloy steels to chloride attack, stainless steels must be used in applications that do not require the enhanced mechanical properties of stainless steels. However, stainless steels do experience higher corrosion rates in marine and other chloride containing environments and exhibit reduced lifetime corrosion performance.
The corrosion resistance of stainless and low alloy steel parts in chloride containing environments is further diminished when powder metal (P/M) steels are used to form the parts. Powder metals are produced by exposing molten metal to cooling gas(es) and/or liquid(s) in such a way that the molten metal solidifies in a particulate powder. The process of producing the powder is known as atomization. An example of a conventional water atomization process is described in U.S. Pat. No. 2,956,304 issued to Batten. While the formability of powder metal provides increased versatility and allows for the production of machine parts that are not readily cast or machined from wrought metal, the corrosion resistance of powder metal parts is generally substantially lower than cast or wrought metal parts. The lower resistance has been thought to be associated with the increased porosity in the compact, which results in increased surface area exposed to the environment, and also related to the exposed microstructure of the powder metal part. As a result, the market for P/M stainless steel parts is only a fraction of the wrought and cast steel markets.
A variety of different metallurgical and mechanical methods have been developed to improve the corrosion resistance of powder metal stainless and low alloy steels. For instance, in U.S. Pat. Nos. 4,240,831, 4,314,849, 4,331,478 and 4,350,529 issued to Ro et al., the inventors disclose that the production of stainless steel powders using conventional water atomization processes, such as that of Batten, resulted in a powder stainless steel that is enhanced in SiO.sub.2 and depleted in chromium near the surface. The chromium depleted region near the surface of the powder resulted in increased susceptibility of the powder to corrosion. Ro et al. found that chromium depletion at the surface could be prevented in the atomization process if certain metals, "metal modifiers", are added to the molten metal prior to atomization. The metal modifiers were found to decrease the amount of silicon dioxide and increase the amount of chromium at the surface of the atomized alloy. The resultant parts formed from the alloy exhibited an improvement in the corrosion resistance over unmodified alloy parts. Ro found tin to be the preferred metal modifier, although other metals such as aluminum, lead, zinc, magnesium, and rare earth metals, were found to concentrate at the surface during atomization and reduce the surface concentration of silicon dioxide, but to a lesser extent than tin.
In U.S. Pat. No. 4,662,939 (the "'939" patent), Reinshagen disclosed a modified molded stainless steel composition, dubbed "Stainless Steel Plus.TM.", having improved corrosion resistance over the base stainless steel that could be prepared by mixing 8-16% of an alloy powder consisting of 2-30% tin and the remainder being either copper and/or nickel with the stainless steel powder prior to molding. However, in subsequent patents, U.S. Pat. No. 5,529,604 and 5,590,384 (the "'604 and '384" patents, respectively), Reinshagen has indicated that the compositions disclosed in the '939 patent grow upon sintering and, as a result, have had only limited acceptance.
In the '604 and '384 patents, Reinshagen discloses that tin could be alloyed with the stainless steel to produce a tin stainless steel powder, similar to Ro et al., which could then be further combined with the Sn-Cu-Ni powder of the '939 patent to provide modified stainless steel powders, named "Stainless Steel Ultra.TM." by the inventor. Powder metal parts formed by the modified stainless steel powder exhibited improved corrosion resistance over conventional stainless steel powder metal parts and do not swell during sintering like the Stainless Steel Plus.TM. parts. See also Reinshagen and Bockius, "Stainless Steel Based P/M Alloys With Improved Corrosion Resistance", a contribution to the 1995 International Conference on Powder Metallurgy and Particulate Materials, May 14-17, 1995, Seattle, Wash.
Other efforts have focused on providing a more tightly compacted powder metal to achieve properties closer to that of cast and wrought materials. Methods include the use of multiple press/sintering processing, including hot forming of the metal powder, varying the treatment conditions of the powder and incorporating powders having higher iron contents. For example, increasing the sintering temperature to more completely reduce the oxide layers on the atomized metal is suggested in "Improving Corrosion Resistance of Stainless Steel PM Parts" Metal Powder Report, Vol. 46, No. 9, p. 22-3 (September 1991). Similar recommendations are made by Reinshagen and Mason in "Improved Corrosion Resistant Stainless Steel Based P/M Alloys" presented at the 1992 Powder Metallurgy World Congress, June 21-26, San Francisco, Calif.
Despite the aforementioned compositional and process changes, powder metal parts have not achieved corrosion resistance that is comparable to cast and wrought parts. Consequently, the market for powder stainless and low alloy steel parts remains only a small percentage of the market for wrought and cast steel parts. As such, the need exists for powder metal compositions that provide increased corrosion resistance, especially with respect to chloride, for use in powder metal parts.

Powder ferrous metal compositions containing aluminum


An imaging lens includes, in order from an object side, a first lens having a positive refractive power and having a meniscus shape with a convex surface directed to the object side thereof, a second lens having a concave object-side surface and a third lens having a negative refractive power in a vicinity of an optical axis. Each of the second and third lenses has at least one aspheric surface. The following conditional expressions are satisfied:0.8<f1/f<1.2  (1)11<|f2/f|  (2)0.04<SA/Y<0.09  (3)TL/2Y<0.9  (4)where                SA denotes the amount of sag of the object-side surface of the second lens in a position where a principal ray passes the maximum image height,        Y denotes the maximum image height, and        TL denotes a distance from an object-side surface of the first lens to an image formation position.

1. Technical Field
The invention relates to a fixed-focus imaging lens that can be suitably mounted on a small-sized imaging apparatus such as (i) a digital camera using an imaging device such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), (ii) a camera using a silver halide film, and the like.
2. Description of the Related Art
In recent years, as permeation of personal computers in homes or the like, a digital still camera (hereinafter, referred to as a "digital camera") capable of inputting image information, such as photographed scenes, persons, or the like, to the personal computer have come into wide use rapidly. As cellular phones are sophisticated, module cameras (portable module cameras) for inputting images have been often mounted on the cellular phones.
In such an imaging apparatus, an imaging device such as a CCD or a CMOS is used. With the recent development in miniaturization of the imaging devices, compactness is requested for such imaging apparatus and an imaging lens mounted thereon. Concurrently, since the number of pixels of the imaging device also increases, the imaging lenses are requested to have higher resolution and higher performance.
JP 2004-302058 A (corresponding to US 2004/0190162 A), JP 2005-173319 A, JP 2005-227755 A and JP 2005-292235 A describe imaging lenses that has a three-lens configuration and that employs an aspheric lens surface, thereby achieving higher performance and compactness.
As described above, as recently miniaturization of the imaging device is further advanced and the number of pixels thereof further increases, particularly an imaging lens for a digital camera is requested to have higher resolution performance and a compact configuration. On the other hand, an imaging lens for a portable module camera has been primarily requested to be low in cost and compact in configuration. Recently, the number of pixels of an imaging device in a portable module camera also tends to increase. Thus, the imaging device in the portable module camera has been highly requested to have good performance.
It is therefore desired to develop a wide variety of lenses comprehensively improved in cost, image-formation performance and compactness. For example, it is desired to develop a low-cost and high-performance imaging lens having high performance with considering mounting it on a digital camera, while ensuring compactness for mounting on a portable module camera.
To meet these requests, for example, a lens configuration can be considered in which the number of lenses is three in order to secure compactness and low cost, and aspheric surfaces are used aggressively in order to secure high performance. In this case, the use of aspheric surfaces contributes to compactness and high performance. However, the aspheric surfaces are disadvantageous in manufacturing efficiency, and the cost may increase. It is, therefore, desired to take the manufacturing efficiency into consideration when the aspheric surfaces are used. The lenses described in the above listed documents have a three-lens configuration using aspheric surfaces. However, those lenses do not achieve a certain level of compatibility between good imaging performance and desirable compactness.


In a MOS type LSI comprising an n channel-open-drain-transistor capable of connecting with an analog IC driven by a high voltage, a surge breakdown voltage and a drain breakdown voltage of the open-drain-transistor is increased, and hence the reliability is increased. An n channel-open-drain-transistor includes a ring-shaped gate electrode and a drain region. A drain region is surrounded by a gate electrode. Drain region includes an n.sup.- region and an n.sup.+ region. An n channel MOS transistor includes a gate electrode and a drain region. Drain region includes an n.sup.- region and an n.sup.+ region. An impurity concentration of n.sup.- drain region of the n channel-open-drain-transistor is higher than an impurity concentration of n.sup.- drain region of the n channel MOS transistor.

1. Field of the Invention
The present invention relates generally to a semiconductor device such as a large scale integrated circuit device (LSI) and, more particularly, a semiconductor integrated circuit device having a field effect transistor driven by a low power supply voltage which can be interconnected to an analog IC (Integrated Circuit) (a linear IC) driven by a high power supply voltage. The present invention is particularly useful for a semiconductor device of a so-called CMOS (Complementary-Metal Oxide Semiconductor) type. The present invention also relates to a manufacturing method of such semiconductor devices.
2. Description of The Background Art
When the present invention is applied to an MOS type LSI which can be connected to an analog IC chip, the most preferable result can be obtained. The MOS type LSI has a logic circuit therein. FIG. 20 is a block diagram schematically showing an MOS type LSI connected to an analog IC. FIG. 21 is a plan view showing a planar arrangement of the MOS type LSI shown in FIG. 20. FIG. 22 is a sectional view taken along a line XXII--XXII in FIG. 21. A structure of a conventional MOS type LSI will be described hereinafter with reference to these figures.
Referring to FIG. 20, an MOS type LSI 100 is connected to an analog IC 200 with a pull up resistor R connected to a power supply voltage (12V) being interposed. MOS type LSI 100 has a pad 55 as a connecting terminal to analog IC 200. Pad 55 is connected to the drain of an n channel-open-drain-transistor 50. The n channel-open-drain-transistor is a transistor having a drain with an output terminal pad connected thereto. The gate of n channel-open-drain-transistor 50 receives a signal ("High" or "Low") from an internal logic circuit 80 through a CMOS inverter. The CMOS inverter is comprised of an n channel MOS transistor 60 and a p channel MOS transistor 70.
Referring to FIG. 21, n channel-open-drain-transistor 50 has a gate electrode 56, a source region 57 and a drain region 58. N channel MOS transistor 60 has a gate electrode 61, a source region 62 and a drain region 63. A p channel MOS transistor 70 has a gate electrode 71, a source region 72 and a drain region 73. Each transistor has a source region, a drain region and a gate electrode connected to an interconnection through contact holes ch.
Referring to FIG. 22, each of transistors 50, 60, 70 is formed in a p type silicon substrate 1. In p type silicon substrate 1, a p type well 2 and an n type well 3 are formed. n channel-open-drain-transistor 50 and n channel MOS transistor 60 are formed in p type well 2. p channel MOS transistor 70 is formed in n type well 3. p.sup.+ inversion preventing region 4 and a thick isolation oxide film 5 thereon are formed in order to electrically isolate transistors 50, 60, 70 from each other. A gate electrode of each of transistors is formed of a polycrystalline silicon layer 7 and a molybdenum silicon layer 8. Polycrystalline silicon layer 7 is formed on the surface of p type well 2 or n type well 3 with a gate oxide film 6 interposed. Source/drain regions of n channel-open-drain-transistor 50 and n channel MOS transistor 60 are comprised of an n.sup.- source/drain region 9 and an n.sup.+ source/drain region 10. A source/drain region of p channel MOS transistor 70 is comprised of a p.sup.+ source/drain region 22. An interlayer insulating layer 11 is formed to cover each of transistors 50, 60, 70. An interconnection layer 12 is provided to be in contact with each of the source/drain regions through each of the contact hole formed in interlayer insulating film 11.
An MOS type LSI structured as mentioned above will be described. Referring to FIG. 20, when a signal output from internal logic circuit 80 through a CMOS inverter is "High", a high voltage is applied to the gate of n channel-open-drain-transistor 50. At this time, n channel-open-drain-transistor 50 is turned on. Current flows from pad 55 to the drain of n channel-open-drain-transistor 50. At this time, a power supply voltage (12V) is distributed correspondingly to values of pull up resistor R and a resistor r of n channel-open-drain-transistor and transmitted to analog IC.
Conversely, when the signal output from internal logic circuit 80 through the CMOS inverter is "low", a low voltage is applied to the gate of n channel-open-drain-transistor 50, so that n channel-open-drain-transistor 50 is turned off. Current does not flow from pad 55 to the drain of n channel-open-drain-transistor 50. As a result, power supply voltage (12V) is transmitted to analog IC 200.
As described above, a drain breakdown voltage of n channel-open-drain-transistor 50 should be over 12V.
FIG. 25 includes a partial plan view (A) showing an enlargement of n channel-open-drain-transistor 50 or n channel MOS transistor 60, and a partial sectional view (B) showing a section taken along line B--B of the partial plan view (A). With reference to FIG. 25(A), drain region 58 (63) has an n.sup.+ impurity diffusion region 58a (63a) with its boundary region extended slightly outward as indicated by a dotted line. Therefore, n.sup.+ impurity diffusion region 58a (63a) overlaps with p.sup.+ inversion preventing region 4 as shown in FIG. 25(B). As a result, a drain breakdown voltage is reduced and determined by the overlapped portion.
In a conventional MOS type LSI, as shown in FIG. 22, n channel MOS transistor 60 connected to internal logic circuit 80 and n channel-open-drain-transistor 50 connected to pad 55 have the same structure. That is, n channel-open-drain-transistor 50 is structured to be driven by a power supply voltage of 5V, as n channel MOS transistor 60. This results in a problem that only a small margin in breakdown voltage specification is allowed for n channel-open-drain-transistor 50. For example, a surge breakdown voltage which is measured by capacitor charging method (one type of a surge breakdown testing method) on condition of 200 pF and 0.OMEGA. cannot reach .+-.300V or more.
FIG. 24 is a enlarged partial sectional view showing one portion of n channel MOS transistor 50 or 60. Polycrystalline silicon layer 7 and molybdenum silicide layer 8 are formed on gate oxide film 6. An oxide film 20 is formed on sidewalls of polycrystalline silicon layer 7 and molybdenum silicide layer 8 forming a gate electrode. Under a sidewall oxide film 20, n.sup.- source/drain region 9 is formed. N.sup.+ source/drain region 10 is formed to connect with n.sup.- source/drain region 9. In the structure shown in FIG. 24, sidewall oxide film 20 is formed of a film having fine step coverage such as a TEOS film (a silicon oxide film formed by a CVD method using Tetra-Ethyl-Ortho-Silicate as raw material). The TEOS film, however, has the property of holding a high density of trapped carriers therein, so that a problem exists that the aforementioned surge breakdown voltage of the n channel-open-drain-transistor decreases more.
Furthermore, the gate electrode has a two-layer structure comprised of polycrystalline silicon layer 7 and a molybdenum silicide layer 8. Because of a difference of etching speeds for the polycrystalline silicon layer and the molybdenum silicide layer, a side portion of polycrystalline silicon layer 7a forming a lower layer is frequently etched to a greater degree than molybdenum silicide layer 8 of an upper layer as shown in FIG. 23. Polycrystalline silicon layer 7a is, so-called, side-etched. Then, the surge breakdown voltage decreases even more.
N channel-open-drain-transistor 50 has a drain connected to pad 55. Pad 55 is connected to external analog IC 200 which is different from MOS type LSI 100. An external surge is directly applied through pad 55 to the drain of n channel-open-drain-transistor 50. Therefore, a surge breakdown voltage of n channel-open-drain-transistor 50 should be higher than a breakdown voltage of n channel MOS transistor 60 constituting the CMOS inverter or the n channel MOS transistor constituting internal logic circuit 80. However, each of the n channel MOS transistors constituting MOS type LSI 100 is formed on the same p type silicon substrate 1, that is, the same p type well 2. As a result, all n channel MOS transistors including n channel-open-drain-transistor 50 have the same breakdown voltage specification.
As a degree of integration of a semiconductor integrated circuit device becomes higher, transistors constituting internal logic circuit 80 are more and more miniaturized. Channel lengths of the miniaturized MOS transistors are becoming shorter. In order to obtain a predetermined drain breakdown voltage in an MOS transistor having such a short channel length, the MOS transistor has an LDD structure. For example, as shown in FIG. 22, n channel MOS transistor 50 or 60 has an LDD structure formed of n.sup.- source/drain region 9 and n.sup.+ source/drain region 10 as a source or a drain region. Also, as a measure to prevent a harmful effect by hot electrons generated in a field effect transistor having a short channel length, an impurity concentration of n.sup.- source/drain region 9 is restricted to a low value. Under the circumstances, a problem exists that it is difficult for a drain breakdown voltage and a surge breakdown voltage of an n channel-open-drain-transistor connected to an external IC to satisfy a prescribed specification.

Semiconductor device interconnected to analog IC driven by high voltage


This light absorbing device includes: a light reflecting layer; a dielectric layer disposed on the light reflecting layer; and a plurality of metal nanostructures disposed on the dielectric layer. A portion of each of the plurality of metal nanostructures is buried in the dielectric layer and another portion thereof is exposed to the outside.

The probability of occurrence of interaction between light and matter is low. As such, various attempts have been made for causing interaction between light and matter. For example, a laser beam is used as light for the purpose of improving the sensitivity of biosensors, the resolution of a bioimaging image, and the like. In addition, highly densely arranged molecules, quantum dots and the like for light absorption, a thickened semiconductors for light absorption and the like are used for the purpose of improving the efficiency of the light energy conversion in a solar cell, artificial photosynthesis and the like. However, such methods may increase the raw material cost, and may reduction in the charge splitting efficiency due to increase in the thickness depending on the type of semiconductor.
Under such circumstances, as a method of increasing the probability of interaction between light and matter, metal nanostructures that exhibit localized surface plasmon resonance, micro resonators that confine light, micro-nanostructures such as photonic crystals have attracted attention. In particular, devices utilizing localized surface plasmon resonance, which can efficiency collect light with only two-dimensionally disposed metal nanostructures (metal nanoparticles), have been actively researched for the last decades. In recent years, it has been reported that, with a plurality of metal nanostructures disposed on an oxide semiconductor substrate, not only amplification of light, but also promotion of electron injection from the metal to the semiconductor can be achieved, and the effect of plasmons can be exerted also on chemical reactions such as the generation of hydrogen and synthesis of ammonia.
However, light cannot be completely collected with the metal nanostructures disposed on the surface of the semiconductor substrate. Usually, the amount of light that can be absorbed with the metal nanostructures disposed on the surface of the semiconductor substrate alone is approximately 50% at most. Moreover, in this case, only light of a specific wavelength that indicates plasmon resonance can be absorbed. It has also been proposed to increase the light absorption amount by forming the semiconductor into a three-dimensional shape such as a nanorod structure, a nanotube structure, and a honeycomb structure so as to support the metal nanostructure therein. This method, however, effectively utilizes only the light of a specific wavelength based on plasmon resonance, and cannot achieve absorption of light of a wide wavelength and increase of internal quantum yield although the apparent light-energy conversion efficiency is increased.
As a light absorbing device capable of absorbing light of a wide wavelength, a light absorbing device called a perfect absorber or a super absorber in which a dielectric layer is formed on a thin gold film and a plurality of metal nanostructures are disposed thereon or therein has been reported (see NPL 1). It is believed that in this light absorbing device, in the gold thin film located on the lower side under the metal nanostructures with the dielectric layer directly below the metal nanostructures therebetween, a plasmon having a phase opposite to that of the plasmon generated in the metal nanostructure is formed as a mirror image, and a strong near-field interaction called "image dipole interaction" occurs between the plasmon in the gold thin film and the plasmon in the metal nanostructure, thus achieving absorption of light of a wide wavelength (see NPL 2). Since this light absorbing device is intended only for light absorption, a metal nanostructure is placed on the dielectric layer or is completely embedded in the dielectric layer. In addition, since this light absorbing device is designed on the assumption of utilization of the image dipole interaction, it has been believed that the thickness of the dielectric layer is required to be reduced.

Light absorbing device, manufacturing method thereof, and photoelectrode

National University Corporation Hokkaido University