The present invention is concerning to a fixing unit position-adjusting apparatus including: a first member configured to include a positioning portion that is formed on a lateral surface of the first member, the positioning portion being engaged with a positioning portion of a main body so that the first member is mounted on the main body in a manner positionable in a left and right direction; and a second member configured to include a reference pin insertion portion that is formed to receive insertion of a reference pin of the main body, the second member being assembled with the first member.

1. Field of the Invention
The present invention relates to a fixing unit position-adjusting apparatus for positioning a fixing unit which fixes a toner image on a record medium, such as a recording paper sheet, with respect to a main body of an image forming apparatus, and to an image forming apparatus.
2. Description of the Related Art
Image forming apparatuses which form an image on a recording paper sheet with an electrophotographic system have conventionally been used as copying machines, facsimile machines, and printers. Such an electrophotographic image forming apparatus charges a photoreceptor with a charging apparatus, and then forms an electrostatic latent image on the surface of the photoreceptor through such operation as optical writing performed in accordance with a document image or image information. The electrostatic latent image is then developed by a developing apparatus into a toner image with use of a toner. The toner image that is a visible image is transferred onto a recording paper sheet that is a recording medium. The recording paper sheet is then heat-pressurized by a fixing unit so that the toner image is fixed onto the recording paper sheet. Thus, copied sheets and printed sheets are obtained.
One example of the fixing unit for use in image forming apparatuses is a roller-type fixing unit made up of a heating roller having a heat source and a pressure roller that rotates in contact with the heating roller. The roller-type fixing unit applies heat and pressure to a recording paper sheet, which has been conveyed to between the heating roller and the pressure roller, to fix a toner image thereon. Another example is a belt-type fixing unit having an endless fixing belt stretched over between the heating roller and the fixing roller. The belt-type fixing unit applies heat and pressure to a recording paper sheet, which has been conveyed to between the fixing belt and the pressure roller, to fix a toner image thereon.
Image forming apparatuses are required to support a wide variety of recording paper sheets, ranging from extra large-size paper sheets that are one size larger than standardized sizes to small postcard sheets with a relatively small size as well as from super-thin paper sheets to super-thick paper sheets. At the same time, high productivity and high image quality are also required. However, it was difficult to satisfy both conveying performance and image quality for the recording paper sheets.
When the positioning accuracy of the fixing unit with respect to the recording paper sheets are poor, the recording paper sheets may enter into the fixing unit with a displaced position, which causes distorted images, generation of wrinkles, edges of the recording paper sheets being folded, and occurrence of paper jam. In such circumstances, enhanced positioning accuracy of the fixing unit is required. In response to such requirements, an adjustment mechanism is used, that adjusts a reference pin of the fixing unit in a conveyance direction.
In one example, the adjustment mechanism is adapted to fix the position of a reference pin on the rear side of the fixing unit while adjusting the position of a reference pin on the near side of the fixing unit in the conveyance direction so as to optimize the parallelism of the fixing unit with respect to the recording paper sheets.
Japanese Laid-open Patent Publication No. 2004-117395 discloses an image forming apparatus including a retract drive means for use in retracting a fixing unit into a main body of the image forming apparatus so as to set the fixing unit in the image forming apparatus. The retract drive means slides the fixing unit in a fixing unit insertion direction so that the fixing unit is retracted to and positioned at a proper position.
However, when the adjustment mechanism is provided, a parts count increases as a plurality of component members need to be added. This causes a problem of a complicated configuration of the apparatus. Similarly, in the case of providing the retract drive means described in Japanese Laid-open Patent Publication No. 2004-117395, the parts count increases as a structure for sliding the fixing unit is needed. This also causes the problem of the complicated configuration of the apparatus.
In view of the above-mentioned conventional art, there is need to provide a fixing unit position-adjusting apparatus which can position the fixing unit with a simple configuration and which can optimize the parallelism of the fixing unit with respect to recording paper sheets that enter into the fixing unit.

Fixing unit position-adjusting apparatus and image forming apparatus


The present invention relates to novel complexes of major histocompability complex (MHC) molecules and uses of such complexes. In one aspect, the invention relates to loaded MHC complexes that include at least one MHC molecule with a peptide-binding groove and a presenting peptide non-covalently linked to the MHC protein. In another aspect, the invention features single chain MHC class II peptide fusion complexes with a presenting peptide covalently linked to the peptide binding grove of the complex. MHC complexes of the invention are useful for a variety of applications including: 1) in vitro screens for identification and isolation of peptides that modulate activity of selected T cells, including peptides that are T cell receptor antagonists and partial agonists, and 2) methods for suppressing or inducing an immune response in a mammal.

1. Field of the Invention
The present invention relates to novel complexes of major histocompability complex (MHC) molecules and uses of such complexes. For example, in one aspect, the invention relates to empty MHC complexes that contain a MHC molecule with a peptide-binding groove and a presenting peptide non-covalently linked to the MHC protein. In another aspect, the invention relates to MHC class II-peptide fusion complexes which include a single chain MHC class II molecule and a presenting peptide covalently linked to the peptide binding groove of the MHC protein. MHC complexes of the invention are useful for a variety of applications including in vitro screens for identification and isolation of peptides that modulate activity of T cells.
2. Background
Antigen-specific T cell responses are invoked by antigenic peptides bound to the binding groove or cleft of major histocompatibility complex (MHC) glycoproteins as part of the mechanism of the immune system to identify and respond to foreign antigens. The bound antigenic peptides interact with T cell receptors and thereby modulate an immune response. The antigenic peptides are bound by non-covalent means to particular "binding pockets" comprised of polymorphic residues of the MHC protein's binding groove.
MHC class II molecules are heterodimeric glycoproteins consisting of α and β chains. The α1 and β1 domains of these molecules fold together to form a peptide binding grove. Antigenic peptides bind the MHC molecule through interaction between anchor amino acids on the peptide and the α1 and β1 domains. Crystal structure of human class II HLA-DR1 complex with an influenza virus peptide indicate that the N- and C-terminal ends of the bound peptide extend out of the binding groove such that the C-terminus of the peptide is proximal to the N-terminus of the β chain [J. Brown et al., Nature, 364:33–39 (1993); L. Stern et al., Nature, 368:215–221 (1994)]. MHC class I molecules have different domain organizations than MHC class II molecules, but generally similar structure with a peptide binding site or groove that is distal to membrane domains [see, e.g., A. Rudensky et al., Nature, 353:622–626 (1991)]. See also U.S. Pat. Nos. 5,284,935; 5,260,422; 5,194,425; 5,130,297; and WO 92/18150 and WO 93/10220 for discussions of MHC molecules.
The α and β chain transmembrane domains play an important role in the assembly and/or intracellular transport of MHC molecules. For example, amino acid changes in the TM domains can result in defective MHC molecules [P. Cosson et al., Science, 258:659 (1992); W. Wade et al., Immunology, 32:433 (1995); H. Kozono et al., Nature, 369:151 (1994)]. The α and β chain transmembrane and cytoplasmic domains have been disclosed [(see e.g., Brown, supra and references therein)].
MHC molecules complexed with antigenic peptides can induce selective immunosuppression by several different mechanisms [see, e.g., J. Guery et al., Critical Reviews in Immunology, 13(3/4):195–206 (1993)].
More specifically, it has been reported that peptide-MHC complexes on the surface of antigen presenting cells will only induce clonal expansion of a T cell line specific for the MHC bound peptide if the antigen presenting cells also deliver co-stimulatory signals. One proposed approach takes advantage of this requirement for T cell activation and reports inhibition of T cell development by interaction with the antigenic peptide bound to the MHC molecule in the absence of co-stimulatory signals [see M. Nicolle et al., J. Clin. Invest., 93:1361–1369 (1994); and S. Sharma et al., Proc. Natl. Acad. Sci. USA, 88:11465–11469 (1991)].
Another proposed approach inhibits T cell development with MHC molecules that contain a bound peptide that is an antagonist or partial agonist to a T cell receptor (TcR) [see B. Evavold et al., Immunology Today, 14(12):602–609 (1993)].
Modifications of the antigenic peptides bound to T cell receptors have been attempted to examine residues responsible for specific T cell responses. Determination of such "activating" amino acids of the antigenic peptides could provide insight of suitable sequence of a TcR partial agonist or antagonist. See Evavold, B. et al., supra.
It also has been speculated that new vaccines might be developed based on determination of the nature of various antigenic peptides bound to MHC molecules [see R. Chicz et al., Immunology Today, 15(4):155–160 (1994)].


A flexible sensor is disposed in a power tool. The flexible sensor has an electrical resistance that varies based on a radius of curvature of the flexible sensor. A trigger partially disposed in the power tool, operates to apply a bending force at an engagement point on the flexible sensor to bend the flexible sensor and alter the radius of curvature. A controller outputs an electrical signal to the power tool based on the electrical resistance to control a function of the power tool.

This section provides background information related to the present disclosure which is not necessarily prior art.
Trigger assemblies are used to control functions of power tools. Existing trigger assemblies can include a variety of sensing devices to translate the movement of the trigger into control of the power tool. The trigger assemblies are often bulky due to the sensing devices. The size and shapes of the trigger assemblies hinder improvement to ergonomic aspects of the design of the power tool. Furthermore, existing trigger assemblies provide limited, linear control and control only one function of the power tool at a time. Therefore, a user of the power tool is required to use one hand to activate the trigger and another hand to change the function of the trigger. Productivity of the user decreases due to delays from switching the tool functionality and uncomfortable ergonomics.

Trigger assembly including a flexible bend sensor


A mother glass panel for manufacturing a plurality of liquid crystal displays (LCD) includes a first substrate; a second substrate attached to the first substrate, wherein column spacers are disposed between the first and second substrates to form cell gaps; and a liquid crystal layer interposed between the first substrate and the second substrate, wherein, the mother glass panel defines a plurality of liquid crystal display regions and at least two of the liquid crystal display regions have different cell gaps.

1. Field of the Invention
The present invention relates to a liquid crystal display device (LCD), and more particularly, to an LCD capable of securing a wide viewing angle by forming a plurality of liquid crystal cells having different liquid crystal cell sizes and different cell gaps over one mother glass.
2. Description of the Related Art
Traditionally, a cathode ray tube (CRT) has been used as an information display device because of advantageous characteristics such as better image quality on a screen and lower price. However, due to the poor portability of the CRT because of its size and weight, liquid crystal display devices (LCDs) have been actively developed in recent years. The LCD devices meet the demand of lightweight and miniaturized size. Furthermore, the LCD devices include more powerful performances, for example, micronization and low power consumption or the like, to overcome the disadvantages of the CRT. Thus, the LCD devices gained popularly as the mainstream information processing apparatuses of today.
The LCD includes a thin film transistor (TFT) and a pixel electrode formed on a substrate (i.e., TFT substrate), and a color filter substrate where a red, a green, and a blue color filters are formed. The TFT acts as a switching device. The LCD further includes a liquid crystal film interposed between the TFT substrate and the color filter substrate, thereafter two substrates are attached to each other. A plurality of liquid crystal cells having the same cell region are formed over a mother glass. In addition, a multi mode on glass (MMG) model LCD has been developed, in which the liquid crystal cells having different sizes are formed on the single mother glass.
FIG. 1 is a schematic view illustrating a related art MMG model LCD. As shown in FIG. 1, liquid crystal cells having cell regions I and II with different sizes are formed on a mother glass 10. The two substrates, the TFT substrate and the color filter substrate, are attached to each other in these regions. A first cell region I includes a large-sized liquid crystal cell having a size of 20 inches or more, whereas a second cell II includes a smaller-sized liquid crystal cell having a size of 15 inches or less. Since the liquid crystal cells having the cell regions I and II are formed simultaneously over one mother glass 10 in the MMG model, the liquid crystal panels of various sizes may be manufactured through one process. In FIG. 1, each capital letter H in the liquid crystal cells denotes the cell gap and it is understood that all of the liquid crystal cells have the same cell gap H regardless of the cell size according to the related art MMG model LCD.
FIG. 2A is a schematic view illustrating a location where a column spacer is formed in a pixel region according to the related art MMG model LCD. FIG. 2B is a cross-sectional view taken along line III-III′ of FIG. 2A. As shown in FIG. 2A, a gate line 21 is arranged in a horizontal direction crossing a data line 23 to define the pixel region, and a pixel electrode 29 is arranged in the pixel region. In addition, a TFT (i.e., a switching device) is formed at an intersection of the gate line 21 and the data line 23.
A column spacer 25 is formed over the gate line 21 to maintain a predetermined cell gap, or alternatively positioned over the gate line 21 to maintain the predetermined cell gap when attaching the color filter substrate to the TFT substrate. The column spacer 25 may be formed by patterning, on the TFT substrate or the color filter substrate. The region where the column spacer 25 is formed or positioned over the gate line 21 is a blocking region.
As shown in FIG. 2B, the gate line 21, a gate insulating layer 12 and a passivation layer 9 are formed over a first insulating substrate 11b in sequence. A reference numeral 29 denotes a pixel electrode. Over the column spacer 25, a color filter substrate including a black matrix 4, a color filter layer 5 and a common electrode 6 is formed over a second insulating substrate 11a. The column spacer 25 is placed over the gate line 21 (i.e., the blocking region of the TFT substrate) and under the black matrix 4 (i.e., the blocking region of the color filter substrate) to maintain the cell gap between the two insulating substrates 11a and 11b.
FIG. 3 is a cross-sectional view illustrating the cell gap of two liquid crystal cells in the related art MMG model LCD. Referring to FIG. 3, when the column spacer 25 is formed in a predetermined shape as illustrated in FIGS. 2A and 2B, the height of cell gap in the first cell region I and II are equal. Accordingly, when the liquid crystal cells having different sizes from one another are formed as in the related art MMG model, the liquid crystal panels with various sizes may be manufactured through single process.
However, as illustrated in FIG. 3, since the cell gaps of the all liquid crystal cells are identically formed regardless of resolution or size of each cell, it is difficult to manufacture the LCD having various viewing angles. For example, after cutting the liquid crystal cells from the related art MMG model mother glass, a wide view polarizer must be attached to secure a wide viewing angle. Thus, the wide view polarizer plays a major role in securing the wide viewing angle that corresponds to a retardation value And of the liquid crystal cell.
However, if all the liquid crystal cells having different resolution and sizes are formed such that they have the same cell gap regardless of the cell size or the like, all the retardation values become equal to one another. As a result, all the liquid crystal cells have the same viewing angle regardless of their size or the like. Therefore, various-sized liquid crystal cells cannot be formed using one glass substrate to secure an optimized viewing angle in each liquid crystal cell.

Liquid crystal display device and method for manufacturing the same


Apparatus 10 discloses a stackable extension sleeve for a coat hanger 22. The stackable extension sleeve is comprised of a unitary body having a curvilinear top surface 26 sloping down from a central aperture 14 with a back wall 28 extending to the base 30 of the opposing ends and a front triangular-shaped skirt 32 having a slot 16 in communication with the aperture. The bottom edge 30 of the extension sleeve forms a horizontal perimeter whereby the extension sleeve can stand unaided and stacked one upon another.

1. Field of the Invention
The present invention relates generally to apparel apparatus and, more specifically, to a stackable extension sleeve for a coat hanger. The stackable extension sleeve is comprised of a unitary body having a curvilinear top surface sloping down from a central aperture with a back wall extending to the base of the opposing ends and a front triangular-shaped skirt having a slot in communication with said aperture. The bottom edge of the extension sleeve forms a horizontal perimeter whereby the extension sleeve can stand unaided and stacked one upon another.
The present invention also provides for additional elements in the form of means for positioning the extension sleeve on a coat hanger and means for aiding in the retention of a garment once placed on said extension sleeve.
Serving as means for positioning the extension sleeve, the present invention provides a plurality of wedge-like projections depending from the underside of the top surface having a wedge bottom surface with the opposing ends angularly displaced. In the preferred embodiment, the angularity extends to its deepest point toward the back wall causing the sleeve back wall to substantially engage the provided hanger. Additionally, the plurality of wedges can be formed with the deepest end toward the front wall or by reversing every other wedge-angularity would essentially cause the coat hanger to reside between the sleeve's front and back wall.
In lieu of or in addition to, the present invention provides for aiding in the retention of a garment once placed on said extension sleeve by incorporating a frictional material covering the top surface in whole or in part thereby preventing casual displacement of the garment when place over the extension sleeve and user provided hanger.
2. Description of the Prior Art
There are other sleeve-like devices designed for coat hangers. Typical of these is U.S. Pat. No. 779,062 issued to Beatty on Jan. 5, 1905.
Another patent was issued to Batts on Dec. 24, 1929 as U.S. Pat. No. 1,740,566. Yet another U.S. Pat. No. 2,353,839 was issued to McFall on Jul. 18, 1944 and still yet another was issued on May 6, 1947 to Samann as U.S. Pat. No. 2,420,101.
Another patent was issued to Landers on Jan. 26, 1965 as U.S. Pat. No. 3,167,224. Yet another U.S. Pat. No. 3,301,447 was issued to Felton on Jan. 31, 1967. Another was issued to Tymoszek on Apr. 30, 1974 as U.S. Pat. No. 3,807,609 and still yet another was issued on Apr. 21, 1987 to Nash as U.S. Pat. No. 4,658,997.
Another patent was issued to Murphy et al. on Feb. 21, 1995 as U.S. Pat. No. 5,390,835. Yet another U.S. Pat. No. 5,718,362 was issued to Silverman on Feb. 17, 1998. Another was issued to Murray on Jan. 11, 2000 as U.S. Pat. No. 6,012,620 and still yet another was issued on Dec. 31, 2002 to McCool as U.S. Pat. No. 6,499,636.
Another patent was issued to Bastani, et al. on Dec. 18, 1995 as CA2,126,139 and still yet another was issued on Oct. 29, 2003 to Ball as U.K. Patent No. GB2387952.


Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.

1. Technical Field
Methods and example embodiments described herein are generally directed to interconnect architecture, and more specifically, to network on chip system interconnect architecture.
2. Related Art
The number of components on a chip is rapidly growing due to increasing levels of integration, system complexity and shrinking transistor geometry. Complex System-on-Chips (SoCs) may involve a variety of components e.g., processor cores, DSPs, hardware accelerators, memory and I/O, while Chip Multi-Processors (CMPs) may involve a large number of homogenous processor cores, memory and I/O subsystems. In both systems the on-chip interconnect plays a key role in providing high-performance communication between the various components. Due to scalability limitations of traditional buses and crossbar based interconnects, Network-on-Chip (NoC) has emerged as a paradigm to interconnect a large number of components on the chip. NoC is a global shared communication infrastructure made up of several routing nodes interconnected with each other using point-to-point physical links. Messages are injected by the source and are routed from the source router to the destination over multiple intermediate routers and physical links. The destination router then ejects the message and provides it to the destination. For the remainder of the document, terms 'components', 'blocks' or 'cores' will be used interchangeably to refer to the various system components which are interconnected using a NoC. Without loss of generalization, the system with multiple interconnected components will itself be referred to as 'multi-core system'.
There are several possible topologies in which the routers can connect to one another to create the system network. Bi-directional rings (as shown in FIG. 1(a)) and 2-D mesh (as shown in FIG. 1(b)) are examples of topologies in the related art.
Packets are message transport units for intercommunication between various components. Routing involves identifying a path which is a set of routers and physical links of the network over which packets are sent from a source to a destination. Components are connected to one or multiple ports of one or multiple routers; with each such port having a unique ID. Packets carry the destination's router and port ID for use by the intermediate routers to route the packet to the destination component.
Examples of routing techniques include deterministic routing, which involves choosing the same path from A to B for every packet. This form of routing is independent of the state of the network and does not load balance across path diversities which might exist in the underlying network. However, deterministic routing is simple to implement in hardware, maintains packet ordering and easy to make free of network level deadlocks. Shortest path routing minimizes the latency as it reduces the number of hops from the source to destination. For this reason, the shortest path is also the lowest power path for communication between the two components. Dimension-order routing is a form of deterministic shortest path routing in 2D mesh networks.
FIG. 2 illustrates an example of XY routing in a two dimensional mesh. More specifically, FIG. 2 illustrates XY routing from node '34' to node '00'. In the example of FIG. 2, each component is connected to only one port of one router. A packet is first routed in the X dimension till it reaches node '04' where the x dimension is same as destination. The packet is next routed in the Y dimension until it reaches the destination.
Source routing and routing using tables are other routing options used in NoC. Adaptive routing can dynamically change the path taken between two points on the network based on the state of the network. This form of routing may be complex to analyze and implement and is therefore rarely used in practice.
Software applications running on large multi-core systems can generate complex inter-communication messages between the various blocks. Such complex, concurrent, multi-hop communication between the blocks can result in deadlock situations on the interconnect. Deadlock occurs in a network when messages are unable to make progress to their destination because they are waiting on one another to free up resources (e.g. at buffers and channels). Deadlocks due to blocked buffers can quickly spread over the entire network, which may paralyze further operation of the system. Deadlocks can broadly be classified into network level deadlocks and protocol level deadlocks.
Deadlock is possible within a network if there are cyclic dependencies between the channels in the network. FIG. 3 illustrates an example of network level deadlock. In the example of FIG. 3, starting at a state with all buffers empty, the blocks initiate the message transfer of A→C, B→D, C→A and D→B simultaneously. Each block takes hold of its outgoing channel and transmits the message toward its destination. In the example of FIG. 3, each channel can hold only one message at a time. From this point on, each channel waits on the next channel to move the message further. There is a cyclic dependency in the wait graph and the network becomes deadlocked. Such network layer deadlock or low-level deadlocks can be avoided by construction using deadlock free routing or virtualization of paths.
Network end points may not be ideal sinks, i.e. they may not consume all incoming packets until some of the currently outstanding packets are processed. If a new packet needs to be transmitted during the processing of an outstanding packet, a dependency may be created between the NoC ejection and injection channels of the module. The dependency may become cyclic based upon the message sequence, position of components and routes taken by various messages. If the deadlock is caused by dependencies external to the network layer, this is called a high-level, protocol or an application level deadlock. In related art systems, most high level tasks involve a message flow between multiple modules on the NoC in a specific sequence. Such a multi-point sequence of intercommunication may introduce complex dependencies resulting in protocol level deadlock. The underlying cause of deadlock remains the channel dependency cycle introduced by the inter-dependent messages between multiple components. Independent messages from one end point to another on the network will not cause protocol level deadlocks; however, depending on the routing of such messages on the network, network level deadlocks are still possible in the system.
FIGS. 4(a), 4(b) and FIGS. 5(a) to 5(c) illustrate an example of protocol level deadlock. Consider an example of a three central processing unit (CPU) system connected to memory and cache controller through a crossbar. The cache controller's interface to the interconnect has a single First-In-First-Out (FIFO) buffer which can hold a maximum of three messages. Internally, the cache controller can process up to two requests simultaneously (and therefore process up to two outstanding miss requests to the memory).
At FIG. 4(a), all three CPUs send read requests to the cache controller.
At FIG. 4(b), read requests are queued in an input buffer to the cache controller from the crossbar.
At FIG. 5(a), the cache controller accepts two requests '1' and '2' from input buffer while the third request '3' remains in the input buffer. '1' and '2' have a read miss in the cache, which in turn issues miss refill requests 'm1', 'm2' to the memory
At FIG. 5(b), the memory returns refill data 'd1', 'd2'. This data gets queued behind '3' in the cache controller's input buffer.
At FIG. 5(c), the cache controller waits for refill data for the outstanding requests before accepting new request '3'. However the refill data is blocked behind this request '3'. The system is therefore deadlocked.
In this system, deadlock avoidance can be achieved by provisioning additional buffer space in the system, or using multiple physical or virtual networks for different message types. In general, deadlock is avoided by manually 1) interpreting the intercommunication message sequence and dependencies, 2) then allocating sufficient buffers and virtual and/or physical channels and 3) assigning various messages in the sequence the appropriate channel.
In large scale networks such as the internet, deadlocks are of a lesser concern. Mechanisms such as congestion detection, timeouts, packet drops, acknowledgment and retransmission provide deadlock resolution. However such complex mechanisms are too expensive in terms of power, area and speed to implement on interconnection networks where the primary demands are low latency and high performance. In such systems, deadlock avoidance becomes a critical architectural requirement.

Automatic construction of deadlock free interconnects


A method and apparatus for digitizing CCD-data, in which an A/D-converter is controlled such that the analog data are evaluated at the correct timings. Instead of delaying one of the clock signals, the analog data from the CCD is delayed by an analog delay circuit such as a low-pass filter. This makes it possible to adjust the delay time more easily, accurately and reliably.

1. Technical Field of the Invention
The invention relates to a method and a system for digitizing analog data. More particularly, the invention relates to a method and system for digitizing data that have been generated by an image sensor including a charge coupled device (CCD), a MOS-imager which is also known as a "charge injection device", and the like.
2. Description of Related Art
Charge coupled devices usually include a large number of light sensitive cells which generate and hold electric charges in response to light incident thereupon. The charges accumulated in each cell during a certain integration time are then transferred to one or more outputs of the CCD and are converted into electric voltages under the control of and in synchronism with a clock signal.
The analog data obtained in this way at the output of the CCD are supplied to an A/D-converter (ADC) via a conditioning circuit in which the offset and the gain factor are adapted to the input characteristics of the ADC.
A block diagram of a conventional CCD system of this type is illustrated in FIG. 3A. A CCD-array 10 supplies CCD-data V.sub.ccd to the conditioning circuit 12 the output of which is connected to the data input of ADC 14. In this example, the CCD-array is of a type which is controlled by a clock signal PHI, the inverted clock signal PHIn and a reset signal RS.
The waveforms of the signals V.sub.ccd, PHI and RS are shown in FIG. 3B. The signals PHI and PHIn serve as transport clock pulses by which the charges accumulated in the CCD cells are shifted through analog shift registers to the output port of the CCD-array which operates as a charge/voltage converter. The signal RS provides reset pulses for this charge/voltage converter. When the converter has been reset in the "low" period of the signal RS, the output port assumes a voltage V.sub.os which corresponds to a CCD cell which has not been exposed to light. At the subsequent transition of the signals PHI and PHIn, the next charge quantity is transferred to the output port and converted into a voltage V.sub.out which represents the amount of light that has been received by the corresponding CCD cell. This voltage V.sub.out has to be converted into digital data by the ADC 14. Accordingly, the ADC has to be controlled by an appropriate converter clock signal CONV in such a manner that the voltage of the signal V.sub.ccd is sampled and converted at a time t.sub.0 within the period in which this signal is valid, i.e. has the value V.sub.out.
As is shown in FIG. 3B, the converter clock signal CONV is a pulse signal which is obtained by delaying the clock signal PHI by a predetermined delay time T. The voltage values are digitized at the H/L-transitions of the signal CONV.
The converter clock signal CONV with the appropriate delay can be obtained in various ways, two of which are illustrated in FIGS. 4 and 5.
In FIG. 4, the signal CONV is derived from the clock signal PHI by means of a delay circuit 16. The delay circuit 16 may be formed for example by a series connection of a certain number of buffers each of which has a certain delay time, so that the total delay time is determined by the number of buffers. However, this implementation has the drawback that the delay times of commercially available buffers are known only within certain tolerances and the tolerances of the individual buffers in the series connection are accumulated, so that the total tolerance of the delay circuit 16 may become too large.
Alternatively, a delay circuit 16 may be used which is specifically designed for delaying a logic signal with a well defined delay time. However, such delay circuits are comparatively expensive and may not be commercially available for the specific delay time which is needed in a given application. In such cases, a user specified device would have to be developed which would increase the costs even more.
In another known implementation which is shown in FIGS. 5(A) and (B), all the signals PHI, PHIn, RS and CONV are derived from a common basic clock signal CLK using a timing circuit 18 which is made up of a number of digital counters and may be considered as a state machine. In this case, the durations of the H and L periods of all signals output by the timing circuit 18 can only be integral multiples of the period of the basic clock signal CLK. Accordingly, in order to achieve a sufficient time resolution, the basic clock signal CLK must have a comparatively high frequency. Such a high frequency clock signal may be difficult to generate and may be unfavorable because it leads to the generation of electromagnetic noise and to problems of electromagnetic compatibility (EMC).
In addition, these known techniques have the disadvantage that the digital output signal of the ADC 14 is delayed relative to the clock signal PHI, so that an additional step is necessary for synchronizing the digital output of the ADC 14 with the system clock CLK.
This specific problem is addressed by a system disclosed in DE-A-36 24 252. In this system, as is shown in FIG. 6, the clock signal PHI, PHIn is directly applied to the control input of the ADC 14 and serves as the converter clock signal CONV. The correct time relationship between the operations of the CCD-array 10 and the ADC 14 is established by appropriately delaying the clock signal PHI, PHIn supplied to the clock input of the CCD-array 10. Thus, the output of the ADC 14 remains synchronized with the original clock signal PHI, PHIn. However, the above-mentioned problems relating to the provision of a delay device which can delay a logic clock signal with sufficient accuracy and reliability are still encountered in this system.

Method and system for digitizing sensor data in synchronism with sensor data readout


A dampening device for a compensating cable operably engaged with an elevator car is provided, wherein the compensating cable includes two linear portions connected by an arcuate portion. A first guide including at least one roller member is disposed within the arcuate portion and is configured to dampen oscillation of the compensating cable. At least one sensor device is disposed within the arcuate portion and is capable of operably engaging at least one of the compensating cable and the at least one roller member to sense an entanglement condition of the compensating cable. In some instances, at least one sensor device is disposed outside the arcuate portion, in addition to or instead of the at least one sensor within the arcuate portion, and capable of operably engaging the compensating cable to sense a suspension rope stretch condition. An associated system and method are also provided.

1. Field of the Invention
The present invention relates to an elevator having a compensating cable and, more particularly, to a dampening device for a compensating cable operably engaged with an elevator car, capable of dampening oscillation of the compensating cable and indicating an abnormal condition thereof, and associated system and method.
2. Description of Related Art
An elevator car installation typically uses a compensating cable arrangement, as will be appreciated by one skilled in the art. Such a compensating cable is generally very flexible and can be hung at very long lengths in an elevator hoistway. Because the compensating cable is attached to the elevator car and a counterweight, which move vertically and opposite each other, the cable is susceptible to oscillations and/or swaying during operation of the elevator. The oscillations of the cable are typically of the greatest magnitude and the most evident in the pit area at the bottom of the elevator hoistway, which is where the cable forms a loop. The oscillations of the cable may pose a problem in the pit when the cable moves and sways near equipment therein. More particularly, the oscillations and/or swaying of the cable can cause the loop to become entangled with the pit equipment or to possibly fall outside the influence of one or more dampening devices intended to dampen the motion of the cable. Thus, during operation, the compensating cable may be at risk of becoming entangled and/or overloaded, and thereby possibly raising operational and safety concerns.
One compensating cable installation method requires a safety loop to be incorporated into the compensating cable. The safety loop may be, for example, located underneath the elevator car where a loop of the compensating cable is supported from the car with a deformable S-hook. The S-hook functions as a mechanical safety link such that, should the compensating cable become entangled and/or overloaded, the S-hook yields and the slack or excess length of cable forming the loop is released from the elevator car. One intended effect of such a configuration is that the released excess cable will allow the cable to untangle itself, thereby reducing the risk of damage to the cable should it become severely overloaded. However, if the elevator car is moving downward and the cable happens to become entangled in the pit or with pit equipment, the portion of the cable underneath the counterweight will tend to become overloaded, while the portion of the cable underneath the car will be slack. As such, the safety loop may not work properly in that instance.
Thus, there exists a need for a dampening device for shallow elevator pits that will not transfer or apply torsion or other forces to the compensating cable, but is capable of dampening the sway of the cable resulting from centrifugal forces and oscillations during operation. Such a dampening device should be operable with different cable configurations, such as a round compensation cable or a flat compensation cable, should contain the cable loop in its proper position, and should properly guide the cable so as to prevent potential entanglements. The dampening device should desirably provide an alternative to or supplement for the compensating cable safety loop, by detecting an abnormal or unsafe compensating cable condition and, as a result, indicating the condition and/or stopping operation of the elevator before damage and/or injury occur. More particularly, such a device should be capable of signaling or warning of an unsafe compensation cable loop condition such as, for example, when the loop in the pit is hanging too low from suspension rope stretch or when the loop is too high due to entanglement of the cable.

Dampening device for an elevator compensating cable and associated system and method


A security assessment tool can determine computer assets in a network and provide an overall security score for the network. The overall security score can represent an objective measure of the security of the network that considers potential security threats to the computer assets, counter measures deployed in the network to address the potential security threats, and the effectiveness of the counter measures. Based on the overall security assessment, the security assessment tool can provide recommendations for improving the security of the network.

In today's distributed computing environments, security is of the utmost importance. Due to the rise of wide-area public networks, users have unlimited access to content, e.g. data, files, applications, programs, etc., from a variety of sources. Additionally, the users' connection to the public networks provides a window for malicious entities to attack the users' computing systems. Malicious entities utilize this ease of accessibility and anonymity to attack the users. For example, the malicious entities can plant viruses, Trojans, or other malicious agents in publicly available content in order to attack the users' computing systems and steal sensitive information from the users and can attack the users' system remotely across the public networks.
To identify security risks in computing systems and networks, users and administrators employ vulnerability assessment and security assessment tools. These tools can identify vulnerabilities in computing systems and networks but only provide discrete information about the vulnerabilities (i.e. that a vulnerability exists). Accordingly, the tools do not provide any assessment of the vulnerabilities within the context of the overall network security.

Systems and methods for assessing security for a network of assets and providing recommendations


A brush board assembly for a DC or AC motor employs a spool-shaped frame unitarily formed of a mounting plate, a series of support members that extend axially and define the brush holders, and an outer support plate that is generally parallel to the mounting plate. This frame may be molded of a high strength, high temperature resin for heavy duty motor use. Brush hold down springs are mounted onto push-in carriers that fit into receptacles on the support members. Preferably, scroll or volute springs are employed, and a stop arm on the carrier allows the free end of the spring to be held out of the way for installation or brush change out.

This invention is directed to electromagnetic rotating machines, and is more particularly directed to an assembly for holding brushes in position in an electrodynamic motor. The invention is more particularly concerned with a brush board and brush holder assembly that may be molded of a high performance plastic resin, with the brush board frame and brush holders unitarily formed for increased strength and durability under heavy duty operating conditions.
In DC motors of the type in which a rotary armature is supplied current through a rotary commutator, it is typical to mount the brushes in brush holders or brush boxes that are attached to a frame or support plate, i.e., a brush board, which is mounted to one end of the motor housing. This will typically have a center aperture to accommodate the commutator structure. The brush boxes or brush holders are separate items, usually made of steel or brass, and are mounted to the brush board by means of mechanical fasteners such as bolts. The carbon brushes are positioned in rectangular profile cavities or chambers, where brush springs urge the brushes to move inward (radially) to contact the contact bars of the commutator (or slip rings in the case of an AC motor).
A number of brush holder arrangements have been presented in the literature, and some of these are illustrated in connection with DC motors as shown in U.S. Pat. No. 5,208,499 to Barber et al., U.S. Pat. No. 5,004,943 to Gagneux, U.S. Pat. No. 4,694,214 to Stewart, Sr., and U.S. Pat. No. 4,293,789 to King. These all employ a single support plate with a number of brush holders mounted or formed on it, and each has a limited ability to withstand temperature loads. This construction can limit the motor to lighter duty operation. Also, in the motors of the prior art it has been difficult to replace worn brushes, and it is usually necessary to disassemble the brush board to achieve that, if it is even possible to do so.
Motors of this type are frequently used in electric vehicles, such as fork lifts and golf carts, where the motor is supplied with low voltage DC, typically 12 to 120 volts, and has a relatively high current draw, e.g., from several amperes to several hundred amperes or more. There can be a substantial voltage drop through the brushes and commutator, producing significant heating of the brush holder arrangement during normal operation.

Brush board for high current electric motor


According to one embodiment of the invention, a method of accessing instruction data from a memory comprises steps of specifying a predetermined address of a memory for storing instruction data; writing instruction data to the predetermined address in the memory; reading the instruction data from the predetermined address after the step of writing instruction data; and determining whether the instruction data is valid. According to another embodiment of the invention, a method describes a method of accessing instruction data from a memory by way of first and second data buses. According to a further embodiment, instruction data read back from the memory is multiplexed to a memory controller. A circuit for accessing instruction data written to a memory is also described.

Memory devices are used for a wide variety of applications in electronic devices, and are used to store different types of information, such as data or instructions. When loading instructions, it is important that the instructions are loaded and stored in a memory properly. One common application for employing memory is in programmable logic devices, such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD), for example. If instruction data loaded in a memory is corrupted, a circuit relying on the instruction data may not function properly. Therefore, it is important to verify that instruction data loaded to a memory is loaded and stored properly.
In conventional devices incorporating memory, an instruction side on-chip memory (ISOCM) interface is used primarily to fetch instructions from an instruction side Block RAM (ISBRAM) attached to it. Instructions may be loaded into the ISBRAM, either during configuration of a programmable logic device or using a dedicated register on a device control register (DCR) bus. As shown in FIG. 1, a conventional integrated circuit having memory comprises a processor 102 which issues a request to perform an instruction fetch starting from a specific ISOCM memory location. The ISOCM controller 104 detects this request, translates the request into control signals for ISBRAM 106, and controls the ISBRAM to perform an instruction fetch. Thus, the ISOCM controller receives instructions from the ISBRAMS via BUS B, and then sends the instructions on the BUS A, so that the processor can execute the instruction.
When there is a write access on BUS C (i.e. the processor gives signals indicating that it will write instructions into ISBRAM using the DCR bus), the ISOCM controller detects the write instructions, and translates them to perform an instruction write. Along with ISBRAM specific, write control signals, the data to be written to ISBRAM also gets transferred onto BUS D. Accordingly, a user can use DCR access to write into the ISBRAM array in such conventional devices. For each write to the ISBRAM, the ISOCM controller writes into the ISBRAM, and increases the address for ISBRAM address, as will be described in more detail below with respect to FIG. 3.
As shown in FIG. 2, a conventional DCR multiplexer 202 selects data from one of a plurality of instruction side registers. In particular, an ISFILL register 204 couples data stored in the ISFILL register to DCR multiplexer 202. Similarly, an ISINIT register 206 couples the initial address to DCR multiplexer 202. An ISCNTL register 208 couples any required control signals to DCR multiplexer 202. Finally, an ISARC register 210 is a DCR register that stores 8 bit of address specified by user. It is used to compare with the upper 8 bits of address that the processor provides to the ISOCM controller. In the ISOCM controller, the upper 8 bits of the processor address are compared with the 8-bits in ISARC. If they match, that piece of the address sent by the processor is within the ISOCM memory space, and the controller will let the instruction side on-chip memory respond to the processor commands. Otherwise, the ISOCM will just ignore the command.
As shown in FIG. 3, a conventional circuit for writing an address to the ISBRAM is shown. In particular, an initial address received from the DCR is coupled to a multiplexer 302. The multiplexer receives a load ISINIT register signal to select to receive either the address from the DCR or an output of a second multiplexer 304, which selects an address which may be incremented by 1, as a result of the Increment by 1 block 306. That is, multiplexer 304 receives a Write ISFILL Command from the processor to determine whether the address is to be retained in the ISINIT Register, or the address is to be incremented by 1.
In order to make sure that the instruction contents of the ISBRAM are written acurately, the instruction data must be verified. In conventional devices incorporating memory devices, it is difficult to provide a software based debugging of the memory device. As processor executes instructions, if a program results in an error or illegal instruction, it is hard for a user to debug since the instruction is fetched from ISBRAMs and fed to the instruction register by way of a bus for fetching instructions. The only known method to read contents of a memory (e.g. BRAM) that serves as an instruction side on-chip memory in an FPGA is using soft FPGA IP based techniques. That is, a user would typically access the contents of the memory by way of a processor local bus, and read the contents through an arbiter and a BRAM controller. However, such techniques, which are well known in the art, result in lower performance and high area overhead. Since it is not very practical to implement soft IP based solutions, an FPGA bitstream read back mechanism is often used to read the contents of ISBRAMs. However, such a bitstream read back mechanism cannot be used with the software debugging tools.
Accordingly, there is a need for a circuit for and method of accessing instruction data written to a memory to read back and verify the instruction contents of a memory.

Circuit for and method of accessing instruction data written to a memory


Methods for applying a dielectric protective layer to a wafer in wafer-level chip scale package manufacture are disclosed. A flowable dielectric protective material with fluxing capability is applied over the active surface of an unbumped semiconductor wafer to cover active device areas, bond pads, test socket contact locations, and optional pre-scribed wafer street trenches. Preformed solder balls are then disposed over the bond pads, and the wafer is subjected to a heating process to reflow the solder balls and at least partially cure the dielectric protective material. During the heating process, the dielectric protective material provides a fluxing capability to enable the solder balls to wet the bond pads. In other exemplary embodiments, the dielectric protective material is applied over only intended physical contact locations and/or pre-scribed wafer street trenches, in which case the dielectric protective material need not include flux material and may additionally include a filler material.

The present invention relates to packaging of electronic devices. More particularly, the present invention relates to methods of forming a protective material layer at the wafer level to protect at least portions of active surfaces and edges of chip scale packages including electronic devices.
Factors of cost and density are increasingly important in the electronics industry. Conventionally, high-density electronic devices in the form of semiconductor dice are packaged in transfer molded housings for protection from the environment and to provide electrical connections with the higher-level circuit structures into which they are incorporated. In an effort to reduce size and expense, semiconductor manufacturers have developed chip scale package ("CSP") structures, which add minimal physical dimension to the completed devices and eliminate capital expense and processing steps associated with conventional packaging methods.
The formation of CSP structures may involve forming a dielectric layer adhered directly on one or more surfaces of a semiconductor die to seal and protect it from mechanical and environmental damage. In conventional CSP-forming processes, a passivation layer is typically formed on the active surface of a semiconductor die with apertures to expose the die bond pads, and an under-bump metallization (UBM) layer may be formed over the exposed bond pads to facilitate wetting of material of a conductive bump, such as a tin/lead solder, to be formed thereon to provide input/output, or "I/O," connections for the CSP. The UBM layer may also, alternatively be located across the passivation layer remote from original bond pad locations at ends of conductive traces in the form of a so-called "redistribution layer" to relocate the external contact (bond pad) locations for connecting the semiconductor die to higher-level circuit structures. In such an instance, another dielectric layer is typically formed over the redistribution layer, apertures through the dielectric layer exposing I/O pad locations at the end of the conductive traces where the UBM layer may be formed. Discrete conductive elements in the form of bumps or balls may then be formed on or attached to the UBM layer-covered external contact locations to enable connection with higher-level circuit structures by flip-chip attachment. A mask layer may optionally be applied to surround the external contact locations prior to forming conductive bumps, which prevents the bump material from wicking onto adjacent die surfaces. Alternatively, a tape automated bonding (TAB) attachment approach may be employed. Finally, a layer of polymer or other dielectric protective material is conventionally coated onto one or more additional surfaces of the die to complete the CSP. The completed CSP is typically no more than 1.2 times larger than the die itself.
A further advantage of CSP structures is that they may be fashioned wholly or in part prior to the singulation of a wafer containing a plurality of semiconductor die locations. This approach, often being referred to as "wafer-level packaging," provides simultaneous formation of a large number of electronic device packages. After the desired circuitry, bond pads, passivation layer, optional UBM and mask layers for the electronic devices have been fabricated on the active side of the wafer, conductive bumps are provided using conventional formation methods. One widely used method is evaporative deposition of metal onto a mask. The mask is formed on the wafer with apertures corresponding to the bond pad or other external contact locations and metal is deposited in the apertures. Once enough metal is deposited, the mask is removed and the metal is reflowed by heating to a molten state to form a discrete conductive element in a final bump or ball shape.
Another alternative for bumping a wafer is to employ stencil printing. Rather than evaporating metal through a mask, a solder paste is screened over a stencil and fills apertures therein corresponding to the bond pad or other external contact locations. The stencil is removed from the surface of the wafer, and the solder is reflowed for bonding to the UBM. Once the conductive bumps are in place, the entire active side of the wafer may or may not be coated with the aforementioned CSP protective layer. This is accomplished by molding, spin-coating or otherwise applying the protective layer to the surface of the wafer by methods known in the art. The wafer is subsequently singulated to excise the individual semiconductor dice, and further protective layers may be added to coat any remaining exposed die surfaces.
A further alternative for wafer bumping is to place preformed metal balls, such as solder balls, on the wafer at selected locations. The wafer is then heated to at least partially melt the solder balls and metallurgically bond them to the UBMs or other contact structures on the wafer. As before, once the conductive bumps are in place, the entire active side of the wafer is coated with the aforementioned CSP protective layer. This is accomplished by molding, spin-coating or otherwise applying the protective layer to the surface of the wafer by methods known in the art. The wafer is subsequently singulated to excise the individual semiconductor dice, and further protective layers may be added to coat any remaining exposed die surfaces.
One disadvantage in conventional wafer-level packaging has been encountered due to the formation of the conductive bumps before applying the layer of dielectric protective material to the active side of the wafer. The layer often completely covers the conductive bumps or, if not, at least contaminates portions of the surfaces of the conductive bumps. Therefore, the dielectric protective material must be etched back, ground down or otherwise partially removed to expose the conductive bumps for electrical contact. Furthermore, surface tension between the dielectric protective material and the conductive bumps can cause irregularities during coating and thereby reduce the uniformity of the protective layer.
Another disadvantage in conventional wafer-level packaging has been encountered in connection with testing CSPs. A singulated die is typically placed in a test socket for testing. Contact between the CSP and the test socket, particularly at edges and corners of the active surface of the CSP, can cause damage to the integrated circuit of the device. Such damage is particularly likely to occur when residual particles remain in the test socket from prior use, providing point loading of the protective layer and the underlying active surface. Damage can also, and frequently does, occur in the ordinary course of handling CSPs.
Yet another disadvantage in known wafer-level packaging is warpage resulting from the formation of protective layers over an entire surface of a CSP, which results in lower yields of CSPs.
In view of the foregoing, there is a clear need for improved methods for wafer-level packaging that address the existing problems associated with forming protective layers in CSPs.

Electronic devices at the wafer level having front side and edge protection material and systems including the devices


A microwave oven excitation system comprising a cylindrical microwave launcher for radiating microwave energy into a heating cavity of a microwave oven which is mounted adjacent to the heating cavity in either a substantially vertical position or a substantially horizontal position, a first hollow waveguide secured to the launcher, a first source of microwave energy at a predetermined operating frequency secured to the first waveguide, a second hollow waveguide secured to the launcher substantially perpendicular to the first waveguide, and a second source of microwave energy at a predetermined operating frequency secured to the second waveguide. Alternatively, a single waveguide is secured to the cylindrical launcher and has only a single source of microwave energy secured thereto. In either case, a mode stirrer can be installed within the cylindrical microwave launcher.

It is well known that electromagnetic energy can be utilized for heating foodstuff or other lossy dielectric materials. The foodstuff or other materials are placed in a cooking cavity of a microwave oven and are exposed to electromagnetic energy that is supplied by a suitable source, e.g., a magnetron. After a relatively short period of time during which the foodstuff is subjected to electromagnetic energy, heat will be generated in the foodstuff to accomplish the desired cooking of the foodstuff.
In a microwave oven, an ideal system for exciting the cooking cavity with microwave energy would evenly distribute the microwave energy across those portions of the cavity in which the food is located. Since food is normally located in only a limited area of the oven it is desirable to maximize the energy in the portion of the cavity in which the food is to be located.
Microwave ovens have employed numerous types of feed and distribution systems in an attempt to maximize the energy supplied to the food. For example, in British Patent No. 1,407,852, there is disclosed a microwave oven which utilizes "near field" effects of electromagnetic radiation to heat foods. In this method, the food is maintained in close proximity with a radiation element, a proximity preferably less than one wavelength of the exciting electromagnetic energy. Also, in U.S. Pat. No. 3,810,248, a microwave apparatus is described in which food is placed in a container over slotted openings in a waveguide. The food is heated directly by the microwave energy exiting the waveguide, and indirectly by a radiation absorbing layer in the container that is contact with the food. In addition, U.S. Pat. No. 3,851,133 discloses a microwave oven which includes an antenna chamber, with an antenna in the form of radially extending arms rotating around a common axis mounted therein, disposed adjacent to the cooking cavity with microwave energy being introduced into the cavity through radiation slots disposed on the side of the cavity adjacent the antenna chamber. Also, U.S. Pat. No. 4,019,009 discloses a microwave oven which heats food by subjecting it to a microwave field generated by a surface wave transmission line comprising a slotted wall.
Other known methods for providing a more uniform distribution of microwave energy rely on the use of rotating devices within the cooking cavity, such as a mode stirrer having blades and being driven by a motor cyclically, a rotating food tray, or a rotating antenna. Each of the methods described above has certain drawbacks, particularly if installed in a hybrid oven which combines microwave heating with conventional oven techniques, where the internal temperature of the oven cavity is normally approximately 500 degrees F, such as is more particularly described in U.S. Pat. Nos. 5,254,823, 5,451,751 and 5,558,793.
A particular problem facing many microwave ovens relates to loading effects caused by the size of the foodstuff installed in the cooking cavity. When a small item is placed in the cavity, or especially when the cavity is empty, and the oven is operated, the microwave energy can reflect back to the magnetron, where it is dissipated as heat and can eventually damage the magnetron. A number of methods have been used to prevent such damage to the magnetron. One such method involved placing a thermostat in proximity to the anode of the magnetron to detect the temperature at the magnetron. A control circuit cut off power to the magnetron when the temperature reached a point at which damage would occur. However, in this method the magnetron can still be stressed by relatively high temperatures. Another method, disclosed in U.S. Pat. No. 3,527,915, provides a no-load sensing device that is mounted within the cooking cavity to cut off the magnetron when a specified temperature is reached within the device. In addition, U.S. Pat. No. 5,451,751 discloses a microwave oven which utilizes a wave guide switching device to vary the energy supplied to the cooking cavity depending upon the load installed therein. Each of these methods has certain drawbacks, particularly if installed in the hybrid oven described above.
In U.S. Pat. Nos. 5,254,823, 5,434,590 and 5,558,793. to McKee et al. ("the McKee Patents"), the contents of which are explicitly incorporated by reference herein, a hybrid oven is disclosed for cooking by both hot air impingement and microwave energy. Each oven includes an apparatus, which is shown in FIG. 1 and is generally designated by reference numeral 10, for illuminating a heating cavity with microwave energy. In FIG. 1, first magnetron 11 feeds microwave energy at a preselected frequency into first waveguide 12, and second magnetron 13 feeds microwave energy at the same preselected frequency into second waveguide 14. First waveguide 12 and second waveguide 14 each feed the respective microwave energy into the common third waveguide 15, which mixes the microwave energy and directs it into launcher 16. Launcher 16 is a cylindrical waveguide which directs the mixed microwave energy upward into the heating cavity (not shown) which is disposed directly above launcher 16. A mode stirrer (not shown) may be optionally installed within the launcher 16 to provide a more uniform pattern of illumination in the microwave energy supplied to the heating cavity. In practice, the conventional devices have certain drawbacks. In particular, the loading effects produced were found to be less than optimal.

Apparatus for supplying microwave energy to a cavity


A pseudo differential circuit is a circuit system taking the advantages of both a CMOS circuit and a differential circuit. However, when process variability and the like are taken into account, a cross point of positive and negative outputs is not constant, thereby increasing a variation in duty of an output waveform. A semiconductor circuit according to the present invention includes: a first transistor being of a first conductivity type, coupled between a first power supply and an output terminal, and applied with an input signal; a second transistor being of a second conductivity type and coupled between a second power supply and the output terminal; a third transistor being of the second conductivity type and coupled between the first power supply and the output terminal; and a fourth transistor being of the first conductivity type and coupled between the second power supply and the output terminal.

1. Field of the Invention
The present invention relates to an output buffer, and more particularly, to an output buffer for compensating a deviation caused by process variability.
2. Description of the Related Art
An output buffer including a CMOS circuit is used for a semiconductor circuit. FIG. 21 is a circuit diagram showing a generally-known output buffer. The output buffer shown in FIG. 21 is a buffer for inverting and out putting a signal applied to an input terminal. When an intermediate potential VDD/2 between a power supply potential (VDD) and a ground potential (VSS) is input to the input terminal of the output buffer, it is preferable to output the potential VDD/2 from an output terminal thereof. A technology of stabilizing the potential at the output stage is described in, for example, JP 2006-245828 A.
However, in an output buffer circuit 11 where a CMOS circuit is included as shown in FIG. 21, when a PMOS transistor and an NMOS transistor are formed, there exists process variability. As a result, when the characteristics of the respective transistors deviates from design values, an output voltage may deviate from VDD/2 even if the VDD/2 is input as an input voltage. Therefore, there is the case where the output buffer circuit 11 does not act as an output buffer which performs an accurate operation.
The output buffer circuit 11 according to the conventional technology includes an input terminal 11 to which an input signal IN is input, an n-type MOS transistor MN1 for generating an inverted logic of the input signal IN, a p-type MOS transistor MP1 serving as a load for the MOS transistor MN1, and an output terminal 2 from which an output signal OUTB is output.
The sizes of the MOS transistors MP1 and MN1 of the circuit as shown in FIG. 21 are generally determined such that, as an operating point (point at which the middle of the amplitude of a signal output to the output terminal 2 relative to a voltage input to the input terminal 1 is equal to VDD/2), a voltage VOUTB output to the output terminal 2 becomes VDD/2 when a voltage VIN input to the input terminal 1 is VDD/2.
However, a semiconductor circuit manufacturing process size has been reduced in recent years, so variations in current gain (β) value and threshold voltage (Vth) value in each of the n-type MOS transistor and the p-type MOS transistor are caused by the process variability as described above. Therefore, even when the semiconductor circuit is formed based on values obtained by theoretical calculation, there is a difference from expected transistor capability, so a predetermined circuit output is not obtained.
Here, a variation in transistor capability being caused by the variability of the manufacturing process (process variability) is expressed as "n-type MOS transistor capability/p-type MOS transistor capability." For example, when the process variability is "large/small," a current gain βN and a threshold voltage VthN of the n-type MOS transistor and a current gain βP and a threshold voltage VthP of the p-type MOS transistor deviate from expected values. Therefore, the operating point of the voltage VOUTB decreases in the case where the voltage VIN is VDD/2. The operating waveforms at this time are shown in FIGS. 22A and 22B. On the other hand, even when the process variability is "small/large," the current gain PN and the threshold voltage VthN of the n-type MOS transistor and the current gain βP and the threshold voltage VthP of the p-type MOS transistor deviate from the expected values. Therefore, the operating point of the voltage VOUTB increases in the case where the voltage VIN is VDD/2. The operating waveforms at this time are shown in FIGS. 23A and 23B.
As described above, there is the case where the theoretical output corresponding to the input is not obtained in the conventional output buffer having the CMOS structure because of, for example, the process variability.


Contact lenses comprising phosphorylcholine groups release beneficial polyionic or guanidinium-containing agents.

The field of the disclosure is ophthalmic devices for administering beneficial agents.
Contact lenses for administering ophthalmic drugs and other beneficial agents to the ocular tissue of a patient have been described. For example, the anionic contact lens material, etafilcon A, has been used in clinical studies to deliver or administer ketotifen, an anti-allergy drug used in the treatment of allergic conjunctivitis (see ClinicalTrials.gov NCT00569777). A problem associated with some ocular delivery devices is that they can be limited in the type of beneficial agent that the device is capable of administering. Another problem associated with some ocular drug delivery devices is that they involve complex manufacturing methods which are not amenable to large-scale manufacturing operations. We have discovered improved methods of manufacturing beneficial agent-releasing contact lenses that address these problems.
Contact lens packages including a sealed receptacle that contains a contact lens made of a silicone hydrogel copolymer in a sterile solution which comprises a stabilizing agent which can form an ionic complex or hydrogen bond with the hydrogel copolymer, have been described in U.S. Pat. Publ. No. 2007/0149428. A packaging system and method for the storage of an ionic hydrogel lens that uses an aqueous packing solution which includes a phosphorylcholine polymer, and which further can include a buffering agent, have been described in U.S. Pat. Publ. No. 2009/0100801. Other background publications include U.S. Pat. Publ. No. 2008/0085922, U.S. Pat. Publ. No. 2007/0265247, U.S. Pat. Publ. No. 2007/20100239637, U.S. Pat. Publ. No. 2008/0124376, U.S. Pat. No. 7,841,716, Karlgard et al, Int J Pharm (2003) 257:141-51 and Soluri et al., Optom Vis Sci (2012) 89:1140-1149.

Ophthalmic devices for delivery of beneficial agents

CooperVision International Holding Company, LP


Provided is a tire sensing system that reduces the power consumption, size, weight, and cost, while suppressing an increase in fuel consumption of moving means. The tire sensing system is adapted to monitor state of a tire or a road surface from vibration information to perform safety control of the moving means having the tire. The tire sensing system includes a sensor disposed in a position of an inner surface of the tire where the sensor can sense the vibration, a receiver for receiving the information sent from the sensor, and a control means for controlling the moving means on the basis of the information from the receiver. The state is estimated from first vibration applied to the sensor upon contact with the road surface via the tire, second vibration applied to the sensor upon departure from the road surface, and a contact time from the contact to the departure.

1. Field of the Invention
The present disclosure relates to a tire sensing system for safety control of a vehicle by monitoring state of a tire or a road surface based on physical information on the tire and its surroundings (for example, information about an air pressure of the tire, vibration from the road surface, and the like).
2. Description of the Related Art
Recently, some attempts have been made to prevent traffic accidents from occurring due to a decrease in air pressure of a tire or an increase in temperature of the tire by recognizing the state of a road surface or the state of a tire, for example, for a motor vehicle or motor bike by use of a wireless sensing network.

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


Allowing an agent to customize their CTI terminal with respect to a variety of terminal attributes such as those associated with previous phone activity, configuration information such as color, and graphical statistical representation of ACD center information. The telecommunication agent is able to store information defining this customization and to retrieve it at another CTI terminal at a later point in time. The storage of the customization information is performed as a file on a file server common to all CTI terminals. The result is that no software must be custom written for the file server in order to allow the saving of customized information. In addition, the programs controlling the CTI terminals are independent of the communication protocol that is utilized between the CTI terminals and the file server. A second embodiment of the invention allows the administrator of a call center to specify that each group of agents will utilize the same customization information. This group customization information is stored on each CTI terminal which reduces the real time load on the file server when a new agent work session starts. Also, each CTI terminal periodically polls the file server to see if a new set of group customization information has been stored on the file server. Call center administrators will routinely store new group customization information on the file server. If a new set of group customization information has been stored on the file server, the CTI terminal accesses this information and stores it internal to the CTI terminal.

In the last decade or so, Computer Telephony Integration (CTI) has come to be employed with switching systems. A CTI terminal is a combination of a Personal Computer (PC) with an attached telephone. The PC is controlled by an application program. This application program emulates a voice terminal used in call centers such as a Callmaster or Callmaster II voice terminals. In addition to emulating a normal call center voice terminal, the PC application allows additional functions to be performed. The PC is interconnected to the switching system utilizing normal telephone communication links. The switching system is programmed to consider the CTI terminal as an ordinary call center voice terminal. In addition, the CTI terminal is interconnected to a file server or client server which provides the CTI terminal database information. CTI terminals have been especially used in call centers. Call centers are systems that enable a group of agents to serve incoming and/or outgoing calls, with the calls being distributed and connected to whichever of the agents happen to be available at the time of the call. The call/distribution function is commonly referred to as Automatic Call Distribution (ACD) is generally implemented in software that executes either in a stored program controlled switching system, such as a Private Branch Exchange (PBX) or in an adjunct processor of the switching system.
In most ACD centers, the number of telecommunication agents is greater than the number of CTI terminals. This occurs since an ACD center is normally active at least 16 hours a day if not 24 hours so there are two or three shifts of telecommunication agents. In addition, some ACD centers schedule breaks of the telecommunication agents such that within a shift there may be more telecommunication agents than available CTI terminals. The result is that often a telecommunication agent will use many different CTI terminals over the course of time. This means that telecommunication agents cannot customize the CTI terminals for their personal needs unless they do it for each CTI terminal.


The present disclosure relates to a method for operating a round baler. The method comprises providing a nonstop baler type machine; feeding of crop into a prechamber and a main bale forming chamber; and providing, by a binding unit, a binding material to the main bale forming chamber for wrapping a bale formed in the main bale forming chamber, comprising, in a first mode of operation, providing a stretching apparatus in contact with the binding material, thereby, applying a compressive force to the binding material for stretching the binding material; and in a second mode of operation, providing the stretching apparatus free of contact with the binding material. Furthermore, a round baler is disclosed.

A baling machine, usually existing of the round or rectangular bale type is used to package crop material into a round or rectangular shape.
A baling machine can be divided up into various areas of components and apparatuses. One of the primary components of the baler is the binding unit usually commonly used to apply a twine/net or a sheeted type material to the bale of product. The binding apparatus can be located on the baler in various locations depending on the type of machine and its use.
Applying binding material to the bale can be a difficult process to achieve high levels of reliability. In particular, problems exist with sheeted materials in that the surface of the material is not of the mesh type and as a result the crop on the bale does not bond with the binding material as efficient as of the mesh type of binding. As a result, the binding sheet type material can often fail to follow the circumference of the bale and may instead follow a rotating component of the baling machine.
In general the machines that can apply this type of sheet binding material, the operator needs to manipulate the intake of crop into the machine as the binding material is being fed into the baling chamber so the incoming crop can enclose the first parts of the sheet material within layers of crop so the sheet binding material is trapped between the crop layers and as a result can successfully follow around the circumference of the bale without leaving the baling chamber.
This intake of crop material to enclose the first parts of the binding material with the crop on the bale is not automated by the machine but instead is solely carried out by the skill of the operator of the machine. This is a difficult process and can also be very unreliable as the operator has to judge the quantity of crop entering the machine and also judge the forward speed correctly of the baling machine. In a standard stop start baler, the driver needs to stop when the baling chamber is full in order to apply the binding material. If the driver stops too early the first part of the binding material will not be enclosed in the bale and the binding material may not follow the bales circumference, if the driver drives forward too far after the baling chamber is full, the first part of the binding material will be enclosed too far beneath the bales surface and excess crop will cover the plastic causing issues at a later stage with the preservation of the crop material and the removal of the binding material. The issues also include incorrect over lap of the binding material, excess crop between the binding layers allowing air or and moisture to enter the bale and/or accumulative issues when trying to remove the binding material from the bale.
Another problem with the binding material of the sheeted plastic type is providing a reliable apparatus to feed the plastic into the chamber, to provide a stretching of the plastic and then to remove some of the braking force at the end of the binding cycle to successfully cut the binding material so the cycle may be successfully started again on the next bale. Due to the elasticity of the binding material, the braking/stretch of the plastic sheet material must be removed at the end of the cycle in order to prevent excessive contraction of the plastic binding material. If there is excessive contraction of the stretched binding material, reliable feeding of the material at the start of the next bale binding cycle may not be possible.
Commonly, a roller is used to provide a stretch on the binding the material. Either the braking roller is pushed onto the roll of binding material and or the binding material is routed around the braking roller for stretching the binding material. The binding material may be wrapped around the braking roller between 100 and 300 degrees of contact with the braking roller depending on the machine type.
The applying compressive force from the braking roller pushing onto the circumference of the roll of plastic may be limited because when feeding the binding material at the start of the binding process, it would not be possible to pull the binding material from the roll of binding material due to the high rolling resistance caused by the excessive compressive forces. As a result of this limited compressive force between the braking roller and the roll of binding material, limitations will exist when stretching the binding material at the higher stretch percent-ages.
The problem presented is, if the force of the braking roller pushing onto the roll of binding material is too great, the binding apparatus will be unable to draw the binding material from the roll of binding so the binding material can enter the baling chamber. If the force of the braking roller pushing on the roll of binding is not sufficient, the release of the braking rotational force at the end of the binding cycle in order to cut the material, the momentum in the roll of binding material will cause the roll of material to rotate after the binding material has been cut and binding cycle has ended. With all of the current binding stretching systems, the stretching roller is always in contact with the binding material either through the binding material passing over, between or around the stretching roller or the stretching roller is pushing on the roll of binding material directly at all times. As a result, if the stretching is excessive or not enough, the binding material passing through the stretching roller can overrun, pull backwards or bind to the stretching roller and as a result, the binding material is not free for the start of the next binding cycle. The systems currently existing have disadvantages of needing to be finely tuning the forces to try and overcome the problems.
Document EP 3 132 672 A1 shows a binding system with a braking/stretching roller and a braking force controlled with a motor. A binding material is in constant contact with the braking/stretching roller at all stages of the binding cycle. As a result, the system needs to be finely tuned especially at the end of the cycle when cutting the binding material so the binding material does not overrun causing the binding material to fully wrap or become lodged on the braking/stretching roller.
Another example of prior art is document WO 2013/124836 A1. In this example a braked/stretch roller is in contact with a binding material and the binding material also wraps around the roller. If the binding material overruns at any point of the binding cycle or breaks at any point of the binding cycle, the plastic will inevitably become entangled and fully wrapped around the braked/stretch roller. This is a major disadvantage with these known binding systems.

Method for operating a round baler and a round baler


Methods and apparatuses for treating a vulnerable plaque are described herein. In one aspect of the invention, the exemplary apparatus includes a medical device to treat a vulnerable plaque within a body lumen, where the medical device is adapted to position a rupturing device to rupture a fibrous cap of a vulnerable plaque. In one particular embodiment, the medical device includes a rupturing wire having a predetermined pattern to enable the rupturing device to rupture the fibrous cap of the vulnerable plaque. Other methods and apparatuses are also described.

Coronary heart disease is generally thought to be caused by the narrowing of coronary arteries by atherosclerosis, which includes the buildup of fatty deposits in the lining of the arteries. The process that may lead to atherosclerosis begins with the accumulation of excess fats and cholesterol in the blood. These substances infiltrate the lining of arteries, gradually increasing in size to form deposits commonly referred to as plaque or atherosclerotic occlusions. Plaques narrow the arterial lumen and impede blood flow. Blood cells may collect around the plaque, eventually creating a blood clot that may block the artery completely.
The phenomenon of "vulnerable plaque" has created new challenges in recent years for the treatment of heart disease. Unlike occlusive plaques that impede blood flow, vulnerable plaque develops within the arterial walls, but it often does so without the characteristic substantial narrowing of the arterial lumen which produces symptoms. As such, conventional methods for detecting heart disease, such as an angiogram, may not detect vulnerable plaque growth into the arterial wall. After death, an autopsy can reveal the plaque congested in the arterial wall that could not have been seen otherwise with currently available medical technology.
The intrinsic histological features that may characterize a vulnerable plaque include increased lipid content, increased macrophage, foam cell and T lymphocyte content, and reduced collagen and smooth muscle cell (SMC) content. As shown in FIG. 1A, this fibroatheroma type of vulnerable plaque 101 is often referred to as "soft," having a large lipid pool 102 of lipoproteins surrounded by a fibrous cap 103. The fibrous cap 103 contains mostly collagen, whose reduced concentration combined with macrophage derived enzyme degradations can cause the fibrous cap of these lesions to rupture under unpredictable circumstances. When ruptured, as shown in FIG. 1B, the lipid core contents, thought to include tissue factor, contact the arterial bloodstream 104, causing a blood clot 105 to form that can completely and very quickly block the artery (e.g., lumen 106) resulting in an acute coronary syndrome (ACS) event. This type of atherosclerosis is coined "vulnerable" because of the unpredictable tendency of the plaque to rupture. It is thought that hemodynamic and cardiac forces, which yield circumferential stress, shear stress, and flexion stress, may cause disruption of a fibroatheroma type of vulnerable plaque. These forces may rise as the result of simple movements, such as getting out of bed in the morning, in addition to in vivo forces related to blood flow and the beating of the heart. It is thought that plaque vulnerability in fibroatheroma types is determined primarily by factors which include: (1) size and consistency of the lipid core; (2) thickness of the fibrous cap covering the lipid core; and (3) inflammation and repair within the fibrous cap.
Some physicians have stated that rupture of a vulnerable plaque during a PTCI (percutaneous transluminal coronary intervention) is desirable. The rationale is that if a rupture is going to occur, it is better to have it happen in the safety and security of the catheterization lab. In this way, an immediate corrective action can be taken to deal with the plaque rupture. It has been further stated that it may be desirable to have the lipid pool under the fibrous cap completely drained to prevent a blood clot build up. Therefore, it is desirable to have a device which will ensure rupture of the fibrous cap during the intervention.

Method and apparatus for rupturing a vulnerable plaque


A debugging system for compiled code may include static analysis of the compiled code to determine current values for variables at a paused location within the compiled code. The static analysis may consist of liveness analysis to determine which variables are ‘live’ and in which memory locations those variables are stored. The variables and their values may be presented to a user. The debugging system may include mechanisms for setting stop points, for pausing and continuing execution, as well as stepping through a step or group of steps. Other static analysis may include unwind information that may determine a point in the code from where the current function was called, as well as partial decompilation of the source code to produce a representation of the compiled code that is closer to that of the source code.

Optimizing compilers may create binary executable programs from high level languages, and may perform many different types of optimization on source code to achieve faster runtime execution and smaller memory footprint. In one example of optimization, complex series of statements in a high level language may be reduced to a few, succinct statements in the binary executable. In another example of optimization, a single register or other memory location may be used for different variables at different stages of a program's execution. The result of an optimizing compiler is often an executable program that does not correlate well with the original high level language.
When debugging an executable program, often much of the debugging is performed without optimizing functions. In many cases, various debugging environments may be used to step through the source code to verify program execution, check variable values, and test the operation of the code. Such debugging functions may become much more difficult when a compiler's optimization functions are used, since the correlation between the executing code and the source code may be degraded.
In many cases, optimizing compilers may generate a program database that may contain some information regarding memory locations and variables, as well as some optimizations performed on the source code. Many such program databases offer some mapping between a source code file and an executable binary, but often not enough information that may allow a debugging application to unwind or decompile the executable binary to correlate with the source code. Even with the program databases, debugging optimized compiled code can be very difficult due to the lack of correlation between the executable code and the original source code.