The invention discloses a wrist watch that offers immediate access to regularly updated content of a previously selected group of web pages without requiring it to keep continually connected to the network. The concept takes advantage of the portability and convenience of a wrist watch and aggregates to it a customizable web browsing capability. A carefully designed power management scheme harmonizes the need of frequent data update with the small footprint of the watch. The update schedule is user-customizable and once connected to the network, the watch behaves exactly like a typical portable web-browsing device.

The underlying concept is that people are interested in having updated information on certain specific topics continually available, but don't want to go through the hassle of connecting to a network, looking for the specific source, etc. Once the interest in checking certain information arises, people want to have it immediately. As people habitually check their wrist watches on a regular basis, it is desirable to have said updated information made readily available in this device with no need to ask for it. However, the typical size and weight restrictions associated with the small footprint of a wrist watch require ingenuous power management. Ideally, the Network Module of the wrist watch does not remain powered up while not needed, as the watch does not have the power to supply the circuitry required to remain continually connected to the network.
The connection to the web using a portable device typically involves a certain delay associated with connecting to a remote server over a wireless network. When the user wishes to have access to the most up-to-date information on the weather, stock market, news, etc. the process of accessing said information involves the steps of powering up the portable device, logging onto the network, accessing a remote server, navigating to the website that contains the desired information and waiting until said information is displayed on the device.
The prior art includes US 2002/0,059,166 by Wang, which discloses a method for parsing web codes which involves the selection of web content and its storage in portable devices. The selected content is not updated automatically, requiring active intervention by the user to connect to the web and request an update of the content previously stored in the portable device. Furthermore, Wang does not address the power management issues associated with a small footprint portable device.

Method for managing web access from a small footprint portable device


Open ends of a number of secondary windings are fixed by winding them around a film projection portion formed by cutting and raising insulating films provided between the layers of the secondary windings. This eliminates the requirement that a number of terminals on a bobbin corresponding to the secondary windings be fixed by winding them around the film projection portion, whereby the number of terminals provided on the bobbin can be reduced, and the bobbin can be made smaller in size.

As a step-up transformer for generating a high voltage for a cathode ray tube, there has hitherto been proposed one which includes a plurality of secondary windings, for example, eight secondary windings laminated in a plurality of layers, for example, eight layers with insulating films therebetween, divided on the basis of a predetermined number of turns, and opened at one-side ends thereof, as shown in FIG. 9.
Referring to FIG. 9, symbol 10 denotes a commercial power source of, for example, 100 V and 50 Hz. One end and the other end of the commercial power source 10 are connected respectively to one end and the other end of a rectifying circuit 11 having a diode bridge configuration, a positive output terminal of the rectifying circuit 11 is earthed through a smoothing capacitor 12, and a negative output terminal of the rectifying circuit 11 is earthed.
The positive output terminal of the rectifying circuit 11 is connected to a power source terminal of an oscillation drive circuit 14 through a resistor 13, and the positive output terminal is earthed through a switching circuit 15 consisting, for example, of a series circuit of MOS-FET switching devices Q1 and Q2. The switching circuit 15 is so driven that the switching devices Q1 and Q2 show alternative conduction at a predetermined frequency by the oscillation drive circuit 14.
Furthermore, the switching circuit 15 constitutes a half-bridge circuit, the positive output terminal of the rectifying circuit 11 is connected to the drain of the switching device Q1, and the source of the switching device Q2 is earthed. In addition, damper diodes D1 and D2 are connected in parallel to the switching devices Q1 and Q2, respectively.
A connection point between the source of the switching device Q1 and the drain of the switching device Q2 is earthed through a series circuit of a resonant capacitor 16, a coil 17, and a primary winding 18 of a step-up transformer T.
The primary winding 18 of the step-up transformer T is supplied with a current at a resonance oscillation frequency intrinsic of the series circuit.
Symbols 19a, 19b . . . 19h denote eight secondary windings which, as shown in FIG. 11, are laminated on a bobbin 107 with insulating films 105 therebetween, are divided on the basis of a predetermined number of turns, and are opened at one-side ends thereof. Rectifying diodes 20a, 20b . . . 20h are each connected, in a vertical row fashion, to a point between the other-side ends of each adjacent pair of the secondary windings, of the eight secondary windings 19a, 19b . . . 19h.
Specifically, the diode 20a is connected to a point between the other-side ends of the secondary windings 19a and 19b, the diode 20b is connected to a point between the other-side ends of the secondary windings 19b and 19c, the diode 20c is connected to a point between the other-side ends of the secondary windings 19c and 19d, the diode 20d is connected to a point between the other-side ends of the secondary windings 19d and 19e, the diode 20e is connected to a point between the other-side ends of the secondary windings 19e and 19f, the diode 20f is connected to a point between the other-side ends of the secondary windings 19f and 19g, the diode 20g is connected to a point between the other-side ends of the secondary windings 19g and 19h, and the diode 20h is connected to a point between the other-side end of the secondary winding 19h and the earth.
An equivalent circuit of the secondary winding system constituted of the eight secondary windings 19a, 19b . . . 19h and the eight rectifying diodes 20a, 20b . . . 20h is as shown in FIG. 10. By subjecting the voltages obtained at the secondary windings 19a, 19b . . . 19h to full-wave double-voltage rectification to produce DC voltages and laying up the DC voltages, it is possible to obtain a high DC voltage, for example, 32.4 kV. In FIG. 10, capacitors 21a, 21b . . . 21h are inter-layer capacitances of the secondary windings 19a, 19b . . . 19h.
In addition, the other-side end of the secondary winding 19a is connected to a high-voltage output terminal 23 through a diode 22, and a connection point between the diode 22 and the high-voltage output terminal 23 is earthed through a smoothing capacitor 24.
Besides, the high-voltage output terminal 23 is earthed through a series circuit of resistors 25 and 26, a detection voltage of a high voltage obtained at a connection point between the resistors 25 and 26 is supplied to a control circuit 27, and the oscillation frequency of the oscillation drive circuit 14 is controlled according to a DC voltage obtained at the high-voltage output terminal 23 by the control circuit 27 so that the high DC voltage obtained at the high-voltage output terminal 23 will be constant.
Meanwhile, a sectional view of an example of the entire constitution of the high voltage generating transformer as shown in FIG. 9 is as shown in FIG. 12, in which symbol 101 denotes the secondary winding system. As shown in FIGS. 11 and 13, the secondary winding system 101 has a structure in which the eight secondary windings 19a, 19b . . . 19h in the state of being laminated in eight layers with the insulating films 105 therebetween are wound around the outer circumferential surface of the roughly cylindrical bobbin 107 having walls along both side edges, the insulating films 105 are, for example, belt-like in shape, and the secondary windings 19a, 19b . . . 19h are so wound as to have a width slightly smaller than the width of the insulating films 105.
Conventionally, the one-side ends and the other-side ends of the eight secondary windings 19a, 19b . . . 19h have been fixed by binding them respectively onto terminals 103 and 104 provided, through terminal bases 103a and 104a, on one side and the other side of the bobbin 107, and the diodes 20 and the like have been connected to the terminals 103 and 104 to assemble a circuit as shown in FIG. 9.
In addition, as shown in FIG. 12, the secondary winding system 101 is disposed so as to penetrate through a core 142, which forms a closed magnetic circuit at the center thereof, together with the bobbin 102a and a primary winding system 102 constituted of the primary winding 18.
However, when the one-side ends and the other-side ends of the plurality of windings, for example, the eight windings 19a, 19b . . . 19h are fixed by binding them respectively onto the terminals 103 and 104 as in the related art, where the number of the secondary windings 19a, 19b . . . 19h connected as required is eight, for example, the numbers of the terminals 103 and 104 provided on the bobbin 107 are each eight, i.e., a total of 16 terminals are needed, as shown in FIG. 13. Thus, in the related art, the number of the terminals needed is large, and the bobbin 107 is enlarged in size accordingly.
In consideration of the foregoing, it is an object of the present invention to make it possible to reduce the number of terminals required on a bobbin and to reduce the bobbin in size.


A hydraulic drive system includes a pump, a steering actuator, a loading/unloading apparatus actuator, a drive device, a relief valve, and an input unit. The drive device: flows hydraulic oil from the pump to the loading/unloading apparatus actuator when an operating tool is operated; flows the hydraulic oil from the pump to the steering actuator when a steering has become an operated state from a non-operated state regardless of an operation of the operating tool; and causes the hydraulic oil from the pump to be discharged to a tank via the relief valve to increase the torque of an engine when an increase instruction is inputted to the input unit and the steering is in a non-operated state.

For construction machinery equipped with an engine, there is a technical problem to solve, which is to reduce particulate matter (which may hereinafter be simply referred to as PM) such as soot contained in exhaust gas discharged from the engine. In order solve the problem, the construction machinery includes, for example, filters in an exhaust gas pipe, a muffler, and the like. PM is collected by the filters, and then the exhaust gas is discharged to the atmosphere.
However, if PM is kept collected, then the PM builds up inside the filters, thereby clogging the filters. In order to suppress such clogging, it is necessary to remove the PM that has built up from the inside of the filters. One of the methods for removing PM is, for example, increasing the load torque of the engine to increase the temperature of the exhaust gas, thereby burning the PM to remove the PM. For example, Patent Literature 1 discloses a work machine that realizes such a PM removal method. The work machine disclosed in Patent Literature 1 is configured such that a controller controls the discharge flow rate of a pump, the discharge pressure of the pump, and an engine speed, thereby increasing the load torque of the engine to increase the temperature of the exhaust gas.


A flat nut is provided with a threadlike retainer cord and structure for self-drilling and slotting a wall to provide a suitable hole for insertion of the nut, and a screw to be threaded into the nut. The retainer cord provides for positioning the nut on the back side of the wall. The nut has an elongated drilling point for making a hole and serrated teeth along an elongated side for making horizontal slots on each side of the hole to accommodate the full width of the nut. The arrangement provides a simple way to fasten objects onto a wall without access to both sides.

The present invention generally relates to a blind fastening system for holding objects onto a modern gypsum wall. It is composed of a self-drilling and slotting fastener nut, a thin retainer cord, and a screw. The fastener nut is inserted through a slotted hole in a surface and held in alignment with the retainer cord for the insertion of a screw for fastening an object onto the surface. The fastener nut has a threaded hole and on the middle of the wide side and an elongated side. The elongated side is a little wider than the width of the threaded hole and has a drilling end. This elongated end is longer than the thickness of the wall and is used to drill a hole through the wall by manually turning the fastener nut. The elongated end also has a serrated side section for making slots on each side of the hole to provide a clean slotted hole in the wall for the full width of the fastener nut.
There are numerous fastening devices that all try to maximize the holding power the fastener exerts onto the back of the surface it is placed onto. The holding power is directly proportional to the amount of surface area that the fastener has on the inside face of the surface. The size of the opening in the surface needed for the insertion of the fastener is another factor in determining the holding power of a fastener. The smaller the hole the less damage the surface has and the stronger the surface is. It is of primary importance that a clean hole be made in the wall for the fastener to achieve maximum holding power. Many products attempt to achieve this, however they quite often fall short.
Some products have a flat wedge shaped fastener being driven through a wall and being used as a fastener. The problem with this device is that the back of the wall gets "blown-out". That is, the inside portion of the wall gets damaged and does not provide a clean flat surface for the fastener to rest against. In addition to the back surface the material between the front and back face of the wall gets damaged. Another problem is the insertion of the screw through the hole made by the wedge. The width of the screw is usually greater than the width of the wedge and also causes the back of the wall to become "blown-out". To avoid that, the width of the wedge would have to match the width of the screw, as shown on FIGS. 6 & 7. Having such a wide wedge only compounds the "blow-out" problem.
Other devices show a fastener that makes use of a flexible cord used to align a fastener nut with a matting screw. This type of system requires that a hole be drilled through the wall by a standard tool. The width of the fastener nut is also limited by the size of the hole made in the wall.
The fastening system described in this application maximizes the holding power by having almost the entire flat surface of the fastener against the inside face of the surface.
In addition to having a maximum of holding power and minimum wall damage, the system is simple to use and inexpensive to manufacture.

Self-drilling and slotting fastener system


An automatic coarseness setting method in a video display apparatus is provided. According to the automatic coarseness setting method, when an automatic adjustment command is input or when a new mode video signal is received to the video display apparatus, a pixel clock of an input video signal is detected, and a coarseness value is automatically set based on the detected pixel clock. Accordingly, it is possible to provide optimum video display using a coarseness value most suitable for the input video signal.

1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to automatically setting coarseness in a video display apparatus, and more particularly, to automatically setting coarseness in a video display apparatus when a video signal input from an external apparatus, such as a personal computer (PC), is displayed on a screen.
2. Description of the Related Art
FIG. 1 is a flowchart illustrating a related resolution setting method in a video display apparatus.
In FIG. 1, if a video signal is input from an external apparatus (S10), the video display apparatus may determine a resolution of the input video signal using a horizontal synchronizing signal (H Sync) and a vertical synchronizing signal (V Sync) of the input video signal (S11). The video display apparatus may also determine whether or not the resolution of the input video signal is equal to a preset resolution (S12). If it is determined that the resolution of the input video signal is equal to a preset resolution, the input video signal may be displayed on a screen based on the set resolution (S16).
If it is determined that the resolution of the input video signal is not equal to the preset resolution in operation S12, the video display apparatus may determine whether a resolution stored in the video display apparatus is equal to the resolution of the input video signal (S13). If it is determined that a resolution stored in the video display apparatus is equal to the resolution of the input video signal, the video display apparatus may convert the preset resolution into the resolution of the input video signal (S14), and may display the input video signal on the screen (S16).
Alternatively, if it is determined that a resolution stored in the video display apparatus differs from the resolution of the input video signal in operation S13, the video display apparatus may convert the present resolution into a resolution close to the resolution of the input video signal (S15), and may display the input video signal on the screen (S16). For example, if the input video signal has a resolution of 800*600 (62 Hz), and if a resolution of 800*600 (60 Hz) closest to the resolution is stored in the video display apparatus, the input video signal may be displayed on the screen at the resolution of 800*600 (60 Hz).
Accordingly, the horizontal (H) position, vertical (V) position and coarseness of the input video signal may deviate off the edge of the screen, and in the worst situation no video signal may be displayed on the screen. In order to solve the problems, the video display apparatus has an automatic setting function to automatically set the H position, V position and coarseness. When the automatic setting function is performed, the coarseness setting may differ according to the type of video signal.
FIGS. 2A and 2B are diagrams showing related video signals transmitted to the video display apparatus.
FIG. 2A is a normal timing diagram of an input video signal. The input video signal shown in FIG. 2A has 2240 pixel clocks for a single screen, and 1680 pixel clocks for an active area, in which video is currently displayed on the screen. Additionally, the H Sync of the input video signal has negative polarity, and the V Sync of the input video signal has positive polarity.
FIG. 2B is an offset timing diagram of an input video signal. Such an input video signal is generally used in a flat type video display apparatus. The input video signal shown in FIG. 2B has 1840 pixel clocks for a single screen and 1680 pixel clocks for an active area of the screen. The H Sync of the input video signal has positive polarity, and the V Sync of the input video signal has negative polarity.
The pixel clocks of the video display characteristics are used to convert a received analog video signal into a corresponding digital video signal, and are set as a coarseness value in the video display apparatus.
FIG. 3 is a flowchart illustrating an automatic coarseness setting method in a related video display apparatus.
In FIG. 3, if a user inputs an automatic adjustment command to the video display apparatus (S20), the video display apparatus may detect a pixel clock of the input video signal (S21), and may determine whether the pixel clock of the input video signal corresponds to a preset coarseness value (S23). If it is determined that the pixel clock of the input video signal differs from the preset coarseness value, the video display apparatus may determine whether the pixel clock of the input video signal is contained in a coarseness adjustment range (S25).
If it is determined that the pixel clock of the input video signal is contained in the coarseness adjustment range in operation S25, the preset coarseness value may be changed to a coarseness value corresponding to the pixel clock of the input video signal (S27). On the other hand, if it is determined that the pixel clock of the input video signal is not contained in a coarseness adjustment range in operation S25, the preset coarseness value may be changed to a default value (S29).
For example, assuming that the default value, minimum value and maximum value are set to 2240, 2160 and 2320, respectively, in a first coarseness adjustment range, if a coarseness value of 2150 is preset in the video display apparatus and if a pixel clock of an input video signal is set to 1900, the input video signal may be displayed on the screen at the default value of 2240 in the first coarseness adjustment range. Accordingly, a portion of the input video signal may deviate off the edge of the screen.
Alternatively, assuming that the default value, minimum value and maximum value are set to 1840, 1760 and 1920, respectively, in a second coarseness adjustment range, if a coarseness value of 1900 is preset in the video display apparatus and if a pixel clock of an input video signal is set to 2150, the input video signal may be displayed on the screen at the default value of 1840 in the second coarseness adjustment range. Accordingly, the input video signal may be displayed at a size smaller than the original size, without covering the entire screen.
If the input video signal is not in compliance with the Video Electronics Standards Association (VESA) standard, it is impossible to clearly distinguish whether an input video signal is applied with normal timing or with offset timing, so the above-described problems may be aggravated.

Automatic coarseness setting method in video display apparatus


A PSA mechanism has adsorption towers. Cleaning valves and off gas valves are connected to the adsorption towers. Valve positions of at least either the cleaning valves or the off gas valves are determined based on an operation suspension period of the PSA mechanism or internal conditions which vary depending on the operation suspension period.

1. Field of the Invention
The present invention relates to a fuel gas production apparatus for reforming a hydrogen-containing fuel into a reformed gas, and refining the reformed gas to produce a hydrogen-rich fuel gas. Further, the present invention relates to a method of starting operation of the fuel gas production apparatus.
2. Description of the Related Art
For example, hydrogen production apparatuses (fuel gas production apparatuses) for reforming a hydrocarbon fuel such as natural gas or a hydrogen-containing fuel such as an alcohol (e.g., methanol) into a hydrogen-containing gas (reformed gas), and refining the hydrogen-containing gas to produce a fuel gas supplied to a fuel cell or the like are adopted conventionally.
For example, Japanese Laid-Open Patent Publication No. 2002-20102 discloses a hydrogen production apparatus shown in FIG. 21. The hydrogen production apparatus includes a compressor 1, a hydrodesulfurization unit 2, a steam reformer 3, a catalyst combustor 4, a gas shift reactor 5, and a PSA (Pressure Swing Adsorption) unit 6. A fuel gas such as a city gas is supplied to the hydrodesulfurization unit 2. After desulfurization of the fuel, the steam reformer 3 reforms the fuel by steam reforming to produce a hydrogen-containing gas (hydrogen rich gas). The catalyst combustor 4 is provided around the steam reformer 3, and combusts the hydrogen and oxygen in the air using catalyst. The gas shift reactor 5 induces a shift reaction for converting carbon monoxide in the hydrogen-containing gas into carbon dioxide and hydrogen. After the gas shift reaction, the PSA unit 6 refines the hydrogen-containing gas into highly pure hydrogen by pressure adsorption.
A hydrogen storage tank 8 and an off gas holder 9 are connected to the PSA unit 6. The hydrogen storage tank 8 temporarily stores the highly pure hydrogen before it is supplied to a polymer electrolyte fuel cell (PEFC) 7. The off gas holder 9 temporarily stores the off gas (impurities) removed by pressure adsorption in the PSA unit 6. The off gas holder 9 supplies the off gas to the catalyst combustor 4 as a fuel for heating the steam reformer 3.
The PSA unit 6 has a plurality of adsorption towers filled with adsorbent material for selectively adsorbing impurities (components other than hydrogen) under high pressure, and desorbing the adsorbed components under low pressure. A series of steps comprising adsorption of impurities, desorption of impurities, replacement of the gas, and pressurization are performed in a cyclic manner in each of the adsorption towers for obtaining the highly pure hydrogen, and discharging the other gas components as the off gas.
For the purpose of interrupting operation of the hydrogen production apparatus, the PSA unit 6 stores interruption conditions of the respective towers in advance. Assuming that the PSA unit 6 has three adsorption towers, generally, two adsorption towers are stopped at high pressures, and the remaining one tower is stopped at a pressure substantially the same as, or lower than the air pressure. The pressure condition is maintained until operation of the hydrogen production apparatus is started again.
However, if operation of the hydrogen production apparatus is suspended for a long period of time, transition to the chemical equilibrium condition occurs in the towers at the high pressure, and the gas components tend to be distributed uniformly in the towers. Thus, when operation of the hydrogen production apparatus is started from the cleaning step, gas components of the cleaning gas moving between the towers may include a lot of impurity components such as a carbon dioxide gas or a nitrogen gas, though the chief gas component of the intended cleaning gas is the hydrogen gas. The impurity gas has a large pipe resistance in comparison with the hydrogen gas.
Therefore, the flow rate of the cleaning gas is reduced, and the amount of the discharged off gas is reduced. As a result, calorie shortage occurs for the capacity of the catalyst combustor 4, and the temperature of the catalyst combustor 4 decreases. In order to address the problem, it is necessary to provide additional fuel supply to the catalyst combustor 4.
Further, in the desorption step, a large amount of the off gas remaining in the towers is supplied to the catalyst combustor 4. Therefore, the catalyst combustor 4 may be heated to the excessively high temperature. Thus, thermal load is applied to the catalyst combustor 4 undesirably.

Fuel gas production apparatus and method of starting operation of fuel gas production apparatus


In plural channel amplifier systems processing many phase locked signals of different frequencies as a combined signal, these signals may drift into a phase convergence causing a peak power occurrence in the amplifier which greatly exceeds the rated capacity of the amplifier system. Therefore, in accord with the invention, a dynamic adjustment system is provided to minimize the peak power to which the amplifier is subjected by adjusting the relative phase relationships of the many signals. The dynamic adjustment system includes a peak power detector, a hard wired logic decision circuit and a timing control to control phase shift adjustment steps.

Wireless telecommunications systems are divided into a series of cell areas covering a service area. Each cell area has a transmitting base station using its own operating frequency set comprising a plurality of radio channels to communicate with mobile subscribers. Each channel represents an information signal at a particular frequency carrier or band.
It has been found advantageous to combine these channels for transmission purposes. The channels are all combined by a broadband signal combiner into a multi-channel signal at low power levels and then amplified by a single linear amplifier (or its equivalent a plurality of linear amplifiers in parallel, each amplifying a reduced power version of the same multi-channel signal) to raise the multi-channel signals to an appropriate transmit power level.
The various radio channels are distributed in frequency with respect to each other in that each operates within a different frequency band. Simultaneous occurrence of individual signal peaks readily occur and hence the multi-channel signal is subject to power maximums where the peak power significantly exceeds the average power of the envelope due to constructive addition of the individual signal peaks.
A straight forward response to this problem has been to select the power rating of the linear amplifier to accommodate the theoretical maximum peak power level of the composite multi-channel signal. However, this significantly increases the cost of the linear amplifier since its power rating must be increased in proportion to the square of the number of signals processed. This high power rating is also only needed for a small fraction of the operating time of the amplifier (that is, during the high peaks of the combined multi-channel signal). It is desirable to operate the system with amplifiers of power handling ratings based on the average power of the sum of the carriers than to require that an amplifier be rated to handle the extreme high peak power caused by the constructive addition of the individual carriers.

Circuitry for minimizing peak power in an amplifier carrying a plurality of signals of differing frequencies


Contact center agents often work in close proximity to other agents. As a primary agent is engaged in a call, a neighboring agent speech may be picked up by the primary agent's microphone. Contact centers using automated speech recognition systems may monitor the agent's speech for key terms and, if detected, respond accordingly. Determining a primary agent spoke a key term, when the true speaker of the key term is a neighboring agent, may cause errors or other problems. Characterizing at least the primary agent's voice and then, once a key term is detected, determining if it was the primary agent that spoke the key term, may help to reduce the errors. Additionally, computational requirements may be reduced as non-key terms may be quickly discarded and optionally, key terms determined to not have been spoke by the primary agent, may also be discarded without further processing.

Speech analytics is a group of methods often employed to automatically find keywords and/or phrases in telephone conversations. The finding of keywords and phrases is intended to provide useful information regarding speech content. Content may include topics, emotions, hold and periods of silence, and business intelligence. Speech analytics, such as Avaya Speech Analytics (ASA), are designed to improve accuracy of speech processing by mapping a form against phonemes. Other speech analytics may search frame by frame to match sounds and vectors.
In many contact centers, agents work in close proximity to one another. While noise cancelling headsets and other technology may be used to help reduce the extraneous sounds, a primary agent's microphone may pick up the voice of a neighboring agent which may be registered as coming from the primary agent's microphone. Contact centers often use speech recognition technology to respond to certain words spoken by an agent. If an agent's microphone picks up a keyword that was actually spoke by a neighboring agent, the system may respond erroneously.

Speech analytics with adaptive filtering


Methods for optimizing postural prism to be added to a pair of ophthalmic multifocal lenses (lenses) adapted to a wearer and to slow down myopia progression are described. The method includes an initial pair of lenses in a providing step S1. In a postural prism adding step S2, a same postural prism is added to each lens. In a gazing step S3, the wearer gazes at a first distance target through the lenses with the added postural prism. A gazing direction determining step S4 determines the wearer's gazing direction during S3. Steps S2 to S4 may be repeated while changing the added postural prism, wherein the added postural prism is smaller than or equal to a maximum prism value. Steps S2 to S4 may be repeated to determine the smallest added postural prism for which the wearer's gazing direction in step S4 passes through the first vision zone.

The discussion of the background of the invention herein is included to explain the context of the invention. This is not to be taken as an admission that any of the material referred to was published, known or part of the common general knowledge at the priority date of any of the claims.
It has been observed that some individuals, in particular children, focus inaccurately when they observe an object which is situated at a short distance away, that is to say, in near vision conditions. Because of this focusing defect on the part of a myopic child which is corrected for his far vision, the image of an object close by is also formed behind his retina, even in the foveal area.
To slow down myopia progression which is due to this focusing defect, it is known to use a myopia-correcting lens which is of the progressive multifocal ophthalmic lens type. An example of such progressive multifocal ophthalmic lens is disclosed in U.S. Pat. No. 6,343,861.
Such a progressive multifocal ophthalmic lens comprises a far vision area, in which the optical power of the lens is adapted to correct the myopia of the wearer when observing far/distant objects, a near vision area, in which the myopia correction is reduced, and an intermediate area which is situated between the far vision and near vision areas, and in which the optical power of the lens varies continually. Such progressive multifocal ophthalmic lenses are adapted for the foveal vision of the weaver.
It has been observed that the efficiency of such progressive multifocal ophthalmic lenses, and more generally the efficiency of myopia control lenses, is highly variable from one wearer to another.
One reason of such high variance is the improper use by the wearer of such myopia control lenses.
Indeed, as most myopic wearers of those lenses are not presbyopic, they do not require any change in power to clearly see near objects and can therefore use any part of a progressive multifocal ophthalmic lens to read or write.
It has been observed that some wearers do not use the proper part of the myopia control lens, in particular when carrying out near vision tasks, thus reducing the beneficial effect of such myopia control lens.
Therefore, there is a need to provide a method that helps the user use properly the myopia control lenses so as to increase the efficiency of such lenses.

Method for optimizing the postural prism of an ophthalmic lens

ESSILOR INTERNATIONAL (COMPAGNIE GENERALE D'OPTIQUE)


A power supply circuit of a low noise block converter (LNB) includes a plurality of output voltage regulators. A first output voltage regulator, a local oscillator circuit, a second output voltage regulator, and an LNA are connected in series in a direction in which a power supply current flows. Therefore, a voltage adjustment width of the output voltage regulator can be reduced and a power loss can be reduced. A value of current flowing in the power supply circuit can also be decreased. Accordingly, an LNB with a reduced power consumption can be realized.

1. Field of the Invention
The present invention relates to a low noise block down converter (abbreviated as LNB hereinafter) of a satellite broadcast receiver.
2. Description of the Background Art
FIG. 19 is a block diagram showing a configuration of a conventional satellite broadcast receiving system.
Referring to FIG. 19, a signal having a frequency of 11.70 GHz–12.75 GHz coming from a broadcast satellite 801 is received at an antenna 801. Antenna 801 is provided with an LNB 802. LNB 802 frequency-converts weak radio waves coming from the satellite into an IF signal of 1 GHz band, amplifies the signal with low noise, and then supplies the signal to a so-called digital broadcasting (DBS) tuner 804 connected thereto. DBS tuner 804 is supplied with a signal with low noise and at a sufficient level because of the operation of LNB 802.
DBS tuner 804 processes the IF signal supplied from a coaxial cable 803 using an internal circuit and supplies the signal to a television 805.
Radio waves are received at a satellite broadcasting antenna, and the signal is introduced to an indoor DBS tuner normally using a coaxial cable. However, the radio waves received at the antenna cannot be introduced indoors directly with the coaxial cable.
A metal tube called a waveguide is required to introduce the satellite broadcast radio waves having an extremely high frequency. The use of a waveguide is not realistic since a big hole has to be made on the wall to introduce the signal from the antenna to the indoor satellite broadcast receiver and in addition much attenuation occurs.
Therefore, an LNB installed at an antenna is normally used to convert a received signal down enough for a coaxial cable to introduce so that the signal is transmitted to an indoor DBS tuner. The indoor DBS tuner contains a scramble decoder, which descrambles the signal to display an image on a television as a display device.
FIG. 20 is a block diagram of the LNB in FIG. 19.
Referring to FIG. 20, an incoming signal of 12 GHz band is received at an antenna probe 3 in a feed horn 2, is then amplified with low noise in a low noise amplifier (LNA) 5, and thereafter passes through a bandpass filter 910 having a function of passing a desired frequency band and removing a signal of an image frequency band. Thereafter, the signal passed through bandpass filter 910 is mixed by a mixer circuit 11 with a local oscillation signal of 10.6 GHz from a local oscillator circuit 913 and is frequency-converted to an intermediate frequency (IF) signal of the 1 GHz band (1100 MHz–2150 MHz). The output of mixer circuit 11 is amplified in an intermediate frequency amplifier 15 to have appropriate noise characteristic and gain characteristic and is output from an output terminal 34 via a capacitor 17.
Output terminal 34 is supplied with a DC voltage exceeding for example 10V from a tuner arranged indoors via a coaxial cable. This DC voltage is applied to a power supply circuit 936 via a choke coil 32. Power supply circuit 936 down-converts the DC voltage applied from terminal 34 and supplies the voltage as down-converted to a predetermined stabilized voltage to LNA 5, local oscillator circuit 913 and intermediate frequency amplifier 15.
FIG. 21 is a circuit diagram showing a detailed configuration of LNB 900 shown in FIG. 20.
Referring to FIG. 21, power supply circuit 936 includes a voltage regulator 38 converting a DC voltage VS1 applied via choke coil 32 to a stabilized DC voltage VO1, and a multi-output voltage regulator 940 receiving DC voltage VO1 to output DC voltages VO2–VO8 lower than DC voltage VO1 and serving as an operating point of each circuit.
DC voltage VO8 is applied to the gate of a transistor 4 connected to the antenna probe in feed horn 2 as a gate bias voltage. DC voltage VO7 is applied to the drain of transistor 4. The drain of transistor 4 is coupled to the gate of a transistor 8 by a capacitor 6. For example, HEMT (High Electron Mobility Transistor) or the like can be used as the transistor.
Transistor 8 has its gate receiving DC voltage VO6 as a gate bias voltage and has its drain receiving DC voltage VO5.
Local oscillator circuit 913 includes a resistor 18 having its one end receiving DC voltage VO4, a transistor 20 having its collector connected to the other end of resistor 18, having its emitter grounded, and having its base receiving a bias voltage Vbias, and a capacitor 16 for transmitting a signal at the collector of transistor 20.
Mixer circuit 11 includes a transistor 14 receiving at its gate a signal from bandpass filter 10 and a capacitor 24 for transmitting a signal output from the drain of transistor 14 to the next stage. Transistor 14 receives DC voltage VO3 as a gate bias voltage at its gate. Transistor 14 also receives DC voltage VO2 at its drain.
Intermediate frequency amplifier 15 includes an amplifier 26 at the first stage receiving a signal via capacitor 24, a capacitor 28 for transmitting an output of amplifier 26, and a transistor 30 receiving at its base a signal via capacitor 28. DC voltage VO1 output from voltage regulator 38 is supplied to the collector of transistor 30, and the operating current passes from the collector to the emitter of transistor 30, is fed from the emitter to amplifier 26, and flows from amplifier 26 to a ground node.
Conventionally, these circuit elements require respective individual circuit currents, the total of which is a circuit current (consumption current) for a product. In order to reduce the product consumption current, the circuit current for each element has to be reduced or some circuit has to be omitted. However, it is not easy to reduce the consumption current by removing the currently used circuits each having a necessary function.
Therefore, power consumption is reduced by cascading amplifier elements within intermediate frequency amplifier 15 as described above. A prior art document for reducing power consumption in this manner includes Japanese Patent Laying-Open No. 5-48480.
This prior art reduces the consumption current by directly applying a DC voltage, separately from the other units, from an external source to an intermediate frequency amplifier at a lower frequency.
A reduced power consumption is also required in LNB. In the configuration shown in FIG. 21, since DC voltage VO1 output by voltage regulator 38 is a voltage high enough for any of DC voltages VO2–VO8 output by the multi-output voltage regulator, the multi-output voltage regulator needs to down-convert DC voltage VO1 by a considerable potential difference to generate each of these voltages. The down-conversion of the voltage causes much power loss in multi-output voltage regulator 940.

Low noise block down converter with reduced power consumption


A differential terminal 21a is connected to a branch line 33a which is provided in the main line close to the differential terminal 21a in the range from the intersection portion 39a to a start terminal on the line. A differential terminal 21b is connected to a branch line 37a which is provided in the main line close to the differential terminal 21b in the range from the intersection portion 39a to an end terminal on the line. A differential terminal 22a is connected to a branch line 33b which is provided in the main line close to the differential terminal 22a in the range from the intersection portion 39b to the start terminal. A differential terminal 22b is connected to a branch line 37b which is provided in the main line close to the differential terminal 22b in the range from the intersection portion 39b to the end terminal.

In a circuit which amplifies or latches a broadband high-frequency signal, in many cases, differential signals including a pair of signals Vin(+) and Vin(−) whose poralities are inverted each other are used. A differential circuit which amplifies or latches the differential signals includes differential input terminals or differential output terminals as a pair of differential terminals.
As such, when the differential circuit which transmit or receive the differential signals is formed on a semiconductor substrate by an integrated circuit (IC) technique, a differential distributed amplifier or a distributed logic circuit has been proposed as a method for obtaining broadband characteristics (Patent Documents 1 and 2).
These circuits have a structure in which the input and output terminals of a plurality of differential circuits that are arranged at regular intervals are connected in series to each other by a transmission line with high characteristic impedance. An artificial transmission line with a high cutoff frequency is formed by the input and output capacitances of the differential circuits and the inductance component of the transmission line. Therefore, it is possible to transmit the differential signals to a plurality of differential circuits in a wide band.
FIG. 16 is a diagram schematically illustrating an example of the layout of a differential distributed amplifier which is formed on a semiconductor substrate, in which a plurality of (in this example, four) differential amplifier circuits 1(1) to 1(4) are arranged in a line at predetermined intervals along the X-axis on a semiconductor substrate (not shown) made of, for example, InP (indium phosphorus) or GaAs (gallium arsenic), with the input and output terminals of all circuits aligned in the same direction. A differential signal transmission line 10 for inputting a signal to a differential amplifier circuit is formed along the X-axis so as to face a pair of differential input terminals 1a and 1b of each differential amplifier circuit and a differential signal transmission line 90 for outputting a signal from the differential amplifier circuit is formed along the X-axis so as to face a pair of differential output terminals 1c and 1d of each differential amplifier circuit.
The differential signal transmission line 10 includes a pair of main lines 11 and 15 which extend in parallel along the X-axis with a predetermined gap G therebetween. The main line 11 includes main line conductors 11b to 11f which are connected in series to each other and the main line 15 includes main line conductors 15b to 15f which are connected in series to each other. The main line conductor is a strip-shaped conductor (formed from metallic, e.g. gold alloy) whose characteristic impedance is arbitrarily set and is represented by a rectangle. A line connecting the main line conductors indicates the connection between the main line conductors. In addition, a branch point of the line is represented by a black circle and a terminal is represented by a white circle.
Differential signals Vin(+) and Vin(−) which are input to start terminals 11a and 15a of the main lines 11 and 15 are absorbed by termination resistors 14 and 18 connected to end terminals 11g and 15g of the main lines 11 and 15. The main lines 11 and 15 are connected to the differential input terminals 1a and 1b of the differential amplifier circuits 1(1) to 1(4) by branch lines 13a to 13d and 17a to 17d which extend along the Y-axis and have a predetermined length. The branch lines 17a to 17d and the main line conductors 11c to 11f intersect each other, with an insulating layer interposed therebetween.
Each of the main line conductors 11b to 11f and 15b to 15f is a transmission line with high characteristic impedance. For example, FIG. 17 shows an equivalent circuit of the structure in which each of the main line conductors 11b to 11f is connected to the differential input terminal 1a of each differential amplifier circuit. The inductance component L of the main line conductor and the parasitic capacitance C of the input terminal 1a form an artificial transmission line. The circuit is designed such that the inductance L and the capacitance C are optimized to obtain broadband transmission characteristics with a high cutoff frequency. In this case, the characteristic impedance of the artificial transmission line is set to be equal to the resistance value of the termination resistor 14.
In FIG. 16 which is a schematic diagram, the differential signal transmission line 90 has a structure which is reversed to the differential signal transmission line 10 which is on the differential input terminal side on the substrate (is obtained by rotating the differential signal transmission line 10 by 180 degrees). Differential output terminals 1c and 1d of each differential amplifier circuit are connected to the differential signal transmission line 90. In the differential distributed amplifier, the output signals which have been input from the differential signal transmission line 10 and then amplified by the differential amplifier circuits are combined with same phase on the differential signal transmission line 90 and signals Vout(+) and Vout(−), which are the amplified signals of the original input signals Vin(+) and Vin(−), are output.
The differential signal transmission line 90 includes a pair of main lines 91 and 95 which extend in parallel along the X-axis with a predetermined gap G′ therebetween. The main line 91 includes main line conductors 91b to 91f which are connected in series to each other from a start terminal (output terminal of the circuit) 91a and the main line 95 includes main line conductors 95b to 95f which are connected in series to each other from a start terminal 95a. The main lines 91 and 95 are connected to differential output terminals 1d and 1c of each differential amplifier circuit by branch lines 93a to 93d and 97a to 97d which extend along the Y-axis and have a predetermined length. The branch lines 97a to 97d and the main line conductors 91c to 91f intersect each other with an insulating layer interposed therebetween. The ends of the main line conductors 91f and 95f are connected to termination resistors 94 and 98, respectively.
Similarly to the input line, the output line is designed such that the inductance components of the main line conductors 91b to 91f and 95b to 95f and the parasitic capacitance of the differential output terminals 1c and 1d form an artificial transmission line with broadband characteristics. In this case, the characteristic impedance of the artificial transmission line is set to be equal to the resistance value of the termination resistor 94 or termination resistor 98.
The electrical lengths of the differential signal transmission lines 10 and 90 are optimized such that the signals input from the start terminals of the differential signal transmission line 10 are sequentially amplified by the differential amplifier circuits 1(1) to 1(4) while being propagated to the end terminals and the amplified signals are combined with same phase while being propagated to the start terminals (the output terminals of the circuit) of the differential signal transmission line 90.
As such, the differential distributed amplifier combines the output signals amplified by a plurality of differential amplifier circuits with same phase. Therefore, it is possible to amplify broadband differential signals with a high gain.


An expandable water trellis is provided including a plurality of hollow pipes of various lengths each having a pair of open ends and a plurality of linearly aligned water dispensers formed along a length thereof. Upon the flow of water within the pipe, water is dispensed through the dispensers for watering purposes. Also included is a plurality of caps each defined by a closed circular face with a periphery coupled thereto for defining an open top for removably securing about one of the open ends of one of the hollow pipes for selectively sealing the same. Next provided is a plurality of T-shaped interconnects each formed of a long tube with a pair of open ends and a short tube integrally coupled to a central extent of the long tube and extending perpendicularly therefrom thereby terminating in an open end which resides in fluidic communication with the open ends of the long tube. Each of the open ends is adapted to be releasably coupled to one of the open ends of one of the pipes in fluidic communication therewith. A plurality of elastomeric stoppers are defined by a portion of a cylinder. Each stopper is adapted to be removably situated within the open ends of the pipes for precluding the flow of water therethrough. A water source connector is included for releasaby connecting to a water source, whereby the water connector is releasably coupleable with the interconnects for supplying a water flow to the pipes.

1. Field of the Invention
The present invention relates to trellis systems and more particularly pertains to a new expandable-portable trellis systems with hydro application for constructing trellis structures of various sizes and shapes for encompassing a garden to water the same.
2. Description of the Prior Art
The use of trellis systems is known in the prior art. More specifically, trellis systems heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art trellis systems include U.S. Pat. No. 5,357,710; U.S. Des. Pat. No. 305,800; U.S. Des. Pat. No. 304,700; U.S. Des. Pat. No. 246,860; U.S. Pat. No. 4,048,752; and U.S. Pat. No. 4,869,018.
In these respects, the expandable-portable trellis systems with hydro application according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of constructing trellis structures of various sizes and shapes for encompassing a garden for watering the same.

Expandable-portable trellis systems with hydro application


Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide duplicate routing paths between source and destination of signals in the design. The duplicate paths are selected such that an SEU in a routing multiplexer included in each path simply switches the signal between the two paths. Thus, if one path is disabled due to an SEU, the other path can still provide the necessary connection, and the functionality of the design is unaffected. The methods can be applied, for example, to routing software for field programmable gate arrays (FPGAs) having programmable routing multiplexers controlled by static RAM-based configuration memory cells.

Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. For example, one type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAMs, processors, and so forth).
FPGA logic blocks typically include programmable logic elements such as lookup tables (LUTs), memory elements, multiplexers, and so forth. The LUTs are typically implemented as RAM arrays in which values are stored during "configuration" (i.e., programming) of the FPGA. The flip-flops, multiplexers, and other components are also programmed by writing configuration data to configuration memory cells included in the logic block. For example, the configuration data bits can enable or disable elements, alter the aspect ratios of memory arrays, select latch or flip-flop functionality for a memory element, and so forth. The configuration data bits can also interconnect the logic elements in various ways within a logic block by programming select values for multiplexers inserted in the interconnect paths within the logic block.
The various logic blocks are interconnected by a programmable interconnect structure that includes a large number of programmable interconnect lines (e.g., metal traces). The interconnect lines and logic blocks are interconnected using programmable interconnect points (PIPs). For example, a PIP can be implemented as a simple CMOS passgate. When the passgate is turned on, the two interconnect lines on either side of the passgate are electrically connected. When the passgate is turned off, the two interconnect lines are isolated from each other. Thus, by controlling the values on the gate terminals of the passgates, circuit connections can be easily made and altered. The value controlling each passgate is also stored in a configuration memory cell.
FIG. 1 shows an exemplary implementation of a routing path between a source logic block (LB) 101 and a destination logic block 102. In the PLD of FIG. 1, each interconnect line (103-107) is driven by an associated programmable routing multiplexer (113-117, respectively). In some PLDs, interconnect line 103 is driven by a driver or multiplexer included in source logic block 101, i.e., multiplexer 113 is omitted. The path between the source 101 and destination 102 logic blocks traverses multiplexer 113, interconnect line 103, multiplexer 114, interconnect line 104, multiplexer 115, interconnect line 105, multiplexer 116, interconnect line 106, multiplexer 117, and interconnect line 107.
FIG. 2 shows one possible implementation of routing multiplexer 116 of FIG. 1, in which routing multiplexer 116 includes a 4-input multiplexer 201 controlled by two configuration memory cells MC1 and MC0. The values stored in configuration memory cells MC1 and MC0 select one of the input signals IN0-IN3 to be passed to the output node OUT. (In the present specification, the same reference characters are used to refer to terminals, interconnect lines, nodes, and their corresponding signals.) In the pictured example, input terminal IN1 of multiplexer 201 is coupled to interconnect line 105 of FIG. 1. The other input terminals IN0, IN2, IN3 are coupled to other interconnect lines (not shown). Configuration memory cells MC1 and MC0 store low and high values, respectively, selecting the signal on interconnect line 105 to be passed to the output node OUT through input terminal IN1. The output node OUT is coupled to interconnect line 106 of FIG. 1.
Routing multiplexers typically include more than four input signals, but four input signals are shown in FIG. 2, for clarity. The number of configuration memory cells controlling the multiplexer depends at least in part on the number of input signals to the multiplexer.
In FPGAs, configuration memory cells are typically implemented as static RAM (random access memory) cells. Each FPGA typically contains many thousands or even millions of these static RAM configuration memory cells.
When bombarded by high-energy particles, a static RAM cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. These inadvertent and undesired state changes are known as "single event upsets", or SEUs. Sometimes an SEU has no effect on the functionality of the design. At other times, an SEU can change the function of an FPGA such that the circuit implemented in the FPGA no longer functions properly.
For example, if a static RAM cell controlling a passgate changes state, but the two interconnect lines on either side of the passgate are not used in the design, this change of state has no effect on the function of the circuit. Similarly, a change of state in a memory cell in an unused LUT has no effect. However, when SEUs occur in portions of the FPGA that are in use, the SEUs can result in loss of function for the design implemented in the FPGA.
In some applications, such as space-based applications in a low-earth orbit, it is important to minimize the effects of SEUs in PLD-based (e.g., FPGA-based) designs. SEUs can also be a concern in some earth-based systems, e.g., systems in high altitude locations. One method of mitigating and minimizing these effects is "triple modular redundancy", or TMR, in which three copies of a circuit are included in a design. Any two copies of the circuit can override output from the third copy, if it generates data different from the other copies. While useful in many applications, implementing a circuit using TMR requires about three times as many programmable resources as a standard implementation.
Therefore, it is desirable to provide methods other than TMR that will reduce the susceptibility to SEUs of a PLD design.

Using redundant routing to reduce susceptibility to single event upsets in PLD designs


An exposure apparatus which irradiates a photosensitive agent applied to a substrate to form a latent image pattern on the photosensitive agent. The exposure apparatus includes a substrate stage which drives the substrate, a focus measurement unit which obliquely irradiates the substrate with measurement light to measure the position of the substrate in the direction of the axis of the exposure beam on the basis of the light reflected by the substrate, and a controller which executes a calibration for correcting, on the basis of the measurement result obtained by the focus measurement unit, a track plane of the substrate stage with reference to the reference plane of the focus measurement unit so as to set the track plane parallel to the reference plane.

In manufacturing an electronic device, such as a semiconductor device, a reduction projection exposure apparatus, which reduction-projects a circuit pattern formed on a reticle (original plate) onto a wafer (substrate) coated with a photosensitive material (resist) to form a latent image pattern on the photosensitive agent, is applied.
In recent years, the mainstream of an exposure apparatus is a scanning exposure apparatus (scanner) as an improved product of a stationary exposure apparatus (stepper), which executes full-plate exposure of a reticle pattern for a shot region. The scanning exposure apparatus drives by scanning a reticle and a wafer with respect to an exposure beam formed into a slit shape through a slit to transfer a circuit pattern of the entire reticle onto the wafer. Since the stationary exposure apparatus executes full plate exposure for the shot region, it is difficult for this apparatus to perform focus/tilt correction within the shot. However, since the scanning exposure apparatus executes scanning exposure, it can follow a variation in local surface shape within the shot. This has a merit of averaging distortion in the scanning direction of a projection optical system.
As the degree of integration of semiconductor devices increases, a projection optical system of an exposure apparatus is demanded to realize a higher resolving power. In order to satisfy this demand, the wavelength λ of an exposure beam for use must be shortened, or the numerical aperture NA must be increased. The resolution is given by k1·λ/NA (k1 is a process constant). A higher resolution requires highly accurate focusing. The focus margin {d=k2·λ/NA2} becomes smaller year by year, and additionally, severe demands are imposed on components associated with focusing.
Typical factors of defocus caused in scanning exposure can be, for example, (1) a pattern offset measurement error which occurs due to a wafer having an asymmetric shape, such as a thickness variation or poor reproducibility in stage scanning, (2) a correction residue for an environmental factor, such as air fluctuations, a variation in air pressure, or a temperature variation, (3) a temporal variation in a measurement optical system, and (4) a correction residue for the lens aberration or exposure history due to exposure heat.
Three planes, i.e., the image plane (this image plane will also be referred to as the lens image plane hereinafter), in which a projection optical system forms a reticle image, the track plane (this scanning plane will also be referred to as the stage scanning plane hereinafter) of a predetermined portion (typically, the surface of a wafer chuck) of a moving wafer stage, and the reference plane (this reference plane will also be referred to as the OPTF reference plane hereinafter) of a compound-eyed focus sensor in an oblique incidence measurement optical system, which measures the focusing direction (Z direction) are not kept parallel to each other. This is a primary factor, which induces defocus in exposure.
The stage scanning plane largely varies upon reset, and its reproducibility decreases, so calibration must be performed so as to set the stage scanning plane parallel to the lens image plane or OPTF reference plane in reset. The variation in stage scanning plane upon reset is caused because the origin reproduction position of the stage is hard to stabilize. As the stage scanning plane varies upon reset, the stage scanning plane is set without being parallel to the lens image plane or OPTF reference plane.
Japanese Patent Laid-Open No. 2001-15422 discloses a technique for correcting the track of a stage driven along a polynomial surface of an N order function to the scanning plane expressed by linear components (plane). To cope with this, the amount of change in stage position in the focusing direction upon driving the stage is measured in advance to generate a correction table, thereby calculating the stage scanning plane with reference to the correction table. In the technique disclosed in Japanese Patent Laid-Open No. 2001-15422, in measurement for correction table generation, a wafer is arranged on the stage to measure the position of the wafer plane in the Z-axis direction.


A programmer for implantable stimulation devices and surface ECG system in wireless communication with each other. A self-powered ECG monitor with conventional surface electrodes transceives signals from and to a programmer provided with a radio frequency transceiver to eliminate hardwiring between the surface electrodes and the programmer. The system reduces the need for supply line frequency filtering and isolation circuitry to protect against high voltage defibrillation shocks.

The ongoing clinical care provided to patients with implantable cardiac device systems often includes the use of surface electrocardiograms (ECG). An ECG is a highly useful diagnostic aid for clinicians for the study of heart rate and rhythm. The ECG indicates the propagation of low amplitude electrical signals, commonly referred to as the cardiac impulse, across the myocardium giving information about depolarization and repolarization characteristics of the heart.
An ECG typically receives signals from a plurality of electrodes (3, 5, and 12 are common numbers) that are placed on the patient's skin surface. The ECG monitors voltage signals appearing between various pairs of the electrodes and performs a vector analysis of the resultant signal pairs to prepare various two-dimensional voltage-time graphs indicative of internal cardiac activity. Surface ECG refers to placement of electrodes on the surface, or skin, of the patient as opposed to directly to cardiac tissue which obviously requires an invasive procedure.
A programmer is a device that enables a clinician to telemetrically communicate with an implantable cardiac device such as pacemaker or defibrillator. Implantable devices often monitor and record a variety of internal physiological parameters of the patient and are often provided with a telemetry system to telemetrically transmit those measured and recorded parameters outside the patient's body. Implantable devices are also often capable of receiving telemetric signals to induce the device to set or change a variety of operational parameters of the device as well as to select among the physiological parameters that the device monitors and records. These parameters are often desirably changed during the implantation period to adjust the therapy provided and/or physiological parameters monitored in order to provide the attending clinician with different information or to adapt the therapy to a more efficacious regimen. It is highly desirable to set these parameters without the expense and health risks to the patient of an invasive procedure. The programmer enables the attending clinician to perform these tasks in a non-invasive, telegraphic manner.
A surface ECG is often used along with the programmer as the surface ECG provides additional information above that provided by the internal measurements obtained by the implantable device. The programmer is typically adapted to obtain a surface ECG through a special cable that generally interconnects the programmer to electrodes placed on the patient. As the programmer is thus electrically coupled to the patient, it is subject to exposure to electromagnetic interference (EMI) that may surround the interconnection. The programmer is also potentially subject to large common-mode 50/60 Hz (supply line frequency) signals that are picked up by the patient's body. Both EMI and common-mode signals degrade the accuracy of the ECG signal.
An additional concern in certain applications where defibrillation may be applied to the patient is the relatively large amplitude (hundred volt to kilovolt range) shocks that are typically applied to interrupt the fibrillation. These high voltage shocks can be conducted through other cabling interconnecting the patient and other equipment such as programmers. Accordingly, the front-end electronics (those directly in contact with the cabling) of the programmer generally require voltage protection adequate to prevent damage from up to 5000V that may be applied to the patient as defibrillation. The inclusion of such protection circuitry increases the cost and complexity of programmers.
The interconnection cable employed in prior art programmers with surface ECG systems presents some further difficulties in use for the clinician and for the patient. The cable is physically attached to the patient and impairs their movement in bed and can become entangled with bedding, I.V. tubes, etc. The cables also physically interconnect the programmer to the patient and thus present a physical obstacle that must be avoided by people moving in the room. The cables present a tripping hazard as well as a potential cause of upset and damage to the programmer or other devices that may be placed on tables or carts.
Another disadvantage of present programmer/ECG systems is that the clinician must physically connect the programmer to surface electrodes with the interconnection cable each time he visits a new patient. Often an individual programmer is not available for each patient due to cost considerations and the clinician must move a single programmer with him as he visits patients. It can be appreciated that disconnecting and reconnecting the cables each time a clinician visits a patient consumes the doctor's valuable time as well as presents a cause of wear and tear on the cables and connectors.
From the foregoing it can be appreciated that there is an ongoing need for a programmer/ECG system that reduces the need for obtrusive and hazardous cables. There is also a need for a system that facilitates movement of the clinician from patient to patient in different locations and maintains the functionality of programmers in communication with surface ECGs without the expense of providing a dedicated programmer at each patient location.

Programmer and surface ECG system with wireless communication


Systems, methods, and devices detect and managing the presence of bursty interference on a wireless communication system. A method of detecting the presence of bursty interference on a wireless network includes receiving, at a wireless device, a message from a transmitting device. The method further includes determining whether the message includes errors caused by bursty interference. The method further includes suspending a channel tracking when bursty interference is detected. The method may further include reporting bursty interference to the transmitting device when bursty interference is detected.

1. Field
The present application relates generally to wireless communications, and more specifically to systems, methods, and devices for detecting and managing interference in wireless networks.
2. Background
In many telecommunication systems, communications networks are used to exchange messages among several interacting spatially-separated devices. Networks may be classified according to geographic scope, which could be, for example, a metropolitan area, a local area, or a personal area. Such networks may be designated respectively as a wide area network (WAN), metropolitan area network (MAN), local area network (LAN), or personal area network (PAN). Networks also differ according to the switching/routing technique used to interconnect the various network nodes and devices (e.g., circuit switching vs. packet switching), the type of physical media employed for transmission (e.g., wired vs. wireless), and the set of communication protocols used (e.g., Internet protocol suite, SONET (Synchronous Optical Networking), Ethernet, etc.).
Wireless networks are often preferred when the network elements are mobile and thus have dynamic connectivity needs, or if the network architecture is formed in an ad hoc, rather than fixed, topology. Wireless networks employ intangible physical media in an unguided propagation mode using electromagnetic waves in the radio, microwave, infra-red, optical, etc. frequency bands. Wireless networks advantageously facilitate user mobility and rapid field deployment when compared to fixed wired networks.
When there are multiple users of a wireless network, to avoid collisions and loss of data, the network may provide a procedure for coordinating access to the wireless medium. In some instances, collisions may occur, causing interference among the various network devices. Improved methods and systems for reducing loss of data in a network with a large number of users are desirable.

Systems and methods for detecting or signaling the presence of bursty interference on wireless networks


A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

1. Field
Example embodiments relate to semiconductor devices and methods of manufacturing the same. More particularly, example embodiments relate to methods of manufacturing semiconductor devices by a selective epitaxial growth (SEG) process and semiconductor devices manufactured by the methods.
2. Description of the Related Art
A semiconductor device may include source/drain regions adjacent to gate structures. Such source/drain regions may include epitaxial layers formed, e.g., by a SEG process. In order to perform the SEG process only on a given region of a substrate, a capping layer having a long incubation time may be used.


At least one embodiment is directed to a semiconductor voltage controller comprising: a start-mode circuit associated with a start-mode; and an off-mode circuit associated with an off-mode, where the voltage controller can be configured to receive a feedback signal and an off-mode signal from a single input and provide an output voltage, where the voltage controller can be configured to be in the off-mode when the feedback signal is less than a skip level and the feedback signal is less than a HV control level, and where the voltage controller can be configured to be in start mode when the feedback signal is greater than HV control level and Vcc is below a Vcc-start.

The present application is a continuation application of U.S. patent application Ser. No. 13/362,186 filed on Jan. 31, 2012, by Jean-Paul Louvel, titled "METHOD OF FORMING A SWITCHED MODE POWER SUPPLY CONTROLLER DEVICE WITH AN OFF MODE AND STRUCTURE THEREFOR" which is hereby incorporated by reference in its entirety, and priority thereto for common subject matter is hereby claimed.
The present invention relates, in general, to electronics, and more particularly, to semiconductors, structures thereof, and methods of forming semiconductor devices.
Current switch mode power supply controllers seek to maintain an output voltage level within a range (e.g., within Vcc-stop and Vcc-start), and send drive signals to regulate voltage within the range. Such regulation occurs whether an initially applied load changes or not, for example if initially there can be a load voltage on the system, the system will regulate the output voltage to provide the load voltage. However if conditions change so that there can be no longer any load for period of time, typical controller systems are unable to provide an off mode that allows the output voltage to drop outside of the range while there can be little load voltage and to quickly provide regulation again when a load can be redetected. If an off-mode can be provided typically its implementation requires an additional pin to a chip configuration that prohibits a simple plug and play implementation with existing pin connections, thus making such solutions difficult to implement in unmodified systems.
Accordingly, it can be desirable to have a method of providing an off-mode in a power controller where the semiconductor configuration does not require any additional pins to implement the off-mode.

Method of forming a switched mode power supply controller device with an off mode and structure therefor

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC


A driver assembly for driving fasteners into a workpiece comprises a multilobular fastener engaging portion for engagement in a complementary multilobular socket or recess on a fastener. Each lobe is bounded on opposite sides by a flute, and each lobe includes a driving side wall and a trailing tapered side wall. The driving side walls are adapted to contact the complementary lobular portions of the fastener for applying torque to the fastener, while the trailing tapered side wall is aligned to contact the complementary lobular portion in wedged engagement at a point when the fastener is applied to the fastener portion. A fastener socket is also provided having a driven side wall and a trailing tapered side wall, which is constructed substantially similarly to the tapered side wall of the drive bit and which provides similar attributes.

The present invention relates generally to a novelly constructed and configured drive system for driving fasteners into a workpiece, and for attaining wedged engagement between a driver and a fastener such that the fastener will be frictionally retained on the end of the driver. More specifically, the invention as illustrated relates to a novel drive bit and drive socket for use with a TORX.RTM. drive system.
Fasteners are a critical component of most structures and mechanisms, from the simplest machine to the highly complex space shuttle. Because of the critical functions performed by these fasteners, improvements in their structure and functional properties are continually sought. One such improvement is the TORX.RTM. drive system, which can be employed, for example, in a drive socket or on a head portion of a fastener, or on a drive bit or socket used for driving such a fastener into a workpiece.
The construction and benefits of the TORX.RTM. drive system are disclosed in U.S. Pat. No. 3,584,667 to Rieland, assigned to the assignee of the present invention. The disclosure of the '667 patent is incorporated herein by this reference. The TORX.RTM. drive represents a significant improvement in the fastener industry.
One such application of the TORX.RTM. drive system is disclose in the patent to Larson et al., U.S. Pat. No. 4,269,246. This patent is also assigned to the assignee of the present invention, and the disclosure thereof is incorporated herein by reference. Specifically, the drive bit of the '246 patent provides means for providing a wedging effect between the bit and a fastener for holding fasteners on the drive bit when the bit is inserted into a recess or socket on the fastener, thereby facilitating one-handed installation of fasteners into a workpiece. This one-handed installation is highly desirable for use in some applications of fasteners where a large number of fasteners are to be installed or inserted into a workpiece, or a plurality of workpieces, such as on an assembly line. This type of frictioned engagement is also desirable where it is preferred to use non-magnetic drives and fasteners. Additionally, the particular construction of the '246 patent helps to prevent "walking" or "wobble" of a fastener, which can cause damage to a workpiece. This "walking" or "wobble" is particularly acute when a pilot hole is not used or during manual installation of self-tapping or self-drilling screws. The drive bit is also self-aligning, which provides significant benefits when utilizing drill screws.
Even though the fastener and the drive bit or assembly provided by the '246 patent are quite effective, there is always room for further improvements and refinements. Specifically, it is to be noted that the drive bit of the '246 patent has a three degree taper on a major diameter thereof. This means that the drive bit makes contact with the fastener at a top of the fastener socket into which the bit is inserted. More definitely, the contact between the bit and the fastener socket occurs at outer, leading edges of lobes on the bit and a center of flutes in the socket. The bit wedges across a major diameter of the bit. Accordingly, the above-discussed wedging effect theoretically occurs at six contact "points," equal in number to the number of flutes and lobes, between the bit and the socket. Because wedging between the bit and the socket occurs only at outside edges of the lobes of the drive bit, high magnitude mechanical stresses can build up at these limited locations. This stress concentration can cause excessive bit wear, as well as loss of dimensional tolerances.
Furthermore, because of the limited contact between the bit and the fastener, a natural tendency arises causing the bit to cam out of the socket in the fastener. Accordingly, there is a potential that the effective lifetime of the drive bit will suffer a reduction, viz. a reduction in ability to prevent wobble, as well as a reduction in the integrity of an interference fit between the bit and the fastener which can make one-handed manual installation more difficult. Additionally, variations in socket fall away, as measured across the major diameter of the socket, which may be difficult to eliminate, can adversely affect depth of penetration of the drive bit into the socket, thereby adding variability of insuring sufficient bit penetration into the socket for driving of the fastener.
A drive system, constructed according to the teachings of the present invention, provides a multilobular drive system which can be embodied in a drive bit, a drive socket, a fastener head post or a fastener socket, which will improve upon the structural and functional characteristics of the drive assembly provided by the above-referenced '246 patent. Specifically, the drive bit of the present invention is configured to wedge in a fastener socket across lobes, between side walls thereof, of the bit. To do this, back-side edges of the lobes of the bit, opposite to the sides thereof which drivingly contact edges of the flutes of the socket, are tapered such that a thickness of the lobes increases from the socket entering end towards the shank of the bit. In this manner, the bit of the invention contacts the socket along the six driving side walls of the bit lobes and the six engaged side walls of the socket flutes, and also contacts the socket at six points proximate the top thereof defined by the engagement between the tapered back-side walls of the bit lobes and the socket flutes, opposite to the engaged side walls thereof. The invention can be employed on a fastener head post in similar fashion.
The multilobular fastener socket of the invention is configured to wedgingly accept a drive bit within flutes, between opposite side walls thereof, of the socket. Specifically, back-side edges of the lobes of the socket, which also define edges of the socket flutes, opposite to the sides thereof which are drivingly contacted by driving edges of the lobes of the drive bit, are tapered such that a width of the socket flutes slopingly decreases, thus causing the thickness of the socket lobes to correspondingly increase, from the socket mouth to the base of the socket. Thus, the socket is contacted by the bit along six driven side walls of the socket flutes, and also at six points proximate the socket base defined by the engagement between the tapered back-side walls of the socket flutes, opposite to the driving side walls thereof, and sides of the bit lobes opposite to the sides thereof in driving engagement with the socket.
It should be noted that engagement at all six lobes, or however many are employed in the multilobular design, is the theoretical maximum. Due to tolerances and wear during use, engagement may occur only at two of three of the drive lobes. Also, while the present invention is illustrated and described with regard to the hexlobular TORX.RTM. drive system, it is applicable to other types of multilobular drive systems.


Body surface potential map (BSPM) pace-mapping is a system and method that can be used in medicine to localize with precision the site of origin of abnormal cardiac electrical activity and to guide the positioning of a catheter over this site of origin, such as the site of ventricular preexcitation in patients with the Wolff-Parkinson-White syndrome or the focus of ectopic activity in patients with tachycardia. Body surface potential distributions are measured with a large number of electrodes, e.g. 24 to 128, distributed over the entire torso surface. The electrical signals are first amplified, converted into digital data and treated to remove electrical or muscle artifacts. Data recorded during abnormal activation (reference beat) are aligned with data recorded during cardiac pacing (paced beat) so as to maximize the average value of the correlation coefficient between the reference and the paced potential distributions during a preset time interval following the beginning of the QRS complex. Reference and paced maps showing color-coded isopotential contour lines are displayed side by side for the same time instant. Visual analysis of these maps according to previously published criteria determines the relative position of the pacing catheter with respect to the focus of abnormal activation, and gives information so as to guide the catheter toward the focus.

1. Field of the Invention
The present invention relates to medical instruments and the field of cardiac electrophysiology, and more particularly to the localization of foci of abnormal cardiac activation by comparative analysis of body surface potential distributions during cardiac pacing.
2. Description of the Related Art
The contraction of the human heart is triggered by an electrical process known as an "action potential" which depolarizes the transmembrane potential of the myocardial cells. This depolarization process is automatic (i.e. an isolated cardiac cell can show repeated action potentials) and also, it propagates from one cell to the neighboring cells. In the normal heart, activation originates from the cells having the fastest ation potential frequency which are located in the sino-atrial (SA) node. The activation propagates from the SA node to the rest of the atria, and then to the ventricles through the atrioventricular (AV) node, which slows down propagation so as to permit the flow of blood from the atria to the ventricles, and then through the His bundle and the Purkinje conduction system which synchronizes the ventricular activation.
Congenital heart diseases or complications following coronary artery disease can produce an abnormal increase of the heart rate known as tachycardia which can be potentially lethal. In patients with the Wolff-Parkinson-White (WPW) syndrome (a congenital disease), an additional conduction pathway joins the atria and the ventricles and this accessory AV pathway can either be responsible for the continuous activation of the ventricles during atrial tachyarrhythmias, or create a reentrant circuit in which activation propagates repeatedly through the ventricles, the accessory AV pathway, the atria, the AV node and the ventricles again. In patients with idiopathic ventricular tachycardia or in patients with ventricular tachycardia (VT) resulting from myocardial infarction, the abnormal activation originates during VT from a circumscribed region of the ventricles with abnormal automaticity and/or propagation properties.
These disorders of the heart rhythm may be cured by the catheter ablation of the arrhythmogenic sites, either the accessory AV pathways or the sites of origin of VT. See: W. M. Jackman et al., "Catheter ablation of accessory atrioventricular pathways, Wolff-Parkinson-White syndrome, by radiofrequency current", New Engl J Med 324:1605, 1991; L. S. Klein et al., "Radiofrequency catheter ablation of ventricular tachycardia in patients without structural heart disease", Circulation 85:1666, 1992. Catheter ablation consists of inserting a catheter percutaneously through veins or arteries inside the heart cavities. The tip of the catheter is placed near the arrhythmogenic site. Electromagnetic energy is then delivered to the myocardium by electrodes or antennas located at the catheter tip. Electromagnetic energy can be used within a wide frequency spectrum ranging from DC current to radiofrequency current, microwave and laser light. The effects of this localized energy delivery is to destroy the arrhythmogenic site and to create a small permanent lesion.
One of the problems with the catheter ablation of arrhythmogenic sites is the duration of the procedure. This procedure is long because cardiologists rely on electrograms recorded with electrodes located near the catheter tip to guide the positioning of the catheter within millimeters of the arrhythmogenic site. On these electrograms, the timing of the local activation deflexion or the presence of accessory pathway potentials can only indicate if the catheter tip is near or far from the arrhythmogenic site, and if it is far, it does not indicate in which direction to move the catheter.
Information about the location of the arrhythmogenic site can be obtained from body surface potential maps (BSPM). As ventricular activation progresses away from the accessory AV pathway or from the VT site of origin, the activation currents generate electrical potentials that can be measured over the torso surface by a large number of electrodes. For WPW patients, Benson et al. (Benson et al., "Localization of the site of ventricular preexcitation with body surface potential maps in patients with the Wolff-Parkinson-White syndrome", Circulation, 65:1259, 1982) correlated the patterns of BSPM recorded during the preexcitation of the ventricles through the accessory AV pathway (delta wave) with the preexcitation sites determined by electrophysiologic studies or surgical ablations and they concluded that at least seven preexcitation sites could be predicted by analysis of the BSPM patterns. Similar patterns were reported by Nadeau et al. (Nadeau et al. "Localization of preexcitation sites in the Wolff-Parkinson-White syndrome by body surface potential mapping and a single moving dipole representation". In Electrocardiographic body surface potential mapping Eds R. T. van Dam, A. van Oosterom, Martinus Nijhoff, pp: 95-98, 1986) in patients who underwent arrhythmia surgery and/or an electrophysiologic study. The latter also noted the progressive changes in the morphology of the BSPM recorded during the delta wave in patients with adjacent preexcitation sites, thus reflecting the continuous distribution of possible accessory AV pathways around the AV ring with the position of the minimum and of negative potentials on the BSPM identifying the pathway location: prominent negativity on the right side of the anterior torso correspond to patients with preexcitation sites located in the right ventricle; a minimum on the back correspond to sites in the left ventricle; negativity over the entire lower torso correspond to posteroseptal sites; otherwise, positivity over the entire lower torso correspond to anterior sites. Similarly, for the localization of sites of origin of VT, Sippens-Groenewegen et al. (Sippens-Groenewegen et al., "Body surface mapping of ectopic left and right ventricular activation. QRS spectrum in patients without structural heart disease", Circulation, 82:879, 1990) reported BSPM patterns obtained during ventricular pacing at known sites and which can be used to estimate the site of origin of ectopic activity.
Another approach to the localization of abnormal cardiac activation which uses electrocardiographic potentials consists of comparing the standard twelve-lead electrocardiogram (ECG) during ventricular pacing at different sites, with the ECG recorded during abnormal ventricular activation (pacing consists of initiating the activation process of the ventricles by applying a small current pulse between the electrodes of a catheter located inside the ventricles). This "pace-mapping" approach relies on the visual analysis of twelve time-varying signals. It can confirm that the pacing catheter is located over the focus of abnormal activation when the paced ECG and the abnormal ECG are identical (because the cardiac activation that generates these two ECGs are localized at the same site). However, it gives only limited information about which direction to move the catheter toward the focus when the two ECG are not identical. See: Josephson et al., "Ventricular activation during ventricular endocardial pacing. II. Role of pace mapping to localize origin of ventricular tachycardia", Am J Cardiol 50:11, 1982.
The Patent literature also provides teachings which are of interest having regards to the invention as described and claimed in the following, for example, U.S. Pat. No. 4,974,598, John, Dec. 4, 1990, U.S. Pat. No. 5,083,565, Parins, Jan. 28, 1992, U.S. Pat. No. 5,069,215, Jadvar et al, Dec. 3, 1991, U.S. Pat. No. 4,751,931, Briller et al, Jun. 21, 1988 and U.S. Pat. No. 4,641,649, Walinsky et al, Feb. 10, 1987.
The teachings of the '598 patent relate to early detection of heart disease with an EKG system which detects heart beats having P, Q, R, S, T and U portions. A large number of electrodes (32 to 64) are placed on the torso of the patient. Readings taken are subjected to statistical analysis and compared with readings of a normal population.
In the '565 patent, an electrosurgical catheter includes a sensor for sensing the polarization signals developed in the heart and for transmitting the sensed signals to an external EKG monitor. It also includes insulated tips to which an RF signal may be applied to destroy selected cells.
A disposable esophageal electrode structure, as taught in the '215 patent, includes a plurality of spaced apart conductive electrode members. Each electrode is connected to a wire by which it is connected to external electrical units.
In the '931 patent, surface electrodes are positioned on the surface of the patient's body in the heart area of the patient. Surface ECG's acquired are enhanced by filtering and then subjected to method steps for detecting low level bioelectric signals.
The '649 patent teaches a method for selective ablation of cardiac tissues by high frequency electromagnetic energy. A catheter, which is introduced into a patient's heart chamber, is terminated by an antenna. Depolarization signals are coupled by the antenna to an ECG monitor for display. External electrodes also detect potentials which are displayed on the monitor. Accordingly, the position of the antenna is adjusted to an appropriate position for ablation procedures.

Comparative analysis of body surface potential distribution during cardiac pacing


An O-ring has a flange which includes a plurality of slots, such that, when inserted into an annular groove of a pipe fitting before crimping, the slots allow the flow of fluid therethrough, such that an installation would not pass pressure tests until such time as a proper crimp has been made. Such a design allows the use of conventional push-on pipe connections by utilizing a unique O-ring seal which works in conjunction with standard push-on crimp-type pipe fittings and conventional crimping tools for subsequently sealing the connection. The O-ring is either circular or elliptical in cross section and the slots define equally spaced annular segments.

The present invention relates to plumbing fittings and particularly to seals for crimp connections between fittings.
In recent years, crimp-on connections have replaced the typical solder connection in copper and other metallic plumbing systems used in homes and industrial applications. Typically, the female pipe fitting will include an annular groove into which an O-ring is positioned and a male fitting inserted through the O-ring and the annular groove subsequently crimped to provide a tight seal. When numerous such connections are made in a plumbing system, particularly in large commercial installations, not infrequently crimps are missed. Frequently, O-ring seals which have not been crimped will initially pass pressure tests but, over time, will leak if the junction is not properly crimped.
There is a need, therefore, for a system which will purposely leak at a connection which has been made but not properly crimped. There have been several attempts at solving this problems, including, for example, providing frangible bands around crimp fittings which, until crimped, remain in place but, once crimped, the typically plastic ring fractures and reveals the fact that the crimp has been made. Some attempts have been made also to provide specialized O-ring designs which purposely allow leakage until such time as a proper crimp has been made.