Disclosed is a peak hold circuit wherein output current corresponding to the peak value of input current is obtained for input currents with little change in magnitude, at essentially higher speeds. Detected drain current and input current of a P-MOS FET are compared, a first reference potential is applied to an NPN transistor, and a second reference potential lower than the first reference potential by a predetermined voltage such that the NPN transistor and a PNP transistor are not simultaneously turned on, is applied to the PNP transistor. In the event that the detected current is greater than the drain current, the NPN transistor is turned on and the PNP transistor is turned off, in the event that the detected current is smaller than the drain current, the NPN transistor is turned off and the PNP transistor is turned on, and in the event that the detected current and the drain current are equal, the NPN transistor and the PNP transistor are both turned off.

1. Field of the Invention
The present invention relates to a peak hold circuit, and particularly relates to a current mode peak hold circuit wherein output current corresponding to the peak value of input current can be obtained even for input currents with little change in magnitude, at essentially higher speeds.
2. Description of the Related Art
An example of a conventionally-known peak hold circuit wherein output voltage corresponding to peak values of input voltage can be obtained is shown in FIG. 25. The voltage of the non-inverting input terminals of an operational amplifier 2502 (equal to the voltage VH held by a capacitor 2507) is initially equal to the voltage VIN1 of the non-inverting input terminals of an operational amplifier 2501.
Thus, the voltage of the output terminal of the operational amplifier 2502, the voltage of the inversion input terminal of the operational amplifier 2501, and the voltage of the output terminal of the operational amplifier 2501 are VH which is VIN1, the voltage at both ends of the diodes 2503 and 2504 are zero, with the diodes 2503 and 2504 being in a non-conducting state.
In this state, even in the event that the voltage of the input terminal 2508 rises and reaches VIN2, the diode 2503 is in a non-conducting state, so the output voltage of the operational amplifier 2501 rises greatly regardless of the negative feedback. Then, when forward voltage is applied to the diode 2504 an the diode 2504 is in a conducting state, the capacitor 2507 is charged, the voltage at both ends of the capacitor 2507 rises, and in the same manner, the voltage of the output terminal 2509 of the operational amplifier 2502 and the voltage of the inverted input terminals of the operational amplifier 2503 rise.
Then, at the point that the voltage at both ends of the capacitor 2507 is equal to the voltage VIN2 of the output terminal 2509 of the operational amplifier 2501, the diode 2504 enters a non-conducting state, and consequently, the voltage VIN2 is held by the capacitor 2507.
In the event that the voltage of the input terminals 2508 drops and changes from VIN2 to VIN3 in this state, while the output voltage of the operational amplifier 2501 drops, the voltage at both ends of the capacitor 2507 (i.e., the held voltage VH) is VIN2, so inverse voltage is applied to both ends of the diode 2504, so the diode 2504 remains in a non-conducting state, and the held voltage VH remains unchanged at VIN2.
Thus, voltage corresponding to the peak value of he input voltage of the input terminals 2508 is output at the output terminal 2509.
However, such voltage mode peak hold circuits are configured of multiple operational amplifiers, diodes, capacitors, and so forth, so the circuit tends to become large in size.
Also, the circuit is arranged so as to make input to the peak hold circuit shown in FIG. 25 following converting the input current into voltage values with a current/voltage converting circuit, so there is a limit to how far the size of the circuit can be reduced, and the circuit has not been able to be reduced in size any further.
A known example of a peak hold circuit which has solved such problems is described in Japanese Patent Application No. 10-5449. This peak hold circuit is known as a current mode peak hold circuit, and has a configuration such as shown in FIG. 26.
FIG. 26 will now be described. This current mode peak hold circuit is configured of P-MOS transistors 2601 and 2602, an NPN transistor 2603, and a PNP transistor 2607. The gates of the P-MOS transistors 2601 and 2602 are connected in common, and the sources are connected to the electric power source VDD. The P-MOS transistor 2601 has the drain thereof connected to the terminal 2604, and the NPN transistor 2602 has the drain thereof connected to the terminal 2606. The collector of the NPN transistor 2603 is connected to the gates of the P-MOS transistor 2601 and 2602 connected in common, the emitter thereof is connected to the drain of the P-MOS transistor 2601, and the base is connected to a reference potential VBIAS1. The emitter of the PNP transistor 2607 is connected to the drain of the P-MOS 26501, the base the base is connected to a reference potential VBIAS2, and the collector is grounded.
The reference potential VBIAS1 and the reference potential VBIAS2 are lower than the voltage of the electric power source VDD but higher than the ground potential, are a potential such that the NPN transistor 2603 and the PNP transistor 2607 do not turn on simultaneously, and the difference potential between the reference potential VBIAS1 and the reference potential VBIAS2 is 0.7 V, for example.
In FIG. 26, V4(t) represents the absolute potential of the terminal 2604 at time t, iD1(t) represents the drain current of the P-MOS transistor 2601 at time t, iin(t) represents input current at time t, and iout(t) is output current at time t, with the direction of the arrows being the forward direction for each. Note that iout(t) matches the drain current of the P-MOS transistor 2602.
(1) Let us say that the P-MOS transistor 2601 is operated at saturation range, and the drain current iD1(t) and input current iin(t) of the P-MOS transistor 2601 match. In this state, the potential of the terminal 2604 is generally the average potential of the two reference potentials VBIAS1 and VBIAS2, the voltage between the base and emitter of the NPN transistor 2603 and PNP transistor 2607 are both around 0.35 V, and both the NPN transistor 2603 and PNP transistor 2607 are in the cut-off state.
In the event that the input current iin(t) increases over a period from time t0 to time t1 as shown in FIG. 27A for example, the relation between the drain current iD1(t) and input current iin(t) of the P-MOS transistor 2601 becomes that represented by iD1(t) less than iin(t), and the voltage of the terminal 2604 drops.
The PNP transistor 2607 maintains the cut-off state, but at the point that the voltage of the terminal 2604 drops around 0.5 V as to the reference potential VBIAS1, the NPN transistor 2603 enters the forward activation range and begins to cause current to flow, and at the point that the voltage of the terminal 2604 drops around 0.7 V as to the reference potential VBIAS1, the NPN transistor 2603 turns on.
At the point that the NPN transistor 2603 turns on, the difference current between the input current and the drain current iD1(t) of the P-MOS transistor 2601, i.e., iin(t)xe2x88x92iD1(t), flows from the node 2605 to the terminal 2604 via the NPN transistor 2603, and the voltage of the node 2605 drops so that the input current iin(t) and the drain current iD1(t) of the P-MOS transistor 2601 are equal. The voltage drop of this node 2605 is generated by charge being extracted from the parasitic capacity between the gate sources of the P-MOS transistors 2601 and 2602 connected to the node 2605, via the NPN transistor 2603. At this time, the peak hold circuit shown in FIG. 26 acts as a current mirror circuit, and output current proportionate to the input current is obtained (see FIG. 27B).
(2) In the event that the increase of the input current iin(t) stops over a period from time t1 to time t2 as shown in FIG. 27A for example, iD1(t) =iin(t), and the NPN transistor 2603 and PNP transistor 2607 are both in the cut-off state, so the voltage of the terminal 2604 rises, and the voltage of the terminal 2604 settles down at around the average potential of the two reference potentials VBIAS1 and VBIAS2. At this time, the node 2605 is in a high-impedance state, so the charge at time t1 at the parasitic capacity between the gate sources of the P-MOS transistors 2601 and 2602 does not change.
On the other hand, the voltage between the gate sources of the P-MOS transistors 2601 and 2602 is maintained at VGS(t1), and output current iout(t) proportionate to the input current iin(t1) at time t1 is maintained (see FIG. 27B).
(3) In the event that the input current iin(t) at time t is smaller than the input current iin(t1) at time t1 in a period from time t2 to time t3 as shown in FIG. 27A for example, voltage of the terminal 2604 further rises, but the NPN transistor 2603 maintains the cut-off state, so the voltage VGS(t1) between the gate sources of the P-MOS transistors 2601 and 2602 is maintained, and the value of the output current iout(t) at time t1 is maintained. Then, at the point that the voltage of the terminal 2604 rises around 0.7 V as to the reference potential VBIAS2, the PNP transistor 2607 enters the forward activation range and turns on, and the difference current between the drain current iD1(t) of the P-MOS transistor 2601 and the input current, i.e., iD1(t)xe2x88x92iin(t), in other words the difference current between the input current at time t1 and the input current at time t, i.e., iin(t1)xe2x88x92iin(t), flows.
(4) In the event that current exceeding the current iin(t1) at time t1 is input in a period from time t3 to time t4 as shown in FIG. 27A for example, and the current continues to increase, the voltage of the terminal 2604 drops, and at the point that the voltage of the terminal 2604 drops around 0.5 V as to the reference potential VBIAS1, the NPN transistor 2603 enters the forward activation range again and begins to cause current to flow, and at the point that the voltage of the terminal 2604 drops around 0.7 V as to the reference potential VBIAS1, the NPN transistor 2603 turns on.
At the point that the NPN transistor 2603 turns on, the difference current between the input current and the drain current iD1(t) of the P-MOS transistor 2601, i.e., iin(t)xe2x88x92iD1(t), flows from the node 2605 via the NPN transistor 2603, and the voltage of the node 2605 drops so that the input current iin(t) and the drain current iD1(t) of the P-MOS transistor 2601 are equal.
Thus, output current iout(t) corresponding to the peak value of the input current iin(t) is obtained.
On the other hand, a current mode peak hold circuit co the configuration shown in FIG. 28 is known. The current mode peak hold circuit shown in FIG. 28 is an arrangement wherein conductor types of the components corresponding to those of the current mode peak hold circuit shown in FIG. 26 are reversed, and is configured of N-MOS transistors 2811 and 2812, a PNP transistor 2813, and an NPN transistor 2817.
The gates of the N-MOS transistors 2811 and 2812 are connected in common, the sources are grounded, the N-MOS transistor 2811 has the drain thereof connected to the terminal 2814, and the N-MOS transistor 2812 has the drain thereof connected to the terminal 2816. The collector of the PNP transistor 2813 is connected to the gates of the N-MOS transistor 2811 and 2812 connected in common, the emitter thereof is connected to the drain of the N-MOS transistor 2811, the base is connected to the reference potential VBIAS1. The emitter of the NPN transistor 2817 is connected to the drain of the N-MOS transistor 2811, the base is connected to the reference potential VBIAS2, and the collector thereof is connected to the electric power source VDD.
The reference potential VBIAS1 and the reference potential VBIAS2 are lower than the potential of the electric power source VDD but higher than the ground potential, are a potential such that the NPN transistor 2813 and the PNP transistor 2817 do not turn on simultaneously, and the difference potential between the reference potential VBIAS1 and the reference potential VBIAS1 is 0.7 V, for example.
In FIG. 28, V14(t) represents the absolute potential of the terminal 2814 at time t, iD11(t) represents the drain current of the N-MOS transistor 2811 at time t, iin(t) represents input current at time t, and iout(t) is output current at time t, with the direction of the arrows being the forward direction for each. Note that the output current iout(t) matches the drain current of the N-MOS transistor 2812.
(1) Let us say that the N-MOS transistor 2811 is operated at saturation range, and the drain current iD11(t) and input current iin(t) of the N-MOS transistor 2811 match, the potential of the terminal 2814 is generally the average potential of the two reference potentials VBIAS1 and VBIAS2, the voltage between the base and emitter of the PNP transistor 2813 and NPN transistor 2817 are both around 0.35 V, and both the PNP transistor 2813 and NPN transistor 2817 are in the cut-off state.
(2) In the event that the input current iin(t) increases over a period from time t0 to time t1 as shown in FIG. 29A for example, the relation between the drain current iD11(t) and input current iin(t) of the N-MOS transistor 2811 becomes that represented by iD11(t) less than iin(t), so the voltage of the terminal 2814 rises. At this time, while the NPN transistor 2817 maintains the cut-off state, but at the point that the voltage of the terminal 2814 rises around 0.5 V as to the reference potential VBIAS1, the PNP transistor 2813 enters the forward activation range and begins to cause current to flow, and at the point that the voltage of the terminal 2814 rises around 0.7 V as to the reference potential VBIAS1, the PNP transistor 2813 turns on.
The current iin(t)xe2x88x92iD11(t) flows to the node 2815 via the PNP transistor 2813 so that iin(t) and iD11(t) match, and the voltage of the node 2815 rises.
The voltage of this node 2815 rises due to charge being supplied to the parasitic capacity between the gate sources of the N-MOS transistors 2811 and 2812 connected to the node 2815, via the PNP transistor 2813. At this time, the peak hold circuit shown in FIG. 28 acts as a current mirror circuit, and output current proportionate to the input current is obtained.
(3) In the event that the increase of iin(t) stops over a period from time t1 to time t2, iD11(t)=iin(t), and the voltage of the terminal 2814 drops so that both PNP transistor 2813 and NPN transistor 2817 reach cut-off, and settles down at around the average potential of the two reference potentials VBIAS1 and VBIAS2. At this time, the node 2815 is in a high-impedance state, so the charge at time t1 does not change, and the voltage between the gate sources of the M-MOS transistors 2811 and 2812 is maintained at VGS(t1). Here, the output current iout(t) is maintained at a current proportionate to the input current iin(t1) at time t1.
(4) In the event that the input current iin(t) at time t is smaller than the input current iin(t1) in a period from time t2 to time t3, voltage of the terminal 2814 further drops, but the PNP transistor 2813 maintains the cut-off state, so VGS(t1) is maintained, and output current iout(t) maintains the value at time t1. At this time, in the event that the voltage of the terminal 2814 drops around 0.7 V as to the reference potential VBIAS2, the NPN transistor 2817 enters the forward activation range and turns on, and a current of iD(t)xe2x88x92iin(t), i.e., iin(t1)xe2x88x92iin(t), flows.
(5) In the event that current exceeding the input current iin(t1) at time t1 is input in a period from time t3 to time t4, and the current continues to increase, the voltage of the terminal 2814 rises, and at the point that the voltage of the terminal 2814 rises around 0.5 V as to the reference potential VBIAS1, the PNP transistor 2813 enters the forward activation range again and begins to cause current to flow, and at the point that the voltage of the terminal 2814 rises around 0.7 V the PNP transistor 2813 turns on.
Then, the current iin(t)xe2x88x92iD11(t) flows to the node 2815 via the PNP transistor 2813, and the voltage of the node 2815 rises so that iin(t) and iD11(t) are equal. Thus, output voltage iout(t) corresponding to the input current iin(t) is obtained. Accordingly, output current corresponding to the peak value of the input current is obtained at the output terminal 2816.
However, in the event that operating the peak hold circuit shown in FIG. 26 with little change in magnitude at higher speeds is attempted, the following problems have occurred.
As described above, the voltage V4(t) of the terminal 2604 repeats rising and dropping according to the input current, and under the above-described bias conditions, the change in voltage thereof is around 0.7 V, as shown in FIG. 30.
On the other hand, there is parasitic capacity at the terminal 2604 such as junction capacitance of the connected devices, so charging and discharging to this parasitic capacity must be performed in order for the terminal 2604 to perform the above-described voltage change, and the charge for charging and discharging is supplied by the difference current between the input current iin(t) and the held current, i.e., with the drain current iD11(t) of the N-MOS transistor 2601.
Accordingly, in the event that the magnitude of change of the input current is small and the speed is high, sufficient charge necessary for voltage fluctuations is not supplied to the parasitic capacity of the terminal 2604, and the peak holding action does not work.
On the other hand, when attempting to operate the peak hold circuit shown in FIG. 28 with a small magnitude of change of the input current at higher speeds, the following problems have resulted.
As described above, the voltage V14(t) of the terminal 2814 repeats rising and dropping according to the input current, and under the above-described bias conditions, the fluctuation in voltage thereof is around 0.7 V, as shown in FIG. 31.
On the other hand, there is parasitic capacity added at the terminal 2814 such as junction capacitance of the connected devices, so charging and discharging to this parasitic capacity must be performed in order for the terminal 2814 to perform the above-described voltage fluctuations, and the charge for charging and discharging is supplied by the difference current between the input current iin(t) and the held current, i.e., with the drain current iD11(t) of the N-MOS transistor 2811.
Accordingly, in the event that the magnitude of change of the input current is small and the speed is high, sufficient charge necessary for voltage fluctuation is not supplied to the parasitic capacity of the terminal 2814, and the peak holding action does not work.
Accordingly, it is an object of the present invention to solve the above-described problems, and to provide a current mode peak hold circuit wherein output current corresponding to the peak value of input current can be obtained even for input currents with little change in magnitude, at essentially higher speeds.
The peak hold circuit according to a first aspect of the present invention comprises: a current mirror circuit for generating a first constant-current source for causing flow of a current that is the same magnitude as an input current from an input terminal, and a second constant-current source for causing flow of a current that is the input current multiplied by a predetermined multiplication factor; a first FET wherein the drain thereof is connected to the first constant-current source and the source thereof is connected to a first electric power source; a second FET wherein the drain thereof is connected to an output terminal and the source thereof is connected to the first electric power source and the gate thereof is connected in common with the gate of the first FET; a two-stage serial circuit comprising first and second transistors having complementary properties, provided between the gates connected in common and a second electric power source which has lower voltage than the first electric power source, wherein the nodes of the first and second transistors are connected to the drain of the first FET; current detecting means for detecting the drain current of the first FET; and applied voltage control means which compare a current which is a drain current detected by the current detecting means multiplied by the predetermined multiplication factor, with a current which is the input current from the second constant-current source multiplied by the predetermined multiplication factor, and applies a first applied voltage which is lower than voltage of the first electric power source to the first transistor, and also applies to the second transistor a second applied voltage which is constantly lower than the first applied voltage by a predetermined voltage wherein the first and second transistors are not simultaneously turned on, wherein, in the event that the detected current detected by the current detecting means is greater than the drain current of the first FET, the first voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor on, and the second voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off, and in the event that the detected current is smaller than the drain current, a third voltage lower by the first voltage by a predetermined voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and a fourth voltage lower by the second voltage by a predetermined voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor on, and further in the event that the detected current is equal to the drain current, an averaged voltage of the first voltage and the third voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and an averaged voltage of the second voltage and the fourth voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off.
A capacitor for holding charge may be connected between the gates of the first and second FETs connected in common and the first electric power source. The peak hold circuit may also further comprise switching means for setting the potential of the gates of the first and second FETs connected in common to the potential of the first electric power source.
Also, the first and second FETs may be P-MOS FETs, the first transistor may be an NPN transistor, and the second transistor may be a PNP transistor. Or, the first and second FETs may be P-MOS FETs, the first transistor may be an N-MOS transistor, and the second transistor may be a P-MOS transistor.
The peak hold circuit according to a second aspect of the present invention comprises: a current mirror circuit for generating a first constant-current source for causing flow of a current that is the same magnitude as an input current to an input terminal, and a second constant-current source for causing flow of a current that is the input current multiplied by a predetermined multiplication factor; a first FET wherein the drain thereof is connected to the first constant-current source and the source thereof is connected to a second electric power source with lower voltage than a first electric power source; a second FET wherein the drain thereof is connected to an output terminal and the source thereof is connected to the second electric power source and the gate thereof is connected in common with the gate of the first FET; a two-stage serial circuit comprising first and second transistors having complementary properties, provided between the gates connected in common and the first electric power source, wherein the nodes of the first and second transistors are connected to the drain of the first FET; current detecting means for detecting the drain current of the first FET; and applied voltage control means which compare a current which is a drain current detected by the current detecting means multiplied by the predetermined multiplication factor, with a current which is the input current from the second constant-current source multiplied by the predetermined multiplication factor, and applies a first applied voltage which is higher than voltage of the second electric power source to the first transistor, and also applies to the second transistor a second applied voltage which is constantly higher than the first applied voltage by a predetermined voltage wherein the first and second transistors are not simultaneously turned on, wherein, in the event that the detected current detected by the current detecting means is greater than the drain current of the first FET, the first voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor on, and the second voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off, and in the event that the detected current is smaller than the drain current, a third voltage higher than the first voltage by a predetermined voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and a fourth voltage higher than the second voltage by a predetermined voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor on, and further in the event that the detected current is equal to the drain current, an averaged voltage of the first voltage and the third voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and an averaged voltage of the second voltage and the fourth voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off.
A capacitor for holding charge may be connected between the gates of the first and second FETs connected in common and the second electric power source. The peak hold circuit may further comprise switching means for setting the potential of the gates of the first and second FETs connected in common to the potential of the second electric power source.
Also, the first and second FETs may be N-MOS FETs, the first transistor may be a PNP transistor, and the second transistor may be an NPN transistor. Or, the first and second FETs may be N-MOS FETs, the first transistor may be a P-MOS FET, and the second transistor may be an N-MOS FET.
Further objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments with reference to the attached drawings.


A lightweight integral corrosion-resistant front-end structure (“front-end structure”) includes a one-piece composite structure, a metal insert, and a series of washers. The one-piece composite structure is formed from a polymer-composite with a washer fluid reservoir, a tray, and/or a wheel housing. The metal insert is coated with the one-piece composite structure and isolated from corrosive substances. The metal insert is attached to a radiator support member and/or a hood pivot member. The washers offset the metal insert from the radiator support member and/or hood pivot member so as to eliminate a galvanic potential. The washers are attached to the metal insert by the one-piece composite structure.

Existing inner fender structures include a high number of steel stampings that are individually fixtured and welded together. Typically, these parts support a battery, washer fluid reservoir, air cleaner, splash shields, and fenders. The high part count can require significant in-plant processing and thus require substantial assembly time, labor, and cost. Also, steel parts can add significant weight to the vehicle and adversely affect its performance.
It is desirable to provide a lightweight, integral, corrosion-resistant front-end structure that enhances vehicle performance, minimizes assembly time, decreases labor, and reduces costs associated therewith.

Lightweight integral corrosion-resistant front-end structure for a vehicle


A single integrated circuit for multiple vehicle voltage regulator applications is inexpensive, programmable and responsive to mixed signals. The integrated circuit provides both analog and digital functions, and uses a single voltage comparator serving all comparator functions. A variety of features are included with the single integrated circuit in order to permit the programmable, mixed signal and multiple application characteristics of the device. Among the features are the provision for a single voltage comparator that serves all comparator functions, logic gates for preventing the simultaneous activation of fixed reference divider analog switches to eliminate current transients, the use of a single TC diode for thermal shut down and multiple temperature compensation curves with different voltage versus temperature rate of change parameters, a single band gap referenced shunt regulator circuit to serve as both a power source to the integrated circuit and as a precision reference voltage for the comparator, and a selectable load control function to gradually apply the field voltage at a programmable rate consisting of reversible and "up" binary counters with associated logic to prevent abrupt torque loads on the driving engine caused by the activation of electrical loads.

With the proliferation of voltage regulator designs, manufacturers and suppliers of compatible voltage regulators are faced with high engineering and tooling costs to accommodate each distinct application. This situation is further complicated by the uncertainty of the need for a particular design, or whether an investment in any design will provide an adequate return. A solution to this dilemma is a design that fulfills a large number of different specialized requirements with a single circuit, with the further advantage of a one time investment in engineering and tooling costs.
One of the key objectives of this invention is a diversified circuit design that will accommodate a variety of voltage regulator applications without compromising individual quality or functionality of each application, while also enhancing reliability. An advantage of providing a single multi-application integrated circuit is that the probability of receiving a return of investment is greatly enhanced in that the cost can be amortized over a greater number of applications.
The following are prior United States patents which are pertinent to the present invention.
______________________________________ U.S. Pat. No. Issue Date Inventor ______________________________________ 4,143,313 3/1979 Arendt 4,266,181 5/1981 Muto et al. 4,315,205 2/1982 Muri et al. 4,360,773 11/1982 Voss 4,412,169 10/1983 Dell'Orto 4,435,676 3/1984 Morishita 4,459,489 7/1984 Kirk et al. 4,470,003 9/1984 Mitcheil 4,561,036 12/1985 Morishita et al. 4,563,631 1/1986 Mashino et al. 4,629,967 12/1986 Voss 4,629,968 12/1986 Butts et al. 4,636,705 1/1987 Bowman 4,636,706 1/1987 Bowman et al. 4,642,548 2/1987 Mashino 4,672,297 6/1987 Gotoh et al. 4,680,530 7/1987 Mashino 4,727,307 2/1988 Kaneyuki et al. 4,760,323 7/1988 Nadi 4,812,732 3/1989 Iwatani 4,831,322 5/1989 Mashino et al. 4,839,576 6/1989 Kaneyuki et al. 4,914,374 4/1990 Iwatani et al. 4,937,514 6/1990 Iwatani et al. 4,945,277 7/1990 Iwatani et al. ______________________________________
Attention is given to U.S. Pat. No. 4,636,706 to Bowman et al. This patent teaches a varible duty cycle field excitation waveform which is generated with a down counter periodically loaded with an up-down counter, and with the magnitude of the duty cycle being proportional to the "up" count in the up-down counter. The magnitude of the up count in the up-down counter is transferred into a down counter, the time it takes for the down counter to count down from its orignal value to zero being the duration of the "on" time that the field is excited in relation to the master cycle time.
In contrast, this invention uses a reversible counter in conjunction with a simple binary up counter with the up counter requiring fewer components than the down counter of the prior art. The magnitude of the field excitation is stored in the reversible counter as a down count, and the down count is transferred into the up counter. The time duration of the up counter counting up to zero determines the field excitation duty cycle.
As also discussed in the Bowman et al '706 patent, alternator speed control is obtained by a conventional frequency counter with a fixed time base circuit. This has the disadvantage of eroneously lighting the vehicle warning lamp for at least the duration of the fixed time base if the voltage regulator operation is interupted for some reason.
The circuit design of the present invention measures the time between the successive pulses provided by the alternator stator phase output. These time measurements are compared to a reference time to determine the speed of the alternator. As successive pulse measurement is incorporated, the time required for an accurate measurement is vastly shorter than the frequency counter, therefore, interruptions to this voltage regulator result in an imperceptible flashing of the warning lamp (in the order of microseconds) that is undetectable by the driver.
In the Bowman et al '706 patent, a linear series power supply which is switched on or off is used to provide reference voltages and digital circuit power. In this arrangement, the series pass transistor must absorb the excess voltage and voltage transients requiring a relatively large pass transistor. In switching the digital circuits on and off, inadvertent noise can simulate a switched condition, resetting the digital circuitry resulting in an erroneous flashing of the warning lamp.
In this invention, a shunt voltage regulator is used with the excess voltage and transients being absorbed by a resistor. The digital circuitry is designed using a "no false state allowed" rule that eliminates the need for a master reset. Thus, the circuit design of this invention only switches either on or off, only the peripheral input/output circuitry which unconditionally emulates the turn on or turn off characteristics of the prior art. With said digital circuitry operating continuously and with the lack of false states, this invention is immune to noise induced problems. As the digital circuitry is of CMOS construction the standby current requirements are essentially negligible.
In the Bowman et al, '706 patent, temperature compensation is accomplished with a chip external temperature compensation element. Such elements requiring trimming as an extra production item.
In contrast, this invention accomplishes temperature compensation of varying selectable slopes with a single "on-the-chip" diode. The characteristics of this diode are fixed in the mask of the chip, and avoid the requirement for trimming during manufacture. This diode is also used to shut down the peripheral drive circuits in the event that the alternator operational temperature exceeds a predetermined limit, thereby preventing catastrophic failure.
In the Bowman et al '706 patent, as with other of the cited patent references, a plurality of analog voltage comparators are used to accommodate the various functions required by each specific application. This plurality of comparators also requires individual trimming for each added comparator.
This invention uses a single analog comparator equipped with digitally switched inputs and outputs, which affords the advantage of having only one comparator to trim during the manufacturing operation. The scanning frequency of this comparator is substantially greater than the expected operational speed for any application of the voltage regulator, thereby producing an effective average voltage of each parameter measured. The Bowman et al circuit requires the use of separate analog and digital integrated circuits, whereas, this invention requires a single chip, representing a major saving in manufacturing costs.
The Bowman et al invention also requires different integrated circuits to accommodate different voltage regulator functions. This invention incorporates many different functions that can be selected by different wiring configurations of the respective data inputs. Thus, a relatively inexpensive change to the surface mount ceramic artwork need be only done to accommodate a variety of different applications.
Giving attention to U.S. Pat. No. 4,636,705 to Bowman, there is disclosed a complex voltage doubling scheme to provide the required biasing inherent to typical power MOSFET transistors.
This invention employs two high voltage on-chip FET transistors, three on-chip resistors, one diode, and one capacitor with a feed forward refresh pulse technique to provide adequate biasing required by a Power MOSFET transistor, which is achieved at far lower cost in terms of required circuit elements
Giving attention to U.S. Pat. No. 4,672,297 to Gotoh et al, this patent relates to the use of a single diode connected to the junction of the field winding and the field driver transistor. Moreover, by using this diode, an inadvertent short from the output of this diode to ground prevents a full field voltage condition that overexcites the alternator, causing possible damage to the vehicle's electrical loads. However, this diode is also subject to positive battery shorts, and this short condition is made more likely by the extensive use of non-conductive materials in the modern automobile. Such a short to a positive voltage conductor or terminal, either caused by wear or by the process of troubleshooting by an unaware mechanic, may cause excessive current to flow through the now forward-biased diode and through the field driver transistor. The magnitude of the current may be destructive to the field driver transistor, causing a flash through short, causing the damage that Gotoh intended to avoid.
This invention adds a redundant field driver FET transistor that inherently limits the shorted diode current to a safe value. As the addition of this redundant transistor isolates the main drive transistor from any accessible terminal, the shorting of the output diode either to ground or to the positive battery source allows the normal field driver circuitry to operate non-disturbed. As the added redundant FET field driver transistor has inherent current limiting, the removal of the inadvertent short would permit the operation of this circuit to return to normal with no damage.
Attention is given to U.S. Pat. No. 4,831,322 Mashino et al, which discloses another method for generating the high voltages required to operate an N-channel power MOSFET in the common source configuration. The technique disclosed by Mashino et al uses four capacitors, three diodes, a resistor, and five inverters to generate the bias voltage. This circuit is essentially a voltage doubler in which the output is buffered and gated with a ramp generator. This circuit also includes a complex feedback circuit consisting of a differential amplifier, a redundant field MOSFET with current sensing and associated components to track the field driver power MOSFET to the ramp generator. One disadvantage of a circuit of this type is that all the above components are operated at or near twice the battery voltage. If the effects of voltage transients are taken into consideration and in particular, in a vehicle where the battery terminals are corroded, the circuit is susceptible to high voltage breakdown unless expensive components were used. Further, in such a circuit arrangement, the bias voltage generation is independent of the field switching action.
In this invention, the bias voltage generation results directly from the field switch action, achieving a more efficient use of components. Only the essential components are operated at or near twice the battery voltage level to greatly lessen the probability of high voltage transient breakdown. The components that are operated at or near twice the battery voltage receive further protection by the inclusion of current limiting series resistors.

Multiple application voltage regulator system and method


There are disclosed a method and an apparatus for removing a cover from a golf ball. There is used a pair of geared rolls in an engaged manner, each geared roll comprising a cylindrical shaft on which teeth are axially formed and are circumferentially arranged at predetermined pitches. After the pair of geared rolls are rotated, the golf ball is placed on the upstream side of rotation of the geared rolls, so that part of the cover of the golf ball is bitten between the geared rolls. The cover bitten between the geared rolls is advanced by a rotational force of the geared rolls and is drawn out to the downstream side of rotation of the geared rolls. In this way, the core and cover of the golf ball are separated from each other. Accordingly, the cover can be mechanically removed from the golf ball with improved efficiency, so that the efficiency of work for recycling golf balls can be improved, and the amount of golf balls disposed as industrial waste can be reduced.

1. Field of the Invention
The present invention relates to a method for removing covers from golf balls and to a method of recycling golf balls through the use of cores or covers separated by the above method.
2. Related Art
Conventionally, in order to recycle solid golf balls such as two-piece golf balls, golf balls are heated so as to be softened to some extent, and subsequently covers are manually separated from cores through the use of pliers, nippers, or the like.
Since manual removal of covers from golf balls takes time, the efficiency in removing covers is relatively low. Also, this work is labor intensive. With production of golf balls increasing in recent years, the amount of golf balls disposed of industrial waste is increasing. If golf balls can be efficiently recycled, the disposal of golf balls as industrial waste will decrease considerably.

Method for separating and removing covers from golf balls and for recycling golf balls


The present invention relates to a method and apparatus for transmitting a bandwidth request (BR) header in a wireless communication system. User equipment transmits a standalone BR header to a base station through a first uplink (UL) resource allocated by a BR-acknowledgement (ACK) A-MAP information element (IE), receives from the base station a hybrid automatic repeat request (HARQ)-non-acknowledgement (NACK) which indicates the base station has not successfully received the standalone BR header, receives a CDMA allocation A-MAP IE from the base station, and retransmits the standalone BR header through a second UL resource allocated by the CDMA allocation A-MAP IE.

1. Field of the Invention
The present invention relates to wireless communications, and more particularly, to a method and apparatus for allocating resources in a wireless communication system.
2. Related Art
The institute of electrical and electronics engineers (IEEE) 802.16e standard was adopted in 2007 as a sixth standard for international mobile telecommunication (IMT)-2000 in the name of 'WMAN-OFDMA TDD' by the ITU-radio communication sector (ITU-R) which is one of sectors of the international telecommunication union (ITU). An IMT-advanced system has been prepared by the ITU-R as a next generation (i.e., 4th generation) mobile communication standard following the IMT-2000. It was determined by the IEEE 802.16 working group (WG) to conduct the 802.16m project for the purpose of creating an amendment standard of the existing IEEE 802.16e as a standard for the IMT-advanced system. As can be seen in the purpose above, the 802.16m standard has two aspects, that is, continuity from the past (i.e., the amendment of the existing 802.16e standard) and continuity to the future (i.e., the standard for the next generation IMT-advanced system). Therefore, the 802.16m standard needs to satisfy all requirements for the IMT-advanced system while maintaining compatibility with a mobile WiMAX system conforming to the 802.16e standard.
A user equipment may request radio resources for transmitting uplink data or control signal. This may be called a bandwidth request (BR) process. The user equipment transmits a BR header to a base station through a UL resource allocated by the base station to request a bandwidth.
A hybrid automatic repeat request (HARQ) may be used even for the BR header. That is, when the base station successfully receives the BR header transmitted by the user equipment, the base station transmits an acknowledgement (ACK) for the BR header to the user equipment to notify that the base station successfully receives the BR header. When the base station does not successfully receive the BR header transmitted by the user equipment, the base station transmits a non-acknowledgement (NACK) for the BR header to the user equipment to notify that the base station does not successfully receive the BR header. The user equipment that receives the NACK may retransmit the BR header to the base station. The HARQ may be divided into an adaptive HARQ and a non-adaptive HARQ.
When the BR header is retransmitted according to the HARQ, a method for efficiently allocating the UL resource for the BR header is required.

Method and apparatus for allocating resources in wireless communication system


The present invention relates to a method for producing whey proteins in nanoparticulated form and to the nanoparticulated whey proteins thus obtained. Specifically, the present invention pertains to the use of these nanoparticulated whey proteins as emulsifiers, fat substitute, micellar casein substitute, whitening, foaming, texturizing and/or filling agents.

The present invention relates to a method for producing whey proteins in nanoparticulated form and to the nanoparticulated whey proteins thus obtained. Specifically, the present invention pertains to the use of these nanoparticulated whey proteins as emulsifiers, fat substitute, micellar casein substitute, whitening, foaming, texturizing and/or filling agents.
Fat containing food material makes up a considerable proportion of the diets of many people. One of the problems encountered with the production of such products resides in that the fat must remain stabilized over the entire shelf life of the product, so that no phase separation occurs.
To this end, emulsifying agents are utilized, that provide a stabilization of the emulsion once formed, based on their inherent property of a lipophilic or hydrophobic part; respectively; being soluble in the non-aqueous phase and a polar or hydrophilic part being soluble in water such that said molecules are facilitate emulsifying one phase in the other phase. Additionally, the emulsifying agents also protect the once formed droplets from aggregation and coalescence. As emulsifying agents naturally occurring substances are used, such as hydrocolloids, phospholipids (lecithin) or glycolipids and on the other hand synthetic agents like stearyl-2-lactylate or mono-, diacylglycerides, etc.
One of the major drawbacks of the agents resides in that these agents sometimes substantially add to the costs of the final product, and do not add to the nutritional value of the product. Sometimes, such kinds of materials also do not show adequate stabilizing properties because of an interfacial competition with proteins. This, there is a need for alternatives to existing emulsifiers that do not show the inherent disadvantages and are readily available. The present invention now satisfies this need.


A switch structure with display and playback functions includes a base, a circuit board, a holder, a display screen, and a cover. The circuit board is received in the base and has an electrical connection region. A supporting member and a flexible flat cable are provided below the holder. An elastic supporting element in the supporting member corresponds in position to the electrical connection region and is provided with an electrical connector. The display screen is provided on the holder and is electrically connected to the circuit board by the flexible flat cable. The cover covers the holder and the display screen. When the cover is pressed downward, thereby compressing the elastic supporting element, the electrical connector is contacted with, and closes the circuit of, the electrical connection region to connect the display screen to the circuit board. The switch structure features a small internal space and small thickness.

1. Technical Field
The present invention relates to the structural design of press-button switches and, more particularly, to a switch structure having display and playback functions.
2. Description of Related Art
An improved electrical connection structure for use in a press-button switch is now commercially available. Basically, a flexible flat cable is provided in a base and is connected to the circuit board supported on a movable support. When the switch housing is pressed, a frame therein and the movable support are moved downward such that the electrical contacts at the bottom of the movable support are in contact with the conductive terminals in the base to provide electrical connection. The flexible flat cable, which changes its physical configuration with the upward and downward movement of the frame and the movable support, does not require additional force to be applied when pressing the switch housing. Once the movable support is provided on the base, the ridges on the four inner walls of the bottom receiving space of the movable support are respectively engaged with the position-limiting blocks in the guide grooves in the four outer lateral sides of the base. The guide grooves serve to guide the ridges of the movable support, allowing the movable support to move smoothly up and down. The conductive terminals and the flexible flat cable are inserted in the through holes and through slot in the base respectively and can be directly detached from the base to facilitate replacement and maintenance.
While the foregoing product effectively reduces the pressing force required, enhances the smoothness of movement of the entire mechanism, and enables easy maintenance and replacement, the internal structure for electrically connecting the circuit board to the LED screen—implemented by contact between the electrical contacts at the bottom of the movable support and the conductive terminals in the base—has the following drawbacks, despite the fact that the aforesaid design allows unhindered upward and downward movement of the movable support and that the electrical contacts have the incidental shock-absorbing and impact-cushioning effects. First, the conductive terminals provided in the base hugely complicate the internal structure of the press-button switch. Second, the distance between the base and the movable support increases the thickness of the switch, which goes against the current trend of making smaller and more compact switches.

Switch structure with display and playback functions


This invention is directed to the measurement of stress-strain relationships in thin films using substantially flat, parallel test surfaces with minimal width. This invention is further directed to the measurement of stress-strain relationships in thin films at controlled temperatures and at high strain rates above 100% per second.

1. Field of the Invention
This invention is directed to a method for the measurement of stress-strain relationships in thin films using substantially flat and parallel test surfaces with minimal width. This invention is particularly directed to a method for the measurement of stress-strain relationships in thin films with a thermo control means for temperature dependent measurements and to an apparatus for making the measurement.
2. Description of the Related Art
A wide variety of techniques have previously been used in the measurement of mechanical properties of thin films. Tensile tests are well-established and most-acceptable tests for measuring in-plane properties of thin films. However, the in-plane properties can be different from out-of-plane properties, and it is the latter which are often more relevant to the performance of the films in their intended applications. In addition, tensile experiments impose tensile stresses on samples, which promote fracture failure earlier in the deformation, and may mask observations of plastic flow. In addition, areas supporting the load in tensile tests decrease as loads increase, leading to instability with necking and non-uniform straining. As a result, reliable large-strain properties cannot be obtained from tensile tests.
Representative of the aforementioned tensile tests is bulge testing, which is a biaxial tensile test. There, both stresses and strains can only be roughly estimated through mathematical modeling because of the complex geometry of deformation.
Nano-indentation testing is a widely-used technique to study the mechanical properties of thin films. While simple in operation, expensive equipment has been required, and the non-uniform deformation results in complicated stress and strain fields, and also makes understanding and interpreting the measurements difficult. Even with the help of sophisticated computational models, no stress-strain relationships can be extracted from nano-indentation measurements.
In addition, methods mentioned above can not provide mechanical property information of thin films under higher strain-rate, i.e., a strain-rate greater than 100% per second.
An improved test and an apparatus were disclosed in U.S. Pat. No. 5,517,860, wherein stress-strain relationships for thin films can be measured in a plane-strain compression condition. The aforementioned U.S. Patent is herein incorporated by reference. However, the method and the testing apparatus provided by the aforementioned patent can only measure stress-strain relationships under strain rates up to about 100 per second (100% per second). Although it is a few orders of magnitude higher than conventional tensile tests which can only measure stress-strain relationships of thin films under strain-rates in a range from 10−3 to 10−1 (0.1 to 10%) per second, the strain-rate applied by the method and the testing apparatus provided by the aforementioned patent is still far below the strain rates expected in a real impact situation which is usually in a range of 102 (10,000%) per second or higher. It is therefore still in need for a testing method and an apparatus that can measure mechanical properties of thin films in strain rates close to the real impact situation. In addition, there are also needs to obtain film mechanical properties at temperatures other than ambient temperatures.

Mechanical property measurement of thin films by micro plane-strain compression


A plurality of modules are removeably mounted in a rack. At least one of the modules is a drive module including a tape drive and at least one of the modules is a storage module including a carrousel for removeably receiving a plurality of magnetic tape cartridges. The storage module includes mechanisms for rotating the carrousel to present a selected cartridge to a withdrawal and replacement position. The drive and storage modules have track segments which are aligned in end-to-relation. A robot carries the selected cartridge between the carrousel and the tape drive. The robot includes a carriage mounted for traveling along the track segments and a gripper for gripping and releasing the selected cartridge. The system further comprises a control and sequencing circuit for rotating the carrousel, moving the carriage and operating the gripper.

The present invention relates to data processing systems, and more particularly, to automated apparatus for selectively loading magnetic tape cartridges from a library into a tape drive.
Tape drives are widely used as peripheral memory storage devices for computer systems. In the early days of computer processing, tape drives typically utilized open reels of one-half inch magnetic tape which were manually loaded onto so-called vacuum column tape drives. Tape cartridges have largely supplanted open reels of tape as the preferred form of tape media used for data storage. Examples of popular data storage tape cartridges are 3M's DC600, IBM's 3480 and DEC's TK/50.
In many data processing environments, it is useful to have on-line access to a selection of tape cartridges. One way to accomplish this is to utilize a magazine that holds a stack of tape cartridges. The magazine can be incremented either up or down so that a tape cartridge loader can access the selected tape cartridge and load it into an associated tape drive. See for example, U.S. Pat. No. 5,045,958 granted Sep. 3, 1991 to Leonard, et al. and assigned to Storage Technology Corporation. While this approach is serviceable, the number of tape cartridges that can be held in the magazine is limited. A much more expansive library of tape cartridges can be stored in a linear arrangement in racks or in carrousels. See for example, U.S. Pat. No. 5,065,265 granted Nov. 12, 1991 to Michel A. Pierrat.
Heretofore mass storage systems for magnetic tape cartridges have required custom cabinets. They have not been flexible in terms of capacity and they have been relatively expensive. Furthermore, they have not easily permitted a user to grow its library of tape cartridges.

Mass storage and retrieval system for magnetic tape cartridges


A substantially light-insensitive black and white monosheet thermographic recording material comprising a support and a thermosensitive element, said thermosensitive element containing a substantially light-insensitive organic silver salt, an organic reducing agent therefor in thermal working relationship therewith, at least one binder and at least one stabilizer represented by formula (I):

Thermography is an image-forming process including a heating step and hence includes photothermography in which the image-forming process includes image-wise exposure and direct thermal processes in which the image-forming process includes an image-wise heating step. In direct thermal printing a visible image pattern is produced by image-wise heating of a recording material.
EP-A 0 901 040 discloses a substantially light-insensitive monosheet recording material comprising a support and a thermosensitive element containing a substantially light-insensitive organic silver salt, an organic reducing agent therefor in thermal working relationship therewith and a binder, characterized in that said thermosensitive element further contains an unsaturated carbocyclic or heterocyclic stabilizer compound substituted with a —SA group where A is hydrogen, a counterion to compensate the negative charge of the thiolate group or a group forming a symmetrical or an asymmetrical disulfide and said recording material is capable of producing prints with a numerical gradation value defined as the quotient of the fraction (2.5−0.1)/(E2.5−E0.1) greater than 2.3, where E2.5 is the energy in Joule applied in a dot area of 87 μm×87 μm of the imaging layer that produces an optical density value of 2.5, and E0.1 is the energy in Joule applied in a dot area of the imaging layer material that produces an optical density value of 0.1.
EP-A 0 897 130 discloses a thermographic recording element having at least one image forming layer, said element comprising an organic silver salt, a reducing agent, and at least one of the substituted alkene derivatives of the general formulae (1) through (14):
wherein W is an electron attractive group, D is an electron donative group, H is hydrogen, the groups represented by W or D attached to the same carbon atom, taken together, may form a cyclic structure, the compound may assume either a trans or cis structure when both trans and cis structures are possible with respect to W or D, and two W groups in formula (14) form a cyclic structure.
U.S. Pat. No. 3,839,041 discloses a photothermographic element comprising a support having thereon photosensitive silver halide in association with an oxidation-reduction image-forming combination comprising (i) a heavy metal salt oxidizing agent with (ii) a reducing agent, a binder, and a stabilizer precursor which is a compound of the formula:
Wherein R3 is acetyl, propionyl, butyryl, pentanoyl, carboxy, cyano, aroyl containing up to 13 carbon atoms, or furyl; R5 is alkyl containing one to five carbon atoms, carboxy, aryl containing six to 12 carbon atoms, or hydrogen; R4 is alkyl containing one to five carbon atoms, carboxy, or hydrogen; n is 0 or 2.
Differences between substantially light-insensitive thermographic recording materials and photothermographic recording materials
The technology of substantially light-insensitive thermographic materials in which image formation is based on the reduction of organic silver salts is significantly different from that of photothermographic recording materials, despite the fact that in both cases the image results from the reduction of organic silver salts. However, this a superficial similarity masking the fact that the realization of the species which catalyze this reduction is completely different, being image-wise exposure of photosensitive silver halide-containing photo-addressable thermally developable elements in the case of photothermographic recording materials and image-wise heating of thermosensitive elements which do not contain photosensitive silver halide in the case of thermographic recording materials. This difference in technology is further underlined by the nature of the ingredients used in the two types of materials, the most significant difference being the absence of photosensitive silver halide and spectral sensitizing agents in substantially light-insensitive thermographic recording materials, but also reflected in the different reducing agents used, stronger reducing agents being used in substantially light-insensitive thermographic recording materials, the different stabilizers, the different toning agents etc. Furthermore, the thermal development processes themselves are significantly different in that the whole material is heated at temperatures of less than 150° C. for periods of seconds (e.g. 10 s) in the case of photothermographic recording materials, whereas in the case of substantially light-insensitive thermographic recording materials the materials are image-wise heated at much higher temperatures for periods of ms (e.g. 10–20 ms). Realization of a neutral image tone is a major problem in the case of substantially light-insensitive thermographic recording materials due to the very short heating times, whereas it is much less of a problem in photothermographic recording materials due to the much longer heating times.

Stabilizers for use in substantially light-insensitive thermographic recording materials

Abstract: wherein R1, R2, R3 and R4 are independently selected from the group consisting of a hydrogen atom, halogen atoms and aliphatic, alkoxy, nitro, acyl, sulfonyl, nitrile, alkaryl, aryl, amino, thioalkyl, aldehyde, urea, —O—(C═O)-alkyl, —O—(C═O)-aryl, —O—(C═O)—O-alkyl, —O—(C═O)—O-aryl, —NH—(C═O)-alkyl, —NH—(C═O)-aryl, —(C═O)—NH-alkyl, —(C═O)—NH-aryl, —NH—(SO2)-alkyl, —NH—(SO2)-aryl, —(SO2)—NH-alkyl, —(SO2)—NH-aryl groups; X is represented by -A(-M)n or is selected from the group consisting of substituted aliphatic groups, unsubstituted aliphatic groups, substituted cycloaliphatic groups, unsubstituted cycloaliphatic groups, substituted aromatic groups and unsubstituted aromatic groups where in each of said groups one or more of the chain or ring carbon atoms may be substituted by one of more atoms selected from the group consisting of S, O, Si, N and P atoms; n is 2, 3 or 4; A is selected from the group consisting of substituted aliphatic groups, unsubstituted aliphatic groups, substituted cycloaliphatic groups, unsubstituted cycloaliphatic groups, substituted aromatic groups and unsubstituted aromatic groups where in each of said groups one or more of the chain or ring carbon atoms may be substituted by one of more atoms selected from the group consisting of S, O, Si, N and P atoms; each (-M) is independently a substituted or unsubstituted group selected from the group consisting of -(2-S-imidazole) groups and -(2-S-imidazole) groups annelated with an aromatic ring system, the optional substituents for -M being selected from the group consisting of halogen atoms and aliphatic, alkoxy, nitro, acyl, sulfonyl, nitrile, alkaryl and aryl groups.


A rectilinear folded and glued container with tiered shelves has multiple shelf panels cut out of a front panel with which the shelf panels, and main container front, side and back panels are integrally connected. The container has an internally placed shelf-raising panel that is attached to the shelf panels as part of a fold and glue processing technique that produces a knocked down flat container to be erected. The shelf raising panel preferably is an integral panel that is separate from the main container panels so as to be relatively movable, and is affixed to the shelf panels. Displacing or translating the shelf-raising panel during erection of the container from its knocked-down-flat configuration articulates the shelves into position. The shelf raising panel can be captured between top and bottom ends of the erected container, thus fixing the erected container and articulated shelves in a rigid shape.

Corrugated and paperboard containers are made from pieces of flat stock that are typically die cut into shapes that define various panels. The shapes are folded along strategic lines between the panels, and at least one overlapping strip or panel is typically glued, taped or otherwise affixed to another panel to form a closed perimeter. The various panels are intended to become the walls, top and/or bottom of a full or partial enclosure when folded into place. Often, the containers are supplied in a collapsed or flattened parallelogram state (known as knocked-down-flat or "KDF"), for efficient storage, handling and shipping. Before packing, the containers are opened out into a hollow form and the panels are folded to reside in orthogonal planes.
Such containers can be more or less complicated. A simple version known as the regular slotted carton (RSC) has four side walls, each of which has a top and bottom flap. More complicated versions have doubled-over panels, reinforcing folded parts, inter-engaging tabs and slots and other features.
Such containers advantageously are produced by feeding flat integral die cut sheets through a fold-and-glue machine, such as those available from Bobst Group, Inc. of Roseland, N.J., to apply adhesive and preliminarily to fold over select panels so that the panels are adhered in a KDF state for shipping or storage, ready to be erected into their final configuration by articulating the panels around adjoining folds. A simple RSC version is erected by pressing inwardly from diagonally opposite corners and folding the flaps inwardly by 90° from their adjoined panels. In relatively more complicated full or partial containers, various panels may need to be folded in appropriate directions in appropriate order. Various tabs may need to be inserted into respective slots and so forth.
Containers as described can be used for displaying items or goods for the consumers at the point-of-sale location. Minimizing the effort and complication required to erect and set up the containers is an important factor for the viability and success of the particular container design. Thus, the number of parts required to erect or assemble the containers from their KDF configuration is an important element in the acceptability of the container design.
Generally, a container design is most efficient if most or all of its panels, tabs and other parts are integral panels and extensions of panels cut from a single flat blank, i.e., integral parts of the same sheet of material. Separate discrete parts such as separate lids, inserted partitions, shelves, reinforcing inserts and the like require attention to inventory, manual assembly steps and other complications during the production, erection and set up of the container. Separate parts are not desirable.
For these reasons, conventional KDF-type containers routinely are provided in a single piece flat blanks wherein all the panels necessary to construct or erect a container are members of a single sheet of stock material, cut out along an outline and scored or perforated at fold lines so as to provide all the necessary parts in an integral unit. The various seams are glued and the various folding connections between panels are cut, scored, compressed, etc.
The die cut integral blanks, preferably preliminarily weakened along prospective fold lines, are processed through the fold and glue machine. Glue is applied at preselected surfaces that are to overlap at seams. Panels are folded around fold joints. The KDF container blanks are thus produced and assembled in a state ready to be packed and shipped. For more complicated container designs, for example including lids or inserts, the KDF container blanks may be accompanied by separate discrete parts, but they add cost and require time for inventory attention, assembly and other reasons.
Because conventional KDF containers preferably are integral sheets, the panel layout design and general container complexity are limited. There is a need for ways to permit container designs to be made into complex structures, but without entailing complex parts and extensive assembly steps.

Folded and glued display container having integral shelf elements erected by displacement of support panel


An actuating drive for an adjustable actuating element may include an actuator for producing drive forces. A toggle lever may be connected to the actuating element by a first toggle lever joint. A force transmission may connect the actuator to the toggle lever. An output-side output element may be mounted pivotably on a supporting housing section of the actuating drive. The toggle lever may be connected to the output element by a second toggle lever joint. A transverse support may be oriented transversely to a linear movement direction and configured to support at least one of the toggle lever and the actuating element on a guiding housing section of the actuating device.

An actuating drive of this type is known from DE 10 2007 054 769 A1. It comprises an actuator designed as an electric motor for generating drive forces and a toggle lever, which is connected to the actuating element by means of a first toggle lever joint. A force transmission arrangement is also provided, which connects the actuator to the toggle lever for the purpose of force transmission. An output-side output element of said force transmission arrangement is mounted pivotably on a support housing section of the actuating element, while the toggle lever is connected in an articulated manner to the output element by means of a second toggle lever joint.
With the known actuating element, the output element is formed by a segment-like toothed element, which can be pivoted about a pivot axis. When the toothed element is pivoted, the second toggle lever joint is moved out of a region which aligns with the movement direction of the actuating element. The toggle lever pivots and drives the actuating element thereby.
It has been shown that the deflection of the toggle lever in the region of the second toggle lever joint out of the movement direction of the actuating element results in transverse forces in the toggle lever, which the latter transmits to the actuating element via the first toggle lever joint. A transverse force load thus occurs in the actuating element, which leads to increased wear.

Actuating drive, exhaust gas recirculating valve, turbocharger


A connection assembly (50) to electrically couple a transparent plate (24) of a liquid crystal display device (51) to an operating subsystem. The connection assembly (50) includes an elongated flexible tape member (52) having an elongated metallic circuit (53) which further includes a main circuit portion (55) fixedly mounted to the tape member (52), and a lead terminal (56). This terminal (56) includes a contact portion (57) adapted to electrically couple to the transparent plate (24), and a substantially flexible and movable conductive joint portion (58). The contact portion (57) and the conductive joint portion (58) electrically couple the transparent plate (24) to the circuit portion (55) of the metallic circuit (53) in a manner substantially minimizing residual stresses formed from the electrical coupling between the transparent plate (24) and the circuit portion (55).

The present invention relates, generally, to liquid crystal display assemblies and, more particularly, relates to miniature liquid crystal display assemblies constructed to reduce residual stresses.
In the recent past, substantial research and development resources have been directed toward small scale Liquid Crystal Display (LCD) and light valve technologies. These high information content, miniature LCD assemblies enable enhanced availability of graphics, data and video information for employment in high resolution projection displays, such as a reflective LCD projectors, SXGA formats (1,280xc3x971,024 pixel resolution) and even HDTV formats (above 1,000 line resolution), or the like.
Reflective LCD projectors, in particular, are highly desirable since they offer the brightness of traditional three-lamp front-projection systems in combination with the high resolution of an LCD panel. At the heart of these optical engines is reflective liquid crystal on crystalline silicon light valve technology which, when combined with sophisticated optical architecture and the appropriate electronic interface, enables very high resolution, high brightness, large screen displays.
One problem associated with both transmissive and reflective-type LCD panels assemblies is bowing or warpage of individual panels caused by residual stresses acting upon the components during operation. This is particularly noticeable in reflective-type LCD panels which have increased flatness requirements due to the nature of the reflective surface of the die. For example, thermal expansion characteristics, as well as lattice mismatching, can generate significant stresses in the underlying substrate material (the silicon), therein causing significant bowing of the mirrored surface. The bowing, which translates to a non-planarity of the surface, causes both (1) a non-uniform thickness of the liquid crystal layer between the bowed reflective surface and the planar transmissive top layer, and (2) variations in the path length of the reflected light from different parts of the element, and of the array. These effects compromise the electro-optic properties of the elements and/or array.
Typically, a primary source of these residual stresses originate from the different materials and composites of the LCD panel having different coefficients of expansion. This is best shown in FIGS. 1 and 2 which illustrate a flex circuit device 18 electrically coupling a conventional small scale LCD assembly 20 to an electronic interface (not shown). The LCD assembly 20 includes a die 21 having a pixel array 22 which is generally composed of rows and columns of electrically conductive pathways each forming an individual pixel (not shown). Each pixel can be individually changed to an xe2x80x9conxe2x80x9d condition by selecting the appropriate row and column of pixel array 22. Positioned around or concentrated on one end of the pixel array are a plurality of die bond pads 23 which are internally connected to the pixel array 22 to enable operational control thereof. Selection of the appropriate pixel is controlled by control circuitry, either included within the die 21 or external to the die 21. In either configuration, external control signals may be used to control the functions of the die 21.
A transparent glass plate 24 is typically placed over the die 21 and the pixel array 22, such that a portion of the glass plate 24 overhangs the die 21. The glass plate 24 is usually affixed to die 21 through an adhesive seal 25 which together cooperate to define a sealed volume encompassing the pixel array 22. This sealed volume is then commonly filled with a solution 26 of Polymer Dispersed Liquid Crystals (PDLC). To facilitate grounding or the application of a charge across the face of the glass plate 24, a conductive coating 37 may be deposited over the undersurface 28 thereof.
The die 21 is typically rigidly or semi-rigidly mounted to a substrate 27 for mounting support and heat conductive dissipation for the die. A conductive adhesive 29 (FIG. 2), such as a conductive epoxy or a thermally conductive non-adhesive grease, is generally applied to the undersurface of the die 21 to affix the die directly to the top surface of the substrate 27. Accordingly, a heat conductive pathway is created directly between the die and the substrate to dissipate heat generated by the die.
The flex circuit 18 includes a plurality of flex circuit bond pads 30 which are typically wire bonded to the die bond pads 23 through bonding wires 31. More recently, a distal ringed coupling portion 32 of flex circuit 18 is adhesively or fixedly mounted to the top surface of substrate 27 for support thereof. Finally, a glob coating 33 is applied to die 21, substrate 27 and the distal end of flex circuit 18. The glob coating 33 (FIG. 3) further normally encapsulates the bonding wires 31 and the die and flex circuit bonding pads 23 and 30 without obscuring a view of the pixel array 22 through the glass plate 24.
As previously indicated, one important aspect in the proper operation of these small scale LCD or light valve assemblies is the maintenance of proper distance uniformity (preferably about 2-4xcexcm) between the pixel array and the undersurface 28 of the glass plate. Variances in the separation of the glass plates may often times cause the pixel array to function improperly or cause operational failure.
Conventional rigid display device constructions, for example, often warp during operation since the substrate 27, the glass plate 24 and the silicon die 21 are all composed of materials or composites having different coefficients of expansion. The individual components of the LCD assembly, therefore, often expand at different degrees and rates. Further, depending in part upon the construction processes, such as the adhesive curing techniques, significant residual stresses may be induced upon the cell. Eventually, in severe instances, the glass plate 24 may delaminate from the die 21. At a minimum, these internal stresses cause optical defects such as variations in color uniformity and fringes, and variations in the cell gap thickness may cause optical shadows.
One particular cause of residual stresses is the formation of an electrical connection between the transparent glass plate 24 and a circuit 36 of the flex circuit 18 which may be employed for applying a charge or the like of the glass plate. A conductive coating 37 of indium tin oxide is typically deposited over the undersurface 28 of the glass plate 24 to facilitate electrical connection therewith. As best viewed in FIG. 3, an indium solder bump or tab 38 is pre-bonded to the indium coating 37 to enhance electrical coupling therewith. A conductive kovar slug 40 is positioned between the solder tab 38 and the circuit 36 which in turn is bonded therebetween using a conductive epoxy 41 or the like.
While this approach sufficiently electrically couples the transparent glass 24 to the flex circuit 18, the electrical connection is substantially rigid in nature. Hence, the epoxies 41, the kovar slug 40 and/or the indium solder tab 38 expand or contract during operation thereof, residual stresses are imparted upon the transparent glass plate by the rigid connection to the circuit 36, which in turn is fixedly mounted to the rigid substrate 27. For example, upon curing of the epoxy 41, shrinkage occurs which imparts a residual stress upon the glass 24.
Accordingly, there is a need to provide a LCD assembly which minimizes residual stress induced upon the cell.
The present invention provides a connection assembly adapted to electrically couple a transparent plate of a liquid crystal display device to an operating subsystem. The connection assembly includes an elongated flexible tape member having an elongated metallic circuit. This metallic circuit includes a main circuit portion fixedly mounted to the tape member, and a lead terminal. This terminal includes a contact portion adapted to electrically couple to the transparent plate, and a substantially flexible and movable conductive joint portion. Collectively, the contact portion and the conductive joint portion electrically couple the contact portion to the circuit portion of the metallic circuit in a manner substantially minimizing residual stresses formed from the electrical coupling between the transparent plate and the circuit portion.
In one embodiment, the conductive joint is provided by a section of the main circuit portion which is physically separated from fixed mounting to the tape member. Hence, the conductive joint is essentially part of the metallic main circuit portion separated from the polyamide tape member which enables substantial movement freedom by the conductive joint for a substantially stress-free electrical connection.
In another configuration, a liquid crystal display assembly is provided including a die having a pixel array and a plurality of bond pads in electrical communication with the pixel array. The display assembly further includes a transparent plate, and an adhesive seal adhesively coupling the die to the transparent plate. The adhesive seal, the transparent plate and the die cooperate to define a sealed volume therebetween encompassing the pixel array upon which a liquid crystal material is disposed within. A flex circuit device includes a flexible tape member, a plurality of primary circuits and a second circuit. The primary circuits terminate at respective first terminals of a coupling region thereof which are electrically coupled to the bond pads of the die. The second circuit includes a main circuit portion fixedly mounted to the tape member and terminates at a second terminal. The second terminal includes a contact portion adapted to electrically couple to the transparent plate and a substantially flexible and movable conductive joint portion electrically coupling the contact portion to the circuit portion of the second circuit in a manner substantially minimizing residual stresses formed from the electrical coupling between the transparent plate and the circuit portion.
In one embodiment of the liquid crystal display assembly, a substrate is provided which is coupled to a backside surface of the die. Moreover, the coupling region of the tape member, which preferably defines a receptacle portion formed and dimensioned for receipt of the liquid crystal display device therein, is fixedly mounted to the substrate.
In this arrangement, the conductive joint may be provided by a section of the main circuit portion which is physically separated from fixed mounting to the tape member and the substrate. This freedom of movement of the conductive joint enable a substantially stress-free electrical connection with the transparent plate.
In yet another embodiment, the substrate includes an aperture formed and dimensioned for receipt of a probe therethrough. During connection of the conductive joint to the transparent plate, a probe may be positioned through the aperture to contact a backside of the conductive joint an urge the same into heated contact against the transparent plate at a bond site for bonding thereof. Preferably, the probe is provided by a heated thermode, and the contact portion of the thermal bond conductive material forms a thermal bond between the transparent plate and the second terminal when contacted by the heated thermode.
In still another embodiment of the present invention, a method of packaging a liquid crystal display assembly is provided including providing a display device including a die having a pixel array, a transparent plate, an adhesive seal adhesively coupling the die to the transparent plate, and a liquid crystal material disposed within a sealed volume formed between the adhesive seal, the transparent plate and the die. The method further includes providing an elongated flexible tape member having a main circuit portion fixedly mounted thereto, and having a lead terminal thereof. The method of the present invention further includes electrically connecting a contact portion of the lead terminal to the transparent plate through a substantially flexible and movable conductive joint portion of the lead terminal to substantially minimize residual stresses formed from the electrical coupling between the transparent plate and the circuit portion.
Another embodiment of the method of the present invention includes forming the conductive joint by physically separating a section of the main circuit portion from fixed mounting to the tape member to enable the substantial flexibility thereof for a substantially stress-free electrical connection. The method further includes thermal bonding, or adhering through an electrically conductive pressure sensitive adhesive, the contact portion to transparent plate.
In another aspect of the present invention, a method of packaging a liquid crystal display assembly is included comprising: providing a display device including a die having a pixel array, a transparent plate, an adhesive seal adhesively coupling the die to the transparent plate, and a liquid crystal material disposed within a sealed volume formed between the adhesive seal, the transparent plate and the die. The method of the present invention further includes providing an elongated flexible tape member including a main circuit portion fixedly mounted thereto, and separating a section of the main circuit portion from fixed mounting to the tape member to form a lead terminal having a contact portion and a substantially flexible and movable conductive joint portion therebetween. The inventive method further includes electrically connecting the contact portion of the lead terminal to the transparent plate such that the substantially flexible and movable conductive joint portion substantially minimizes residual stresses formed from the electrical coupling between the transparent plate and the circuit portion.
In this arrangement, the method further includes mounting the die of the liquid crystal display device to a substrate, and affixing a distal coupling region of the tape member to the substrate. The electrically connecting may further include thermally bonding the contact portion to transparent plate.

Apparatus and method for substantially stress-free electrical connection to a liquid crystal display


A power switching module is adaptable for installation in a variety of existing circuit breaker panels. The module contains electrical controls providing selected control functions, such as an integral timer function. The module plugs into an existing breaker position in the circuit breaker panel adjacent a conventional circuit breaker on the same panel. The module has external terminals, including an interchangeable clip for connecting to the circuit breaker panel buss, a switched-circuit input series-connected to the load line output from the adjacent circuit breaker, a switched circuit output for carrying power to an external load being controlled by the switch, and a neutral wire extending to a neutral terminal on the panel. A microprocessor contained in the module provides the switched timer function that is set by digital inputs and displayed on the module housing. The microprocessor obtains operating power from the circuit breaker panel buss and controls operation of the switch solenoids. The power switching module obtains power for the switched load and over-current protection from the series-connected circuit breaker.

Due to concerns for energy conservation, three has been a recognized need for control devices for automatically switching electric power. Electronic timers for automatically controlling the on and off cycles of appliances or outdoor lights are an example. In order to reduce wiring and installation costs, power switching controllers have been adapted for installation in a standard circuit breaker panel. U.S. Pat. No. 4,272,687 to Borkan discloses a single-pole device for this purpose, and U.S. Pat. No. 4,754,162 to Kundou, et al. discloses a multi-pole device. A disadvantage of these devices is that both include a power switching controller and circuit breaker integrated within a circuit breaker housing that attaches to the breaker panel. As a result, each device must be produced in all the standard ampere ratings desired, in order to be used in a specific application. Further, they must be produced in various housings and configurations required by the available circuit breaker panels. Both of these objections result in higher production costs and subsequent lower utilization.

Adaptable power switch module for circuit breaker panels


Methods and systems are provided for controlling an audio and video transmission. The method includes receiving audio and video information reported from terminals, after establishing an audio and video transmission connection according to an audio and video transmission connection request; acquiring terminal types and a type of the audio and video transmission connection request; adjusting one or more audio and video transmission parameters according to the audio and video information, the terminal types, and the type of the audio and video transmission connection request; and issuing the adjusted audio and video transmission parameters to the corresponding terminals.

With the development of network technology, online meetings can be realized through the application of video software and one party can play video for another party, which brings great convenience to the users. Conventionally, when a user A and a user B want to start a video chat, user A can send a video invitation to user B, who can accept the video chat after receiving the video invitation. Meanwhile, a server can send commands to establish a video connection between client terminals of user A and user B. The client terminals of user A and user B first attempt to establish a direct channel connection. If the direct channel connection fails, the client terminals can a relay channel connection. When the audio and video connection is successful, audio and video transmission parameters can be adjusted at the client terminals. However, the adjustment of audio and video transmission parameters at the client terminals generally needs to revise a control logic of audio and video streaming at the client terminals. Thus, there is a need to release a new version of the application, which will increase operating costs, and the control of audio and video transmission parameters has poor flexibility.

Methods, devices, and systems for controlling audio and video transmission

TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED


A method for monitoring fluid media, such as a dynamic biological system, in a biological reactor containing developing culture fluid media. The method includes the step of directing light into the fluid media by way of one or more optical fibers to produce an illuminated fluid media and then measuring the intensity of light reflected from the illuminated fluid media by way of one or more optical fibers, the optical fibers being partitioned from the fluid media by a transparent window having inner and outer surfaces; the fibers having ends terminating adjacent to and confronting the inner surface of the window and extending in a direction away from the window, the corresponding ends of the fibers being radially and circumferentially spaced from one another, the corresponding ends of the fibers having converging and intersecting longitudinal projections therefrom, the intersecting longitudinal projections from the fibers being entirely within the window. Additionally, a fiber-optic probe is discussed.

The use of bacterial cells to produce protein-based therapeutics is increasing in commercial importance. One of the goals in developing a bacterial expression system is the production of high quality target polypeptides quickly, efficiently, and abundantly. An ideal host cell for such an expression system would be able to efficiently utilize a carbon source for the production of a target polypeptide, quickly grow to high cell densities in a fermentation reaction, express the target polypeptide only when induced, and grow on a medium that is devoid of regulatory and environmental concerns. There are many hurdles to the creation of a superior host cell. First, in order to produce a recombinant polypeptide, an expression vector encoding the target protein should be inserted into the host cell. Many bacteria are capable of reverting back into an untransformed state, wherein the expression vector is eliminated from the host. Such revertants can decrease the fermentation efficiency of the production of the desired recombinant polypeptide.
Fiber-optic probes can be used to determine cell concentration measurements in the fermentation process. These determinations are often performed off-line via an optical density analyzer, for example, a visible light spectrophotometer. On-line and in situ probes are available but they frequently require calibration processes specific for each fermentation process. One probe that can be used in this manner is the fiber-optic probe of U.S. Pat. No. 4,707,134 (the MiniView suspended solids gauge from Guided Wave, Inc., Rancho Cordova, Calif. (formerly Optical Solution Inc.)). This probe can be used for in situ detection and measurement of the intensity of light scattered by particles suspended in a transparent or translucent fluid medium. However, when the effective optical density of the medium exceeds about 50, the response can flatten out. Some mediums in need of analysis, such as biological growth media containing bacteria, can have a turbidity expressed in terms of optical density in the range of from about 50 to even as high as 200. Thus, it could be advantageous if a fiber-optic probe system were discovered that produced a more linear response in the optical density range of from about 50 to about 200.

Fiber-optic probes and methods of measuring biological materials


A collision avoidance system for a vehicle of the type having a powered lift mechanism with a lift control used to move the mechanism between a predetermined safe position and an elevated position includes a first sensor to determine whether the mechanism is in the safe or the elevated position, and a second sensor used to determine whether an operator is using the lift control to power the mechanism beyond the safe position. If the mechanism is in the elevated position and the operator is not using the lift control to power the mechanism beyond the safe position, control electronics are operative to automatically transfer the mechanism from the elevated position back to the safe position without operator intervention. Means may be provided for alerting an operator of the vehicle when the mechanism is in the elevated position, for example, in the form of an intermittent, periodic audible and/or visual indicator which continues until the mechanism is brought back to the safe position. A vehicle speed sensor coupled to the control electronics may also be provided to cause the automatic transfer of the mechanism to occur move rapidly as a function of increasing vehicle speed.

Problems associated with vehicles having lift mechanisms which collide with overhead obstructions have become increasingly prevalent in recent years. There are many reasons for this, including increased truck traffic, drivers who are unfamiliar with the operating environment of their vehicles, and the deterioration of highway infrastructures due to reduced budgetary allocations.
U.S. Pat. No. 5,389,912, entitled TRUCK CLEARANCE ANTI-COLLISION DEVICE, provides a useful background associated with the problem of tractor-trailer type semi-trucks coming in contact with overhead obstructions such as bridges, and so forth. As a solution to this problem, this patent proposes a vehicle clearance anti-collision device which includes an ultrasonic transmitter and receiver for receiving signals reflected off of an object disposed vertically above the cab portion of the vehicle. An on-board computer operatively associated with the transmitter and receiver automatically calculates the vertical distance between the height of the truck and the object being approached, and provides to an operator information as to the available clearance.
There are many potential problems associated with systems of the kind just described. Firstly, in the event that the vehicle is traveling at high speed, despite the warning provided by the transmitter/receiver, notification to an operator may come too late. Secondly, by virtue of the ultrasonic transducers involved, in conjunction with the computer automation and operator indicators, such a system may be too expensive for all but the most precious vehicles or cargo. In addition, this patent, and others like it, do not address the particular needs of vehicles having vertical extensible but retractable apparatus in the form of dump boxes, booms, lift buckets and fork lifts, which may only present a hazard with respect to overhead objects when the apparatus is in its extended position. That is, with the apparatus retracted, collision may inherently be avoided. Accordingly, there remains a need for a simple solution to collision avoidance in the case of vehicles having such vertically extensible/retractable apparatus.

Collision avoidance system for vehicles having elevated apparatus