Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.

1. Field of the Invention
The present invention relates to a semiconductor device provided with a high voltage transistor, particularly, to a semiconductor device having a high degree of integration and a method of manufacturing the same.
2. Description of the Related Art
The construction of a conventional nonvolatile semiconductor memory device will now be described with reference to FIGS. 21 and 22. FIG. 21 is a cross sectional view showing the construction of the cell portion and the peripheral circuit portion of a NOR type flash memory.
As shown in FIG. 21, the NOR type flash memory comprises a high voltage transistor 203 used for writing, reading and erasing information in a memory cell 202 and a low voltage transistor 204 in addition to the memory cell 202 formed of a stacked transistor including a stacked gate structure having a floating gate 200 having a memory retaining capability and a control gate 201.
The memory cell 202 is constructed such that a gate structure is interposed between source/drain diffusion layers 214. The gate structure has a stacked gate structure including a tunnel oxide film 218 formed on a semiconductor substrate 223, the floating gate 200 formed on the tunnel oxide film 218, an interlayer insulating film 219 formed on the floating gate 200, and the control gate 201 formed on the interlayer insulating film 219. Further, a gate side wall 209b is formed in a manner to surround the stacked gate structure noted above. Incidentally, the memory cell 202 is separated from the memory peripheral element such as a high voltage transistor by a shallow trench isolation layer 221.
The high voltage transistor 203 is constructed such that a gate structure is interposed between two N− type diffusion layers 206 formed in the surface region of the substrate 223. The gate structure noted above includes a thick gate oxide film 205 formed on the semiconductor substrate 223 and a gate electrode 211 formed on the gate oxide film 205. A gate side wall 209 equal in thickness to the gate side wall 209b of the memory cell 202 is formed to surround the gate structure, and the surface region of the N− diffusion layer 206 is covered with the gate insulating film 205 and the gate side wall 209. Further, N+ diffusion layers 207 are formed to extend away from the gate structure on those portions of the surface of the substrate 223 which are positioned outside the N− diffusion layers 206.
Further, the low voltage transistor 204 referred to previously is formed away from the high voltage transistor 203, with a shallow trench isolation layer 221 interposed therebetween. In the low voltage transistor 204, a gate electrode is formed between adjacent N− diffusion layers 216. The gate structure comprises a thin gate oxide film 220 formed on the semiconductor substrate 223 and a gate electrode 212 formed on the gate oxide film 220. A side wall 209a equal in thickness to the memory cell 202 is formed to surround the gate structure of the transistor 204. Further, N+ diffusion layers 215 are formed to extend from the N− diffusion layers 216 to the outside of the gate structure.
The high voltage transistor 203 is used for supplying a high voltage of ten and several volts to the memory cell 202 for the operation of, for example, writing and erasing information. In the high voltage transistor 203, the gate oxide film 205 has a large thickness, e.g., 20 nm, in order to prevent the gate oxide film 205 from being subjected to the insulation breakdown under a high voltage. In addition, it is necessary to set the junction breakdown voltage of the source/drain diffusion layers 206 and 207 at a high value of ten and several volts.
Under the circumstances, the diffusion layer 206 having a low concentration of N-type (P-type) impurity is formed deep. At the same time, a distance 208 (hereinafter referred to as an LDD length 208) of the tip of the diffusion layer 206 having a low concentration of the N-type (P-type) impurity, the tip being positioned below the gate insulating film 205 and the gate side wall 209, from the boundary between the diffusion layer 207 having a high concentration of an N-type (P-type) impurity and the diffusion layer 206 having a low impurity concentration noted above is set at a large value so as to facilitate the expansion of the depletion layer within the diffusion layer 206 having a low impurity concentration, thereby increasing the junction breakdown voltage.
Particularly, in the case of the high voltage transistor 203 is of a PMOS transistor, a P-type impurity of boron tends to be diffused into the semiconductor substrate 223 by the various heating steps employed in the process between the formation of the diffusion layers 206, 207 and the completion of the semiconductor device. Therefore, unless the thickness of the gate side wall 209 determining the LDD length 208 is maintained at a level not lower than a certain level, the LDD length 208 of the low impurity concentration region 206 positioned below the gate insulating film 205 and the gate side wall 209 is shortened or tends to be eliminated by the diffusion of boron from the high impurity concentration region 207 into the low impurity concentration region 206.
On the other hand, in a high voltage NMOS transistor (not shown), an N-type impurity of arsenic has a degree of diffusion in the heating step lower than that of the P-type impurity of boron so as to make it possible to form the gate side wall in a thickness smaller than that for the PMOS transistor 203.
However, in the conventional LDD structure shown in FIG. 21, the gate side wall 209 has a large thickness, e.g., 0.2 μm. The thickness of the gate side wall 209 is determined to conform with the PMOS transistor 203 requiring a high breakdown voltage. It follows that the gate side walls 209b and 209a of the memory 202 and the transistor 204 have thicknesses conforming with the high voltage PMOS transistor 203.
The ion implantation of a low concentration of a P-type impurity in the high voltage transistor 203 is performed after formation of the gate electrode 211, followed by forming the gate side wall 209. It is possible to set the LDD length 208 at a large value if the ion implantation of a P-type impurity is performed, after formation of the gate side wall 209, for forming the P+ diffusion layer 207 with the gate side wall 209 used as a mask. In the prior art, each of the side wall 209a of the low voltage transistor 204 and the side wall 209b of the memory cell 202 is formed in a large thickness of about 0.2 μm like the side wall of the high voltage transistor 203. What should be noted is that, in the prior art, the side walls 209b, 209 and 209a of the memory cell 202, and the transistors 203 and 204, respectively, are uniformly formed in the same thickness so as to decrease the number of process steps by forming simultaneously the side walls of the memory cell 202 and the transistors 203 and 204 in the same manufacturing process.
It should be noted that the distance between a contact hole 210 of the memory cell 202 and the gate electrode 201, the distance between a contact hole 210 of the transistor 203 and the gate electrode 203, and the distance between a contact hole 210 of the of the transistor 203 and the gate electrode 212 are equal to the sum of, for example, a side wall thickness 224 of the high voltage transistor 203 and an aligning allowance 225 between the side wall 209 and the contact hole 210. The aligning allowance is determined by the accuracy in the deviation of the alignment between the contact hole 210 and a gate electrode 211, the accuracy of the size in the contact hole 210 itself, and the accuracy of the size in the gate electrode 211 itself. This is also the case with the other memory cell 202 and the transistor 204.
Japanese Patent Application No. 11-46728 filed by the same assignee of the present application also discloses a semiconductor device relevant to the present application. This prior art will now be described with reference to FIG. 22. Incidentally, those portions of FIG. 22 which are equal to FIG. 21 are denoted by the same reference numerals so as to avoid an overlapping description.
In the prior art shown in FIG. 22, two kinds of the gate side wall structures are used for the memory cell and the transistors, including a thick gate side wall 112 used in the high voltage transistor 203 and a thin gate side wall 114 having a predetermined thickness 115, which is used in each of the memory cell 202 and the low voltage transistor 204. The first gate side wall 112 of the high voltage transistor 203 has a predetermined thickness 120 larger than the thickness 115 of the gate side wall 114 of the memory cell 202 and the low voltage transistor 204. Further, a second side wall 111 is formed in an upper portion of the first gate side wall 112.
In the case of employing the structure shown in FIG. 22, it is possible to ensure a sufficient LDD length 116, which permits obtaining the required junction breakdown voltage, in the high voltage transistor 203. It is also possible to use the side wall 114 thinner than that in the prior art shown in FIG. 21 in each of the memory cell 202 and the low voltage transistor 204. What should also be noted is that, since the LDD length 117 in the low voltage transistor 204 is smaller than the LDD length 116 of the high voltage transistor 203, it is possible to diminish the distance 119 between the gate electrode 212 and the contact hole 210.
The distance 119 is a sum of the side wall thickness 115 and the aligning allowance 225. In the high voltage transistor 203, the distance 118 between the gate electrode 211 and the contact hole 210 is equal to the sum of the side wall thickness 120 of the high voltage transistor 203 and the aligning allowance 225, which is larger than the distance 119 between the gates 200, 201, 212 and the contact hole 210 in the memory cell 202 and the low voltage transistor 204, respectively.
Further, FIG. 1 of Japanese Patent Disclosure (Kokai) No. 8-23031 discloses a semiconductor integrated circuit in which a double layer structure is employed in the gate side wall in order to increase the withstand voltage of the high voltage MOS transistor and to improve the driving capability of the low voltage MOS transistor. In this prior art, a diffusion layer of a high impurity concentration is formed with respect to the outer layer of the gate side wall having a double layer structure on the side of the high voltage MOS transistor, and a diffusion layer of a high impurity concentration is formed with respect to the inner layer of the gate side wall having a double layer structure on the side of the low voltage MOS transistor.
The method of manufacturing the conventional semiconductor device shown in FIG. 21 gives rise to the problem pointed out below.
Specifically, in forming the contact hole 210, there is a possibility for the contact hole 210 to be formed close to each of the gate electrodes 201, 211 and 212 because of the deviation in the mask alignment. There is also a possibility to bring about the inconvenience that the contact hole 210 is caused to deviate to cover partly the gate side walls 209a, 209 and 209a because of the enlargement in the size of these members. Where the material forming the gate side wall is unlikely to be etched, the bottom surface of the contact hole 210 fails to be brought into contact with the surface of the diffusion region formed in the surface region of the semiconductor substrate 223 as designed. Since the contact area between the bottom surface of the contact hole 210 and the surface of the substrate 223 is diminished, the contact resistance of the contact hole 210 is increased.
On the other hand, where the semiconductor device is designed such that a sufficient distance, e.g., 0.2 μm, is provided between the contact hole 210 and each of the gate side walls 209b, 209 and 209a so as to prevent the contact hole 210 from being brought into contact with any of the gate side walls 209b, 209, 209a, the distance between the contact hole 210 and each of the gate electrodes 201, 211 and 212 is rendered large, e.g., 0.4 μm, leading to an increase in the chip size.
Concerning the memory cell 202, the N+ diffusion layers 214 are formed as the source/drain regions in a manner to overlap partly with the floating gate 200, with the result that the LDD side wall structure 209b is originally unnecessary. It should be noted in this connection that, in forming the LDD structure for the peripheral transistors during the manufacturing process of the semiconductor device, the gate side wall 209b is also formed simultaneously in the memory cell 202, with the result that the gate side wall is also present in the memory cell 202.
However, if the memory cell 202 is made finer so as to make smaller the distance between the adjacent word lines connected to the memory cells, the area of the bottom surface of the contact hole 210 is made very small or is eliminated completely by the thick gate side wall 209b so as to make it impossible to design the semiconductor device such that a contact is formed between the adjacent word lines. Such being the situation, in order to form a contact hole between the adjacent word lines, it is unavoidable to enlarge the cell size because the side wall is thick. This is a very serious problem inhibiting the miniaturization of the semiconductor device.
A serious problem also remains unsolved in the low voltage NMOS transistor 204 of the peripheral circuit. Specifically, since the side wall 209a is rendered thick, the LDD length 217 of the N− diffusion layer 216 is rendered long so as to increase the parasitic resistance, leading to the problem that the current driving capability of the transistor 204 is lowered.
Under the circumstances, since a high junction breakdown voltage is unnecessary in the low voltage transistor 204, the inconvenience is brought about that the circuit pattern is rendered large and the performance is deteriorated.
The prior art shown in FIG. 22 is capable of resolving the problem inherent in the prior art shown in FIG. 21. In the prior art shown in FIG. 22, however, the thick gate side wall 112 is formed in only the high voltage transistor 203 and, thus, the gate side walls 112 and 114 are formed separately by adding one or two photolithography steps to the prior art shown in FIG. 21. It follows that the gate side wall forming steps are rendered complex, leading to an increase in the number of manufacturing steps, compared with the prior art shown in FIG. 21.

Semiconductor device and method of manufacturing the same


A flow sensor comprises a heater module, a fluid temperature sensor and a Wheatstone bridge module. In the heater module, a heater is disposed very close to a heater temperature sensor and an insulation layer electrically isolates these two elements. The heater and the heater temperature sensor are disposed together on a floating membrane positioned normally to the fluid flow. The Wheatstone bridge module regulates electric current supplied to the heater, based on a constant temperature difference between the heater and the fluid, and provides voltage information of the electric current. A microprocessor converts the voltage information into velocity of fluid to be measured. A bypass channel is designed to adjust flow impedance of the fluid. Further disclosed is a fluid temperature sensor with the same design of the heater module whereby the factor of flow direction of the fluid may be ignored.

A thermal flow sensor measures fluid velocity of, such as, gas and liquid utilizing the principle of balancing input and output energy. In a balanced system of a thermal flow sensor, the input is simply thermal energy converted into electric format and the output thermal energy includes thermal conductivity, thermal radiation and convective heat losses. Among them, the convection heat loss is the dominating term. When the input energy and the output energy are balanced, the convective heat-loss is used to measure the velocity of the fluid.
FIG. 1 illustrates the system diagram of a conventional thermal flow sensor. As shown in the figure, a thermal flow sensor comprises: a fluid channel 1 (see FIG. 3) through which fluid F flows, a fluid temperature sensor 6 to sense the temperature of the fluid F, a heater 72 to supply thermal energy to the fluid F, a DC power supply 9 to supply electric current to heater 72, a heater temperature sensor 74 to sense the temperature of the heater 72, a Wheatstone bridge module 10 to regulate the DC current supplied to the heater 72 and a microprocessor 11 to measure changes in the voltage of the current supplied to the heater 72 and to convert said change into velocity values of the fluid F.
In order to shorten the response time, a thermal flow sensor operates under a "constant temperature difference mode". Under such mode, heater 72 is positioned inside the fluid channel 1 (see FIG. 3), and a constant temperature difference between heater 72 and the fluid F is maintained, such that the temperature of the heater 72 is always higher than that of the fluid F. In doing this, temperature information obtained from the fluid temperature sensor 6 and the heater temperature sensor 72 may be taken for reference. In order to transfer thermal energy from the heater 72 to the fluid F, heater 72 is always in direct contact to the fluid F. When the fluid flows, due to the temperature difference between the heater and the fluid, thermal energy contained in the heater is carried away by the fluid. The thermal energy carried away by the fluid is in direct proportion to the square root of velocity of the fluid. To maintain a constant temperature difference, a feedback control loop is used to regulate electrical current supplied to heater 72. When the constant temperature difference is maintained, the thermal energy (electric currency) needed to retrieve the temperature of the heater 72 may be measured and the fluid velocity may be known.
In the conventional art, the said feedback control loop may be a Wheatstone bridge module. FIG. 2 illustrates the circuit diagram of a Wheatstone bridge module for a thermal flow sensor. As shown in the figure, a Wheatstone bridge module 10 has a Wheatstone bridge 21, an operational amplifier 22 and a heater R.sub.H. At one branch of the Wheatstone bridge there are fluid temperature sensor R.sub.f and resisters R.sub.1 and R.sub.2, while at the other branch are heater temperature sensor R.sub.5 and resistor R.sub.3. Temperature sensor R.sub.f and resisters R.sub.1 and R.sub.2 provide a reference voltage V.sub.1 to the operation amplifier 22 and heater temperature sensor R.sub.5 and resistor R.sub.3 Provide another reference V.sub.1 to the operation amplifier 22. By setting up a minute voltage difference between V.sub.1 and V.sub.2, i.e., with the assistance of resistor R.sub.1, the circuit will come to a steady state by heating up resistor R.sub.H (the heater temperature sensor 74) and resistor R.sub.5 (fluid temperature sensor).
In order to improve the overall performance of a thermal flow sensor system, it is necessary to enhance the ratio of the heat convection loss, in contrast to the radiational and conductive losses of the thermal energy, during the flow of the fluid. Over the past years various improvements for the thermal flow sensor have been invented. Among these improvements, some used silicon micro-machining technology to minimize the size of the heater 72 or to isolate the heater 72 from the rest parts of the flow sensor, so to minimize unwanted losses of thermal energy during the flow of the fluid. Some proposed to position the heater temperature sensor 74 as close as possible to the heater 72 by using concrete elements such as multi-layer, thin film resistors positioned on a microbridge or on a micro membrane.
Other developments to the performance of the thermal flow sensor include: U.S. Pat. No. 4,326,412, to Hiroshi et al. (1982), U.S. Pat. No. 5,186,051, to Stecher et al. (1996) and U.S. Pat. No. 5,623,097, to Horiguchi et al. The Hiroshi invention disclosed a thermal flow sensor used in fuel control system for auto combustion engine. In the Hiroshi invention, a network of metal wire segments in two cross sectional planes in a fluid pipe is used to measure a non-uniform flow of gasoline in an average manner. In the flow, adjacent to the boundary the dragging effect slows down the velocity of the gasoline. In the Stecher invention, disclosed are a thin film heater and a heater temperature sensor coupled very close to each other in order to provide precise measurement of the heater temperature. In the Horiguchi invention disclosed is a heater with a sensor stacked to it and positioned on a microbridge. These and other improvements, however, have a common problem. That is, the heater and temperature sensor are positioned in parallel to the fluid flow. This arrangement creates a thermal boundary layer on the surface of the heater-temperature assembly. The thermal boundary layer impedes the heat convection efficiency from the heater to the fluid. Other problems include that the components used in these disclosures are not compact enough and make the device bulky.
In the conventional art, the fluid temperature sensor 6 is positioned in the up-stream direction of the flow and the heater 72 in the down-stream direction. This creates a problem in installing the flow sensor while the direction of the flow shall be taken for consideration.
It is thus a need in the industry to provide an integrated flow sensor with higher precision. It is also a need to provide a thermal flow sensor where the area of the thermal boundary layer may be minimized. It is also a need to provide a thermal flow sensor that is easy to manufacture under semiconductor manufacture process, so that the heat capacity of the system may be reduced. It is also necessary to provide a thermal flow sensor where the factor of flow direction may be ignored.


A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.

The present invention relates to the field of signal synchronizing and frequency synthesis circuits for sequence control of integrated circuit logic. More specifically, the present invention relates to a signal synchronizing and frequency synthesis circuit of the phase locked loop type.
Synchronization of a microprocessor system is accomplished through the use of one or more clock signals. Each component within the system uses a clock signal to synchronize the particular component""s internal sequential logic circuitry to that of the entire system in order to operate in accordance with the desired operating protocol standard. In high-speed systems, synchronization of clock signals with each of the clocked components must be maintained with high efficiency to eliminate or reduce system timing errors and delays which may result. A system utilized in maintaining the synchronization of microprocessor systems is the phase lock loop (PLL).
Signal synchronizing and frequency synthesis circuitry such as PLLs are used in synchronous microprocessor systems. In integrated circuit (IC) logic, PLLs are used in order to minimize timing delays and errors which may occur due to the delays. A PLL can be used to synchronize a plurality of signals to conform to a desired frequency signal. The synchronization of the plurality of signals allows a plurality of circuits within the same system to operate in accordance with a desired timing protocol.
Problems in synchronization may occur when various clock signals operating within the same system become misaligned in phase, i.e. skewed, while passing through intermediate circuitry having varying propagation delays. In a high-speed multiple chip computer system, it is desirable to maintain the phase difference between clock signals at various locations in the system to a specified minimum value. However, variations in propagation can be caused by variations in circuitry structure or tolerance associated with the system""s manufacturing process.
Additionally, synchronizing or timing problems may occur with respect to typical microprocessor systems that have an external clock signal and another clock signal which is internal to the microprocessor core. These two external and internal clock signals may sometimes become out of phase in relation to each other, as between the clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core.

High frequency system with duty cycle buffer


A bubble wand includes a primary member and an auxiliary member. The primary member is substantially entirely formed in a first, single plane and defines an elongated slot and a first plurality of bubble-forming rings. The first plurality of bubble-forming rings includes a different bubble-forming ring positioned on each of at least two opposing sides of the elongated slot. Each of the first plurality of bubble-forming rings defines an opening therethrough. The auxiliary member is substantially entirely formed in a second, single plane and is coupled to the primary member such that the auxiliary member extends through the elongated slot of the primary member such that a first side portion of the auxiliary member is maintained on a first side of the primary member and a second side portion of the auxiliary member is maintained on a second side of the primary member. The auxiliary member defines at least one additional bubble-forming ring in each of the first side portion and the second side portion of the auxiliary member.

Hand-held bubble wands and other bubble blowing tools that are dipped into soaps or bubble blowing solutions have been used for many years. Bubble wands typically are generally formed in a single plane with holes for holding bubble solution being defined within that single plane. Such wands typically hold a limited amount of bubble solution following each dip into a reservoir of bubble solution based on their exposed surface area. Accordingly, many repeated dips of the bubble wand into the bubble solution are generally necessary to create a larger amount of bubbles. Non-planar bubble blowing devices typically include bubble enclosures creating crevices and bubble reservoirs in a more complicated design that is too complex for easy use by young children and that increases maintenance for the devices.

Bubble wand and associated systems and methods


An architecture for oversampled delta-sigma (.DELTA.-.SIGMA.) analog-to-digital (A/D) conversion of high-frequency, narrow-band signals includes multistage .DELTA.-.SIGMA. modulators that incorporate band-reject noise shaping centered at one fourth the clock frequency Fs. These modulators cascaded with a bandpass digital filter also centered at a frequency of Fs/4 perform A/D conversion for high-frequency, narrow-band signals centered at the same frequency. The bandpass modulators are implemented by use of resonators in existing low-pass multistage modulators.

1. Field of the Invention
This invention relates in general to analog-to-digital (A/D) converters and, more particularly, to a new architecture for oversampled delta-sigma (.DELTA.-.SIGMA.) A/D conversion of high frequency, narrow band signals using cascaded low order stages to obtain high overall order of noise shaping.
2. Description of the Prior Art
Prior art single-loop bandpass delta-sigma (.DELTA.-.SIGMA.) modulation is described by R. Schreier and M. Snelgrove in "Bandpass Sigma Delta Modulation," Electronics Letters, Vol. 25, 9th Nov. 1989, pp. 1560-1561. Z.X. Zhang, G.C. Temes and Z. Czarnul in "Bandpass .DELTA..SIGMA. A/D Converter Using Two-Path Multibit Structure", EIectronics Letters, Vol. 27, 24th Oct. 1991, pp. 2008-2009, citing Schreier et al., supra, describe a modification of the basic structure using N-path switched capacitor circuits. Subsequently, R. Schreier, G.C. Temes, A.G. Yesilyurt, Z.X. Zhang, Z. Czarnul, and A. Hairapetian in "Multibit Bandpass Delta-Sigma Modulators Using N-Path Structures", IEEE International Symposium on Circuits and Systems, May 1992, pp. 593-596, describe simulation results of two switched-capacitor circuits for use in a multi-bit bandpass sigma-delta modulator.
Typically, cascaded low-order delta-sigma stages have been used to implement higher order delta-sigma modulators for A/D conversion of low-pass signals. See, for example, D.B. Ribner, "A Comparison of Modulator Networks for High-Order Oversampled Sigma-Delta Analog-to-Digital Converters," IEEE Trans. Circuits and Systems, Vol. CAS-38, No. 2, pp. 145-159, Feb. 1991. Those cascades comprise combinations of first and second-order individual stages and thereby avoid the stability problem prone to single-loop modulators of third-order and higher. See also D.E. Ribner U.S. Pat. Nos. 5,084,702, 5,103,229, and 5,148,166, all assigned to the instant assignee, for further background on plural-order sigma-delta analog-to-digital converters. U.S. Pat. Nos. 5,084,702, 5,103,229 and 5,148,166 are hereby incorporated by reference.

Multistage bandpass .DELTA. .SIGMA. modulators and analog-to-digital converters


A hand tool for gripping and moving building materials includes a linkage having a grip at a first end. A plate having a gripping face is pivotally attached to a second end of the linkage. A generally U-shaped bracket is pivotally attached to the linkage adjacent to the plate and extends beyond the second end of the linkage so that a gripping face thereof is disposed generally opposite the plate gripping face. Upon inserting a building material between the plate and bracket gripping faces and lifting the linkage upwardly, the plate and bracket pivot so that the gripping faces firmly contact and grip opposite sides of the building material for transport.

The present invention generally relates to tools for use in building construction. More particularly, the present invention relates to a hand tool which is designed to hold and grip heavy and/or unwieldy materials used in the construction of buildings and the like.
In the construction industry, there are a variety of building materials which are large in size, heavy or otherwise unwieldy. Such materials include panels, boards and sheets of dry wall wallboard, plasterboard, sheet rock, plywood, particle board, pressed-wood, melamine, granite, marble and glass.
Although pallets of these materials may be loaded onto a truck bed for delivery to the construction site, or even lifted by crane to areas of the construction site or levels of the building being constructed, they still must be individually transported to their final destination within the building structure. Although such materials are often heavy, they are capable of being carried to their final destination by only one or two construction workers. The difficulty in transporting these materials lies in the fact that they are very large. For example, a sheet of plywood can be four to six feet in width and eight feet or more in length. Such materials typically lack handle holds or apertures for grasping. Thus, to carry a sheet of material, a construction worker typically grasps an edge of the material tightly between the fingers and palms of his hands and lifts the sheet of material a few inches off the ground while walking to deliver the sheet of material to its final destination. Not only awkward, this method of carrying such sheets of material fatigues the worker""s hands, arms, upper torso and neck.
Some of these materials, such as glass or marble, can be quite slippery and slip out from the grasp of the construction worker""s hands. Such falls can render the sheet of material at least partly if not fully useless, resulting in increased cost for the construction project.
Accordingly, there is a need for a tool which is designed to assist a construction worker in gripping and holding unwieldy panels and sheets of construction material. Such a tool should be configured so as to grasp such sheets firmly without damaging the material. Such a tool should also enable the construction worker to more naturally hold and carry the sheet of material such that the weight is distributed over the construction worker""s body, instead of in front of or to the side of the body, to prevent fatigue and injury. The present invention fulfills these needs and provides other related advantages.
The present invention resides in a hand tool for gripping and moving building materials, such as sheets and panels of material. The hand tool generally comprises a linkage including a grip at a first end thereof, and a plate pivotally attached to a second end of the linkage and having a gripping face. A bracket is pivotally attached to the linkage intermediate the first and second ends thereof. The bracket extends beyond the second end of the linkage and has a gripping face disposed generally opposite the gripping face of the plate. Upon inserting a building material between the plate and bracket gripping faces and lifting the linkage upwardly, the plate and bracket pivot so that the gripping faces thereof firmly contact and grip opposite sides of the building material.
The linkage generally comprises a pair of support arms attached to opposite ends of the grip so as to be generally parallel with one another. The support arms are each L-shaped in configuration, having integral first and second sections that are angularly offset from one another. In a particularly preferred embodiment, the first and second sections of each support arm are angularly offset by twenty-two degrees.
The bracket is generally U-shaped. The plate and bracket gripping surfaces are generally flat, and may include a cushion insert attached thereto to enhance the frictional contact with the building material, as well as preventing scratches and marring of finished surfaces of the building material, such as when the building material comprises glass, marble, etc. The insert may be comprised of a rubber material to achieve these objectives.
Other features and advantages of the present invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.

Hand tool for gripping and carrying objects


A user equipment power-saving method includes: determining a second signaling on the basis of a first signaling, wherein the second signaling is a radio resource control (RRC) connection request signaling and carries a signaling element that characterizes a cause value for requesting to establish an RRC connection as a discontinuous reception (DRX) cycle update; and sending the second signaling.

In a wireless communication system such as a Long-Term Evolution (LTE) system, to improve power saving performance of User Equipment (UE), Discontinuous Reception (DRX) is proposed. UE in a DRX mode may receive downlink data and a downlink scheduling command on a Physical Downlink Control CHannel (PDCCH) discontinuously based on a DRX cycle. When neither downlink scheduling command nor downlink data are to be received, UE may be in a sleep state. A PDCCH may be monitored periodically discontinuously, thereby saving power.
In related art, a system network side may determine a duration of a DRX cycle based on a factor such as paging capacity. UE may be notified of a duration of a DRX cycle. However, a DRX cycle configured by a system network side may not meet a demand of UE, thereby failing to optimize power saving performance.

User equipment power-saving method and device, user equipment and base station

BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.


An apparatus and a method for controlling memory in a base station modem supporting multi-users including a memory divided into logical blocks for supporting the multi-users, and a controller for allocating the memory blocks dynamically in hardware. This allows non-continuous memory allocation and the size of memory can be increased or reduced during operation through the dynamic allocation structure of the memory.

1. Field of the Invention
The present invention relates to an apparatus for controlling a memory in a base station modem, and more particularly, to an apparatus and a method for controlling a memory in a base station modem supporting multiple users.
2. Background of the Related Art
Recently, as mobile terminals proliferate rapidly due to increasing mobile subscribers, the need for using limited radio resources effectively is highlighted. The quality of mobile communication service varies with the designs and features of base stations that connect the mobile subscribers to enable communication with each other.
The memory of a base station modem is typically a high priced system resource, and various algorithms for managing the memory more efficiently are being suggested.
Generally, there are two approaches for allocating memory areas. A first method is a dynamic allocation method in which the memory is allocated to respective users according to space requests required by the user connected to the modem. A second method is a fixed allocation method, in which the memory is divided into blocks of certain sizes that are defined in advance, and a block having a corresponding requested size is selected and allocated when memory is requested.
Both of the memory allocation methods described above may be performed by software. However, in case of the dynamic allocation, an additional step of calculating synchronization for re-allocating the memory to the user using the software is required. In addition, since the blocks of the memory are fixed in the fixed allocation, the memory cannot be allocated for a request greater than the allocated blocks, and the memory area is divided repeatedly for the requests smaller than the blocks. Therefore, the memory may not be further allocated, even if there is sufficient memory available to do so.
That is, the conventional memory allocating method for the base station modem is not able to perform non-continuous memory allocation when allocating the memory for multiple users, and the dynamic memory re-configuration cannot be made during operation.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.

Apparatus and method for controlling memory for a base station modem


Provided is a method of manufacturing an electronic part having a plurality of wiring patterns and an insulating layer interposed between the wiring patterns and serving to establish electrical connection between the wiring patterns through an interlayer connecting portion penetrating the insulating layer. In the method, a first step of forming a wiring pattern and a columnar conductor and a second step of forming a layer having a uniform thickness by bonding an insulating sheet from above and pressing the insulating sheet to the height of the columnar conductor with the columnar conductor as a stopper so as to conform the thickness of the insulating sheet to the height of the columnar conductor are repeated.

Up to now, there have been known an electronic part and a print wiring board in which: wiring patterns are formed on an insulating layer; and the wiring patterns are laminated in a thickness direction thereof to form a multi-layer structure.
Various manufacturing methods of forming the multi-layer structure have been proposed and disclosed. FIG. 6A and FIG. 6B are step explanatory diagrams each showing a conventional step of manufacturing an electronic part for each layer.
In FIG. 6A, laser irradiation is performed to make a hole on a surface of an insulating layer 1. Then, a hole 2 is formed through laser processing, and thereafter, a conductor portion, which is composed of a film or has a columnar shape, is formed inside the hole 2 by filling a conductive paste into the hole 2 or performing plating.
In FIG. 6B, conductor portions 4 are formed on a surface of a preformed insulating layer 3 through plating or etching. After the conductor portions 4 are formed through the above step, an insulating resin 5 is applied onto a surface of each of the conductor portions 4 through spin coating (for example, refer to JP 10-22636 A).
Another method has been known in which: a bump composed of a conductive paste is formed on a wiring of a substrate; then, an interlayer connecting insulating member and a metal layer are arranged; the bump is made to penetrate into a forming resin through pressing; and resultingly, the bump is conductively connected with the metal layer (for example, refer to JP 2002-137328 A).
Further, a method has been disclosed in which: a penetrating hole is formed by means of a carbon dioxide gas laser or the like; a paste containing powder of a low-resistance metal such as gold, silver, copper, or aluminum is filled into the penetrating hole; and resultingly, a via hole conductor is formed (for example, refer to JP 2002-134881 A).
Moreover, a method has been disclosed in which: a resin is applied to the periphery of an interlayer connecting conductor post; and the resin is pressed through an emery paper-like mould releasing film having moderate roughness on its surface to form an insulating layer (for example, refer to JP 06-57455 B).
As regards the electronic part including a multi-layer structure, incorporating elements and the like into the electronic part has been examined with the aim of attaining a higher density and a higher function. Here, when an element such as a passive part is to be formed between wiring patterns overlapped in a lamination direction, a distance between the wiring patterns serves as an important factor that determines characteristics of the element. Thus, for the purpose of stabilizing the element characteristics, a method of manufacturing an electronic part has been desired in which the distance between the wiring patterns, that is, the thickness of each layer in the electronic part can be reliably controlled.
However, in the above-mentioned manufacturing method shown in FIG. 6A, it is only performed that: the insulating layer 1 is subjected to laser processing for making a hole; and the conductor portion is formed inside the hole 2. The thickness of the entire layer is not managed.
Further, in the manufacturing method shown in FIG. 6B, the resin is applied through spin coating to form an insulating resin layer so as to cover the conductor portion; however, a swell is generated on a surface of the insulating resin depending on the existence of the conductor portion 4. Thus, it has been difficult to uniformly set the thickness of the entire layer.
Moreover, a method of controlling the thickness of the entire layer has not been disclosed either in the method in which: a bump composed of a conductive paste is formed on a wiring on a substrate; and then, the bump is made to penetrate into a forming resin through pressing. Furthermore, also in JP 2002-134881 A, it is only performed that filling of the paste is conducted to form the via hole conductor, and the thickness of the entire layer is not controlled.
In JP 06-57455 B, after the pressing step is completed, the mould releasing film needs to be released from a surface of the insulating layer. However, an external force may act on the surface of the insulating layer due to this releasing operation, which causes deformation or the like on the surface of the insulating layer. Also, as in FIG. 6B, since the resin is applied to cover the conductor portion, a swell is generated on the surface of the insulating resin. Thus, it may be difficult to uniformly set the thickness of the entire layer.
In the mean time, in a general method of manufacturing an electronic part, it is generally performed that a surface of an insulating layer is roughened to improve adhesion property with respect to a copper foil that forms a wiring pattern. However, it is known that some of resins for forming an insulating layer are chemically stable, and thus, are difficult to be subjected to a roughening process with the use of chemicals. Therefore, a manufacturing method has been desired in which a bonding strength with respect to a wiring layer can be reliably secured even with the use of such a chemically stable resin.

Electronic part manufacturing method and electronic part


The lid with re-closable spout invention can be used with a hot and/or cold beverage container or other fluid container. The lid fits onto the container as is known in the art. The lid includes a spout formed on the lid and extending from the lid which allows one to access the contents of the fluid container. The spout can be positioned in a closed position wherein it is folded in to prevent the contents of the fluid container from exiting the spout. The spout may be locked into a closed position. In a second, open position, the spout is folded out to allow the fluid within the fluid container to be poured out of the fluid container through the spout. After use and/or between uses, the spout can be re-closed and re-sealed. The spout can be any desired configuration including generally square or rectangular, or generally cylindrical. The sealing means can be a zipper-type engagement formed on the upper edge of the spout.

1. Field of the Invention
This invention relates generally to a spill-proof spout for a lid of a container, and more specifically to a spout for a liquid container that can be opened for use and then closed and sealed after use or between uses.
2. Related Art
Disposable and re-usable containers for beverages and/or other fluids are in wide use. Numerous attempts have been made in the past to provide lids with mechanisms to prevent the spilling of the fluid within the container during use. For example, with beverage containers, it has been known to form small openings in the lid to decrease the likelihood of spillage. Additionally, lids with frangible portions have been made, the frangible portions being broken prior to use. Such lids, however are difficult, if not impossible, to re-seal and do not adequately function to prevent spillage.
Commonly, beverages are purchased in disposable containers and then taken along by a person either in a car or in some other type of transportation, or the container is carried and the contents consumed while one travels to a location. However, it is widely known that there is a risk associated in that the beverage can spill onto the user, or within the vehicle, if the beverage container is tilted to far or dropped.
Accordingly, what is desirable and has not heretofore been developed, is a lid which can be closed between uses and/or after use, and which can be sealed when closed, and which can be easily opened to allow one to drink or otherwise utilize the fluid within the container with a reduced risk of spilling the fluid.
Some of the numerous efforts to provide a lid that prevent the spilling of fluid are as follows:
Proshan, U.S. Pat. No. 5,538,157, discloses a lid having a rectangularly shaped spout with upper and lower ends interconnected with the lid. The user can drink from a container by use of the spout. PA1 Coy, U.S. Pat. No. 4,782,975, discloses a lid which includes a spout with a flow control valve housed within the spout. The valve and spout are formed of a resilient material. The valve is normally closed, but is openable by pressure applied external to the spout by one's lips. The lid may be formed of any desired material such as plastic or paper or cardboard. A tab is initially applied over the spout. The spout includes a valve formed of a flexible and resilient material such as rubber. PA1 Gartner, U.S. Pat. No. 4,756,440, discloses an anti-spill lid having a drinking spout formed on the lid. The spout includes a plurality of apertures on the upper tip thereof to allow one to suck liquid out from the container. No vent is supplied on the lid so that one must apply suction in order to remove liquid from the container, the suction pulling the flexible lid downward during use. After the spout is released, air enters into the container via the apertures in the spout. PA1 Brandlein, U.S. Pat. No. 4,579,257, discloses a lid for a can, the lid including a pouring spout. The spout can serve to pour contents or can be used directly as a drinking opening. A cap may be provided for the spout. PA1 Park, et al., U.S. Pat. No. 4,561,557, discloses a beverage container including a spout. The spout is positioned to extend below the lid and is opened upon pulling a tab to pivot the spout to extend up from the lid. PA1 Combs, U.S. Pat. No. 4,407,425, discloses a lid for a beverage container including a flexible spout member with a base portion secured to the lid. A closure strip is applied over the spout and the spout is folded down in a closed position and when opened, by removing the closure strip, the spout pivots upwardly to an open position. PA1 Lobbestael, U.S. Pat. No. 4,243,156, discloses a lid having a tubular spout and having a cap formed on the spout for closing the spout. The cap can be detached from the spout to utilize the spout for drinking. PA1 Lang, et al., U.S. Pat. No. 4,239,123, discloses a mouthpiece for use on a container having a tear-open closure slot. The mouthpiece is insertable into the opening in the container to form a liquid tight seal therewith.
None of these efforts, taken either alone or in combination, teach or suggest all of the benefits and the utility of the present invention.


A length of wire is toroidally wound, and then the toroid is encapsulated and cut in two along a plane that is perpendicular to the toroidal axis. The resulting portions are used as stator and/or armature of a solenoid, and in the solenoid the cut face of each forms one side of the solenoid's working gap so that the faces move toward and away from each other as the solenoid operates.

The state of the art contains a substantial number of patents relating to solenoids for valves, such as solenoids for fuel injectors. Typically, a solenoid valve comprises an armature that reciprocates between a first and second position for causing a valve member such as a needle to seat on and unseat from a valve seat thereby closing and opening the valve. The basic solenoid design comprises an electromagnetic coil and a ferromagnetic pole forming a stator, and a ferromagnetic armature that is connected to the valve member. The armature is kept separated from the stator by a force such as gravity, spring, or pressure.
One of the factors slowing the response time of the solenoid is eddy current generation in the ferromagnetic materials. When the solenoid is energized, eddy currents tend to inhibit the rate at which the magnetic force builds. Likewise, eddy currents tend to inhibit the rate at which the magnetic force decays upon solenoid de-energization.
Previous methods of reducing eddy currents have involved laminating the ferromagnetic material. The lamination approach, however, tends to be limited to a rectangular package. Unfortunately, fitting the lamination design into a cylindrical package like a typical fuel injector results in either a larger cylindrical package or a smaller flux path with reduced force output.
It is seen then that there still exists a need for further reducing eddy currents in a the solenoid of a cylindrically shaped valve, like a typical fuel injector.
This need is met by a low eddy current magnetic flux circuit according to the present invention, wherein a magnetically permeable wire, or filament, is toroidally wound on a tubular electromagnetic coil, and then encapsulated. The assembly is then severed into two parts, namely a stator assembly and an armature assembly.
For a fuller understanding of the present invention and its attendant features and advantages, reference may be had to the following detailed description taken in conjunction with the accompanying drawings and the appended claims.


A client computer may split a process into sub-processes, send each sub-processes to a different group of peers in a blockchain network, wherein each group has at least one peer from each essential organization in the blockchain network, receive processed sub-transactions from the peers in the blockchain network, validate each sub-transaction, and validate the transaction based on the validation of all sub-transactions, wherein all sub-transaction must be valid for the transaction to be valid.

The present disclosure relates generally to the field of blockchain processing, and more specifically to improvements of blockchain processing time.
Blockchains offer immutability of data by replicating data across all nodes of a network. In order to be able to validate the blockchain, nodes generally require access to the complete history of actions. A complete history of actions is typically listed on the chain and is visible for all participants.

Parallel processing of blockchain procedures

International Business Machines Corporation


A phase-domain delta-sigma (ΔΣ) modulator in a phase digitizer determines a demodulated phase error based on a phase-modulated frequency signal, in which a carrier frequency is modulated with a fundamental frequency and an associated phase, and a selected one of a set of reference signals, where the demodulated phase error represents a difference between the phase and a reference phase of the selected one of the set of reference signals. Moreover, a digital filter in the phase-domain ΔΣ modulator filters the demodulated phase error. Furthermore, a latch in the phase-domain ΔΣ modulator provides a bit stream by sampling one or more bits of the filtered demodulated phase error, where an average value of the bit stream represents the phase. Next, control logic in the phase-domain ΔΣ modulator selects the one of the set of reference signals.

Because of their small size, low cost, ease of use and digital output, integrated temperature sensors are widely used. These integrated temperature sensors are often based on the temperature dependence of bipolar transistors (BJTs). However, because BJTs are sensitive to process spread, their untrimmed inaccuracy is typically limited to a few degrees Celsius. While the inaccuracy of BJTs can be improved by trimming individual devices, this usually increases production test time and the device cost. Furthermore, in advanced deep-submicron CMOS technologies (such as those used in state-of-the-art microprocessors), the performance of BJT-based temperature sensors usually deteriorates significantly. For example, temperature errors of up to 5° C. have been reported. This degraded performance is at odds with the increasing need for thermal management (and for integrated temperature sensors) in microprocessors and other very-large-scale integrated circuits (ICs) because of the increasing power density and the increasing number of processing cores in such chips.
Another technique for measuring temperature (T) is via the thermal diffusivity of silicon (D), which has a T1.8 temperature dependence. For example, D can be determined by measuring the characteristics of an electrothermal filter (ETF). As shown in FIG. 1, an existing ETF can include a heater and a relative temperature sensor (such as a thermopile) fabricated on the substrate of a silicon chip. In the ETF, power dissipated in the heater generates heat pulses that diffuse through the silicon over a distance (s) between the heater and the temperature sensor, creating temperature fluctuations at the temperature sensor. The time it takes for these pulses to diffuse is a function of absolute temperature or, in other words, the ETF adds a temperature-dependent phase shift (φETF) to a signal at a particular frequency. When the heater is driven at a frequency (fdrive), the temperature sensor output has the same frequency but with a relative phase shift that can be approximated as
      ϕ    ETF    ∝            -      s                                                π                                                                                f              drive                                D                    .      At constant fdrive, φETF has a near-linear T0.9 temperature dependence. Therefore, by digitizing the time delay associated with diffusion of the heat pulses, ETFs can be used as temperature sensors. Note that microprocessors typically operate at well-defined clock frequencies, so that a known fdrive is usually available in these applications.
In contrast to BJTs, ETFs usually do not require trimming because, for IC-grade silicon, D is well-defined and the distance between the heater and the relative temperature sensor is typically accurately determined by lithography. As a consequence, the inaccuracy of an ETF-based temperature sensor scales with the critical dimension of the lithographic process used. For example, ETFs with identical geometry have achieved untrimmed inaccuracies of ±0.7° C. (3σ) and ±0.2° C. (3σ) in 0.7 μm and 0.18 μm CMOS, respectively, indicating that the dominant source of error is lithographic spread. Therefore, the performance of ETFs is expected to improve greatly in modern microprocessors, which are implemented in even more advanced deep-submicron CMOS processes. Furthermore, because D is only weakly sensitive to doping fluctuations at the doping levels typically used in IC technology, the variation between wafers and process lots is small.
The availability of a known driving frequency together with the scaling properties of ETFs make them a promising alternative to current thermal management solutions in modern microprocessors. However, because of power-consumption constraints, the amount of power dissipated in the heater of an ETF is typically limited. In conjunction with the high thermal conductivity of silicon, this power-dissipation constraint leads to small signals at the output of the temperature sensor. Therefore, a precision readout interface is usually needed to extract φETF (and, thus, temperature information) from these small signals.
FIG. 2 illustrates an existing system that includes a phase-detection circuit. In this circuit, the ETF is driven at a constant frequency fdrive (which may be obtained from a digital system clock), and its phase-shifted output is multiplied with a reference signal at the same frequency but having a controlled phase shift (φdemod). Furthermore, the DC component of the multiplier output is proportional to the cosine of φdemod−φETF. The integrator in the phase-detection circuit in FIG. 2 drives the phase-shift controller so that this DC component becomes zero, which corresponds to a fixed 90° difference between the two phase shifts. As a consequence, this feedback loop functions as a narrowband and, therefore, low-noise, phase detector. While FIG. 2 includes a sine-wave drive, fdrive can be associated with an arbitrary periodic signal. For example, a square-wave may be used. Note that, because the ETF is a low-pass filter, the amplitude of the higher harmonics of fdrive in its output signal will be quite small.
When the feedback loop in the phase-detection circuit is locked, the analog control signal driving the phase shifter is a measure for φETF. However, the processing of the signals output by the ETF typically requires them to be digital, and so a phase-domain analog-to-digital converter (ADC) is often used. Such an ADC digitizes the relative phase difference between two signals, both of which are at the same frequency.
As shown in FIG. 3, one way to implement a phase-domain ADC is to replace the analog-controlled phase shifter with a digital one. In this circuit, an n-bit ADC samples the integrator output at a sampling rate fsample (which may be oversampled for high resolution), and feedback is provided through an n-bit digital phase rotator. However, for high n (for example, more than 12 bits), the implementation of an accurate digital phase rotator or an n-bit ADC is usually non-trivial. Typically, a single-bit phase-domain delta-sigma ADC (PDΔΣ) is easier to implement.
An existing system that includes a single-bit PDΔΣ ADC is illustrated in FIG. 4. This PDΔΣ ADC is a 1-bit implementation of the phase-detection circuit shown in FIG. 3. The two phase shift references, φ0 and φ1, are digitally generated square-waves with the same frequency as the input signal and which span the phase-shift input range of interest (for clarity, the fundamental harmonics are indicated in FIG. 4). Moreover, the value of fsample is chosen to be substantially larger than the signal bandwidth, which is referred to as 'oversampling.' In such an oversampled modulator (which is often referred to as a 'delta-sigma modulator'), the quantization error associated with the 1-bit ADC is shifted out of the frequency band of interest through noise shaping, thereby offering high resolution after filtering by an appropriate decimation filter. The digital value obtained at the output of the decimation filter is thus a weighted average of the value of the input signal over the conversion period, and so such delta-sigma ADCs belong to the class of averaging converters. Delta-sigma ADCs are well suited for digitizing narrowband signals with high resolution, as is typically required for sensor interfacing. PDΔΣ ADCs have been successfully used to read out ETFs, achieving effective phase resolutions of up to 16 bits.
Usually, the phase-shift input range of the PDΔΣ ADC is chosen large enough to span the expected range of values for φETF over temperature. For example, φ0 and φ1 may be −45° and +45°, respectively, so that, as φETF varies from 60° to 100°, the cosine of φETF−φ0−90 is always positive, while the cosine of φETF−φ1−90 is always negative. This design choice ensures stable feedback-loop operation. FIG. 5 illustrates the measured ETF phase characteristic.
In many existing phase-domain ADCs there are typically non-idealities associated with the analog implementation of the integrator (loop filter) and the modulator. In particular, an analog integrator has several non-idealities, such as: limited dynamic range, non-linearity and finite DC gain. Moreover, the non-ideal switches used in analog demodulators can introduce charge injection and residual offset. It is increasingly difficult to design such analog circuits in modern nanometer-scale CMOS processes, which are basically optimized for the realization of digital circuits. The main challenges include the low intrinsic gain of the transistors (which often requires the use of complicated multi-stage amplifiers) and the low supply voltages (which reduce dynamic range and signal-to-noise ratio). Consequently, it is increasingly difficult to scale such readout architectures to the nanometer-scale CMOS processes in which large-scale integrated circuits (such as microprocessors) are realized.
Therefore, there is a need for a phase digitizer without the problems listed above.

Stiching Vour de Technische Wetenschappen


Provided is a method for the production of transgenic animals, especially pigs, by the use of nuclear transfer from genetically modified or other embryonic stem cells to either enucleated oocytes which were matured in vivo or in vitro and activated or to enucleated zygotes.

The field of this invention is the area of methods for the genetically engineering of non-human animals, in particular those comprising the step of nuclear transfer, and animals produced by such methods.
Techniques for transgenic animal production have been well established for mice (Gordon and Ruddle, 1981) and pigs (Brem et al., 1985; Hammer et al., 1985). However, efficiencies for production of transgenic animals, especially large domestic animals, are generally low. The efficiency of producing a transgenic pig from pronuclear injection can range from 1 to 10% at a cost of approximately $25,000 (Wheeler and White, 1993). The possible use of embryonic stem (ES) cells to produce transgenic animals provides a unique opportunity to increase the efficiency and decrease the cost of transgenic pig production as well as provide more stable gene integration (Wheeler, 1994).
Embryonic stem cells offer an effective tool for producing genetically identical individuals. Embryonic stem cells can be electroporated with deoxyribonucleic acid (DNA) to introduce, replace or inactivate genes of interest. These ES cells can be screened, in vitro, for incorporation of genes in the appropriate location within the genome. Theoretically, screened ES cells could be used as karyoplasts (donor nuclei) for nuclear transfer (NT) to produce an entire individual. This technology has many exciting uses including acceleration of genetic progress, propagation of superior genetic lines and production of transgenic animals. Transgenic animals can be developed for the production of human pharmaceutical proteins, tissues and organs for human transplantation, and animals with improved quantitative traits (i.e., reproduction, growth, carcass or milk composition; Wheeler, 1994). Further, development of NT embryos provides a method for testing the totipotency of ES cell lines.
Nuclear transfer has been reported in amphibians, mice, rats, rabbits, sheep, pigs, cattle (see Prather and First [1990] for review), goats (Yong et al., 1991), domestic cats (Shin et al., 2002), monkeys (Mitalipov et al., 2002), fish (Lee et al., 2002) and mules (Holden, 2003). Numerous studies concerning NT with blastomeres from early embryonic stages have been reported (Prather and First, 1990). However, the number of genetically identical blastomeres is limited with these transfers.
There is a need in the art for efficient means for producing transgenic animals and for reproducing animals, endangered species as well as domesticated livestock.

Nuclear transfer with porcine embryonic stem cells

The Board of Trustees of the University of Illinois


The present invention provides methods for increasing secretion of dopamine and other neurotransmitters and treating or reducing the incidence of diseases involving decreased secretion of dopamine and other neurotransmitters, e.g. Parkinson's disease, comprising administering to the subject a uridine or a source thereof, and compositions for treating or reducing an incidence of Parkinson's disease, comprising a uridine, a uridine monophosphate, or a source thereof.

Parkinson's disease (PD) is a common disabling disease of old age affecting about one percent of the population over the age of 60 in the United States. The disease is associated with a reduction in dopamine release from the corpus striatum, leading to severe imbalance of dopamine/acetylcholine in the brain. Dopamine acts in the brain as a neurotransmitter in the synaptic cleft of the neurons, promoting signal transmission between cells.
Parkinson's is a progressively degenerative disease characterized by, among other symptoms, muscle rigidity, coarse tremors and postural deformity. Most conventional treatment methods try to ameliorate the resulting chemical imbalance by either reducing acetylcholine production and/or increasing dopamine concentration, with accompanying side effects that are the result of the new balance attained. One such method of treating PD involves the administration of a dopamine precursor like L-DOPA to promote dopamine release and the stimulation of its post-synaptic receptors. However, L-DOPA has a short half-life in the body and the effect of L-DOPA eventually becomes sporadic and unpredictable, resulting in fluctuations in motor function, dyskinesias and psychiatric side effects.
Thus, there is a need for a treatment of conditions characterized by decreased dopamine release. It is also desirable to have a treatment that will delay the onset of symptoms, and/or alleviate or retard symptomatic expression of the disease.


A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

Traditional signal amplitude detection circuit usually detects signal amplitudes by a way of using analog circuit filtering or analog signal amplitude-energy conversion, namely by a way of using analog circuits to realize the detection for the signal amplitude mainly. However, the detection result of the analog circuits may have an error due to some factors in technological process, and the bandwidth of analog filters and working point of the analog signal amplitude-energy conversion circuit cannot be determined accurately; moreover, no matter whether the analog filter or the analog signal amplitude-energy conversion circuit is used, it's necessary to add an extra A-D conversion circuit if the signal amplitude undergoes a detection by a following digital circuit, which brings a complicated structure for the whole signal amplitude detection circuit, thereby resulting in a difficult implementation.
Therefore, there is a need to provide an improved signal amplitude detection circuit to overcome above drawbacks.

IPGOAL MICROELECTRONICS (SICHUAN) CO., LTD.


A method of analyzing exhaust gas emissions from an internal combustion engine is modified by the provision of a data process or connected to an exhaust gas analyzer and adapted to monitor changes in exhaust gas concentrations and to identify changes indicative of the state of operation of a catalytic system provided in the engine exhaust delivery system. The catalyst-on condition is identified by reference to the characteristic shape of the plot of the gas concentrations against time. Similar identification of catalyst-off conditions is provided by corresponding analysis of concentration changes and concentration values. The system can distinguish between various causes of the catalyst-off condition.

1. Field of the Invention
This invention relates to a method and apparatus applicable inter alia to determining catalyst operation in automotive vehicle exhaust systems and applicable to comparable operations for other internal combustion engine systems. A principal application of the invention is to a method and apparatus for use in routine testing of automotive vehicle exhaust gas emissions. In such testing work, the presence of catalytic systems, and the operation of such systems has a direct bearing on the results obtained from such testing work, and there is a need for a more systematic approach to dealing with the variables introduced into such testing work by the presence of catalytic converters.
A broader aspect of the invention relates to the analysis of exhaust gases from an engine system in such a way that transient changes in the concentrations of the exhaust gases are used to provide an indication of the state of operation of the engine and/or its exhaust delivery system including a catalytic converter, if provided.
In automotive applications of the present invention, it will be understood that the method and apparatus will usually find application as part of the routine test equipment employed for analyzing the exhaust gas emissions from such automotive vehicles. The information provided by the method and apparatus of the invention in relation to the operation of a catalytic converter system will usually be used as part of the systematic test work carried out to determine the levels of exhaust gas emissions, and in particular as to whether such emissions meet legislative requirements. The information provided by the method and apparatus of the invention enables a test operation to be carried out with greater certainty and precision. It also enables, in certain cases, a relatively rapid determination to be made that replacement of a catalytic system is required or that associated control equipment such as the so-called lambda sensor or the vehicle's ECU require attention.
2. Description of the Prior Art
Turning to the general background of the invention, it is well known that in response to legislative pressure, catalytic converters are being installed in all new vehicles, at least in certain countries. A catalytic converter however may fail or degrade as a result of age or prolonged usage. Damage arising from failure of another component within the emissions system of the vehicle can also occur. Examples of such related failures are failures of the so-called lambda sensor (which senses the appropriate air/fuel ratio in the engine fuel feed and controls same to ensure proper operation of the catalyst). Another example is the engine electronic control unit (ECU), operation of the engine with leaded fuel or with too lean a fuel mixture, physical shock etc. These factors can all cause total or partial failure of a catalytic converter. Additionally, such converters do not operate at low temperatures i.e., during the first minutes of operation of a vehicle, and neither do they operate in conditions of low exhaust gas flow, e.g., when the engine is idling in heavy traffic.
Accordingly, tests carried out to determine whether a vehicle's exhaust emissions meet legislative requirements need to take into account the state of functionality of the catalytic converter itself and/or its associated control equipment. If, for example, a catalyst fails to turn on (known as "light-off") during emissions testing, as a result of the vehicle not having been warmed up or operated for a sufficient length of time, the vehicle may fail its roadworthiness test. Equally, a catalyst may turn off during testing if the vehicle idles (e.g., at 1K rpm) too long between test phases (e.g., at 2K rpm). A means for automatically indicating catalyst switch-on and/or switch-off would greatly assist in avoiding this problem. Furthermore, a means to detect related partial or complete failures such as those of associated control equipment and an ability to detect and distinguish between such failures and partial or complete failure of the catalyst itself would be an aid to more general diagnostic work.
There is disclosed in U.S. Pat. No. 5,175,997 (Blanke) a feedback control system which analyses three different constituents of the exhaust stream and selectively controls the fuel mixture and air injection of the engine to positively activate and deactivate the catalytic converter, for taking measurements from which the efficiency of the converter can be calculated. The system does not use the gas concentration data to determine the operating state of the converter.
U.S. Pat. No. 5,341,643 (Hamburg) discloses an on-board feedback control system which utilises analysis of plural constituents of the exhaust emissions to control the air/fuel mixture operation of the engine so as to maintain optimum convertor efficiency.
U.S. Pat. Nos. 5,157,921 (Ito) and 5,400,592 (Mukaihira) and 5,417,061 (Maeda) and 5,526,643 (Mukaihira) all disclose on-board systems for detecting deterioration of the catalyst of a catalytic convertor system by means of monitoring concentrations of one or more constituents of the exhaust emissions.
To the best of the Applicants' knowledge a method and apparatus for determining the characteristic shape of the plots of gas concentrations against time of two or more constituents of the gas content of the exhaust output from an internal combustion engine as a means for determining catalyst state of operation, such as catalyst-on or catalyst-off condition, or indeed the analysis of the switch-on and switch-off speeds as a basis for determination of catalyst efficiency and/or remaining life, has not previously been proposed.

Method and apparatus for analyzing catalyst and other systems operations


A pet food containing vitamin D analogs for use in treatment of cancer in pets, such as dogs and cats, is described. Also described is a method for treating pets, such as dogs and cats, for cancer by feeding the pet a pet food containing at least one vitamin D analog.

Pets play an important role in many peoples lives, and consequently many pet owners will go to considerable lengths to treat their pets for major illnesses, such as cancer. Cancer is one of the major forms of mortality in pets such as cats and dogs, and therefore the pet owners desire ways of treating this disease in their pets to increase their longevity. Such treatments ideally would be not only economical, but also practical for owners rather than veterinarians to administer to the pet.
Present methods of treating cancer in pets focus primarily on surgical resection of solid tumors. Surgery is expensive, and moreover, is not suitable treatment for many cancers. Among these are leukemias and lymphomas, where surgery obviously is not an option, but this class includes highly disseminated malignancies as well as ones with poorly defined margins or those arising in inoperable locations.
It would therefore be desirable to have a way of treating cancer in dogs and other pets that could be administered routinely by pet owners and that would not be resisted by the pet. Ideally, such treatment could be administered with the pet's food.

Method and product for treating cancer in pets


A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer.

A finned field effect transistor (finFET) is a FET that includes a fin-shaped channel region. A gate structure intersects the channel region, and the ends of the fin structure receive source and drain doping. The dimensions of the fin affect the operation of a finFET. For example, the length of the fin under the gate, measured in the direction from source to drain, determines the effective channel length of the device. It is desirable to form fins having a consistent height, and forming a finFET on a silicon-on-insulator (SOI) wafer provides improved fin height uniformity. This improved uniformity may be important as fin height scales.
For various applications, including system on chip (SOC) operation, it is useful to make finFETs with fins having at least two different heights. When bulk silicon is used, fin height can be controlled by removing different amounts of the shallow trench isolation (STI) oxide layer around different groups of fins. Essentially, all fins have the same height when measured from the underlying silicon layer, but different amounts of the STI oxide region are left around different fins so that different heights of the fins are left projecting from the STI layer. However, when an SOI wafer is used, the thickness of the silicon layer is predetermined, and the conventional method cannot be used without modification to achieve different fin heights. Instead, it may be necessary to form an STI layer on the SOI active silicon layer, mask the area over a fin that is to be a shorter fin and selectively etch the STI layer around another fin to form a taller fin, which is similar to the method used in bulk substrate and that undermines the intended benefit of finFET on SOI substrate.
Another known method for forming a finFET on an SOI wafer with fins having different heights is illustrated in FIGS. 1-6. FIG. 1 illustrates a conventional SOI wafer 100 that includes a substrate 102, a bottom oxide (BOX) layer 104 and an active silicon layer 106 having a top surface 108. In FIG. 2, a hardmask 202, which may comprise silicon nitride, for example, is formed on the top surface 108, and a patterned resist 204 is formed on the hardmask so that a first portion 206 of the SOI wafer 100 is masked and a second portion 208 of the SOI wafer 100 is not masked. In FIG. 3, the portion of the hardmask 202 that is not protected by the resist 204 is etched down to the top surface 108. With the top surface 108 exposed and the first portion 206 of the SOI wafer 100 protected, the top surface 108 is oxidized to form a depression 402 filled with a top oxide layer 404 as illustrated in FIG. 4. The oxidation process produces a generally symmetric oxide layer 404 which projects upwardly beyond the top surface 108 of the active silicon layer 106 about as far as it projects downwardly into the active silicon layer 106.
FIG. 5 shows the SOI wafer 100 after the hardmask 202 and patterned resist 204 have been removed at which time a first plurality of masks 502 are formed in the first portion 206 of the SOI wafer 100 and a second plurality of masks 504 are formed in the second portion 208 of the SOI wafer 100 on the top oxide layer 404. The silicon not protected by the first plurality of masks 502 in the first portion 206 and the silicon and oxide not protected by the second plurality of masks 504 in the second portion 208 are etched away to produce a plurality of fins. FIG. 6 illustrates a first plurality of fins 602 in the first portion 206 of the SOI wafer 100 that are taller than a second plurality of fins 604 in the second portion 208 of the SOI wafer 100. While this method may produce fins for a finFET that are acceptable for some applications, the uneven top surface created by the top oxide layer 404 protruding from the top surface 108 of the active silicon layer 106 may make it difficult to apply masks for later forming the first and second plurality of fins.
It would therefore be desirable to provide a method of forming fins on an SOI wafer that have different heights in a manner that does not require the addition of an STI layer to the SOI wafer and that provides a substantially even surface on which to form a mask for forming the different height fins.

Method of forming finFET having fins of different height


An ultrasonic probe comprising a coaxial cable 11 capable of transferring an energizing pulse voltage and an echo signal, at least one piezoelectric element 5, an acoustic matching layer 7 disposed on a sound transmitting face side of each piezoelectric element 5 and an acoustic backing layer 8 disposed on its opposite side, the above ultrasonic probe being adapted to transmit and receive an ultrasonic wave, wherein each piezoelectric element 5 has the following distribution of spontaneous polarization according to positions of the piezoelectric element. The spontaneous polarization of the ultrasonic probe of the present invention has differences such that the spontaneous polarization is caused to be strong at a position where the absolute value of Bessel function J.sub.0 (x/a) is large while the spontaneous polarization is weak at a position where the absolute value of J.sub.0 (x/a) is small.

1. Field of the Invention
The present invention relates to an ultrasonic probe and ultrasonic probe device for use in, for example, ultrasonic endoscopes employed for medical purposes, a process for producing a piezoelectric element for use in such an ultrasonic probe and an ultrasonic diagnostic equipment and system using such an ultrasonic probe.
2. Discussion of Related Art
The common structure of conventional ultrasonic probes is as shown on page 186 of "Handbook of Medical Ultrasonic Equipments" edited by Electronic Industries Association of Japan (corporate juridical person) and published by Corona Publishing Co., Ltd., Tokyo, Japan, and they are fabricated by bonding a piezoelectric element composed of a piezoelectric ceramic plate as represented by PZT whose two principal surfaces are provided with a pair of electrodes to an acoustic backing layer and further bonding an acoustic matching layer and an acoustic lens thereto.
In this ultrasonic probe, a pulser applies pulsed energizing voltage of about one hundred or hundreds of volts to the above piezoelectric element, so that a rapid morphology change is caused to occur by the converse piezoelectric effect of the piezoelectric element. The resultant vibration is transmitted through the acoustic matching layer and the acoustic lens to thereby effectively transmit pulses toward an object to be observed. The transmitted pulses are reflected at each tissue interface of the body in medical uses or at a noncontinuous part such as any of various defects inside an object to be examined in nondestructive inspections and retransmitted through the acoustic lens and the acoustic matching layer to thereby apply mechanical vibration to the piezoelectric element. This mechanical vibration is converted to electrical signal by the piezoelectric effect of the piezoelectric element, which is observed by means of a diagnostic equipment.
Various methods are available for enhancing the resolution in the imaging, which include modifying the acoustic lens and the pattern of the electrode of the piezoelectric element and curving the surface of the piezoelectric element itself so as to slenderize the transmitted ultrasonic beam. Further, an annular array sound field forming is being tried in which the electrode is split into several parts to thereby cause applied energizing pulse voltages to have differences.
Moreover, with respect to the ultrasonic probe, for example, an invention is noted which is described in Japanese Patent Application Laid-Open Specification No. 111198/1990. In this invention, for example, a full covering electrode 152 is disposed on one side of a piezoelectric ceramic 151 while split electrodes 153a, 153b, 153c are disposed on the other side of the piezoelectric ceramic as shown in FIGS. 47 and 48. Thus, the invention provides a piezoelectric element 154 in which, with respect to the distribution of polarization intensity, the central split electrode 153a has a strong spontaneous polarization, the spontaneous polarization becoming weaker as the distance to the peripheral split electrode 153c is decreased, and also provides an ultrasonic probe including this piezoelectric element 154.
However, all the conventional methods of improving the resolution of an ultrasonic image of the ultrasonic probe have had respective advantages and disadvantages. In particular, the ultrasonic probe including an acoustic lens or a piezoelectric element that has a curving, especially concave, surface advantageous in that the ultrasonic beam is slenderized near the focus to thereby enable obtaining an image of high resolution but has a drawback in that the beam width is enlarged as the distance from the focus is increased to thereby deteriorate the image quality. Accordingly, the optimum observation distance permitting practical observation becomes unfavorably small.
In this connection, measuring the sound field of ultrasonic beam transmitted from the ultrasonic probe and determining the beam width thereof demonstrates that the region where the beam width is small is extremely reduced so that the optimum observation distance (depth of focus) permitting practical observation is small as shown in FIG. 49 (in FIG. 49, the axis of abscissa represents the distance X (mm) between the face transmitting ultrasonic beam and the measuring point while the axis of ordinate represents the beam width (mm) at the measuring point; the above beam width means the portion of at least 50% (-6 dB) of the maximum acoustic pressure in a plane at right angles to the beam axis, the beam width meaning the diameter of the area thereof).
In the use of the ultrasonic probe of the annular array type, it is known that the focusing point of ultrasonic beam can be changed (the depth of focus can be increased) by, for example, providing a plurality of pulsers or devising the circuit to thereby control the phase of voltage applied to each ring-shaped electrode.
That is, the ultrasonic wave can be converged so as to focus on a point to be observed to thereby enable clear observation of the point. Further, it is feasible to repeat ultrasonic wave transmission and receiving a plurality of times while changing the focal length and synthesize received signals so that a clear image is obtained in a wide range.
However, in the above method, a plurality of leads must be connected to the piezoelectric element. Complete shielding is required for avoiding the entry of noise between the plurality of leads. This is disadvantageous from the viewpoint of the reduction of the diameter of the ultrasonic probe for use in medical applications and the like. Further, there is the problem that the requirement for a complex electrical circuit capable of phase control as mentioned above would cause a huge increase of the cost of the diagnostic equipment.
In the method comprising repeating transmission and receiving while changing the focal length and synthesizing a plurality of received signals, the time required for gaining a sheet of image is increased, so that the frame rate (number of images per time) is lowered. Consequently, the problem occurs that the image is fluctuated by, for example, the somatic movement, respiration or heart beat of the examinee to thereby disenable satisfactory diagnosis.
In the use of a concave transducer as another usage of the annular array type, a technique is available such that all parts are simultaneously driven at the time of transmission to thereby transmit ultrasonic wave while the area of receiving parts is increased in accordance with the observation distance at the time of receiving to thereby attain enhanced resolution. However, as in the above method, this technique encounters problems such that not only is the wiring complex to thereby render production difficult but also the electrical circuit such as an adder circuit becomes complex so that high cost and lowered reliability would result.
Distributing the ultrasonic wave transmitted by an ultrasonic transducer so as to be strong in the center and weak in the periphery enables reducing the side lobe, i.e., transmission of ultrasonic wave in essentially unintended directions. It is known that the side lobe reducing effect is especially high when a provided acoustic pressure distribution has a graphical profile of the normal distribution (Gaussian distribution). The object of the invention of Japanese Patent Application Laid-Open Specification No. 111198/1990 is directed toward this effect, but the invention has drawbacks in that there is no effect of focusing ultrasonic wave with the optimum observation distance being small.
It is known that distributing the ultrasonic wave transmitted by an ultrasonic transducer in a profile of the zeroth-order Bessel function would cause the ultrasonic wave to become diffractionless ultrasonic beam, i.e., wave being propagated without diffusion. The use of the thus obtained diffractionless ultrasonic beam enables obtaining image produced by ultrasonic beam of uniform width from near the ultrasonic transducer to a position distant therefrom. That is, image of line focus can be obtained realizing clear focusing from near the ultrasonic transducer to a position distant therefrom.
The method was reported for realizing the above ultrasonic beam, in which use is made of a piezoelectric element provided with concentric multi-ring electrodes to each of which a driving circuit is connected by means of cables and in which the energizing pulse voltage applied to each electrode ring is distributed in a Bessel profile. However, in this method, a plurality of cables must be connected to the piezoelectric element. Complete shielding is required for avoiding the entry of noise between the plurality of cables. This is disadvantageous from the viewpoint of the reduction of the diameter of the ultrasonic probe for use in medical applications, especially, applications inside the body cavity. Further, there is the problem that the requirement for a complex electrical circuit capable of effecting voltage and phase controls would cause a grave increase of the cost of the diagnostic equipment.
The following reference describes a method of fabricating a piezoelectric element of the Bessel polarization type which has similarity to the piezoelectric element for use in the present invention:
title: Bessel beam ultrasonic transducer: Fabrication method and experimental results, PA1 authors: D. K. Hsu, F. J. Margetan and D. O. Thompson, and PA1 publication: Appl. Phys. Lett. 55(20), 13 Nov. 1989, pp 2066-2068. PA1 a piezoelectric element is fabricated which is provided with two concentric circular grooves of different depths and a central cavity, PA1 polarization is effected by the application of polarization voltages having polarities different between the grooves and the face opposite thereto; at that time, mutually neighboring grooves and cavity have respective voltages of different polarities applied thereto, and PA1 the grooves are polished to thereby remove the same, so that a flat piezoelectric element is obtained. PA1 polarization voltage is applied not only between the electrodes opposite to each other with the piezoelectric element interposed therebetween but also between the electrodes neighboring to each other, so that the occurrence of part 155 polarized parallel to a principal surface of the piezoelectric element 154 as shown in FIG. 50 is inevitable with the result that undesired vibration is likely to occur at the time of driving with voltage applied to thereby transmit ultrasonic wave of undesired frequency in undesired directions, which generates virtual image attributed to artifacts on the ultrasonic image to thereby deteriorate the quality of the ultrasonic image, and PA1 major portion of the piezoelectric element is polished away after the polarization, so that the fabrication time is prolonged and that the yield becomes poor because of the required grooving and polishing after the polarization.
The above reference employs the following method in which:
However, the piezoelectric element obtained by the method of this reference has drawbacks in that:

Ultrasonic probe, ultrasonic probe device. process for producing piezoelectric element for use in ultrasonic probe and ultrasonic probe and ultrasonic diagnostic equipment and system using ultrasonic probe


A plastic component, usable in a combustion engine, is made by forming an elastomeric seal onto at least one support element. The support element, complete with the seal, is placed in a cavity or fixture of a plastic injection mold, and the plastic component is created only by forming plastic material onto the support element. The finished plastic component with the molded-on seal is removed from the cavity.

1. Technical Field
The invention consists of a process for the manufacture of a plastic component, usable in a combustion engine, connected effectively with an elastomeric seal.
2. Related Art
A plastic cover, made by injection molding, and made of at least two different plastics, can be seen in EP-A 0665370. The cover can be effectively connected with an elastomeric seal. A stiffening material is not indicated between the seal and the plastic cover. In EP-B 0860602, a process for the manufacture of a cylinder head cover for a combustion engine, as well as a cylinder head cover, is described. The cylinder head cover is made using the following process steps:
Forming the cover component out of plastic
Activation of an opposing surface of the seal, in the cover component, by coronal treatment
Application of adhesive on the activated surface of the seal and/or a corresponding surface on the cover component
Placing the cover component and the seal in a heatable, pre-warmed adhesive fixture
Holding the adhesive fixture in a closed condition for a prescribed time at a prescribed temperature, and
Removing the finished cylinder head cover from the adhesive fixture.
The seal, which is provided with a support element, is created independently from the cover, so that two different molds are needed to make the individual parts, and a further mold is needed to accept both elements, before an effective connection of the two elements can be achieved.
A cover fixture for closing off motor housings can be seen in DE-A 196 233 36, in particular a valve cover fixture for the cylinder head of a motor vehicle motor. The cover fixture contains a valve cover as well as an elastically bending seal that is seated in a groove that runs around the surface of the valve cover that is oriented toward the cylinder head. A seal holder that can be connected to the valve cover, and which holds the shape of the seal that can be attached between the groove floor and the cylinder head, is provided with pass-through openings for the seal.
For components that are made of plastic, such as covers, lids, or similar, due to the properties of larger tolerances relative to metal covers, the seals have to be able to adapt more. This is based largely on the lower stiffness and larger relaxation and modifying influences than with metal covers.

Process for the manufacture of a plastic component with a seal, and assembly unit

Federal Mogul Sealing Systems Bretten GmbH & Co. KG