A method and apparatus for sputter deposition in which both a pulsed DC power supply and an RF power supply apply power to the target in the sputter deposition equipment. The pulsed DC power supply provides an on cycle where power is applied to the target, and an off cycle, in which a reverse polarity is applied to the target. The application of the reverse polarity has the effect of removing any charge that may have built up on the surface of the target. This reduces the likelihood of arcing occurring on the surface of the target, which can degrade the quality of the film being deposited on the substrate. By applying RF power simultaneously with the pulsed DC power to the target, the ionization efficiency on the target surface is increased. This results in a greater amount of material being removed from the target surface more quickly.

Thin film conductive and non-conductive coatings on a substrate have many uses in industry, including coatings on flat panel displays, semiconductors, touch screen displays, energy control coatings on glass, and optical interference filters, among other uses.
These films are applied to surfaces in a variety of methods. One commonly used method is referred to as sputter deposition. Typically, in a sputter deposition process, the article to be coated, the substrate, is placed in a chamber. A plate of the material to be used in the coating, called the target, is also placed inside the chamber. The target is electrically connected to a voltage source, and serves as an electrical cathode/target. Typically, the sputtering chamber is evacuated, and a gas under pressure is pumped into the chamber. The gas selected for use in the chamber is dependent upon whether the sputtering process is to be a reactive or non-reactive process. If it is a reactive process, the gas is selected such that it reacts with the material of the target to form the desired material to be sputtered onto the substrate. For non-reactive sputtering, an inert, non-reactive gas is selected.
The target is electrically energized. The electrical field between the anode of the electrical source and the cathode/target will ionize the gas in the chamber. The gas ions are then driven into the target by the electrical field. When this is done with sufficient energy, some of the material is dislodged from the target. The dislodged material typically becomes electrically neutral a short distance from the target, and travels through the chamber from the target to the surface of the substrate. If the process is a reactive sputtering process, the dislodged material reacts with the gas as it is traveling through the chamber and may also be reacted at the surface of the substrate. At the substrate, the target material or reacted target material forms a thin film coating on the surface of the substrate. This method produces a high quality film, but the speed of sputtering must sometimes be very slow to overcome certain problems associated with the sputter deposition process and still maintain a consistent film coating.
There are several problems associated with sputter deposition processes, and in particular with reactive sputter deposition processes. For example, as the material is being sputtered, reactions can occur between the gas in the chamber and the target surface, forming a dielectric layer on the target that can act like a capacitor and cause electrical arcing. The arcing can cause uneven application of material to the substrate and defects in the coating. Varying the voltage applied or the speed at which sputtering is performed have helped reduce the problems and improve the quality of the film coating, but have not been completely successful in achieving all of these goals.
Non-reactive sputter deposition processes are relatively fast. Arcing typically occurs more frequently in reactive sputter deposition processes because reactions between the target material and the gas in the chamber occur more frequently. For this and other reasons, reactive sputter deposition is generally performed more slowly than non-reactive sputtering.
A variety of types of electrical sources have been used in an attempt to reduce or compensate for the electrical arcing that occurs. Electrical voltage sources used have included direct current (DC), alternating current (AC), and radio frequency (RF). While the different electrical sources have been found to reduce the incidence of arcing in certain configurations, there have continued to be problems with the systems. Additionally, with reactive sputtering, the speed at which deposition could be performed is still very slow, which increases the time necessary to produce an acceptable product, and therefore kept costs fairly high.
Therefore, what is needed is a system and method for performing sputter deposition that reduces or eliminates electrical arcing from the target, that does not impact the quality of the film being deposited and minimizes the reduction in speed of coating, especially when reactive sputtering is used.

System and apparatus for control of sputter deposition process


Guidewires and thin-film catheter-sheaths, fabricated using vacuum deposition techniques, which are monolayer or plural-layer members having ultra-thin wall thicknesses to provide very-low profile delivery assemblies for introduction and delivery of endoluminal devices.

The present invention relates generally to the field of medical devices, and more particularly to guiding means such as a guidewire for advancing a catheter within a body lumen to perform a minimally invasive procedure such as percutaneous transluminal coronary angioplasty (PTCA). The present invention further pertains to catheters and sheaths for delivering and deploying an implantable device within a body lumen.
In a typical PTCA procedure a guiding catheter having a preformed distal tip is percutaneously introduced into the cardiovascular system of a patient by means of a conventional Seldinger technique and advanced proximally until the distal tip of the guiding catheter is seated in the ostium of a desired coronary artery. A guidewire is positioned within an inner lumen of a dilatation catheter and then both are advanced through the guiding catheter to the distal end thereof. The guidewire is first advanced out of the distal end of the guiding catheter into the patient's coronary vasculature until the distal end of the guidewire crosses a lesion to be dilated, then the dilatation catheter having an inflatable balloon on the distal portion thereof is advanced into the patient's coronary anatomy over the previously introduced guidewire until the balloon of the dilatation catheter is properly positioned across the lesion. Once in position across the lesion, the balloon is inflated one or more times to a predetermined size with radiopaque fluid to compress the arteriosclerotic plaque of the lesion against the inside of the artery wall and to otherwise expand the inner lumen of the artery. The balloon is then deflated so that blood flow resumes through the dilated artery and the dilatation catheter is removed.
In a conventional stent delivery procedure, a stent is delivered endoluminally on a delivery catheter, then expanded either by an angioplasty balloon or by removing a constraining sheath and permitting the stent to radially expand by its shape memory, superelastic or self-expanding properties. Conventional guidewires for angioplasty and stent-delivery procedures usually comprise an elongated core member with the distal portion of the core member having one or more tapered sections and a flexible body such as a helical coil disposed about the distal portion of the core member. A shapeable member, which may be the distal extremity of the core member or a separate shaping ribbon which is secured to the distal extremity of the core member extends through the flexible body and is secured to a rounded plug at the distal end of the flexible body. Torquing means are provided on the proximal end of the core member to rotate, and thereby steer, the guidewire while it is being advanced through a patient's vascular system.
Further details of guidewires can be found in U.S. Pat. No. 4,516,972 (Samson); U.S. Pat. No. 4,538,622 (Samson, et al.); U.S. Pat. No. 4,554,929 (Samson, et al.); U.S. Pat. No. 4,616,652 (Simpson); U.S. Pat. No. 4,748,986 (Morrison et al.); U.S. Pat. No. 5,135,503 (Abrams); U.S. Pat. No. 5,341,818 (Abrams et al.); and U.S. Pat. No. 5,411,476 (Abrams et al.) each of which is hereby incorporated herein in their entirety by reference thereto.
A major requirement for guidewires and other intraluminal guiding members, whether they be solid wire or tubular members, is that they have sufficient column strength to be pushed through a patient's vascular system or other body lumen without kinking. However, they must also be flexible enough to pass through tortuous passageways without damaging the blood vessel or other body lumen through which they are advanced. Efforts have been made to improve both the strength and flexibility of guidewires in order to make them more suitable for their intended uses, but these two properties tend to be diametrically opposed to one another in that an increase in one usually involves a decrease in the other.
The prior art makes reference to the use of alloys such as NITINOL (nickel-titanium alloy) which have shape memory and/or superelastic or pseudoelastic characteristics in medical devices which are designed to be inserted into a patient's body. The shape memory characteristics allow the prior art devices to be deformed while in the martensite phase to facilitate their insertion into a body lumen or cavity and then be heated within the body to transform the metal to the austenite phase so that the device returns to its remembered shape or to exert a force on whatever prevents the device from returning to its zero strain configuration. Superelastic characteristics on the other hand generally allow the metal to be deformed and restrained in the deformed condition to facilitate the insertion of the medical device containing the metal into a patient's body, with such deformation causing the phase transformation, e.g. austenite to martensite. Once within the body lumen the restraint on the superelastic member can be removed, thereby reducing the stress therein so that the superelastic member can return to its original undeformed shape by the transformation back to the original austenite phase or so that the superelastic member can exert a force on whatever prevents the superelastic member from returning to its zero strain configuration. In other applications, the stress induced austenite to martensite transformation is utilized to minimize trauma while advancing a medical device such as a guidewire within a patient's body lumen.
Shape memory or superelastic alloys generally have at least two phases, a martensite phase, which has a relatively low strength and which is stable at relatively low temperatures and higher strains, and an austenite phase, which has a relatively high strength and which is stable at temperatures higher and strains lower than the martensite phase. Shape memory characteristics are imparted to the alloy by heating the metal at a temperature above body temperature, preferably between about 40° to about 60° C., while the metal is kept in a constrained shape and then cooled to ambient temperature. The cooling of the alloy to ambient temperature causes at least part of the austenite phase to transform to the martensite phase which is more stable at this temperature. The constrained shape of the metal during this heat treatment is the shape programmed when the alloy is reheated to these temperatures causing the transformation of the martensite phase to the austenite phase. The metal in the martensite phase may be plastically deformed to facilitate the entry thereof into a patient's body. The metal will remain in the pre-programmed shape even when cooled to a temperature below the transformation temperature back to the martensite phase, so it must be reformed into a more usable shape, if necessary. Subsequent heating of the deformed martensite phase to a temperature above the martensite to austenite transformation temperature causes the deformed martensite phase to transform to the austenite phase and during this phase transformation the metal reverts back to its remembered shape or to exert a force on whatever prevents the device from returning to its zero strain configuration.
When stress is applied to a specimen of a metal such as NITINOL® exhibiting superelastic characteristics at a temperature at or above which the transformation of martensite phase to the austenite phase is complete, the specimen deforms elastically until it reaches a particular stress level where the alloy then undergoes a stress-induced phase transformation from the austenite phase to the martensite phase. As the phase transformation proceeds, the alloy undergoes significant increases in strain but with little or no corresponding increases in stress. The strain increases while the stress remains essentially constant until the transformation of the austenite phase to the martensite phase is complete. Thereafter, further increase in stress is necessary to cause further deformation. The martensitic metal first yields elastically upon the application of additional stress and then plastically with permanent residual deformation.
If the load on the specimen is removed before any permanent deformation has occurred, the martensitic specimen will elastically recover and transform back to the austenite phase. The reduction in stress first causes a decrease in strain. As stress reduction reaches the level at which the martensite phase transforms back into the austenite phase, the stress level in the specimen will remain essentially constant (but substantially less than the constant stress level at which the austenite transforms to the martensite) until the transformation back to the austenite phase is complete, i.e., there is significant recovery in strain with only negligible corresponding stress reduction. After the transformation back to austenite is complete, further stress reduction results in elastic strain reduction. This ability to incur significant strain at relatively constant stress upon the application of a load and to recover from the deformation upon the removal of the load is commonly referred to as superelasticity or pseudoelasticity.
The prior art makes reference to the use of metal alloys having superelastic characteristics in medical devices which are intended to be inserted or otherwise used within a patient's body. See for example, U.S. Pat. No. 4,665,906 (Jervis) and U.S. Pat. No. 4,925,445 (Sakamoto et al). The Sakamoto et al. patent discloses the use of a nickel-titanium superelastic alloy in an intravascular guidewire which could be processed to develop relatively high yield strength levels. However, at the relatively high yield stress levels which cause the austenite-to-martensite phase transformation characteristic of the material, it did not have a very extensive stress-induced strain range in which the austenite transforms to martensite at relative constant stress. As a result, frequently as the guidewire was being advanced through a patient's tortuous vascular system, it would be stressed beyond the superelastic region, i.e. develop a permanent set or even kink which can result in tissue damage. This permanent deformation would generally require the removal of the guidewire and the replacement thereof with another. Products of the Jervis patent on the other hand had extensive strain ranges, i.e. 2 to 8% strain, but the relatively constant stress level at which the austenite transformed to martensite was very low, e.g. 50 ksi.
The prior methods of using the shape memory characteristics of these alloys in medical devices intended to be placed within a patient's body presented operational difficulties. For example, with shape memory alloys having a stable martensite temperature below body temperature, it was frequently difficult to maintain the temperature of the medical device containing such an alloy sufficiently below body temperature to prevent the transformation of the martensite phase to the austenite phase when the device was being inserted into a patient's body. With intravascular devices formed of shape memory alloys having martensite-to-austenite transformation temperatures well above body temperature, the devices could be introduced into a patient's body with little or no problem, but they had to be heated to the martensite-to-austenite transformation temperature which was frequently high enough to cause tissue damage and very high levels of pain.
What has been needed and heretofore unavailable is tubular body for intravascular devices, such as guidewires or catheter-sheaths, which have at least a portion thereof exhibiting superelastic and/or shape memory characteristics and which is fabricated by vacuum deposition techniques to provide precise control over the crystalline structure of the material used to fabricate the device.

Guidewires and thin film catheter-sheaths and method of making same


A resource unit has a request interface to allow the unit to receive a request and associated data. The resource unit also has a hashing engine to create a hash of the associated data, a modulo engine to create a modulus result, a read engine to perform a memory read, and a results interface to allow the device to return results.

With the increasing use of packet-based transmissions, many network devices such as switches and routers now use network processors. Network processors may be thought of as general purpose processors with special features or architectures to enhance and/or to optimize packet processing within networks. These processors are typically adapted to be more flexible and more easily programmable with regard to their packet processing features.
Much of the work of network processors involves activities such as accessing data structures for a particular data flow through the network device. They may also determine which of a set of parallel interfaces should receive packets from a particular input or corresponding to a particular flow. For example, a packet enters the network device and the processor needs to determine to which flow that packet belongs. This involves a cluster of information such as the source address of the packet, the destination address, etc.
This cluster of information is used to access static or dynamic per-flow state and other information such as a table of input interface attributes etc. for whatever entities inside the network device are involved in the flow for that packet. Reducing this cluster of information down to a more manageable size is useful to speed up access of the information needed to route the packet on its way. For example, ten or more bytes of source address, destination address, and protocol information might be reduced to a three-byte key which could be used to access state information for that particular flow.
This reduction is generally accomplished using hashing and modulo functions, in which a hash of the information is further reduced modulo the size of a table, and is then used as the access key to the table. However, hashing, particularly high-quality hashing which distributes the data sufficiently randomly across the desired address space, may be very time-consuming and require either more circuitry which raises costs, or more processor cycles which lowers performance.
In addition, many network processors may not have division units used to carry out the modulo reduction of the hash result. Division is generally an expensive operation to implement in hardware, uses too many cycles to be implemented efficiently in software, and is not generally needed for any packet-processing operations other than modulo reduction of the hash result. Therefore, network processor architectures usually do not include division capabilities.


The occurrence of more and the deterioration of performance are suppressed. A data compression unit stores identification data indicating the presence or absence of periodicity, and printing data correlated with the identification data in a first memory area of a RAM. A color conversion processing unit that performs speculation processing stores printing data that has undergone color conversion processing corresponding to printing by a printer in a second memory area of the RAM. A screen processing unit that performs speculation processing performs AM screen processing on printing data. The screen processing unit confirms the identification data stored in the first memory area of the RAM by the data compression unit, and in a case where the identification data indicates there is periodicity, instructs to perform color conversion processing corresponding to printing by a copier on printing data, and performs FM screen processing on the printing data.

In an image forming apparatus such as a MFP Multifunction Peripheral), and the like, for example, a method of performing gradation representation of an image such as AM screen processing, which is amplitude modulation for reproducing halftones, or FM screen processing, which is a frequency modulation method, is used.
Incidentally, an AM screen represents gradation by changing the size of regularly arranged halftone dots, and is generally used for printing by a printer. On the other hand, an FM screen represents gradation in density of small halftone dots arranged in random, and generally, it is often used for printing by a copier.
Note that when an AM screen is used, although the shade of color may be represented by changing the size of halftone dots, interference fringes (hereinafter referred to as moire) may occur in an image due to the regularity of halftone dots. On the other hand, an FM screen does not have regularity in halftone dots, so although moire is not likely to occur, advanced techniques are required for managing minute halftone dots.
Here, as a technique for suppressing the occurrence of moire, Patent Literature 1 proposes an image forming apparatus that, when a reading unit reads an image of a document as document image data, a control unit switches the image processing method for image data to be overwritten onto the document based on the document image data.

Image forming apparatus and image forming method


An apparatus for diagnosing an abnormality of a vehicle sensor is provided. The apparatus includes a sensor configured to measure an acceleration and an angular velocity of a vehicle, a camera configured to generate a front time series image frame of the vehicle, and a controller configured to estimate the acceleration and the angular velocity of the vehicle by using the front time series image frame generated by the camera and diagnose an abnormality in the sensor based on the acceleration and the angular velocity of the vehicle estimated by the controller.

Recently, an autonomous emergency braking (AEB) system, a forward collision warning (FCW) system, an adaptive cruise control (ACC) system, a lane departure warning system (LDWS), a lane keeping assist system (LKAS), a blind spot detection (BSD) apparatus, a rear-end collision warning (RCW) system, a smart parking assist system (SPAS), and the like have been mounted on a vehicle.
In addition, various sensors, such as a camera sensor, a light detection and ranging (LiDAR) sensor, a radio detection and ranging (RADAR) sensor, an ultrasonic sensor, a gyro sensor, an acceleration sensor, and the like, are provided in a vehicle to operate the various systems described above normally. In this case, the gyro sensor and the acceleration sensor may cause measurement errors due to impact on the vehicle while driving and deterioration over time.
In general, a technique for correcting a bias error of a gyro sensor extracts feature points between successive image frames output from an image sensor, converts a movement displacement between the extracted feature points into a posture angle, and extracts an angular velocity by dividing the converted movement displacement by the frequency of the image frame, and corrects the error of the gyro sensor based on the extracted angular velocity.
Such a conventional technique discloses a technique for extracting feature points in a 'Harris corner detection' scheme and matching feature points in an 'optical flow' scheme to estimate the angular velocity. However, there has been disclosed no technique for estimating the angular velocity based on an artificial neural network (ANN). In particular, according to the related art, only a technique for estimating an angular velocity has been disclosed, but any techniques for estimating an angular velocity and an acceleration together have not been disclosed.
The matters described in this background section are intended to promote an understanding of the background of the disclosure and may include matters that are not already known to those of ordinary skill in in the art.

Apparatus for diagnosing abnormality in vehicle sensor and method thereof

Ajou University Industry-Academic Cooperation Foundation


In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

1. Field of the Invention
The present disclosure generally relates to techniques for testing semiconductor devices, and, more particularly, to techniques for testing integrated circuits that include logic circuitry portions and embedded memory portions with memory built-in self-test logics connected thereto.
2. Description of the Related Art
In manufacturing semiconductor devices including relatively complex circuitry, the testing of the device may represent a part of the manufacturing process which is frequently underestimated in terms of cost and effort required to obtain reliable data with respect to proper functionality and reliability of the device. One reason in failing to meet performance specifications of the integrated circuit may reside in design errors that may be identified and remedied by circuit verification on the basis of software simulation and/or prototype testing prior to mass production of the integrated circuits under consideration. An improper functionality of the integrated circuit may further be caused by the manufacturing process itself when the completed circuitry does not correspond to the verified circuit design owing to process fluctuations in one or more of the very large number of process steps. Although measurement and test procedures are incorporated at many points in the manufacturing process, it is nevertheless extremely important to ascertain the correct functioning of the final semiconductor device, since, according to a common rule of thumb, the costs caused by defective chips increase with each assembly phase by approximately one order of magnitude. For example, the costs caused by a defective circuit board including a faulty chip are typically significantly higher than identifying a defective chip prior to shipping and assembling the circuit board. The same holds true for a system, when a failure thereof is caused by one or more defective circuit boards, as a downtime of an industrial system may result in averaged costs of approximately several hundred dollars per minute compared to a price of a few dollars for an integrated circuit chip having caused the defect.
Hence, there is a vital interest in developing test procedures to identify as many defects as possible in completed integrated circuits while not unduly increasing the total manufacturing costs. In particular, with the demand for more features and lower costs of circuits, there is a tendency to integrate a plurality of different circuit portions into a single chip to provide a complete system on a chip (SOC). A semiconductor device comprising various functional blocks may typically include, in addition to one or more logic blocks, one or more embedded memory portions, such as are used as on-chip cache for CPUs or as buffers for data packets that are transferred between different clock domains.
As discussed above, economic constraints force semiconductor manufacturers to not only minimize the defect level of the total manufacturing process, but also to provide, in combination with a reduced defect level, a high fault coverage so as to reduce the delivery of defective chips at reasonable cost for appropriate test procedures and techniques. For moderately complex integrated circuits, it has become standard practice to develop the basic design of the circuit while taking into consideration a plurality of constraints posed by effective test procedures. Moreover, typically, additional hardware resources are provided in the chip that may enable the identification of faulty circuit components for a broad class of operating conditions, wherein the additional hardware resources, in combination with design specifics of the basic circuit and sophisticated test procedures and test patterns, substantially determine the fault coverage of the test procedure.
In many circuit designs, the functional logic portion is tested by so-called scan chains, which represent a chain of flip-flops connected to a specific area of the functional logic in such a way that the functional logic or a specific area thereof may be initialized with a desired state that has previously been entered into the scan chain. Moreover, upon providing one or more clock signals to the functional logic, the state thereof, that is the state of each logic gate connected to a dedicated flip-flop of the scan chain, may then be stored in the scan chain and may be shifted out by supplying respective shift clock signals to the scan chain. Depending on the bit pattern or input vector entered into the scan chain for initializing the functional logic, corresponding faulty logic gates may be identified. However, the fault coverage, i.e., the potential for identifying any error within the functional logic, significantly depends on the design, selection and number of appropriate scan chains and suitable input vectors. In principle, such scan test techniques may also be modified to include the testing of memory portions, wherein, however, only for small memories, appropriate scan test patterns, i.e., the number and size of appropriate input vectors, may exhibit a size that allows the testing of memory portions within acceptable time intervals.
For this reason, frequently, a so-called memory built-in self-test (MBIST) logic is provided as an additional hardware resource within a chip to implement a memory test procedure requiring fewer clock cycles and supporting the testing of important extended fault models that are specific to memories. With reference to FIGS. 1a-1c, the configuration and the test procedures for a representative conventional semiconductor device including functional logic and a memory portion are described in more detail so as to more clearly illustrate the problems involved.
FIG. 1a schematically shows a circuit diagram of a semiconductor device 100 including a functional logic circuitry 110, which may be connected to a memory portion 120 via write lines, read lines and control lines that are commonly referred to as lines 121. The device 100 further comprises an MBIST logic 130 including, for instance, a finite state machine 131 for implementing a desired algorithm for testing the memory portion 120. The MBIST logic 130 further comprises all components required for disconnecting the memory portion 120 from the functional logic 110 so as to enable the operation of the memory portion 120 fully under control of the MBIST logic 130 when operating the logic 130 for the memory test.
On the other hand, when disabled, the MBIST logic 130 is "transparent" for the lines 121 to allow proper operation of the logic circuitry 110 in combination with the memory portion 120. The MBIST logic 130 comprises a first control input 132, which is also referred to as MBIST-start, and a second control input 133, also indicated in the drawing as MBIST-enable. Moreover, a first output 134, also referred to in the drawing as MBIST-good, and a second output 135, also indicated as MBIST-done, are provided in the MBIST logic 130. It should be noted that, for convenience, any additional inputs or outputs of the logic 130, such as clock inputs, reset inputs and other control lines, are not shown.
When operating the device 100 in a memory test mode, the MBIST logic 130 may be enabled by providing a corresponding signal at the input 133 (MBIST-enable) to disconnect the memory portion 120 from the surrounding logic circuitry 110. By supplying a corresponding signal at the input 132 (MBIST-start), the circuit portion 130 is started to generate address values and to write data into the memory portion 120. The circuit 130 may also include a comparator, which may be configured to check if the data written into the memory 120 may be correctly read back from the memory, and which may provide a corresponding value at the output 134 (MBIST-good). For instance, the value of the output 134 may show logic "0" as long as no error occurs in writing data into the memory 120 and reading back the data, while the output 134 may be set to a logic "1" once a mismatch between the actually read data and the expected data is detected. After the test of the memory 120 is completed, a corresponding signal may be presented at the output 135 (MBIST-done), for instance, the output 135 may be switched from logic "0" to logic "1" if the test is completed.
FIG. 1b schematically illustrates the semiconductor device 100 which may comprise a plurality of embedded memories 120A, 120B that are connected to corresponding portions of the built-in test circuitry. For example, each of the memory portions 120A, 120B may be connected to a corresponding "glue logic" 140A, 140B, which may provide control and data signals to the memory 120A, 120B during a corresponding test phase and which may provide the desired transparency of the built-in test circuitry in a standard operating mode, as previously discussed. Moreover, corresponding circuit portions 160A, 160B may connect to the glue logics 140A, 140B, respectively, in order to provide appropriate control signals and test data patterns as required by the test algorithm under consideration. For convenience, the circuit portions 160A, 160B may also be referred to as "slaves," which in turn may be controlled by an MBIST controller 138, which in turn may be configured to provide appropriate operation code sequences for performing a desired sequence of memory operations in each of the memories 120A, 120B and which may also provide the required test data patterns. It should be appreciated that a plurality of test algorithms are presently used, each of which may provide a certain degree of fault coverage with respect to individual memory cells and also corresponding circuit components for controlling the memory arrays. For example, test algorithms may be applied in which each memory cell may be written to and may be read out according to a specified addressing scheme, while in other cases appropriate patterns may be written into the memory array, such as a checkerboard pattern and the like, in order to determine the static and dynamic behavior of the memory area and the associated circuitry for performing the read and write operations. It should be appreciated that respective test algorithms may be specifically designed for certain types of memories, technology standards used for actually fabricating the memories and the like, so that, with a change in memory design, technology and the like, appropriately adapted test algorithms may be required. Consequently, in many built-in test circuits, a certain degree of flexibility may be provided so as to allow the employment of different types of test algorithms, if required.
During operation, the semiconductor device 100 in a memory test operating mode, the controller 138 may instruct one or more of the slaves 160A, 160B to initiate a memory self-test by providing a corresponding sequence of instructions, such as memory addresses and respective control signals in combination with the desired test data pattern, which may be accomplished by conveying the signals via bus lines 150A, 150B, which may also include appropriate bus lines for conveying a failure signal from the glue logic 140A, 140B to the slaves 160A, 160B. It should be appreciated that the signal transmission via the busses 150A, 150B may typically be associated with a certain latency, i.e., the transport of the signal may require a specified number of clock cycles corresponding to the number of pipeline stages that may typically be used in order to relax time constraints as may typically occur in sophisticated semiconductor devices, which may be operated with clock frequencies of several hundred megahertz and significantly higher. Consequently, the point in time of issuing a certain memory operation from the slave 160A, 160B to the glue logic 140A, 140B may differ from the point in time when a corresponding memory operation may actually be served in the memory 120A, 120B. Upon executing the memory operations, for instance writing a specified data pattern into the memory array 120A, 120B and reading back the corresponding data according to a specified test algorithm, a comparison may be made between the originally written bus data and the data read out from the memory 120A, 120B and thereby detecting corresponding memory failures depending on the test algorithm used. The comparison result, for instance, obtained on the basis of a comparing logic 141A may then be forwarded to the slave 160A, 160B, which may also require a certain number clock cycles, depending on the overall configuration of the buses 150A, 150B, as previously explained. For an enhanced evaluation of any memory failures that may be detected during the test algorithm under consideration, at least the correspondence between a failure signal obtained in the slave 160A, 160B and a corresponding memory operation causing the failure signal may have to be determined, which, however, requires an appropriate adaptation of the various time delays involved in transferring the operation code instructions, the test data patterns and the failure signals from the slave 160A, 160B to the glue logic 140A, 140B and back to the slave. Moreover, in many cases, additional information is obtained, for instance, the form of each of the comparison results 141A obtained from the memory 120A at the point in time where a certain memory failure, for instance a read memory failure, is detected. For example, this information may be read out and may finally be transferred to the controller 138, from which the single global failure signal 135 may be obtained, for instance for an external test equipment, and also a corresponding bitmap 138A may also be supplied to an external test equipment via any appropriate interface system.
FIG. 1c schematically illustrates a portion of the semiconductor device 100 including the memory portion 120A and the glue logic 140A, the control and data busses 150A and the slave circuit 160A. As illustrated, the slave circuit 160A comprises a decode unit 166, which represents any appropriate circuit for providing control and operating code data 161 to the glue logic 140A. For example, addresses and control signals may be provided so as to perform a predefined sequence of memory operations, for instance, writing a specific data pattern into the memory 120A, reading specified memory locations and the like. The data 161 is transmitted through the bus 150A, thereby experiencing a certain degree of latency, which may be caused by the presence of a specific number of pipeline stages 151, which may be required in view of timing constraints and the like. Additionally, appropriate test data 162 are provided by the slave circuit 160A, for instance by operating a specified logic circuitry, which may evaluate a sequence of data, by receiving appropriate test data patterns from memory and the like. The data 162 is also transferred to the glue logic 140A through bus 150A including the specified number of pipeline stages 151. The control data 161 may be supplied to the memory 120A in order to initiate a corresponding sequence of memory operations, such as a sequence of write operations using the test data 162, that is supplied to the memory 120A by means of any appropriate circuit, such as a multiplexer 142, and the like. At the same time, the test data 162 may also be supplied to a latency adaptation stage 143, which may thus impart a specified latency to the test data that is equal to the latency experienced by the test data when subjected to corresponding memory operations initiated by the control and address data 161. Consequently, the data 162 as output by the adaptation stage 143 may be considered as reference data that can be compared to memory data 162M that are obtained by performing respective read operations in accordance with the test algorithm under consideration. For example, the comparison may be performed on the basis of exclusive OR gates 141A, 141B, thereby obtaining a comparison result for a portion of the data 162M. It should be appreciated that, due to the increased width of sophisticated memories, such as memory 120A, typically each item of the data 162M, 162R may represent an appropriate number of individual bit values, which may individually be compared, thereby providing a corresponding bitmap, which may be considered as the entirety of bit values representing the result of the comparison between the data 162M and 162R. For example, the corresponding result data or bitmap may be stored in a register 141C. Consequently, for a definition as used above, each logic 1 in the register 141C may represent a corresponding memory failure at a given point in time, thereby obtaining a topographical overview of the memory 120A for each global failure state, which may be indicated by a failure signal 141D obtained on the basis of an OR gate 141E, which may therefore assert the signal 141D upon occurrence of one or more individual failure bits in the register 141C. The failure signal 141D is then applied to the slave circuit 160A via a corresponding line 152, which in turn may also comprise a specific number of pipeline stages. The failure signal 141D may trigger a failure counter 164 in order to monitor the number of memory failures obtained during the corresponding test algorithm. The failure counter 164 in turn may lock an operation counter 163, which may count the number of operations issued to the glue logic 140A after starting the test algorithm under consideration. Consequently, the value of the counter 163 is indicative of the number of memory operations that resulted in the generation of a corresponding global failure indicated by the signal 141D. However, due to the various latencies induced by the pipeline stages 151, 152, the value of the counter 163 may not directly indicate the specific read operation that causes the failure under consideration. In order to obtain a reliable correspondence between the value of the counter 163 and a corresponding memory operation under consideration for a specified memory failure, respective design measures may have to be taken, such as appropriately adapting the pipelines 151 and 152, inserting a predefined number of wait cycles in the counter 163 in order to balance any latency differences of the corresponding signal line and the like. As previously discussed, during the design and verification of complex integrated circuits, it may frequently be desirable to add additional pipeline stages, for instance in view of superior signal routing and the like, in particular where semiconductor devices are considered that are operated based on high clock frequencies, which, however, may require a total redesign for a built-in self-test circuit in order to provide the required consistency between the bitmap obtained on the basis of the register 141C and the corresponding failure signal 141D. That is, by adding additional pipeline stages in a late design state, the corresponding delicate balancing of the pipelines 151, 152 required for appropriately associating a memory operation with a corresponding bitmap, or the incorporation of appropriate wait cycles, and the like may no longer be appropriate, thereby requiring the redesigned pipelines stages.
In view of the situation described above, the present disclosure relates to semiconductor devices and methods for operating the same in which flexibility in designing memory built-in self-test circuits may be enhanced by avoiding or at least reducing the effects of one or more of the problems identified above.

Latency detection in a memory built-in self-test by using a ping signal


A rechargeable battery including: an electrode assembly including a first electrode, a second electrode, and a separator between the first and second electrodes; a case receiving the electrode assembly; a cap plate coupled to the case; an electrode terminal connecting the electrode assembly to an outside of the cap plate; and a lead tab electrically connecting the electrode assembly and the electrode terminal, and the electrode assembly includes a coated region of the first electrode, and an uncoated region of the first electrode adjacent an end portion of the coated region, the uncoated region having a through hole formed therein and connecting an inner portion of the electrode assembly to an outside of the electrode assembly.

1. Field
Aspects of embodiments of the present invention relate to a rechargeable battery.
2. Description of the Related Art
A rechargeable battery is a battery that is repeatedly charged and discharged, unlike a primary battery. Low-capacity rechargeable batteries may be used for portable compact electronic apparatuses such as mobile phones, notebook computers, and camcorders, and high-capacity rechargeable batteries may be used as a power supply for driving a motor of a hybrid vehicle, an electric vehicle, etc.
For example, the rechargeable battery generally includes an electrode assembly, a case for receiving the electrode assembly, a cap plate combined to an opening of the case, and an electrode terminal installed in the cap plate and connected to the electrode assembly. The cap plate includes a terminal hole for installing the electrode terminal and a vent hole. The vent hole has a vent plate made of a thin plate with a thinner thickness than the cap plate and is welded to the cap plate to close and seal it.
The rechargeable battery generates internal gas during charge and discharge of the electrode assembly. Also, under an internal short circuit generation of the rechargeable battery, that is, under a short circuit of a positive electrode and a negative electrode of the electrode assembly, heat is generated and an electrolyte solution is decomposed while a potential difference of the charged positive electrode and negative electrode is quickly reduced. When the electrolyte solution is decomposed, a large amount of gas such as methane, hydrogen, or carbon dioxide is generated such that the internal pressure of the rechargeable battery is quickly increased.
Generally, the electrode assembly includes a negative electrode and a positive electrode at respective surfaces of a separator and is formed by winding the negative electrode, the separator, and the positive electrode in a jelly roll state, and has an uncoated region of the negative electrode and the positive electrode where the separator is not interposed. The uncoated region is welded to a lead tab that is compressed and deformed, thereby being electrically connected to the electrode terminal.
The uncoated region blocks the negative electrode, the separator, and the positive electrode from the outside of the electrode assembly, while forming a slant region at the end of the coated region under the compression and deformation. Accordingly, under the internal short circuit generation of the electrode assembly or when leaving the rechargeable battery, the internal gas generated inside the electrode assembly is blocked in the slant region. The dispersion and emission of the internal gas is thereby deteriorated.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.


According to the present invention, in an air conditioner for a vehicle, when the cool air passage is opened, the sliding door slides so as to incline with respect to the flowing direction of the cool air in such a manner that an end portion of the sliding door at a side of said cool air passage is located at the most air downstream side. That is, when the sliding door is controlled to fully open the cool air passage (i.e., the warm air passage is fully closed), for example, in the maximum cool mode, the sliding door slides while inclining with respect to the flowing cool air. In this operation, the air is blocked from flowing into the warm air passage, and such air is smoothly guided into the cool air by the sliding door, because the sliding door inclines with respect to the flowing direction of cool air, thus increasing the amount of cool air into the passenger compartment.

1. Field of the Invention
The present invention relates to an air conditioner for a vehicle.
2. Description of Related Art
In a conventional air conditioning unit for a vehicle as shown in Japanese Utility Model Laid-Open No. Hei 2-15508, a plate-shaped sliding door as an air mixing door slides in a direction crossing the cool air and warm air passages to adjust the mixing ratio of the cool air and the warm air. In such an air conditioning unit for a vehicle, it is necessary to fully close the cool or warm air passage with the sliding door in the maximum cool mode where no air is sent to the heater core and in the maximum hot mode where all of the air having passed through the evaporator bypasses the heater core, and therefore, the cross sectional area of the cool air passage is set to be equal to that of the warm air passage.
In an air conditioning unit for a vehicle, there has been a demand to increase an amount of blowing air as much as possible in the maximum cool mode to improve cooling performance especially in summer. However, according to the air conditioning unit in the above-described Japanese Utility Model Publication, the amount of blowing air is restricted by the sliding door, because the surface at the air upstream side of the sliding door extends perpendicularly with respect to the flowing direction of the air passing through the evaporator in the maximum cool mode.


A method for testing a digital to analog converter, which operates in an undersampling environment, wherein signals of a tested DAC and a signal generator are modulated by a PWM device and then processed by a digital processing circuit to generate a digital signal, whereby is formed a low-speed equivalent ADC. The signal generator is provided by uniform-distribution random test patterns, and the signal generator generates an uniform-distribution random analog signal to the equivalent ADC. Thereby, the test error caused by the non-ideality of the signal generator is corrected, and the tested circuit can work in a full speed.

In testing an analog circuit or a mixed-signal circuit, the measurement of analog signals is a big challenge because analog signals are likely to be affected by noise. Further, the accuracy and stability of sampling in the recipient side also directly influences the entire test result. From the viewpoint of signal processing, the analysis of the output test eigenvalues can be accelerated if the outputs are digitized signals. Besides, the digitized signals are less likely to be distorted during transmission. Moreover, the external ATE (Automatic Test Equipment) can also process the digitized signals more efficiently.
There have been sophisticated digital-circuit test methods widely applied to mass-produced chips. However, as great difference exists between different types of analog circuits or mixed-signal circuits, the test technology thereof still has much room to develop. A typical test method for a digital to analog converter (DAC) usually includes the following procedures: the analog output terminal of the tested DAC is connected to the input terminal of a measurement analog to digital converter (ADC); digital control signals are sent to the input terminal of the tested DAC; the measurement ADC digitizes the output voltage signals of the tested DAC and outputs digital signals for analysis. Such a method is a full-digital approach, wherein the generation and analysis of digital signals are undertaken by a digital processing unit. Nevertheless, this method can only apply to a chip simultaneously having ADC and DAC. However, many chips have only DAC. If it is only for testing DAC that high-speed and high-resolution ADC should be built in the chip, the cost of test will be too high, and the chip design will become more complicated.

Method for testing a high-speed digital to analog converter based on an undersampling technique

National Yunlin University of Science and Technology


To avoid a difficulty of inserting a spline shaft into a spline hole, respective holding members 29 constituting a holding device 28 for holding a hub 3 are displaced in a radial inward direction of a small diameter stepped portion 15. The inner peripheral surface of the inside end of an original hole 25 is elastically deformed radially inward the same as or slightly greater than the elastic deformation caused by externally securing tightly an inner ring to the small diameter stepped portion 15. In this condition, a female spline portion for constituting a spline hole is formed in the original hole 25.

In order to rotatably support a wheel with respect to the suspension system, there are used various kinds of drive wheel rolling bearing units in which an outer ring and an inner ring are rotatably combined together through rolling elements. For example, in Japanese Unexamined Patent Publication No. 2003-139174, a drive wheel rolling bearing unit 1 as shown in FIGS. 23 and 24 is described. This drive wheel rolling bearing unit 1 comprises an outer ring 2, and a hub 3 and an inner ring 4 which are rotatably supported on the inner diameter side of the outer ring 2 through a plurality of rolling elements 5. Out of these members, the outer ring 2 is securely connected to a knuckle 7 constituting a suspension system by the use of a first flange 6 provided on the outer peripheral surface thereof, and is not rotated even when used. Moreover, on the inner peripheral surface of the outer ring 2, there are provided double row outer ring raceways 8, so as to rotatably support the hub 3 and the inner ring 4 on the inner diameter side of the outer ring 2 concentrically with the outer ring 2.
The hub 3 is provided with a second flange 11 for supporting a wheel 9 constituting a vehicle wheel, and a disc 10 constituting a disc brake, on a portion towards the axial outside end of the outer peripheral surface ("outside" in relation to the axial direction, is the outside in the widthwise direction of the vehicle in a condition when assembled in the vehicle; the left side in the figures. The same applies throughout to this specification and claims). The wheel 9 and the disc 10 are fixedly connected to the outside surface of the second flange 11 by means of a stud 12 and a nut 13. A first inner ring raceway 14 is formed in a middle portion on the outer peripheral surface of the hub 3. The inner ring 4 which is formed with a second inner ring raceway 16 on the outer peripheral surface thereof, is externally fitted with an interference fit to a small diameter stepped portion 15, which is a fitting cylindrical surface portion and is formed on the axial inside end ("inside" in relation to the axial direction is the side towards the widthwise center when assembled in the vehicle; the right side in the figures. The same applies throughout to this specification and claims).
In the center of the hub 3, a spline hole 17 is provided. A spline shaft 19 constituting a constant velocity universal joint 18 is inserted into the spline hole 17 from the axial inside towards the outside. A nut 21 is screwed onto a male screw portion 20 which is provided in a portion protruded beyond the outside end surface of the hub 3 on the axially outside end portion of the spline shaft 19, and is further tightened, so that the constant velocity universal joint 18 and the drive wheel rolling bearing unit 1 are securely connected to each other. In this condition, the axial inside end surface of the inner ring 4 is abutted against the axial outside end surface of a constant velocity universal joint outer ring 22 constituting the constant velocity universal joint 18, so that the inner ring 4 is not displaced in a direction to come away from the small diameter stepped portion 15. At the same time, an appropriate preload is applied to the respective rolling elements 5.
The shapes, and the like, of the components of the constant velocity universal joint 18 are similar to those of a known constant velocity joint of a Rzeppa type or a Birfield type, and have nothing to do with the gist of the present invention. Therefore, detailed illustration and description are omitted. Moreover, as shown in FIG. 25, a structure where a cylindrical portion 23 existing on a portion protruded axially inside beyond the inner ring 4 which is fitted onto the small diameter stepped portion 15a on the axial inside end of the hub 3a is swaged and expanded (plastically deformed) radially outward to form a crimped portion 24, and the inside end surface of the inner ring 4 is clamped by the crimped portion 24, is described in Japanese Unexamined Patent Publication No. 2003-139174 and the like, and is heretofore well known. In the case of such a structure, an appropriate preload is applied to the respective rolling elements 5 in a condition with the inside end surface of the inner ring 4 clamped by the crimped portion 24.
The operations for forming the spline hole 17 in the center of the hubs 3 and 3a, and assembling the respective components, have been heretofore performed as follows, either for the case of the structure to clamp the inside end surface of the inner ring 4 by means of the constant velocity universal joint outer ring 22 as shown in the FIGS. 23 and 24, or for the case of the structure to clamp the inside end surface of the inner ring 4 by means of the crimped portion 24 as shown in the FIG. 25. The following description mainly focuses on the structure shown in FIGS. 23 and 24. Firstly, as shown in FIG. 26, before assembling the respective components including the inner ring 4 into the hub 3 (3a), a female spline portion for constituting the spline hole 17 as shown in FIG. 27 is formed by applying broaching to the inner peripheral surface of an original hole 25 which is provided in the center of the hub 3 (3a). Next, as shown in FIG. 28, in a condition with the respective components, excluding the inner ring 4, assembled into the hub 3 (3a), then as shown in FIG. 29, the inner ring 4 is externally secured to the small diameter stepped portion 15 which is provided on the axial inside end of the hub 3. Then, after forming the crimped portion 24 (refer to FIG. 25) if necessary, the drive wheel rolling bearing unit 1 and the constant velocity universal joint 18 are assembled to each other by inserting the spline shaft 19 constituting the constant velocity universal joint 18, into the spline hole 17 as shown in FIG. 23. In this manner, conventionally, the operation for forming the spline hole 17 in the center of the hub 3 (3a) has been performed before assembling the inner ring 4 into this hub 3 (3a).
However, if in this manner the inner ring 4 is externally secured to the small diameter stepped portion 15 after the processing for the spline hole 17, it is unavoidable that the axial inside end of the spline hole 17 is contracted radially inward although slightly. That is, since the inner ring 4 is externally secured to the small diameter stepped portion 15 (with the inner diameter A of the inner ring 4 in the free state< the outer diameter B of the small diameter stepped portion 15 in the free state), a large force directed radially inwards acts around the whole periphery of the small diameter stepped portion 15 which is relatively thin when fitted. Then due to such a force, the axial inside end of the spline hole 17 is deformed radially inward as shown exaggerated in FIG. 29, and the diameter of the inner peripheral surface of the axial inside end of the spline hole 17 is contracted (the inner diameter of the inscribed circle of the female spline grooves and female spline teeth and the overpin diameter are contracted). When the diameter of the inner peripheral surface of the axial inside end of the spline hole 17 is contracted in this manner, it becomes difficult to insert the spline shaft 19 into the spline hole 17, and the assembly operation for the drive wheel rolling bearing unit 1 and the constant velocity universal joint 18 becomes difficult to perform.
In order to avoid this inconvenience, Japanese Unexamined Patent Publication No. 2002-317824 discloses an invention wherein a female spline portion for constituting the spline hole 17 is formed in a condition where the inner ring 4 or a jig having an equivalent inner peripheral surface, is externally secured to the small diameter stepped portion 15. That is, by externally securing the inner ring 4 or the jig to the small diameter stepped portion 15 in this manner, the axial inside end of the spline hole 17 is elastically deformed in the same condition as where the inner ring 4 is externally fitted tightly to the small diameter stepped portion 15. Then, by forming the female spline portion in this condition, the female spline portion is formed with compensation for the deformation which is caused by externally fitting tightly the inner ring 4 to the small diameter stepped portion 15. Therefore, the difficulty of performing the assembling operation for the wheel drive rolling bearing unit 1 and the constant velocity universal joint 18, caused by the difficulty of inserting the spline shaft 19 into the spline hole 17 can be avoided.
However, in the case of forming the female spline portion in a condition with the inner ring 4 or the jig externally fitted to the small diameter stepped portion 15 in this manner, it is necessary to take off the inner ring 4 or the jig from the small diameter stepped portion 15 after forming the female spline portion 4. Such a procedure of taking off the inner ring 4 from the small diameter stepped portion 15 may cause damage to the respective peripheral surfaces due to rubbing between the inner peripheral surface of the inner ring 4 and the outer peripheral surface of the small stepped portion 15 because this inner ring 4 and the small stepped portion 15 are tightly fitted to each other. By forming the female spline portion in the center of the hub 3 in the condition where at least the outer ring 2, the respective driving elements 5, and the inner ring 4 are assembled into the hub 3, it becomes unnecessary to take off the inner ring 4 from the small stepped portion 15. However, when forming the female spline portion in the condition where the respective components 2, 4, and 5 are assembled in this manner, treatment to prevent cutting scraps caused by the process of forming the female spline portion, from entering the gap between the respective components 2, 4 and 5 becomes necessary, and an operation to rinse out these cutting scraps becomes more troublesome. Therefore this method is undesirable.
Moreover, as shown in the FIG. 22, in the abovementioned structure where the crimped portion 24 is formed on the inside end of the small diameter stepped portion 15a, Japanese Unexamined Patent Publication No. 2002-327715 discloses an invention to avoid the difficulty of inserting the spline shaft 19 into the spline hole 17 due to contraction of the inner diameter of the axial inside end of the spline hole 17 caused by the formation of the crimped portion 24. That is, in the case of the invention described in Japanese Unexamined Patent Publication No. 2002-327715, as shown in FIG. 30, by externally fitting tightly a jig 26 to the small diameter stepped portion 15a, the inner peripheral surface of the axial inside end of the spline hole 17 is elastically deformed in the same condition as when the crimped portion 24 (FIG. 22) is formed. Then, by forming the female spline portion for constituting the above spline hole 17 in this condition, this female spline portion is formed in a condition with compensation for the deformation caused by forming the crimped portion 24.
Also for the invention described in this Japanese Unexamined Patent Publication No. 2002-327715, it is necessary to take off the jig 26 from the small diameter stepped portion 15a after forming the female spline portion, similarly to the above invention described in Japanese Unexamined Patent Publication No. 2002-317824. Moreover, in the case of the invention described in Japanese Unexamined Patent Publication No. 2002-327715, since the inner peripheral surface of the axial inside end of the spline hole 17 is elastically deformed in the same condition as when the crimped portion 24 is formed, the interference between the inner peripheral surface of the jig 26 and the outer peripheral surface of the small diameter stepped portion 15a becomes greater. Therefore, damage of the outer peripheral surface of the small diameter stepped portion 15a becomes greater, and can be too much to ignore.

Manufacturing method for a drive wheel rolling bearing unit and manufacturing apparatus therefor


Method and system for automating operations of a computing arrangement. A pattern database is configured with pattern definitions and associated response definitions, and one or more of the response definitions include one or more commands for operating the computing arrangement. A message processor receives messages from components in the computing arrangement and matches the messages against the patterns in the database. If a message matches a pattern, the message processor performs the actions specified in the associated response definition. One or more of the response definitions queue commands to a command queue. The message processor then dequeues and issues the commands at times that are compatible with the operation being automated.

Single Point Operations software supports centralized control and automated operations of multiple data processing systems. As a part of the Single Point Operations software, Single Point Autoaction Message System (SP-AMS) software supports automated operations. SP-AMS is a utility that allows a user to specify messages to match and actions to perform when a message is received and matched.
Some systems require extremely complex sequences of commands to be entered by an operator in order to take advantage of certain system capabilities. For example, the Symmetrix storage system from EMC has disaster recovery capabilities that require operator knowledge of which disk groups are attached to which data processing system and entry of a long sequence of cryptic commands in a particular order. Proper use of this capability requires extensive training of operators. Even with proper training, however, the entry of commands may be error prone. Thus, Single Point Operations software and SP-AMS would appear to be suitable for automating operations of systems such as the Symmetrix storage system.
The Symmetrix storage system is configurable to provide data storage for multiple host data processing systems, and the storage space is separately administered for each host. Certain administrative operations performed on the Symmetrix system, for example, a remote copy, can be performed simultaneously for different host systems. The complex command sequences required to perform these operations and the need for multiple host systems to perform these operations simultaneously makes automation of these operations a non-trivial task. While SP-AMS software is generally used for automating complex command sequences, SP-AMS does not include support of multi-threaded command sequences.
A method and system that address the aforementioned problems, as well as other related problems, are therefore desirable.

Automation of complex user-level command sequences for computing arrangements


The present disclosure provides a hydraulic system of a cantilever device, which comprises an end cap, an adjustment brace, an adjustment bolt, a slider, and an upper pivot. The end cap comprises an upper wall, a bottom wall, and side walls. The bottom wall has a securing groove. Each side wall has an upper pivot hole adjacent to the upper wall. The adjustment brace is fastened to the end cap and is secured in the securing groove. The slider comprises a first slider portion and a second slider portion, wherein the first slider portion has two shaft portions located on both sides of the adjustment portion. The upper pivot comprises a shaft body portion located between the bolt head and the bolt shoulder of the adjustment bolt.

With reference to FIGS. 1 and 2, a hydraulic system 9 of a cantilever device as disclosed in U.S. Pat. No. 7,540,457 is suitable for connecting a top support (not shown) to a bottom support (not shown) of the cantilever to a force adjustment device (not shown). The force adjustment device may be a gas spring or an oil force adjustment device. The force adjustment device 9 includes an end cap 92 that can be inserted in a base 91 and has an opening 920, an adjustment bolt 93 rotatably arranged on the end cap 92, a slider 94 having a first end 941 and a second end 942, a fixing plate 95, two bolts 96, an upper pivot 97 for pivoting the top support to the end cap 92, and a lower pivot 98 for pivoting the bottom support to the end cap 92.
The end cap 92 comprises an upper wall 921, a bottom wall 922, a stopping wall 923 that connects the upper wall 921 to the bottom wall 922, and two side walls 924 that connect the upper wall 921 to the bottom wall 922 and are located on both sides of the stopping wall 923. The edge of the upper wall 921, the edge of the bottom wall 922 and edges of the side walls 924 are jointly surrounded for defining the opening 920. The upper wall 921 has an internal surface 925 facing the bottom wall 922, an external surface 926 opposite to the internal surface 925, and a through hole 927 passing through the internal surface 925 and the external surface 926 and receiving a bolt head 931 of the adjustment bolt 93. The bottom wall 922 has a top surface 951, two joint portions 952 that are respectively located on both sides of the stopping wall 923 and protrude from the upper surface 951 toward the upper wall 921, a connecting portion 953 that are located between the joint portions 952 and protrudes from the upper surface 951 toward the upper wall 921, and a groove 954 formed in the connecting portion 953 and for receiving a distal portion 932 of the adjustment bolt 93. Each side wall 924 has an upper pivot hole 961 adjacent to the upper wall 921, and a lower pivot hole 962 adjacent to the bottom wall 922.
In assembling, the first end 941 of the slider 94 is screwed to an adjustment portion 933 of the adjustment bolt 93, and a bolt shoulder 934 of the adjustment bolt 93 is abutted against the internal surface 925 of the upper wall 921 (at this time, the end 932 of the adjustment bolt 93 is received in the groove 954 of the bottom wall 922); then the bolts 96 are respectively passed through the fixing plate 95 and are locked to the joint portions 952 of the end cap 92; then the second end 942 of the slider 94 is pivoted to one of the ends (not shown) of the force adjustment device and the other end (not shown) of the force adjustment device is pivoted to the top support; and finally the upper pivot 97 is passed through the upper pivot hole 961 of the end cap 92 and an end (not shown) of the top support, and a lower pivot 98 is passed through the lower pivot hole 962 of the end cap 92 and the end (not shown) of the bottom support. Additionally, both the other end of the top support and the other end of the bottom support are pivoted to a connector piece (not shown) that is opposite to the end cap 92 such that the preliminary assembling work of the cantilever device can be completed.
Such a hydraulic system 9 enables a user to axially move the slider 94 up and down along the direction of the adjustment bolt 93 by rotating the adjustment bolt 93. An angle between the force adjustment device and the top support is changed and thus the overall load capacity of the force adjustment device is adjusted. However, in practice, such a hydraulic system 9 has the following disadvantages:
First, in order to allow the adjustment bolt 93 to be limited within the end cap 92, the method disclosed in the above prior art adopts a design in which the end 932 of the adjustment bolt 93 is abutted against the top surface 951 of the bottom wall 922 (for preventing the adjustment bolt 93 from falling downward) and an external diameter of the bolt shoulder 934 of the adjustment bolt 93 is made to be larger than an external diameter of the bolt head 931 (for preventing the adjustment bolt 93 from falling outward from the through hole 927). Therefore, it should be appreciated that, when the user rotates the adjustment bolt 93, a feeling that the rotation is less smooth exists because the end 932 of the adjustment bolt 93 is abutted against the upper wall 921. Therefore, in general, the end 932 of the adjustment bolt 93 is additionally processed to obtain a smooth surface and is preferably designed to be tapered so as to minimize the contact area between the adjustment bolt 93 and the bottom wall 922, thereby reducing the friction force. Namely, the design of the adjustment bolt 93 and the end cap 92 of the hydraulic system 9 is sophisticated and complicated, which results in a disadvantage that the manufacturing cost cannot be reduced.
Second, the slider 94 of the hydraulic system has only one guiding bevel 943 abutting against the stopping wall 923, and the slider 94 is not limited and fixed between the side walls 924. Therefore, when the user rotates the adjustment bolt 93 to axially move the slider 94 up and down along the direction of the adjustment bolt 93, the slider 94 will shake between the side walls 924, resulting in unnecessary noise. Also, when the force adjustment device changes a free end position of the cantilever device due to external force, unnecessary abnormal friction noise may be produced between the force adjustment device and other components (such as the top support or the bottom support) as the slider 94 that connects the force adjustment device shakes. Additionally, when the force adjustment device applies force onto the slider 94 because of the angle change and then the force is transmitted to the adjustment bolt 93, the end 932 of the adjustment bolt 93 will naturally deviate toward the direction of the opening 920 due to the generation of torque which requires the hydraulic system 9 to have a fixing plate 95 to limit the end 932 of the adjustment bolt 93 to the groove 954 of the bottom wall 922.
As described above, in order to achieve a stable operation of the force adjustment device while using such a hydraulic system 9, the fitting relationship between the essential elements of the hydraulic system 9 needs to be complicated and many essential elements are required, and thus, the overall manufacturing cost cannot be reduced.

Cantilever device and hydraulic system thereof


Imatinib can be used in the treatment of stroke in a new dosage regime, where Imatinib is administered to the patient at a dose of 650 mg/day or higher for at least 3 consecutive days, and preferably administered in a starting dose of 1000 mg/day or higher on day 1, and at a dose in the interval of 650 mg/day to 1000 mg/day on the subsequent days. A method for the treatment of stroke, a pharmaceutical composition and a kit of parts is/are also disclosed.

A stroke is defined as the sudden death of brain cells in a localized area due to interrupted or inadequate blood flow. According to the European Cardiovascular Disease Statistics 2012, stroke is the second single most common cause of death in Europe: accounting for almost 1.1 million deaths each year. Over one in seven women (15%) and one in ten men (10%) die from the disease (Melanie Nichols et al., European Cardiovascular Disease Statistics, 2012 Edition, Department of Public Health, University of Oxford).
Depending on the causative factor and progression, a stroke can be designated as one of the following two main types:
Ischemic stroke, which occurs as a result of an obstruction, or clot, within a blood vessel supplying blood to the brain. This accounts for the vast majority of all stroke cases.
Hemorrhagic stroke, which occurs when a blood vessel ruptures. The reason for the rupture can be an aneurysm or an arteriovenous malformation, which can be congenital defects. The most common cause is however uncontrolled hypertension.
The following disclosure will focus on ischemic stroke, and in particular acute ischemic stroke, but is not limited thereto. The goal of all existing treatments of ischemic stroke is to quickly restore the blood flow and to prevent or at least reduce the likelihood of another stroke. Currently, the only FDA approved treatment for ischemic strokes is tissue plasminogen activator (tPA, ALTEPLASE®, ACTIVASE®). tPA works by dissolving the clot and improving blood flow to the part of the brain being deprived of blood flow. If administered early tPA may improve the chances of recovering from a stroke. tPA is however known to have serious side effects such as neurotoxicity and increased vascular permeability due to an altered blood-brain barrier function. There are indications that the balance between the positive effects of tPA and the side effects becomes less favourable to the patient when the onset of tPA therapy is delayed. The exact thresholds vary, but it is recommended in general that tPA therapy should be started as soon as possible, and preferably not later than 4-5 hours after the stroke. Sometimes an even narrower therapeutic window is recommended.
Before administering tPA or other pharmaceutical thrombolysis, it has to be determined if the patient suffers from an acute ischemic stroke of from a hemorrhagic stroke. In the case of haemorrhage, the thrombolysis would worsen the condition. The symptoms alone are usually not specific enough to make this distinction, so usually the patient is subjected to a CT scan or MRI scan to rule out any intracranial haemorrhage. Only then can thrombolytic treatment be started. Depending on the available resources and diagnostic capabilities, this may delay the starting time of thrombolytic therapy, or even make the care giver refrain from such therapy altogether as a precaution. Further, in order to be most effective, thrombolysis should be started within 3 hours from the occurrence of the stroke, preferably as early as possible.
Thrombolysis is the treatment of choice for acute stroke within 3 to 4.5 hours after symptom onset. There are trials indicating that alteplase 3-4.5 h after onset was better than placebo, and a registry study supporting this. Professional recommendations have issued in favour of these results but remain to be fully accepted. However, there are indications that late onset thrombolytic therapy may be associated with more severe side effects. As a consequence, it is possible that a patient does not receive the most appropriate therapy, either because of an uncertainty in the diagnosis (ischemic v. hemorrhagic stroke), or a delay in reaching the diagnosis (delays in obtaining a CT, or the lack of the necessary equipment), or a combination. In practice, only about 10% of the patients receive thrombolytic therapy. Other treatments include mechanical thrombectomy, i.e. the surgical removal or disintegration of the clot, and antiplatelet therapy, preventing new clots from forming. Cumulating experience shows that thrombectomy significantly increases the odds of recovery or at least reduces the neurological damage following a stroke. Unlike thrombolytic drugs, the anti-platelet agents do not have effect on clots that are already present. Aspirin is the most commonly used antiplatelet agent, and there are indications that it is effective for the early treatment of acute ischemic stroke, preferably in combination with dipyridamol.
WO 2007/124308 discloses methods and compositions for preventing or ameliorating the side effects, and for improving the treatment, or extending the treatment window, of tPA where thrombolysis is desired, by using platelet-derived growth factor (PDGF) and PDGF receptor antagonism to counter the undesirable effects of tPA. WO 2007/124308 also discloses a combination therapy in the treatment of ischemic stroke using tPA and a PDGF receptor antagonist. Imatinib mesylate is given as one example of suitable substances that inhibit the PDGF receptor.
In any case, considering the high prevalence of acute ischemic stroke, and the serious consequences such as disabilities and death, there is a need for improved treatments and new drugs.

Imatinib for use in the treatment of stroke

Brain Consultant Nils Gunnar Wahlgren AB


A method for locating a badge for a motor vehicle handsfree system includes transmission in the form of an inquiry of a signal by a first group of antennas of the vehicle to the tag, response of the tag to this first inquiry, transmission in the form of an inquiry of a signal by a second group of antennas of the vehicle to the tag, and response of the tag to this second inquiry. In responding to the first inquiry, the tag stores for a predetermined time span the fact that it has responded to a signal transmitted by an antenna of the first group of antennas. The response made to the second inquiry may include a cue indicating that a response has already been transmitted following an inquiry originating from the first group of antennas.

Generally, for such a hands-free system, a group of antennas is intended to detect the presence of the tag outside the vehicle and another inside the latter. If an authorized tag is detected outside the vehicle, the control and management system will allow access on board the vehicle without however allowing starting, whereas if this tag is inside the vehicle, starting of the engine will be able to occur.
To locate the tag, a signal is sent to a group of antennas which then carry out a corresponding transmission while no signal is sent to the other antennas so that they remain mute. The antennas used are LF (low frequency) antennas transmitting a magnetic field with a frequency usually lying around 125 kHz with a restricted range thus allowing good locating of the corresponding tag. The dialogs between the inside antennas and the tag are of a different kind from the dialogs between the outside antennas and tag. This enables the tag to know in advance the response expected by the vehicle. This response is generally effected by transmitting an RF (radio frequency) signal with a frequency generally lying in the vicinity of 433 MHz.
The inside antennas are generally regarded as reliable. The field transmitted by them does not generally spill over out of the cabin of the vehicle. On the other hand, the outside antennas generally transmit a signal inside the cabin of the vehicle too, generally limited to near the latter's doors. A tag is then regarded as being outside the vehicle if it responds to the outside antennas without however responding to the inside antennas.
The locating of a tag outside the vehicle is therefore based on a nonresponse of the tag to a request by the inside antennas. It may however happen that the tag responds to a request by the inside antennas but that this response is not received by the antennas management device. This problem may stem from several causes, such as for example the presence of glitches or the sending of an RF frame of another system using the same frequency band. This nonreceipt of the response by the vehicle antennas management system will be interpreted as a nonresponse to the request of the inside antennas and the tag will then be regarded as being outside the vehicle although it is in fact inside the latter. The management device will therefore give its agreement to execute an order to lock the vehicle although the user does not have his tag on him. Moreover, anybody will be able to unlock the vehicle with the tag still in the vehicle.

Method for locating a badge for a motor vehicle hands-free system


A portable disc jockey sound system is an apparatus that houses and stores in disc jockey (DJ) equipment in a safe and organized manner. The apparatus includes a pedestal, a table, a base, a portable computing device, a power source, and a sound system. The pedestal uplifts the table from the ground so that a user may engage the sound system with the portable computing device while standing. The table supports and presents the portable computing device and a variety of DJing equipment for the user so that the user may readily access the portable computing device and DJing equipment. The base balances the platform with the ground. The portable computing device controls the sound of the music emitted with the sound system. The power source provides the necessary power for the portable computing device, the sound system, and a variety of other electronic devices connected with the apparatus.

Traditional disc jockey (DJ) equipment are large in size and require a great amount of time and space to set up. DJ equipment are also expensive and easily damaged throughout transportation without proper storage. Taking the time to load and unload expensive DJ equipment cuts into the time a DJ may use elsewhere preparing for an event. Furthermore, events that typically require a DJ are held at venues with strict cleanup times that require the DJ to quickly pack up and leave the venue.
It is therefore an objective of the present invention to facilitate the setup and cleanup for a DJ. The present invention is a portable disc jockey sound system that secures DJ equipment throughout transportation and use. Furthermore, the present invention presents the DJ equipment to a user in an organized manner. The present invention allows a user to accommodate a variety of settings and venues by housing any and all DJ equipment necessary to provide a continuously entertaining performance throughout the entire event.


A neural network development utility assists a developer in generating one or more filters for data to be input to or output from a neural network. A filter is a device which translates data in accordance with a data transformation definition contained in a translate template. Source data for the neural network may be expressed in any arbitrary combination of symbolic or numeric fields in a data base. The developer selects those fields to be used from an interactive menu. The utility scans the selected field entries in the source data base to identify the logical type of each field, and creates a default translate template based on this scan. Numeric data is automatically scaled. The developer may use the default template, or edit it from an interactive editor. When editing the template, the developer may select from a menu of commonly used neural network data formats, and from a menu of commonly used primitive mathematical operations. The developer may interactively define additional filters to perform data transformations in series, thus achieving more complex mathematical operations on the data. Templates may be edited at any time during the development process. If a network does not appear to be giving satisfactory results, the developer may easily alter the template to present inputs in some other format.

Modern computer systems are being used to solve an ever increasing range of complex problems. The use of computers to perform tasks normally associated with human reasoning and cognition is known as artificial intelligence. As the capabilities of computers expand, they are increasingly being used to perform tasks in the field of artificial intelligence. However, although computer hardware to perform complex tasks is available, it is very difficult and time-consuming to write artificial intelligence programs.
In recent years, there has been an increasing amount of interest in solving complex problems with neural networks. A neural network is a collection of simple processors (nodes) connected together, each processor having a plurality of input and output connections. Each processor evaluates some relatively simple mathematical function of the inputs to produce an output. Some of the processor nodes receive input or produce output external to the neural network, but typically most connections run between nodes in the network. An adaptive weighting coefficient is associated with each connection. A neural network is trained to solve a particular problem by presenting the network with examples of input data for the problem and the desired outputs. The neural network adjusts the weighting coefficients to minimize the difference between the output values of the network and the desired output values of the training data. Ideally, a neural network consists of physically separate processor nodes. However, such a neural network is frequently simulated on a single processor computer system with suitable programming. As used herein, the term "neural network" shall encompass an ideal neural network of separate physical processors for each node as well as a simulated neural network executing on a single or other multiple processor computer system.
The promise of neural networks has been that they can be programmed with far less programming effort and expertise than conventional application programs designed to solve problems in the field of artificial intelligence. In theory, the neural network requires no programming at all. Instead, the system is fed a large amount of training data, and finds the solution to the problem based on this data. In reality, constructing a neural network solution is not so simple. A neural network requires that data be presented to it in a suitable form. The programmer must decide what information is to be used as input and output, how this information is to be presented, and other matters. Except in the rare case where information is stored in a form directly usable by the neural network, the programmer will have to create conversion routines to convert raw data into a form which the neural network can use, and to convert the network output into some desired form. The need to code and maintain such conversion functions reduces the benefits that would otherwise be present in neural network applications, and makes it difficult for persons without appropriate programming expertise to build such applications.
Considerable research and development effort has been directed toward making the neural network itself run more efficiently and solve a wider range of problems. However, there has been little emphasis on making the network easier to use. As the capabilities of neural networks increase, an increasing portion of the effort of developing a neural network application will be devoted to the problem of converting input data to an appropriate form for use by the network, and converting output data to an appropriate form for the user. At the same time, as increasing numbers of people develop neural network solutions, the programming sophistication of the average user is likely to decline. Accordingly, there exists a need for mechanisms that will assist the developer of neural network applications in converting input and output data.
It is therefore an object of the present invention to provide an enhanced method and apparatus for using a neural network.
Another object of this invention is to provide an enhanced method and apparatus for developing a neural network application.
Another object of this invention to provide an enhanced method and apparatus for converting data input and output of a neural network.
Another object of this invention is to reduce the cost of developing a neural network application.
Another object of this invention is to reduce the amount of time and effort required to develop a neural network application.
Another object of this invention is to reduce the level of expertise required of the developer of a neural network application.
Another object of this invention is to facilitate the modification of data representation in a neural network during the development of a neural network application.

Apparatus and method for facilitating use of a neural network

International Business Machines Corporation


The present invention is an airtight case comprising a base for receiving a stick-type product, a hollow cap, and a hollow plug sleeve inserted within the cap. The plug sleeve has an open end and a closed end, the closed end being a flexible bellows.. This case is useful in reducing the adverse effects caused by the pressure build-up associated with sealing or airtight cases. When the cap of the present invention is placed on the base of the case the bellows expands in response to the compressing of the air located within the inner chamber of the case, thus preventing the cap from being pulled away from the base. Also, when the cap is removed, the bellows contracts and prevents the product from being pulled out of the base.

It is desirable to have stick-type products that contain a volatile solvent because the volatile solvent provides for a better "feel" of the product when applied to the skin, and allows the product to dry or set quickly. The problem encountered with these types of formulations is that they readily lose the volatile solvent contained within their composition due to evaporation from the product.
The loss of a volatile solvent from a stick-type product can adversely affect the physical properties of the product as well as reduce the amount of volatile delivery. Even when not stored above room temperature, it has been noted that there is loss of the volatile solvent over time.
Prior art cases have tried to remedy this problem by providing a sealed case (see U.S. Pat. Nos. 5,197,814 and 5,342,134). This case provided for the insertion of a flexible sleeve into the cover of the case. When the cover is placed on the base of the case the flexible sleeve makes contact with an outer wall of the base and effectively seals the case and its contents from volatile loss. The flexibility of the sleeve, as described in this invention, is for the purpose of making a seal between the base of the case and the cover, whereby the sleeve flexes around any minor defects on the surface of the base and makes a seal.
The problem with these types of cases is that, although the case does effectively create a seal between the internal chamber and the external environment, a pressure build-up is experienced. This build-up of pressure is created through the compression of the air contained within the case when the cover is applied.
This compression of the air in the case creates a number of unappealing effects. First, when the cover is applied the compression of the air causes a back-pressure which pushes the cover away from the base. This creates a gap between the cover and the base which is not aesthetically appealing and which reduces the effectiveness of the seal between the base and the cover. Modifications can be made to eliminate this problem, for example, reducing the internal diameter of the cover to create a tighter fit between the cover and the base. This, in turn, makes the cover more difficult to remove from the base, which is unacceptable to consumers.
The tighter fit of the cover eliminates the problem of the back-pressure moving the cover away from the base, but in addition to the greater force required to remove the cover, additional drawbacks are encountered. With the cover in place, the pressure build-up within the internal chamber of the case will slowly dissipate through micro-leaks and equilibrate to that of the external environment. This is not an immediate occurrence. The cases will be filled, stored in a warehouse, and then shipped to the counter for consumer purchase. Dissipation of the internal pressure will occur over the time it takes the filled case to reach the consumer, which can take months.
With the internal pressure equal to that of the external environment, removal of the cover causes a depressurizing of the internal chamber. This creates a suction effect which will "pull" on the product and the internal components of the case. This suction will cause the product to either dislodge from the holder, or fracture, thus making the product unusable by the consumer.
This invention provides a case for a volatile solvent-containing stick-type product that aids in preventing the loss of the volatile solvent from the stick-type product.
This invention also provides a case that aids in preventing the undesirable effects associated with pressure build-up and dissipation within sealed cases.
This invention further provides a case for a volatile solvent-containing stick-type product wherein most components of the existing standard cases can still be employed thereby minimizing package re-tooling costs.
Further, this invention provides a case for a volatile solvent-containing stick-type product that prevents the loss of the volatile solvent from the stick-type product while at the same time being a relatively simple device that avoids interference with the package aesthetics.