An unsaturated imide compound represented by formula (1): ##STR1## wherein Q is an alicyclic structure-containing hydrocarbon group having 4-20 carbon atoms; each of R.sub.1, R.sub.2, R.sub.3, R.sub.4, R.sub.i and R.sub.j represents a hydrogen atom, a halogen atom, a hydrocarbon group having 1-6 carbon atoms or a halogen-containing hydrocarbon group having 1-6 carbon atoms; each of a, b, c, d, e and f represents an integer of 0 to 4 satisfying a+b.ltoreq.4, c+d.ltoreq.4 and e+f.ltoreq.4 and D represents a divalent organic group having 2-24 carbon atoms and an ethylenically unsaturated double bond, a process for producing the unsaturated imide compound of formula (1) and intermediates for producing the unsaturated imide compound of formula (1). The unsaturated imide compound of formula (1) is well soluble in organic solvents and can give cured products excellent in heat resistance, low water absorption and flexibility.

This invention relates to a novel unsaturated imide compound which is well soluble in an organic solvent and gives a cured product excellent in heat resistance, low water absorbability and flexibility; a process for producing the unsaturated imide compound; and an intermediate therefor.
A thermosetting resin composition comprising the above unsaturated imide compound as a main component can be used as a laminate, sealing material, insulating material, sliding material and other molding materials in the electric and electronic fields.
This invention is also concerned with a dinitro compound and a diamino compound which are intermediates for producing the above unsaturated imide compound.
Heretofore, electric and electronic parts such as semiconductor and the like have been sealed with an epoxy resin. This is because the sealing with an epoxy resin is more economically advantageous than hermetic seal system using glass, metal and ceramic. However, the recent trend is that the conditions for use of electronic parts become severe. For example, the fabrication method is now switching from insert fabrication to surface fabrication, and this is accompanied by a result that sealing materials per se are exposed to solder bath temperatures. Consequently, the sealing material is required to have excellent heat resistance; however, epoxy resins do not sufficiently satisfy the requirement for heat resistance.
Thermosetting polyimide resin-sealing has been proposed for the purpose of obtaining high heat resistance. For example, 4,4'-diphenylmethane bismaleimide has been known as a bismaleimide type thermosetting resin. The cured product of this compound is excellent in heat resistance, but is brittle and high in hygroscopicity. Also, this compound has a low solubility in general purpose organic solvents and it is difficult to prepare a varnish therefrom in the formation of a laminate or the like.
The known general method for preparing unsaturated imide compounds is a chemical ring-closure method which comprises reacting an aromatic amine solution with a solution of an acid anhydride such as maleic anhydride or the like, and then allowing a dehydrating agent to act thereon [U.S. Pat. No. 2,444,536; Org. Synth., 41, 93 (1961) and the like]. However, this method has a tendency that acetic acid, though in a slight amount, remains in the product and hence acetic acid odor becomes a problem when the product is cured at a high temperature. Impurities due to acetic acid tends to be produced under some conditions, whereby the purity of product is lowered. Many proposals have been made for solving this problem. A typical example thereof is a method comprising reacting an aromatic amine solution with a solution of an acid anhydride such as maleic anhydride or the like, and then heat-dehydrating the resulting amic acid solution to cause ring-closure (for example, Japanese Patent Kokoku No. 55-46,394, Japanese Patent Application Kokai No. 60-11,465 and the like). According to this method, no acetic acid is produced, and hence, there is no problem due to acetic acid. However, since unsaturated imide compounds which are thermosetting resins are exposed to high temperature during curing, there are such problems that a high molecular weight product and gel are produced depending upon the reaction conditions and the structure and reactivity of the imide, whereby the purity of product is lowered and the still is contaminated. When the reaction conditions are made mild for solving the above problems, the reaction time must be greatly prolonged.

Unsaturated imide compounds containing alicyclic structure, process for producing the same and intermediate therefor


A patterned substrate for epitaxially forming a light-emitting diode includes: a top surface; a plurality of spaced apart recesses, each of which is indented downwardly from the top surface and each of which is defined by a recess-defining wall, the recess-defining wall having a bottom wall face, and a surrounding wall face that extends from the bottom wall face to the top surface; and a plurality of protrusions, each of which protrudes upwardly from the bottom wall face of the recess-defining wall of a respective one of the recesses. A light-emitting diode having the patterned substrate is also disclosed.

1. Field of the Invention
This invention relates to a patterned substrate and a light-emitting diode having the patterned substrate.
2. Description of the Related Art
A light-emitting diode (LED) has been widely used in a backlight module of a display, a traffic light, a lighting equipment, etc. When the LED serves as a light source for illumination or for supplying optical energy, a sufficient luminance is one of the basic requirements for the LED.
Therefore, in order to solve the problem of insufficient luminance of the LED, the inventors of this application had proposed a light-emitting element that is disclosed in Taiwan patent no. 1236773. Referring to FIGS. 1 and 2, the light-emitting element includes a substrate 11 that is primarily made of sapphire, an epitaxial layer unit 12 formed on the substrate 11, a Ti/Al/Ti/Au contact electrode 13, and a Ni/Au contact electrode 14.
The substrate 11 is patterned, and has a top surface 111, and a plurality of recesses 112 that are indented downwardly from the top surface 111 and that are spaced apart from each other. Each of the recesses 112 has a depth of 1.5 microns, and a bottom wall face having a diameter of 3 microns. A center-to-center distance between adjacent ones of the recesses is greater than 3 microns (for example, 5 microns).
The epitaxial layer unit 12 primarily made of a GaN material is formed on the top surface 111 of the substrate 11 and fills the recesses 112. The epitaxial layer unit 12 includes, from bottom to top, an n-type semiconductor layer 121 that is formed on the top surface 111 of the substrate 11 and that fills the recesses 112, a light-emitting layer 122 that partially covers the n-type semiconductor layer 121 and that is capable of emitting light with a predetermined range of wavelength, and a p-type semiconductor layer 123 covering the light-emitting layer 122.
The Ti/Al/Ti/Au contact electrode 13 and the Ni/Au contact electrode 14 are respectively disposed on the n-type semiconductor layer 121 and the p-type semiconductor layer 123, and are used to supply electricity to the epitaxial layer unit 12.
After external electricity is applied to the Ti/Al/Ti/Au contact electrode 13 and the Ni/Au contact electrode 14, the electricity flows to the n-type semiconductor layer 121, the p-type semiconductor layer 123, and the light-emitting layer 122, and is converted to optical energy to emit light outwardly.
When the light from the light-emitting layer 122 toward the substrate 11 travels to the top surface 111 and the recesses 112 of the substrate 11, the light can be reflected by the top surface 111 and the recesses 112 more than one time. Accordingly, the luminance of the light-emitting element is higher than that of a light-emitting element without a patterned substrate.
On the other hand, the recesses 112 may efficiently reduce defects and dislocation of the epitaxial layer unit 12. Therefore, an internal quantum efficiency of the light-emitting element may be enhanced, thereby resulting in an increase in luminance of the light-emitting element.
Because the patterned substrate 11 may efficiently improve the quality of the epitaxial layer unit 12 and may vary a traveling pathway of the light, studies to further enhance the luminance of the light-emitting element by varying patterns on the substrate 11 are continuously ongoing.

Patterned substrate and light-emitting diode having the same


A memory device includes a memory cell array including a plurality of memory cells, a common source line to which sources of the plurality of memory cells are commonly connected, and a second electrical connection path further connecting the common source line to a ground voltage using erase-mode memory cells when the common source line forms a first electrical connection path and is connected to the ground voltage.

The present invention relates to a memory device and, particularly, to a memory device including a common source line that commonly connects sources of a plurality of memory cells.
Flash memory has been widely used as nonvolatile memory, and a larger capacity and a higher speed are demanded with the advancement of information and communications technology.
FIG. 27A shows a structure of a memory cell constituting a typical flash memory. Note that the memory cell is the minimum unit to store information of "0" or "1".
As shown in FIG. 27A, a memory cell 10 is one type of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and includes an insulated floating gate 13, which is different from a typical MOSFET. A selection gate (word gate) 11 is formed above the floating gate 13, and the floating gate 13 and the selection gate 11 are insulated from each other with an inter-polysilicon dielectric film 12 interposed therebetween. The inter-polysilicon dielectric film 12 is called "inter-poly dielectric (IPD)" because the selection gate 11 and the floating gate 13 are generally made of polysilicon. Further, a gate dielectric film 14 is formed between the floating gate 13 and a silicon substrate, which is the same as a typical MOSFET. Further, inside the surface of the silicon substrate, electrodes serving as a source 16 and a drain 15 are formed with a gate placed therebetween, which is the same as a typical MOSFET.
As shown in FIG. 27B, the memory cell 10 performs storage operation by accumulating charge in the floating gate 13. Because the floating gate 13 is completely insulated from the surroundings, it has a structure (nonvolatile structure) where the accumulated charge does not escape from the gate even when the power is off. Thus, the memory cell 10 stores one bit of data depending on the presence or absence of charge by electrons in the floating gate 13.
The memory cell array according to related art where such memory cells are arranged in an array is disclosed in Japanese Unexamined Patent Application Publication No. 2000-49316. FIGS. 28A to 28C show the memory cell array according to related art disclosed therein.
As shown in FIGS. 28A to 28C, in a memory cell array 900 according to related art, a source region 903 and a drain region 904 are formed separately from each other in the surface area of a silicon substrate 901. The source region 903 is formed in a continuous pattern along the row direction and commonly connected between adjacent memory cells (common source line). On a channel region between the source region 903 and the drain region 904 of each cell transistor, a floating gate 906 is formed with a tunnel oxide film 905 interposed therebetween.
A control gate 908 is formed above the floating gate 906 with a dielectric film 907 interposed therebetween. The control gate 908 lies along the row direction and forms a word line.
On the above-described stacked gate structure, an interlayer dielectric film 909 is formed, and a bit line 910 and a source line 911 are formed on the interlayer dielectric film 909 along the column direction intersecting each word line (control gate) 908. The source line 911 is connected to the source region 903 via a through hole 913 in a source contact portion 912, and the bit line 910 is connected to the drain region 904 via a through hole 914.

Memory device with erase mode memory cells


A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information. In erasing data, the redundancy control circuits switch the erasing bias circuits so as to inhibit the application of an erasing bias to word and source lines connected to control gates of the normal memory cell array that is replaced by the redundant memory cell array and also inhibit the erasing bias application to those connected to control gates of the unused redundant memory cell array.

1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that stores information in floating gates.
2. Description of the Related Art
A nonvolatile semiconductor memory stores information by the presence or absence of charge accumulated on floating gates. Examples of such a nonvolatile semiconductor memory include a flash memory, which erases information in memory cells simultaneously. FIG. 24 shows the configuration of a conventional flash memory array. In FIG. 24, reference numeral 1 is a nonvolatile memory cell including a floating gate and a control gate, 2 is a word line connected to the control gate of the nonvolatile memory cell 1, 3 is a bit line, and 4 is a source line. As shown in FIG. 24, each nonvolatile memory cell 1 is formed independently at the intersection of the word line 2 and the bit line 3.
To erase data from the nonvolatile memory cells 1, a high voltage is applied to the word lines 2 and the source lines 4. At the time of erasing, the same voltage VNEG is applied to all the word lines via switching elements 5 selected by an erasing block decoder 6. For reading and writing, each of the nonvolatile memory cells is selected independently by a selecting circuit (not shown in FIG. 24). Like the word lines 2, the same voltage VPOS is applied simultaneously to the source lines 4 during erasing. In other words, data is erased at once during erasing.
The nonvolatile memory includes a redundant memory cell array 8, which is located adjacent to a normal memory cell array 7, to repair memory defects in a redundant manner. The normal memory cell array 7 and the redundant memory cell array 8 share the bit lines 3. When a redundant word line 2R is used, the word line having a defective bit is not used.
However, an erasing voltage is applied to the cells connected to the defective word line because the erasing circuit is the same. Consequently, those cells are over-erased, compared with the cells connected to other normal word lines 2. Thus, the memory cells connected to the defective word line are depleted to cause bit-line leakage during reading, resulting in malfunction.
To solve the problem, e.g., JP 7(1995)-230700 A discloses a method for preventing the application of an erasing bias to the source line of a replaced defective cell. Using this method, however, the erasing bias is applied to the word line. Therefore, charge is drawn from the floating gate, which may cause over-erasing.
There is another method in which a redundant word line is provided or each erasing block, as shown in FIG. 25. For example, when a second formal erasing block 72 is found to be defective, it is replaced by a redundant erasing block 8, as shown in FIG. 25. Since the second normal erasing block 72 is not accessed permanently, no erasing bias is applied thereto. Therefore, such over-erasing as described above does not occur.
However, the erasing block is usually composed of tens to hundreds of kilobits as a unit, and the size of a unit to be replaced for one defective cell is the same as that of the erasing block. Thus, the repair efficiency is rather poor.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a nonvolatile semiconductor memory device that can prevent over-erasing even if a memory cell is replaced in the word line direction and provide high repair efficiency.
To achieve the above object, a first nonvolatile semiconductor memory device of the present invention includes: N (N is a natural number) normal memory cell arrays, a redundant memory cell array, (N+1) erasing bias circuits, N erasing decode circuits, and N redundancy control circuits. Each of the N normal memory cell arrays includes the arrangement of two or more nonvolatile memory cells, each having a control gate and a floating gate. The redundant memory cell array includes the arrangement of two or more nonvolatile memory cells, each having the same configuration as that of the nonvolatile memory cell in the normal memory cell array. The (N+1) erasing bias circuits apply an erasing bias for erasing data stored in the N normal memory cell. arrays and the redundant memory cell array. The N erasing decode circuits decode defective address information. The N redundancy control circuits are connected in series so that a preceding stage controls the next in order to store the defective address information for switching the (N+1) erasing bias circuits based on the defective address information responsive to output signals from the respective N erasing decode circuits. The (N+1) erasing bias circuits inhibit application of the erasing bias to word and source lines connected to the control gates of any one of the N normal memory cell arrays that is replaced by the redundant memory cell array and also inhibit application of the erasing bias to word and source lines connected to the control gates of the unused redundant memory cell array under a switching operation by the N redundancy control circuits in erasing data.
In the first nonvolatile semiconductor memory device, it is preferable that the size of an array of the N normal memory cell arrays is the same as that of the redundant memory cell array and is equal to or less than that of a minimum erasing block.
In the first nonvolatile semiconductor memory device, it is preferable that the (N+1) erasing bias circuits apply the erasing bias to any number of memory cell arrays among the N normal memory cell arrays and the redundant memory cell array under a switching operation by the N redundancy control circuits based on output signals from the N erasing decode circuits.
In the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes an input terminal, a first output terminal, and a second output terminal. The input terminal receives an output signal from the erasing decode circuit and a defective address program activation signal. The first output terminal switches an erasing bias activation signal and outputs it to one of the adjacent erasing bias circuits, and the second output terminal switches the erasing bias activation signal and outputs it to the other erasing bias circuit. It is also preferable that the second output terminal of one of the adjacent redundancy control circuits and the first output terminal of the other redundancy control circuit are connected in common. Each of the N redundancy control circuits stores the defective address information based on the output signal from the erasing decode circuit when the defective address program activation signal is activated, and among the N redundancy control circuits, a redundancy control circuit storing the defective address information controls the next redundancy control circuit so as to switch the terminals for outputting the erasing bias activation signal.
The above configuration can eliminate over-erased memory cells because no erasing bias is applied to the unused word and source lines of a memory cell array. Therefore, it can prevent malfunction due to bit-line leakage. Moreover, this configuration enables the replacement of a normal memory cell array by a redundant memory cell array for each word line, thus providing a higher repair efficiency than that of a conventional replacement for each erasing block.
In the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes a nonvolatile memory cell having a control gate and a floating gate to store the defective address information.
In such a case, it is preferable that each of the N redundancy control circuits includes the following: a nonvolatile memory cell having a gate connected to the preceding redundancy control circuit, a source connected to a first power line, and a drain connected to a common node; a first PMOS transistor having a gate connected to the gate of the nonvolatile memory cell, a source connected to a second power line, and a drain connected to the common node; a second PMOS transistor having a gate connected to the next redundancy control circuit, a source connected to the second power line, and a drain connected to the common node; an inverter having an input terminal connected to the common node and an output terminal connected to the gate of the second PMOS transistor; a first NMOS transistor having a gate receiving the defective address program activation signal, a drain connected to the common node, and a source receiving the defective address information from the erasing decode circuit; a second NMOS transistor having a gate connected to the output terminal of the inverter, a source acting as the first output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor; and a third NMOS transistor having a gate connected to the input terminal of the inverter, a source acting as the second output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor.
According to this configuration, defective address information is stored in the redundancy control circuit via an erasing decode signal. Therefore, only the defective address program activation signal FAPEN is used as a redundancy control signal. Thus, many signals for redundancy decoding are not necessary, which enables the replacement for each word line with a simple layout.
Alternatively, in the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes a static memory cell having two inverters to store the defective address information.
In such a case, it is preferable that each of the N redundancy control circuits includes the following: a static memory cell having first and second inverters, where an input terminal of the first inverter is connected to an output terminal of the second inverter, while an output terminal of the first inverter is connected to an input terminal of the second inverter; a first NMOS transistor having a gate receiving the defective address program activation signal, a drain connected to one input/output terminal of the static memory cell, and a source receiving the defective address information from the erasing decode circuit; a second NMOS transistor having a gate connected to the other input/output terminal of the static memory cell and a source connected to a first power line; a third NMOS transistor having a gate connected to the preceding redundancy control circuit, a drain connected to a common node, and a source connected to the drain of the second NMOS transistor; a first PMOS transistor having a gate connected to the gate of the third NMOS transistor, a drain connected to the common node, and a source connected to a second power line; a second PMOS transistor having a gate connected to the next redundancy control circuit, a source connected to the second power line, and a drain connected to the common node; a third inverter having an input terminal connected to the common node and an output terminal connected to the gate of the second PMOS transistor; a fourth NMOS transistor having a gate connected to the output terminal of the third inverter, a source acting as the first output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor; and a fifth NMOS transistor having a gate connected to the input terminal of the third inverter, a source acting as the second output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor.
This configuration employs the static memory cell to store defective address information. Therefore, it is not necessary to apply a high voltage, which eliminates the need for a device with a high withstand voltage. Thus, a large separation width, longer channel length, channel offset, and the like are not required to maintain a withstand voltage, simplifying the layout.
To achieve the above object, a second nonvolatile semiconductor memory device of the present invention includes an erasing pre-decode circuit and erasing decode circuits: the erasing pre-decode circuit receives a plurality of erasing address signals and outputs a plurality of first and second erasing pre-decode signals; the erasing decode circuits receive the first and second erasing pre-decode signals and output a plurality of erasing decode signals. Any combination of the erasing address signals activates the desired number of erasing pre-decode signals of the first and second erasing pre-decode signals so that the desired number of erasing decode signals are activated.
This configuration can set the size of a block to be erased in a nonvolatile memory array flexibly with the same erasing decode circuit. Thus, modification of the erasing circuit can be made easily in accordance with the use of a memory chip.
In the second nonvolatile semiconductor memory device, it is preferable that the erasing pre-decode circuit includes an address degeneration circuit and a multiplex pre-decode circuit: the address degeneration circuit receives the erasing address signals and outputs the same number of address degeneration signals as that of the erasing address signals; the multiplex pre-decode circuit receives the erasing address signals and the address degeneration signals and outputs the erasing pre-decode signals. A combination of the erasing address signals generates any address degeneration signal so as to degenerate any address of the erasing address signals and thus any of the erasing pre-decode signals are multiplexed.
This configuration provides the address degeneration circuit and the multiplex pre-decode circuit separately. Therefore, the erasing pre-decode signals can be combined for multiplexing with the same erasing pre-decode circuit and only by modifying the contents of the address degeneration circuit. Thus, modification of the erasing circuit can be made easily in accordance with the use of a memory chip.
In such a case, it is preferable that the address degeneration circuit includes a decoder and a group of combinatorial logic elements: the decoder receives the erasing address signals; the group of combinatorial logic elements receives all outputs from the decoder and outputs the address degeneration signals. It is also preferable that the group of combinatorial logic elements includes OR circuits, each receiving the same number of control signals as that of the erasing address signals and outputting the address degeneration signal in accordance with a combination of the erasing address signals and the control signals. Moreover, it is preferable that the control signals are stored in an information storage means located separately from the address degeneration circuit on the same substrate.
This configuration can change the combinations for address degeneration by changing the states of the control signals in the same chip. Thus, the size of a block to be erased can be changed in the same chip, allowing the device to be used for many applications.
In the second nonvolatile semiconductor memory device, it is preferable that the group of combinatorial logic elements includes OR circuits, each including the same number of nonvolatile memory cells as that of the erasing address signals; control gates of the nonvolatile memory cells are each supplied with the erasing address signal and drains thereof are connected in common to form an output node of the OR circuit; and the OR circuit outputs the address degeneration signal in accordance with a combination of the erasing address signals and information stored in the nonvolatile memory cells. In such a case, it is preferable that desired information is stored in the nonvolatile memory cells by supplying the erasing address signals to each of the control gates of the nonvolatile memory cells and applying a desired voltage to the output node of the OR circuit.
This configuration can change the combinations for address degeneration by modifying the contents of the nonvolatile memory cells in the address degeneration circuit in the same chip. Thus, the size of a block to be erased can be changed in the same chip, allowing the device to be used for many applications. Moreover, the number of excess control signal lines can be reduced, so that a smaller layout area can be achieved.
It is preferable that the first nonvolatile semiconductor memory device further includes an erasing pre-decode circuit including an address degeneration circuit and a multiplex pre-decode circuit: the address degeneration circuit receives a plurality of erasing address signals and outputs the same number of address degeneration signals as that of the erasing address signals; the multiplex pre-decode circuit receives the erasing address signals and the address degeneration signals and outputs a plurality of first and second erasing pre-decode signals. It is also preferable that the erasing decode circuits receive the first and second erasing pre-decode signals from the erasing pre-decode circuit and output erasing decode signals, with which any number of normal memory cell arrays in a plurality of combinations are activated so as to repair a defective address of any one of those normal memory cell arrays. In such a case, it is preferable that the erasing decode circuits are shared in an erasing mode and a program mode, and the number of source lines to be selected in the program mode is made smaller than that in the erasing mode by changing the activated address degeneration signals depending on the erasing and program modes.
According to this configuration, the number of source lines to which a bias is applied in the program mode can be made smaller than that in the erasing mode. Thus, source-line disturbance can be reduced, thereby ensuring high reliability.

Matsushita Electric Industrial Co., Ltd.


An echo canceler has an adaptive filter that generates an echo replica signal from a far-end signal. The filter coefficients of the adaptive filter are updated according to a residual error signal, which is obtained by subtracting the echo replica signal from a near-end signal to cancel echo. A background noise estimator estimates the near-end background noise power level from the residual error signal. A step size calculator uses the estimated near-end background noise power in determining the step size of the adaptive updating of the filter coefficients. When the estimated near-end background noise level is high, a small step size is used, which improves echo cancellation under these conditions. When the estimated near-end background noise level is low, a larger step size is used to permit rapid convergence of the filter coefficients.

1. Field of the Invention
The present invention relates to an echo canceler and echo canceling method useful, for example, for canceling line echo arising from a hybrid circuit in a telephone circuit.
2. Description of the Related Art
Referring to FIG. 1, a conventional echo canceler 10 of this type comprises an adaptive filter 11, a subtractor 12 (depicted as an adder with a negative subtrahend input terminal), a double-talk detector 13, a squared norm calculator 14, and a step size calculator 15.
The echo canceler 10 receives a far-end input signal Rin from the party at the far end of the telephone connection. This far-end input signal Rin is furnished to the party at the near end of the connection as a far-end output signal Rout, and is furnished to the adaptive filter 11 as a digital far-end signal x(n).
The adaptive filter 11 uses a set of filter coefficients to filter the far-end signal x(n) (which is identical to Rin), thereby generates an echo replica signal y(n), and updates the filter coefficients according to a residual error signal e(n).
The subtractor 12 subtracts the echo replica signal y(n) from a near-end input signal Sin received from the party at the near end to generate the residual error signal RES (also denoted e(n)), which is input to the adaptive filter 11 and, at the same time, is transmitted toward the party at the far end. The subtractor 12 thereby removes an echo from the outgoing signal sent to the far end.
The double-talk detector 13 monitors the far-end input signal Rin, near-end input signal Sin, and residual error signal RES to supervise the state of speech on the line. The double-talk detector 13 disables the updating of the coefficients in the adaptive filter 11 when the party at the near end speaks, when both parties speak, and when neither party is speaking, and enables updating of the coefficients when only the party at the far end speaks.
The squared norm calculator 14 receives the far-end input signal Rin (x(n)), calculates its squared norm (∥x(n)∥2), and outputs the calculated result to the step size calculator 15. The squared norm (∥x(n)∥2) is calculated as follows:
                                                                    x                                            (                n                )                                                          2                =                                            x              2                                                  (              n              )                                +                                    x              2                                                  (                              n                -                1                            )                                +          …          +                                    x              2                                                  (                              n                -                M                +                1                            )                                                              =                                                                          x                                                  (                                      n                    -                    1                                    )                                                                    2                    +                                    x              2                                                  (              n              )                                -                                    x              2                                                  (                              n                -                M                            )                                          The letter M indicates the tap length of the adaptive filter 11.
The step size calculator 15 receives the squared norm (∥x(n)∥2) of the far-end input signal Rin (x(n)) and the residual error signal RES (e(n)), calculates a step size for updating the filter coefficients, and provides the step size to the adaptive filter 11.
The hybrid circuit 20 in FIG. 1 has a two-wire/four-wire conversion function with which it interfaces the two-wire circuit leading to the near-end telephone (not shown) with the four-wire circuit formed by the separate transmitting and receiving paths in the echo canceler 10.
When the party at the far end speaks, the input signal Rin that the echo canceler 10 receives from the far end is passed to the hybrid circuit 20 as the far-end output signal Rout (Rout is identical to the far-end input signal Rin) and, at the same time, is provided internally to the adaptive filter 11.
The hybrid circuit 20 transmits the far-end output signal Rout onward to the party at the near end, or more precisely, to the near-end party's telephone (not shown). Some of the signal energy, however, leaks into the near-end input signal Sin and returns to the echo canceler 10 as line echo. If only the far-end party is speaking, substantially all of the near-end input signal Sin may be line echo.
In the echo canceler 10, the adaptive filter 11 uses the filter coefficients to filter the far-end input signal x(n), thereby generates the echo replica signal y(n), and outputs it to the subtractor 12. The subtractor 12 subtracts the echo replica signal y(n) from the near-end input signal Sin to remove the echo.
One known algorithm for updating the coefficients of the adaptive filter is the normalized least mean squares (LMS) algorithm.
The normalized LMS coefficient updating formula can be written, for example, as follows (k=0, 1, 2, . . . , M−1):
            h      k                  (              n        +        1            )        =                    h        k                          (        n        )              +                            α                                                                          e                                      (              n              )                                                β          +                                                                  x                                                  (                  n                  )                                                                    2                                            x                          (                      n            -            k                    )
In the above equation, α is a step size parameter, the terms hk(n) and hk(n+1) are the filter coefficients before updating and after updating, respectively, and M is the filter tap length. The quantity β is a constant that is normally greater than zero, but may be set to zero.
The term ∥x(n)∥2 represents the squared norm of the far-end input signal Rin (x(n)) and can be calculated as shown above.
If a step size μ variable is defined as
      μ    =          α              β        +                                                        x                                            (                n                )                                                          2                      ,the variable μ can be used to rewrite the normalized LMS coefficient updating formula in the following form:hk(n+1)=hk(n)+μ·e(n)·x(n−k)
The adaptive filter 11 calculates the value of the echo replica signal y(n) as follows:
      y              (      n      )        =            ∑              k        =        0                    M        -        1                                x                          (                      n            -            k                    )                    ·                        h          k                                  (          n          )
From these equations, the step size calculator 15 calculates the step size μ and the adaptive filter 11 updates the filter coefficients hk(n) and generates the echo replica signal y(n).
The normalized LMS algorithm converges if 0<α<2. Convergence is fastest with unity step size (α=1.0), but with smaller step size values, the updating of the filter coefficients becomes more conservative and the stability of the adaptive filter is improved. Improved stability means that the filter coefficients are less apt to diverge because of disturbances such as near-end background noise, or because of narrow-band signal inputs such as tone signals.
Details of the normalized LMS algorithm can be found in Adaptive Filter Theory by Simon Haykin (Prentice Hall, fourth edition 2001).
An ideal echo canceler should have high convergence speed, little residual error after adaptation has converged, and high stability.
A problem with the conventional echo canceler described above is that the echo cancellation performance is significantly degraded in environments with much near-end background noise.
FIGS. 2A to 2E show simulated signal waveforms in the conventional echo canceler in an environment with little background noise: FIG. 2A represents the received far-end input signal Rin; FIG. 2B shows the corresponding echo that leaks through the hybrid circuit 20; FIG. 2C represents near-end background noise Sgen; FIG. 2D shows the near-end input signal Sin; FIG. 2F represents the residual signal RES after echo cancellation. Time (t) in seconds (sec) is indicated on the horizontal axis in these figures. The vertical scale in FIG. 2A is compressed in relation to the vertical scales in FIGS. 2B to 2E. FIGS. 3A to 3E show the corresponding simulated signal level waveforms, signal level being expressed in dBm.
In these simulations, the characteristics of the echo path were modeled by use of echo path model 1 in Annex D of Recommendation G.168-2004 of the Telecommunication Standardization Sector of the International Telecommunications Union (ITU-T). The hybrid echo return loss was assumed to be 10 dB, so the signal level of the echo signal Echo in FIG. 3B is 10 dB lower than the signal level of the far-end input signal Rin in FIG. 3A.
Near-end background noise is indicated by the symbol Sgen. A background noise level of −65 dBm is assumed as an example of an environment with little background noise.
The near-end input signal Sin is the sum of the echo signal Echo and the near-end background noise Sgen.
The signal levels in FIGS. 3A to 3E were calculated according to the level measurement method described in the G.168-2004 Section 184.108.40.206.1.
In the simulations in FIGS. 2A to 2E and FIGS. 3A to 3E, the step size parameter α, constant β, and filter tap length M were set to the following values: α=0.5, β=0, M=128.
Although the double-talk detector 13 monitors the far-end input signal Rin, near-end input signal Sin, and residual error signal RES to supervise the speech state, since the near-end party was assumed not to be speaking in this simulation, the operation of the double-talk detector 13 was simplified as follows. If the condition∥x(n)∥2≦−40 dbmis true, the far-end input signal Rin(x(n)) is treated as silent and the double-talk detector 13 disables updating of the coefficients in the adaptive filter 11; otherwise, the double-talk detector 13 enables updating of the coefficients in the adaptive filter 11. The threshold value (−40 dBm) is exemplary; other values could be used instead.
As shown by the signal levels in FIGS. 3B and 3E, although the echo signal level of the near-end input signal Sin reaches peak values of about −15 dBm, the level of the residual error signal RES after convergence is close to the background noise level of −65 dBm, indicating that the echo has been successfully canceled.
FIGS. 4A to 4E and FIGS. 5A to 5E show simulation results for the conventional echo canceler in an environment with much background noise. The signals represented and the scales on the horizontal and vertical axes are the same as in FIGS. 2A to 2E and FIGS. 3A to 3E.
As an example of an environment with much background noise, the level of the background noise Sgen generated at the near end was assumed to be −45 dBm. The other conditions were the same as in the preceding simulation of an environment with little background noise.
As shown by the signal levels in FIGS. 5B and 5E, the peak echo signal level of the near-end input signal Sin was again about −15 dBm, and the level of the residual error signal RES after convergence was about −35 dBm. Accordingly, although the echo was reduced, the residual signal level was still larger by about 10 dBm than the background noise level of −45 dBm, indicating significantly degraded echo canceling performance.
The reason why echo canceling performance is degraded in an environment with much background noise is thought to be as follows. The near-end input signal Sin input to the subtractor 12 includes background noise from the near end and line echo from the hybrid circuit 20. Subtraction of the echo replica signal y(n) from the near-end input signal in the subtractor 12 reduces the line echo, but does not reduce the near-end background noise, which remains present in the residual error signal RES. When the adaptive filter 11 updates its coefficients, this background noise interferes so that the filter coefficients do not converge as expected, making the echo replica signal an inaccurate replica of the true line echo.
The echo canceling performance in an environment with much background noise can be improved by reducing the step size parameter α and increasing the constant β, but this method has the drawback of reducing the speed of convergence in an environment with little background noise.


The new and distinct hybrid plant of Heuchera named ‘Berry Timeless’ with foliage having broad silver variegation and dark-green regions surrounding the veins, flowering without vernalization requirement, from early summer to fall frost with coloring of light pink petals and effective, persistent, dark-rose calyxes just above foliage suitable for landscaping or as cut flower or foliage decoration. The new plant is vigorous, compact in habit and tolerates heat and humidity well.

The present invention relates to a new and distinct cultivar of Coral Bells in the Saxifragaceae family and given the cultivar name of 'Berry Timeless'. Heuchera 'Berry Timeless' was hybridized by Hans A. Hansen on Jan. 24, 2012 at a nursery in Zeeland, Mich., USA and originally given the breeder code of H12-129-01. The seed or female parent was a selected, unreleased, proprietary seedling known as Heuchera K10-46-01 (not patented) and the pollen or male parent was Heuchera 'Cherry Cola' U.S. Plant Pat. No. 22,967. The new invention has a mixture of Heuchera americana, H. brizoides, H. micrantha and H. villosa in the pedigree.
Heuchera 'Berry Timeless' was first selected in the spring of 2012 and passed final evaluation in the fall of 2013 from among thousands of other seedlings from the same cross and hundreds of other crosses. Heuchera 'Berry Timeless' was has been asexually propagated by division at the same nursery in Zeeland, Mich. and by careful tissue culture propagation, and the resultant plants have remained stable and exhibit the same characteristics as the original plant for multiple generations.
Heuchera 'Berry Timeless' has not been made publically available or sold anywhere in the world prior to the filing of this application. Any public disclosure of 'Berry Timeless' has been by the inventor, or one who obtained the material either directly or indirectly from the inventor, and any such disclosure has not been made more than one year prior to the application of this invention.


A four valve, double overhead camshaft diesel engine (10) has a precombustion chamber (30) with an angled and tapered transfer passage (60) leading to the main combustion chamber (44). The transfer passage (60) is tapered to provide a larger lower end (62) facing the main chamber (44) and smaller upper end (64) facing the pre-combustion chamber (30). The pre-combustion chamber is spherical, located on one side of the main combustion chamber. Air passing through the passage (60) during the compression stroke undergoes heating and swirling within the pre-combustion chamber. The piston has a domed upper surface with recessed lobes (20) and (22). Each recessed lobe functions as a valve pocket for the intake and exhaust valves (32) and (42).

High speed automotive diesel engines capable of 4500 to 5000 r.p.m. that have been in mass production are the Daimler-Benz engine or variations of the Ricardo "Comet" design. The engines have all been 2 valves; OHV or OHC design. Diesel engines have their own distinctive complications due to the high compression ratios needed to run these engines. Firstly, a strong bridge is desired in the cylinder head between the exhaust and intake valves to allow for sufficient strength and for providing in the "Comet" design, a coolant passage to pass through the bridge.
Secondly, valve lift during valve overlap with the piston at or near top dead center is reduced to prevent hitting the valves with the piston, due to the small clearance required between the valves and the piston to maintain the high compression ratios needed for operation. In theory, the maximum valve lift is in direct proportion to the inner seat diameter of the valve. Further valve lift beyond the calculated maximum valve lift provides for very little additional air flow due to the restriction of the diameter at the throat of the port. The valves on these prior art diesels are made substantially smaller than valves for an equivalent version of a gasoline spark ignition engine to allow for larger valve bridges to withstand the higher diesel firing pressures. The smaller size and reduced lift gravely affect the volumetric efficiency and air flow of diesel engines, especially prior-art engines with only two valves.
With two-valve engine technology compared to multi-valve engines, and high lifts on account of the large valve sizes; proper valve dynamics dictate very long valve periods to achieve high lifts. Mechanically, also, the spring forces are very high and that increases valve-train friction and power loss.
The valve lift is adversely affected at the critical valve overlap period when the intake valve is beginning to open and the exhaust valve is closing for these prior art two-valve engines use flat topped pistons (except for known combustion spectacles) and flat bottomed cylinder heads. The limitation of valve lift at this time affects the thorough flushing of the exhaust gases and inhibits the cylinder filling process for the subsequent cycle. The reduced valve lift during the overlap period, and the large valve periods force a late intake closing and an early exhaust opening. A late intake closing reduces the effective compression ratio with detrimental starting and running consequences, and greatly reduces the volumetric efficiency at low speeds. An early exhaust valve opening wastes energy and raises the exhaust gas and exhaust valve temperature which forces the use of more expensive and exotic high temperature valve and seat materials. An early exhaust closing raises the probability of a recompression spike, or "lock-up" at TDC during the scavenging or overlap portion of the cycle at high speed and high load, when in some engines, there is not sufficient real time available for a complete evacuation of the exhaust gases. Recompression spikes, apart from inhibiting the proper gas-flow process and reducing volumetric efficiency and power, consume power by creating negative work on the exhaust stroke near TDC. The exhaust valve closing should occur late enough during an extended overlap period with the intake valve to prevent a recompression spike near top dead center which is a difficult objective to obtain due to the piston being near top dead center.
Diesel engines tolerate these problems at low speeds. The operation at low speed provides sufficient time for the air flow through the intake and exhaust valves to pass into and out of the cylinder even with a delayed intake valve opening or early exhaust valve closing. Speeds increased slowly as fuel systems, materials and lubrication improved and engine sizes were reduced. The problems associated with valve timing and air flow lag become magnified at high speeds. Moreover, the high compression ratios of a conventional high-speed I.D.I. diesel engine with the piston at top dead center being very close to the valves dictate that the intake valves cannot be opened early due to crashing into the piston and the exhaust valve cannot be closed late due to the crashing of the piston into the exhaust valve. The unnatural valve timings detract from the potential high-speed capability of these type of diesel engines.
A major compromise of these prior-art high-speed, 2-valve engines results when the valve opening duration must be extended at high speed to improve the volumetric efficiency lost by the lack of proper overlap. In every case, the intake valve closes excessively late in the compression stroke, and the effective compression ratio, effective compression pressure and effective compression temperature are too low even for the high speeds. When such engines run at low speeds, the same applies, but in addition, the volumetric efficiency suffers because the upward piston motion on the compression stroke "spit-back" into the intake manifold the air which has already been admitted into the engine and for which energy has been spent. Negative work (more energy wasted) also results from returning certain amounts of this already-admitted air back into the intake manifold. The situation is further aggravated at cranking speeds, especially cold when the batteries are weak and the oil is thick and said speeds are in the order of 100-150 rpm. The effective compression ratio and volumetric efficiency (i.e. compression pressure and temperature) under said conditions is lowered so much that cold startability is greatly affected or impossible.
Another compromise is when engines attempt to use the same components for both gasoline and diesel engines. In the past, gasoline and diesel engines did not have many components that were interchangeable. Neither engine could be economically and feasibly converted to the other type. This makes diesel engines less desirable because of its lower sales volume.
Lower speed diesel engines running up to 2600 r.p.m. have been developed with four valves to circumvent the breathing and valve timing problems of their prior art two valve counterparts. The use of four valves decreases the restriction of air flow through the valve openings. It is common to have a 40% increase in total air flow cross-section as compared to a conventional two valve cylinder head engine. Since each valve is smaller compared to a two valve cylinder head assembly, the lift can be reduced. The stem can also be made smaller in diameter, shorter and with less mass. Because each valve is lighter, the springs can be made softer. The softer springs provide for a more efficient engine. Because there is decreased lift for each valve, the cams on the cam shaft are often contoured, if desired, for less valve duration with reduced valve dynamic problems. Furthermore, the timing in which the valve needs to be open can be shortened because there is less lift to contend with even with the same valve accelerations. A further improvement results from lower exhaust valve temperatures since each smaller valve has less ratio of surface heat pick-up area to seat heat rejection area and runs much cooler. Furthermore, with the larger valve opening areas but overall smaller diameter valves, the designer can afford to make slightly wider bridges and such bridges are shorter in length, which, added to the lower valve temperature, results in much lower valve head deflections and longer valve and seat life. Additionally, with shorter valve periods the exhaust valve spends less time open, exposed to the exhaust gases, and more time closed and rejecting heat, which lowers the valve temperature even further.
The few known four valve diesel engines by Caterpillar and Continental Motors had a centrally located pre-combustion chamber with a large diameter transfer passage between the pre-combustion chamber and main combustion chamber. The burn or combustion duration was short enough for these lower speed engines but are not short enough to be adapted to high speed diesel engines. Furthermore, the pistons in these diesel engines tended to have heat checking and cracking due to the torch like flame exiting the pre-combustion chamber and impinging at a near perpendicular angle onto the piston surface. These engines suffered from two extra combustion drawbacks: first, by the disposition of their valve train, with pushrods, rocker arms and rocker arm bridges operating the valves, the two intake (and the two exhausts) were in an axis transversal to the main axis of the engine and their porting and flow characteristics were not what would be considered appropriate today. With such disposition of the valves, swirl, or rotational air movement about the cylinder axis, was generated and, although swirl may have been welcomed by the general philosophy of the combustion chamber, it was a weak swirl field and a high air-flow penalty was taken in order to generate it. Secondly, the straight transfer passage of the pre-cup did not promote swirled air motion into the pre-cup. The results were more combustion knock, NO.sub.x, Hydrocarbons, smoke and particulate than a swirling pre-cup could have provided. Yet, both the Caterpillar and the Continental Motors engines were the first engines certified for low emissions, meeting the 1975 truck emission standards.
Modifications to pistons have also increased efficiency of engines. Many engines have a piston with a recess to form part of the combustion chamber or to enhance air swirl. The "Comet" diesel engine had a "spectacle-shaped" recess in its piston to form the main combustion chamber. It was not aligned or coordinated with the valves to act as a pocket to increase the clearance between the valves and the piston at TDC. All previous cylinder heads that helped air tumble have been limited to gasoline spark ignited engines. What is needed is a high-speed diesel engine with highly improved air flow and power output with lower fuel consumption, smoke, particulates and gaseous emissions, improved startability and reduced combustion noise and harshness, and offering increased durability of valves and piston. Means must be provided to achieve such objectives, such as a direct-acting double overhead camshaft configuration to achieve a lightweight, low stress, low power consumption, stiff and quiet valve train with superior air flow characteristics, and a combustion system capable of accomplishing fast and clean combustion both in the early (pre-combustion, in the precombustion chamber) and late (main chamber) combustion.
The subject of this patent provides all the elements to achieve such results in a modern, relatively inexpensive engine package, with a possible cylinder head even converted from appropriate gasoline engine counterparts featuring the airflow capacities of a four valve design with a zero or narrow valve-included angle and DOHC, preferably a mechanically stiff direct-acting design with shorter valve periods, increased effective compression ratio and decreased nominal compression ratio, with a highly turbulent mixture generated in the pre-chamber for quick ignition and fast burn, followed by combustion in the main chamber being characterized as a fast process based on a combination of air tumble, squish, mixing with the fuel and products of combustion exiting from the pre-chamber and burning quickly and efficiently by maintaining said prechamber products airborne while mixing and burning with the air in the main chamber. The process takes advantage of, and is based on, appropriate recesses incorporated in the piston which, apart from functioning as mini-combustion chambers, also provide for valve pockets to allow for the proper valve events and lifts without combustion or manufacturing compromises, and which contribute to an even thermal loading. Earlier intake closing and higher effective compression ratio allow the lowering of the nominal compression ratio which in turn allows for more volume in the pocket to keep the flame and the fuel-air mixture airborne. The combination of volumetric efficiencies and valve timings providing previously unheard of startability, smooth, quieter combustion and reduced firing pressures, even while producing increased power outputs, with lower fuel consumption, smoke, particulate and gaseous emissions than any previously known high speed, I.D.I. diesel engine.

Double overhead camshaft four valve diesel engine with side prechamber


A control system for a light-generating apparatus can include a control cyclically operating a switching element in series with the circuit including the apparatus's power source and light. Upon actuation of the apparatus's switch within a specified switching interval, the control shifts to a drift mode causing the circuit to automatically pass through consecutive excitation states such that the light passes through successive levels of preferably increasing intensity at a rate independent of the switching interval over an adjustment interval of momentarily indefinite duration. Another switch actuation shifts to set mode, which stops the light at a desired intensity. The drift and set operations are repeatable. An indicator preferably enables the operator to adjust the light's intensity based on the available remaining life of the power source as differently determined for each different intensity. To facilitate interchangeability between differently sized apparatus, the control's housing can include an adjustable spacing element.

The present invention relates to a system for controlling a light-generating apparatus. The light-generating apparatus envisioned includes a circuit having a power source and a light. For example, the apparatus may constitute an ordinary flashlight, the light may be the flashlight's bulb, and the power source may be one or more batteries removably inserted into the battery compartment of the flashlight.
A problem typically encountered with light-generating apparatus is that shortly after replenishment of the power source, the performance of the power source starts to degrade, and the intensity of the light quickly begins to dim to unacceptable levels. In the case of the ordinary incandescent flashlight bulb, for example, as described in Weber, U.S. Pat. No. 5,821,697 (the "Weber reference"), an objectionable "yellow" light begins to appear with merely a 10–20% decrease in battery voltage. Indeed, as Weber further points out, only a 7% drop in battery voltage causes the bulb to lose 20% of its light output. Broadhurst, U.S. Pat. No. 6,316,880 (the "Broadhurst reference"), suggests that this steep performance decline is an inherent characteristic of the tungsten filament used in incandescent bulbs, which act as a black body radiator producing light proportional to the fourth power of the filament temperature.
The filler gas used in the bulb also affects performance. As described, for example, in Salerno, U.S. Pat. No. 6,246,184 (the "Salerno reference"), a typical xenon-filled flashlight bulb loses 50% of its intensity with only a 20% drop in input voltage. The problem is even more severe with "Krypton" gas-filled bulbs that, as Weber points out, drain the battery relatively more rapidly. Aggravating this problem further is the performance of the typical dry-cell battery under load. As Weber describes, such a battery exhibits three pronounced performance regions: the first during the initial portion of operation where its internal impedance increases rapidly; the second during the middle portion where the internal impedance tends to level off; and the third during the final portion where the impedance again increases rapidly to the point where the battery has no further practical value. Accordingly, designers and operators have faced a trade-off between diminished lighting ability, with attendant frustration and risks, and premature replacement or replenishment of the batteries, with attendant inconvenience, inefficiency, and costs.
To address the foregoing problem, various mechanisms for stabilizing the lamp's intensity have been proposed. One frequently cited design is shown in Mallory, U.S. Pat. No. 4,499,525 (the "Mallory reference"). In the Mallory reference, a lamp of lower voltage rating replaces the lamp originally installed, and a switching element is inserted in the circuit between the power source and the light to enable pulsed operation of the circuit. As the battery voltage declines, this decline is detected through a feedback circuit, and the width of the pulses are increased so as to increase the duty cycle of the pulse train and automatically compensate for the declining voltage.
A related design is shown in Nilssen (FIG. 5), U.S. Pat. No. 5,498,934 (the "Nilssen reference"), where an integrated circuit (IC) performs the switching function and the duty cycle is varied from 100% (with the IC switched out of the circuit) to 50% as based on feedback provided from direct sensing of the light's intensity through a photodetector. A contrasting design is shown in the Weber reference in which, in order to reduce purported circuit inefficiencies and tolerance sensitivities, the switching element is replaced by an active element that continuously adjusts the current level in the circuit in noncyclical or linear fashion. In one variant described in The Weber reference, for example, the current flow is continuously adjusted through a MOSFET in response to changes in voltage detected across the lamp. The common theme in each of these approaches is self-regulation of the lamp's intensity by means of active feedback.
As disclosed in Schmidt et al., U.S. Pat. No. 6,040,660 (the "Schmidt reference"), control devices of the above type have been conveniently packaged in disk-like or flattened form with their external contact points arranged on opposite sides. This enables an existing flashlight or lantern to be retrofitted with the device by simply opening the battery compartment and inserting the device behind the batteries. The device can also be made to be inserted above the batteries in a position proximate the lamp in the manner suggested by the Salerno reference. Still another approach has been to embed the device in a battery of conventional size as suggested in Bruwer, U.S. Pat. No. 6,621,225 (the "Bruwer '225 reference").
After the light-generating apparatus has been initially switched on, some prior mechanisms provide for a dimming function. Here the intensity of the light is backed off or decreased from its fully lit level in order to provide for variable lighting and to conserve battery and lamp life. Typically, such dimming is controlled by a manual switch, that is, either the switch can be toggled from its normal position to a dimmed position, as indicated by Yee, U.S. Pat. No. 6,160,355 (the "Yee reference"), or the switch is of variable type providing a continuous range of dimming, that is, each different position of the switch corresponds to a unique dimming level, as shown in the Nilssen reference. The variable switch, from a circuit standpoint, represents a variable resistor, and this switch can either be integrated with the primary power switch, as Nilssen shows, or separately provided, as shown in the Broadhurst reference.
Yet another approach to implementing the dimming function is described in the Schmidt reference and the Bruwer '225 reference. Under this approach, after the circuit is initially switched to its fully on position, the primary switch is briefly actuated in accordance with a predefined sequence, such as being switched off and back on again within a predetermined "switch-over" time, to indicate a dimming operation is desired. The dimming interval is set to correspond either to the switch-over interval, that is normally extremely brief because of the need to maintain power to the lamp, or a predetermined time interval following the switch-over interval, in which case the dimming operation proceeds in stages, that is to say, in stepwise fashion. In the Schmidt reference, for example, the first switch actuation signaling dimming reduces the light intensity by 50%, whereas the second such actuation reduces the intensity by another 50% (to one-quarter of the original intensity). Under this approach, it will be noted that discrete switch actions result in discrete dimming operations. Although this approach does not require special modification of the switch, as is frequently the case with a variable switch, "fine-tuning" of the lamp's intensity in the manner offered by the variable switch is not provided.
Another function found in some prior mechanisms is an indicator that signals a weakened condition of the batteries. In the Weber reference and the Yee reference, for example, when the battery voltage reaches some fixed percentage of the rated voltage so as to establish the batteries are near exhaustion, either an indicator LED turns on or a supplemental battery is switched into the primary circuit.
In the Bruwer '225 reference, a "good" battery condition is indicated by an LED briefly flashing every 10 seconds or other interval. As Bruwer explains, this also assists the user in more easily finding the flashlight in the dark. Consistent with this, Bruwer describes how an internal energy storage element, such as a capacitor, can be charged by the battery during the off portion of each switch cycle, so that the switch control has a source of reserve power to continue switching operations even when the battery's available power is primarily being directed to the lamp. This type of intermittent flashing may be contrasted with a more regular flashing routine where, for example, the flashlight is flashed on and off every half second or so. Bruwer also discloses this other type of flashing routine for signaling distress or emergency, as do several others of the references above cited.

Light-generating apparatus control system


A slope sample value at a sample point on a target route and a distance sample value from a reference point on the target route to the sample point are calculated based on three-dimensional position data of the target route. Undetermined elements contained in a model formula for the approximation formula representing relation between the slope sample value and the distance sample value are determined using an error evaluation formula for the model formula. The error evaluation formula contains a slope error evaluation component for evaluating a slope error between the slope sample value and a slope model value that is calculated using the model formula, and an altitude error evaluation component for evaluating an altitude error between an altitude model value that is obtained through integration of the slope model value and an altitude value that is obtained from the three-dimensional position data.

In recent years, a mobile mapping system (MMS) has been increasingly used, which acquires three-dimensional point group information, such as a road surface and roadside equipment, simultaneously with traveling of a surveying vehicle. Note that, the surveying vehicle is equipped with surveying functions, such as a global positioning system (GPS) device, a laser radar, and a camera.
Acquired three-dimensional point group information as it is has a very large data volume, and thus processing of extracting only necessary pieces of information is performed. For example, as for an in-vehicle device, three-dimensional positions and three-dimensional shapes, such as a central position of a road (hereinafter also referred to as a "road center line"), a central position of each traffic lane on a road (hereinafter also referred to as a "traffic lane center line"), a sectioning line, and a traffic sign, are useful. Therefore, such pieces of information are extracted.
However, three-dimensional shape information such as the road center line may have a large data volume, necessitating a technology of compressing the three-dimensional shape information. As such a technology, there is known a technology of expressing the three-dimensional shape information using a function. For example, Patent Document 1 discloses a technology of expressing three-dimensional point group information using functions of an arc, a straight line, and a transition curve. The gist of the technology is as follows.
Firstly, a planar traveling locus, which is a locus in a horizontal plane, is generated from a three-dimensional traveling locus. Then, a control point of each curved part in the planar traveling locus is detected. The control point is a point of intersection between two straight parts set on both sides of the curved part. After that, a transition curve that smoothly connects to the arc and the straight part is detected. With this, the planar traveling locus is described using functions of the straight line, the arc, and the transition curve. Similar processing is performed also on a vertical traveling locus, which is a locus in a vertical plane.

Map data generation system and method for generating map data


In order to provide a semiconductor device of high reliability which suppresses a degradation of the fatigue strength of solder connection portions and warping of a tape-type wiring substrate forming the cause of the inferior contact between solder bumps and an external substrate, and a method of manufacturing the semiconductor device, a frame-like member is disposed on the inner peripheral part of the tape-type wiring substrate so as to relax constraint on the thermal deformation of the tape-type semiconductor substrate.

The present invention relates to a semiconductor device wherein wiring patterns to be electrically connected to the electrodes of a semiconductor chip or element are formed on a soft insulating substrate, and wherein external terminals made of solder bumps are connected to the wiring patterns.
In the future, it will be a requirement to increase the packaging densities of semiconductor crevices, to reduce the sizes thereof and to curtail the costs of their manufacture more and more. As a technique for coping with an increase in the number of external connection terminals attendant upon a higher packaging density of a semiconductor device, a semiconductor device having a ball grid array (hereinbelow, termed "BGA"), wherein a semiconductor chip is mounted on the front surface of a printed-wiring substrate and wherein metal bumps are arranged on the rear surface of the printed-wiring substrate, is disclosed in, for example, U.S. Pat. No. 5,216,278 (hereinbelow, referred to as "prior-art technique #1").
On the other hand, as a technique for attaining a reduced size and enhanced productivity of a semiconductor device, a tape carrier semiconductor device package (hereinbelow, termed "TCP"), wherein wiring patterns to be electrically connected to the electrodes of each semiconductor chip are formed on an insulating film and wherein the semiconductor chip is arranged in an opening formed in the insulating film, is disclosed in, for example, the official gazette of Japanese Patent Application Laid-open No. 251502/1993 (hereinbelow, referred to as "prior-art technique #2").
The prior-art technique #1 is effective as a technique which can cope with the increased number of external terminals ascribable to the higher packaging density, without enlarging the size of the semiconductor device. However, the productivity of this technique is not high, which forms a hindrance to the curtailment of the cost of manufacture of the semiconductor device.
On the other hand, the prior-art technique #2 can form semiconductor devices in succession on a long and narrow insulating film, and this technique is therefore capable of reducing the size of each semiconductor crevice and of curtailing the cost of manufacture thereof. Since, however, external terminals can be arranged only on the outer peripheral parts of the insulating film, this technique cannot be adopted for a semiconductor chip which has a large number of external terminals.
The inventors have therefore studied ways to simultaneously achieve a heightened packaging density, a reduced size and a curtailed cost of manufacture of a semiconductor device by replacing the printed-wiring substrate of the BGA (prior-art technique #1) with the insulating film (hereinbelow, termed "tape-type wiring substrate") of the TCP (prior-art technique #2).
In this regard, in the case where a semiconductor device was fabricated by replacing the printed-wiring substrate of the BGA with the tape-type wiring substrate of the TCP, both the degradation of the fatigue strength of solder connection portions, which were no serious problem in the BGA, and the warp of the tape-type wiring substrate, which were no serious problem in the TCP, appeared when the semiconductor device was mounted on an external substrate.
In general, the degradation of the fatigue strength of the solder connection portions shortens the lifetime of a semiconductor device, and the warp of a tape incurs inferior contact between solder bumps and an external substrate. Therefore, the reliability of semiconductor device fabricated in this way is very low.
An object of the present invention is to provide a semiconductor device of high reliability which suppresses the degradation of the fatigue strength of solder connection portions and the warp of a tape-type wiring substrate forming the cause of the inferior contact between solder bumps and an external substrate, and a method of manufacturing such a semiconductor device.
The inventors eagerly inquired into causes of a warp of a tape-type wiring substrate and degradation of the fatigue strength of solder connection portions when a semiconductor device employing the tape-type wiring substrate (hereinbelow, this device shall be termed a "tape-type BOA") was mounted on an external substrate. From this, it has been found that the cause is heating during the mounting operation.
Now, the mechanics which result in these drawbacks will be explained with reference to FIGS. 10 and 11. FIG. 10 is a sectional view showing the state in which a tape-type BGA in the prior art is mounted on an external substrate, while FIG. 11 is a model diagram for elucidating the mechanics which result in the warp of the tape-type wiring substrate of the tape-type BGA in the prior art. Fatigue fracture of Solder connection portions!
In case of mounting the tape-type BGA on the external substrate 8, as illustrated in FIG. 10, the BGA is tentatively fastened at a predetermined position on the external substrate 8, followed by heating the external substrate 8 and the tape-type BGA while they are fastened together. Herein, the solder balls melt due to the heating so as to mount the tape-type BGA on the external substrate 8.
After the mounting is complete, the external substrate 8 and the tape-type BGA are restored to a normal temperature. Since, however, the external substrate 8 and the tape-type BGA have different coefficients of thermal expansion, the magnitudes of their contractions consequently involve a difference, and the difference is directly borne by solder bumps 6 which intervene between the external substrate 8 and the tape-type BGA.
It is assumed by way of example that a soft insulating substrate serving as the basic material of the tape-type wiring substrate 2 is a polyimide tape. In this regard, there are various kinds of polyimide tapes which range from one exhibiting a coefficient of thermal expansion close to that of the external substrate 8, to one exhibiting a considerably smaller coefficient of thermal expansion. Irrespective of the coefficients of thermal expansion, however, the thermal deformation of the tape-type wiring substrate 2 is constrained by a semiconductor chip 1 in the solder connection portions nearest to the semiconductor chip 1, and hence, the difference in thermal expansion of the wiring substrate 2 with respect to the external substrate 8 becomes large, so as to incur the problem of degradation of the fatigue strength of the solder connection portions. Besides, with increase in the number of terminals of the semiconductor device, the size of the semiconductor chip 1 is further enlarged, and so the distance from the outer peripheral part of the semiconductor chip 1 to each of the solder connection portions becomes shorter, so that the burdens to be borne by the solder bumps 6 and the solder connection portions become increasingly heavier.
This phenomenon becomes especially conspicuous because the thermal deformation of the tape-type wiring substrate 2 is constrained by the semiconductor chip 1. It is accordingly advantageous for the solder bumps 6 to replace the sealing resin 4, which seals the inner leads 3 and the circuit surface of the semiconductor chip 1, with a resin of lower elasticity and higher thermal expansion than that in the TCP, so that the constraint of the thermal deformation of the tape-type wiring substrate 2 around the semiconductor chip 1 will be relaxed or relieved. To lower the elasticity of the sealing resin 4, however, signifies to decrease the filler content of the sealing resin 4, so that the moisture resistance of the resin becomes problematic in relation to the protection of the circuit surface of the semiconductor chip 1.
Warp of Tape-type wiring substrate!
The tape-type wiring substrate 2 is provided substantially centrally with respect to an opening in which the semiconductor device is accommodated. The semiconductor chip 1 is placed in the opening, whereupon the outer peripheral part of the semiconductor chip 1 and that of the opening are joined by the sealing resin 4.
As illustrated in FIG. 11, a difference of thermal deformations appears between the outer peripheral part of the tape-type wiring substrate 2 and the inner peripheral part thereof (i.e., the outer peripheral part of the opening) when the tape-type BGA is heated. The reason therefor is that the thermal deformation of the outer peripheral part of the tape-type wiring substrate 2 is produced in conformity with the coefficient of thermal expansion of this substrate 2 itself, whereas the thermal deformation of the inner peripheral part of the tape-type wiring substrate 2 is constrained by the semiconductor chip 1, because the semiconductor chip 1 is firmly fixed in the opening by the sealing resin 11. In this manner, the tape-type wiring substrate 2 is deformed more at the outer peripheral part thereof than at the inner peripheral part. Consequently, the warp in the vertical direction as viewed in the drawing appears at each outer peripheral corner of the tape-type wiring substrate 2. Further, the quantity of the warp is enlarged by the bimetal effect of the wiring patterns formed on the tape-type wiring substrate 2 or the solder resist (7 in FIG. 10) and a binder or adhesive.
The appearance of the warp of the tape-type wiring substrate 2 signifies that the heights of the solder bumps (6 in FIG. 10) change depending upon the positions thereof. When the magnitude of the change is large, some of the solder bumps fail to come into contact with the external substrate (8 in FIG. 10) in the mounting operation. With an increase in the number of the external terminals, the area of the tape-type wiring substrate 2 becomes larger, and the diameter of each of the solder bumps becomes smaller, so that the allowable value of the warp of the tape-type wiring substrate 2 becomes still smaller.
As thus far explained, it is a major cause for both the degradation of the fatigue strength of the solder bumps and the warp of the tape-type wiring substrate that the thermal deformation of the inner peripheral part of the tape-type wiring substrate is constrained. Accordingly, the object of the present invention can be accomplished by relaxing the constraint of the thermal deformation of the inner peripheral part of the tape-type wiring substrate.
As an expedient for relaxing the constraint of the thermal deformation of the inner peripheral part of the tape-type wiring substrate, according to the present invention, a frame-like member is joined to the inner peripheral part of the surface of the tape-type wiring substrate opposite to the surface thereof formed with the wiring patterns.
FIG. 3 graphically illustrates changes in the quantities of the warp of packages in the cases where tape-type wiring substrates are respectively provided with frame-like members, each having a rectangular section, each being made of copper, and each being formed into an inner shape which is substantially the same as the shape of an opening formed in the tape-type wiring substrate in order to accommodate a semiconductor chip, and into an outer shape whose contour lies at a position corresponding to the outermost peripheries of wiring patterns formed on the tape-type wiring substrate in order to locate solder bumps nearest to the semiconductor chip. The frame-like members mentioned above have heights (hereinbelow, termed "thicknesses") of 0.05 mm, 0.1 mm and 0.2 mm. The figure also illustrates changes in the case where a tape-type wiring substrate is not provided with any frame-like member, and in the case where a tape-type wiring substrate is provided on its whole surface with a frame-like member of copper having a thickness of 0.2 mm. It is understood from the figure that the frame-like member which has a thickness of 0.05 mm is not very effective to prevent warp because of a low rigidity, whereas the frame-like member whose thickness is 0.1-0.2 mm can diminish or relieve the warp. Besides, in the case where the whole surface of the tape-type wiring substrate is covered with a frame-like member having a thickness of 0.2 mm, a warp of large magnitude develops contrariwise due to the bimetal effect of the frame-like member and the tape-type wiring substrate. In order to suppress the warp by providing a frame-like member on the whole surface of a tape-type wiring substrate, the frame-like member must be thickened up to about 2 mm so as to constrain the deformation of the tape-type wiring substrate by virtue of the rigidity of the frame. With such a frame-like member of great thickness, however, it becomes impossible to achieve a thinning of the semiconductor package. Moreover, the weight of a semiconductor device increases, and in some packaged states of the semiconductor device, the solder bumps are burdened with excessive loads and might have their lifetime shortened.
Further, the inventors made a study on the thicknesses of the frame-like members. As a result, it has been revealed that, when the thickness is less than 0.1 mm, the effect of preventing the tape-type wiring substrate from warping cannot be expected due to a low rigidity, so the thickness needs to be at least 0.1 mm. On the other hand, it can be said that the thickness needs to be made at most 2 mm for the purposes of saving space and lightening loads on the solder bumps in the packaged state of the semiconductor device. Also, from the viewpoints of easy availability of material and the enhanced productivity of the frame-like member, it can be said that the thickness should desirably be greater than 0.1 mm and less than 0.3 mm.
Meanwhile, regarding the plane geometries of the frame-like member, like the experimental conditions in FIG. 3, the frame-like member is formed into an inner shape, which is substantially the same as the shape of an opening formed in the tape-type wiring substrate in order to accommodate a semiconductor chip, and into an outer shape, whose contour lies at a position corresponding to the outermost peripheries of wiring patterns formed on the tape-type wiring substrate in order to locate the solder bumps nearest to the semiconductor chip. Thus, the thermal deformations of those parts of the tape-type wiring substrate which lie just over the connection portions of the solder bumps nearest to the semiconductor chip can be caused to follow the thermal deformation of an external substrate. Therefore, the mitigation of the distortions of the solder bumps and the solder connection portions can be attained in addition to the diminution of the warp of the tape-type wiring substrate. By way of example, the plastic strain of lhe solder connection portions nearest to the semiconductor chip can be halved by employing a frame-like member of copper having a thickness of 0.2 mm.
Further, a study was made on the outward sizes of the frame-like members. As indicated in FIG. 3, in the case where a frame-like member having a thickness of 0.2 mm is provided on the whole surface of the tape-type wiring substrate, a warp of large magnitude appears due to the bimetal effect of the frame-like member and the tape-type wiring substrate. In contrast, in a case where the frame-like member is provided on a region which extends up to 4/5 of the full width of the tape-type wiring substrate from the outer peripheral part of the opening of the tape-type wiring substrate, the effect of preventing warp is observed.
This will come from the fact that the elongation magnitude of the frame-like member at the position of 4/5 of the full width of the tape-type wiring substrate from the outer peripheral part of the opening of the tape-type wiring substrate balances with the elongation magnitude of the insulating member itself.
When the outer peripheral part of the frame-like member exceeds 4/5 of the full width of the tape-type wiring substrate, the elongation magnitude of the frame-like member becomes larger than that of the insulating member itself, and hence, warp appears in the tape-type wiring substrate.
Regarding the properties of the frame, the coefficient of linear expansion of the frame should preferably be equal to or greater than the coefficient of linear expansion of the basic material (polyimide rape) of the tape-type wiring substrate and be close lo the coefficient of linear expansion of the external substrate made of glass epoxy. It is therefore effective to employ a copper-based or aluminum-based material. Even in case of employing an organic material such as resin, the material which has a high rigidity and which meets the above conditions of the coefficient of linear expansion is selected.
In a semiconductor device having a semiconductor chip, a soft insulating member, which is formed with wiring patterns on its surface and which is formed with an opening for inserting the semiconductor chip therein, and a sealing resin which seals a surface of the semiconductor chip formed with circuits and joined parts between the semiconductor chip and the insulating member, wherein solder bumps are connected as external terminals to the wiring patterns, the semiconductor device of the present invention is characterized by the following constructions:
(1) A frame-like member is provided on a surface of said insulating member opposite to the surface formed with said wiring patterns. PA1 (2) A sheet of a first frame-like member which is made of the same material as that of said wiring patterns is bonded on a surface of said insulating member opposite to the surface on which said wiring patterns are formed, the first frame-like member being formed into an inner shape thereof which is substantially equal to a shape of the opening of said insulating member, and into an outer shape thereof which is substantially equal to a shape of an outer peripheral part of said insulating member; and a second frame-like member is provided on the sheet, the second frame-like member being formed into an inner shape thereof which is substantially equal to the shape of said opening of said insulating member, and into an outer shape thereof which lies within a range of positions up to 4/5 of a width of said insulating member from a position corresponding to outermost peripheries of said wiring patterns for depositing the solder bumps nearest to said semiconductor chip, a thickness of said second frame-like member being set within a range of 0.1 mm to 2 mm, inclusive. PA1 (3) The solder bumps are arranged in regions which oppose respective sides of an outer periphery of said semiconductor chip. PA1 1) the step of providing an opening in said insulating member, thereafter bonding a sheet for said wiring patterns to said insulating member, and subsequently forming said wiring patterns from the sheet for said wiring patterns; PA1 2) the step of arranging said semiconductor chip in ,aid opening of said insulating member, and thereafter laying necessary wiring; PA1 3) the step of using a sealing resin to seal the surface of said semiconductor chip formed with the circuits and the joined parts between said semiconductor chip and said insulating member; and PA1 4) the step of bonding the frame-like member to a desired position of said insulating member.
Polyimide is usually employed as the material of the insulating member. Besides, the wiring patterns are usually made of copper, but they may well be made of gold, silver or aluminum or this material plated with nickel. Regarding the properties of the frame-like member, the coefficient of linear expansion of the frame-like member should preferably be equal to or greater than the coefficient of linear expansion of the basic material (polyimide tape) of the tape-type wiring substrate and be close to the coefficient of linear expansion of an external substrate made of glass epoxy. It is therefore effective to employ a copper-based or aluminum-based material for the frame-like member. Even in case of employing an organic material, such as resin for the frame-like member, a material which has a high rigidity and which has a coefficient of linear expansion equal to or greater than the coefficient of linear expansion of the basic material (polyimide tape) of the tape-type wiring substrate is selected.
Owing to the provision of the frame-like member, it is possible to suppress the warping of the tape-type wiring substrate and to prevent the degradation of the fatigue strength of the solder bumps.
Further, the frame-like member becomes more effective in such a way that the contour of the inner shape thereof is made substantially the same as the outer peripheral part of the opening of the insulating substrate, while the contour of the outer shape thereof is located within the range of positions up to 4/5 of the width of the insulating substrate from a position corresponding to the outermost peripheries of the wiring patterns for depositing the solder bumps nearest to the semiconductor chip, and that the thickness thereof is set within the range of 0.1 mm to 2 mm, inclusive.
Besides, from the viewpoints of easy availability of the material and enhanced productivity of the frame-like member, it can be said that the thickness of the frame-like member should more desirably be greater than 0.1 mm and less than 0.3 mm.
Incidentally, the "width of the insulating substrate" mentioned here designates the distance between one latus of the outer peripheral part of the semiconductor chip and that latus of the outer peripheral part of the tape-type wiring substrate which confronts the former latus.
Owing to this construction, the sheet of the same material as that of the wiring patterns is provided on the whole area of the surface of the tape-type wiring substrate opposite to the surface thereof on which the wiring patterns are formed, so that a warp which is ascribable to the bimetal effect of the wiring substrate and the wiring patterns can be prevented. Furthermore, a warp which is ascribable to the difference between the coefficients of expansions can be diminished by the frame-like member.
Besides, in a case where the first frame-like member and the second frame-like member are unitarily constructed, the number of fabricating steps of the frame-like member increases, but a single bonding operation suffices, so that the productivity of the semiconductor device the time of assembly rises.
Owing to this construction, no solder ball is arranged in any of the regions of corners in which the magnitudes of the warps of the tape-type wiring substrate become the largest during heating during the manufacture of the semiconductor device. Therefore, the connection reliability of a soldering operation is sharply improved.
In a method of manufacturing a semiconductor device having a semiconductor chip, a soft insulating member which is formed with wiring patterns on its surface and which is formed with an opening for inserting the semiconductor chip therein, and a sealing resin which seals a surface of the semiconductor chip on which circuits are formed and joined parts between the semiconductor chip and the insulating member, wherein solder bumps are connected as external terminals to the wiring patterns, and a frame-like member is provided on a surface of the insulating member opposite to the surface on which the wiring patterns are formed, the method of manufacturing a semiconductor device according to the present invention is characterized by:
Owing to these steps, the warp of the tape-type wiring substrate is diminished, and the degradation of the fatigue strength of the solder bumps can be suppressed.
Incidentally, in a case where the step 4) precedes the step 2), the frame-like member can be bonded before the sealing resin adheres around the opening of the tape-type wiring substrate. Therefore, the inner shape of the frame-like member can be made the same as the shape of the opening of the tape-type wiring substrate. Thus, warping of the tape-type wiring substrate can be prevented, and the degradation of the fatigue strength of the solder bumps can be suppressed.