An information processing apparatus that provides content information, a control method thereof, and a computer program. In a case where a predetermined condition regarding a request of access such as capacity for a communication band and a number of requests of access is satisfied when requests of direct or indirect access to content information associated with a first user from information terminal apparatuses of a plurality of second users are received, the information processing apparatus controls provision of information to each of the information terminal apparatuses on a basis of priority set for each information terminal apparatus.

The technology is known that allows a user to access a sight (scene from a mobile object other than the user) from a person or an object other than the user.
For example, there has been proposed a mobile camera system that remotely acquires an image captured by a mobile camera mounted on a mobile object such as a vehicle (e.g., see Patent Literature 1). In addition, there has been proposed an image processing system that provides a person who wears a head-mounted display with information similar to visual information acquired by a person who wears eyeglasses in which an imaging sensing wireless apparatus is disposed (e.g., see Patent Literature 2). In addition, there has been proposed an image display system in which a display apparatus side that displays a captured image of a mobile object designates, for an imaging apparatus of the mobile body, a viewpoint position and a line-of-sight direction for performing imaging, and speed at the time of imaging (e.g., see Patent Literature 3).
Further, the telepresence technology has also been proposed that transmits, through an interval such as the sight of a robot in a remote location, a sensation that a person feels as if the person were on the spot, and provides an interface for operating an object in the remote location (e.g., see Patent Literature 4).

Information processing apparatus, control method thereof, and computer readable medium for visual information sharing


A wheel dolly for moving truck tires and drums to and from a wheel on a truck has an elongated frame for disposition on a base surface oriented in substantial axial alignment with the wheel of a vehicle. The frame has a pair of elongated and parallel spaced cylindrical members formed of sections which have telescoping adjacent ends. End braces extend across and are secured to the opposite ends of the cylindrical members. A carrier is slidably seated on the cylindrical members for movement therealong, and it has a planar central portion and angular portions depending therefrom outwardly of the frame to provide ramp surfaces. The carrier also has rollers supported on the lower surface of the central portion which are configured to seat on the cylindrical members.

The present invention relates to movable carriers for tires, and, more particularly, to a dolly for moving truck tires and drums relative to the wheel of a tractor or cab.
In order to effect repairs on brakes of a truck or to perform other repairs involving the wheels of the truck, it is necessary to remove the tires and drums which are both heavy and cumbersome. The problem is particularly acute in the instance of double tires which are utilized in large trailers for carrying substantial loads.
A number of handling devices have been proposed to facilitate the movement of the tires inwardly and outwardly of the wheel, namely those shown in Gentry Pat. No. 2,246,882, Hennings et al Pat. No. 2,525,351, Sagen Pat. No. 2,539,274 and Crow Pat. No. 2,659,717. These devices are generally heavy and cumbersome and do not readily lend themselves to use in the field. Some do not readily lend themselves to placement on uneven surfaces, and most are not conveniently transportable.
It is an object of the present invention to provide a novel wheel dolly for moving the tires and drums relative to the truck wheel.
It is also an object to provide such a wheel dolly which can be readily disassembled to facilitate storage for transport to a location where needed.
Another object is to provide such a wheel dolly which can be readily fabricated from easily available components to provide a long lived structure enabling facile movement of the truck tires inwardly and outwardly of the wheel.


This disclosure relates to a method, and a network node for determining a charging of a battery of a user device. Network traffic of the user device is monitored, where the network traffic comprises network traffic of an application and/or a service of the user device. A network traffic pattern is identified for the monitored network traffic and a battery-charging event is detected based on the identified network traffic pattern. Charging of the battery is determined of the user device, based on the detected battery-charging event. These features and operations offer a number of advantages. For example, they allow a network operator to implement detection of battery-charging events using the operator's current network setup, because the teachings herein require no changes to existing network deployments, nor are additional protocols needed.

Smartphones of today typically comprise a fast central processing unit (CPU), a large display and a fast access to a network such as Internet, and therefore often consume considerable amounts of energy.
Battery consumption can be reduced by focusing on user device-related network behavior optimization. This can only be achieved with some compromise on quality of experience e.g., the user has to switch to a lower performance channel or periodically switch off the radio unit to spare energy.
Moreover, optimization for the battery has paramount importance if the battery is close to getting depleted. For this reason it would be useful to have access to charging information of the UE and to take into account a battery status at optimization decisions.
From Zhang, et al., "Accurate online power estimation and automatic battery behavior based model generation for smartphones" in 2010 IEEE/ACM/IFIP International conference on Hardware/Software Co-design and System Synthesis, an automated power model construction technique using built-in battery voltage sensors and knowledge of battery discharge behavior to monitor power consumption, is known. This technique does not require external measurement equipment. A second component of this method applies the constructed power models for online power estimation. This method is totally terminal based, as it collects data locally, creates power models locally and utilizes them locally.
There is a need for information about charging of a user device without the need to install software components on the user devices.

Method and arrangement for determining a charging of a battery of a user device


An antenna device of the type including an array antenna comprised of a plurality of planar antenna elements, wherein the planar antenna elements are arranged in a staggered pattern such that two adjacent ones of the antenna elements are disposed diagonally with each other. With this staggered arrangement, the spacing between the adjacent antenna element becomes larger than that in a conventional matrix arrangement, whereby the interference between the adjacent planar antenna elements is considerably reduced, while the antenna efficiency of the planar antenna elements is improved.

1. Field of the Invention
The present invention relates generally to an antenna device having an array antenna comprised of a plurality planar antennas, and more particularly to such an antenna device having a high antenna efficiency.
2. Description of the Related Art
Japanese Patent Laid-open Publication No. HEI 8-97620 discloses a multiple-beam planar array antenna comprised of a plurality of patch antennas (planar antennas) arranged over one surface of a dielectric substrate, a feeder part or unit, and feeder lines connecting the feeder unit and the individual patches antennas. The patch antennas are arranged so as to form a plurality of antenna parts each of which radiates beams of different tilt angles that are determined depending on the differences in length of the feeder lines connected to the individual patch antennas. The feeder lines are provided with a feed selecting means for selectively starting and stopping the feed of radio frequency energy to each of the antenna parts. The feed selecting means is composed of a plurality of selectively switchable PIN diodes.
In the disclosed antenna device, however, since the patch antennas (planar antennas) are arranged in the form of a matrix or rectangular array, the adjacent planar antennas tend to cause interference during transmission and reception of electromagnetic waves, thereby lowering the antenna efficiency (radiating efficiency) of the antenna device.


A degradable ball sealer for use in the oil and gas industry is disclosed. The ball seat comprises a particular composition of matter and injection molding technique that provides a ball seal which will dissolve in stimulation or wellbore fluids after stimulation operations are complete. In use, the surface of the ball sealer softens slightly assuring a solid seal between the ball the and the casing perforation. The composition when dissolved into wellbore fluids does not pose a hazard and disperses well in aqueous based wellbore fluids. The same composition, made into a larger ball, may be used as a tubing sealer for pressure testing.

Produced fluids (fluids are defined as liquids and gases) coming from a wellbore in the oil and gas industry are drawn from subterranean formations. The formation itself tends to restrict the flow of its own fluids, and the industry has defined a parameter which measures the tendency of fluids to flow under unequal pressure within a formation called permeability. Thus, the industry is interested in the permeability of a producing formation and employs techniques to maximize the permeability. There are several factors which affect the permeability of the formation which includes the effect of pores (the interstitial structure of the formation--namely voids, holes and other spaces), the effect of other fluids within the formation, and the effect of pore throats. Pore throats are essentially small pores within the formation.
After the actual drilling of a wellbore is complete, and if the well is successful, the industry performs an operation called completion. Completion is a series of involved operations and includes casing of the wellbore (running a steel tube from basically the bottom of the wellbore to the surface), cementing the casing in place within the wellbore (this operation fills voids between the steel casing and the formation strata and assures that one or more zones will not be in direct communication except through casing perforations), explosive perforation of the casing (punching holes through the steel tube and cement into the subterranean formation at the points where produced fluids are located), followed by cleaning and stimulation of the particular producing formation or formations.
Perforation involves the controlled explosive release of gases which are designed to penetrate the casing, penetrate any cement, and penetrate the subterranean formation immediately to next to the casing. The penetration into the formation is dependent on the size of the charge, the type of formation (sand, sandstone, etc.), the size and thickness of the casing, and myriad other parameters; thus, the perforation extending from the casing into the formation ranges from a couple of inches to several feet. The term "perforation " as used in the industry generally refers to the holes punched in the casing. It is assumed that the perforation operation will "punch" circular holes through the casing and cement into the formation. Most of the time this assumption is true; however, perforations can be irregular in shape.
After the perforation operation is complete, and as part of well completion the wellbore and the producing formation (or formations, in the case of multiple zones) must be cleaned and prepared for production. This series of operations are designed to remove remaining wellbore cuttings (the ground formation strata due to the drilling operation), remaining drilling fluids which are trapped behind the casing and in the production zone or zones, and stimulate the production by increasing the permeability. These operations are run from the surface and involve pumping various fluids, including acids, surfactants and other stimulation and cleaning fluids, down the wellbore into the production formation. The fluids will pass through perforations in the casing and into the formation. After a period of time, pressures are reduced so that the fluid will back-flow and draw impurities back into the wellbore and up to the surface. Sometimes the operator must pressure stimulate the producing zone (or zones) which requires pumping a fluid such as an acid, liquefied gas, a sand slurry, a viscous liquid, or another liquid into the wellbore under high pressure. The high pressure fluid flows through the casing and cement perforations and into the formation where the high pressure causes the formation to crack or fracture; hence, the name fracturing is used to describe this operation.
There is one substantial drawback in the initial cleaning and stimulation operations. The fluids will readily flow through the casing perforations and into the formation wherever the formation permeability is high. Thus, wherever the permeability is low, and treatment is a necessity, cleaning and stimulation fluids will not penetrate and extra pressure will be required to force the fluids into the formation. This extra pressure will in turn force additional fluids into zones which already have high permeability and could damage those zones by fracturing them. In the case of acid fracturing (a high pressure operation) the possibility of damage to production formation is substantially increased. Thus, a method for diverting, controlling or directing the flow of stimulation or cleaning fluids into the formation through casing perforations is required.
After the wellbore is placed in service and as the produced fluids flow through the formation, the produced fluids draw other materials along which often precipitate out (or just drop out) of the fluid. These materials will block the pores; thus, decreasing the permeability over time.
After a period of time, the operator of the wellbore must return to the site and retreat the formation to improve the permeability. These secondary stimulation treatments are similar to the initial treatments and generally include acids and surfactants, both of which are pumped into the wellbore and into the formation. During these secondary treatment operations, the areas of the formation where the permeability has decreased should be treated. Unfortunately, the treating fluids will flow most readily into the formation with the highest permeability--namely where the fluids are not needed, which is the same problem encountered during the initial treatment. In limited cases fracturing is again used and the danger of formation damage reappears. Thus, it is desirable to control or divert fluid flow into the regions with high permeability while forcing the fluids into regions of low permeability.
The industry has developed a product and method to control and direct treatment fluids through casing perforations and into the production zone or zones. The product is called a ball sealer: in reality a series of ball sealers which are capable of plugging the casing perforations. The ball sealers are slightly larger than the casing perforation and are capable of shutting off fluid flow through the casing perforation if and when they fall in front of a perforation. (The art is placing the sealers in the wellbore so that they will seal a perforation at the right time.) The associated method involves pumping the ball sealers into the wellbore along with the treatment fluids in an orderly manner so that they plug the offending perforation at the right time.
The standard method of use requires that the ball sealers be staged in the stimulation fluid as it is pumped into the wellbore. For example, assume that a simulation treatment requires 24 barrels (1,000 gallons) of fluid, and it is known that there are 24 perforations in the wellbore; thus 48 balls will be required. (The operator generally doubles the number of perforations to determine the number of balls.) In this example, the operator would release one ball for each one-half barrel pumped into the wellbore. This will help assure that each perforation is treated with an adequate amount of stimulation fluid before the next ball contacts the next perforation sealing it prior to increased fluid pressure breaking down (opening up) the next unsealed perforation and treating the formation associated with that perforation. The sequence of seal a perforation, treat the next, seal that perforation, treat the next, etc. continues until all the perforations have been ideally treated. At the surface, the operator will note a slight increase in pressure as one perforation is sealed and until the next formation opens up under pressure with an associated pressure decrease. The actual order of perforation treatment will not be from bottom to top, but will be associated with the order in which a given formation associated with a given perforation opens up. Ideally, at the end of the operation, all perforations seal and a sharp pressure increase is seen at the surface: this phenomena is called "balling out" and indicates that all perforations have been treated.
Once the initial or secondary operations are complete, the ball sealers fall away from the perforations (due to flow from the formation into the wellbore) and generally remain in the wellbore where they become a nuisance and present operational problems. Most wellbores contain a `rat hole` which is an extension of the wellbore below the lower casing perforation about 20 plus feet in depth. (In some wellbores this rat hole can become filled with debris and no longer exists.) The balls fall into the rat hole, where, under some circumstances one may be picked up by the motion of the produced fluid and carried to surface. At the surface a renegade ball can plug the surface production valves creating a safety hazard. Some operators will place "ball catchers" at the surface to avoid this problem. Often the wellbore operator must reenter the hole with drilling tools and the excess balls surround the drilling pipe or downhole tools jamming the pipe or tools in the wellbore. This results in an expensive "fishing" operation to retrieve the jammed tools.

Injection molded degradable casing perforation ball sealers


Part of light emitted downward by an active layer is reflected by an electrode functioning as a reflective layer, and travels upward to radiate outside. Since the electrode is made of a metal, it reflects almost all light regardless of its incident angle, and light can be efficiently extracted.

The present invention relates to a semiconductor light-emitting element.
In recent years, semiconductor light-emitting elements are widely used in an outdoor display, automobile indicator, and the like. The semiconductor light-emitting element is a device using emission recombination of electrons and holes injected in a p-n junction region. Emission ranging from infrared radiation to ultraviolet radiation can be realized by changing the semiconductor material of a light-emitting layer.
FIG. 30 shows the structure of a conventional semiconductor light-emitting element. An n-type GaAs buffer layer 3202, an n-type DBR (Distributed Bragg Reflector) reflective layer 3203 made of InGaAlP and GaAs to reflect light using the Bragg reflection effect, an n-type InGaAlP cladding layer 3204, an active layer 3205, a p-type InGaAlP cladding layer 3206, a p-type AlGaAs window layer 3207, and a p-type GaAs contact layer 3208 are sequentially formed on the upper surface of an n-type GaAs substrate 3201.
An n-type electrode 3209 is formed on the lower surface of the n-type GaAs substrate 3201, and a p-type electrode 3210 is formed on the p-type GaAs contact layer 3208. Power is supplied to the light-emitting element to emit light from the active layer 3205. Light emitted downward in FIG. 30 by the active layer 3205 is reflected by the reflective layer 3203, and radiated to above the element via the window layer 3207 together with the light emitted upward.
The conventional semiconductor light-emitting element suffers the following problem.
Part of light that is emitted downward by the active layer 3205 and travels straight toward the reflective layer 3203 is reflected by the reflective layer 3203 without being absorbed by the substrate 3201, and can be effectively extracted outside.
However, the reflective layer 3203 exhibits a very low reflectivity with respect to light traveling diagonally toward the reflective layer 3203, so not all the light from the active layer 3205 can be extracted outside.
The semiconductor light-emitting element absorbs light by a substrate which provides a critical angle defined by the difference in refractive index between the semiconductor crystal and the atmosphere or enables crystal growth. For this reason, light which can be extracted outside is only several % of internally emitted light.
FIG. 26 shows the structure of another semiconductor light-emitting element relating to the present invention.
A multilayered reflective film 1001, p-type contact layer 1002, p-type cladding layer 1003, active layer 1004 functioning as a light-emitting layer, n-type cladding layer 1005, and n-type contact layer 1006 are formed on a p-type semiconductor substrate 1000. An n-type electrode 1007 is formed on the contact layer 1002, whereas a p-type electrode 1008 is formed on the contact layer 1006.
Part of light emitted by the active layer 1004 that travels toward the n-type cladding layer 1005 is extracted outside via the cladding layer 1005.
Light that travels toward the p-type cladding layer 1003 is reflected by the multilayered reflective film 1001, and extracted outside via the n-type cladding layer 1005.
In this structure, light emitted toward the substrate 1000 can be reflected by the reflective film 1001, and extracted outside.
However, the reflectivity of light which is not vertically incident on the reflective film 1001 is low, the electrodes 1007 and 1008 which shield light exist on the light extraction surface, and the active layer 1004 is formed on the reflective film 1001. This results in low crystallinity and short service life.
FIG. 27 shows still another semiconductor light-emitting element relating to the present invention. An n-type InGaP buffer layer 1102, n-type InAlP cladding layer 1103, InGaAlP active layer 1104 functioning as a light-emitting layer, p-type InAlP cladding layer 1105, and p-type GaAs contact layer 1106 are formed on the upper surface of an n-type GaP substrate 1101. A p-type electrode 1107 is formed on the p-type GaAs contact layer 1106, while an n-type electrode 1100 is formed on the lower surface of the substrate 1101.
Light emitted by the InGaAlP active layer 1104 is reflected by the n- and p-type electrodes 1100 and 1107, and extracted outside from a region of the contact layer 1106 which is not shielded by the p-type electrode 1107.
In this structure, however, light concentrated immediately below the electrode 1107 is shielded by the electrode 1107, and cannot be extracted outside.
In the element shown in FIG. 27, only several % of light emitted by the active layer 1104 can be extracted outside owing to the difference in refractive index between the crystal and the air.
As the semiconductor light-emitting element, a compound semiconductor light-emitting element using a GaAs-based semiconductor material is adopted to emit light ranging from red to green, and a gallium nitride-based compound semiconductor light-emitting element using Al(x)Ga(y)In(1−x−y)N (0≦x, y≦1, x+y≦1) is adopted to emit light from the ultraviolet range to the blue/green range.
However, the refractive indices of these light-emitting elements are high (GaN=2.67, GaAs=3.62), their critical angles are small (GaN=21.9°, GaAs=16.0°), and thus their light extraction efficiencies are low.
The GaAs system exhibits large light absorption on the substrate. Emitted light is absorbed by the substrate to decrease the light extraction efficiency.
FIG. 29 shows still another semiconductor light-emitting element relating to the present invention.
An n-type GaAs buffer layer 1301, n-type InGaAlP cladding layer 1302, InGaAlP active layer 1303, p-type InGaAlP cladding layer 1304, and p-type AlGaAs current diffusion layer 1305 are sequentially grown on the upper surface of an n-type GaAs substrate 1300. A p-side electrode pad 1307 is formed on the p-type AlGaAs current diffusion layer 1305, whereas an n-side electrode 1306 is formed on the lower surface of the n-type GaAs substrate 1300.
In this structure, a current flowing from the p-side electrode 1307 is widened by the p-type AlGaAs current diffusion layer 1305, and injected from the p-type InGaAlP cladding layer 1304 to the InGaAlP active layer 1303. The light is extracted outside the element via the p-type AlGaAs current diffusion layer 1305.
In the GaAs-based compound semiconductor light-emitting element having this structure, part of light emitted by the active layer 1303 that travels toward the substrate 1300 is absorbed by the substrate 1300, and cannot be extracted outside the element. More specifically, 50% of the emitted light cannot be extracted, which is fatal to high luminance.
As described above, the elements relating to the present invention suffer low light extraction efficiency.


A method (FIG. 11) and corresponding wireless communication unit (102, FIG. 5) and mobility manager (116, FIG. 6) for facilitating a handover from one communication network (106) to another communication network (108) of an ongoing communication (120, 122) between a wireless communication unit (102) and a peer communication unit (114, 714). The method including obtaining call information (1103) corresponding to the ongoing communication where the ongoing communication uses the first communication network; and ascertaining a handover number (1105) for use by the wireless communication unit to originate a handover call (1107) via the second network (108), the handover number terminating within the first communication network for use in facilitating the handover of the ongoing communication to the second communication network.

Wireless Local Area Networks (WLANs) are being contemplated or are known. Such WLANs are typically supported by WLAN servers, which may alternatively be referred to as private branch exchanges (PBXs) or enterprise servers. The PBX normally provides a control and switching function for the WLAN and communication units operating therein or users thereof. The WLAN can be an attractive and inexpensive alternative for typical voice services such as telephony or dispatch services and may provide additional amenities such as high-speed wireless Internet and Intranet access as well as other real-time applications that may be more specific to a given enterprise.
Wireless wide area networks (wireless WANs or WANs) such as conventional cellular telephone systems are also known. Such networks provide the advantage of wide area coverage but may not be economically attractive for routine access to wideband or high speed data capabilities, such as are required for certain Internet or Intranet applications. Nevertheless a communication unit that is operating on a WLAN may move beyond the effective service area for the WLAN and thus need support or services from a WAN. In situations, sometimes referred to as loosely coupled systems, where the WAN is essentially not aware of the WLAN or communication unit operating thereon this can present problems, particularly for ongoing communication and handoffs or handovers thereof.
Therefore, a need exists for methods and apparatus to support handovers or handoffs between a first and a second communication network


An encoding preprocessing part 1 extracts the amount of image feature relative to image data and passes the amount of image feature to a control part 2 as image feature amount information 11 and also sends image data 10 to an encoding part 3. The control part 2 determines whether there is a dissolve image or not based on the image feature amount information 11 and if it is determined that the image data 10 is the dissolve image, an encoding parameter 12 is set so that a configuration of GOP which is normally M=3 is changed into the configuration of GOP of M=2, and the encoding part 3 performs encoding based on the encoding parameter 12. As a result of that, a prediction error of a B-picture frame in a dissolve interval becomes substantially zero and on encoding in the dissolve interval, the amount of information occurrence in frames except I-picture and P-picture frames can be reduced and thus the amount of information occurrence as a whole can be reduced.

1. Field of the Invention
The present invention relates to a moving image encoding apparatus and a moving image encoding method of performing inter-frame encoding of moving images by encoding techniques such as MPEG2.
2. Description of the Related Art
In conventional moving image encoding, MPEG2 etc. are used, and respective pictures are encoded by any of an I-picture for encoding only a frame, a P-picture for encoding the difference between a frame and a reference image using the past frame already encoded on a time basis as the reference image, and a B-picture for encoding the difference between a frame and a reference image using average values of the past frames already encoded on a time basis, the future frames or the past and future frames as the reference image. What these plural pictures are combined is defined as GOP and the number of frames constructing the GOP is indicated by N. Also, a distance between the I-picture and the neighboring P-picture of the GOP is denoted by M, and a configuration of the GOP is represented by the N and M and a distance between the nearest neighboring two P-pictures is also M.
FIG. 8 shows an example of the GOP configuration for N=15 and M=3.
In FIG. 8, images are arranged in the sequence of a frame 201, a frame 202, a frame 203, . . . , a frame 215 in order of time. Encoding first starts with the frame 203 which is the I-picture and next, the B-picture frames of the frame 201 and the frame 202 which are a frame older than the I-picture on a time basis are encoded. Then, the P-picture of the frame 206 after three pictures from the I-picture is encoded, and encoding is performed in the sequence of the frame 204 and the frame 205 which are two B-picture frames present between the I-picture and the P-picture. In like manner below, the P-picture after three pictures is encoded before encoding two B-pictures sandwiched between the I-pictures or the P-pictures, so that encoding is performed in the sequence of the frame 209, the frame 207, the frame 208, the frame 212, the frame 210, the frame 211, the frame 215, the frame 213 and the frame 214.
However, when predictive encoding of moving images is performed, an inter-frame prediction error may increase for some frames and thus, there was a problem that the amount of information occurrence in the case of prediction error encoding becomes large and degradation in image quality is caused.
Particularly, in the case of an image for making a special change in which special video processing is performed as a dissolve image, unlike motion of an object or pan of a camera, motion compensation prediction does not fall and the prediction is difficult, so that a prediction error signal might increase. As a result of that, when predictive encoding of the image for making a special change was performed, the amount of information occurrence became large and degradation in image quality was caused.

Moving image encoding apparatus and moving image encoding method


A tie rod suitable for use with known concrete forming systems is constructed from a non-metal fiber, such as fiberglass, that is wound about a pair of opposed thimble elements. The resultant tie rod is as strong as a metal tie rod without the drawbacks of conventional metal tie rods. Each of the thimble elements has a main body having a channel formed in an outer surface of the main body, and the fiberglass fiber is disposed within the channel when wound thereabout.

Conventional concrete walls may be created by pouring concrete into a suitable concrete form. As is known in the art, concrete foundation walls are generally poured between two sets of concrete forms disposed in essentially parallel relationship and defining therebetween a channel having a dimension for the desired thickness of the concrete wall. Such opposed, spaced apart walls are generally held in a fixed relationship relative to each other against the immense weight of any poured concrete by tie-wires and turnbuckle assemblies having abutment surfaces against which a locking or latching arm on adjacent form sections abut. Once assembled into the shape of the wall, wet concrete is poured into the channel formed between the concrete forms and allowed to dry. The concrete forms typically comprise multiple form panels, which may for example be formed of wood, metal or any other suitable well known material. The height of the form panel may vary by application.
Multiple form panels may be placed side-by-side in order to construct a wall of a desired length. Because the wet poured concrete takes the shape of the forms in which it is placed, the finished concrete wall corresponds in configuration to the assembled form. Therefore, it is important to align precisely the panels composing the concrete form in order to ensure that the finished wall has the desired appearance and strength.
The concrete forming systems can also employ tie-rods that are disposed between aligned panels in order to keep the panels properly spaced apart and to ensure that the panels are coupled to each other in a secure manner. The tie rods extend through openings formed in the spaced apart form panels and hold the sections against relative movement toward each other. The tie-rods may extend outwardly of the sections by a selected amount as is known in the art. The portion of the tie-rods that extend beyond the panel forms typically include a flattened or coined section that is adapted to engage with the latch that is coupled to the panel bar. Once the concrete is poured between the panel forms and allowed to cure, the portion of the tie rods that extend beyond the concrete walls can be snapped off.
Conventional tie rods are typically formed of metal, such as steel. However, the prior art has also designed systems that employ fiberglass ties in the shape of linear rods. The fiberglass tie rods are typically formed of fiberglass fibers that are all essentially disposed parallel to each other and hence extend in a longitudinal direction. The rods can be coupled to the concrete forms according to known techniques. According to a first known system and method, the fiberglass tie rods can have a thread formed thereon so as to accept a corresponding fastening nut. A drawback of these types of rods is that it is expensive to grind the threads into the finished rod, and the fastening nuts can be difficult to attach at times.
According to another known system and method, the fiberglass rod can be secured to the form panels using complex and expensive fastening hardware. The hardware can include a bearing plate, a tensioning nut, and a barrel and jaw assembly that employs a wedge shaped gripper to grip the exposed end of the tie rod. A drawback of this type of hardware is that it is expensive, labor intensive, prone to rusting, and over time can be difficult to use. Further, the hardware when removed typically needs to be cleaned and maintained in order to remove excess concrete therefrom.
Another form of non-metallic tie used a fiberglass strip similar in form to conventional metal flat ties. However, a drawback of ties of this type are that they are significantly lower in strength relative to conventional metal ties, and leaves a larger exposed end in the face of the wall when the exposed portion of the tie is removed. Further, these types of ties have poor water sealing capabilities and make it difficult to user a water stopping element, such as round rubber washer.

This patent is subject to a terminal disclaimer.

Loop tie for concrete forming panel systems


A fabric has an upper layer and a lower layer. The lower layer connects partially to the upper layer to integrally form multiple connecting segments formed on the upper layer and the lower layer. The at least one channel is formed on the upper layer and the lower layer and is formed respectively between adjacent connecting segments. The fabric is produced by a sewing step and a connecting step. The sewing step comprises sewing multiple raw fibers to respectively form the upper layer and the lower layer. The connecting step comprises connecting partially the upper layer to the lower layer by fiber to integrally form the connecting segments and the at least one channel. Thus, time and a cost of a production of the fabric can be reduced to relieve customers' burdens.

1. Field of Invention
The present invention relates to a fabric, and more particularly to a fabric that has at least one channel formed integrally with the fabric to reduce a cost of the fabric.
2. Description of the Related Art
A normal sewing machine can produce only a piece of fabric. However, the fabric such as a bra may be thickened partially to make people comfortable when they wear the fabric.
A conventional fabric with at least one channel is formed by following three steps:
(1) multiple upper layers and multiple lowers layer are formed respectively;
(2) a normal sewing machine is used to sew some of the upper layers respectively on some of the lower layers to form multiple connecting segments;
(3) a double needle bar warp knitting machine for simplex fiber is used to sew remains of the upper layers and remains of the lower layers to form at least one single channel; and
(4) the at least one channel is sewed respectively between the connecting segments to form the fabric with multiple channels.
Each of the at least one channel may be filled with fillers to partially thicken the fabric. However, the conventional fabric with the at least one channel is formed by complex procedure that wastes time. Thus, a cost of the fabric with the at least one channel will increase and customers have to pay more to get the fabric.
To overcome the shortcomings, the present invention provides a fabric to mitigate or obviate the aforementioned.


A process of forming an electronic device is disclosed. An organic device layer is formed. The organic device layer includes a charge-selective material and a radiation sensitizer and has a first electrical conductivity and a first surface energy. First portions of the organic device layer are selectively exposed to radiation. The electrical conductivity and surface energy of the first portions of the organic device layer are modified.

1. Field of the Disclosure
This disclosure relates in general to processes for forming organic electronic devices.
2. Description of the Related Art
Electronic devices, including organic electronic devices, continue to be more extensively used in everyday life. Forming circuits in such electronic devices includes forming conductive pathways in organic layers such as those that lie between electrodes of the electronic device. One method to define the conductive pathway is to form a conductive structure by removing portions of a previously formed conductive layer. Another method is to print the conductive structure using a selective deposition technique. Insulating material can be deposited between such conductive structures to provide electrical insulation and planarization. When the insulating material is blanket deposited, openings are made in the insulating layer such that the conductive structures can be electrically connected to form conductive pathways. Another method is to form a well within bank structures such that a conductive liquid deposited over the bank structures collects in the wells to form conductive structures. However uniform formation and fill of many individual structures can be difficult to control.
Improved methods for defining conductive pathways are desired.

Process for forming an organic electronic device including an organic device layer


An electrical connector, electrical connection assembly implementing at least one such electrical connector, and method of making such an electrical connector are disclosed. The method includes attaching a wire to a conductive component that includes at least one of a pin and a socket, positioning the conductive component into a supporting structure, and positioning a retaining component in relation to the supporting structure, where the retaining component serves to substantially prevent relative movement of the conductive component relative to the supporting structure. The method further includes overmolding at least portions of the supporting structure and the wire.

Electrical connector assemblies, which allow for the connection of one or more electrical nodes or lines with one or more other electrical nodes or lines, are ubiquitous in a variety of electronics applications. Among these are applications involving electrical power distribution as well as applications involving electronic communications such as computer networks.
Commonly, electrical connector assemblies include male and female connectors, the former having pins and the latter having complementary sockets. Further, one known manner of manufacturing such male and female connectors involves the fitting of metallic pins or sockets into plastic support structures or "inserts," where the plastic inserts have complementary holes for receiving the pins/sockets. When the pins/sockets are fully assembled into the plastic inserts, the pins/sockets extend beyond their complementary holes and outward from one or more surfaces of the plastic inserts such that contacting ends of the pins/sockets can receive/be received by complementary sockets/pins.
Also, typically extending from the ends of the pins/sockets opposite to their contacting ends are leads or wires, which often are crimped within recesses of the pins/sockets so as to affix the wires to the pins/sockets. Thus, the final positioning of the pins/sockets and wires on a connector typically is such that pins/sockets extend from a surface proximate one end of the connector and wires (or a cable) extend from a surface proximate the other end, where the pins/sockets and portions of the wires are generally supported by and positioned within the plastic inserts.
When the pins/sockets and wires are in place with respect to an insert, an overmolding step typically is performed upon a large portion of the insert so as to more fully and permanently lock the pins/sockets and corresponding wires in place with respect to the plastic insert. The overmolding step often involves encapsulating the end of the insert from which the wires extend in a plastic or rubber-type material.
One difficulty in manufacturing connector assemblies in this manner involves the tendency of the pins/sockets and corresponding wires to fall out of the complementary holes within the plastic inserts prior to the application of the overmolding. This tendency conventionally is overcome in one of two manners. One manner involves forcibly locking the pins/sockets into place within their complementary holes within the plastic inserts. A second manner involves, prior to the application of the overmolding, the application of a glue-type material often termed "hot melt" to lock the pins/sockets in place with respect to the plastic inserts.
Each of these conventional manners of securing the pins/sockets and corresponding wires in place with respect to the plastic inserts is disadvantageous. The first manner involving forcible insertion of the pins/sockets is undesirable at least insofar as the insertion process is difficult to standardize and often must be done by hand. As a result, the process can be time-consuming and costly to perform. The second manner involving the application of hot melt is undesirable at least insofar as it requires an additional manufacturing step that takes additional time to perform and also can be messy.
For at least these reasons, therefore, it would be desirable if a new type of connector (and/or connector assembly) was developed that could be manufactured without the need for either manual insertion of pins/sockets into plastic inserts or the application of hot melt. Further, it would be desirable if the new type of connector had the same external capabilities as conventional connectors, both in terms of its connectability with other connectors (and/or other complementary terminals), and also in terms of its robustness.

Connector assembly and method of making same


Network interworking with no cross-domain state may be provided. First, an edge node may receive a packet from an intermediate node in a first domain. The edge node may be between the first domain and a second domain. Next, the edge node may pop, in response to a first Service Identifier (SID) in the packet, headers corresponding to the first domain from the packet. The edge node may then push, in response to the first SID, a label stack corresponding to the second domain onto the packet. The first SID may include data corresponding to the label stack. Then the edge node may route the packet to the second domain destine to an end node in the second domain.

Multi-Protocol Label Switching (MPLS) is a type of data-carrying technique for high-performance telecommunications networks that directs data from one network node to the next based on short path labels rather than long network addresses, avoiding complex lookups in a routing table. The labels identify virtual links (paths) between distant nodes rather than endpoints. MPLS can encapsulate packets of various network protocols, hence its name "multiprotocol". MPLS supports a range of access technologies, including T1/E1, Asynchronous Transfer Mode (ATM), Frame Relay, and Digital Subscriber Line (DSL).
Internet Protocol (IP) may comprise a communications protocol that provides an identification and location system for computers on networks and routes traffic across the Internet. Internet Protocol version 6 (IPv6) is a version of the Internet Protocol (IP). IPv6 was developed to deal with the problem of Internet Protocol version 4 (IPv4) address exhaustion. IPv6 provides other technical benefits in addition to a larger addressing space. In particular, IPv6 permits hierarchical address allocation processes that facilitate route aggregation across the Internet, and thus limit the expansion of routing tables. The use of multicast addressing is expanded and simplified, and provides additional optimization for the delivery of services.


A circuit provides a high impedance input to an operational amplifier by substituting a p-channel field effect transistor for the bias resistor normally used on the input to an operation amplifier. By placing a PFET in place of the bias resistor, a resistance value can be created that is hundreds of times higher, for the same area of silicon within the integrated circuit, as that created with an actual resistor. This PFET has parasitic capacitance which may be significantly offset by connecting the gate of the PFET to the output of a source follower circuit having its input connected to the inverting input of the operational amplifier. The circuit may be still further improved by using a voltage follower amplifier circuit in place of the source follower.

When a high pass filter is needed on the input to an operational amplifier, a bias resistor, used to bias the input to the operational amplifier, also serves as the resistive component of a high pass RC filter. The capacitive component of the RC filter may be the circuit capacitance of the circuit connected to the input to the operational amplifier, and therefore, may be very small. When the capacitance is very small, and the high pass filter needs to have a very low cutoff frequency, the bias resistor needs to be of a very large value, typically in the 1 gigohm range (10.sup.9 ohms). Obtaining gigohm resistance values within an integrated circuit requires a very large amount of space within the integrated circuit.
Prior art devices, such as those shown in FIGS. 1 and 2, described below, typically use bootstrapping to create an effective large resistance. Using the technique of bootstrapping, the effective resistance of the bias resistor is multiplied by a ratio of two resistors connected between the inverting input of the operational amplifier and the voltage source, and since this ratio may typically have a value of 50, only a 40 megohm resistor is needed for the bias resistor to accomplish an effective resistance of 1 gigohm. The bootstrap ratio is limited by the offset voltage of the amplifier, and creating a 40 megohm resistor requires considerable amount of integrated circuit space.
A FET may be used to create the resistor, however, this method requires that the FET be of a very large size. Because of the large size, there is a large parasitic capacitance within the FET which acts as a voltage divider, reducing the value of the input signal.
There is need in the art then for a circuit that will provide an equivalent high value bias resistance while requiring far less space than that occupied by creating a resistor within an integrated circuit, and can offset the effect of large parasitic capacitance within a large FET. The present invention meets these and other needs.


A modular heat sink including a first heat sink and a second heat sink is disclosed. The first heat sink includes a first base having a female connecting part and a first fin assembly disposed on the first base. The second heat sink is connected to the first heat sink and includes a second base having a male connecting part for coupling the female connecting part and a second fin assembly disposed on the second base. The male connecting part is coupled with the female connecting part.

1. Field of the Invention
The invention relates to a heat sink and, more particularly, to a modular heat sink.
2. Description of the Related Art
With the progress of the semiconductor technology, the size of the display tends to be large. The flat panel display such as the household liquid crystal display (LCD) and plasma display panel (PDP) and the light emitting diode (LED) display applied to the large outdoor billboard are common displays.
Taking the large outdoor billboard as example, on the basis of the condition that the problem of signal delay is not absolutely solved and the consideration for the cost, a common large outdoor billboard is usually composed of a plurality of small LCDs, PDPs or LED displays. Taking the LED display as example, the LED display is composed of a plurality of LED modules arranged in array to obtain the needed size.
Under the limitation of the size and the heat dissipation effect of the heat sink, only a small LED module cooperates with one or a plurality of heat sinks nowadays. However, when a plurality of small LED modules are connected together and form a large LED display, the small LED modules at the periphery of the LED display contact the cold environment and have good heat dissipation effect. Relatively, the small LED modules at the center of the LED display have a bad heat dissipation effect.


A housing system can comprise a plastic cover (12); a plastic base (14) comprising a floor (20) having sidewalls (22, 24); a first elevation (26); a second elevation (34); a first mounting column (40) located in a transformer end (32) of the plastic base (14) adjacent a major axis first sidewall (22); a second mounting column (42) located in the transformer end (32) of the plastic base (14) adjacent a major axis second sidewall (22); wherein the first and second mounting columns (40,42) have a top surface (44) that protrudes a distance from the floor (20), in the Z direction, in an amount greater than or equal to elevation walls (28,36), wherein the top surface (44) is configured to receive an attachment element (46). The housing system can also comprise a transformer (72), physically attached to the mounting columns; a capacitor (74); a fan (78), and a printed circuit board (80).

Inverters are electrical devices that are generally connected to a power supply and convert a part of incoming electricity (e.g., convert direct current (DC) to alternating current (AC)) to supply power. Inverters can also convert a part of incoming electricity and store it in a storage device, which is utilized to supply power when a power outage occurs. Inverters are generally surrounded by a housing that protects the inverter components from damage, heat, or other outside elements that could impair the functionality of the inverter. Inverter housings made from sheet metal with slots or perforations for dissipation of internal heat by conduction or convection suffer from a lack of design freedom, which restrict the possibilities for aesthetic enhancement. The use of metal for inverter housings also increases the weight of the inverter system and requires the use of secondary operations such as painting, powder coating, and system. This increases the overall time to produce the inverter and the inverter housing, thus leading to increased production costs.
Thus, there is a need for inverter housings with increased design freedom and that are lighter in weight than all metal designs, and which can be produced and assembled more quickly, eliminating some or all secondary operations.


A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first internal clock from an external clock in a first frequency band, a second DLL circuit for generating a second internal clock from an external clock in a second frequency band different from the first frequency band, and a selector for selecting any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputting the selected clock as the operation clock of the memory module.

The present invention relates to an information processing apparatus and a memory module. Particularly, the present invention relates to a memory module for generating an internal clock synchronized with an external clock, the memory module being operated based on the internal clock as an operation clock, and to an information processing apparatus having the memory module.
In a notebook type personal computer of recent years, mechanisms by no means inferior to those of a desktop type personal computer, such as a processor capable of high-speed processing and a monitor displaying a sharp and clear image, have been mounted. In connection with this, power consumption required for obtaining desired performance in the notebook type personal computer has been increased, and an extension of a battery lifetime of the notebook type personal computer has become a great subject.
In order to solve such a subject as described above, a graphic processor enabling power saving by selectively using different clock frequencies has been proposed (for example, refer to Non-Patent Document 1). This graphic processor is equipped with a high performance mode operating the graphic processor at a high clock frequency when high performance is required, and with a power saving mode operating the graphic processor at a low frequency by which power saving is realized. The high performance mode and the power saving mode are switched in accordance with a switching action of a user, a switching between an AC mode and a DC mode, and the like.
[Non-Patent Document 1]
Original Internet URL (at the time of this writing) located at: http://www.ati.com/jp/technology/hardware/mobility_fgl—7800/powerplay/
However, in the conventional graphic processor, a graphic memory cannot be operated at a frequency lower than a minimum clock frequency of a DLL circuit thereof. Therefore, the clock frequency of the graphic memory cannot be lowered, and thus it has been impossible to realize sufficient power saving of the graphic processor.

Processing system and memory module having frequency selective memory


An embodiment of a method, system, and structure communicating messaging data in a header of a packet are provided. The data structure includes a data packet comprising a header and a payload, wherein part of the header includes first and second data portions, wherein the first data portion indicates a type of message encoded in the second data portion, and wherein the second data portion includes message data. An embodiment of a method includes encoding a communications message, which would otherwise be inclusive in a payload portion of a packet into a portion of a header of a packet, encoding an indication that indicates a type of messaging that said messaging is, and facilitating the communication of the packet to a destination.

Sending data in packets is one way to communicate information. Generally, packets have included a header portion and a payload portion. Historically, these portions separate header information from payload information. But the current state of the art could be improved by including payload-type information (e.g., messaging information) in a portion of a packet header.

Data communications method and structure


A wireless transmit/receive unit (WTRU) determines PDCCH candidates. For a slot, the WTRU determines a number of valid PDCCH candidates associated with at least one search space based on a number of designated search spaces associated with the WTRU in the slot, a type of the search space, a priority associated with the search space, a number of required CCE channel estimates associated with the search space, a maximum number of PDCCH candidates in a slot, and a number of control resource sets (CORESETs) associated with the slot. The WTRU may then attempt to decode CCEs in the at least one search space to recover a PDCCH associated with the WTRU. The WTRU may drop PDCCH candidates from the search space when the number of PDCCH exceeds a maximum value.

A radio access network (RAN) is part of a mobile telecommunication system providing wireless transmit receive units (WTRUs) with connection to a core network (CN). In fifth generation (5G) or next generation (NG) wireless systems, the RAN may be referred to as New Radio (NR) or next generation RAN. NR is designed to support great flexibility. Such flexibility ensures that WTRUs with different capabilities can be simultaneously served with different types of traffic. The different capabilities for NR are varied and may be classified into extreme Mobile Broadband (eMBB), Ultra High Reliable and Low Latency communications (URLLC), and massive Machine Type Communications (mMTC). In addition, NR needs to support transmission in much higher frequency bands, such as centimeter (cm)-wave and millimeter (mm)-wave frequencies. In order to support all of these capabilities and transmission methods, a WTRU may need to monitor a multitude of Physical Downlink Control Channel (PDCCH) candidates and determine when it is scheduled to receive a data transmission. As such, the WTRU would need to check all possible PDCCH candidates and this may necessarily increase blind detection complexity. Thus, it would be desirable to limit the blind detection complexity by determining which PDCCH candidates need to be monitored at any given moment.

Methods for physical downlink control channel (PDCCH) candidate determination


In a preferred embodiment, a bioassay plate washer, including: a housing; a first wash assembly disposed in the housing; the first wash assembly including wash and aspirate manifolds having defined therein, respectively, a wash liquid chamber and a vacuum chamber; a plurality of wash needles for communication between the wash liquid chamber and a first point below the first wash assembly; a plurality of aspirate needles for communication between the vacuum chamber and a second point below the first point; and each one of the plurality of aspirate needles being disposed internally of each one of the wash needles.

1. Field of the Invention
The present invention relates to the washing of bioassay plates generally and, more particularly, but not by way of limitation, to a novel washer for washing bioassay plates, the washer including concentric aspirate and wash needles.
2. Background Art
In clinical diagnostics and pharmaceutical research, a common protocol is enzyme linked immunosorbent assays (ELISA). In general terms, a reagent is bound to a container's surface. Other reagents react with the bound reagent, and are finally detected using an enzyme to cause a substrate to provide a color reaction. In these protocols, it is necessary to wash away the excess regent between each step.
The current de facto standard for ELISA protocols is to perform them in a 96-well microplate. Each well holds approximately 300 microliters. The wells are arranged on an 8.times.12 matrix on 9 mm centers. The antigen, or antibody, reagent is coated on the well surface. Typically, 200 microliters of a blocking reagent is added and allowed to react for a period of time with the antigen reagent. A plate washer is used to aspirate the blocking reagent from the well. Then, the well is refilled with a washing liquid and aspirated empty several times to remove any excess blocking reagent that is not bound to the side walls. This process is repeated several times with the other reagents used in the specific protocol.
Since the reaction is on the surface of the walls of the well and not in the liquid within the well, it is desirable to maximize the surface area and minimize the liquid reagents required to fill the well. This need for reduction in the use of reagents is driven by the cost of the reagents. Many antigens and antibodies must be grown in animals. This makes them precious.
To meet the demand for reduction in reagent use and cost and still meet the demands of high throughput screening, the trend is toward the use of a 384-well plate in the same overall physical dimensions as the current 96-well plate. The 384 wells are arranged in a 16.times.24 matrix on 4.5 mm center-to-center spacing. The brim volume of each well is approximately 80 microliters, with a working volume of around 30 microliters.
This close spacing obsoletes the plate washers that are currently on the market. The number of wells to be aspirated simultaneously increases four fold. This puts a different demand on the vacuum requirements for aspiration. The tight spacing requires a smaller, more precisely aligned wash and aspirate needle assembly.
For the foreseeable future, there will be a need to wash both 96-well and 384-well plates and to do so in a manner that washes all wells on a plate simultaneously. Heretofore, no plate washer has been known which could simultaneously wash all wells on a 384-well plate. Conventional washers for the latter type of plate employ two or three needles and treat one row of wells at a time.
Accordingly, it is a principal object of the present invention to provide a bioassay plate washer that can simultaneously wash all wells on a bioassay plate having a large number of wells.
It is a further object of the invention to provide such a bioassay plate washer that can easily accommodate bioassay plates having different numbers of wells.
It is an additional object of the invention to provide such a bioassay plate washer that is economically constructed.
Other objects of the present invention, as well as particular features, elements, and advantages thereof, will be elucidated in, or be apparent from, the following description and the accompanying drawing figures.

Bioassay plate washer having concentric aspirate and wash needles


A charging device for charging a storage battery mounted on an electric vehicle includes: a first relay to generate a communication start signal for causing communication between the charging device and the electric vehicle to be started; a cable including a connector for connection to a plug of the electric vehicle at one end to electrically connect the charging device and the electric vehicle; a signal line included in the cable and connected to the first relay; a power supply circuit to pass a current to the signal line when the connector is connected to the plug; a current detection circuit to detect a current flowing in the signal line; and a controller to control the first relay and start the communication when the current detection circuit detects the current.

In recent years, the charging infrastructure has been spreading with the increase in electric vehicles such as electric vehicles (EVs) and plug-in hybrid vehicles (PHVs). There has also been proposed Plug and Charge (PnC) that automatically starts charging by simply connecting a connector of a charging device to an electric vehicle.
Moreover, storage batteries mounted on electric vehicles are used, together with a charging/discharging device, as a virtual power plant (VPP) to adjust electric power sold and purchased at home in a Vehicle to Home (V2H) system or to adjust the supply and demand balance of commercial power in a Vehicle to Grid (V2G) system. In order to manage the number of storage batteries that can be used by a charging device or charging/discharging device, means for checking a connection state between the charging device or charging/discharging device and the electric vehicle is required.
The configuration and operation of the electric vehicle and the charging device are defined in the guidelines that, for example, the electric vehicle and the charging device include a connector connection checking means, a charge start/stop means, and a communication means. Moreover, specifications define that the electric vehicle and the charging device start to communicate with each other when the connector of the charging device is connected to the electric vehicle and a charge start/stop relay of the charging device is turned on. The charging/discharging device has the function of a discharging device in addition to the function of the charging device, and thus operates similarly to the charging device at the start of charging.
Patent Literature 1 discloses a charging/discharging device including a connector connection checking means for detecting a connection state between the charging/discharging device and an electric vehicle using a connector connection checking line between the electric vehicle and the charging/discharging device.

Charging device and charging/discharging device


Described herein is a wet wipe including a substrate and a lotion. The lotion includes from about 98.5% to about 99.9% water, from about 0.061% to about 0.084% benzoic acid, and from about 0.024% to about 0.072% by weight of sodium benzoate, wherein the amount of benzoic acid is greater than or equal to the amount of sodium benzoate. The benzoic acid is derived from dissociation of the sodium benzoate within the lotion. The lotion has a pH from about 3.6 to about 4.8.

Wet wipes are constructed from porous or absorbent sheets impregnated with a lotion and they are sold and stored in an air-tight container or wrapper to prevent the sheets drying out. Wet wipes are made for a variety of uses. The two main categories of use are firstly, those for general household cleaning tasks, such as the cleaning of hard surfaces like floors or kitchen surfaces and secondly, those made for personal cleansing, such as the removal of make-up, or the cleaning of infants prior to the fitting of a new diaper or the simple refreshment of the skin after meals or while traveling. Wipes have also found use with feminine health and adult incontinence products.
A major proportion of the wipes intended for the cleansing of human skin are wet wipes which are designed for use with infants and young children. They are particularly used by parents during the changing of babies to clear away any excess fecal or urine residues in the peri-anal region before applying a fresh diaper or nappy. Wet wipes are required to be effective at cleaning while at the same time being very gentle and mild on the skin of the baby. This is especially important given that the skin of the baby around the genitals and anus may become very sensitive or rash-prone after extended contact with urine and fecal matter.
One way to formulate a gentle and mild lotion for a wet wipe is to increase the water content of the lotion. Increasing the water content of the lotion has the added benefit of decreasing the amount of chemicals applied to the skin. However, the higher the water content of a lotion, the more difficult it is to meet preservative system efficacy requirements for microbial growth.
Therefore, there is a need for a wet wipe comprising a gentle, high water content lotion that meets preservative system efficacy requirements for microbial growth. More specifically, there is a need for a wet wipe comprising a gentle, 99% water lotion that meets preservative system efficacy requirements for microbial growth.


This invention relates to thermosetting resin compositions useful for mounting onto a circuit board semiconductor devices, such as CSPs, BGAs, LGAs and the like, each of which having a semiconductor chip, such as LSI, on a carrier substrate. The compositions of this invention are reworkable when subjected to appropriate conditions.

1. Field of the Invention
This invention relates to thermosetting resin compositions useful for instance, in mounting onto a circuit board semiconductor devices, such as chip size or chip scale packages ("CSPs"), ball grid arrays ("BGAs"), land grid arrays ("LGAs") and the like, each of which having a semiconductor chip, such as large scale integration ("LSI"), on a carrier substrate. The compositions of this invention are reworkable when subjected to appropriate conditions.
2. Brief Description of Related Technology
In recent years, the popularity of small-sized electronic appliances, such as camera-integrated video tape recorders ("VTRs") and portable telephone sets, has made size reduction of LSI devices desirable. As a result, CSPs, BGAs and LGAs are being used to reduce the size of packages substantially to that of bare chips. Such CSPs, BGAs, LGAs improve the characteristics of the electronic device while retaining many of their operating features, thus serving to protect semiconductor bare chips, such as LSIs, and facilitate testing thereof.
Ordinarily, the CSP/BGA/LGA assembly is connected to electrical conductors on a circuit board by use of a solder connection or the like. However, when the resulting CSP/BGA/LGA/circuit board structure is exposed to thermal cycling, the reliability of the solder connection between the circuit board and the CSP/BGA/LGA often becomes suspect. Recently, after a CSP/BGA/LGA assembly is mounted on a circuit board, the space between the CSP/BGA/LGA assembly and the circuit board is often now filled with a sealing resin (often referred to as underfill sealing) in order to relieve stresses caused by thermal cycling, thereby improving heat shock properties and enhancing the reliability of the structure.
However, since thermosetting resins are typically used as the underfill sealing material, in the event of a failure after the CSP/BGA/LGA assembly is mounted on the circuit board, it is very difficult to replace the CSP/BGA/LGA assembly without destroying or scrapping the structure in its entirety.
To that end, techniques for mounting a bare chip on a circuit board are accepted as substantially similar to the mounting of a CSP/BGA/LGA assembly onto a circuit board. One such technique, disclosed in Japanese Laid-Open Patent Publication No. 102343/93, involves a mounting process where a bare chip is fixed and connected to a circuit board by use of a photocurable adhesive, where, in the event of failure, this bare chip is removed therefrom. However, this technique is limited to those instances where the circuit board includes a transparent substrate (e.g., glass) which permits exposure to light from the back side, and the resulting structure exhibits poor heat shock properties.
Japanese Laid-Open Patent Publication No. 69280/94 discloses a process where a bare chip is fixed and connected to a substrate by use of a resin capable of hardening at a predetermined temperature. In the event of failure, this bare chip is removed from the substrate by softening the resin at a temperature higher than the predetermined temperature. However, no specific resin is disclosed, and there is no disclosure about treating the resin which remains on the substrate. Thus, the disclosed process is at best incomplete.
As pointed out in Japanese Laid-Open Patent Publication No. 77264/94, it is conventional to use a solvent to remove residual resin from a circuit board. However, swelling the resin with a solvent is a time consuming process and the corrosive organic acid ordinarily used as the solvent may reduce the reliability of the circuit board. Instead, that disclosure speaks to a method for removing residual resin by irradiation with electromagnetic radiation.
Japanese Laid-Open Patent Publication No. 251516/93 also discloses a mounting process using bisphenol A type epoxy resin (CV5183 or CV5183S; manufactured by Matsushita Electric Industrial Co., Ltd.). However, the removal process so disclosed does not consistently permit easy removal of the chip, the curing step is lengthy at elevated temperatures, and the process generally results in poor productivity.
Of course, mechanical methods of removing/replacing semiconductor chips from/on a substrate are known, such as by cutting the chip to be removed/replaced. See U.S. Pat. No. 5,355,580 (Tsukada).
Thermoplastic underfill resins are known for use in semiconductor chip attachment. See U.S. Pat. No. 5,783,867 (Belke, Jr.). However, such thermoplastic resins tend to leak under relatively modest temperature conditions. In contrast, thermosetting resins cure into a matrix which ordinarily have greater thermal stability under end use operating temperatures.
U.S. Pat. Nos. 5,512,613 (Afzali-Ardakani), 5,560,934 (Afzali-Ardakani) and 5,932,682 (Buchwalter), each refer to a reworkable thermoset composition based on a diepoxide component in which the organic linking moiety connecting the two epoxy groups of the diepoxide includes an acid cleavable acyclic acetal group. With such acid cleavable acyclic acetal groups forming the bases of the reworkable composition, a cured thermoset need only be introduced to an acidic environment in order to achieve softening and a loss of much of its adhesiveness.
U.S. Pat. No. 5,872,158 (Kuczynski) and 6,008,266 (Kuczynski), each refer to thermosetting compositions capable of curing upon exposure to actinic radiation, which are based on acetal diacrylates and acetal diepoxides, respectively, and reaction products of which are reported to be soluble in dilute acid.
U.S. Pat. No. 5,760,337 (Iyer) refers to thermally reworkable crosslinked resins to fill the gap created between a semiconductor device and a substrate to which it is attached. These resins are produced by reacting a dienophile (with a functionality greater than 1) with a 2.5-dialkyl substituted furan-containing polymer.
International Patent Publication No. PCT/US98/00858 refers to a thermosetting resin composition capable of sealing underfilling between a semiconductor device including a semiconductor chip mounted on a carrier substrate and a circuit board to which said semiconductor device is electrically connected. The composition includes about 100 parts by weight of an epoxy resin, about 3 to about 60 parts by weight of a curing agent, and about 1 to about 90 parts by weight of a plasticizer. Here, the area around the cured thermoset is to be heated at a temperature of about 190 to about 260° C. for a period of time ranging from about 10 seconds to about 1 minute in order to achieve softening and a loss of much of its adhesiveness.
U.S. Pat. Nos. 5,948,922 (Ober) and 5,973,033 (Ober), each refer to a certain class of compounds having tertiary oxycarbonyl linkages, and compositions based on such compounds, which when cured provide thermally decomposable compositions capable of being reworked.
Notwithstanding the state of the art, it would be desirable for an underfilling sealing material to provide good productivity, thermal shock and mechanical stress absorbing properties, while allowing the substrates with which it is to be used to be readily processed and easily separated from a semiconductor device without application of too extreme conditions that may compromise the integrity of the semiconductor devices remaining on the substrate or the substrate itself. In addition, it would be desirable to provide such a material which is based on an epoxy material for reworkability that may be prepared from readily available and inexpensive starting materials.

Reworkable thermosetting resin composition


The image forming apparatus includes an image processing portion for creating image data of a document read by an image reading portion and a communication portion for transmitting the created image data to a server or cloud, and obtains the image data saved in the server or the like to perform required processing, in which a reduced image generating portion for creating reduced image data based on the created image data, a main storage portion for linking the reduced image data and a saving destination of the data serving as original thereof for storage, and a display portion for displaying an operation screen are included, and the reduced image data stored in the main storage portion is displayed on the display portion to select image data for which the required processing is performed.

An image forming apparatus which reads an image of a document to generate image data and performs processing of printing or the like for the image data generally has a mechanism for temporarily saving the image data before processing in the apparatus. In the case of this form, however, in an image forming apparatus such as a low-price model that is not provided with a large storage, it is impossible to store large amount of image data.
Thus, there is a method that an external storage device such as cloud/server connected through a network serves as a saving destination of image data. In the case of this form, however, the image data is not able to be confirmed without accessing the above-described external storage device through the network.
Japanese Laid-Open Patent Publication No. 2006-295256 discloses as follows, as to the technology for using an external storage device connected through a network as a saving destination of image data. That is, in a technology disclosed in Japanese Laid-Open Patent Publication No. 2006-295256, a digital camera transmits created image data to a server through a wireless LAN (Local Area Network) for storage, a server creates a thumbnail image based on the received image data, and when receiving a browsing request of image data from a user terminal, transmits the thumbnail image. When the user terminal displays the received thumbnail image, a user is able to select the target image data.
However, when the technology disclosed in Japanese Laid-Open Patent Publication No. 2006-295256 is applied to an image forming apparatus so that a thumbnail image received from the external storage device through the network is displayed by the image forming apparatus in response to a user request to cause the user to select image data to be processed by the image forming apparatus, time from the user request till when the thumbnail is displayed becomes long, thus lacking user-friendliness.


A system and method for controlling a "serialization" of accesses to main storage in a tightly coupled multi-processing apparatus is disclosed. The system includes a plurality of central processing units (CPUs), a main storage unit commonly shared by the plurality of CPUs and a memory control unit operatively connected to each of the CPUs. A process for ensuring that a correct sequence of accesses to the main storage is followed is called a "serialization." When a serialization occurs subsequent to a "STORE" instruction in a particular CPU, the system for controlling a serialization notifies the occurrence of a serialization to all other CPUs before the particular CPU requests the memory control unit for the serialization. If the particular CPU is not notified of any occurrence of a serialization in the other CPUs, the particular CPU immediately executes the following "FETCH" operation without waiting for completion of the particular CPU's serialization. Even if notified of an occurrence of a serialization in the other CPUs, the particular CPU need only wait for completion of the other CPU's serialization to execute the following "FETCH". When a serialization does not occur in the particular CPU, serialization notifications by the other CPUs are disregarded.

The present invention relates to a system for performing a serialization control of main storage accesses between central processing units (CPUs) in an information processing apparatus in which the main storage is shared by a plurality of CPUs.
A plurality of fetch or store accesses from a CPU to a main storage apparatus are generally conducted in parallel. It is necessary to ensure that these accesses are conducted in accordance with a predetermined order of instructions and that an instruction is executed in accordance with a predetermined set of operands in a predetermined order.
In particular, if a cache memory is employed, a STORE is conducted through a main storage and is thus slow, but a FETCH is conducted only through a cache and is thus fast, as shown in FIGS. 1A and 1B. As shown in FIG. 1A, an instruction I comprises an operand (OP) code and address portions, such as a first operand register number R1, a second operand index register number X2, a second operand base register number B2 and a second operand displacement D2. A STORE is conducted as follows. In a pipeline operation MA for a main storage access, an operand code of an instruction I is decoded in a D-cycle and the instruction I is used for accessing a general purpose register GPR. A signal of the address portion R1 is transmitted to a register R and to the next register R in the next cycle and so on. In an A-cycle, the contents of GPR are added to the displacement D2 for a logic address at effective address generator EAG, thereby providing an effective address. Then, in a pipeline operation CA for a cache access, the priority for a store request by operand request valid signal OP REQ VAL is determined in an operand request priority cycle OPP. In a T-cycle, it is detected whether or not the effective address exists in a cache. A cache comprises a translation look-aside buffer TLB, a tag TAG and a local buffer storage LBS. If the effective address matches the addresses existing in TLB and TAG, a real address for accessing LBS is set in real address register RAR. On the other hand, in a B-cycle, the WRITE data is obtained from another general purpose register GPR based on the address transmitted from instruction I. In an E-cycle, the WRITE data is set in register R1. While the real address is set in register R2 in an R-cycle, the WRITE data are stored in a register in accordance with operand status signal OP STV and subsequently in another register R in a W-cycle and in LBS in an S-cycle. The WRITE data and the real address are respectively transmitted to the memory control unit (MCU) through a register R and a part by memory control unit request signal MCU REQ so that the WRITE data may be stored in the main storage after a completion of one execution cycle of one instruction. Therefore, it takes time to store the WRITE data in the main storage.
A FETCH operation is shown in FIG. 1B. In an A-cycle, an effective address is obtained based on address portions B2 and D2 of instruction I and the priority for a fetch request by a signal OP REQ VAL is determined in an OPP-cycle. It is determined in a T-cycle by referring to TLB and TAG, whether or not the effective address exists in a cache. If it does, the data is obtained from LBS in a B-cycle and transmitted to result word register RWR through operand word register OWR in accordance with a signal OP STV in an E-cycle. Moreover, the data is transmitted from RWR and stored in a general purpose register GPR after a W-cycle. It is thereby subjected to a fetch operation before a completion of an execution cycle of an instruction.
Therefore, when a FETCH instruction is produced after a STORE instruction, the actual fetch operation is completed before the STORE operation. Thus, previous data in which the result of STORE is not yet reflected are fetched by the FETCH operation. In order to fetch the new data in which the result of STORE is properly reflected, it is necessary to perform a serializing process by providing a serialization request signal.
In some information processing apparatuses a main storage apparatus is shared by a plurality of CPUs. In these apparatuses a case arises in which a plurality of stores must be conducted by a CPU and be observed in accordance with an execution order from the CPUs when respective CPUs perform processes using a common area in the main storage apparatus.
In this case, when a certain process of several instructions or an interruption is conducted, a particular CPU must observe that another CPU completes its store access to the main storage apparatus before its following fetch access to the main storage apparatus. The process for ensuring that this sequence is followed is called serialization.
The serialization process is conducted as follows:
1. A first operation is conducted during the period from when a particular CPU transmits the serialization request after a store pending signal becomes 0 to when the MCU receives the serialization completion signal. This is the period during which the following fetch operation is stopped.
2. A second operation is conducted during the period from when the MCU receives the serialization request to when it completes distributing the serialization request to CPUs except for the particular CPU.
3. A third operation is conducted during the period to when an invalidation of a cache is completed by a store previously executed by the CPU from when the other CPUs receive the serialization request. This is the period during which following accesses to the main storage are stopped.
The CPUs' parallel processing ability should be increased so that the serializing process in a main storage access in a plurality of CPUs is executed at high speed.
FIG. 1C shows a structure of an information processing apparatus of a type to which the present invention is directed.
In FIG. 1C, N+1CPU 1-0, 1-1 . . . and 1-N (N is an integer larger than 1) operate in parallel. Memory control apparatus (MCU) 2 processes access requests of respective CPUs and main storage unit (MSU) 3 is shared by respective CPUs. Caches 4-0 to 4-N, comprising a high-speed small-capacity buffer, are provided at respective CPUs and constitute a hierarchical memory architecture together with main storage unit MSU. Instruction control units 5-0 to 5-N are provided for the respective CPUs and perform an execution instruction control using a pipeline.
A store-in function and a store-through function exist for controlling these caches. Store-in means that STORE is reflected only on a cache upon an execution of a store, and a group of data to be stored is transmitted to main storage unit MSU when the serialization is conducted or when the STORE of the particular CPU is reflected on all caches in other CPUs. Store-through is a method for always transmitting data to the main storage unit MSU every time STORE is performed.
The serialization process differs greatly depending on whether the cache control method is a store-in or a store-through. Examples of both cases are described as follows.
For a store-in, the store in which the control is classified depends on whether the area is private or public. In a public area, the contents of the cache are transmitted to the main storage unit MSU upon serialization. When the caching operation is invalidated, the next access to the main storage is performed so that the most recent data are obtained from the main memory unit, thereby ensuring that the serialization operation is executed.
For a store-through, a group of data to be stored of respective CPUs is generally transmitted to the main storage unit MSU, and the data in the other CPU caches are invalidated if the data of the store area are maintained in caches of other CPUs. This process including data transmission and cache invalidation is expressed by words reflection process in the following paragraphs. For a CPU which performs the serialization, the following access to a main storage is delayed until the reflection process on other CPUs is completed. Two serialization methods are available based on the time relationship between a main storage access of the operation accompanied with the serialization and a main storage access of the serialization object.
The first is a pre-serialization method. This method ensures that a main storage access in an operation accompanied with a serialization is conducted after a main storage access preceding the operation is completed. The other is a post-serialization method. This method ensures that a main storage access which follows the operation accompanied with a serialization is conducted after the operation is completed.
FIG. 2 shows a timing chart of a pre-serialization according to a prior information processing apparatus in FIG. 1C. FIG. 3 shows a timing chart of a post-serialization according to the prior apparatus. The prior art pre-serialization in FIG. 2 is explained as follows.
1) shows an execution flow in pipeline operations, a main storage access pipeline MA and a cache access pipeline CA of an instruction accompanied with a serialization. D represents an instruction decode cycle, A represents a generation cycle of an effective address for an operand, T represents a cycle of an address translation conducted by accesses to TLB and TAG and a detection of the existence of data in the buffer by an access to TAG. B represents a buffer 0 (cache) access cycle, E represents an execution cycle, and W shows a writing cycle of the result. OPP represents an operand request priority cycle conducted by an operand request valid signal OP REQ VAL and R represents a reading cycle conducted by an operand status valid signal OP STV.
2) is a store pending signal transmitted to a CPU when the memory control unit (MCU) is processing the storing request preceding the instruction to be serialized. The store pending signal is on until a STORE operation is entered into a pipeline operation of the MCU after an A-cycle starts, as shown in FIGS. 1A and 2.
3) is a serialization request signal, transmitted after a store pending signal is turned off, for the CPU performing a serialization to conduct a serialization request.
4) is a period of serialization processing in which the MCU informs other CPUs of a serialization request and the result of the preceding store of the CPU is reflected on the caches in other CPUs (i.e. the caches are invalidated). Other CPUs stop access to the main storage in this period.
5) shows a serialization completion signal transmitted from the MCU to the CPU performing the serialization after the serialization process 4) is completed. The CPU completes the serialization process when it receives this signal.
6) is an interlock period, in which the instruction execution of 1) is delayed by the serialization operation. The fetch operation of the operand using the address generated during the A-cycle is kept waiting for this interlock, and is carried out through the cache LBS during B-cycle when the interlock is released upon completion of the serialization.
Next, a prior art post-serialization method is explained by referring to FIG. 3.
1)' shows an execution flow in pipelines MA and CA of an instruction having a store request in the CPU S represents a store cycle for storing data in a cache followed by a memory control unit request signal MCU REQ.
2)' is a store pending signal transmitted to the CPU by an execution of a preceding store request. The store operation has not been invoked in a MCU pipeline and is not guaranteed to be transacted in the order of other requests from the CPU.
3)' is a post-serialization trigger signal produced in the CPU in a B-cycle. This signal is turned on in order to perform the serialization process independently from the flow requesting the serialization process.
4)' is a serialization request signal transmitted from CPU to MCU as a result of 3)', when the store pending signal of 2)' is turned off.
5)' is a period of serialization processing in which, after the CPU transmits a serialization request signal 4)' to the MCU, the MCU informs other CPUs of this signal. The result of the store from the present CPU is reflected on caches in other CPUs (i.e. the caches of other CPUs are invalidated). In this period, other CPUs stop performing a main storage access, from when the serialization signal is received to when the request for invalidating the cache, which is received previously, is completed.
6)' is a serialization completion signal transmitted from the MCU to the CPU performing the serialization, when a reflection process on the caches of other CPUs is completed. The serialization completion signal is turned on when the serialization request signal received by all the CPUs in a system, namely, when it is guaranteed that, after the request for invalidating the caches due to the previous store is completed in all CPUs other except for the particular CPU, the following memory access is executed by respective CPUs.
7)' is an execution instruction sequence to be executed after a store instruction ST of 1)'. A fetch conducted using an address generated at the A-cycle of 7)' is interlocked by generation of post-serialization trigger 3)' and is kept waiting until a completion of the serializing process of 5)'.
8)' is an interlock period of 7)'.
An operation of the prior art shown in FIGS. 2 and 3 is explained by referring to the structure shown in FIG. 1C.
Any one of instruction control units 5-0 to 5-N of respective CPUs 1-0 to 1-N may perform a store operation accompanied by an instruction execution. The serialization request signal is transmitted to the memory control unit MCU after reaching a cycle in which an interface between the corresponding caches 4-0 to 4-N and the memory control unit MCU is not affected, that is, in which the store pending signal is turned off. Thereafter, the main storage access is stopped until the serialization request signal reaches other CPUs.
The MCU processes sequentially such serialization request signals in order of receipt, in a similar manner to the store request, and thereafter transmits the serialization request signal to the other CPUs. As a result the other CPUs stop their main storage accesses until the previously received cache invalidation request is completed.
Namely, when the serialization request signal transmitted after the store pending signal is turned off reaches the other CPUs from the MCU, serialization is ensured so that the previously conducted store is reflected in all the caches of the other CPUs. In an information processing apparatus having a plurality of CPUs with individual caches and a common main storage apparatus, there is a problem that a main storage access following the serialization process is kept waiting, without any condition, until the store reflection process or cache invalidation process at the time of the serialization is completed, regardless of whether the cache is controlled by store-in or store-through method. Thus, the parallel processing capability of a plurality of CPUs is decreased.

System and method for serialization control of accesses to a common main storage