A semiconductor memory device includes a write driver, a first precharging unit, and a second precharging unit. The write driver loads data applied to a first data line onto a second data line. The first precharging unit precharges the second data line to a precharging voltage in response to a precharging signal. The second precharging unit overdrives the second data line to a voltage higher than the precharging voltage in response to an overdriving signal enabled for a predetermined time period during an initial precharging interval of the second data line.

The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device capable of precharging a local input/output (I/O) line to a stable voltage level.
Generally, a plurality of memory banks are designed in a semiconductor memory device such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and each memory bank is comprised of a plurality of cell arrays. Each cell array comprises cell groups, each of a plurality of memory cells. The memory cell includes a cell transistor and a cell capacitor, and stores one bit of data.
Herein, an area where the memory bank is located is a core cell region, and an area which is formed for inputting/outputting data to/from the memory bank is a peripheral circuit region. The data transferred to the peripheral circuit region through a data input/output (I/O) pin in a write operation of the semiconductor memory device is inputted into the core cell region through a write driver located on a boundary of the core cell region. Generally, a data line coupled to the data I/O pin and the write driver to transfer data is a global input/output (I/O) line GIO, and a plurality of the global I/O lines is called a global input/output (I/O) bus GIO_BUS. The data transferred through the write driver is written in the corresponding memory cell, wherein a data line that is shared with the write driver and each memory cell is called a local input/output (I/O) line LIO.
On the other hand, a precharge operation of the local I/O line LIO is performed as a means to reduce power consumption and increase speed in the semiconductor memory. The precharge operation is performed before the write operation in the semiconductor memory device to bring the local I/O line LIO to a precharging voltage level of a constant voltage level so as to obtain the write operation with higher speed and low power consumption.
FIG. 1 is a block diagram illustrating a partial structure of a conventional semiconductor memory device.
As shown, the conventional semiconductor memory device includes a memory bank 110, a plurality of write drivers 130A and 130B, a plurality of lower precharging units 150A and 150B, and a plurality of upper precharging units 170A and 170B.
The memory bank 110 includes a plurality of cell arrays and sub_hole areas to share a plurality of local I/O lines LIO<0>, /LIO<0>, LIO<1>, and /LIO<1>. Each of write drivers 130A and 130B is connected between a corresponding pair of local I/O lines LIO<0>, /LIO<0> and LIO<1>, /LIO<1>, and a global I/O bus GIO_BUS. Each of lower precharging units 150A and 150B is connected to a corresponding pair of local I/O lines LIO<0>, /LIO<0> and LIO<1>, /LIO<1>. Each of upper precharging units 170A and 170B is located on the other side of the write driver 130A and 130B on the basis of the memory bank 110 and connected to a corresponding pair of local I/O lines LIO<0>, /LIO<0> and LIO<1>, /LIO<1>.
Herein, a plurality of memory cells are provided in the cell array area, and a sense amplifier driver (not shown) is provided in the upper side and the lower side of each cell array area. The sub_hole includes plural circuits sub_hole such as a power source generating unit of the sense amplifier driver (not shown) for generating a power source of the sense amplifier driver corresponding to the cell array, a word line repeater (not shown), and an I/O switch (not shown), etc.
FIG. 2 is a block diagram illustrating a write operation and a precharge operation of the conventional semiconductor memory device.
For the sake of convenience, FIG. 2 shows a partial structure connected to a pair of local I/O lines LIO<0> and /LIO<0> shown in FIG. 1.
With reference to FIG. 2, the simple write operation will be described.
A data input from a global I/O line GIO<0> is applied to a write driver 130A, and the write driver 130A drives the pair of local I/O lines LIO<0> and /LIO<0> to pull up or pull down according to the data applied thereto in response to an enable signal BWEN. Here, the pair of local I/O lines LIO<0> and /LIO<0> comprises a main local I/O line LIO<0> and a sub local I/O line /LIO<0>. For example, the write driver 130A drives the main local I/O line LIO<0> to pull up and the sub local I/O line /LIO<0> to pull down, when the applied data is a logic high level. When the applied data is a logic low level, the write driver 130A drives the main local I/O line LIO<0> to pull down and the sub local I/O line /LIO<0> to pull up.
The data transmitted through the pair of local I/O lines LIO<0> and /LIO<0> is written in the memory cell of the corresponding cell array. The pull up/pull down operation of the main and sub local I/O lines LIO<0> and /LIO<0> is illustrated in FIG. 3.
Subsequently, the precharge operation of the pair of local I/O lines LIO<0> and /LIO<0> before or after the write operation will be described.
First, the lower precharging unit 150A precharges the pair of local I/O lines LIO<0> and /LIO<0> in response to an inverted reset signal RSTB, and the upper precharging unit 170A precharges the pair of local I/O lines LIO<0> and /LIO<0> in response to a reset signal RST. Herein, the inverted reset signal RSTB is generated by inverting the reset signal RST. Further, a signal for precharging the pair of local I/O lines LIO<0> and /LIO<0> such as the reset signal RST and the inverted reset signal RSTB may be changed according to a circuit structure of the lower and upper precharging units 150A and 170A.
For reference, an input/output (I/O) switch 160A includes an n-type metal-oxide semiconductor (NMOS) transistor having a drain-source path connected between the main local I/O line LIO<0> and the sub local I/O line /LIO<0>, and a gate receiving the reset signal RST. In addition, the I/O switch 160A connects the main local I/O line LIO<0> to the sub local I/O line /LIO<0> to equalize voltage levels between two lines in response to the reset signal RST. FIG. 3 illustrates a more detailed write operation, and FIGS. 3 and 4 illustrate the precharge operation.
FIG. 3 is a circuit diagram of the write driver 130A and the lower precharging unit 150A of FIG. 2.
FIG. 3 shows the write driver 130A and the lower precharging unit 150A, wherein the write driver 130A loads data applied on the global I/O line GIO<0> to the pair of local I/O lines LIO<0> and /LIO<0> in response to the enable signal BWEN, and the lower precharging unit 150A precharges the pair of local I/O lines LIO<0> and /LIO<0> to a voltage level of a core voltage VCORE in response to the inverted reset signal RSTB.
In the write operation of the write driver 130A, the inverted reset signal RSTB maintains a logic high level.
If data applied to the global I/O line GIO<0> is a logic high level, a logic low level is latched to a first latching unit LAT1 and the logic high level is latched to a second latching unit LAT2. Thereafter, when the enable signal BWEN is a logic high level, a second driving control signal CTR_DRV2 is a logic low level, thereby to drive the main local I/O line LIO<0> to pull up and the sub local I/O line /LIO<0> to pull down according to the logic levels latched to the first and the second latching units LAT1 and LAT2.
In contrast, if the data applied to the global I/O line GIO<0> is a logic low level, a logic high level is latched to the first latching unit LAT1 and the logic low level is latched to the second latching unit LAT2 so as to drive the main local I/O line LIO<0> to pull down and the sub local I/O line /LIO<0> to pull up. The pair of local I/O lines LIO<0> and /LIO<0> driven to pull up/pull down transmits data to the memory cell of the corresponding cell array.
The lower precharging unit 150A includes first to third PMOS transistors PM1, PM2, and PM3. The first PMOS transistor PM1 has a source-drain path connected between the core voltage VCORE and the main local I/O line LIO<0>, and a gate receiving a signal corresponding to the inverted reset signal RSTB. The second PMOS transistor PM2 includes a source-drain path connected between the core voltage VCORE and the sub local I/O line /LIO<0>, and a gate receiving the signal corresponding to the inverted reset signal RSTB. The third PMOS transistor PM3 includes a source-drain path connected between the main local I/O line LIO<0> and the sub local I/O line /LIO<0>, and a gate receiving the signal corresponding to the inverted reset signal RSTB.
In the precharge operation of the lower precharging unit 150A, if the inverted reset signal RSTB is a logic low level, the first to third PMOS transistors PM1 to PM3 of the lower precharging unit 150A are turned on so that the pair of local I/O lines LIO<0> and /LIO<0> is precharged to the voltage level of the core voltage VCORE. Further, the first to third PMOS transistors PM1 to PM3 equalize the voltage level of the main local I/O line LIO<0> and the sub local I/O line /LIO<0>.
FIG. 4 is a circuit diagram of the upper precharging unit 170A of FIG. 2.
As shown, the upper precharging unit 170A includes first to third PMOS transistors PM4, PM5, and PM6. The first PMOS transistor PM4 includes a source-drain path connected between the core voltage VCORE and the main local I/O line LIO<0> and a gate receiving a signal corresponding to the reset signal RST. The second PMOS transistor PM5 includes a source-drain path connected between the core voltage VCORE and the sub local I/O line /LIO<0> and a gate receiving the signal corresponding to the reset signal RST. The third PMOS transistor PM6 includes a source-drain path connected between the main local I/O line LIO<0> and the sub local I/O line /LIO<0> and a gate receiving the signal corresponding to the reset signal RST.
In the precharge operation of the upper precharging unit 170A, if the reset signal RST is a logic high level, the first to third PMOS transistors PM4 to PM6 of the upper precharging unit 170A are turned on so that the pair of local I/O lines LIO<0> and /LIO<0> is precharged to the voltage level of the core voltage VCORE, and equalize the voltage level of the main local I/O line LIO<0> and the sub local I/O line /LIO<0>.
Referring back to FIG. 1, when the memory bank 110 shares the pair of local I/O lines LIO<0> and /LIO<0>, the precharge operation is performed to the voltage level of the core voltage VCORE in the pair of local I/O lines LIO<0> and /LIO<0> through the lower precharging unit 150A and the upper precharging unit 170A. In order to precharge the pair of local I/O lines LIO<0> and /LIO<0> to the voltage level of the core voltage VCORE more quickly, the lower precharging unit 150A and the upper precharging unit 170A are provided.
In other words, since the pair of local I/O lines LIO<0> and /LIO<0> is very long lines in the semiconductor memory device, when the precharge operation is performed only by one of the lower precharging unit 150A and the upper precharging unit 170A, it takes a long time for all portion of the pair of local I/O lines LIO<0> and /LIO<0> to be up to the voltage level of the core voltage VCORE. If so, operation after the precharge operation may be also delayed.
Consequently, there is a disadvantage of increasing the total operation time of the semiconductor memory device. To solve the problem, the lower precharging unit 150A and the upper precharging unit 170A are provided on both sides of the pair of local I/O lines LIO<0> and /LIO<0> to perform the precharge operation.
However, since a voltage level of an external source voltage VDD is decreased and rapid operation speed of the memory device is desired, it is required that the pair of local I/O lines LIO<0> and /LIO<0> is more stably and quickly precharged up to the desired voltage level.
Furthermore, in the precharging operation of the plurality of pairs of local I/O lines according to the conventional structure, there is a problem that the voltage level of the core voltage VCORE is not stable when the plurality of pairs of local I/O lines are precharged at the same time using the core voltage VCORE.

Semiconductor memory device and method for driving the same


A refining apparatus and a refining method for recycling waste plastics. The refining apparatus includes a feeding device, a pyrolysis furnace, a chloride-decomposing device, a first condensation device, a temporary storage, a still, a sieve plate tower, a second condensation device, and a receiving tank. The waste plastics are cracked by the pyrolysis furnace to produce plastic gas by heating. The chlorides of the plastic gas are removed by the chloride-decomposing device having the ammonia to produce a first oil gas. The first oil gas is condensed by the first condensation device to produce raw oil. The raw oil is heated by the still to produce a second oil gas. The second oil gas is sieved by the sieve plate tower to produce a third oil gas. The third oil gas is condensed by the second condensation device to produce finished oil received by the receiving tank.

1. Field of the Invention
The present invention relates to an apparatus and method for recycling waste plastics, in particular with respect to a refining apparatus and a refining method for recycling waste plastics.
2. Description of the Related Art
With the development of technology and progress of civilization, people reply more and more on products of petrochemical industry, such as plastic product and gasoline and so on. However, as the amount of the petroleum crude oil used in the petrochemical industry has been declining as people's excessive dependence; recently, countries over the world have been developing the economy while engaging in how to reduce the usage of the petroleum crude oil.
In addition, people also have to process the waste plastics generated by the used plastic products, and if the waste plastics are buried, the plastic, which is difficult to decompose is not easy to decay, and it also destroys the soil environment. Consequently, the waste landfill will inevitably cause severe environmental problem. With the gradual increase of environmental protection consciousness, countries over the world will dedicate to the development of environmental industry and substantially commercialize the application to the environmental process. However, the problem is that the current technology still cannot refine the recycling waste plastics as the renewable oil of high purity by using the limited resource effectively.

Refining apparatus and refining method for recycling waste plastics


An electrical connector includes an insulative housing having a reception surface for receiving a complementary connector, an engaging surface opposite the reception surface for connecting with an external cable including a plurality of cable lines, and a plurality of receptacles formed in the insulative housing in communication with the reception surface and the engaging surface. A plurality of contacts are respectively received in the receptacles of the insulative housing and each contact has a reception portion for electrically engaging with the corresponding cable line of the cable. First and second shieldings secured together enclose the insulative housing and at least one end of the first and second shieldings is secured to a peripheral edge of the reception surface of the insulative housing. A positioning member is adapted to be received between the engaging surface of the insulative housing and the two shieldings to abut against the engaging surface of the insulative housing, wherein passageways are defined in the positioning member in communication with the receptacles and retain the cable lines therein. The positioning member prevents sputtered plastic particles from entering an interior of the insulative housing via the engaging surface during formation of a plastic shell which encloses the two shieldings.

1. Field of the Invention
The present invention relates to a high frequency electrical connector, and particularly to an easily configured high frequency electrical connector which is durable and can effectively reduce noise.
2. The Prior Art
Conventional electrical connectors of high frequency input/output devices have structures similar to standard electrical connectors which comprise an insulative housing, a plurality of contacts received in the insulative housing, and one or more shielding members enclosing the insulative housing for suppressing noise. Other features of conventional high frequency connectors include the contacts thereof electrically connected between a cable and corresponding number of contacts of a complementary connector, and a shell or the like provided to enclose the shielding. Manufacture of the conventional electrical connector is laborious due to the above features which result in the following disadvantages:
i) plastic particles are sputtered during formation of the shell and tend to enter an interior of the insulative housing via the cable or the passageways of the housing thereby adversely affecting the electrical connection between contacts of the electrical connector and a complementary connector.
ii) The insertion end of the electrical connector is apt to deform due to friction from repeated insertions/detachments of the complementary connector thus diminishing the retention capability of the contacts received in the insulative housing which in turn weakens the electrical connection between contacts of the electrical connector and the complementary connector.
Therefore, an improved high frequency electrical connector is required which can overcome the disadvantages of the conventional electrical connectors.


A laminated coil component includes a magnetic material part containing a metal magnetic material and a first glass component, and a nonmagnetic material part containing a ceramic material and a second glass component, and a coil conductor is formed so that at least the main surface of a coil pattern is in contact with the nonmagnetic material part. The magnetic material part is formed with the volume content of the first glass component based on the total amount of the metal magnetic material and the first glass component is 46 to 60 vol %. The nonmagnetic material part is formed with the volume content of the second glass component based on the total amount of the ceramic material and the second glass component is 69 to 79 vol %. A laminated coil component having good high-frequency characteristics and magnetic characteristics is obtained and a method for producing the laminated coil component.

A laminated coil component with a coil conductor included in a component element assembly formed of a magnetic material composition has been heretofore known as an electronic component used for a choke coil that is used at a high-frequency, a power supply circuit through which a large current passes, a power inductor for a DC/DC converter circuit, or the like.
In this type of laminated coil component, when an apparent relative permittivity increases between coil conductors or between a coil conductor and an external electrode to increase a stray capacitance, the resonance frequency may be shifted to a low frequency side, leading to deterioration of high-frequency characteristics.
For avoiding such an increase in stray capacitance, a low-dielectric-constant layer having a low relative permittivity may be provided as a part of the component element assembly.
In this case, however, when different materials are co-sintered in the production process, structural defects such as cracking and peeling may occur due to mutual diffusion and a difference in shrinkage behavior between materials.
Thus, for example, JP 2004-343084 A proposes an electronic component including: a magnetic material part composed of an iron-based oxide magnetic composition; a nonmagnetic material part formed in contact with the magnetic material part and composed of a glass ceramic composite composition; and an internal conductor part formed on at least one of the magnetic material part and the nonmagnetic material part, wherein the glass ceramic composite composition contains a crystallized glass as a main component and a quartz as a filler as a secondary component, the crystallized glass contains 25 wt % to 55 wt % of SiO2, 30 wt % to 55 wt % of MgO, 5 wt % to 30 wt % of Al2O2 and 0 wt % to 30 wt % of B2O2, and the quartz is contained in an amount of 5 to 30 parts by weight based on 100 parts by weight of the crystallized glass and dispersed in the crystallized glass.
In JP 2004-343084 A, the magnetic material part is formed of an iron-based oxide magnetic composition (ferrite-based magnetic material), and the nonmagnetic material part composed of a glass ceramic composite composition is formed in contact with the magnetic material part. A glass ceramic composite composition having reduced mutual diffusion between itself and the iron-based oxide magnetic composition that forms the magnetic material part is used to thereby obtain good co-sinterability.
Since the glass ceramic composite composition described in JP 2004-343084 A has a low magnetic permeability and dielectric constant, good insulation quality, and an effect of suppressing diffusion to a metal material such as Ag, a low-resistance material such as Ag can be used for an internal conductor, so that the direct-current resistance of an electronic component can be reduced.
On the other hand, a metal magnetic material is harder to be magnetically saturated as compared to a ferrite-based magnetic material, and has good direct-current superimposition characteristics, and therefore various kinds of laminated coil components obtained by using the metal magnetic material have been heretofore proposed.
For example, JP 2010-62424 A proposes a method for producing an electronic component, wherein a glass containing SiO2, B2O3 and ZnO as main components and having a softening temperature of 600±50° C. is added to a magnetic alloy material containing Cr, Si and Fe so that the volume of the glass is less than 10% of the volume of the magnetic alloy material, whereby a surface of the magnetic alloy material is covered with the glass to obtain a metal magnetic material, a molded article including a coil is formed using the metal magnetic material, and the molded article is fired at 700° C. or higher and lower than the melting point of a conductor material of the coil in a non-oxidizing atmosphere in vacuum, or without oxygen or at a low oxygen partial pressure.
In JP 2010-62424 A, a sufficient glass film can be formed on the surface of the metal magnetic material, and therefore generation of a gap between metal magnetic materials can be suppressed, whereby the insulation resistance can be increased without increasing the coil resistance, so that an electronic component such as a power inductor, which has good direct-current superimposition characteristics and a low magnetic loss, can be obtained.

Laminated coil component and method for producing same


A dietary supplement composition is disclosed which comprises a calcium salt, vitamin D and at least one mineral, preferably a boron compound. Other minerals may be present, in addition to, or instead of the boron compound, such as copper compounds, Magnesium compounds, manganese compounds and zinc compounds.

Mineral and vitamin compositions are routinely used as dietary supplements either as therapeutic preparations directed to a specific medical problem or as general nutritional supplements.
Calcium and trace mineral supplementation is important for adults as well as growing children. The adult population requires additional calcium to help prevent the bone loss that goes along with the normal aging process. Postmenopausal women require more calcium due to the change in their hormonal status, which can accelerate the bone loss rate leading to osteoporosis.
Osteoporosis is a prevalent condition, affecting as many as 15-20 million individuals in the United States. In osteoporosis, bone mass decreases causing bones to be more brittle, thus bones become more susceptible to fracture. It has been estimated that at least 1.3 million fractures in the U.S. are attributable to this disease National Osteoporosis Foundation, Stand UP to Osteoporosis, Your Guide to Staving Healthy and and Independent Through Prevention and Treatment, Washington, D.C. 1992!. Many scientist believe that a chronic shortage of dietary calcium is one very important factor leading to osteoporosis. Optimal calcium intake (1000-1500 mg) for adults may be achieved through diet, calcium fortified foods, calcium supplements or combinations thereof. Studies show that the usual intake of calcium for adult woment in the U.S. is between 450-500 mg per day U.S. Department of Health and Human Services, Public Health Service National Institutes of Health, Osteoporosis. Cause, Treatment Prevention, Maryland, National Institutes of Health, 1987!; this amount is well below the United States Recommended Daily Allowance (U.S. RDA). It has recently been reported that in addition to calcium, the minerals boron, copper, magnesium, manganese and zinc, play an important role in bone formation Strause, L., et at: The Role of Trace Elements in Bone Metabolism, Nutritional Aspects of Osteoporosis, New York, Raven Press, p. 223-233, 1992 and Nielsen, F.: Facts and Fallacies about Boron, Nutrition Today, 27 (3): 6-12, May/June 1992). In addition, vitamin D is known to play a critical role in the absorption of calcium by the human body. The recommended daily intake of vitamin D is between 400 INternational Units, hereinafter called I. U., and 800 I.U. for an elderly person.
The present invention relates to a calcium, vitamin D and multimineral dietary supplement composition. The multiminerals can comprise one or more salts of boron, copper, magnesium, manganese, zinc. The composition also comprises pharmaceutically acceptable carriers and excipients.


A method and apparatus for reliably delivering messages (200) from a central terminal (102) to a communication receiver (130) in a communication system (100), such as an electronic mail system. The central terminal (102) sequentially transmits messages (200) to the communication receiver (130) and the communication receiver (130) receives transmitted messages (200) over a first communication medium (122). The communication receiver (130) reconciles messages that it failed to receive over the first communication medium (122) with the central terminal (102) over a second communication medium (152). The reconciliation between the communication receiver (130) and the central terminal (102) utilizes message sequence identifiers (208) transmitted with the messages (200) that identify the transmission sequence of the sequentially transmitted messages (200).

Communication systems, such as paging systems, typically communicate messages from an originating device to one or more destination devices. These messages can include numeric and alphanumeric information for a user of the destination device. The destination device, e.g., a selective call receiver or pager, typically presents the information received to the user by displaying the information on a display.
Contemporary paging systems offer a limited message length for communicating information. For example, an alphanumeric message may be typically 80 characters or less. These typical message lengths have provided reasonably reliable delivery of messages to the users of the communication system.
On the other hand, a distinct trend in the market is for customers desiring much longer messages, such as messages that are ten to one hundred times longer or more. Transmission of these messages over a paging channel can encounter a number of obstacles to reliable delivery of the longer messages, such as different types of interference, fading, noise, and other phenomena detracting from error-free and reliable communication of the messages to the destination devices.
This difficulty in reliable transmission of the longer messages is especially frustrating to customers that are used to communicating long messages over a more reliable communication medium, such as direct wire line or dial-up telephone communication. This is particularly the case for electronic mail system users which typically desire to send relatively long messages with a high degree of certainty that the messages are received error free. Typically, an originating device, such as a personal computer or workstation, can send long messages to one or more destination devices, such as other personal computers or workstations, over a direct wire line interface, or over a local area network (LAN), or over a dial-up telephone line connection using the public switched telephone network (PSTN).
Therefore, a need exists to enhance the reliability of transmitting messages, including long messages, in communication systems that utilize paging systems for delivering the messages.


Provided is a wireless communication apparatus by which reduction of a diversity gain can be suppressed at minimum in the case of employing a repetition technology in multicarrier communication. In the wireless communication apparatus (100), repetition sections (102-1 to 102-n) repeat each data symbol inputted from modulating sections (101-1 to 101-n) to create a plurality of identical data symbols. An allocating section (103) outputs each data symbol to a multiplexing section (105) by allocating the data symbol to a plurality of subcarriers constituting an OFDM symbol. At this time, the allocating section (103) allocates at least one of the repeated identical symbols to a subcarrier different from a subcarrier to which the symbol is allocated in an adjacent sector.

In the field of wireless communication, especially in mobile communication, a variety of information such as image and data in addition to voice becomes transmission targets in recent years. It is anticipated that the demand for high-speed transmission becomes further increased in the future, and to perform high-speed transmission, a wireless transmission scheme, which utilizes limited frequency resources more effectively to achieve high transmission efficiency, has been required.
OFDM (Orthogonal Frequency Division Multiplexing) is one of radio transmission techniques, for meeting these demands. OFDM is one of multicarrier communication techniques, whereby data are transmitted in parallel using a large number of subcarriers, and it is known that OFDM provides high frequency efficiency and reducing inter-symbol interference under a multipath environment and is effective to improve transmission efficiency.
Studies are being conducted for performing frequency scheduling transmission and frequency diversity transmission using this OFDM on the downlink, when data for a plurality of radio communication mobile station apparatuses (hereinafter simply "mobile stations") are frequency multiplexed on a plurality of subcarriers (see Non-Patent Document 1 for example).
In frequency scheduling transmission, a radio communication base station apparatus (hereinafter simply "base station") adaptively allocates subcarriers for mobile stations, based on received quality of each frequency band in each mobile station, so that it is possible to obtain a maximum multi-user diversity effect, thereby enabling extremely efficient communication. This frequency scheduling transmission scheme is mainly suitable for data transmissions when a mobile station moves at low speed. On the other hand, since frequency scheduling transmission requires feedback of received quality information from each mobile station, frequency scheduling transmission is not suitable for data transmissions when a mobile station moves at high speed. Moreover, frequency scheduling transmission is performed based on received quality from each mobile station, and so it is difficult to apply frequency scheduling transmission to a common channel. Also, frequency scheduling is usually performed per subband, which groups a certain number of neighboring subcarriers adjacent to coherent bandwidth into a block, and so not much frequency diversity effect is provided.
On the other hand, frequency diversity transmission maps data for the mobile stations in the subcarriers of the entire band in a distributed manner so that a high frequency diversity effect can be obtained. Moreover, frequency diversity transmission does not require feedback of received quality information from mobile stations, so that frequency diversity transmission is a useful scheme where frequency scheduling transmission is difficult to apply, as described above. On the other hand, the frequency diversity transmission is performed regardless of received quality for each mobile station, and so multi-user diversity effect such as the frequency scheduling transmission cannot be obtained.
Moreover, in OFDM, the quality of each subcarrier may greatly fluctuate depending on frequency selective fading due to multi-path. In this case, since the signal allocated to a subcarrier at a position of a fading valley has a poor quality, thus making demodulation thereof difficult, the quality of the signal needs to be improved so as to make demodulation possible.
A technique for improving the quality in OFDM is the so-called repetition. The repetition is a technique in which a certain symbol is repeated to generate a plurality of same symbols, and these same symbols are allocated to a plurality of different subcarriers or different times to be transmitted. These same symbols are subjected to maximum ratio combining at the receiver side, whereby a diversity gain can be obtained (refer to Non-Patent Document 2, for example).    Non-Patent Document 1: R1-050604 "Downlink Channelization and Multiplexing for EUTRA" 3GPP TSG RAN WG1 Ad Hoc on LTE, Sophia Antipolis, France, 20-21 Jun., 2005    Non-Patent Document 2: Maeda, Atarashi, Kishiyama, Sawahashi "Performance Comparison between OFC DM and OFDM in a Forward Link Broadband Channel", Technical Report of IEICE, RCS2002-162, August 2002

Wireless communication base station apparatus and wireless communication method in multicarrier communication


The present invention provides a layout yield improvement tool that performs wire spreading to optimize integrated circuit (IC) designs in the physical design stage after detail routing. Preferably, the wire spreading is performed on a geotopological layout. Each modifiable wire thereof is processed to generate a geometric bottom-up shape (BUS) and a top-down shape (TDS). The BUS and TDS are merged to form a final geometrical Middle Shape (MS). Each point in the MS has a position is averaged from the positions of the two correlated points in the BUS and TDS. Unnecessary short jogs are removed from the MS of each wire. A final layout is generated by combining all of the final geometric shapes of each wire segments. As such, the wire-to-wire spacing is increased to more than the minimum spacing requirement without causing any design rule violations.

1. Field of the Invention
This invention relates generally to automatic layout optimization tools for semiconductor integrated circuit designs. More particularly, it relates to a new physical design tool that is able to increase the spacing between metal wires in the layout effectively and efficiently without violating any design rules.
2. Description of the Related Art
The flow for designing an integrated circuit (IC) can be roughly divided into the logical design phase and the physical design phase. The logical design phase includes several design stages: from the design specification to architectural behavioral design stage, to the register transfer level (RTL) design stage, to the gate design stage, after which the logical IC design is ready for the physical design phase. The physical design phase includes floor planning, placement, and routing, which produces the physical IC design layout.
Today, state-of-the-art integrated circuits usually contain tens of millions of transistors and over a million of metal wires on a single chip. To achieve a dense design, automatic physical design tools use the minimum spacing rules and the minimum width wires. The minimum spacing is usually only 1/10 micron or less, which is about the same or smaller than the size of dust particles. Consequently, bridging fault is one of the most critical reliability problems responsible for the lower yield in the semiconductor manufacturing process.
Bridging fault happens when the adjacent metal wires are inadvertently and erroneously connected due to dust contamination during the manufacturing process. The entire design could be ruined by a single dust particle lying between two different metal wires. Since the possibility of the dust contamination usually decreases by cubic root as the size of dust increases, even a very small increment on wire-to-wire spacing can remarkably avoid the false connection by the dust. Wire spreading is one of the most effective solutions to reduce bridging fault, hence reduce yield loss.
In addition to reducing dust related yield loss, wire spreading offers many other benefits. One of them is that it reduces the dummy metal fill for layout density control. Uniformed layout metal density is an important requirement for yield in the modern IC manufacture process. Generally, the dummy metal fill is inserted to the low density area in the layout to achieve a similar density as in the high density area. The problem is, the more the amount of metal fill, the more the manufacture variation, the more the possible yield loss.
Wire spreading increases the spacing between wires that originally follow the minimum spacing and, at the same time, decreases the spacing between wires which have more than the minimum spacing. The overall effect to the layout is that the metal density in the high density area is decreased and the metal density in the low density area is increased. The total amount of required dummy metal fill is reduced, so is the related yield loss.
Another benefit is that wire spreading reduces crosstalk noise. By enlarging the spacing between timing critical nets, the design performance can be greatly improved. What is more, the total capacitance of the layout is reduced by wire spreading, so the overall power consumption is reduced, which is welcomed in any designs.
Since wire spreading inevitably changes the wire routing path, the problem remains in how to increase the wire-to-wire spacing without causing any design rule violations.
Due to the nature of routing, the layout routers have to use the minimum spacing rule between wire paths during the routing stage. To fix timing or signal integrity problems, as one of the post-routing optimization, the router could enlarge the spacing between specific net pairs. However, the routers cannot achieve wire spreading which increase the wire-to-wire spacing on any possible nets throughout the whole layout.
Existing wire spreading tools that increase the net-to-net spacing on a routed layout through some automatic layout tool are based on the traditional geometrical layout representation. Since in a geometrical layout the wire path of every net has the determined shape and position, those wire paths imposes geometrical constrains on any modification to the layout. Consequently, to avoid introducing design rule violations, these geometrical layout based wire spreading tools have a limited capability. They usually can only process designs with less than 100K cells and usually take tens of hours or even days to complete the process.
Considering that the minimum size of a routing layout is usually over 1000K cells and that the routing can typically be completed within a few hours, there is a clear need in the art for an automatic layout optimization solution that can provide better and faster wire spreading on the whole layout effectively and efficiently without violating any design rules. The present invention addresses this need.

Wire spreading through geotopological layout


A modular guided keeper base, guided keeper assembly, and related method includes a modular guided keeper base that mounts to a die member. The guided keeper base has an integrated stop for guide pin retention. The guided keeper base can also accommodate a variety of bushings within the base. The guided keeper base is attached to a die member using a mounting flange(s). Mounting fasteners pass through the fastener holes in the mounting flanges and are anchored in the die member to securely retain the guided keeper assembly in place. A retainer ring is mounted in an associated groove in the base over the heads of the mounting fasteners to prevent unintentional unfastening of the fasteners from the die member.

The present invention relates to metal forming dies, and particularly to a modular guided keeper base and associated methods.
Metal forming dies, such as stamping dies and the like are well known in the art. Progressive metal forming dies are unique, very sophisticated mechanisms which have multiple stations or progressions that are aligned longitudinally, and are designed to perform a specified operation at each station in a predetermined sequence to create a finished metal part. Progressive stamping dies are capable of forming complex metal parts at very high speeds, so as to minimize manufacturing costs.
Heretofore, the dies used in metal forming presses have typically been individually designed, one of a kind assemblies for a particular part, with each of the various components being handcrafted and custom mounted or fitted in an associated die set, which is in turn positioned in a stamping press. Not only are the punches and other forming tools in the die set individually designed and constructed, but the other parts of the die set, such as stock lifters, guides, end caps and keepers, cam returns, etc., are also custom designed and individually installed in the die set. Current die making processes require careful machining, precision holes and recesses in the die set for mounting the individual components, such that the same are quite labor intensive, and require substantial lead time to make, test and set up in a stamping press. Consequently, such metal forming dies are very expensive to design, manufacture and repair or modify.
A modular guided keeper base that can accommodate many mounting and bushing options with integrated solid stops for guide pin retention would be clearly advantageous in simplifying metal forming die constructions and reducing the costs in designing, manufacturing and repairing the same.

This patent is subject to a terminal disclaimer.


To obtain a band pass delta sigma modulator (excluding θ0−±(π/2)×n; n is an integer being 1 or greater) for a desired frequency by replacing z in a z domain model of a low pass delta-sigma modulator with z′ below:z′=fcnv(z,θ0), wherein                fcnv(z, θ0) is a function in which the absolute value of fcnv(z, θ0) is always 1 for any z and θ0,θ0=2π×(f0/fs),        fs is a sampling frequency, and        f0 is a center frequency of a quantization noise stop band of the band pass delta-sigma modulator.

A delta-sigma modulation is a kind of oversampling modulation, and in general, is a technology used in AD conversion or DA conversion (see Non Patent Literature 1).
In delta-sigma modulation, noise shaping for greatly reducing quantization noise in a signal band by moving the quantization noise in the signal band to outside the signal band is performed.
Here, the term "delta-sigma modulation" means low pass delta-sigma modulation in many cases.
In low pass delta-sigma modulation, noise shaping is performed such that quantization noise at low frequencies is moved to higher frequency side, whereby quantization noise at low frequencies is attenuated. That is, in low pass delta-sigma modulation, a noise transfer function has a characteristic of stopping passing noise at low frequencies (near 0 Hz).
As delta-sigma modulation, other than the low pass delta-sigma modulation, there also is band pass delta-sigma modulation in which a noise transfer function stops passing noise at frequencies higher than 0 Hz.

Method for designing band pass delta-sigma modulator, band pass delta-sigma modulator, signal processing device, and radio transceiver


Systems and methods for providing a cost estimate for a data processing system are provided. An exemplary method may include selecting application programs from a set of application programs, wherein each application program may have a number of objects. The method may further include entering data descriptive of a load profile, retrieving a set of sizing coefficients for each object of the selected application programs, and estimating the hardware requirements for each one of the objects of the selected application programs by entering the sizing coefficients and the load profile into a sizing model. The method may further include entering the hardware requirements for each one of the objects of the selected application programs into a cost estimation component to provide a cost estimate for each one of the program objects of the selected application programs. The method may further include calculating a total hardware requirement by adding the hardware requirements, and calculating the total cost estimate for the data processing system by adding the cost estimates for each object of the selected application programs.

Various sizing methodologies for predicting the hardware investment needed to run software applications are known from the prior art. "Sizing" encompasses the determination of the central processing unit (CPU) requirements, volatile memory requirements (e.g., cache memory or random access memory), and mass storage requirements (e.g., hard disk capability) of a data processing system that is capable of running a given software application at acceptable performance levels.
U.S. Pat. No. 6,542,854 shows a method and mechanism for sizing a hardware system for a software workload. The workload is modelled into a set of generic system activities which are not directly tied to a specific hardware platform. Suitable hardware systems or components are selected by analyzing the workload and hardware profiles in terms of the generic system activities.
U.S. Pat. No. 6,542,893 shows a database sizer. The database sizer calculates the total mass storage requirements for a relational database table including database storage requirements, application and software requirements, system table requirements, scratch and sort requirements, log file requirements, and growth requirements. The database sizing is done by providing detailed inputs for tables in the database sufficient to calculate the required table size for each table; providing detailed inputs for each index for each table in the database sufficient to calculate the required index size for each table; providing input parameters for each database system, including the page size, the fill factor, the log file space, the temporary space (as a percent of the formatted database size including indexes), the space required for operating system and application software, the space required for system databases, the percent growth required for the database, and the page file space; calculating a total storage requirement for the database using the inputs and input parameters; and calculating a storage requirement for the data base management system using the inputs and input parameters. The calculated storage requirements include separately output operating system and application software space requirements, system table space requirements, scratch and sort space requirements, and log file space requirements.
Quick Sizer is a SAP® program product which assists in selecting the hardware and system platform that meets specific business requirements. Quick Sizer provides online, up-to-date sizing based on business-oriented figures, such as the number of users or expected number of business processes and documents (http://www.sap.com/andeancarib/soluciones/technology/documentacion/Ouick%20Sizer.pdf).
The Optimizer Model for SAP is an option to the HyPerformix Integrated Performance Suite™ (IPS). (http://www.hyperformix.com/whitepapers/Optimizer%20Model%20for%20SAP.pdf). The Optimizer Model for SAP includes models for the major SAP R/3 software modules (e.g., Financials, Sales and Distribution) and combines them with the extensive hardware library found with the HyPerformix Infrastructure Optimizer™ (Optimizer) product. Optimizer enables its users to analyze and optimize end-to-end performance of their SAP application on various hardware configurations.
The Optimizer Model for SAP takes workload and configuration parameter inputs. Workload parameters include the number of users of each SAP R/3 module. Configuration parameters include the number of servers at each tier (e.g., web, application) and the number of processes (e.g., Dialogue workers) on each server. Once workload and configuration parameters are specified, an application model is generated and automatically added to a hardware topology model created using Optimizer. "What-if" experiments can then be carried out to evaluate various performance questions.
The Optimizer Model for SAP provides a default set of resource usage metrics for each of the SAP modules. These metrics are similar to those used in SAP Quick Sizer and include both CPU and network usage metrics. Early in the design phase, architects can quickly build models using the default resource metrics to do first-cut sizing performance analysis. Later, models can be calibrated with actual measurements collected during functional testing. Scenarios can then be rerun to ensure the application is still on target to meet its performance goals. At least one problem with the above discussed systems is that they do not provide for cost contributions based on a per object and/or a per transaction basis. Accordingly there is a need for better systems and methods for providing a cost estimate for a data processing system.

Method and computer system for providing a cost estimate for sizing a computer system


The disclosure relates to methods and systems for predicting time of occurrence of future server failures using server logs and a stream of numeric time-series data occurred with a particular time window. Method performed by processor includes accessing plurality of server logs and stream of numeric time-series data, applying density and sequential machine learning model over plurality of server logs for obtaining first and second outputs, respectively, applying a stochastic recurrent neural network model over the stream of time-series data to obtain third output. The method includes aggregating first, second, and third outputs using an ensemble model, predicting likelihood of at least one future server anomaly based on the aggregating, and determining time of occurrence of the at least one future server anomaly by capturing server behavior characteristics using time-series network model. The server behavior characteristics include time-series patterns of the stream of numeric time-series data.

Most enterprise applications are organized as high-level workflows that incorporate at least one phase of associations between client devices and at least one data center server. For instance, a payment workflow can incorporate a phase for handling payment exchanges received from acquirer servers, which continues to an authorization stage for checking information received in a payment request, which at that point continues to the last checkout stage for sending the payment request to issuer servers for approval. The exchange of information in the various stages of the workflows is usually handled by computing components associated with a server. Such computing components may include hardware resources (e.g., computing devices, switches, etc.) and software resources (e.g., database applications). These resources may be used to collect and store data at various times related to a variety of measurable properties, including network, hardware, or database performance properties measured at different times.
Each computing component generates fault codes to the operations and activities performed by the server, known as server logs. The severity of the fault codes may vary from 'info' to 'critical'. Based on the severity, the server takes action to minimize the chances of server failure. In one example, server failure may occur due to, but not limited to, virus attack, physical disaster, human error, hardware/software failure, human error, failed upgrade/update, etc.
In existing frameworks, server failures are identified manually on a receptive basis using related server logs which results in a loss in both business and manual effort. Further, existing ways to deal with the computerized server failure prediction process includes fitting a likelihood distribution on normal logs (i.e., "healthy log data") and grouping logs as anomalies that deviate from the likelihood appropriation. Also, the conventional statistical methodologies for server failure prediction give false positives because of complexity in the logs, the structure of the logs. False server failure prediction may lead to false reporting, which may desensitize users to anomaly reports and/or lead to unnecessary maintenance or remedial operations being performed.
Additionally, the existing frameworks are not able to detect server failure time before its occurrence, so that immediate action cannot be taken to minimize huge losses of data and many other important computing resources.
Thus, there is a need for a technical solution for predicting server failures and time of server failures well before their occurrences using automated means to an unprecedented manner/degree, through the use of artificial intelligence and machine learning.

Methods and systems for predicting time of server failure using server logs and time-series data


A method for fabricating a high specific surface area mesoporous alumina is disclosed, which includes the following steps: (a) providing a water solution containing an aluminum salt and a fluoro-surfactant; (b) adding concentrated hydrochloric acid to adjust the PH value of the solution to about 6.0 to 8.0; (c) aging the solution at 70° C. to 110° C. for 12 to 20 hours; (d) washing the precipitate with water; (e) washing the precipitate with an organic solvent; (f) drying the precipitate; and (g) sintering the precipitate in a furnace of 500° C. to 1000° C.

1. Field of the Invention
The present invention relates to a method for fabricating an alumina, and more particularly, a method for fabricating a high specific surface area mesoporous alumina.
2. Description of the Related Art
According to pore sizes, porous materials are generally classified into microporous materials with a pore size less than 2 nm, mesoporous materials with a pore size between 2 nm and 50 nm, and macroporous materials with a pore size more than 50 nm. However, because the pore diameters of microporous materials are too small and the pores of macroporous materials are not uniformly distributed, mesoporous materials without the above defects are widely used as catalysts, carriers for catalysts, gas adsorptive agents, filter materials, etc. Among the mesoporous materials, mesoporous alumina is easy to obtain and quite cheap so that it is used a great deal. Besides, with the greater needs for specialty chemicals, mesoporous alumina is highly profitable as a high unit priced fine-purification, adsorptive material.
The conventional method for manufacturing a mesoporous alumina is mainly divided by starting material into a more expensive group of aluminum alkoxide and a cheaper group of aluminum salts such as aluminum nitrate and aluminum sulfate. Taking aluminum alkoxide as a starting material, the method for fabricating a mesoporous alumina can produce a porous alumina with its porous diameter maintained on 11 nm. However, the cost of aluminum alkoxide is high, and its specific surface area would be less than 150 m2/g when sintering at 1030° C. with the result that it would be limited in practice.
Comparing with aluminum alkoxide, taking the aluminum salts, such as aluminum nitrate, aluminum sulfate, aluminum chloride and sodium aluminate, as the starting material could lower the material cost, but the mesoporous alumina obtained by the conventional method has many defects in its porous characteristics. For example, the distribution of the pores is too wide to apply to a fine-purification system that requires high operating demands; the temperature for sintering is too low to use in petroleum cracking; the pore volume is too small, etc. Although the conventional method could overcome the above limitations by adding a PEO surfactant as a structure directing material, the pore volume of its mesoporous product is still too small.

Method for fabricating a high specific surface area mesoporous alumina

Industrial Technology Research Institute


The invention relates to processes for preparing 3-aminomethyl-3,5,5-trimethylcyclo-hexylamine (isophoronediamine, IPDA) having a high cis/trans isomer ratio. IPDA having a cis/trans isomer ratio in the range from 63/37 to 66/34 can be obtained in any desired cis/trans isomer ratio, irrespective of temperature, by reacting IPDA with H2 and NH3 in the presence of a hydrogenation catalyst. IPDA having a cis/trans isomer ratio of at least 73/27 which is an important starting material for the synthesis of polyurethanes and polyamides can be obtained by combining this isomerization process with distillative processes.

1. Technical Field
The invention relates to processes for preparing 3-aminomethyl-3,5,5-trimethylcyclo-hexylamine (isophoronediamine, IPDA) having a high cis/trans isomer ratio.
2. Discussion of the Background
IPDA is used as a starting product for preparing isophorone diisocyanate (IPDI), an isocyanate component for polyurethane systems, as an amine component for polyamides and as a hardener for epoxy resins. IPDA is customarily prepared from 3-cyano-3,5,5-trimethylcyclohexanone (isophoronenitrile, IPN) by converting the carbonyl group to an amino group and the nitrile group to an aminomethyl group in the presence of ammonia, hydrogen and customary hydrogenation catalysts. Mixtures of cis-IPDA and trans-IPDA are obtained. The two isomers have differing reactivities, which is of significance for the intended technical application. According to DE-A 42 11 454, the use of an IPDA isomer mixture consisting of above 40% of the trans-isomer and below 60% of the cis-isomer as a reaction component in polyaddition resins, in particular epoxy resins, both lengthens the pot life and reduces the maximum curing temperature. Conversely, to achieve a very high reaction rate, preference is given to IPDA isomer mixtures which have a very high cis-isomer content (≧70%). Commercially obtainable IPDA therefore has a cis/trans isomer ratio of 75/25.
Various processes for achieving a high cis/trans or a high trans/cis ratio are already known from the prior art.
According to DE-A 43 43 890, the animating hydrogenation of IPN to IPDA is effected by allowing a mixture of IPN, ammonia and a C1-C3-alcohol to trickle through a trickle bed reactor equipped with a cobalt and/or ruthenium fixed bed catalyst in the presence of hydrogen at from 3 to 8 MPa and a temperature of from 40 to 150° C., preferably from 90 to 130° C., and distillatively working up the reaction mixture to remove NH3, H2O and by-products. When an Ru supported catalyst is used, high cis/trans isomer ratios of 84/16 (total yield of IPDA: 81%) are achieved.
DE-A 43 43 891 describes a process for preparing IPDA by reacting IPN with hydrogen in the presence of ammonia and a suspension or fixed bed hydrogenation catalyst from the group of cobalt, nickel and noble metal catalysts at a pressure of from 3 to 20 MPa and a temperature of up to 150° C., and distillatively working up the reaction mixture. The reaction is carried out in two stages, and precisely defined temperature ranges have to be observed for the individual stages. A cis/trans isomer ratio of 80/20 can be achieved at an overall IPDA yield of 91.9%.
In the process of EP-A 0 926 130, the hydrogenation is carried out in the presence of an acid over catalysts which comprise copper and/or a metal of the eighth transition group of the periodic table. Both Lewis and Brönstedt acids are used; preference is given to using 2-ethylhexanoic acid. The addition of acid increases the cis/trans isomer ratio. The cis/trans isomer ratios are generally ≧70/30 at an overall IPDA yield of ≧90%.
The process of EP-B 0 729 937 is notable in that the process is carried out in three spatially separated reaction chambers using cobalt, nickel, ruthenium and/or other noble metal catalysts. Upstream of the second reactor, aqueous NaOH solution is metered in, which reduces the formation of cyclic by-products such as 1.3.3-trimethyl-6-azabicyclo[3.2.1]octane.
In the process of DE-A 101 42 635.6, which has an earlier priority date but was unpublished at the priority date of the present invention, IPDA having a cis/trans isomer ratio of at least 70/30 is obtained, starting from IPN, by using a hydrogenation catalyst in the hydrogenation step which has an alkali metal content of ≦0.03% by weight, calculated as the alkali metal oxide.
A disadvantage of the existing processes for preparing IPDA having a high cis content is the costly and inconvenient preparation of the catalysts used. In addition, these catalysts generally suffer from aging, which reduces their catalytic activity in the course of time. In order to compensate for this, the reaction temperature is usually increased, which leads, however, to a deterioration in the cis/trans isomer ratio and the selectivity and therefore to an increase in the formation of by-products. In addition, most of the processes known from the prior art are notable for a complicated reaction procedure.
A process for preparing isophoronediamine having a high trans/cis isomer ratio can be taken from DE-A 42 11 454. In this process, trans-isophoronediamine is prepared from isophoronenitrile via isophoronenitrile azine. It is also described that trans-isophoronediamine would be obtained by distilling the commercially obtainable cis/trans isomer mixture. However, since the cis-isomer occurs as the main product, this process is uneconomic.

Method for the production of isophorondiamine (ipda, 3-aminomethyl-3,5,5-trimethyl- cyclohexylamine) having a high cis/tran-isomer ratio


A near-eye display apparatus is disclosed. The near-eye display apparatus includes a lens and an optical path folding assembly. The lens is configured to receive incident light of a first image, which is projected by a micro-display, and shape the first image; the lens includes a primary optical axis and a first lens face and a second lens face which are opposed in a first direction where the primary optical axis of the lens is positioned, and both the first lens face and the second lens face are aspheric surfaces; and the optical path folding assembly is configured to receive light of the first image shaped by the lens and fold an optical path from the lens to an exit pupil of the near-eye display apparatus. By adopting the bi-aspherical lens, image quality of the near-eye display apparatus can be improved and the volume can be reduced.

An Augmented Reality (AR) display apparatus can implement fusion of an outside real scene and a virtual scene by superposing a virtual scene image displayed by the AR display apparatus into the outside real scene. Therefore, the AR display apparatus can promote a user's cognitive ability of the real world, thereby improving user experience.

Near-eye display apparatus including lens with aspheric surfaces

Beijing BOE Optoelectronics Technology Co., Ltd.


Chromatic dispersion in an optical cable is measured by applying to the cable a signal that rapidly switches between a wavelength generated by a tunable optical source and a different wavelength generated by a reference source. The two sources are modulated in such a way that a delay line phase detection scheme at the far end of the cable can accurately measure relative delay between the tunable source and the reference source. The chromatic dispersion is determined by measuring the relative delay between the two sources for several different wavelengths of the tunable source.

Very long optical fiber transmission paths, such as those employed in undersea or terrestrial lightwave transmission systems and which employ optical amplifier repeaters, are subject to decreased performance due to a host of impairments that accumulate along the length of the optical transmission path. The source of these impairments includes amplified spontaneous emission (ASE) optical noise generated in the Erbium-Doped Fiber-Amplifiers (EDFAs), nonlinear effects caused by dependence of the single-mode fiber's index on the intensity of the light propagating through it, and chromatic dispersion, which causes different optical frequencies to travel at different group velocities. Typically it is advantageous to operate long-haul transmission systems at high data rates per channel. For example, useful data rates include multiples of the Synchronous Digital Hierarchy (SDH) standard of 2.5 Gb/s. As the bit rates rise into the gigabit per second range it becomes more critical to understand the accumulated dispersion in the transmission medium.
Chromatic dispersion can directly effect the quality of the transmission by distorting the waveform in a manner that is often referred to as a dispersion penalty (for example, see P. S. Henry et al., "Introduction to Lightwave Systems," Chapter 21 in Optical Fiber Telecommunications II Academic Press 1988). Chromatic dispersion can also indirectly effect the quality of the transmission through the fiber's nonlinear index of refraction. For long-haul systems the nonlinear refractive index can couple the data signal with optical noise or with different signal channels in a wavelength division multiplexed system. Chromatic dispersion can reduce the propagation distance over which closely spaced wavelengths overlap (known as phase matching). Accordingly, chromatic dispersion can reduce the amount of interaction through the nonlinear index in the fiber. Therefore, it is important to understand the fiber cable's dispersion characteristics to satisfactorily operate an optical transmission system.
Accurate systems for measuring the chromatic dispersion in single-mode fibers are commercially available. More recently, techniques have become available that can accurately measure the dispersion characteristics of concatenated sections of single-mode fiber and optical amplifiers, such as described by Horiuchi in "Chromatic Dispersion Measurements of 4564 km Optical Amplifier Repeater System," Electronics Letters, Vol. 29, No. 1 1993 p4-6. Typically, dispersion is measured by intensity modulating a tunable optical source, and measuring the delay difference versus the transmitted wavelength. Accurate delay measurements in the picosecond range are achieved by comparing the transmitted and received timing information, usually in the form of a phase detection. Unfortunately, most of the existing techniques require the two ends of the optical cable to be located in close proximity to each other, which is not always possible before a cable has been installed and which is virtually impossible after it has been installed. Moreover, international transoceanic cables systems are often developed by more than one supplier and typically various cable sections are connected only after the different supplier's sections have been installed. Thus, the completed cable is often not available to properly measure its chromatic dispersion characteristics. Therefore, it is important to be able to measure the chromatic dispersion of installed cables, where of course, the cable ends are in different locations. It is also important to be able to determine the chromatic dispersion of installed cables because the dispersion characteristics of cables can change due to a variety of effects such as temperature and pressure and therefore, even if the cable could be accurately measured in the factory, the value of dispersion could be different in the field.

Chromatic dispersion measurement in a fiber optic cable


An empty/load changeover valve device for a railway car having a proportioning valve including a valve member via which brake cylinder pressure is supplied and released and a balance piston to which the valve member is connected. The balance piston has equal opposing pressure areas both of which are subject to brake pressure in the "load" setting of the changeover valve device, one of the pressure areas being vented in the "empty" setting, thereby establishing either a non-proportioning mode of brake control or a proportioning mode of brake control. In the "empty" setting, brake supply pressure is connected to an equalizing reservoir. A regulating valve is provided to interrupt this connection until the brake supply pressure reaches a predetermined value, thereby preventing the other pressure area of the balance piston from being unloaded sufficiently to cause an inadvertent opening of the check valve member and a consequent drop in brake cylinder pressure.

The present invention relates to an empty/load type brake control system for a railway freight car and, more particularly, to an empty/load changeover valve device that employs a proportioning valve to load-adjust the brake cylinder pressure in the empty range of car weight.
Single capacity brake equipment produces a brake shoe force that is independent of car loading, thus making it difficult to achieve desirably higher braking ratios for a loaded car without exceeding an empty car braking ratio sufficient to cause wheel slide. Sliding wheels are undesirable from the standpoint of reduced braking retardation, and slid-flat wheels.
Special brake equipment is therefore necessary to increase the loaded car braking ratio without incurring the consequence of a wheel slide condition when braking an empty car. Such equipment automatically adjusts brake shoe force according to the load condition of the car. These special equipments fall into two primary categories, dual capacity empty/load braking and multiple capacity or continuously variable braking.
In the dual capacity empty/load equipment, there are just two settings, one for "empty" braking and one for "load" braking, the changeover point between the "empty" and "load" settings being selected at some predetermined car weight, usually at 20% of the full load capacity weight. In arbitrarily selecting this changeover point, it will be appreciated that a given car can be generally under-braked by the reduced brake pressure when the car weight is in the upper end of the "empty" weight range, since essentially the same adhesion demand is available at the lower end of the "load" weight range at which maximum braking force is capable of being supported without sliding the car wheels.
In the variable load type equipment, braking pressure is proportioned according to the actual load, generally throughout the full range of car loading. It will be appreciated, however, that the proportioned brake pressure is selected in accordance with the maximum brake pressure (emergency) capable of being developed from the maximum running pressure normally carried by a train (110 psi). Therefore, when making relatively light service brake applications or when making a maximum brake application from a relatively low running pressure (70 psi), the proportioned brake pressure may be far less than that capable of being supported by the adhesion demand. Accordingly, less than optimum brake efficiency is realized under certain brake conditions with variable load type brake equipment, as well as single capacity equipment, in order to protect against wheel sliding on an empty car under maximum braking conditions.
In U.S. Pat. No. 5,005,915, an empty/load valve device is disclosed comprising a balance piston having equal opposing pressure areas, the balance piston being connected to a supply check valve via which brake pressure is connected from the car control valve device to the brake cylinder and released therefrom. One pressure area of the balance piston is subject to the upstream brake pressure under all conditions of car loading, while the opposing pressure area is either pressurized or de-pressurized depending upon the car being in an "empty" or "load" condition. In the "empty" condition, a differential pressure is created across the balance piston to establish a proportional mode of brake control in which the brake cylinder pressure is reduced by a certain percentage. A proportioning spring acts on the balance piston to vary this percentage of proportioning according to the actual car load during "empty" condition.
However, since an equalizing reservoir is required in such proportional type dual capacity equipments, to maintain proper equalization pressure at the car control valve and thereby prevent an over-reduction of brake pipe pressure from producing brake cylinder pressure in excess of the desired empty brake cylinder pressure, it is possible under certain operating situations to experience an undesirable drop in brake cylinder pressure during changeover from "load" to "empty" condition of brake control. For example, should the buildup of upstream brake cylinder pressure supplied by the car control valve be terminated when changeover between "empty" and "load" occurs, the connection of upstream brake pressure to the previously vented equalizing reservoir could create such a drop in the upstream pressure that the pressure differential across the balance piston would no longer be able to hold the supply check valve closed against the proportioning spring. The sufficiency of this reduction in the upstream brake pressure could arise, for example, where the pipe volume between the car control valve and empty/load changeover valve is relatively small as compared to the volume of the equalizing reservoir. Consequent opening of the supply check valve by the proportioning spring, in turn, connects the brake cylinder pressure to the equalizing reservoir, resulting in the aforementioned undesirable drop in brake cylinder pressure.

Empty/load changeover valve for railway car


In a control apparatus for performing serial data communication, a transmitting section includes a memory to store data for other control apparatuses and a transmission control section to generate a frame containing the data and memory storage information indicating a storage position of the data in buffer memories of the receiving sections of the other control apparatuses. A receiving section includes a reception control section to extract the memory storage information and the data from the frame, a buffer memory to store the extracted data, and a data-storage processing section to store the extracted data in an address of the buffer memory designated by the memory storage information. The memory storage information is set for each of the control apparatuses. A control section reads out the data from an address of the buffer memory for each of the other control apparatuses.

In a control apparatus including a controller that controls the entire apparatus and a plurality of motors, in general, the controller and the motors are connected by serial communication. Because the devices are connected by the serial communication, it is possible to realize wire-saving and improvement of maintainability of the entire apparatus.
In general, the motors include motors and motor driving devices. The serial communication is performed between the controller and the motor driving devices. By the serial communication, moving commands for positions, speeds, torques, and the like are transmitted from the controller to the motor driving devices, and control state amounts such as positions, speeds, and driving current values of the motors are transmitted from the motor driving devices.
In such serial communication for driving control for the purpose of motor control, the controller and the motor driving devices transmit the moving commands and the control state amounts to each other at a fixed interval to stably perform the operation of the motors. The controller performs serial communication control with the fixed interval set as a communication period. The controller sequentially updates the moving commands and transmits the moving commands to the motor driving devices at the fixed communication period. The controller performs the motor control such that the motor driving devices perform reception processing at every communication period and follow commands extracted from received data. Consequently, the controller can control the motors with desired positions, speeds, torques, and the like.
According to necessity, the controller applies, at every communication period, reception processing to the control state amounts sequentially updated and transmitted from the motor driving devices at the fixed communication period, applies necessary control processing to the motor driving devices, based on necessary control state amounts extracted from received data, reflects a result of the control processing on next motor control commands, and controls the entire motor driving devices.
In the serial communication for driving control, because the commands and the state amounts are sequentially updated as explained above, a reception control section in the serial communication updates received data at every communication period. In some case, an FIFO (First In, First Out) buffer is used for a buffer memory, which stores the received data, to retain a plurality of received data at one communication period or retain a plurality of received data at a plurality of communication periods.
When the reception control section retains a plurality of received data at a plurality of communication period, in the serial communication for driving control, once communication between apparatuses is started, a specified communication frame is periodically transmitted at a specified communication period. Therefore, the reception control section periodically stores received data of communication frames in the buffer memory for reception according to a management table for managing a storage position of the received data (see, for example, Patent Literature 1).
As in the normal serial communication, in the serial communication for driving control, when the communication frame is transmitted, the communication frame is accompanied by check data for detecting data corruption on a communication path. A reception side checks reliability of received data from the received data and the check data and retains a result of the check as a received data state. When a plurality of packets of received data is retained, it is necessary to retain received data states by the amount of the retained received data (see, for example, Patent Literature 2).
The communication frame of the serial communication is transmitted with specific bit patterns added to the start and the end of data to be transmitted. The specific bit pattern at the start is referred to as start flag. The bit pattern at the end is referred to as end flag. A receiving section identifies the start flag to start reception processing for the communication frame. The receiving section recognizes, with the end flag, the end of the communication frame to receive one communication frame.

Control apparatus, control system, and communication method for controlling one or more motors in serial communication with a controller


Provided is a display panel having a plurality of pixels arranged in a matrix of rows and columns. Each of the pixels is composed of a plurality of first sub-pixels emitting light of different colors. Each of the first sub-pixels is composed of a plurality of second sub-pixels emitting light of the same color. Each of the second sub-pixels includes: a first electrode; a second electrode above the first electrode; and a light-emitting layer between the first electrode and the second electrode.

In recent years, organic EL panels making use of electro-luminescence in organic materials have been actively developed. An organic EL panel has a plurality of pixels arranged in a matrix of rows and columns. The number of pixels varies depending on resolution. For example, resolution of Full HD is 1920×1080, and resolution of 4K2K is approximately 4000×2000. Each pixel is composed of a plurality of sub-pixels emitting light of different colors. The colors of light are typically red (R), green (G), and blue (B). Full HD is currently popular as a standard for resolution of a digital television. As a next generation standard, 4K2K having a higher resolution than Full HD has been proposed. The number of pixels of 4K2K is approximately four times the number of pixels of Full HD.
Meanwhile, display panels can have display defects referred to as an unlit dot, a dark dot, and a bright dot. The unlit dot refers to a case where a light-emitting element in a sub-pixel is constantly off. The dark dot refers to a case where a light-emitting element in a sub-pixel constantly emits dim light. The bright dot refers to a case where a light-emitting element in a sub-pixel constantly emits bright light.
It is extremely difficult to reduce the number of display defects to zero in manufacturing the display panels. Thus, a display panel having some display defects is usually shipped as a non-defective product if the number and distribution of the display defects are within an allowable range. The allowable range for the display defects is defined for example in IS013406-2.

Display panel and production method for same


A heating, ventilation, and air conditioning (HVAC) system includes an expansion device disposed between a condenser and an evaporator of a vapor compression system and a control panel communicatively coupled to the expansion device. The control panel is configured to: determine a liquid refrigerant level set point of the condenser based on parameters of the vapor compression system, provide a first control signal to increase an opening of the expansion device in response determining that the current liquid refrigerant level in the condenser is greater than a determined liquid refrigerant level set point of the condenser, and provide a second control signal to decrease the opening of the expansion device in response to determining that the current liquid refrigerant level in the condenser is less than the determined liquid refrigerant level set point of the condenser.

This application relates generally to chiller systems, and, more specifically, to redistributing refrigerant charge in a vapor compression system to improve efficiency and reliability.
Chiller systems and other types of vapor compression systems utilize a working fluid, typically referred to as a refrigerant, which changes phases between vapor, liquid, and combinations thereof, in response to being subjected to different temperatures and pressures associated with operation of the vapor compression system. Within a water-cooled chiller system, the refrigerant is vaporized by relatively warm water traversing conduits (e.g., boiling tubes) that extend through the evaporator, and the refrigerant is condensed by a coolant traversing conduits (e.g., condensing tubes) that extend through the condenser. In traditional chiller designs, the liquid refrigerant level in the condenser is controlled to a fixed value, while the liquid refrigerant level in the remainder of the vapor compression system (e.g., the evaporator) generally fluctuates based on this fixed liquid refrigerant level in the condenser.

Redistributing refrigerant between an evaporator and a condenser of a vapor compression system


A bougie is disclosed with a body, and a first depth indicator and a second depth indicator on the body. The body has a first end, a second end, and at least one surface extending between the first and second ends. The first depth indicator is spaced a first distance from the first end and indicates a first predetermined depth range such that the first end is positioned a first predetermined insertion range past the mouth of the patient when the body is positioned into the mouth of the patient. The second depth indicator is spaced a second distance from the second end and indicates a second predetermined depth range such that the second end is positioned a second predetermined insertion range past the mouth when the body is positioned into the mouth of the patient.

A bougie is used to assist placement of an endotracheal tube in a patient's trachea to aid in oxygenation of the patient. The bougie is placed within the trachea of the patient as a guide over which a tube is passed. Often prior to procedures requiring anesthesia, a bougie is inserted between the vocal cords by a user using a laryngoscope. An endotracheal tube is passed over the bougie into the trachea of the patient. After placement of the endotracheal tube, the bougie is removed. Generally, the bougie is used in situations in which the endotracheal tube cannot be passed into the trachea directly or easily
Bougies are generally formed from flexible materials, being either straight or curved. Some bougies are formed from self-lubricating materials such as the bougie described in U.S. Pat. No. 8,161,967, while others require a user to lubricate a surface of the bougie to insert the bougie into the trachea of the patient, such as the Sun-Med Bougie Introducer™ (Sun-Med™ Largo, Fla., USA.).
A laryngoscope may be used to assist with the placement of a tube into a patient's trachea to aid with the oxygenation of the patient. The laryngoscopes often use either a straight or curved blade that allows for the visualization of the patient's vocal cords which are used for locating the patient's larynx and subsequently the trachea. This reduces the risk of intubating the patient's esophagus which would cause air to be blown into the stomach, causing stomach distension and vomiting not to mention depriving the patient of oxygen, and possibly death.
The presence of blood, saliva, and vomit secretions can interfere with the proper placement of the laryngoscope, further necessitating the use of the bougie. Further, in emergency situations, the proper placement of the laryngoscope must be done in a quick and safe manner. Often determining a proper depth of insertion for a bougie may be difficult, for example in emergency situations or in the presence of obscuring fluids or objects. Despite good technique by the health care provider utilizing the bougie, there is still a need for an improved bougie that can be used in difficult or emergency situations in and out of a medical facility while being reliably positioned at a proper insertion depth.

Bougie and method of making and using the same


A base station for use in a wireless network that communicates with wireless mobile stations. The base station comprises: 1) a transceiver for transmitting forward channel data to a first mobile station via a beam-forming antenna array; and 2) a beam-forming circuit for maximizing data throughput to the first mobile station by jointly optimizing i) selection of a beam for transmitting the forward channel data to the first mobile station, ii) a level of Walsh code multiplexing of the forward channel data, and iii) a modulation scheme used to transmit the forward channel data.

Wireless communication systems have become ubiquitous in society. Business and consumers use a wide variety of fixed and mobile wireless terminals, including cell phones, pagers, Personal Communication Services (PCS) systems, and fixed wireless access devices (i.e., vending machine with cellular capability). Wireless service providers continually try to create new markets for wireless devices and expand existing markets by making wireless devices and services cheaper and more reliable.
In code division multiple access (CDMA) networks, for example, adaptive antenna arrays have been developed to increase the capacity and quality of calls handled within CDMA networks. Adaptive antenna arrays use beam-forming techniques to provide directional antenna beams in the downlink from the base station to the wireless terminal. For example, angle of arrival (AOA) information determined from a received signal at an adaptive antenna array may be used to determine beam-forming coefficients that are used to generate a narrow beam spatially directed to a specific wireless terminal in the downlink (or forward channel). This provides improved capacity and signal quality. The narrow beam carries a traffic signal intended for the specific wireless terminal.
The prior art discloses a number of techniques for maximizing the throughput of a base transceiver station. Many of these techniques attempt to maximize throughput by selecting an optimum value of a particular variable, such as Walsh multiplexing (i.e., bits per Walsh code), or beam selection, or modulation rate. However, there are significant drawbacks to these conventional techniques. For instance, conventional CDMA base stations use a static table to look up the optimum discrete beamwidth for a specific location. The table is built during a specific learning or calibration phase. Once the table is built, the base station simply lookups the beamwidth for that location from the table.
However, using such a static table prevents the base station from compensating for changing conditions. The prior art systems either do not dynamically detect new beams or cannot detect optimum beams if the modulation scheme is modified. Also, the prior art techniques optimize the variables (i.e., Walsh multiplexing, modulation rate, beam selection) separately. Thus, the prior art techniques provide a local optimum value, but not a global optimum value.
Therefore, there is a need in the art for an improved downlink (or forward channel) beam-width optimizing system that is able to dynamically adapt to changing traffic conditions. In particular, there is a need for a base station that is capable of maximizing throughput by jointly optimizing more than one variable.

System and method for maximizing throughput in the forward packet data channel of a 1xEVDV wireless network


A light source unit is provided which includes a light source with a plurality of light emission portions two-dimensionally arranged; a substrate on which the light source is mounted; a first support portion supporting the substrate; a bias member biasing the substrate towards the first support portion; a coupling element coupling a light beam emitted from the light source; a second support portion supporting the coupling element; and a holding member holding a position of the substrate relative to the first support portion.

1. Field of the Invention
The present invention relates to a light source unit emitting a light beam, an optical scan apparatus scanning a scan surface with a plurality of light beams and an image formation apparatus incorporating such an optical scan apparatus.
2. Description of Related Art
In the prior art, an image formation apparatus forming images by Carlson process is known. For example, such an image formation apparatus scans the surface of a rotating photoconductive drum with a light beam to form an electrostatic latent image, visualizes the electrostatic latent image as a toner image, and fuses the toner image on a sheet of paper as a recording medium to form an image. This type of the image formation apparatus has been popularly used in simple printmaking for an on-demand print system. There has been increasing demand for high-density images and high-speed image outputs.
Japanese Laid-open Patent Application Publication No. 2003-211728, for example, discloses an image formation apparatus which has a light source such as a vertical cavity surface emitting laser (VCSEL) array with plural light emission portions two-dimensionally, monolithically arranged and is capable of concurrently scanning a scan surface with plural light beams.
Such a vertical cavity surface emitting laser array used in the image formation apparatus is composed of the light emission portions on a chip contained in a package, which is made of a ceramic material or the like. For mounting the light emission portions on a circuit board by soldering, the mounted light emission portions are not uniform in height. With such non-uniformity in height, the surface of the package is inclined relative to the surface of the circuit board. As a result, positional relations between the individual light emission portions and the circuit board surface may not be the same.
In such a light source unit the positions of optical elements such as a coupling element (lens) are often determined on the basis of the circuit board surface. In this case, there will be a problem that the positional difference between each light emission portion and the circuit board surface leads to a positional difference between the optical elements and each light emission portion.
For prevention of such a problem, Japanese Laid-open Patent Application Publication No. 2004-6592 discloses a method for positioning the package surface relative to the optical elements in a semiconductor laser unit by elastically bending the circuit board to bring the package into contact with the surface of a support member by pressure.
However, such a method still has a problem that enforcedly bending the circuit board causes solder of electric components mounted thereon to be peeled off, which may adversely accelerate deterioration of the laser unit over time, for example.

Light source unit, optical scan apparatus, and image formation apparatus


Various datacenter or other computing center control apparatus and methods are disclosed. In one aspect, a method of computing is provided that includes defining plural processor performance bins where each processor performance bin has a processor performance state. At least one processor is assigned to each of the plural processor performance bins. Processor performance metrics of at least one of the processors are monitored while the at least one of the processors executes an incoming task. Processor power is modeled based on the monitored performance metrics. Future incoming tasks are assigned to one of the processor performance bins based on the modeled processor power.

1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for controlling the behavior of multiple processors in a distributed computing system.
2. Description of the Related Art
Explosive growth in data center construction has fueled a need for energy consumption awareness, both from the perspective of server power and data center cooling power. Modern servers routinely contain multiple processors and data centers scores or hundreds of servers. Spread out over hundreds of servers, processor power consumption can be enormous. Large numbers of servers and processors dissipate heat and require significant amounts of chilled air to both avoid thermal performance or shutdown issues and to operate at more electrically efficient temperatures. The power consumed by servers directly affects the power required by auxiliary equipment and cooling. Thus, server power conservation translates into overall data center power savings.
Central processing units (CPUs) are organized as nodes with multiple nodes combined into a cluster. One existing solution to increase power consumption efficient utilizes a local algorithm(s) that attempts to maximize power efficiency utilizing information from the processing node. These solutions that rely solely on the local governor provided by the CPU vendor are consequently local to a node and not necessarily related to the cluster workload.
Another prior solution utilizes heterogeneous clusters composed of processors having distinct power and performance characteristics. These approaches use rough heuristics to direct workloads to the processors with the expected best match. Such approaches are static in nature, since the cluster configuration is static, and do not take dynamic workload execution characteristics into consideration. Other previous solutions override the local CPU governor and control the power states globally. Due to the global nature, these solutions are less likely to be able to react quickly to local changes in the power demands.
Modern processors feature Dynamic Voltage and Frequency Scaling (DVFS). Power-aware optimizations make use of this feature to trade-off power and performance. Each voltage and frequency operating point represents a power-saving state of the processor. There are multiple levels of power conservation, the deeper the state the higher the savings, though with an increasing time penalty for state switching. Such processors are equipped with the aforementioned local governors that react to microarchitectural utilization parameters and control processor power states. Such governors are able to react quickly to changing architectural demands, however the decision process is made utilizing only local information.
Another prior solution involves asymmetric clusters consisting of nodes of varying computation capabilities, and corresponding power envelopes. One cluster is composed of power-efficient and lower-performance Atom processors, and more high-performance (and power-hungry) Sandy Bridge processors. This technique utilizes a heuristic to classify each task as either CPU-bound or I/O-bound. CPU-bound tasks are scheduled to high-performance (and thus higher power consumption) processors, whereas I/O tasks are scheduled to the lower-performance (lower power consumption) nodes.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.

Combined dynamic and static power and performance optimization on data centers