A sidelobe canceller for a transducer arrangement such as an antenna or sonar transducer uses a main transducer and one or more auxiliary transducers. The auxiliary received signals are weighted by FIR filters or by multipliers, and the weighted auxiliary signals are summed, and the summed, weighted auxiliary signals are subtracted from the main signal to produce the desired low-sidelobe main signal. The weighting signals are generated in conventional manner from intermediate weighted signals. The intermediate weighting signals are produced by a reduced-hardware arrangement. When FIR filters are used, the signals being multiplied by weights include mutually delayed samples.

This invention relates to sidelobe cancellers for sensing systems such as radar and sonar, and more particularly to improved weight determination arrangements which reduce redundant processes and thereby allow higher operating speed, reduced or simplified weight determination hardware, or both.
FIG. 1 is a simplified block diagram of a radar system in accordance with the invention. In FIG. 1, a first or main antenna 10 is coupled by a diplexer 12 to a transmitter (TX) 14 and to a receiver 16. Main antenna 10 produces a receive "beam" designated as 18, which includes a main lobe 20, and also includes a plurality of sidelobes 22 by which energy may be received from directions other than the main lobe. Representative first and second ancillary or auxiliary antennas 24a . . . 24n are located near main antenna 10, and respond generally to signal from the direction of the main lobe and from other directions. Each auxiliary antenna 24a . . . 24n is coupled to an individual receiver, illustrated as receivers 28a . . . . 28m. The receivers amplify, frequency convert, and perform analog-to-digital conversion, and other known functions as may be required to produce signals representative of amplitude and phase. The received signals from main receiver 16 are coupled to a delay (D) 30, and to the noninverting (+) input port of a summing circuit 32. The received signals from receivers 28a . . . 28m are applied to input ports of finite impulse response (FIR) filters 34a . . . . 34p associated with the receivers.
The received signals from auxiliary receivers 28a . . . 28m of FIG. 1a are also applied over buses 29a . . . 29s to a plurality of delay lines illustrated as blocks 38a . . . 38r. Representative delay line 38a is illustrated in FIG. 1c, and uses a cascade of delay elements represented as shift registers (S) 138a, 138b, and 138c to produce four time-sequential samples of the received signals on output data paths a1, a2, a3, a4 of a of bus 39a for application to weighting signal generator 40 of FIG. 1a. Weighting signal generator 40 processes the a1 . . . a4 sequential signal samples from delay 38a, the u1 . . . u4 sequential signal samples from delay 38r, other sets of sequential signal samples from other ones of the delays 38 (not illustrated), and the single delayed main signal sample from delay 30, to produce intermediate weighting signals on data paths 36a . . . . 36g. The intermediate weighting signals on paths 36a . . . 36p are processed in processor 50 to form weighting coefficients. The weighting coefficients are applied over buses 35a . . . 35q to FIR filters 34a . . . 34p. FIR filters 34a . . . 34p filter the complex received signals received over paths 29a . . . 29s from receivers 28a . . . 28m under the control of weighting signals, received over buses 35a . . . . 35q from weighting signal processor 50. The FIR filters filter the auxiliary signals originating from auxiliary antennas 24a . . . 24n. The filtered auxiliary signals are applied from FIR filters 34a . . . 34p to a summing (Σ) circuit illustrated as a block 42. The summed, filtered auxiliary signals are applied from summing circuit 42 to the inverting (−) input of summing circuit 32, where they are subtracted from the main signal to produce on data path 52 the desired signal, which represents the main lobe signals in which the unwanted signals arriving from directions other than that of main lobe 20 as suppressed.
FIG. 1b illustrates details of representative FIR filter 34a of FIG. 1a. In FIG. 1b, each FIR filter includes a tapped delay line, multipliers and a summer which together provide frequency response shaping to improve cancellation performance. In FIG. 1b, a tapped delay 134 includes shift registers 110, 112 and 114, which delay the signal from receiver 28a of FIG. 1a. A set of four multipliers 120, 122, 124 and 126 is coupled to receive mutually delayed signal samples from delay line 134. Each multiplier receives an independent weighting coefficient over bus 36a from weighting signal processor 50. As a result, the same signal sample moves in sequence from multiplier to multiplier within FIR filter 34a of FIG. 1b. More specifically, each undelayed sample arriving on path 17 is applied to multiplier 120 or multiplication by a first weighting coefficient. At the next clock cycle, shift register 110 stores the sample and makes it available to multiplier 122, and a new sample arrives at the input of shift register 110 and is applied to multiplier 120. During succeeding clock cycles, the original sample moves from shift register to shift register within delay line 134, being applied in succession to input ports of multipliers 120, 122, 124 and 126, and being multiplied therein by one of the weighting coefficients. At any moment, the sum signal generated at the output of summing circuit 128 of FIG. 1b is the sum of a plurality of time-sequential samples of the received auxiliary signals, each multiplied by a different one of the weighting coefficients (although one or more of the weighting coefficients may happen to have the same value).
FIG. 2a is a simplified block diagram of a radar system similar to that of FIG. 1a, but in which simple multipliers are used instead of FIR filters. Elements of FIG. 2a corresponding to those of FIG. 1a are designated by the same reference numerals. In FIG. 2a, weighting signal generator 240 has fewer input ports than weighting signal generator 40 of FIG. 1a, and consequently has fewer levels of calculation, but is otherwise identical. The intermediate weighting signals produced by weighting signal generator 240 of FIG. 2c are applied over data paths 236a . . . 236q processor 50, which generates the desired weighting coefficients for application to multipliers 234a . . . 234p for multiplying the auxiliary received signals. The multiplied auxiliary received signals are applied to summing circuit 42, and the summed, weighted auxiliary signals are subtracted from the main signal in summing circuit 32.
FIG. 2b is a simplified block diagram of intermediate weighting signal generator 240 of FIG. 2a. Weight generator 240 of FIG. 2b is illustrated for the case in which a single input signal or vector x5 originating from main antenna 10 of FIG. 2b is received by way of receiver 16, together with four auxiliary signals x1, x2, x3 and x4 originating from auxiliary antennas 28a . . . 28m. The arrangement of FIG. 2b is similar to, but not identical with that described at Chapter 4 in the Doctoral Dissertation in Electrical Engineering entitled, "Time and Order Recursive Multichannel Adaptive Filtering Techniques," by Stanley Man Fung Yuen, presented to the faculties of the University of Pennsylvania in 1988.
It should initially be noted that the structure of weighting signal generator 240 of FIG. 2b can be used to directly generate the desired main signal free of the signals from unwanted directions. This is accomplished by, in the structure of FIG. 2b, taking signal x5 to be the main signal, and x1–x4 to be the auxiliary signals. In the arrangement of FIG. 2b, the main signal x5 is ultimately decorrelated or orthogonalized with the x1, x2, x3 and x4 vectors. The x1, x2 . . . x5 signals are applied to a first row of processors including processors designated A and B, described further in relation to FIG. 2c. The outputs from Row 1 are residues q21 to q51, which are used as inputs to the next row of decorrelators. Each residue q represents an input vector x decorrelated or orthogonalized from one or more of the other vectors x. For example, q21 produced by B processor 2121,2 represents vector x2 decorrelated from vector x1. Similarly, residue q32 produced at the output of B processor 2122,3 represents vector x3 decorrelated from vectors x1 and x2. This iterative process continues until the last residue is obtained, which in this case is q54, which is the residue of the main signal vector X5 which has made orthogonal to the remainder of the input vectors x1 . . . . x4. Residue q54 is made available on a path 208 of FIG. 2a and may be directly applied to further processing and display devices (not illustrated) rather than the difference signal from data path 52.
For the simple, illustrative case of FIG. 2b, taking the desired signal from conductor 208 may be appropriate. However, as mentioned below, it may be desirable to use weighting signals generated as intermediate products in the structure of FIG. 2b to produce the weighting signals for multipliers 234a–234p of FIG. 2a. As part of their operation, each B processor produces an intermediate weighting coefficient lxy, where subscript x describes the row, and subscript y describes the column.
More particularly, in FIG. 2b, the x1 auxiliary signal is applied as an input to A processor 2101, and to an input port of each of B processors 2121,2, 2121,3, 2121,4 and 2121,5. Auxiliary signal x2 is applied to another input port of B processor 2121,2, auxiliary signal x3 is applied to another input port of B processor 2121,3, and auxiliary signal x4 is applied to another input port of B processor 2121,4. Main signal x5 is applied to another input port of B processor 2121,5. A processor 2101 and B processors 2121,2 . . . 2121,5 are included within a first row (Row 1) of generator 240. In Row 1, the processed output of A processor 2101, which is designated L1,1, is applied to further input ports of each of B processors 2121,2, 2121,3, 2121,4 and 2121,5 of Row 1. The B processors of Row 1 of FIG. 2a produce intermediate weighting coefficients l and residues q. The residue produced by main B processor 2121,5 is designated q51, which is applied to an input of a B processor 2122,5 of Row 2. Processor 2121,2 of Row 1 produces a residue designated q21 which is applied to the input of an A processor 2102 of Row 2, and to inputs of B processors 2122,3, 2122,4, 2122,5 of Row 2. The residue produced by Row 1 B processor 2121,3 is designated q31, which is applied to an input port of Row 2 B processor 2122,3. The output signal produced by Row 1 B processor 2121,4 is designated q41, and is applied to an input port of Row 2 B processor 2122,4.
In Row 2 of FIG. 2b, the output signal of A processor 2102, which is designated L2,2, is applied to input ports of B processors 2122,3, 2122,4, 2122,5. The Row 2 B processors 2122,3, 2122,4, and 2122,5 each produce a residue. These residues are designated q32, q42, and q52, respectively. In FIG. 2b, residue q32 produced by B processor 2122,3 of Row 2 is applied to the input port of A processor 2103 of Row 3, and to input ports of B processors 2123,4 and 2123,5 of Row 3. Residue q42 produced by B processor 2122,4 of Row 2 is applied to an input port of B processor 2123,4 of Row 3. Residue q52 produced by B processor 2122,5 of Row 2 is applied to an input port of B processor 2123,5 of Row 3. Also within Row 3, the output, designated L3,3 produced by A processor 2103 is applied to further input ports of B processors 2123,4 and 2123,5. B processors 2123,4 and 2123,5 of Row 3 produce residues q43 and q53, respectively.
The q43 residue produced by B processor 2123,4 of Row 3 of FIG. 2b is applied to the input port of A processor 2104 of Row 4, and to B processor 2124,5. The q53 residue produced by B processor 2123,5 of Row 3 is applied to another input of B processor 2124,5 of Row 4. Also in Row 4, the output signal, designated L4,4, of A processor 2104 is applied to an input port of B processor 2124,5. B processor 2124,5 produces the final desired residue q54, which is the residue of the main signal vector x5 which has been made orthogonal to the rest of the input vectors.
As so far described, the arrangement of FIG. 2b generates the desired orthogonalized main signal. When the process of cancellation must be applied to large numbers of range cells, the above-described method may not be efficient, and may introduce speed limitations.
An alternative method for using the structure of FIG. 2b in the radar system of FIG. 2a is to ignore the signal on data path 208, and use only a subset of the range cells to generate weighting signals in the arrangement of FIG. 2a, which are then applied to the multipliers of FIG. 2a for all range cells. To generate the weights in this manner, sets of intermediate weighting coefficients designated generally as 1 are derived from weighting signal generator 240 of FIG. 2b. An intermediate weighting coefficient designated 1xy is generated in each B processor during generation of the residues, where subscript x represents the row in which the B processor is located, and subscript y represents the column. These intermediate weighting coefficients are extracted in sets at each row of the structure of FIG. 2b, and are further processed in processor 50 to produce the weights which are applied to multipliers 234a . . . 234p of FIG. 2a. The processing required in processing block 50 of FIG. 2b to form the weighting coefficients from the intermediate weight coefficients for application to multipliers 234a . . . 234p is well known in the art and is described in, for example, the aforementioned Yuen dissertation. This technique uses some of the range cells to produce weighting coefficients which are applied to the signals of all the range cells, thereby reducing the amount of processing.
FIG. 2c illustrates details of the A and B processors of FIG. 2b. More particularly, for definiteness, FIG. 2c illustrates representative A processor 2101 of FIG. 2b, and B processor 2121,2.
In FIG. 2c, the x1 auxiliary signal is applied in batches to a first input port of a summing multiplier (XΣ) 222 of a processor 2101,1 and to a processing block 220 designated by an asterisk (*) for taking the complex conjugate of input signal x1. The complex conjugate is applied to a second input port of summing multiplier 222. Such processing circuits are well known in the art, and are described, for example, in U.S. Pat. No. 4,941,117 issued Jul. 10, 1990 in the name of Yuen. The output signal L1,1, produced by A processor 2101 of FIG. 2c is applied to an input port 233 of B processor 2121,2, together with the x1 auxiliary signal applied to input port 232 and the x2 auxiliary signal applied to input port 231.
In B processor 2121,2 of FIG. 2c, the x1 signal applied to input port 232 is applied to a delay circuit or buffer 240 and to a complex conjugate processor 238, which produces the complex conjugate of x1 and applies it to an input port of summing multiplier 258. The x2 auxiliary signal input is applied to an input of a delay or buffer circuit 244, and to a second input of summing multiplier 258. Summing multiplier 258 takes the sum of products, and applies the result to the input of a dividing (÷) circuit 246, where the signal from summing multiplier 258 is divided by the L1,1 signal applied to input port 233 of B processor 2121,2. The divided signal, designated l1,2 is applied to a multiplier 242, where it is multiplied by the delayed x1 signal from buffer 240, to produce a signal which is applied to the inverting (−n) input port of a summing circuit 248. The non-inverting input port of summing circuit 248 receives delayed x2 signal from buffer 244, and combines it with the output of multiplier 242 to produce at an output port 254 of B processor 2121,2 a residue signal q21 for application to other processors as described in conjunction with FIG. 2b. The divided signal l1,2 produced at the output of dividing circuit 246 is the desired intermediate weighting signal produced by B processor 2121,2. Each of the other B processors of Row 1 of weighting signal generator 240 of FIG. 2b produces its own intermediate weighting coefficient, and taken together, the four weighting coefficients l1,2, l1,3, l1,4 and l1,5 produced by the B processors of Row 1 constitute one set of intermediate weighting coefficients.
Similarly, the three intermediate weighting coefficients l2,y of Row 2 of FIG. 2b are extracted as one set, the two l3,y of Row 3 constitute one set, and the set of Row 4 includes the single intermediate weighting coefficient l4,5.
The system of FIGS. 2a, 2b and 2c produces both the desired orthogonalized residue signals q, and the intermediate weighting coefficients lx,y, which can also be used to produce weighting signals for generating orthogonalized signals. Thus, the arrangement produces more information than the minimum required to produce the desired result. It would be desirable to reduce the amount of processing to produce the desired weight signals.
A further inefficiency exists when the scheme of FIGS. 2b and 2c is used in an arrangement such as that of FIG. 1a. When used to process sets of auxiliary signals such as a1 . . . a4; . . . ;u1 . . . u4; of FIG. 1a, the processing arrangement of FIG. 2b treats all its inputs as independent, even though the signals of any set of inputs (e.g. a1 . . . a4) are merely mutually delayed from each other, as described below in conjunction with FIG. 5. Thus, in the context of FIG. 1a, a weighting signal generator 40 operating as described in conjunction with FIG. 2b performs more than the minimum amount of processing. In such a case, the input signals to weighting signal generator 240 of FIG. 2b may be processed to take advantage of the time relationship of the signals in the shift registers of the FIR filters.

High speed weighting signal generator for sidelobe canceller


A means of varying both the opening and closing angle of internal combustion engine cam-operated valves by means of a mechanism which responds to the torque applied to the camshaft by the valve springs in such a way that the opening angle of the valves is retarded and the closing angle advanced and in which a means of inhibiting this operation can be incorporated.

1. Field of the Invention
This invention relates to variable valve timing for an internal combustion engine.
2. Discussion of Prior Art
In an internal combustion engine of the four-stroke (Otto cycle) type the phase of the engine cycle during which the inlet and exhaust valves are open is usually referred to as valve timing and is quoted as the opening and closing angles for both the inlet and exhaust valves before or after the point at which the piston reaches "top dead center" (TDC) or "bottom dead center" (BDC). In a conventional engine these angles are fixed and do not vary over the entire engine speed and load range.
The fixed valve timing is a compromise setting over most of the engine operating range because the dynamic behavior of the gas flows in the cylinder and through the valves varies considerably over the entire range. For this reason the fixed valve timing can only be correct for some required engine performance characteristic (eg. minimum exhaust emissions, maximum power, lowest fuel consumption) at one particular engine speed and load situation and over the rest of the range poorer performance must be accepted.
This behavior of the fixed-valve-timing internal combustion engine has been known almost since its invention but the simplicity of fixed valve timing has led to its retention, with individual engine designs being 8 compromise aimed at some particular performance characteristic in which some desirable characteristics are sacrificed for others; for example an engine design might aim for high output power at high speed at the expense of low speed tractability.
There is a great deal of published information and patents on means of varying the valve timing of an engine. The methods that are described in these vary widely but one group of mechanisms change the valve timing by changing the phase of the camshaft relative to the crankshaft. All of these mechanisms have a source of power separate from the camshaft to effect this variation in phase.


A permanent magnet degausser includes at least one magnetic field generator comprising magnetic elements arranged near a media conveyance path and a conveyor for transporting magnetic media through a magnetic media conveyance path. A passive belt or protector plate may be provided to assist the passage of the magnetic media through the applied magnetic field. The conveyor may be a continuous motion conveyor belt including cleats for holding the magnetic media or a reciprocal media conveyor including magnetic storage media bin. The magnetic field generator may include permanent magnets of varying intrinsic coercivities and/or remanences.

Prior degaussers typically require manual manipulation of magnetic storage media, such as magnetic storage tape, hard disk drives, and the like, by a user in between passes of the media through a magnetic field to achieve uniform multidirectional magnetic field exposure for optimum erasure performance. The raw magnetic strength applied to certain magnetic storage media such as hard disk drives can overcome the lack of multidirectional exposure in the plane of the disk along the directions of the circular tracks recorded on the disk. Meanwhile, hard disk drive technology has advanced to the era of perpendicular recording on the disk with increasing coercivity ratings requiring a higher applied magnetic field strength for erasure.
Perpendicular recording and the possibility of further coercivity increases in magnetic disk drives are creating a demand for perpendicular magnetic field strength and an approximately equivalent horizontal magnetic field strength to be applied in degaussers. Typically, the disks are only partially constrained in the drive by the frictional force of parked heads, and strong erase fields acting on the spindle rotors might overcome that force, leading to less than certain demagnetization results.
Certain prior attempts to erase hard disk drives included apparatuses that apply a degaussing magnetic field almost directly to the disk while rotating the disk within the drive. The relationship, however, between external features of various hard disk drive brands and models and their internal components like spindle motors and head motors are not universally obvious. Therefore, in general application it is desirable to treat the entire volume of each hard disk drive.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention. It will further be appreciated that certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the arts will understand that such specificity with respect to sequence is not actually required. It will also be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein.

Method and reciprocating apparatus for permanent magnet erasure of magnetic storage media


The present invention relates to an apparatus and method for improving transaction processing performance in a transaction processing system, particularly but not exclusively, in a transaction processing computing system comprising a plurality of processors.

As the demand for computing resources has increased exponentially over the past decade, new ways have been sought to allow computing systems to process large amounts of data and user requests in an efficient manner.
A common way to handle a large number of simultaneous user requests on a single computing system is to divide the requests either by software or by hardware, into separate "tasks" or "transactions". In a software environment, this has become known as multi-tasking, a method whereby simultaneous user requests are placed in a queue, and executed in a sequential manner by a process. A transaction request will be understood to be a request generated by a software application, for some task to be performed by a computing system. A process will be understood to be a component (usually software) within an operating system which accepts a transaction request (hereinafter referred to as a "transaction"), queues the transaction, and then processes the transaction. Processing the transaction will be understood to mean carrying out a task or tasks requested by the transaction. The task and/or tasks may include any suitable instructions, such as searching a database, carrying out a mathematical calculation, writing to a file, accessing a hardware device, or any other activity which may be performed by a computing system. In a hardware environment, the ability to handle multiple simultaneous user requests has commonly been enhanced by using more than one central processing unit (processor).
When constructing operating systems, or other software designed to run in a multi-tasking environment, programmers are faced with the issue of deciding how transactions are allocated amongst several processes. The simplest way to decide which process a transaction will be sent to is to allocate the process in a round robin fashion. That is, a transaction currently waiting in the queue would be allocated to the next available process.
Alternatively, other operating systems allocate transactions randomly to any process, irrespective of its availability or other operating characteristics.
Such allocation systems have been found by the present applicants to be sub-optimal, because they do not take into account the time overhead involved in flushing various memory caches used for the previous process, and restocking various memory caches before the new transaction can be processed.
When a transaction is scheduled to be executed by a process that has been idle for some time rather than by a process that has recently completed executing a transaction, there is a high likelihood that the code and data used by the previous transaction has been flushed from the process's associated cache (for example, the cache in a processor used by the process). Therefore, the probability of cache misses is increased and performance suffers accordingly.
In addition, when a transaction is scheduled to a process that has been idle for some time rather than to a process that has recently become available, the likelihood that the process's associated virtual memory has been paged out to disk is also increased. Therefore, the probability of page faults occurring is increased and performance suffers accordingly. A page fault will be understood to mean an error which occurs when a program requests data that is not currently loaded into memory. This requires an operating system to fetch the requested data from a storage device and load it into memory.
Similarly, the same performance degradation may occur with any type of associated cache memory whether it be processor cache, main system memory, or virtual memory on a data storage device, such as a hard disk.
The problem of having a high number of process cache misses or other secondary cache misses due to the random scheduling of incoming transactions to any available process is not addressed by the prior art. It has generally been assumed by programmers that the operating system which resides on the computing system will schedule the transactions to processes in the most efficient manner possible. This assumption may be incorrect for certain applications.
While it is true that some operating systems have better scheduling strategies than others, in general the operating system is not aware of the specific architecture of the applications it is running, and therefore it cannot fully optimise the transaction scheduling for these applications.
In the past, the problem of having increased page faults due to the scheduling of incoming transactions to processes that may have already had their virtual memory swapped out to disk is generally addressed by adding more RAM (Random Access Memory) to a system. While this works well in general, it increases the hardware requirements for the system. Thus, adding RAM is also a sub-optimal solution as it does not address the fundamental nature of the problem. Therefore, there is a need for a new system and method which allows for more efficient use of computing resources.

Transaction-processing performance by preferentially reusing frequently used processes


When a print key on a console panel is depressed, a main CPU confirms enlargement/reduction rate information input via the console panel, and then, performs line thinning by setting a line thinning parameter according to the same magnification, an enlargement rate or a reduction rate in a line thinning processing unit in an image processing apparatus.

1. Field of the Invention
The present invention relates to an image processing apparatus for reading an image of, for example, a document by a scanner so as to process data on the read image, an image forming apparatus provided with the image processing apparatus, for forming an image, and an image forming method.
2. Description of the Related Art
In a copying machine, a printing rate is one of factors of determining toner consumption per sheet of transfer paper. The printing rate is a value determined by a printing area of a copying image in a specific evaluation chart, and it is greatly relevant to the number of dots of an image to be formed in an image forming unit. Therefore, it is possible to reduce the number of dots of the image by narrowing the width of a line of a character or the like by image processing. Consequently, the reduction of the printing rate by narrowing the width of the line by the image processing is effective in saving the toner consumption.
A line has been conventionally thinned (in other words, the width of a line has been conventionally controlled) (with respect to binary image data) after pseudo gradation processing such as error diffusion. A method for identifying an edge and a non-edge in image data has been performed by matching with a template pattern prepared in advance.
However, there has been a limit to identifying accuracy as long as the binary image data after the gradation processing has been processed, and therefore, there may be some identifying errors here and there, thereby degrading a quality of an image. Furthermore, there has arisen a problem in reducing or enlarging the image data. In the case of the reduction, the size of an output image such as a character or a thin line has become small, thereby causing a trouble such as faint printing. In contrast, in the case of the enlargement, the size of an output image such as a character or a thin line has become large, thereby causing a trouble of deterioration of a line thinning effect.

Image processing apparatus, image forming apparatus and image forming method


A tension-torsion strap, for example for a rotor aircraft, including a continuous length of carbon fiber tow arranged in multiple loops to form an elongated member extending between opposing ends and a flexible cover encasing the carbon fiber tow.

This section provides background information to facilitate a better understanding of the various aspects of the disclosure. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art.
Rotor systems are well known in the art for effectively utilizing a plurality of rotor blades to create horizontal and vertical flight. During operation, the rotor blades exert forces on the hub assembly, for example, lead/lag, feathering, centrifugal, coning, and flapping forces. In some embodiments, one or more of these forces could cause the rotor system to fail. Thus, rotor systems typically include different means for compensating these and other forces exerted on the hub assembly. For example, in some embodiments the rotor system could include elastomeric elements, spring-rate dampers, bearings, and/or other suitable means for reducing, and in some cases eliminating, the effects of these forces on the hub assembly.


The present invention is a method for providing guidance towards a far-point position for a vehicle implementing a satellite-based guidance system. The method includes capturing an image. The method further includes providing the image in a digital format to an algorithm. The method further includes isolating far-point pixelized data of the provided image. The method further includes generating data for causing a steering control system of the vehicle implementing the satellite-based guidance system to maintain the vehicle on a straight-line path towards the far-point position.

Satellite-based guidance systems, such as GPS-based guidance systems, are commonly used today as a navigation aid in cars, airplanes, ships, computer-controlled harvesters, mine trucks and other vehicles. For instance, GPS-based guidance systems utilized in farming implements may allow for precise application of crop protection products, such as fertilizers, pesticides or lime. However, current GPS-based guidance systems may experience difficulty guiding when heavy foliage or other permanent obstructions (mountains, buildings, etc.) prevent or inhibit GPS signals from being accurately received by the system. A number of GPS-based systems may include Inertial Measurement Units (IMUs) or Terrain Compensation Units (TCUs) to provide guidance capabilities under GPS-obstructed conditions. However, IMUs and TCUs tend to experience problems with drift (i.e., an ever-increasing error between IMU/TCU determined location and an actual location.
Therefore, it may be desirable to have a system and method for providing far-point vision augmentation functionality in a satellite-based guidance system which addresses the above-referenced problems and limitations of the current solutions.

System and method for providing guidance towards a far-point position for a vehicle implementing a satellite-based guidance system


The invention relates to a LED strip lighting device for a cabin of a passenger aircraft, the device comprising at least one LED strip, comprising a plurality of N independently controllable LED segments (S), wherein each LED segment (S) comprises at least four LED selected from red, green, blue, ice blue, warm white and cold white or another type of LED; a plurality of M driver units, wherein each LED section (S) is connected to a driver unit for providing a control signal to the respective LED section (S); and a bus system connecting all M driver units. The device further comprises a micro controller connected to the bus system for providing control signals for each driver unit, such that each LED segment (S) emits light in intensity and color according to a predetermined illumination pattern.

In general it is known to illuminate the cabin of a passenger aircraft for generally providing light. It is further known to adapt this light to special moods, for example changing color or intensity of the light to adapt the interior illumination to specific flight situations or passenger wishes. From US 2015/0008282 of Zodiac Aerotechnics, for example, a system is known which comprises a display device for an aircraft cabin, comprising a display adapted to display a plurality of stars. This device simulates a starry sky at a cabin roof portion. Furthermore it is disclosed that such a display device is arranged at wall sections of the aircraft cabin and that the aircraft cabin or compartment comprises a plurality of wall sections and a plurality of light emitting means for individually illuminating each wall section, wherein said wall sections and said light emitting means form such a display device. Such a display, again, is adapted to display a plurality of stars. Therefore the starry sky also is shown at wall sections of the aircraft cabin.
Such a system however is complex and can hardly be used for other purposes. Furthermore it is difficult to retrofit such a system.
Therefore, the invention seeks to provide an LED strip lighting device for a cabin of a passenger aircraft, a passenger aircraft, a method and a corresponding software product, which provides an illumination device which is usable for different purposes, in particular which is usable for safety purposes and which can be retrofitted in existing aircrafts.


A walking assistance moving vehicle includes a walking assistance moving vehicle main body with a pair of drive wheels, a drive wheel rotational speed sensor, a turning sensor, and a controller. The drive wheel rotational speed sensor senses drive wheel rotational speed of each of the drive wheels. The turning sensor directly senses at least one of a first lateral acceleration and a first turning angular velocity. The controller indirectly acquires at least one of a second lateral acceleration and a second turning angular velocity based on the drive wheel rotational speed sensed by the drive wheel rotational speed sensor. The controller performs a first control to decelerate or stop drive of the drive wheels based on a comparison of the first turning angular velocity and the second turning angular velocity or a comparison of the first lateral acceleration and the second lateral acceleration.

1. Field of the Invention
The present invention generally relates to a walking assistance moving vehicle. More specifically, the present invention relates to a walking assistance moving vehicle with a drive wheel rotational speed sensor.
2. Background Information
A walking assistance moving vehicle having a drive wheel rotational speed sensor is known in the art (see Japanese Unexamined Patent Application Publication No. 2002-37120 (Patent Literature 1), for example).
The above-mentioned Patent Literature 1 discloses an omnidirectional movement type of cart having four drive wheels and a speed sensing means for monitoring the rotational speed of the four drive wheels. This omnidirectional cart performs control to determine whether or not the drive wheels are freewheeling from a sensing value obtained by the speed sensing means.


An object of the invention is to provide type IV collagen without contamination by other proteins and without degradation or denaturation. The present invention provides a type IV collagen which is derived and extracted from lens capsules without the use of an enzyme and has a minimum molecular weight of 160 to 180 kDa measured by SDS-PAGE under reduced conditions.

Collagen is the most abundant protein in the animal kingdom, accounting for one third or more of all animal proteins. Collagen is a major constituent of connective tissues of animal skin, tendons, bones, and the like. Also, animal bodies are constituted by numerous cells and collagen plays a key role as an intercellular matrix.
Up to the present, as many as about 20 types of genetically different collagen species have been discovered, and differences in properties and functions among them have been demonstrated. Different collagen species are referred to as type I, type II, or the like, and they have been distinguished from one another. It is known that common helical regions of collagen comprising repetitions of Gly-X-Y (wherein X and Y each independently represent any amino acid) are present in the centers of collagen molecules and that triple-helical structures are formed in such regions. Such helical regions of collagen have low immunogenicity and excellent biocompatibility because of the highly conserved sequences thereof among different animal species.
Up to the present, various types of collagens have been extracted from various animal tissues and extensively utilized in the fields of medicine, pharmaceutical products, biochemistry, cosmetics, food, or the like. Depending on the raw material from which collagen is to be extracted, the collagen species to be obtained varies. For example, type I collagen is mainly contained in and extracted from skin, tendons, or bones. Type II collagen is extracted from the cartilage, and type III collagen is extracted from blood vessel walls, for example. Type IV collagen that constitutes the basal membrane is obtained from the placenta or the like. It should be noted that several collagen species might be extracted together from a given raw material.
As a method for extracting collagen, a method involving treatment of materials such as animal bones or skin with an enzyme is known. In such a method, for example, pepsin is allowed to act on such materials in a dilute acetic acid solution. With the extraction method involving use of enzyme treatment, however, a non-helical region of collagen is cleaved with an enzyme. Also, proteins other than collagens that are present in tissues may be eluted from such tissues. Consequently, collagens may be disadvantageously degraded and denatured and a large quantity of proteins other than collagens may be disadvantageously contained in an extract. In order to obtain highly purified collagen, it is necessary to use adequate tissues as raw materials and to prevent contamination by other collagens as much as possible. In order to attain the inherent properties or functions of collagens, collagens that have not undergone degradation or denaturation are required.
Type IV collagen has at its N terminus the 7S domain, which has a triple-helical collagen structure but contains abundant cysteine residues, and at its C-terminus a non-helical region of collagen (NC1 domain). The 7S domain at the N terminus is capable of interacting with the 7S domain and forming a polymer tetrad. At the C terminal NC1, 2 molecules are capable of polymerization. These domains play very important roles for intermolecular interactions of type IV collagen. Unlike other collagens, the helical region of type IV collagen is known to contain 21 Gly-X-Y triplet interruptions. Because of such molecular features, it is very important to extract molecules having all of the functional domains, i.e., the NC1 domain, the 7S domain, and the helical region of collagen, without denaturation or degradation thereof.
In the past, a major raw material for type IV collagen was placenta. Placenta contains abundant collagens other than type IV collagens, such as type I and type V collagens. Accordingly, the placenta is not an optimal raw material from which to extract type IV collagen of high purity. Many methods for extracting type IV collagens are in accordance with the method of Sage et al. (J. Biol. Chem., vol. 254, No. 19, pp. 9893-9900, 1979), which involves solubilization of collagen by pepsin hydrolysis. JP Patent Publication (kokai) No. 11-171898 A (1999) discloses a technique of isolating a polymer fraction of type IV collagen. In this isolation technique, however, type IV collagen is solubilized by pepsin hydrolysis and then extracted, as with the method of Sage et al. With such techniques, type IV collagens having functional domains similar to those in vivo cannot be extracted. Further, collagens have features such that collagen molecules become bound to and aggregated with one another because of the properties of their helical regions. Accordingly, collagen cannot be purified by a technique involving the use of a column that is commonly used for protein purification. Thus, it is very difficult to remove contaminating proteins other than collagens or other collagen species at the time of extraction. Therefore, type IV collagens of high purity have not been obtained.


Techniques are provided for image decompression. Compressed pixels are pipelined through various decompression processes. As contexts for some pixels are resolved, the resolved contexts are fed back into selective portions of the decompression processes in order to resolve contexts for other pixels currently being processed.

Context-adaptive arithmetic coding is a technique for entropy coding of bi-tonal images as evinced by a variety of current industry standards (e.g., Joint Bi-level Image Experts Group (JBIG, JBIG2), etc.). Essentially, pixels of an image are compressed into a series of bits that have a unique pattern. A compression algorithm maps a sequence of symbols embedded in the image being compressed into a real number interval. The compression algorithm successively divides the interval into sub-intervals based on inputted symbols parsed from the image and their associated probabilities (likelihoods that a parsed symbol is matched with a known symbol). The performance of the compression algorithm is in direct proportion to how well it does with estimating the symbol probabilities, because as symbols become known the compression algorithm adjusts itself if the estimations were incorrect.
A model is used by a compression algorithm to estimate symbol probabilities for input symbols based on contexts associated with the input symbols. The model maintains a state file for each context of each input symbol, and the model is updated as symbols are received and processed.
Decompression proceeds in a similar manner as compression. That is, compressed pixels represented as a series of bit values are acquired and their contexts are resolved. Based on contexts, a most likely symbol is determined and that most likely symbol is outputted as a portion of the decompressed image. Again, if the decompression algorithm does not estimate the symbols or pattern correctly, then the performance of decompression degrades as the decompression algorithm adjusts itself.
Because arithmetic decompression is heavily dependent on the contexts of previously processed compressed values and contexts of values that may have not yet been processed, the decompression performance becomes restricted. Thus, portions of the decoding remain idle until enough information becomes available to predict a context. Stated another way, sequential dependencies which are inherent in a binary compressed image restrict processing throughput of existing implementations of decompression algorithms to a tightly coupled process that linearly progresses.


A hydraulic circuit (10) is disclosed for use in controlling a horizontal boring machine which requires hydraulic fluid under pressure for rotating a drill bit or backreamer through a rotation circuit and hydraulic fluid under pressure for thrusting the drill bit or backreamer within the bore hole through a thrust circuit. Pressures from both the thrust circuit and control circuit are combined through restrictors in a mixing zone or area (26). The control port of a diversion valve (32) is connected to mixing zone (26). When the combined pressure in the mixing zone exceeds the adjustable spring bias on the diversion valve, the diversion valve will open, diverting fluid from the thrust circuit to a low pressure zone. This will cause a reduction in the pressure in the rotation circuit as well. The reduction of both pressures will reduce the combined pressure in the mixing zone (26), causing the diversion valve to close and the pressures to increase. The hydraulic circuit maintains a constant maximum output for both circuits for a given horsepower input to the boring machine and productivity is enhanced due to reduced operator fatigue.

This invention relates to a hydraulic control circuit for a boring device, such as a horizontal boring device for installing utility services and the like.
Horizontal boring machines are used more and more frequently to install or replace utility services. The machines include a surface mounted boring unit which has a rotation motor to rotate a drill string having a drill bit at the end thereof and a thrust motor to thrust the drill string forward in the bore hole. The machine can also be used to backream a hole previously bored to enlarge the hole and pull in the new service.
Many horizontal boring machines require the operator to manually and individually adjust the rotation torque and thrust force which together define the amount of power applied to the downhole boring tool. Maintaining the correct balance of power between these two functions is necessary to maximize the efficiency of the unit. Inexperienced operators find it difficult to keep an efficient balance of thrust and rotation. Although necessary for both the boring of the pilot bore and backreaming to enlarge the size of the bore hole, the need for finite control is usually greater when backreaming. Therefore, a need exists for an apparatus to provide for operation of the machine at optimum efficiency even when used by inexperienced operators.
In accordance with one aspect of the present invention, a hydraulic control circuit is provided for use in a horizontal boring machine which rotates a drilling element with hydraulic fluid at a rotation pressure from a first source of hydraulic pressure and thrusts the drilling element in a given direction with fluid at a thrust pressure from a second source of control pressure. The control circuit includes a mixing zone and a diversion valve connected between the second source of hydraulic pressure and a zone of low pressure. A first passage connects the first source of hydraulic pressure and the mixing zone. The first passage has a flow restrictor so that if the pressure from the first source of hydraulic pressure is high for a sufficient amount of time for the pressure in the mixing zone to be increased to a high level, the diversion valve opens to direct a portion of the flow of fluid from the second source of hydraulic pressure to the zone of low pressure to reduce the pressure from the second source of hydraulic pressure.
In accordance with another aspect of the present invention, a second passage having a flow restrictor is connected between the second source of hydraulic pressure and the mixing zone. The first passage has a flow restrictor slightly larger than the restrictor in the second passage so if the pressure from the first source of hydraulic pressure is low, the pressure in the mixing zone will also be lowered. Conversely, if pressure in the first passage is high, the pressure in the mixing zone will also be higher. Pressure in the mixing zone is highest when both the first and second sources of hydraulic pressure are high. When pressure in the mixing zone is high, the diversion valve opens to direct the flow of fluid from the second source of hydraulic pressure to the zone of low pressure to reduce the pressure from the second source of hydraulic pressure.

Hydraulic circuit for automatic control of a horizontal boring machine


The present invention relates to a method and network node for distributing a network parameter information among network nodes of a transmission network. A spanning tree of routing paths corresponding to the shortest paths from said network node to other nodes is determined based on a topology information of the transmission network, and is used to distribute the network parameter information from the network node to the other network nodes. Thereby, the updating message or packet traffic can be reduced dramatically as compared to the conventional flooding scheme.

In a Code Division Multiple Access (CDMA) based cellular network all users in the same cell or in different cells may share the same frequency spectrum simultaneously. In spread spectrum transmission, the interference tolerance enables universal frequency reuse. This enables new functions such as soft handover, but also causes strict requirements on power control. Due to the universal frequency reuse, the connection of a radio terminal, e.g. a mobile terminal, mobile station or user equipment to the cellular network can include several radio links. When the radio terminal is connected through more than one radio link, it is said to be in soft handover. If, in particular, the radio terminal has more than one radio link to two cells on the same side, it is in softer handover. Soft handover is a form of diversity, increasing the signal-to-noise ratio when the transmission power is constant.
At network level, soft handover smoothes the movement of a mobile terminal from one cell to another. It helps to minimize the transmission power needed in both uplink and downlink.
Thus, a radio terminal of a network subscriber can transmit the same information on a plurality of redundant transmission parts that are set up parallel via a radio transmission interface from the cellular network to the radio terminal or from the radio terminal to the cellular network in order to achieve an optimal transmission quality. Such a transmission structure is called macrodiversity. The redundant transmission paths can be dynamically set up and cleared down while the radio terminal changes its location. The information sent out by the radio terminal in the transmission frames on various transmission paths can be merged in the trans-mission network at combination points at which respectively two transmission paths are combined into a single transmission path in one transmission direction (uplink) and the single transmission path is divided into two transmission paths in the other transmission direction (downlink). A corresponding network architecture is described for example in the U.S. Pat. No. 6,198,737 B1.
In order to obtain the most efficient RAN architecture, which is based on using the advantageous characteristics of IP, some functionality is relocated between network elements. According to a recent new architecture, a network element, known as Base Station Controller (BSC) or Radio Network Controller (RNC) is no longer required, although this functionality must remain in the RAN architecture. Therefore, a location of a combining point, e.g. MDC point, can no longer be centralized for all base stations in the RAN. Consequently, some RNC functionality has been transferred to the base stations in order to enable soft handover and associated signaling to happen along the shortest path, producing minimum delay and signaling load to those paths of the network where this is not necessary. This new RAN architecture is described e.g. in the White Paper "IP-RAN, IP—the future of mobility", Nokia Networks, 2000.
In such a new RAN architecture, the MDC point can be selected dynamically e.g. by a serving base station instead of having this functionality in one pre-selected point like the RNC in the conventional RAN architecture or in the base station that initiates the call. In the new RAN architecture, base stations are able to act as MDC points.
However, in order to select the MDC point dynamically, the corresponding network node or entity needs up-to-date information of the RAN network, e.g. its parameters such as link state, link utilization, node utilization, MDC load, and any other QoS-related parameters. When any change of a parameter happens, the change parameter needs to be distributed among the network nodes or entities. In addition, any change of a parameter will invoke a tide of messages or packets in the network for keeping all network nodes updated. If the known flooding scheme as described e.g. in J. Moy, "OSPF Version 2", IETF specification RFC1583, 1994 is used, a parameter change can, in the worst case, invoke as many messages or packets as twice the total number of links in the RAN. Thus, updating traffic may become a source of network congestion itself. Furthermore, the flooding scheme is not scalable with an increase of the dimension of the RAN. Given the on-changing nature of the RAN, a scalable and efficient distribution scheme is therefore required for this purpose.

Distribution scheme for distributing information in a network


Disclosed herein are transmembrane transporter compounds containing guanidinium groups to enhance transport of a polymer backbone across biomembranes. Therapeutic and other biologically active moieties may be attached to the compounds. The polymer backbone may include peptide nucleic acid monomer units.

1. Field of the Invention
The present invention relates to the fields of chemistry and medicine. More particularly, the present invention relates to guanidinium containing compounds that exhibit enhanced transmembrane transport of biologically active molecules.
2. Description of the Related Art
Protein transduction domains (PTD) are short cationic peptides that are capable of delivering molecules into mammalian cells. They include many diverse peptide sequences from many diverse sources. The phenomenon that peptide sequences can assist molecules across biological barriers is ubiquitous in biological systems. Such phenomenon can take place at different levels, including subcellular (e.g., nuclear membranes), cellular (e.g., cell membranes), and tissue levels (e.g., epithelial tissue). Sometimes the same peptide sequences can promote different translocation events at different biological levels.

Peptide nucleic acid based guanidinium compounds


An electrical contact (2) for electrically connecting an IC package having solder balls (4) with a substrate and includes a base portion (21), a spring arm (24) extending upwardly from the base portion (21) and a rear portion (23) extending downwardly from the base portion (21), the spring arm (24) defines a contact portion (25) at the end thereof to connect with the solder ball (4) of the IC package, the contact portion (25) includes a wide portion (252) with a width larger than other portions of the contact portion (25), the wide portion (252) includes a pair of higher end portions (2520) at opposite ends thereof and a lower middle portion (2521) between the pair of end portions (2520).

1. Field of the Invention
The present invention relates to an electrical contact for connecting with an IC package, and more particularly to an electrical contact with improved contact portion to establish robust electrical connection between the electrical contact and the IC package.
2. Description of Related Art
U.S. Pat. No. 7,097,463 issued to Hsiao on Aug. 29, 2006 discloses a conventional electrical connector for electrically connecting an IC package with a substrate. The electrical connector includes an insulative housing and a plurality of electrical contacts received in the insulative housing. Each of the electrical contacts comprises a main portion received in the insulative housing, a soldering portion extending downwardly from the main portion and a contact portion extending upwardly from the main portion. The soldering portion is used to be soldered to the substrate through a solder ball. The contact portion is used to contact with the solder ball of the IC package. When the IC package is assembled to the electrical connector, the solder ball of the IC package press the contact portion, thus a robust electrical connection is established between the IC package and the electrical connector. Due to the solder ball is configured with a circular shape, when the solder ball presses the contact portion, the solder ball is easy to slide away from the contact portion of the electrical contact. Thus, the electrical connection between the IC package and the electrical connector is disconnected.
Hence, it is desirable to provide an improved electrical connector to overcome the aforementioned disadvantages.

Electrical contact and electrical connector used thereof


A rotary pump for a fluid metering system is provided. The rotary pump reciprocates, and is reversed by a signal from a limit switch that is deflected by an actuator arm on a rotating sleeve of the pump system. The rotary pump includes a plunger and optional stopper formed from a two-shot molding process, and including seals overmolded onto the head of the plunger and the head of the optional stopper.

Diabetes is a group of diseases marked by high levels of blood glucose resulting from defects in insulin production, insulin action, or both. Diabetes can lead to serious health complications and premature death, but there are well-known products available for people with diabetes to help control the disease and lower the risk of complications.
Treatment options for people with diabetes include specialized diets, oral medications and/or insulin therapy. The primary goal for diabetes treatment is to control the patient's blood glucose (sugar) level in order to increase the chances of a complication-free life. It is not always easy, however, to achieve good diabetes management, while balancing other life demands and circumstances.
Currently, there are two principal modes of daily insulin therapy for the treatment of type 1 diabetes. The first mode includes syringes and insulin pens that require a needle stick at each injection, typically three to four times per day. These devices are simple to use and relatively low in cost. Another widely adopted and effective method of treatment for managing diabetes is the use of an insulin pump. Insulin pumps can help users keep their blood glucose levels within target ranges based on their individual needs, by providing continuous infusion of insulin at varying rates to more closely mimic the behavior of the pancreas. By using an insulin pump, users can match their insulin therapy to their lifestyles, rather than matching their lifestyles to how an insulin injection is working for them.
However, conventional insulin pumps suffer from several drawbacks. For example, lead screw and piston type metering systems typically used in insulin pumps are often cumbersome to users, requiring a large height and a large a footprint.
Conventional insulin pumps also typically require a large number of components and moving parts, thereby increasing risks of mechanical failure.
Conventional insulin pumps also typically have too long a tolerance loop for dose accuracy, depending on too many factors, which are sometimes difficult to ascertain. This can result in a loss in dose accuracy.
Conventional insulin pumps also typically have too complex a fluid path. This can result in complicated or inadequate priming and air removal.
Conventional insulin pumps also typically require high precision actuators, thereby increasing the cost of conventional patch pumps.
Some insulin pumps are also at risk of creating direct fluid paths between a reservoir and a cannula of an insulin patch. This can result in an overdose to a user.
Conventional insulin pumps also typically require complex sensing schemes. This can result in increased cost and reduced accuracy and reliability.
Conventional insulin pumps also typically have valves that are prone to leaking at elevated system back pressures. This can result in reduced accuracy and reliability.
Conventional insulin pumps also typically require large working volumes and large system volumes exposed to potentially high back pressure. This can result in reduced accuracy and reliability.
Conventional insulin patches also typically have low efficiency motors requiring large batteries, thereby increasing the size of the insulin patch.
Accordingly, there is a need for a metering system with reduced height and footprint, compared to conventional lead screw and piston type metering systems, to increase comfort to users.
There is also a need for a metering system with a reduced number of components and moving parts, compared to conventional insulin pumps, to increase the mechanical safety of insulin patches.
There is also a need for a metering system with a short tolerance loop for dose accuracy, which depends on few factors, compared to conventional metering pumps, thereby increasing dose accuracy.
There is also a need for a metering system with a simple fluid path, compared to conventional metering systems, thereby simplifying priming and air removal.
There is also a need for a metering system utilizing a low precision actuator, compared to conventional metering systems, thereby reducing the cost of insulin patches.
There is also a need for a metering system with no direct fluid path between the reservoir and the cannula, compared to conventional metering systems, thereby better safeguarding a user against overdose.
There is also a need for a metering system with simple sensing schemes, compared to conventional metering systems, thereby reducing cost and increasing accuracy and reliability of insulin patches.
There is also a need for a metering system with valves that are robust with respect to leaking at elevated system back pressures, compared to conventional metering systems, thereby increasing accuracy and reliability of insulin patches.
There is also a need for a metering system with a small working volume and a low system volume exposed to potentially high back pressure, compared to conventional metering systems, thereby increasing accuracy and reliability of insulin patches.
There is also a need for a metering system requiring a high efficiency motor with small batteries, compared to conventional metering systems, thereby reducing the size of insulin patches.

This patent is subject to a terminal disclaimer.

Rotational metering pump for insulin patch


A variable resistance element is configured to be provided with a perovskite-type oxide between a first electrode and a second electrode, of which electric resistance between the first electrode and the second electrode is changed by applying a voltage pulse of a predetermined polarity between the first electrode and the second electrode, and the variable resistance element has a resistance hysteresis characteristic, in which a changing rate of a resistance value is changed from positive to negative with respect to increase of a cumulative pulse applying time in the application of the voltage pulse. The voltage pulse is applied to the variable resistance element so that the cumulative pulse applying time is not longer than a specific cumulative pulse applying time, in which the changing rate of the, resistance value is changed from positive to negative with respect to increase of the cumulative pulse applying time in the resistance hysteresis characteristic.

1. Field of the Invention
The present invention relates to a driving method of a variable reistance element including a perovskite-type oxide between a first electrode and a second electrode, of which electric resistance is changed by applying a voltage pulse of a predetermined polarity between the both electrodes, and a memory device provided with the variable resistance element.
2. Description of the Related Art
In recent years, as a next-generation Nonvolatile Random Access Memory (NVRAM) capable of being operated at a high speed in place of a flash memory, various device structures such as a Ferroelectric RAM (FeRAM), a Magnetic RAM (MRAM), and an Ovonic Unified Memory (OUM) or the like are proposed and in view of a high performance, a high reliability, a low cost, and a process matching, competition in development of them has been intensified. However, these current memory devices have both merits and demerits respectively and it is difficult to realize the ideal "universal memory" having each merit of a SRAM, a DRAM, and the flash memory.
On the contrary to these existing arts, a method of changing an electric resistance in a reversible fashion by applying a voltage pulse to a perovskite material that is known as a supergiant magnetic resistance effect is disclosed by Shangquing Liu and Alex Ignatiev et al. of University of Houston (refer to the specification of U.S. Pat. No. 6,204,139, Liu, S. Q. et al., "Electric-pulse-induced reversible Resistance change effect in magnetoresistive films", Applied Physics Letter, Vol., 76, pp. 2749-2751, 2000). This is very epoch-making because the resistance change across several digits appears even at room temperature without applying a magnetic field while using the perovskite material that is known as the supergiant magnetic resistance effect. A Resistive Random Access Memory (RRAM) does not require any magnetic field differently from the MRAM, so that this has an excellent advantage such that the power consumption is very low, minuteness and high integration can be easily realized, and multilevel storage is possible since a dynamic range of the resistance change is very large as compared to the MRAM. The basic structure of the real device is very simple, and it is made in such a manner that a lower electrode material, the perovskite-type oxide, and an upper electrode material are deposited in a direction vertical to a substrate. In the meantime, according to the element structure illustrated in the specification of U.S. Pat. No. 6,204,139, the lower electrode material is made of a yttrium barium copper oxide YBa2Cu3O7 (YBCO) film deposited on a single crystal substrate of a lantern—aluminum oxide LaAlO3 (LA); the perovskite-type oxide is made of a crystalline praseodymium calcium manganic oxide Pr1−xCaxMnO3 (PCMO) film; and the upper electrode material is made of an Ag film deposited by sputtering, respectively. It is informed that the operation of this memory element can change the resistance in the reversible fashion by applying 51 volt of the voltage pulse between the upper and lower electrodes in positive and in negative. It means that a new nonvolatile memory device is available by reading a resistance value in this reversible resistance change operation (hereinafter, referred to as "the switching operation" appropriately).
However, the present inventor variously conducted a study regarding the nonvolatile memory device by using the perovskite-type oxide of which resistance is changed due to the voltage pulse, particularly, the PCMO film, and as a result, there are problems such that the switching operation is not always carried out, for example, the switching operation is not carried out although the resistance is changed due to the voltage pulse and the resistance value is not changed. These problems are major barriers to practical application thereof. In other words, it means that the nonvolatile memory device that can be repeatedly rewritten cannot be realized if the stable switching operation cannot be secured.

Driving method of variable resistance element and memory device


Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the worst case logical one or worst case logical zero within a read-only memory array of memory cells. The dummy bit line voltage is used as a control signal to a trigger circuit. The trigger circuit generates at the appropriate threshold a triggering signal used to control sense amplifiers coupled to the memory circuit. Therefore, by programmably altering the delay time on the dummy bit line, the read cycle of the memory can be programmably altered to either minimize the read time cycle to provide a fast, high quality memory product, or to maximize the read time cycle to provide for a slower but higher yield memory product at less expense.

1. Field of the Invention
The invention relates to improvements in a read-only memory. In particular the invention relates to a VLSI memory array precharge improvement, a latch circuit improvement to minimize metastability in dynamic digital circuits,
2. Description of the Prior Art
Memory Array Precharge
FIG. 19 of the parent application referenced above shows a precharged circuit whose operation is illustrated in the timing diagram of FIG. 20 of that same application. The architecture of this memory array is comprised of four blocks: (1) a Y-decoder block for the high address portion; (2) a Y-decoder block for the low address portion; (3) a memory cell block; and (4) a precharge block. The memory array is provided with a precharge voltage, VPC. Charging and discharging the bit lines are controlled by the signals, SELV, PCO, PC1 and PC2.
PC2 serves to precharge the bit line from the memory array itself. PC2 provides a bit charge which charges only selected bit lines which are connected to a sense amplifier to a certain precharge level.
PC1 is then coupled in common to the gates of a plurality of precharged transistors which are coupled in series with each virtual ground line and bit line within the memory cell block. PC1 is therefore used as a blanket precharge and charges all bit lines and source side select lines to a predetermined charge level.
PC0 is coupled in common to the gates of the precharged transistors within the memory array, which transistors are coupled between adjacent bit lines in the array similar to that as shown in FIG. 18 of the parent application incorporated above. The precharged transistors short each of the bit lines together to allow a precharge to be coupled through the transistors to all the bit lines within the memory block. PC0 is therefore a bank precharge signal. PC0 charges all the bit lines in a selected bank which are precharged and shorted together so that the previous charge from any previously selected memory cell access within the block is eliminated. The bit lines are precharged equally with a predetermined precharged level.
The control signal, SELV, is a select virtual ground command which pulls the source side of a selected memory cell bit to ground level.
The address lines YDLi and YDUi, corresponding to the lower and upper address bits, are typically low during precharge. Only one address line YDUi and one address line YDUi are driven high during the evaluate or read cycle.
Metastable Latch Circuit
In memory circuits or other dynamic digital circuits, latches are used to accepts various signals, such as addresses to implement the read or write signal with proper timing. In some cases the latch is likely to fall into a metastable state which can cause a dynamic ROM, for example, not to accept any new address transitions or to cause a dynamic ROM to output incorrect data. To avoid latch contentions design modifications of the latches are used which introduce time delays. These delays then must be accommodated by the logic design of the architecture. What is needed is a latch design which is not susceptible to failure in latch contentions and which is transparent insofar as the timing of the circuitry is concerned.
Data Multiplexing in Very Large Scale Integrated Memories with Optimum Operating Speed
FIG. 6 illustrates a typical prior art, read-only memory in which the memory core is divided into a left core half 62 and right core half 64. Each core half 62 and 64 produces eight bits or one byte of the output word. The bytes are multiplexed through a multiplexer 66 whose output is coupled to a sense amplifier 68. The output of the sense amplifier in turn is provided as an input to a driver circuit 70 whose output is connected to the output pads 72 to communicate the left and right bytes in sequence to the outside environment, typically a bus.
The disadvantages of the prior art approach as shown in FIG. 6 is that both halves of the memory core 62 and 64 must be powered up and coupled through multiplexer 66 to sense amplifier 68. The chip layout for this coupling is geometrically complex and generally introduces opportunities for undesirable parasitic effects. The generation of internal noise voltages within the two memory core halves 62 and 64 also creates an inherent limitation to circuit speed.
Therefore, what is needed is a memory organization and supporting sense amplifier and multiplexer circuitry which overcomes these defects.
A One Shot Pulse Generator for a Very Large Scale Integrated Memory Precharge Time Control
The parent application upon which this depends shows the advantages of dynamic precharge and blanket precharge of all the core elements within a very large scale integrated read only memory. A typical approach to generate the timing signals is depicted in FIG. 12. The logic circuitry of FIG. 12 determines when to switch the precharge clock PC0 to a logical zero as measured from the start of the memory cycle by means of several cascaded logic gates. The propagation delay time through the cascaded gates determines when PC0 will be switched low. The prior art design of FIG. 12 is, however, ill adapted for a CMOS circuitry and more generally is difficult to provide an optimum precharge time for the ROM core because timing control, which is subject to process variations, temperature and supply voltage variations, is very approximate.
Therefore, what is needed is a circuit which will overcome each of the defects of a memory precharge timing circuit as exemplified by the prior art of FIG. 12.
CMOS Trigger Circuit
A typical NMOS ROM trigger circuit is shown in FIG. 24 of the parent application and uses two inputs and has one output which switches or triggers from a logical zero to a logical one when the input ramps downwardly relatively slowly to about 0.2 volts less than the second input.
What is needed is a CMOS sense circuit which includes an automatic quick power-down to zero after the output switches have switched to a logical one. Further, also what is need is a trigger circuit which can trigger on less than 0.2 voltage difference in the inputs.
One-shot Pulse Generator for VLSI Memory Timing Control
FIG. 21 in the copending parent application shows NMOS ROM timing control circuit which determines by means of a word dummy line and associated control logic gates the time at which to switch the precharge clock, PC0, to 0 as measured from the start of a memory cycle. The precharge clock, PC0, is not switched to 0 until the output of the dummy word line delay circuit, OWUP, has switched low.
This design is not compatible with CMOS processing and requires the use of two dummy word lines. The prior art circuit also has no means for powering-down when inactive and therefore continues to use power even when inactive. Therefore, what is needed is a timing control circuit which is not subject to each of these limitations of the prior art.
RC Delay Circuit To Block Address Transition Detection
Means have previously been described in the parent copending application for blocking address transition detection at the time that output buffers are changing through the use of a timing circuit whose output is SURG. However, the circuitry there described in connection with FIG. 35 of the copending parent application is not adapted to a CMOS process, and is based upon logic gates and inherent delays in those gates. These delays are subject to variations in process parameters and operating voltages. Therefore, what is needed is a delay circuit which can block address transition detection in a controlled manner without being subject to these process and operating voltage variations.
CMOS Sense Amplifier/Latch Circuit for a Single Data Input Signal
The NMOS read-only memory sense amplifier described in the parent application upon which this application copends used four inputs and had a latch function. This design is ill adapted to the CMOS environment. Further, improved data latch operation would be desired to provide some type of means for increasing immunity to bit line noise. Still further, it would be advantageous to power-down the sense amplifier to zero power dissipation while retaining the latched data.
A Low Noise X Decoder Circuit for Use in a Semiconductor Memory
X decoders used in addressing memories provide a selection function by which a particular polysilicon or polycide word line is moved from a lower, offvoltage state to a higher on-voltage state with all word lines held low. The particular word line which is selected is determined according to the voltages or signals on the multiple address input lines. Each unique combination or configuration of addresses selects one unique word line. Conventional read-only memories, random access memories or programmable read-only memories have X decoders which are designed using stages of logic gates, NAND and NOR gates followed by buffers. In the case of NMOS technology, voltage pumps are used to insure full scale voltage expressions.
This prior art approach is particularly susceptible to noise of a type which the present invention suppresses. Noise in the X decoder is a product of the decoder design and becomes apparent in very large memories which are now beginning to be built.
Therefore, what is needed is a means for suppressing the unique type of electrical noise which occurs in these types of X decoders.
Improved Tune Constant Generation Circuit
The accurate control of circuits used in semiconductor memories is based upon the availability of a stable time reference. Typically, for the sake of simplicity and cost, an RC time circuit is provided using integrated resistive and capacitive elements. Typical prior art approaches for creating time delays have used: (1) pair delay integrated circuit logic elements; (2) RC time delay using integrated elements; (3) RC time delays using hand-selected resistive and/or capacitive external element; and (4) crystal based tuning elements using external crystals and connectors. Each of these supposes varying cost and accuracy proportionately with the first approach being the least costly and accurate and the last being the most costly and accurate.
What is needed is a means for utilizing low cost timing approaches such as described in the first and second options above, but to do so with accurate results not typical of those prior art approaches.
Memory Circuit Yield Generator and Timing Adjustor
The use of a dummy decoder in a semiconductor memory to obtain an optimum sense time and to provide adjustment for device leakage, capacitance loading, transistor characteristics and the like is well known. However, no means has been devised to provide for higher production yields in such dummy decoders when the circuit being produced had a slower speed requirement.

Memory circuit yield generator and timing adjustor


The present invention provides a broadband transmitting protective coating (10) including an AlGaP protective layer (14) deposited on an optical substrate (12) and an anti-reflection film (16) deposited on the AlGaP protective layer (14). The coating (10) is suitable for use with typical infrared and broadband optical substrate materials such as germanium or multi-spectral ZnS. In the case of a germanium substrate (12), the anti-reflection film (16), (16a) preferably consists of a single layer of hard carbon or alternating layers of hard carbon and silicon. In the case of a multi-spectral ZnS substrate (12a), the anti-reflection film (16b) preferably consists of layered Al.sub.2 O.sub.3 /TaO.sub.5 /LaF.sub.3 /MgF.sub.2. The protective coating (10) is preferably deposited on the optical substrate (12) by a metal organic chemical vapor deposition process wherein an initial layer of AlP is nucleated on the substrate (12) at a temperature of approximately 400.degree. C. The temperature of the substrate (12) is then raised to approximately 600.degree. C. and a layer of AlGaP (14) is grown on the substrate (12) to a preselected thickness. The AlGaP coated optical substrate (12) is then polished to a desired smoothness. The anti-reflection film (16) is then deposited on the AlGaP layer (14) using an RF chemical vapor deposition process or a thermal evaporation process.

1. Technical Field
The present invention generally relates to protective coatings for optical window substrates and, more particularly, to a protective and anti-reflection coating for optical windows employed in airborne and ground based tactical and surveillance sensors.
2. Discussion
Optical windows employed in airborne and ground based tactical and surveillance sensors are often exposed to hostile environments where they collide with rain and sand. The degree to which the window can withstand the impact of the rain and sand directly influences the operational envelope available for the sensor. Additionally, failed windows must be replaced which results in sensor idle time and maintenance expense.
Conventional optical windows begin to sustain impact damage at aircraft speeds well below Mach 1 and fail prematurely due to high speed rain/sand particle impact. Prior art anti-reflection coatings provide minimal resistance against impact damage. The impact resistance, or knoop hardness, of these coatings does not allow the windows to operate safely at high rain/sand impact speeds without significantly degrading optical performance.
Furthermore, boron phosphide and gallium phosphide coatings which do provide good impact resistance have a relatively narrow band gap and therefore provide only marginal optical transmittance over a relatively narrow optical bandwidth. For example, boron phosphide has an optical absorption property which makes it suitable for operation primarily in the long wave infra-red (LWIR) range. Therefore, these coatings are not suitable with the newer class of broadband, common aperture optical sensors which employ broadband optical window materials such as multi-spectral zinc sulfide and operate in bandwidths from the television (TV) to mid-wave infra-red (MWIR) or from the TV to LWIR.
The drawbacks of conventional coatings results in the need to frequently refinish and/or replace optical windows which causes high window life cycle costs. Moreover, the operational envelope for sensor systems employing prior art coatings is restricted by their relatively poor optical performance at high rain/sand impact speeds.
Accordingly, it is desirable to provide a combined protective and anti-reflection coating having excellent broadband transmittance and yielding significant impact protection for the optical window from high speed rain/sand particles.

Broadband protective optical window coating


The subject matter of the invention is a process for the production of metal salts of trifluoromethane sulphonic acid by reacting trifluoromethane sulphonic acid with a metal alcoholate and the use thereof as esterification catalyst and/or transesterification catalyst for the production of hydroxycarboxylic acid esters.

1. Field of the Invention
The invention relates to a process for the production of metal salts of trifluoromethane sulphonic acid by reacting trifluoromethane sulphonic acid with a metal alcoholate and their use as esterification catalyst and/or transesterification catalyst for the production of hydroxycarboxylic acid esters.
2. Description of Prior Art
Trifluoromethane sulphonic acid (CF3SO3H) is one of the strongest organic acids. Its protonation power is stronger than that of sulphuric acid. Its metal salts, i.e. metal perfluoromethane sulphonates, also called metal triflates, are available as solids or in solution.
The most frequent fields of application of metal compounds of trifluoromethane sulphonic acid are their use as catalyst in the polymerisation of aromatic alkenes, of aromatic monomers, in electrophilic polymerisation of 1,3-pentadiene, the cationic ring opening polymerisation of tetrahydrofuran, in the Michael reaction of O-silylated ketene acetals with alpha,beta-unsaturated esters. Further fields of application are aldol and Friedel-Crafts reactions.
From U.S. Pat. No. 4,219,540, the production of metal salts of trifluoromethane sulphonic acid and their use in antiperspirants is known. The aluminium salt of trifluoromethane sulphonic acid is produced by adding trifluoromethane sulphonic acid at room temperature to an aqueous suspension of barium carbonate and stirring the mixture, filtering it and removing water from it at reduced pressure and elevated temperature and drying it.
The barium trifluoromethane sulphonate thus obtained is again dissolved in water, stirred and aluminium sulphate dissolved in water is added at room temperature. After heating, filtration is carried out and the filtrate is decolorised with carbon, filtered once more and water is driven off at reduced pressure and elevated temperature, and it is dried. In a similar manner, the corresponding triflates have been produced for the rare earth metals Ce, La and the Nd—Pr alloy didymium [neodymium-praeseodymium-alloy].
A disadvantage is the complicated recovery of the metal triflate and the low yield with respect to the trifluoromethane sulphonic acid used.

Process for the production of metal salts of trifluoromethane sulphonic acid and their use as esterification catalysts


There is disclosed a process for producing 3-methyl-tetrahydrofuran which comprises the step 1 of subjecting the compound represented by the general formula [I] EQU ROOC--CH(CH.sub.3)--CH.sub.2 --CHO [I]. wherein R is an alkyl group having 1 to 3 carbon atoms and the formyl group may be present as an acetal having an alkanol with 1 to 8 carbon atoms, to hydrogenation and alcohol-eliminating cyclization to synthesize 2-methyl-.gamma.-butyrolactone; the step 2 of separating the 2-methyl-.gamma.-butyrolactone formed in the step 1 from alcohols by means of distillation, etc.; and the step 3 of hydrogenating the 2-methyl-.gamma.-butyrolactone which is formed in the step 2. The above process enables the production of the objective highly-pure 3-methyltetrahydrofuran substantially free from an alcohol in high efficiency and high conversion through simplified production steps.

1. Field of the Invention
The present invention relates to a process for producing 3-methyltetrahydrofuran, which is an extremely useful substance that is utilized as a comonomer for modifying poly(tetramethylene ether glycol) obtained by polymerizing tetrahydrofuran. [Refer to Japanese Patent Application Laid-Open No. 235320/1988 (Sho-63) and European Patent Application Laid-Open No. 343985].
2. Description of the Related Arts
As a process for producing 3-methyltetrahydrofuran, Japanese Patent Application Laid-Open No. 219981/1994 (Hei-6) describes the process for producing 2-methyl-1,4-butane-diol and 3-methyltetrahydrofuran by the hydrogenation of an itaconic acid ester or a 3-formyl-2-methylpropionic acid ester, and also Japanese Patent Application Laid-Open No. 217768/1996 (Hei-8) describes the process for producing 3-methyltetrahydrofuran by the hydrogenation of a methyl-succinic acid ester. However, when an attempt is made to produce 3-methyltetrahydrofuran by the use of the above-mentioned ester as a starting raw material, it is inevitable that the reaction product contains an alcohol as well as the objective 3-methyltetrahydrofuran. 3-Methyltetrahydrofuran forms an azeotropic mixture with most of the lower alcohols, for example, with methanol, forming an azeotropic mixture having an azeotropic point of 64.5.degree. C. and an azeotropic composition consisting of 25% by weight of 3-methyltetrahydrofuran and 75% by weight of methanol, thus it requires a large amount of energy to separate 3-methyltetrahydrofuran from the azeotropic mixture. In particular, the 3-methyltetrahydro-furan which is employed for modifying poly(tetramethylene glycol) is required to have highly purity and to have contents of alcohols not more than 0.2%

Process for producing 3-methyltetrahydrofuran


An article of manufacture includes a substrate, a first patterned layer deposited on the substrate in a first region, and a second patterned layer deposited on the substrate in a second region. The first patterned layer encodes first information in first symbols that are detectable by an optical sensor. The second patterned layer encodes second information in second symbols that are detectable by a non-optical sensor. The second information is distinct from the first information and the second region at least partially overlaps the first region.

Computing systems to facilitate global commerce have simplified tracking products during shipment. Computing systems may gather information for computer-based inventory and tracking system using computer-readable labels or devices, such as radio-frequency identification (RFID) tags, bar codes, etc. Such computer-readable labels or devices are generally read using single purpose readers (e.g., RFID tag readers or bar code readers). Thus, for example, when a bar code is present on a box, in order for the bar code to be useful for automated inventory and tracking recordkeeping, a bar code reader is needed. If the box is at a location that has an RFID tag reader but does not have a bar code reader, then the bar code is not helpful.
Additionally, different computing systems may use different types of information for tracking purposes. To illustrate, a first country may require that a shipping container includes a label in a particular language describing contents of the container and a second country may require that the shipping container includes a label in a different language describing contents of the container. As another example, during examination of a container at a first port of entry within a country, the container may need to be labeled with particular information, whereas, when it is being loaded onto a truck for shipment within the country, the container may need to be labeled with different information. Accordingly, providing sufficient labeling information in a format that is computer-readable can be problematic.

Encoding information in multiple patterned layers

INTERNATIONAL BUSINESS MACHINES CORPORATION


A thermal alarm clock including an alarm clock controller that activates a heating device to wake a slumbering person. The thermal alarm clock incorporates traditional alarm, clock, and radio functions as well. The heating device is located adjacent a sleeping person and can be activated with, or instead of, an audible alarm. A slumbering person will be gently awakened by the heat of the device instead of the jarring sound from an audible alarm clock. The thermal alarm clock is also effective at waking a single person from a plurality of sleepers and is effective for users with special needs, such as the hearing impaired or blind. In one embodiment, the thermal alarm clock incorporates sensors and circuitry to monitor a user's presence.

Millions of people use alarm clocks to wake themselves up in the morning. Typically, an alarm clock will sound an audible alarm, such as a ringing or buzzing sound, to wake up a person at a preset time. These audible alarm clocks can be driven mechanically or electrically. In either case, the waking experience produced by an audible alarm clock is very abrupt and jarring.
A major advancement in the alarm clock's waking experience was the integration of the radio. So-called "clock radios" allow a person to wake up while listening to a radio broadcast. It is thought that using the sound of music or talking as a means to wake up is a more comfortable experience than being assaulted with a ringing or buzzing noise. While music does help to reduce the jarring effect associated with a buzzing alarm, the waking experience is often still abrupt. The radio alarm also loses its effectiveness as the human body adjusts to the radio station.
Another downside to any audible type alarm is that they are ineffective for hearing-impaired people. Therefore, vibrating alarm clocks have been developed. These alarms typically pulsate a pillow or mattress in an attempt to wake up the sleeping individual. Pillow vibrators are undesirable because a sleeping person's head may not be in contact with the pillow, or the pillow may be pushed aside. Mattress vibrators do not work well with the cabin style beds that do not have a box spring or bed frame. Users need alarm clocks that are consistently effective. In particular, the hearing impaired would benefit from an effective silent alarm clock.
Alarm clocks have also incorporated visual methods for arousing a person. For example, an alarm clock can be used to turn on a room's lights when the alarm is activated. This is useless for blind users, and sleeping individuals tend to avoid bright lights, thereby rendering these alarms largely ineffective. In any event, waking up to a suddenly bright room is just as jarring and annoying as an audible alarm.
Yet another branch of alarm clocks are wearable alarm clocks, including vibrating wristbands and ear mounted audible alarms. However, many people find sleeping with devices attached to them uncomfortable. Some people will even remove these objects, such as wristbands or earplugs, when they fall asleep. These devices can also be inadvertently dislodged during the night. As a result, these types of alarms are not very effective.
When there is more than one sleeping person within range of an alarm clock, it is to be expected that the people may desire to wake up at different times. The traditional audio and visual alarms disturb everyone in the vicinity. Therefore, couples or roommates would also benefit from a silent alarm clock that can wake a single individual.
It can be seen that a need exists for an alarm clock that is effective for a wide variety of users that also provides a gentle waking experience. Ideally, the alarm clock would incorporate known features and alarm options so that it is both easy-to-use and adaptable to individual preferences. The improved alarm clock would be comfortable, safe, and effective for all users, including those with special needs such as the hearing impaired or blind. The alarm clock could also wake a single individual from a plurality of sleeping people. The thermal alarm clock in accordance with the present invention provides such an alarm clock, and it overcomes the obstacles and deficiencies that have prevented the development of a satisfactory silent alarm clock.