A motion picture retrieval information storage apparatus (40) storing retrieval information for retrieving a motion picture, expressed by motion picture data, and constituted of one or more partial motion pictures (140, 142, 144, 146, 160) on the time axis includes a retrieval information generating section (102, 103, 104, 105) generating retrieval information corresponding to each of the one or more partial motion pictures on the basis of the motion picture data and a storage section (106) storing said retrieval information into a storage medium together with a correspondence information between the retrieval information and the motion picture data, wherein retrieval information generating section (102, 103, 104, 105) includes a first summary information generating section (103) for generating summary information (188) of one or more spatially partial motion pictures obtained by spatially splitting each of the one or more partial motion pictures (140, 142, 144, 146, 160) on the time axis.

With improvement on performance of a computer, realization of a storage apparatus having a large capacity, expansion of a communication infrastructure and other progresses, a service or the like has been coming into wide spread use that maintains a data base of a large amount of pictures and delivers a necessary picture when a necessity arises. Since a technology for digitizing a picture has progressed, an individual can build a data base of motion pictures.
When a data base of motion pictures has been built, then how to retrieve a desired picture therefrom becomes a problem. The present invention relates to an improvement on such a technology for retrieval of a motion picture.
The term "motion picture" used in the present specification includes both types of motion picture data not processed and constituted of RGB (Red, Green and Blue) signals and motion picture data digitized and coded according to a motion picture compression format as is in MPEG (Moving Picture Experts Group) or the like.
The term "scene" means a constituent unit of a motion picture including a consecutive plural picture frames and for example, of a motion picture obtained in one time shooting from the start to the end of recording or a motion picture for which editing has been finished, a length of the motion picture partitioned with two edit points at both ends thereof. An edit point includes, in a case, special effects such as fading and a dissolve. Furthermore, one scene may include plural scenes.
The term "a scene change point" means a position on the time axis at which two scenes are switched over therebetween and a leading frame directly after a scene is switched is referred to as "a scene change frame."
The term "a key frame" means a distinctive frame utilized in retrieval or the like, representing a scene or all of a motion picture.
A motion picture data is "contents" constituted of image information changing along the time axis. Motion picture data becomes an object of retrieval in the entirety. Therefore, the simplest method for retrieval of a desired motion picture is to select a desired motion picture by seeing all of a motion picture. However, it takes a time to see all of a motion picture. Therefore, when the number of motion pictures registered at a data base increases, it takes an extremely long time to take out a desired motion picture. Accordingly, this method is unrealistic.
In a generally adopted method for efficient retrieval of a motion picture, various kinds of information for retrieval (retrieval information) representing contents of respective motion pictures are prepared so as to be ready for use in retrieval of the respective motion pictures and retrieval is performed on the basis of the retrieval information.
Information used as retrieval information includes information attached to a picture (attached information), information expressing characteristics of a picture (characteristic information) and information expressing an outline of a picture (outline information). The attached information includes a title or a descriptive text prepared accompanying a motion picture. The characteristic information includes information expressing characteristics of a picture such as a frequency of a luminance value derived from a picture signal, motion information between frames, or the like. The outline information includes information of scene change points, key frames, or the like, which are determined by characteristic information of a picture or an input from the outside.
Of the above-described information, the characteristic information is especially convenient and important. For example, a key frame representing a motion picture can be selected by using characteristic information. The characteristic information is easily digitized and if a characteristic of a desired motion picture is digitized in the form of characteristic information, it can be easy to extract a motion picture having a characteristic coinciding with a requested characteristic information. In the following description, the term "retrieval information" means this characteristic information.
In general, a motion picture includes plural scenes. When a retriever retrieves a motion picture, the retrieval is performed in order to find out a desired frame or a desired scene included in a motion picture or one of a plurality of motion pictures which are an object for retrieval. A fundamental method for finding out a desired frame or a scene in a motion picture using retrieval information is to follow a procedure in which retrieval information relating to frames or retrieval information relating to scenes is obtained in advance and a frame or a scene is selected on the basis of such retrieval information.
An apparatus and process are disclosed in Japanese Patent Laying-Open No. 9-284702 in connection with this point in which a total sum of motion vectors of each frame and a continuity of a plurality of small regions constituting a frame, in a frame and between frames are adopted as feature of a frame for detection of a scene change point.
Furthermore, a control method is disclosed in Japanese Patent Laying-Open No. 7-38842 in a case where the average of motion vectors in magnitude and color histograms of pictures in each scene are used as a feature of the scene and a representative picture of each scene is displayed as a picture index.
If an apparatus for storing information for retrieving a motion picture (a motion picture retrieval information storage apparatus) and an apparatus for retrieving a motion picture (a motion picture retrieving apparatus) are fabricated, taking into consideration such prior art techniques, the apparatuses will be as shown below.
Referring to FIG. 1, a prior art motion picture retrieval information storage apparatus which is assumed includes: an analysis section 601 for analyzing inputted motion picture data to divide the data into scenes and output information expressing a structure of a motion picture such as scene dividing positions (scene change); a retrieval information generating section 602 for a frame unit, connected so as to receive an output of analysis section 601 and inputted motion picture data and for generating and outputting summary information of a picture such as a total sum of motion vectors corresponding to each of frames in a scene as retrieval information on the basis of motion picture structure information and motion picture data outputted from analysis section 601; a retrieval information generating section 603 for a scene unit, connected so as to receive an output of retrieval information generating section 602 for a frame unit and generating and outputting summary information such as the average value of motion vectors in magnitude for all of a scene as retrieval information on the basis of summary information of a frame unit outputted from retrieval information generating section 602 for a frame unit; a retrieval information generating section 604 for a motion picture for arranging, into a prescribed format, motion picture structure information outputted from analysis section 601, retrieval information of each frame outputted from retrieval information generating section 602 for a frame unit and retrieval information for all of a scene outputted from retrieval information generating section 603 for a scene unit to generate and output retrieval information corresponding to a motion picture; and a storage section 605 for storing original motion picture and the retrieval information corresponding to a motion picture outputted from retrieval information generating section 604 for a motion picture, in a state of both being related to each other, into a storage medium 606.
Note that one frame can be considered to be a unit of a motion picture obtained by temporal division of the motion picture. Hence, a frame can be called as one example of a temporally divided block.
In this specification, a notation of "retrieval information of a frame unit" is used for expressing retrieval information provided with a frame as a unit. Similarly, a notation of "retrieval information of a scene unit" is used for expressing retrieval information provided with a scene as a unit.
Referring to FIG. 2, a prior art motion picture retrieving apparatus which is assumed includes: a read-out section 701 for reading out motion picture retrieval information and motion picture data from storage medium 606; a retrieval information managing section 702 for holding each motion picture retrieval information supplied from read-out section 701 and receiving a request for retrieval information to output retrieval information of a scene unit and retrieval information of a frame unit together with structure information of a motion picture; a retrieval executing section 703 for a scene unit for receiving a request for retrieval with a scene as a unit to request retrieval information of a scene unit and motion picture structure information from retrieval information managing section 702 and detecting a scene meeting the retrieval request on the basis of the retrieval information of a scene unit and the motion picture structure information of a scene received to output information on the detected scene; a retrieval executing section 704 for a frame unit for receiving a request for retrieval with a frame as a unit to request retrieval information of a frame unit in a scene and motion picture structure information from retrieval information managing section 702 and detecting a scene or a frame meeting the retrieval request on the basis of the retrieval information of a frame unit in a scene and the motion picture structure information received to output information on the detected scene or frame; a data managing section 705 for taking out and outputting picture data corresponding to a detected scene or frame through read-out section 701 on the basis of information on the detected scene or information on the detected frame, outputted from retrieval executing section 703 for a scene unit and retrieval executing section 704 for a frame unit; and a retrieval control section 706 for responding to a retrieval instruction given by an operator to provide a retrieval request to retrieval executing section 703 for a scene unit or retrieval executing section 704 for a frame unit, and for repeating a process displaying motion picture data provided from data managing section 705 as a retrieval result to output the retrieval result at the end of retrieval.
The apparatus shown in FIG. 1 is considered to operate as follows: When motion picture data is inputted, analysis section 601 divides motion picture data into scene units. Analysis section 601 further outputs motion picture structure information.
Retrieval information generating section 602 for a frame unit generates summary information corresponding to a frame in a scene on the basis of motion picture structure information outputted from analysis section 601 and motion picture data. Retrieval information generating section 602 for frame unit further outputs the summary information thus generated to retrieval information generating section 603 for a scene unit and retrieval information generating section 604 for a motion picture as retrieval information.
Retrieval information generating section 603 for a scene unit generates summary information for all of a scene on the basis of the summary information of a frame unit provided from retrieval information generating section 602 for a frame unit. Retrieval information generating section 603 for a scene unit further provides the summary information thus generated to retrieval information generating section 604 for a motion picture as retrieval information.
Retrieval information generating section 604 for a motion picture receives motion picture structure information, retrieval information of a frame unit and retrieval information for all of a scene, from analysis section 601, retrieval information generating section 602 for a frame unit and retrieval information generating section 603 for a scene unit, respectively, and generates retrieval information corresponding to a motion picture, arranging the information into a prescribed format. Retrieval information generating section 604 for a motion picture provides the retrieval information corresponding to a motion picture thus generated to storage section 605.
Storage section 605 stores original motion picture data and the retrieval information provided from retrieval information generating section 604 for a motion picture into storage medium 606. At this time, storage section 605 attaches information indicating that the motion picture data and the retrieval information, to be both stored there, correspond with each other, to one or both of the motion picture data and the retrieval information; or stores the information of the correspondence separately from the motion picture data and the retrieval information.
Referring to FIG. 2, it is assumed that the prior art retrieving apparatus operates in the following way: At the start of retrieval, an operator gives a retrieval instruction to retrieval control section 706. Retrieval control section 706 selects retrieval of a scene unit or retrieval of a frame unit in response to the retrieval instruction.
It is assumed that, for example, retrieval of a scene is selected. Then, retrieval control section 706 provides a retrieval request to retrieval executing section 703 for a scene unit. Retrieval executing section 703 for a scene unit responds to this request to request retrieval information of a scene unit and motion picture structure information from retrieval information managing section 702 and receives the retrieval information of a scene unit and motion picture structure information outputted from retrieval information managing section 702.
Retrieval executing section 703 for a scene unit detects a scene meeting the retrieval request provided from retrieval control section 706 on the basis of the retrieval information and the motion picture structure information of a scene unit. Retrieval executing section 703 for a scene unit outputs information on the detected scene to data managing section 705.
Data managing section 705 reads out corresponding picture data from storage medium 606 through read-out section 701 on the basis of information on a scene provided from retrieval executing section 703 for a scene unit to provide the picture data to retrieval control section 706.
Retrieval control section 706 displays the picture data. The operator sees the displayed picture data to determine a next retrieval policy and gives a next retrieval instruction to retrieval control section 706. The similar process is repeated hereinafter.
A picture that the operator desires to take out from the data base is taken out in such a way, and then the retrieval finishes. A retrieval result is outputted from retrieval control section 706.
In the prior art, retrieval information of a scene is generated on the basis of retrieval information of frame units included in the scene. This is because of general understanding that the minimum unit constituting a scene is a frame.
Retrieval information of a scene is generated on the basis of retrieval information of frame units in such a way and then spatial features in each frame obtained by splitting the frame into small regions (retrieval information of a screen-split block units) can be used as retrieval information. However, a problem has been encountered since in a prior art apparatus, spatial features of a picture over all of a scene having a length on the time axis cannot be handled. In the present specification, such spatial features of a picture over all of a scene is referred to as "retrieval information of a spatially split block unit."
Consider, for example, a case where a scene is taken out that has a feature that an object in a vigorous motion is displayed in a middle portion of a screen. In the prior art, it was not able to take out such a scene from retrieval information of a scene unit but a necessity arose for retrieval using retrieval information attached to each of frames included in a scene. For this reason, in the prior art, such retrieval was performed with a very low efficiency.
The present invention has been made in light of the above-described problem and it is an object of the present invention to provide a motion picture retrieval information storage apparatus and a motion picture retrieving apparatus capable of efficiently performing retrieval of a motion picture using a new index expressing a feature of a scene with correctness.
It is another object of the present invention to provide a motion picture retrieval information storage apparatus and a motion picture retrieving apparatus capable of efficiently performing retrieval of a motion picture by extracting not only a feature of a scene by dividing a scene into blocks on the time axis but also another feature by splitting the scene only spatially without dividing the scene on the time axis.
It is still another object of the present invention to provide a motion picture retrieval information storage apparatus and a motion picture retrieving apparatus capable of efficiently performing retrieval of a motion picture using a new index expressing a feature of a scene with correctness, with an small amount of information for the retrieval.

Dynamic image search information recording apparatus and dynamic image searching device


An optical communications network architecture and associated method which employs time and wavelength-interleaving for homing between nodes/satellites and hubs and for grooming, while employing wavelength-division-multiplexed wavelength circuits between hubs without requiring cross-connects or routers therebetween.

As communications networks employing optical fiber and wavelength-division-multiplexing technologies (WDM) continue to evolve and carry an ever-increasing volume and variety of traffic between increasing numbers of individual nodes, network designers are faced with significant network design problems such as the management of their growth. Consequently architectures and/or methods that provide a more convenient framework for their optimization, graceful growth, and evolution would represent an advance in the art.

Optical telecommunications network and method


There is provided an anhydrous topically applicable aerosol foam composition comprising a foamable anhydrous liquid, a foaming agent selected from the group consisting of methyl glucose C.sub.16 -C.sub.18 aliphatic acid esters and a propellant, said propellant being capable of existing in gaseous form at ambient pressure and temperature and being present in an amount sufficient to produce a stable measurable foam but insufficient to produce a spray when said composition is ejected through an aerosol valve.

Non-aqueous aerosol foams have been disclosed heretofore. The selection of suitable foaming agents has however been a problem. U.S. Pat. No. 3,135,658 to Hanus and Oulette, discloses a method of treating bovine mastitis using a milk miscible, non-aqueous surfactant stabilized oleaginous liquid material, which foams upon contact with the milk in the cow's udder. The material which is administered does not, of itself, create a foam. A heat generating composition, one of the uses of the foams disclosed herein, is disclosed in U.S. Pat. No. 3,250,680 to Menkart and Ricciuti. This material is not a foam but utilizes aluminosilicate molecular sieve materials taken up in non-aqueous carriers such as polyethylene glycol, using sorbitan monostearate or polyoxyethylene sorbitan mono oleate as surfactant materials in the composition.
The first true non-aqueous aerosol foam is disclosed in U.S. Pat. No. 3,419,658 to Sanders. The Sanders foam however is limited to white mineral oil as the anhydrous liquid. The surfactants are also rather limited to their particular category. It should be noted that the same author published a somewhat extensive review of non-aqueous aerosol foams in Soap and Chemical Specialties, November 1960, page 87 through 109. White Sanders projects several uses for such materials, the non-aqueous liquids are limited to alkylene glycols and the ethers thereof. Furthermore, the surfactants are similarly of the propylene glycol monostearate or polyoxyethylene sorbitan monostearate type.
U.S. Pat. No. 3,770,648 to Leonard Mackles (one of the inventors herein) is directed to an aerosol foam utilizing a silicone resin as the foaming agent. U.S. Pat. No. 4,379,143 to Sherry, et al., is directed to a topical self-heating liquid or ointment used for analgesic purposes which comprises a zeolite and an anhydrous liquid. There is no disclosure in Sherry of the possibility of foaming the compositions since no foaming agent is disclosed. Furthermore, the invention is specifically limited to the use of the zeolite as the sole warming agent. U.S. Pat. No. 4,627,973 to Moran, et al., is directed to a skin mousse. Moran, et al., however comprises a substantial amount of water and cannot therefore be considered to fall within the category of the present invention.
U.S. Pat. No. 4,639,367 to Leonard Mackles is directed to an edible anhydrous aerosol foam composition comprising a foamable liquid oil, a dispersed solid, a foaming agent and a propellent. However, the disclosure of this invention being directed to edible foams, does not consider the requirements necessary for foaming a topically absorbable, as opposed to an ingestible, anhydrous liquid.
U.S. Pat. No. 4,752,465, which is a continuation-in-part of the aforementioned U.S. Pat. No. 4,639,367, is directed to a similar product having dispersed therein a particular proportion of solid particles.
It will thus be seen that the problem of providing an anhydrous topically applicable aerosol foam containing a foamable topically absorbable anhydrous liquid, has not been satisfactorily addressed by the prior art. In order to provide commercially satisfactory products in the aforementioned category, it is necessary that foams be preparable from a diverse group of anhydrous liquids such as glycerol fatty acid esters; e.g., soybean oil, corn oil, mono and diglycerol esters, acetylated monoglycerides, glyceryl triacetate; di and triethyl esters of organic acids, e.g., triethyl citrate, diethyl phthalate; aromatic acid esters, e.g., methyl salicylate, benzyl benzoate; and water soluble glycols, e.g., propylene glycol sand polyethylene glycol 400.
While the art, as shown by the aforementioned references, teaches a large number of foaming agents, it has been our surprising finding that these foaming agents are not satisfactory for foaming all of the aforementioned anhydrous liquids.


A nonvolatile semiconductor memory device particularly relates to an EEPROM having NAND-structured cells, and an optimizing programming method thereof. The device includes a memory cell array arranged as matrix having NAND cells formed by a plurality of serially-connected memory cells each of which is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, and enables electrical erasing by the mutual exchange of a charge between the charge storage layer and the substrate, a data latch circuit, a high voltage supply circuit, a current source circuit, a program checking circuit, and a program status detecting circuit. The programming state is optimized while being unaffected by the variance of process parameters, over-programming is prevented by the use of a verifying potential, and the performance of the chip is enhanced by automatically optimizing the programming with a chip's internal verification function. External control is not required, which enhances performance of the overall system. Also, a page buffer of an existing flash memory having the page mode function is employed, which is applicable to the currently used products.

The present invention relates to a nonvolatile semiconductor memory device and an optimizing programming method thereof, and more particularly to a EEPROM having NAND-structured cells and a method capable of optimizing the data programming using the same.
FIG. 1 is a plan view showing a conventional NAND-structured cell string of the first generation, and an equivalent circuit thereof. FIG. 2 shows control voltage conditions during a read operation and the timing of the control voltage during erasing and programming operations of a flash memory having the NAND structured cell string of the first generation.
The operating condition of a selected cell while erasing and programming in the conventional flash memory of first generation is as follows. First, while erasing, by supplying an erase voltage (17 V) to the gate CL6 of a selected cell CL6, and 0 V to the drain of the cell, electrons are injected from the drain to a floating gate by F-N (Fowler-Nordheim) tunneling, so that the cell's threshold voltage becomes positive.
While programming, by supplying 0 V to the gate of selected cell CL6 and a program voltage (22 V) to its drain, electrons are emitted from the floating gate to the drain of the cell by F-N tunneling, so that the threshold voltage of the cell becomes negative (refer to IEEE Journal of Solid-State Circuits, Oct. 1989, pp. 1238-1243). Therefore, while erasing and programming, stress is continuously imposed on the thin gate oxide layer for tunneling at the drain-side of the cell, which affects endurance (the number of write cycles) and data retention (the charge retention characteristic of a floating gate) of the cell. In particular, if the cell size is increasingly scaled down by achieving higher densities and larger capacitances, the above-described reliable characteristic of the cell is further degraded.
FIGS. 3A and 3B are schematic sectional views of a cell for illustrating the erasing and programming operations of a flash memory having a conventional NAND-structured cell of the second generation.
In the flash memory of the second generation, while erasing (FIG. 3A), 0 V is supplied to a gate CG of a selected cell, and an erase voltage (20 V) is supplied to a substrate SU, a source S, and a drain D, so that electrons are emitted from a floating gate FG of the cell to substrate SU, which makes the threshold voltage of the cell negative. While programming (FIG. 3B), a program voltage (20 V) is applied to gate CG of the selected cell, and 0 V is supplied to substrate SU, source S and drain D, so that electrons are injected from substrate SU to floating gate FG of the cell, which makes the threshold voltage of the cell positive. That is, the operational condition is contrary to that of the flash memory of the first generation, and the injection and emission of electrons are not limited to the cell's drain, but occur throughout its floating gate, substrate, source as well as the drain. Therefore, leakage current through the thin gate oxide layer for tunneling which is caused by stress during erasing and programming can be decreased, thereby greatly enhancing reliability of the cell. In addition to this, the threshold voltage of the cell is negative during erasing, and the problem of over-erasing is solved (refer to Symposium on VLSI Technology/1990, pp. 129 and 130).
However, as shown in FIG. 4A, since the threshold voltage distribution characteristic of the programmed cell degrades due to high voltage variations caused by the variation of process parameters during the cell programming in the flash memory of the second generation, an over-programming phenomenon occurs. In other words, even if only one cell is over-programmed within a cell string of a NAND-structured flash memory, the entire cell string is not read out. Accordingly, some means for preventing over-programming is required to maintain the optimized programming condition.
When the programming is repeated via program verification as shown in FIG. 4B, it can be noted that the threshold voltage of a cell is evenly distributed.
Thus, conventionally, programmed data states of a flash EEPROM are verified and the re-programming of data is carried out by an external verifying controller which performs the algorithm shown in FIG. 5, in order to optimize data programming. The data program verification algorithm loads data in a page mode and latches input data. Then, after programming the latched data into each cell of a selected cell line, data is read out to verify the programmed state of the data. When the read-out data is the same as an expected value, programming is completed. Meanwhile, when the read-out data differs from the expected value, as shown in FIG. 6, data bits corresponding to a cell which has failed in the programming of a "1" are maintained at "1," and data bits corresponding to a cell into which a data bit "1" or "0" is normally programmed are set to zero. The data processed as described above is repeatedly adjusted in the page mode, and the adjusted data is re-programmed into each cell of the selected cell-line. After repeating the programming, the data is read out to check the programmed state of each cell, so that the programming operation is finished when the programming is in the normal state. Otherwise, the cycling process of reading out data and programming the corrected data is repeated as described above when the programming is in an abnormal state (refer to IEEE Journal of Solid-State Circuits, April 1991, pp. 492-496).
However, according to the foregoing conventional verification algorithm, the process wherein data programmed by an external controller is read out and checked, and then loaded again for re-programming should be repeatedly carried out until the normal programmed state of every cell is detected, which degrades the performance of the overall system.

Nonvolatile semiconductor memory device and an optimizing programming method thereof


A system wherein a customer is provided with a debit card, cash value is loaded onto the customer's card and a customer account is set up. To allow money remittance, specific information is obtained of the customer and the recipient. These include their names, address, phone number and a recognizable government identification number. The personal information of the customer and the recipient is verified with a government agency. Once the personal information has been verified as acceptable, a recipient's account is established related to the customer's account. The amount of money requested by customer is transferred from the customer's account to the recipient's account. The recipient may be provided with a card providing access to the recipient's account. The recipient may be in the same country or in a foreign country.

The present disclosure is directed to a method for remitting money and more specifically to a remittance method including a debit card and a related account.
Debit cards are generally cards by which the customer can make purchases and the amount of the purchase is debited against either prestored value on the card and/or an account which is backed up by an account in a financial institution or merely by an account and financial institution. For some customers, they do not have the capability or wherewithal to open a banking account with a formal financial institution and therefore prepaid debit cards are common. These are used, for example, as phone cards or gifts cards. The present method uses such a reloadable value debit card as a basis for its remittance system.
The present disclosure provides the customer with a debit card, loads cash value on the customer's card and sets up a customer account. To allow money remittance, specific information is obtained of the customer and the recipient. These include their names, address, phone number and a recognizable government identification number. The personal data or information of the customer and the recipient is verified with a government agency. Once the transaction has been verified as acceptable, a recipient's account is established related to the customer's account. The amount of money requested by customer is transferred from the customer's account to the recipient's account. The recipient may be provided with a card providing access to the recipient's account. The recipient may be in the same country or in a foreign country.
To comply with the appropriate regulations, the amount of money that may be loaded onto a customer card or the number of cards issued to the customer is limited. Also there is recording and tracking of all card transfers. A central location verifies the financial transaction, establishes the recipient accounts, and transfers the amount of money from the customer's account to the recipient's account. The operation center provides for obtaining the customer information as well as obtains state and federal licenses to allow authorized agents to sell debit cards and load cash value on the customer card at point-of-sale devices under the licenses. The operation center records and tracks all card-to-account transfers.
These and other aspects of the present disclosure will become apparent from the following detailed description of the invention, when considered in conjunction with accompanying drawings.


An organic waste material treatment process comprising subjecting the organic waste material to conditions under which anaerobic digestion occurs followed by conditions under which aerobic composting occurs. Preferably, the organic waste material is pre-conditioned before anaerobic digestion by subjecting the organic waste material to aerobic composting conditions to facilitate a rise in temperature of the organic waste material. The treatment process is conducted in a single vessel, wherein air and water are evenly distributed to the contents of the vessel. A plurality of vessels may be interconnected, such that water may be extracted from one vessel, whose contents have undergone anaerobic digestion, then recirculated to an interconnected vessel to facilitate conditions for anaerobic digestion of the contents of the interconnected vessel.

It is well known that degradation of solid organic waste material to a bioactive, stabilised end product such as compost for gardens, can be achieved by treating the solid organic waste material under either anaerobic or aerobic conditions in which anaerobic or aerobic microorganisms, respectively, metabolise the waste material to the end product.
Aerobic decomposition of solid organic waste material takes place in the presence of oxygen. Energy produced during aerobic decomposition is released as heat, the temperature of the material frequently rising to 75° C. under ambient conditions. The resulting solid end product is generally rich in nitrates which is a readily bioavailable source of nitrogen for plants. Thus the bio-available resultant end product is an excellent fertilising material for gardens and has commercial value as such.
Anaerobic digestion of solid organic waste takes place in the absence of oxygen. Typically, the solid organic waste must be heated to a mesophilic or thermophilic temperature range in order for anaerobic microbial metabolism to be optimised. Energy produced during anaerobic digestion is conserved as biogas, predominantly methane and carbon dioxide. The resultant solid end product is generally rich in ammonium salts.
Ammonium salts are not readily bio-available for uptake by plants. It is known, therefore, to treat residues, resulting from anaerobic digestion, with conditions under which aerobic decomposition will proceed. Thus, the material is converted to one rich in nitrates and which is of commercial value.
Systems have generally been designed to cater discretely for each type of degradation, although some systems have been designed to combine both anaerobic and aerobic decomposition processes.
German Patent Number 4440750 relates to an apparatus for raw material and energy recovery from biomass which has an anaerobic fermentation unit, an aerobic composting unit, a gasification unit and a power generating plant. The apparatus utilises byproducts from the anaerobic fermentation unit and the aerobic composting unit to work synergistically to provide reduced amounts of residues and to improve raw material and energy production.
International Patent Application Number WO 94/24071 discloses treatment of organic bioresidues especially from municipal and industrial wastes, including raw and/or cooked food residues, agricultural wastes and/or plant vegetable components. The bioresidues are first homogenised, fermented in an anaerobic reactor wherein the resulting biogas is removed, and then the residual solids are transferred to a composting chamber.
These and other similar systems provide discrete and separate chambers or vessels for aerobic decomposition and anaerobic digestion, respectively. Material which has undergone one set of conditions is transferred to a separate location to undergo a secondary processing phase. The transfer of material from one location to another is not efficient in terms of time, costs and labour.
The present invention seeks to overcome, at least in part, some of the aforementioned disadvantages.

Organic waste material treatment process


A high availability aircraft network architecture incorporating smart points of presence (SPoP) is disclosed. In embodiments, the network architecture divides the aircraft into districts, or physical subdivisions. Each district includes one or more mission systems (MS) smart network access point (SNAP) devices for connecting MS components and devices located within its district to the MS network. Similarly, each district includes one or more air vehicle systems (AVS) SNAP devices for connecting AVS components and devices within the district to the AVS network. The AVS network may remain in a star or hub-and-spoke topology, while the MS network may be configured in a ring or mesh topology. Selected MS and AVS SNAP devices may be connected to each other via guarded network bridges to securely interconnect the MS and AVS networks.

Mission systems updates aboard aviation assets may require a long time to build, test, and certify. Current network architectures are optimized, with size, weight, and power (SWaP) considerations in mind, into interwoven "safe flight" and "mission success" systems. While it may be possible to separate architectures into independent, interactive air vehicle systems (AVS) and mission systems (MS) subsystems, the underlying "hub and spoke" network topologies require long wiring runs (doubly so in the case of duplex systems) which translates to increased wire weight, high rewiring costs, and high I/O density at the hubs, which complicate LRU designs and may require additional switches to extend the network topology.
Current interwoven architectures may require lengthy testing in order to achieve airworthiness certification. However, mission systems may be subject to far more rapid change and update cycles than air vehicle systems. While the emergence of autonomous systems may in turn require more redundant systems, legacy input/output (I/O) and power systems will persist as components of the solution space for the foreseeable future, as there is as yet no "one size fits all" I/O or power solution capable of supplanting them.

Smart point of presence (SPOP) aircraft-based high availability edge network architecture


Method for repairing hardware faults in memory chips. According to one embodiment, a method is provided for repairing bit errors in memory chips having a multiplicity of memory cells. The method can include detecting bit errors using an error identification algorithm. Further, the method can include determining the addresses of faulty memory cells. The method can also include setting a data bit initiating a repair mode in response to detecting a bit error. In the repair mode, a signal present on a data line to the memory chips can be interpreted as a repair command to perform a repair. In addition, the method can include repairing the bit errors by activating redundant memory cells.

In modern data processing systems, information needs to be processed, stored and read with as little error as possible. As memory size increases, the likelihood of an error rises, which in the worst case can result in the system crashing.
Memory chips, such as DRAMs, SRAMs or ROMs, are therefore tested precisely before they are installed in a finished product, such as a PC.
The memory chips can be checked for faults at several times in the memory chips' manufacturing process. A first test on the chips is normally effected at wafer level (the chip is still in the raw state and has not yet been inserted into a package), with faulty memory cells being identified and repaired by laser cutter, for example.
If the memory chip is already in a package, a fault can be located and repaired using a tester, for example. To this end, the chip needs to have redundant memory cells which are activated by means of e-fuses (electrically activatable fuses), for example.
The checking routines applied during the tests can never fully check a memory chip with certainty, however, and therefore have gaps. During normal operation of a DIMM module (DIMM: Dual Inline Memory Module), data combinations can therefore arise which provoke a fault. In this case, the end user has no way of locating and repairing faults.
It is known practice for data processing units to incorporate an error identification algorithm (ECC algorithm; ECC: Error Correction Code) which can identify and correct single-bit errors and possibly also multibit errors. In this case, however, error correction is performed exclusively using correction algorithms and leaves the actual cause of the error, namely the hardware fault in the chip, untouched.


A method of making a two-phase charge coupled device (CCD) includes forming a layer of a conductive material over and insulated from the surface of a body of a semiconductor material of one conductivity type having a channel region of the opposite conductivity type in the body and extending to the surface. Sections of a first masking layer are formed on the conductive material layer spaced along the channel region. A conductivity modifying dopant is implanted into the channel region through the spaces between the sections of the first masking layer. A layer of a second masking layer is formed over the sections of the first masking layer and on the surface of the conductive material layer in the spaces between the sections of the first masking layer. A layer of indium-tin oxide (ITO) is formed over the portions of the second masking layer which extend across the ends of the sections of the first masking layer, and a layer of carbon is formed on the second masking layer between the ITO layers. The ITO layers along the ends of the sections of the first masking layer are then removed, and exposed portions of the second masking layer are removed. The portions of the conductive material layer under the removed portions of the second masking layer are then removed so as to leave the conductive material layer divided into individual very closely spaced apart (submicron spacing) gate electrodes.

A CCD, in general, comprises a body of a semiconductor material, such as single crystalline silicon, having a channel region in and along a surface of the body. A layer of an insulating material, typically silicon dioxide, is on the surface of the body and over the channel region. A plurality of conductive gate electrodes, typically of doped polycrystalline silicon, are on the insulating layer and extend across the channel region. The gate electrodes are positioned along the entire length of the channel region.
In a two-phase CCD, the gate electrodes are arranged in two sets which alternate along the channel region. The gate electrodes of one set are connected to a first phase potential, and the gate electrodes of the other set are connected to a second phase potential. A true two-phase CCD also typically includes in the body a barrier region under an edge of each of the gate electrodes and extending across the channel region. The barrier regions prevent the charge from moving backwards along the channel region.
The two sets of gate electrodes could be formed from a single layer of the conductive material by depositing the single layer and defining it by photolithography and etching to form the spaced gate electrodes along the channel region. However, using commercial type photolithographic and etching techniques and equipment, it is difficult to form the gate electrodes having very narrow submicron gaps therebetween with the gaps being uniform across the entire width of the gate electrodes. Since relatively wide and/or non-uniform gaps can form potential barriers and/or wells between the gate electrodes, they can interfere with the transfer of charge from one gate electrode to the next. Therefore, it has been the practice to form the gate electrodes from two separate levels (layers) of the conductive material.
For a two level system, a first layer of the conductive material is deposited and defined to form one set of the gate electrodes. The first set of gate electrodes are then covered with a layer of an insulating material, typically silicon dioxide. A second layer of the conductive material is then deposited over the first set of gate electrodes and the gaps between the first set of gate electrodes. The second layer of the conductive material is then defined to form the second set of gate electrodes which are between the gate electrodes of the first set. Also, each of the gate electrodes of the second set overlaps the adjacent gate electrodes of the first set. U.S. Pat. No. 4,613,402 (Losee et al.), issued Sep. 23, 1986, and U.S. Pat. No. 3,853,634 (Amelio et al.), issued Dec. 10, 1974, each describes a method of making a two-phase CCD having a two level gate electrode structure. Since the gate electrodes overlap each other, there are no gaps therebetween which can form undesirable potential barriers and/or wells. However, two level gate electrode structure is non-planar since portions of the second set of electrodes extend over the first set of electrodes. Also, there exists undesirable capacitance between the two sets of gate electrodes where they overlap.
Heretofore, submicron-gap, planar gate CCD structures have been reported, but they have been primarily three or four-phase devices. A two-phase submicron gap CCD, described in an article entitled "Charge-Coupled Devices With Submicron Gaps" by V. J. Kapoor, published in IEEE Electron Device Letters, Vol. EDL-2, No. 4, page 92, April 1981, suffers from formation of potential wells between the barrier and storage regions within each phase resulting in low transfer efficiency. This is because this device is not a true two-phase structure, but has separate electrodes for the individual barrier and storage regions within each phase. Each of U.S. Pat. No. 4,994,405 (K. M. Jayakar), issued Feb. 19, 1991, application for U.S. Ser. No. 995,393 of E. G. Stevens et al., filed Dec. 18, 1992 and having a common assignee with the present application, and application for U.S. Ser. No. 945,073 of J. P. Lavine, filed Sep. 15, 1992 and having a common assignee with the present application, discloses a method of making a true two-phase CCD having a planar gate electrode structure. Although the method described in each of these applications provides a true two-phase CCD having a planar gate electrode structure, the methods are relatively complex to carry out. Therefore, it would be desirable to have a relatively simple method of making a true two-phase CCD having a single level gate electrode structure so that the gate electrode is planar and has submicron gaps between the gate electrodes.

Method of making two-phase charge coupled device


In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Today large system-on-chips (SOC) are being designed that include a myriad of different types of complex functional circuits. Standardized IC test interfaces and architectures are needed for testing these functional circuits within the IC, and also for testing the board/substrate on which the IC will eventually reside.
This disclosure describes two separate IC test standards, IEEE 1149.1, adopted on Feb. 15, 1990, and IEEE P1500, provisional, that can be used to test circuitry embedded within ICs. Each IC test standard has its own test interface and architecture, and unique testing features. Thus an IC may require both test standards to be implemented to achieve an overall testing goal. Having to include both test standards in ICs can be costly in circuit area overhead and test complexity.
To facilitate the understanding of the present disclosure, an overview of two test standards to be combined is provided. FIGS. 1-17 give an overview of IEEE standard 1149.1 and FIGS. 18-45 give an overview of IEEE standard P1500.
IEEE 1149.1 Overview
FIG. 1 illustrates an example of a test interface 104 and architecture 102 that is commonly used in both ICs and core circuits within ICs. The test interface and architecture are well known and were standardized in 1990 as IEEE Standard 1149.1. While initially developed as an IC test standard for primarily supporting board level IC to IC interconnect testing, this standard has evolved into additional uses and formed the basis for a family of additional IEEE standards.
The test interface 104 includes a test access port (TAP) state machine controller and signals TDI, TCK, TMS, TRST, and TDO. The test architecture 102 includes an instruction register and a set of selectable data registers. As seen in FIG. 1, the data registers consists of various types including but not limited too, a boundary scan register, digital test registers, debug/emulation registers, programming registers, mixed signal test registers, and a bypass register. The TAP receives a test clock (TCK), test mode select (TMS), and test reset (TRST) input signals. The TAP responds to the TCK and TMS input signals to shift data through either the instruction register or a selected data register from the test data input (TDO) signal to the test data output (TDO) signal. The TAP has proven to be an efficient and popular test control interface for ICs and cores.
For example, other TAP based standards have evolved from the original IEEE 1149.1 standard. These other TAP based standards include; (1) IEEE standard 1149.4 (a mixed signal test standard), (2) IEEE standard 1149.6 (an advanced interconnect test standard), (3) IEEE standard 1532 (an in-system programming standard), and (4) IEEE standard 5000 (a debug/emulation standard). The naming of the data registers in FIG. 1 indicates the presence of these additional TAP based IEEE standards. In addition to the multiplicity of TAP based IEEE standards, numerous core and/or IC provider companies have developed proprietary emulation and debug architectures based upon the IEEE 1149.1 TAP and architecture of FIG. 1.
FIG. 2 is a different view of the FIG. 1 test interface and architecture emphasizing the instruction registers ability to select one of the data registers for access between TDI and TDO.
FIG. 3 is a block diagram of the key circuit elements of FIGS. 1 and 2. The TAP 318 regulates TDI to TDO access of the instruction register 314 via instruction register control bus 302 and the TDI to TDO access of a selected one of a set of data registers 316 via data register control bus 304. As seen, a gating circuit 308 receives input 306 from the instruction register to allow the data register control bus 304 from the TAP to pass through the gating circuit and be output on bus 310 to operate a selected data register. The gating circuit is typically viewed as being part of the instruction register and is shown in FIG. 2 as the dotted box on the instruction register. The data registers 316 also receive mode control input 312 from the instruction register to place them in various modes of operation.
FIG. 4 indicates the TAP's state controller diagram. The TAP is clocked, via TCK, through these states in response to input on TMS. Since all TAPs operate from this diagram, standardized plug and play compatibility between TAPs is guaranteed. The operation of the TAP controller is well known.
FIG. 5 illustrates typical TAP 318 input (TCK, TMS, TRST) and output signals. The ClockIR, ShiftIR, and UpdateIR form the signals on bus 302 to the instruction register. The ClockDR, ShiftDR, and UpdateDR form the signals on bus 304 to gating circuit 308. The Select signal is used to select either the instruction register or selected data register to be coupled to TDO. The Reset signal is used to reset the instruction register and optionally the data registers whenever the TAP is in the TRST state of FIG. 4. As seen in FIG. 5, a TAP state bus 502 can be output from the TAP to indicate what state of FIG. 4 the TAP is in. The TAP state bus is useful in controlling synchronous instruction and data register designs and is therefore shown as being part of the instruction and data control buses 302 and 304, respectively.
FIGS. 6, 6A and 6B illustrate a gated instruction register design style. The instruction register comprises a shift register 602, an update register 604, and an instruction decode logic 606. The shift register comprises serially connected scan cells 608 that operate to capture and shift data from TDI to TDO. The update register comprises a flip-flop or latch 610 for each shift register scan cell 608. In operation, the TAP outputs control (ClockIR and ShiftIR) to cause the shift register to capture data (IN) then shift data from TDI to TDO. After capturing and shifting, the TAP outputs control (UpdateIR) to cause the latches 610 of update register 604 to load data from the scan cells 608. The latched data is output from the update register to the decode logic, where it is decoded into control output bus 612 which, among other things, drives buses 306 and 312. While not shown, both the scan cell 608 and update latch 610 can be reset by the reset output from the TAP.
FIG. 7 illustrates a timing example of the TAP performing the above described gated instruction register scan operation. As seen, the TAP gates the ClockIR on in the CaptureIR state to perform the capture operation (C) and in the ShiftIR state to perform the shift operations (S). The TAP manipulates the ShiftIR output to control the scan cells 608 to perform the capture and shift operations. Also, the TAP gates a clock pulse on UpdateIR during the UpdateIR state to perform the update operation (U).
FIGS. 8, 8A, and 8B illustrate a synchronous instruction register design style. The synchronous instruction register design style differs from the gated instruction design style in that the shift register 802 is comprised of scan cells 804 which operate from the free running TCK input, not the ClockIR input of FIG. 6. The shift register 802 receives TAP state (502) input from bus 302 to indicate when the TAP is in the CaptureIR state and ShiftIR state. When the TAP is in the CaptureIR state the scan cells 804 capture data (IN) and when the TAP is in the ShiftIR state the scan cells shift data from TDI to TDO. When the TAP is not in the CaptureIR or ShiftIR state, the scan cells hold their present value. The operation of the update register 604 and decode logic 606 is the same as describe in FIG. 6.
FIG. 9 illustrates a timing example of the TAP performing the above described synchronous instruction register scan operation. As seen, when the TAP enters the CaptureIR state the scan cells 804 perform a capture operation (C) and when the TAP enters the ShiftIR state the scan cells perform shift operations (S). As with the FIG. 7 timing diagram, the TAP gates a clock pulse on UpdateIR during the UpdateIR state to perform the update operation (U).
FIGS. 10 and 10A illustrate a first gated data register design style. The data register 1002, referred to as data register 1, is an example of a gated boundary scan data register that could be used at the I/O boundary of a core or IC. Data register 1 comprises serially connected boundary scan cells 1004 each having an scan cell 1006 operable to capture data from the IN input and to shift data from TDI to TDO, and an update latch 1008 operable to load data from the scan cell. If selected by the instruction in the instruction register, gates 1010-1012 within gating circuit 308 are enabled by a signal 1014 on bus 306 to couple the TAP's ClockDR, ShiftDR, and UpdateDR outputs to data register 1's Clock-1, Shift-1, and Update-1 inputs, respectively. This enables scan access of data register 1. In the figures of the provisional application from which priority is claimed, a capital "A" in a gate symbol indicates the gate is an AND function and a capital "O" in a gate symbol indicates the gate is an OR function. During a data scan operation, the TAP outputs control (ClockDR and ShiftDR) to cause the scan cells 1006 of boundary scan cells 1004 to capture data (IN) then shift data from TDI to TDO. After capturing and shifting, the TAP outputs control (UpdateDR) to cause the update latches 1008 of the boundary scan cells to load data from the scan cells 1006. If data register 1 is in test mode, the Mode-1 input from instruction register bus 312 will be set to cause the data in update latch 1008 to be output from data register 1002.
FIG. 11 illustrates a timing example of the TAP performing the above described gated data register scan operation. As seen, the TAP gates Clock-1 (ClockDR) on in the CaptureDR state to perform the capture operation (C) and in the ShiftDR state to perform the shift operations (S). The TAP manipulates Shift-1 (ShiftDR) to control the scan cells 1006 to perform capture and shift operations. Also, the TAP gates a clock pulse on UpdateDR-1 during the UpdateDR state to perform the update operation (U). It is important to note for later reference in this and following timing figures that the dotted box area beginning with A and ending with B indicates when the TAP is in the ShiftDR state.
FIGS. 12 and 12A illustrate a first synchronous data register design style. The data register 1202, referred to as data register 2, is an example of a synchronous boundary scan data register that could be used at the I/O boundary of a core or IC. Data register 2 comprises serially connected boundary scan cells 1204 each having an scan cell 1206 operable to capture data from the IN input and to shift data from TDI to TDO, and an update latch 1208 operable to load data from the scan cell. If selected by the instruction in the instruction register, gates 1210-1214 within gating circuit 308 will be enabled by a signal 1216 on bus 306 to couple the TAP's CaptureDR state, ShiftDR state, and UpdateDR outputs to data register 2's Capture-2, Shift-2, and Update-2 inputs, respectively. This enables scan access of data register 2. The Clock-2 input of data register 2 is coupled to the free running TCK. During a data scan operation, the TAP outputs state indications (bus 502 & 304) to cause the scan cells 1206 to capture data (IN) during the CaptureDR state (Capture-2 set high) then shift data from TDI to TDO during the ShiftDR state (Shift-2 set high). As seen, the scan cell holds its state when the TAP is not in the CaptureDR or ShiftDR states. After capturing and shifting, the TAP outputs control (UpdateDR) to cause the update latches 1208 of the boundary scan cells to load data from the scan cells 1206. If data register 2 is in test mode, the Mode-2 input from instruction register bus 312 will be set to cause the data in update latch 1208 to be output from data register 1202.
FIG. 13 illustrates a timing example of the TAP performing the above described synchronous data register scan operation. As seen, when the TAP is in the CaptureDR state, the Capture-2 input is high causing data register 2 to capture data (C). When the TAP is in the ShiftDR state the Shift-2 input is high causing data register 2 to shift data (S). Also, the TAP gates a clock pulse on UpdateDR-2 during the UpdateDR state to perform the update operation (U).
FIGS. 14 and 14A illustrate a second gated data register design style. The data register 1402, referred to as data register 3, is an example of a gated scan data register that could be used as an internal scan path of a core or IC. Data register 3 comprises serially connected conventional scan cells 1404 each operable to capture data from the IN input and to shift data from TDI to TDO. If selected by the instruction in the instruction register, multiplexers 1405-1407 within gating circuit 308 are enabled by a signal 1408 on bus 306 to couple the TAP's ClockDR and ShiftDR outputs to data register 3's Clock-3 and Shift-3 inputs, respectively. Multiplexers 1405-1407 are used instead of gates since switching between a functional and test clocks and between functional and test modes is required when using scan cells that are shared for functional and test operations. This enables scan access of data register 3. During a data scan operation, the TAP outputs control (ClockDR and ShiftDR) to cause the scan cells 1404 to capture data (IN) then shift data from TDI to TDO.
FIG. 15 illustrates a timing example of the TAP performing the above described gated data register scan operation. As seen, the TAP gates Clock-3 (ClockDR) on in the CaptureDR state to perform the capture operation (C) and in the ShiftDR state to perform the shift operations (S). The TAP manipulates Shift-3 (ShiftDR) to control the scan cells 1404 to perform capture and shift operations.
FIG. 16 illustrates a second synchronous data register design style. The data register 1602, referred to as data register 4, is an example of a synchronous scan data register that could be used as an internal scan path of a core or IC. Data register 4 comprises serially connected scan cells 1604 each operable to capture data from the IN input and to shift data from TDI to TDO. If selected by the instruction in the instruction register, multiplexers 1606-1610 within gating circuit 308 will be enabled by a signal 1612 on bus 306 to couple the TAP's CaptureDR state output, the TAP's ShiftDR state output, and the TCK to data register 4's Capture-4, Shift-4, and Clock-4 inputs, respectively. Again, multiplexers 1606-1610 are used instead of gates since switching between a functional and test clocks and between functional and test modes is required when using scan cells that are shared for functional and test operations. This enables scan access of data register 4. During a data scan operation, the TAP outputs state indications to cause the scan cells 1604 to capture data (IN) during the CaptureDR state (Capture-4 set high) then shift data from TDI to TDO during the ShiftDR state (Shift-4 set high). As seen, the scan cell holds its state when the TAP is not in the CaptureDR or ShiftDR states.
FIG. 17 illustrates a timing example of the TAP performing the above described synchronous data register scan operation. As seen, when the TAP is in the CaptureDR state, the Capture-4 input is high causing data register 4 to capture data (C). When the TAP is in the ShiftDR state the Shift-4 input is high causing data register 4 to shift data (S).
IEEE P1500 Overview
FIG. 18 illustrates an example of a test interface 1804 and architecture 1802 that is being developed as IEEE standard P1500. This standard test interface and architecture is being developed for the purpose of testing cores within ICs. While not yet standardized, the state of the P1500 standard is stable and near complete. The architectural similarities between the IEEE P1500 standard of FIG. 18 and the previously described IEEE 1149.1 standard of FIG. 1 are clearly seen.
The test interface 1804 includes a wrapper serial port (WSP) and signals WSI, Clock, Capture, Shift, Update, Transfer, Select, Reset, and WSO. The architecture 1802 includes a wrapper instruction register and a set of selectable wrapper data registers. As seen in FIG. 18, the wrapper data registers include wrapper boundary registers, digital test registers, and a wrapper bypass register. The WSP receives clock, capture, shift, update, transfer, select, and reset input signals. The WSP responds to these signals to shift data through either the wrapper instruction register or a selected wrapper data register from the wrapper serial input (WSI) signal to the wrapper serial output (WSO) signal. Unlike the TAP of FIG. 1, which is a state machine, the WSP is simply a combinational decode circuit. With the exception that IEEE standard P1500 uses a WSP in the test interface 1804 and IEEE standard 1149.1 uses a TAP in the test interface 104, the two standards are very similar architecturally. For the purpose of simplifying the following description, it will be assumed that the IEEE P1500 architecture 1802 can be viewed as being the same as the previously described IEEE 1149.1 architecture 102 of FIG. 1. While there may be subtle differences between the two architectures, these differences are transparent to the overall objective of the present disclosure.
FIG. 19 is a different view of the FIG. 18 test interface and architecture emphasizing the instruction registers ability to select one of the data registers for access between WSI and WSO.
FIG. 20 is a block diagram of the key circuit elements of FIGS. 18 and 19. The WSP 202 regulates WSI to WSO shifting of the instruction register 314 via instruction register control bus 302 and the WSI to WSO shifting of a selected data within a set of data registers 316 via data register control bus 304. As seen, a gating circuit 308 receives input 306 from the instruction register to allow the data register control bus 304 from the WSP to pass through the gating circuit and be output on bus 310 to operate the selected data register. The gating circuit is typically viewed as being part of the instruction register and is shown in FIG. 18 as the dotted box on the instruction register. The data registers 316 also receive mode control input 312 from the instruction register to place them in various modes of operation.
FIG. 21 illustrates an example WSP 202 circuit. As mentioned, the WSP is a combinational circuit and does not include any sequential memory elements. Like the TAP, the WSP has a control bus 302 of outputs, ClockIR, ShiftIR, CaptureIR, and UpdateIR, that are used to control scanning of the instruction register, and a control bus 304 of outputs, ClockDR, ShiftDR, CaptureDR, UpdateDR, and TransferDR, that are used to control scanning of a selected data register.
The operation of the WSP is simple. If the select input to the WSP is low the select output from the WSP is low and the WSP couples the clock, shift, capture, update, and transfer inputs to the ClockDR, ShiftDR, CaptureDR, UpdateDR, and TransferDR outputs to enable scanning of a data register. The low on the select output selects the data register between WSI and WSO. If the select input to the WSP is high the select output from the WSP is high and the WSP couples the clock, shift, capture, and update inputs to the ClockIR, ShiftIR, CaptureIR, and UpdateIR outputs to enable scanning of the instruction register. The high on the select output selects the instruction register between WSI and WSO. The reset output from the WSP is coupled to the reset input to the WSP and is used, as was the reset output of the TAP in FIG. 5, to reset the instruction register and optionally the data registers when asserted low. The WSP Transfer input and TransferDR output signals are new data register control signals introduced by IEEE P1500. An example of their use will be described later in regard to FIGS. 40-45.
FIGS. 22, 22A, 22B, and 23 are provided to illustrate that the WSP is capable of providing timing and control to the gated instruction register design of FIG. 6. FIG. 23 illustrates that the WSP can mimic the gated TAP timing diagram of FIG. 7. The dotted line clock pulses shown on portions of the inactive clock input signal indicates TCKs that would be input to the TAP during the instruction register scan timing diagram of FIG. 7.
FIGS. 24, 24A, 24B, and 25 are provided to illustrate that the WSP is capable of providing timing and control to the synchronous instruction register design of FIG. 8. FIG. 25 illustrates that the WSP can mimic the synchronous TAP timing diagram of FIG. 9. Being able to mimic TAP instructions and, as will be shown below, data register scan timing is important since it provides for serially connecting the IEEE 1149.1 and IEEE P1500 standard test architectures together in a daisy-chain arrangement.
FIGS. 26, 26A, and 27 are provided to illustrate that the WSP is capable of providing timing and control to the gated data register 1 design of FIG. 10. FIG. 27 illustrates that the WSP can mimic the gated TAP timing diagram of FIG. 11. Again, the dotted line clock pulses shown on portions of the inactive clock input signal indicates TCKs that would be input to the TAP during the data register scan timing diagram of FIG. 11.
FIG. 28 illustrates an alternate method of scanning gated data register 1 of FIG. 26. Since the WSP is combinational in operation it does not have to mimic TAP state transition timing. Indeed one of the primary reasons IEEE P1500 uses the WSP instead of the TAP is that the WSP provides greater flexibility in controlling scan operations. For example, in FIG. 28 the WSP provides scan timing control to data register 1 where the shift (S), capture (C), and update (U) operations are occurring in a tightly timed sequence.
FIGS. 29, 29A, and 30 are provided to illustrate that the WSP is capable of providing timing and control to the synchronous data register 2 design of FIG. 12. FIG. 31 illustrates that the WSP can mimic the synchronous TAP timing diagram of FIG. 13.
FIG. 31 illustrates an alternate method of scanning synchronous data register 2 of FIG. 26, whereby the shift (S), capture (C), and update (U) operations are occurring in a tightly timed sequence.
FIGS. 32, 32A, and 33 are provided to illustrate that the WSP is capable of providing timing and control to the gated data register 3 design of FIG. 14. FIG. 33 illustrates that the WSP can mimic the gated TAP timing diagram of FIG. 15.
FIGS. 34 and 35 illustrate alternate methods of scanning gated data register 3 of FIG. 32. FIG. 34 illustrates a tightly timed capture (C) and shift (S) scanning sequence, and FIG. 35 illustrates a tightly timed back to back capture (C) and shift (S) sequence.
FIGS. 36, 36A, and 37 are provided to illustrate that the WSP is capable of providing timing and control to the synchronous data register 4 design of FIG. 16. FIG. 37 illustrates that the WSP can mimic the synchronous TAP timing diagram of FIG. 17.
FIGS. 38 and 39 illustrate alternate methods of scanning synchronous data register 4 of FIG. 36. FIG. 38 illustrates a tightly timed capture (C) and shift (S) scanning sequence, and FIG. 39 illustrates a tightly timed back to back capture (C) and shift (S) sequence.
FIGS. 40 and 40A illustrate one example of how the IEEE P1500 Transfer signal might be used during test. Data register 5, 4002, is comprised of a plurality of serially connected scan cells 4004, each capable of performing shift and transfer operations. As seen, the scan cell 4004 circuit example consists of an input multiplexer 4012, a series of flip flops 4014, and an output multiplexer 4016. The input multiplexer 4012 serves to either shift data from TDI (WSI) to TDO (WSO) in shift mode (Shift5 is high) or to shift in data from the output (OUT) of the output multiplexer 4016 during transfer mode (Transfer5 is high). Gates 4006 and 4008 of gating circuit 308 are enabled by signal 4010 to couple the ClockDR and TransferDR outputs from the WSP to the Clock-5 and Transfer-5 inputs to data register 5, respectively, when a transfer instruction is loaded into the instruction register.
A pair of Mode-5 signals, Mode-5a and 5b, are output from the instruction register on bus 312 to control the scan cell output multiplexers 4016. During transfer operations, the output multiplexers 4016 of scan cells 4004 that output test signals will be controlled to couple the output of the flip flops 4014 to the output multiplexer output (OUT), while the output multiplexers 4016 of scan cells 4004 that input test signals will be controlled to couple the input (IN) of the scan cell to the output (OUT) of output multiplexers 4016. Thus two separately controllable Mode-5 signals, Mode-5a and 5b, will typically be required from the instruction register to achieve a desired output multiplexer test setting.
FIG. 41 illustrates an example transfer test arrangement whereby an AND gate function 4102 to be tested is bounded by two cells A and B 4004 for providing input to the AND gate and one cell C 4004 for receiving output from the AND gate. The AND gate can exist within a core containing the IEEE P1500 architecture or external to a core containing the IEEE P1500 architecture. Also, the cells A-C may be in the same data register 5 of one IEEE P1500 architecture or be in separate data register 5's of separate IEEE P1500 architectures. The dotted line beginning at the TDI input of cell A and ending at the TDO output of cell C indicates the process of shifting data through the cells to load test input data to cells A and B and unload test output data from cell C. As seen, the shifting occurs in response to Shift-5 being high, Transfer-5 being low, and Clock-5 being active. While for simplicity the example of FIG. 41 shows the serial path to only include cells A-C, additional scan cells of various types may exist in the scan path as well.
FIG. 42 illustrates cells A, B, and C 4004 in their transfer mode. As seen, the transfer mode occurs in response to Shift-5 being low, Transfer-5 being high, and Clock-5 being active. During transfer mode, cells A and B circulate their data, as shown in dotted line, from the output (OUT) of their output multiplexers to the input of their input multiplexers, to provide the test signal input to AND gate 4102. Simultaneously, cell C shifts in the test signal output from AND gate 4102, again as shown in dotted line. The Mode-5a and Mode-5b inputs to the cell output multiplexers have been set, as previously described, for this particular transfer test arrangement.
FIG. 43 shows a first transfer test input and output session to AND gate function 4102. FIG. 44 shows a second transfer test input and output session to AND gate function 4102. The first transfer test session tests the AND gate's ability to pass a stream of data from its In1 input to its Out output, while its In2 input is high. The second transfer test session tests the AND gate's ability to pass a stream of data from its In2 input to its Out output, while its In1 input is high.
FIG. 45 illustrates an example timing diagram for the transfer test of the test arrangement of FIGS. 41-44. Firstly, the cells A-C are shifted, during time frame 4502, to load the test input patterns to be applied during the first transfer test session of FIG. 43. Secondly, the first transfer test session of FIG. 43 is executed during time frame 4504. Thirdly, the cells A-C are shifted, during time frame 4506 to load the test input patterns to be applied during the second transfer test session of FIG. 44 and to unload the results of the first transfer test session of FIG. 43. Fourthly, the second transfer session of FIG. 44 is executed during time frame 4508. Lastly, the cells A-C are shifted, during time frame 4510 to unload the test results of the second transfer test session.
While the above description has provided one detailed example of how an IEEE P1500 transfer test may be performed, there are numerous other ways of designing and operating scan cells to achieve transfer testing.
FIG. 46 represents the problems presented if both TAP based (i.e. IEEE 1149.1, 1149.4, 1149.6, 1532, 5000, and ad-hoc) and the WSP based (i.e. IEEE P1500) standard architectures (domains) are required in core and/or IC designs. In FIG. 46, box 4602 represents a circuit which can be either a core circuit for use in an IC or an entire IC. The circuit 4602 is shown including both TAP based standards (1149.1, 1149.4, 1149.6, 1532, 5000, and/or ad-hoc) and the WSP based standard (IEEE P1500).
As seen in FIG. 46, each of the TAP based standards included in circuit 4602 advantageously share a common TAP 318 interface and architecture 4604. The architecture 4604 includes a commonly shared instruction register 314, a commonly shared set of selectable data registers 316, commonly shared gating circuitry 308, and commonly shared instruction 302 and data 304 control buses to the commonly shared TAP 318. The external TAP test bus 4608 is achieved using 5 signals (TDI, TDO, TCK, TMS, and TRST). Regardless of whether circuit 4602 is a core or an IC, these 5 signals are dedicated and reserved for use in accessing the TAP to perform testing or other operations with the common architecture 4604. The availability of the dedicated TAP test bus has proven very beneficial since it provides non-intrusive access to a functionally operating circuit 4602 to perform real time test, emulation, debug, and other operations. The dedicated TAP test bus has also lead to an ever increasing set of TAP interface support tools supporting test, emulation, debug, programming, and other TAP based operations.
As seen in FIG. 46, the IEEE P1500 WSP 202 interface and architecture 4610 is separate from the IEEE 1149.1 TAP 318 interface and architecture 4604. Therefore the IEEE P1500 architecture is forced to include its own instruction register 314, its own set of selectable data registers 316, its own gating circuitry 308, and its own instruction 302 and data 304 control buses to WSP 202. The primary reason for this forced separation is due to the differences in operation between the TAP 318 and WSP 202 interfaces. The external test bus 4612 to WSP 202 is achieved using 9 signals (WSI, WSO, Clock, Capture, Shift, Update, Transfer, Select, and Reset). If circuit 4602 is a core, these 9 signals will be dedicated terminals of the core. However, if circuit 4602 is an IC, these 9 signals are not required to be dedicated ICs pins, as are the TAP pins 4608, and will typically be shared with functional pins on the IC and invoked only when testing of the IC is required. If they are shared it is not possible to use them for real time test, emulation, debug, or other operations that can be used with the TAP 318 and its dedicated test bus 4608. The non-dedicated nature of the WSP test bus 4612 will most likely limit use of IEEE P1500 in other areas such as emulation and debug. However, since improved testing of core based ICs is the primary objective of IEEE P1500 that limitation will not matter, especially since TAP based solutions already exist for these expanded needs.
If the circuit 4602 is a core for use in an IC it will require a 5 signal bus for interfacing to the TAP 318 and a 9 signal bus for interfacing to the WSP 212. The total number of signals therefore that need to be routed in the IC for connection to core 4602 is 14. In some ICs the routing of 14 test signals to a core can be prohibitive, especially if multiple cores exist with each potentially needing its own bus of 14 test signals. Thus having two separate standards implemented in a core, each with separate test bus interfaces, can lead to problems related to wire routing area overhead.
From the above description it is clear that if TAP based and WSP based domains are used in a circuit 4602, the area overhead will be increased due to the need of the WSP domain to have its own architecture separate from the TAP domain architecture. Also it is clear that access to WSP domains, unlike TAP domains, will be limited to testing circuits 4602 when circuits 4602 are in a non-functional mode of operation. Further, it is clear that due to the nature of the non-dedicated WSP 9 pin interface, the range of WSP interface support will be most likely limited to testing. Lastly, having both TAP and WSP based domains in cores can lead to IC wire routing and density problems.

IR enabled gating of TAP and WSP shift, capture, transfer


The present invention relates to a sliding device (100) for a vehicle seat, comprising a pair sliding tracks (10), each including a lower rail (20) and an upper rail (30), which allow to obtain an improved stability and to reduce the sliding efforts when the upper rails slide relative to the lower rails. Each upper rail is constrained to a respective lower rail and is free to slide relative thereto, balls (70) are arranged between said upper rail and said lower rail, and said upper and lower rails are shaped so as to define a lower and an upper ball guides (72, 74) on each side thereof. The design of said upper and lower rails at said lower and upper ball guides (72, 74) is such that efforts during relative sliding movements of the rails are reduced, while enhancing stability of the rails and preventing deformations thereof.

Vehicle seats generally have a sliding function for pushing or pulling the seat cushion in a forward or backward direction, a height adjustment function for adjusting the height of the seat cushion and a reclining function for adjusting the inclination of the seat backrest relative to the seat cushion.
The aforesaid sliding function is generally implemented by a sliding device which comprises a pair of parallel tracks, each of which comprises a lower rail attached to the vehicle floor and an upper rail attached to the vehicle seat, the upper rail being constrained to the lower rail, but being able to slide relative to said lower rail.
Each track of the sliding device further comprises a latch for allowing/preventing movement of the upper rail relative to the lower rail. Such latch is normally in a locking position, in which it prevents the upper rail from sliding with respect to the lower rail, thus avoiding accidental displacements of the seat with respect to the vehicle floor. The sliding device is further provided with a releasing member which can be used by a user for moving the latches of the tracks to an unlocking position, in which the upper rail is free to move relative to the lower rail, so that the position of the seat with respect to the vehicle floor can be adjusted. Such releasing member can be made, for instance, as a "U"-shaped handle having two substantially parallel arms, the end portions of which are configured to simultaneously act upon respective latches of the tracks of the sliding device for driving them to their unlocking position.
Such a sliding device is disclosed, for instance, in patent application EP 752 338.
In order to constrain the upper rail to the respective lower rail, sliding device are known in which the lower rail has as an upwardly oriented "U" shaped cross-section and the upper rail has a downwardly oriented "U" shaped cross-section and the upper and lower rails have respective flanges that cooperate for constraining the upper rail to the lower rail.
In order to allow and enhance a sliding movement of the upper rail relative to said lower rail, balls are provided between the upper and lower rails, which rails are shaped so as to define guides for said balls.
Patent applications US 2015/0291062, US 2018/0257515, US 2018/0222352, US 2007/0069099 and JP 2018-043717 all disclose sliding devices having the structure described above.
However, the sliding devices of disclosed in the aforesaid documents are not free from drawbacks.
More particularly, in said sliding devices the design of the lower and upper rails is not optimized, namely with respect to the stability of the rail coupling and the efforts during sliding movements of the upper rail relative to the lower rail.
Therefore, the main object of the present invention is to provide a sliding device with sliding tracks comprising lower and upper rails having an improved design, allowing to improve the stability of the sliding device and to reduce the sliding efforts.
A further object of the present invention is to provide a sliding device with a compact and cost-effective construction.
These and other objects are achieved by a sliding device as claimed in the appended claims.

Sliding device for a vehicle seat provided with an improved rail design


In this cooler grate according to the invention the supporting surfaces of the grate plates fixed on grate plate supports are provided with cooling gas openings which open upwards and are constructed in the form of substantially endless annular gaps, so that on the one hand a particularly effective cooling of the grate plates and on the other hand a particularly intensive cooling of the material transported over the cooler grate is achieved.

Grate coolers with a cooler grate are known in various forms. For example, DE-AS 20 11 518 discloses a cooler grate construction in which the parts of the individual grate plates through which cooling air streams have ribs which project vertically upwards and define box-shaped troughs, in the bases of which are conical bores which extend vertically for the passage of cooling air.
In another known construction (DE-OS 38 12 425) also the individual grate plates are constructed with troughs open towards the upper face of the supporting surfaces to receive material to be cooled, and here too the cooling gas holes open into the trough region. Moreover, at least some of the cooler grate plates can be constructed with hollow ribs running in the conveying direction for conducting the cooling gas, and the cooling gas holes can be provided in these longitudinally extending hollow ribs.
In the known constructions described above, particularly the constructions of the grate plates belonging to the grate cooler or the cooler grate, it proves difficult to meet some essential requirements all together on such grate plates. For example a favourable production possibility should be guaranteed but it should also be possible to ensure that at the same time an optimum gas distribution is achieved, as well as sufficient cooling of the sections of the supporting surfaces of the grate plate which come into contact with the hot material and also above all an intensive cooling of the material which is transported away over the cooler grate.
The object of the invention, therefore, is to create a cooler grate in which the requirements elucidated above (particularly in the region of the grate plates) can be met all together in a particularly favourable manner.


A new HOT WATER HEATER LEAK PROTECTION SYSTEM for PREVENTING OVERFLOW OF HOT WATER IN IF A HOT WATER HEATER BREAKS. The inventive device includes an overflow tank having a cylindrical stand positioned centrally thereon for positioning a hot water heater thereon. The overflow tank has a supplemental housing secured therein. The supplemental housing has an opening in a lower portion thereof to allow water to flow therethrough. An automatic float switch is positioned within the supplemental housing. A pump is disposed within the supplemental housing. The pump is in communication with the automatic float switch. A shut off valve is disposed within a housing coupled to a water line leading into the hot water heater. The shut off valve is in communication with the pump and the automatic float switch.

1. Field of the Invention
The present invention relates to OVERFLOW SYSTEMS and more particularly pertains to a new HOT WATER HEATER LEAK PROTECTION SYSTEM for PREVENTING OVERFLOW OF HOT WATER IF A HOT WATER HEATER BREAKS.
2. Description of the Prior Art
The use of OVERFLOW SYSTEMS is known in the prior art. More specifically, OVERFLOW SYSTEMS heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art OVERFLOW SYSTEMS include U. S. Pat. No. 5,334,973 to Furr; U.S. Pat. No. 5,029,605 to Dowling et al.; U.S. Pat. No. 4,805,662 to Moody; U.S. Pat. No. 4,987,409 to Jackson; U.S. Pat. No. 4,569,312 to Ridell et al.; and U.S. Pat. No. Des. 353,436 to Hess.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new HOT WATER HEATER LEAK PROTECTION SYSTEM. The inventive device includes an overflow tank having a cylindrical stand positioned centrally thereon for positioning a hot water heater thereon. The overflow tank has a supplemental housing secured therein. The supplemental housing has an opening in a lower portion thereof to allow water to flow therethrough. An automatic float switch is positioned within the supplemental housing. A pump is disposed within the supplemental housing. The pump is in communication with the automatic float switch. A shut off valve is disposed within a housing coupled to a water line leading into the hot water heater. The shut off valve is in communication with the pump and the automatic float switch.
In these respects, the HOT WATER HEATER LEAK PROTECTION SYSTEM according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for PREVENTING OVERFLOW OF HOT WATER IF A HOT WATER HEATER BREAKS.


A method and an apparatus for detecting a collision in a wireless multi-access channel are disclosed. The method of detecting the collision in the wireless multi-access according to an exemplary embodiment includes generating a request-to-send (RTS) message by a transmission terminal, transmitting the RTS message to a reception terminal, and receiving a response message from the reception terminal and determining whether a collision occurs based on a number of pieces of tone information included in the response message.

1. Field
The present invention relates to a method of detecting a transmission collision between terminals when at least two terminals access a wireless channel and transmit data simultaneously.
2. Description of Related Art
According to conventional art, when at least two terminals attempt transmission simultaneously and collide to fail to transmit data in a wireless channel, an acknowledgement (ACK) from a reception terminal does not arrive, which may be considered as a collision due to simultaneous connection to the channel. However, an ACK may also not be received even when the reception terminal fails to receive data due to a channel error. Current technology may not distinguish failure of transmission due to a collision from failure of transmission due to a channel error.

Method and apparatus for detecting collision in wireless multi-access channel

Electronics and Telecommunications Research Institute


A system for illuminating and reading information on a target (12) includes an illuminating device (14) for illuminating the target, separate from the illuminating device a user wearable reader device (11) for capturing an optical image of the target when illuminated by the illuminating device, detector means (30, 35) for detecting the location of the reader device and adjustment means (36, 22) for adjusting the illumination provided by the illumination device in response to a signal provided by the detector means so that a region (33) on the target illuminated by the illuminating means is readable by the reader device. A method of use of the system and an illumination unit for use in the system are also described.

Use of optically readable legends or labels such as bar codes on products to record and track the products is widely practised in industry and commerce. It is becoming common for bar code scanner devices which are used to read bar codes, such devices being herein referred to as 'imagers', to be worn on the hand of a user to provide a more ergonomically satisfactory and natural operation for the user. Also with the development of low power, short-range radio data transmission standards such as that known in the industry as Bluetooth™, it is not necessary to have a wired connection from the imager to the equipment processing and using the barcode or image data.
The use of CMOS imager chips in imagers is also becoming more popular because of their lower power consumption (as compared, for example to laser bar-code imagers), allowing a much smaller power source to be used. For example, the Motorola MCM20014 VGA resolution ImageMOS™ sensor can capture an image in 1/30th second whilst consuming 70 mA at 3.3V whereas a conventional laser scan engine imager will take 1/20th second and require 150 mA at 5V. An imager chip requires, however, an additional light source to illuminate the target area, e.g. the area on a product where a barcode is provided, if the ambient background light is not sufficient, whereas a laser scanner imager is its own light source. The additional light source is normally provided by a number of LEDs (Light Emitting Diodes or forward biased semiconductor p-n junction diodes) incorporated in a unit which also provides the reader function. The power consumption of the additional light source is considerable and causes the overall imager power consumption to be raised typically to 120 mA at 5V. This is nearly the same as that for the laser scanner imager.
In some proposed scanning and LED illuminating imager devices, an attempt has been made to increase the amount of ambient light on the target by employing light collection and guidance, for example as described in U.S. Pat. No. 6,042,012 but such optical collection systems add considerably to the size and weight of the imager and so are not suitable for use in wearable scanner applications.
Other proposed imagers use a targeting light spot or frame to ensure that the illuminating light source is aligned on the target before scanning so reducing the total illumination time and therefore the energy consumption, as for example described in U.S. Pat. No. 6,340,114. However, again the necessary optical system unfortunately adds considerably to the size of the imager.
In summary, prior art imagers also incorporating an illuminating device are bulky and relatively heavy and are not particularly suitable for hand carried operation.

System, method and equipment for reading information on a target


The valve controller is driven by a motor. The valve controller has a control circuit and a driving circuit. The driving circuit drives a motor based on a control signal generated by the control circuit and a rotational position signal generated by a rotational position sensor. The driving circuit generates a rotation number signal representing an actual rotation number of the motor according to the rotational position signal, and transfers the rotation number signal to the control circuit.

As shown in JP-U-4-105906A, the valve controller changes valve timing of an intake valve and/or an exhaust valve by rotational torque of an electric motor. Alternatively, the valve controller changes valve lift of an intake valve and/or an exhaust valve by rotational torque of an electric motor as shown in JP-11-324625A.
In such a valve controller, an electric current supplied from a driving circuit to the motor is controlled by a control circuit. A control signal is generated in the control circuit according to a rotation number signal detected by a rotation sensor which detects an actual rotation number of the motor. A rotational position signal of the motor is detected by a rotational position sensor. The operation of the motor is controlled based on the control signal and the rotational position signal.
The conventional valve controller driven by the electric motor needs the rotation number sensor and the rotational position sensor independently. Thus, the size of the valve controller becomes large and the production cost increases.


Methods, apparatus, systems, and articles of manufacture to simulate sensor data are disclosed. An example apparatus includes a noise characteristic identifier to extract a noise characteristic associated with a feature present in first sensor data obtained by a physical sensor. A feature identifier is to identify a feature present in second sensor data. The second sensor data is generated by an environment simulator simulating a virtual representation of the real sensor. A noise simulator is to synthesize noise-adjusted simulated sensor data based on the feature identified in the second sensor data and the noise characteristic associated with the feature present in the first sensor data.

In recent years, machine learning (e.g., using neural networks) has become increasingly used to train, among other things, autonomous devices (e.g., robots, self-driving cars, drones, etc.) to understand the environment(s) in which they operate and to take appropriate action.
The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.

Methods and apparatus to simulate sensor data