A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the quantum of charge stored to provide reconstruction of data. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the Automotive specifications even with some area penalty.

A number of Flash Memory products exist today. They can be divided into two categories, the high-density components, mainly used for mass storage, and the high speed products, used for operational data storage. The Non-volatile field can be hence sub-divided in terms of the technology as the NOR implementation which is mainly good for very fast random access with execute in place capability, and the NAND implementation which is typically accessed in a serial mode, for program and read of large chunks of data at a time, that is suitable for high-density storage. Today the NOR and NAND memories share the market, with the NOR being larger in volume. The NAND memories are denser and the market for it has been growing at a faster pace than any other types of memories. Related Memories include architectural variations on the NAND memory interconnections for program and access using existing cell structures. This disclosure is a storage element and cell structure that can be used under different architectures by the people conversant with NAND and NOR memories, but it will be described using the well known and standard NAND structure for simplicity and understanding.
The NAND implementation is characterized by its capability to store and move large chunks of data, which can be accessed using a serial interface. In a typical NAND cell, area per storage bit is smaller than that for the NOR cell, as the NAND consists of multiple storage elements connected in series in the form of a NAND string which is in series with a drain select gate and a source select gate between two contacts. Typical number of storage elements in the NAND string has increased to 32 or more elements per cell. These elements in a cell are isolated from the rest of the cells that are connected to a bit line and the common source connection by The two select devices one at the drain end (drain select), between the drain contact and its nearest (the first) storage element, and another at the source end (source select) between the source contact and its nearest (the last) storage element in the string The interlink between the select devices and the storage elements and between the storage elements in a string is by a connective diffusion (the connect diffusion).
The program and erase functions of a typical NAND structure is by FN Tunneling between the floating gate and the memory well using voltages of 18 to 22V. This requires that devices that can withstand High voltage be used, in the peripheral circutry. The use of these high voltage devices, impact the speeds and make the devices slow. They also are large devices to prevent punch through with larger spacing between devices to avoid breakdown and leakage, thereby making the chip larger and more costly to manufacture.
Prior Art
FIG. 1 shows a typical prior art NAND memory structure. B1 to B4 are memory elements connected in series in a NAND string. A1 is a drain select device and A2 is a source select device. The drain diffusion (2) with the drain contact is separated from the nearest (first) memory element B1 by the Drain select device A1. Similarly the source diffusion (2x) and source connection are separated from the nearest (last) memory element B4, by the Source select device A2. The connect diffusions (7) link the memory element to the Source select and Drain select devices and to each other to provide an integrated series conductive path from source to drain in the cell when the select devices and the memory elements are in the "on" condition. The typical NAND cell in FIG. 1 is formed in a P-well (1) and comprise of N-channel elements and devices. The memory element of the prior art NAND cell is typically a channel region (8) controlled by the storage element (Bn), where 'n' is the number of the storage element (1 to 4) in FIG. 1. The storage element comprise, a stack etched floating gate poly silicon (12) separated from the channel (8) by a thin tunnel oxide (10), a control gate (14) that also acts as a word line over laying the floating gate and coupling to it through an inter-poly dielectric or protection oxide (13), as is well known and used in the Non-volatile memory cells. The NAND string or series connected storage elements B1 to B4 in FIG. 1 are isolated from the word line drain contact diffusion (2) and source line diffusion (2x) by the drain select device A1, and the source select device A2. A1 isolates the first connect diffusion (7) from the drain (2) by having a select channel (4) controlled by poly-silicon select gate (6) over laying a gate oxide (5). Similarly A2 isolates the last connect diffusion (7) from the source (2x) by having a select channel (4x) controlled by poly-silicon select gate (6x) over laying a gate oxide (5x). An integrated and interconnected channel can be formed by the diffusions (7) the channel regions (8) under the storage elements (B1 to B4), the channel regions under the select devices (4 and 4x) connecting the drain diffusion (2) to source diffusion (2x) in each storage cell.
In a memory, the cells are arranged in columns, each column having a bit line that connects all the drains of the cells in a column together. The source is common and connected together typically by a diffusion running in a direction perpendicular to the bit line and parallel to the word direction. The columns are then arranged together to form an array as will be well known to those who are involved in the art of memory. Every row of elements in an array is interconnected, in a direction perpendicular to the bit line direction, that is, the in a row direction, by the control gate that form the word line. The drain select lines and the source select lines are also interconnected in the row direction in the array providing selection capability to a row of cells in the array. The formation of the array and its various interconnection methods are well known to practitioners in the industry. NAND arrays are erased as a block of cells, that is, a number of pages of elements in one or more rows of cells. In a typical NAND array each column of cells has one or more data registers attached to the bit line. The data is loaded in serial fashion into, and also read from, these data registers. The data is then transferred in parallel to the set of elements selected (a typical page of data at a time) during program. Similarly data from a set of elements selected for read are transferred in parallel into the registers for serial read out during read operation.
A typical memory array (referred at times as bulk) comprise of all blocks of memory where a typical block comprise a group of cells with elements distributed and connected along the rows by the word lines. Typically each word line interconnects elements in a row to form a page of memory. Blocks can be one or more cells in depth along the column though a typical block is a cell in depth. The bulk is the entire memory array comprising of all the cell blocks. It should be noted that there are different ways of interconnecting the elements and cells in an array. Those who are conversant with memories and their architectures will know the different interconnection modes within the array.
The typical write operation of a prior art NAND cell, comprise both the erase operation where by the electron charge is removed, are by Fouler-Nordheim Tunneling (FN Tunneling) in a block or bulk mode, and the program operation, where by electrons are stored in the floating gate. The first operation is typically the erase operation when the electron charge in the floating gates of the storage elements are removed. This is done by generating a voltage gradient of sufficient magnitude across the tunnel oxides (10) of the storage elements to remove electrons from the floating gate (12), by high voltage gradient of the right polarity applied between the control gate (14), that will be coupled down to the floating gate from the control gate, and the well (1) to appear across the floating gate oxide. The necessary field across the tunnel oxide to achieve erase can be induced in three ways: 1) by applying a high negative voltage (−Vpp) to the control gate with the well at '0'V, 2) by applying a lower negative voltage (approx. −½ Vpp) to the control gate and applying a positive voltage (approx. ½ Vpp) to the well, or 3) by applying a high positive voltage (Vpp) to the well while keeping the control gates at '0' potential. Of these the most common is to apply high voltage to the well with control gate at '0' potential for erase. This mode of erase is non selective and the memory cells are erased as a block (group of cells in a row or multiple rows in a specific well) or bulk (all cells on chip), based on the applied voltage on the control gate and the well.
Typically program is the selective operation and it is done on a page (all storage elements along a row or word line) level. The data which may be '1' or '0' is loaded into a set of registers serially and then presented to the cells through the bit lines, the lines connecting the drains of all the devices in a column of the array. Typically a self boost scheme is employed to write a '1', that is leave the selected storage element, on the selected word line in the erased state while a '0' allows programming of the selected storage element.
Assume that the data register is loaded with a '0' indicating that the element in the cell needs to get programmed. The '0' loaded in the register keeps the bit line connected to it and hence the drain diffusions (2) in the column of cells connected to the bit line at ground '0' potential. The gate (6) of the Drain select transistor (A1) of the selected row of cells is pulled to value approx. equal to Vdd, during write, turning on the drain select device. The source select transistor (A2) is kept in the off condition by keeping the gate (6x) of that device at ground or '0' potential. The unselected word lines in the selected cell are kept at an intermediate high voltage close to half the programming voltage (Vpp/2). This turns on the channel (8) of unselected storage elements by the application of the voltage (½ Vpp) to the control gates (14) of the storage elements connected to the unselected word lines. The coupled down voltage to the floating gates (12) of the unselected storage elements, is not sufficient to cause tunneling across the tunnel oxide (10) between the floating gate and the channel (8), even though the channel is at ground potential. The selected word line is pulled up to the full programming voltage (Vpp). This provides the high voltage (Vpp) to the control gate (14) of the selected storage element. This voltage applied is sufficient, as the channel (8) of the selected element is at ground or '0' potential, to produce a coupled down voltage on the floating gate (12) of the selected storage element, if the channel is at ground potential, to provide sufficient potential gradient across the tunnel oxide (10) between the floating gate (12) and the channel (8) of the selected storage element, to cause tunneling of carriers across the tunnel oxide (10) and accumulation of charge in the floating gate from the channel. Since the select gate (6) for drain select transistor is approx. at Vdd and the bit line connected to the drain (2) is at ground, and all the series storage elements in that selected cell are fully on, the ground voltage from the bit line appears in the channel under the selected element, and hence cause programming of the element. This programming process does not generate a current flow in the cell, other than that required to charge the capacitors and program the storage element, in fact it is a very low power programming process.
Now if the register connected to the bit line is loaded with a '1', that is a value close to Vdd, when the word lines in the selected cell is pulled up, the unselected word lines to approx. Vpp/2 and selected word line to Vpp, similar to the case explained earlier, the floating gates in the cell has a coupled up voltage which in turn tries to pull up the channel voltage by capacitive coupling. If the channel voltage is not actively pulled to ground as in the earlier case, but is allowed to rise to a value close to Vdd value, the drain select device of the selected cell, by virtue of having its gate (6), its drain diffusion (2) and its source diffusion, which is the first connect diffusion (7) all at a voltage close to Vdd, is shut off and the channel remains free to float to a value of voltage dictated by the capacitive coupling limited by the leakages. This causes the integrated channel {all the connect diffusions (7) and the channels beneath the storage devices (8)} to be pulled up to a value high enough by the coupled voltage to prevent the potential gradient across the tunnel oxide (10) of the selected storage element from reaching a value sufficient to generate a potential gradient across the tunnel oxide for tunneling to take place. This in turn result in the selected storage element being left erased. Thus the data stored in the selected storage element is directly related to the information stored in the register connected to the related bit line. In a NAND cell this program operation is done for storage elements connected to a single word line in a row of selected cells at a time and is called page program.
Read back of the data is accomplished by checking the status of the storage element using a sense circuit and hence getting the data back and it is well known in the industry. Multiple sense schemes are available for sensing and retrieving the data stored in the storage elements of the cell. Typically the read back is also done for an entire page at a time and data stored in page register and is serially streamed out from these registers.
It has been shown that the thickness of the tunnel oxide is of the order of 70A and cannot be scaled without impacting the reliability and disturb characteristics of the elements. In order to cause tunneling typical potential gradient of 10 MeV/cm is necessary, that is a voltage of over 7 V applied across the tunnel oxide is essential to initiate tunneling with the 70A oxide. The prior art NAND cells use the stack etch technology to self align the control gate and the floating gate. This provides a three-sided coverage of the floating gate by the control gate. The coupling between the control gate and the floating gate of the storage element is typically of the order of 45-50%. This means that only about half the voltage applied to the control gate is coupled down to the floating gate to appear across the tunnel oxide. This in turn mandates relatively high voltage Vpp use during program and erase operations. In order to improve this coupling ONO, an Oxide-Nitride-Oxide sandwich inter-poly dielectric, with a Nitride inter-layer that has a higher dielectric constant than oxide, has been used in the prior art. This ONO process adds to the mask count and process complexity and hence the cost of the memory. In return it reduces the high voltage requirement of the cell marginally by increasing the coupling to around 60%. The ONO introduces problems of retention as the Nitride itself conducts charge through hopping conduction that is well known in the industry. The use of the two oxide layers on top and bottom of the Nitride of sufficient thickness is to prevent this leakage, which in turn increase the thickness of the inter-poly dielectric and hence reduce the coupling and the ability to scale. It should be noted that if the coupling ratio of the NAND Storage element, that is the ratio of the coupling between the control gate and floating gate as against the total coupling to the floating gate from all sides is low, only that amount of the applied voltage to the control gate appear on the floating gate. This also means that voltage gradient due to Vpp (1-the coupling ratio) appear across the inter-poly dielectric, causing stress to that dielectric increasing the leakage through the dielectric ONO layer.
The Nitride layers are also prone to accumulation of charge by trapping in the layer. At high voltages used in the program and erase process of the prior art cell, the Inter-layer dielectric is subject to high potential gradients. These are usually sufficient to cause charge transport through the layer and hence trapping. This trapped charge will cause accelerated window closing during write cycling and reduce the reliability of the cell in operation.
The leakage characteristics and the charge trapping characteristics of the ONO are made worse under high temperature and high voltage conditions and impact the high temperature characteristics of the storage element, typically making it less suitable for high temperature operation in industrial and automotive applications.
Another problem that has been identified in the prior art cells as the technology shrinks is the problem of coupling of the floating gate to adjacent memory elements through the open sides of the floating gates. This can result in voltage swings in the cell that are not designed in and controlled.
All these results in problems of cell disturb and problems of data retention in the memory cells.
Another problem is the encroachment of the connect diffusion under the tunnel oxide. This has the effect of reducing the reliability of the cell by making a high doped region with its field regions to be under the tunnel oxide and the floating gate thereby changing the uniformity of tunneling from the channel. This can reduce the program-erase or write cycling characteristics of the memory elements by localized degradation. This also has an impact on the high temperature characteristics of the cells and retention characteristics of the cell due to generation-recombination in the depletion region resulting in collection of charge by the floating gate.
Some of the problems of the typical present day NAND flash cell are:    1. Very high Voltage program and erase operation.    2. Low coupling resulting in increased stress on the inter-poly dielectric.    3. Lack of ability to scale vertically the inter-poly dielectric.    4. Lack of ability to scale without being affected by coupling to neighboring cells.    5. Need for sophisticated program erase controls to prevent over programming and over erase.    6. Full processor controlled reliability screening and redundancy due the cells being prone to disturb conditions.    7. Frequent checks and error correction methods are needed to ensure that the cells retain the data.    8. Reduced high temperature capability (typical commodity operation).    9. Reduced data retention.    10. Reduced program erase cycling.    11. Difficult to scale devices with technology node without impacting performance due to punch trough.    12. Process complexity increases with ONO.
What is Proposed
What is proposed is a cell and technology to be used in a NAND memory array. Three separate modifications/improvements are proposed, that improve the operation, the operating temperature range and increase the reliability, both retention and endurance, of the cell. The first modification (modification 1) is one that uses a five side overlapping control gate, to improve coupling ratio with associated reduction in the program and erase voltages, and elimination of unwanted disturb conditions due influence of the neighboring cell through coupling to the floating gate. The high coupling ratio reduces the stress on the inter-poly dielectric and hence improves retention and endurance characteristics. The second modification (modification 2) is by using the five side overlapping control gate structure to space away the diffusion edge from the floating gate and providing a pair of side select gates in parallel with the floating gate, on either side of the floating gate, to eliminate the variations in the field due to high doping in the channel and hence improve the uniformity of tunneling from the channel through the tunnel oxide. This improvement moves the high field depletion regions where electron hole pair generation takes place, especially with increased temperature, away from the floating gate, there by improving the operating temperature range of the devices. This improvement also improves the endurance and data retention characteristics of the cell by improving the uniformity of current flow through the tunnel oxide and hence reducing the damage to the oxide. The use of the five side coverage of the floating gate with the improvement in coupling ratio provide a third improvement, (modification 3) that is the ability to use high quality grown or deposited oxide or a combination of the two oxides as inter-poly dielectric instead of ONO. The increased coupling ratio also allows reduction in the inter-poly oxide thickness as the voltage appearing across it is reduced. FIG. 2 is a first implementation of some of the proposed embodiment with the modification 1 that provides the five side coverage of the floating gate by the control gate, and FIG. 3 is the preferred implementation with modifications 1 and 2. Modification 3 can be implemented in both implementations shown in FIG. 2 and FIG. 3, as both have high coupling ratios due to the coverage and low inter-poly voltage drop. Use of Oxide as the inter-poly dielectric brings with it some additional advantages. First is the simplification of the manufacturing process due to the elimination of steps needed for ONO processing. Second is the improvement of retention characteristics of the cells due to elimination of charge leakage by hopping conduction through the Nitride. Third is the improvement in write cycling reliability, by the reduction of window closing effect due to charge trapping in the Nitride of the ONO.
The cell architected is not for high-density and is not the smallest NAND cell, instead it has been architected for improved manufacturability, quality and reliability. The disturb conditions have been eliminated by cell and array design and retention and endurance (write cycling) characteristics are improved. This cell will also be much more manufaturable and yieldable as ONO issues are eliminated and lower voltages are used to program and erase. The use of the side select gates of the embodiment in FIG. 3 enable the cells to be in depletion or enhancement during operation.
Some of the advantages of the proposed cell are:    1. A lower program erase voltage is used as compared to the existing NAND structures at the same node due to the improved coupling ratio from 50 to 80%.    2. Eliminates the need for ONO and allows the use of Oxide as inter-poly dielectric, making the element easier to manufacture and more robust.    3. The cell with side select gates is immune to over erase problems.    4. Eliminates the unwanted coupling from adjacent cells to the floating gate.    5. The lower Program-erase voltage reduces the stress on the inter poly oxides and hence increases the reliability of the cell.    6. Provides cells that are capable of high temperature operation by moving the junction depletions, where thermal generation and acceleration take place, away from under the floating gate.    7. Very high retention is achieved due to low and uniform tunnel currents by elimination of junction depletion overlap of floating gate.

Highly reliable NAND flash memory using five side enclosed floating gate storage elements


The frame plating process of the invention comprises the dry film resist pattern formation step at which a part of the dry film resist is located in such a way as to cap the upper position of the given pattern of opening concavity corresponding to the site needing film thickness precision. It is thus possible to obtain a fairly good film thickness distribution at the specific site needing film thickness precision in a simple manner yet without depending on the film thickness distribution of the plated film based on plating conditions.

1. Field of the Invention
The present invention relates generally to a frame plating process, and more particularly to a frame plating process that enables a fairly good film thickness distribution to be obtained at a specific site needing film thickness precision in a simple way yet without depending on the film thickness distribution of a plated film based on plating conditions.
2. Explanation of the Prior Art
One technique of forming a micropatterned thin film (micropattern), for instance, includes a frame plating process. According to that process, for instance, an electrode film is formed on a substrate, and a resist is formed by coating on the electrode film. Then, that resist layer is patterned by photolithography so that a frame for forming a plated film is formed by the remnants of the patterned resist (mask pattern). Thereafter, that frame is used for electroplating using the previously formed electrode layer as a seed so that a patterned thin film comprising an electroconductive material is formed.
Micropattern thin films formed by the frame plating process are used for, for instance, microparts, microlayer components, interconnecting patterns or the like that constitute, for instance, a microdevice. Exemplary micro-devices are thin-film inductors, thin-film magnetic heads, semiconductor devices, sensors using thin films, and actuators using thin films.
When a given shape of frame plated film is formed for the purpose of fabricating such microdevices, there is often a demand for only a specific area of the formed frame plated film to have an increased film thickness precision (that means that there must be a decreased fluctuation of the thickness distribution of the plated film). One possible approach to increasing the plated film thickness precision at such a specific site is to polish or otherwise smoothen that site alone; however, the operation of partial polishing or the like taking aim at a microarea alone involves much difficulty, and is impractically poor in efficiency as well.
The present invention has been made with such situations in mind, and has for the object the provision of a frame plating process that enables a good film thickness distribution to be obtained at a specific site needing film thickness precision in a simple way yet without depending on the thickness distribution of a plated film based on plating conditions.


A software application that provides images of multiple items associated by a common seller on an on-line commerce network comprising query software for automatically retrieving from a list all items associated by a common seller from a server, retrieving the location of an image of each item and retrieving the image of each item after a user has identified an item being sold by the seller from a list, display software for automatically displaying the retrieved images as thumbnail images with an image map layer containing each location on the server of a file associated with each thumbnail image. The invention also comprises a method of doing the same.

This invention relates to the capture and display of files on a network. More specifically the invention relates to the display and management of items on sale at an online commerce site.
As Internet access has increased so to has the importance of e-commerce strategies for businesses. In 2000, 41.5% of U.S. households (44 million households) had Internet access. Global internet usage is at 34% with 15% of these users making an on-line purchase. 32% of all Internet users in the U.S. have made an on-line purchase. Of the items being purchased, the most popular include books, CDs, PC hardware and software, office supplies as well as apparel and accessories.
Much of the success of an online commerce site depends on how users interact online with the company. It is imperative that the online experience of a user be convenient and efficient to close on sales and maintain customer loyalty. The current experiences created by these sites have limitations. In particular, person-to-person commerce sites such as popular auction sites lack certain functions that would add convenience and efficiency to their transaction systems.
Internet auction sites such as Ebay, Yahoo, and other online commerce sites, have several things in common. The sellers are all registered and assigned a user identification. All items registered for sale are assigned unique identifiers. Among the user supplied detail information regarding an item for sale, a picture can be included. The sites have functions that allow visitors of the site to view items for sale grouped by predetermined criteria. The criteria could include viewing all items for sale by a particular seller but most often is viewing items for sale that match a phrase in the description of the item (such as show me all antique gold jewelry). A list is produced that includes multiple sellers of antique gold jewelry. The lists are usually sorted. The items might be shown chronologically in the order they were registered for sale with the newest registered showing first. They might be shown with the items registered for sale most recently. They might be shown with the least expensive items listed first or the most expensive items listed first. Typically once an item is no longer available for sale it is not shown in the list.
A site visitor can choose to learn more about a particular item in a list by clicking on a single entry displayed on the view. That action brings the site visitor to a detail view of that item containing detail information such as a description, a picture of the item, the current bid or cost of the item.
An individual seller's items have limited visibility in this typical demonstration since, unless the site visitor chooses to view all the items of the seller, there are typically thousands of competing items in a list. The seller's items are only most visible for the short time they are at the top of the list.


A special connector for use with a drapery headrail incorporates an attachment clamp for flexible tubular lighting devices at one end of the connector. At the opposite end the connector incorporated a protuberance or some other structure for removably interacting with the headrail (i.e., the protuberance snaps into a channel or groove on the head rail). The connector may also incorporate a clamp to grasp a valance and thus act as an improved valance clip which is removably attachable to the drapery headrail and to the valance and also incorporates a device to hold a length of flexible tube accent lighting. The clips may be readily rearranged on the head rail to prevent drooping of the flexible tube or to create complex patterns with the tube. The flexible tube may be readily removed for replacement of defective elements. Clips can be available in different configurations so that the accent lighting is most prominent on the valance, most prominent on the drapery or is even aimed upwards towards the ceiling. Modified head rails may incorporate a channel that acts as a clamp to hold the tubular accent lighting.

1. Field of the Invention
The present invention concerns the field of shades and drapery and more particularly to a device for simplifying the application of illumination to valances.
2. Description of Related Art
The idea of adding a source of illumination to shades and drapery is probably as old as electric illumination which possible the addition of light without the danger of fire. The valance surrounding and concealing a drapery rod and mechanism seemed the ideal vehicle for also hiding electric lights. The early attempts to illuminate drapery tended to treat the drapery as just another light fixture. That is, the valence was used to hide relatively large electric lamps which were intended to illuminate both the drapery and pictures or the immediate portion of the room. For example, see U.S. Pat. Nos. 2,528,132 to Gibson et al. and 2,564,865 to Turner et. al. Also typical of this approach is U.S. Pat. No. 2,569,518 to Deutsch et al. which discloses a valance-like enclosure for fluorescent tubes and U.S. Pat. No. 2,662,163 to Mollner which discloses a combination curtain rod and tubular fluorescent lamp fixture. In the same vein is U.S. Pat. No. 2,708,711 to McGinty et al. which discloses fluorescent tubes and incandescent flood lamps concealed behind a drapery valance.
More recently interior designers have become aware of the usefulness of "accent lighting" in which a plurality of relatively dim electric lights create a pattern of interesting shadows or appear like twinkling stars. Accent lighting is not intended to produce significant room illumination for reading, etc. although it may serve as a safety role as well as a decorative role by making structures visible to prevent collisions in a darkened room, etc. The present inventor has been involved in providing ornamental designs for such accent lighting. For example, see U.S. Pat. D-365,955 which shows a possible ornamental effect of lighting on a valance.
One currently popular method of creating such accent lighting is to employ a plurality of tiny, low-voltage incandescent lamps, often in some type of flexible transparent tube. For example, see U.S. Pat. Nos. 3,755,663 to George, Jr. and 4,812,956 to Chen which disclose, respectively, a flexible transparent tube containing a double parallel string of lamps, and a flexible tube with lamp strings enclosed in an exterior groove. Another flexible tube device, disclosed in U.S. Pat. No. 4,665,470 to George, Jr., incorporates a transparent gel to surround and cushion the tiny lamps.
Closely related lighting devices are flexible tapes taught, for example, in U.S. Pat. No. 4,471,412 to Mori which discloses a flexible tape device containing a plurality of illumination elements and U.S. Pat. No. 4,761,720 to Solow which includes LEDs (light emitting diodes) in a tape; these tapes may be applied to a wide range of objects by merely peeling off a protective backing. Significant drawbacks to this type of installation are that the adhesive generally fails in time (resulting in drooping or total detachment of the illuminated tape) and that the tapes are almost impossible to remove cleanly for repositioning or replacement of failed lamps.
Flexible tube devices 10 may be readily attached to surfaces with U-shaped clamps 12 as shown in FIG. 1. The U-shaped clamps 12 are available with peel and stick adhesive or may be attached with screws or nails (not shown). Although these clamps 12 and similar devices allow ready installation in a wide variety of locations, they generally suffer from adhesive failure with time, and an inability to readily reposition the clamps 12. Further applying screws or nails to the relatively tiny clamps 12 may be extremely tedious.
Despite the apparent ease of using various flexible light tubes or tapes to apply accent lighting, a number of more specialized fixtures have recently been developed. Most probably there is a desire to make the installation more permanent and less messy since tapes can readily become detached and flexible tubes may sag and appear somewhat sloppy. Although low voltage lamps last a very long time, they eventually fail and must be replaced, and may of the tube and tape designs make this replacement very difficult or impossible. U.S. Pat. No. 4,158,221 to Agabekov shows a rigid elongated fixture to accommodate elongated tubular incandescent lamps. This fixture is fairly complex but allows ready replacement of single lamps when they fail. U.S. Pat. No. 5,260,859 to Lettenmayer discloses another elongate fixture for use with similar, low voltage tubular incandescent lamps. While U.S. Pat. No. 5,404,279 to Wood discloses a fixture in which individual screw-based lamps can be readily replaced. While these and similar fixtures may provide a way for applying neat and replaceable accent lighting to draperies, they are expensive and not readily adaptable to a wide range of decors.


A front mask of a display device having luminous parts (LED) and peripheral parts (a connector and the like) are integrated by resin-molding with the parts being electrically connected in advance by a film insulated wire. Each part is arranged at a predetermined position prior to resin-molding. Then, electrical connection is make between these parts by the film insulated wire. Finally, resin is injected to manufacture an integrated body.

1. Field of the Invention
The present invention relates to a front mask of a display device in which display parts of an image display device such as LED displaying an image, and the peripheral parts are integrated by resin-molding, as well as to a manufacturing method thereof.
2. Description of Related Art
Japanese Utility Model Application Laid-Open No. 62-49192(1987) discloses a front mask of a display device in which display parts and peripheral parts are integrated by resin-molding. FIG. 1 shows a perspective view of the conventional front mask which has been disclosed as mentioned above. FIG. 2 shows a partially cutaway view of FIG. 1 as seen along the direction II. FIG. 3 shows a sectional view as seen along the line III--III of FIG. 2. A front mask 30 has an LED 22, which functions as luminous parts, and peripheral parts of the luminous parts, including a resistor 23 and a connector 24 to be connected to an external device, are integrated by resin-molding. A terminal 25 of the LED 22 and a terminal 26 of the resistor 23 project beyond the surface 27 of a mask main body 21. An electrical connection is made between the terminal 25 and the terminal 26, between the terminal 25 and the connector 24, and between the terminal 26 and the connector 24, by a conductor pattern 28 which is formed on the surface 27 by printing.
The manufacturing process of the front mask 30 which has such structural features as mentioned above is described below. First, a mold for forming is prepared. The LED 22, the resistor 23, and the connector 24 are installed at the mounting portion, which has been formed at a predetermined position of the mold. Then, liquid resin is injected through an injection opening of the mold. After the resin is hardened, the mold is demolished, and the mask main body 21 which is integrated with each part is taken out. Then, the conductor pattern 28 is formed by printing at the predetermined position on the surface of the mask main body 21 between the terminal 25 and the terminal 26, between the terminal 25 and the connector 24, and between the terminal 26 and the connector 24.
Since a conventional front mask 30 of a display device is constructed as mentioned above, the LED 22, the resistor 23, and the connector 24 are integrated with the mask main body 21. This makes it possible to manufacture such a device with a high level of accuracy in size. There, however, exist problems. For example since the connection between these parts is made by the printed conductor pattern 28, the printing process is complicated. Further since each part should be arranged by considering the level of printing performance of the conductor pattern 28, there is a considerable limitation in the degree of freedom in the arrangement of each part and design.

Front mask of display device and manufacturing method thereof


A software-based computer security enhancing process and graphical software-authenticity method, and a method to apply aspects of the two are disclosed. The process provides protection against certain attacks on executable software by persons or other software used on the computer. Software using this process is protected against eavesdropping (the monitoring of software, applications, the operating system, disks, keyboard, or other devices to record (steal) identification, authentication or sensitive data such as passwords, User-ID's, credit-card numbers and expiry dates, bank account and PIN numbers, smart-card data, biometric information (for example: the data comprising a retina or fingerprint scan), or encryption keys), local and remote tampering (altering software to remove, disable, or compromise security features of the altered software) examination (viewing the executable program, usually with the intent of devising security attacks upon it), tracing (observing the operating of an executable program step-by-step), and spoofing (substituting counterfeit software to emulate the interface of authentic software in order to subvert security) by rogues (eg: Trojan Horses, Hackers, Viruses, Terminate-and-stay-resident programs, co-resident software, multi-threaded operating system processes, Worms, Spoof programs, key-press password capturers, macro recorders, sniffers, and other software or subversions). Aspects include executable encryption, obfuscation, anti-tracing, anti-tamper & self-verification, runtime self-monitoring, and audiovisual authentication (math, encryption, and graphics based method permitting users to immediately recognise the authenticity and integrity of software). FIG. 5 in the specification depicts the many components and their interaction.

The present invention relates to a computer program having enhanced security features, and also to a system and method for enhancing the security features of a computer program. In particular, the present invention relates to such a program, and the system and method for creating the program, having increased security features to prevent ID data (as defined) eavesdropping and/or theft and/or ensure authenticity.

Computer software authentication, protection, and security system


A package arrangement is provided. The package arrangement in general includes a blister pack having a backing construction secured thereto. In preferred arrangements, a removable header is provided. The backing construction preferably includes a flexible film having resealable pressure sensitive adhesive on a side thereof, by which the backing portion is secured to the blister pack. A portion of the backing construction is formed as a hinged cover portion, by two cuts, preferably parallel, extending through the backing construction portion and overlapping a selected section of the blister pack. In a preferred arrangement, each cut terminates at a stop structure.

For film or sheet products, such as breath films or other oral care strips, the product packaging preferably serves numerous purposes including:                1. securely containing and protecting the product during shipping and handling;        2. displaying the product at the point of purchase;        3. containing and protecting unused product during repeated opening and closing, i.e., as individual films are dispensed and used;        4. convenient fit in a pocket or purse; and        5. tamper evidence indication.
One example of current oral care strip product available on the market is the "Cool Mint Listerine PocketPaks" product available from Warner-Lambert Consumer Health Care, Morris Plains, N.J. The product packaging for this product involves a cardboard or paperboard slipcover (about 3 and ⅝ inches by about 3 inches) having enclosed therein and removable there from, another cardboard or paperboard piece (about 3 and ⅜ inches by about 2 and 15/16 inches) having a blister pack attached thereto. After the second piece is removed from the slipcover, it is torn open by removal of a panel (about 1 and 5/16 inches by about 1 and ⅞ inches) in the cardboard or paperboard packing. Underneath the removable panel, a barrier film or metallized sheet is encountered which, once tom open or removed, allows access to inside of the blister pack. Contained within the blister pack is a plastic dispenser (about 1 and ⅛ inches by about 1 and ⅞ inches) which can be removed. The remainder of the package is discarded. The dispenser has a hinged panel selectively opened (and reclosed) with a tab, that allows access to internally received oral care strips.
In general, improvement in such packaging is desirable.

Dispenser package arrangement; and, methods


A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue that correspond to a particular support processor. A main processor decodes an interrupt and determines which support processor generated the interrupt. The main processor then determines whether a kernel or an application should process the interrupt. Interrupts such as page faults, segment faults, and alignment errors are handled by the kernel, while “informational” signals, such as stop and signal requests, halt requests, mailbox requests, and DMC tag complete requests are handled by the application. In addition, multiple identical events are maintained, and event data may be included in the interrupt using the invention described herein.

1. Technical Field
The present invention relates in general to a system and method for message delivery across a plurality of processors. More particularly, the present invention relates to a system and method for using ring queues to manage interrupt requests that are received from the plurality of processors.
2. Description of the Related Art
Computer systems are becoming more and more complex. The computer industry typically doubles the performance of a computer system every 18 months (e.g. personal computer, PDA, gaming console). In order for the computer industry to accomplish this task, the semiconductor industry produces integrated circuits that double in performance every 18 months. A computer system uses integrated circuits for particular functions based upon the integrated circuits' architecture. Two fundamental architectures are 1) microprocessor-based and 2) digital signal processor-based.
An integrated circuit with a microprocessor-based architecture is typically used to handle control operations whereas an integrated circuit with a digital signal processor-based architecture is typically designed to handle signal-processing manipulations (i.e. mathematical operations). As technology evolves, the computer industry and the semiconductor industry realize the importance of using both architectures, or processor types, in a computer system design.
The computer industry is moving towards a multi-processor architecture which includes a main processor to execute a main operating system, and one or more support processors to support application tasks. The main processor typically executes a main operating system, and invokes application programs. In turn, the application programs use the support processors for offloading particular tasks. A challenge found in multi-processor architectures, however, is managing interrupts that are received from the support processors. The amount of interrupts that occur in a computer system increases linearly as the number of processors increase. For example, if a computer system includes one main processor and eight support processors, the amount of interrupts that the processors generate may be eight times more than a computer system that includes only one processor.
Another challenge found with multi-processor interrupt management is the ability to track interrupt sequence. For example, an application may use four support processors for task execution, and each of the support processors send interrupts to the main processor. In this example, if the main processor does not manage the order in which the interrupts were received, the application may process the interrupts out of order and, in turn, generate erroneous results.
In addition, a challenge found with existing art is that if a main processor receives multiple identical event interrupts, the main processor typically combines the multiple identical event interrupts into one interrupt. This causes problems if, for example, four support processors each send an identical interrupt, and each of the identical interrupts is combined into a single interrupt.
Furthermore, a challenge found with existing art is that interrupts that are received from support processors include little or no data. This approach may force an application to spend time retrieving data from memory in order to process the corresponding interrupt.
What is needed, therefore, is a system and method to effectively manage interrupt requests in a multi-processor environment while minimizing interrupt processing load.

System and method for message delivery across a plurality of processors

International Business Machines Corporation


A hot forging press machine includes a fixed lower die, a vertically movable upper die, a punching blade for punching, and a deburring blade. The deburring blade includes a deburring upper blade and a deburring lower blade to perform deburring. The deburring upper blade is fixed to a lower portion of the upper die, and the lower blade is fixed to an upper portion of the lower die. A lower sweeping plate urged upward by a spring is slidably fitted to an outer circumference of the lower blade to perform deburring, and an upper sweeping plate of the upper die presses an entirety of an upper surface of a flange portion of a pressed product to perform the discharging.

1. Field of the Invention
The invention relates to a hot forging press machine.
2. Discussion of the Background
Conventionally, as a hot forging press machine used in punching and deburring, one such as described in JP 11-270580 A (FIG. 2(6), Paragraph No. 0019) has been known. It is described that when such a hot forging press machine is used, it is preferable to form flange's outer circumference, a rectangular hole, and a spline hole by punching simultaneously. According to the description, it is considered possible to eliminate relative misalignment in position among the flange's outer circumference, a rectangular hole, and a spline hole and form them by punching in one process.


A liquid crystalline compound having a remarkably high .DELTA.n and good miscibility with other liquid crystalline compounds, and expressed by the general formula (1) ##STR1## wherein R.sub.1 represents, for example, a halogen atom, cyano group, or an alkyl or alkenyl group of 1 to 15 carbon atoms in which alkyl or alkenyl group hydrogen atom may be replaced, for example, by fluorine atom, and one or not-adjacent two or more methylene groups may be replaced by oxygen atom, --CH.dbd.CH-- or --C.tbd.C--; R.sub.2 represents an alkyl group of 1 to 10 carbon atoms or hydrogen atom; rings A.sub.1, A.sub.2, A.sub.3, and A.sub.4 independently represent, for example, 1,4-cyclohexylene or 1,4-phenylene in which hydrogen atom may be replaced by a halogen atom or cyano group; Z.sub.1, Z.sub.2, and Z.sub.3 independently represent, for example, a covalent bond or --CH.sub.2 CH.sub.2 --; s and t are 0 or 1; u is an integer of 1 to 5; and each of the elements in the general formula may be its isotope. A liquid crystal composition and a liquid crystal display device using the compound are also disclosed.

Liquid crystal display devices utilize optical (refractive) anisotropy and dielectric anisotropy of liquid crystal materials. Liquid crystal display devices have widely been used for the display of watches, word processors, computer terminals, and televisions. Liquid crystal materials mean principally liquid crystal compounds exhibiting a liquid crystal phase. These materials have been used in a form of a composition in which various kind of compounds are usually mixed. At that time when the composition is produced, compounds which do not exhibit by themselves a liquid crystal phase, but can exhibit a liquid crystal property when mixed with a liquid crystal compound or liquid crystal composition and thus clearly have a latent liquid crystallinity are also useful. For purpose of the present invention, the term "liquid crystalline compounds" include the latter compounds having a latent liquid crystallinity in addition to the liquid crystal compounds.
While various properties are required of liquid crystal compositions, optical anisotropy (.DELTA.n) is one of especially important properties. Since when the product (.DELTA.n.multidot.d) of the .DELTA.n and cell thickness (d) is a specific value (first minimum or second minimum), display qualities (contrast and viewing angle) of liquid crystal display devices become optimum, cells now being practically used have been designed according to the optimum value. However, in order to satisfy other required performances up to maximum, several different values are sometimes selected for d under the conditions described above. For instance, increase of response speed is strongly required lately, and there is a trend toward a small d with an improvement in cell preparation technology for a background to satisfy the requirement. Accordingly, exploitation of liquid crystal compositions having a high optical anisotropy, namely, exploitation of liquid crystalline compounds which can achieve a high optical anisotropy have been demanded.
Heretofore, compounds expressed by any one of the formulas (10) to (12) are disclosed, as liquid crystal compounds having a comparatively high .DELTA.n, in Laid-open Japanese Patent Publication No. Sho 61-5031, Mol. Cryst. Liq. Cryst., 48, 175 (1978), or Laid-open Japanese Patent Publication No. Hei 2-180,840. ##STR2##
However, compounds expressed by the formula (10) do not exhibit a sufficiently high .DELTA.n. Whereas compounds expressed by the formula (12) exhibit a comparatively high .DELTA.n, the compounds are considerably poor in miscibility with other liquid crystalline compounds. Whereas compounds expressed by the formula (11) exhibit a comparatively high .DELTA.n and good miscibility, the compounds are considerably poor in chemical stability and have such a problem that they are naturally decomposed even when allowed to stand at room temperature.

Liquid crystalline compound having alkynyl group, and liquid crystal compositions and liquid crystal display device therefrom


Disclosed is a method and system for performing periodic replication using a write-ordered log. According to one embodiment, a plurality of write operations to a primary data volume are tracked using a write operation log and then data associated with the plurality of write operations is replicated to a secondary data volume by coalescing the plurality of write operations utilizing the write operation log and transferring data associated with the plurality of write operations to the secondary data volume. According to another embodiment the described tracking includes storing metadata associated with the plurality of write operations within the write operation log. In another embodiment, the described coalescing includes identifying a non-overlapping portion of a first write operation and a second write operation of the plurality of write operations utilizing the metadata.

1. Technical Field
The present invention relates to data storage and retrieval generally and more particularly to a method and system for performing periodic replication using a log.
2. Description of the Related Art
Data replication products replicate data associated with application write operations or "updates" over a network to remote sites, making the replicated data available for processing (e.g., backup, disaster recovery, decision support, data mining, etc.). Conventional data replication products offer different modes of replication each offering different guarantees on the content and availability (recovery point and recovery time) of the data at the remote site. Such replication modes typically fall into one of three categories, synchronous, asynchronous and periodic.
When replicating synchronously, a replication product maintains secondary site data completely up to date with respect to primary site data. An application write operation on a synchronously replicated data volume completes as soon as the update is logged at the primary site, and, transmitted to and acknowledged by all secondary sites. In this mode of replication, a remote site is always up-to-date or "current" and consistent. Synchronous replication has the overhead of including a network round trip time to each write operation service time and hence tends to decrease application performance.
In asynchronous replication, the transfer of a write to a secondary site occurs outside of the main input/output (I/O) path. A log is used to record each write and the write operation request is indicated as complete to the requesting application once the write has been logged. The logged writes are then sent "asynchronously" to each remote site while maintaining write-order fidelity and consequently consistency. Synchronization between primary and remote secondary data volumes is not consistently maintained in an asynchronously replicated system however and consequently secondary data volumes cannot be relied on to be "up-to-date" at any given instant.
Utilizing conventional periodic replication, changes or "updates" to a primary data volume stemming from application write operations are tracked using a change map. Each remote site is then incrementally synchronized using the tracked changes at periodic or scheduled intervals. In a typical periodic replication system, such change maps are implemented as bitmaps where each bit represents a region in the data volume or "set" to be replicated. Consistency is maintained by atomically synchronizing secondary data volumes with all changes which took place during a given tracking period or interval. Accordingly, each remote site in a periodically replicated system is "current" up to the last synchronization event that occurred.
A significant drawback associated with both synchronous and asynchronous modes of replication is that data may be inefficiently or unnecessarily transmitted over an associated network if the same blocks of the primary data volume are written to multiple times (e.g., with identical data due to the operation of an application or with different data where the final write operation is the only one of importance). While periodic replication avoids this disadvantage by transferring cumulative data changes occurring over a period of time, because each write operation can "dirty" a large data volume region data, periodic replication may also result in the unnecessary transmission of unchanged data when there is little spatial locality of writes.

Method and system for performing periodic replication using a log


A method, system, and program for publishing hold queue characteristics are provided. Characteristics of an on hold system are monitored. Then, responsive to a selection by a caller of a format and interface for publishing the characteristics, the characteristics are transferred to the selected interface in the selected format.

1. Technical Field
The present invention relates in general to telecommunications and, in particular, to call hold queues. Still more particularly, the present invention relates to publishing call queue information to a caller in a caller specified format.
2. Description of the Related Art
Many companies provide telephone-based access to help staff, sales personnel, representatives, and automated menus. Where high telephone call traffic is typical in telephone access to a company's representatives, a PBX system receives the call and distributes the call to an automatic call distributor (ACD). ACDs are often employed to provide an even and systematic distribution of incoming calls to multiple representatives. In particular, ACDs typically provide incoming calls with a direct connection to an available representative until all representatives are busy. Then, calling parties are placed in a call queue, and selectively connected to a representative once a representative comes available.
Call queues may cause frustration and ill will of consumers towards a company, particularly where excessively long waits, full queues and accidental disconnects are encountered. One way to alleviate some of the frustration associated with call queues is by alerting callers to a current position within the call queue and an estimated hold time.
For example, a call queue system may inform callers waiting in a call hold queue of the expected waiting time through a voice announcement prior to connection to an attendant. While periodically informing callers via voice announcement of a queue position informs callers of progress within the call queue, callers only receive limited information as to an expected wait time.
Therefore, in view of the foregoing, it would be advantageous to provide a method, system, and program for publishing call queue information to each caller that will aid each caller in understanding the relative position of each caller within a call queue. Further, it would be advantageous to provide a method, system, and program for publishing call queue information in a format most practical and accessible to the caller.


The present disclosure is directed to a mechanism for optimized application performance in SD-WAN, and includes the steps of receiving initial traffic packets at a first site for transmission to a second site; determining whether a direct tunnel is established between the first site and the second site based on a state of the second site, the state comprising an active state indicating that a direct tunnel is established between the first and second sites or an inactive state indicating that the direct tunnel is not established between the first and second sites; and in response to determining that the direct tunnel is not established, determining that the initial packets satisfy a configured trigger; forwarding the initial packets to the second site via a backup path; establishing the direct tunnel between the first and second sites; and forwarding subsequent traffic packets to the second site via the established direct tunnel.

Many SD-WAN implementations support a full-mesh topology, wherein each site is directly connected to every other site in the network. An edge router at each site may establish transport links, such as Internet Protocol Security (IPsec) tunnels, to other remote sites and bidirectional forwarding detection (BFD) probes may be used to monitor the path characteristics of the transport links. In a full-mesh network having numerous sites, low-end edge routers having reduced memory and/or processing capabilities may not be able to sustain connections with every other remote site.

Scalable mechanism for optimized application performance in SD-WAN


A storage device is disclosed. The storage device includes a storage controller. The storage controller includes a direct memory access (DMA) Descriptor Manager (DM) to generate DMA descriptors by monitoring user data and a data integrity field (DIF) transferred between a host memory and a local memory based upon a function being performed.

Serial attached storage protocols, such as serial ATA (SATA) and serial Small Computer System Interface (SCSI) (SAS) are becoming more prevalent for connecting storage devices to a computer system. In computer systems implementing such serial storage devices, one storage device in the system may communicate with others. For example, a device requesting data (referred to as the initiator device) may receive data from a target device.
A storage device typically includes a direct memory access (DMA) engine to perform data transfer operations to assist in transferring input/output (I/O) data from (to) a host memory and to (from) a local memory. The DMA engine usually includes a Data Integrity Engine that performs desired data integrity checks (e.g., Cyclic Redundancy Checking (CRC), Application Tag check and/or Reference Tag check etc.). The Data Integrity Engine operates on data blocks which may or may not have data integrity field (DIF). A data block with no DIF typically includes a 512 B (or 520 B, 2 KB, 4 KB etc.). User Data Field and a data block with DIF is a data block appended with an 8 B Data Integrity Field (DIF), also referred to as Block Guard (BG).
When BG is enabled and either an Insert or Strip function is selected, the number of bytes transferred on the local interface of the DMA will not equal the number of bytes transferred on the host interface. Consequently, a programmer of the DMA engine accounts for the expansion or compression of the data stream across descriptors when the Insert or Strip functions are selected. Typically, the programming of the DMA engine (e.g., generating the descriptors by keeping track of the exact amount of user data versus the data integrity data that is being transferred across from the source to the destination) is done in firmware. Programming the DMA engine via firmware is a burden on the local processor, which results in less optimal overall performance. Also, the processor cannot keep up with the ever-increasing link rates, thus affecting the overall system I/O performance.


The invention relates to touch panels for use in a variety of electronic apparatuses, and designed to prevent separation of a lower substrate and an antireflection layer, and to ensure reliable operation. An undercoat layer (9) made of any of silicon oxide and a compound having a principal ingredient of silicon oxide is disposed between the antireflection layer (5) and the lower substrate (2) made of glass having the same principal ingredient of silicon oxide, to improve strength of adhesion between the lower substrate (2) and the antireflection layer (5), thereby preventing separation of the antireflection layer (5) from the lower substrate (5), and providing the touch panel with reliable operation.

There has been significant progress in recent years in performance and diversification of various electronic apparatuses such as mobile phones and portable terminals. These apparatuses use optically transparent touch panels in a manner that they are mounted to front faces of display devices such as liquid crystal displays. When making selection of any of functions of an electronic apparatus, a user operates the touch panel by pressing it with a finger, a pen or the like while visually checking a screen of the display device disposed to the backside of this see-through touch panel. There is therefore a demand for electronic apparatuses having easy-to-see screens of display devices behind touch panels, in addition to good operability.
The accompanying figures show touch panels illustrated in a scale enlarged only in the dimension of thickness to make their structures readily understandable.
FIG. 3 is a sectional view of a touch panel of the prior art. Touch panel 10 comprises a film-like transparent upper substrate 1, and transparent lower substrate 2 made of a pane of glass or the like material. Upper substrate 1 has transparent upper conductive layer 3 of indium-tin oxide or the like material formed on main surface 1a, and lower substrate 2 has lower conductive layer 4 formed on its main surface 2a through antireflection layer 5.
Antireflection layer 5 is thus disposed between lower conductive layer 4 and lower substrate 2. Antireflection layer 5 comprises low-refraction layer 5A made of silicon oxide, magnesium fluoride or the like material having a smaller refractive index than that of lower conductive layer 4, and high-refraction layer 5B made of niobium oxide, titanium oxide or the like material having nearly same refractive index as lower conductive layer 4.
Lower conductive layer 4 has a plurality of dot spacers (not shown in the figure) formed of an insulation resin at regular intervals on one of the main surfaces facing spacer 6. Upper conductive layer 3 is provided with a pair of upper electrodes (not shown) formed at two side ends thereof, and lower conductive layer 4 is also provided with a pair of lower electrodes (not shown) at two side ends thereof in a direction orthogonal to the upper electrodes.
Spacer 6 has a frame-like shape, and it bonds between upper substrate 1 and lower substrate 2 along their peripheries with adhesive layers (not shown) formed on both of its upper and lower surfaces. In touch panel 10 of this kind, upper conductive layer 3 and lower conductive layer 4 are arranged in a manner to face each other with a predetermined space.
Touch panel 10 constructed as above is placed on a front face of a liquid crystal display or the like device and mounted to an electronic apparatus of any kind. The pairs of not-illustrated upper and lower electrodes are then connected to an electronic circuit (not shown) employed in the electronic apparatus of such kind.
In this touch panel 10, when a user presses main surface 1b of upper substrate 1 with a finger, a pen or the like while visually checking a screen of the liquid crystal display or the like device behind the touch panel, upper substrate 1 bends in a manner that upper conductive layer 3 at the pressed portion comes into contact with lower conductive layer 4.
A voltage is then impressed from the not-illustrated electronic circuit to the upper electrodes and the lower electrodes in a consecutive manner, so that the electronic circuit detects the portion being pressed according to a voltage ratio between these electrodes, and switches a variety of functions provided in the electronic apparatus.
When touch panel 10 is used in a bright environment, especially outdoors or under fluorescent lamps, the external light such as sunlight and lamplight passing through upper substrate 1 and upper conductive layer 3 is reflected in lower conductive layer 4 provided on main surface 2a of lower substrate 2, and this gives rise to a problem of making the screen in the liquid crystal display device difficult to see since it is located behind the touch panel. Antireflection layer 5 is therefore placed between lower conductive layer 4 and lower substrate 2 for the purpose of preventing reflection of the external light.
In other words, touch panel 10 of the prior art comprises low-refraction layer 5A of a comparatively small refractive index and high-refraction layer 5B of a comparatively large refractive index, both of which are laminated on main surface 4b of lower conductive layer 4 of generally the same refractive index as high-refraction layer 5B. Because of this structure, the external light hitting upon main surface 4a of lower conductive layer 4 is allowed to pass easily through the interior of lower conductive layer 4, low-refraction layer 5A, and high-refraction layer 5B. Since this results in a reduction of the external light reflected in main surface 4a of lower conductive layer 4 by the amount allowed to pass therethrough, the structure here provides the user with an easy-to-see screen of the liquid crystal display device behind touch panel 10 by virtue of this reduction of the reflected external light.
One example of the prior art techniques relevant to the present invention is illustrated in International Publication, No. 02/029830.
In the conventional touch panel 10 described above, however, high-refraction layer 5B and low-refraction layer 5A are laminated to form antireflection layer 5 on main surface 2a of lower substrate 2 made of glass or the like material. High-refraction layer 5B formed of niobium oxide, titanium oxide or the like has weak adhesion to lower substrate 2 of the glass, which leaves a problem that antireflection layer 5 is liable to separate from lower substrate 2 if touch panel 10 is warped due to an excessive force applied to it during manufacturing, transporting or mounting to an electronic apparatus.
The present invention is contrived to overcome the above problem of the prior art technique, and to provide a touch panel having a simple structure and easy to operate while preventing separation of the antireflection layer from the lower substrate.


A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Traditional central processing units "CPUs" process instructions based on "clocked time." Specifically, CPUs operate such that information is transmitted at regular time intervals. Based on complementary metal-oxide-semiconductor "CMOS" technology, silicon-based chips may be manufactured with more than 5 billion transistors per die with features as small as 10 nm. Advances in CMOS technology have been parlayed into advances in parallel computing, which is used ubiquitously in cell phones and personal computers containing multiple processors.
However, as machine learning is becoming commonplace for numerous applications including bioinformatics, computer vision, video games, marketing, medical diagnostics, online search engines, etc., traditional CPUs are often not able to supply a sufficient amount of processing capability while keeping power consumption low. In particular, machine learning is a subsection of computer science directed to software having the ability to learn from and make predictions on data. Furthermore, one branch of machine learning includes deep learning, which is directed at utilizing deep (multilayer) neural networks.
Currently, research is being done to develop direct hardware implementations of deep neural networks, which may include systems that attempt to simulate "silicon" neurons (e.g., "neuromorphic computing"). Neuromorphic chips (e.g., silicon computing chips designed for neuromorphic computing) operate by processing instructions in parallel (e.g., in contrast to traditional sequential computers) using bursts of electric current transmitted at non-uniform intervals. As a result, neuromorphic chips require far less power to process information, specifically, artificial intelligence (AI) algorithms. To accomplish this, neuromorphic chips may contain as much as five times as many transistors as a traditional processor while consuming up to 2000 times less power. Thus, the development of neuromorphic chips is directed to provide a chip with vast processing capabilities that consumes far less power than conventional processors. Further, neuromorphic chips are designed to support dynamic learning in the context of complex and unstructured data.
When utilizing an analog array, values stored thereon may be susceptible to leakage or drifting, which may cause errors in the output voltage. Specifically, current leakage may be introduced to the circuitry of the analog array which may cause a voltage drift at the output. Provided herein are systems and methods for detecting current leakage or voltage drift and in response, reprogramming the analog array.

This patent is subject to a terminal disclaimer.


Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Programmable logic devices ("PLDs") are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array ("FPGA"), conventionally includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks ("IOBs"), configurable logic blocks ("CLBs"), dedicated random access memory blocks ("BRAMs"), multipliers, digital signal processing blocks ("DSPs"), processors, clock managers, delay lock loops ("DLLs"), and so forth. As used herein, "include" and "including" mean including without limitation.
Each programmable tile conventionally includes both programmable interconnect and programmable logic. The programmable interconnect conventionally includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points ("PIPs"). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic conventionally may be programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external non-volatile memory, such as flash memory or read-only memory) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more "function blocks" connected together and to input/output ("I/O") resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays ("PLAs") and Programmable Array Logic ("PAL") devices. In CPLDs, configuration data is conventionally stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration ("programming") sequence.
For all of these programmable logic devices ("PLDs"), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms "PLD" and "programmable logic device" include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Conventionally, embedded processors are designed apart from the PLDs. Such embedded processors are generally not specifically designed for implementation in PLDs, and thus such embedded processors may have operating frequencies that significantly exceed a maximum operating frequency of programmable logic of such PLDs. Moreover, parameters such as latency, transistor gate delay, data throughput, and the like designed into the embedded processors may be assumed to be present in the environment to which the embedded processors are to be coupled. Thus even though a PLD may include an embedded processor, such one or more operating parameters of the embedded processor may be substantially disparate from those of programmable logic of the PLD.
For purposes of clarity by way of example and not limitation, an FPGA with an embedded processor is described; however, it should be appreciated that other PLDs, as well as other integrated circuits with programmable logic or other circuitry fabric with less performance than the embedded processor, may likewise be used in accordance with the following description.
Performance of a design instantiated in programmable logic of an FPGA ("FPGA fabric") coupled to an embedded processor may be significantly limited by disparity between operating parameters of the FPGA fabric and those of the embedded processor. Thus, if, as before, embedded processor interfaces such as processor local bus ("PLB") interfaces are brought directly out to FPGA fabric, disparity between respective operating parameters of the embedded processor and the FPGA fabric is a significant limitation with respect to overall performance. For example, operations between a memory controller instantiated in FPGA fabric and an embedded processor have heretofore been significantly bottlenecked due to having to wait on the slower memory controller.
Alternatively, to enhance performance, a memory controller instantiated in FPGA fabric may be hardened or provided as an ASIC core coupled to the embedded processor. By hardening a circuit instantiated in FPGA fabric, it is generally meant replacing or bypassing configuration memory cells with hardwired or dedicated connections. Even though the example of a memory controller is used, it should be understood that other peripherals may be hardened or provided as ASIC cores for coupling to an embedded processor. However, as the memory controller or peripheral ASIC or hardened core is not configurable, this reduces overall flexibility. For purposes of clarity by way of example and not limitation, ASIC cores are described even though hardened cores instantiated in FPGA fabric may also be used.
Semiconductor processes and semiconductor process integration rules ("semiconductor process design rules") associated with ASICs are generally more challenging, and thus yield for such ASICs may be relatively low as compared to yield of FPGAs of the same size. FPGAs, which may have a larger and longer run rate than ASICs, may employ semiconductor process design rules that are less aggressive but are more conducive to a higher die per wafer yield than that of ASICs.
It should be understood that an FPGA manufactured with an ASIC core uses FPGA semiconductor process design rules. Thus, ASIC cores manufactured in FPGAs perform worse than such ASIC cores manufactured as standalone ASICs using more aggressive ASIC semiconductor process design rules. Thus, manufacturing FPGAs with ASIC cores conventionally will not achieve competitive performance with standalone ASICs.
For FPGAs provided with ASIC cores that take the place of some FPGA fabric resources, users conventionally are locked into the particular offering of ASIC core memory controllers or peripherals, and have less flexibility of design due to fewer FPGA fabric resources for implementing their circuit design. This loss of flexibility combined with the fact that such ASIC core memory controllers or peripherals implemented in FPGA fabric may make FPGAs less attractive to users.
Accordingly, it would be desirable and useful to enhance performance of FPGAs without a significant loss of design flexibility associated with adding ASIC cores, such as memory controllers or peripherals.

Translation of commands in an interconnection of an embedded processor block core in an integrated circuit


A gas containing malodorous/harmful components is treated with an iodine- and/or inorganic iodide-supporting activated carbon honeycomb 6 disposed in a gas passageway 5 extending from a gas inlet 3 to a gas outlet 4. The gas may be treated with this iodine-and/or inorganic iodide-supporting activated honeycomb 6 and an acid-supporting activated carbon honeycomb 7. A fan 8 may be provided in a downstream position within the gas passageway. The operation of the fan may be associated with a sensor for detecting malodorous/harmful components and/or a timer which controls the operating duration of a motor. The above activated carbon honeycomb will eliminate various malodorous/harmful substances, such as ammonia and sulfur-containing compounds, with high efficiency and low flow resistance. The activated carbon honeycomb can be used for the treatment of a variety of gases and is particularly useful for the deodorization of toilets.

For the elimination of malodorous and harmful gaseous components, methods and apparatuses are known which comprise passing a gas containing malodorous and other components through a bed of granular or fibrous activated carbon. Such malodorous or harmful gases may contain sulfur-containing compounds such as hydrogen sulfide, mercaptans, sulfides, and nitrogen-containing compounds such as ammonia, amines, and aldehydes, carboxylic acids, hydrocarbons and carbon monoxide. These malodorous and harmful gaseous components are usually present in very low concentrations in the atmosphere but with the above-mentioned activated carbon alone, it is difficult to adsorb and remove all of these malodorous and harmful components. The rate and amount of elimination are also very meager. Therefore, a large quantity of activated carbon is required for the adsorption/removal of malodorous and harmful components. Furthermore, since the activated carbon bed presents a large flow resistance, it cannot smoothly remove the malodorous and harmful components, with the result that a fan is essentially required but this results in an increased electric utility cost. Replacement of deactivated carbon with a fresh one is also complicated.
For the adsorption/elimination of malodorous components which cannot be easily removed with activated carbon, the use of a chemical-supporting activated carbon honeycomb is proposed in Japanese Patent laid open No. 262742/1987. This honeycomb, when it is supporting an acid chemical such as sulfuric acid on activated carbon, is capable of removing ammonia, while it is able to remove hydrogen sulfide and the like when an alkaline chemical is supported.
However, even with this chemical-supporting activated carbon honeycomb, the malodorous and harmful components which can be adsorbed and removed are limited by the type of chemical supported. Therefore, it is difficult to adsorb and remove a variety of malodorous and harmful components with sufficient efficiency. Moreover, when an alkaline chemical is supported for elimination of sulfur-containing compounds such as hydrogen sulfide, the ignition point of the honeycomb is depressed. It is dangerous to use such an alkali-supporting activated carbon honeycomb in an ordinary inhabited area. In addition, since the activated carbon honeycomb is carbonaceous, it becomes readily inflammable, thus causing trouble in use. On the other hand, the addition of a flame retardant leads to a decrease in the amount of adsorption per unit specific surface area and, hence, a decrease in deodorizing efficiency. In these honeycombs, it is necessary to support a large amount of chemicals on the activated carbon honeycomb in order that an enough adsorption effect is achieved.
Japanese Patent Publication No. 9377/1987 discloses a deodorizer comprising an oxide and/or oxo acid of iodine supported on activated carbon. However, since this deodorizer is granular, the flow resistance in deodorization is too large for smooth treatment of gases. It is not easy to handle it, for example, changing a deactivated one for a fresh one.

Activated carbon honeycombs and applications thereof


An arm cord handle is disclosed that includes a flexible loop handle having a U shaped distal end and having proximal ends joined together at a common base portion. An external strap lies around and against the U shaped distal end in a storage position. The external strap has its ends fastened to the loop handle at a location spaced from the common base portion. The external strap can be deployed to an operational position away from the U shaped distal end of the flexible loop handle so that the arm cord handle is converted into a foot loop handle with the external strap positioned around a user's ankle while the U shaped distal end is positioned around the user's forefoot during exercise.

1. Field of the Disclosure
This disclosure generally relates to resistance based exercise equipment and more particularly to an arm cord handle for attaching a user's foot to an arm cord connected to a spring biased resistance exercise apparatus such as a reformer exercise apparatus utilized to perform various Pilates exercises.
2. Description of Related Art
Today, many types of exercise devices are available and used for fitness and/or medical reasons to burn off undesired calories, to improve cardiovascular ability, to tone or strengthen muscles, or to improve flexibility, balance, posture, etc. No matter what the desired end goal of a user of exercise equipment may be, almost all types of exercise equipment aid the user to achieve his or her desired goal by exerting some form of adequate and effective resistance against repeated bodily movements of the user.
A reformer is one such exercise device originally developed by Joseph Pilates. A reformer is basically a rectangular frame that sits on a floor and constitutes or carries a pair of stationary parallel rails or tracks. A movable carriage for supporting a user's body is mounted on the rails for movement toward and away from one end, the foot end, of the frame. The carriage is typically elastically biased toward the foot end of the frame by one or more coil springs having one end attached to the carriage and the other to a hook or post on an anchor bar near the foot end of the frame.
A pair of arm cords or ropes 8 that can be grasped by a user are attached at one end to the carriage. Each cord runs through a pulley generally located at the head end of the reformer. The free end of each arm cord typically has a handle or loop removably fastened thereto for the user to grasp with his or her hand. This handle is typically a single closed loop of fabric or leather, or alternatively may be a nested set of two loops, one larger one for large hands and an inner loop for those users with small hands.
Such loops are easily grasped in a user's hand. A user may also perform exercises wherein the user's foot engages the loop. However, during such use a user's foot can slip out of the loop because the user cannot easily grasp the loop itself.
To address this issue, Y-loop handles were developed that can be swapped for the regular hand loops or hard handles. These Y-loop handles are designed to fit a user's foot with one leg of the Y-loop around the user's instep or forefoot and the other leg of the Y-loop behind the user's heel, i.e., around the user's ankle, so as to maintain a more secure connection between the arm cord and the user's foot. A conventional Y-loop handle 10 is shown positioned properly on a user's leg 12 in FIG. 1 and a pair of Y-loop handles 10 is shown separately in FIG. 2.
A disadvantage with the Y-loop handles 10 is that they are separate handles and must be swapped out for the normally used single or double hand loops in order to be used. Furthermore, when the Y-loop handles 10 grasped by a user's hand, the extra loop is jutting out to the side and presents at least a distraction to the user. What is needed is a loop handle design that can also be used as a Y-loop for the user's foot when needed but remains out of the way when used as a regular loop handle. The present disclosure addresses this need.


An optical disk recording thereon compressed moving picture data and an optical disk reproduction apparatus each capable of easily effecting trick play such as high speed reproduction and a retrieval operation at a high speed. Additional information necessary for trick play is recorded in an arbitrary area of an optical disk such as a TOC (Table of Contents) or a leading sector (sector 0) of the disk, and a sector address is added to each sector. To conduct trick play, an I picture, a P picture and a B picture contained in a GOP layer inside a bit stream of compressed image data are extracted and reproduced in accordance with a reproduction speed by looking up a trick play table.

This invention relates to an optical disk recording thereon compressed data of an image, and to an optical disk reproduction apparatus for reproducing the image data from the optical disk.
A so-called "CD-ROM" is a typical example of those systems which reproduce digital data by using an optical disk. The CD-ROM records data for a computer on an optical disk having the same physical format as CDs for audio use, and has the data format to be next described. A data string recorded on the optical disk comprises the smallest unit referred to as a "frame", and each frame contains digital data such as sync data, subcode, main information and an error correction code.
Further, the CD-ROM employs the sector structure in which 98 frames (2,352 bytes) are gathered into 1 sector, and each sector comprises a 12-byte sync data, a 4-byte header data representing an address and a mode, a 2,048-byte digital data and a 288-byte error detection/correction code.
On the other hand, a system comprising the combination of an inter-frame prediction with orthogonal transform, quantitization and variable-length encoding is well known as an encoding system of moving picture, and an MPEG system of the ISO (International Organization of Standardization) is also based on this system. In the case of MPEG2, for example, the bit stream of the encoded image data is divided into six hierarchical layers, i.e. a sequence layer, a GOP (Group of Pictures) layer, a picture layer, a slice layer, a macro-block layer and a block layer. Among them, the GOP layer contains three kinds of data, that is, an I picture encoded from the information alone without using inter-frame prediction, a P picture generated by executing prediction from the I picture or P picture and a B picture generated by bidirectional prediction. The sequence layer comprises a GOP containing image data starting from the I picture and obtained by gathering the I picture, the P picture and B picture into one group, and an SH (Sequence Header) added to the leading part of the GOP.
When moving pictures are converted to compressed image data by high efficiency encoding, there is known a system which encodes the signal by reducing a compression ratio for scenes having vigorous motion, or in other words, at a high transfer rate, and by increasing the compression ratio for scenes having small motion, or in other words, at a low transfer rate. The variable transfer rate compressed image data so encoded can reduce image deterioration due to compression in comparison with compressed image data of a fixed transfer rate obtained by fixing the compression ratio at a mean value.
An apparatus for recording the compressed image data having the variable transfer rate or the fixed transfer rate into the optical disk such as the CD-ROM and reproducing the data has been announced already.

Optical disk and optical disk reproduction apparatus


A recharging system for a battery operated tool such as a lawn mower. A slidable cover is used which is movable between an open position and a closed position. The slidable cover alternately exposes a receptacle adapted to receive a removable fuse key and an electrical connector adapted to receive an electrical power cord. The receptacle and the electrical connector are longitudinally aligned with the cover so that for the cover to move to the open position and expose the electrical connector, the fuse key must be removed. The receptacle is electrically connected in series with an activation switch, the battery and the electric motor to form a motor circuit. When the fuse key is removed to expose the electrical connector, the motor circuit is broken which prevents the electric motor from being activated whether or not the activation switch is engaged. When the cover is moved to the closed position exposing the receptacle, the fuse key may be inserted into the receptacle, completing the motor circuit enabling the activation switch to activate the electric motor.

Recently, on-board chargers for battery operated tools have become desirable. When rechargeable batteries of battery operated tools are being recharged, it is essential that the motor be disengaged or inoperable. The system to be utilized with such on-board charges should prevent the motor from being engaged while the battery is being recharged regardless of the position of the activation switch. For the system to operate effectively, it must be user friendly. If the system for engaging and disengaging the motor circuit is difficult to operate, then operators are likely to attempt to devise a method to by-pass the system, defeating the benefits thereof.
In battery operated tools not having on-board rechargers, preventing activation of the motor when the tool is being recharged has been accomplished by various methods. An example of one approach is in U.S. Pat. No. 3,696,593 to Froud et al., which discloses a receptacle and two plugs which have obstructing members such that the plug corresponding to normal operation of the motor must be removed and a recharging plug must be inserted thereby preventing activation of the motor.
A related approach is disclosed in U.S. Pat. No. 3,581,480 to O'Connor et al., which contains two plugs, one for normal operation of the motor and one for recharging the battery such that to recharge the battery it is first necessary to unplug the first plug thereby preventing activation of the motor.
A more recent approach appears in U.S. Pat. No. 5,085,043 to Hess et al., which discloses an electro-mechanical interlock and module system for lawn mowers or other electrical devices. A mechanical key is adapted to be inserted into a specially configured opening in a top of a motor shroud. The key activates a plunger of a normally open interlock switch, thereby closing the switch and enabling the lawn mower power circuit. An integral tab simultaneously blocks the charging ports so the operator cannot connect a male plug from an outlet--mounted charging transformer while the power circuit is enabled. When the key is removed, the interlock switch returns to an "off" position and the power circuit of the lawn mower is disabled. When the key member is removed, the charging port is exposed permitting connection of the charger circuit to the charging transformer.
The present invention is directed to improving known recharging systems for a battery operated tool having an on-board transformer.

Recharging system for a battery operated tool having an on-board transformer