In a vehicle frame structure, an upper edge of a frame member is fixed to a lower face of a substantially flat panel, and a bottom wall of an upper stiffener fixed to an inner face of an upper part of a curved portion of the frame member and a bottom wall of a lower stiffener fixed to an outer face of a lower part of a region between two inflection points of the curved portion are arranged in an X shape relative to a top point of the curved portion. Therefore, when a compressive load in the longitudinal direction acts on the frame member, the curved portion of the frame member is effectively prevented from bending by counterbalancing the upward load acting on the lower stiffener bottom wall with the downward load acting on the upper stiffener bottom wall. Moreover, the upper stiffener and the lower stiffener are U-shaped cross-section members that can be formed by bent sheet metal, and thereby minimize any increase in weight due to installation of the stiffeners.

1. Field of the Invention
The present invention relates to a vehicle frame structure in which an upper edge of a frame member having an upwardly opening U-shaped cross-section is fixed to a lower face of a substantially flat panel so as to form a closed cross-section, and the frame member has a curved portion formed in a longitudinally middle section thereof, the curved portion having an upwardly curving bottom wall.
2. Description of the Related Art
If a longitudinal load due to a collision of an automobile is applied to a front side member having a closed cross-section that is bent in a crank shape when viewed from the side, there is a problem that a bending moment is generated in the bent portion (kick-up portion), thus causing a large degree of bending deformation. Japanese Patent Application Laid-open No. 2003-231483 discloses an arrangement in which the kick-up portion of the front side member is reinforced by a reinforcing member only on the compressive deformation side, thereby improving the rigidity of the kick-up portion while minimizing the increase in weight.
Also, a portion of an automobile rear frame mounting a rear wheel suspension system is curved upward into an arch shape in order to avoid interference with a suspension spring or a hydraulic damper, leading to another problem that a floor panel covering an upper face of the rear frame should also be curved upward, thus hindering effective utilization of the capacity within a vehicle compartment. If the upper face of the rear frame is made flat in order to make the floor panel flat, not only is the rigidity greatly degraded by an arch-shaped curved portion formed on a lower face of the rear frame, but also the curved portion is bent upward by the longitudinal load imposed on the rear frame when the automobile is involved in a collision, whereby it becomes difficult to exert an impact absorbing effect by making a front or rear portion of the rear frame effectively buckle.
In order to solve these problems, the arch-shaped curved portion formed in the rear frame is reinforced by a reinforcing member, thus making it difficult for the curved portion to be bent by the longitudinal load. However, unless the shape and arrangement of the reinforcing member are carefully determined, only the weight is increased without increase of the strength against the bending load.


Provided is a nanocomposite binder for an electrode mix of a secondary battery, comprising carbon nanotubes in a photo- and/or thermo-polymerizable material or polymer, or a mixture thereof; and a lithium secondary battery comprising the same.

Technological development and increased demand for mobile equipment have led to a rapid increase in the demand for secondary batteries as an energy source. Among these secondary batteries, lithium secondary batteries having high energy density and voltage are commercially available and widely used. The lithium secondary batteries generally use a lithium transition metal oxide as a cathode active material and a graphite-based material as an anode active material.
However, the anode formed of the graphite-based material has a maximum theoretical capacity of only 372 mAh/g (844 mAh/cc), thus suffering from a limited increase of capacity thereof. Consequently, such a graphite-based anode is incapable of carrying out a sufficient role as an energy source for next-generation mobile equipment undergoing rapid development and advancement. Further, lithium metals, studied for use as the anode material, have a very high energy density and thus may realize a high capacity, but raise problems associated with safety concerns due to growth of dendrites and a shortened cycle life as the battery is repeatedly charged/discharged. In addition, carbon nanotubes (CNTs) have been used as an anode active material, but have suffered from problems such as low productivity, high costs and low initial efficiency of less than 50%.
In recent years, a number of studies and suggestions have been proposed as to silicon, tin or alloys thereof, as they are known to be capable of performing reversible absorption (intercalation) and desorption (deintercalation) of large amounts of lithium ions through the reaction with lithium. For example, silicon (Si) has a maximum theoretical capacity of about 4020 mAh/g (9800 mAh/cc, a specific gravity of 2.23) which is substantially greater than the graphite-based materials, and thereby is promising as a high-capacity anode material.
However, upon performing charge/discharge processes, silicon, tin or alloys thereof react with lithium, thus undergoing significant changes of volume, i.e., ranging from 200 to 300%, and thus repeated charge/discharge may result in separation of the anode active material from the current collector, or significant physicochemical changes at the contact interfaces between the anode active materials, which are accompanied by increased resistance. Therefore, as charge/discharge cycles are repeated, the battery capacity sharply drops, thus suffering from a shortened cycle life thereof. For these reasons, when a conventional binder for a graphite-based anode active material, without any special treatment or processing, is directly applied to a silicon- or tin-based anode active material, it is impossible to achieve desired effects. In addition, when an excessive amount of a polymer as the binder is used to decrease volume changes occurring upon charge/discharge cycles, the electrical resistance of the anode is increased by an electrical insulating polymer used as the binder, which consequently results in problems associated with a reduced battery capacity and a decreased charge/discharge speed.
In order to cope with such problems, there is an urgent need for the development of a binder having low electrical resistance while exhibiting adhesive strength and mechanical properties sufficient to withstand large volume changes of anode active materials occurring during a charge/discharge process in lithium secondary batteries using silicon- or tin-based anode active materials. In addition, conventional graphite-based lithium batteries also require high-speed charge capability via further enhanced conductivity of the binder.
On the other hand, as an attempt to use conventional carbon nanotubes as an anode mix (a mixture of an active material, a conductive material, a binder and the like) of a lithium secondary battery, Japanese Patent Laid-open Publication Nos. 2004-319186 and 2005-004974 disclose incorporation of the carbon nanotubes as the conductive material into the anode mix, thereby improving the conductivity of the anode. However, to the best of our knowledge, no case has been known to the art in which the carbon nanotubes were used as the binder of the anode mix. Furthermore, the carbon nanotubes are highly expensive materials, and therefore incorporation thereof in a content required as the conductive material into an electrode mix leads to the fundamental problem associated with significantly increased production costs of the batteries.

Composite binder containing carbon nanotube and lithium secondary battery employing the same

Abstract: The carbon nanotube-containing composite binder according to the present invention and a lithium secondary battery comprising the same employs a novel nanocomposite, prepared by combination of carbon nanotubes with a conventional binder material, as a binder of an anode. As a result, the present invention provides advantages such as improved conductivity of the anode due to decreased electrical resistance of the binder, and enhanced mechanical properties of the binder and thereby being capable of preventing the separation of an anode active material layer from a current collector due to volume changes occurring upon charge/discharge cycles.


A universal anonymous data collection and exchange service is provided where individuals and entities initially register with the service utilizing “legally authentic” identity documentation to obtain a “universal ID” (UXID). The UXID consists of a sting of alphanumeric digits selected from a hash function that is performed on a string of personally identifying information. Once registered, the individual and entity UXIDs are used as a means by the service to engage in a pre-defined confidential data collection and exchange protocol between participating, registered UXID holders. The service is designed for use across many applications, individuals and entities, and may support one-time or recurring collection of data.

There is a widespread need for universal identifiers—database "keys"—to facilitate the collection, merger and exchange of data across broad-based populations and time scales. Within the United States, the Social Security Number (SSN) has become the de facto standard identifier that is used to associate data with a selected individual. However, since the SSN is so readily tied to the individual, use of the SSN as a database key poses the risk of privacy abuses, including but not limited to identity theft. Since the use of a universal identifier (such as the SSN) is often outside the knowledge or control of the person to whom the identifier is assigned, the potential for continued and ongoing misuse is significant.
Because individual privacy and confidentiality rights cannot be safeguarded with current approaches, governmental efforts to assign unique universal personal identifiers have met with significant legal opposition in the United States. For example, the National Center for Education Statistics (NCES) has proposed the introduction of "unit-level" data collection to allow for the aggregation of a variety of personally-identifiable data about students over the course of their education. Collection of comprehensive educational data is essential for informed decision and policy making, but attempts to implement mandatory national data collection via personally identifiable IDs have met with significant legal challenges, in additional to financial and logistical ones.
Many types of national, state and other initiatives have been under scrutiny and subject to cancellation because they are unable to collect and analyze the data needed to determine program efficacy and cost-effectiveness.
In general, universal identifiers and their use in the collection of personal and confidential data are currently prohibited or protected by a wide body of law, especially in legal, medical, educational and financial contexts. Many social, financial, medical and other types of applications share these types of difficulties and thereby lack the means for collecting data which is needed for rigorous evaluation and scientific investigation.
Thus, a need remains in the art for providing a universal process that may be used to confidentially collect and exchange data from a variety of sources for a variety of purposes.

Systems and methods for controlling data access by use of a universal anonymous identifier


A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device in the first thin semiconductor film to an integrated circuit in the second thin semiconductor film. The two thin semiconductor films are formed separately from the substrate. The first thin semiconductor film may include an array of semiconductor devices. The first and second thin semiconductor films may be replicated as arrays bonded to the same substrate.

1. Field of the Invention
The present invention relates to a semiconductor apparatus useful in, for example, a light-emitting diode (LED) print head in an electrophotographic printer.
2. Description of the Related Art
Referring to FIG. 28, a conventional LED print head 900 includes a circuit board 901 on which are mounted a plurality of LED array chips 902 having electrode pads 903, and a plurality of driving integrated circuit (IC) chips 904 having electrode pads 905. The electrode pads 903, 905 are interconnected by bonding wires 906 through which current is supplied from the driving IC chips 904 to LEDs 907 formed in the LED array chips 902. Further electrode pads 909 on the driving IC chips 904 are connected to bonding pads 910 on the circuit board 901 by further bonding wires 911.
For reliable wire bonding, the electrode pads 903, 905, 909 must be comparatively large, e.g., one hundred micrometers square (100 μm×100 μm), and the LED array chips 902 must have approximately the same thickness as the driving IC chips 904 (typically 250–300 μm), even though the functional parts of the LED array chips 902 (the LEDs 907) have a depth of only about 5 μm from the surface. To accommodate the needs of wire bonding, an LED array chip 902 must therefore be much larger and thicker than necessary simply to accommodate the LEDs 907. These requirements drive up the size and material cost of the LED array chips 902.
As shown in plan view in FIG. 29, the electrode pads 903 may need to be arranged in a staggered formation on each LED array chip 902. This arrangement further increases the chip area and, by increasing the length of the path from some of the LEDs 907 to their electrode pads 903, increases the associated voltage drop.
The size of the driving IC chips 904 also has to be increased to accommodate the large number of bonding pads 905 by which they are interconnected to the LED array chips 902.
Light-emitting elements having a thin-film structure are disclosed in Japanese Patent Laid-Open Publication No. 10-063807 (FIGS. 3–6, FIG. 8, and paragraph 0021), but these light-emitting elements have electrode pads for solder bumps through which current is supplied. An array of such light-emitting elements would occupy substantially the same area as a conventional LED array chip 902.

This patent is subject to a terminal disclaimer.

Combined semiconductor apparatus with thin semiconductor films


A system for drying vehicle bodies and/or for controlling the temperature thereof. The system includes a cabin and has a heater for heating hot air for the cabin. The system is equipped with a mechanical energy-consuming device, for example, a generator and/or a fan. The heater contains at least one heat exchanger. The hot exhaust gas of a thermal engine can be supplied to the heat exchanger. The thermal engine is coupled to the mechanical energy-consuming device, for example, the generator, so as to move together. Because of the coupled movement, mechanical energy can be transmitted from the thermal engine to the mechanical energy-consuming device.

Such a system is known from EP 1 302 737 B1, which describes a painting or coating plant for vehicle bodies, which include a drying module with a heating-up cabin for drying freshly painted or coated vehicle bodies. To this end, hot air can be circulated in the drying module with the aid of a fan. The circulated hot air is heated in a heat exchanger.
To ensure reliable operation of industrial plants and assembly lines, in particular in the production of automobiles, it is necessary to continuously supply electrical energy to the control and drive systems provided therein. This is not a given in, among others, the so-called developing countries and emerging market countries. There, a failure occasionally occurs in the utilities or power grids for electrical energy. Therefore, the utilities of production facilities are provided with emergency backup generators or systems for storing electrical energy to maintain production even in the case of a breakdown of the power supply voltage.


A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.

1. Field of the Invention
The present invention relates to a semiconductor memory with an error correction function.
2. Description of the Related Art
A semiconductor memory with an error correction function includes regular cell arrays for storing data from the outside, and parity cell arrays for storing parity data of data written into the regular cell arrays. The parity data are generated corresponding to the write data by means of a parity generation circuit. It is therefore not easy to write predetermined data into the parity cell array. In consideration of this problem, there are disclosed technologies in which external parity data terminals for reading data from the parity cell arrays and writing data into the parity cell arrays are formed in a semiconductor memory, and data is directly written into the parity cell arrays and directly read from the parity cell arrays during the test mode, thereby saving test time (for example, Japanese Unexamined Patent Application Publication No. 5-54697).
Meanwhile, the ratio of the parity cell array occupied in the regular cell array is lowered as the bit number of data for generating parity data is increased. Thus, it has small influence on the chip size. For this reason, in this kind of a semiconductor memory, in order to minimize an increase in the chip size, there is a case where parity data are generated using data having a large bit width, which are written into a plurality of regular cell arrays to which different addresses are allocated. In this case, data supplied to external data terminals are written into any one of the regular cell arrays, which is selected according to an address. In parity memory cells, addresses correspond to a plurality of different regular memory cells. Thus, if the external parity data terminals are formed in this kind of the semiconductor memory, an address map of regular cell arrays and an address map of parity cell arrays are different during the test mode where the external parity data terminals are used.
In the event that the aforementioned semiconductor memory is tested, test data supplied to the external data terminals are written into any one of the regular memory cells of the regular cell array according to an address. The test parity data supplied to the external parity data terminals are written into any one of the parity memory cells of the parity cell array according to an address.
As described above, in the test mode, the address maps of the regular cell arrays and the parity cell arrays are different. Due to this, there is no co-relation in physical locations between the regular memory cell into which the test data are written, and the parity memory cell into which the parity test data are written. That is, the regular memory cell and the parity memory cell into which data are written do not exist relatively at the same location within the regular cell arrays and the parity cell arrays. Accordingly, in this kind of the semiconductor memory, there is a problem in that it is difficult to find the relation between a regular cell array where failure has occurred and a parity cell array. Further, in the case where failure occurring due to the interaction between data stored in memory cells is evaluated, it is necessary to generate test patterns for the regular cell array and the parity cell array, respectively, in order to evaluate their interaction. This results in an increase in the number of test patterns to be managed since the design time needed for the test patterns becomes lengthy. Furthermore, in a redundancy decision test for determining the use of a redundancy circuit that corrects failure, a redundancy decision test must be performed on a regular cell array and a parity cell array, respectively. Accordingly, there is a problem in that the test efficiency is low.


A user interface engine may be created that uses a descriptive language to describe the user interface fields, the corresponding device properties, and other layout attributes. This information may be stored in description file. The user interface engine may then read in this description file, render the user interface, and generate device property value payload. Then the payload may be deployed to target devices. This allows a network management application to be modified without requiring user interface code or data structure classes to be written or changed.

The management of computer networks has grown in complexity as networks have become larger and more advanced. New features offered by the networks require new features in the management software. As such, delivering a streamlined and effective network management product to businesses has become a goal of many software designers.
As network management applications have been developed for many years, there are a number of applications with complex code. This is due to the fact that typically programmers will add additional code when new features are added, but will not remove outdated or redundant code, either by choice or by simply not being able to locate all of the portions to be removed. This can all be traced to many companies' lack of a true development process and lack of adequate documentation regarding the created code.
This condition ultimately requires a steeper and longer learning curve for new developers to develop new features: as the code becomes more and more complex, it becomes harder and harder for developers to add additional features, and those additional features add more complexity to the code, making it even hard for developers to add newer features, and so on. This also puts a business at risk due to knowledge and design not being documented.
As such, programmers are often unable to meet shorted product cycles for new network management applications due to product requirement changes. For example, the label of a user interface may change, or new user interface fields in the application may need to be added. These changes are even more significant and complex if the Simple Network Management Protocol (SNMP) management information base (MIB) definitions are changed, which results in more work for modifications, backward compatibility issues, etc. Furthermore, once all this is changed, a Quality Assurance (QA) and documentation team must also reperform all testing and update the user manuals, all of which ultimately delays product delivery.
Furthermore, past solutions have been plagued by an inefficient network management software development process. Whenever a new product feature is required, a new graphical user interface (GUI) or Java applet may be developed, although the underlying workflow has not changed (getting user settings from the GUI, binding them to the SNMP MIB variables, and deploying the settings to the target devices). This leads to laborious programming, error-prone and repetitive work, code duplication, etc. The more code that is written, the more that bugs will be encountered. This includes time consuming software debugging and maintenance, as well as support costs. The past development process fails to identify the commonalities underlying network management software applications.
What is needed is a way to be able to massively produce network management software applications without laborious programming.
Furthermore, what is needed is a solution that allows network administrators to customize network management applications to meet their own needs. There currently is no widely-known way for a network administrator to change the network management application's user interface to allow him to add/delete/update the user interface to the network administrator's own liking, or to manage new devices that are not native to the network management application. If a customer has a new request, they must ask the application vendor to develop a customized solution just for the one customer, which may not be needed by other customers. This adds costs to the network management application that other customers must bear.

Description-based user interface engine for network management applications


A method for manufacturing an inkjet recording medium comprising the steps of: applying a coating color containing a pigment and a binder as major components to at least one side of a base material using a transfer roll coater, subsequently drying coating layer to form an ink absorbing layer, wherein Hercules viscosity of coating color is 5 m Pa·s to 30 m Pa·s and pigment contains a synthetic silica having an oil absorption of 90 ml/10 g to 200 ml/100 g, a BET specific surface area of 45 m2/g to 200 m2/g and an average particle diameter of 1.0 μm to 3.0 μm and/or a precipitated calcium carbonate-silica composite having an oil absorption of 100 ml/10 g to 250 ml/100 g, a BET specific surface area of 5 m2/g to 150 m2/g and an average particle diameter of 1.0 μm to 10 μm.

1. Field of the Invention
The present invention relates to a method for manufacturing an inkjet recording medium of which the ink absorbing layer is formed using a transfer roll coater.
2. Description of the Prior Art
Inkjet recording method involves ejecting small droplets of ink using various mechanisms and forming images and letters by allowing the droplets onto a recording medium such as paper. This recording method has become phenomenally popular in homes since it readily performs at high speed and provides full color prints, less noisy in printing, and the printing devices are inexpensive. In commercial applications, non-impact printing (NIP) has been previously used to print variable information (invoices and receipts for public fees and credits, shipping bills, advertisements and the like), and high speed inkjet printers having a line head recently started to replace existing methods.
The recording medium used for inkjet recording is roughly classified into a non-coated paper type on which an ink absorbing layer containing a pigment has not been formed and a coated paper type on which an ink absorbing layer containing a pigment has been formed. The less expensive non-coated paper is ordinarily used for home page printing and business reports and the coated paper that can reproduce high resolution images is used to print outputs from digital cameras and the like.
Especially, the inkjet recording comes to have various uses, and a coated paper type inkjet recording medium that can be printed on both sides and can reproduce high resolution images inexpensively is needed. In order to improve productivity and reduce the cost of inkjet recording medium production, a technology that enables the use of an on-machine coater is urgently needed.
In addition, offset printability is also needed in an inkjet recording medium since, in some cases, backgrounds (borders, logo marks and the like) are printed first using offset printing before inkjet printing is used.
As a technology for manufacturing an inkjet recording medium using an on-machine coater, a technology in which an inkjet recording paper that can be printed using an offset printing method is manufactured using an on-machine coater (see, for example, Unexamined Japanese Patent Publication(Kokai) 2002-127587) and a technology for manufacturing an inkjet recording paper having the feel of non-coated paper (see, for example, Unexamined Japanese Patent Publication(Kokai) Hei 4-219267) have been disclosed. In addition, as a technology to manufacture general purpose printing paper at high speed, a technology to manufacture a coated paper for printing using a gate roll coater (see, for example, Unexamined Japanese Patent Publication(Kokai) Hei 6-25997) has been disclosed.

Process for producing inkjet recording medium


A method and apparatus for lifting and transferring a disabled person to and from a wheel chair includes an elongated sheet of material having handles at each end. This sheet of material is spread beneath the buttocks of a seated disabled person. An attendant reaches for the handles to either side of the person and straightens up to lift the person slightly from the place at which the person is seated. The attendant pivots on one foot to swing the person to a new location to be seated and bends over to allow the person to be seated in that location. The attendant either leaves the elongated sheet of material beneath the buttocks of the person for a later lifting and transferring or slides it from beneath the buttocks to leave the person freely seated in the new location. These steps may be taken to place a person in a wheel chair from a seated position or vise versa.

1. Field of the Invention
The present invention relates to lifting and transferring disabled persons from one resting place to another. More particularly, the present invention relates to an apparatus that may be used to lift a disabled person and to transfer the person to and from a wheelchair, from and to a stationary chair, bed, or automobile seat or the like. The present invention also relates to the method by which the apparatus is to be used.
2. Description of the Prior Art
Any number of methods and systems have been used to lift and transfer disabled persons, that is, persons disabled in the sense that they are not able to move themselves. Some patent references teach the concept of a lifting device that would be always positioned beneath a person while that person is seated and that would be available for an attendant to lift the person by grasping the device to either side of the person and lifting.
U.S. Pat. No. 2,835,902 issued to Fash on May 27, 1958, discloses a lifting sheet for lifting and handling a person who is not able to move about under his or her own power. The form of construction of the Fash lifting sheet is especially designed for use in lifting a patient from a wheelchair to a table, bed, or the like. The lifting sheet is formed of a suitable fabric having the desired tensile strength to support the weight of the body to be lifted, carried, or moved about. The sheet is preferably rectangular in plan view. It has elongated slips which extend inwardly from an edge portion that, when placed on a chair, would be most proximate the shoulders of the person being lifted and handled. It also has arm sleeves into which the arms of attendants may be slid. Near the arm sleeves are parallel slits which provide straps to be grasped by the hands. This device does not have handles extending from the sheet, but rather within the sheet's boundary. The structure of this device is particularly adapted for use by two cooperating attendants, which is a disadvantage for a single attendant.
U.S. Pat. No. 3,859,677, issued to Nordwig on Jan. 14, 1975, discloses a substantially rectangular sheet of flexible material which has aligned loops formed along opposite edges for receiving a pair of rigid, elongated handles. The loops are spaced apart so that hands may be inserted for grasping or lifting the device. This device essentially teaches using an elongated sling as a lifting seat which extends between handles at opposite ends. As a drawback, this device depends on the structure of the rigid bar handles for lifting, which would be difficult to slide beneath a person seated in a wheel chair and uncomfortable for the person so seated while the device is put in place for use.
U.S. Pat. No. 4,716,607 issued to Johansson, on Jan. 5, 1988, discloses a patient transfer mat for aiding and moving a patient who cannot move himself or herself. The teaching is particularly adapted to using two mats, one of which would be placed under the buttocks of a patient, while the other would be placed under the shoulder of the patient. The method of using this device is to move the patient by sliding of lifting the patient while the patient is in a stretched out position and does not contemplate use of the device to transfer a patient from one sitting position to another and so is not particularly adapted for use with a wheel chair.
U.S. Pat. No. 4,723,327 issued to Smith on Feb. 9, 1988, discloses a device to transport and move bedridden patients easily and securely without potential injury to either the patient or the attendant. The device is a generally square sheet of flexible fabric material. An integral perimeter handle is movably positioned within the fabric. This device is contemplated for use with a bed ridden patient, and there is no teaching in the reference suggesting a methodology for lifting and transferring a person using a wheelchair.
U.S. Pat. No. 4,737,997 issued to Lamson on Apr. 19, 1988, discloses a method of moving a person from a bed to a wheelchair. Lamson employs a seat section and a conveyor section. What is of particular interest is that the seat section is left in place once the person is positioned in the wheelchair. But while this teaching of leaving a transporting device in place in a wheelchair is now known in the art, the particular structure called for by Lamson requires a special, and not a standard wheelchair for its use. The methodology taught by Lamson also requires the specialized wheelchair equipment.

Method for lifting and transferring a disabled person to and from a wheelchair


A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points. Each of the plurality of semiconductor chips includes first and second terminals. Moreover, a first wiring up to the first terminals and a second wiring up to the second terminals are in a positional relationship of being shifted parallel to each other in a planar direction of the wiring board so as not to come into electrical contact with each other. In each of the first and second wirings, a wire is provided between a connection point for the terminal in a first one of the semiconductor chips and a position of a root, a complete binary tree structure in which all leaves are at the same depth from the root is formed, connection points for the terminals in the rest of the semiconductor chips are positioned at the respective leaves, and the paths of wires respectively corresponding to branches at the same depth in the tree structure include vias and the lengths of the paths of wires including the lengths of the vias are equal to each other.

1. Field of the Invention
The present invention relates to a wiring board and more particularly relates to a wiring board including wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points.
2. Description of the Related Art
There are a wide variety of electronic devices that implement one-to-many connection between a plurality of semiconductor chips, for example, between one memory controller chip and a plurality of random access memories (hereinafter referred to as RAMs), all of which are mounted on a board. Such boards include a board having a plurality of semiconductor chips or semiconductor modules mounted thereon, such as a semiconductor package board, a printed circuit board, a system-in-package board and a multichip module board.
In the connection between a memory controller chip and a plurality of RAM chips, wiring for a plurality of signals on data, address, clock, clock enable and chip select are drawn out by bus wiring method, branched in the middle and connected to the plurality of RAM chips. In order to complete, within the board, functions of such a system including two kinds of chips, the memory controller chip and the RAM chips, it is preferable that all the bus wiring paths between the memory controller chip and the RAM chips be set to have an equal length, thereby eliminating a phase difference due to wiring delay in signal transmission.
Japanese Patent Application Laid-open No. 2004-119454 (Patent Document 1) discloses a printed circuit board in which all wires in a bus wiring are set to have an equal length. FIGS. 3A and 3B are views schematically showing a structure of the printed circuit board disclosed in the Patent Document 1. FIG. 3A is a plan view. In FIGS. 3A and 3B, one memory controller IC 102 and two RAMs 103 and 104 are mounted on a printed wiring board 100. The printed wiring board 100 is a semiconductor package board including two layers, which are a front-side and a back-side layers, each layer having wiring. Reference numeral 110 denotes a bus wiring path which connects the memory controller IC 102 to the RAM 103. The bus wiring paths 110 are provided on the front-side layer of the printed wiring board 100. Reference numeral 111 denotes a bus wiring path which connects the memory controller IC 102 to the RAM 104. The bus wiring paths 111 are respectively provided by branching the bus wiring paths 110, which are extended from the memory controller IC 102, at vias 120 and are connected to the back-side layer of the printed wiring board 100. The bus wiring paths 110 and 111 are line-symmetrically drawn out toward the RAMs 103 and 104, respectively, from the vias 120 to be branch points. Moreover, the bus wiring paths 111 are routed back to the front-side layer of the printed wiring board 100 through vias 121 and are connected to the RAM 104.
Here, in the bus wiring paths 110, the positions of the vias 120 are determined so that the wires from the vias 120 to the memory controller IC 102 can be parallel to each other and have an equal length. Moreover, the positions of the vias 120 are determined so that the length of the each wire from the corresponding via 120 to the RAM 103 in the bus wiring paths 110 and the length of each wire from the corresponding via 120 to the RAM 104 in the bus wiring paths 111 can be linearly equal to each other. Since the RAMs 103 and 104 are identical RAM chips, the wires are connected to the RAM 103 at identical positions where the wires are connected to the RAM 104. Therefore, the vias 120 are disposed at middle points between the RAMs 103 and 104 while the series of vias 120, the RAMs 103 and 104 are arranged in parallel with one another.
FIG. 3B is a perspective view schematically showing the printed circuit board shown in FIG. 3A. The printed circuit board has the structure in which the length of each wire from the via 120 to the RAM 103 in the bus wiring paths 110 and the length of each wire from the via 120 to the RAM 104 in the bus wiring 111 are set to be equal to each other. However, with reference to FIG. 3B, the length of each wire leading from the vias 120 to the RAM 103 and the length of each wire leading from the via 120 to the RAM 104 are not completely equal. Specifically, in the wiring paths from the memory controller IC 102 to the RAM 104, the vias 120 and 121 are used to provide wiring to connect the front-side and back-side layers. Therefore, the wiring length from the memory controller IC 102 to the RAM 104 is longer than the wiring length from the memory controller IC 102 to the RAM 103 by the lengths of the vias 120 and 121.
Meanwhile, there has recently been an increasing demand for higher-speed memories up to beyond gigabit speed. Accordingly, great importance has been placed on the impact of wiring delay on signal transmission. Thus, there is an increasing need to set all the bus wiring paths between the memory controller chip and the RAMs to have an equal length. However, according to the conventional technology, the lengths of all the bus wiring paths cannot be set completely equal since some include the lengths of the vias while other do not. Therefore, there is a difference in delay of signal transmission among the wiring paths within the board. As a result, there is an increasing risk that a stable operation cannot be guaranteed in an operation beyond the gigabit speed.


A system for augmenting spinal vertebrae utilizing a system that increases the bone density of adjacent vertebral bodies is disclosed. This system may be placed in the cranial and/or caudal end positions of the spinal construct to address potential adjacent level failure.

The spinal column is a complex system of bones and connective tissues that provide support for the human body and protection for the spinal cord and nerves. The adult spine is comprised of an upper and lower portion. The upper portion contains twenty-four discrete bones, which are subdivided into three areas including seven cervical vertebrae, twelve thoracic vertebrae and five lumbar vertebrae. The lower portion is comprised of the sacral and coccygeal bones. The cylindrical shaped bones, called vertebral bodies, progressively increase in size from the upper portion downwards to the lower portion.
An intervertebral disc along with two posterior facet joints cushion and dampen the various translational and rotational forces exerted upon the spinal column. The intervertebral disc is a spacer located between two vertebral bodies. The facets provide stability to the posterior portion of adjacent vertebrae. The spinal cord is housed in the canal of the vertebral bodies. It is protected posteriorly by the lamina. The lamina is a curved surface with three main protrusions. Two transverse processes extend laterally from the lamina, while the spinous process extends caudally and posteriorly. The vertebral bodies and lamina are connected by a bone bridge called the pedicle.
The spine is a flexible structure capable of a large range of motion. There are various disorders, diseases and types of injury, which restrict the range of motion of the spine or interfere with important elements of the nervous system. The problems include, but are not limited to, scoliosis, kyphosis, excessive lordosis, spondylolisthesis, slipped or ruptured discs, degenerative disc disease, vertebral body fracture, and tumors. Persons suffering from any of the above conditions typically experience extreme or debilitating pain and often times diminished nerve function. These conditions and their treatments can be further complicated if the patient is suffering from osteoporosis, or bone tissue thinning and loss of bone density.
Spinal fixation apparatuses are widely employed in surgical processes for correcting spinal injuries and diseases.
One growing trend seen post-surgical treatment of a patient's spine is the incidence of proximal junctional kyphosis (PJK), which is typically an adult spinal deformity surgical outcome if the lumbar lordosis and thoracic kyphosis are not properly restored post-surgery. PJK appears at or above the cranial-most thoracic level treated. Even though PJK most commonly occurs in the thoracic region of the spine, it can also occur in various spinal regions and may occur above or below the instrument levels and may impact the next adjacent level or two that is not instrumented. This type of failure is called adjacent level failure. Symptoms of PJK and adjacent level failure include pain, neurological deficit, ambulatory difficulty and poor maintenance of sagittal balance. For patients that present with these symptoms, often the only treatment is an additional surgery. The incidence rate of PJK, but may be upward of 50% of long construct, instrumented fusion cases.
What is needed is a treatment targeted to the instrumented levels, and/or adjacent vertebral level(s) from those that are instrumented thereby reducing the likelihood of PJK.


A donor substrate having a plurality of recesses and isolation structures may be provided. The isolation structures may be defined by the recesses. A first electrode is formed on a first substrate. A pixel defining layer may be formed on the first electrode to define a plurality of pixel regions. The donor substrate may be arranged over the first substrate, and a laser induced thermal imaging process may be performed to form a plurality of light emitting layers in the pixel regions. A second electrode may be formed on the pixel defining layer and the light emitting layers. The organic light emitting layers having minute dimensions may be effectively obtained from the donor substrate. The isolation structures may be formed integrally with the substrate, and thus the donor substrate may be easily recycled after the laser induced thermal imaging process.

1. Field
Example embodiments of the invention relate to donor substrates, methods of manufacturing donor substrates and methods of manufacturing organic light emitting display devices using donor substrates.
2. Description of Related Art
Generally, an organic light emitting display device may include a thin film transistor, a pixel electrode, an organic layer, a common electrode, etc. The organic layer may include an organic light emitting layer emitting at least one of a white color of light, a red color of light, a green color of light and a blue color of light. The organic layer may additionally include a hole injection layer (HIL), a hole transfer layer (HTL), an electron transfer layer (ETL), an electron injection layer (EIL), etc.
In a process for forming organic light emitting layers in a comparable organic light emitting display device, a red organic transfer layer, a green organic transfer layer and a blue organic transfer layer may be formed on a donor substrate, and then the organic transfer layers may be transferred onto the pixel electrode using a laser beam, thereby forming the organic light emitting layers on pixel electrodes of pixels in the comparable light emitting display device. In this case, contaminations of the organic light emitting layers may be frequently generated because of static electricity, and color mixing of adjacent pixels in the comparable organic light emitting display devices may likely occur.

Donor substrates, methods of manufacturing donor substrates and methods of manufacturing organic light emitting display devices using donor substrates


In a system that plural apparatuses mutually perform data communication, it enables to prevent decrease in productivity and to smoothly operate the entire system. In the system, when data received from an image data generation apparatus through a data communication medium is image data, acceptance from other image data generation apparatus is invalidated, and a printing process for the image data from the image data generation apparatus is performed. According as the data received from the image data generation apparatus through the data communication medium is first information output when an error occurs in the image data generation apparatus and representing this error, the invalidation of the acceptance from the other image data generation apparatus is released.

1. Field of the Invention
The present invention relates to an image forming apparatus capable of performing data communication with other apparatus, an image forming system, a control method thereof, an image forming method, and a storage medium.
2. Related Background Art
Recently, it has been proposed an image forming system in which plural image data generation apparatuses and plural image forming apparatuses remotely located mutually perform data communication through a transmission medium. Especially, the image forming system called a remote copying system in which the image data generation apparatus such as a scanner or the like and the image forming apparatus such as a printer or the like are connected by the transmission medium has been thought.
However, in this remote copying system, when the image data generation apparatus side starts the data communication to the image forming apparatus and then some error occurs on the image data generation apparatus side, there is a possibility for the image forming apparatus to be on standby until the error is released. Thus, when it enters once such a state, output jobs transmitted from other scanner, computer and the like can not be accepted, the standby state for execution of such the jobs continues, whereby it is anticipated that productivity of the entire system decreases.

Image forming system, image forming apparatus, control method thereof, image forming method, and storage medium


Methods for separating metal ions from pulp material are disclosed including treating the pulp with a chelating agent to produce a pulp flow with dissolved metal ions, washing that pulp flow prior to bleaching with hydrogen peroxide or ozone and mixing the washed liquid containing metal ions with another flow of lignocellulose-containing material in order to bind the metal ions to that flow, washing that flow, and subsequently washing that flow at a reduced pH to produce a wash flow containing metal ions.

In present pulp mills, as well as those contemplated in the future, there are and will be liquid flows which are contaminated by various metal ions, which can disturb the bleaching reactions which take place during bleaching with hydrogen peroxide or ozone. These liquid flows occur, for example, during totally chlorine-free bleaching, so-called TCF-bleaching (TCF=Totally Chlorine Free), when the pulp is treated with chelating agents, such as EDTA or DTPA, in order to substantially reduce the metal ion content of the pulp prior to its bleaching with peroxide or ozone. This type of bleaching, in order to yield high ISO-brightness, requires that both the pulp and the process water be free or substantially free of certain metal ions since otherwise the charged hydrogen peroxide will effectively disintegrate to water and oxygen gas, and the charged ozone to oxygen gas, without having any simultaneous bleaching effect.
Particularly at those times when the pulp mill is closed, for example for environmental reasons, these liquids containing metal ions can be very difficult to deal with in order to prevent their contact with the bleaching step which would then deteriorate bleaching efficiency.

Method of separating metal ions from pulp using a chelating agent


The present disclosure provides an image acquisition method, an electronic apparatus, an electronic device, and a storage medium. The method includes: receiving an image function enabling instruction and controlling, according to the image function enabling instruction, a touch display apparatus to enter an image acquisition interface; receiving a touch action on a screen of the image acquisition interface; determining whether image acquisition duration of the touch action on one same area of the screen of the image acquisition interface is greater than or equal to a preset image acquisition preparation time; and controlling an image sensing apparatus to acquire a corresponding image if the image acquisition duration of the touch action on the screen of the image acquisition interface is greater than or equal to the image acquisition preparation time.

At present, with the continuous development of electronic technologies, there are more and more electronic devices that can be configured to photograph, for example, a mobile phone, a digital camera, and a tablet computer. Using a mobile phone as an example, at present, most mobile phones are equipped with a touch screen and a photographing button; when the mobile phone is in a photographing mode, the touch screen may display in real time a preview image for reference to a user; and after selecting a target to photograph, the user may perform a photographing operation by tapping the photographing button.
However, when the user needs to take a selfie by using a rear camera or needs to photograph by raising the mobile phone high above the head top (during photographing in accident onlookers, car exhibition, music concerts, or model photographing), a problem easily occurs that the user cannot tap or even cannot find the photographing button. Moreover, as the size of a smart phone increases continuously, a user cannot conveniently tap a photographing button to start a shutter; in particular, tapping a photographing button becomes harder for a user having small hands or a user that wants to complete a photographing operation with one hand.
At present, a technical solution to the foregoing defect is to set a touch screen photographing function in a photographing device of a mobile phone, where photographing is performed by tapping a screen after the touch screen photographing function is opened in settings. As shown in a schematic diagram of a photographing device in the existing technology in a set state in FIG. 1, a touch screen 11 and a setting button 12 are included. A user may open a setting interface by pressing the setting button 12, so that a touch screen photographing function key 121 and other functional keys 122 are displayed. However, in the technical solution, the user is required to tap the setting button to select the touch screen photographing function, photographing by tapping a screen easily causes an unintended operation, and the touch screen photographing function conflicts with other functions of the photographing device, for example, when the touch screen photographing function key 121 is in a selected state, some of the other functional keys 122 (for example, an autofocus functional key) is inoperable.

Image acquisition method, electronic apparatus, electronic device, and storage medium

TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED


Methods and structures within a SAS expander for initiating communication with one or more SAS initiators in a SAS domain to inform the initiators of sensed changes in the domain without the need for a full SAS Discovery process. In one aspect hereof, the expander may transmit a vendor unique BROADCAST primitive to inform SAS initiators that they should initiate a vendor unique SMP or SSP exchange with the expander to determine changes to the SAS domain. In another aspect hereof, the SAS initiator may respond as an SMP or SSP target device in response to initiation of vendor unique SMP or SSP exchanges by the expander. The expander may report to initiators regarding sensed changes in the domain and/or statistics regarding operation of the expander or other elements of the domain.

1. Field of the Invention
The invention relates generally to serial attached SCSI ("SAS") domains and more specifically to methods and structures enabling a SAS expander to initiate communication with a SAS initiator to identify sensed changes in the SAS domain.
2. Discussion of Related Art
Small Computer Systems Interface ("SCSI") is a set of American National Standards Institute ("ANSI") standard electronic interface specification that allows, for example, computers to communicate with peripheral hardware. Common SCSI compatible peripheral devices may include: disk drives, tape drives, CD drives ("CD-ROM", "CD-RW", etc), DVD drives, printers and scanners. SCSI as originally created included both a command/response data structure specification and an interface and protocol standard for a parallel bus structure for attachment of devices. SCSI has evolved from exclusively parallel interfaces to include both parallel and serial interfaces. "SCSI" is now generally understood as referring either to the communication transport media (parallel bus structures and various serial transports) or to a plurality of primary commands common to most devices and command sets to meet the needs of specific device types as well as a variety of interface standards and protocols.
The collection of primary commands and other command sets may be used with SCSI parallel interfaces as well as with serial interfaces. The serial interface transport media standards that support SCSI command processing include: Fibre Channel, Serial Bus Protocol (used with the Institute of Electrical and Electronics Engineers 1394 FireWire physical protocol; "IEEE 1394") and the Serial Storage Protocol (SSP).
SCSI interface transports and commands are also used to interconnect networks of storage devices with processing devices. For example, serial SCSI transport media and protocols such as Serial Attached SCSI ("SAS") and Serial Advanced Technology Attachment ("SATA") may be used in such networks. These applications are often referred to as storage networks. Those skilled in the art are familiar with SAS and SATA standards as well as other SCSI related specifications and standards. Information about such interfaces and commands is generally obtainable at the website http://www.t10.org. As used herein, reference to SAS devices and protocols may be understood to include SATA devices and protocols. The problems discussed herein and the solutions provided by this invention are similarly applicable to SATA devices.
Such SCSI storage networks are often used in large storage systems having a plurality of disk drives to store data for organizations and/or businesses. The network architecture allows storage devices to be physically dispersed in an enterprise while continuing to directly support SCSI commands. This architecture allows for distribution of the storage components in an enterprise without the need for added overhead in converting storage requests from SCSI commands into other network commands and then back into lower level SCSI storage related commands.
A SAS network typically comprises one or more SAS initiators coupled to one or more SAS targets often via one or more SAS expanders. In general, as is common in all SCSI communications, SAS initiators initiate communications with SAS targets. The expanders expand the number of ports of a SAS network domain used to interconnect SAS initiators and SAS targets (collectively referred to as SAS devices or SAS device controllers).
In general, a SAS initiator directs information to a SAS target device through ports of one or more SAS expanders in the SAS domain. A "port" in SAS terminology is a logical concept. A port may comprise one or more physical links in a SAS domain. Such physical links are often referred to as PHYs in the terminology of SAS domains. A port may use a single PHY or, if the port is configured as a wide port, may use multiple PHYs logically grouped to provide higher bandwidth.
When a SAS domain starts up, one or more initiator devices perform a "Discovery" process in accordance with the SAS specifications so that each SAS component may generate information indicative of the SAS domain topology. In other words, the SAS Discovery process specified by the SAS specifications permits each SAS device and each SAS expander in the domain to discover information about immediate neighbors coupled to its ports as well as information about other devices and expanders coupled to ports of neighboring components. Thus, each SAS device and SAS expander in a SAS domain may acquire information regarding the overall geometry or topology of the SAS domain.
When a change occurs in the SAS domain, a SAS expander as presently known in the art has only a limited role in adapting devices in the SAS domain to reconfigure for the sensed change. In particular, if a SAS expander senses a change in the SAS domain, as presently known in the art, the SAS expander may issue a BROADCAST(CHANGE) primitive to broadcast to all SAS initiators the fact that some change has occurred. The SAS expander does not inform the SAS initiators what change has been detected. Rather, a SAS initiator that receives the BROADCAST primitive on he SAS communication medium will perform the SAS Discovery process anew. The SAS Discovery process re-discovers all configuration and topological information regarding devices in the SAS domain—whether changed or not changed. Performing a complete SAS Discovery process to detect any change in a SAS domain, even a small change, consumes valuable resources in the SAS initiator and valuable bandwidth in the SAS domain communication paths.
It is therefore evident from the above discussion that a need exists for improved solutions in a SAS domain to easily identify changes in a SAS domain while reducing overhead processing and communication in the SAS domain.

Methods and structure for SAS expander initiating communication to a SAS initiator to identify changes in the SAS domain


A novel transflective liquid crystal display (LCD) is provided with a multilayer dielectric film transflector. The dielectric transflector is composed of alternating high and low refractive index dielectric material layers deposited directly on the inner side of the LCD substrate to avoid parallax. The transmittance of the dielectric transflector can vary from approximately 5% to approximately 95% by simply adjusting the individual dielectric layer thickness and the arrangement of layers. The thickness of the 10-layer film is approximately 700 nm, which does not affect the voltage drop on the LC. Two structures of the dielectric film using different positions of the materials of construction are provided and demonstrated. Such a transflective LCD exhibits outstanding features, such as, robust dielectric film, single cell gap, no parallax, and a simple fabrication process.

Integrating transmissive LCD's high contrast ratio and good color saturation and reflective LCD's low power consumption, transflective LCD is viewable at anytime and anywhere. Transflective LCD is an emerging display technology with wide application including mobile displays and communication displays, like mobile phone, barcode scanners, gaming, global positioning system (GPS)/navigation devices, personal data assistant (PDA), e-books, and the like.
A transflective LCD is disclosed in U.S. Pat. No. 6,281,952 B1 to Okamoto et al.; U.S. Pat. No. 6,295,109 B1 to Kubo et al.; U.S. Pat. No. 6,330,047 B1 to Kubo et al., using a split-pixel approach, i.e. each pixel is split into reflective (R) and transmissive (T) sub-pixels. Usually, the R and T area ratio is 4:1, in favor of reflective display mode in order to conserve power. The transmissive region with small area ratio is used for dark ambient surroundings only.
Two types of transflective LCDs have been developed: single cell gap 100 type as shown in FIG. 1 and double cell gap 200 type as shown in FIG. 2. In the single cell gap type, the cell gap 100 of the T-region is substantially equal to that of the R-region, which leads to the same response time in both T and R regions; however, their electro-optical curves cannot overlap well because light passes through the T-region once but through the R-region twice.
In the double cell gap approach, the cell gap 200 of the T-region and that of the R-region have approximately two times the difference so that the response time has approximately four times the difference between the R-region and the T-region. The split-pixel approach, regardless of whether single or double cell gap, has complicated structures and fabrication processes since each pixel is divided into R and T sub-pixels. Thus, the double cell gap LCD is more complicated than the single cell gap LCD.
In U.S. Pat. No. 6,124,971 to Ouderkirk et al., assigned to 3M Innovative Properties Company, a transflective structure is provided, using a reflective polarizing transflector, as shown in FIG. 3. The structure in FIG. 3 is a single cell gap 300 approach without split-pixel, thus, it is easy to fabricate. However, the transflector is located between the polarizer and backlight source, which results in parallax (double image) and deteriorates the resolution. In U.S. Pat. No. 4,093,356 to Bigelow, assigned to the General Electric Company, a transflective LCD with a metallic mirror 400 is described and shown in FIG. 4. The transflector is a half-silver metallic mirror, which is quite thin (˜50 nm) so that it can crack easily. The transflective LCD designs provided by both the 3M inventors and the General Electric inventor suffer from parallax. Parallax is that double image with displacement that occurs when one views a display panel from an oblique angle. Thus, it is desirable to have a parallax-free, transflective LCD that is robust, easy and inexpensive to fabricate.

Transflective LCD using multilayer dielectric film transflector

University of Central Florida Research Foundation, Inc.


The present invention discloses a method and system for computer-aided circuit design for checking the equivalence of data flow graphs by splitting data flow graphs representing finite precision arithmetic circuits into lossless subgraphs representing infinite-precision arithmetic circuits, and edges with information loss. The set of lossless subgraphs generated are leveled, and checked for equivalence as expressions. The edges with information loss are compared by establishing the equivalence of their bit width. The present invention declares data flow graphs as equal, if the respective lossless subgraphs and the bit-width at the corresponding edges with information loss are equal.

The present invention relates to the field of computer-aided chip design and, in particular, to comparison of circuits performing finite precision arithmetic operations, for equivalence.
Improved information processing has led to an increase in the complexity of the chips being used. With an increase in the complexity, a larger number of semiconductor devices, like logic gates, memories, central processing units, etc, are integrated in a single chip. This has generated a further demand for improvement in the existing techniques for circuit verification. In the rest of this application 'circuit' and 'chip' will be used interchangeably.
The process of circuit verification begins with the designing of the desired circuit. Circuits are designed using known computer-aided design tools, like Gemini CSX available from IKOS Systems, Cupertino, Calif., and System Realizer available from Quickturn Design Systems, Mountain View, Calif. These computer aided design tools use higher-level programming languages and Register Transfer Level (RTL) hardware programming languages to design a circuit. The higher level programming languages, and the RTL languages that are commonly used for circuit design are C and C++, and Verilog and VHDL respectively.
There are two main approaches to verify the correctness of a circuit. The first approach is known as Model Checking. In this approach, abstract properties that a circuit should satisfy are defined first. These properties are commonly defined using temporal logic, such as Linear Temporal Logic (LTL). Once these properties are defined, the verification of the circuit proceeds by checking that all the models of the circuit satisfy the property.
The second approach is based on equivalence checking of a circuit against a 'golden' model, i.e., another circuit that has been previously verified to be correct. An equivalence check is used to verify that a given circuit is functionally equal to the golden model. The golden model can be a circuit designed by higher level programming languages, like C, C++, etc., or could be an earlier version of the RTL circuit that needs to be refined.
Two main techniques have evolved to test the equivalence of circuits. In the first approach, the circuits are simulated for all possible set of inputs and the respective outputs are tested for equivalence. This process typically proceeds by creating a simulation driver that produces the simulation inputs and a simulation monitor that monitors the simulation outputs for equivalence. A limitation attached to this method is that with an increase in the complexity of circuits, covering all possible sets of inputs for determining equivalence becomes difficult. In addition, for complex circuits the time taken for simulation becomes high and as a result, the process of circuit comparison becomes slow.
The second approach is based on testing the equivalence of circuits by formal verification methods. In this approach, typically a circuit and the corresponding golden model are synthesized into bit-level designs. These bit-level designs are typically compared, using either decision diagram based techniques or SAT-based techniques. In the decision diagram based techniques, the bit-level designs are converted into canonic representations, which are then compared for equality. The most commonly used canonic representations are the Binary Decision Diagrams (BDDs). The SAT-based techniques transform the bit-level designs into boolean clauses, so that the clauses are simultaneously satisfiable, if and only if the circuits are inequivalent. The satisfiability of the clauses is determined through search-based techniques.
The main drawback of both approaches is that they require synthesis of the circuits being compared into bit-level designs. The representation of the synthesis tends to be exponential if the circuits are complex. Consequently, these approaches become impractical for complex circuits.
The problem associated with the blowing up of bit-level synthesis of complex circuits has been overcome by word-level techniques. One of the components of the word-level techniques for checking circuit equivalence is the use of theorem-provers for proving equivalence of arithmetic expressions.
Theorem provers, such as Cooperating Validity Checker (CVC), CVC Lite, developed by the Formal Verification Group of Stanford University, and Integrated Canonizer and Solver (ICS) developed by SRI, can be used to prove the equivalence of arithmetic expressions. These techniques check the equivalence of circuits involving arithmetic operations such as addition, subtraction, multiplication, division and comparison operations, such as 'less-than', etc. These theorem proving techniques use the associativity of addition and multiplication, and the distributivity of multiplication over addition, to transform arithmetic expressions into a unique canonic form, which can be compared for equality.
However, the theorem proving techniques such as CVC, CVC Lite and ICS can only test for the equivalence of arithmetic expressions of infinite precision. These techniques are not directly applicable for the comparison of circuits, since circuits are inherently associated with a finite precision. The principles of associativity and distributivity cannot be applied in the case of finite precision. For example, in the case of an infinite precision arithmetic expression such as a*(b+c), the principle of distributivity can be applied to obtain the equivalent expression a*b+a*c. However, such principles cannot be applied in a circuit with three finite width inputs, a, b and c that perform the operation a*(b+c), if the bit width of the output of any operator is different from that of the other operator. As a result, techniques such as CVC, CVC Lite and ICS cannot be directly used for the comparison of circuits.
In light of the preceding discussion, there exists a need for a method that efficiently compares arithmetic circuits with finite precision for equality. There is also a need of a method for circuit comparison that does not synthesize the circuits down to the bit-level. There is also a need of a method for circuit comparison that is computationally less intensive than the existing methods.

Circuit comparison by information loss matching


A multi-chassis network device includes a plurality of nodes that operate as a single device within the network and a switch fabric that forwards data plane packets between the plurality of nodes. The switch fabric includes a set of multiplexed optical interconnects coupling the nodes. For example, a multi-chassis router includes a plurality of routing nodes that operate as a single router within a network and a switch fabric that forwards packets between the plurality of routing nodes. The switch fabric includes at least one multiplexed optical interconnect coupling the routing nodes. The nodes of the multi-chassis router may direct portions of the optical signal over the multiplexed optical interconnect to different each other using wave-division multiplexing.

A computer network is a collection of interconnected computing devices that can exchange data and share resources. In a packet-based network, such as an Ethernet network, the computing devices communicate data by dividing the data into variable-length blocks called packets, which are individually routed across the network from a source device to a destination device. The destination device extracts the data from the packets and assembles the data into its original form.
Certain devices, referred to as routers, maintain routing information representative of a topology of the network. The routers exchange routing information so as to maintain an accurate representation of available routes through the network. A "route" can generally be defined as a path between two locations on the network. Upon receiving an incoming data packet, a router examines information within the packet, often referred to as a "key," to select an appropriate next hop to which to forward the packet in accordance with the routing information.
In general, service providers, such as an Internet service provider providing network services within the core of the Internet, continue to struggle to meet increasing bandwidth demands. One way to meet increasing bandwidth needs is to use "multi-chassis" routers. A multi-chassis-router is a router in which multiple routing nodes are physically coupled and configured to operate as a single routing node. One example of a multi-chassis router includes multiple line card chassis (LCCs), which include one or more interface cards (IFCs) for sending and receiving packets, and a central switch control chassis (SCC), which provides top-down management of the LCCs. This type of multi-chassis router is often referred to as a single-headed multi-chassis router, i.e., a routing system in which all routing computations are done on a single routing engine that is designated as the master of the routing system. To peer routers on the network, the multi-chassis router appears as a single routing node. Because multi-chassis routers combine resources of multiple routing devices, multi-chassis routers have much higher bandwidth capabilities than standalone routers. For example, the use of multi-chassis routers can simplify and improve routing on a service provider network by consolidating routing functions onto fewer routers.

Multi-chassis router with multiplexed optical interconnects


A process for obtaining purified hemicellulose, cellulose and cellulose-hemicellulose complexes comprising the steps of adding alcohol to caustic liquor from alkali extraction of fiber to precipitate the hemicellulose and the simultaneous, or about simultaneous, density separation of hemicellulose from the caustic liquor. The alcohol transforms the soluble high molecular weight hemicellulose into a light precipitate which floats on top of the caustic liquor solution. The caustic liquor can be subjected to a second separation step whereby the insoluble components (e.g. cellulose and cellulose-hemicellulose complexes) can be removed from the caustic liquor.

1. Field of the Invention
The invention pertains to a process for preparing purified fractions of hemicellulose and cellulose-hemicellulose complexes from alkali treated fiber. Specifically, the process involves the dispersion of alcohol in caustic liquor from alkali treatment of fiber to separate hemicellulose from impurities. The hemicellulose physically separates from the impurities, including cellulose and cellulose-hemicellulose complexes, by floating to the top of the caustic liquor after precipitation with alcohol. Density separation techniques are used to separate the floating precipitated hemicellulose simultaneously, or about simultaneously, with the formation of floating hemicellulose precipitate. The insoluble cellulose and cellulose-hemicellulose complexes can be removed from the caustic liquor by a further separation step.
2. The Prior Art
Fiber consists of hemicellulose, cellulose, some small amount of lignin, oil, starch, and protein. Alkali treatment of fiber, such as corn fiber or other seed fibers, solubilizes about two thirds of the available hemicellulose, and makes an insoluble cellulose-hemicellulose material. Both materials have value as hydrocolloids, however, a complex and difficult separation and refinement has been traditionally necessary to separate the material to produce separate products.
Also, the hemicellulose fraction will have impurities from the alkali separation. Purified hemicellulose has many commercial uses, including uses in the processed food industry; however the value of hemicellulose as a commercial product becomes limited if impurities obtained during the extraction of hemicellulose from fiber remain present in the final hemicellulose product.
U.S. Pat. No. 3,716,526 describes a process for obtaining refined hemicellulose comprising the steps of suspending powdered dried crude hemicellulose in aqueous organic acid and/or organic solvent and then physically separating impurities in the suspension to obtain purified hemicellulose. U.S. Pat. No. 2,868,778 describes a process involving precipitation of hemicellulose from extract by use of a solvent. U.S. Pat. No. 3,935,022 describes a method for treating caustic liquor, such as that originating in the alkaline refining of pulp or viscose manufacture, with one or more organic compounds which have a boiling point below 100° C. and are miscible with water (preferably ethanol) and sodium hydroxide to precipitate hemicellulose from the caustic liquor and then separating the precipitate by ordinary techniques of separation such as filtration, sedimentation and decantation, centrifugation and the like.
We have discovered a process whereby hemicellulose can be separated from caustic liquor by the simultaneous, or about simultaneous, precipitation of the hemicellulose from alkali solutions containing hemicellulose as well as insoluble cellulose and cellulose-hemicellulose complexes, such that hemicellulose precipitate floats on the caustic liquor. Density separation techniques can be used to separate the floating precipitated hemicellulose from the caustic liquor. In the process, the hemicellulose precipitate floats on the top of the caustic liquor as a result of the nature of the alcohol solution used for precipitation and separation parameters. The precipitated hemicellulose is removed from the caustic liquor before it swells and settles into the fluid, mixing with the insoluble cellulose and cellulose-hemicellulose complexes. The cellulose and cellulose-hemicellulose complexes can then be separated from the caustic liquor in a subsequent separation step.
All parts and percentages in this Specification are on a weight-by-weight basis, unless stated otherwise.

Process for preparing purified fractions of hemicellulose and cellulose-hemicellulose complexes from alkali treated fiber and products made by the process