An image display method and device for image display of 2.sup.N gradation characterized by previously making a write timing number table expressed in a numeration with a base of M (M: the number of gradation levels set for scanning line selection sequence) in which data of a specific digit corresponds to the gradation level and data of other digits differs in every scanning line, selecting a scanning line and a gradation level by referring the timing numbers generated in the course of time to the write timing number table, writing display data corresponding to the selected gradation level in batch into pixels on the selected scanning line, and forming N (N.ltoreq.M) images of single gradation, in which each image of single gradation includes all scanning lines.

The present invention relates to an image display method for gradation display by display means having pixels arranged in a matrix, and a device used for its execution.
Recently, image display devices of flat panel type using LCD (liquid crystal display), PDP (plasma display panel), and the like are used in various fields.
In this kind of image display device, generally, plural pixels are arranged in a matrix, scanning lines are disposed in the horizontal direction, and data lines, in the vertical direction. Accordingly, by selecting an arbitrary scanning line, display data can be written in batch from the data line into the pixels on that scanning line. By writing in this way while sequentially selecting all scanning lines for composing one screen, display data can be written into all pixels, and one image is formed.
That is, the image display device of flat panel type employs a different control system from the CRT (cathode ray tube) for scanning an electron beam continuously from top to bottom, and from left to right.
As an example of a device employing such control method, an image display device using PDP is disclosed in "Improvement in the Picture Quality on a 20-Inch Color Gas-Discharge TV Display" in Technical Report EID89-73 of Electrocommunications Society (published Jan. 18, 1990).
FIG. 1 is a block diagram showing an example of constitution of essential parts of the conventional image display device using PDP. This image display device comprises a display unit 20 having plural pixels arranged in a matrix, a cathode driving circuit 21 for driving the cathode of a display element for composing each pixel 200, an anode driving circuit 22 for driving the anode of a display element, an auxiliary anode driving circuit 221, a display control unit 23, and a field memory 24 for storing and holding display data.
In the display unit 20, moreover, plural cathode lines 201 are disposed in the horizontal direction, and plural anode lines 202 and auxiliary anode lines 203 are disposed in the vertical direction. The cathode of each pixel 200 is connected to one cathode line 201, and the anode is connected to one anode line 202.
Using this image display device, first, a method of displaying an image of single gradation will be described.
The display control unit 23 selects one out of the plural cathode lines 201. The cathode driving circuit 21 drives the selected cathode line 201 at a predetermined voltage level, and allows of writing into each pixel 200 on the selected cathode line 201. The display control unit 23 outputs an address to the field memory 24. The field memory 24 gives display data corresponding to each pixel 200 on the selected cathode line 201 on the basis of this address. The display data is on/off data corresponding to lighting or extinguishing of each pixel in the case of data for forming an image of single gradation.
The anode driving circuit 22 drives each anode line 202 at a predetermined voltage level in accordance with the display data, and writes display data into each pixel 200 on the selected cathode line 201.
The display control unit 23 selects different cathode lines 201 sequentially, and repeats same operation, so that display data can be written into all pixels 200 for composing the display unit 20, thereby displaying the image of single gradation.
Meanwhile, the auxiliary anode driving circuit 221 is a circuit for decreasing the delay time for starting discharge by discharging with preliminal auxiliary the pixels 200 before writing display data by the anode driving circuit 22.
Using the same image display device, a method of displaying an image having gradations (gradation image) is described. FIG. 2 is an explanatory diagram showing a method of displaying an image of 2.sup.8 gradations. The period required for forming one gradation image is called one field, and one field is divided into periods called sub-fields. In each sub-field, an image of single gradation is displayed, and by combining images of such single gradation, a gradation image can be displayed in one field.
In the case of gradation display, usually, the number of gradations is selected in 2.sup.N for the ease of control, and the division of the period of one field by this integer N is one sub-field. In the case of display in 2.sup.N gradations, the display data can be expressed in binary notation in N bits, and each sub-field corresponds to each bit of display data. That is, by defining the light emission time in each sub-field at a ratio of 2.sup.K (K=0, 1, . . . , N-1), each image of single gradation is weighted of luminance corresponding to each light emission time, so that an image of 2.sup.N gradations can be displayed.
In FIG. 2, supposing eight divided sub-fields to be seventh sub-field, sixth sub-field, fifth sub-field, zeroth sub-field, the display unit 20 is driven according to the seventh bit (MSB) of display data in the seventh sub-field, the sixth bit of display data in the sixth sub-field, the fifth bit of display data in the fifth sub-field, and so forth, and the zeroth bit (LSB) of display data in the zeroth sub-field.
In each sub-field, each cathode line 201 is selected sequentially, and display data is written in sequentially, as a result each pixel 200 to emit light starts to emit light sequentially. After lapse of different light emission time preset in each sub-field, each cathode line 201 is sequentially selected for extinguishing, and each pixel 200 is extinguished sequentially.
The light emission (display) time in each sub-field is, supposing to be 1 in the zeroth sub-field, 2 in the first sub-field, 4 in the second sub-field, 8 in the third sub-field, 16 in the fourth sub-field, 32 in the fifth sub-field, 64 in the sixth sub-field, and 128 in the seventh sub-field according to weighting by ratio, and, as a result, display of 2.sup.8 gradations is obtained.
In such conventional image display device, the light emission (display) time in the period of one field is short, and the utility rate of light emission time (the rate of light emission time in the period of one field) is very small. Therefore, as compared with the light emission performance of the display device itself, only a dark display is made.
For example, specifically describing by referring to FIG. 2, supposing the maximum light emission time in the seventh sub-field to be 100, it is 50 in the sixth sub-field, in the fifth sub-field, decreasing to half thereafter, and 0.78125 in the zeroth sub-field. Hence, the possible display time in the period of one field is 100+50+25+12.5+6.25+3.125+1.5625+0.78125=199.21875, and therefore if displayed at maximum brightness, only about 25% of the period of one field 100.times.8 is utilized, and it is very inefficient.
In "AC Type Plasma Display" in Journal of Society of Electricity, Vol. 116, No. 8, 1996, a method of driving the sub-fields by dividing the sub-fields further into the address period common in time and sustain period in the whole area. More specifically, in the address period, a feeble discharge is generated by scanning in every line according to the display data, and the wall charge is first accumulated in the display cells of the entire panel surface. Afterwards, in the sustain period, sustain pulses are applied simultaneously in display cells of the whole screen, and discharge is continued in the cells in which wall charge is formed, and the display is performed. Since the pulse applied in the address period can be narrowed, it is possible to drive in a very short period of 3 .mu.s or less per line when one second is composed of 60 frames each of which is divided into eight sub-fields.
Japanese Patent Application Laid-Open No. 6-242743 (1994) discloses a display method of enhancing the rate of display period executed in one field, by scanning the scanning lines at specified intervals changing gradually, and driving the display means using data of each bit of display data according to the intervals.


A method is disclosed for producing a ceramic substrate made of base that includes a stack of layers. Each layer in the stack includes a non-sintered ceramic material and a binder. The method includes debinding the layers in a temperature interval of TE1-TE3, where TE1 is a minimum debinding temperature and TE3>TE1, and sintering the layers at a temperature TS, where TS≧TE3. Debinding and sintering are performed in a same furnace, and a temperature T of the base does not fall below TE1 during debinding and sintering.

A method is known in which, for example, the decarbonization of the basic body is performed in a batch furnace, which is heated over an extend period of time to a temperature suitable for decarbonization. Then the basic body, cooled to room temperature, is removed from the batch furnace and, together with other already decarbonized basic bodies, placed onto a conveyer belt and fed into a sintering furnace configured for conveyor belts. The use of a continuous process is feasible here, because the sintering is not as time-consuming as the decarbonization.
A disadvantage of the known method is that it is unsuitable for the production of multi-layer substrates made of various ceramic materials having different relative permittivities and generally different coefficients of thermal expansion, in which layers with feedthroughs are provided. It was discovered that during the production of such multi-layer substrates, cracks often occur between the feedthroughs, which are normally made of a metalliferous paste, and the ceramic layer forming the surrounding environment of the feedthrough.

Method for producing a ceramic substrate


An electronic device including a metal casing and a covering structure is provided. The metal casing has a first opening. The covering structure includes a cover and a conductive component. The cover is assembled to the metal casing and covers the first opening, wherein the cover has at least one hole. The conductive component is fixed to the cover and has at least one contacting portion, wherein the contacting portion passes through the hole and contacts the metal casing, and an electromagnetic wave is adapted to pass through the conductive component to be transmitted to the metal casing.

Field of the Invention
The invention relates to an electronic device and a covering structure, and more particularly, to an electronic device and a covering structure having an electromagnetic interference shielding ability thereof.
Description of the Related Art
As technology advances, personal computers have been widely applied in work and life. The current common personal computers include desktop and notebook computers.
In terms of the personal computer, a casing of a host thereof generally has a reserved opening for facilitating an assembling an optical drive for expansion to the host, and then the opening is to be covered with a plastic cover. In addition, in order to prevent an electromagnetic wave generated by electronic components of the personal computer from causing an interference to other electronic devices and to avoid the electromagnetic wave from the outside from influencing the normal operation of the personal computer, a conductive component is usually being installed at the casing to cover the opening, so that the electromagnetic wave is able to be transmitted to the casing through the conductive component, thereby achieving an electromagnetic interference shielding effect. When a user is to install the optical drive for expansion to the host, the user has to firstly dissemble the plastic cover covering the opening of the casing and then to dissemble the conductive component, before installing the optical drive; and in some certain designs, the user even has to use tools to remove screws in order to smoothly perform the dissembling, and thus it is relatively time and labor costing.

Electronic device and covering structure


A method for generating content links between a first digital file and a second digital file by detecting a content feature of a first digital file segment of the first digital file during playback of the first digital file segment of the first digital file, searching an index of a plurality of content features for a plurality of segments including a second digital file segment of the second digital file, and dynamically generating a link between the first digital file one segment of the first digital file and the second digital file segment of the second digital file when a content feature of the first digital file segment of the first digital file is related to the content feature of the at least one segment of the second digital file.

1. Technical Field
Aspects of the example embodiments are directed to browsing for a digital video, and more specifically, using a link generated based on a content feature to browse for the digital video.
2. Description of Related Art
Usually, when browsing resources for content during open-ended information searching tasks, users must locate and synthesize ideas and concepts found across various resources. Within the context of textual material, browsing may combine alternatingly quickly skimming and intensively reading multiple documents. In practice, users need to be able to search and examine multiple documents simultaneously.
Related art video interfaces have been developed with an expectation that the user views a single video at a time, except in specific situations that require synchronized video streams (e.g. security surveillance). Such related art video interfaces may suggest an additional video to the user based on its similarity to the entire video currently being viewed. For example, a video may be suggested based on similar titles, or other similar text associated with the video (e.g. author, or abstract).
Alternatively, in the related art, a video may be suggested based on similar characteristics between the viewer and other viewers who have expressed a preference about the video, or have watched the video. Additionally, in the related art, a video may be suggested based on similarity of the metadata associated with the video. However, these suggestions are based on complete videos, and the related art systems do not support access to portions or segments within the video. Moreover, the similarity is judged with little or no context. Further, the only feature of the context that is used to generate suggestions is a recent or currently watched video of the user.
Related art video search sites suggest a related video based on metadata associated with the entire single video. Further, these related art search sites rely on author pre-defined web links or behavioral information of the author and/or viewer.
The related art systems provide links to related videos (and other media) which are reflective of the video content, in particular of named people appearing in those videos. However, linking is from a whole video to another whole video, rather than from one segment of a video to another segment of a single video. Further, linking is performed based on manually defined (i.e., by an author or a viewer) textual metadata.
One related art system presents video segments using a browsing interface where one axis (e.g., the horizontal axis) is time (i.e., temporal closeness), and another axis (e.g., the vertical axis) indicates content-based similarity. In this system, the user can navigate in any chosen dimension (e.g., in either the temporal dimension or the content-based dimension) from the current position. However, this related art system is strictly limited to segment-based analysis and relies on a "thread model" where frames are only organized linearly. As used herein, "thread model" means that the user can only navigate to the next closest object in any given dimension (i.e., the user can choose to go to the next/previous shot in time, the next/previous shot in relevance to the current search, visual similarity, text transcript similarity, automatically-determined concept similarity). In this related art system, there is no facility to allow the user to select the region of the video which is important. More generally, in this related art system, there is no way to add explicit feedback to the query dynamically. For example, to update recommendations by adding a text term, the entire query session needs to be reinitiated, which in turn changes all rankings (per thread) that appear in the interface. Existing related art systems do not allows for a more incremental approach to exploration by accumulating aspects of interest to the user while reviewing results.
A related art content-based video processing system has an object designated in one frame that can have its other occurrences in the video recalled. However, this system merely creates a custom timeline based on appearances of an object within one source video, and is merely an offline proof of concept system, which is not interactive. For instance, an object may appear at multiple times and in multiple scenes throughout a movie. This related art system allows a user to "recall" or be presented with other portions of the movie where the object appears. However, this related art system does not provide linking between different videos, and bases linking upon detected object appearance, not other content-measures. There is no actual interactive system presented and only linking is proposed with visual (SIFT) features based on entire frames or sub-frames.
Another related art system sequences a digital photo slideshow using metadata, but does not determine similarity between segments within the slide show, or navigation between these segments. This related art system sequences digital photos and relies only on metadata to establish photo similarity and re-rank the photos, but does not disclose sequencing videos or does not providing direct navigation between photos.
Yet another related art system allows users to select an object in a video and attach a link to the object. More specifically, the object is tracked throughout the video, and the link persists as long as the object is in the video. However, the link must be manually specified by the user, and is not determined automatically.
Another related art system user interface for playing hypervideo (aka "hyperlinked video"; "A displayed video stream containing embedded, clickable anchors") is provided. During playback, pre-authored video hyperlinks appear statically in the interface, and the user can follow the static hyperlinks. However, hyperlinks are not dynamically generated.

Hypervideo browsing using links generated based on user-specified content features


A bicycle display apparatus comprises a display device adapted to be mounted to the bicycle, wherein the display device displays various types of information to a rider; a light sensor; and a display control element operatively coupled to the display device and to the light sensor for controlling the display device in accordance with signals from the light sensor. An apparatus provided for shifting a bicycle transmission having a plurality of gear positions comprises a running condition detector that detects a running condition of the bicycle; a light sensor; and a gearshift control element operatively coupled to the running condition detector and to the light sensor and providing a control signal for controlling the bicycle transmission in accordance with signals from the light sensor.

The present invention is directed to bicycles and, more particularly, to bicycle devices that may be controlled at least in part by lighting conditions.
Bicycle computers often have an LCD display, for example, for displaying various types of information to the rider. Such information may include time, the bicycle speed, running distances, cadence (crank RPM), the gearshift position, and other information related to running conditions. Bicycle-mounted gearshift systems, and automatic gearshift systems in particular, comprise running condition detecting means for detecting the running condition of the bicycle, a gearshift apparatus, and gearshift control means for upshifting and downshifting the gearshift apparatus in accordance with the running condition of the bicycle.
Because the surrounding brightness differs between daytime and nighttime, there are cases when it is convenient to have the display and running conditions differ when riding the bicycle at these times. For example, at night it is more difficult to view the display and operate the bicycle even with a front headlight switched on. The desired information displayed in the morning and in the evening also may differ. However, there are only a few known systems that change the display and running conditions in conjunction with such surrounding conditions, and these systems are limited to changing the ON/OFF state of the front headlight in accordance with the illumination. As a result, advantageous display and running conditions cannot be provided in conjunction with the surrounding conditions.


In a ferroelectric data processing device for processing and/or storage of data with passive or electrical addressing a data-carrying medium is used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched between these and is provided as a continuous layer in or adjacent toelectrode structures in the form of a matrix. A logic element (4) is formed at the intersection between an x electrode (2) and a y electrode (3) of the electrode matrix. The logic element (4) is addressed by applying to the electrodes (2, 3) a voltage greater than the coercivity field of the ferroelectric material. Dependent on the polarization state and the form of the hysteresis loop of the ferroelectric material a distinct detection of the polarization state in the logic element (4) is obtained and it may also be possible to switch between the polarization states of the logic element, which hence may be used for implementing a bistable switch or a memory cell. The data processing device according to the invention may be stacked layerwise if the separate layers are separated by an electrical isolating layer and hence be used for implementing volumetric data processing devices.

The present invention concerns a ferroelectric data-processing device, particularly for processing and/or storage of data with active or passive electrical addressing, comprising a data-carrying medium in the form of a thin film of ferroelectric material, wherein the ferroelectric material by an applied electric field may attain a first or a second polarization state by being switched from a disordered state to one of the polarization states or from the first to the second polarization state or vice versa, wherein the ferroelectric material comprises logic elements, wherein a polarization state assigned to a logic element represents a logical value of the logic element, wherein the ferroelectric thin film is provided as a continuous or patterned layer, wherein a first and second electrode structure each comprises substantially mutually parallel strip-like electrodes, such that the electrode structures mutually form a substantially orthogonal x,y matrix, wherein the electrodes in the first electrode structure constitute the columns of the electrode matrix or the x electrodes and the electrodes in the second electrode structure the rows of the electrode matrix or y electrodes, wherein a portion of the ferroelectric thin film at the overlap between an x electrode and a y electrode of the electrode matrix forms a logic element such that the logic elements jointly form an electrically connected passive matrix in the data-processing device.
The present invention also concerns a method for manufacturing the ferroelectric data-processing device, as well as a method for readout in the addressing of logic elements in a ferroelectric data-processing device, particularly a ferroelectric data-processing device according to claims 1-9, wherein the method supports a protocol for readout and comprises steps for respectively reading, verification and reset. Finally the invention concerns the use of a ferroelectric data-processing device according to the invention.
Generally the invention concerns data-processing devices with logic elements implemented in a ferroelectric material. The phenomena of ferroelectricity is in this connection supposed known by persons skilled in the art, as the field is comprehensively treated in the literature, for instance in J. M. Herbert, Ferroelectric Transducers and Sensors, Gordon and Breach, 1982, wherein in pp. 126-130 there is proposed using a ferroelectric memory based on single crystals of barium titanate provided between orthogonal electrodes in an x,y electrode matrix. The author concludes that there are substantial practical difficulties connected with the use of ferroelectric single crystals for information storage in this simple manner. In regard of recent survey literature, reference may be made to R. G. Kepler and R. A. Anderson, Advances in Physics, Vol. 41, No. 1, pp. 1-57 (1992).
To illustrate the development of ferroelectric memories in a historical context, reference may be made to a paper by W. J. Merz and J. R. Anderson titled xe2x80x9cFerroelectric Storage Devicesxe2x80x9d, which was published in September 1955 (Bell Lab. Records, 1:335-342 (1955)) which discloses the use of inorganic ferroelectric crystalline materials, particularly barium titanate in, in memory and switching devices. Particularly they suggest a ferroelectric memory device based on this material, the latter being provided as a planar 50-100 xcexcm thick slab between overlapping sets of parallel electrodes, one set of the electrodes being orthogonal to the electrodes of the other and thus providing ferroelectric memory cells in portions of the ferroelectric material between the overlapping electrodes. Thus they disclose a ferroelectric device with a passive electrode matrix for addressing (see FIG. 10 of their paper), anticipating the general layout of all later ferroelectric memory devices with matrix-based addressing. They even hint at the use of transistors for switching, but forming an active memory cell with a switching transistor and with sufficiently small dimension would hardly be practical before the advent of say integrated field effect transistors.
As mentioned above, the data-processing medium is a ferroelectric material in the form of thin film. Such ferroelectric thin films which either may be inorganic, ceramic materials, polymers or liquid crystals have been known for some time and it may in this connection be referred to the above-mentioned article by Kepler and Anderson. There are for instance from J. F. Scott, Ferroelectric memories, Physics World, February 1995, pp. 46-50, known data storage devices based on ferroelectric memory materials. They all have in common that at least one transistor is necessary in each bit location or memory cell. In the most common embodiments the ferroelectric material is used as a dielectric in the associated memory circuit and comprises a bit-storing capacitor. Due to the high dielectric constant of ferroelectric materials, the capacitor may be made much smaller than otherwise possible and will additionally provide a quite superior charge lifetime. Recently the development has focused on another property of ferroelectric materials, namely their ability to be polarized electrically when they briefly are subjected to a strong electric field. During the polarization process the dipoles of the ferroelectric material attain a preferred orientation, something which results in a macroscopic dipole moment which is retained after the removal of the polarizing field. By thus including the ferroelectric material in the gate electrode structure of a field effect transistor in the memory cell circuit, the transconductance characteristics of the transistors may be controlled by controlling the polarization state of the ferroelectric material. The latter may be switched, for instance by polarizing fields with a direction which either causes a transconductant state xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d in the transistor.
EP patent 0 721 189 discloses a ferroelectric memory with discrete memory cells provided in an electrode matrix. In addition to a discrete ferroelectric capacitor each memory cell also comprises switching means, preferably in the form of at least one transistor. The discrete memory cells hence do not form a passive matrix. With discrete memory cells it shall here be understood that the ferroelectric capacitor is formed by a discrete component, such that the ferroelectric material cannot form a continuous layer in the matrix. There are provided separate data and selection lines and the readout of a stored datum may take place in current or voltage mode on data lines provided for this purpose, but according to a relatively complicated protocol, such as disclosed by patent claim 6. It must also be remarked that the number of memory cells connected in a data signal line must be adjusted in order to accommodate parasitic capacitance on each data signal line during the readout, such that the voltage variation on one of the data signal lines is minimized.
U.S. Pat. No. 5,592,409 concerns a non-volatile ferroelectric memory wherein data may be read out without destruction. The memory cells are included in an active matrix and are formed as transistor structures therein, wherein the gate electrode forms one of the electrodes in a ferroelectric capacitor. It is evident that the ferroelectric capacitors are discrete components. The polarization of the capacitor takes place in a well-known manner, but by the readout which takes place in current mode it is the drain current that is detected, this in order to prevent the stored data from being erased.
Even if the use of ferroelectric materials as mentioned above represents substantial improvements relative to alternative technologies for storage of data, the basic architecture of ferroelectrically based memories is directed to the use of active microcircuits included in each memory cell. This has negative consequences for the achievable data storage density, i.e. the number of bits which may be stored on a given surface area, as well as for the cost of each bit stored, something which partly may be due to complicated manufacturing technology and the use of active semiconductive components.
Recently proposals have been made for a return to ferroelectric memory devices configured as a memory cell array in a passive electrode matrix. Thus U.S. Pat. No. 5,329,485 (U. Isono and al.) discloses a memory element and a matrix memory cell array including memory cells each having a non-linear conductivity bipolar switching element constituted by a multi-layered structure which performs writing/reading operations of a polarization state on a ferroelectric body which forms a recording medium of the memory cell. The switching element is in the form of an insulating film which acts as a switching element to accumulate charges in a charge accumulating ferroelectric capacitor which constitutes the memory cell proper. The insulating film, which particularly may be a polyimid film, allows a direct tunnel current to flow when a voltage exceeding a predetermined value is applied to the insulating film. When the voltage is turned off, the film recovers its insulating property and retains the charges by preventing leakage thereof. According to Isono and al. the film shall have non-linear current voltage characteristics and provides a high write speed without a high operation voltage due to a large part of the drive current of the insulating film being a direct tunnel current. This also allow a high integration density of the memory cells, while the switching film forming a diode junction in the memory cell reduces crosstalk between the cells.
U.S. Pat. No. 5,375,085 discloses another example of a ferroelectric memory in the form of a ferroelectric integrated circuit realized with a passive electrode matrix with a ferroelectric layer provided between the electrode sets forming the substantially orthogonal matrix. As usual, the memory cell is formed in the portion of the ferroelectric layer between the overlapping electrode of each electrode set. By providing an insulating layer over the electrode matrix a second electrode matrix may be deposited on the top of the former and so on, thus forming a stacked structure realizing a volumetric three-dimensional ferroelectric integrated circuit with passive matrix addressing. This is, however, already known from the above-mentioned U.S. Pat. No. 5,329,485, see for instance column 14, 1. 31-36 thereof.
Additionally it could also be mentioned that passive matrix addressing is, of course, well-known in the case of ferroelectric liquid crystal elements as for instance used in liquid crystal displays. Reference may in this regard be made to e.g. U.S. Pat. No. 5,500,749 (Inaba and al.)
It has also been shown that ferroelectric polymer materials may be used in erasable optical memories. For instance there are disclosed devices for ultrafast non-volatile information storage with ferroelectric polymers as the active storage elements (IBM Technical Disclosure Bulletin 37:421-424 (no. 11, (1994)). Preferred embodiments utilize poly(vinylidene fluoride) (PVDF) or PVDF-trifluoroethylene (PVDF-TrFE) copolymers as the ferroelectric material since these polymers can be obtained as very thin films and can have response times of better than 350 picoseconds. The ferroelectric polymers can be used in the gate of a standard dynamic or static RAM device. The most basic information storage device suggested consists of a ferroelectric thin film with a set of parallel conducting electrodes deposited on one side and an orthogonal set of conducting electrodes deposited on the other side. The individual storage cells are formed at the junctures of the opposing electrodes. A stack of two-dimensional passive arrays of this kind can be fabricated by alternately depositing conducting strips and ferroelectric material to build up a three-dimensional array of ferroelectric capacitors which easily could be stacked vertically on an integrated circuit with addressing logic sense amplifiers and thus providing a volumetric or three-dimensional ferroelectric memory.
Further, M. Date and al. has in the paper xe2x80x9cOpto-ferroelectric Memories using Vinylidene Fluoride and Trifluoroethylene Copolymersxe2x80x9d, IEEE Trans. Electr. Ins., Vol. 24, No. 3, June 1989, pp. 537-540, proposed a data medium comprising a dye-doped vinylidene fluoride trifluoroethylene copolymer with a thickness of 2 xcexcm, spin deposited on a ITO coated glass plate. The information is written as sequences of positive and negative polarizations generated by irradiating with a focused laser beam with a diameter of about 5 xcexcm in the presence of sign controlling electric fields. The data is read out pyroelectrically by scanning with a laser beam. A carrier/noise ratio of 48 dB has been obtained by using a regularly repeating data train in the form or 0/1-state with a pitch of 20 xcexcm and with the use of a laser power of 12 mW and field strength of 25 MV/m. The reading speed was then 100 mm/s.
A disadvantage shared by all prior art ferroelectric memory devices is that the arrangement of the electrode matrix gives rise to serious fabrication problems when an organic ferroelectric memory medium is used in combination with inorganic, i.e. metallic, electrode strips and inorganic substrates, due to the need for processing the various materials in different thermal regions. Realized as thin film structures both organic materials as well as crystalline inorganic ferroelectric materials have turned out to be thermally incompatible with the temperatures required for processing the other materials of the device.
The object of the present invention is thus to provide a simple logic architecture which may be used for realizing either bistable switches or memory cells in a data-processing device or to provide a purely ferroelectric data storage device which offers the possibility of storing a very high number of bits in an area unit and which at the same time may be produced in simple manner in high volume with low cost, such that the above-mentioned disadvantages of the prior art thin film devices are avoided.
This object and other advantages are achieved according to the invention with a ferroelectric data-processing device which is characterized in that a layer of an electrical isolating material is provided between and adjacent to the electrodes of the first and the second electrode structure, that the ferroelectric thin film is provided in the form of a continuous or patterned layer over the electrode structures on one side thereof, and that the logic elements are formed respectively in a portion of the ferroelectric thin film along the side edges of an y electrode at the overlap between the x electrode and the y electrode; a method for manufacturing a ferroelectric data-processing device characterized by successive steps for depositing a first electrode structure on a substrate, depositing a layer of electrical isolating material over the first electrode structure, depositing a second electrode structure over the isolating layer, removing the isolating layer where it is not covered by the second electrode structure, such that the electrodes in the first electrode structure is exposed except in the overlapping intersections between the electrodes of respectively the first and the second electrode structure, and depositing a ferroelectric thin film in the form of a continuous or patterned layer over the electrode structures; and a method for readout characterized by applying in the reading step a voltage with a determined polarization to a logic element and detecting a charge transfer between the electrodes thereof as an either high or low first current value indicative of a logical value stored in the logic element, applying in the verification step a voltage of the opposite polarity to that of the voltage applied in the reading step and detecting a charge transfer between the electrodes of the logic element as a high second current value, and, in the case the logical value stored in the logic element was destroyed in the reading or the verification step, applying in the step for reset a voltage to the logic element restoring an initial polarization state thereof.
Advantageously, a logic element forms a bistabile switch in a data processor means or a memory cell in a data storage means.
According to a preferred embodiment of the invention the electrode structures and the ferroelectric thin film are provided on a substrate.
According to the invention the ferroelectric thin film is advantageously formed of a ceramic material or a ferroelectric liquid crystal material or a polymer, the polymer preferably being polyvinylidene fluoride, or a copolymer, the copolymer preferably being a vinylidene fluoride/trifluoroethylene copolymer.
In the method for manufacturing the ferroelectric data-processing device it is according to the invention advantageous that the substrate is formed of a crystalline, polycrystalline or amorphous semiconducting material, for instance silicon.
Advantageously, a continuous layer of an electrical isolating material is deposited between the substrate and the first electrode structure before depositing the first electrode structure on the substrate.
In a first embodiment of the method for readout reset is performed after reading without verification by applying a voltage of the opposite polarity to that of the reading voltage only in the case of detecting a high current signal in the reading step.
In a second embodiment of the method for readout reset is performed after reading in conjunction with verification by applying a voltage of the same polarity as that of the reading voltage only in the case of detecting a low current signal in the reading step.
In the method for readout according to the invention it is particularly preferred applying a voltage which between the electrodes of the logic element generates a field strength which is more than twice the coercivity field of the ferroelectric material. Advantageously, the applied voltage is generated as a ramp voltage or a threshold voltage in the reading and/or verification steps. According to the invention it is preferred that the current detection in the reading step takes place either by sampling in the time domain or in a time window dependent on the saturation time constant of the polarization. Advantageously the current detection, particularly in the latter case, takes place by a level comparison.


The invention provides branched trialkylamine oxides with improved properties. The trialkylamine oxides of the invention produced from branched trialkylamines, in one embodiment, can be made using certain branched C10-12 enals and aldehydes. The invention also provides an trialkylamine oxide having the formula:

There is a commercial need for novel surfactants with desirable properties such as low foaming, effective oily soil removal, performance in cold water, compatibility with other ingredients in a cleaning formula, mildness to skin, and a favorable environmental and safety profile.
A common trialkylamine hydrophobe used to make surfactants is dimethyl alkyl amine, made from C12 and C14 fatty alcohols reacted with dimethylamine, sometimes referred to as dimethyl laurylamine, or DIMLA. Neither DIMLA, its trialkylamine intermediate or the surfactants made from it contain branching.
Certain petrochemical detergent alcohols can also be used as surfactant hydrophobes. The most common synthetic detergent alcohols are produced by ethylene oligomerization, for instance, according to the Shell Higher Olefin Process (SHOP) process or the Ziegler alcohol process. Olefins can also be obtained from a Fischer-Tropsch process out of synthesis gas. The processing of producing detergent alcohols adds considerably to energy and facilities usage and consequently to product cost. Also, the resulting hydrophobes are typically over 85% linear.
Certain mixtures of C14 branched hydrophobes have also been described with some of the hydrophobe mixture containing a single branch point. When mixtures of hydrophobes are used to make surfactants, the individual hydrophobes in the mixture are not known to perform as well as the mixtures.
There remains a need in the industry for novel compositions which can be used to produce novel surfactants with desirable properties, for example, low foaming, mildness to skin, effective oily soil and/or stain removal (especially in cold water), high solubility in water, no gelling, ease of formulation, compatibilization or stabilization of other ingredients in a formula, retention of good hydrophobicity compared to linear hydrophobes, tolerance of extreme pH, and/or a favorable environmental and safety profile. There also remains a need in the industry for effective reactants and processes to make branched surfactants and corresponding surfactant intermediates with fewer reaction byproducts, fewer reaction steps, and/or reduced reaction solvent(s).

Abstract: wherein R5, R6 and R7 are independently at least one of C3H7, C2H5, CH3, or H, or mixtures thereof; and wherein R5 and R6 are not H at the same time. In one embodiment, the trialkylamine oxides of the invention can be useful in making various products, for example, as surfactants.


Described herein are compositions (e.g., a pharmaceutical composition) and compounds of formula I, and their use in the treatment and/or prevention of diseases and disorders.

Antiviral activities in saturated alcohols were identified 30 years ago. Activities have been observed for C10-C12 alcohols including cytotoxic and hemolytic effects. In addition, antiviral activity has been observed for C20-C26 alcohols (See e.g., U.S. Pat. No. 4,874,794; International Publication No. WO 03/032915; U.S. Publication No. US2004/0033982; and EP Patent No. 1557167. An example of one of the antiviral alcohols is 1-docosanol, the active ingredient in the FDA-approved OTC treatment for cold sores, Abreva®.
Cold sores (i.e., recurrent herpes simplex labialis (HSL)) are recurrent infections caused by herpes simplex virus 1 (HSV-1). 1-Docosanol (behenyl alcohol) is a C22 primary alcohol that inhibits HSV replication in tissue culture. It blocks one or more steps of viral entry, perhaps predominantly interfering with viral fusion with the host cell. The spectrum of antiviral activity of docosanol is not limited to HSV-1, and includes HSV-2, VZV, HCMV, HIV-1, respiratory syncytial virus, and influenza A. The mechanism of antiviral action in this class of compounds has not yet been fully delineated.
Antiviral activity has also been documented for certain fatty alcohol esters of hydroxycarboxylic acids (See e.g., U.S. Publication No. US2006/0229364 (2006)). Accordingly, topical antiviral activity can be expected by the application of a C7-C14 saturated fatty alcohol ester of a C2-C8 hydroxycarboxylic acid, e.g., lauryl (C12) lactate or myristyl (C14) lactate, either alone or in combination with another antiviral component.


A control assembly configured for a narrow stile door and for interaction with an exit device. The control assembly provides a means to translate user input, such as rotating a lever to operate a centercase. The control includes a slider for sliding movement within a housing between a first position extending a latchbolt of the exit device and a second position withdrawing the latchbolt. The control assembly configuration incorporates a swivel locking latch rotatable into the path of the slider to prevent the slider from moving out of the first position.

This invention relates generally to a control, such as a door latch assembly, for activation of centercase assemblies for exit devices and more particularly to a control assembly to activate narrow stile panic-type exit devices.
Narrow stile doors present difficulties in the installation and design of controls for exit devices. Stile is a term commonly used to refer to a vertical member of a door frame. Due to the thin width of a narrow stile door (1¾″), many of the commonly available controls to operate exit devices cannot be installed without the control overlapping the glass portion of the door. This overlap is found to be aesthetically undesirable. To avoid overlap, many exit device controls are known which are specifically designed narrow enough to fit upon a narrow stile. However, in order to activate the many diverse functions available in exit devices (rim, surface vertical, concealed vertical) unique controls are often required for each of the different functions.
Many exit device controls also only allow uni-directional input by the user to activate the control. One solution is to centrally locate a uni-directional output of the control such that it matches a centrally located uni-directional input for unlatching of a universal centercase assembly. Bi-directional mechanical activation of the control by the user is desirable over uni-directional activation. This allows the control to be activated in both down and upstroke of its activating lever, knob, etc. Thus the control must convert bi-directional activation input to uni-directional output to match the device.
When unlocked, a control is used to unlatch the exit device latching mechanism. Two types of locking and unlocking controls are what are commonly known as ANSI function 08 and ANSI function 09. ANSI function 09 allows the user to enter a key into the controls key cylinder (often what is commonly known as a mortise type) and turn the key not more than approximately 359 degrees to unlock the control. The key is not removable unless the control is locked. ANSI function 08 allows the user to enter the key into the controls key cylinder and turn the key 360 degrees to unlock the cylinder. If the key is then removed without further rotation of the key, the control remains unlocked. Relocking is the reverse of unlocking. Further, a means of electrically unlocking and locking the control is often desirable when the application is used in an electrically controlled security system. Accordingly, the manufacturer, distributors, and end user must often deal with a large number of parts, assemblies, and stocking units to provide a control to match for each unique device function, handing, and desired unlocking application.
It is apparent then that a control that is narrow enough to fit on a narrow stile, has a universal output location to match a corresponding universal input location on an exit device, provides bi-directional input, is reconfigurable to both left hand and right hand doors, provides for both ANSI 08 and ANSI 09 function in the same assembly, and is configurable for electrical unlocking, is desirable. It is the object of this invention to address the matter and set forth a narrow stile control that accomplishes these functions.


A compact combined position locating and analog cellular telephone unit. A single processor is coupled to a position locating system and a cellular telephone system. In the present invention, the single processor controls the functions and operation of both the position locating system and the cellular telephone system. In one embodiment, the position locating system, the cellular telephone system and the single processor are all disposed on a single substrate.

Portable global positioning system (GPS) devices, such as the Scout by Trimble Navigation, Ltd. of Sunnyvale, Calif. and hand-held cellular telephone devices, such as the Micro Tac flip-phones by Motorola, Inc. of Schaumberg, Illinois are well known in the prior art. Combined position locating and cellular telephone devices are also known in the art. The combined position locating system and cellular telephone devices commonly operate in different regimes and function independently of each other. An example of a prior art combined position locating and cellular telephone device is shown, for example, in U.S. Pat. No. 5,043,736 to Darnell et al. The position locating portion of Darnell's device includes an antenna, an RF "L" band receiver, a position locating demodulator, a dedicated microprocessor, and RAM. The cellular telephone portion of the L band signals received at the antenna are for a global positioning system, and a cellular phone system. Prior art combined position locating and cellular telephone devices typically include a complete position locating system including a dedicated position locating microprocessor. The complete position locating system and dedicated position locating microprocessor occupy at least one printed circuit board. Prior art combined position locating and cellular telephone device further includes a complete cellular telephone system and a dedicated cellphone microprocessor for controlling cellular telephone functions. The cellular telephone system and dedicated cellphone microprocessor also occupy at least one other printed circuit board. Therefore, prior art combined position locating and cellular telephone devices have at least two microprocessor units and occupy at least two printed circuit boards or other similar substrates. Thus, prior art combined position locating and cellular telephone devices are much bulkier and are more complex than conventional stand-alone position locating or standalone cellular telephone systems.
As an additional disadvantage, prior art combined position locating and cellular telephone devices suffer from significant drawbacks. That is, prior art combined position locating and cellular telephone devices are more expensive, and are more complex than conventional stand-alone position locating or cellular telephone systems. The additional bulk, cost, and complexity associated with such devices may not appeal to a consumer.
Thus, the need has arisen for a position locating and cellular telephone combination which does not have the additional bulk, cost, and complexity associated with prior art combined position locating and cellular telephone devices.

Combined position locating and cellular telephone system with a single shared microprocessor


Disclosed are various embodiments for designing a network site. A grid layout component is provided in conjunction with a network page. The network page has at least one text element and at least one image element. The grid layout component has a plurality of cell configurations. Each cell configuration includes at least one text cell and at least one image cell. An indication is received from a user, indicating that one of the cell configurations is to be an initial cell configuration. In response to the user indication, the at least one text element and the at least one image element are displayed in a grid having the initial cell configuration. Layout code is generated which renders the grid, including the at least one text element and the at least one image element, within the network page for display by the browser.

A network site including network pages may be hosted by a hosting provider. A site administrator for the network site may design the network pages to include text and images, arranged in various ways on the page. The site administrator may further link the network pages in a hierarchical manner so that a user sees the network pages as a single network site.

Grid layout control for network site design


A method of transmitting a channel quality indicator (CQI) includes obtaining CQIs for each of a plurality of sub-bands, a sub-band comprising a plurality of sub-carriers, dividing the plurality of sub-bands into a plurality of layers according to a CQI of a sub-band, a layer comprising at least one sub-band, obtaining a representative value of a representative layer, the representative layer including a sub-band having maximum CQI and transmitting the representative value of the representative layer. Signaling overhead due to CQI feedback can be reduced.

In order to transmit a high-quality and high-capacity of data using limited radio resources in a wireless communication system, a variety of transmission methods have been developed and employed.
Closed-loop system provides a feedback channel from a user equipment to a base station. In the closed-loop system, when a user equipment provides channel information to a base station, the base station adjusts several system parameters, such as a power level and a transmission format, based on the channel information in order to maximize the performance. For example, an Adaptive Modulation and Coding (AMC) scheme is a method for increasing link performance by adjusting a modulation and coding scheme (MCS) based on the channel information. When channel state is good, the data rate is increased. On the contrary, when the channel state is not good, the data rate is lowered.
An example of channel information is a channel quality indicator (CQI). In general, the CQI is measured by a user equipment and feedback through an uplink control channel. The base station can assign appropriate resources to each user equipment based on the CQI.
For example, it is assumed that 5 bits (25=32 level) are used for CQI transmission.
CQI values between −10 dB and 22 dB can be quantized and represented every 1 dB distance. Or, CQI can be represented by one of 32 MCS levels. The 5 bits of CQI are channel-coded and then transmitted. If CQI is missed or distorted during transmission, AMC scheme can be much degraded. Accordingly, CQI needs to have high code rate to guarantee reliable transmission. But high code rate requires lots of radio resources.
In particular, in a multi-carrier system based on Orthogonal Frequency Division Multiplexing (OFDM), CQI may differ per on frequency (sub-carrier) basis. To acquire perfect channel information, it is needed that CQIs for every sub-carrier are measured and reported. But this may cause signaling overhead and low data rate.
Accordingly, there is a need for a method of efficiently transmitting CQI.

Method of transmitting channel quality indicator in wireless comunication system


The invention comprises a gallium arsenide driver with float capability for logic high and logic low signals including logic means for receiving an input signal and providing logic high and low signals therefrom. Level shift means responsive to the high and low signals downshift the voltage levels thereof. Common gate means responsive to the downshifted signal voltage levels amplify these signals, and output source-follower means responsive to the amplified signals provide output signals to a pad.

1. Field of the Invention
The invention relates to a GaAs driver employing MESFETS, diodes, and optionally saturated resistors.
2. Description of the Prior Art
The closest prior art known is S. A. Ransom et al U.S. Pat. No. 4,410,815, entitled Gallium Arsenide To Emitter Coupled Logic Level Converter, issued Oct. 18, 1983. It discloses an alternate approach to achieving the function of a GaAs driver capable of signal level shifting and amplification. It depends upon differential amplification and correspondingly necessary circuits rather than the application of a predetermined reference voltage to the gate of a common gate amplifier.
The present invention may uniquely employ saturated resistors and also operate at much lower voltages with all attendant advantages, and is not limited to driving ECL circuits or GaAs circuits; but, with V.sub.BB increased, it will also drive TTL circuits.


An electronic tongue strike mechanism which can be mounted in a door frame is disclosed. The electronic tongue strike mechanism has a main mounting bracket which is mountable to a door frame, a tension plate which is mounted to the main mounting bracket a tongue strike mounted on the tension plate for engaging a door bolt and a pressure sensor mounted on the tension plate to sense relative movement between the tension plate and the main mounting bracket caused by the door bolt being urged against the tongue strike. The pressure sensor feeds electronics which operate to control release of the tongue strike.

Numerous latching mechanisms have been developed for retaining and/or opening doors. Some of these mechanisms consist of a matched set of hardware for mounting both on the door and the door frame such that the latching device is actuated by an electric solenoid which retracts a latching mechanism on the frame or actuates a mechanism that releases a latching member from engagement with its mating structure mounted on the door. The solenoid may be activated from a remote location to release or lock the door allowing control over door locking and releasing. These mechanisms are typically designed with the door and doorframe and sold as an assembly.
An electric strike assembly is shown in U.S. Pat. No. 5,076,625 in which a door mechanism having a deadlocking-type latch is disclosed. The latch consists of a forked tongue mounted on a pivot shaft so that it may pivot about the axis of the shaft only when released by movement of a rod. The rod in turn is actuated by a manual release bar or by a keeper to rotate slightly counter-clockwise bringing the outer edge of the nub horizontally and thereby release the forked tongue. A spring biases the tongue so that the keeper is returned to its last position only when the door is closed, striking the stop, and rotating the tongue against the force of the biasing spring. The strike is adapted to provide an electric release for doors equipped with a companion forked tongue mechanism.
Another electrically operated securing plate for door locks, mounted inside a door frame, is shown in U.S. Pat. No. 5,195,792. That patent teaches a mechanism having a securing plate and a ratchet means cooperating with the securing plate to retain the securing plate in a locked position. The securing plate pivots about the spindle and is arranged to be moved between an open and closed position by the bolt and to remain in one or the other of these positions. A cam and pin also act as an indicator designed to cooperate with the securing plate in sensing the position of the bolt in relation to a limit breaker or the like when the securing plate is in a closed position. The securing plate is so arranged that by pressing against a side wall of the plate recess during a closing movement, the bolt will force the securing plate from the open door position to the closed door position. It is also arranged so that by pressing against a side wall of the plate recess during an opening movement, the bolt will force the securing plate from the closed door position to the open door position.
While these mechanisms and others within the state-of-the-art provide a securely locked door, they generally require activation of a high voltage high current solenoid by an electric signal to release the door lock. The strike plates and latching mechanisms are specifically designed to bind or otherwise lock when the door is urged and the latching mechanism is in a locked position. In many circumstances, if the door is urged at the same time that the electrical signal is sent to the solenoid for release, binding occurs against the latching mechanism thus preventing it from releasing. Also, the electrical signal that activates the solenoid generally comes from key entry, card swipe or manual handheld button actuating devices thus requiring several actions to open the door. Additionally prior art indicates that present electric strike mechanisms are mounted inside the door frame using high current high voltage solenoids eliminating marketing to the average homeowner handyman. What is needed is a simple door opening mechanism that may be operated in an automated fashion such that binding of the latching mechanism during release is prevented.


Disclosed is an automated system which collates (i.e. counts and assembles packages into stacks) and positions the stacks on a cartoner conveyor. The system includes an abort plate movable between a first position and a second position for supporting a stack of packages when in the first position and permitting packages to fall past the first position when in the second position; a pusher plate movable between a first package supporting position and a second position permitting packages to fall onto the abort plate when the abort plate is in the first position and further adapted to push the stack off the abort plate when the pusher plate is moved from the second to first position; and a gate movable between a first package separating position and a second position for permitting the packages to fall onto the pusher plate.

1. Field of the Invention
The present invention relates to a system for handling packages. In particular, the present invention relates to an automated system for collating or assembling packages into stacks and for positioning the stacks on a conveyor.
2. Description of the Related Art
A known package forming and handling system 10 is illustrated in FIGS. 1 and 2. The system 10 includes a tablet press (not illustrated) for forming tablets 12 and a packaging system 14 for sealing the tablets 12 within packages 15.
The packaging system 14 drops the packages 15 onto a conveyor 16. The conveyor 16 is normally operated at low speed. But when a predetermined number of packages 15 have fallen onto the conveyor 16, the conveyor 16 is operated at a relatively high speed for a predetermined, short period of time. This produces separate, "shingled" stacks 18.
At the end of the conveyor 16, the packages 15 are scooped up by human loaders 20, counted and manually loaded onto a cartoner conveyor 22.
The system 10 is generally not sufficiently efficient, reliable and accurate. For example, the conveyor 16 may not maintain the packages within the stacks 18 as desired. As the stacks 18 are conveyed toward the cartoner conveyor 22, the stacks 18 tend to become disoriented and the packages 15 tend to commingle with each other. This makes it difficult to accurately and quickly load the packages 15 onto the cartoner conveyor 22.
Moreover, new systems have been developed for forming and packaging the tablets 12. These new systems are capable of producing packages 15 at a very high speed. The intermittent shingling conveyor 16 is too slow to be used with the new systems.


A method and system for extracting a silhouette of a 3D mesh representing an anatomical structure is disclosed. The 3D mesh is projected to two dimensions. Silhouette candidate edges are generated in the projected mesh by pruning edges and mesh points based on topology analysis of the projected mesh. Each silhouette candidate edge that intersects with another edge in the projected mesh is split into two silhouette candidate edges. The silhouette is extracted using an edge following process on the silhouette candidate edges.

The present invention relates to medical imaging, and more particularly, to automatic extraction of a silhouette of a 3D mesh represented anatomical structure segmented in a 3D image volume. Aortic valve disease affects a large number of people globally and is the most common type of valvular disease in developed countries. Implantation of a prosthetic aortic valve is often necessary to replace a severely damaged native valve. Although open-chest valve surgery is a well established procedure, minimally invasive transcatheter aortic valve implantation (TAVI) is an emerging technique, especially for high-risk patients, to minimize the surgical trauma. Interventional surgeries, such as TAVI, are typically performed under the guidance of real time fluoroscopic (x-ray) images. Many anatomical structures are not visible on these 2D x-ray images when no contrast agent is applied. Overlay with a 3D anatomical model extracted from other imaging modalities, such as computed tomography (CT), C-arm CT, or magnetic resonance imaging (MRI), can provide valuable visual guidance. Such a 3D anatomical model is often represented as a surface mesh. However, overlay with a solid mask of the anatomical structure generated from the surface mesh can be too intrusive and valuable information can be blocked by the mask.

Method and system for efficient extraction of a silhouette of a 3D mesh


Provided are an information processing apparatus and a method, and in particular, an information processing apparatus and a method for employing a 3D model generated using 3D-CAD.

1. Field of the Invention
The present invention relates to an information processing apparatus and a method therefor, and in particular to an information processing apparatus for using a 3D model (computer aided geometry model in 3D) generated by using 3D-CAD, and a method therefor.
2. Related Background Art
Conventionally, a CAD apparatus (especially, a 3D-CAD apparatus) is employed to design objects (hereinafter simply referred to as parts) having a three-dimensional shape, such as parts for goods or products. Further, based on this design, metal molds for manufacturing parts are generated.
Before using the design information prepared by the CAD apparatus, attribution information, such as dimensions, dimensional tolerances, geometric tolerances, annotations and symbols, are entered for a 3D model (3D geometry).
In order to enter this attribution information for the 3D model, planes, ridge lines, center lines and vertexes of the 3D model are selected. For example, attribution information shown in FIG. 26 is entered for a 3D model shown in FIG. 24 (the front view, the plan view and the side view of this 3D model are shown in FIG. 25). The attribution information includes:                distances (lengths, widths and thicknesses), angles, hole diameters, radii, chamfering dimensions, and dimensional tolerances accompanied by dimensions;        geometric tolerances and dimensional tolerances to be added to planes and ridge lines, without dimensions being entered;        annotations to be transmitted or instructed for machining or manufacturing parts, units and products; and        symbols that are determined in advance as a premise for representing, for example, surface roughness.
For adding attribution information to a 3D model, roughly two methods, as follow, are employed.    (1) Method for adding dimensions, dimensional tolerances, geometric tolerances, annotations and symbols            Dimension lines and projection lines are required for the entry of dimensions and dimensional tolerances.        Leader lines are required for the entry of geometric tolerances, annotations and symbols.            (2) Method for adding dimensional tolerances, geometric tolerances, annotations and symbols without dimensions being provided.            Dimension lines and projection lines are not required.        Leader lines are required for the entry of dimensional tolerances, geometric tolerances, annotations and symbols.
Further, a metal mold is produced by using a 3D model. In this case, an examination must be performed to determine whether a metal mold and a product for which the metal mold is used are obtained as designed.
The following problem has arisen with the conventional method for adding attribution information to the 3D model.
In case (1) described above, a dimension and a dimensional tolerance, and a dimension line and a projection line used to enter the dimension and the dimensional tolerance, become complicated, and it is difficult to see the geometry of a 3D model and the attribution information.
If, as is shown in FIG. 24, the 3D model has a comparatively simple shape and there are only several tens of attribution information sets, they can somehow be identified. However, since several hundreds or thousands, as needed, of attribution information sets are provided for a 3D model having a complicated or large shape, the reading of attribution information is extremely difficult because "attribution information sets are overlapped", "attribution information is overlapped with the dimension line, the projection line or the leader line", or "the position of the dimension line, the projection line or the leader line is not easily apprehended". It is rather difficult to see even the step-shaped corner shown in FIG. 26.
In the above case, since it is difficult for an operator to see attribution information that is input, the operator can not confirm the contents of input information, i.e., the input of attribution information becomes difficult.
In addition, the reading of associated attribution information is also extremely difficult. Further, since the space occupied by attribution information is increased for a 3D model, the geometry of the 3D model and the attribution information can not be seen at the same time on a display screen having a limited size.
Furthermore, for the attribution information (e.g., the depth of a 12±0.1 counter bore in FIG. 24) that is to be designated in the cross-sectional view, for example, the location whereat the attribution information is provided for the 3D model does not appear and is hard to be understood.
In case (2), since the leader line is employed while the dimension line and the projection line are not required, as in case (1), the leader lines are complicated and it is difficult to see the geometry of the 3D model and the attribution information. Further, since several hundreds to several thousands, as needed, of attribution information sets are provided for a 3D model having a complicated or large shape, the reading of attribution information is extremely difficult.
In addition, the measurement of dimensions is required in the process for examining a manufactured metal mold and a product obtained using the metal mold. Therefore, the operation using the measurement function for 3D geometry is required in order to read the dimensional values.
In this case, a portion that is used as a reference dimension must be selected to read a desired plane or ridge line. In order to read the dimensions of a plurality of portions, many operations and a long processing time are required. Further, erroneous readings due to mistakes can not be avoided. Furthermore, an extremely large amount of labor is required to read the dimensions of all the portions.
Originally, a 3D model and attribution information are data for the machining or manufacture of parts, units and products, and must be transmitted efficiently and accurately by a data input operator, i.e., a designer, to a recipient operator, i.e., a machining, production or inspection engineer, so that the data can be easily understood. The conventional technique does not satisfy these requests, and is not industrially effective.
It is, therefore, one object of the present invention to add attribution information to 3D data generated by a CAD apparatus, so that the information can be transmitted efficiently and accurately and can therefore be easily understood. It is another object of the invention to add attributions to data to improve the operation.
It is an additional object of the invention to efficiently employ an attribution that is added.
It is a further objective of the invention to efficiently produce parts by utilizing data created by a CAD apparatus.
It is a still further object of the present invention to efficiently perform an inspection process by using data created by a CAD apparatus.

Information processing apparatus and information processing method

Abstract: When attribution information (a distance, an angle, the diameter of a hole, a dimensional tolerance, etc.) is added to a 3D model, as the amount of additional information is increased, it becomes difficult for the geometry of a 3D model and the attribution information to be seen on a display screen.

Abstract: The visual direction (the attribution allocation plane) is set for a generated 3D model, and attribution information is entered that is to be positioned on an attribution allocation plane. By designating the attribution allocation plane, the designated attribution information, together with the geometry of the 3D model, is displayed on the screen.


The present invention provides a method for receiving a paging message of an idle-mode terminal in a multi-carrier system, comprising the steps of: receiving, from a network, a paging message through a first carrier corresponding to a predetermined condition in a paging listening interval; transmitting, to the network, a first ranging request message that includes control information indicative of a location updating procedure for notifying a start of E-MBS service reception; determining, as a paging carrier, a second carrier from which an E-MBS service is transmitted; and receiving the paging message from the network through the determined second carrier.

16m E-MBS (Enhanced Multicast and Broadcast Service)
An E-MBS provides an efficient method for simultaneous transmission of common downlink data to a group of users who use a common multicast STID (MSTID) and FID. The E-MBS service is only provided in downlink and coordination or synchronization is performed between base stations belonging to one group in order to allow macro diversity.
E-MBS is associated with a service flow provided along with quality of service (QOS) and traffic parameters for the service flow. Service flows for transmitting E-MSB data are accounted for to an individual terminal participating in the service while the terminal performs a general operation. During accounting, the terminal conforms the service and learns parameters associated with the service flow.
Each base station which may provide an E-MBS service belongs to a specific E-MBS zone and one base station may belong to a plurality of E-MBS zones. The E-MBS zone is defined as one set of base stations using the same MSTID and FID in order to transmit content of a specific service flow. Each E-MBS zone is identified by a unique E-MBS zone ID.
In order to guarantee an appropriate multicast operation over a network of a base station supporting an E-MBS, MSTIDs and FIDs used for a common E-MBS content and service should be the same to all base stations included in the same E-MBS zone.
This allows a terminal which has already registered with a specific service to seamlessly receive an E-MBS in an E-MBS zone, without reregistering with another base station included in the E-MBS zone and performing uplink communication.
Hereinafter, a carrier will be briefly described.
A user may perform a modulation operation with respect to the amplitude, frequency and/or phase of a sine wave and a periodic pulse wave. A sine wave or a pulse wave for carrying information is called a carrier.
Examples of a carrier modulation scheme include a Single-Carrier Modulation (SCM) scheme and a Multicarrier Modulation (MCM) scheme. Among others, the SCM scheme is to perform modulation with respect to all information carried on one carrier.
The MCM scheme refers to a technology of dividing an overall bandwidth channel of one carrier into several sub-channels each having a small bandwidth and transmitting a plurality of narrowband sub-carriers through the sub-channels.
At this time, when the MCM scheme is used, each of the sub-channels is approximated so as to have a flat channel due to the small bandwidth. A user can compensate for distortion of a channel using a simple equalizer. In addition, the MCM scheme is implemented at a high speed using Fast Fourier Transform (FFT) and is more advantageous in high-speed data transmission than the SCM scheme.
As capabilities of a base station and/or a terminal have been developed, a frequency bandwidth provided or used by the base station and/or the terminal has expanded. Accordingly, in the embodiments of the present invention, a multicarrier system supporting a wideband by aggregating one or more carriers is disclosed.
That is, in the following multi-carrier system, one or more carriers are aggregated and used, unlike the MCM scheme of dividing one carrier into sub-carriers and utilizing the sub-carriers.
In order to efficiently use multiband or multicarrier, a technique of managing several carriers (e.g., several frequency carriers (FCs)) by one medium access control (MAC) entity has been proposed.
FIGS. 1(a) and 1(b) are diagrams illustrating a method of transmitting or receiving a signal based on a multiband radio frequency (RF).
In FIG. 1, in a transmitter and a receiver, one MAC layer may manage several carriers in order to efficiently use multicarrier. In order to efficiently transmit or receive multicarrier, it is assumed that both the transmitter and the receiver can transmit or receive multicarrier. Since the frequency carriers (FCs) managed by one MAC layer do not need to be contiguous to each other, flexible resource management is possible. That is, both contiguous aggregation and non-contiguous aggregation are possible.
In FIGS. 1(a) and 1(b), a physical layer (PHY) 0, a physical layer 1, . . . , a physical layer n−2 and a physical layer n−1 represent multiple bands of the present technique and each band may have an FC size assigned for a specific service according to a predetermined frequency policy. For example, the physical layer 0 (RF carrier 0) may have a frequency band size assigned for a general FM radio broadcast and the physical layer 1 (RF carrier 1) may have a frequency band size assigned for mobile telephone communication.
The frequency bands may have different frequency band sizes according to frequency band characteristics. However, in the following description, for convenience of description, it is assumed that each FC has a size of A [MHz]. Each frequency allocation band is representative of a carrier frequency for utilizing a baseband signal in each frequency band. Hereinafter, each frequency allocation band is referred to as "carrier frequency band" or simply "carrier" representative of each carrier frequency band if such use will not lead to confusion.
Recently, as in the 3GPP LTE-A, the above carrier may be referred to as "component carrier" in order to be distinguished from a subcarrier used in an MCM scheme.
Therefore, the above "multiband" scheme may be referred to as a "multicarrier" scheme or a "carrier aggregation" scheme.
FIGS. 2(a) and 2(b) show an example of using multicarrier in a general wireless communication system.
Multicarrier of a general technique may be a contiguous carrier aggregation as shown in FIG. 2(a) or a non-contiguous carrier aggregation as shown in FIG. 2(b). A unit for aggregating carriers is a basic bandwidth unit of a legacy system (e.g., LTE in case of a long term evolution (LTE)-advanced system or IEEE 802.16e in case of an IEEE 802.16m system) which is a general technique.
In the multicarrier environment of the general technique, the following two types of carriers are defined.
First, a first carrier (or a primary carrier) refers to a carrier for exchanging full physical (PHY)/MAC control information and traffic of a terminal and a base station. In addition, the primary carrier may be used for a general operation of a UE, such as network entry. Each terminal has one primary carrier in one cell.
A second carrier (or a secondary carrier) refers to a supplemental carrier which may be used to exchange traffic according to a rule and a BS-specific allocation command received from the first carrier. The second carrier may include control signaling in order to support a multicarrier operation.
In the general technique, the carrier of the multicarrier system may be divided into a fully configured carrier and a partially configured carrier based on the primary and secondary carriers.
The fully configured carrier refers to a carrier in which control signaling is set. In addition, parameters and information on multicarrier management and other carriers may be included in the control channels.
The partially configured carrier refers to a carrier in which all control channels supporting downlink transmission is set in a downlink carrier which is not paired with an uplink carrier in a time division duplex downlink transmission (TDD DL transmission) or frequency division duplex (FDD) mode.
In general, a terminal performs initial network entry through a primary carrier and may exchange information about mutual multicarrier capabilities in a registration process through exchange of a registration request/response (AAI_REG-REQ/RSP) message with a base station.

Paging method and device for E-MBS terminal in multi-carrier system


An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor substrate with an nFET and a pFET. The semiconductor structure includes a gate dielectric layer on the interfacial layer and a pFET work function metal layer on a portion of the gate dielectric layer over an area above the pFET. The semiconductor structure includes a nFET work function metal layer on a portion of the gate dielectric layer over an area above the nFET and on the pFET work function metal layer in the area above the pFET. The semiconductor structure includes a gate electrode metal on the nFET work function metal layer where a plurality of fluorine atoms and a plurality of reducing gas atoms are incorporated into at least a portion of the interfacial layer, the gate layer, and a portion of the nFET work function metal.

The present invention relates generally to the field of semiconductor technology, and more particularly to semiconductor manufacture.
Semiconductor device scaling to smaller feature sizes is facing significant challenges. Traditional semiconductor materials and processes for device formation become less effective as physical dimensions shrink down to the nanometer regime. With this reduction in feature size, the thickness of gate dielectrics layers has continually decreased. As gate layers become thinner, a number of issues arise. Time-related voltage breakdowns, hot carrier effects, and diffusion of impurities from the gate electrode to the substrate may occur which can adversely affect the stability of transistors formed with thinner gate dielectric materials. The migration to high-k gate dielectric materials that improve gate current density for a similar effective oxide thickness may be done for improved electrical performing in shrinking devices particularly, in sub-micron regimes.
Negative bias temperature instability (NBTI) is a key reliability issue in metal-oxide semiconductor field-effect devices (MOSFET). NBTI is observed as an increase in the threshold voltage with an associated decrease in drain current and transconductance of semiconductor devices over time. NBTI occurs when a gate electrode is negatively biased at high temperatures, which may result in a drift in the electrical performance of a MOSFET device. NBTI is of particular concern in p-channel devices that operate at high temperatures with negative gate to source voltage. With the introduction of high k dielectrics and the use of metal gates, a similar mechanism, positive bias temperature instability (PBIT) may be observed with n-channel devices when a positive gate to source voltage is applied at high temperatures over time.

Forming a semiconductor structure for reduced negative bias temperature instability

International Business Machines Corporation


In order to provide a spot size converter and a method for making the same which enable the optical connection with low loss and are able to reduce the excess loss for the position misalignment in mounting, a spot size converter according to an exemplary aspect of the present invention includes: a substrate on which an optical waveguide including a first core is laminated and which includes a notch; a core reducing part which is formed so that a cross-section area of the first core may gradually decrease toward an end part of the first core in the direction of light propagation; a second core which surrounds the core reducing part and is made of a material whose refractive index is smaller than that of the first core; a peripheral clad which surrounds the second core and is made of a material whose refractive index is smaller than that of the second core; and a lower clad which is formed in a lower part of the second core and includes the peripheral clad; wherein the lower clad is formed in the notch.

As an optical circuit chip used generally, there is an optical circuit chip having a silica-based optical waveguide which uses silica-based material for both a core and a clad included in an optical waveguide. The relative refractive index difference of the core and the clad is as small as about 0.3% in the silica-based optical waveguide. Therefore, even if the waveguide size is large, single mode conditions are easily satisfied, and the mode field diameter is generally about 5 to 10 μm.
By the way, when an optical circuit chip is connected to another optical component, a form interposing an optical fiber is taken in many cases in order to expand the versatility. The mode field diameter of a commonly-used single mode optical fiber is approximately 9 to 10 μm in the wavelength region of 1.3 μm band and 1.55 μm band, which is close to the mode field diameter of the silica-based optical waveguide. Therefore, it is possible to obtain a low-loss optical coupling between the optical circuit chip having the silica-based optical waveguide and the single mode optical fiber.
On the one hand, in recent years, a research on an optical waveguide with a high refractive index difference is active in which the relative refractive index difference between the core and the clad is increased much larger than that of the silica-based optical waveguide by using, as the core, a high refractive index semiconductor such as silicon and gallium indium arsenide phosphorus. The bend radius of the high refractive index difference optical waveguide is generally equal to or shorter than 100 μm and is a few orders of magnitude less than that of the silica-based waveguide. Therefore, if the high refractive index difference optical waveguide is used, the size of the circuit chip becomes smaller dramatically, which enables significant high-density integration. In particular, in the optical circuit chip using an SOI (Silicon on Insulator) substrate having a silicon oxide film layer and a silicon layer on a substrate, it is possible to utilize a low refractive index silicon oxide film layer as a clad and the high refractive index silicon layer as a core. Therefore, it is possible to divert fine processing technologies and production facilities for silicon processes used for producing an LSI (Large Scale Integration) to the production of the optical circuit chip having the SOI substrate, and its commercialization is highly anticipated.
In the optical circuit chip including such high refractive index difference optical waveguide, it is a connection by means of an optical fiber that is used most widely as a connection method to another optical component. However, while the mode field diameter of a commonly-used single mode optical fiber is equal to 9 to 10 μm, each mode field diameter of most high refractive index difference optical waveguides is equal to several hundred nanometers. Therefore, if the optical fiber is directly connected to the optical circuit chip including the high refractive index difference optical waveguide, a large optical loss is generated because of the large difference between both mode field diameters. As a method for adjusting both mode field diameters to obtain a low-loss optical coupling, there is a method for providing a spot size converter to change a mode field diameter for at least one of an optical circuit chip and an optical fiber. In this case, the spot size converter to expand the mode field diameter is required for the optical circuit chip. On the other hand, the spot size converter to reduce the mode field diameter is required for the optical fiber.
A spot size converter provided for the optical fiber is commonly used in which the core size of the optical fiber gradually decreases toward a connection end to reduce the mode field diameter.
On the other hand, a spot size converter provided for the optical circuit chip is classified into the following two general types. The first type is a spot size converter in which the mode field diameter is expanded by gradually increasing the core size of the optical waveguide toward the connection end of the optical circuit chip. The second type is a spot size converter in which the core size of the optical waveguide is gradually decreased toward a connection end and the core is terminated short of the end face of the optical circuit chip, and the mode field diameter is expanded by transferring the optical energy to the second core formed around the core.
Above-mentioned first type of the spot size converter among the spot size converters provided for the optical circuit chip is described in non-patent literature 1, for example. In this case, by additionally forming a silicon layer about 10 μm thick on an SOI substrate and further processing the thick silicon layer complicatedly, the core size is expanded. Thus, when the core size is expanded, a high refractive index semiconductor to be a core must be formed thick. Therefore, there is a problem that a production cost becomes higher.
Above-mentioned second type of the spot size converter among the spot size converters provided for the optical circuit chip is described in non-patent literature 2, for example. FIG. 1 shows schematic views of a spot size converter 100 described in non-patent literature 2. FIG. 1A is a top view of the spot size converter 100. FIG. 1B is a cross-sectional view taken along the line of FIG. 1A. FIG. 1C is a right side view of FIG. 1A. Although a silicon core 103 and a core reducing part 104 which are shown by a dotted line in FIG. 1A are not actually exposed on an upper surface as shown in FIG. 1B, they are shown in order to make their locations understandable. Much the same is true on the core reducing part 104 shown by a dotted line in FIG. 1C.
In the spot size converter 100 shown in FIG. 1, 200 nm thick of the silicon core 103 on the SOI substrate is processed into a tapered shape. That is to say, the core width is reduced so as to become about 80 nm at the terminal of the silicon core 103 in the direction of the optical propagation. Here, a second core 105 with a cross-sectional surface of 3 μm height by 3 μm width is formed over the core reducing part 104 where the silicon core 103 is made a tapered shape. The second core 105 is made of a material whose refractive index is smaller than that of the silicon core 103 and larger than that of a buried oxide film layer 102, such as a silica-based material. In this case, the optical energy of the light propagating through the silicon core 103 is coupled with and transferred to the waveguide mode in the second core 105 while it is propagating through the core reducing part 104. And the optical energy coupled with the fundamental mode formed in the second core 105 is coupled with a single mode optical fiber.
It is possible to make the spot size converter 100 shown in FIG. 1 in a relatively simple way by means of diverting the manufacturing technology of a silica-based optical waveguide.
Non-patent literature 1: Assia Barkai et al., "Double-Stage Taper for Coupling Between SOI Waveguides and Single-Mode Fiber", JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 26, NO. 24, Dec. 15 and 2008, pp. 3860-3865
Non-patent literature 2: Tai Tsuchizawa et al., "Microphotonics Devices Based on Silicon Microfabrication Technology", IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 11, NO. 1, January/February 2005, pp. 232-240

Spot size converter and method for making the same