A method for providing a decorative cover for a floral grouping wherein the decorative cover is provided with card holder assembly for securing a card to the decorative cover, and a design indicia bearing portion which extends above the remainder of the decorative cover and thereby enhances the visual aesthetic effect of the decorative cover. The decorative cover is formed from a sheet of material having a design indicia, the sheet of material having an opening extending therethrough wherein the opening is offset from a central portion of the sheet of material in a direction generally away from the indicia bearing portion of the sheet of material. A lower portion of a stem end of a floral grouping is inserted through the opening in the sheet of material and the sheet of material is wrapped about the floral grouping to provide a decorative cover having a design indicia bearing portion which extends above the remainder of the decorative cover and thereby enhances the visual aesthetic effect of the decorative cover and a card is secured to the decorative cover.

Not applicable.
The present invention relates to a decorative cover for a floral grouping, and more particularly but not by way of limitation, to a decorative cover for a floral grouping and to a method for producing such decorative cover wherein the decorative cover includes design indicia to personalize or enhance the visual aesthetic effect of the decorative cover and a card holder assembly for securing a card to the decorative cover.
The present invention relates generally to a decorative cover for a floral grouping wherein the decorative cover has design indicia for enhancing the visual effect of the decorative cover and a card holder assembly for securing a card to the decorative cover. In one aspect, the decorative cover has an indicia bearing portion which extends a distance above the remainder of the decorative cover so as to enhance the visual aesthetic effect of decorative cover and a card holder assembly for securing a card to the decorative cover. In yet another aspect, the present invention relates to a method for producing a decorative cover for a floral grouping wherein the decorative cover is provided with a design indicia and a card holder assembly wherein the method for producing the decorative cover includes the steps of: (a) providing a sheet of material having a design indicia bearing portion, a card holder assembly and an opening in the sheet of material adapted to receive a lower portion of a stem end of a floral grouping, the opening being offset from a central portion of the sheet of material in a direction generally away from the indicia bearing portion of the sheet of material; (b) disposing a lower portion of a stem end of a floral grouping in the opening in the sheet of material; and (c) forming the sheet of material into a decorative cover about the floral grouping such that the indicia bearing portion of the decorative cover extends above the remainder of the decorative cover and thereby enhances the visual aesthetic effect of decorative cover and (d) securing a card to the card holder assembly.
An object of the present invention is to provide a decorative cover for a floral grouping wherein the decorative cover is provided with an indicia bearing portion for enhancing the visual aesthetic effect of the decorative cover and card holder assembly for securing a card to the decorative cover.
Another object of the present invention, while achieving the before stated object, is to provide a method of producing a decorative cover for a floral grouping wherein the decorative cover is provided with an indicia bearing portion for enhancing the visual aesthetic effect of the decorative cover and a card holder assembly for securing a card to the decorative cover.
Other objects, features and advantages of the present invention will be apparent to those skilled in the art from the-following detailed description when read in conjunction with the accompanying drawings and appended claims.

Method for providing a decorative cover for a floral grouping


Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

1. Field
The present invention relates to network communication, and, more particularly, to processing messages received via a network such as an Ethernet network.
2. Related Art
Local area networks (LANs), wide area networks (WANs) and other types of networks typically include a number of information processing systems coupled via connections operating according to various packet based communications protocols. For example, the Ethernet IEEE 802.3 protocol is a widely used LAN protocol based on the carrier-sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are sometimes referred to as Ethernet. 10/100 Ethernet provides increased Ethernet speed from 10 to 100 megabits per second (Mbps) and provides a simple, cost-effective option for backbone and server connectivity. Gigabit Ethernet is another Ethernet protocol which builds on top of the basic Ethernet protocol, but increases speed tenfold over 10/100 Ethernet to 1000 Mbps, or one gigabits per second (Gbps).
Devices in a network often receive messages which are intended for them and messages which are not intended for them. Thus, such devices must locally analyze each incoming message to determine if they should accept the message. Typically each device has an address which must be compared to an address in each received message in some form. An exact address match is computationally intensive because of address length and the large numbers of addresses to be compared. Because a device can accept messages for a number of other devices, and a very large number of messages may be received, and the speed of networks is increasing, the problem of processing (e.g., accepting or rejecting) incoming messages can cause a bottleneck at various devices in a network and slow down overall performance. Traditional destination address recognition methods require post filtering which is done at higher Open Systems Interconnection (OSI) levels than the media access control (MAC) level and require significant software and general processing hardware intervention. Some techniques employ content addressable memories (CAMs) but such techniques are typically expensive, excessively power consumptive, and inflexible. Thus, there is a need to enhance the performance of processing incoming messages.
In addition to merely accepting or rejecting incoming messages, each device typically has various tasks to perform responsive to receiving the messages. Accordingly, some data received by messages needs to be stored and accessed within a short amount of time. Thus, it would be advantageous to enhance the processing of such messages by preprocessing the received messages (e.g., by sorting inbound messages before they are examined by a processor or software driven system resources) to free the use of such resources for other tasks and to reduce the latency of accessing critical or high priority frames.

Network message processing using inverse pattern matching


The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.

1. Field of the Invention
This invention relates in general to an integrated circuit package, and more particularly, to an integrated circuit package having a substrate vent hole.
2. Description of Related Art
Integrated circuits are typically assembled into a package that is soldered to a printed circuit board. FIG. 1 illustrates a type of integrated circuit package that is commonly referred to as flip chip of C4 package. The integrated circuit 1 contains a number of solder bumps 2 that are soldered to a top surface of a substrate 3.
The package may include an underfill material 4 that is located between the integrated circuit 1 and the substrate 3. The underfill material 4 is typically an epoxy which strengthens the solder joint reliability and the thermo-mechanical moisture stability of the IC package.
The package may have hundreds of solder bumps 2 arranged in a two-dimensional array across the bottom of the integrated circuit 1. The epoxy 4 is typically applied to the solder bump interface by dispensing a single line of uncured epoxy material along one side of the integrated circuit. The epoxy then flows between the solder bumps. The epoxy then flows between the solder bumps. The epoxy must be dispensed in a manner that covers all of the solder bumps 2.
It is desirable to dispense the epoxy 4 at only one side of the integrated circuit to insure that air voids are not formed in the underfill. Air voids weaken the structural integrity of the integrated circuit/substrate interface. Such air voids are typically formed from trapped air or from gasses released during the underfill cure process. Moisture released during the underfill process may also be absorbed by the substrate, resulting in delamination and other reliability-related failures during the surface mount process. Moreover, the bumps may extrude into the voids during thermal loading, particularly for packages with a relatively high bump density.
Accordingly, there is a need in the technology for an apparatus and method for providing an integrated circuit package that avoids the aforementioned problems.
The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.

Integrated circuit package having a substrate vent hole


Systems, methods and devices for tensioning posterior crucial ligaments during cruciate or bi-cruciate ligament-sparing arthroplasty. Non-limiting examples of such systems may include at least one series of tibial inserts of equal size; the at least one series of tibial inserts having at least one set of tibial inserts of equal thickness. The at least one set of tibial inserts of equal thickness may include at least two tibial inserts having different geometries in a posterior portion, the different geometries being configured to change the tension in the posterior cruciate ligament (PCL). The different geometries in the posterior portions of the tibial inserts are configured so as to allow the posterior cruciate ligament to be tensioned or loosened independently of the tibial insert thickness and/or size. By providing different posterior geometries for each insert within a set of a series, a surgeon may be provided with more flexibility in choosing an insert that satisfies stability requirements in a non-invasive manner.

1. Related Fields
Artificial body members used in knee and other joint arthroplasty, and systems and methods using the same, for tensioning ligaments, tendons or other soft tissues.
2. Related Art
There are currently three total knee arthroplasty (TKA) cruciate ligament options available to surgeons. A first option is to sacrifice both the posterior cruciate ligament (PCL) and the anterior cruciate ligament (ACL). A second option is to retain the PCL and sacrifice the ACL. A third option is to preserve both cruciate ligaments. Generally, the first and second options are more common, because most patients having indications for total knee arthroplasty also typically have an ACL deficiency. For younger and more active patients with a healthy posterior cruciate ligament, it may be desirable in some instances to select the second or third option and retain at least the PCL. In doing so, stability may in some cases be achieved with the patient's own ligamentous soft tissue, instead of the implant.
Referring now to FIGS. 1, 2A, and 2B, there are typically two approaches to retaining the PCL during total knee arthroplasty. To this end, surgeons may resect the entire proximal portion of the affected tibia (10) as shown in FIG. 2A, or may resect most portions of the proximal tibia, leaving only a small area (12) of protruding bone and cartilage (13, 15, 17) at the posterior portion as shown in FIGS. 1 and 2B. Because the PCL (20) has an attachment point (16) that is slightly inferior to the resection plane (14), the PCL (20) usually stays attached to the tibia (10) regardless of which method is used. The benefits and disadvantages for each of the PCL-sparing resection techniques shown in FIGS. 2A and 2B have been widely debated. It has been suggested by those in the art that the function of the PCL changes with removal of the bone above the PCL attachment to the tibia.
Many surgeons find it difficult to leave a small area (12) of protruding bone and cartilage (13, 15, 17) at the posterior portion of a proximal tibia (10) due to the location of the PCL and surrounding bony structure. In fact, many surgeons prefer a total proximal resection (14) because it takes less practice and decreases operating time. In addition, it is generally very easy to notch the small area (12) of remaining bone or accidentally cut it off. Therefore, the approach of many surgeons is to resect the entire proximal tibia (10) in the first place as shown in FIG. 2A.
The problem associated with the PCL-sparing technique of resecting the entire proximal tibia as shown in FIG. 2A is that it may affect laxity, stiffness, tension, and other kinematic factors of the PCL (20). Essentially, by removing the small area (12) of protruding bone and cartilage (13, 15, 17), the tension (T) in the PCL may be reduced and forces associated with the PCL may be altered. Additionally, some of the edges of the PCL (20) may be inadvertently cut along the resection plane (14), thereby increasing elasticity of the PCL due to a smaller diameter. A loose PCL may affect anterior-posterior stability of the femur in relationship to the tibia (10) and may defeat the purpose of retaining the PCL in the first place.
Another problem associated with some PCL-sparing techniques involving resecting the entire proximal tibia occurs during trial reduction. Tibial inserts of the patient's size and having different thicknesses are typically placed between the femur and tibia until the best possible stability throughout a full range of motion is achieved. Unfortunately, an appropriately sized insert may over-stretch the PCL, or under-stretch the PCL, leaving the surgeon to make compromises. Often, if the PCL is over-stretched or placed in too much tension after an appropriate insert thickness is selected, invasive and difficult soft tissue and ligament releasing is performed. Alternatively, if the PCL is too loose, under-stretched, or insufficient for stability, a deep dish cruciate-retaining insert or a posterior stabilized implant may be used.

Systems and methods for tensioning ligaments and other soft tissues


A chip for nucleic acid analysis includes a body (2, 9), in which a detection chamber (7) is formed for accommodating nucleic acid probes (12, 12′). A waveguide (8) is integrated in the body (2, 9) is and is arranged at the bottom of the detection chamber (7) so that an evanescent wave (EW), produced at an interface (8a) of the waveguide (8) when a light radiation is conveyed within the waveguide (8), is irradiated towards the inside of the detection chamber (7). An apparatus for inspection of nucleic acid probes includes: a holder (22), on which a chip (1) for nucleic acid analysis is loaded, the chip containing nucleic acid probes (12, 12′); a light source (24) for supplying an excitation radiation to the nucleic acid probes (12, 12′); and an optical sensor (25) arranged so as to receive radiation coming from the nucleic acid probes (12, 12′).

As is known, the analysis of nucleic acids requires, according to different modalities, preliminary steps of preparation of a sample of biological material, of amplification of the nucleic material contained therein, and of hybridization of individual target or reference strands, corresponding to the sequences sought. Hybridization occurs (and the test yields a positive outcome) if the sample contains strands complementary to the target strands.
At the end of the preparatory steps, the sample must be examined to control whether hybridization has occurred (the so called detection step). For this purpose, various inspection methods and apparatuses are known, for example of an optical or electrical type. In particular, the methods and apparatuses of an optical type are frequently based upon the phenomenon of fluorescence. The reactions of amplification and hybridization are conducted so that the hybridized strands, contained in a detection chamber made in a support, include fluorescent molecules or fluorofors (the hybridized strands may be either grafted to the bottom of the detection chamber or remain in liquid suspension). The support is exposed to a light source having an appropriate spectrum of emission, such as to excite the fluorofors. In turn, the excited fluorofors emit a secondary radiation at an emission wavelength higher than the peak of the excitation spectrum. The light emitted by the fluorofors is collected and captured by an optical sensor. In order to eliminate the background light radiation, which represents a source of disturbance, the optical sensor is provided with band-pass or interferential filters centred at the wavelength of emission of the fluorofors.
However, the difference between the maximum peak of the emission spectrum of the fluorofors and the peak of the excitation spectrum (also referred to as "Stokes shift") is not very high, and the filters, however selective they may be, can only attenuate the light emitted by the source and subsequently diffused, without, however, eliminating it altogether. It should also be taken into account that the materials used for providing the supports often have high reflecting power. For example, microfluidic devices for the analysis of nucleic acids integrated in semiconductor chips are increasingly widespread. In integrated microfluidic devices, the detection chamber often has the bottom coated with a layer of silicon dioxide and, sometimes, also metal electrodes are present, for example of gold or aluminium. In effect, hence, only a relatively small part of the light emitted by the source is absorbed, whereas a conspicuous fraction is reflected and is potentially capable of disturbing the detection of the light emitted by the fluorofors.

Nucleic acid analysis chip integrating a waveguide and optical apparatus for the inspection of nucleic acid probes


This n-phased electromagnetic motor having two rotation senses and in which n is greater than 1, is particularly intended to drive the mechanism of a timepiece movement. It comprises n magnetic circuits, each being magnetically decoupled from n-1 other magnetic circuits. Each magnetic circuit includes two stator poles (4a and 4c, 4b and 4d) each comprising a polar expansion (6a to 6d respectively) partially defining a stator cavity (3) in which a rotor (2) is housed. These two stator poles are diametrally opposite one another relative to the axis (X--X) of the rotor (2). The magnetic separation of the magnetic circuits is assured by means of one or several gap(s) (15) judiciously arranged.

There is known from the Japanese patent application JP-61-10958 a two-phase symmetric stepping motor having two rotation senses which is formed of two single-phase stator parts superposed onto one another and with an angular shift of 90.degree. relative to one another.
The two single phase stator parts are fastened to one another, but are located in different planes. They are magnetically insulated from one another while being each provided with an excitation winding. Furthermore, each stator part defines an opening for a permanent magnet rotor common to both of them, the openings being aligned on the axis of rotation of the latter.
In order to define a stable position of the rotor, the edge of each opening of such stator parts is provided with two positioning notches which are diametrally aligned along a direction separated by 45.degree. relative to the principal direction of the magnetic flux passing through the rotor and generated by excitation of the corresponding winding. In the absence of excitation, the stable position of the rotor is attained when the North-South axis of the permanent magnet of the rotor is perpendicular to the alignment axis of the notches.
Thanks to this construction, the two stator parts work under exactly the same conditions with the rotor, however, because of their 90.degree. shift each assures the rotation of the rotor in a sense which is individual to it. If one admits that the volume of the permanent magnet of the rotor traversed by each of the two magnetic fluxes is the same, the resulting motor couple is identical for both senses of rotation.
This known motor exhibits several disadvantages. Initially, the volume occupied by the permanent magnet of the rotor is only partially used since each magnetic circuit surrounds less than the half of this volume. This disadvantage is further aggravated by the fact that the magnetic circuits are necessarily spread apart from one another along the rotor axis in order to assure the magnetic insulation thereof. There results therefrom a comparatively substantial height which is above all inconvenient when the motor is employed in horological applications.
Another disadvantage resides in the fact that the openings of the magnetic circuits must be aligned with precision along the rotor axis which causes manufacturing difficulties so as to increase in an exaggerated manner the cost of the motor.
The invention has as its purpose to provide an electric motor of the type indicated hereinabove which does not exhibit these disadvantages.

Electromagnetic motor with two rotation senses particularly intended for a timepiece


Novispirin peptides are antimicrobial agents with potent activity against Gram-negative bacteria. The peptides are nonhemolytic, exhibit reduced in vitro cytotoxicity relative to other antimicrobial peptides, and were well-tolerated in vivo after intravenous injection. Novispirins also bind lipopolysaccharide (LPS), a property that may mitigate symptoms associated with Gram-negative bacterial infection. A pharmaceutical composition comprising novispirin as an active agent is administered to a patient suffering from or predisposed to a microbial infection, particularly Gram-negative bacterial infections.

Background
The development of effective antimicrobial agents was once seen as a definitive cure for bacterial diseases. But even before the development of the first antibiotics, bacteria had demonstrated an ability to adapt to stress in the environment, resulting in the development of resistance. In recent years, the variety of antimicrobial agents has increased substantially, along with a parallel increase in resistant pathogenic microorganisms. Resistance is now recognized against all clinically available antimicrobial agents. The response to antimicrobial resistance in the medical community has been to use new or alternative antibiotics not previously used against the resistant bacteria. This approach has required the continuous development of new antibiotics, either as modifications of currently existing compounds or as combinations of compounds that may inhibit or bypass the bacterial resistance mechanisms.
Natural polycationic antibiotic peptides have been found in many different species of animals and insects and shown to have broad antimicrobial activity. In mammals, these antimicrobial peptides are mainly represented by two families, the defensins and the cathelicidins. Nearly all of these peptides have membrane affinity, and can permeate and permeabilize bacterial membranes, resulting in injury, lysis, and/or death to the microbes. For example, the human peptides termed alpha-defensins are produced by neutrophils and intestinal Paneth cells. In three-dimensions, defensins manifest an amphiphilic, largely beta-sheet structure, with a polar face formed largely by its arginines and with N- and C-terminal residues playing an important role in defining antimicrobial potency and spectrum. (See Gudmundsson et al. (1999) J Immunol Methods 232(1-2):45-54.) Antimicrobial peptides are reviewed by Hancock and Lehrer (1998) Trends in Biotechnology 16:82.
Cystic fibrosis (CF) is an inherited disorder that occurs in one of every 3,300 U.S. newborns. It affects some 30,000 Americans today. The median survival age of patients with CF is only 31.3 years, making CF the most common life-shortening inherited disease in the U.S. Most CF patients die from pulmonary failure that results from chronic, progressive infection by Pseudomonas aeruginosaxe2x80x94a Gram-negative bacterium that is widely distributed throughout the environment. P. aeruginosa has limited ability to infect normal individuals, but can be a devastating secondary invader in immunocompromised, severely burned, or antibiotic-treated persons. Because Pseudomonas aeruginosa strains frequently are or become resistant to conventional antibiotics, infections caused by them are often difficult to eradicate.
The in vitro activity of antimicrobial peptides, including cecropin P1, indolicidin, magainin II, nisin and ranalexin has been tested against clinical isolates of P. aeruginosa. The peptides were found to have a varied range of inhibitory values, and showed some synergy when combined with conventional antibiotics (Giacometti et al (1999) J Antimicrob Chemother. 44(5):641-5)
There is a clinical need for novel antibiotic agents that are active against drug resistant Gram-negative bacteria, and which have low toxicity against mammalian cells. The present invention addresses this need.
Relevant Literature
Saiman et al. (1999) Pediatr Pulmonol, Suppl. 17:320 report that drug resistant organisms from CF patients are inhibited by cathelicidin peptides; and Brogden et al. (1999) Pediatr Pulmonol, Suppl. 17:320 report on the efficacy of SMAP29 in an ovine model of pulmonary infection and its potential for treating P. aeruginosa infection in patients with cystic fibrosis (CF).
Methods and compositions are provided for the use of novispirin peptides. Novispirin peptides are small antimicrobial agents with potent activity against Gram-negative bacteria, including Chlamydia trachomatis, Pseudomonas aeruginosa, Eschelichia coli and Stenotrophomonas maltophilia. The peptides are nonhemolytic, exhibit reduced in vitro cytotoxicity relative to other antimicrobial peptides, and are well-tolerated in vivo after intravenous injection. Novispirins are equally effective against growing and stationary phase P. aeruginosa, and they retain activity in the presence of high concentrations of salt or human serum. Novispirins also bind lipopolysaccharide (LPS), a property that may mitigate symptoms associated with Gram-negative bacterial infection.
A pharmaceutical composition comprising novispirin as an active agent is administered to a patient suffering from a microbial infection, particularly bacterial infections. The protein is also effective at killing a variety of microbial organisms in vitro. Novispirin may be administered alone, or in combination with other bacteriocidal agents, e.g. antibiotics, as a cocktail of effective peptides, etc. Novispirin mediated killing of microbes is also useful for modeling and screening novel antibiotics.

The University of Iowa Research Foundation

The Regents of the University of California


Processing a digitized image signal includes selectively adjusting interpolated color values on the basis of correlations between pre-identified reference patterns of values and the patterns of values within the neighborhoods in which the interpolated color values reside. The reference patterns may be various possible combinations of a high reference value and a low reference value within a selected neighborhood configuration. When minimum and maximum color values are used as the reference values, the reference patterns are representative of the various maximum luminous gradient possibilities within the selected neighborhood configuration.

A digitized image signal generated by a two-dimensional array of sensors consists of pixel values representing the color intensities at each point of the color image. Conventional color photography utilizes three overlapping color sensing layers having sensitivities in different regions of the color spectrum. Typically, red, green and blue are the three selected colors. However, digital cameras are limited to a single array of sensors, so that there is only one "layer." Within this layer, each sensor determines the intensity of a particular color. As a result, the color array does not produce a color image in the traditional sense, but rather a collection of individual color samples. The assignment of the colors to the individual pixels within the array is sometimes referred to as the color filter array (CFA), or the color "mosaic pattern." To produce a true color image in which each pixel has a full set of color samples, a substantial amount of interpolation is required in order to estimate the missing information. The interpolation operation is typically referred to as "demosaicing."
The general concept of demosaicing will be described with reference to FIG. 1. An image sensor array 10 for capturing a digitized image signal is represented by a mosaic pattern that follows an arrangement referred to as a Bayer pattern (i.e., a repeating 2×2 sensor array kernel having two green pixels diagonally positioned within the kernel and having one red sensor and one blue sensor). The sensor array is a color-sampling device that acquires its samples using a number of discrete color-specific detectors. By example, the array may have 1500 columns and 1500 rows, but the numbers of columns and rows are not significant to the overall understanding of the process.
In the demosaicing of the image that is captured by the sensor array 10, the image may be considered as being decomposed into four input image planes 12, 14, 16 and 18. Each input image plane satisfies two conditions. First, the planes have the identical number of samples within a horizontal and vertical sampling interval. Second, all of the samples in the given input image plane have identical color properties, although multiple image planes can have the same color properties. For example, the image planes 12 and 18 have green samples, as indicated by the letter "G." Image plane 14 includes all of the samples that are specific to the color blue, as indicated by the letter "B," while image plane 16 includes all of the red samples from the sensor array 10, as indicated by the letter "R." Alternatively, only three input image planes may be considered, if the two image planes having green samples are combined. While the illustrated embodiment shows a Bayer pattern, other patterns are used by persons skilled in the art.
In FIG. 1, there are three different colors and there are four possible color arrangements within a two-by-two neighborhood of pixels. The number of possible color arrangements is consistent with the number of image planes 12, 14, 16 and 18. It is possible to use twelve convolution kernels (3×4=12) in the demosaicing process. The twelve convolution kernels are selected on the basis of which of the input image planes contains the sample for the pixel that is to be the current center of a movable neighborhood in which interpolation occurs and on the basis of which monochromatic output plane 20, 22 and 24 is presently being constructed. Each monochromatic output plane contains original color samples and contains interpolated intensity values that are derived from the intensity values of the input image planes.
To generate the missing information at a particular pixel, information from neighboring pixels is used, since there is a statistical dependency among the pixels in the same region of a particular image. Various demosaicing algorithms are available. "Bilinear interpolation" is an approach that attempts to minimize the complexity of the demosaicing operation. A bilinear interpolation algorithm interpolates color intensities only from the same-color sensors. That is, the information from the red sensors is treated independently from the information from the green and blue sensors. Similarly, the information from the green sensors is treated independently from the red and blue sensors, and the information from the blue sensors is treated independently from the outputs of the red and green sensors. To provide a red intensity value at a given pixel, the values measured by the red sensors in a designated size neighborhood (e.g., in a neighborhood of nine sensors having the given pixel as its center) are interpolated. If the mosaic pattern of sensors is a Bayer pattern, the bilinear interpolation algorithm may use twelve kernels of convolution to reconstruct the image, as previously noted.
The bilinear interpolation approach of isolating the different colors in the demosaicing operation requires a relatively low level of computational overhead. The tradeoff is that the reconstructed image often contains significant artifacts. Other interpolation approaches that consider different-color sample values may introduce fewer artifacts, but the cost may be a significant increase in the computational overhead.

Correlation-based color mosaic interpolation adjustment using luminance gradients


A network system (10). The system comprises a first network node (N6), and the node comprises an input (30IN) for receiving packets. During operation, the first network node operates as a downstream node when receiving packets at the input from an upstream node (N5). The node also comprises a buffer (30), coupled to the input and for storing received packets, and circuitry (32) for detecting when a number of packets stored in the buffer exceeds a buffer storage threshold. The node also comprises circuitry (32), responsive to a detection by the circuitry for detecting that the number of packets stored in the buffer exceeds the buffer storage threshold, for issuing a message to the upstream node. The message selectively commands the upstream node to reduce a rate of transmission of packets from the upstream node to the downstream node to a non-zero rate.

The present embodiments relate to computer networks and are more particularly directed to a network system in which the upstream switch transmission rate is controlled in response to traffic buffering in the adjacent downstream switch.
Ethernet networks are one type of network that has found favor in various applications in the networking industry and for various reasons. For example, Ethernet is a widely used and cost effective medium, with numerous interfaces, and capable of communications and various speeds up to the Gbps range. Ethernet networks may be used to form a Metro Ethernet network, which is generally a publicly accessible network that provides a Metro domain, typically under the control of a single administrator, such as an Internet Service Provider ("ISP"). Metro Ethernet may be used to connect to the global Internet and to connect between geographically separated sites, such as between different locations of a business entity.
An Ethernet network includes various nodes for transporting traffic among the network, where such nodes include what are referred to in the art as switches or routers, where for sake of consistency in this document are hereafter only referred to as switches or switch nodes, while one skilled in the art will appreciate that such switching functionality may be employed in other network devices. The switches implement known techniques for servicing traffic that arrives from different nodes and for minimizing transient (i.e., short term) congestion at any of the nodes. The IEEE 802.3x is the IEEE standard on congestion control. Under IEEE 802.3x, and in the event of congestion in a buffer corresponding to a switch input port, the switch provides "backpressure" by sending a pause message to any directly upstream Ethernet switch that has an output port that is transmitting to the input port that has developed the congestion. Such congestion is detected by a switch in response to its buffering system reaching a threshold, where once that threshold is reached and without intervention, the switch becomes unable to properly communicate its buffered packets onward to the link extending outward from that switch. In response to receiving the pause message, the upstream adjacent switch is thereby commanded to cease the transmission of data to the congested switch for a period of time specified in the pause message, thereby permitting the congested switch additional time to relieve its congested state by servicing the then-stored data in its buffering system. However, because IEEE 802.3x is a non-selective back-pressure congestion control, all the traffic aggregates passing through the congested link get paused irrespective of their ongoing traffic rates. This results in unfairness, as non-aggressive sessions also get penalized along with aggressive sessions.
Another approach also has been suggested for responding to congestion in Metro Ethernet networks. In "Selective Backpressure in Switched Ethernet LANs", by W. Noureddine and F. Tobagi, published by Globecom 99, pp. 1256-1263, and hereby incorporated herein by reference, packets directed to a same Metro Ethernet network destination MAC address are stored in a specific output buffer within a node. When the packet occupancy within such a buffer reaches a threshold limit, backpressure is applied to all the adjacent upstream nodes that have a buffer containing packets of that corresponding MAC destination. However, such an approach has drawbacks. For example, the approach is non-scalable, as there should be n number of buffers (or buffer space) in a node that switches traffic to n different MAC destinations. The number of buffers required also increases when traffic-class is introduced. Also if one of the buffers is not optimally utilized, other traffic with a different MAC destination is not able to utilize the unused resources in the sub-optimal buffer(s), thereby leading to wastage. Further, each session capacity requirement and path can vary with time as well as network condition and, hence, there is no provision for local Max-Min fairness.
Two additional documents also suggest response to congestion in Metro Ethernet networks. Specifically, in "A Simple Technique That Prevents Packet Loss and Deadlocks in Gigabit Ethernet", by M. Karol, D. Lee, S. J. Golestani, published by ISCOM 99, pp. 26-30, and in "Prevention of Deadlocks and Livelocks in Lossless, Backpressure Packet Networks", by M. Karol, S. J. Golestani, D. Lee, and published by INFOCOM 2000, pp. 1333-1342, and hereby incorporated herein by reference, a buffer is described that is shared by more than one session, where a session is defined as a packet or packets communicated between a same ingress and egress Metro Ethernet network edge node (i.e., as identifiable by the addresses in the MAC-in-MAC addressing scheme used for Metro Ethernet networks). The buffer is divided into segments and each segment is given an identification number. Each segment is allowed to store packets with different MAC addresses at the same time, but an arriving packet can only be stored in a segment that currently has packets with the same MAC addresses. If a segment fills to its limit, the node disallows any arriving packets from being stored not only in the congested segment but also other segments whose identification number is smaller than the congested one. At the same time, a backpressure message is sent to every adjacent upstream node. The upstream-nodes will then temporarily stop serving all buffer segments that have identification number similar or smaller than the downstream congested-node segment. Thus, the upstream node is prevented not only from transmitting to the segment that was filled, but also to other segments as well (i.e., those with a smaller identification code). These segments also will be temporarily prevented from accepting any arriving packets. These approaches do not therefore provide for fairness.
In addition to the limitations of the approaches noted above, it has been observed in connection with the preferred embodiments that congestion response at the Ethernet layer may be further improved with consideration of traffic qualifiers at a different network layer. In particular, under the International Standard Organization's Open System Interconnect ("ISO/OSI") model, there are seven network layers. Layer 2 of the ISO describes the data link which includes the logical connections to a network packet destination, using a network interface which includes the Ethernet interface and the concept of Ethernet addresses. The Ethernet address is a 48-bit address, often referred to as a Media Access Control ("MAC") address. Thus, each Ethernet device has a unique MAC address and the packet header at this layer includes both a source and destination MAC address so as to properly traverse the layer. Layer 3 of the ISO is the network layer and includes the Internet (or Internetwork) Protocol ("IP"), which permits routing of packets from one network to another. In this layer 3, "Differentiated Services" ("DiffServ") are expected to be widely deployed. In particular, "Assured Services" of the DiffServ architecture facilitate a priority-based drop precedence in the event of congestion. Packets of a session/flow are colored, in descending order of importance or drop precedence, as green, yellow, and red, depending on the rate and thereby leading to a highly scalable congestion management in ISO layer 3. As a consequence, the present inventors have observed that Ethernet, being the ISO layer 2 transportation technology, would be highly improved as supporting such differentiation that is not only scalable but is also consistent with the Assured Forwarding model of the DiffServ.
In view of the above, there arises a need to address the drawbacks of the prior art as well as the considerations of other layer technologies, as is accomplished by the preferred embodiments described below.

Network system with color-aware upstream switch transmission rate control in response to downstream switch traffic buffering


A Recovery Control Register is embodied as two multi-bit registers; a staged register and an immediate register. The immediate register contains the information which is read by the CP microcode and used during recovery. The staged register is a platform where a footprint can be assembled by the CP microcode before the retry checkpoint is changed. The CP microcode can operate on either register through the use of "SET", "AND" and "OR" functions. The choice of these operators as well as the decision to separate the registers into bit ranges provides the microcode with maximum flexibility when setting up new checkpoint values. When a recovery algorithm requires that the recovery footprint change immediately, microcode operates on the immediate register. If, however, the recovery footprint needs to be synchronized with the event which requires the change, for example a store being released, the microcode puts the appropriate footprint into the staged register and issues a release signal to the completion/interrupt logic within the CP. When the release is processed and broadcast as a Completion Report a variable number of cycles later, the checkpoint is advanced and the immediate register is updated in the same cycle, thereby allowing for a crisp transition from one recovery window to the next.

1. Field of the Invention
This invention relates to data processing systems having provision for error detection and recovery. More particularly, this invention relates to data processing systems which recover from errors by returning to and executing from a checkpoint in the instruction stream.
2. Related Art
The occurrence of random errors in data processing systems can have a substantial adverse effect on reliability and performance. A random or "soft" error is a deviation from the expected output or result which is not due to a continuing fault in the system. These random errors are generally characterized by non-reproducible fault syndromes caused by electrical noise or other randomly occurring sources. In contrast, "hard" errors are typically associated with electrical or mechanical component failures resulting in errors which are reproducible.
In early systems, random errors were handled by resetting the system and re-executing the affected program from the beginning. As programs became longer, this solution became unacceptable. Thus, in later systems, programs were segmented into parts such that errors could be handled by rerunning the program only from the beginning of the part in which the error occurred. As data processing systems and operating systems became more complex (due to, for example, multi-tasking) and time dependent, even this later approach became inadequate.
U.S. Pat. No. 4,901,233 to Liptay discloses a system which can execute instructions concurrently and out-of-sequence. A large number of instructions can be in some state of execution at any given time. While instructions can be executed out-of-sequence in such systems, the results of most instructions are not made visible to the rest of the system until the instruction is "architecturally completed". Completion of the instruction occurs when the execution of the instruction is finished, all exceptions associated with the instruction have been tested for and reported, and the instruction is the next one to logically complete (i.e. instructions complete in their logical program sequence). The challenges of recovering a Central Processor (CP) based on such a design from an error include the following:
1) determining which of the many instructions currently in process were affected by the error;
2) determining a known good state before the error occurred and and returning the CP to that state; and
3) modifying the state of the machine in a manner consistent with the logical program sequence while retrying the instructions.
FIG. 1 shows six hypothetical instructions in various states of execution. Each division on this chart represents a clock cycle or machine cycle. Execution of one machine instruction can take one to many machine cycles depending on what function is to be accomplished, availability of data and resources, and other factors. The instructions are numbered in the order in which they were programmed, i.e. Instruction 0 is followed by Instruction 1 which is followed by Instruction 2 etc. Instruction 0 begins execution in cycle 1 and completes in cycle 3. Instruction 1 begins in cycle 2 but does not finish execution until cycle 6. Although Instructions 2 and 3 finish before Instruction 1, they cannot complete until Instruction 1 completes in order for the program to execute in its logically programmed order.
U.S. Pat. No. 4,044,337 to Hicks et al. entitled "INSTRUCTION RETRY MECHANISM FOR A DATA PROCESSING SYSTEM" and assigned to the International Business Machines Corporation describes an error recovery mechanism that establishes a checkpoint at the beginning of the execution of a machine instruction. Since instructions are executed out-of-sequence in the system described in Liptay's patent, application of this technique to this system would require checkpointing up to the maximum number of instructions capable of being outstanding at one time and sorting out the order to reexecute the instructions. The amount of checkpoint information to accomplish this would be large and the probability that the checkpoint information itself was damaged by the error would therefore increase, lowering the overall ability of the processor to recover from the error.
A further complication is introduced by the potential of instructions executed out-of-sequence to be cancelled if a previous, yet unfinished instruction results in a change in the assumed instruction sequence. This could be due to a branch resolving differently than was expected or an instruction encountering an exception or an asynchronous interruption (for example an I/O, external, or repressible machine check interrupt or an operator request) becoming pending or enabled during some point in the processing. This would also have to be sorted out during the retry process to determine which checkpoints to save and which to discard.
Given that in Liptay's processor design some instructions may have already finished but not yet completed, another approach could be to save the results of the finished instructions and apply Hick's algorithm to only those instructions not yet finished.
In FIG. 1, if an error occurs in cycle 5, instruction 4 has begun, instruction 3 is just finishing and instruction 2 is finished although not yet complete. Since the error could have potentially affected one, some, all or none of the instructions in process, instructions 1, 3, and 4 need to be redone. Although instruction 2 has finished, trying to preserve its results has the following problems:
1) the logic to determine which instructions are finished and then sort out which need to be redone is prohibitively complex;
2) changes in the assumed instruction sequence would still have to be sorted out, discarding or saving checkpoints and finished results in this case instead of only checkpoints; and
3) any soft error in the logic which retains the finished status of an instruction would make the instruction unretrievable since this information would be required to retry successfully.
Additionally, some operations executed by processors designed to meet the specifications described in the Enterprise Systems Architecture/390 Principles of Operations (ESA/390 POP), require or are implemented such that results are made visible to and possibly cause a reaction in other system facilities as part of their execution and before they complete. For example, in some computer systems, communication between the I/O subsystem and the Central Processor is accomplished via interlocked updates to data areas in storage known as control blocks.
An interlocked update consists of first fetching a particular part of the control block called a lock byte using a hardware interlocked fetch. A hardware interlocked fetch, also called obtaining a hardlock, is a mechanism which insures that the requestor of such a fetch has exclusive rights to the data and no other requestors may store into or fetch that data until the interlock has been released. Once the hardlock is obtained, an identifying tag known as a softlock is placed into this byte, the lock byte is stored and the hardlock is released. Any other elements wanting to use the data covered by this softlock will see the tag in the lock byte and will not use the data until the lock byte is cleared. Both obtaining the softlock and releasing it require updating storage before the instruction has completed. Additionally, once the processor has control of the softlock, it will proceed to update other areas in the control blocks thereby initiating the desired I/O operation and changing the state of the I/O Subsystem. If an error occurs during one of these I/O instructions, storage has been altered and the effects potentially seen by other system elements. The altered storage location also may have caused a reaction in another processing element. Thus, simply backing up the processor to its state before or at the start of that operation will not nullify the effects of the execution even though the instruction did not complete. Special handling of these types of operations is therefore required when a soft error is encountered. It is desired however, that the number of special cases to be handled be minimized to reduce the number of algorithms to be developed, maintained and tested.
Two other examples of such operations which updated system facilities before they have completed are certain implementations of Page In and Page Out to Expanded Store. During execution of these instructions, a page of data is moved into or out of main storage, respectively. For some implementations, paging occurs before the instruction completes. The data which is moved can thus be seen by processing elements other than the Central Processor which executed the instruction. If an error occurs while this instruction is executing, the results cannot be undone by backing up the processor to its state before the execution of this instruction.
As an additional aid in error recovery, it is known in the art to provide a computer system with a checkpoint register. Such a facility is described in an article entitled "CHECKPOINT REGISTER" (IBM Technical Disclosure Bulletin, Vol. 27, NO. 4A, September 1984, pp 2231-2232). The checkpoint register, located in the instruction element of a central processor, can be set to any value by the Central Processor microcode via an emit field. The checkpoint register is reset at the beginning (successful first cycle) of each instruction. The register can be tested by CP microcode for retry and detailed error reporting.
When an error in the CP occurs, the CP clocks are stopped. A maintenance and support service facility (MSSF) then scans the registers and triggers in the CP including the checkpoint register. The MSSF tests an error trigger which denotes checkpoint register parity error. If this trigger is on, the MSSF considers the error unretriable, a system damage (SD) indication is set, and the CP is set to the checkstop state. The MSSF then checks the Checkpoint register. A value of 64 through 255 indicates system damage. The MSSF then tests the non-retriable triggers in the CP. If retriable, the system damage will only be reported when the retry threshold is reached and a machine check interrupt is taken.
The value contained in the Checkpoint register tells the MSSF what type of operation was in progress in the CP when the error occurred, as well as whether or not special action is required by the MSSF to return the CP to a logically consistent state, or that the CP cannot be brought back to a consistent state except by a system reset (i.e. a "System Damage" condition exists).
In summary, the Checkpoint Register is a means of communicating to the MSSF the internal state of the CP for purposes of error recovery (checkpoint retry), and error reporting to the program (machine check interruption).
While the above described "prior art" Checkpoint Register provides many advantages in terms of error recovery, it does not provide for crisp transitions synchronized with the completion of checkpoints. In the above described register, data that is entered into the register is immediately available to the MSSF. In systems such as described in U.S. Pat. No. 4,901,233 to Liptay however, where checkpoint transitions are marked by instruction completion, the data presently in the register may be incorrect or premature. Thus, a mechanism is needed to ensure that the data provided to the MSSF is neither obsolete nor premature.


There is described a helicopter having a first member movable with respect to a second member; lubricated supporting means for supporting the first member with respect to the second member; and a primary lubricating circuit for lubricating the supporting means and in turn having primary storage means for accumulating a lubricating fluid, and primary fluid feed means for feeding the lubricating fluid to the supporting means; the helicopter also has an auxiliary lubricating circuit supplied continually by the primary storage means with a first lubricating fluid flow value, and itself continually supplying the supporting means with a second lubricating fluid flow value lower than the first value, so as to produce an auxiliary storage volume of lubricating fluid for use in the event of breakdown of the primary lubricating circuit.

As is known, helicopters are normally equipped with a number of transmissions for transmitting motion from one or more turbines to the main and/or tail rotor, and/or from the turbine to a number of accessory devices, i.e. for powering on-board equipment, for example.
The transmissions normally comprise a first member movable with respect to a second member; and a number of bearings for supporting the first member with respect to the second member. Helicopters also comprise a circuit for supplying and lubricating the bearings with lubricating oil contained inside special tanks.
In the event of damage to the lubricating circuit, the oil pressure falls, thus preventing operation of the transmission.
In the industry, a need is felt to ensure, in such cases, correct operation of the transmission for a predetermined length of time, e.g. at least thirty minutes and preferably an hour, to allow the helicopter to land.
Moreover, for missions of a given duration, helicopter certification regulations require that the helicopter be able to maintain level flight for said predetermined length of time.

Helicopter with an auxiliary lubricating circuit


Method and system integrating wireless/wireline and circuit/packet networks (to bypass GSM Memorandum of Understandings) for cellular/PCS services so that GSM subscribers roaming into CDMA networks can be provided with basic wireless call delivery services as long as the roamers can pay the bill with their valid credit card. This is achieved by integrating wireless and wireline networks as well as circuit and packet networks, using IP networks and protocols as an alternative to the existing telephony-based approach.

Not Applicable.
Not Applicable.
The present invention relates to cellular or wireless call delivery services provided by cellular/PCS operators. Call delivery service permits a cellular or wireless subscriber to receive phone calls either in a home network (e.g., London) or while away from the home network (e.g., in Chicago).
Global Systems for Mobile Communications (GSM) is a widely popular Time Division Multiple Access (TDMA)-based standard used in Europe. TDMA is a digital wireless technology.
A subscriber who roams to Code Division Multiple Access (CDMA) wireless networks may be denied wireless services even if the subscriber""s mobile device is capable of dual-mode (CDMA or analog, and GSM) operation, and the subscriber has the ability to pay for wireless calls with his/her valid credit card. The basis for the denial of service is simply because there is a lack of a GSM Memorandum of Understanding (MoU) between the home GSM network and visited CDMA network for billing settlement.
1. Field of the Invention
The present invention relates to the field of Internet Protocol as used to replace traditional telephony infrastructure for roaming wireless users. The present invention also relates to the field of providing mobile wireless telephone service for users roaming outside their own predefined service area. The present invention also relates to the field of inter-operability of CDMA and GSM/TDMA wireless networks.
2. Description of Related Art
A GSM MoU is an agreement between a consortium of GSM wireless service providers. For example, a subscriber of a first GSM service provider may roam to a service area controlled by a second GSM service provider. An established MoU allows the first GSM service provider to still serve the subscriber while that subscriber is in the service area corresponding to the second GSM service provider. In practice, the second GSM service provider gets paid a portion of the service/roaming charge the first GSM service provider charges the subscriber, which is one reason why wireless xe2x80x9croaming chargesxe2x80x9d are so expensive.
The Local Number Portability (LNP) feature could be used, to some extent, to bypass GSM MoU. LNP allows a telephone subscriber to xe2x80x9cportxe2x80x9d his/her phone number when that subscriber relocates to a different region of the country, even when the local area code may be different (e.g., a subscriber may reallocate from Chicago to New York, but still keep the original phone number used in Chicago which has an area code of 312).
However, LNP updates are not dynamic by design and thus can have serious limitations. A subscriber who wants LNP typically will request that service by filling out a form. The phone company""s administrative staff will manually process the form and make necessary updates of various databases to effect the requested LNP. Note that LNP is designed to support occasional change of location/re-location, and is typically done manually, thus there is a scalability issue in practice.
Public Switched Telephony Network (PSTN) refers to the public phone networks as we know them. PSTN is composed of switches and T1/E1 trunks, central office, etc. PSTN uses circuit-switched technology, in which necessary resources are allocated (dedicated) for the duration of a phone call. An IP network (e.g., the Internet), in contrast, is composed of nodes of computers, serves, routers, and communications links, etc. It employs packet-switching technology which decomposes data (e.g., voice, web pages, an e-mail message) into IP packets. Each packet is then transmitted over an IP network to a destination identified by an IP address and reassembled at the destination. An IP transmission is completed without pre-allocating resources from point to point.
Dynamic Host Configuration Protocol (DHCP) service provides a dynamic IP address with a short term lease. DHCP is covered by RFC 2131. As of the date of this disclosure, RFC 2131 may be obtained from URL http://nic.mil/ftp/rfc/rfc2131.txt. The major use of DHCP is to support dynamic IP address assignment. For example, an ISP (Internet Service Provider) can use DHCP to dynamically assign an IP address to a subscriber after he/she logs in over a dial-up connection; once the session is over, the IP address is recycled for other dial-in users.
Mobile IP is described by Internet Engineering Task Force (IETF) Request for Comments (RFC) number 2002. As of the date of this disclosure, RFC 2002 may be obtained from URL http://nic.mil/ftp/rfc/rfc2002.txt. Unlike H.323, Mobile IP does supports packet mobility, but smooth handoffsxe2x80x94as smooth as circuit cellular voicexe2x80x94are not supported.
The Diffie-Hellman algorithm is a math method allowing two parties to establish a temporary secret for secure transmission of information. This technique is detailed in: Diffie, W. and Hellman, M., xe2x80x9cNew directions in cryptography,xe2x80x9d IEEE Transactions on Information Theory, Vol. IT-22, Nov. 1976, pp. 644-654.
The present invention addresses the above issues of denial of service by combining and integrating the proper pieces of circuit and packet, and that of wireless and wireline. The present invention provides a way to bypass GSM MoU so that GSM users roaming into CDMA networks, having the ability to pay wireless calls with a credit card, can be provided with basic call delivery wireless services.
These and other aspects and attributes of the present invention will be discussed with reference to the following drawings and accompanying specification.

GSM MoU bypass for delivering calls to GSM subscribers roaming to CDMA networks


An air bearing slider supports a transducer over a moving recording medium based on air flow generated by the movement of the recording medium. A first pad is formed near a leading edge of the slider and has a first leading edge contoured to provide a first effective length relative to the air flow for the first pad. A second pad is formed near a trailing edge of the slider and has a second leading edge contoured to provide a second effective length relative to the air flow for the second pad. A third pad is formed near the trailing edge of the slider and has a third leading edge which is contoured to provide a third effective length relative to the air flow for the third pad. The first, second, and third effective lengths vary as the air bearing slider moves relative to the moving recording medium to maintain a desired orientation and fly height for the slider during such movement.

1. Field of the Invention
This invention relates generally to air bearing sliders that support transducers over moving recording media and, more particularly, to an air bearing slider which exhibits an improved takeoff velocity.
2. Background Description
Conventional magnetic disk drives are information storage devices which utilize at least one rotatable magnetic media disk with concentric data tracks, a read/write transducer for reading and writing data on the various tracks, an air bearing slider for holding the transducer adjacent to the track generally in a flying mode above the media, a suspension for resiliently holding the slider and the transducer over the data tracks, and a positioning actuator connected to the suspension for moving the transducer across the media to the desired data track and maintaining the transducer over the data track during a read or a write operation.
During operation of the magnetic disk drive, the slider is suspended (i.e., xe2x80x9cfliesxe2x80x9d) above the magnetic media disk. The separation between the slider and the magnetic media disk is referred to as the xe2x80x9cfly height.xe2x80x9d The goal of air bearing slider design is to achieve a minimal fly height without having the slider physically impact the magnetic media disk. Smaller fly heights are desired so that the transducer can distinguish between the magnetic fields emanating from the closely spaced tracks of the magnetic disk media, thereby making possible an increased recording density for the magnetic disk drive.
In so-called xe2x80x9ccontact start-stopxe2x80x9d (xe2x80x9cCSSxe2x80x9d) magnetic disk drive designs, it is common for a region on the surface of the magnetic media disk to be textured. This textured region, which is found at the inner diameter of the disk and is referred to in this specification as the xe2x80x9clanding zonexe2x80x9d, is the region from which the slider lifts off when the magnetic media disk begins moving and is the region to which the slider returns when the magnetic media disk ceases moving.
When used with disks that include a landing zone, a slider must achieve lift quickly once the disk has begun moving to clear the height of the texturing provided on the surface of the disk in the landing zone. The longer the slider takes to lift off the surface of the landing zone (i.e., the slower the slider""s take-off velocity), the longer the time (or the number of rotations) that the slider is in contact with the magnetic media disk. The result is increased wear at the interface of the slider and the magnetic media disk. Furthermore, a slider that has a slow take-off velocity also has the added drawback that any collisions between it and the magnetic media disk that occur at the late stages of the take-off process occur at a high velocity. Such high velocity collisions also increase the wear at the interface of the slider and the magnetic media disk.
The prior art has addressed the problem of achieving a desired take-off, or clearance between the slider and the magnetic media disk. For example, U.S. Pat. No. 5,418,667 to Best et al. entitled SLIDER WITH TRANSVERSE RIDGE SECTIONS SUPPORTING AIR-BEARING PADS AND DISK DRIVE INCORPORATING THE SLIDER (xe2x80x9cthe Best ""667 Patentxe2x80x9d) discloses an air bearing slider pad which rests on a step surface and which is angled to provide extra air bearing lift to the slider at the inner diameter of the magnetic media disk. U.S. Pat. No. 5,870,250 to Bolasna et al. entitled METHOD AND APPARATUS FOR IMPROVING FILE CAPACITY USING DIFFERENT FLYING HEIGHT PROFILES discloses different embodiments of air bearing sliders which use angled rails to create desired air pressure distributions at predetermined radii of a recording medium. Similarly, U.S. Pat. No. 5,796,550 to O""Sullivan et al. entitled METHOD AND APPARATUS FOR PROVIDING DIVERGING RAIL EDGE GEOMETRY FOR AIR BEARING SLIDER discloses a slider having air bearing pads or rails that have at least one edge diverging from the side edges of the pad""s or rail""s support structure to reduce the slider""s sensitivity to skew and roll.
The prior art has also addressed the problem of the altitude sensitivity of the fly height air bearing sliders. U.S. Pat. No. 5,777,825 to Dorius entitled NEGATIVE PRESSURE STEP PAD AIR BEARING DESIGN AND METHOD FOR MAKING THE SAME (xe2x80x9cthe Dorius ""825 Patentxe2x80x9d) discloses several embodiments of an air bearing slider which use front and back air bearing surface pads that rest on leading and trailing step surfaces. According to the Dorius ""825 Patent, prior art air bearing slider designs exhibit sensitivity to changes in altitude. This sensitivity poses a reliability problem for magnetic disk drives in that a decrease in a slider""s fly height caused by an increase in altitude results in more interactions between the slider and the magnetic media disk of the magnetic disk drive. Consequently, the incidence of magnetic disk drive failures increases with increases in altitude. The Dorius ""825 Patent is directed to providing an air bearing slider which possesses a reduced sensitivity to changes in altitude. The air bearing slider design described in the Dorius ""825 Patent takes a step-pad (i.e., bobsled) design and adds a negative pressure (i.e., subambient pressure) pocket between the leading-edge and trailing edge pads of the slider. The slider is described as requiring only two etch depths to manufacture, and the negative pressure pocket is described as being etched to a specific depth to achieve the desired reduction in altitude sensitivity.
The prior art has not, however, addressed the problem of improving the take-off velocity of an air bearing slider. The Best ""667 Patent, for example, is directed to achieving a clearance between the slider and the magnetic media disk, but it does not address the problem of achieving a faster take-off velocity for the slider. The Dorius ""825 Patent, by way of another example, is strictly directed to improving the altitude sensitivity of sliders, and does not recognize the need to improve the take-off velocity of air bearing sliders. Nor does the Dorius ""825 Patent recognize the need to balance the altitude sensitivity of a slider with its take-off velocity. Accordingly, there is a need in the art for an air bearing slider that has an improved take-off velocity.
The present invention is directed to an apparatus that satisfies the need for an air bearing slider that has an improved take-off velocity. According to the embodiments of the present invention, the time (or the number of rotations) during which the slider is in contact with the magnetic media disk is reduced.
According to an embodiment of the present invention, an air bearing slider for supporting a transducer over a moving recording medium comprises: a first pad formed near a leading edge of the slider and defining a negative pressure region of the slider; a second pad formed at a trailing edge of the slider and having an air bearing surface with a leading edge which is contoured such that air flow incident upon the second pad creates a predetermined positive pressure underneath the second pad at a first skew angle of the slider; and a third pad formed at the trailing edge of the slider and having an air bearing surface with a leading edge which is contoured such that air flow incident upon the third pad creates a predetermined positive pressure underneath the third pad at a second skew angle of the slider.
The air bearing slider may further comprise a first ramp surface contiguous with a leading edge of the air bearing surface of the first pad. The first pad may further comprise first and second legs connected by a bridge section to form a generally horseshoe shape.
The air bearing slider may further comprise a second ramp surface contiguous with a leading edge of the air bearing surface of the second pad.
The air bearing slider may further comprise a third ramp surface contiguous with a leading edge of the air bearing surface of the third pad.
The first skew angle may comprise a skew angle of the slider at an inner diameter of the recording medium. An air flow vector representing the air flow incident on the second pad at the first skew angle may be orthogonal to the leading edge of the air bearing surface of the second pad.
The second skew angle may comprise a skew angle of the slider at an outer diameter of the recording medium. An air flow vector representing the air flow incident on the third pad at the second skew angle may be orthogonal to the leading edge of the air bearing surface of the third pad.
The first, second, and third ramp surfaces may comprise step-type ramp surfaces. The step-type ramp surfaces may be formed at a first etch depth.
The negative pressure region may be formed at a second etch depth that is greater than the first etch depth.
The first and second pads and the first and third pads may define air bleed slots.
The above, and other features, aspects, and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numerals designate the same elements.

Air bearing slider having improved take-off velocity

Matsushita Kotobuki Electronics Peripherals of America, Inc.


An animal trap for capturing a small-weight animal. The animal trap includes a capturing enclosure 12 provided with a first entrance 11, a swing plate 13, provided in an approach 15 of an animal entered from the first entrance 11, for plugging up the first entrance 11 by swinging forward, and a locking mechanism 14 for temporarily locking the swing plate 13 so that the swing plate 13 swung to plug up the first entrance 11 does not swing back. The temporary locking mechanism 14 includes a first lock part 21A and a second lock part 21B that are disposed in a front end part of the swing plate 13. The lock parts are constructed to have mutually different heights at which the swing plate 13 is temporarily locked. When an animal enters, the swing plate 13 swings to plug up the first entrance 11, and it is temporarily locked. The swing plate 13 can be swung by a small weight.

Conventionally, as trapping apparatuses for capturing animals, such as rats and raccoons, trapping apparatuses utilizing a seesaw plate as illustrated, for example, in the following Patent Documents 1 and 2, are provided. Note that the reference numerals in brackets used in the following description are the same as those published in the official gazettes.


A pixel circuit, an active sensing array, a sensing device, and a driving method thereof are provided. The pixel circuit includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to a sensing element and a data line. The reset transistor is electrically connected to a first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and a second scan line. During a compensation period, the reset transistor is turned on in response to a first scanning pulse from the first scan line, so that the sensing transistor is connected into a diode configuration, and the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration in response to switching of a level of the data line.

Along with the development of optoelectronic technology, sensing devices have been broadly applied to different technical fields, such as optical image sensors, digital radiography sensors (DRS), and touch screen sensors. A sensing device is mainly composed of an active sensing array, and the active sensing array includes a plurality of pixel circuits.
In order to meet the high security demand, a sensing device is designed to have high sensitivity, so that the pixel circuit can detect incident energy of low-dose radiation. Besides, in order to meet the demand for high resolution, the area of a single pixel circuit is relatively reduced, and accordingly the photosensitive area of a sensing element in the pixel circuit is reduced. It should be noted that the intensity of an electric signal generated by the pixel circuit is drastically reduced with the decrease in the radiation dose of the incident energy and the photosensitive area of the sensing element.
The characteristic differences between transistors in the pixel circuit become obvious and can not be neglected due to the weak electric signal. For example, the threshold voltage of each transistor changes with process variation. Besides, when the transistors have different threshold voltages, different sensing results will be produced even though the same incident energy is supplied to each pixel circuit. As a result, sensing errors will be produced.
To resolve the problem mentioned above, some techniques for compensating the threshold voltages of the transistors in a pixel circuit have been developed, such as the "Investigation of gain non-uniformities in the two TFT, current programmed amorphous silicon active pixel sensor for fluoroscopy, chest radiography and mammography tomosynthesis applications" published by N. Safavian et al. in volume 7622 of proceedings of SPIE and the "TFT active image sensor with current-mode readout circuit for digital x-ray fluoroscopy" published by N. Safavian et al. in volume 5969 of proceedings of SPIE.
The technique provided by N. Safavian et al. in the volume 7622 of the proceedings of SPIE cannot provide regional compensation or one-time compensation to the pixel circuits (i.e., cannot effectively compensate each pixel circuit in an active sensing array). Additionally, the pixel circuit disclosed by N. Safavian in the volume 5969 of the proceedings of SPIE has a 3-transistor (3T) structure. Thus, the pixel circuit has a large layout area therefore can only be applied to low-resolution sensing devices.
Thereby, how to eliminate the sensing errors caused by the characteristic differences between different elements when the resolution and sensitivity of a sensing device are improved has become a major subject in the design of sensing devices.

Pixel circuit, active sensing array, sensing device and driving method thereof

Industrial Technology Research Institute


The present invention provides a process and a system for matching buyers and sellers of goods and/or services for a project. The invention enables a buyer to specify a project in terms of physical, functional, temporal, financial, and/or transactional parameters (102) which are then automatically converted, by the present invention, into at least one request for goods/services (104) needed to complete the project. The requests are suitably provided to at least one seller, who may be pre-identified by the buyer as a preferred seller. Upon receiving a request, the seller may submit a response to the request, as desired. Additionally, the invention provides a forum for the negotiation of any agreemments and the formation of contracts to provide the requested, or alternative goods/services (106). Further, the present invention provides a system and process for targeting marketing to online buyers based upon profiles established for the buyers, profiles for the sellers, and the current on-line activities of a buyer. The targeted marketing features are preferably provided by utilizing Profile links which provide hyper links to a web page associated with a seller.

1. Field of the Invention
The invention relates to the acquisition of research and development expertise, personnel, facilities, and resources through the use of requests for proposal.
2. Background
In the non-profit and government sector, matching research and development (R&D) needs with the personnel and organizations able to deliver such R&D solutions and resources traditionally involves the following multi-step procurement process: (1) a suitable request for proposal (RFP) is created to identify the research and development needs; (2) the RFP is advertised publicly and broadly to attract research and development providers; (3) interested research and development providers submit proposals, or bids, on fulfilling the needs; (4) the submitted proposals are evaluated based on published criteria; and (5) one or more proposals are selected for funding.
For a number of reasons, this traditional procurement process is problematic for use in the private sector. If an R&D buyer (hereinafter to mean any individual or organization interested in acquiring R&D expertise, personnel, facilities or resources) in the private sector were to use an RFP in the conventional way, the public distribution of the RFP tends to inform the entire R&D community as to which R&D buyers are interested in what types of R&D. Furthermore, the detailed information in an RFP can make the specifics of innovative technology and/or science known to the entire R&D community. Thus, a private entity's business strategy and intellectual property can be made vulnerable by the traditional procurement process. Further, the fear of competition inhibits the information flow inherent in and critical to the proper execution of the traditional procurement process.
Likewise, R&D suppliers (hereinafter to mean any individual or organization interested in providing R&D expertise, personnel, facilities or resources) not only have no assurance that the effort and costs associated with developing a proposal in response to the RFP will be rewarded by a private sector R&D buyer, but the ideas and solutions presented in an R&D supplier's proposal can themselves be valuable intellectual property to the R&D supplier that would be made vulnerable by disclosure. Because of the difficulty in identifying qualified R&D suppliers, the difficulty of publicly advertising R&D buyer needs, and that the intellectual property of both R&D buyers and suppliers can be made vulnerable through mutual, unprotected disclosures, the traditional procurement process has not and cannot be used in the private sector and the state of the private sector R&D community is one of a community with fragmented R&D buyers and suppliers.
Public and government agencies, such as the Whitaker Foundation and the National Science Foundation, facilitate the operation of the traditional procurement process by providing an interface to the R&D community (in the case of the government, for example, by publishing in the Commerce Business Daily or CBD), matching R&D suppliers with public and government R&D needs. However, companies in the private sector do not have such a public and broadly referenced interface to facilitate matching R&D needs and sources. Further, the requirements for matching private sector R&D buyers with R&D suppliers can be more varied and complex than those involved in the public sector. As a result, companies in the private sector are disadvantaged financially and logistically in acquiring external R&D and leveraging internal R&D.
Because of these reasons and the lack of any standards or metrics for R&D quality, the private sector's search and acquisition of R&D resources is typically inefficient, time-consuming and ad hoc.

Systems and methods for facilitating research and development


Automatically populating contact information fields of a contact information database, such as for instance an electronic address book is performed without requiring an individual to manually enter data for the contact. A message is sent to the newly added contact requesting that they fill in their contact information. When the individual is a member of a service filling in the contact information is automatable.

Electronic messaging has dramatically changed the manner in which people communicate with one another in the digital age. Electronic messaging systems, for example, permit users on different computers to communicate with one another by transmitting information such as text messages and the like between the different computers. Electronic messaging is often used to permit employees in a company to communicate with other employees connected to the company's internal network, regardless of whether they are in the same or another company facility. Also, due to the explosive growth of the Internet, electronic messaging has now become a relatively common way for anyone with a computer to communicate with other computer users all over the world.
In most electronic messaging systems, users are assigned user identifiers, or "user id's" that uniquely identify each user. Furthermore, each user is typically assigned one or more "mailboxes," (also referred to as "post office boxes") that have a unique address so that any user wishing to send an electronic message (often referred to as an "e-mail") to another user can do so by addressing the electronic message to the mailbox assigned to that user.
Many electronic messaging systems furthermore keep electronic "address books," which typically include contact information databases within which are stored records of the mailbox addresses for different users. Therefore, for example, a user wishing to send an electronic message to a user named John Smith, whose mailbox address is "email@example.com", is then able to search through an address book to find an entry for "Smith, John", rather than having to remember a relatively cryptic mailbox address that is assigned to that user.
Some address books also store additional information about users, such as telephone numbers, mailing addresses, job titles, and other information that is more or less unrelated to electronic messaging. Such an address book is often referred to as a "contact manager," as a user is capable of using the address book to maintain a wide variety of information about many different people (referred to in this context as "contacts"). As the use of electronic messaging has become more widespread, many computer users send and receive more electronic messages to and from a larger number of other computer users.
Typically, a user of a prior art contact management software application is required to enter the contact information that they want to store in their address book. A variety of methods exist for entering this contact information. It may be entered manually using a keyboard device, imported from an existing file on their computer, or imported via a peripheral device such as a business card scanner. Unfortunately, often the user does not have a complete set of contact information, and accordingly some contact information fields remain unpopulated when a new contact is added to the address book.
Prior art methods of updating and maintaining contact information databases are known. For example, services such as Internet-Based "White Pages" and E-Mail Directory Services are used to synchronize contact information of locally maintained address books with current contact information stored on a central storage system. Such a service may be used to populate empty contact information fields at some time after a new contact has been added to a local address book. It is a disadvantage of this form of service that each party is required to be a member of the service and that members of the address book, which are not already subscribed, still have to manually inform the subscribed user of their contact information. Furthermore, it is a disadvantage that this form of service requires the contact information to be stored on a central storage system. Although security may be strictly enforced, there are still privacy and security concerns because all personal information is accessible from outside the server.
It would be highly advantageous to provide a method for populating contact information fields for newly added contacts within a contact database absent security concerns, privacy concerns and mandatory subscription to a service by each party within a given contact list.

Method of automatically populating contact information fields for a new contract added to an electronic contact database


An image synthesizing apparatus according to the present invention comprises coefficient setting means for setting a blending coefficient α(0≦α≦1) at a specified value when a value of a specific picture element component included in picture element components A of a first image is a predetermined value; and arithmetic means for performing an operation on the picture element components A, picture element components B of a second image, and the blending coefficient α as follows: A*α+B*(1−α), and performing the operation on all the picture element components A and the picture element components B of a picture element that has the specific picture element component representing the predetermined value by using the blending coefficient α set by the coefficient setting means.

The present invention relates to an image synthesizing apparatus for synthesizing two pieces of image data and outputting synthesized image data, and particularly to an image synthesizing apparatus for effecting image synthesis by using an α blending method.
Recently, functions of a television receiver have been diversified. Since conventional mechanical switches such for example as buttons provided on the body of the television receiver and a remote control are not sufficient for setting the functions of the television receiver, the functions are more often set by menu operation such as displaying a menu image on a monitor screen, selecting a setting item, and supplying an input on a displayed setting screen. In some of such cases, an image for menu operation is superimposed on a television image currently selected for viewing by a television tuner on the monitor screen.
FIG. 7 shows an example of a display screen of a television receiver for such menu operation.
FIG. 7 shows a menu screen 71 to be superimposed, a television screen 72 selected by a television tuner or the like, and a synthesized screen 73 in which the menu screen 71 is superimposed on the television screen 72. Selection buttons 71a, 71b, and 71c shown on the menu screen 71 for example represent a "sound selection" button for switching between a main-channel sound and a sub-channel sound, a "channel" button for setting the display number of a channel, and a "return" button for stopping the display of the menu screen, respectively.
The television screen 72 being viewed can be seen through the menu selection buttons 71a, 71b, and 71c on the synthesized screen 73 in which the menu screen 71 is superimposed on the television screen 72. An image synthesizing method that makes one image seen through the other image in such a manner is referred to as α blending. This processing method is often used for menu operation on a television screen.
According to the α blending method, when an image to be superimposed is set to be A, a background image is set to be B, and a blending coefficient α is set to be α(0≦α≦1), an operation is performed on each element forming respective one of the images A and B so that an output image S satisfies the following equation, and then the result is outputted.S=A*α+B*(1−α)An arbitrary value in a range of 0≦α≦1 is selected for the blending coefficient α to thereby define transparency; when α is zero, the image A to be superimposed on the image B is completely transparent, while when α is unity, the image A to be superimposed on the image B is completely opaque.
When the menu screen is superimposed on the television screen by using the α blending method as described above, the blending coefficient α is generally determined for each menu screen using a table referred to as a color look-up table (hereinafter referred to as a CLUT).
FIG. 8 shows an example of a CLUT. In FIG. 8, Y, Cb, and Cr are picture element components that form a picture element, and Y represents a luminance component while Cb and Cr represent color difference components. Coordinate values represent coordinates (x, y) of a picture element on a monitor screen obtained when an x-component is taken in a horizontal direction and a y-component is taken in a vertical direction. In order to simplify description, it is assumed that only four sets of coordinates are present in FIG. 8. The values of the luminance component Y, the color difference component Cb, the color difference component Cr, and α are converted into 8-bit data for convenience of operation.
In order to change transparency of a synthesized screen for each picture element, the α blending method using a CLUT requires information on an α value for each picture element, as shown in FIG. 8. Therefore, the finer the picture elements on a monitor screen, the larger the amount of information of the CLUT, thereby increasing memory size and the load of the above-mentioned operation processing, and thus decreasing image-generating rate. In order to deal with the problem, circuit scale, power consumption, and cost of the television receiver must be increased.

Image synthesizing apparatus and image synthesizing method