The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to be operated at significantly faster clock speeds. The external strobe signal (XDQS) may be used to generate at least two derivative strobe signals therefrom. Instead of the XDQS signal, the derivative strobe signals are then used, in a predetermined order, to clock in or strobe the data to be written into memory cells. The last generated derivative strobe signal may be used to finally transfer the data bits into memory cells. Once the last of the derivative strobe signals is activated, and so long as there are no more data writes pending in the command pipe for the next clock cycle, the rising or falling edge of the last derivative strobe signal can be detected to turn off further generation of the strobe signals prior to any onset of postamble ringing on the XDQS signal. Thus, false data may not get “clocked in” or written into the memory chip because of postamble ringing. This prevents data corruption and preserves the integrity of the data written into a memory chip.

1. Field of the Disclosure
The present disclosure generally relates to memory devices and, more particularly, to a system and method to avoid DQS postamble ringing during memory writes.
2. Brief Description of Related Art
Memory devices are widely used in many electronic products and computers to store data. A memory device is a semiconductor electronic device that includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation. FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins 24 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 24 may constitute memory address pins or address bus 17, data (XDQ) pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17–19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address select (RAS) signal, a column address select (CAS) signal, an external data strobe (XDQS) signal, etc. (not shown)) on the control lines or control bus 19. The "width" (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 26. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 26 generally arranged in rows and columns to store data in rows and columns. A row decode circuit 28 and a column decode circuit 30 may select the rows and columns in the memory cells 26 in response to decoding an address, provided on the address bus 17. Data to/from the memory cells 26 is then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) circuit or I/O unit 32. The I/O circuit 32 may include a number of data output buffers to receive the data bits from the memory cells 26 (e.g., during a memory read operation) and provide those data bits or data signals to the corresponding data lines in the data bus 18. Alternatively, during a memory write operation, the I/O unit 32 may receive data bits externally supplied by a processor or memory controller (not shown) and may transfer or write the data bits into appropriate memory cells 26 using the externally supplied data strobe signal (XDQS) as discussed in more detail hereinbelow.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock signal, a Chip Select signal, a Row Access Strobe signal, a Column Access Strobe signal, a Write Enable signal, an external data strobe signal (XDQS), etc. The memory chip 12 communicates to other devices connected thereto via the pins 24 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIG. 2 illustrates a prior art circuit showing how two bits of data (D0, D1) are written into appropriate memory cells 26 using the external strobe signal (XDQS) 19. It is noted here that for the sake of convenience the reference numeral "19" is used in the discussion below to refer to the XDQS signal or XDQS pin on the memory device 12. As discussed before, the XDQS pin is of course part of a set of control signal pins 19. However, because the following discussion is primarily related to the XDQS signal (as opposed to other control signals in the control bus 19), the reference numeral "19" is conveniently used to refer to the XDQS signal. This usage is for sake of convenience only and, does not, in any way, imply that the XDQS signal is the only control signal in the control bus 19. Furthermore, as FIG. 2 is illustrative in nature, only two bits of data (D0 and D1) are shown being written into memory cells 26. It is evident to one skilled in the art that the circuit shown in FIG. 2 may be replicated (e.g., by adding additional flipflops) for each data pin and for transferring or writing more than two data bits, as needed.
In FIG. 2, an external data pin (XDQ) 18 is shown to carry data bits to be written into memory cells 26. Again, as in the case with the designation of the XDQS pin, the reference numeral "18" is conveniently used to refer to one of the data pins—the XDQ signal or pin, instead of the entire data bus 18. It is evident that many more such XDQ pins 18 constitute the data bus. The data bits over the XDQ pin 18 are supplied to two data flipflops 36, 38, which are "strobed" or clocked by the external data strobe signal (XDQS) 19. Typically, the externally supplied strobe signal—the XDQS signal 19—is first received at an input buffer 34 in the I/O unit 32. The Enable control 40 of the buffer 34 allows controlled application of the XDQS signal 19 to the flipflops 36, 38. When the Enable control 40 is turned "on" or "activated", the XDQS signal 19 is buffered through the buffer 34. On the other hand, turning "off" or deactivating the Enable control 40 may prevent further transmission of the XDQS signal 19 out of the buffer 34. In FIG. 2, the buffered XDQS signal 19 is designated as the DQS (data strobe) signal 39, which is the internal strobe signal that is used by the I/O unit 32 to strobe data on the XDQ pin 18 into appropriate memory cells 26. Thus, memory's internal data strobe signal (the DQS signal) 39 is derived from the external strobe signal XDQS 19. Further, as seen from the circuit configuration in FIG. 2, each of the data bits is output on one of the edges—rising edge or falling edge—of the DQS signal 39. Thus, the circuit configuration in FIG. 2 may be used to write data into a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) chip.
FIG. 3 depicts a typical XDQS signal 19 and an exemplary memory data write operation using the XDQS signal 19 as the data strobe signal. The XDQS signal 19, per its specification, may contain a preamble ringing 42 and a postamble ringing 44. Although the signals in the preamble and postamble ringings 42, 44 are shown as triangular waves, it is understood that these signals may have any form—sinusoidal, triangular, sawtooth, random etc. Further, as is known in the art, the signal level of the XDQS signal 19 during these pre- and post-amble ringings 42, 44, is undefined. However, after preamble ringing 42 is over, the XDQS signal 19 stabilizes and transitions in synchronism with the system clock (not shown). The lined portion in the data waveform in FIG. 3 indicates unknown state of the data pin. The data bits may be valid only during certain times. In FIG. 3, the data bits 0–4 on the external data pin (XDQ) 18 are shown to appear in appropriate timing relationship with the XDQS signal's rising and falling edges. The XDQS signal 19 may keep toggling (in synchronism with the system clock (not shown)) until all data bits are written. For example, in FIG. 3, only four data bits are to be written and, hence, the XDQS signal 19 remains "active" for two cycles to strobe four data bits into the memory cells 26—one data bit on each of the two rising and two falling edges.
As is known to one skilled in the art, the specification for the XDQS signal 19 defines a postamble time 46 as the time for which the XDQS signal 19 remains in a "low" state after the last bit of data (e.g., Bit 3 in FIG. 3) is clocked in. After the postamble time 46, however, the state of XDQS 19 is no longer guaranteed and it could assume any value. After the postamble time 46, the postamble ringing 44 may start and any such ringing on XDQS 19 may cause erroneous bits of data to be clocked in because the postamble ringing 44 may be erroneously recognized by the data latching flipflops (e.g., the flipflops 36 and 38 in FIG. 2) as valid data clocking edges (or edge transitions) of the XDQS signal 19. But, as shown in FIG. 3, during the postamble ringing period 44, the state of data signals on the data pin XDQ 18 is unknown because the last bit of data (e.g., Bit 3 in FIG. 3) is already written and there is no more data to write. Therefore, any triggering of data flipflops by postamble ringing will result in incorrect data bits to be written into memory cells.
To avoid accidental triggering of data flipflops 36, 38 during postamble ringing 44 (and, hence, to avoid incorrect data outputs to be sent to memory cells 26), the data writing circuitry in FIG. 2 turns "off" or deactivates the Enable control 40 during the postamble time 46 so as to effectively prevent the application of the XDQS signal 19 (and its postamble ringing 44) to the data flipflops 36, 38 via the DQS signal 39. Thus, the Enable control 40 prevents the DQS signal 39 from having the postamble ringing 44 of the XDQS signal 19. However, this approach may be well suited for slower speed DDR SDRAM memory chips, where the postamble time 46 may be in the range of 3–5 nanoseconds (ns). In the modern, faster DDR2 and DDR3 SDRAM chips, the clock periods of the system clocks themselves are in the range of 2.5 to 3 ns. Such DDR2 and DDR3 chips, in turn, require correspondingly shorter postamble time 46 because the postamble time 46 is typically equal to 0.4 tCK (where "tCK " represents the clock period of the system clock) per XDQS specification. Therefore, in such faster versions of DDR SDRAM chips, the postambe time 46 would be typically in the range of 1 to 1.2 ns. This time of 1–1.2 ns may be too short for the Enable control 40 to turn off the buffer 34 in time prior to onset of postamble ringing 44 because of the very high frequency of XDQS 19 and DQS 39 signals. The high frequency DQS signal 39 may be itself 0.25tCK early or late with reference to the system clock. Therefore, the effective time for the buffer 34 to act prior to postamble ringing 44 is even less than 1–1.2 ns.
It is thus seen that the current buffer-based control of DQS postamble ringing may not be effective in itself, especially when modern memory chips are operated at ever faster clock speeds. Therefore, it is desirable to devise a scheme whereby DQS postamble ringing problem in higher speed memory chips is significantly reduced or eliminated so that false data may not get "clocked in" or written into the memory chip because of postamble ringing. The prevention of data corruption and preservation of integrity of data written into a memory chip is also desirable.

Solution to DQS postamble ringing problem in memory chips


A permanent electrical contact applicable to the web of rails. The contact comprises a bush in electrically conductive material having a tubular stem suitable for inserting in a hole in the web of a rail, a flanged head radially widened compared to the stem and suitable for engaging in abutment with a portion surrounding the hole, and an axial through hole in which a punch can be inserted to expand the tubular stem radially and join a radially outer surface of the stem closely with the hole. At least a portion of the outer surface of the stem is substantially made of a first conductive metal and at least a portion of the flanged head is substantially made of a second conductive metal different from the first conductive metal.

1. Field of the Invention
The present invention relates to a permanent electrical contact applicable to the web or flange of rails and the like.
2. Description of the Related Art
As known, permanent electrical contacts for the electrical connection of sections of rail are required to have contact characteristics which reduce contact resistances and need to be structurally simple and robust. To such purpose, it is known to make permanent electrical contacts applicable to the web of a rail, by means of a bush in electrically conductive material having a cylindrical stem insertable in a hole made in the web of the rail and a flanged head suitable for engaging in abutment with the portion of rail surrounding the hole, wherein the bush has an axial through hole into which a punch can be inserted to generate a radial expansion of the cylindrical stem against the hole in the rail. Given its excellent mechanical characteristics (plastic deformation capacity and close engagement with the inner surface of the hole during the drawing of the material by means of the punch, elevated mechanical resistance and toughness) and electrical characteristics (high electric conductivity and electrogalvanic compatibility with steel), as well as its high resistance to corrosion, copper has up to today been the natural choice for making the contact bushes.
However, on account of the significant increase in the cost of copper and consequent frequent theft of conductors made from such metal, over recent years the use of electric conductors and connectors (so-called cable terminals) in aluminium has increased, the use of which however entails exposure to the environment of metals with different galvanic potential, such as copper and aluminium, with consequent risks of interstitial galvanic corrosion in the contact area between the aluminium connector and the contact bush in copper.
In order to overcome the problem of galvanic corrosion which could occur in the contact area between the aluminium and the copper, bi-metal connectors are currently sold on the market having a hollow seat in aluminium suitable for being compressed onto the conductor, as well as a terminal connection portion made of copper suitable for being connected in contact with a terminal, in which the hollow seat and the terminal connection portion are welded to each other.
Such solution, while resolving the problem of interstitial corrosion of the cable terminal in a satisfactory manner, is not without drawbacks. The manufacturing process of the single parts in aluminium and copper and their subsequent joining by welding is, on the one hand, complex and costly and, on the other, is not able to obtain a sufficiently reliable and resistant copper-aluminium connection for applications in which the connectors are subject to vibrations.

Permanent electrical contact applicable to the web of rails and the like


The present invention is a tubular structure which inflates upon side or oblique impact to protect the occupants of a vehicle such as an automobile. The structure is mounted in its undeployed state along the periphery of the vehicle's window. The primary component of the present invention is a braided tube containing a gas generator. When a side impact is detected, the gas generator is ignited, inflating the braided tube. As the braided tube inflates, the diameter of the tube increases and its length decreases. The tube then pulls out of its storage location and forms a taut, semi-rigid structural member across the vehicle's window.

1. Field of the Invention
The present invention relates to safety apparatus for protecting the head and neck of the occupant of a motor vehicle to reduce the extent and severity of injuries sustained during a side impact crash. More specifically, it relates to a system of components that inflate to cushion the head and neck from direct impact with the interior structure of the vehicle.
2. Background of the Invention
Side or lateral impacts are a leading cause of injuries and fatalities in automotive crashes. According to the Insurance Institute for Highway Safety (IIHS), 30 percent of all automobile occupant fatalities in the United States in 1989 involved side impact crashes.
Occupants killed in side impact crashes typically have a high incidence of head and neck injuries. Side impact crashes also cause severe injuries to other body regions including the chest, abdomen, pelvis and extremities. FIG. 1 summarizes the distribution of injuries by body region, based on an IIHS study of 91 struck-side and 49 opposite-side fatalities in the United Kingdom in 1985. FIG. 1 shows the distribution of greater than 3 on the Abbreviated Injury Scale (AIS) by body region for fatalities in struck-side and opposite-side crashes. "Struck-side" refers to occupants seated on the side of the vehicle that was struck, while "opposite-side" refers to occupants who were seated on the side that was not struck. According to the IIHS study, 64% of struck-side occupants suffered head injuries; 12% suffered neck injuries; 85% suffered chest injuries; 26% suffered pelvis injuries; 2% suffered injuries to their upper limbs and 21% to their lower limbs; and 59% suffered abdomen injuries. FIG. 1 also shows that 82% of opposite-side occupants suffered head injuries; 20% suffered neck injuries; 73% suffered chest injuries; 14% suffered pelvis injuries; 10% suffered injuries to their upper limbs and 12% suffered injuries to their lower limbs; and 49% suffered abdomen injuries. FIG. 1 shows that serious head and neck injuries can occur in either seating position.
Conventional automotive safety belt and air bag systems offer inadequate protection to the head and neck in side impact crashes. These systems are generally designed to protect occupants from primary injuries sustained only in frontal impacts, or in oblique impacts up to approximately +/-30 degrees.
Federal Motor Vehicle Safety Standard (FMVSS) 214 currently defines the test procedures and performance requirements for occupant protection in side impact crashes. The dynamic requirements of FMVSS 214 are scheduled to be phased into practice based on an escalating percentage of each manufacturer's annual production starting Sep. 1, 1993.
In response to FMVSS 214, several developments in side impact countermeasures have occurred. These countermeasures primarily include the reinforcement of side components and door structures with improved door beams, modified pillars, and improved energy-absorbing door padding.
All of these developments in response to FMVSS 214 focus on limiting the intrusion of an object into the passenger compartment. Additionally, energy-absorbing padding helps distribute the impact force to the struck-side occupant over a larger surface area. An excellent production example of these technologies is the side impact protection system incorporated into current Volvo automobiles which carries door beam loads through the front seats into a center tunnel structure.
Another countermeasure recently being considered by several vehicle manufacturers are air bags that deploy from the door panel to provide protection for the thorax, abdomen and pelvic regions. These systems help distribute the impact force over a larger body surface area to reduce the extent and severity of injuries sustained during a side impact crash. However, these systems are not expected to provide significant protection to the head, face and neck. Therefore, as increasing numbers of vehicles are equipped with these countermeasures, head injuries will likely emerge as the predominant injury in all side impact crashes.
There are three major causes of head, neck, and face injuries in side impact crashes:
(1) The head and neck regions strike the upper interior side components of the vehicle. These components include the upper door frame, the A and B-pillars, the roof rail and the upper door frame. FIG. 2 shows the relative positions of A-pillar 20, B-pillar 21, roof rail 23, and upper door frame 25.
(2) The head and neck regions collide with the striking (or struck) object.
(3) The head flailing through the window frame. Typically, the side window is shattered early in the impact, and is therefore not a strike hazard. However, the head of the occupant is not restrained inside the passenger compartment. Moreover, the window cannot be used as a load bearing surface for a conventional type of air bag.
In light of these potential dangers, an effective side impact head and neck protection system must prevent or cushion the head from directly colliding with the upper side components of a vehicle, cushion or prevent the head and neck from directly being impacted by the striking or struck object, and restrain the head inside the confines of the vehicle.

Side impact head strike protection system


In various examples, object fence corresponding to objects detected by an ego-vehicle may be used to determine overlap of the object fences with lanes on a driving surface. A lane mask may be generated corresponding to the lanes on the driving surface, and the object fences may be compared to the lanes of the lane mask to determine the overlap. Where an object fence is located in more than one lane, a boundary scoring approach may be used to determine a ratio of overlap of the boundary fence, and thus the object, with each of the lanes. The overlap with one or more lanes for each object may be used to determine lane assignments for the objects, and the lane assignments may be used by the ego-vehicle to determine a path or trajectory along the driving surface.

Autonomous driving systems and advanced driver assistance systems (ADAS) may leverage sensors, such as cameras, to perform various tasks—such as lane keeping, lane changing, lane assignment, camera calibration, and localization. For example, for autonomous and ADAS systems to operate independently and efficiently, an understanding of the surrounding environment of the vehicle—in real-time or near real-time—may be generated. This understanding may include information as to locations of objects and/or obstacles in the environment with respect to various demarcations—such as lanes, road boundaries, intersections, and/or the like. The information of the surrounding environment may be used by a vehicle when making decisions, such as what path or trajectory to follow, whether to speed up or slow down, whether a lane change or other maneuver is currently safe, etc.
In conventional systems, lane (or other location) assignments for objects (e.g., vehicles, pedestrians, etc.) may be interpolated from real-time images processed using various computer vision or machine learning techniques (e.g., from visual indicators identified via image processing). For example, images captured of a driving surface including lanes and vehicles may be analyzed to determine correlations between the vehicles and the lanes. However, because an entire vehicle's interactions with lanes may be used, the actual lanes of travel of the vehicle may be inaccurately identified in conventional systems. For example, in image space, and dependent on the perspective of the camera, a vehicle may appear to extend into an adjacent lane (e.g., when a camera has a perspective of a vehicle to its left, the top of the vehicle may appear to extend into left adjacent lanes of the vehicle) even when the vehicle is actually in a single lane. This may not provide the most accurate results for use by the autonomous and/or ADAS systems when attempting to understand the surrounding environment—thereby decreasing the overall effectiveness and reliability of this environmental information.

Leveraging obstacle and lane detections to determine lane assignments for objects in an environment


A message transmission method for a mobile communication terminal is includes the steps of: inputting a message including a plurality of unit messages; matching a unit message to a receiver address; and transmitting the matched unit message to a mobile communication terminal having the particular receiver address identified by an identification symbol. The method may transmit a message pre-stored in a mobile communication terminal. The method reduces the time required for group transmission because the mobile communication terminal transmits different messages individually to a plurality of receivers by using unit messages newly input or pre-stored in the mobile communication terminal.

1. Field of the Invention
The present invention relates to a message transmission method for a mobile communication terminal. More particularly, the present invention relates to a message transmission method for a mobile communication terminal enabling transmission of different messages individually to a plurality of receivers by using unit messages.
2. Description of the Related Art
With developments in mobile communication technology, the capabilities of mobile communication terminals include the ability to provide voice communications with few restrictions regarding time and location. In addition to voice communications, various functions, such as character information service, image information service, MP3, and games have been added to capabilities of many mobile communication terminals, and a user may freely select a desired function.
As the popularity of mobile communication terminals has increased, so has the popularity of using a short message service (SMS) to transmit a message to a receiver, regardless of an operating status of a receiving mobile communication terminal. SMS is also popular because it is a wireless call service enabling transmission of a user-created message to another party at a low cost.
In addition, (MMS) a multimedia messaging service has become an increasing popular method to transmit and receive various types of data, such as voice, music, still image, and moving pictures.
The methods for message transmission may be divided into a single transmission and a group transmission. The single transmission method is typically used for transmitting a message to a receiver. The group transmission method is typically used for transmitting a message to a plurality of receivers simultaneously.
However, one drawback of the conventional group transmission method is that an identical message is transmitted to a plurality of receivers. Therefore, the conventional group transmission method is not suitable for transmitting different messages individually to a plurality of receivers.
Moreover, when there is a need to transmit different messages individually to a plurality of receivers, the single message transmission method must be used repeatedly to transmit different messages individually to a plurality of receivers. Accordingly, the user is often inconvenienced by having to prepare and transmit each different message repeatedly to the plurality of receivers. Additionally, more time is required to transmit the messages.

Message transmission method for a mobile communication terminal

Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do


A projection apparatus arranged such that the first light source, the second light source and the third light source provide the first colored light, the second colored light and the third colored light, respectively. The first digital micromirror device (DMD) modulates and reflects the first colored light, while the second DMD modulates and reflects the second and third colored lights guided by the first light guiding device. Subsequently, the second light guiding device guides the colored lights reflected from the first DMD and the second DMD to the projection lens.

1. Field of the Invention
The present invention relates to a projection apparatus that uses two digital micromirror devices (DMDs) and adopts light emitting diodes (LEDs) as the light source.
2. Descriptions of the Related Art
Currently, projection apparatuses have found a widespread use in offices, households, conference rooms and the like as imaging devices. Among various projection apparatuses, the digital light processing (DLP) projection apparatus, which applies both digital projection and display technologies, is capable of receiving a digital signal to generate a sequence of digital light pulses. The main concept of the DLP technology is to use a digital micromirror device (DMD) with a plurality of micromirrors, so that the light projected on these micromirrors will be reflected onto an imaging lens to form an image.
A projection apparatus can use three DMDs for each of the three primary colors to achieve a luminance of up to several thousands lumens and a high resolution. However, the expensive DMDs and more optical elements are required for achieving the desired effect tend to increase the cost of the product significantly. On the other hand, reducing the number of DMDs may reduce costs, but will degrade the luminance and resolution thereof. Therefore, a projection apparatus with two DMDs that have satisfactory optical efficiency has been developed in the art.
A conventional DLP projection apparatus comprising two DMDs is depicted in FIG. 1. The projection apparatus 1 mainly comprises a light source 11, a color wheel 14, a total internal reflection (TIR) prism 15, two DMDs 16a, 16b, a dichroic mirror 17, and a projection lens 18. The light source 11 is generally an ultra high pressure (UHP) mercury lamp. In more detail, light emitted from the light source 11 is converted into two kinds of colors by two kinds of segments of the color wheel 14. After entering the TIR prism 15, the light beams of two kinds of colors are further separated by the dichroic mirror 17 into three primary colors and projected onto the two DMDs 16a, 16b. Since the UHP mercury lamp has a poor red light spectrum, one DMD 16a is used for red color and the other DMD 16b is used for green and blue colors. Upon reflection from the DMDs 16a, 16b, the light beams are recombined and projected out of the projection lens 18 through the TIR prism 15.
However, a conventional DLP projection apparatus that employs a UHP mercury lamp as the light source 11 suffers from a number of disadvantages. Since the UHP mercury lamp relies on the excitation of mercury to generate ultraviolet light and thereby to provide a light source with high luminance, it takes a long time for the luminance to increase to the desired level. Furthermore, to generate light beams of the three primary colors, a color wheel has to be used in conjunction with the UHP mercury lamp, which may decrease the service life, be difficult to replace, decrease the color gamut, pollute the environment, consume power, and occupy a large space.
In summary, a conventional projection apparatus using two DMDs and an UHP mercury lamp is still deficient in performance, heat dissipation, and color gamut. In view of this, it is important to provide a projection apparatus that uses two DMDs and has a higher efficiency, wider color gamut, smaller profile, simpler structure, more inexpensive cost, and reduced starting time.

Dual DMD projector having a modular heat dissipation device


A rotary actuator including a housing provided with a fluid actuated drive assembly operatively connected to a rotary plate arranged to effect the drive thereof, wherein the housing and the rotary plate are provided with complementary cooperating stop abutment and groove or track for limiting the angular rotation of the rotary plate in either the clockwise or counterclockwise rotation. An adjustment is provided to adjust the angular rotation of the rotary plate. Also provided is a control or adjustment for independently regulating the speed of rotation of the rotary plate either in the clockwise or counterclockwise rotation.

Heretofore, the known rotary actuators utilized an air driven piston and cylinder drive assembly for driving a pinion gear operatively connected to a rotary plate. In such known actuators, the angular rotation of the rotary plate was determined by the piston engaging a stop to limit the stroke of the piston and thus determining the degree of angular rotation of the rotary plate. However, it has been noted that abruptly limiting or stopping the stroke of the piston by a stop imposed severe impact on the meshing gear teeth of a complementary pinion gear and associated piston rack which, over time, introduced considerable play or backlash and/or damage to the meshing gear teeth to result in greatly reducing the accuracy or precision of the rotary actuator and/or the useful life of the rotary actuator.


A method for manufacturing an integrated circuit, a measurement apparatus of an integrated circuit, and a wafer that reduces damages inflicted on bonding pads while enabling a probe test to be accurately performed. A sensor cell is arranged on a wafer between chip formation regions. The sensor cell has a diaphragm. Sensor pads, connected to a doping region, are arranged on the surface of the diaphragm. Probe needles contact the sensor pads. This strains the doping region and produces a corresponding voltage measured by the probe needles connected to the sensor pads. Relative inclination angle and relative distance of a probe card, which includes the probe needles, and the wafer are determined based on the measured voltage. A conduction test is performed by having the probe needles contact the bonding pad of the wafer while maintaining the determined the relative position.

The present invention relates to a method for manufacturing an integrated circuit, a measurement apparatus for an integrated circuit, and a wafer.
Presently, integrated circuits are used in a variety of applications. In order to improve the productivity of integrated circuits, a plurality of integrated circuit chips are simultaneously manufactured on a single wafer. More specifically, devices and wiring patterns for a plurality of integrated circuits are formed on a wafer. Then, a dicing process is performed to divide the wafer into a plurality of chips to form the integrated circuits. Before dividing the wafer into chips, each integrated circuit undergoes a conduction test, which is referred to as a probe test.
A typical probe test is conducted by pressing a probe needle against a bonding pad of the chip so as to test the operation of the chip. Contact between the probe needle and the bonding pad must be ensured during the probe test to reduce contact resistance between the bonding pad and the probe needle. However, the bonding pad may be damaged if the probe needle is pressed too hard against the bonding pad. Therefore, research has been carried out to develop a method for manufacturing a semiconductor that avoids damaging of the bonding pad during the probe test (refer to, for example, Japanese Laid-Open Patent Publication No. 8-306751).
In the invention described in Japanese Laid-Open Patent Publication No. 8-306751, a probe pad is arranged in a region between chips along a scribe line. The probe pad is connected to a bonding pad by a wire. A probe needle is pressed against the probe pad to conduct the probe test through the bonding pad. This prevents the bonding pad of the chip from being damaged even if the pressure of the probe needle damages the probe pad.
However, in the invention of Japanese Laid-Open Patent Publication No. 8-306751, the probe pad is connected to the bonding pad by a wire. Therefore, capacitance generated between the substrate and a wire or bonding pad may interfere and lower measurement accuracy. The influence of such capacitance is particularly prominent when conducting a probe test with high-frequency waves.

Method for testing integrated circuit, and wafer


Provided is a metal coated steel sheet having a coating layer including a metal having a level of Gibbs free energy equal to that of Fe or above and an oxide thereof. Accordingly, the quality of a plated steel sheet may be improved by preventing the generation of bare spots through inhibition of the formation of Mn oxide, Si oxide, or Al oxide on the surface thereof, and simultaneously, the complexity of a manufacturing facility or an increase in manufacturing costs may be minimized. Economic benefits are thus realized.

Hot-dip galvanized steel sheets have been widely used in automobiles, building materials, various structures, and household appliances due to having excellent corrosion resistance properties, and in particular, the high strengthening of steel sheets has been continuously undertaken in line with recent demands for weight reductions in vehicles. However, since the ductility of steel sheets relatively decreases when the strength thereof is increased, high-strength steels having improved ductility, such as dual phase (DP) steels having manganese (Mn), silicon (Si), or aluminum (Al) added to a base steel sheet, complex phase (CP) steels, and transformation induced plasticity (TRIP) steels, have been manufactured.
However, Mn, Si, or Al, added to steel sheets, may react with a trace of oxygen existed in an annealing furnace to form a single or complex oxide of Si, Mn, or Al, and thus, bare spots may be generated to degrade surface qualities of the plated steel sheet.
As a typical method for addressing the foregoing limitations, Japanese Patent Application Laid-Open Publication No. 2005-200690 discloses a technique in which a base steel sheet is coated with metal, such as nickel (Ni), after annealing and cooling to cover Mn oxide, Si oxide, or Al oxide formed on a surface thereof during annealing with the metal coating layer. In general, a continuous hot-dip galvanizing process is integrally configured in order to maintain a reducing atmosphere from an annealing process to a galvanizing process. However, with respect to the above technique, the annealing and galvanizing processes must be separated in order to allow for an annealing process before the metal coating process, and thus, a manufacturing facility may be complicated and manufacturing costs may be increased.
As another typical method for addressing the foregoing limitations, there is provided a technique, in which metal coating is performed in advance, and annealing and plating are subsequently performed. However, in the case that a temperature of 750° C. or above is used during annealing, the coated metallic materials may be diffused into a base steel sheet to this dissipate or thin a metal coating layer, and thus, there may be limitations in substantially preventing the surface diffusion of Mn, Si, or Al.
Therefore, the need for a economical technique, allowing for the surface qualities of a plated steel sheet to be improved by preventing the generation of bare spots through the inhibition of the formation of Mn oxide, Si oxide, or Al oxide on the surface of the steel sheet, has rapidly increased.


A thrust aid device to permit a bicycle rider to apply increased thrust to the pedals of the bicycle. The thrust aid device comprises an elongated mounting member having one end adapted to be fastened to the seat post of a bicycle and a movable thrust arm connected to the opposite end of the mounting member. The thrust arm is selectively movable between a first storage position and a second raised and operable position wherein the rider can push his or her hips against the thrust arm in the second position while pedaling in order to apply increased thrust to the pedals. One preferred embodiment has a vertically oriented sleeve in which the thrust arm slides between a retracted position and a raised operating position. The rider pushes the thrust arm down to move it to the retracted or storage position. A spring raises the thrust arm to the operating position when a latch is actuated. Another preferred embodiment has a rotary joint where the rider pushes the arm down to disengage a slot and then rotate the arm rearward to a storage position.

1. Field of the Invention
This invention generally relates to bicycles and more particularly to an aid for increasing leg thrust that can be applied to the pedals by the bicycle rider while seated on the bicycle seat.
2. Description of the Related Art
Mountain bikes have been developed over the past ten years particularly for use off and on normal bike paths and roadways. These bicycles are particularly sturdy. They must be capable of being ridden over all types of terrain. In navigating such terrain, the rider often must stand on the pedals and position his or her weight ahead of or behind the saddle or seat. In this latter instance, the rider must be able to clear the seat easily. Thus narrow seats are preferred as opposed to the wide, cushioned seats often found on older model touring or recreational bicycles. The mountain bike rider also must go up much steeper slopes than most road bikes are designed for. Such slopes require very low gearing and substantial thrust applied to the pedals.
Thrust aids for use by a bicycle rider to enhance his or her leg thrust applied to the pedals have been proposed in several patents. U.S. Pat. No. 4,909,5306 discloses a short, contoured back support which is adapted to be attached to the contoured sides of the bicycle seat. This support projects above the rear of the seat several inches. U.S. Pat. No. 4,363,516 discloses an inverted U shaped thrust support which has its free legs fastened to the rails which support the bicycle seat on the seat post. This thrust support also projects upward behind the seat several inches.
Both of these supports are relatively permanently attached to the bicycle seat and because they project up above the seat, they preclude the rider positioning his or her weight well to the rear of the seat as may often be necessary on downhill runs on a mountain bike. Thus these supports, while effective to assist in applying maximum thrust to the pedals while sitting on the seat, are effectively unusable on mountain bikes. Other back rests and supports are disclosed in U.S. Pat. Nos. 4,475,770; 3,901,534; and 1,190,8312. None of these back rests are designed as an aid to the rider in applying force to the pedals. Accordingly, there is a need for a thrust support for a bicycle which can be readily utilized on mountain bikes. There is also a need for a thrust support which does not hinder the rider in negotiating downhill portions of a trail and still provide substantial support for leg thrusts while the rider is seated.


A system and a method generate a device user interface executable by an information handling system. A device database includes a list of devices for which user interface components are available to implement functions for controlling the devices, and a resource database includes the user interface components. The device to be controlled by the user interface is identified and compared to a database of devices for which user interface resource components are available. A user interface generator determines whether the device is included in the device database and retrieves the user interface components from the resource database. A layout manager assembles the user interface components into a user interface. If the device is not listed, generic device user interface components are retrieved, otherwise device specific user interface components are retrieved, and assembled into a layout matrix. The user interface is created from the layout matrix.

Information handling systems are increasingly utilized as a central control unit for multimedia devices. Typical multimedia devices include media players such as audio amplifiers, receivers, videocassette recorders (VCRs), compact disc (CD) players, digital versatile disc (DVD) players, audio equalizers, audio and video processing systems, etc. Since multimedia devices are manufactured by a variety of manufacturers, many features offered by the manufacturer of one type of media device are not included with the same type of device from a different manufacturer. Further, the same manufacturer of multiple models of the same type of media device does not always provide the same features and functions for all of those devices. Therefore, only a common denominator of functions exists in each of a single type of media device. For example, the common denominator for VCR devices includes the "play", "stop", "pause", "fast forward" and "rewind" functions. Other functions may or may not exist on any particular media device.
Existing user interfaces for managing multimedia devices with an information handling system are forced into only providing the common denominator functions for a given category of devices. As a result, these user interfaces cannot exploit the rich variety of features and functions included with many of the latest models of media devices, thereby limiting the usefulness of managing the multimedia devices with an information handling system. Thus, there lies a need for a user interface which is capable of providing control of all, or nearly all, of the available functions of multimedia devices beyond the common denominator functions of the category of media devices.

Method and apparatus for automatically generating a device user interface


A three piece tool for reassembly and disassembly of poppet valve spring assemblies which are set inside bores in engines. The tool includes a tubular part that closely fits the engine bore, slides down and around the spring assembly, and contacts the top of a washer of the spring assembly. Compression, using a C-clamp or like tool, forces the tubular member, and the washer, downward and allows the keepers to be removed from the valve stem. Release of the compression allows the spring assembly to be disassembled. Reassembly is accomplished using the tubular member with a liner and a plunger. With the keepers, springs and washer positioned, the tubular part, with a liner and plunger, is inserted into the bore and the tubular member pushed downward to compress the springs. The plunger serves to move the keepers into their operational position so that release of the force on the tube relocks the spring assembly into its operational position.

It is necessary to disassemble and reassemble poppet valves in engine cylinder heads when rebuilding the engine and regrinding the valves and for other purposes such as replacing a broken or worn part. Many modern small engines have the spring assembly (spring/retainer washer/keeper and valve stem) recessed within a bore in the engine cylinder head. Recessed valve assemblies were designed to have less moving parts and to downsize engines. The cam rides directly above valves so there is no need for a rocker arm assembly or push rods. Lifters ride directly on top of the valve and the cams are seated oil top of the lifters. However, this compact arrangement makes it more difficult to disassemble and reassemble the valve for repair or replacement. U.S. Pat. No. 5,207,196 illustrates this type of compact engine cylinder head and one tool for inserting a preassembled valve unit when constructing the engine, as in the initial assembly of the engine at the factory.
While a number of tools have been proposed for use on earlier, more easily accessible valve stem assemblies (such as U.S. Pat. Nos. 5,375,308; 4,304,035; and 4,667,388) there exists a need for a simple tool that can allow the quick and easy disassembly, and aid in the more important and more difficult task of reassembly, of a bore-surrounded valve stem assembly at the repair shop without the need of using a preassembled total replacement unit.


In a semiconductor gate circuit, an MOS transistor having a low threshold voltage and a standard MOS transistor having threshold voltages of large absolute values are connected in series between an output node and a power supply node. The MOS transistor having the threshold voltage of the large absolute value receives on a gate thereof, a signal preceding in phase a signal applied to a gate of the MOS transistor having the small threshold voltage. In the semiconductor gate circuit, a dependency of input/output characteristics on a power supply voltage is small, and a leak current during standby is reduced. The standard MOS transistor turns on prior to turning on of the low threshold voltage MOS transistor, and turns off when the low threshold voltage MOS transistor turns off. The output node driving current is controlled by the low threshold voltage MOS transistor while a subthreshold leak current is suppressed by the standard transistor. A gate circuit having a small dependency of an input/output characteristics on the power supply voltage is implemented without increasing the power consumption.

1. Field of the Invention
The present invention relates to a semiconductor gate circuit for effecting a predetermined processing on an applied signal for outputting, and in particular to a buffer circuit or a delay circuit in which rising and falling times of an output signal or a delay time thereof has a reduced dependency on a power supply voltage.
2. Description of the Background Art
Portable information equipments have recently been widely used. Many portable information equipments use batteries as their power sources. Therefore, elements used in such a portable information equipment are required to operate fast for a long time with a small number of batteries. In a semiconductor device, however, if the power supply voltage is simply lowered for reducing the power consumption without changing a conventional circuit structure, a current driving capability of a MOS transistor (insulated gate field-effect transistor) abruptly lowers, and therefore an operation speed of the element significantly lowers. This results in significant increase in an access time, if the semiconductor device is a memory. In order to suppress lowering of the current driving capability, it is necessary to reduce an absolute value of a threshold voltage of the MOS transistor in accordance with lowering of the power supply voltage so that the operation speed of the MOS transistor may not lower even with a low power supply voltage. In the case of a low power consumption SRAM (Static Random Access Memory), however, there is a strict restriction on a current during standby (that a standby current must be about 1 .mu.A), so that even a leak current alone which flows through an off state MOS transistor exceeds a specification value if measures other than reduction in absolute value of the threshold voltage are not employed. This is due to a subthreshold current of the MOS transistor. The subthreshold current is a current which flows when Et gate to source voltage lowers to or below the threshold voltage (in the case of the n-channel MOS transistor).
FIG. 43 shows a relationship between a gate-source voltage Vgs and a drain current Ids in a subthreshold region of an n-channel MOS transistor. In FIG. 43, the abscissa gives gate-source voltage Vgs, and the ordinate gives, on a logarithmic scale, the drain current Ids. The subthreshold region is a region in which curves S1 and S2 extend straight. The drain current exponentially lowers in accordance with a difference between the gate voltage and the threshold voltage. Threshold voltage Vth of the MOS transistor is defined as a gate-source voltage which causes flow of a predetermined current Ith in a MOS transistor having a predetermined gate width. Therefore, the MOS transistor having drain current characteristics represented by curve Si in FIG. 43 has the threshold voltage of Vtha. If the threshold voltage of MOS transistor is lowered from Vtha to Vthb, characteristics represented by curve S2 is obtained. When the MOS transistor is off, the gate-source voltage Vgs is 0V, and a current I0 flows in the MOS transistor having threshold voltage Vtha, while a current I1 flows in the MOS transistor having threshold voltage Vthb. In the n-channel MOS transistor, therefore, the leak current (subthreshold current) in the off state increases with decrease in threshold voltage. For example, when threshold voltage Vth lowers by 0.3 V, the leak current of the MOS transistor increases 1000 times, resulting in flow of a leak current larger than the standby leak current prescribed in the specification.
In an inverter buffer using MOS transistors, if a only standard MOS transistors, i.e., MOS transistors having threshold voltages of ordinary absolute values are employed, the current consumption during standby can be reduced, but rising and falling times of an output signal increase during an operation with a low power supply voltage due to lowering of the current driving capability of the MOS transistors during the operation with the low power supply voltage. This impairs the input/output characteristics. Particularly in a delay circuit formed of a plurality of cascaded inverter buffers, a dependency of a delay time on the power supply voltage increases during the operation with the low power supply voltage, so that it is impossible to change internal signals at desired timings. For use with a low power supply voltage, therefore, a semiconductor gate circuit such as an inverter buffer or a delay circuit is required to satisfy the following two conditions.
1. A drive current value is determined by a low-Vth transistor, i.e., a MOS transistor of which threshold voltage is reduced in absolute value in accordance with lowering of the power supply voltage and of which current driving capability does not significantly lower even with a low power supply voltage.
2. During standby, a leak current hardly flows. Thus, a standard MOS transistor is necessarily arranged at every current path, and this MOS transistor is held in the off state during standby.
FIG. 44 shows an example of a structure of a conventional delay circuit which has been devised to satisfy the foregoing two conditions. In FIG. 44, the delay circuit includes four cascaded inverters IV1, IV2, IV3 and IV4. Each of inverters IV1-IV4 operates receiving as operation power supply voltages a power supply voltage on a power supply node 1 and a ground voltage on a ground node 2. Each of inverters IV1-IV4 includes a p-channel MOS transistor PQL and an n-channel MOS transistor NQL which are connected in series between power supply node 1 and a common node 3 and each receive on its gate an input signal IN or an output signal of the inverter at the immediately preceding stage. MOS transistors PQL and NQL have threshold voltages of small absolute values, respectively.
The delay circuit includes an n-channel MOS transistor NQS, which is selectively turned on in response to control signal .phi.ACT, and thereby electrically connects common node 3 to ground node 2. This MOS transistor NQS is a standard MOS transistor having threshold voltage larger in absolute value than threshold voltages of MOS transistors PQL and NQL. Control signal .phi.ACT specifies a standby cycle and an active cycle in a semiconductor device using this delay circuit. An operation of the delay circuit shown in FIG. 44 will be described below with reference to a signal waveform diagram shown in FIG. 45. During standby, control signal .phi.ACT is at the ground voltage level or L-level, and MOS transistor NQS is off. Thereby, common node 3 is electrically isolated from ground node 2.
MOS transistor NQS has a high threshold voltage, and therefore hardly causes a leak current flowing from common node 3 to ground node 2. In this standby cycle, input signal IN maintains a certain logical level. FIG. 45 shows a signal waveform in the case that input signal IN is fixed to H-level. When input signal IN is at H-level, p- and n-channel MOS transistors PQL and NQL in inverter IV1 are off and on, respectively. In this state, a leak current flows from power supply node 1 to common node 3 through p- and n-channel MOS transistors PQL and NQL. However, MOS transistor NQS is off, so that the leak current flowing into common node 3 does not flow to ground node 2.
In this standby cycle, output signal OUT is held at H-level because the potential on common node 3 rises by the leak current. When input signal IN is at L-level, MOS transistors PQL and NQL in inverter IV1 are on and off, respectively. However, output signal OUT is held at H-level because the leak current likewise flows.
In the active cycle, input signal IN changes in accordance with an operations of another circuit or an externally applied signal. In this active cycle, control signal .phi.ACT is set to the power supply voltage level, i.e., H-level, and MOS transistor NQS is on, so that common node 3 is electrically connected to ground node 2, and common node 3 attains the ground voltage level. In accordance with change of input signal IN from H-level to L-level, output signal OUT falls from H-level to L-level after elapsing of a delay time TD determined by inverters IV1-IV4. When input signal IN rises from L-level to H-level, output signal OUT rises from L-level to H-level after elapsing of a delay time TD'.
When the delay circuit shown in FIG. 44 is used, the operation is performed as follows. While this delay circuit is in a standby state, common node 3 is electrically isolated from ground node 2, so that there is no current path from power supply node 1 to ground node 2. Therefore, leak current IL during standby can be sufficiently suppressed even if low-Vth MOS transistors are used in the inverter circuits. In the active cycle, since common node 3 is set to the ground voltage level, low-Vth MOS transistors PQL and NQL in each of inverters IV1-IV4 are on and off complementarily, so that, even with the low power supply voltage, the output node can be driven with a current driving capability of a magnitude similar to that under a normal power supply voltage, and output signal OUT can be changed in accordance with input signal IN at high speed.
FIG. 46 schematically shows an arrangement of delay circuits in a conventional semiconductor device. In FIG. 46, a semiconductor device SD includes delay circuits DL1, DL2 and DL3 arranged dispersedly. Delay circuits DL1, DL2 and DL3 delay signals .phi.1, .phi.2 and .phi.3 for outputting the same, respectively. Each of delay circuits DL1-DL3 has the same structure as that shown in FIG. 44. However, delay circuits DL1-DL3 may have different delay times, respectively. Delay circuits DL1-DL3 are dispersed to occupy optimum positions in the device in accordance with contents of processing, i.e., signals .phi.1-.phi.3 applied thereto, respectively.
Control signal generating circuit CG generating control signal .phi.ACT must apply control signal .phi.ACT to each of delay circuits DL1-DL3. Therefore, a signal line SGL arranged between control signal generating circuit CG and delay circuits DL1-DL3 extends over a long distance in semiconductor device SD, so that signal line SGL has a large interconnection resistance and a large parasitic capacitance. Therefore, control signal .phi.ACT changes slowly, and delay circuits DL1-DL3 cannot be driven fast, so that response of delay circuits DL1-DL3 is slowed down during changes from the standby cycle to the active cycle and vice versa, which reduces an effect of reducing a current consumption. It is necessary to delay the operation start timings of delay circuits DL1-DL3 in accordance with a delay of control signal .phi.ACT, so that a fast operation cannot be achieved.
Control signal generating circuit CG must rapidly drive the gates of power-cut MOS transistors, i.e., MOS transistors for cutting off the power included in delay circuits DL1-DL3 as well as signal line SGL. This results in a problem that fast driving of the large load requires a large current consumption.
The above problem arises in not only the delay circuits but also a buffer circuit for buffering an applied signal. This is because an inverter buffer is achieved if only inverter IV1 at the initial stage in the delay circuit shown in FIG. 44 is employed.

Semiconductor gate circuit having reduced dependency of input/output characteristics on power supply voltage


The ability to combine multiple audio signals captured from the microphones in a microphone array is frequently used in beamforming systems. Typically, beamforming involves processing the output audio signals of the microphone array in such a way as to make the microphone array act as a highly directional microphone. In other words, beamforming provides a “listening beam” which points to a particular sound source while often filtering out other sounds. A “generic beamformer,” as described herein automatically designs a set of beams (i.e., beamforming) that cover a desired angular space range within a prescribed search area. Beam design is a function of microphone geometry and operational characteristics, and also of noise models of the environment around the microphone array. One advantage of the generic beamformer is that it is applicable to any microphone array geometry and microphone type.

1. Technical Field
The invention is related to finding the direction to a sound source in a prescribed search area using a beamsteering approach with a microphone array, and in particular, to a system and method that provides automatic beamforming design for any microphone array geometry and for any type of microphone.
2. Background Art
Localization of a sound source or direction within a prescribed region is an important element of many systems. For example, a number of conventional audio conferencing applications use microphone arrays with conventional sound source localization (SSL) to enable speech or sound originating from a particular point or direction to be effectively isolated and processed as desired.
For example, conventional microphone arrays typically include an arrangement of microphones in some predetermined layout. These microphones are generally used to simultaneously capture sound waves from various directions and originating from different points in space. Conventional techniques such as SSL are then used to process these signals for localizing the source of the sound waves and for reducing noise. One type of conventional SSL processing uses beamsteering techniques for finding the direction to a particular sound source. In other words, beamsteering techniques are used to combine the signals from all microphones in such a way as to make the microphone array act as a highly directional microphone, pointing a "listening beam" to the sound source. Sound capture is then attenuated for sounds coming from directions outside that beam. Such techniques allow the microphone array to suppress a portion of ambient noises and reverberated waves (generated by reflections of sound on walls and objects in the room), and thus providing a higher signal to noise ratio (SNR) for sound signals originating from within the target beam.
Beamsteering typically allows beams to be steered or targeted to provide sound capture within a desired spatial area or region, thereby improving the signal-to-noise ratio (SNR) of the sounds recorded from that region. Therefore, beamsteering plays an important role in spatial filtering, i.e., pointing a "beam" to the sound source and suppressing any noises coming from other directions. In some cases the direction to the sound source is used for speaker tracking and post-processing of recorded audio signals. In the context of a video conferencing system, speaker tracking is often used for dynamically directing a video camera toward the person speaking.
In general, as is well known to those skilled in the art, beamsteering involves the use of beamforming techniques for forming a set of beams designed to cover particular angular regions within a prescribed area. A beamformer is basically a spatial filter that operates on the output of an array of sensors, such as microphones, in order to enhance the amplitude of a coherent wavefront relative to background noise and directional interference. A set of signal processing operators (usually linear filters) is then applied to the signals form each sensor, and the outputs of those filters are combined to form beams, which are pointed, or steered, to reinforce inputs from particular angular regions and attenuate inputs from other angular regions.
The "pointing direction" of the steered beam is often referred to as the maximum or main response angle (MRA), and can be arbitrarily chosen for the beams. In other words, beamforming techniques are used to process the input from multiple sensors to create a set of steerable beams having a narrow angular response area in a desired direction (the MRA). Consequently, when a sound is received from within a given beam, the direction of that sound is known (i.e., SSL), and sounds emanating from other beams may be filtered or otherwise processed, as desired.
One class of conventional beamforming algorithms attempts to provide optimal noise suppression by finding parametric solutions for known microphone array geometries. Unfortunately, as a result of the high complexity, and thus large computational overhead, of such approaches, more emphasis has been given to finding near-optimal solutions, rather than optimal solutions. These approaches are often referred to as "fixed-beam formation."
In general, with fixed-beam formation, the beam shapes do not adapt to changes in the surrounding noises and sound source positions. Further, the near-optimal solutions offered by such approaches tend to provide only near-optimal noise suppression for off-beam sounds or noise. Consequently, there is typically room for improvement in noise or sound suppression offered by such conventional beamforming techniques. Finally, such beamforming algorithms tend to be specifically adapted for use with particular microphone arrays. Consequently, a beamforming technique designed for one particular microphone array may not provide acceptable results when applied to another microphone array of a different geometry.
Other conventional beamforming techniques involve what is known as "adaptive beamforming." Such techniques are capable of providing noise suppression based on little or no a priori knowledge of the microphone array geometry. Such algorithms adapt to changes in ambient or background noise and to the sound source position by attempting to converge upon an optimal solution as a function of time, thereby providing optimal noise suppression after convergence. Unfortunately, one disadvantage of such techniques is their significant computational requirements and slow adaptation, which makes them less robust to wide varieties in application scenarios.
Consequently, what is needed is a system and method for providing better optimized beamforming solutions for microphone arrays. Further, such a system and method should reduce computational overhead so that real-time beamforming is realized. Finally, such a system and method should be applicable for microphone arrays of any geometry and including any type of microphone.

System and method for beamforming using a microphone array


An in-plane switching mode LCD device includes first and second substrates, a gate line and a data line arranged horizontally and vertically on the first substrate and defining a pixel, a switching device at each crossing of the gate line and the data line, a first common electrode having a first grid structure disposed in the pixel, a first pixel electrode having a second grid structure disposed in the pixel, a first region in the pixel region defined by first sides of the first grid and second sides of the second grid, a second common electrode connecting the first sides and a second pixel electrode connecting the second sides and defining a second region in the first region, a first alignment film and a second alignment film at facing surfaces of the first and second substrate, and a liquid crystal layer between the first and the second substrates.

1. Field of the Invention
The present invention relates to a liquid crystal display device and, more particularly, to an in-plane switching mode liquid crystal display device capable of maintaining maximum light transmittance.
2. Description of the Related Art
A liquid crystal display device is typically used as a high image quality and low-power flat panel display device. The liquid crystal display device is formed by attaching a thin film transistor array substrate and a color filter substrate facing each other with a uniform interval therebetween. A liquid crystal layer is formed between the thin film transistor array substrate and the color filter substrate. Pixels are arranged on the thin film transistor array substrate in a matrix form, and a thin film transistor, a pixel electrode and a capacitor are formed at a unit pixel. A common electrode for applying an electric field to the liquid crystal layer with the pixel electrode, an RGB color filter for implementing color and a black matrix are formed on the color filter substrate. Alignment films are formed at facing surfaces of the thin film transistor array substrate and the color filter substrate and rubbed to make the liquid crystal layer be arranged in a certain direction.
When an electric field is applied between the pixel electrode formed at each unit pixel of the thin film transistor array substrate and the common electrodes formed at the entire surface of color filter substrate, the liquid crystal is rotated due to dielectric anisotropy, whereby the light is transmitted or blocked by unit pixels to display a character or an image. However, such twisted nematic mode liquid crystal display device disadvantageously has a narrow viewing angle. Thus, recently, an in-plane switching mode LCD which solves the problem of the narrow viewing angle by aligning liquid crystal molecules in an almost horizontal direction with respect to the substrate has been actively studied.
FIGS. 1A and 1B illustrate a unit pixel of the related art in-plane switching mode LCD device. Specifically, FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line I-I of FIG. 1A. As shown in FIGS. 1A and 1B, a gate line 1 and a data line 3 are arranged horizontally and vertically on the first transparent substrate 10, defining a pixel region. In an actual liquid crystal display device, the 'N' number of gate lines 1 and the 'M' number of the data line 3 cross each other to form N×M number of pixels, but in the drawings, only one pixel is shown.
A thin film transistor 9 consisting of a gate electrode 1a, a semiconductor layer 5 and source/drain electrodes 2a and 2b is disposed at a crossing of the gate line 1 and the data line 3. The gate electrode 1a and the source/drain electrodes 2a and 2b are connected to the gate line 1 and the data line 3, separately. A gate insulation film 8 is deposited over on the entire substrate.
A common line 4 is arranged parallel to the gate line 1 in the pixel region, and a pair of electrodes, namely a common electrode 6 and a pixel electrode 7, for switching liquid crystal molecules are arranged parallel to the data line 3. The common electrode 6 is simultaneously formed together with the gate line 1 and connected to the common line 4, and the pixel electrode 7 is simultaneously formed together with the source/drain electrodes 2a, 2b and connected to the drain electrode 2b of the thin film transistor 9.
A passivation film 11 is formed over the entire surface of the substrate including the source electrode 2a and the drain electrode 2b. A pixel electrode line 14 is formed overlapping the common line 4 and connected to the pixel electrode 7. The pixel electrode line 14 forms a storage capacitor (Cst) together with the common line 4 with an gate insulation film 8 interposed therebetween.
A black matrix 21 for preventing a leakage of light to the thin film transistor 9, the gate line 1 and the data line 3, and a color filter 23 for implementing colors are formed on the second substrate 20, on which an overcoat film 25 for flattening the color filter 23 is formed. Alignment films 12a and 12b for determining an initial alignment direction of liquid crystal are formed at the facing surfaces of the first and second substrates 10 and 20, respectively. A liquid crystal layer 13 for controlling light transmittance by a voltage applied across the common electrode 6 and the pixel electrode 7 is formed between the first substrate 10 and the second substrate 20.
FIGS. 2A and 2B illustrate a driving principle of the related art in-plane switching mode LCD device. FIG. 2A shows driving of the liquid crystal molecules when the voltage is not applied between the common electrode 6 and the pixel electrode 7 and FIG. 2B shows driving of the liquid crystal molecules when a voltage is applied therebetween.
First, with reference to FIG. 2A, when the voltage is not applied to the in-plane switching mode LCD device, the liquid crystal molecule in the liquid crystal layer is aligned along a rubbing direction (the direction of arrow ↑ in FIG. 2A) of the alignment films formed at the facing surfaces of the first and second substrates. With reference to FIG. 2B, when a voltage is applied across the common electrode 6 and the pixel electrode 7, an electric field is generated therebetween and the liquid crystal molecule transmits an amount of light corresponding to the intensity of the electric field.
FIG. 3 is a graph showing light transmittance characteristics according to a drive voltage of an in-plane switching mode LCD device in accordance with the related art. As shown in FIG. 3, as the voltage-applied to the common electrode and the pixel electrode increases, the light transmittance linearly increases. However, if the voltage continues to increase, the light transmittance decreases begins to decrease at 6V. In this case, assuming that the voltage value representing a maximum light transmittance is Vmax, the Vmax voltage value is the voltage at which the liquid crystal molecule makes a 45° with respect to the initial alignment direction of the alignment film.
If a voltage greater than Vmax is applied, the transmittance drops. However, the transmittance obtained in the graph shows an ideal case, and an actual product has maximum luminance at a voltage lower than Vmax, which is a theoretical voltage value. Thus, the in-plane switching mode LCD device has a problem in that the liquid crystal molecules of the liquid crystal layer are always switched on the same plane, reducing the grey level in the vertical and horizontal viewing angle directions and light transmittance at voltages higher voltage than Vmax is less. To solve such problems, a voltage lower than Vmax is set as a Vmax of the actual product, but in this case, there is a high possibility that maximum luminance of the product will not occur. In addition, even though the white state needs to be displayed by applying Vmax, since liquid crystal molecules are collectively arranged in one direction, a screen image viewed in the direction of the shorter side of the liquid crystal molecules has a yellowish and a screen image viewed in the direction of the longer side has a bluish, degrading image quality.

In-plane switching mode liquid crystal display device


A body structure for a vehicle having a sliding door. The structure has a slide rail, provided in a side face of the vehicle, for guiding the sliding door; and a rail cover, having a cover portion and an extension, for covering the slide rail. The cover portion extends along a lower edge of a rear side glass of the vehicle, and the extension extends from a rear end portion of the cover portion along a rear pillar of the vehicle. The rail cover is positioned for the vehicle's body in a front-rear direction and a vertical direction via the rear end portion of the cover portion. The rail cover may be further positioned in the vertical direction via a front end portion of the cover portion. A screening member may be provided between a rear edge of the extension and a panel of the vehicle's body.

1. Field of the Invention
The present invention relates to a body structure for vehicles having a sliding door.
Priority is claimed on Japanese Patent Application No. 2004-140986, filed May 11, 2004, the content of which is incorporated herein by reference.
2. Description of Related Art
In conventional vehicles having a sliding door, a rail cover may be provided for covering a slide rail which is arranged at the back of the sliding door (see, for example, Japanese Unexamined Utility Model Application, First Publication No. H05-017249). In the disclosed rail cover, a lower portion overlaps with the slide rail in the vehicle's width direction, and the slide rail is covered except for a gap, provided between the lower edge of the rail cover and the vehicle body panel, for guiding a door support arm. An upper edge portion of the above rail cover forms a parting line together with a lower edge of the rear side glass which is arranged above the slide rail, so as to prevent a panel joint line from appearing in a vicinity of the rear side glass.
However, even in the above structure, a panel joint line between the rail cover and the vehicle body panel may be produced in the vicinity of the rear pillar at the back of the rear side glass, which affects the appearance of the vehicle, and relevant improvement has been required.
In addition, the rail cover is arranged from a lower edge portion of the rear side glass over the slide rail and is thus a relatively large member. Therefore, improvement in performance of mounting the rail cover to the vehicle body has also been required.

Body structure for vehicle having sliding door


An internally lubricated, longitudinally split sleeve is positioned on a small diameter portion a mandrel having a rear end connected to a piston with a puller tool. The rear end of the split sleeve is flared and is against the front end of a tubular sleeve stop which immediately surrounds the mandrel. The puller tool includes a tubular sleeve holder which surrounds the sleeve stop. A forward main portion of the sleeve holder is separated by a pair of longitudinal slots into a pair of elongated fingers. The forward ends of the fingers define a sleeve and mandrel receiving end opening and jaws radially outwardly bounding the opening. The mandrel and sleeve holder are both extended and then the puller tool is moved into alignment with a sleeve and is moved endwise to push the mandrel through the sleeve until the flared end of the sleeve is against the sleeve stop. Then the sleeve holder is retracted. Next, the mandrel and sleeve are inserted into a hole in a workpiece and the tool is moved forwardly until the front ends of the jaws are against the workpiece. Then, the puller tool is operated to retract the mandrel through the sleeve and into the sleeve stop. Retraction of the mandrel moves first an increasing diameter portion of the mandrel and then a maximum diameter portion of the mandrel through the sleeve which radially expands the sleeve and cold expands the material immediately surrounding the hole in the workpiece. After the mandrel is retracted into the sleeve stop, the puller tool is moved away from the workpiece. The jaws of the sleeve holder engage and retain the sleeve so that the sleeve is pulled out from the hole in the workpiece.

Split sleeve cold expansion of fastener holes and other openings in structural members is a process in which a tapered mandrel is used in conjunction with a disposable, internally lubricated split sleeve, to compressively prestress a significant zone in the material surrounding the opening. This compressive prestressing offsets the stress concentration of the hole itself to produce substantial improvement in structural fatigue performance of the material on which the opening is formed.
Split sleeve cold expansion is most often performed on one side of the workpiece. The mandrel has a rear end portion which is connected to a piston within a puller tool. Starting from the rear end, and moving forwardly, the mandrel includes in order, a small diameter portion, an increasing diameter portion and a maximum diameter portion. The piston is retractable to retract the mandrel and is extendible to extend the mandrel. A split sleeve is moved endwise over the maximum and increasing diameter portions of the mandrel and onto the small diameter portion of the mandrel. The split in the sleeve allows the sleeve to expand as it is moved relatively over the maximum in creasing diameter portions of the mandrel. When the sleeve is on the small diameter portion of the mandrel it is contracted and has an outside diameter equal to or slightly smaller than the maximum diameter portion of the mandrel. The maximum diameter portion of the mandrel is sized to fit through a workpiece opening that is to be expanded. The split sleeve, while in a contracted position on the small diameter portion of the mandrel, is also fittable through the workpiece opening.
As a first step of a cold expansion method, as it has been practiced to date, a mandrel is extended out from the puller tool. Then, a split sleeve is hand installed onto the mandrel and is moved onto the exposed portion of the small diameter portion of the mandrel. Then the puller tool is hand moved to align the maximum diameter portion of the mandrel with the hole in the workpiece. Next, the puller tool is hand moved endwise to move the mandrel and sleeve into the hole. This endwise movement of the puller tool is continued until the split sleeve is within the hole and a nose piece on the puller tool is against the workpiece. The puller tool is then operated to retract the piston and the mandrel. Movement of first the increasing diameter portion and then the maximum diameter portion of the mandrel through the split sleeve causes another expansion of the split sleeve. The split sleeve thickness is significantly greater than the clearance between the maximum diameter portion of the mandrel and the wall of the workpiece opening. As a result, movement of the in creasing and maximum diameter portions of the mandrel through the split sleeve poses on the split sleeve a radially outward which acts on the workpiece material immediately surrounding the opening and increases the diameter of the opening. The diameter of the opening is increased a significant amount to introduce a compressive hoop prestress into the material surrounding the opening. The puller tool is operated to pull the mandrel completely through the split sleeve. Then, the puller tool is hand pulled by the operator away from the workpiece while the split sleeve remains in the workpiece. After cold expansion, and after movement of the puller tool and mandrel away from the workpiece, the used sleeve is removed from the opening as an additional step.
A principal object of the present invention is to provide a method and apparatus for facilitating the placement of a split sleeve on a mandrel, prior to cold working, and for easily and automatically removing the used sleeve from the hole following cold expansion, in response to movement of the puller tool and mandrel away from the workpiece.
The prior art processes and tooling are described in detail U.S. Pat. No. 3,566,662 , granted Mar. 2 , 1971, to Louis A. Champoux; U.S. Pat. No. 4,187,708, granted Feb. 12, 1980, to Louis A. Champoux; and U.S. Pat. No. 4,425,780, granted Jan. 17, 1984, to Louis A. Champoux. U.S. Pat. No. 4,583,388, granted Apr. 22, 1986, to Franciscus Hogenhout, discloses a puller tool for a split mandrel. The above patents, and the following additional U.S. patents, should be considered for the purpose of putting the present invention into proper perspective relative to the prior art. U.S. Pat. No. 3,892,121, granted Jul. 1, 1975, to Louis A. Champoux, Horace E. Hill and Joseph L. Phillips; U.S. Pat. No. 4,423,619, granted Jan. 3, 1984, to Louis A. Champoux; U.S. Pat. No. 4,471,643, granted Sep. 18, 1984, to Louis A. Champoux and Charles M. Copple; U.S. Pat. No. 4,524,600, granted Jun. 25, 1985, to Robert L. Champoux and Charles M. Copple; and U.S. Pat. No. 4,557,033, granted Dec. 10, 1985 to Robert L. Champoux.


Electronic equipment comprises a main body, a front panel and a recording medium receiving unit. The front panel is provided movably between an opened position and a closed position on a front side of the main body. A card-type recording medium is to be loaded or unloaded into or from the recording medium receiving unit. The recording medium receiving unit is concealed and inaccessible in case where the front panel is in the closed position. The recording medium receiving unit is displaced along with movement of the front panel so as to be exposed and accessible when the front panel moves from the closed position to the opened position.

1. Field of the Invention
The present invention relates electronic equipment, and more particularly to electronic equipment having on its front side an openable and closable front panel.
2. Description of the Related Art
Installation of electronic equipment such as an audio device and a navigation device on a vehicle has widely been put into practice.
On the other hand, use of a card-type recording medium having a small size, called a "memory card" has also recently been generalized.
It has recently become possible to store information, which is to be used in the above-mentioned electronic equipment, in the card-type recording medium, so as to provide information sharing between the electronic equipment and a domestic or personal computer, as well as between a plurality of electronic equipment.
With respect to installation of the above-mentioned card-type recording medium on electronic equipment, a casing of the electronic equipment, which has a stationary front panel 101 as shown in FIG. 9, is embedded into a dashboard of a vehicle. As a result, it is necessary to form a slot-shaped insertion opening 106 into or from which the card-type recording medium is to be loaded or unloaded, on any place of the front panel 101.
It is however necessary to provide parts such as an operating dial 102, operating mode buttons 105, an operation displaying unit 104 and selection buttons 103a and 103b, by which the electronic equipment is caused to function, on the above-mentioned front panel 101. Accordingly, the above-mentioned insertion opening 106 must be formed on a place other than the above-mentioned parts such as the operating dial 102. Formation of the insertion opening 106 is however restricted by design which is made when determining arrangement of the parts such as the operating dial 102 on the front panel 101, thus causing problems.
The insertion opening 106 is exposed on the front panel 101, resulting in an increased possibility that the card-type recording medium loaded into the insertion opening 106 may be stolen, thus also causing problems.
There has also been known electronic equipment, which is to be mounted on a vehicle and has an openable or closable front panel. FIG. 10(a) is a partial side view of typical electronic equipment 200 in which a front panel 201 is opened by swinging the front panel 201 around a pivot shaft 206 provided on the lower side of the front panel 201, while moving forward a supporting member 202 to which the pivot shaft 206 is connected. FIG. 10(b) is a partial side view of the other typical electronic equipment 200 in which a front panel 201 is opened by swinging the front panel 201 around a pivot shaft 206.
In either case, there is adopted a structure that an insertion opening 205 for the card-type recording medium MC is formed on an inner wall 204, which is exposed from the front end opening of the casing of the electronic equipment when the front panel 201 is kept in the opened position (i.e., a state as shown in the lower portions of FIGS. 10(a) and 10(b)), and a connector 203 into which the card-type recording medium MC is to be inserted is further provided in a place corresponding to the insertion opening 205.
However, the card-type recording medium MC, which has an extremely small size, is connected to the connector 203 so as to project from the above-mentioned inner wall 204 by a small length. As a result, it is not easy to pull out the card-type recording medium MC from the insertion opening 205, thus causing a problem, even when the front panel 201 is opened as shown in the lower portions of FIGS. 10(a) and 10(b).


An image processor includes an input device that inputs image data representing a target image, and a color gamut mapping device that performs a color gamut mapping process. The image processor also includes a color reproduction process device that performs a color reproduction process, and a judgement device that judges whether a monochromatic mode for forming an image on a recording medium is set. A controller controls the color gamut mapping device and the color reproduction device, with the controller inhibiting the color gamut mapping device from performing a color mapping process on the input image data when a judgment is made that the monochromatic color mode is set.

1. Field of the Invention
The present invention relates to an image processing apparatus and method for performing a color gamut mapping process (or color space compression process).
2. Related Background Art
In recent years, it has been thought a color gamut mapping technique which converts input image data including image data outside a color reproduction gamut (or range) of an output device into optimal image data within the color reproduction gamut of the output device.
However, since a color gamut mapping process has been conventionally performed irrespective of a mode to be set, there has been a problem that a process suitable for each mode is sometimes impossible.

Image processing apparatus with color gamut dependent on color mode


A first resistor string provides a plurality of first polarity gamma-reference-voltages. A second resistor string provides a plurality of second polarity gamma-reference-voltages. A first main-thermal compensation section exhibits a resistance value that increases with an increase of temperature. A second main-thermal compensation section has a resistance value that is decreases with an increase of temperature. Thus, gamma-reference-voltages corresponding to white gradation are decreased and gamma-reference-voltages corresponding to black gradation are maintained, so that a deviation of kickback voltage corresponding to the white gradation is decreased.

1. Field of the Invention
The present invention relates to a gamma-reference-voltage generating circuit and an apparatus for generating gamma-voltages and a display device having the circuit. More particularly, the present invention relates to a gamma-reference-voltage generating circuit having a thermal compensation feature, an apparatus for generating gamma-voltages having the gamma-reference-voltage generating circuit and a display device including the gamma-reference-voltage generating circuit.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) device displays an image by providing a pixel with an analog gradation voltage using a thin-film transistor (TFT). The analog gradation voltage is a data voltage that is provided to a data line of the LCD device.
When a gate voltage of a high level is applied to the thin-film transistor, the thin-film transistor is turned-on, so that the data voltage is charged in a pixel that is defined by a liquid crystal capacitor and a storage capacitor. The variation of the voltage difference between the charged data voltage and a common voltage changes the transmittance of the light passing through a liquid crystal layer, and thus desired gradations are displayed.
When the high value of the gate voltage that is applied to a thin-film transistor of the pixel, the pixel voltage reaches the data voltage. However, the pixel voltage drops by as much as a kickback voltage due to parasitic capacitors of the thin-film transistor after the gate voltage becomes low.
The kickback voltage varies significantly depending on the voltage difference between the pixel voltage and the common voltage as well as depending on the pixel voltage itself. It is because the capacitance of the liquid crystal capacitor depends on the voltage across the liquid crystal capacitor due to the dielectric anisotropy of the liquid crystal. Therefore, the liquid crystal capacitance is varied in accordance with a white gradation displaying and a black gradation displaying, so that the kickback voltages corresponded to each gradations is varied.
Due to the difference of kickback voltages of each gradation, when an image corresponding to a new pattern is displayed after a predetermined image is displayed for a long time, this causes a defect in the LCD device referred to as image sticking.
In order to remove the image sticking, for example, a method of decreasing a remaining DC voltage may be used, which is calculating a kickback voltage corresponding to gradations and compensating a gamma using the calculated kickback voltage.
In order to remove the image sticking, for another example, a method of reducing a difference between kickback voltages corresponding to gradations may be used, which is decreasing an absolute value of the kickback voltages.

Gamma-reference-voltage generating circuit and apparatus for generating gamma-voltages and display device having the circuit


Techniques for multimedia metadata security are disclosed. In one particular embodiment, the techniques may be realized as a method for multimedia metadata security comprising receiving an indication that multimedia metadata has been created for a multimedia file, and encrypting, using at least one computer processor, the multimedia metadata stored in a body of the multimedia file.

Digital images and video may contain embedded metadata including, for example, an owner's name, location, time of day, camera settings, and other image associated attributes. For example, some digital cameras and other devices may use the Exchangeable Image File format (EXIF) to store metadata in an image, video, or audio file. The use of such metadata is increasing with an increase in the use of digital cameras, cell phones, PDAs, and other devices. Such metadata may be useful to search for and/or organize images or video by location, time, name, etc. However, digital images and/or video are frequently not secured and may be shared (e.g., posted to the Internet on a social networking site or a photo sharing site.) Users may not be aware of the metadata associated with their images and/or video and may not understand implications and potential vulnerabilities of making metadata and images or video publicly available. A malicious user could use this information to stalk someone. A criminal could search for public social networking profiles (e.g., Facebook profiles) in an area, download the images and try to figure out the times of day that a person is out of their house, etc. In addition to criminal threats, a user loses further privacy by publicly exposing not only the image but also the date, time, and name associated with the image or other media file.
Deleting such metadata may lose all of the benefits of the metadata. Making all of the metadata publicly available may create all of the vulnerabilities described above.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with current multimedia metadata security technologies.