An improved combined clutch and brake apparatus is disclosed having a pressure disk positioned on a hub between a brake thrust disk and a pneumatic cylinder. The present invention is configured to allow the apparatus to be efficiently serviced. The brake thrust disk forms an outer surface of the invented combined clutch and brake apparatus. A movable piston positioned in a casing of the pneumatic cylinder forms an external face of the invented combined clutch and brake apparatus. This arrangement allows failed sealing collars sealing the piston to the casing to be efficiently replaced. Readily accessible screws also allow clearances between the pressure disk and the brake thrust disk and between the pressure disk and a clutch thrust ring to be efficiently maintained at optimal levels via stepless adjustment from either side of the invented combined clutch and brake mechanism or from both sides. This is particularly important because friction elements which engage the driven disks are subject to extensive wear and therefore continuously alter the clearances. Finally, a bolt connecting the piston to the pressure disk allows the length the piston is free to travel to be efficiently adjusted as desired.

Combined clutch and brake mechanisms are used for driving power presses in which the movement of a crank or eccentric shaft must be stopped immediately after the clutch is disengaged. Combined clutch and brake mechanisms are designed such that, when the clutch is engaged, the brake is automatically disengaged, and, when the brake is engaged, the clutch is automatically disengaged.
Combined clutch and brake mechanisms utilize friction linings or friction elements which are engageable with a clutch disk and a brake disk. Friction elements undergo extensive wear during use and frequently must be replaced. Friction element wear is particularly problematic because any variation in the clearance between the friction element and the clutch disk seriously affects the proper functioning of the clutch. Similarly, any variation in the clearance between the friction element and the brake disk seriously affects the proper functioning of the brake. As a consequence, a prescribed clearance between the linings and the disks must be maintained to enable the combined clutch and brake mechanism to operate properly.
Existing combined clutch and brake mechanisms are difficult to service. Adjusting the clearances between the friction elements and the brake and clutch disks on those mechanisms requires numerous time-consuming steps. Replacing worn friction elements is also a time-consuming process. To replace a friction elements, the entire mechanism must be completely disassembled, the friction elements replaced, and the mechanism must then be reassembled. Consequently, existing combined clutch and brake mechanisms are subject to significant down time.
A need therefore exists for a combined clutch and brake mechanism that permits the clearances between the friction elements and the clutch and brake disks to be quickly and easily adjusted and allows worn friction elements to be efficiently replaced.
In addition, existing combined clutch and brake mechanisms are prone to mechanical failure as the difficulties in accessing the friction elements unduly delays their replacement. This is particularly problematic where one of the sealing collars which secure the piston in the casing of the pneumatic cylinder fails and the piston is no longer able to move the clutch into an engagement position.
A need exists for a combined clutch and brake mechanism that allows for easy maintenance of parts requiring replacement.
During operation, frequent adjustments must be made to the length of the piston stroke in the pneumatic cylinder of a combined clutch and brake mechanism. Existing combined clutch and brake mechanisms require that the entire mechanism be disassembled before the stroke length can be adjusted and reassembled after the adjustment is made. This also is time-consuming and subjects existing clutch and brake mechanisms to significant down-time.
Therefore, a need exists for a combined clutch and brake mechanism having an increased service life and having improved performance, particularly under emergency conditions.


There is disclosed a vertical deflection circuit for use in a display device employing a CRT. The vertical deflection circuit has a DSP (digital signal processor) for producing a digital current signal during each main period. This digital current signal shows plural current values which increases in first equal increments from a different value during each main period. The digital current value is converted into an analog current signal by a D/A converter and then averaged by a low-pass filter. A vertical deflection current is produced based on the averaged analog current signal. Because plural different current values are averaged, the average value varies linearly. Accordingly, the vertical deflection current varies linearly with each main period.

1. Field of the Invention
This invention relates to a vertical deflection circuit used in a display device employing a cathode-ray tube (CRT) that displays an image by scanning an electron beam. The invention also relates to a processor used in this vertical deflection circuit and to a CRT display using the aforementioned vertical deflection circuit.
2. Background Art
CRTs having electron guns that emit an electron beam scanned vertically and horizontally in two dimensions to display an image on a viewing screen have been heretofore known. In this kind of CRT display, an electron beam is deflected in two dimensions by magnetic forces. Thus, substantially horizontal scanning lines are drawn in turn from the top end of the viewing screen toward the bottom end. In this way, the CRT accomplishes a display of an image.
The magnetic forces for deflecting the electron beam are normally offered from vertical and horizontal deflection coils. These coils are mounted in the path of the electron beam. Electric currents are supplied to the coils from vertical and horizontal deflection circuits. Owing to the supply of the currents, the coils can generate magnetic fields necessary to deflect the electron beam vertically and horizontally.
FIG. 18 is a diagram illustrating an electric current (hereinafter referred to as the xe2x80x9cvertical deflection currentxe2x80x9d) supplied from the vertical deflection circuit to the vertical deflection coils. In FIG. 18, the horizontal axis indicates time, while the vertical axis indicates the value of the vertical deflection current. Point A indicates the value of the vertical deflection current at the top end of the viewing screen. Point B denotes the value of the vertical deflection current at the bottom end of the viewing screen.
As mentioned previously, the scanning lines are successively drawn from the top end toward the bottom end of the viewing screen. Therefore, the vertical deflection current supplied to the vertical deflection coils is so set as to vary linearly from the top end of the viewing screen toward the bottom end to vary the vertical deflection angle of the electron beam in substantially uniform angular increments. To return the electron beam to the top end of the viewing screen after reaching the bottom end of the viewing screen, the vertical deflection current is so set as to return to its original value during a short retrace period and again start to vary linearly.
Some of vertical deflection circuits for generating such vertical deflection currents produce vertical deflection currents digitally. This kind of vertical deflection circuit normally generates a digital current signal by a digital value-generating portion corresponding to some functions of a digital signal processor (DSP). A vertical deflection current corresponding to the generated digital current signal is produced. The digital current signal is generated during each main period in which the vertical deflection angle of the electron beam is varied, and has one digital current value.
The vertical deflection circuit is described in further detail. This vertical deflection circuit includes a D/A (digital-to-analog) converter, a low-pass filter (LPF), and a driver circuit, in addition to the digital signal value-generating portion described above. The D/A converter converts a digital current signal into an analog current signal. In this case, the analog current signal has an analog current value that shows a 1:1 correspondence to one digital current value forming the digital current signal. The analog current signal is supplied to the driver circuit via the LPF. The driver circuit supplies a current corresponding to the aforementioned analog current value as a vertical deflection current to the vertical deflection coils.
However, this vertical deflection circuit has the disadvantage that it may not be able to convert the digital current signal into an analog current signal of a desired amplitude due to distortion in the linearity of the input/output characteristics of the D/A converter. In this case, the angular increment of the deflection angle of the electron beam varies from location to location. As a result, spacing between the scanning lines becomes nonuniform, giving rise to fringes of varying shade on the viewing screen.
More specifically, the vertical deflection circuit is intended to vary the vertical deflection current linearly over the whole period for displaying a frame of image. That is, the vertical deflection circuit linearly varies the deflection angle of the electron beam to draw scanning lines at regular intervals, thus displaying an image at a uniform density.
However, where the linearity of the input/output characteristics of the D/A converter has distortion, the vertical deflection current varies in unequal increments. As a result, the vertical deflection angle of the electron beam varies in unequal angular increments In particular, the input/output characteristics of the D/A converter are normally distorted as indicated by the solid line in FIG. 19(a) from ideal characteristics indicated by the broken line. That is, even if the digital current signal is varied in uniform increments, the analog current signal produced from the D/A converter varies in nonuniform increments.
In this case, in locations where the analog current signal varies in larger increments, the deflection angle of the electron beam varies in greater increments, resulting in lower scanning line densities.Consequently, the viewing screen becomes darker.
On the other hand, in locations where the analog current is varied in smaller increments, the deflection angle of the electron beam varies in smaller increments, resulting in higher scanning line densities. The result is that the viewing screen becomes brighter. Hence, the viewing screen contains both locations 50 where the scanning lines density is lower and hence are darker and locations 60 where the density is higher and hence are brighter as shown in FIG. 19(b). This produces a fringe pattern.
Accordingly, it is an object of the present invention to provide a vertical scanning circuit that solves the foregoing technical problems and is capable of producing a vertical scanning current which varies linearly if the linearity of the input/output characteristics of the D/A converter has distortion.
It is another object of the invention to provide a processor used in the vertical deflection circuit described above.
It is a further object of the invention to provide a CRT display that uses the above-described vertical deflection circuit to thereby make uniform the scanning line density.
This invention is intended to achieve the aforementioned objects and pertains to a vertical deflection circuit for generating a vertical deflection current supplied to vertical deflection coils that generate a magnetic field necessary to deflect an electron beam vertically. That is, a vertical deflection circuit in accordance with this invention comprises a digital signal value-generating portion for producing a digital current signal, a D/A converter for converting the digital current signal produced by this digital value-generating circuit into an analog current signal, a filter for extracting the average value of the analog current signal produced from the D/A converter, and a driver circuit for supplying a vertical deflection current corresponding to the average value of the analog current signal extracted by the filter to the vertical deflection coils described above. This digital value-generating portion produces a digital current signal that shows plural different digtal values during a predetermined each main period which a vertical deflection angle of the electron beam is varied. The digital current values determine vertical deflection current values.
In this structure, the digital current signal showing plural different digital current values during each main period is produced. The average value of the analog current signal corresponding to the digital current signal is taken as the reference for the vertical deflection current. Accordingly, if the linearity of the input/output characteristics of the D/A converter has distortion, the vertical deflection current can be varied in substantially uniform increments. Therefore, the vertical deflection angle of the electron beam can be varied in substantially uniform angular increments. This prevents the scanning line density from becoming nonuniform. In consequence, a high-quality image can be produced on the viewing screen.
The above-described digital value-generating portion can be one function of a processor used in a vertical deflection circuit that supplies a vertical deflection current to vertical deflection coils after the average value of the analog current signal converted from the digital current signal by the D/A converter is extracted by a filter, the vertical deflection current corresponding to the average value. That is, this processor has a digital value-generating means that generates a digital current signal having plural different digital current values defining vertical deflection current values during a predetermined each main period in which the vertical deflection angle of the electron beam is varied and delivers this digital current signal.
In this structure, the digital current signal is generated in software and so it is easy to cope with the situation whatever input/output characteristics does the D/A converter have, the D/A converter being used as a part of the vertical deflection circuit. Therefore, excellent generality can be given to the vertical deflection circuit.
The present inventors have found that the method of selection of cells forming the D/A converter is one cause of generation of distortion in the linearity of the input/output characteristics of the D/A converter.
In particular, in the prior art D/A converter, where plural cells are selected, they may be spaced from each other. Cells located close to each other show similar characteristics. However, cells remotely spaced from each other exhibit different characteristics. In this way, cells normally are not uniform in characteristics. Accordingly, if cells remote from each other are selected, the linearity of the input/output characteristics of the D/A converter is distorted.
Accordingly, it is conceivable that this invention for achieving the aforementioned objects makes use of a D/A converter including plural cells arranged in two dimensions and turned on and off and a cell-selecting means for selecting only adjacent cells when a necessary number of cells are turned on based on the digital current value contained in the digital current signal.
In this structure, only mutually adjacent cells are selected and so distortion in the characteristics can be suppressed unlike in the prior art technique in which cells physically remotely spaced from each other have produced distortion in the characteristics. Therefore, the input/output characteristics of the D/A converter can be stabilized. Consequently, the vertical deflection current can be varied in substantially uniform increments. This assures that the vertical deflection angle of the electron beam is varied in substantially uniform angular increments. This prevents the scanning line density from becoming nonuniform. Hence, a high-quality image can be produced on the viewing screen.
In addition, the aforementioned vertical deflection circuit can be used in a CRT display. In particular, this CRT display comprises an electron gun for emitting an electron beam, vertical deflection coils for producing a vertical magnetic field necessary to deflect the electron beam vertically, the aforementioned vertical deflection circuit for producing a vertical deflection current necessary to produce the vertical magnetic field required to deflect the electron beam vertically, horizontal deflection coils for producing a horizontal magnetic field necessary to deflect the electron beam horizontally, and a display portion on which scanning lines are drawn by the electron beam whose direction of travel is deflected in two dimensions by the magnetic fields produced by the vertical deflection coils and the horizontal vertical deflection coils.
In this structure, the scanning line density can be made uniform. Consequently, a high-quality image can be produced on the viewing screen.

Vertical deflection circuit, processor for vertical deflection, and CRT display


A solid-state light source has a wavelength conversion chip affixed to a light emitting diode. Optical coatings, vias, light extraction elements, electrical connections or electrical bond pads can be fabricated on the wavelength conversion chips.

The recent proliferation of solid-state lighting has created a need for high performance wavelength conversion materials. The standard approach is to form wavelength conversion materials (e.g. phosphors) using solid state processing as known in the art. These phosphors are then ground down to powders in the micron size range and deposited on a surface using a variety of deposition techniques such as settling, encapsulation, and spray coating. Large extended area devices such as cathode ray tubes (CRTs), fluorescent lighting, and plasma displays require a large amount of standard high volume phosphors. These phosphors can be acquired for less than $100/Kg for the large extended area devices. Though relatively inexpensive, the phosphors generated using this method suffer from high levels of dislocations and lattice defects. In addition, the compositional purity is also difficult to maintain. In the majority of cases, this does not represent a major problem because of the reduced excitation levels. It has been shown, however, in accelerated aging studies that very high excitation levels can degrade the output luminescence of powdered phosphors severely and impact overall life performance. These levels of high excitation exist within solid-state lighting applications. This is mainly due to the small size and concentrated flux density of the LED die itself. It is also true that in the case of individual or arrays of LEDs, phosphor usage is measured in milligrams rather than grams. It is apparent that higher performance wavelength conversion materials are needed and can be afforded for applications like solid-state lighting. The expense of higher performance materials can be absorbed and even offset if the problems associated with the degradation and reduced conversion efficiency of phosphors used in solid-state lighting can be overcome.
Several material characteristics contribute to this degradation and/or loss in efficiency problem such as lattice defects, out-gassing, and compositional purity. It has been shown that polycrystalline and mono-crystalline phosphor films either grown on a substrate or as single crystal boules tend to exhibit much better luminosity and life characteristics than powders. In addition, every phosphor has a thermal quenching level that can degrade the output at the temperatures created by elevated excitation levels. In the case of powdered phosphors, this can be a major issue because the phosphor particles are usually isolated from any reasonable thermal conduction path. At very high excitation levels the energy associated with less than unity quantum efficiency and Stokes shift losses can induce a significant localized thermal rise within the phosphor particles. The need exists for creation of an improved thermal conduction path for the luminescent material. Also, because the particles are roughly spherical the packing density can be significantly degraded. This affects the tradeoff between maximum absorption/conversion of the excitation energy and reabsorption of the emitted light. The scattering created by the use of a powder can reduce the overall light output due to the backscattering and subsequent absorption of the generated light.
Mueller-Mach et al. in U.S. Pat. No. 6,696,703 disclose the deposition of a thin film phosphor directly on the LED die. However, as-deposited thin film phosphors have relatively poor wavelength conversion efficiency. A high-temperature annealing step is required in order to properly activate the phosphor. This annealing step can damage the semiconductor layers of the LED. In addition, the absorption cross-sections of most thin film phosphors are low, especially for blue and near ultraviolet (UV) excitations typically used within solid-state lighting. It is neither economical nor practical in most cases to create a sufficiently thick layer of luminescent material directly on the LED. Another drawback to depositing a phosphor directly on the LED die is that a large portion of the light generated within a deposited phosphor layer can be trapped due to total internal reflectance. The need therefore exists for a method to utilize high performance phosphors within an LED package such that the best phosphor can be used efficiently (e.g. with sufficient quantity, minimal backscatter, and maximum light extraction). The need also exists for a method to fabricate high efficiency phosphors without damaging the LED semiconductor layers.
Another important aspect of phosphors relates to characterization and overall device efficiency. Phosphors are typically characterized in terms of quantum efficiency and Stokes shift losses. As an example, a powder phosphor layer is deposited on a glass surface and excited. The luminescence is measured as a function of excitation energy and the result is usually compared to a standard phosphor of known quantum efficiency. The losses associated with Stokes shift can be subtracted and the result would be the intrinsic quantum efficiency. Several problems exist with this method of characterization such as backscattered light, coating thickness variability and light trapping. In the case of phosphor powders, the majority of the generated light can escape from the phosphor particles due to their substantially spherical nature and to scattering centers located on or in the material itself. The main problem measuring the efficiency of phosphor powders is backscattering of the light from thick samples. For deposited phosphor films or grown phosphor boules, however, the problem of measuring the phosphor efficiency is affected by light extraction. The majority of the light generated in the phosphor can be trapped within the material itself due to total internal reflection. Several approaches have been used to solve the total internal reflection problem including various roughening techniques and shaping approaches. In these cases, the overall efficiency becomes as much a function of the extraction means as the conversion efficiency. Deposited phosphor films have the added complication of a secondary substrate material with its associated indices and losses.
Mayer et al. in U.S. Pat. No. 6,565,770 describe thin interference pigment flakes that can be made on a flexible substrate and then mechanically removed by flexing the substrate. The dichroic reflectors discussed are used in security enhancement on money and other decorative optical effects. The use of luminescent materials is discussed but is related to the formation of a particular optical effect such as UV illumination for security markings. No explanation for improving the output efficiency of LEDs or other light emitting devices is discussed and no device based on integrating the phosphor layer with the excitation source to form an efficient solid-state lighting element is disclosed.
The use of flake-like phosphors is also discussed by Aoki et al. in U.S. Pat. No. 6,667,574 for use in plasma displays, but the patent again lacks any reference to solid-state lighting applications or methods to enhance their output. In addition, the above two applications are very much cost driven because of the large areas typically required in making a plasma display or the marking of money or decorative items. In order to maximize the performance of these wavelength-converting materials high temperature processing is preferred.
Mueller-Mach et al. in U.S. Pat. No. 6,630,691 disclose a thin single-crystal phosphor substrate onto which an LED structure is fabricated by epitaxial growth techniques. However, single-crystal phosphor substrates are expensive and finding a single crystal phosphor substrate that has the proper lattice match to allow the growth of the LED structure can be difficult.
Ng et al. in US Patent Application No. 20050006659 disclose a planar sheet of a single-crystal phosphor that is placed over the output surface of an LED as a portion of a preformed transparent cap. However, single-crystal phosphor sheets must be grown by epitaxial processes or sliced from bulk single crystals of phosphor material. Single crystal phosphor sheets are therefore too expensive for most practical applications. Planar sheets of polycrystalline phosphors are not disclosed in US Patent Application No. 20050006659. Bonding the planar sheet of a single-crystal phosphor directly to the surface of the LED to improve heat dissipation in the phosphor sheet is also not disclosed.
A need exists to maximize the efficiency of wavelength conversion materials within a solid-state lighting application and to improve the thermal conductivity properties of the materials. In addition, a need exits for low-cost phosphors that have light extraction enhancements and the ability to control the level and type of scatter within the phosphor in order to enhance the overall conversion efficiency.

Wavelength conversion chip for use with light emitting diodes and method for making same


In an information processing apparatus, even when a large volume of data is displayed in a limited display area in which the number of data items that can be displayed at once is restricted, rough searching for data and specific identification of data are facilitated. In the information processing apparatus, the number of data items to be displayed is determined. When the number of data items to be displayed is less than or equal to a predetermined number of data items that can be displayed in a display area, the data items are displayed in a first mode. If the number of data items to be displayed is greater than the predetermined number, the data items are displayed in a second mode.

1. Field of the Invention
The present invention relates to information processing apparatuses that are capable of displaying schedulers. More specifically, the present invention relates to an information processing apparatus with an improved ease of visually recognizing data displayed along a time axis of a scheduler on a display.
2. Description of the Related Art
Techniques for displaying data in a display area of a limited size, for example, displaying data along a time axis of a scheduler on a display, have been generally known. Schedule data can be displayed in a calendar format by a schedule displaying apparatus implementing such techniques.
FIG. 34 is a flowchart showing an example of a calendar-format displaying process according to a related art.
Referring to FIG. 34, in step S101, a calendar frame for displaying schedule data is displayed in a format. Various formats are described later with reference to FIGS. 36 and 37. In step S102, schedule data to be displayed in the calendar frame displayed in step S101 is obtained. Then, in step S103, the object of processing is initialized to the beginning of a schedule data set obtained in step S102. In step S104, it is determined whether or not to exit the procedure.
If it is determined in step S104 not to exit the procedure, in step S105, the schedule data of the object is displayed at an appropriate position of the screen displayed in step S101. In step S106, the procedure proceeds to a next object. The procedure then returns to step S104, and procedure is repeated.
When the processing for all the objects has been finished and it is determined in step S104 to exit the procedure, the procedure is exited.
FIG. 35 is a diagram showing an example of a schedule database storing a schedule to be obtained in step S102.
Each item of the schedule data stored in the schedule database includes a start time, an end time, and a summary. In obtaining the schedule data in step S102, schedule data of a specified period is obtained.
FIGS. 36 and 37 are illustrations showing examples of screens displayed in the calendar-format displaying process in step S101.
FIG. 36 shows an example of a display screen showing a weekly schedule on a time axis. A schedule summary 100a is displayed, and scheduled events are shown in relation to periods. FIG. 37 shows an example of a display screen showing a time-based daily schedule. A schedule summary 100a is displayed, and scheduled events are shown in relation to periods.
As described above, according to the related art, schedule data associated with periods can be efficiently searched for and manipulated in a calendar format with an improved visibility in relation to time. It was not possible, however, to display information of processing relating to operations performed by a user, events that occurred, plans, and the like, in a calendar format. Although such information is associated with periods similarly to schedule data, efficient searching and manipulation of such information has not been possible.
In order to solve the problem described above, techniques for displaying other data together with schedule data have been proposed.
FIG. 38 is a flowchart showing an example of a calendar-format displaying process according to the proposed techniques.
Referring to FIG. 38, in step S501, a calendar frame for displaying schedule data is displayed in various modes described later with reference to FIGS. 39 and 40. In step S502, schedule data that is to be displayed in the calendar frame displayed in step S501 is obtained. In step S503, the object of processing is initialized to the beginning of the schedule data set obtained in step S502. In step S504, it is determined whether or not to exit the procedure.
If it is determined in step S504 not to exit the procedure, in step S505, the schedule data obtained is displayed at the appropriate position of the screen displayed in the calendar-frame displaying process in step S501. In step S506, the procedure proceeds to a next object. The procedure then returns to step S504, and the procedure is repeated.
When the processing for all the objects has been finished and it is determined in step S504 to exit the procedure, processing information to be displayed in the calendar frame displayed in step S501 is obtained in step S507. In step S508, the object is initialized to the beginning of the data. In step S509, it is determined whether or not to exit the procedure.
If it is determined in step S509 not to exit the procedure, in step S510, processing information of the object is displayed at an appropriate position of the screen displayed in step S501. In step S511, the procedure proceeds to a next object. The procedure then returns to step S509, and the procedure is repeated.
When the processing for all of the objects has been finished and it is determined in step S509 to exit the procedure, the procedure is exited.
FIGS. 39 and 40 are illustrations showing examples of screens displayed in the calendar-format displaying process according to the related art.
FIG. 39 is an example of a display screen showing a time-based weekly schedule. A schedule summary 500a and processing information 500b are displayed, and scheduled events are shown in relation to periods. FIG. 40 shows an example of a display screen showing a time-based daily schedule. A schedule summary 500a and processing information 500b are shown, and scheduled events are shown in relation to periods.
As described above, according to the proposed art, other data is displayed together with schedule data on a scheduler screen, so that the efficiency of data searching is improved.
Other related art include techniques for manipulating terminal data while grasping an overview of data classified in a hierarchical manner, as disclosed, for example, in Japanese Patent Laid-Open No. 9-305363, and techniques for improving visibility by converting original data into a display mode optimal for a display terminal, as disclosed, for example, in Japanese Patent Laid-Open No. 2000-155667.
According to the proposed techniques, however, in a display mode in which data is shown in a display area of a limited size on the time axis, for example, in a scheduler screen, the number of data items that can be displayed at once is restricted. This has been a factor that deteriorates visibility in cases where a large number of data items are displayed.
Furthermore, according to Japanese Patent Laid-Open No. 9-305363, mentioned above, although it is possible to manipulate terminal data while grasping an overview of data classified in a hierarchical manner, it is impossible to identify data while grasping an overview of data arranged on a time axis.
Furthermore, according to Japanese Patent Laid-Open No. 2000-155667, mentioned above, although the ease of visual recognition is improved by converting original data into a display mode optimal for a display terminal, it is impossible to identify data while grasping an overview of data arranged on a time axis.

Information processing apparatus capable of displaying scheduler


The present invention refers to a method and a transmitter element (35) for transmitting channel information (CI) for link adaptation of a radio channel (33) in a wireless network (11). In order to allow for reliable and efficient transfer of the channel information (CI) and to adapt the detection probability to the importance of the CI as well as to the channel stability, it is suggested that the method comprises encoding (19) the channel information (CI) using multi-level coding, said multi-level coding (19) comprising combining multiple bit sequences (c1, c2, . . . , cn, d), each bit sequence (c1, c2, . . . , cn, d) corresponding to a coding level (1, . . . , n) of said multilevel coding (19) and assigning (37) one of said coding levels (1, . . . , n) to at least a part (ci1, ci2) of the channel information (CI) such that at least a part (ci1, ci2) of the channel information (CI) corresponds to the bit sequence (c1, c2, . . . , cn) of that coding level (1, . . . , n). Furthermore, the present invention refers to a method and a receiver element for receiving the transmitted channel information (CI).

Base stations of cellular communication networks known in the art are arranged for adapting a transmission mode for data transmission to a particular mobile terminal registered with that base station, with this adaptation depending on a current state of a radio channel between the base station and the terminal. Adapting the data transmission to the state of the channel is often referred to as link adaptation.
It is known to transfer channel information describing the current state of the radio channel from the individual terminals to the base station. However this transfer of channel information consumes transmission resources. Moreover, transmission errors may occur when transferring the channel information to the base station, which may lead to a mismatch between the actual channel state and the channel state represented by the channel information received by the base station.

Method and transmitter element for transmitting channel information for link adaptation, method and receiver element for receiving the channel information


The system includes an illumination system, a scanner, a non-linear optical element, and a pumping light source. The illumination system emits imaging beam and the scanner scans the beam incident from the illumination system. The non-linear optical element is made of a material having a Kerr effect or the like and forms a lens automatically aligned while following a path of the imaging beam scanned from the scanner. The pumping light source actives the non-linear optical element to cause a non-linear refractive index change of the non-linear optical element.

1. Field of the Invention
The present invention relates to an optical scanning imaging system, and more particularly, to an optical scanning imaging system capable of improving resolution.
2. Description of the Related Art
As multimedia-oriented society emerges rapidly, a large-sized and high quality display screen is required. Recently, emphasis is put on realization of natural color in addition to high resolution.
A light source such as a laser having high color purity should be used to realize perfect natural colors. One of apparatus realizing a screen using a laser is an optical scanning laser imaging system using a scanner. An optical scanning laser imaging system has mainly used a polygonal rotating mirror and a galvanometer mirror. The optical scanning laser imaging system using the polygonal rotating mirror or the galvanometer mirror is difficult to manufacture in a small size and a unit price thereof is high.
Considering above problems, the present applicant has suggested a laser imaging system using a scanner adopting a microelectromechanical system (MEMS), which is disclosed in a U.S. Pat. No. 6,636,339.
The laser imaging system using the MEMS scanner is one of promising projection display devices of small form factor, low power consumption, and natural color realization.
To realize a laser imaging system of a large-sized screen and high resolution by applying the MEMS scanner, a sufficient scanning speed, a wide scanning angle, and a large mirror size are required.
Since a laser beam is coherent light and diffraction occurs much while the laser beam propagates as the width of the laser beam is small, it is difficult to make the width of the laser beam infinitely small. Also, as is well known in the art, a light beam is not focused as a point due to diffraction nature thereof and thus there exists a limit of resolution. In addition, when the size of a light beam incident to a lens system is large, the size of the light beam focused gets small.
Therefore, it is required to make the size of the unfocused light beam large so as to raise resolution. A large scanning frequency and a large value θD are required to realize an image of high resolution. Image resolution of a laser beam scanning optical system is determined by an optical invariant represented by a product θD of the diameter D of a collimated beam and a beam scanning angle θ.
The performance of a raster scanning system is defined by θD [deg·mm]. A VGA class and a XGA class require θD of about 7.50 and about 12.0, respectively. It is known that a product θD of about 22.5 is required to realize a high definition class display. θ is a mechanical scanning angle (unit: degree) of a scanner in one direction and D is the width of a beam, i.e., the effective mirror size (unit: mm) of the scanner in a laser scanning apparatus.
To realize a high resolution imaging system, the mirror size of the MEMS scanner should be large. Also, to realize a large-sized, high resolution laser imaging system, a scanning speed should be fast.
However, when the mirror size is increased, it is difficult to make a maximum operation speed of the MEMS scanner fast due to a physical property such as the moment of inertia, so that a scanning speed gets slow. Therefore, it is difficult to make the mirror size large while making the scanning speed fast.
Also, it is impossible to make a scanning angle of the MEMS scanner infinitely large and thus the scanning angle is limited.
To realize a subminiature high performance laser beam projection display, the MEMS scanner capable of scanning in high speed is considered as a reliable beam scanning device, but it is not easy to design a high speed MEMS scanner realizing a high resolution image due to trade-off relationship between an operation speed, an operation angle, and a reflection mirror size in device design. Therefore, it is difficult to obtain an MEMS scanner capable of accomplishing a sufficient scanning speed and scanning angle to realize a high definition, high resolution display while meeting a sufficient mirror size using a current MEMS manufacturing technique.


A picture element conversion system consists of a simple electric circuit for reducing or enlarging an image at high quality. The system includes a cumulative adding unit for cumulatively adding a multiplying factor, in synchronization with clock signals, and outputting the added data and a carry signal. A contiguous picture element output unit temporarily holds a picture element data array along one of two scanning directions and outputs at least two contiguous picture element data. A typical value calculation unit divides a section defined by the contiguous picture element data into sub-sections and obtains typical values corresponding to each sub-section from the picture element data output from the contiguous picture element output unit. A typical value selecting unit selects and outputs only one value from among the typical values output from the typical value calculation unit in accordance with the added data of the cumulative adding means, and a control unit controls the contiguous picture element output unit and the cumulative adding unit in accordance with the carry signal and an externally supplied selection data to determine whether a reduction conversion or an enlargement conversion should be carried out.

1. Field of the Invention
The present invention relates to an image enlargement and reduction processor, more particularly, to an image enlargement and reduction processor used in a picture image processing apparatus, such as a digital copy machine and a facsimile machine, and a method thereof.
2. Description of the Related Art
In a known conventional picture element conversion system, an optical system of a picture image reader is shifted in order to enlarge or reduce a scale of a picture image projected on an image sensor, whereby a picture element density read by the image sensor is converted. Further, in another known picture element conversion system, the picture element density is converted by an electrical method, whereby the picture element density is fixed when reading. As conventional electric methods, a most contiguous picture element substitution method, linear interpolation method, third dimension function convolution method, and so on are known. Among these methods, the known interpolation method has a high image quality. When an interpolation calculation is carried out according to the interpolation method, however, it is necessary to use various kinds of multipliers and dividers, or to use a ROM table.
According to the conventional picture element conversion system in which the optical system of the picture image reader is shifted, the system suffers from disadvantages such that the mechanism of the system is complicated. Also, to obtain enough light intensity in the case of an enlargement projection, it is necessary to make a light intensity of a light source irradiating a paper for reading high requiring a high consumption of electric power. On the other hand, according to another conventional picture element conversion system in which the picture element density is converted by the electrical method, the system suffers from the disadvantages set forth below. Namely, where the electrical system consists of a simple electric circuit, the image quality obtained after the conversion of the picture element density is poor. Further, where the electric system consists of various kinds of multipliers and dividers, the image quality is better but the electric circuit is inevitably large and complicated. Furthermore, where the electric system contains the ROM table, precision of a multiplying factor of the picture element density conversion is restricted in accordance with a capacity of the ROM, and it is substantially impossible to vary the multiplying factor on a fine scale.

Image enlargement/reduction processor and method


A method for migrating a hierarchical layout between manufacturing processes is accomplished without specification of a technology file and design rules. Different scaling factors and bias values in the X and Y directions may be applied to each layer in the source hierarchical layout during the migration. In addition, the target hierarchical layout maintains connectivity, and is free of notches, jogs and small edges. A cell hierarchy tree is created, which guides expansion of the target hierarchical database to resolve issues related to rounding of floating point numbers to integers. Boolean operations are performed to determine the differences between target flat database and the target hierarchical database. The differences are eliminated by modifying the target hierarchical database to match the layout in the flat database.

1. Field of the Invention
The present invention relates to integrated circuits; in particular, the present invention relates to "scale and bias" layout migration methods used to adapt a layout of an existing integrated circuit that is designed for fabrication by one manufacturing process to another, typically more advanced, manufacturing process.
2. Discussion of the Related Art
In the integrated circuit (IC) industry, a circuit design and its corresponding "layout" (i.e., the physical implementation1) are often migrated from one fabrication process to a different, often more advanced, fabrication process. When a layout is migrated to a newer fabrication process, the physical dimensions in the layout are scaled down to achieve a smaller "chip size" or footprint and better performance. The well-known Moore's law predicts a doubling of IC performance every 18 months. At the same time, the size of an IC chip for a given complexity would also decrease, as a result of advance in process technology. As more advanced processes use smaller feature sizes, a layout targeted for fabrication in one process may be re-targeted for fabrication in a newer or different process. The designer typically prefers to reuse an existing layout as much as possible, rather than having to redesign the layout from "scratch," for time-to-market considerations, as the integrated circuit industry is under intense competition. 1A layout database that represents a layout is typically organized by layers, with each layer representing the image of a photo-lithographical mask. The image of each layer consists of a number of polygons that define areas through which light is allowed to pass or is occluded. The term "geometries" are also colloquially used for the polygons. In this description, the term "polygon" is used throughout interchangeably with the term "geometry."
In digital circuits, advanced development in computer-aided-design (CAD) tools and the cell-based design methodology made possible extensive reuse of cell-based digital designs. In contrast, for custom circuit designs (i.e., designs that do not follow a cell-based design methodology), CAD tools still require significant amount of manual intervention. Often, custom circuit designers have to rely on their past experience and expertise to achieve a desired performance. Migrating a custom design to a new fabrication process, or to a new design specification, often involves manual redrawing of many parts—if not all—of the layouts. Naturally, such a process is both time consuming and tedious. Therefore, a methodology for automatically migrating a layout to a new fabrication process or a new design specification is important, especially in light of design and turn-around times reduction considerations.
In migrating a layout between fabrication processes, "scale and bias" is a technique that is often used. The technique is used, for example, in the lambda design rule system, which is part of the original VLSI design flow proposed by Mead and Conway more than 30 years ago. In the lambda design rule system, any feature in the layout can naturally be scaled and biased from one fabrication process to another sufficiently similar fabrication process. The technique relies on the assumption that all geometry in the layout scale proportionally. However, this assumption is valid only when the two fabrication processes are sufficiently similar, and when the design rules are conservative and not optimized. The resulting scaled layout typically requires a larger silicon area than is desirable, as some techniques used in the original process may not be able to take advantage of minimum size or spacing for some features or elements in the target process. Over time, the lambda design rule system is replaced by a more complicated "micron design rule system" which uses in the layout database the actual dimensions in the design rules for the target fabrication process.
Historically, influenced by Moore's law, successively generations of fabrication processes typically reduce area requirements by one-half. This reduction means that the X and Y dimensions are each reduced by around 30% or, essentially, a scaling factor of about 0.7. Often, a fabrication process of intermediate dimensions may also be provided. In that case, the generational process would be known as a "full node" process, while the intermediate dimension fabrication process is known as a "half node" process. Other than the difference in feature dimensions, the half node process is often a minor variation of the full node process. Under the scale and bias technique, a layout may be scaled from a "full node process" to a "half node" process through a proportional reduction that can be performed substantially automatically by computer during preparation of the photo-lithographical masks. For example, the 45 nm process is a full node process and 40 nm process is a half node process. The layout can be migrated from 45 nm to 40 nm through a "90% shrink." The same reduction procedure can be performed for migrations from a 32 nm process to a 28 nm process and from a 22 nm process to a 20 nm process.
To illustrate a layout migration process, for a database resolution of 1 nm and a design grid unit of 1 nm, an edge in a polygon that is 23 units long is scaled to 20.7 units. For computational reasons, all stored dimensions in a layout database are typically expressed in integers. Therefore, in this example, the scaled edge is rounded to 21 units long, thus losing 0.3 units of accuracy. If the database resolution is decreased from 1 nm to 0.1 nm, then the scaled edge may be expressed as 207 units long at a 0.1 nm resolution, without loss of accuracy. In fact, it is typical that the manufacturing database has 10 times the resolution of the design database in anticipation of support for the shrink conversion to the half-node process. The 10 times resolution readily supports single significant digit scaling factors, such as 0.9, 0.8 or 0.7. To support two significant digit scaling factors, such as 0.75 or 0.71, the resolution in the manufacturing database needs to be two orders of magnitude greater than that of the design database. For this reason, the most frequently used scaling factor in the manufacturing database is 0.9, for approximately a 20% area reduction.
The scale and bias technique can only be applied to a "flat" database, however. The flat database is much larger than a hierarchical database, which is typically the form that is used for design. The flat database is not suitable for design use because of its size and also because modifying the layout in a flat database is difficult. If scaling is attempted in a hierarchical database, however, rounding errors may create connectivity problems, notches, jogs and small edges. Connectivity problems are detected in a layout versus schematic (LVS) check. Notches, jogs and small edges may be detected at a design rule check (DRC). For small blocks, such errors are few and manageable, and can be manually corrected. Correcting such errors is quite tedious and time consuming, nevertheless. For a medium to large circuit, the number of such errors may be prohibitively large for manual correction.
Conventional layout scaling requires the same scaling factor in both X and Y directions. In an advanced MOS fabrication process, circuit layout rules are driven by photo-lithographical limitations. One of the most important constraints is gate pitch, which is the center-to-center distance between the gates of two adjacent transistors. In an advanced process, the gates of neighboring transistors are required to have the same pitch or separation distance and further, such separation distance must be one of a limited number of pitches. Typically, all transistor gates are required to be aligned in the same direction. Such a requirement dictates the scaling factor applicable to the direction that is perpendicular to the alignment direction of the transistor gates. For example, if all gates of the transistors are aligned in the X direction, a fixed pitch is required between the gates in the Y direction. If the original process requires a gate pitch of 120 nm and the new process requires a gate pitch of 90 nm, then the scaling factor for the Y direction is 0.75. At the same time, if the transistor gates are aligned in the X direction, the transistor width after migration is determined by the X direction scaling factor. This scaling factor is significant, as the width of an MOS transistor is an important parameter that determines MOS circuit performance. Ideally, therefore, although the transistor gate pitch scaling factor (in this case the Y direction scaling factor) is determined by the process technology, the X direction scaling factor is determined by both process technology and design performance specifications. Thus, in most cases, the desired X and Y scaling factors are different. The different desired X and Y scaling factors make a traditional scale and bias method—which use the same X and Y scaling factors—ineffective for migrating real circuit design and layout.
Bias operations (i.e., growing or shrinking specific elements) are typically applied after the X and Y direction scaling operations are performed. The bias operations further refine the migration process to meet the requirements of the target process. In a lambda design rule system, all dimensions and design rules are scaled proportionally, which is not true of micron design rule systems that are used in practically almost all designs today. In a micron design rule system, although the design rules typically do not scale proportionally, the elements are scaled close to proportionality in general, so as to track an overall geometry shrinking scale. If the overall scaling for a given process is 70%, most dimensions and design rules would preferably be scaled around 70%. Consider a feature in the original layout measuring 90 nm in the X dimension. If the applicable scaling factor is 0.7, the resulting X dimension feature would be 63 nm after scaling. However, if the new design rule requires such a feature to be 65 nm, a bias operation is required to extend the feature by 2 nm, e.g., extending by 1 nm on each side in the X direction, in order to meet the new design rule. It is also often desirable to have different bias conditions in the X and Y directions. As scaling factors in the X and Y directions may be different, a square contact or via may become rectangular with unequal sides after scaling. Separate X and Y bias operations may be required to grow or shrink the migrated contact or via back to a square.
Most layout migration algorithms are based on layout compaction, which is a process that preserves the topology of the source layout. Typically, the user provides a technology file which describes the design rules of the target process. Since design rules have become very complicated for the advanced process, not all design rules can be coded into the technology file. In fact, for efficiency reason, often the basic design rules are the only ones coded in the technology file. Typically, the source layout is analyzed and each design rule is used as a constraint on all applicable elements in the layout. A reasonably optimized layout that satisfies these constraints can be obtained only by linear programming (LP) or graph-based algorithms. For a large layout, and as design rules have become increasingly complicated, even writing a technology file is a daunting task. Even a small block in a layout can result in applications of millions of constraints. Thus, even using linear programming or sophisticated techniques, the number of constraints and variables result in prohibitively long total runtime in a layout migration. Due to resource constraints, compaction algorithms are useful only on small circuits. As not all design rules can be coded into a technology file, manual corrections are inevitable for a complete layout migration. For medium to large circuits, the source layouts are divided into blocks and are migrated separately. The migrated blocks are subsequently integrated at the top-level. Even this top-level integration is not straightforward, as the operation may require further modifications of the already migrated lower-level blocks.
As a result, existing layout migration does not provide a complete solution, as the current methods can only work with a small block at a time and require integration of the migrated blocks.
Therefore, what is needed is a systematic approach to allow migration of entire layouts to new fabrication processes. Since existing layout migration tools can migrate only small, lower-level blocks efficiently, what is needed is a tool that can migrate the entire circuit efficiently, so as to eliminate the need for subsequent top-level integration. This approach must ensure that the migrated layout satisfies basic layout requirements, such as correct connectivity, transistor pitches, transistor gate lengths, metal widths, and contact or via sizes. The migrated circuit and layout should also satisfy a first-pass circuit performance requirement before further optimization is required. Such a migrated layout should be able to serve as a framework for lower-level block migrations using existing migration tools.
U.S. Pat. No. 5,640,497, entitled "LAYOUT REDESIGN USING POLYGON MANIPULATION" and U.S. Pat. No. 8,352,899, entitled "METHOD TO MODIFY AN INTEGRATED CIRCUIT (IC) DESIGN" each disclose layout modification. Other layout migration methods are disclosed, for example, in (a) U.S. Patent Application 20120304139, entitled "METHOD OF FAST ANALOG LAYOUT MIGRATION," (b) U.S. Patent Application 20110161907, entitled "PRACTICAL APPROACH TO LAYOUT MIGRATION," and (c) U.S. Patent Application 20130019219, entitled "SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUT."

Layout migration with hierarchical scale and bias method


An apparatus for impregnating fibrous strands with plastic material as matrix material including: an impregnating core having an outer limiting surface; an impregnating shell defining a cavity therein having an inner limiting surface, the impregnating shell completely enveloping the impregnating core and being disposed with respect to the impregnating core such that the limiting surfaces together define an impregnating channel therebetween, the limiting surfaces concentrically enclosing the impregnating channel along a joint symmetry axis such that the impregnating channel has a ring-shaped cross section in a plane transverse to the joint symmetry axis, the ring-shaped cross section having an outside dimension which diminishes by stages in a flow direction for the impregnation, feeding channels for the fibrous strands and the matrix material being defined at an intake side of the impregnating channel and a discharge opening for impregnated fibrous strands being defined at an exit side of the impregnating channel; and a plurality of expanding elements disposed on the limiting surfaces along the impregnating channel in the flow direction for the impregnation. A method for producing long fiber reinforced plastic materials or unidirectionally fiber reinforced profiles involves the use of the above apparatus in conjunction with an extruder or a pultrusion plant, respectively.

With such an impregnating apparatus on an extruder for feeding in a fibrous strand, known from DE 40 16 784 A1, the feeding in of the strand as well as the discharge of the strand following the impregnating occurs on a level plane, with little adaptability as to the requirements of the strand wetting. With another apparatus, known from DE 38 35 574 A1, continuously unidirectionally fiber-reinforced linear profiles can be produced. The extrusion-impregnating apparatus here consists of a level, divided housing. Excess material and glass fiber pieces, which have developed from broken fibers during impregnation, must be discharged via an overflow. The fiber content and the cross-sectional geometry of the linear profiles are adjusted via the discharge nozzle. The area of application for this apparatus is strongly limited because of the special features thereof. From EP 0 300 321 B1, it is known that fibrous bundles are pulled through a plastics chamber. The plastics chamber is fed from the side by an extruder with thermoplastic plastics melt. Rotary devices are installed in the plastics chamber for impregnating the fibrous bundles with molten thermoplastic plastic material and to apply a tension to the fiber bundle. However, said rotary devices permit only a limited adaptation to the requirements for impregnating the fibrous strands.
Further serious disadvantages result from the level arrangement of the above-described known designs. Thus, no satisfactory fiber strand guidance is possible, for example, for a central strand discharge that is desired for many applications, in which case the many individual fibrous strands must be combined to form a single strand or a strand profile. Another disadvantage of the known designs is the irregular flow of the melt in the impregnating nozzle, caused by edge influences or an asymmetric run of the fibrous strands. Furthermore, an application over a wide range is countered by the relatively expensive production engineering and the limited options for application. Last but not least, a compact design is no longer possible with the frequently required large number of individual fibrous strands.

Apparatus and method for impregnating fibrous strands with plastic material


A wine closure replaces the traditional cork and foil and includes a gasket/stopper which engages into the neck of the bottle. Encasing the finish and upper neck of the bottle is a plastic outer closure cap, generally cylindrical, with a top center disc which is adhered to the top of the stopper. A circle of frangible elements at the periphery of the disc provide for breakage of the disc away from the sleeve, causing it to remain with the stopper when the plastic cap is opened. Coarse, shortlength threads are formed on the outside of the container neck, spaced appreciably below the finish, to be engaged by internal thread lugs of the plastic cap. On initial unscrewing of the cap, the disc breaks away from the remainder of the cap. A small vertical clearance is provided in the engagement between the internal cap structure and the gasket/stopper, so that the cap does not begin to lift the gasket/stopper until static friction against the elastomeric gasket/stopper has been overcome.

This invention is concerned with closures for containers carrying liquids for human consumption. Specifically the invention relates to a closure having a tamper-evident feature with a virtually hermetic seal which can easily be removed by hand. In one aspect of the invention the closure is adapted for wine bottles and has been designed to provide an aesthetic image in keeping with quality wines and retaining the "ceremony" involved with opening a bottle of wine without the need for an opening instrument as is currently employed.
Throughout the world and for several centuries, wines have been contained in glass bottles with corks. Even today, wines of medium to high quality are still packaged in the same way, although some lower quality wines have screw-threaded closures or employ alternative packaging. Corks are traditionally manufactured in Portugal and come in a variety of grades, the quality of which is determined only visually. There is a shortage of high quality corks, making it difficult for smaller vintners to secure a cork of consistent quality. A percentage of wine becomes "corked" after filling, that is, tainted by cork taste due to imperfect corks. Although no accurate industry figure is available, 4% of production is not an unusual number. A fair percentage of wines sold commercially reach the consumer in a "corked" condition. Cork maintains a substantially hermetic seal if it is kept moist by storing the bottle on its side. However, if the cork dries out it will lose its hermeticity due to its open cellular nature. Some people believe this open cellular structure provides additional air pockets or even permits air exchange with exterior air, and that this will enhance the aging of wine, especially red wine; however, another school of thought also exists which believes that wine should be produced at the quality level required under controlled manufacturing circumstances and packaged in an hermetically sealed environment thereafter to ensure a consistent quality level to the consumer. Inevitably some aging, i.e. changes to the wine, will occur in the bottle whether the seal is hermetic or not.
The quality of corks varies greatly and as cork ages it deteriorates and eventually crumbles, prompting certain high quality producers such as Chateau Lafite-Rothschild (Chateau & Estates) to periodically send its staffers to key wine markets to recork older bottles for their customers. The reported fact that corkiness taints an estimated $2 billion to $3 billion worth of wine each year is staggering.
Additionally, recent reports from various vintners in the United States would indicate that there is a high percentage of leakers, the exact reason for which no one seems fully to understand. This is prompting various vintners to store bottles in an upright position, drying the cork, and thus affecting the long term hermeticity of the closure and reducing the long term shelf life of the beverage.
The problems associated with corks are well documented and several vintners have already begun to use alternative stoppers such as the synthetic cork "Cellukork" and a metal screw-threaded closure called "Vin-Lok".
The traditional lead capsule has also become a thing of the past due to the FDA's concerns regarding lead contamination. In response to this problem, many new capsule materials have recently been developed to overcome the problem, none being as easy to remove as the original lead product.
Further, there is a widely held opinion in the wine industry today that the traditional wine package is not "user friendly", in that a cork requires a tool to remove it from the bottle, deemed by some to be an unnecessary nuisance and a deterrent for many potential customers, including the elderly and those less mechanically inclined.
It is also clear that the traditional cork offers no protection whatsoever to tampering and that the package can easily be contaminated by use of a syringe, causing a considerable exposure and liability for wine producers.
It is an object of this invention to replace the traditional wine cork with a sanitary, safe, easily-used, tamper-evident closure which provides an hermetic seal, is aesthetically pleasing and maintains some semblance of the traditional ceremony involved with the opening of a bottle of wine.


The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly.

In order to improve both performance and integrity of integrated circuit chips, feature sizes of devices are scaled down continually in view of Moore's law, which nowadays have already reached into the nanometer regime. Traditional planar bulky Si CMOS technology cannot any more boost improvement in device performance and decrease power consumption at the meantime of improving integrity of circuits. Consequently, device parameters fluctuate randomly and the threshold voltage cannot be scaled down proportionally, which further brings limits on enhancement of whole device performance. In technology node of 45 nm and below, dramatically soaring short-channel effects also raise difficulties of further scaling down devices proportionally.
Fully depleted SOI (FDSOI) devices, which exhibit outstanding suppression of short-channel effects, excellent sub-threshold properties, small leakage currents and slight influence of random doping fluctuations, are regarded as preferred structures for replacing traditional bulky Si devices at technology node of 32 nm and below. FDSOI devices are usually configured with an ultra-thin (≦50 nm) SOI structure, thus decrease in thickness (≦50 nm) of buried oxide layer (BOX) can further improve device performance, lessen influences arising from self-heating effects, peripheral fields and the like. Besides, owing to introduction of a ground layer into the back face of ultra-thin BOX layer so as to enhance controls and regulations of back gates, such Ultra-Thin Body and BOX (UTBB) SOI devices are able to reduce electric fields coupling at source/drain regions and to increase controls of threshold voltages, such that they exhibit broad prospects of being utilized in applications of low power consumption. However, circuit area has been increased inevitably due to introduction of back gate contact and relevant wiring, thereby increasing manufacturing cost. Therefore, for UTBB SOI devices, how to find a balance between optimal device performance and costs has now become a critical problem that is waiting for a solution.

FDSOI semiconductor structure and method for manufacturing the same

Institute of Microelectronics, Chinese Academy of Sciences


A turbine housing of an exhaust gas turbocharger with a variable turbine geometry is provided, having a support ring to which vanes are fastened which are adjustable for controlling the charge pressure, and having a covering ring for the vanes. The support ring and covering ring are spaced for forming a vane gap by spacing elements which are each penetrated by a holding element which is fastened in the support ring and/or the covering ring. The spacing elements have recesses which, during the operation of the exhaust gas turbocharger, permit a direct action of the exhaust gas flow upon the holding elements.

The invention relates to a turbine housing of an exhaust gas turbocharger with a variable turbine geometry.
Exhaust gas turbochargers, in the case of which the supercharging pressure can be controlled by means of adjustable vanes, are known, for example, from German Patent Document DE 103 12 324 B3. In the turbine housing of such VTG (variable turbine geometry) chargers, a vane apparatus is fastened which consists of a support ring for the vanes, as well as a covering ring which is situated opposite the support ring while maintaining a vane gap distance. For the spacing of the support ring and the covering ring, spacing elements, for example, in the form of spacing sleeves, are provided which are arranged to be radially distributed around the circumference of both rings, which spacing elements are held or penetrated by corresponding fastening elements, for example, in the form of fastening screws. Particularly when these VTG chargers are used in the case of Otto engines, these components are exposed to high exhaust gas temperatures. In this case, the spacing elements, which are penetrated by the holding elements, are particularly critical. When the spacing elements are acted upon by a hot exhaust gas flow, they correspondingly expand in the longitudinal direction, while the holding elements are still relatively cold. This may lead to an unacceptable linear expansion of the holding elements beyond their yielding point. Conversely, in the event of a subsequent load jump (full load to lower partial load), first the spacing element is cooled by the exhaust gas flow while the holding element is still relatively hot. This leads to a faster shrinking of the spacing element with respect to the holding element. If the holding element is constructed as a fastening screw, this results in a loss of prestressing force. As a result of loss of prestressing force, the fastening screw now has to absorb all transverse forces occurring because of the engine operation, which, under certain circumstances, may lead to component failure of the fastening screw.
It is an object of the invention to overcome the above-described disadvantages so that a reliable continuous operation of the VTG charger is guarantied.
As a result of recesses provided in the spacing elements, it is ensured that also the holding element is directly acted upon by the exhaust gas mass flow. While the material characteristics are the same or similar, this leads to a uniform expansion or shrinkage behavior of both components, so that a durable fastening is guarantied.
The characteristics indicated below allow additional developments and further developments of the turbine housing or of the vane apparatus for a VTG charger.
The recesses, which permit a direct action upon the holding elements by means of the exhaust gas flow, are advantageously placed in the generated surface of the spacing elements.
In this case, the recesses are constructed in a simple manner as bores, for example, four bores, which are each placed radially offset by 90 degrees with respect to one another in the generated surface.
As a second embodiment, the recesses are constructed as slots which are made from the direction of the face of the spacing elements.
Recesses, in which the spacing elements engage with their faces in a form-locking manner, are provided in the support and covering ring. This results in a fit by way of which transverse forces are absorbed, so that the holding elements are essentially free of transverse forces at this point.
Other objects, advantages, and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Turbine housing of an exhaust gas turbocharger with a variable turbine geometry

Dr. Ing. h.c.F. Porsche Aktiengesellschaft


The invention provides an emitter tube for an irrigation system, the tube being of resiliently flexible material having a base inlet end adapted to be mounted and a free outlet end adapted to be unmounted, the arrangement being such that, with liquid flowing at a sufficient rate through the emitter tube, hydraulic forces exerted by the flowing liquid on the tube cause the outlet end continuously to move about, further having a base section and an end section downstream from the base section when the end section is of greater flexibility than the base section.

1. Field of the Invention
THIS invention relates to an emitter tube suitable for an irrigation system.
2. Description of Related Art
The Applicant's U.S. Pat. No. 4,915,312 discloses an irrigation system which includes a sprinker device for liquids comprises an emitter tube of resiliently flexible material having a base inlet end adapted to be mounted and a free outlet end adapted to be un-mounted, the arrangement being such that, with liquid flowing at a sufficient rate through the emitter tube, hydraulic forces exerted by the flowing liquid on the tube cause the outlet end continuously to move about. The emitter tube is mounted on a fitting which has a flow passage there through which leads into the emitter tube, the flow passage having, at its inlet end, a pair of grooves which lead tangentially into the flow passage. These tangentially arranged grooves impart a swirling motion to water entering the emitter tube. A pop-up sprinkler is also disclosed in which the emitter tube is mounted on a plunger which is displaceable in a barrel, the emitter tube protruding through an opening at the end of the barrel.
This system is further disclosed in the Applicant's U.S. Pat. No. 4,856,552 which relates to a flow regulating device suitable for use in the above system.
The specifications of these U.S.A. patents are incorporated into this specification by way of reference. It has been found that the emitter tube which is disclosed in the above United States patents, lends itself to advantageous modifications for certain applications.
For example, in certain applications a greater radius of throw of irrigation water is desirable and it has been found that the emitter tube can be modified to achieve such a results.
Also for example a more even water distribution with a single sprinkler as well as water distribution with sprinklers laid out on the standard group spacing could be achieved by modifying the emitter tube. Further for example where the size of the droplets of irrigation water is to be controlled, the emitter tube could likewise be modified to achieve such a result.


An outer mirror includes: a mirror base which is attached to a side surface of a vehicle body of a vehicle; a shaft which is erected on the mirror base; and a mirror housing which is rotatably attached to the shaft and is provided with a mirror for reflecting a rearward of the vehicle body. The shaft is exposed in a gap between a top surface of the mirror base and a bottom surface of the mirror housing. The shaft includes at least one of a concave portion or a convex portion on a part of an outer circumferential surface of the shaft which faces to a front side of the vehicle body.

1. Field of the Invention
The present invention relates to an outer mirror that is attached to a side door of a vehicle or to the vicinity of the side door.
2. Description of the Related Art
A conventional outer mirror includes, as its main parts, a mirror base attached to a side surface of a vehicle body, a shaft erected on the mirror base, a mirror housing that is rotatably attached to the shaft and is provided with a mirror for reflecting the rearward of a vehicle.
In such an outer mirror, since the mirror housing is rotatable with respect to the mirror base, the top surface of the mirror base and the bottom surface of the mirror housing are opposed to each other with some gap in between. Because of the gap, a whistling noise is generated by a wind blowing through the gap between the mirror base and the mirror housing when the vehicle is running.
In some conventional mirrors, a plurality of dimples is formed on the top surface of the mirror base or the bottom surface of the mirror housing to generate a turbulence in the wind blowing through the mirror base and the mirror housing so that whistling noise is reduced (disclosed in Japanese Patent Application Publication No. 11-78695), for example.
The above described configuration in which a plurality of dimples is formed on the top surface of the mirror base or the bottom surface of the mirror housing, however, has a problem that the whistling noise can not be reduced which is generated by a wind hitting the outer circumferential surface of the shaft exposed in the gap between the mirror base and the mirror housing.


A cache module leverages a logical address space and storage metadata of a storage module (e.g., virtual storage module) to cache data of a backing store. The cache module maintains access metadata to track access characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not currently in the cache. The access metadata may be separate from the storage metadata maintained by the storage module. The cache module may calculate a performance metric of the cache based on profiling metadata, which may include portions of the access metadata. The cache module may determine predictive performance metrics of different cache configurations. An optimal cache configuration may be identified based on the predictive performance metrics.

Cache devices may be used to improve the input/output performance of a computing system. A cache device may comprise a high-performance storage device, such as a volatile memory, non-volatile storage (e.g., Flash storage), or the like. Cache devices can be leveraged most effectively by selectively admitting frequently accessed data. A cache can be "poisoned" by admitting less-frequently accessed data. This less-frequently accessed data may consume the limited capacity of the cache to the exclusion of more frequently accessed data, which may obviate the performance benefits of the cache. Moreover, information pertaining to storage operations, such as storage recovery operations, may not be communicated to the cache, which may obviate potential performance benefits.

Systems and methods for profiling a non-volatile cache having a logical-to-physical translation layer

Intelligent Intellectual Property Holdings 2 LLC


By repeating a purification process of a light-emitting organic compound several times, a thin film made of the light-emitting organic compound to be used in an EL display device contains ionic impurities at the concentration of 0.1 ppm or lower and has a volume resistivity in the range of 3×1010 Ωcm or larger. By using such a thin film as a light-emitting layer in the EL device, a current caused by reasons other than the carrier recombination can be prevented from flowing through the thin film, and deterioration caused by unnecessary heat generation can be suppressed. Accordingly, it is possible to obtain an EL display device with high reliability.

1. Field of the Invention
The present invention relates to a light-emitting organic compound (including a complex that contains a metal in its molecular formula) capable of providing Electro Luminescence (EL), and an EL display device utilizing the same. Typically, the present invention relates to a high-molecular type EL display device which utilizes a light-emitting organic compound made of a high-molecular compound.
The present invention also relates to an electronic apparatus including the above-mentioned EL display device as its display portion. It should be noted that the above-mentioned EL display device will be also referred to as the OLED (Organic Light-emitting Diode).
2. Description of the Related Art
Development of a display device including an EL layer as a self-light emitting element that utilizes EL phenomenon (i.e., the EL display device) has been proceeded in these years. Since the EL display device is of the self-light emitting type, no back light is required to be contained therein, unlike a liquid crystal display device or the like. Moreover, the EL display device exhibits a wide viewing angle. From the above features, the EL display device is advantageous to be used as a display portion for a portable device which is likely to be used outdoors.
A light-emitting layer as a principal portion of the EL element is made of an insulating material. When a voltage is applied across a cathode and an anode with the light-emitting layer interposed therebetween, carriers (electrons and holes) are injected into the light-emitting layer and recombined to emit light. Thus, a current flowing through the light-emitting layer is caused by the recombination of carriers. An EL material that can be used for the EL display device is described in, for example, Japanese Patent Application Laid-Open No. Hei 2-311591.
In a light-emitting element such as a light-emitting diode in which a semiconductor junction is formed, Na (sodium) that may exhibit an adverse effect as a movable ion causes a resistance value of the light-emitting layer to decrease, and therefore, can cause a current flow other than that caused by the carrier recombination. When such an unnecessary current flows, an amount of heat generation is increased and the light-emitting layer is more likely to deteriorate. The same disadvantage may occur in the EL device. However, any sufficient countermeasure against the disadvantage caused by the movable ion has not been provided for the EL material.

Light-emitting organic compound with improved reliability

Semiconductor Energy Laboratory Co., Ltd.


A method of content delivery executed by a computer is provided. The computer specifies an identifier of a content associated with an user identifier, an identifier of a device at a delivery destination of the content, and time until data of the content is delivered to the device at the delivery destination, when event data including the user identifier read by a sensor is received. The computer calculates, from the specified time, a clock time to start content sending to the device at the delivery destination of the content or a clock time to start data sending to a device that carries out the content sending, and stores these data, and sends the stored data to the device of the delivery destination, at a clock time that is stored in the data storage unit.

For example, there is a behavioral targeting advertising system that displays advertisement recommended for individual persons in accordance with a situation at that time, such as preference of a person that is understood from a purchase history and the like and an air temperature.
In such a system, it is sought to deliver a content real-time. For example, in an advertisement display system in a railroad yard, in a case of displaying advertisement on an automatic vending machine, a customer looks at the panel only for several seconds approximately, so that it turns out to finish a series of process, from input of a user identifier (ID) to display of advertisement, in a few seconds (for example, one second through two seconds).
That is, as a user ID is inputted to an automatic vending machine, process of determining a content to be presented to the user and delivering data of the content to the automatic vending machine for display is finished in a few seconds, thereby enabling the user to look at the content.
However, in a case of delivering data of a content utilizing server resources that are put into one distant data center, there is a problem of delivery delay that is derived from communication delay. In general, the throughput between an automatic vending machine with a display that is located in a downtown and a server that is located at a data center is low (approximately several Mbps) and the size of a video content to be delivered is large (several tens of megabits). For example, when the throughput is 10 Mbps and the content size is 60 megabits, it takes six seconds for delivery while a user is often not willing to wait as much as six seconds.
Regarding such a problem related to the time for display, the following techniques are proposed. That is, a center server obtains an event indicating that a user has come near a display device from an entrance and exit system of a building or the like to deliver a content, taking it as a trigger, for that user to a cache server near the display device in advance. This enables to display the content immediately as the user places an IC card or the like over the display device for reading of the user ID.
However, such techniques have a configuration of sending an event from an entrance and exit system directly to a center server, so that as the number of users increases, events focus on the center server and a decrease in the processing speed of the center server sometimes occurs.
Examples of related art may include Japanese Laid-open Patent Publication No. 2008-252735, Japanese Laid-open Patent Publication No. 2004-310593, Japanese Laid-open Patent Publication No. 2009-100057, and Matoba, K.; Abiru, K.; Ishihara, T., "Service oriented network architecture for scalable M2M and sensor network services", Intelligence in Next Generation Networks (ICIN), 2011 15th International Conference on 4-7, Oct. 2011, pp. 35-40.

Method of content delivery, information processing device, and information processing system