A composite vehicle wheel hub includes an inner wheel hub portion formed from a first material and an outer wheel hub portion formed from a second material and joined to the inner wheel hub portion. A method for producing the composite vehicle wheel hub of this invention includes the steps of: (a) providing one of an inner wheel hub portion and an outer wheel hub portion formed from a first material; (b) placing the one of the inner wheel hub portion and the outer wheel hub portion in a mold; (c) casting the other one of the inner wheel hub portion and the outer wheel hub portion formed from a second material in situ within the mold to thereby produce the composite vehicle wheel hub; and (d) removing the composite vehicle wheel hub from the mold.

This invention relates in general to a vehicle wheel end assembly and in particular to an improved structure for a wheel hub for use in such a vehicle wheel end assembly and method for producing such a composite vehicle wheel hub.
A typical vehicle wheel end assembly for a front wheel of a vehicle includes a wheel hub, a steering knuckle, and a bearing assembly. The wheel hub is supported by the bearing assembly and the bearing assembly is secured to a non-rotatable component of the vehicle, which in this case is the steering knuckle, so as to rotatably support the wheel hub relative thereto. In the case of a driven wheel application, the wheel hub can include an internal bore provided with internal splines for receiving mating external splines provided on an axle for rotatably connecting the wheel hub to the axle for rotation therewith. In the case of a non-driven wheel application, the wheel hub does not include the internal splines.
The wheel hub also includes a generally radially outwardly extending flange. The flange includes a plurality of circumferentially spaced stud receiving holes formed therein. The stud receiving holes are adapted to receive studs and nuts for securing a rotatable brake component, such as for example a brake rotor and a vehicle wheel to the wheel hub for rotation therewith.
To secure the bearing assembly and the wheel hub together for rotation with one another and also to preload the bearing assembly, a spanner nut is installed on a threaded inner end of the wheel hub and tightened to a predetermined torque in order to exert a predetermined clamp load on the bearing assembly. U.S. Pat. No. 6,089,673 to Wiacek et al. shows such a design in prior art FIGS. 1–3. Alternatively, a threaded retention nut or non-threaded retention ring can be installed on a respective threaded or non-threaded inner end of the wheel hub and the inner end of the wheel hub can be deformed outwardly to secure the bearing assembly and wheel hub together and to preload the bearing. U.S. Pat. No. 6,089,673 to Wiacek et al. shows such designs in FIGS. 4–7 and 9–12.

Composite vehicle wheel hub and method for producing same


An organic light emitting device and a method of manufacturing the same are provided. The organic light emitting device, from bottom to top, includes a substrate, an indium tin oxide layer, a semiconductor layer, and a pixel defining layer. The semiconductor layer covers foreign particles on the indium tin oxide layer to make the indium tin oxide layer have an even thickness. The method of manufacturing the organic light emitting device including steps of providing an indium tin oxide layer, providing a semiconductor layer, patterning, and providing a pixel defining layer. The disclosure prevents from uneven brightness (mura) causing from a bright spot or a dark spot appearing at the foreign particles and ensures an overall even brightness of the organic light emitting device by providing the semiconductor layer disposed on the indium tin oxide layer to cover foreign particles on the indium tin oxide layer.

Organic light emitting diodes (OLEDs) have been widely used in display field, lighting field and smart wearable device field due to their good self-luminous characteristics, high contrast and fast response times.
Main methods for preparing organic light emitting devices are vapor deposition and printing. Now, technologies of preparing large, medium or small-sized organic light-emitting devices by full evaporation method are quite mature compared with printing technology, and have been used for commercial production. However, full evaporation technology has a problem that material utilization rate is low and it is difficult to prepare a high-resolution device. The material utilization rate of the printing technology preparing device is as high as 90% or more. Cost of preparing the device by the printing technology is about 17% lower than that of the full evaporation technology. Masks are not required in the printing process. The printing technology can be used for preparation of a high-resolution display device. Therefore, preparation of large-size, and high-resolution organic light-emitting devices is a research hotspot in the display field.
FIG. 1 is a schematic diagram of a process for fabricating an organic light emitting device using a prior art printing process. The printing process is as follows: forming an indium tin oxide layer 2 on a substrate 1, and preparing a wall structure 41 (bank) after pattering the indium tin oxide layer 2. The indium tin oxide layer 2 at the bottom is a hydrophilic substance, the surrounding wall structure 41 is a hydrophobic substance, and area of an edge portion of the indium tin oxide layer 2 overlays with the wall structure 41. However, it was found in the printing process that there are micron-sized foreign particles 21 in some of pixels on a surface of the indium tin oxide layer 2, so that causing a foreign object protrusion at a thin functional layer 42 after drying when the printing process is completed. Thereby causing a problem of uneven brightness (mura) because a bright spot or a dark spot appearing at the foreign particles 21 when the device emits light, therefore, resulting in overall uneven brightness of the organic light-emitting device.
Therefore, there is a need to solve the above problems.

Organic light emitting device and method of manufacturing same

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.


In a frequency hopping communications receiver an automatic gain control process in which the mean signal strength of bursts of different frequencies and co-channel interference are detected, a weighted average based on the signal strength and co-channel interference is formed and the weighted average is used as a gain control signal.

In the GSM system, each base station is assigned a group of transmitting frequencies for communication channels. The base station can switch at regular intervals between such transmitting frequencies in a predetermined sequence. Each mobile telephone in the service zone of a base station receives data from the base station to enable it to establish a pattern of frequency-hopping to receive data transmitted in its communication channel.
The mobile telephone receiver has several control loops which track, for example, timing, frequency and signal strength of the bursts and operate to ensure that the receiver remains in synchronism with the transmitter and to provide a usable signal to the following stages.
In the particular case of an automatic gain control loop, for example, changes in signal strength are a result of normal attenuation dependent on the distance between transmitter and receiver, shadow fading effects caused by a physical object blocking the direct path and Rayleigh fading caused by the receiver moving through multiple reflected signals. Shadow fading has a spacial correlation which may be assumed to be unity over many wavelengths. The Rayleigh fading, however, may be totally uncorrelated between bursts.
It is usual to exclude the effects of Rayleigh fading by averaging over a plurality of bursts.
A problem arises, however, if co-channel interference is present at one of the hopping frequencies. Such interference will make the signal strength at that frequency greater although the signals being received are, in fact, unwanted. Gain will be reduced for all frequencies.

Frequency hopping communications receivers


A myogenic protein isolate from mammalian bone is provided that stimulates lineage commitment and differentiation of stem cells in vitro and in vivo. The protein isolate is characterized by its ability to cause muscle stem cell differentiation without excessive proliferation of connective tissue proximal to the delivery site. Treated muscle stem cells differentiate into myotubes and multinucleated structures with minimal formation of scar tissue, resulting in functional muscle tissue restoration in vivo, and therefore useful in the treatment of a number of disorders and injuries. The protein isolate is preferably administered by implanting a bioerodible polymer matrix, preferably a surface erodible polymer such as a polyanhydride or a polyorthoester, interspersed with the protein isolate near the site of muscle injury or degeneration, but can be administered directly to cells cultured in vitro.

Mammalian skeletal muscle normally undergoes a reparative process after traumatic injury. The process of skeletal muscle repair is actually a series of discrete overlapping events, which can be segregated into trauma, tissue degeneration, inflammation, phagocytosis, angiogenesis, stem cell activation, migration of the stem cells to the site of injury, proliferation of undifferentiated stem cells, reinnervation, differentiation of the stem cells, and remodelling of the tissue.
The early restored muscle tissues approximate embryonic-like myotubes containing centrally-located nuclei and lie adjacent to mature myofibers containing peripherally-located nuclei. Unfortunately, restoration of physiological function is compromised due to the increased proliferative nature of the surrounding connective tissues, eventually forming non-functional scar tissue.
To circumvent the decreased function due to scar tissue formation, Carlson and Faulkner, Med. Sci. Sports Exerc. 15:187-198 (1983); Faulkner and Carlson, Fed. Proc. 45:1454 (1986); and Donovan and Faulkner, J. Appl. Physiol. 62:2507-2511 (1987) severed existing vascular and nervous tissue connections prior to grafting homologous and autologous muscles. This procedure apparently inhibited myogenic differentiation of cultured cells and Faulkner and colleagues reported some restoration of function using it.
Research in other areas has indicated that various factors such as platelet derived growth factor (PDGF), chicken muscle growth factor (CMGF), epidermal growth factor (EGF), sciatic nerve extract, insulin, and somatomedins stimulate a mitogenic or proliferative response in cultured muscle cells. This response should be contrasted with a myogenic response which does not induce myogenic lineage commitment of uncommitted stem cells, but instead induces the lineage commitment of the stem cells.
Three growth factors, insulin and insulin-like growth factors, namely insulin-like growth factor-I (IGF-I), also called somatomedin-C, insulin-like growth factor-II (IGF-II), also called myogenic stimulating activity, have been shown to be potent stimulators of skeletal muscle cell growth and differentiation in cultured myosatellite cells and myogenic lineage-committed stem cells by Ewton and Florini, Dev. Biol. 83:31-39 (1981); Florini et al., J. Biol. Chem. 261:16509-16515 (1986); Florini et al., Am. J. Physiol. 250:C771-778 (1986); Sejersen et al., Proc. Natl. Acad. Sci. 83:6844-6848 (1986); Ewton et al., Fed. Proc. 45:1454-1455 (1987).
Several in vivo studies have employed basic-fibroblast growth factor (b-FGF), transforming growth factor beta (TGF-.beta.), and epidermal growth factor (EGF) to stimulate internal wound healing. Buckley et al., Proc. Natl. Acad. Sci. 82:7340-7344 (1985); Grotendorst et al., J. Clin. Invest. 76:2323-2329 (1985); Franklin et al., J. Lab Clin. Med. 108:103-108 (1986); Roberts et al., Proc. Natl. Acad. Sci. 83:4167-4171 (1986); Mustoe et al., Science 1987; Sprugel et al., Am. J. Path. 129:601-613 (1987); and Davidson et al., Prog. Clin. Biol. Res. (1988) noted that administration of b-FGF, TGF-.beta.B, and EGF appeared to promote proliferation of connective tissue elements to form scar tissue and thus aid in wound healing of mammalian skeletal muscle.
In vitro studies have demonstrated the influence of other growth factors on the resultant phenotypic expression in myogenic cultures. For example, Hauschka and co-workers have reported that acidic-fibroblast growth factor (a-FGF) and basic-fibroblast growth factor (b-FGF) play a dual role in stimulating myoblast proliferation while directly repressing terminal differentiation, as described by Linkhart et al., Dev. Biol. 86:19-30 (1981), the chapter of Linkhart et al. entitled "Control of mouse myoblast commitment to differentiation by mitogens." In: Molecular and Cellular Control of Muscle Development. M. L. Pearson and H. F. Epstein, eds., Cold Spring Harbor Laboratory, New York, p. 377-382 (1982); Lim and Hauschka, J. Cell Biol. 98:739-747 (1984); and Olwin and Hauschka, Biochemistry 25:3487-3492 (1986).
Unfortunately, the administration of growth factors that inhibit terminal myogenic differentiation, promote myoblast proliferation, and promote fibroblast proliferation and differentiation as a method to promote muscle repair appears to cause an increase in connective tissue scar formation. In muscle, increased scar formation creates decreased physiological function. A decrease in connective tissue scar formation with a compensatory increase in skeletal muscle mass plus revascularization and reinnervation of the tissues is necessary for the restoration of physiological function.
Implantation of demineralized bone into ectopic sites (i.e., intramuscular pouch, subcutaneous pouch) result in the induction of cartilage and bone within these tissues, as reported by Urist, Science 150:194-199 (1965); Urist et al., Clin. Orthopaed 64:194-220 (1969); and Reddi and Huggins, Proc. Nat. Acad. Sci. USA 69:1601-1605 (1972). Young et al, Anat. Rec. 223:231-241 (1989), demonstrated the existence of stem cells, arising from the connective tissues associated with muscle, cartilage, and bone, that contributed to the blastemal population during epimorphic limb regeneration in the adult terrestrial salamander. Combined, this work suggest the potential for the presence of quiescent uncommitted stem cells or quiescent lineage-committed stem cells located within or nearby these tissue matrices that upon the appropriate stimulus would form differentiated tissues. The stimulus or stimuli required for differentiation is not known.
A number of delivery systems have been proposed for administration of various drugs and other biologically active compounds. The most promising for practical reasons are the polymer based systems, as described, for example, for general drug delivery using the bioerodible polyanhydrides, in U.S. Pat. No. 4,906,474 to Langer, et al., U.S. Pat. No. 4,888,176 to Langer, et al., and U.S. Pat. No. 4,757,128 to Langer, et al. The more specific use of polymeric delivery systems for administration of antibiotics to bone is described in U.S. Ser. No. 07/810,324 entitled "Bioerodible Polymers for Drug Delivery in Bone" filed Dec. 19, 1991 by Gerhart, et al., the more specific delivery of osteogenic factors is described in U.S. Ser. No. 07/313,953 entitled "Delivery System for Controlled Release of Bioactive Factors" filed February 1989 by Laurencin, et al.
It would be advantageous if muscle morphogenic factors could be identified and delivered to the area around bone or in injured areas, especially if the factors are water soluble and likely to disperse rapidly in vivo, which would be useful in enhancing healing of muscle injuries without a concomitant increase in scarring.
It is therefore an object of the present invention to provide a myogenic differentiating composition.
It is a further object of the present invention to provide a method of restoring functional mammalian muscle with minimal scar formation.
It is another object of the present invention to provide a delivery system for a myogenic differentiating composition.

Muscle morphogenic protein and use thereof


A driving position adjusting device comprises a seat-position adjusting mechanism to adjust height and seat-face angle of a seat cushion in accordance with longitudinal movement of a driver's seat, and a floor adjusting mechanism to adjust a height of a floor board in accordance with the operation of the longitudinal adjustment of the driver's seat, wherein the seat-position adjusting mechanism is configured so that an inclination angle of the seat cushion becomes smaller as the driver's seat is moved forward from a middle position, and the floor adjusting mechanism is configured so that the height of the floor board becomes higher as the driver's seat is moved forward from the middle position. Accordingly, the sitting position of the driver and the operational function of the operational pedal can be provided properly regardless of the body size of the driver.

The present invention relates to a driving position adjusting device that adjusts a driving position of a driver seated in a driver's seat properly.
Conventionally, such a driving position adjusting device is known as disclosed in Japanese Patent Laid-Open Publication No. 2006-44422, for example, which comprises a body-size detecting means for detecting a body size of a driver, an operational pedal, such as a brake pedal, to be pressed-operated by the driver, a movable floor portion that is provided near the operational pedal so as to be movable vertically, and a movable-floor-portion adjusting means for adjusting the height of the movable floor portion. Herein, the movable-floor-portion adjusting means is configured so that the adjusted height of the movable floor portion is changeable in accordance with the body size of the driver detected by the body-size detecting means in such a manner that the height of the movable floor portion becomes higher when the driver's body size is smaller. Further, the above-described driving position adjusting device further comprises a seat adjusting means that can move a seat cushion of the driver's seat in a vehicle longitudinal direction so as to adjust a vertical position and a longitudinal position of the seat cushion and also adjust an inclination angle of the seat cushion, so that the sitting position can be properly adjusted in accordance with the body size of the driver so as to provide appropriate positions of driver's eyes and its relative position to a steering wheel.
According to the above-described driving position adjusting device, the proper adjustment of the moving amount (height) of the movable floor portion may improve the operational function of the operational pedal. However, since the longitudinal position, vertical position and inclination angle of the seat cushion are respectively changed in accordance with the body size of the driver as described above, the sitting position of the driver would change too much. Thus, there is a problem in that it would be difficult to adjust the moving amount (height) of the movable floor portion properly, so that the position of the driver would be unstable or the operational function of the operational pedal would deteriorate.
That is, in a case where the drivers change, the new driver may try to move the driver's seat to a proper position for him/her by operating a seat-position adjusting mechanism so that the appropriate front view can be obtained by placing the height of his/her eye point on the appropriate eye line. Herein, however, since the vertical position and the inclination angle of the seat cushion change at the same time in accordance with the longitudinal movement of the driver's seat, the sitting position of the driver, more specifically, an upright angle of the driver's upper body relative to the horizontal line, a knee angle of the driver that is a bending angle between the driver's thigh portion and knee-lower portion and the like may change, and the operational function of the operational pedal may change accordingly. Accordingly, there is a problem in that even if the position of the movable floor portion was adjusted merely based on the size of the driver's foot according to the body size of the driver, both the sitting position of the driver and the operational function of the operational pedal could not be improved properly at the same time.
Meanwhile, another type of driving position adjusting device is disclosed in U.S. Patent Application Publication No. 2005/0109555 A1. This device can provide various useful advantages, but it might still have room for improvement in solving the above-described particular problem.


A structure and method for demodulating two-level differential amplitude-shift-keying signals using simple adding operations are provided. Threshold values are dynamically adjusted according to the channel response. By comparing the threshold values and the differential amplitude values, it can be found whether the amplitude of the received signal is changed. Furthermore, it no needs to know the changed value of received signal amplitudes and the differential two-level amplitude-shift-keying signals can be demodulated by just detecting whether the amplitude of the received signal is changed. By this idea, the complexity of the receiver implementation is simplified and the demodulator can get better performance.

1. Field of the Invention
The present invention relates to a demodulating mechanism of a communication system. More particularly, the present invention relates to a demodulation mechanism utilizing two-level differential amplitude-shift-keying and a communication system using the same.
2. Description of the Related Art
In this modern world, communication techniques and communication systems play very important roles in daily life. Popular communicating systems include mobile phones and wired/wireless networks. In recent years, in the wire/wireless network and digital terrestrial broadcasting applications, orthogonal frequency division multiplexing (OFDM) transmission techniques based on multi-carrier modulation are useful in overcoming multi-path reflection effects. The multi-path reflection effects originate when, in digital communication or broadcasting application, information signals in the form of electromagnetic waves are transmitted from a transmitter through a physical channel (for example, air) to a receiver. Due to the non-ideal properties of the physical channel, multi-path reflection and attenuation occur so that the input signals are distorted.
According to the modulation technique applied, the OFDM system can be categorized as coherent OFDM systems and non-coherent OFDM systems. For coherent modulation at the receiver of the coherent OFDM system, the transmitter transmits pilot signals and information signals. The receiver performs channel estimation and equalization operation based on pilot signals and compensates for distortion due to channel effects. Popular coherent OFDM systems applying quadrature amplitude modulation (QAM) include: digital video broadcasting-terrestrial (DVB-T), asymmetric digital subscriber line (ADSL), very-high-speed digital subscriber line (VDSL) and wireless local area network (WLAN) 802.11a/g/n.
In the non-coherent OFDM system, the transmitter utilizes differential modulation to transmit the difference (the relative magnitude instead of the absolute magnitude) between neighboring transmitted signals. The receiver uses reverse differential demodulation techniques to recover the transmitted signal. The compensation for channel effect is already existed within the differential demodulation process. Non-coherent OFDM systems applying differential quadrature-phase-shift-keying (D-QPSK) include: digital audio broadcasting (DAB), home plug and integrated services digital broadcasting-terrestrial (ISDB-T).
The coherent OFDM system and the coherent OFDM system have drawbacks and merits. The non-coherent OFDM system has two major advantages: firstly, no frequency bandwidth sacrificed in transmitting the pilot signal at the transmitter; and, secondly, a simple receiver because no channel estimation and equalization are required. However, the non-coherent OFDM system also has its drawbacks. The non-coherent OFDM system has a worse theoretical demodulating performance than the coherent OFDM system.
The aforementioned non-coherent OFDM system uses the D-QPSK modulation technique. Hence, the corresponding demodulation just requires simple multiplication operations. Furthermore, using the differential phase-shift-keying (D-PSK) in the same bandwidth for increasing the number of phase bits increases the efficiency of the frequency spectrum in the non-coherent OFDM system. Although this method can still get aforementioned advantages, higher signal-to-noise ratio (SNR) will lead to significant drops in the operation efficiency of the system. Therefore, the differential amplitude—phase-keying (D-APSK) modulation technique has been developed for the non-coherent OFDM system to increase its spectrum efficiency. Nevertheless, the D-APSK modulation technique combines the differential phase-shift-keying (D-PSK) technique and the differential amplitude-shift-keying (D-ASK) technique together.
In the following the D-ASK signal modulation and related conventional techniques are described. The first conventional technique is disclosed in the U.S. patent application publication No. 2004/00366471, titled "Differential amplitude detection diversity receiver". The first conventional technique uses a divider to serve as a diverse antenna receiver for demodulating the received D-ASK signal.
In the first conventional demodulation technique, three devices, an absolute value unit, a delay unit and a divider unit, are used to demodulate the differential amplitude signal and the result is transmitted to an amplitude selection unit for evaluating the magnitude of the amplitude. Since the method of determining the differential amplitude requires a divider, the implementation is highly complicated.
The second conventional demodulation technique is disclosed in U.S. Pat. No. 5818875, titled "Modulation and demodulation method, modulator and demodulator". The second conventional technique uses a logarithmic-to-linear conversion to demodulate the D-ASK signals. In the second conventional technique, the amplitude of the input signals is transformed to logarithmic value so that the division operations with linear values are implemented by subtraction operations with logarithmic values. After obtaining a difference value in the logarithmic domain, it is converted back to a linear value in the linear domain so that a differential quantity is produced. This replacement method for division is more aptly applied to an analog circuit design. If implemented in digital, a look-up table is needed in the logarithmic/linear area conversion. Ultimately, the sophistication in hardware implementation is a problem.
The third conventional demodulation technique is disclosed in U.S. Pat. No. 6,148,007 titled "Method for data transmission in a digital audio broadcasting system". The D-ASK signals are demodulated according to the following schemes:|R[n]|<|R[n−1]|*((1+a/b)/2)→u[n]=1,|R[n]|>|R[n−1]|*((1+b/a)/2)→u[n]=1,otherwise,u[n]=0.In the aforementioned equations, R[n] and R[n] and R[n−1] are transmitted from the transmitter, 'a' and 'b' represent the amplitude of the transmitted signal, and u[n] is the amplitude bit determined by the receiver. In practice, if |R[n−1]| on the right side of the inequality is moved to the left side, and then it is equivalent to a division.
The fourth conventional demodulation technique is disclosed in U.S. Pat. No. 6,046,629 titled "Method of an apparatus for demodulating amplitude-modulated signals in an amplitude-phase-shift-keying (APSK) system". The fourth conventional demodulation technique can be regarded as using the third conventional demodulation technique in a corresponding demodulation device. The threshold value acquisition circuit and the amplitude change decision circuit are major devices.
In the D-APSK demodulation technique, the D-PSK signal demodulation is simple while the D-ASK signal demodulation is sophisticated. The D-ASK signal demodulation is based on the concept of using divider. However, division circuits are more sophisticated. Moreover, demodulation based on division frequently leads to enhance noise effect in the demodulated signals and reduces the demodulation capacity. Hence, how to effectively demodulating D-ASK signals has become a critical point in designing the receiver of a communication system.

Communication system with demodulation of two-level differential amplitude-shift-keying signals

Industrial Technology Research Institute


The invention relates to a semiconductor component, in which regions of the conduction type opposite to the conduction type of the drift zone are incorporated in the drift zone and also in the region of the active zones.

The invention relates to a semiconductor component having at least two electrodes that are provided on a semiconductor body and a drift zone of one conduction type, which is located between the at least two electrodes in the semiconductor body.
DE 198 00 647 C1 describes an SOI high-voltage switch having an FET structure, in which a drift zone of one conduction type is provided between a gate electrode and a drain electrode in the drain region. Incorporated in this drift zone are pillar-like trenches in the form of a lattice which are filled with semiconductor material of the other conduction type. An SOI high-voltage switch, which can be produced in a simple manner for practically any desired lateral extents and has a high dielectric strength in conjunction with a low on resistance, is intended to be provided in this manner.
Junction Barrier Schottky (JBS) diodes, the semiconductor body of which comprises silicon carbide for enhancing the performance and increasing the switching speed, are furthermore disclosed in IEEE Transactions on Electron Devices, Vol. 49, No. 11, November 2002, Ranbir Singh et al. "High-Power 4H-SiC JBS Rectifiers".


A method for producing a cis-9, trans-11 fatty acid from a fatty acid containing double bonds in the cis-configuration at positions 9 and 12, includes the step of combining a Lactobacillus microorganism with free fatty acids in a fermentation process. The conjugated fatty acid products can include, for example, cis-9, trans-11 conjugated linoleic acid (CLA).

Linoleic acid is an 18 carbon molecule that contains double bonds in the cis-9, cis-12 configuration. Conjugated linoleic acid (CLA) is a general term for a set of positional and geometric isomers of linoleic acid that possess conjugated double bonds, in the cis or trans configuration, at positions 9 and 11 or at positions 10 and 12. CLA occurs naturally in a wide variety of foods, especially in foods such as cheese that are derived from ruminant animals. Ha, Y. L., N. K. Grimm and M. W. Pariza, Carcinogenesis, Vol. 8, No. 12, pp. 1881-1887 (1987); Ha, Y. L., N. K. Grimm and M. W. Pariza, J. Agric. Food Chem., Vol. 37, No. 1, pp. 75-81 (1987).
CLA is now recognized as a nutritional supplement and an effective inhibitor of epidermal carcinogenesis and forestomach neoplasia in mice, and of carcinogen-induced rat mammary tumors. CLA can prevent adverse effects caused by immune stimulation in chicks, mice and rats, and can decrease the ratio of low density lipoprotein cholesterol (LDL-cholesterol) to high density lipoprotein cholesterol (HDL-cholesterol) in rabbits fed an atherogenic diet. CLA also reduces body fat in mouse, rat and chick models. The effective behavior of CLA in such animal systems suggests similar benefit when provided in the human diet. In contrast, linoleic acid, the precursor of CLA is associated with enhancing mammary cancer in rodents.
Methods of using CLA are described in issued U.S. Pat. Nos. 5,017,614; 5,070,104; 5,208,356; 5,428,072; 5,430,066; 5,504,114, and 5,554,646.
Linoleic acid can be converted to CLA by chemical methods (American Oil Chemists' Society Official Method Cd 7-58, pages 1-11, American Oil Chemists' Society, Champaign, Ill. (1973), or by enzymatic isomerization. The non-toxic salts of the free CLA acids may be made by reacting the free acids with a non-toxic base. Natural CLA may also be prepared from linoleic acid by the biological action of .DELTA..sup.12 -cis, .DELTA..sup.11 -transisomerase from a harmless microorganism such as Butyrivibrio fibrisolvens, a strictly anaerobic rumen bacterium, that produces both a cis-9, trans-11 CLA isomer and a cis-9, trans-11, cis-15 linolenic acid isomer as intermediates in the biohydrogenation of linoleic acid and linolenic acid, respectively. Kepler, C. R., et al., J. B. C. 245:3612-3620 (1970); see also Kemp, P. et al., J. Gen. Microbiol. 90:100-114 (1975), Mills, S. C. et al., Aust. J. Biol. Sci. 23:1109-13 (1970), Verhulst, A. et al., FEMS Microbiol. Ecol. 31:255-259 (1985), Fujimoto, K. et al., Biosci. Biotech. Biochem. 57:1026-1027 (1993), and Eyssen H. and A. Verhulst, Appl. Environ. Microbiol. 47:39-43 (1984). Jack, C. I. et al., Clinica Chimica Acta 224:139-146 (1994) purport to identify a large number of bacteria that convert linoleic acid into CLA. However, no reliable analytical methodology was presented. It is more likely that linoleic acid was oxidized rather than converted to CLA. Harmless microorganisms in the intestinal tracts of rats and other monogastric animals may also convert linoleic acid to CLA (S. F. Chin, W. Liu, K. Albright and M. W. Pariza, 1992, FASEB J.6:Abstract #2665). The presence in rumen of bacteria that possess linoleate isomerase, such as B. fibrisolvens, could explain the high concentration of CLA in tissues obtained from ruminant animals. B. fibrisolvens is not commercially useful to produce CLA from its free fatty acid precursor because it is a very strict anaerobe that is difficult to grow, even under laboratory conditions. In addition, B. fibrisolvens has an undesired reductase activity that converts the active products to other compounds. Other rumen bacteria are known to hydrogenate cis, cis linoleic acid isomers having double bonds at positions 5 and 8, 8 and 11, 11 and 14 to octadecanoic acid (Kemp, P. and Lander, D. J., Brit. J. Nutr. 52:171 (1984)).
Nicolosi, R. J. et al, "Dietary Conjugated Linoleic Acid Reduces Aortic Fatty Streak Formation Greater than Linoleic Acid in Hypercholesterolemic Hamsters" Circulation 88 (suppl.), 2458 (1993), and Lee, K. L. et al. "Dietary Conjugated Linoleic Acid and Atherosclerosis in Rabbits" Atherosclerosis 108:19-25 (1994) established that CLA inhibits atherosclerosis in rabbits and hamsters.
Fairbank, J. et al., The Lancet p. 329, Aug. 6, 1988, reported detecting cis, trans isomers of 18:2(9,11) in cultures of Lactobacillus. However, this paper presented no standards, and, given the difficulties inherent in sorting out bacterial metabolism, thus included no credible evidence for making CLA using a bacterial system. This report was refuted by Thompson, S. and M. T. Smith, Chem. Biol. Interactions J. 55:357-366 (1985), which showed that a method described by Fairbank did not produce authentic CLA, but rather oxidized linoleic acid.
Uchida, K., Aqr. Biol. Chem. 39:561-563 (1971) describes a strain of Pediococcus that synthesizes certain unspecified CLA isomers de novo and deposits them in its membrane. The strain does not use linoleic acid as a substrate for a linoleate isomerase enzyme. Moreover, the strain produces numerous isomers. Even if one is active, it represents too small a fraction of the total production of conjugated fatty acids to make the strain commercially practical.
Verhulst, A. et al., System. Appl. Microbiol. 9:12-15 (1987) describes the production of trans-10, cis-12 CLA by Propionibacterium acnes. This organism is a pathogen that includes a reductase that reduces the useful trans-10, cis-12 product to other non-CLA fatty acid products.
Of the various positional and geographic isomers present in CLA, the cis-9, trans-11 isomer is believed to be an active form, at least for the anticarcinogenic activity of CLA. Between 76 and 92% of the CLA isomers in uncooked meat is in the cis-9, trans-11 configuration. In processed plant oils, about 42% of the isomers were in the cis-9, trans-11 configuration and another 42% were in the trans-10, cis-12 configuration, as was the case in CLA prepared chemically from linolic acid. The trans-10, cis-12 CLA isomer may also have biological activity of the type described, but it has not been possible to prepare quantities of this isomer enzymatically for testing. It is also thought that CLA is not unique in this ability, but rather that cis-9, trans-11 and trans-10, cis-12 isomers of other fatty acids will have comparable biological activities.
It is known that linoleic acid can be efficiently converted to CLA when the linoleic acid is provided in the form of free fatty acid, rather than as a triglyceride.
It would be desirable to obtain a microorganism capable of producing the active isomer or isomers of CLA and other conjugated fatty acids, where the organism is easily grown and used and is food-safe.

Method of producing conjugated fatty acids


An apparatus and method for accelerating interpreters, interpretive environments, and the like optimizes the use of caches closest to a processor. An instruction set implementing a virtual machine (interpreter, interpretive environment) is written to fit each instruction at an individual cache line's address in the processor cache. The processor cache may be loaded with the instruction set in a compiled, linked, loaded image. After loading the processor cache, the cache is pinned, locked, disabled from flushing the contents or replacing the contents of any cache line. Faster loading of the processor cache may be achieved by flushing the processor cache and running an application containing all of the instructions of the virtual machine instruction set. Level-1 processor caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention. Examples include Intel's Pentium.TM. class products and Motorola's Power PC Processors.

1. The Field of the Invention
The invention relates generally to computers hosting interpreted languages and emulators, and more specifically to accelerators for emulators and interpreters such as Windows.TM., JAVA, Visual Basic, and other virtual machine environments executable by processors having access to caches.
2. The Background Art
Operations executed by a processor of a computer proceed in a synchronization dictated by a system clock. Accordingly one characteristic of a processor is a clock speed. For example, a clock speed may be 33 megahertz, indicating that 33 million cycles per second occur in the controlling clock.
A processor may execute one instruction per clock cycle, less than one instruction per clock cycle, or more than one instruction per clock cycle. Multiple execution units, such as are contained in a Pentium.TM. processor, may be operated simultaneously. Accordingly, this simultaneous operation of multiple execution units, arithmetic logic units (ALU), may provide more than a single instruction execution during a single clock cycle.
In general, processing proceeds according to a clock's speed. Operations occur only as the clock advances from cycle to cycle. That is, operations occur as the clock cycles. In any computer, any number of processors may exist. Each processor may have its own clock. Thus, an arithmetic logic unit (ALU) may have a clock operating at one speed, while a bus interface unit may operate at another speed. Likewise, a bus itself may have a bus controller that operates at its own clock speed.
Whenever any operation occurs, a request for interaction is made by an element of a computer. Then, a transfer of information, setup of input/output devices, and setup of the state of any interfacing devices, must all occur.
Each controller of any hardware must operate within the speed or at the speed dictated by its clock. Thus, clock speed of a central processing unit does not dictate the speed of any operation of a device not totally controlled by that processor.
These devices must all interface with one another. The slowest speed will limit the performance of all interfacing elements. Moreover, each device must be placed in the state required to comply with a request passed between elements. Any device that requires another device to wait while some higher priority activity occurs, may delay an entire process.
For example, a request for an instruction or data within a hard drive, or even a main, random-access memory, associated with a computer, must negotiate across a main system bus. A central processing unit has a clock operating at one speed. The bus has a controller with a clock that may operate at another speed. The memory device has a memory management unit that may operate at another speed.
Further to the example, a Pentium.TM. processor having a clock speed of 100 megahertz may be connected to peripheral devices or main memory by an industry standard architecture (ISA) bus. The ISA bus has a specified clock speed of 8 megahertz. Thus, any time the Pentium.TM. processor operating at 100 megahertz requests data from the memory device, the request passes to the opposite side of the ISA bus. The data may not be processed or delivered at a speed greater than that of the bus at 8 megahertz. Moreover, a bus typically gives low priority to the central processing unit. In order to avoid underruns and overruns, the input/output devices receive priority over the processor. Thus, the 100 megahertz processor may be "put on hold" by the bus while other peripheral devices have their requests filled.
Any time a processor must access any device beyond its own hardware pins, the hardware interface to the computer outside the processor proper, the required task cannot be accomplished within one clock count of the processor. As a practical matter, a task is not usually completed in less than several clock counts of the processor. Due to other priorities and the speeds of other devices, as well as the need to adjust or obtain the state configurations of interfacing devices, many clock counts of a processor may occur before a task is completed as required.
Associated with every hardware interface between hardware components, elements, and the like (anything outside an individual integrated chip), a hardware handshake must occur for any communication. A handshake, including a request and an acknowledgement, must occur in addition to a transfer of actual data or signals. Handshake protocols may actually involve several, even many, clock counts for the request alone, the acknowledgement alone, and for passing the data itself. Moreover, a transmission may be interrupted by a transaction having a higher priority. Thus, communicating over hardware interfaces is relatively time consuming for any processor. Hardware interfacing may greatly reduce or eliminate the benefits of a high-speed processor.
To alleviate the need to communicate across hardware interfaces during routine processing, modern computer architectures have included caches. In general, processors benefit from maintaining as close to themselves as possible all instructions, data, and clock control. This proximity reduces the need for interfaces, the number of interfaces, the interface complexity, and thus, the time required for compliance with any instruction or necessary execution. Thus, caches have been moved closer and closer to the processor.
Memory caches are common. Such a cache is created within a dedicated portion of a memory device. These are different, however, from caches dedicated to a processor.
The INTEL 386.TM. processor contains an optional external cache connected to the processor through a cache controller chip. The INTEL 486.TM. contains an internal 8 kilobyte cache on the central processing unit itself. Within the chip containing the processor, is integrated a cache. This cache is dedicated to both code and data accesses.
The 486.TM. also supports another cache (a level-2 cache, as opposed to the primary or level-1 cache just described above). Access to the level-2 cache is through an external cache controller chip, similar to that of the 386.TM.. In each case, for both the 386.TM. and 486.TM. processors, the external cache controller is itself positioned on a side of the processor's internal bus (CPU bus) opposite that of the processor.
The Pentium.TM. processors contain a level-1 (primary) data cache as well as a level-1 code cache. Thus, code and data are segregated, cached separately. The Pentium.TM. processors continue to support an external, level-2 cache across a CPU bus.
One should understand that the expression "bus", hereinabove, refers to the processor bus, rather than the system bus. For example, the main system bus connects a processor to the main memory. However, the cache controllers and caches on a processor, or external to the processor but simply located across a processor's internal bus interface unit, do not rely on the main system bus.
A cache has some fixed amount of memory. A code cache will contain certain executable instructions, a data cache will contain data, and a non-segregated cache may contain both. The memory of any type of cache is typically subdivided into cache lines. For example, a typical cache line may contain 32 bytes of information. Thus, a cache line contains a standard number of bytes in which space may be stored a copy of certain information obtained from a main memory device.
Associated with each cache line is a tag. The tag binds a physical address and a logical address corresponding to the contents of an associated cache line.
The physical and logical addresses contained in the tag associated with a cache line may correspond to a physical location in the main memory device, and a logical position within an application respectively.
Caches associated with a processor are transparent, even hidden, with respect to a user and an application. Each cache has an associated controller. In operation, a cache controller effectively "short circuits" a request from a processor to a memory unit. That is, if a particular address is referenced, and that address exists in a tag associated with the contents of a cache line in a cache, the cache controller will fulfill the request for the instruction out of the cache line containing it. The request is thus fulfilled transparently to the processor. However, the effect of a cache is to eliminate, as much as possible, communication through hardware interfaces as described above. Thus, a cache may greatly improve the processing speed of applications running on processors.
Tags may also have associated therewith two numbers referred to as "use bits." The use bits may typically represent a simple count of use. This count may be useful to the cache controller in determining which cache lines are the least recently used. Accordingly, a cache controller may refer to the least recently used (LRU) count to determine which cache lines have been referenced the least number of times.
Incidently, but significantly, with respect to the invention, some cache controllers may churn a cache. That is, if an insignificant number of bits is contained in the LRU or use bits, then a counter may be improperly reset to zero due to count "wrap-around" during high use. Thus, highly-used cache lines may actually be swapped out, churning the cache and dramatically decreasing efficiency.
Several difficulties exist with caches. A cache controller has a general purpose function to service address requests generally. For example, a virtual machine may be implemented in some limited number of instructions. In operating such a virtual machine, a computer processor has an underlying native language in which the virtual machine instructions are written. The virtual machine instructions will be requested repeatedly. The virtual machine instructions are accessed relatively slowly if they are treated simply as another general purpose instruction being retrieved periodically into the cache.
Many processors pipeline instructions. Two problems may occur with pipelining. The first is flushing a pipeline as a result of a branch. The other is stalling due to requested data not arriving within a next clock count in sequence. That is, whenever a cache "miss" occurs, a request has been made to the cache, but the cache cannot respond because the information is not resident. Misses may occur repeatedly over extensive numbers of clock counts while a cache controller accesses a main memory device to load the requested instructions or data. Misses decimate the efficiency of processors. Meanwhile, even with branch prediction methods, a pipeline may flush several instructions with a resulting loss of processing performance.

Accelerator for interpretive environments


In one embodiment, techniques are shown and described relating to dynamically determining node locations to apply learning machine based network performance improvement. In particular, a degree of significance of nodes in a network, respectively, is calculated based on one or more significance factors. One or more significant nodes are then determined based on the calculated degree of significance. Additionally, a nodal region in the network of deteriorated network health is determined, and the nodal region of deteriorated network health is correlated with a significant node of the one or more significant nodes.

Low power and Lossy Networks (LLNs), e.g., Internet of Things (IoT) networks, have a myriad of applications, such as sensor networks, Smart Grids, and Smart Cities. Various challenges are presented with LLNs, such as lossy links, low bandwidth, low quality transceivers, battery operation, low memory and/or processing capability, etc. is The challenging nature of these networks is exacerbated by the large number of nodes (an order of magnitude larger than a "classic" IP network), thus making the routing, Quality of Service (QoS), security, network management, and traffic engineering extremely challenging, to mention a few.
Machine learning (ML) is concerned with the design and the development of algorithms that take as input empirical data (such as network statistics and states, and performance indicators), recognize complex patterns in these data, and solve complex problems such as regression (which are usually extremely hard to solve mathematically) thanks to modeling. In general, these patterns and computation of models are then used to make decisions automatically (i.e., close-loop control) or to help make decisions. ML is a very broad discipline used to tackle very different problems (e.g., computer vision, robotics, data mining, search engines, etc.), but the most common tasks are the following: linear and non-linear regression, classification, clustering, dimensionality reduction, anomaly detection, optimization, association rule learning.
One very common pattern among ML algorithms is the use of an underlying model M, whose parameters are optimized for minimizing the cost function associated to M, given the input data. For instance, in the context of classification, the model M may be a straight line that separates the data into two classes such that M=a*x+b*y+c and the cost function would be the number of misclassified points. The ML algorithm then consists in adjusting the parameters a,b,c such that the number of misclassified points is minimal. After this optimization phase (or learning phase), the model M can be used very easily to classify new data points. Often, M is a statistical model, and the cost is function is inversely proportional to the likelihood of M, given the input data. Note that the example above is an over-simplification of more complicated regression problems that are usually highly multi-dimensional.
Learning Machines (LMs) are computational entities that rely on one or more ML algorithm for performing a task for which they haven't been explicitly programmed to perform. In particular, LMs are capable of adjusting their behavior to their environment (that is, "auto-adapting" without requiring a priori configuring static rules). In the context of LLNs, and more generally in the context of the IoT (or Internet of Everything, IoE), this ability will be very important, as the network will face changing conditions and requirements, and the network will become too large for efficiently management by a network operator. In addition, LLNs in general may significantly differ according to their intended use and deployed environment.
Thus far, LMs have not generally been used in LLNs, despite the overall level of complexity of LLNs, where "classic" approaches (based on known algorithms) are inefficient or when the amount of data cannot be processed by a human to predict network behavior considering the number of parameters to be taken into account.

Dynamically determining node locations to apply learning machine based network performance improvement


A cosmetic container, such as a lipstick container, having a tubular inner sleeve rotatable within a tubular outer sleeve and a cosmetic carrier positioned therein. The cosmetic container may be extended and retracted for the application and storage of the cosmetic. The inner sleeve includes a shank defining a longitudinal slot for receiving lugs extending radially outward from the cosmetic carrier and a manually rotatable base. The shank includes at least one radially outwardly facing rib extending circumferentially along at least a portion of the shank. Preferably a plurality of ribs extend from the inner sleeve and are positioned in a flexible region thereof. The outer diameter of the ribs is at least equal to the inner diameter of the outer sleeve to create torque therebetween.

The quality of cosmetic containers, such as lipstick containers, is often indicative of the quality of the cosmetic contained therein. From the consumer's standpoint, a high quality lipstick container has a certain "feel" to it, rotating freely due to its relatively low swivel torque but having enough "resistance" or torque to feel "sturdy". It is within this range of preferred torque which cosmetic companies strive to achieve when crafting cosmetic containers.
Conventional lipstick containers include a cosmetic carrier, a tubular inner sleeve, a tubular outer sleeve and a decorative sleeve. The cosmetic carrier supports the lipstick and is generally configured as a sleeve having radially extending lugs on opposing sides and is received within the inner sleeve. The inner sleeve defines longitudinally extending channels on opposing sides wherein the lugs of the cosmetic carrier extend therethrough. An outer sleeve defining a continuous helical channel is positioned about the inner sleeve wherein the lugs of the cosmetic carrier are configured to be received and to traverse along the length of the helical channel. This results in the cosmetic carrier being moved upwardly as the lugs traverse the length of the helical channel when a bottom portion of the inner sleeve is rotated. The decorative outermost sleeve is provided for aesthetic purposes. In operation, a bottom portion of the inner sleeve extends beyond the bottom of the outer decorative sleeve. The user rotates the bottom portion to cause the cosmetic carrier and, hence, the lipstick to extend from the case for applying the lipstick and to retract into the case for storage.
It is particularly desirable to provide a lipstick container having an inner sleeve which may be effortlessly rotated within the outer sleeve but which has enough torque to feel sturdy. The prior art includes several attempts at achieving the desired amount of torque, many of which experience significant shortcomings. For example, many are complicated, relatively expensive to manufacture, require exact tolerances, or experience wear over extended use thereby adversely effecting torque produced between the relatively rotating sleeves.

Cosmetic container having an inner sleeve for creating torque


A semiconductor memory device including a clock buffer, a column selection line decoder, a control signal generation circuit, and a column selection line driver is provided. The clock buffer receives an external clock signal and information about a column address strobe (CAS) latency and generates either a first clock signal which synchronizes with rising edges of the external clock signal or a second clock signal which synchronizes with falling edges of the external clock signal depending on the type of CAS latency information. The column selection line decoder receives and decodes a column selection address and outputs a decoding address used to select either a column selection line signal synchronized with the first or second clock signal. The control signal generation circuit outputs control signals that synchronize with one of the first and second clock signals. The column selection line driver drives the column selection line signal in synchronization with one of the first and second clock signal in response to the decoding address and the control signals.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having different synchronizing timings depending on a column address strobe (CAS) latency (hereinafter, referred to as a CL).
2. Description of the Related Art
As the operating frequency of a semiconductor memory system gradually increases, the performance of a semiconductor memory increases. Semiconductor memories are developed to have high frequency bandwidths. Synchronous DRAMs (SDRAMs) are synchronous semiconductor memories manufactured using a pipelining technique. SDRAMs are classified as single data rate (SDR) SDRAMs or double data rate (DDR) SDRAMs. An SDR SDRAM controls an output data buffer to be enabled/disabled in synchronization with the rising edge of every clock, that is, in synchronization with every clock cycle. A DDR SDRAM controls an output data buffer to be enabled/disabled in synchronization with every rising edge and every falling edge of a clock, that is, in synchronization with every half a clock cycle.
Hence, in an SDR SDRAM, a column address strobe (CAS) latency (hereinafter, referred to as a CL), which represents the reaction interval between the time when a column address is input to the memory until the time when data is output from the memory, must vary in units of one clock cycle, such as, CL=1, CL=2, CL=3, and the like. On the other hand, in a DDR SDRAM, the CL must vary in units of half a clock cycle, such as, CL=2, CL=2.5, CL=3, and the like. Accordingly, a DDR SDRAM requires a higher frequency bandwidth and a greater timing margin than those required by an SDR SDRAM.
FIG. 1 is a timing diagram of signals when data is read from a conventional DDR SDRAM. Referring to FIG. 1, outputting of data from the memory cells of a page selected by a row active operation is based on a column selection line signal CSL. The column selection line signal CSL is produced once during a cycle of an external clock signal EXTCLK. When a data read command READ is received after an external active command ACTIVE, the column selection line signal CSL is produced in synchronization with a rising edge of the external clock signal EXTCLK. When the CL is 2, data is read out in synchronization with a rising edge of the external clock signal EXTCLK that is two clock cycles after the data read command READ has been input. When the CL is 2.5, data is read out in synchronization with a falling edge of the external clock signal EXTCLK that is 2.5 cycles after the data read command READ has been received. When the CL is 3, data is read out in synchronization with a rising edge of the external clock signal EXTCLK that is three cycles after the data read command READ has been received.
Time between the timing of a rising edge of the external clock signal EXTCLK at which the data read command READ is received and the timing of readout of first data DQ0 is referred to as tAA. Also, tRCD (where RCD is an abbreviation of RAS-to-CAS Delay) denotes time corresponding to several clocks delayed until a CAS command is received after a reception of a row address strobe (RAS) command. In FIG. 1, tRCD is the time interval from when the external active command ACTIVE is received to when the data read command READ is received. The RAS command is a command to activate a specific page within a memory. Only after the page is activated, a CAS command is received so that data can be input to and/or output from the memory. A page denotes a specific address block within a memory.
FIG. 2 is a timing diagram of signals when a conventional DDR SDRAM is controlled in a CSL controlling approach. Referring to FIG. 2, the conventional DDR SDRAM is designed so that a column selection line signal CSL is controlled in response to rising edges of a clock signal. Both when a CL is 2.5 and when the CL is 3, the column selection line signal CSL is controlled in synchronization with a rising edge 200 of the external clock signal EXCLK. That is, in both cases, the column selection line signal CSL is enabled or disabled at an identical timing.
A first pulse of a first read pulse signal FRP, which is generated to initially read cell data, is produced in synchronization with a rising edge 210, which is one clock behind a rising edge at which a read command READ is received. A second pulse of the first read pulse signal FRP is produced in synchronization with a rising edge 220, which is one clock behind the rising edge 210. Since the pulses of the signal FRP are produced in response to a CSL signal, the timing of the signal FRP when the CL is 2.5 is identical to that when the CL is 3.
On the other hand, the pulses of a second read pulse signal SRP are produced at different timings depending on the value of a CL. When the CL is 2.5, a first pulse of the signal SRP is produced in response to a falling edge 230, which is one clock and a half after the receipt of the read command READ, and a second pulse is produced in response to a falling edge 240, which is one clock after the clock falling edge 230. When the CL is 3, a first pulse of the signal SRP is produced in response to a rising edge 250, which is 2 clocks after the receipt of the read command READ, and a second pulse is produced in response to a rising edge of the signal EXTCLK which is one clock after the rising edge 250. Consequently, a difference between the pulse timing of the signal SRP where CL=2.5 and that where CL=3 is half a clock.
Since the CSL signal is controlled in response to the clock rising edge 200 both when the CL is 2.5 and when the CL is 3, tAA margins within a memory when the CL is 3 are the same as those when the CL is 2.5. Consequently, the conventional DDR SDRAM is designed so that there is no big difference in a tAA margin controlling way between when the CL is 2.5 and when the CL is 3. That is, there is no difference in the pulse timing of the signal CSL or FRP, which determines a read tAA performance, between when the CL is 2.5 and when the CL is 3. There is only a difference of half a clock between the pulse timing of the signal SRP when the CL is 2.5 and that when the CL is 3. Hence, a difference in tRCD, which is a core parameter, between the two cases of CL=2.5 and CL=3 is hardly expected. A gain that can be obtained when the CL is 3 cannot be considered extremely greater than that when the CL is 2.5. That is, a path along which tRCD is determined when the CL is 2.5 is identical to the path when the CL is 3.
The conventional DDR SDRAM is also designed so that when the CL is 3, a first pulse of the signal SRP and a second pulse of the signal FRP are produced at an identical clock (which is indicated by both reference numerals 220 and 250). However, in the conventional DDR SDRAM designed as describe above, if the waveform of the signal SRP is deformed due to a severe jitter of an internal delay locked loop (DLL), the falling edge of the first pulse of the signal SRP moves into the second pulse of the signal FRP. Thus, the conventional DDR SDRAM may fail to operate.
FIG. 3 is a timing diagram of signals when a DLL of the conventional DDR SDRAM jitters. Referring to FIG. 3, when the CL is 3, the rising edge of a second pulse of the signal FRP is earlier than the falling edge of a first pulse of the signal SRP. In this case, an error may be generated during data reading or the like, resulting in a malfunction of the conventional DDR SDRAM. This problem may be generated when the FRP and SRP signals have insufficient pulse-timing margin, since the signal FRP is controlled in response to the external clock signal EXTCLK and the signal SRP is controlled by the internal DLL. Also, as a semiconductor memory is being developed so as to operate within a high frequency range, the interval between clocks becomes narrow. In this case, a timing margin between pulses of the signals SRP and FRP when CL=3 becomes important.

Semiconductor memory device having different synchronizing timings depending on the value of CAS latency


This invention relates to a method and apparatus for short-messaging in a communication network. More particularly, the invention is directed to an improved method for short-messaging which allows for a service that is adaptable to different communication networks and complies with accepted standards in the industry. The system utilizes a unique UUI format that allows for improved short-messaging service and short-messaging service-based information retrieval.

This invention relates to a method and apparatus for short-messaging in a communication network. More particularly, the invention is directed to an improved method for short-messaging which allows for a service that is adaptable to different communication networks and complies with accepted standards in the industry. The system utilizes a unique message format that allows for improved short-messaging service and short-messaging service-based information retrieval.
While the invention is particularly directed to the art of short-messaging and is described with specific reference to the personal handyphone system (PHS), it will be appreciated that the invention may have usefulness in other fields and applications. For example, the invention may have application in other wireless and wireline networks which are compatible with the described message format.
By way of background, the PHS is a wireless system which has been deployed in Japan and other countries such as Thailand, China, Taiwan, . . . etc. The PHS system is built on existing wireline public network by using ISDN signaling (a subset of Q.931 and Q.932 messages).
Because the PHS system is implemented in different environments in different countries, a short-messaging service that is adaptable to such different environments is desired. In this regard, it is desirable that a short-messaging service meet the ITU-T standards and provide seamless operation between country borders.
For example, user-to-user information (UUI) elements may have a format generally defined by ITU-T recommendation Q.931 and RCR STD-28 (both of which are incorporated herein by reference), as illustrated in FIG. 1. As shown, the UUI format is eight (8) bits in width and may have a maximum length of 131 octets or bytes. A user-to-user information (UUI) element identifier 12, a user-to-user content length 14, a protocol identifier 16 and user information 18 are part of the content of the UUI 20. However, no known short-messaging services meet the above stated objectives and complies with the relevant standards, in terms of User-to-User Signaling which carries User-to-User information (UUI) shown in FIG. 1, and in terms of flexibility and SMS-based service completeness.
The present invention contemplates an improved short-messaging service system that resolve the above-referenced objectives and others.

Method and apparatus for supporting short-messaging in a communication network


A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.

Automated or automatic test systems are widely used by manufacturers in the electronics industry to test various devices, including electronic components and ICs, to cull defective devices before they are incorporated in products. Broadly, there are three types of digital devices that are commonly tested using automated test systems, those having memory arrays or circuits, such as flash memory or random access memories (RAM), those having logic circuits, such as micro controllers, application specific ICs (ASICs) and programmable logic devices (PLDs), and those having both memory circuits and logic circuits. Generally, it is desirable to test the devices at several points during the manufacturing process including while they are still part of a wafer or substrate, and after packaging the devices but before they are mounted or assembled on modules, cards or boards. This repetitive testing imposes demands on automated test systems to perform tests at high speed and with a high degree of accuracy. Moreover, the trend in the electronics industry has been to further increase the miniaturization of electronic devices and circuits, thereby allowing for an increase in the complexity of the devices. As the devices become more complex, the complexity of the test systems and their cost increase correspondingly.
Test systems have traditionally been packaged in fixed sized chassises with a defined maximum pin count for each chassis size. To expand to pin counts greater than the capacity of a given chassis, the traditional approach has been to use a new and bigger chassis incorporating bigger power supplies, more PC board slots, and a larger Device Under Test (DUT) interface apparatus. To realize pin counts smaller than the maximum available in a given (typically large) chassis, the traditional approach has been to depopulate the chassis by removing PC boards. The pin count of the tester is reduced in this way, but there is still a tremendous expense carried in the product in unused backplanes, power supplies, cabling, and mechanical structure not required for the small number of PC boards in a small pin count configuration.
The exact same arguments hold for the electronic section of the tester. Designing, debugging, and manufacturing different electronic hardware for different sized test systems is very expensive. The electronics in a tester is typically two to five times more expensive than the mechanical portion of a tester and the development costs scale accordingly. Thus, minimizing the number of circuit board types to design, manufacture, and support across a wide range of tester sizes has a huge impact on the tester manufacturer's expenses and inventory costs.
Another problem with conventional test systems having a fixed sized chassis arises from their size and weight. Because ICs are manufactured, packaged and tested in controlled fabrication facilities known as fabs, an important consideration in selecting equipment is the amount of floor space occupied by the equipment. This is often referred to as the equipment footprint. Thus, it is generally desirable that equipment used in the clean room, such as the test system, present as small a footprint as possible. It is also often desirable that equipment be capable of being quickly and easily relocated within the facility from a standby location to a testing area, or between multiple testing areas within the fab or even between multiple fabs, thereby saving on both floor space and investment in testing systems.
Yet another problem with the conventional approach of maintaining different test systems for testing of DUTs having different pin counts is the expense associated with training operators and maintenance technicians on each different test system or differently configured test system. Indeed, because the need for trained operators and maintenance technicians continues for the life of the test system, this expense can be more significant than that of maintaining spare parts for multiple test systems.
Accordingly, there is a need for a test system and method of operating the same that can be quickly and easily scaled to enable testing of a DUT having a number of pins greater than can be accommodated on any single tester, or to simultaneously test a large number of smaller DUTs in parallel on different testers. There is a further need for a test system that conserves floor space in a manufacturing facility by reducing or minimizing system footprint for test systems having larger capacity. There is still a further need for a test system that increases manufacturing efficiency by reducing the volume of spare parts and assembly documentation maintained per test system, and by reducing manufacturing and service training required per test system.
The system and method of the present invention provides these and other advantages over the prior art.

System for testing DUT and tester for use therewith


A skateboard tool includes a multi-armed body, where four of the arms extend generally in a cross and a fifth arm extends generally perpendicular to a connection between the four arms and is elongated to serve as handle, two of said four arms and the fifth arm include ends formed with sockets therein, a third of the four arms has an end which includes a threading tool and a fourth arm of the four arms has an end which includes a bearing tool.

1. Field of the Invention
The present invention relates to improvements to skateboard tools, particularly to a multifunctional skateboard tool for use in repairing and adjusting skateboards.
2. Description of the Related Art
Skateboarding is a significant sporting activity today and there are specially designed courses for such sport. Due to the extreme wear and use a skateboard undergoes during skateboarding, skateboards frequently require maintenance. Skateboards are used to perform a variety of jumps in addition to rolling and the bearings and support mounts undergo significant stress.
Consequently, tools are used to tighten, adjust or repair the mechanical parts of the board. Such tools include have commonly included socket wrenches of different sizes, a Phillips head screwdriver and/or an Allen key for securing the fasteners which retain the skate on the board or adjusting the axles, etc. as is shown and taught in U.S. Pat. No. 6,279,434, for example.
U.S. Pat. No. 6,279,434 is the current state of the art providing T shaped body having three sockets, one on each end of the T-shaped body. The tool also includes an axially inward open center surface and groove in an upper part of one arm of the T-body to receive an L shaped screw driver with one end having a Phillips head and another end having an Allen wrench head which. One end of the screw driver is intended to be removably disposed within open center surface and the other end seated in the groove.
There is a need to improve tools which are used in the skateboard industry. The present invention improves upon such tools.


A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.

The present invention relates to fault tolerant computers and more specifically to a method and apparatus for operating in an error free manner when a microprocessor error is induced.
Three basic factors contributing to the functioning of a computer, and more specifically to a microprocessor or microprocessors included in a computer are power, performance and environment-induced radiation effects. New models or generations of computers seek to achieve higher performance at lower power levels. Additionally, in applications in which microprocessors are exposed to ionizing radiation, it is necessary to provide a mechanism for maintaining reliable operation when it is a virtual certainty that the ionizing radiation will cause processor errors. An example of applications in which sufficient levels of radiation will be encountered to cause errors in spaceborne computers. In applications in which particle or ionizing radiation is not present, errors can be caused by other fault mechanisms such as electrically induced noise pulses.
The most significant error events are Single Event Upset (SEU) and Single Event Functional Interrupt (SEFI). SEU is defined by NASA as "radiation-induced errors in microelectronic circuits caused when charged particles (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs. In other words SEU is a change of state or transient induced by an energetic particle such as a cosmic ray or proton in a device. SEUs are "soft errors" in that a reset or rewriting of the device causes normal device behavior thereafter. However, the error must be accounted for when it is included in data to be acted upon. An SEFI is a condition in which an SEU in the device's control circuitry places the device into a test mode, halt, or undefined state. The SEFI halts normal operations, and is believed to require a power reset to recover. SEU error rates in a nominal application for commercial microprocessors can range from 0.2 to 9 MeV/mg/cm2. This range of rates is reflected in processor performance, depending on the processor and its environment, from a quite acceptable single upset per year to an unacceptable multiple upsets per hour.
Improved SEU performance when designing microprocessor systems commonly results in increased power consumption. However, this technique does not solve the problem of SEUs and SEFIs due to radiation or electrically induced noise pulses. One prior art approach comprises utilizing radiation hardened microprocessors which will not be susceptible to the errors induced by radiation. However, radiation hardened microprocessors are not available in state of the art versions. They have over the past ten years lagged non-hardened processors by two to three generations. For example, currently available radiation hardened microprocessors include a 0.35 micron SOI (Silicon on Insulator) microprocessor and a 0.25 micron bulk CMOS on EPI processor (Complimentary Metal Oxide Semiconductor on Epitaxial Layer). However, state of the art microprocessors utilize 0.13 and 0.10 geometries. Radiation hardened microprocessors also lag the state of the art in terms of MIPS (Million Instructions Per Second) capability.
Another known technique is TMR, triple modular redundancy, applied at the system level, also known as spatial redundancy. Three individual or discrete processors run instructions in parallel and synchronously. The outputs of the processors are sent to a comparator that utilizes voting logic. When an SEU occurs in one processor, the other two processors will still produce matching outputs. The comparator will pass the majority output. SEFI errors are treated as SEUs. However, the processor experiencing the SEFI will remain offline until reset or otherwise corrected. TMR triples the processor power requirements compared to a single processor. Synchronizing the processors is difficult, and operation must be slowed with respect to the speed achievable by a single processor.
Time redundancy has been employed at the system level to provide the advantage of redundancy as described above while permitting the use of a single processor. In this technique, the processor executes the same instruction three times, or two times, comparing results, and runs a third time when the results do not agree. The result, or a checksum indicative of the result, is stored and the three stored outputs are compared. Three matching results indicate the absence of an SEU. If there is an SEU, a voting circuit selects the correct result. When the SEU corrupts data, the time redundancy technique will operate correctly. However, if the SEU causes an instruction to be corrupted, the technique will not operate correctly. A bit instructing a wrong operation will cause the wrong operation to be performed all three times. SEUs are not detected and SEFIs are not corrected. An improved form of time redundancy was developed by the Stanford Advanced Research and Global Observations Satellite Project (ARGOS). This technique is described in Oh, N., P. P. Shirvani and E. J. McCluskey, "Error Detection by Duplicated Instructions In Super-scalar Processors," IEEE Transactions on Reliability, Vo. 49, No. 7, September 2001, pp. 273-284. Many errors were corrected, but still others were not.
Another prior art alternative is to build a processor using commercial, non-radiation hardened integrated circuit process and apply known RHBD (radiation hardness by design) techniques to improve radiation hardness. Once again, as in the case of radiation hardened processors, die area is increased and operating speed are compromised. Also, while commercial switching logic utilizes simple flip-flops, RHBD logic requires latches built out of many flip-flops and further logic such as inverters. Performance comparable to commercial processors which are not radiation hardened is not provided.
Examples of an improved radiation hardened system and a time redundant system are respectively disclosed in my copending patent application Ser. No. 10/435,626 filed May 6, 2003 entitled Fault Tolerant Computer and Ser. No. 10/656,720 (with a coinventor) filed Sep. 8, 2003 entitled Functional Interrupt Mitigation for Fault Tolerant Computer, the disclosures of which are incorporated by reference herein. It is desirable to provide a system in which a minimal amount of radiation hardening need be done. It is desirable to provide a system in which a time redundant system is also made space redundant, but in an efficient, reliable manner. For example, it is desired to avoid the problem of synchronizing a plurality of processors.
There is little patent literature on SEFIs. Many testing efforts with microprocessors do not report SEFIs, or "hangs." It is probable that all microprocessors will exhibit SEFIs whether they have been previously observed or not. This will include both commercial and radiation hardened devices. SEUs may take place in any transistor within a complex microprocessor. When the upset occurs in a memory location, whether a register or memory site, this can be measured and corrected. However, when the upset occurs in more subtle ways, the processor may be placed in a state from which it is not recoverable. An example is the case of an induced error in combinatorial logic or in state-machine transistors. It may be initially impossible to observe an error condition within the processor. However, the error may propagate within combinatorial logic. Other unrecoverable faults could include illegal branching, upset induced exceptions, upsets in the program counter or other unobservable faults. Work by such researchers as Dr. James W. Howard of Jackson and Tull Chartered Engineers of Washington, D.C. has demonstrated that SEFIs will occur in Pentium®, PowerPC and other processors. It is highly probable that all microprocessors will exhibit SEFIs whether they have been previously observed or not. It is therefor highly desirable to provide a way of detecting SEFIs so they may be responded to and also providing a way of responding to them.


Sensor assemblies including transmitter and receiver antennas to respectively transmit or receive electromagnetic energy. The sensor assemblies are disposed in downhole tools adapted for subsurface disposal. The receiver is disposed at a distance less than six inches (15 cm) from the transmitter on the sensor body. The sensor transmitter or receiver includes an antenna with its axis tilted with respect to the axis of the downhole tool. A sensor includes a tri-axial system of antennas. Another sensor includes a cross-dipole antenna system.

1. Field of the Invention
The invention relates generally to the field of subsurface exploration. More particularly, the invention relates to techniques in which instruments equipped with antenna systems having cross-magnetic dipoles are used for improved subsurface electromagnetic measurements and imaging.
2. Background Art
Electromagnetic (EM) induction and propagation logging techniques are well known in the field of hydrocarbon exploration and production. A typical EM logging tool comprises a transmitter antenna and one or more (typically a pair) receiver antennas disposed at a distance from the transmitter antenna along the axis of the tool. The tools are disposed within a subsurface formation that has been penetrated by a borehole to measure the electrical conductivity (or its inverse, resistivity) of the formation. EM energy emitted from the transmitter interacts with the borehole fluid ("mud") and surrounding formation to produce signals that are then detected and measured by the receiver(s). By processing the detected signal data using inversion algorithms and models well known in the art, a profile of the borehole or formation properties is obtained.
Geologists and petrophysicists historically have found it necessary to visually analyze full well cores extracted from zones of interest to assess complex or thinly laminated (also referred to as bedded) reservoirs and aid in the discovery of hydrocarbons. High resolution "microresistivity" measurement techniques have been developed over the years to contribute to the identification of hydrocarbons in low resistivity pay zones. High resolution measurements have helped improve the estimation of reserves in such reservoirs.
Microresistivity tools have been developed for wireline and while-drilling applications. Examples of wireline microresistivity tools include the Formation MicroScanner™ tool and the Fullbore Formation Microimager tool (FMI™) produced by Schlumberger. Logging-while-drilling (LWD) EM tools capable of providing subsurface images are described in U.S. Pat. No. 5,235,285. The '285 patent describes an LWD tool that can measure the resistivity at the bit. Examples of tools based on this and related principles include the RAB™ (resistivity at the bit) and GVR™ (geovision resistivity) tools produced by Schlumberger. These tools are capable of providing borehole resistivity images of the reservoir rock being drilled.
Early microresistivity techniques were implemented for use with conductive muds, usually a mixture of salt water and weighting solids to control mud density. These EM tools have been designed to investigate the formation beyond the invaded zone present when the well is drilled with a water-base mud. More and more new wells are now being drilled with oil-based mud (OBM) containing chemical additives that build and leave a thin impermeable mudcake and usually prevent significant invasion into the permeable zones around the borehole. Synthetic-based muds have also been introduced in the industry. Early microresistivty tools were based on low frequency electrode devices that are not very suitable for wells drilled with OBM.
Conventional logging tools have been developed to provide subsurface images in wells drilled with OBM. U.S. Pat. Nos. 3,973,181, 6,191,588, and 6,600,321 describe tools capable of imaging operations in OBM. While progress has been made in the development of wireline OBM tools, the development of EM tools suitable for while-drilling operations in OBM has been relatively slower. A need remains for improved EM imaging and logging techniques, particularly in while-drilling applications using OBMs.

Subsurface electromagnetic measurements using cross-magnetic dipoles


An introducer assembly (100) including at its distal end a dilator tip (20) and an inner catheter for supporting an implantable medical device (1) for deployment, is provided with a plurality of strut elements (102, 202) extending from the dilator tip (20) to the proximal end of the medical device (1). The strut elements (102, 202) act to apply both a pulling and a pushing force against the proximal end of the medical device (1), having the effect of assisting in the correct positioning of the proximal end of the medical device in a patient's lumen, particularly where this is curved such as with the aortic arch. The strut elements (102, 202) form part of the introducer assembly and are removed from the patient following the deployment procedure. The device avoids the need for bare stents at the end of a stent graft.

Implantable medical devices for the repair of vascular defects, including for example vascular aneurysms, are well known in the art. A common device for treatment of such a medical condition is a stent-graft.
Medical devices of this type are typically deployed endoluminally through a vein or artery adjacent a surface of a patient, aortic devices, for example, being commonly fed through the femoral artery. A generally accepted method of deployment involves the location of a guide wire along the path to be followed by the introducer assembly, up to the site in the vasculature to be treated. Once the guide wire is in place, a series of catheters is advanced along the guide wire, finally with the introduction of a catheter assembly which carries the stent or stent-graft to be fitted. The catheters have sufficient trackability to follow the guide wire along the curves and turns of the patient's vasculature and some can also curve sufficiently so as to be able to fit a stent-graft, for example, into a highly curved vessel such as the aortic arch.
Even though such a procedure is possible into the aortic arch, it is mired in difficulties as a result of the tight curvature of the aorta in this location. One such difficulty arises in connection with the proximal end of the stent-graft, which is liable to be incorrectly fitted such that it incompletely seals around the inner wall of the aorta as a result of the curvature imparted to the stent-graft. This can lead to leakage of blood around the outside of the stent-graft and thus a less than effective treatment. Furthermore, as a result of the non-optimal placement of the stent-graft using known procedures, it is necessary to have a reasonable length of healthy vascular wall in order to provide a seal around the proximal end of the stent-graft. This limits the application of such stent-grafts, in particular for the treatment of aneurysms close to a branch vessel and to conditions where there is at least a certain length of healthy vessel wall tissue, thus making the procedure not available to treat a reasonable proportion of medical cases.
In addition, in some instances at least, a part of the proximal end of the stent-graft can remain loosely located in the vessel, leading to premature fatigue failure as well as thrombus effects.
Attempts have been made to resolve these difficulties. For instance, in the applicant's U.S. Pat. No. 6,974,471, mechanisms are described for imparting a curvature to the stent-graft at the moment of its deployment.
Another example, disclosed in US-2006/155366, applies a curve to the introducer assembly in order to impart a curvature to the stent graft in order to place the latter in a curved lumen.
The deployment of stent-grafts and other devices, particularly in the aortic arch, in lumens having short necks of healthy vascular wall and other difficult pathologies also requires very precise placement of the device to ensure a good coupling to healthy tissue and in particular a coupling which has longevity and which provides a fluid-tight seal with the vessel wall. Prior art systems do allow for a certain amount of coarse re-positioning of the device. However, if the device is not fitted precisely in the correct location, the procedure may need to be repeated, for example by withdrawing the device back into its delivery introducer (where this is possible) and starting the deployment operation afresh. Repeating the procedure increases operating time, trauma to the patient and still does not guarantee a successful outcome. In some instances, it is necessary to abort the procedure.
Prior art introducer systems include wire tie elements able to pull the proximal end of the stent graft in the direction of the introducer. This does not, however, always provide a mechanism for ensuring correct positioning of the proximal end of the stent graft in a lumen, particularly in cases where the lumen is particularly curved.
Problems can also arise with the correct placement and orientation of a stent graft in other lumens or regions of the aorta of a patient and in order to ensure correct placement stent grafts are often provided with a stent ring which extends beyond the end of the graft material, often being called a bare stent. Such a bare stent typically plays no part in closing off blood supply to a lumen or part thereof, as does a graft covered stent, and normally only serves to support the end of the graft material correctly in the lumen.
While such bare stents can achieve the intended function efficiently, they can be the cause of other problems. For example, they require a length of suitable lumen against which to press. They can also induce stenosis or restenosis in the location in which they are fitted.

Apparatus for curving an implantable medical device in a lumen