Methods of treating pain by delivery of anti-inflammatory cytokines, proinflammatory cytokine antagonists, and agents that act to reduce or prevent proinflammatory cytokine actions, to the nervous system are described. These agents can be delivered using gene therapy techniques. Alternatively, the agents can be delivered in protein compositions.

Gene therapy using genetically engineered cells and viruses has undergone impressive development over the past 40 years. Gene therapy techniques have been applied to diverse medical problems and have been used in over 350 clinical trials (Wu et al., Meth. Strat. Anesthes. (2001) 94: 1119-1132). However, gene therapy has only recently been used in attempts to control pathological pain. Several approaches have been explored. For example, spinal implantation of genetically engineered cells has been used to increase inhibitory transmitters, including GABA (Eaton, M., J. Peripheral Nerv. Sys. (2000) 5:59-74), galanin (Eaton et al., J. Peripheral Nerv. Sys. (1999) 4:245-257), and beta-endorphin (Ishii et al., Exp. Neurol. (2000) 166:90-98). Herpes viruses have been utilized for their ability to be retrogradely transported from peripheral nerve terminals to dorsal root ganglion somas. In this way, elevations in preproenkephalin (Antunes Bras et al., J. Neurochem. (1998) 70:1299-1303; Wilson et al., Proc. Natl. Acad. Sci. USA (1999) 96:3211-3216) and decreases in CGRP via induced production of CGRP antisense (Lu et al., Soc. Neurosci. Abs. (1998) 24:1625) have been produced in sensory neurons. Lastly, adenoviruses have been injected into CSF to achieve virally driven beta-endorphin release from meningeal cells (Finegold et al., Hum. Gene Ther. (1999) 10:1251-1257. These gene therapy approaches focus on decreasing the excitability of spinal cord pain transmission neurons to incoming pain signals.
Activated spinal cord microglia and astrocytes appear to contribute to the creation and maintenance of pathological pain. In particular, activated glia appear to do so, at least in part, via their release of the proinflammatory cytokines interleukin-1 (IL1), tumor necrosis factor (TNF), and IL6 (for review, see Watkins et al., Trends in Neurosci. (2001) 24:450-455). These proinflammatory cytokines amplify pain by enhancing the release of "pain" neurotransmitters from incoming sensory nerve terminals and by enhancing the excitability of spinal cord dorsal horn pain transmission neurons (Reeve et al., Eur. J. Pain (2000) 4:247-257; Watkins et al., Trends in Neurosci. (2001) 24:450-455).
Astrocytes and microglia express receptors for IL-10 (Mizuno et al., Biochem. Biophys. Res. Commun. (1994) 205:1907-1915) while spinal cord neurons do not (Ledeboer et al., J. Neuroimmunol. (2003) 136:94-103). In vitro studies have shown that IL-10 can selectively suppress proinflammatory cytokine production and signaling in these glial cells (Moore et al., Ann. Rev. Immunol. (2001) 19:683-765). In fact, IL-10 is an especially powerful member of the anti-inflammatory cytokine family in that it can suppress all proinflammatory cytokines implicated in pathological pain (IL1, TNF and IL6). IL-10 exerts this effect by inhibiting p38 MAP kinase activation (Strie et al., Crit. Rev. Immunol. (2001) 21:427-449); inhibiting NFkappaB activation, translocation and DNA binding (Strie et al., Crit. Rev. Immunol. (2001) 21:427-449); inhibiting proinflammatory cytokine transcription (Donnelly et al., J. Interferon Cytokine Res. (1999) 19:563-573; inhibiting proinflammatory cytokine mRNA stability and translation (Hamilton et al., Pathobiology (1999) 67:241-244; Kontoyiannis et al., EMBO J. (2001) 20:3760-3770); and inhibiting proinflammatory cytokine release (Moore et al., Ann. Rev. Immunol. (2001) 19:683-765). In addition, IL-10 stabilizes mRNAs of Suppressors of Cytokine Signaling, thereby increasing the production of a family of proteins that further inhibit proinflammatory cytokine production (Strie et al., Crit. Rev. Immunol. (2001) 21:427-449). IL-10 also interrupts proinflammatory cytokine signaling by downregulating proinflammatory cytokine receptor expression (Sawada et al., J. Neurochem. (1999) 72:1466-1471. Lastly, it upregulates endogenous antagonists of proinflammatory cytokines, including IL1 receptor antagonist and TNF decoy receptors (Foey et al., J. Immunol. (1998) 160:920-928; Huber et al., Shock (2000) 13:425-434).
The known effects of IL-10 are restricted to suppression of proinflammatory functions of activated immune and glial cells, leaving non-inflammatory aspects of cellular functions unaffected (Moore et al., Ann. Rev. Immunol. (2001) 19:683-765). While some neurons express IL-10 receptors, the only known action of IL-10 on neurons is inhibition of cell death (apoptosis) (Bachis et al., J. Neurosci. (2001) 21:3104-3112). Laughlin et al. (Laughlin et al., Pain (2000) 84:159-167) reported that intrathecal IL-10 blocks the onset of intrathecal dynorphin-induced, IL1-mediated mechanical allodynia. These investigators then tested the effect of IL-10 on pathological pain induced by excitotoxic spinal cord injury, a manipulation that activates astrocytes and microglia at the site of injury (Brewer et al., Exp. Neurol. (1999) 159:484-493). IL-10 decreased pathological pain behaviors when given 30 minutes following injury (Plunkett et al., Exper. Neurol. (2001) 168:144-154; Yu et al., J. Pain (2003) 4:129-140). This is in keeping with the fact that systemic IL-10 can reduce spinal cord proinflammatory cytokine production in response to excitotoxic injury, a manipulation that allows systemic IL-10 to reach the injured spinal cord due to disruption of the blood-brain barrier (Crisi et al., Eur. J. Immunol. (1995) 2:3033-3040; Bethea et al., Neurotrauma (1999) 16:851-863).
However, delivery of IL-10 systemically to treat CNS disorders is problematic. IL-10 does not cross the intact blood brain barrier in appreciable amounts (Banks, W. A., J. Neurovirol. (1999) 5:538-555), has a short half life such that sustainable delivery for prolonged periods would be difficult (Radwanski et al., Pharm. Res. (1998) 15: 1895-1901), has not been successfully delivered orally, so presents problems for systemic administration, and would disrupt the normal functions of the body's immune system and would be expected to be detrimental to the health of the patient (Xing et al., Gene Ther. (1997) 4:140-149; Fedorak et al., Gastroenterol. (2000) 119:1473-1482; Tilg et al., J. Immunol. (2002) 169:2204-2209). Moreover, previous experimenters found that delivery of IL-10 24 hours after dynorphin-induced allodynia did not reduce the allodynia (Laughlin et al., Pain (2000) 84:159-167).
Previous reports have documented that IL-10 gene therapy reduced pneumonia-induced lung injury (Morrison et al., Infect. Immun. (2000) 68:4752-4758), decreased the severity of rheumatoid arthritis (Ghivizzani et al., Clin. Orthop. (2000) 379 Suppl.:S288-299), decreased inflammatory lung fibrosis (Boehler et al., Hum. Gene Ther. (1998) 9:541-551), inhibited cardiac allograft rejection (Brauner et al., J. Thoracic Cardiovasc. Surg. (1997) 114:923-933), suppressed endotoxemia (Xing et al., Gene Ther. (1997) 4:140-149), prevented and treated colitis (Lindsay et al., J. Immunol. (2001) 166:7625-7633), and reduced contact hypersensitivity (Meng et al., J. Clin. Invest. (1998) 101:1462-1467).
However, the ability of IL-10 gene therapy to reverse ongoing pain has not been documented prior to the present invention.

Methods for treating neuropathic pain by administering IL-10 polypeptides


Techniques are disclosed for classifying a sound environment for hearing assistance devices using redundant estimates of an acoustical environment from two hearing assistance devices and accessory devices. In one example, a method for operating a hearing assistance device includes sensing an environmental sound, determining a first classification of the environmental sound, receiving at least one second classification of the environmental sound, comparing the determined first classification and the at least one received second classification, and selecting an operational classification for the hearing assistance device based upon the comparison.

Hearing aid users are typically exposed to a variety of sound environments, such as speech, music, or noisy environment. Various techniques are known and used to classify a user's sound environment, e.g., the Baynesian classifier, the Hidden Markov Model (HMM), and Gaussian Mixture Model (GMM). Based on the classified sound environment, the hearing assistance device can apply parameter settings appropriate for the sound environment to improve a user's listening experience.
Each of the known sound environment classification techniques, however, has less than 100% accuracy. As a result, the user's sound environment can be misclassified. This misclassification can result in parameter settings for the hearing assistance device that may not be optimal for the user's sound environment.
Accordingly, there is a need in the art for improved sound environment classification for hearing assistance devices.

This patent is subject to a terminal disclaimer.

Sound environment classification by coordinated sensing using hearing assistance devices


The specification and drawing figures describe and show a wrench and reamer tool that includes two handle plates. On one handle plate a serrated ledge is formed. Beneath the ledge is an arcuate shoulder that forms a seam for positioning the wrench adjacent an opening in a pipe. On the second handle plate a tapered nose is formed with an inclined face to enable insertion into a pipe. A plurality of opposing edges is formed on the handle plates for deburring a pipe.

Electricians, plumbers, and similar artisans often work in cramped environments where, once positioned, it would be useful to have a tool that can be used to perform a variety of operations that customarily performed using several different tools. Valuable time is lost switching from one tool to another tool or searching for a misplaced tool. In addition, toolboxes and tool belts are awkward appendages in cramped environments, and their weight can strain anatomical features of an artisan to the point of disabling the artisan.
An electrician, for example, often is required to grasp portions of conduit or pipe to cut conduit or pipe with a cutting device such as a saw. After the conduit or pipe is cut, an electrician generally is required to remove burrs from the pipe, particularly burrs adjacent the opening in the pipe that is formed by having cut the pipe. The edges of a pipe near the cut opening in the pipe must be smoothed by reaming to prevent damage to one or more wires inserted through the pipe.
Wrenches currently available in the market are, however, not adapted to ream burrs formed adjacent an opening in the pipe. Accordingly, a need exists in the industry for a new and useful multipurpose hand tool that serves as both a wrench and a reamer.


A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device such as a data processing device (microprocessor) having a high-speed CMOS (complementary metal-oxide-semiconductor) TLB (translation look-aside buffer).
The virtual storage method is a known method of memory management for use with microprocessors.
To use the virtual storage method requires establishing correspondence between two kinds of address space: virtual (i.e., logical) address (called VA) space, and real (i.e., physical) address space.
The most common technique by which to have virtual address space correspond with real address space is what is known as the paging system or page segmenting system. The system involves allocating address space in units of pages.
The paging or page segmenting system involves dividing virtual and real address space into contiguous blocks called pages. The virtual (logical) page numbers (VPN) of virtual address space are arranged to match the real (physical) page numbers (PPN) of real address spaces That is, a virtual address is assigned to the real addresses for each of the pages.
Suppose that a virtual address space accessed by a 32-bit virtual address (VA 31 : 0!) is divided into 4-kilobyte (KB) pages. In such a case, the high-order 20 bits of the virtual address (VA 31 : 12!) are used to designate the page number of a page in the virtual address space. The low-order 12 bits (VA 11 : 0!) of the virtual address are used to specify a displacement (or offset) address within the page.
In the description that follows, the notation m : n! is assumed to indicate the bit positions from bit m to bit n.
A page number in the virtual address space is translated into the corresponding page number in the real address space (the process is called address translation or memory mapping). A page number in the real address space is combined with a replacement address for access to real memory.
It should be noted that the replacement address in each page is not translated.
Translation of a page number in the virtual address space to the corresponding page number in the real address space is carried out by both hardware and software: by a memory management unit (called the MMU), and by the operating system.
High-performance microprocessors generally incorporate a memory with functions for address translation called a translation look-aside buffer (TLB) in order to implement a high-speed virtual storage setup.
The TLB, included in the MMU, translates a given page number of the virtual address space into the corresponding page number of the real address space.
The translation table as a whole for designating correspondence between the page numbers in the virtual address space and those in the real address space (real memory) is held in a page table in main memory or in a secondary storage (memory) device.
A partial copy of the page table is retained in the TLB. The TLB works as a cache memory (address mapping cache memory) for the page table.
The address translation time of the TLB affects the speed of processing by the microprocessor in question. Thus attempts have been made to shorten the address translation time of the TLB.
Part of such attempts are presented illustratively as TLB circuits disclosed in the following two publications for reference:
(A) T. Takayanagi et al., "2.6 Gbyte/sec Bandwidth Cache/TLB Macro for High-Performance RISC Processor" Proceedings of Custom Integrated Circuits Conference, pp. 10.2.1-10.2.4, 1991
(B) G. Gerosa et al., "A 2.2W, 80 MHz Superscalar RISC Microprocessor," J. Solid-State Circuits, Vol. 29, No. 12, pp. 1440-1454, Dec. 1994
The TLB circuit discussed in the reference (A) above takes a total of 12 ns for address translation and cache memory access. The TLB has a match line discharge circuit implemented as a dynamic circuit so as to shorten the address translation time.
The TLB circuit described in the reference (B) attempts to shorten the address translation time by having its comparator arrangement operating as a dynamic circuit.
The virtual storage setup (paging or page segmenting system) operating in units of pages requires as many "address translation pairs" as the number of pages involved.
An address translation pair is a page number of virtual address space paired with the corresponding page number of real address space. These pairs are held in the page table to designate the correspondence between the two kinds of address space.
When the memory space of a fixed storage capacity is divided into pages, the smaller the size of each page (i.e., page size), the larger the number of pages available in the divided memory space.
Conversely, the larger the page size, the smaller the number of pages divided and made available. Larger page sizes mean a smaller number of address translation pairs, which translates into a less memory capacity required for the page table.
However, making the page size too large can increase unusable fields within the pages (due to internal fragmentation). For that reason, high-performance microprocessors recently marketed generally allow any of a plurality of page sizes to be selected for different purposes.
To handle a plurality of page sizes requires that the TLB also accommodate a plurality of page sizes.
In addition to the address translation time and the number of usable page sizes, the so-called hit rate is cited as an important performance indicator of the TLB (the hit rate is a rate at which necessary address translation pairs are found in the TLB).
The hit rate is related to what kind of associative method is in use and how large the size of the TLB is (i.e., the number of entries).
There are two kinds of associative methods CAM (content addressable memory) method, and set-associative method.
The CAM method permits a high hit rate with the use of a small-capacity memory. One disadvantage of this method is that it is difficult to design. Another disadvantage is the tendency of a setup implementing the CAM method to consume large amounts of power. That is, the CAM-based setup has its numerous memory cells incorporate a comparator each, the large number of comparators being liable to dissipate high quantities of power in operation.
On the other hand, although the set-associative method provides a high hit rate only in combination with a large-capacity memory, it nevertheless offers a number of advantages. One such advantage is a low level of power consumption where the degree of association (i.e., number of ways) is low. Another advantage is that a setup implementing the set-associative method is relatively easy to design. Moreover, since most cache memories operate on the set-associative methods the same kind of memory as cache memories may be adopted by the TLB. This reduces the design period of the TLB circuit.
The following publications illustratively disclose a page size variable TLB each:
(C) Tanaka et al., "5-ns Access Time CMOS Translation Look-aside Buffer," technical report of the Institute of Electronics, Information and Communication Engineers of Japan, ICD92-57, pp. 29-35, 1992
(D) Japanese Patent Laid-Open No. Hei 5-282877
The page size variable TLB circuits disclosed in the references (C) and (D) above use a CAM circuit to vary the range of comparison (associative range) between an input virtual address (i.e., its tag field) and the (tag) data held in memory. The associative range is varied in accordance with the memory cell data indicating page sizes. The scheme permits storage of address translation pairs of different page sizes for each of the entries accommodated.
Another page size variable TLB circuit is disclosed illustratively by the following publication:
(E) T. Takayanagi et al., "Embedded Memory Design for a Four Issue Superscalar RISC Processor," Proceedings of Custom Integrated Circuits Conference, pp. 26.1.1-126.1.6, June 1994
The page size variable TLB circuit disclosed in the reference (E) above constitutes a TLB setup that utilizes the set-associative method in varying, according to the page size in effect, those bit positions of a given virtual address which are handled by control signals as an index field in part (an address part for selecting a set-associative set in the virtual address) and as a tag field in another part (an address part of the virtual address for comparison with the data held in the TLB).

Translation lookaside buffer supporting multiple page sizes


Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Technical Field
This disclosure relates to memory devices, and more particularly in at least one embodiment to post-packaging repair of a memory device.
Description of Related Technology
Memory cells of memory devices such as dynamic random access memories (DRAMs), static RAMs (SRAMs), flash memories, or the like may experience defects leading to errors and/or failures. Memory cells can also fail to operate with sufficient speed, short enough latencies, or the like. In some cases, memory cells may be identified as defective (hereinafter "defective memory cells") after the memory device (e.g., a memory chip) has been packaged, such as in cases where the memory cells were not detective before the packaging process. Examples of packaging include, but are not limited to, encapsulation by epoxy, ceramic packages, metal/glass packages, and the like. After a memory device has been packaged, the memory device may be tested to identify defective memory cells. Addresses mapped (e.g., assigned) to defective memory cells may be remapped (e.g., reassigned) to functional or otherwise more desirable memory cells (e.g., memory cells that have not been identified as defective) so that the memory device may still be effective or meet a desired operational characteristic.
Non-volatile memory (e.g., fuses or antifuses) may be programmed to store data corresponding to one or more addresses mapped to defective memory cells. An antifuse has a high resistance in its initial state. An antifuse may permanently create an electrically conductive path when a relatively high voltage is applied across the antifuse. An antifuse may have a structure similar to that of a capacitor, i.e., two conductive electrical terminals are separated by a dielectric material. To create an electrically conductive path, a relatively high voltage is applied across the terminals, breaking down the interposed dielectric material and forming a conductive link between the antifuse terminals. Creating a conductive path through an antifuse is referred to as "blowing an antifuse."
Certain protocols exist for performing post package repair. Such existing protocols have various drawbacks. Accordingly, a need exists to improve post package repair.

Repair of memory devices using volatile and non-volatile memory


A frame synchronizer for use in a receiver that receives an encoded signal from a transmitter includes a conjugation unit, a delay unit and multiplier coupled together to process the encoded signal. The multiplier multiplies either the received encoded signal by a conjugated, delayed version of the received encoded signal or multiplies a conjugated version of the received encoded signal by a delayed version of the received encoded signal to produce a first product signal. A further multiplier multiplies the first product signal with a locally-stored signal to generate a second product signal. An accumulator accumulates the second product signal over a plurality of bit times to generate an accumulated signal having a magnitude representing a time synchronization offset between the receiver and the transmitter and phase representing a frequency synchronization offset between the receiver and the transmitter. A synchronization correction unit generates a time offset correction and a frequency offset correction from the accumulated signal and these corrections are used to correct offsets between the receiver and the transmitter.

The present invention relates generally to receivers and, more particularly, to a frame synchronizer for use in a digital receiver.
Communication systems employing digital transmitters and digital receivers are widely used. Such systems, which are commonly employed in mobile communication applications, such as mobile or car telephones, use digital modulation techniques such as binary phase shift keying (BPSK), differential binary phase shift keying (DPSK), quadrature phase shift keying (QPSK) or differential quadrature phase shift keying (DQPSK) and the like. Using these techniques, digital information is transmitted in bursts called frames, which are typically 20 milliseconds (ms) long. Frames have a number of sections or subsections that may range in size from 160 microseconds (xcexcs) to 640 xcexcs and that contain numerous digital symbols, which are transmitted approximately every 40 xcexcs. As is known, digital symbols may be encoded to each represent a number of digital bits. Furthermore, each frame may include a preamble (midamble, etc.) bit sequence that is, for example, 14 bits or 560 xcexcs in length and that is known by each receiver that is to receive the transmitted frame. Each frame also includes data sections having various bits or symbols that represent digitized audio. In some applications, the preamble may be used to address the frame to a particular receiver or receivers while the data sections include the encoded audio (or other) signal for that receiver. As will be appreciated by those familiar with the communication arts, not all of the information in every frame will be received error free because the fidelity of any particular communication system, while it may be high, is not perfect.
Mobile receivers, such as cellular telephones using, for example, time division multiple access (TDMA) standards like the IS-136 standard, are turned on and off on a regular basis and, thus, need to synchronize in both time and frequency to incoming signals to properly decode those signals. In some cases, mobile receivers decode the received signal to produce a bitstream and then perform an auto-correlation procedure on the decoded bitstream to recognize the location of the preamble, which may be designed to have a particularly recognizable auto-correlation function. In other cases, the receiver may perform a cross-correlation procedure between the incoming bitstream and a locally-stored and known preamble to detect the location of the preamble. Generally speaking, the step of decoding the received symbols is prone to error because of both timing and frequency offsets between the receiver and the transmitter. For example, a slight frequency offset between an RF unit of the receiver and an RF unit of the transmitter that transmitted the signal will cause decoding errors. Similarly, sample time offsets between the receiver and the transmitter may lead to the incorrect decoding of symbols, thereby producing erroneous bits in the bitstream.
Bit error rate (BER) is a well-known metric that is used to specify or quantify the fidelity of a digital communication system. BER is a comparison between bits sent over a channel by a digital transmitter and bits received from the channel by a digital receiver. If the received bits are identical to the sent bits, the BER is zero, thus indicating that the communications system including the communication channel, the digital transmitter and the digital receiver has perfect fidelity. Conversely, if the bits received are substantially different from the bits that were sent, the communication system has low fidelity. For example, if there is one bit error in 100 bits, the BER of a particular communication system is 0.01.
Digital communication systems are susceptible to various noise sources that decrease the fidelity of a communication system and, therefore, increase the BER of the communication system. Thermal noise (also called KT noise) is noise resulting from the temperature of various critical components in the digital communication system. Co-channel noise is noise caused by interference on the communication channel over which a digital transmitter is broadcasting. Of particular interest in mobile communication systems is multipath noise.
Multipath noise is noise caused by reception of delayed versions of a previously-received signal because energy from a digital transmitter may take more than one path to a digital receiver. For example, energy from a digital transmitter that takes the most direct path to the receiver arrives at the receiver first, while energy taking another path, such as one with one or more reflections from obstructions, the earth or the atmosphere, arrives at the digital receiver some relatively short time later. Energy that does not take the most direct path from the digital transmitter to the digital receiver is called multipath energy, or simply xe2x80x9cmultipath.xe2x80x9d In a mobile communications system, such as a cellular system, where either a digital receiver or a digital transmitter is moving, the communication path between a transmitter and receiver is constantly changing and, therefore, so is the multipath. For example, as a person using a cellular phone travels in his or her car, multipath may range from nonexistent at one geographic location, to extremely high at another geographic location. Because the multipath is always changing, it is difficult for a digital receiver in a mobile system to synchronize to a digital transmitter in both time and frequency. Typically in a digital system, time synchronization can only be achieved after frequency synchronization is achieved. Accordingly, prior approaches to time and frequency synchronization are relatively time consuming because the synchronization steps must be performed sequentially. A digital receiver such as may be found in a cellular telephone and the like, therefore, may have a significant time delay, due to synchronization operations between when a user attempts to use the receiver and when the receiver is synchronized and ready for use.
A synchronizer for use in a receiver that receives an encoded signal from a transmitter includes a conjugation unit, a delay unit and multiplier coupled together to process the encoded signal. The conjugation unit and the delay unit create both a conjugated version of the received encoded signal and a delayed version of the received encoded signal or create a single conjugated, delayed (e.g., conjugated and then delayed or delayed and then conjugated) version of the received encoded signal. The multiplier then multiplies either the received encoded signal and the conjugated delayed version of the received encoded signal or multiplies the conjugated version of the received encoded signal by the delayed version of the received encoded signal to produce a first product signal. A further multiplier multiplies the first product signal with a locally-stored signal to generate a second product signal. An accumulator accumulates the second product signal over a plurality of bit times to generate an accumulated signal that includes a time offset metric representative of a time synchronization offset between the receiver and the transmitter and that includes a frequency offset metric representative of a frequency synchronization offset between the receiver and the transmitter. A synchronization correction unit generates one or both of a time offset correction and a frequency offset correction from the time offset metric and the frequency offset metric. The receiver may use these corrections to correct offsets in the receiver.
The synchronizer may also or instead include a symbol extractor communicatively coupled to the first multiplier adapted to process the first product signal to generate a first digital bitstream and an exclusive OR (XOR) unit communicatively coupled to the symbol extractor that exclusive ORs the first digital bitstream with a locally-stored digital bitstream to produce an output signal. A second accumulator coupled to the XOR unit counts a number of differences between the first digital bitstream and the locally-stored digital bitstream based on the output signal to produce a second accumulated signal including a further time offset metric representative of the time synchronization offset between the receiver and the transmitter.
According to another aspect of the invention, a method of synchronizing a receiver to a transmitter that transmits an encoded signal spanning multiple bit times includes the steps of multiplying the encoded signal associated with a first bit time by a conjugate of the encoded signal associated with a second bit time to create a first product signal and multiplying the first product signal by a locally-stored signal to create a second product signal. The method also accumulates the second product signal over a plurality of bit times to generate an accumulated signal having a magnitude that corresponds to a time synchronization offset between the receiver and the transmitter and a phase that corresponds to a frequency synchronization offset between the receiver and the transmitter. If desired, the method may adjust the receiver based on at least one of the magnitude and the phase of the accumulated signal.


A non-pneumatic wheel assembly is provided. More particularly, a non-pneumatic wheel assembly is provided having a removable hub i.e., a hub that may be separated from the remainder of the wheel assembly. The hub may be reused and other portions of the non-pneumatic wheel assembly replaced as needed. In addition, the hub may be constructed from a different material than used for other portions of the non-pneumatic wheel.

Non-pneumatic tires and wheels have been disclosed. By way of example, U.S. Pat. No. 7,201,194, which is incorporated herein by reference, describes a non-pneumatic tire. In an exemplary embodiment, this non-pneumatic tire includes an outer annular shear band and a plurality of web spokes that extend transversely across and radially inward from the annular band and are connected to a hub. In certain exemplary embodiments, the annular shear band may further comprise a shear layer, at least a first membrane adhered to the radially inward extent of the shear layer and at least a second membrane adhered to the radially outward extent of the shear layer. Under load, the annular band deforms in the contact area with the ground surface through a mechanism that includes shear deformation of the annular band. In addition to the ability to operate without a required inflation pressure, the invention of U.S. Pat. No. 7,201,194 provides advantages that include a more uniform ground contact pressure throughout the length of the contact area, which in turn provides performance characteristics similar to a pneumatic tire without certain drawbacks of prior non-pneumatic tires.
For non-pneumatic constructions such as e.g., the invention described in U.S. Pat. No. 7,201,194, the web spokes transmit tension forces between the hub and outer annular band. The outer annular band supports a tread portion. By way of example, the web spokes and tread portion can be constructed from rubber and/or polymer materials that, in certain applications, may wear or be damaged during the lifetime of the wheel. For constructions where the web spokes or tread portion are permanently attached to the hub or integrated permanently into a structure that includes the hub, replacement of the web spokes and/or tread portion can require discarding the hub as well when the hub would otherwise by reusable. In addition, for certain applications it may be desirable to manufacture the hub from a different material than used in the construction of the web spokes including e.g., a metal construction for the hub and a polymeric construction for the web spokes. In such case, integral attachment of the hub and the web spokes may be not be practical or would be undesirable.
Accordingly, non-pneumatic wheel having a removable hub portion would be useful. A non-pneumatic wheel assembly having a removable hub portion that may be reused and/or constructed from a different material than the web spokes or other portions of the wheel would be particularly useful. These and other advantages of the present invention will be apparent from the description that follows.

Non-pneumatic wheel assembly with removable hub

Compagnie Generale des Etablissements Michelin


A counter-balanced sinker device for drift fishing or trolling comprising a tubular weight detachably affixed at one end to a flotation unit capable of holding said one end substantially vertically above the other end of such weight but incapable of lifting the entire weight, with means on the flotation unit to allow a fishing line to run freely therethrough. The device may be equipped with a weed or rocks deflector and with means to produce a fish-attracting noise when in use.

1. Field of the Invention
The present invention relates to a fishing device and more particularly pertains to such device which may be used to troll or drift fish a lure at a predetermined depth without snagging or hanging up on the bottom.
2. Description of the Prior Art
The use of fishing line sinkers is well is known in the prior art. More specifically, devices heretofore devised and utilized for the purpose of sinking a fishing lure are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
In this respect, the device according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of trolling or drift fishing a lure at depth without snagging on the bottom.
Some of the various configurations of prior art sinker devices are illustrated in U.S. Pat. Nos. 4,691,468; 4,450,646; 3,955,305; 3,461,597; and Des. 282,956.
Therefore, it can be appreciated that there exists a continuing need for new and improved sinker devices which can be snag-free. In this regard, the present invention substantially fulfills this need.


A new and unique crested Japanese fern Athyrium plant named ‘Crested Surf’ characterized by stiff upright habit and compound foliage with alternate deep-green bipinnately with light-green color near the center and wine-colored petioles and midribs. Pinnae and pinnules have compound crested apices.

The present invention relates to the new and distinct Athyrium niponicum given the cultivar name 'Crested Surf' and developed by the inventor in a greenhouse at a wholesale perennial nursery in Zeeland, Mich., USA. Through trials at the same nursery the plant was referred to by the code 09-124-01. The new plant has been successfully asexually propagated initially by division in 2015 followed by shoot tip tissue culture at the same nursery in Zeeland, Mich. Both these asexual propagation systems has been found to produce stable and identical plants that maintain all the unique characteristics of the original plant in successive generations.


A method of fabricating thermal ink jet printheads comprises aligning and bonding a pair of silicon wafers together, which have, on opposing confronting surface thereof, a plurality of sets of linear arrays of heating elements and associated driver circuitry on one wafer surface and a plurality of sets of parallel grooves and a communicating reservoir for each set of grooves. The grooves and reservoirs are filled with a filler material which is solid or gels at room temperature and liquid at higher temperatures. The bonded pair of wafers are severed into a plurality of individual printhead sby dicing processes conducted at room temperature. One of the dicing processes cuts the grooves in a direction perpendicular thereto in order to form concurrently the nozzle face and nozzles. The solid filler material supports fragile edges of the wafers and prevents entry of dicing debris and other contaminants. The printheads are subjected to heat, spinning, and high pressure water spray to remove the filler material.

This invention relates to thermal ink jet printing, and more particularly, to an improved method of fabricating a thermal ink jet printhead by use of a filler material in the internal cavities of bonded ink jet silicon wafers which is solid or gels at room temperature during the dicing operation which separates the bonded wafers into a plurality of individual printheads.
Thermal ink jet printing is a type of drop-on-demand ink jet systems, wherein an ink jet printhead expels ink droplets on demand by the selective application of a current pulse to a thermal energy generator, usually a resistor, located in capillary-filled, parallel ink channels a predetermined distance upstream from the channel nozzles or orifices. The channel end opposite the nozzles are in communication with a small ink reservoir to which a larger external ink supply is connected.
U.S. Pat. No. Re. 32,572 to Hawkins et al discloses a thermal ink jet printhead and several fabricating processes therefor. Each printhead is composed of two parts aligned and bonded together. One part is a substantially flat substrate which contains on the surface thereof a linear array of heating elements and addressing electrodes, and the second part is a substrate having at least one recess anisotropically etched therein to serve as an ink supply manifold when the two parts are bonded together. A linear array of parallel grooves are also formed in the second part, so that one end of the grooves communicate with the manifold recess and the other ends are open for use as ink droplet expelling nozzles. Many printheads can be made simultaneously by producing a plurality of sets of heating element arrays with their addressing electrodes on a silicon wafer and by placing alignment marks thereon at predetermined locations. A corresponding plurality of sets of channel grooves and associated manifolds are produced in a second silicon wafer. In one embodiment, alignment openings are etched in the second silicon wafer at predetermined locations. The two wafers are aligned via the alignment openings and alignment marks, then bonded together and diced into many separate printheads.
U.S. Pat. No. 4,638,337 to Torpey et al discloses an improved thermal ink jet printhead similar to that of Hawkins et al, but has each of its heating elements located in a recess. The recess walls containing the heating elements prevent the lateral movement of the bubbles through the nozzle and therefore the sudden release of vaporized ink to the atmosphere, known as blow-out, which causes ingestion of air and interrupts the printhead operation whenever this event occurs. In this patent a thick film organic structure such as Riston.RTM. or Vacrel.RTM. is interposed between the heater plate and the channel plate. The purpose of this layer is to have recesses formed therein directly above the heating elements to contain the bubble which is formed over the heating elements, thus enabling an increase in the droplet velocity without the occurrence of vapor blow-out and concomitant air ingestion.
U.S. Pat. No. 4,878,992 to Campanelli discloses an ink jet printhead fabrication process wherein a plurality of printheads are produced from two mated substrates by two dicing operations. One dicing operation produces the nozzle face for each of a plurality of printheads and optionally produces the nozzles. This dicing blade, together with specific operating parameters, prevent the nozzles from chipping and the nozzle faces from scratches and abrasions. A second dicing operation with a standard dicing blade severs the mated substrates into separate printheads. The dicing operation which produces the nozzle face is preferably conducted in a two-step operation. A first cut makes the nozzle face, but does not sever the two mated substrates. A second dicing cut severs the two substrates, but does so in a manner that prevents contact by the dicing blade with the nozzle face.
In all ink jet printing systems, the nozzle or orifice size, shape, and surface conditions affect the characteristics and trajectory of the ink droplet emitted from the nozzle. Some ink jet printers have a separate nozzle plate which is independently fabricated to obtain the desired dimensional tolerances and surface conditions. This nozzle plate is then aligned and bonded to the droplet generator or printhead. In addition to the dimensional precision, attachment is sometimes difficult and debonding is a constant concern. Also, if an adhesive is used, it may flow into the nozzle or ink paths, thereby restricting or impairing the droplet ejection and/or trajectory. Other ink jet printers have printheads fabricated from two substrates, as disclosed in the prior art discussed above, in which one substrate contains the heating elements and the other contains ink recesses, which, when the substrates are aligned and bonded together, serve as ink passageways. The open ends of the passageways terminate about 1.0 to 5.0 mils in front of the heating elements and create the nozzles. The front face of the printhead containing the nozzles have a major impact on the droplet characteristics and trajectories. One discontinuity at the nozzle is made by chipping of the unsupported edges of the channels during the dicing operation which concurrently forms the nozzle face and nozzles by cutting across one end of the channels in a direction perpendicular thereto. A second problem with severing bonded silicon wafer pairs in a plurality of individual printheads, is that dicing debris is readily forced through the nozzles and wedged into the channels. The dicing debris is usually difficult, if not impossible, to remove because of the relatively small cross-sectional areas of the channels and nozzles.
This invention overcomes the above-mentioned two problems associated with the standard dicing techniques used to separate bonded, thermal-ink-jet, silicon-wafer pairs into a plurality of printheads.

Method of reducing chipping and contamination of reservoirs and channels in thermal ink printheads during dicing by vacuum impregnation with protective filler material


An object of the present invention is to provide a switching power supply which can stably determine whether an overcurrent occurs or not on the secondary side. A sample voltage corresponding to a load current value detected by detection resistors R7 and R8 is compared with a reference voltage by an input-side transistor Q4 and an output-side transistor Q3 which compose a first current mirror circuit 14, so that it is possible to determine whether an overcurrent occurs or not. Moreover, a current passing through the output circuit of the transistor Q3 is temperature-compensated by a second current mirror circuit 17 made up of transistors Q6 and Q5.

In a power supply, an overcurrent protection circuit is provided for limiting a load current to protect the power supply and a load from an overload. Generally, overcurrent protection is broadly divided into three methods shown in FIGS. 8(a), 8(b) and 8(c).
In FIG. 8(a), when an output current exceeds the set upper limit, an output voltage decreases and the output current is reduced to provide protection. This method is called Fold-back Type Drooping Characteristic based on the pattern of the correlation characteristic of the output voltage and the output current.
In FIG. 8(b), when an output current exceeds the set upper limit, the output current is immediately reduced to provide protection. This method is called "pendent character" based on the pattern of the correlation characteristic of an output voltage and the output current.
In FIG. 8(c), when an output current exceeds the set upper limit, the output current is reduced at a constant power to provide protection. This method is called an inverted V-shaped characteristic based on the pattern of the correlation characteristic of an output voltage and the output current.
In the case of a switching power supply for detection for overcurrent protection only on the primary side of a transformer, an overcurrent protection set value is deviated by a change of an input voltage, resulting in low accuracy.
In the case of the overcurrent protection characteristic of FIG. 8(c), it is possible to protect a switching transistor on the primary side of a transformer but a current increases in a diode for rectification on the secondary side of the transformer even under protection, which is disadvantageous to overcurrent protection (described in Patent Document 1 and so on).
As compared to FIG. 8(c), when a load current is detected on the secondary side of a transformer T1 as shown in FIG. 6, satisfactory overcurrent protection can be expected.
In FIG. 6, to a primary winding 11 of the transformer T1, an input DC voltage V1 is applied through a switching transistor Q1 acting as a series control element. The frequency of a pulse signal Psw applied to the base of the switching transistor Q1 is controlled by a control circuit 13.
The output of a secondary winding 12 of the transformer T1 is half-wave rectified by a diode D2 and the output is smoothed by a capacitor C3 to obtain an output voltage Vo. A load current i1 is detected by a detection resistor R7 disposed in a secondary-side circuit.
An error amplifier Z2 for supplying information to the control circuit 13 according to a detected voltage of the detection resistor R7 is configured as follows:
A current mirror circuit 14 is made up of an input-side transistor Q4 and an output-side transistor Q3. Between a reference potential G and the base of the transistor Q4 whose base and collector are connected to each other, a voltage source B1 is connected via a resistor R6. The emitter of the transistor Q4 is connected to the detection resistor R7 on the side of the reference potential G.
The base of the transistor Q3 is connected to the base of the transistor Q4 and the collector of the transistor Q3 is connected to the junction point of the resistor R6 and the voltage source B1 via a resistor R4. The emitter of the transistor Q3 is connected to a junction point 15 of the detection resistor R7 and the secondary winding 12 via a resistor R3.
A junction point 16 of the collector of the transistor Q3 and the resistor R4 is connected to the base of an output transistor Q2 via a resistor R2. The emitter and collector of the transistor Q2 are interposed between one end of a resistor R1 having the other end connected to the control circuit 13 and the reference potential G.
In the error amplifier Z2 configured thus, the resistor R4 for determining a reference voltage is connected to the collector of the transistor Q3 and the amplification degree of the error amplifier Z2 is determined by a ratio between the resistance values of the resistors R3 and R4.
When the load current i1 increases, a voltage drop across the detection resistor R7 increases, the voltage of the junction point 16 of the resistor R7 and the resistor R3 decreases, and the collector current of the transistor Q3 increases. Accordingly, a potential decreases on the junction point 15 of the collector of the transistor Q3, the base current of the output transistor Q2 increases, and the load current i1 increases to a set value. At this point, the resistor R1 connected to the control circuit 13 is connected to the reference potential G via the output transistor Q2 and the switching frequency of the primary side is controlled to achieve overcurrent protection of "Fold-back Type Drooping Characteristic" shown in FIG. 8(a).    Patent Document 1: Japanese Patent Laid-Open No. 2004-215394


The present invention relates to speech recognition systems, particularly speech-to-text systems and software and decoders for the same. The present invention provides a decoder for an automatic speech recognition system for determining one or more candidate text unit concatenations according to a predetermined criterion and which correspond to a speech segment, the decoder comprising: means for receiving a sequence of feature vectors corresponding to the speech segment; means for mapping with different likelihood values the feature vectors to sequences of nodes in a decoding network, every sequence representing a concatenation of text units; means for determining one or more candidate node sequences in the decoding network corresponding to the candidate text unit concatenations by implementing a dynamic programming token passing algorithm in which each token corresponds to a node and is associated with a number of text unit concatenations and likelihood values for these concatenations, and wherein a token associated with a node in the decoding network is derived from the tokens associated with the previous nodes in the network; wherein tokens from different nodes that are to be passed to a common node are combined to generate a new token corresponding to the common node and associated with an identifier for text unit concatenations and likelihood values associated with the previous tokens of said different nodes. This is combined with means for merging a said token having a said identifier, the text unit concatenations of the said previous tokens being associated with said merged token dependent on their corresponding likelihood values.

Automatic Speech Recognition (ASR) systems are used in many applications to convert speech to text, for example digital dictation on a computer system or voice command recognition in embedded systems such as those provided in modern cars. Such systems take a digitised audio signal of an utterance, such as speech, as input and provides the text transcription of the audio signal as output. ASR is memory and processing power intensive, which is particularly problematic for embedded applications where limited use of resources and low cost are desirable.
The recognition is achieved by taking short samples of the speech, converting them to feature vectors that represent a speech segment, and mapping sequences of these vectors to possible sequences or concatenations of text units or words. The system associates a probability or likelihood to text unit sequences given a sequence of feature vectors, depending on how well they correspond to the feature vectors. The particular sequence of text units having the highest probability is prima facie the most likely textual transcription of the speech or feature vector sequence.
A typical application would be an on-board speech recognition system on a car. The effective resources available to the system may be limited to 1 megabyte RAM and 1 megabyte ROM memory and 100 MIPS cpu power. Typical input sentences could be "open the window" and "navigate to Baker Street". The actual footprint required differs strongly between a small command and control system (which perhaps only needs to recognise some 100 short phrases such as "start cd player") and a nagivation system (which may need to recognise thousands of streetnames).
Depending on the application, the set of all possible text unit sequences (sentences) can be small or very large. A language model represents a constraint on possible text unit sequences which make sense in the application. This is combined with a lexicon, which contains one or more pronunciations for every text unit. Using the language model and the lexicon a decoding network is constructed, such that a path through the network corresponds to a specific pronunciation of a specific text unit concatenation. An acoustic model is used to assign likelihood values to any path through the decoding network. These values depend on how closely the pronunciation implied in the path matches the observed feature vectors.
The decoding network represents the (often huge) number of paths in an efficient way by representing the paths as a network that connects nodes with arcs, possibly using techniques such as null nodes (that only serve to connect other nodes). A typical decoding network contains labels on arcs that represent text units, such that all paths together represent all valid sequences of text units in a particular language domain, for example the totality of valid commands in an in-car voice command recognition system. The nodes in such a network each represent one step in the chain of observations of feature vectors. This is usually associated with one or more states, but as noted above there are also null nodes which don't map to any state. A state is a multidimensional probability density function that enables calculating likelihoods of observations. One state can be associated to multiple nodes in one path, reflecting multiple occurrences of a sound, or in different paths, representing the same sound in different potential utterances.
A calculation is then performed to determine which path is the most likely, and in many applications this is taken as the textual transcription of the speech segment. In the above in-car command recognition system, this transcribed command is then input for a controller to, for example, open the window. This calculation is typically carried out using the Viterbi algorithm. Alternatively the Baum-Welch (or Forward-Backward) algorithm may be used. These algorithms can be formulated as Token Passing algorithms, as described in Token Passing: a simple conceptual model for connected speech recognition systems, by S. J. Young, N. H. Russell, J. H. S. Thornton, Cambridge University Engineering Department, Jul. 31, 1989.
These algorithms can be thought of as using tokens that are associated with a node in the decoding network and represent the best partial path from the start node up to that node. Each token is a (logical) data structure, is stored in memory, and is associated with a text unit or word history corresponding to the best partial path leading to that node. The tokens also comprise a likelihood "score" for the word history.
In many applications, the N-best word sequences are required, for example in case the user or speaker indicates that the best or highest likelihood sequence is incorrect, the next best or second highest likelihood sequence is offered as an alternative, and so on up to N. In the N-best case, not only the best but the N best paths up to every node have to be stored. The algorithms can handle this by extending a token such that it contains N word histories and associates a likelihood or score with every such word history. A further reason for maintaining the N best paths up to every node is the use of a statistical languguage model, which is a score based on the relative frequency of text unit sequences, which can be added to the likelihoods inside the token. In the specific case of using words as text units and considering the last three words, this is commonly known as a trigram language model. In that case it is still possible to provide alternative sequences to the application if required.
In these algorithms, a first token is created with an empty word history and is associated with the start node. After this, for every new feature vector, every token is copied to all nodes that it can reach though network arcs. There are also 'self-loop' arcs, which connect a node with itself, effectively making it possible for a token to remain at a node for some time. Every likelihood is updated with the likelihood of the feature vector given that state and also with a transition probability associated with the arc leading to the next node. When two or more tokens with equal word history meet, either the highest likelihood (Viterbi) or the combination is used (Baum-Welch). When two or more tokens with different word history meet, either the best one is chosen (1-best) or a selection from the various word histories is chosen that reflects the N best from the two tokens.
Processing through the network may halt after a predetermined end node is reached, and/or after a certain period, for example corresponding to the end of the speech segment. If successful, the token associated with the end node will contain a likelihood score corresponding to the or each sequence of nodes in the path(s) leading to the end node.
In a practical network containing perhaps thousands of nodes and far more possible paths, this has implications for memory space and cpu requirements. Various techniques are used to reduce the processing and/or the amount of memory resources utilised in the token passing process. For example pruning is used to delete tokens corresponding to very unlikely sequences so that further processing associated with that sequence can be halted in order to free up processing power and memory space.
Even with these existing techniques, ASR systems require significant processing power and memory resources, which is particularly problematic in smaller embedded applications such as in-car voice command recognition systems where there is a desire to minimise processor and/or memory resources.


A computer-implemented method provides power to a fingerprint reader while the remaining components of the information handling system are held in a low power, non-operating state. Placement of a finger across the fingerprint reader is detected with the information handling system in the non-operating state. A fingerprint is read and a corresponding fingerprint image is generated. The fingerprint image is buffered and an embedded controller is triggered to start an authentication device having a secure storage. The fingerprint image is compared to a fingerprint template contained in the secure storage. In response to the fingerprint image matching the fingerprint template, the authentication device signals the embedded controller to activate a user authenticated wake-up cycle to provide power to the other components of the information handling system such that the information handling system activates an operating system and enters a fully powered and user authenticated, operational state.

1. Technical Field
The present disclosure generally relates to providing secure access to an information handling system and in particular to enabling fingerprint-based access to a user-authenticated operational state of an information handling system.
2. Description of the Related Art
As the value and use of information continue to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes, thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Providing secure access to an information handling system is important to prevent unauthorized access to applications and/or data available on the information handling system. Various methods are known to provide secure access to information handling systems. For example, various levels of passwords can be used to limit access to an information handling system. Biometric data can also be used to restrict access to the information handling system by only authorized users. One problem with the use of passwords and biometric data is that at least a portion of the passwords and biometric data is stored on unsecure system memory that is vulnerable to theft or modification by malware, viruses and other malicious programs.
Another problem with the use of passwords and biometric data is that at least an entire authentication system is required to be powered and continues to consume power even when the information handling system is in a powered down or sleep state. Unfortunately, for portable information handling systems that are battery powered, when the information handling system is in a sleep state, to allow for quick resumption of the system, the authentication system continues to consume and deplete battery power. Over a period of time, the battery can be completely discharged resulting in a non-operational information handling system.

Apparatus and method for enabling fingerprint-based secure access to a user-authenticated operational state of an information handling system


A fluxometer system and method is provided. The fluxometer comprises a frame, a simulated circuit board disposed in the frame and having a plurality of holes formed therein extending generally transverse to a plane of the board and a cover. The cover is received on the frame over the simulated circuit board and includes several protrusions simulating leads that extend into the holes of the simulated circuit board. The fluxometer further includes an indicator sheet disposed between the simulated circuit board and the cover, the protrusions extending through the indicator sheet.

The invention relates generally to wave solder systems, and more specifically to a fluxometer used for monitoring flux deposition.
Wave soldering is a common method of forming solder joints between electronic components and circuit traces on a printed circuit board (PCB). Typically, electronic components are placed on the PCB and their leads are inserted into holes in the circuit board such that the leads are in contact with metal pads or plating on vias to which they are eventually soldered.
A typical automatic wave soldering system includes conveyors driven to move the PCB at a constant speed from an entrance to an exit end of the system. The board is first carried to a fluxer where a spray of flux is applied to the bottom of the board. The PCB is then carried over heaters to evaporate excess flux deposits, activate the flux and minimize thermal shock. After the PCB is heated to a desired temperature, the board is passed over a solder pot to receive solder. The board is finally transported to a cool down zone where the solder is cooled and solidifies.
To ensure that all component leads are appropriately soldered, flux should be appropriately deposited such that it coats each component lead hole on the PCB even with the presence of leads of the electronic components. In general, components tend to solder better when the amount of flux deposited in the holes is sufficient. When the holes are partially coated, the boards may pass a testing stage but in time one or more of the component leads breaks away from the board due to poor soldering.
Several parameters of the fluxer are therefore set to ensure that flux is sprayed on to the PCB such that it properly contacts and/or fills each hole or via. Examples of fluxer parameters include atomization of the flux, a driving force of the fluxer spray, speed of a spray head of the fluxer, etc. The amount of flux deposition on the holes of the PCB directly depends on these fluxer parameters.
Typically, fluxer parameters are adjusted by testing a batch of PCBs that are first soldered using a set of fluxer parameters and subsequently making adjustments to the fluxer parameters based on the test results. This technique however is time consuming, expensive and may not render accurate settings for the fluxer. Fluxometers have been developed for testing application of flux to the desired regions of the board, but these are generally ineffective at accurately simulating and evaluating flux coverage.
Therefore, there is a need for a method and system to accurately set the parameters of the fluxer to ensure that the flux is appropriately deposited on printed circuit boards.

Fluxometer with a cover having protrusions


Rotation of photosensitive drums 21, 22, 23 and 24 is started and a full-color mode by a transfer roller drive unit is set for the exposing by an exposing unit 11. When the full-color mode is set, a transfer belt 25 contacts all the photosensitive drums 21, 22, 23 and 24. Then, after a paper sheet P passes through a secondary transfer roller 57, an all-separate mode by the transfer roller drive unit is set, and the rotation of the photosensitive drums 21, 22, 23 and 24 is stopped. When the all-separate mode is set, the transfer belt 25 separates from all the photosensitive drums 21, 22, 23 and 24.

An image forming apparatus having color copying capability is provided with photosensitive drums for yellow, magenta, cyan and black colors. A laser beam is applied to the surfaces of these photosensitive drums, and electrostatic latent images are formed on the surfaces of the photosensitive drums. The electrostatic latent images are developed with developers for the yellow, magenta, cyan and black colors, and become visible images. The visible images are transferred to a transfer belt, which is moved in making contact with the surfaces of the photosensitive drums. The visible images of each color transferred to the transfer belt are transferred to a paper sheet. The transferred paper sheet is sent to a heating roller. The heating roller heats the paper sheet to fix the visible image transferred to the surface of the paper sheet. The transfer belt is pressed to the surfaces of the photosensitive drums by transfer rollers.
In such an image forming apparatus, the transfer belt is moved continuously even after the visible image is transferred to a paper sheet, until the unnecessary developer remaining on the transfer belt is eliminated by a cleaner. As the movement of the transfer belt is continued, the rotation of the photosensitive drum contacting the transfer belt is also continued.
A cleaning blade contacts the surface of each photosensitive drum, and eliminates the unnecessary developer remaining on the drum surface. Thus, if the rotation of the photosensitive drum is continued, the photosensitive drum surface becomes unnecessarily worn and the drum life is reduced.
Moreover, a developing roller of a developing unit contacts the surface of each photosensitive drum. The developing roller supplies developer to the surface of the photosensitive drum while rotating together with the drum. Thus, when the rotation of the photosensitive drum is continued, the developing roller is rotated unnecessarily causing unnecessary shift and stir of the developer, and the developer is degraded unnecessarily.

Image forming apparatus with selectively movable transfer rollers


Directly operating on data structures in a generic manner regardless of the type of data structure being operated upon and without requiring dedicated executable code for manipulating data structures of the particular data type. A common set of commands (e.g., insert, delete, replace, update, query) are recognized that may be used to operate on data structures of a number of different data types. A navigation module accesses a request to execute one of the common command methods on at least an identified portion of an identified data structure. Then, the navigation module accesses a navigation assistance module to access a set of rules associated with the particular data type, the set of rules allowing the navigation module to find the portion of the data structure that is to be operated on. If appropriate, the command operation is then executed on the identified portion of the data structure.

1. The Field of the Invention
The present invention relates to the field of data access technologies. Specifically, the present invention relates to methods, systems, and computer program products for accessing heterogeneous data in a standardized manner.
2. Background and Related Art
The success of the information age is widely attributed to the ability to efficiently access data. Data comes in a wide, almost unlimited, variety of different data types. For example, there may be data types corresponding to calendar information, task information, in-box information, word processing documents, presence information, favorite web site information, or a host of other different types of information.
Typically, a data structure is accessed using an object that is customized with special executable code and properties that are tailored towards accessing data structures of particular data types. This conventional model is illustrated in FIG. 1. The illustrated model 100 includes only three types of data being accessed; namely, calendar data 110, in-box data 120, and document data 130. Although the conventional model includes any number of different data types, only three are shown for clarity.
Each of the data types, such as calendar data 110, in-box data 120, and document data 130, are encapsulated by a corresponding object such as calendar object 111, in-box object 121, and document object 131, respectively. These objects each contain code (e.g., calendar code 112, in-box code 122, and document code 132) and properties (e.g., calendar properties 113, in-box properties 123, and document properties 133) that are customized to the particular data type being encapsulated. In addition, the various services of the objects are accessed through controlled and type-specific interfaces (e.g., calendar interface 114, in-box interface 124, and document interface 134) that offer customized methods that are appropriate for the corresponding data type. For example, these interfaces may service customized function calls.
While this conventional model allows various entities to access corresponding data, the access methods differ from data type to data type. In addition, a customized data object is required for each data type. In this context, what is desired are methods, systems, and computer program products that facilitate access to data in a more efficient manner.

Accessing heterogeneous data in a standardized manner


A new and distinct cultivar of Azalea plant named ‘Lazamoropi’, characterized by its medium purple-colored flowers, dark green-colored foliage, moderately vigorous, semi-upright growth habit, and strong multi-seasonal reblooming, is disclosed.

The present invention relates to a new and distinct cultivar of Azalea plant botanically known as Rhododendron hybrid and hereinafter referred to by the cultivar name 'Lazamoropi'.
The new cultivar originated in a controlled breeding program in Independence, La. during the spring of 1996. The objective of the breeding program was the development of Azalea cultivars with attractive flower color with multi-seasonal blooming and that perform well in the garden.
The new Azalea cultivar is the result of open-pollination. The female (seed) parent of the new cultivar is the proprietary breeding selection coded VFXOHI-1, not patented, characterized by its medium fuchsia-colored flowers, dark green-colored foliage, and vigorous, upright growth habit. The male (pollen) parent of the new cultivar is unknown however the female was outdoors and in close proximity to numerous proprietary hybrids that had cold hardiness, compact growth habit, and multi-seasonal blooming traits. The new cultivar was discovered and selected as a single flowering plant within the progeny of the above stated open-pollination during the fall of 2010 in a controlled environment in Independence, La.
Asexual reproduction of the new cultivar by terminal stem cuttings since the fall of 2010 in Independence, La. and later in Loxley, Ala. and Irvington, Ala. has demonstrated that the new cultivar reproduces true to type with all of the characteristics, as herein described, firmly fixed and retained through successive generations of such asexual propagation.


An evaporative cooler which includes a sealed loop of conduit with a first portion in a space to be cooled and a second portion in a space where heat is rejected, a volume of working fluid, and a fan inside the conduit loop. The fan forces air over the working fluid to accelerate its evaporation, which requires heat. Evaporation creates vapor-enriched air which carries heat and is forced by the fan to the second portion. Within the second portion, the vapor-enriched air rejects the absorbed heat before being forced back to the first portion. In certain cases, a portion of the working fluid in the vapor-enriched air condenses out and drains or is pumped back to the first portion. In certain uses, the cooler provides cooling to an area. In other uses, the cooler captures vaporized water, producing an impurity-free condensate for removal or use.

The comforts of air conditioning, refrigeration and access to clean water are considered necessities in our modern world. However, air conditioning, refrigeration, and even access to clean water rely heavily on an abundance of reliable energy and wealth to obtain, install, power, and maintain associated systems. In fact, it is common to have separate devices for providing air conditioning, refrigeration, and clean water, each with its own costs and energy needs. Further, conventional cooling and refrigeration systems are typically complex with many different parts, stages, and underlying principles, in addition to being costly and requiring reliable energy sources. Indeed, both air conditioning, refrigeration, and water purification systems typically have dedicated personnel to design, install, maintain, and repair them.
However, many portions of the world are too remote and impoverished to have access to the wealth, experience, and reliable energy sources necessary to provide, power, and maintain air conditioning, refrigeration, or clean water systems. Even in industrialized nations, many people are seeking ways to lower the costs and energy requirements necessary to provide, power, and maintain such systems. Efforts to lower the complexity, costs and energy requirements of air conditioning and refrigeration have been proposed which involve alternative cooling methods. One such method is evaporative cooling. Devices which utilize evaporative cooling, loosely identified as evaporative coolers, are known in the art. Evaporative coolers are generally far simpler and require less energy than typical air conditioning systems which utilize electro-mechanical vapor compression refrigeration or absorption refrigeration. However, in most climates, evaporative coolers increase indoor humidity—a factor in mold growth and upper respiratory infections—unless there is a continuous exhaust of treated air from indoor areas. Also, evaporative coolers generally require a constant supply of water to continuously operate. Furthermore, no known evaporative coolers are designed for the capture of airborne water vapor as part of their operation.
Consequently, it would be advantageous to provide a device and method which, in one or more aspects, overcomes the aforementioned limitations of the current state of the art, providing an alternative to electro-mechanical vapor compression refrigeration and absorption refrigeration while not requiring the continuous exhaust of treated air or a constant supply of water, while simultaneously dehumidifying and providing clean water for alternative uses.

Evaporative cooler and moisture condenser with vapor recovery and method


A protective device comprises an input, an output, a first power switch, a second power switch and a drive unit. The first and second power switches are electrically connected in parallel with one another between the input and the output. The first power switch is configured to conduct a first forward current in a conducting state and to limit said first forward current in a current-limiting state. The second power switch is configured to conduct a second forward current in a conducting state and to interrupt said second forward current in an interrupting state. The second power switch comprises a lower on resistance than the first power switch. The switch arrangement is configured, for limiting the current flowing between the input and the output, to interrupt the second forward current with the second power switch and to limit the first forward current with the first power switch.

Fieldbus systems comprising fieldbus modules are used in automation technology, inter alia, in order to control automation processes in installations comprising components arranged in a distributed fashion. Fieldbus systems generally comprise a fieldbus, via which a controller is connected to the fieldbus modules arranged in a distributed fashion. The fieldbus modules generally comprise inputs and/or outputs. The sensor arrangement is connected to the inputs of the fieldbus modules, and the actuator arrangement of the fieldbus system is connected to the outputs of the fieldbus modules. The sensor arrangement comprises for example all sensors that detect the state of the automation process to be controlled. The actuator arrangement comprises for example all actuators that may alter the state of the process to be controlled. Actuator arrangement and sensor arrangement are part of the field devices of the fieldbus system.
The fieldbus generally comprises a data transmission medium, for instance a network connection, via which data are transmitted between the controller and the fieldbus modules. For controlling the automation process, the fieldbus modules read in input signals from the sensor arrangement via their inputs, wherein the input signals represent the measurement values detected by the sensors. The fieldbus modules convert the input signals into input data, which are then transmitted via the fieldbus to the controller. The controller carries out a logic operation on the input data in order to generate output data for controlling the automation process by the actuator arrangement. The output data are transmitted via the fieldbus from the controller to the fieldbus modules and are converted into output signals by the fieldbus modules. The output signals are in turn output via the outputs of the fieldbus modules in order to drive the actuators.
An electrical supply energy required for the operation of the fieldbus modules or of the field devices connected to the fieldbus modules is generally provided by an energy supply device of the fieldbus system. The energy supply device is connected to the fieldbus modules generally via a supply line. In order to prevent the supply line, the energy supply device, the fieldbus modules or the field devices from being overloaded during the process of providing the supply energy, a protective device may be inserted into the supply line, which safeguards the supply line and the components connected to the supply line. The protective device is connected to the supply line generally between the energy supply device and the field devices to be safeguarded.
A protective device of this type is generally configured to monitor the supply line to which the supply energy is applied, for example by monitoring a voltage or a current flow on the supply line. The protective device generally comprises a power switch configured to interrupt the supply line and thus the forwarding of the supply energy to the field devices if a fault is ascertained during the monitoring of the supply line. The fault may be for example an in particular permanent, exceedance of a maximum permissible current or an exceedance of a maximum permissible voltage.
In addition, the power switch may be configured to limit the current intensity of the forwarded supply energy. The power switch may limit the current intensity in particular in the case of abrupt load changes at the output of the protective device, such as occur for example when capacitive or inductive loads are switched on or off.
The power switches used in the protective devices generally comprise a finite on resistance even in the on, that is to say closed, state, with the result that in the power switch electrical losses occur and heat loss is generated. The electrical losses are particularly high if high currents occur when the supply energy is forwarded via the supply line. This is the case particularly for the supply of actuators, for instance of electric motors.
In order that the protective device may effectively and reliably limit the current flow on the supply line, the power switch should be designed in such a way that it may take up and dissipate the power loss that arises during the limiting of the current flow. The power loss that arises may be greater by a multiple than the power loss that arises on account of the on resistance with the power switch permanently switched on. Therefore, the current limiting may generally be maintained only for a predefined maximum duration. If it is still necessary to limit the current flow after the maximum duration has elapsed in order to protect the field devices, the power switch must completely interrupt the current flow on the supply line.
In order to dissipate the heat that arises during the operation of the power switch, the power switch is generally provided with a heat sink, which may occupy a large amount of structural space at the housing of the protective device. In many protective devices the size of the heat sink determines the minimum size of the housing, with the result that it is difficult to arrange protective devices in compact housings.
The document DE 10 2011 120 466 A1 describes a protective device which is referred to as an electronic circuit breaker and which comprises a power switch for limiting the current flow in a current path to be monitored.

Protective device and fieldbus module comprising a protective device