Techniques for forming an application from a particular file that has source code in a particular language include receiving, from the particular file, comment data. The comment data is ignored according to the particular language. The comment data includes build data indicating how to use the source code in a build process. The build process packages compiled code to form the application. Based on the build data in the comment data, build-input data is generated. The build-input data indicates input for the build process. These techniques automatically provide, for the application build process, build information known to the application developer who produced the source code.

Software applications execute on computing devices to perform a variety of functions related to processing and presenting information to users. A large application is typically made up of one or more source code modules, each written in a high-level programming language designed to facilitate human understanding of the steps involved in each module. Example high-level programming languages include FORTRAN, Microsoft Visual Basic, C, C++, and Java®. Statements in such languages are combined to write each module. One or more source code modules are stored together in a source code file. The statements are converted to instructions for a processor on a computing device, which instructions are sometimes called machine instructions, by a particular process, such as a compiler. A compiler generates machine instructions based on several statements or an entire module. The machine instructions are peculiar to particular families of processors.
The machine instructions derived from a source code module constitute an object code module. One or more object code modules are stored together in an object code file. Object code modules use relative addresses to refer to locations in memory. An executable code is generated from object code by linking together the object code and converting relative addresses to absolute addresses.
After the source code modules that make up the software application are written in a programming language, the application is built from the source code files. Building involves retrieving the files containing the source code modules and compiling or interpreting them, depending on the language of the source code, to produce object code files. In some circumstances other files that contain data used by the modules are also retrieved. In some circumstances, building also involves storing one or more object files together with any data files needed in one or more packages. In some circumstances, the modules are linked together and stored as an executable in one of the packages. Some systems use dynamic linking, which links object code modules as needed during the course of the processing. In systems using dynamic linking, the executable is not generated during the build process or stored in one of the packages. The packages are then deployed in one or more directories on a computing device, or on one or more computing devices on a network, to be accessed by users of the application.
For example, in the Java language each source code module is a class that defines attributes and methods for objects formed from the class. The Java class is compiled into bytecode that is executed by a Java virtual machine (JVM) process running on a processor. Under some circumstances, a Java application is formed by packaging bytecode of all the Java classes for the application in a Java archive ("jar") file. The jar file may then be downloaded from one computing device on a network to a second computing device on the network. The application may then be executed on the second computing device.
Building and deploying a large application is a tedious task. Dozens of modules in thousands of files spread over dozens of directories may be involved. Some modules are used only in testing and should be included in debug versions but not in release versions of the application. Some modules change with different versions of the application. Some modules are appropriate for interactions with a web server and others for interaction using other network protocols or no network at all. Thus the modules used in a build depend to some extent on the way the application is deployed.
Several tools have been developed to handle tasks involved in building an application. For example, "make" tools are available on several computer devices running the UNIX operating system and derivatives thereof, such as LINUX. Similar make tools are available for other operating systems. A make tool receives, as input, a make file that is manually prepared by a build engineer and includes names and locations of modules and data files, and names and locations of packages, as well as names and locations of compilers, interpreters and linkers. The make tool processes the make file and generates a set of operating system commands to retrieve and compile the modules listed in the input and to package object code files or executable files with data files. However, a disadvantage is that such tools may be configured to operate only with a specific operating environment configuration.
Another disadvantage is that the build data is retrieved from two locations: the source files (e.g., as directed by import or include statements) and the makefiles (e.g., including the jar file that such files belong to). This makes the build data complicated and hard to handle. Still another disadvantage is that the makefiles, operation of the make tool, and overall supervision of the build process is normally carried out by a release engineer or build engineer, whereas the best source of knowledge about the contents of the source code is normally a different individual, such as a development engineer. Thus, there is no central point of comprehensive knowledge about both the source code and the build process.
Recently, a tool called "Ant" has been introduced that allows the build engineer to specify input for the build tool in an extensible markup language (XML) file. The Ant tool processes the XML file and executes necessary commands in the same general manner as Make. "Ant" is written in Java, and therefore runs on a larger variety of operating systems; it is also more expressive than Make, and is extendible. Descriptions of the Ant tool at the time of this writing can be viewed from file index.html on the ant directory on the worldwide web (www) at domain jakarta.apache.org.
In this description, the term "build" tool is used to refer to any tool, including make tools and Ant, which packages compiled code to form an application.
A problem arises in building complex applications that are created by a team of engineers or developers, because the information used for the build tool does not reside in the knowledge of a single person or working group. The choice of package names and the use of individual modules in different deployments of the application are best known to the application developer or development group. However, information about the deployment computer devices and installed tools is best known by a build engineer or build group. For example, the choice of the number and location of packages depends on the components, architecture and operating systems of the deployment computing devices and network. The choice of compilers, interpreters, and linking processes depend on the software tools already installed on the deployment computing devices and network. The expressions for listing modules, files and tools depend on the scripting language or XML input used in the build tool.
One past approach is for the developer to provide the build engineer with source code. The build engineer employs a build tool to construct the packages. If the build engineer does not include all the modules needed, an error occurs during the build or upon execution of the resulting application. Upon occurrence of an error, the build engineer communicates with the developer to formulate some corrective action. The process is repeated until an application is produced without errors.
However, this approach has numerous disadvantages. It is tedious to reiterate the process and test for errors. Even if no errors are found, the application may include extraneous modules that did not cause an error. For example, the packages may include debug routines that are not used in a release version. As another example, the package may include obsolete modules that cause a known fault in some circumstances not apparent to the build engineer and not expressed during routine testing. Furthermore, after several months or years of evolution for the application, the original developer may no longer be employed by the company that provides the application. Thus the original developer may be inaccessible to the build engineer.
Based on the foregoing, there is a clear need for techniques that automatically provide, for the build process, any build information known to the application developer.

Techniques for generating software application build scripts based on tags in comments


The device for treating food wastes comprises a housing which includes a feeding port formed at an upper side of the same for feeding food wastes, a drainage port formed at one side of a lower surface of the same for discharging leachate separated from the fed food wastes, and a discharge hole formed at the other side of the lower surface of the same for discharging dehydrated remnants among the food wastes; an inner casing which is installed at a certain distance from an inner wall of the housing and includes a drainage net installed at an upper side for discharging water fed together with the food wastes, a drum which is installed at a center of the same and has a plurality of wall surface blades at an inner circumferential surface, and a dehydration net installed at a lower side of the same for discharging leachate; a grinding screw which is vertically installed at an inner side of the inner casing and includes a plurality of screw blades installed at an outer circumferential portion and contacting with a wall surface blade of the drum, and the dehydration net.

1. Field of the Invention
The present invention relates to a device for treating food wastes capable of significantly decreasing food wastes in such a manner that a device for treating food wastes is installed at a lower side of a drainage port of a kitchen sink for thereby dehydrating and grinding food wastes.
2. Description of the Background Art
Generally, a food waste treating device has a body formed of a feeding part for feeding food wastes, a discharge part for discharging food wastes, and a screw for grinding food wastes.
The Korean patent laid-open No. 240229 invented and filed by the applicant of the present invention discloses a conventional device for treating food wastes. As shown in FIG. 1, in the above conventional device 100 for treating food wastes, a grinding screw 102 is engaged at a drum body 106 having a cutting blade 107 and a drainage port 108. The food wastes are dehydrated in such a manner that the grinding screw 102 is rotated with respect to the drum body 106. A dehydrating cap 113 having a dehydrating port 11 for discharging only water and a discharge port (not shown) for discharging food remnant is screw-engaged at one side of the drum body 106. A cover 115 detachable at a filtering net 114 formed of a plurality of through holes is fixedly engaged at the other side of the same.
In the food waste treating device 100, the feeding part 116 is vertically installed while the grinding screw 102 is horizontally installed, so that food wastes are moved in a horizontal direction for thereby compressing and grinding the food wastes. Therefore, if flexible and smooth food wastes are fed, the remnants are not well moved and discharged. In this case, the remnants are discharged through the drainage port 108 in a colloid state together with leachate for thereby causing a water pollution problem. If hard foreign substances, which are not well ground by the grinding screw 102, are fed, the food waste treating device 100 is damaged, so that it is needed to repair the damaged food waste treating device 100.
In addition, as shown in FIG. 2, a certain shelf 60′ is additionally needed so that a food waste box 60 is installed at the discharge port 13, and a certain engaging unit should be provided for engaging the food waste box 60 and the discharge port 13. In the conventional, it is impossible to know a discharge time of the food wastes because a user cannot check the amount of the food wastes.


An improved anti-corrosive material used to protect buried conduits from corrosion. The anti-corrosive material is comprised of a conduit contacting layer of polyolefin having the anti-corrosive agents impregnated therein. The preferred embodiment of the material is a multi-layered co-extruded, calendered, or laminated polyolefin. The material has an outer layer, or environment contacting layer, preferably comprised of a low density polyethylene having characteristically strong tensile strength and elongation properties to provide conventional protection from soil, water, air, or other potentially damaging elements. The material has a center layer preferably comprised of a high density polyethylene having superior tensile strength to provide a high density barrier between the outer layer and an inner layer. The inner layer, or conduit contacting layer, is preferably comprised of a low density polyethylene impregnated with one or more antimicrobial additives. The antimicrobial additives are incorporated into and dispersed throughout the conduit contacting layer for killing corrosion-inducing bacteria on the surface of the conduit. The antimicrobial additives are able to migrate through the low density polymer matrix but the rate of migration of the biocide is considerably slowed through the high density polymer. Thus, the antimicrobial agents are substantially prevented from escaping into the surrounding environment, but rather, are trapped within a xe2x80x9cprotection zonexe2x80x9d immediately adjacent the conduit surface to provide extended protection against corrosion.

The present invention relates to an improved anti-corrosive material. Particularly, the present invention relates to a protective material for preventing microbiologically influenced corrosion in buried conduits. More particularly, the present invention relates to a multi-layered material used to encase buried conduits to prevent corrosion.
Buried conduits are ubiquitously used for carrying various materials, such as water, natural gas, oil, and sewage. A major problem with buried conduits comprised of metal or concrete with metal reinforcements is corrosion. The severity and rate of corrosion is dependent on the type of material comprising the conduit and the environment in which the conduit is buried. Insuring the longevity of buried conduits is an important part of the infrastructure in the United States and the world. Significant costs are involved in design, development, manufacture, and installation of water, gas, and sewage systems. Failure of these systems from conduit corrosion represents appreciable costs.
The control of corrosion of metals has been a quest of producers and consumers for the entire history of ferrous materials. Corrosion is typically understood to be the result of oxidation and/or galvanic processes. Historically, corrosion prevention has primarily addressed the reduction of oxygen component or control of galvanic action to prevent the occurrence of corrosion. Some typical corrosion prevention processes are painting or coating the metal to prevent oxygen from reaching the surface, volatile corrosive inhibitors that remove the available oxygen, and/or cathodic protection. Even after utilizing all the currently available mechanisms for the prevention of corrosion there are instances where unexplained corrosion occurs in buried metal pipes and conduits.
In the 1930""s, the mechanisms of Microbiologically Influenced Corrosion (xe2x80x9cMICxe2x80x9d) were proposed by Von Wolzen Kuhr to explain corrosion initiated or accelerated by microorganisms. Since that time, studies have shown the Von Wolzen Kuhr theory to be valid, and it has been established that a consortium of microorganisms contribute to many metal corrosion failures. These microorganisms, alone or more typically in combination, include as follows:
Sulphate-reducing bacteria including Desulfovibrio, Desulfobacter, and Desulformaculum. Sulphate-reducing bacteria are anaerobic and are the primary cause of Microbiologically Influenced Corrosion. Sulphate-reducing bacteria are associated with the reduction of sulphate under anaerobic conditions and an associated production of hydrogen sulfide, which creates an alkaline environment that can accelerate corrosion.
Iron-oxidizing bacteria including Gallionella, Sphaerotilus, Leptothrix, Clonothrix, and Crenothrix. Iron-oxiding bacteria are associated with the oxidization of various forms of iron and, in some cases, an associated production of ferric chloride and an acidic environment that can accelerate corrosion.
Sulfur-oxidizing bacteria including Thiobacillus, Thiodendron, Beggiatoa, and Sulfolobus. Sulfur-oxiding bacteria are aerobic bacteria that form sulphuric acid, which is corrosive to many metals, from the oxidation of sulphur or sulphur-bearing compounds.
Slime-forming bacteria including Pseudomonas, Escherichia, Flavobacterium, Aerobacter and Bacillus.
Susan Watkins Borenstein, Microbiologically Influence Corrosion Handbook ch. 2 (1994).
Hereto, no one has effectively addressed the elimination of the microbiologically influenced corrosion occurring in buried metal pipes and conduits. For example, ductile iron pipe (DIP) typically exhibits a low risk to severe corrosion compared to other metals; however, a rapid increase in the corrosion rate can be initiated by oxygenated water, tidal action, or specific soil types such as soils containing sulfides. Because of the high costs associated with removal and replacement of corroded conduits, the industry has expended substantial resources attempting to solve this problem.
Initially, conduits were covered with paint coatings, wraps, or other materials to separate the conduit surfaces from the environment. However, specialized coatings are either susceptible to deterioration by sulfate-reducing bacteria or are sophisticated to the point that they are no longer cost effective. Later, barrier films of polyethylene were used to protect DIP conduits. By insulating the exposed surfaces from soil, electrical currents, and oxygenated water, corrosion is usually prevented. However, due to improper installation, tears and punctures to the barrier film occurring during the installation and backfill process, free flow of water from tidal action, or soil or water becoming entrapped between the film and the conduit surface, actual corrosion still occurs in many cases. The industry has attempted to solve these problems by using more durable barrier films to encase the conduit surfaces, such as high density cross-laminated polyethylenes (HDCLPE). The superior impact strength, tear resistance, and tensile strength of HDCLPE has reduced some of the problems associated with the installation and backfill process; however, HDCLPE does not adequately address or control the problem of microbiologically influenced corrosion. Since there has not been an adequate alternative, present industry standards typically use either an 8 mil low density polyethylene (LDPE) film or a 4 mil HDCLPE film, a mil being equal to one thousandth of an inch (0.0254 millimeter), to wrap around the conduits for protection against corrosion.
Polyethylenes, as well as other plastic films, limit the free flow of water against the conduit surfaces, thereby reducing available oxygen. Any moisture that becomes trapped between the film and the conduit surface will eventually become deaerated. A problem arises where deaerated water levels are attained in the presence of the previously identified sulfate reducing bacteria. Many anaerobic bacteria, such as Desulfovibrio desulfuricans, thrive in certain fresh water, brackish water, sea water, sulfate soils, or warm soil conditions. These bacteria act as a catalyst to initiate or augment the rate of corrosion in an environment that is normally adverse to corrosion, and as previously noted are a primary cause of microbiologically influenced corrosion. Additionally, other types of bacteria are believed to play a part in corrosion propagation and it appears that bacteria are also responsible for degradation of the polyethylene film. A possible solution to this problem is to treat the materials used to encase the conduit with bactericides. However, most bactericides are topical and water soluble, thereby offering only initial protection that loses their effectiveness when used in buried systems exposed to wet conditions. Since conduits are buried for decades, this would not provide adequate long-term protection.
Another possible solution is to use certain volatile corrosion inhibitors (VCIs) which can be introduced either in contact or near the metal surface to eliminate or reduce the presence of corrosion. An example of a commonly used VCI is illustrated in U.S. Pat. No. 3,425,954. These VCIs can be used to prevent conditions from developing inside the film barrier which are favorable to corrosion. VCIs work at a micron level to passivate the surface of metal with a passive film, thus reducing the chemical reactivity of its surface. VCIs are normally used in kraft papers for short term protection of metal parts, as illustrated in U.S. Pat. No. 4,557,966; however, paper is not suitable to be buried. VCIs could be added to the polyethylene film, but the effectiveness will be shortened since the vapor tends to escape from the film, thus preventing extended protection. VCIs also lose their effectiveness when used in buried systems. An additional possible solution is the practice of isolating the system to prevent corrosion due to galvanic action; however this technique is ineffective against bacterial corrosion. However, currently available methods for controlling conduit corrosion do not address microbiologically influenced corrosion, or their application is technically complex and very expensive, or they are not suitable for buried conduits
From the foregoing it may be seen that hereto, no one has adequately addressed the elimination of the microbiologically influenced corrosion element for the long-term protection of buried conduits. A need exists for an improved anti-corrosive material for protecting conduits buried in conditions favorable to microbiologically influenced corrosion.
It is the object of the present invention to provide an improved anti-corrosive material which is superior to those presently used to protect buried conduits.
It is an additional object of the present invention to provide an improved anti-corrosive material that provides long term protection of buried conduit by preventing microbiologically influenced corrosion.
It is another object of the present invention to provide a material that contains an antimicrobial additive to prevent bacterial-induced or enhanced corrosion.
It is a further object of the present invention to provide a material that contains volatile corrosion inhibitors to prevent corrosion.
It is another object of the present invention to provide an anti-corrosive material comprising a conduit-contacting layer having an antimicrobial additive impregnated therein, incorporated into and dispersed throughout the conduit-contacting layer such that the antimicrobial additive can migrate within the conduit-contacting layer to contact the conduit surface and thereby prevent microbiologically influenced or enhanced corrosion therein.
It is another object of the present invention to provide a multi-layered, anti-corrosive material having a barrier layer adjacent the conduit-contacting layer that prevents the antimicrobial additive from penetrating the barrier layer and entering the surrounding environment.
It is still a further object of the present invention to provide a material which is co-extruded, calendered, or laminated into a multi-layered material comprising a conduit contacting layer having antimicrobial additives impregnated therein, incorporated into and dispersed throughout the conduit contacting layer such that the anti-corrosive agents can migrate within the conduit contacting layer to contact the conduit surface and prevent corrosion.
It is yet a further object of the present invention to provide a material which is co-extruded, calendered, or laminated into a multi-layered material further comprising a barrier layer adjacent the conduit contacting layer which prevents the anti-corrosive agents from penetrating the barrier layer and escaping into the surrounding environment.
These and other objects of the present invention are accomplished through the use of an improved anti-corrosive material used to protect buried conduits from corrosion. Incorporated into the improved anti-corrosive material are antimicrobial additives that effectively eliminate bacteria associated with microbiologically influenced corrosion. The additives can be blended with polyethylene raw materials in a manner that disperses the material throughout the product and be insoluble in aqueous conditions. Since the additive is designed as a contact agent, a requirement of manufacture is that proper dispersion and percent content be effected to generate the proper barrier against microbial growth. A test program was implemented to develop the proper polyethylene film manufacturing techniques that would yield proper protective characteristics. This product is a new cost effective anti-corrosive material used to protect buried conduits comprising ductile iron, steel, or concrete reinforced with steel by reducing or eliminating previously unexplained failures of buried conduits caused or accelerated by microbiologically influenced corrosion.
The anti-corrosive material is comprised of a conduit contacting layer of polyolefin having the anti-corrosive agents impregnated therein. The anti-corrosive agents, or antimicrobial additives, are incorporated into and dispersed throughout the conduit contacting layer such that the anti-corrosive agents can migrate within the conduit contacting layer to contact the conduit surface and prevent corrosion.
Another embodiment of the anti-corrosive material is a multi-layered co-extruded, calendered, or laminated polyolefin. The material has an outer layer, or environment contacting layer, preferably comprised of a low density polyethylene having characteristically strong tensile strength and elongation properties to provide conventional protection from soil, water, air, or other potentially damaging elements. The material has a center layer preferably comprised of a high density polyethylene having superior tensile strength to provide a high density barrier between the outer layer and an inner layer. The inner layer, or conduit contacting layer, is preferably comprised of a low density polyethylene impregnated with an antimicrobial additive such as a biocide or a volatile corrosion inhibitor (VCI), or both. The antimicrobial additive is incorporated into and dispersed throughout the conduit contacting layer for killing corrosion-inducing bacteria on the surface of the conduit. The antimicrobial agents are able to migrate through the low density polymer matrix but the rate of migration of the antimicrobial additive is considerably slowed through the high density polymer and the VCI is essentially unable to penetrate it. Thus, the antimicrobial agents are substantially prevented from escaping into the surrounding environment, but rather, are trapped within a xe2x80x9cprotection zonexe2x80x9d immediately adjacent the conduit surface to provide extended protection against corrosion.
The present invention is not limited to simply overcoming the deficiencies of the prior art but introduces enhanced technical advantages in corrosion protection that were not previously available for the long term protection of buried conduits while continuing to meet established industry standards.
These and other objects and advantages of the invention will become apparent from the following detailed description of the preferred embodiment of the invention.

Pipe wrap for preventing microbiologically influenced corrosion in buried conduits


A silver halide photographic light-sensitive material comprising a support having thereon at least one light-sensitive silver halide emulsion layer, wherein at least one hydrophilic colloidal layer containing said light-sensitive silver halide emulsion layer comprises the polymer latex stabilized by gelatin, and the outermost layer on the side containing said light-sensitive silver halide emulsion layer and/or the outermost layer on the other side comprises the anionic fluorine containing surfactant and/or cationic fluorine containing surfactant.

The present invention relates to a silver halide photographic light-sensitive material, and specifically, a silver halide photographic light-sensitive material with excellent dimensional stability, free from stickiness and deterioration of sensitivity after storage.
Gelatin has high swellability and gelation performance and is crosslinked easily by various hardeners. It is generally used as a binder for silver halide photographic light-sensitive material. Gelatin is an excellent binder to coat, by adjusting the physical properties of a coating solution, uniformly a wide area of such materials unsuitable to high temperature as light-sensitive silver halide.
The silver halide grains change into extremely hard metallic silver when the gelatin layer absorbs water and swells sufficiently during development of the silver halide photographic light-sensitive material. As a result, the emulsion layer does not recover after drying and the size of the light-sensitive material before and after processing is different.
Therefore, there is a known technique of improving the physical properties of light-sensitive materials by including polymer latex in the silver halide emulsion layer and backing layer.
Such a technique is described, for instance, in Research Disclosure No. 19951, Japanese Patent Examined Publication Nos. 39-4272, 39-17702 and 43-13482, U.S. Pat. Nos. 2376005, 2763625, 2772166, 2852386, 2853457 and 3397988. Additionally, Japanese Patent L.O.P. Nos. 59-38741, 61-296348, 61-284756 and 61-285446 disclose the method of making fine oil particles of paraffin and vinyl polymer contained in. However, conventional technic is not sufficient and needs improvement. When a large amount is added in the gelatin, the latex flocculates and any further additional amount shows no effect. It is especially required to improve the variation of dimensional difference before and after processing, depending on environmental humidity.
Moreover, a large amount of latex added in the gelatin causes sticking and deterioration of sensitivity after long preservation. While Japanese Patent Examined Publication No. 58-9408 discloses the method of adding a fluorine type surfactant to improve such stickiness, a comprehensive solution, including improvement of dimensional stability, is demanded.

Silver halide photographic light-sensitive material


A display panel comprising a substrate, a plurality of first electrodes formed on a surface of the substrate and extending from a first portion of the substrate, and a plurality of second electrodes formed on the surface of the substrate and extending from a second portion of the substrate. The first electrodes and the second electrodes are alternately arranged in rows. The first electrodes include a shorted segment in the first portion of the substrate that couples ends of the first electrodes. The shorted segment includes an electrode formation region and electrode void regions. The electrode void regions are formed in a predetermined pattern in the electrode formation region.

1. Field of the Invention
The present invention relates to a plasma display panel (PDP). More particularly, the present invention relates to a PDP in which an electrode shorted segment has various configurations enabling its formation at a substantially uniform thickness.
2. Discussion of the Related Art
A PDP displays images through excitation of phosphors by plasma discharge. Specifically, an applied voltage between two electrodes in a discharge region of the PDP generates a plasma discharge between them. Ultraviolet rays generated during the plasma discharge excite phosphor layers to display images. The different types of PDPs include alternating current (AC) PDPs, direct current (DC) PDPs, and hybrid PDPs.
FIG. 5 shows a partial exploded perspective view of a conventional PDP 100. The conventional AC-PDP 100 includes a lower substrate 101 and an upper substrate 102 provided opposing one another with a predetermined gap therebetween. Address electrodes 103 are formed on a surface of the lower substrate 101 opposing the upper substrate 102. The address electrodes 103 are formed in a stripe pattern substantially along direction Y. A dielectric layer 105 is formed on the lower substrate 101 covering the address electrodes 103, and a plurality of barrier ribs 107 are formed on the dielectric layer 105. The barrier ribs 107 function to maintain the panel gap and prevent crosstalk between discharge cells. A phosphor layer 108 is formed between each adjacent pair of the barrier ribs 107 covering the dielectric layer 105 and side walls of the barrier ribs 107.
Formed on a surface of the upper substrate 102 opposing the lower substrate 101 are display electrodes 104. The display electrodes 104 are formed substantially along direction X, that is, substantially along a direction perpendicular to the address electrodes 103. The display electrodes 104 are formed such that a pair of the same is positioned over each of the discharge cells defined by the barrier ribs 107. A dielectric layer 106 and a protection layer 109 are formed on the upper substrate 102 covering the display electrodes 104.
In the conventional PDP with this configuration, each pair of the display electrodes 104 is comprised of a sustain electrode and a scanning electrode. A drive voltage is received from the address electrodes 103 and the scanning electrodes to thereby effect address discharge therebetween and form a wall charge on the dielectric layer 105. Sustain discharge is effected between the sustain electrodes and the scanning electrodes in the discharge cell selected by the address discharge by a signal that is alternatingly supplied to the sustain electrodes and the scanning electrodes.
Accordingly, a discharge gas filled in the discharge region where the discharge cells are formed is excited such that the discharge gas generates ultraviolet rays. Visible light is generated by the excitation of the phosphors of the phosphor layers by the ultraviolet rays, thereby resulting in the formation of images.
A silver (Ag) paste is typically used to form sustain electrodes and scanning electrodes, as well as address electrodes. A screen printing or photolithography process is typically used to form these electrodes since they may be formed at widths of 70 to 80 μm. Lift-off and thin film methods are other possible alternatives. However, these conventional methods for forming electrodes may not be suitable when manufacturing large screen PDPs. Therefore, an offset printing process method is being explored, which may be used to precisely and stably print electrodes.
FIG. 6 is a schematic sectional view showing sequential steps of the offset printing process.
The offset printing process generally involves the main steps of paste deposition and doctoring, step A, an off process, step B, and a set process, step C. Step A involves depositing a paste 23 on an intaglio 21 having a plurality of indented grooves. A doctor blade 22 is scraped along the intaglio 21 in a direction (a doctoring direction) to remove excess paste 23, leaving paste 23 in the indented grooves. Next, in step B, a blanket 24 (partially shown), which may be made of silicone rubber and cylindrical in shape, is used to remove the paste from the indented grooves of the intaglio 21. Finally, in step C, the blanket 24 and the paste 23 are pressed against a substrate 25 to transfer the paste 23 onto the substrate 25.
However, the offset printing process may have drawbacks. Although this process may effectively form small and narrow electrode portions, when forming large electrode portions, such as terminal electrodes, problems may be encountered during the doctoring process since that process may be best suited for forming long and narrow electrode sections that extend along the doctoring direction. Hence, large electrode portions formed by the offset printing process may not meet desired quality standards.
FIG. 7 and FIG. 8 show problems with the conventional offset printing process just described.
FIG. 7 is a partial perspective view showing an intaglio 21 with a paste 23 formed thereon following an offset printing process. A doctor blade (not shown) was run across the intaglio 21 in a doctoring direction, as indicated in FIG. 7, to remove excess portions of the previously deposited paste 23.
FIG. 8 is a schematic sectional view showing the sequential steps involved in the offset printing process when forming shorted segments of sustain electrodes. The views are taken along line I-I of FIG. 7.
In step A of FIG. 8, after depositing the paste 23 on the intaglio 21, the doctor blade 22 is used to remove the overflow paste. At the beginning of the doctoring process, the remaining paste 23 is substantially coplanar with an upper surface of the intaglio 21. However, as shown in step B, as the doctor blade 22 progresses along the doctoring direction, it may enter a region where it no longer contacts the intaglio's upper surface, and the doctor blade 22 may descend into the intaglio's indented groove. This situation may continue as the doctor blade 22 further progresses along the doctoring direction, as shown in step C. At the end of doctoring process, as shown in step D, a middle portion of the paste 23 may be concave.
When transferring the paste 23 with the concave middle portion onto a substrate using a blanket to form sustain electrode shorted segments, the shorted segments may not be uniformly thick. The end result is that discharge characteristics of the PDP may be adversely affected by the uneven thickness of the shorted segments.

Plasma display panel having electrode shorted segment with electrode void regions formed therein


A method and an apparatus for searching sentences by analyzing words. The method arranges the expressive conceptual words of words in a sentence data base to establish a corresponding index table of conceptual words and sentences. Next, the conceptual words of words are arranged, namely, by performing the conceptual distinguishing of words to establish a corresponding index table of words and conceptual words. After a user inputs a word, many expressive conceptual words of the word are searched through the corresponding index table of words and conceptual words. After the user inputs an option signal to select an expectant conceptual word of the word, appropriate sentences are searched through the corresponding index table of conceptual words and sentences and a sentence data base. Using the above method, the present invention can effectively raise the ratio of hitting the target for searching an appropriate sentence, and increase the speed of searching sentence.

1. Field of the Invention
The present invention relates to an apparatus and a method for searching sentences, and more particularly to an apparatus and a method of correctly analyzing a word and rapidly searching sentences.
2. Description of the Prior Art
The conventional method for searching sentences generally adopts an index table that is created using the corresponding relation of words and sentences according to every word in all sentences. After inputting a word, a sentence corresponding to the word is searched using this index table. This searching method usually finds a lot of unnecessary sentences, when the inputting word has multi-explanation (i.g., multi-conceptual word or multi-meaning).Therefore, the method lacks correctness and real effect. Generally speaking, when a word is input, a method of searching sentences by a computer is described according to some basic steps as follow:
1. Inputting a Chinese word, an English word, or the other language word to a computer.
2. Searching a sentence corresponding to the inputting word by an index table which is created using the corresponding relation of words and sentences.
Because a word in different sentences usually has multi-conceptual word in every language, a sentence is searched by a user that is possible not what the user really wants. For an example of a user inputting a word "Miss" to find a sentence expressing the meaning of giving thought to (a person), the user will obtain the result of searching sentence as follow:
"All right, I won't miss it for anything"
The outputting result will be improper.
Additionally, because a word with the same meaning can be replaced with a lot of similar meaning words, the other proper sentences having the similar meaning expressed using different words are always lost while searching a proper sentence. For example, a user inputs a word "tolerance" to search a sentence, and it is impossible that the user can search a sentence as follow:
"He can not brook being interfered with."
Accordingly, the conventional method for searching sentences can not effectively search a sentence which the user really wants to express the meaning of the inputting word, and it also can't have the function of searching a sentence having the similar conceptual word which is expressed with a plurality of similar meaning words. Therefore, the conventional searching method limits the development of the other searching functions.

Method and apparatus for searching sentences by analyzing words


A latch circuit receives complementary signals and consists of an nMOS transistor whose source is connected to an input terminal of the latch circuit and a series-connected circuit consisting of first and second pMOS transistors arranged between and connected to a drain terminal of the nMOS transistor and a high-potential power supply. The complementary signals are a first signal and a second signal that is an inversion of the first signal. Each of the signals has a pulse characteristic that rising time is longer than falling time. The latch circuit latches a quick fall by passing the first signal through the nMOS transistor. On the other hand, the latch circuit latches a slow rise by turning on the second pMOS transistor in response to a fall in the second signal.

1. Field of the Invention
The present invention relates to a latch circuit for latching complementary signals that rise and fall oppositely to each other and an arithmetic unit employing the latch circuit.
2. Description of the Prior Art
FIG. 1 shows a latch circuit employing clock-controlled inverters according to a prior art, and FIG. 2 shows a latch circuit employing CMOS transmission gates according to another prior art.
In FIG. 1, the latch circuit consists of a clock-controlled inverter 11, an inverter 12, a clock-inverter 13, and an inverter 14. The inverter 11 is connected to an input terminal D. The inverter 12 has an input terminal connected to an output terminal of the inverter 11. The inverter 13 has an input terminal connected to an output terminal of the inverter 12 and an output terminal connected to the output terminal of the inverter 11. The inverter 14 has an input terminal connected to the output terminals of the inverters 11 and 13. The inverter 11 inverts and transmits an input signal when a clock signal .phi. is low level and an inverted clock signal .phi. is high level. The inverted clock signal .phi. is an inversion of the clock signal .phi..
The clock-controlled inverter 13 inverts and transmits the output of the inverter 12 when the clock signal .phi. is high level and the inverted clock signal .phi. is low level.
In FIG. 2, the latch circuit consists of CMOS transmission gates 25 and 28 and inverters 12, 14, and 27. The gate 25 is connected to an input terminal D. The inverter 12 has an input terminal connected to an output terminal of the transmission gate 25. The inverter 27 has an input terminal connected to an output terminal of the inverter 12. The transmission gate 28 has an input terminal connected to an output terminal of the inverter 27 and an output terminal connected to the output terminal of the transmission gate 25. The inverter 14 has an input terminal connected to the output terminals of the transmission gates 25 and 28. The transmission gate 25 transmits an input signal when a clock signal .phi. is low level and an inverted clock signal .phi. is high level. The transmission gate 28 transmits a signal when the clock signal .phi. is high level and the inverted clock signal .phi. is low level.
In the latch circuit shown in FIG. 1, the clock-controlled inverter 11 arranged in a first stage becomes conductive if the clock signal .phi. is low level and the inverted clock signal .phi. is high level, to fetch an input signal supplied to the input terminal D and transfer the same to an output terminal Q. In the latch circuit shown in FIG. 2, the CMOS transmission gate 25 arranged in a first stage becomes conductive if the clock signal .phi. is low level and the inverted clock signal .phi. is high level, to fetch an input signal supplied to the input terminal D and transfer the inverted signal D to an output terminal Q. Thereafter, when the clock signal .phi. changes to high level and the inverted clock signal .phi. to low level, the inverter 11 or the transmission gate 25 is turned off, while closing a circuit for holding the current output, i.e., the fetched input signal, which is, therefore, not affected by any change in an input signal. The current output is held as it is until the clock signal .phi. again changes to low level and the inverted clock signal .phi. to high level.
These latch circuits may receive, for example, output signals of a selector circuit of FIG. 3. The selector circuit has input terminals D1 and D2 for receiving input signals D1 and D2 and input terminals D1 and D2 for receiving inverted input signals D1 and D2. The selector circuit consists of nMOS transmission gates 31 to 34. The transmission gate 31 has a source terminal connected to the input terminal D1 and a gate terminal to receive a control signal A. The transmission gate 32 has a source terminal connected to the input terminal D2, a gate terminal to receive an inverted control signal A, which is an inversion of the control signal A, and a drain terminal connected to a drain terminal of the gate 31. The transmission gate 33 has a source terminal connected to the input terminal D1 and a gate terminal to receive the control signal A. The transmission gate 34 has a source terminal connected to the input terminal D2, a gate terminal to receive the inverted control signal A, and a drain terminal connected to a drain terminal of the gate 33. The selector circuit further has pMOS transistors 35 and 36. The transistor 35 has a gate terminal connected to the drain terminals of the transmission gates 33 and 34, a source terminal connected to a power supply for supplying a high level potential, and a drain terminal connected to an output terminal OUT. The transistor 36 has a gate terminal connected to the drain terminals of the transmission gates 31 and 32, a source terminal connected to the power supply, and a drain terminal connected to an output terminal OUT. The output terminal OUT provides a signal which is an inversion of an output signal provided by the output terminal OUT.
The operation of the selector circuit of FIG. 3 will be explained. If the control signal A is high level and the inverted control signal A is low level, the transmission gates 31 and 33 are conductive, and the transmission gates 32 and 34 are in the OFF state. As a result, the input terminals D2 and D2 are disconnected from the output terminals OUT and OUT and become irrelevant to them. Under this state, if the input terminal D1 is high level, the drain terminal of the transmission gate 31 provides a signal which is equal to the high level potential minus the gate threshold voltage Vth thereof. On the other hand, the input terminal D1 is low level, and therefore, the drain terminal of the transmission gate 33 quickly transmits the low level signal to the output terminal OUT. When the output terminal OUT becomes low level, the transistor 35 becomes conductive, to connect the drain terminal of the gate 31, i.e., the output terminal OUT to the power supply. As a result, the output terminal OUT receives the high level potential of the power supply compensating voltage drop due to the gate threshold voltage Vth.
If the input terminal D1 is low level, the input terminal D1 is high level, to achieve an operation opposite to the one mentioned above. Namely, the drain terminal of the transmission gate 31 quickly transmits the low level signal to the output terminal OUT, and the transmission gate 33 transmits a signal equal to the high level minus the gate threshold voltage Vth. The output terminal OUT is low level to turn on the transistor 36 to connect the power supply to the output terminal OUT. As a result, the output terminal OUT correctly provides the high level potential compensating the voltage drop due to the gate threshold voltage Vth.
If the control signal A is low level and the inverted control signal A is high level, the transmission gates 32 and 34 become conductive contrary to the above-mentioned case, and the pMOS transistors 35 and 36 help to provide a high-level output.
In the above operation, the high level is accomplished with aids of the transistor 35 or 36, while the low level is transmitted directly to any one of the output terminals OUT and OUT. Hence the transition to low level is always faster than the transition to the high level. Namely, as shown in the timing chart of FIG. 4, the completion of a rise in the output OUT is always behind the completion of a corresponding fall in the output OUT, and the completion of a rise in the output OUT is always behind the completion of a corresponding fall in the output OUT.
As explained above, the selector circuit of FIG. 3 provides complementary signals having the relationship of FIG. 4. It is usual that one of corresponding rise and fall in complementary output pulses is behind the other. If the output OUT of the complementary outputs of FIG. 4 is connected to the input terminal D of any one of the latch circuits of FIGS. 1 and 2, the latch circuit operates at high speed when the output OUT falls and slowly when the output OUT rises. To latch such signal having different rising time and falling time, the latch circuit must adjust itself to the slower timing. This hinders a high-speed latching operation even if the latch circuit is capable of speedily operating on one of the rise and fall of an input signal.

Latch circuit and arithmetic unit having the same


A device and related method for coupling segments of an extended local area network (LAN) in such a way that message traffic employing inter-network protocols such as TCP/IP will be handled without the difficulties usually associated with bridges, and without the complexity and expense of full IP router capability. The device operates like a bridge for non-TCP/IP traffic. For TCP/IP traffic it operates in a bridge-like manner but maintains a database associating extended LAN segment addresses with port numbers in the device, so that packets can be automatically forwarded over a spanning tree connecting the network segments. A host computer in any network segment can address others in different network segments of the extended LAN as though all were in a single LAN. The device of the invention functions to block the flow of ARP messages and to generate ARP replies that render the device of the invention transparent to hosts within the extended LAN. The device is also transparent to true IP routers, which may still be used to effect communication with points outside the extended LAN.

This invention relates generally to local area networks (LANs) of computers and, more particularly, to multiple LANs that are interconnected by bridges and routers. More specifically, the invention is concerned with a problem that arises in interconnected networks using a set of protocols generally known as TCP/IP. TCP stands for Transmission Control Protocol, and IP is Internet Protocol. The following background material introduces various computer network concepts and definitions. Those familiar with computer networks and TCP/IP may wish to skip to the subsection headed "The Problem."


In a memory device employing a memory sense amplifier of the grounded-gate type, by putting a word line in an active state from a point of time in a precharge period, a high-speed operation can be implemented with no increase in access time due to a lagging change of the electric potential at the gate of the grounded-gate transistor because of an effect of a wire resistance. In addition, by lowering the electric-potential of the gate of the grounded-gate transistor using a current-mirror circuit, low power consumption can be realized.

1. Field of the Invention
The present invention relates to a memory device and, in particular, to a sense amplifier employed in a semiconductor memory.
2. Description of the Prior Art
FIG. 8 is a circuit diagram showing the configuration of a memory device employing a conventional memory sense amplifier of the grounded-gate type. In the drawing, numerals T1 to T6 and T18 and T19 each denote an N-channel transistor, numerals T21 to T25 each denote a P-channel transistor, numerals I1 and I2 are each an inverter, numeral SL denotes a selector and numeral MB3 is a memory block.
FIG. 2 is a circuit diagram showing the configuration of the selector SL. In the drawing, numerals G30 to G33 each denote a NAND gate, numerals 130 to 135 are each an inverter, numerals T30 to T33 are a group of N-channel transistors having the same channel length and the same channel width and numerals T34 to T37 are another group of N-channel transistors having the same channel length and the same channel width.
FIG. 9 is a circuit diagram showing the configuration of the NOR-type memory block MB3. In the drawing, numerals G60 to G63 each denote an AND gate, numerals I40 to I41 are each an inverter, numerals C1 to C10 are memory-cell transistors having the same channel length and the same channel width, numerals C11 to C16 are other memory-cell transistors having the same channel length and the same channel width and numerals R1 to R12 are wire resistances of word lines W0 to W3. The memory-cell transistors C1 to C16 are each an N-channel transistor forming a memory cell. It should be noted that the memory-cell transistors C11 to C16 each have a threshold voltage equal to or higher than 5V so that, even with the gate voltage thereof varied in the range 0 to 5V, the drain current is smaller than 1 nA and can be said to be almost not flowing.
The operation of the memory device is explained by referring to FIGS. 2, 8 and 9 as follows.
The electric potential VDD of the power supply of the conventional memory device is about 5 V. The memory device is operative when a chip-select signal CS of the memory device shown in FIG. 8 is connected to the electric potential of the ground GND which is referred to hereafter as an "L" level. If the chip-select signal CS is connected to the electric potential VDD of the power supply which is referred to hereafter as an "H" level, on the other hand, the memory device is put in a deselected state and thus not operative. When the chip-select signal CS is put at the "L" level, the P-channel transistor T25 is turned on, pulling up the electric potentials of the sources of the P-channel transistors T24, T23 and T21 connected to the P-channel transistor T25 to the electric potential VDD which is about 5 V. The P-channel transistor T24 and the N-channel transistors T18 and T19 work as a source of voltage supplying an electric potential to the gate of the N-channel transistor T1. To put it in detail, when a current of about 200 .mu.A flows from the drain of the P-channel transistor T24 to the N-channel transistors T18 and T19, the electric potential of the gate of the N-channel transistor T1, that is, the electric potential of a node N3, is about 2.5 V.
On the other hand, the P-channel transistor T23 and the N-channel transistors T4 to T6 work as a source of voltage supplying an electric potential to the gate of the P-channel transistor T21 which serves as a source of current supplying a current to a node N1. The N-channel transistor T4 has the same channel length and the same channel width as the N-channel transistor T1. By the same token, the N-channel transistor T5 has the same channel length and the same channel width as the N-channel transistor T30 employed in the selector SL. Likewise, the N-channel transistor T6 has the same channel length and the same channel width as the memory-cell transistor C1. On the other hand, the P-channel transistor T23 has the same channel length as the P-channel transistor T21 but the channel width of the former is five times that of the latter.
As a result, affected by the current-mirror effect, the drain current of the P-channel transistor T21 is about 150 .mu.A which is about 1/5 of the drain current (referred to hereafter as a memory-cell drain current) of, for example, the memory-cell transistor C1 with the gate voltage thereof set at about 5 V. Since the N-channel transistor T1 is a grounded-gate amplifier, the electric potential at the node N1 is changed in accordance with the magnitude of a current drawn from a node S. The inverter I1 outputs an "L" or "H" level to a node N2 depending upon whether or not the electric potential at the node N1 is higher than a predetermined value. During a precharge period (a period in which the signal level of a clock P1 signal is set at "H"), the inverter I2 and the P-channel transistor T22 precharge one of bit lines B0 to B3 connected to the node S through the nodes N1 and S and the selector SL. The N-channel transistors T2 and T3 work as a positive feedback circuit which draws a current from the node N1, accelerating the change in electric potential when the electric potential at the node N2 changes from "L" to "H".
The inverters I30 and I31 and the NAND gates G30 to G33 employed in the selector SL shown in FIG. 2 constitute an ordinary two-to-four decoder. Depending upon the combination of the "H" or "L" levels of two address input signals A1 and A0, the output of one of the four NAND gates G30 to G33 is reset to the "L" level while the remaining three outputs are all set at the "H" level. The inverters I32 to I35 and the N-channel transistors T30 to T33 couple one of the bit lines B0 to B3 which is associated with the NAND gate reset at the "L" level to the node S. The bit line B0, B1, B2 or B3 coupled to the node S is referred to hereafter as a selected bit line. At that time, the N-channel transistors T34 to T37 reset the electric potentials of the bit lines other than the selected bit line at the ground level, that is, at 0 V.
Assume, for example, that the levels of the address input signals A1 and A0 are set at "H" and reset at "L" respectively. In this case, the output of the NAND gate G32 employed in the selector SL is reset at the "L" level which is inverted by the inverter I34 to an "H" level. As a result, the gate input of the N-channel transistor T32 is set at the "H" level, turning on the N-channel transistor T32. In this state, the bit line B2 is coupled to the node S by the conduction of the N-channel transistor T32. On the other hand, the electric potentials of the bit lines B0, B1 and B3 are pulled down to 0 V. This is because the electric potentials of the gates of the N-channel transistors T34, T35 and T37 are all set at the "H" level, turning on all the N-channel transistors T34, T35 and T37 which, in turn, couple the bit lines B0, B1 and B3 respectively to the electric potential GND of the ground.
By the same token, the inverters I40 and I41 and the AND gates G60 to G63 employed in the memory block MB3 shown in FIG. 9 constitute an ordinary two-to-four decoder with the outputs of the AND gates G60 to G63 connected to the word lines W0 to W3 respectively. Since the gates G60 to G63 are AND gates, however, one of the word lines W0 to W3 specified by the address input signals A3 and A2 is set to the "H" level while the other word lines are reset at the "L" level. The word line W0, W1, W2 or W3 specified by the address input signals A3 and A2 is referred to hereafter as a selected word line. It should be noted that, since the AND gates G60 to G63 input a clock signal P2 as a strobe signal, it is only during the "H"-level period of the clock signal P2 that the selected word line is set at the "H" level. Since the memory-cell transistors C1 to C10 turn on when the word line connected to their gate is set to the "H" level, they draw a memory-cell current from the bit line connected to the drain thereof. On the other hand, the threshold voltage of the memory-cell transistors C11 to C16 is higher than 5 V. As a result, there is no effect on the memory-cell transistors C11 to C16 even if the electric potentials of the word lines connected to their gates are changed.
Next, the operation of the memory device is explained by referring to timing charts shown in FIG. 10.
The explanation begins with a first example of a case in which the levels of the address input signals A3, A2, A1 and A0 are set at "L", "H", "L" and "L", respectively. In this case, the output of the NAND gate G30 employed in the selector SL shown in FIG. 2 is reset at the "L" level which is inverted by the inverter 132 to an "H" level. As a result, the gate input of the N-channel transistor T30 is set at the "H" level, turning on the N-channel transistor T30. In this state, the bit line B0 is the selected bit line connected to the node S by the conduction of the N-channel transistor T30. On the other hand, the electric potential of the AND gate G61 employed in the memory block MB3 shown in FIG. 9 is set at the "H" level, selecting the word line W1 as a selected word line.
As a result, the memory-cell transistor C11 is selected.
First of all, the chip-select signal CS is reset to the "L" level and the address input signals A0 to A3 are received. At the same time, the level of the clock signal P1 changes from "L" to "H". When the chip-select signal CS of the memory device shown in FIG. 8 is reset to the "L" level, the P-channel transistor T25 is turned on, causing the electric potentials of the node N3 and a node N4 to rise to a predetermined value. The selector SL selects the bit line B0 as described above, coupling the bit line B0 to the node S. Since the level of the clock signal P2 in the memory block MB3 is "L", no operation affecting bit lines is carried out.
In this state, the level "H" of the clock signal P1 turns on the P-channel transistor T22, charging up the node N1 toward the 5 V electric potential VDD of the power supply. At the same time, the electric potentials of the node S and the bit line B0 are also charged up to about 1.5 V through the N-channel transistor T1. As a result, the output of the inverter I1, that is, the electric potential of the node N2, is reset to the "L" level. Then, after the bit line B0 has gotten in an all but steady state, the level of the clock signal P1 becomes "L". The period up to this point of time is referred to a precharge period.
As the level of the clock signal P1 turns to "L", causing the P-channel transistor T22 to no longer supply a current, the electric potentials of the nodes N1 and S as well as the bit line B0 slightly decrease. However, the electric potentials decrease only by an amount small enough not to have an effect on the output of the inverter I1. Later on, the drain current of the P-channel transistor T21 causes the electric potentials of the nodes N1 and S as well as the bit line B0 to rise little by little.
Next, the level of the clock signal P2 turns to "H". As a result, the level of the electric potential of the word line W1 changes from "L" to "H". Since the threshold voltage of the gate of the N-channel transistor serving as the memory-cell transistor C11 is higher than 5 V, however, the memory-cell transistor C11 is not turned on, having all but no effect on the bit line B0. Thus, the electric potentials of the node S connected to the bit line B0 and the node N1 do not change and the electric potential of the node N2 remains at the "L" level as it is. As a result, "L" information is read out from the memory device.
The explanation continues to a next example of a case in which the levels of the address input signals A3, A2, A1 and A0 are all reset at "L". In this case, the output of the NAND gate G30 employed in the selector SL is reset at the "L" level which is inverted by the inverter 132 to an "H" level. As a result, the gate input of the N-channel transistor T30 is set at the "H" level, turning on the N-channel transistor T30. In this state, the bit line B0 is the selected bit line coupled to the node S by the conduction of the N-channel transistor T30. On the other hand, the electric potential of only the AND gate G60 employed in the memory block MB3 is set at the "H" level, selecting the word line W0 as a selected word line. As a result, the memory-cell transistor C3 is selected. Also in this case, operations till the level of the clock signal P2 turns to "H" are the same as the first example described above. As the level of the clock signal P2 turns to "H", the output of the AND gate G60 and the electric potential of the word line W0 turn to the "H" level. As a result, the gate of the N-channel transistor serving as the memory-cell transistor C3 is raised, turning on the memory-cell transistor C3 which draws a memory-cell current from the bit line B0.
Since the magnitude of this current is five times that of the drain current of the P-channel transistor T21, the electric potential of the node N1 gradually decreases. The electric potentials of the node S and the bit line B0 also decrease but, since the capacitance of the bit line B0 is much larger than that of the node N1, the drop in electric potential on the bit line B0 is small. When the electric potential of the node N1 becomes equal to or lower than a predetermined value, the level of the output of the inverter I1 changes from "L" to "H". In this state, since the N-channel transistor T3 is turned on at a point of time the level of the clock signal P1 turns to "L", the N-channel transistor T2 is turned on, thus drawing a current much larger than the memory-cell current from the node N1. As a result, the drop of the electric potential of the node N1 is accelerated and the rise of the electric potential of the node N2 from "L" to "H" is also accelerated. Thus, "H" information is read out from the memory device.
The following is description of an example of a case in which the levels of the address input signals A3, A2, A1 and A0 are set at "L", "L", "H" and "H", respectively. In this case, using the same reasoning as those of the two examples described above, the selected bit line and the selected word line are found to be B3 and W0 respectively, selecting the memory-cell transistor C10. The operations in this case are all but the same as the case described above in which the memory-cell transistor C3 is selected except that the selected bit line is now B3. In this case, however, due to the resistances of wire resistors R4, R8 and R12 in conjunction with the gate capacitances of the memory-cell transistors C5, C15 and C10, the timing with which the electric potential of the gate of the memory-cell transistor C10 rises much lags behind the word line W0. As a result, the timing with which the electric potentials of the bit line B3 and the nodes S and N1 decrease lags as well and, in its turn, the change of the electric potential of the node N2 also lags as shown in the drawing. As a result, "H" information is read out from the memory device but the time it takes to read the information, that is, the access time, is longer than that of the previous example.


Aspects described herein provide structures for a force sensor, and force sensors using such structures, which are compact and easy to manufacture, for example by 3D printing. In particular the structures comprise a pair of stacked ring sensor elements, the ring sensor elements in turn being formed by upper and lower ring elements joined together at points around the circumference thereof by resiliently mounted connection bars. The connection bars may extend in the same plane as the rings, in which case sensitivity to torque about the axis of the rings is much reduced, such that a five-axis sensor is effectively obtained, or the connection bars may extend obliquely between the upper and lower rings of each sensor element, such that they have a directional component in the direction of the axis of the rings (the rings of each element being co-axially stacked). In this second case application of a torque about the ring axis causes the oblique connection bars to either increase or decrease their directional component in the axial direction, thus providing sensitivity to torque about the axis, and providing a compact six axis sensor.

Multi-axis force sensors that measure multiple degrees of freedom (DoF) are known already, but often take complicated and expensive forms. In a three dimensional Cartesian co-ordinate space there are up to six degrees of freedom that can be measured, being linear force F in each of the x, y, and z directions (i.e. Fx, Fy, and Fz), and also turning moment M about each of the x, y, and z axes (i.e. Mx, My, and Mz). In order to measure all six degrees of freedom previously, it has been necessary to combine multiple 2 or 3 DoF sensors together, usually by having to over-provision the number of sensors, such that overall cost of the resulting sensor is high.
For example, Optoforce, of Budapest, Hungary, provide a three-axis force sensor that uses one LED and four photo diodes to measure three force and torque components (two moments Mx and My and one axial force Fz). To measure 6-axis force/torque components (Fx, Fy, Fz Mx, My, Mz), three or four units of the three-axis force/torque sensor are currently being combined. For this reason, the six-axis sensor's overall size is bigger (50.0×50.0×25.0 mm3) than the leading commercialised six-axis force/torque sensor available (ATI Industrial Automation: F/T Sensor Nano17 (strain gauges based technology), Φ17×14.5 mm3). Despite the Optoforce sensor's brand name of 'three-axis force sensor', it cannot measure three-axis pure force components (Fx, Fy, Fz), but force and moments. The three-axis force components can be accurately measured only whilst external force is applied around the centre of the top on the semi-sphere surface.
As another example, the Minebea Co., Ltd of Japan supply a 6-axial force sensor for measuring x- and y-directional displacements. The 6-axis sensor comprises three sets of the 3-axial displacement-measuring instruments arranged in 120° rotary symmetric positions. Each 3 axis sensor comprises a light source being an infra-red high bright LED (the product of Stanley Electric Corp., Model BN-401) with a 1.0 mm thick pinhole having the diameter of 0.6 mm, and a photo sensor having a square shaped silicon PIN photodiode having 2.5 mm sides divided into quadrant (the product of Moririka Co., Model MI-33H4D). Light emitted from the source is diffused at passing the pinhole, and the optical sensor unit can then measure minute displacements not only in x and y directions but also in the z-direction. The 3-axis force sensor makes use of this effect, and the combination of three of the three-axis force sensors arranged in a circle 120 degrees apart can measure 6-axis force/torque components. However, again, more than two three axis units (in this case three) are required in order to measure six axes.
In view of the above, there is still a need for a lower cost multiple axis sensor that is able to measure greater than 3 degrees of freedom.