The lens of the present invention relates to multifocal spectacle lenses, including bifocal and trifocal lenses, with improved cosmetic appearance, optical performance and wide visual field. The lens comprises a plurality of axially layered and bonded lens sections of continuous curvature at least one of which has a changing refractive index incorporating a refractive index blend area oriented transverse to a meridian of the lens. The blend eliminates visibility of the joining area of adjacent portions of generally constant refractive index and the abrupt magnification shift and image jump typical of segmented multifocal lenses. The areas of generally constant refractive index provide the refractive powers for corresponding discrete vision portions of the lens. The other layer(s) of the lens incorporates a constant or similarly changing refractive index.

Multifocal spectacle lenses are visual aids used in the management of presbyopia, the condition wherein the accommodative function of the eye is partially or fully lost. The Vision Council of America defines a multifocal as a 'lens designed to provide correction for two or more discrete distances'. As such Bifocal and trifocal lenses are multifocal lenses and are distinguished from a progressive addition lens, which is 'designed to provide correction for more than one viewing distance in which the power changes continuously rather than discretely'. The first multifocal lens was the original bifocal lens invented by Benjamin Franklin in 1784. Trifocal lenses were later introduced by John Hawkins in 1826. A bifocal lens typically has one power correction for distance vision and one for near vision, while a trifocal lens typically has one power for distance vision, one for intermediate vision and one for near vision, although there are exceptions to this. Some multifocal lenses are task specific and have a refractive power other than that for distance vision in the upper portion of the lens, or are reversed, with the add power segment in the upper portion and distance vision correction in the lower portion. A quadrafocal lens may take the form of trifocal lens with an added top bifocal segment. Similarly, a 'double D' bifocal lens has a 2nd bifocal segment in the upper portion of the lens.
Bifocal segments can have one of several shapes variously termed flat top, curved top, round, rectangular, and 'Executive'. Trifocals are commonly available in flat top and 'Executive' styles. Like bifocals, trifocals segments are available in many sizes and heights. A flat top design is the most common type of bifocal. Segment sizes range from 25 through 40 mm with 28 mm being the most common segment. The curved top bifocal lens is similar to the flat top in general shape, but the top of the segment is curved. The round segment of the 'Kryptok' bifocal lens is less noticeable than the curved top bifocal segment. The near vision portion of an 'Executive' bifocal lens comprises the entire bottom section of the spectacle lens, providing the largest reading area of all bifocal lenses. In this respect it is most like the original Benjamin Franklin bifocal lens, and is most useful for extended near work requiring a large visual field. Less common today is the Ultex design wherein the segment has a curved upper portion but otherwise comprises the entire bottom section of the spectacle lens like the 'Executive' bifocal. Segment tops are generally but not always positioned at or a few millimeters below the lower lid margin, with round segments decentered nasally 2 to 3 mm to allow for convergence.
The majority of bifocal lenses produced today are one piece plastic lenses with the 'add' portion integrally formed into the body of the lens. Due to the discontinuous nature of the surface contour where the two sections meet, the segment is visible within the lens and the patient may perceive image jump or image displacement when looking at an object through the different power zones of the lens. Often times there is a noticeable ridge with segments that have a flat top. Fused glass bifocal and trifocal lenses are less common now than years ago. These lenses utilize two compatible glasses with different refractive indices that are fused together at over 600° c. The higher refractive index segment of the fused glass lens as well is visible within the lens and image jump is also present.
No-line or blended bifocals attempt to hide segment visibility by blending the area that joins the different sections of the lens. Blended bifocal lenses have not gained great popularity as the blend area incorporates a curvature inflection or deformation that exhibits blur and distortion.
In addition to bifocal and trifocal lenses, progressive addition lenses are used to provide correction for more than one viewing distance. Unlike bifocal and trifocal lenses, a progressive lens has a gradient of increasing lens power that provides a continuous range of focus between near and far distances. The extent of the power gradient typically ranges from around 12 to 18 mm. Progressive lenses have cosmetic appeal as the segment line and visibility present in bifocal and trifocal lenses is absent, but the useful area of the progressive and near vision zones of the lens is restricted as aberrations resulting from the power change of the lens result in poor vision especially in the lower lateral portions of the lens. As a result, some individuals do not adjust well to progressive lenses and prefer either reading glasses or bifocal or trifocal spectacle lenses.
Prior to the advent of plastic progressive lenses and blended bifocals, designers attempted to develop multifocal lenses with refractive index gradients between viewing portions of the lens to hide the segment line by locally modifying the refractive index at the interface of the segment and carrier lens. Ion exchange methods for segmented glass lenses have been suggested for this purpose, as described in U.S. Pat. No. 3,542,535 to Hensler, for example. The use of inorganic salts to modify the refractive index of a porous glass to create an ophthalmic lens with localized areas of power change has also been suggested. U.S. Pat. No. 4,073,579 to Deeg, et al describes such a lens. None of the lens systems has ever found commercial success, due in part to the difficulty involved in their respective manufacturing processes and the relatively small amount of refractive index change induced. Although some of these methods may be useful for the correction of optical aberrations, a greater amount of refractive index change is required to provide the refractive power needed for the high diopter additions of bifocal and trifocal lenses.
Gradient index plastic lenses produced by diffusion or other methods have been suggested.
U.S. Pat. No. 5,861,934 to Blum et al and U.S. Pat. No. 4,944,584 Maeda et al describe a multifocal lens having a gradient index resin layer between a first resin layer and the second resin layer. The inner portion has a curved segment-like region that provides add power. The refractive index gradient ranges between that of the first layer to that of the second layer in an axial direction and therefore makes the transition between the first and second layers less abrupt and thus makes the finished multifocal zone more invisible. Both of these lenses will exhibit a localized area of plus power and its associated optical properties and aberrations.
U.S. Pat. No. 3,485,556 to Naujokas describes a plastic multifocal lens with a uniform refractive index gradient between upper and lower lens portions of different refractive index. This lens at first appears to be capable of providing the stated distance and near vision properties. A ray tracing of the lens in accordance with the parameters set forth in the patent shows that only when a significantly high plus power configuration is utilized can an add power of even 1 diopter be achieved. Using the refractive indices of 1.5 and 1.6 identified in the patent a calculated plus power of 4.714 diopters is needed in the distance vision portion to achieve the only slightly greater power of 5.714 diopters in the near vision portion, thus the lens is useful only to those needing high plus power correction for distance vision. Furthermore, if a prescription incorporating cylinder power is produced on either the front or back surface, the cylinder power will vary and cause aberrations as a result of the gradually or progressively varying refractive index.
U.S. Pat. No. 6,942,339 to Dreher describes a multifocal or progressive lens constructed with a layer of variable index material, such as epoxy, sandwiched in between two lens blanks. The inner epoxy coating aberrator has vision zones configured to correct aberrations of the patient's eye and higher order aberrations. The variable index coating that comprises the inner layer of this lens does not provide the progressive add power of the lens, rather as stated in the patent it corrects for aberrations of the patient's eye. The lens has many of the limitations typical of aspheric progressive lenses.

Multi-layered multifocal lens with blended refractive index


In a silver-plated product wherein a surface layer of silver is formed on the surface of a base material or on the surface of an underlying layer formed on the base material, the surface layer of silver is formed by electroplating in a silver plating bath which contains 1 to 15 mg/L of selenium and wherein a mass ratio of silver to free cyanogen is in the range of from 0.9 to 1.8, and thereafter, an aging treatment is carried out to produce a silver-plated product wherein an area fraction in {200} orientation of the surface layer is 15% or more.

As conventional materials of contact and terminal parts, such as connectors and switches, there are used plated products wherein a base material of stainless steel, copper, a copper alloy or the like, which is relatively inexpensive and which has excellent corrosion resistance, mechanical characteristics and so forth, is plated with tin, silver, gold or the like in accordance with required characteristics, such as electrical and soldering characteristics.
Tin-plated products obtained by plating a base material of stainless steel, copper, a copper alloy or the like, with tin are inexpensive, but they do not have good corrosion resistance in a high-temperature environment. Gold-plated products obtained by plating such a base material with gold have excellent corrosion resistance and high reliability, but the costs thereof are high. On the other hand, silver-plated products obtained by plating such a base material with silver are inexpensive in comparison with gold-plated products and have excellent corrosion resistance in comparison with tin-plated products.
As a silver-plated product obtained by plating a base material of stainless steel, copper, a copper alloy or the like with silver, there is proposed a metal plate for electrical contacts, wherein a silver plating layer having a thickness of 1 micrometer is formed on a copper plating layer having a thickness of 0.1 to 0.5 μm which is formed on a nickel plating layer having a thickness of 0.1 to 0.3 μm which is formed on the surface of a thin base material plate of stainless steel (see, e.g., Japanese Patent No. 3889718). There is also proposed a silver-coated stainless bar for movable contacts, wherein a surface layer of silver or a silver alloy having a thickness of 0.5 to 2.0 μm is formed on an intermediate layer of at least one of nickel, a nickel alloy, copper and a copper alloy having a thickness of 0.05 to 0.2 μm, the intermediate layer being formed on an activated underlying layer of nickel which has a thickness of 0.01 to 0.1 μm and which is formed on a base material of stainless steel (see, e.g., Japanese Patent No. 4279285). Moreover, there is proposed a silver-coated material for movable contact parts, wherein a surface layer of silver or a silver alloy having a thickness of 0.2 to 1.5 μm is formed on an intermediate layer of copper or a copper alloy having a thickness of 0.01 to 0.2 μm, the intermediate layer being formed on an underlying layer of any one of nickel, a nickel alloy, cobalt or a cobalt alloy which has a thickness of 0.005 to 0.1 μm and which is formed on a metallic substrate of copper, a copper alloy, iron or an iron alloy, the arithmetic average roughness Ra of the metallic substrate being 0.001 to 0.2 μm, and the arithmetic average roughness Ra after forming the intermediate layer being 0.001 to 0.1 μm (see, e.g., Japanese patent Laid-Open No. 2010-146925).
However, when conventional silver-plated products are used in a high-temperature environment, there are some possibility that the adhesion properties of the plating film may be deteriorated and/or the contact resistance of the product may be very high. When the silver-plated products proposed in Japanese Patent Nos. 3889718 and 4279285 are used in a high-temperature environment, there are some possibility that the rise of the contact resistance of the product cannot be sufficiently restrained. On the other hand, when the silver-plated product proposed in Japanese Patent Laid-Open No. 2010-146926 is used in a high-temperature environment, the adhesion properties of the plating film are good, and the rise of the contact resistance of the product can be restrained. However, it is required to adjust the arithmetic average roughness Ra of a pressure roll to be 0.001 to 0.2 μm so that the arithmetic average roughness Ra of a metallic substrate, which is transferred by the pressure roll, is adjusted to be 0.001 to 0.2 μm. It is also required to appropriately choose the current density in plating and the kinds of additives in a plating solution during the formation of the intermediate layer to adjust the arithmetic average roughness Ra to be 0.001 to 0.1 μm after forming the intermediate layer, so that the process is complicated and the costs thereof are increased.
For that reason, the applicant has proposed to produce an inexpensive silver-plated product, which has good adhesion properties of the plating film and which can restrain the rise of the contact resistance of the product even if it is used in a high-temperature environment, by causing the crystalline diameter in a direction perpendicular to {111} plane of the surface layer to be 300 angstroms or more in a silver-plated product wherein a surface layer of Ag is formed on an intermediate layer of Cu which is formed on an underlying layer of Ni formed on the surface of a base material of stainless steel (Japanese Patent Application No. 2010-253045).
However, in a silver-plated product wherein a silver plating film is formed on the surface of a base material of copper or a copper alloy, or on the surface of an underlying layer of copper or a copper alloy formed on a base material, there is a problem in that copper diffuses to form CuO on the surface of the silver plating film to raise the contact resistance thereof if it is used in a high-temperature environment. There is also a problem in that cracks are formed in the silver-plated product to expose the base material if the silver-plated product is worked in a complicated shape or in a shape of small contact and terminal parts, such as connectors and switches.

This patent is subject to a terminal disclaimer.

Silver-plated product and method for producing same


An ambiguous usage of a name in a statement of a computer program is resolved at least partially by adding to an entry statement thereof a definition that includes the ambiguously used name followed by constructing a definition-use graph, followed by checking whether or not an edge from the added definition reaches the statement containing the ambiguously used name. If all edges into the ambiguous statement are from the added definition, then the name is deemed to be a function call. If all edges into the ambiguous statement are not from the added definition, then the name is deemed to be a memory access. If some edges into the ambiguous statement are from the added definition but other edges are not, then the statement is flagged as a dual usage.

Dynamically-typed programming languages (such as the MATLAB® programming language) provide a powerful prototyping and development mechanism for programmers. Because such programming languages allow variables to take on the types of expressions that are assigned to them during program execution, programmers do not have to worry about details such as declaring the variable types or creating functions specific for a given variable type. Such languages support a programming style where programmers create (or in some cases, recreate) variables based on local contexts. Variables are frequently used in several different ways and for several different purposes because programmers basically just create variables as they need them.
While dynamically-typed languages support a relaxed programming style for programmers, they present significant challenges for the programming tools that support them. In particular, the most obvious methods for executing dynamically-typed languages provide extremely slow execution speeds. The result is that programmers cannot develop large applications in a dynamically-typed language because a program of any significant size requires too much time to run. The key to making dynamically-typed languages useful is optimizing their execution performance, increasing their execution speed and thereby decreasing the time required to execute programs of any significant size. The technology behind such execution improvement is commonly called "code optimization", and the tool used to effect those improvements is commonly called a "code optimizer" or just "optimizer".
Optimizers work by "statically" analyzing a program prior to its execution (or its "run-time") to predict how the program will behave when executed on input data. Using those predictions, optimizers change the code that is executed so as to minimize the run time required to perform the calculation. In a very simplistic example, an optimizer will analyze a program that always computes and prints "7*6", and realize that the program will always print "42". In such a case, the optimizer will remove all instructions used in the computation, and leave in only the instructions required to print "42". The effectiveness of an optimizer depends on its ability to predict, prior to program execution, how a program will behave when it executes.
Dynamically-typed languages present a significant challenge for optimizers, since by their very nature dynamically-typed languages hide information until execution time. Since the optimizer has less information prior to execution about how a program behaves when it executes, the optimizer is less able to statically predict program behavior and is thereby limited in its ability to improve program execution.
The most significant hindrance in dynamically-typed languages is the inability to statically distinguish between function calls and array accesses. In many programming languages, function calls are distinguished syntactically by the appearance of parentheses; e.g. a function call in the source is indicated by "function_name (arg1, arg2, . . . )". Parentheses are also commonly used to indicate array accesses (or memory accesses) in languages; e.g. an array access in the source is indicated by "array_name (subscript 1, subscript 2, . . . )" Statically-typed languages are able to easily distinguish between these different uses from variable declarations. The programmer has to provide extra information about the variables to the compilation tool, which allows the tool to determine whether a given usage is an array access or a function call. In dynamically-typed languages, however, where variables can change type during the execution of a single assignment statement, such hints are not readily available. For instance, the variable "x" can be used as a function call in one statement of a program in the form "x(1,1)", then be used as an array access two statements later in the same form: "x(1,1)". Users cannot always easily determine whether a given reference is a function call or array access, making it difficult for them to provide hints to a compilation tool.
A programming reference such as "x(1,1)" above which may be either a function call or a memory access when examined from a strictly syntactic analysis is known as an "ambiguous reference" and the variable associated with that reference ("x" in the example) is known as an "ambiguous name". "Function calls" are variable references that when executed in the interpreter cause the program counter of the computer to jump to a non-sequential location, execute some number of instructions, then jump back to the next sequential instruction (accounting for "branch slots") following the function call. An "array access" is a reference to a variable that represents a collection of elements; the access may either fetch or set the values for some number of that collection. A "scalar access" is a reference to a variable that represents one element, and the access may either fetch or set the value of that element. "Memory access" refers to either an array access or scalar access, particularly when the collective nature of the variable is unknown. If a programming reference is used as a function call along some execution paths and as a memory access along other execution paths, the reference is considered a "dual usage".
The MATLAB® programming language (as defined by the MATLAB interpreter version 13.1) is one example of a dynamically-typed language. It not only supports parentheses as the syntactic notation for both function calls and array accesses, but it also requires that a function that takes no arguments be called without following parentheses. This means that a simple variable access (in MATLAB, such a reference can be either scalar or vector) is ambiguous with function calls. This ambiguity greatly increases the difficulty of building effective programming tools for the language.
The MATLAB programming language is defined by the actions of the interpreter provided for the language by The MathWorks, Inc. Interpreters are useful programming tools for dynamically-typed languages, in that they provide a mechanism naturally suited for resolving typing questions during execution. Interpreters create and maintain an execution state environment (such as a symbol table) while they dynamically execute a program. This environment allows an interpreter at any point during execution to examine the state of the program, including the values and types that have been assigned to variables. This environment allows an interpreter to easily resolve any ambiguity between array accesses and function calls, because it can determine precisely the characteristics of the variable in question. The following paragraph (from "MATLAB: The Language of Technical Computing—Using MATLAB Version 6", The MathWorks, Inc., 2002. p. 16-13) describes how MATLAB resolves variables as it executes:
"When MATLAB comes upon a new name, it resolves it into a specific function by following these steps:                1 Checks to see if the name is a variable.        2 Checks to see if the name is a subfunction, a MATLAB function that resides in the same M-file as the calling function. . . .        3 Checks to see if the name is a private function, a MATLAB function that resides in a private directory accessible only to M-files in the directory immediately above it. . . .        4 Checks to see if the name is a function on the MATLAB search path. MATLAB uses the first file it encounters with the specified name"
Once MATLAB has identified a name as a function rather than as a variable, it resolves the function using the following algorithm ("MATLAB: The Language of Technical Computing—Using MATLAB Version 6", The MathWorks, Inc., 2002. pp. 21-67 and 21-68):
"Function Precedence Order
The function precedence order determines the precedence of one function over another based on the type of function and its location on the MATLAB path. From the perspective of method selection, MATLAB contains two types of functions: those built into MATLAB, and those written as M-files. MATLAB treats these types differently when determining the function precedence order.
MATLAB selects the correct function for a given context by applying the following function precedence rules, in the order given.
For built-in functions:
1) Overloaded Methods
If there is a method in the class directory of the dispatching argument that has the same name as a MATLAB built-in function, then this method is called instead of the built-in function.
2) Nonoverloaded MATLAB Functions
If there is no overloaded method, then the MATLAB built-in function is called. MATLAB built-in functions take precedence over both subfunctions and private functions. Therefore, subfunctions or private functions with the same name as MATLAB built-in functions can never be called.
For nonbuilt-in functions:
1) Subfunctions
Subfunctions take precedence over all other M-file functions and overloaded methods that are on the path and have the same name. Even if the function is called with an argument of type matching that of an overloaded method, MATLAB uses the subfunction and ignores the overloaded method.
2) Private Functions
Private functions are called if there is no subfunction of the same name within the current scope. As with subfunctions, even if the function is called with an argument of type matching that of an overloaded method, MATLAB uses the private function and ignores the overloaded method.
3) Class Constructor Functions
Constructor functions (functions having names that are the same as the @directory, for example @polynom/polynom.m) take precedence over other MATLAB functions. Therefore, if you create an M-file called polynom.m and put it on your path before the constructor @polynom/polynom.m version, MATLAB will always call the constructor version.
4) Overloaded Methods
MATLAB calls an overloaded method if it is not masked by a subfunction or private function.
5) Current Directory
A function in the current working directory is selected before one elsewhere on the path.
6) Elsewhere On Path
Finally, a function anywhere else on the path is selected."
Because the MATLAB interpreter dynamically maintains the program state, it can precisely resolve any ambiguity in the use of a name.
The just-described method for resolving the ambiguous usage of a name in a statement is well-suited for an interpreter, but does not work for a compiler because the compiler must create executable code well before any statements in the program being compiled are executed. Specifically, whether or not a name is defined as a function at the time of execution of a particular statement is unknown ahead of time. Compilers and related tools work by statically predicting the program's execution at run-time. Because they are predicting, and not directly executing, these tools do not have the advantage of a dynamically-maintained execution state.
Resolving the ambiguity, particularly between function calls and array/memory accesses, is an extremely important problem. Since function calls may have widely different effects on a program's state than array accesses, separating them is critical to the success of any program analysis such as optimization. For instance, determining how information flows across procedure calls is an important area of analysis. Such analysis is impossible to perform without knowledge of the procedure calls, which cannot be determined unless procedure calls, memory accesses, and dual usages are separated. This type of information, which is typically used to build a call graph of the procedures and analyze across them, is valuable both to compiler tools and to interpreters that want to pre-optimize program performance before initiating execution. This information may also be useful in contexts other than building a call graph, such as when performing localized procedure inlining.
Because of the significance of the problem, much research has been performed on the problem of statically distinguishing among function calls, array/memory accesses, and dual usage in ambiguous dynamically-typed languages. De Rose and Padua (De Rose, Luiz, and Padua, David, "Techniques for the Translation of MATLAB Programs into Fortran 90", ACM Transactions on Programming Languages and Systems, Vol 21, No. 2, March, 1999. Pages 286-323) developed a state transition diagram to be used with a simple walk over the program representation to distinguish function calls, array accesses, and dual usages. This approach suffers from two deficiencies: a) it does not take advantage of control flow, and b) it does not account for the fact that a dynamically-typed language may have multiple variables that share the same name. The first deficiency will cause the approach to incorrectly label some cases of dual usage. The second deficiency will cause the approach to label as dual usages many variables that are not. In particular, since dynamically-typed languages allow variables to be created and destroyed as values are assigned to them, it is very feasible for a variable to be a function call in the first part of a program and an array access in the later part—in essence, being two completely different variables. De Rose and Padua's technique will force the two variables into one, causing a false dual usage. A compiler transformation "variable renaming" eliminates this false usage when utilized in the embodiment of this invention.
Almasi and Padua developed a different approach based on a data flow analysis framework in a 2002 paper (Almasi, George and Padua, David, "MaJIC: Compiling MATLAB for Speed and Responsiveness", ACM Conference on Programming Language Design and Implementation, June, 2002, Pages 294-303). Their approach is based on a dataflow analysis approach using the fact that "a symbol that has a reaching definition as a variable on all paths leading to it MUST be a variable" (emphasis added). They incorporate this fact into a meet-over-all-paths data analysis framework by defining for each statement a set s of symbols which are known to be variables at that statement. The set s can then be computed for every statement by any number of well-known techniques for computing fixed-point solutions in a lattice. A similar, but different, meet-over-all-paths analysis framework can be set up to determine that set of variables at each statement that are known to be function calls.
Almasi and Padua's approach provides significantly more precision than De Rose and Padua's approach, but still suffers from two significant disadvantages. First, different approaches are required to compute variables and function calls: the computations, while similar, cannot be performed simultaneously on the same data. This means that computing both the variables and the function calls requires roughly twice the amount of some resource (a skilled practitioner will realize that time and memory can be traded off in programmed computers, so that computing both requires roughly either twice the memory or twice the computation time of computing either alone). Since it is necessary to compute both in order to compute "dual usage" variables, this extra overhead is required for most programs. Second, in addition to neither approach (that is, to computing function calls and variable accesses) being able to solve the other problem, neither approach can be applied to other data flow problems, such as dead code elimination, constant propagation, or variable renaming. These transformations are data flow analysis problems that are commonly used by compilers and interpreters to improve program execution. Since they require a different dataflow lattice than that used by Almasi and Padua, an optimizer that attempts both Almasi and Padua's approach and common optimization transformations will incur even more computational overhead.
A problem similar to that of inferring function calls in ambiguous, dynamically-typed languages is the problem of detecting uninitialized variables in statically-typed languages such as FORTRAN. U.S. Pat. No. 5,615,369 granted to Holler on Mar. 25, 1997, which is incorporated by reference, specifies an invention for detecting and initializing uninitialized variables in FORTRAN. Holler's framework computes over all paths whether it is possible for the use of a variable to reach back to the entry of a program without passing through a definition of that variable. If so, the variable may be uninitialized when used, and the invention inserts an initialization at the source. Holler's method provides the same dataflow lattice that is used in more conventional optimization problems, allowing it to be reused for other transformations. However, Holler's approach computes information over all possible control flow paths, causing it to be expensive to compute in some instances.
Dataflow analysis frameworks, lattices, and techniques are well known in the art and are discussed fully in Chapter 4 of a book by Allen, Randy and Kennedy, Ken entitled "Optimizing Compilers for Modern Architectures", Morgan Kaufmann publishers, 2002. This chapter is incorporated by reference herein in its entirety. The goal of dataflow analysis is to relate each "use" of a variable in the program (where "use" means any programming construct that may read or in any other way use the value that the variable contains in the computer's memory) to all possible "definitions" of that variable in the program (where "definition" means any programming construct that may set or change the value that the variable contains in the computer's memory) that can possibly set the value that the use may receive. "Definitions" are also commonly called "defs". A "reference" (or "ref") is any form of reference to a variable, either a use of the variable or a definition of the variable
It is well known in the art how to go from a definition of a variable to all locations in a computer program that may use the definition at execution time. Specifically, a "definition-use chain" is a data structure that is commonly used to perform such an operation. A definition-use chain is comprised of nodes and edges, where nodes represent variable references in the user's program, and an edge exists between two nodes when one node is a definition whose value may be used by the second node. In other words, an edge connects a definition to all possible runtime uses of that definition. While edges are normally indicated as going from definition to use, following the flow of data within the program, they may be as easily thought of as flowing from use to def (indicating a use that needs a value defined by the def), and a skilled artisan can easily construct data structures that allow both forms to be used. Note that the term "definition use graph" is more appropriate than the traditional "definition-use chains" because "graph" more correctly characterizes the nature of the information the data structure contains. The definition-use chain (or graph) is essentially a scalar version of true dependences within a program. Note that each node in a definition use graph is also referred to as a "permanent node" if the node represents a permanent definition (e.g. represents a statement or represents a variable) originally present in the user's computer program. In contrast if a node represents a temporary definition that is added automatically (for all variables in most embodiments) then the node is called a "temporary node". As noted below, a temporary node becomes a permanent node in some embodiments during optimization if a variable in the user's computer program was originally undefined.
Constructing definition-use edges within a single straight-line block of code is well known. One visits each statement in order in the basic block, noting the variables defined by each statement as well as the variables used by each statement. For each use, an edge is added to the definition use graph for that use back to the last exposed definition in the block of that variable—in other words, to every definition that reaches the use. Whenever a new definition is encountered for a variable, the new definition kills (i.e. over-writes) the existing definition, so that later uses are linked only to the new definition, not to the old. When the end of the block is reached, the definition use graph is complete.
Constructing a definition-use graph across a program comprised of more than a single straight-line block of code is more complicated. Standard art contains many different methods for computing definition-use graphs for programs containing control flow, many of which are summarized in Chapter 1 by Kennedy, Ken entitled "A survey of data-flow analysis techniques", In a book by S. S. Muchnick and N. D. Jones, editors, "Program Flow Analysis: Theory and Applications,", pp. 1-51. Prentice Hall publishers, 1981. At a high level, the methods all work by decomposing a program into simpler units (basic blocks, intervals, or others) and a control flow graph indicating the flow between the units. In a local pass, information is computed for each individual unit, regardless of the control flow among the units. Such information typically consists of sets of variables that are used, defined, killed ("kills" are definitions where all existing values in a variable can safely be assumed to be replaced), and reaches ("reaches" are definitions that can reach a given use). This local information is then combined into global information by propagating it along the control flow graph, using any of a number of dataflow propagation techniques (including iterative, interval, parse, and others). After the global information is available for the whole program, a definition-use graph can then be constructed by distributing the information back across the local units.
Dataflow information (e.g. in most embodiments definitions and uses) are propagated by several techniques (i.e. iterative, interval, and so on) are based on framing the problem inside a lattice(also referred to in this patent application as a dataflow framework). A lattice, as defined in S. Muchnick, Advanced Compiler Design and Implementation, Morgan Kaufmann, 1997, consists of a set of values and two operations "meet" and "join", both of which are closed, commutative, associative, distributive (in this patent application, but not in general), and monotonic (again in this patent application, but not in general). A lattice also has two designated elements "top" and "bottom". All the dataflow propagation techniques discussed at the beginning of this paragraph can be applied to any problem that can be embedded in such a lattice (or dataflow framework). Propagating uses and definitions of variables is certainly one type of information embedded in a lattice in all embodiments of the invention.
When definitions and uses are propagated through a lattice, it is often convenient to abstract the resulting flow of data in a definition-use graph. Definition-use graphs can be embodied in a number of different forms, including linked lists, bit matrices, sets, bit vectors, etc. While the description of the techniques most often refers to a linked list of edges, skilled practitioners will readily recognize that all representations are equivalent in terms of the application of this invention.
One of the reasons that the ability to distinguish function calls from memory accesses is critical to optimizing programs written in a dynamically-typed language is that an understanding of function calls is critical to constructing definition-use graphs and optimizing transformations. A memory access that is only a use (a fact that can be determined from a syntactic analysis of the program in most languages that are not dynamically-typed) is guaranteed not to change the state of memory (other than registers) in a programmed computer. A memory access that is a definition (a fact that can again be determined from a syntactic analysis of the program in most languages that are not dynamically-typed) is guaranteed to change only a limited number of elements of memory of a programmed computer. A function call, however, can execute an arbitrary number of instructions, which may fetch and set any number of elements of a computer's memory. Since the goal of optimization is to predict at compile time what a program is going to do at run time, function calls are a large source of unpredictability, and thus are difficult for optimization techniques to handle. Memory accesses, on the other hand, have a limited set of effects, and are much more easily handled. As a result, separating function calls from memory accesses is critical to effectively optimizing a program, and in particular to constructing an accurate definition-use graph for a program.
"Entry points" and "entry nodes" are well defined terms in compiler literature. An entry point is a program location by which control may enter a function. In many programming languages, that is a single statement, such as in MATLAB, where the function header is the only entry point. In other languages, such as FORTRAN, multiple entry points into a procedure are supported, and any of those serves as an entry point. For analysis, compilers often simplify programs with multiple entry points by creating one unique entry point and by making the multiple entry points labels. When control reaches the unique entry point, it immediately branches to the appropriate label representing the former entry point to which control was to transfer. An "entry node" is the intermediate representation of the unique entry point.

Inferring function calls in an ambiguous language computer program


An image forming apparatus including: an image forming apparatus main unit; an image carrier provided in the image forming apparatus main unit; at least one developing device supported retractable from the image carrier; and a developer supply portion adapted to supply developer to the developing device, wherein: a developer inlet port provided in the developing device is slidably joined with a developer supply port provided in the developer supply portion; a seal portion is provided between the developer inlet port and the developer supply port; the seal portion includes a seal portion body made of an elastic material, a sliding portion provided on at least one of surfaces of the seal portion body, and a drawing-out portion connected to the seal portion body and to the sliding portion; and the seal portion is enabled to be drawn out by using the drawing-out portion.

1. Field of the Invention
The present invention relates to an image forming apparatus, such as a printer, a facsimile, and a copying machine, and to a seal portion for use in the image forming apparatus.
2. Background Art
An image forming apparatus has, within an image forming apparatus main unit thereof, an image carrier constituted by, for example, a photoreceptor, an optical writing device adapted to form a latent image on this image carrier, and a developing device adapted to visualize the latent image formed on the image carrier by this optical writing device. A developer supply portion supplies developer to the developing device. There has been known one such a developing device which is disposed retractable from the image carrier and which is adapted to be retracted, for instance, in a case where the image carrier is exchanged, thereby to prevent the image carrier from being damaged, for example, being scratched. In the case where the developing device is retracted, a developer inlet port provided in the developing device is slidably joined with a developer supply port provided in the developer supply portion.
Incidentally, JP-A-2002-341650 discloses technology of applying a film member to an elastic member fixed to the periphery of at least one of openings, which are respectively provided in two casings so that developer is transferred therebetween, thereby to enhance slidability at opening/closing of the opening portions of the two casings and also enhance ability to seal the leakage of toner. Also, Japanese Patent No. 3054323 discloses technology of pasting an elastic member onto a sliding portion, which slides through a guide portion of an openable and closable shutter of a refill toner container, and also coating a film member, which is applied to a sliding surface of the sliding portion, with a coating layer made of a silicon based material so that the container has good slidability at opening/closing of the shutter and excels in ability to seal the leakage of toner.
At shipping inspection of an image forming apparatus, developer is supplied into a developing device. Then, an image is printed on test paper by using the developer stored in the developing device. However, there has been caused a problem that the developer stored in the developing device leaks from the developer inlet port, the developer supply port, and the sliding portion during the image forming apparatus is transported after the shipping inspection. Neither JP-A-02-341650 nor Japanese Patent No. 3054323 discloses how to assure sealability against the leakage of developer from the developer inlet port, the developer supply port, and the sliding portion.

Image forming apparatus and seal portion for use in the same


Methods and apparatus for finding a match between a target bit pattern and multiple filter bit patterns. A filter array is created from the filter bit patterns and at least one intermediate array is generated from the filter array. Specific columns of the intermediate arrays are then extracted based on bit values of the target bit pattern. A row by row AND operation is performed on these columns to arrive at a match vector. the match vector identifies which of the filter bit patterns in the filter array match the target bit pattern. The method is implemented by using multiple classifier elements operating in parallel with each classifier element handling multiple filter bit patterns.

In data networks, routers classify packets to determine the micro-flows the packets belong to and then apply the classification to the packets accordingly. Flow identification is the essential first step for providing any flow dependent service. A number of network services require packet classification including access-control, firewalls, policy-based routing, provision of integrated/differentiated qualities of service, traffic billing, secure tunnelling. In each application, the classifier determines which micro-flow an arriving packet belongs to so as to determine whether to forward or filter, where to forward it to, what class of service it should receive, the scheduling tag/state/parameter that it is associated with, or how much should be charged for transporting it. The classifier maintains a set of rules about packet headers for flow classification.
To clarify, a router is multi-port network device that can receive and transmit data packets from/to each port simultaneously. Data packets typically has regular format with uniform header structure. The header structure usually contain data fields such as address, packet type. When a packet is received from a port, the router uses the header information to determine whether a packet is discarded, logged, or forwarded. If a packet is forwarded, then the router also calculates which output port the packet will be going to. The router also accounts for the number of each type of packet passing by. The forwarding decision (where to send the packet) is typically made based on the destination address carried in the packet. In an Internet Protocol Router, forwarding involves a lookup process called the Longest Prefix Match (LPM) that is a special case of the general mask matching process.
The LPM uses a route table that maps a prefix rule (a mask-matching rule with all the wildcard bits located at the contiguous least significant bits) to an output port ID. An example of an LPM route table is given below:
#32-bit PrefixOutput PortID1xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxxport 021111 0010 1100 xxxx xxxx xxxx xxxx xxxxport 131101 0011 0001 xxxx xxxx xxxx xxxx xxxxport 341111 0010 1100 1100 0011 xxxx xxxx xxxxport 250010 0000 0001 1111 1111 0000 1101 0000port 4
An input packet with destination address="1111 0010 1100 1100 0011 1111 1111 1111" should be forwarded to port 2 because it matches entry #3 and #4, but #4 has priority over #3 because the prefix length (number of non-wildcard bits) of #4 is longer than #3.
The router/firewalls examine the input packets to determine if they should be discarded and logged. This is usually done with an Access Control List (ACL) Lookup. An ACL can be a suer configurable mask-matching rule set (based on packet header fields) that categorizes certain types of traffic that may be hazardous to the network. Hence, when a packet that matches an ACL entry, the router/firewall should take action according to the ACL to discard/log the packet or alarm the network administrator.
Such devices as explained above use general multi-layer classification methods in carrying out the devices function. General multi-layer classification requires the examination of arbitrary data/control fields in multiple protocol layers. The grammatical/lexical parser provides flexible solutions to this problem, but the cost of supporting a large rule set is high.
A multiple field classifier is a simple form of classifier that relies on a number of fixed fields in a packet header. A classic example is the 7-dimensional classification, which examines the SA/DA/TOS/Protocol in the IP header, and the SPORT/DPORT/PROTOCOL_FLAG in the TCP/UDP header. Because a multi-field classifier deals with fixed fields, parsing is not required. Instead of dealing with variable length packets, the multi-field classifier does classification on fixed sized search keys. The search key is a data structure of the extracted packet data fields. The Multi-field classifier assumes the search keys are extracted from the packet before being presented to the classifier.
The problem of multiple field classification can be transformed into the problem of condition matching in multi-dimensional search key space, where each dimension represents one of the data fields the classifier needs to examine. A classification rule specifies conditions to be matched in all dimensions.
The classification rules specify value requirements on several fixed common data fields. Previous study shows that a majority of existing applications require up to 8 fields to be specified: source/destination Network-layer address (32-bit for Ipv4), source/destination Transport-layer port numbers (16-bit for TCP and UDP), Type-of-service (TOS) field (8-bits), Protocol field (8-bits), and Transport-Layer protocol flags (8-bits) with a total of 120 bits. The number of fields and total width of the fields may increase for future applications.
Rules can be represented in a number of ways including exact number match, prefix match, range match, and wildcard match. Wildcard match was chosen to be the only method of rule representation that did not sacrifice generality. Any other forms of matching are translated into one or multiple wildcard match rules. A wild card match rule is defined as a ternary string, where each bit can take one of three possible values: '1', '0', or 'x'. A bit of '1' or '0' in the rule requires the matching search key bit in the corresponding position to have exactly the same value, and a bit of 'x' bit in the rule can match either '0' or '1' in the search key.
An example of a rule specification on a 16-bit field is given below:
The classifier wants to match   1111  0000  xx1x  0xx1The mask is:   1111  1111  0010  1001The target value is:   1111  0000  0010  0001
Prefix match rules can be represented in wildcard rules naturally by contiguous 'x' bits in the rules. However the don't-care bits in a general wildcard do not have to be contiguous. Ranges or multiple disjoint point values may be defined by using multiple masked matching rules. For example, an 8-bit range must be broken into two masked matching rules '00010xxx' and '00110xx'. Even with this limitation, the masked matching form is still considered to be an efficient representation, because most of the ranges in use can be broken down into a small number of mask rules. A compiler can handle the task of breaking down user rule specification in a convenient syntax, therefore the complexity can be hidden from the user.
Each rule represents a region in the multi-dimensional space. Each search key (representing a packet to be classified) defines a point in this space. Points that fall into one region are classified as a member of the associated class. Ambiguity arises when multiple regions overlap each other. A single priority order is defined among the rules to resolve the ambiguity. The rules are numbered from 0 to N−1. The rule indices define the priority among the rules in ascending order. The region with higher priority will cover the region with lower priority. In other words, if a packet satisfies both rule[i] and rule[j], if i<j, it is classified into class[i], otherwise into class[j].
One advantage of mask matching is its dimension independence. Multiple fields concatenated can be classified with the same method as if they were one wide field. This is accomplished by concatenating the masks of the target strings.
The prior solutions can be grouped into the following categories:
Sequential Match
For each arriving packet, this approach evaluates each rule sequentially until a rule is found that matches all the fields of the search key. While this approach is simple and efficient in use of memory (memory size grows linearly as the size of the rule set increase), this approach is unsuitable for high-speed implementation. The time required to perform a lookup grows linearly with rule set size.
Grid of Tries
The 'Grid of Tries' (or Tuple Space Search) uses extension of tries data structure to support two fields per search key. This is a good solution for two-dimensional rule set. But it is not easy to extend the concept to more fields. The cross-producting scheme is an extension of the 'Grid of Tries' that requires linear search of the database to find the best matching filter. Hence the effectiveness of cross-producting is not clear. The grid of tries approach requires intensive precompute time. The rule update speed is slow.
A scheme based on tries is presented by Douceur et al. in U.S. Pat. No. 5,995,971 and U.S. Pat. No. 5,956,721. This method utilizes a tri-indexed hierarchy forest ("Rhizome") that accommodates wildcards for retrieving, given a specific input key, a pattern stored in the forest that is identical to or subsumes the key. This approach has the weakness of not supporting "conflict" between patterns (as stated in line 21˜26, column 22 of U.S. Pat. No. 5,995,971). Patterns that partially overlap but do not subsume one another (E.g. pattern "100×" and "1×00") are in "conflict" because they overlap each other partially, may not be stored in the rhizome defined by the invention, since no defined hierarchical relationship holds for these patterns. In networking applications, these conflicts widely exist in router access list and firewall policies. This weakness limits the use of the classification scheme.
Concurrent Cross Producting
T. V. Lakshman in "High Speed Policy-Based Packet Forwarding Using Efficient Multi-Dimensional range Matching", Proceedings of ACM SIGCOMM' 98 Conference, September, 1998, presented a hardware mechanism for concurrent matching of multiple fields. For each dimensional matching this scheme does binary search on projections of regions on each dimensions to find the best match region. A bit-level parallelism scheme is used to solve the crossproducting problem among dimensions. The memory size required by this scheme grows quadratically and memory bandwidth grows linearly with the size of the rule set. Because of the computation complexity in the cross-producting operating, this scheme has a poor scaling property. This scheme also requires a time consuming data structure generation process, hence the rule update speed is slow.
Ternary CAM
Hardware Ternary CAMs (Content Addressed Memory) can be used for classification. Ternary CAMs store three value digits: '0', '1' or 'X' (wildcard). The CAMs have good look-up performance, fast rule update time. But the hardware cost (silicon area) and power consumption are high. More over, the CAMs require full-custom physical design that prevents easy migration between different IC technologies. For these reasons, current available CAMs are typically small.
Recursive Flow Classification
The recursive flow classifier (RFC) as discussed in Pankaj Gupta and Nick Mckeown, "Packet Classification on Multiple Fields", Sigcomm, September 1999, Harvard University and Pankaj Gupta and Nick Mckeown, "Packet Classification using Hierarchal Intelligent Cuttings", Proc. Hot Interconnects VII, August 99, Stanford, exploits the heuristics in typical router policy database structure(router microflow classifier, access list, fireware rules). RFC uses multiple reduction phases; each step consisting of a set of parallel memory lookups. Each lookup is a reduction in the sense that the value returned by the memory lookup is shorter (is expressed in fewer bits) than the index of the memory access. The algorithm can support very high lookup speed at relatively low memory bandwidth requirement. Since it relies on the policy database structure, in the worst case, little reduction can be achieve at each step. Hence the performance becomes indeterministic. In a normal case, the lookup performance gain is achieved at the cost of high memory size and very long precomputation time. For a large ruleset (16K), the RFC precompute time exceeds the practical limit of a few seconds. In general, RFC is suitable for small classifiers with static rules.
Based on the above, any solution developed must therefore have a number of features. The first is that of a fast look up speed. Since look up speed is determined by the number of steps (or hardwired clock cycles) required to perform each look up, any solution must have either a small constant value for its number of steps or this must be bounded by a small constant value. The second requirement is that any solution must be capable of supporting a large mask-matching rule set size. The size of the rule set must be capable of expansion at linear hardware/memory cost without sacrificing throughput.
A third requirement is of an expandable field width. A solution must allow for variable width of a search key or must support varied number of dimensions (number of fields) at linear cost.
A fourth requirement is that in implementing a solution no external memory should be required. many classification methods consume either a huge amount of memory storage and/or memory bandwidth. Both external memory storage and memory bandwidth are expansive factors that must be considered in chip architecture. These factors directly affect chip feasibility if either factor is too large. A solution should limit the rule set data structure in on-chip memory to prevent off-chip memory accesses.
A solution should also allow for fast rule updates. it should have a linear pre-compute time for rule set data structures random (non-intrusive) access to rule set image to allow for fast incremental insertion, deletion, and modification of individual rules. Some classification methods require a very long pre-processing time and/or intrusive reload of rule image data structure for a small change in the rule set. The long update/pre-processing time prevents such methods from being effective for microflow classification for provision of differentiated/integrated QOS (Quality of Service) where the rule sets are often session dependent or require frequent updates with low latency tolerance.
Ideally, a solution should not rely on the heuristics by how rules are structured. It should give deterministic performance and cost for an arbitrary rule set of certain size. This allows such a solution to be used to support existing and future applications where rule structures are not well understood.

Multi-field classification using enhanced masked matching


In an example embodiment, a process is introduced and acted upon a table prior to the rendering of the table. This process involves optimizing the display of the table by, among other things, automatically setting column widths to reduce extra white space, removing columns with no data, and/or generally reducing the size of the table to attempt to, if possible, remove the presence of a horizontal scroll bar.

Various different types of computer applications display data in user interfaces in the form of tables, namely by displaying data in cells of columns and rows. Spreadsheet applications, for example, lay out a spreadsheet using such columns and rows, and indeed many database retrievals and data analysis applications utilize a similar column and row based presentation of data.
From a visual standpoint, it is usually considered more visually pleasing to present such tables using rows of equal height (i.e., no variance in height from row to row), but to allow for variation on column width to accommodate the user needs and the data itself. Traditionally, however, such variation was controlled by the end-user, who could, for example, click a marker indicating a vertical border of a column and drag it left or right to increase or decrease the width of the column. This customization would then be preserved upon future views of the same table.
While this was a satisfactory solution for a number of years, in more recent times users have begun utilizing more than one type of computer system to view data, such as using a desktop computer at work, a laptop computer at home, and a mobile device (or multiple mobile devices), conceivably all being used to view the same table at different times. This is problematic because each of these devices has a different screen size and resolution. This creates the technical problem of the user's selection of a column width on one device causing a visually unpleasing layout on another device. Additionally, even within the same device, the rise of mobile devices have also increased the likelihood that the same device could be easily swapped between different viewing modes, the most common being switching between portrait and landscape mode. The result is that a user's selection of a column width in portrait mode may cause a visually unpleasing layout when the user switches to landscape mode, and vice-versa.
What is needed is a technical solution that optimizes the view of a table no matter the device or viewing mode used.


A system for transmitting a digital broadcasting signal includes a supplementary reference signal (SRS) inserter receiving a dual transport stream in which a normal stream and a turbo stream are multiplexed, and inserting an SRS into a stuffing region provided in the dual transport stream, a Reed-Solomon encoder encoding the dual transport stream having the SRS inserted therein, an interleaver interleaving the encoded dual transport stream, a turbo processor detecting and encoding the turbo stream from the interleaved dual transport stream, stuffing the dual transport stream with the encoded turbo stream, and compensating for a parity corresponding to the encoded turbo stream, and a trellis/parity corrector performing a trellis encoding of the dual transport stream processed by the turbo processor, which can robustly process a turbo stream included in the dual transport stream and easily confirm the channel state between a transmitter side and a receiver side.

1. Field of the Invention
Aspects of the present invention relate to a system for processing and transmitting a digital broadcasting signal and a method thereof, which can robustly process and transmit a digital broadcasting transport stream, and more particularly, to a system for processing and transmitting a digital broadcasting signal and a method thereof, which robustly process and transmit a digital broadcasting transport stream with a simple construction, that strives for the performance improvement through performing an information exchange and mapping on a dual transport stream including normal data and robust data, and which can confirm the channel state using a supplementary reference signal, in order to improve the receiving performance of an Advanced Television Systems Committee (ATSC) Vestigial Side Band (VSB) system that is an American type digital terrestrial broadcasting system.
2. Description of the Related Art
An Advanced Television Systems Committee (ATSC) Vestigial Side Band (VSB) system an American type digital terrestrial broadcasting system and is a signal carrier type broadcasting system. The ATSC VSB system uses a field sync signal in the unit of 312 segments. Accordingly, this system's receiving performance is not good in an inferior channel, and particularly, in a Doppler fading channel.
FIG. 1 is a block diagram illustrating the construction of a transmitter/receiver of an ATSC DTV standard as a general American type digital terrestrial broadcasting system. The digital broadcast transmitter of FIG. 1 is an enhanced VSB (EVSB) system proposed by Philips, which forms and transmits a dual stream. The dual stream is produced by adding robust data to normal data of the basic ATSC VSB system. As illustrated in FIG. 1, the digital broadcast transmitter includes a randomizer 11 randomizing a dual stream. A Reed-Solomon (RS) encoder 12 in the form of a concatenated coder adds parity bytes to the transport stream in order to correct errors occurring due to the channel characteristics in a transport process. An interleaver 13 interleaves the RS-encoded data according to a specified pattern. A ⅔-rate trellis encoder 14 maps the interleaved data onto 8-level symbols by performing a ⅔-rate trellis encoding of the interleaved data. The digital broadcast transmitter performs an error correction coding of the dual stream.
The digital broadcast transmitter further includes a multiplexer 15 inserting a field sync signal and a segment sync signal into the error-correction-coded data as illustrated in FIG. 2. A modulator 16 inserts a pilot tone into the data symbols into which the segment sync signal and the field sync signal have been inserted by adding a specified DC value to the data symbols. The modulator 16 performs a VSB modulation of the data symbols by pulse-shaping the data symbols, and up-converts the modulated data symbols into an RF channel band signal to transmit the RF channel band signal.
In the digital broadcast transmitter, the normal data and the robust data are multiplexed (not illustrated) according to a dual stream system that transmits the normal data and the robust data through one channel. The multiplexed data is inputted to the randomizer 11. The input data is randomized through the randomizer 11, outer-encoded through the RS encoder 120 that is an outer encoder, and then distributed through the interleaver 13.
Also, the interleaved data is inner-encoded in the unit of 12 symbols through the trellis encoder 14, and then mapped onto the 8-level symbols. After the field sync signal and the segment sync signal are inserted into the encoded data, the data is VSB-modulated by inserting the pilot tone into the data, and converted into an RF signal.
The digital broadcast receiver of FIG. 1 includes a tuner (not illustrated) converting an RF signal received through a channel into a baseband signal. A demodulator 21 performs a sync detection and demodulation of the converted baseband signal. An equalizer 22 compensates for a channel distortion of the demodulated signal occurring due to a multi-path. A Viterbi decoder 23 corrects errors of the equalized signal and decodes the error-corrected signal to symbol data. A deinterleaver 24 rearranges the data distributed by the interleaver 13 of the digital broadcast transmitter. A RS decoder 25 corrects errors. A derandomizer 26 de-randomizes the data corrected through the RS decoder 25 and outputs an MPEG-2 transport stream. Accordingly, the digital broadcast receiver of FIG. 1 down-converts the RF signal into the baseband signal, demodulates and equalizes the converted signal, and then channel-decodes the demodulated signal to restore the original signal.
FIG. 2 illustrates a VSB data frame for use in the American type digital broadcasting (8-VSB) system, into which a segment sync signal and a field sync signal are inserted. As shown in FIG. 2, one frame is composed of two fields. One field is composed of one field sync segment that is the first segment, and 312 data segments. Also, one segment in the VSB data frame corresponds to one MPEG-2 packet, and is composed of a segment sync signal of four symbols and 828 data symbols. In FIG. 2, the segment sync signal and the field sync signal are used for the synchronization and equalization in the digital broadcast receiver. That is, the field sync signal and the segment sync signal refer to known data between the digital broadcast transmitter and receiver, which is used as a reference signal when the equalization is performed in the receiver side.
The American type digital terrestrial broadcasting system as illustrated in FIG. 1 is a system that can form and transmit a dual stream produced by adding the robust data to the normal data of the existing ATSC VSB system. This system transmits the robust data together with the existing normal data. However, the American type digital terrestrial broadcasting system of FIG. 1 has the problem that it has almost no effect of improving the inferior receiving performance in a multipath channel due to the transmission of the existing normal data, even though the system transmits the dual stream produced by adding the robust data to the normal data. That is, the robust data has almost no effect of improving the receiving performance according to the improvement of the normal stream.
Also, even with respect to a turbo stream, the robust data does not have a great effect of improving the receiving performance in a multipath environment.
In addition, according to the conventional digital broadcasting system, it is impossible to confirm the channel state between a transmitter side and a receiver side.

System for processing and transmitting digital broadcasting signal and method thereof


An optical device includes a light-emitting device and a sensor device (a light receiving element). The light-emitting device includes a substrate, a plurality of light-emitting elements, and a plurality of light-transmitting units. The substrate has a first surface and a second surface. The second surface is opposite the first surface. The plurality of light-emitting elements are located on the first surface side of the substrate. Each of the plurality of light-transmitting units is located between light-emitting elements adjacent to each other. The light-emitting device has light-transmitting properties by the plurality of light-transmitting units. Light from the plurality of light-emitting elements is emitted mainly from the second surface of the substrate. The amount of light leakage from light emitted from each light-emitting element and leaked toward the outside of the first surface of the substrate is suppressed.

In recent years, organic light-emitting diodes (OLEDs) having light-transmitting properties have been developed. Patent Document 1 and Patent Document 2 disclose one example of a light-transmitting OLED. This OLED includes a substrate, a first electrode, an organic layer, and a plurality of second electrodes. The first electrode and the organic layer are laminated on the substrate in order. The plurality of second electrodes are disposed on the organic layer in a striped pattern. Light from outside the OLED can be transmitted through a region between the second electrodes adjacent to each other. Thus, the OLED is provided with light-transmitting properties.
Patent Document 3 describes installing a light-transmitting OLED on a rear window of an automobile. Such a light-transmitting OLED can function as a marker light of an automobile, for example, as a high-mount stop-lamp.


The present invention is applicable to the interface field, and in particular, relates to a power supply method for a terminal device, where the terminal device is communicatively connected to an accessory device. The method includes: detecting, by the terminal device, an ID resistance value of the accessory device; identifying a type of the accessory device according to the detected ID resistance value; selecting a power supply mode of the terminal device according to the identified type of the accessory device; and supplying power according to the selected power supply mode. In this way, the power input or output of the terminal device is free from the restriction of an OTG working mode of the terminal device.

In designing a product, a USB (Universal Serial BUS, universal serial bus) interface of a terminal device is usually used to connect to accessories to extend functions. USB OTG (On-The-Go) is a main outbound communication interface of an internal processor of the terminal device. With respect to implementation, the USB OTG automatically switches between a host (master device) working mode and a device (slave device) working mode by using a USB interface ID (Identity, identity) signal level. When the ID signal has a low level, the OTG working mode of the terminal device is set to a host mode. In this case, 5 V power needs to be output to an external accessory through a VBUS (USB voltage line) power supply of the terminal device; or, when an ID signal is floating or has a high level and the OTG working mode of the terminal device is set to a Device mode, the VBUS power supply of the terminal device needs to input power from the outside for the purposes of charging a battery of the terminal device and powering the system.
In the process of implementing the present invention, the inventor finds that the prior art has at least the following disadvantages: In the solution described above, the power output needs to be bound to the host mode; or, the power input needs to be bound to the Device mode. That is, in the existing implementing solution, the power input or output of a terminal device is restricted by the OTG working mode binding of the terminal device.

Terminal device and power supply method for terminal device


A spindle drive for a member to be driven includes a driven spindle with a longitudinal axis extending through a spindle nut. The spindle drive                includes the spindle nut having a pusher dog with first and second contact surfaces for driving the member. The contact surfaces are oriented in opposite directions to each other along the longitudinal axis of the spindle.        First and second drive surfaces are provided, facing each other and spaced apart from each other along the longitudinal axis of the spindle.        A distance between the two drive surfaces exceeds a distance between the contact surfaces. The spindle drive further includes        an actuator provided connected to the spindle nut for actuating another device, when the pusher dog between the drive surfaces is being displaced.

Usually, the spindle nut is connected to the door wing via the pusher dog, so that the door wing opens or closes an open door when the spindle is being rotated. Besides movement of the door wing, other measures are often required or desirable, for example separately locking or opening the door wing, respectively. For this, separate locking members are commonly used, which are operated via work cable or linkages. Alternatively, locking may also be done via the engine brake of the spindle drive. All systems require additional construction space and are high in cost and maintenance.


An electrosurgical coagulator (10) has a hollow elongate tube (20), insulation material (30) covering a major portion of the tube (20), a handle (40) of molding material covering a proximal section of the tube (20) and insulation material (30), a power cord (50) electrically connected to the tube (20), and a contact pin (52) terminating the power cord (50) for attachment to an external power supply (60). The tube (20), insulation (30), and handle (40) are coaxial; the handle (40) extends furthest proximally and terminates in a fitting (42) that is engageable with an external suction source (70). The tube (20) has a distal portion (22) for contacting to bleeding tissue and coagulating the same, the distal portion being beveled and having a notch (25) for superior resolution and ease of positioning, clog prevention, and ease of cleaning.

Electrosurgical devices for coagulating bleeding tissue have been available for some time. Most generally, such devices include a hollow conductive tube having an insulating coating over all but a most distal tube portion, so that the distal tube portion forms a generally annular ablating electrode; a hollow insulating handle coaxially surrounding the tube; a suction source attached to a proximal portion of the tube for evacuating excess blood and smoke from the surgical site; and wire electrical connectors attached to a power source for electrically activating the electrode. Such a device is described in, for example, U.S. Pat. No. 4,932,952 (Wojciechowicz, Jr., 1990).
Hemostasis in the nose can be desirable to treat a severe nosebleed, and to close surgically created wounds in the nose. None of the electrosurgical coagulation devices known to the inventor have been engineered with the particular problems associated with nasal hemostasis. While known electrosurgical devices are used to effect nasal hemostasis, such devices have not been optimized. In particular, the electrodes do not provide for precision coagulation. The generally ring-shaped electrodes have a circular cross section and therefore do not allow for selective ablation except by repositioning the entire device--stated another way, the circular electrodes are blunt and do not provide highly selective control. While electrosurgical knives are known (see for example U.S. Pat. No. 4,960,419 (Rosenberg, 1990), attaching a separate blade to a suction tube increases the manufacturing complexity as compared to the above described method of electrically activating a conductive tube so that the tube is both an electrode and a suction element. Other shaped electrosurgical tips are disclosed in U.S. Pat. No. 5,267,994--again, such tips are physically distinct from a suction tube and are therefore more complex and may be less reliable than the simpler cylindrical device first described above. A tip having more precision than the cylindrical shape, while maintaining its essential simplicity and reliability, will provide an improved coagulation device.
Electrosurgical suction coagulators can clog with blood or tissue during operation, interrupting the hemostasis procedure and requiring additional effort by the operating physician and staff. A venting port in the handle of a device may reduce clogging, but does not prevent it. See Wojciechowicz, Jr. for a description of such ports. Ventilation ports also hinder 360 degree operation of a device, in that a physician cannot easily rotate a device while maintaining a finger over the port.
A coagulator that is more postionalble, more accessible to a tangential passage, less prone to clogging, and easier to clean if clogged than known coagulators is therefore a welcome advance in the art, particularly when such benefits are realized in a rugged, reliable, and relatively simple design.


An accessory drive tensioner assembly may include a bracket assembly, a fastener and a tensioner hub. The bracket assembly may include first and second bearings axially spaced from one another. The fastener may extend through the first and second bearings to rotationally couple the bracket assembly to an engine structure and may define a rotational axis for the bracket assembly. The tensioner hub may be coupled to the bracket assembly and may be located axially between the first and second bearings.

This section provides background information related to the present disclosure which is not necessarily prior art.
Engine assemblies may include belt tensioning mechanisms to maintain tension on a belt engaged with rotationally driven engine components. During operation, the load on the belt may vary based on drive requirements of the rotationally driven components. The tensioning mechanism may include a tensioner arm having a first end rotationally coupled to a bracket and a second end having a tensioner hub coupled thereto. The bracket may include a bearing rotationally supporting the bracket relative to an engine structure. The tensioner arm may be rotationally biased to displace the tensioner hub toward the bearing during operation. However, the bearing may be in the same plane as the tensioner hub and belt and may limit travel of the tensioner hub.


A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.

Silicon Carbide (SiC) power MOSFETs are expected to enable a significant improvement in efficiency of power converters across different application areas. However, comprehensively understanding and improving their reliability remains an ongoing challenge. To this end, standard accelerated aging tests were often used to proactively test long term device reliability within a short duration. Among the standard tests, DC power cycling was widely used to accelerate package related aging mechanisms in power MOSFETs. Bond-wire heel cracking, bond-wire liftoff and die attach solder layer delamination were the common failure modes observed in this test. In addition to the above modes, power MOSFETs could also fail due to gate bond-wire liftoff or cracking leading to a gate-open failure. The consequent loss of gate control can lead to unwanted drain to source conduction, large increase in threshold voltage or open circuit failure of device.

Systems, circuits, and methods to detect gate-open failures in MOS based insulated gate transistors

Board of Regents, The University of Texas System


A liquid crystal display device includes a plurality of data lines arranged along a first direction on a substrate, a plurality of gate lines arranged a second direction perpendicular to the first direction on the substrate to define a plurality of pixel regions, each of the gate lines having at least one first set of protrusions and depressions, a driving device within each of the pixel regions, a pixel electrode within each of the pixel regions, and a metal layer overlapping each of the gate lines to create a storage capacitor.

1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and in particular to a liquid crystal display device and a method of fabricating a liquid crystal display device.
2. Description of the Related Art
In display devices, particularly, in flat panel display devices, such as liquid crystal display devices, active devices, such as a thin film transistors (TFTs) are arranged within pixel regions to drive the display device using an active matrix driving method. In the active matrix driving method, the active devices are disposed within each pixel region and are arranged in a matrix configuration to drive corresponding pixels.
FIG. 1 is a plan view a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display device 1 includes an N×M-number of pixels arranged along horizontal and vertical directions, wherein each pixel includes a TFT 10 formed at a cross region of a gate line 3 for receiving a scan signal from an external driving circuit and a data line 5 for receiving an image signal. The TFT 10 includes a gate electrode 12 connected to the gate line 3, a semiconductor layer 14 on the gate electrode 12 that is activated by the scan signal supplied to the gate electrode 12, and a source electrode 16 and a drain electrode 17 on the semiconductor layer 14. A pixel electrode 28 is formed within a display portion of the pixel region, and is connected to the drain electrode 17 to supply the image signal to a liquid crystal material layer (not shown). In addition, a storage capacitor metal layer 7 is formed to overlap the gate line 3 and is arranged along the horizontal direction of the gate line 3 to provide a storage capacitance for the liquid crystal display device 1.
FIG. 2 is a cross sectional view along I-I′ of FIG. 1 according to the related art. In FIG. 2, the gate electrode 12 of the TFT 10 (in FIG. 1) and the gate line 3 are disposed on a first substrate 20, which is made of a transparent insulating material, such as glass, and a gate insulating layer 22 is deposited over an entire surface of the first substrate 20. The semiconductor layer 14 is formed on the gate insulating layer 22, and the source electrode 16 and the drain electrode 17 are formed thereon to form the TFT 10 (in FIG. 1). In addition, the storage capacitor metal layer 7 is disposed on the gate insulating layer 22 so that the gate insulating layer 22 is sandwiched between the storage capacitor metal layer 7 and the gate line 3 to create the storage capacitance.
A passivation layer 24 is deposited over an entire surface of the first substrate 20, and the pixel electrode 27, which is made of a transparent electrode, such as indium tin oxide (ITO), is formed on the passivation layer 24. In addition, a contact hole 27 is formed in the passivation layer 24 to electrically interconnect the drain electrode 17 of the TFT 10 (in FIG. 1) and the pixel electrode 28.
In FIG. 2, a black matrix 32 and a color filter layer 34 are formed on a second substrate 30. The black matrix 32 is formed within a portion the TFT 10 (in FIG. 1), and a portion of the black matrix 32 is formed between adjacent pixels (i.e., the gate line 3 and regions of the data line 5) to block light within regions where liquid crystal molecules of the liquid crystal material layer 40 are not activated, i.e., non-display regions. The color filter layer 34 includes red (R), blue (B), and green (G) color filter elements.
In general, the storage capacitance of the liquid crystal display device 1 improves sustaining characteristics of the voltage supplied to liquid crystal material layer 40, thereby stabilizing gray levels and reducing flicker and generation of residual images. Accordingly, storage capacitance of the liquid crystal display device is considered very important. In FIG. 2, the gate insulating layer 22 is sandwiched between overlapping portions of the gate line 3 and the metal layer 7, thereby creating the storage capacitance. Accordingly, an amount of the storage capacitance can be controlled by adjusting the area, i.e., width and length of the metal layer 7, of overlap between the gate line 3 and the metal layer 7.
With the advent of high resolution-liquid crystal display devices applicable of displaying high picture quality images, such as the high definition TVs (HDTVs), a size of each pixel should be very small. However, the overlap between the metal layer 7 and the gate line 3 is limited so as not to be greater than a set length. Accordingly, the overlap region of the gate line 3 and the metal layer 7 may be limited.
In order to generate sufficient amounts of the storage capacitance, the overlap region between the gate line 3 and the metal layer 7 is increased by increasing the widths of the gate line 3 and the metal layer 7 (since the length of the metal layer 7 is limited). Alternatively, an additional storage capacitance is created by forming two storage capacitor metal layers at other regions of a pixel (i.e., a central region of a pixel) to overlap with the gate line 3 even with the gate insulating layer remaining therebetween. However, increasing the width of the gate line 3 or forming the second metal layer reduces aperture ratio.

Liquid crystal display device and method of fabricating the same