The present invention is generally directed to improved methods, structures and systems for interfacing microfluidic devices with ancillary systems that are used in conjunction with such devices. These systems typically include control and monitoring systems for controlling the performance of the processes carried out within the device, e.g., controlling internal fluid transport and direction, monitoring and controlling environmental conditions and monitoring results of the processes performed, e.g., detection.

Despite the advancements in the fields of microfluidics, microfabrication and the like, there remains a fundamental problem with the implementation of these technologies in achieving their full potential. Specifically, although microfluidic systems are readily applicable to high throughput, low volume, automatable chemical and biochemical analyses and syntheses, many of the advantages gained through the use of microfluidic systems are lost through the lack of interfacing systems that are capable of functioning at the horizons of these microfluidic systems. For example, one of the major advantages of these microfluidic systems is the ability to perform operations using extremely small fluid volumes, thereby requiring smaller amounts of potentially valuable reagents and/or samples. However, although a microfluidic system may be capable of operating with fluid volumes in the nanoliter range, the lack of fluid handling systems capable of delivering such volumes to these microfluidic systems renders this advantage substantially unrealized. Specifically, the user is still required to utilize reagents and/or samples in the 1 to 10 .mu.l range.
One example of a fluidic interface which addresses these problems, namely, the introduction of samples and other fluids into microfluidic analytical systems, is described in commonly assigned U.S. application Ser. No. 08/671,986, filed Jun. 28, 1996, now U.S. Pat. No. 5,779,868 and incorporated herein by reference. In brief, the described system includes an electropipettor interfaced with the channels of a microfluidic device, for electrokinetically introducing very small volumes of samples or other materials into the microfluidic device.
In addition to fluidic interfaces, microfluidic systems also require additional device:world interfaces, including an interface between the device and the detection, sensing or monitoring means that are utilized with the system. Also required are interfaces between the device and the systems that control the operation of the device, such as systems that control fluid direction and transport within the device, and/or environmental conditions present within or around the device, and the like.
Microfluidic devices previously described in the literature have generally included only crude device:world interfaces which severely limited or eliminated a substantial proportion of the promised benefits of microfluidic systems, including automatability, ease of use, low volume and high throughput, which have been the goals of these systems.
Accordingly, there exists a need in the art for improved interfaces between microfluidic devices and the ancillary systems that are utilized with these microfluidic systems, such that these microfluidic systems can realize a greater proportion of their promised benefits. The present invention provides a solution to many of these and other problems.

Controller/detector interfaces for microfluidic systems


An omnidirectional speaker system includes woofer and tweeter speakers mounted in a concave, curved upper fabricated of a relatively hard shell exterior and a foam interior, preferably plastic. Beneath the upper housing is a base, including a generally conical phase compensation plug which disperses the sound waves equally in all directions through a circumferential aperture between the upper housing and base. In a preferred embodiment, the cross-sectional shape of the upper housing is parabolic and the cross-sectional shape of the phase compensation plug is hyperbolic.

The prior art has not provided an outdoor speaker system which projects a high-fidelity sound throughout a 360.degree. angle in a horizontal plane; which is vandal, theft and weather-proof; and which is relatively inexpensive to manufacture. U.S. Pat. No. 4,574,906 to White et al. discloses an outdoor speaker which includes downwardly directed low-frequency (woofer) and high-frequency (tweeter) speaker cones and generates sound throughout a 360.degree. horizontal angle. However, the speaker enclosure is fabricated with relatively thin plastic, and a sound absorbing material must be placed in the hollow cavity above the woofer to suppress any standing and reflective waves and reduce cabinet resonances. This adversely affects the quality and fidelity of the sound produced
U.S. Pat. No. 3,326,321 to Valuch describes an omnidirectional speaker system with an upwardly facing tweeter and a downwardly facing woofer. Apart from separating the high-frequency and low-frequency sound waves in an undesirable manner, the speaker system is vulnerable to vandalism and weather and is therefore not suitable for outdoor use.


Provided is a locking plate system for treatment of a distal radius fracture including a locking plate (4) that is a flat laminate of intermediate molding materials that includes carbon fibers as a reinforcing material and thermoplastic resin as a matrix; a screw anchor (5) having a shaft portion (10) which has a principal thread (13) achieving a self-tapping action formed thereon and an outer circumference of a head portion of the screw anchor (5) which has an auxiliary thread (13) achieving a self-tapping action tapped thereon; and a through-hole (6) in the radius locking plate (4), which allows the radius main body (3) and the fractured bone piece (2) to be threadably fixed to the radius locking plate (4) and having a diameter that is oversized relative to the principal thread (11), and that is undersized relative to the auxiliary thread (13).

Typical parts tending to suffer a fracture due to a brittle-bone disease include a humerus, a radius, a vertebrae, and a femur, and fractures of these bones are called "humeral neck fracture", "distal radius fracture", "vertebral fracture", and "femoral neck fracture". When a person falls down due to stumbling or the like, distal radius fractures are caused by a fall on an outstretched hand with the wrist in dorsi-flection or palmar-flexion. A radius is a tubular bone that extends from an elbow to a wrist side by side with an ulna and that has a bone marrow cavity present therein. As depicted in FIG. 29(a), the ulna 51 is positioned on the side of the little finger (on the left) and the radius 1 is positioned on the side of the thumb (on the right).
The distal tip of the ulna has thereon a styloid process that protrudes toward the side of the little finger, and the distal tip of the radius also has thereon a styloid process 52 that protrudes toward the side of the thumb. The radius is somewhat shorter than the ulna while the radius is thicker than the ulna and has a teardrop portion defining recess (which is often referred to as "teardrop recess") 53 depicted in FIG. 29(b) formed on the palmer side due to a protrusion of a lunate bone fossa positioned on side opposite to that of the styloid process. The teardrop constitutes an important portion that functions as a portion to receive a load to the wrist.
The radius extends from the teardrop recess to the diaphysis with a substantially rectangular column-like cross-section, resulting in a complicated shape. Generally, there exists an individual variation in the morphology of bones of a human body and in the same way exists an individual variation in the morphology of teardrop recess 53 as depicted in FIG. 30.
In a surgical operation for a fracture of the distal tip, the attachment of the radius locking plate is not therefore easy for the operator so that it matches its shape of the radius locking plate with the shape of the teardrop recess and the regions in front and in the back thereof. A flexor tendon failure is remarkably highly likely to occur when, on the radius distal tip, a distal portion of the radius locking plate or the vicinity thereof interferes with the thumb flexor tendon that extends close to the palmer side of the distal radius.
The radius locking plate replaces a splint and a cast made of plaster or an FRP (fiber reinforced plastic) that each fix a limb or a joint from the outside of the fracture region. This is a plate to be directly attached to the radius that can be explored through a volar incision at the wrist, and this plate has a length of 5 cm to 6 cm to have a size capable of being implanted in a living body. This plate establishes robust fixation, which also enables early functional recovery.
Titanium, an alloy thereof, or the like that is strong and lightweight, and that is qualified to have high body safety or biocompatibility is used for the radius locking plate to be implanted in a body. When it is attempted to produce the radius locking plate as a custom-made optimal product of metal, a unique molding mold is necessary that is matched with the shape and the size of bones of each individual.
In this manufacturing scenario, significant increase in production cost and lead time are inevitable. The plate is usually produced as a ready-made product to have those of typical sizes lined up, and reduction of the price of the product is thereby facilitated. In a surgical operation, the plate best matching for the individual bone is employed from the line-up, and any individual perfect fitting cannot therefore be expected.
A practice like the above is also executed for a resin plate. Patent Document 1 describes an example of use of PEEK with which the body safety can be secured. During a surgical operation executed under image intensifier (x-ray) control, a metal plate 54 has an advantage that the metal plate 54 can be clearly perceived as depicted in FIG. 31 while the metal plate 54 has a disadvantage that the affected site is hidden thereby. When the resin plate is employed, the X-ray transmits through it, which enables the position and the orientation of a fractured bone piece to be easily perceived and the affected site can therefore be meticulously cared.
The radius locking plate maintains the fracture reduction, and integrally fixes the radius main body and the fractured bone piece to each other through the plate using some screw anchors. The screw anchors each need to be a hard and strong screw anchor that can laterally self-tap the radius that includes the compact cortical bone, and the cancellous bone in the bone marrow cavity. In many cases, the screw anchors are each made of titanium or an alloy thereof similarly to the radius locking plate.
Through-holes each for the screw anchor to advance in the radius are provided in the radius locking plate. When a large portion of the head portion of the screw anchor remains outside the plate, this causes local pressing or local grazing on the flexor tendon. Necessary is at least a head portion receiving part in each of the holes so as to sink the head portion in the through-hole to accommodate the head portion therein and to prevent any falling out of the anchor. This can be coped with by simply forming a stepwise recess while introduction of a thread mechanism is necessary in the lower half portion of the through-hole (hereinafter, referred to as "in-hole thread").
A thread (hereinafter, referred to as "outer circumference thread") to be screw-fixed to the in-hole thread is naturally formed on the outer circumference of the head portion of the screw anchor. Enabled is the block of any falling out of the anchor toward the side of the radius as well as any reverse-falling out toward the palmer side. Examples of this technique are described in Patent Document 2 and Patent Document 3.
The radius locking plate has a thickness of, for example, 2 mm to 3 mm. When the radius locking plate is made of metal, the disposition of the in-hole thread is not impossible at all. It may be desired that the axis line of the screw anchor directed to the point to which the screw anchor is advanced is displaced from or inclined against the axis line of the in-hole thread. In this case, any falling out of the anchor can be avoided when substantial engagement is achieved between the outer circumference thread and the in-hole thread. Some Patent Documents listed below describe the means for the above.
FIG. 32 depicts the state where the enveloping surface of the tooth tips lining on and beneath the outer circumference thread is formed to be a partial spherical surface and the tooth tip enveloping surface of the in-hole thread is also formed to be a partial spherical surface. These examples are described in Patent Document 3 and Patent Document 4. A recess 55 in the center of each of FIGS. 32(a), 32(b), and 32(c) has a petal-like shape or a hexagonal shape seen as a planar view, and is a wrench hole to rotate the screw anchor.
FIG. 33 depicts the state where the tooth circumference direction of the in-hole thread 56 is formed to be intermittent, and these examples are described in Patent Document 1 and Patent Document 3. FIG. 34 depicts dual holes 57 each having therein a threaded hole and a non-threaded hole partially overlapping with each other, and the dual holes 57 are described in Patent Document 3 and Patent Document 5.
Any one of the above intends to cause the flexibility to be achieved to enable some degree of variation of the direction of the advancement of the screw anchor during a surgical operation. When the in-hole thread mechanism is introduced in the PEEK resin plate, as depicted in FIG. 33(c), a metal thread insert 58 having a tooth circumference direction intermittent thread formed thereon is fitted to be fixed (See Patent Document 1). This thread insert is thinner than the plate, resulting in that disposition of the intermittent thread is not easy or costs remarkably high.
For hard threads each made of titanium or the like, structurally allowed looseness can be used by the non-tooth portion while a change of engagement to vary the orientation of the screw anchor is not necessarily made smoothly. It is not easy to advance the screw anchor in the desired direction. With the dual hole, when the one hole of the dual hole is inappropriate, the other hole copes with the situation. In the case where the radius locking plate is removed, when the engagement of the metal threads is robust, a large operation power is necessary for releasing the screw-fixation and this aggravates the operator. In any case, the operator is forced to use high-level techniques and high-level skills to achieve the engagement to vary the advancement direction.

Locking plate system for treatment of distal radius fracture

NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY


A spring system in particular for upholstery and/or mattresses of push-carriage seats, furniture for sitting on or lying on or the like, having a plurality of successively spaced-apart slats (20), in particular resilient slats, and having supporting bodies (21) for supporting the slats directly or indirectly on a carrying structure. The bearing points or bearing regions (27) of the slats (20), in which the slats (20) are supported by the supporting bodies (21), are arranged exclusively between the slat ends (31, 32).

1. Technical Field
The invention relates to a spring system, in particular for upholstery and/or mattresses of push-carriage seats, furniture for sitting on or lying on or the like, having a plurality of successively spaced-apart slats, in particular resilient slats, and having supporting bodies for supporting the slats directly or indirectly on a carrying structure.
2. Related Art
Push-carriage seats and furniture for sitting on or lying on usually have a spring system comprising a so-called slatted base. The slatted base of the spring system has a plurality of slats, in particular resilient slats, located one beside the other at parallel spacings. The resilient slats are usually connected by supporting bodies to longitudinal members of a rectangular frame, which is part of the spring system. Various embodiments of supporting bodies are known in the prior art. In all of these embodiments, the ends of the resilient slats, arranged on opposite sides, are supported on the frame by the supporting bodies. This type of support results in the slat ends being secured in spatial terms, but at least in the movement capability of the slat ends being restricted to a considerable extent. Furthermore, an external frame, on the longitudinal members of which the slat ends are supported, is necessary in each case.

Spring system for upholstery, mattresses or the like


A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.

Memory cells of a dynamic random access memory (DRAM) generally comprise a storage capacitor for storing an electrical charge which represents information to be stored, and an access transistor connected to the storage capacitor. The access transistor comprises first and a second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The transistor usually is at least partially formed in a semiconductor substrate. The portion in which the transistor is formed generally is denoted as the active area. The gate electrode forms part of a word line, and the gate electrode is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out. In particular, the information is read out to a corresponding bit line via a bit line contact.
In currently-used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends into the substrate in a direction perpendicular to the substrate surface. According to another implementation of a DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
Generally, a DRAM memory cell array having a higher packaging density is desirable. For example U.S. Pat. No. 6,419,948, the disclosure of which is incorporated herein by reference in its entirety, discloses a memory cell array in which the active area is formed as a continuous line. The active area line and the bit line are formed as waving lines, so that one bit line and one corresponding active area line intersect at many points. According to this layout, the memory cells can have an area of about 6 F2, wherein F denotes the minimum pitch according to the technology used.
In addition, U.S. Pat. No. 6,545,904, the disclosure of which is incorporated herein by reference in its entirety, discloses a memory cell including an access transistor and a storage capacitor which can be formed so as to implement a 6 F2 (6F*F) DRAM array. In particular, two neighboring access transistors are arranged, so that they have one common bit line contact. In addition, neighboring access transistors formed on a single active area line are electrically isolated from each other by an isolation gate line.
DE 199 28 781 C1 discloses a 6 F2 memory cell in which two adjacent memory cells share one common bit line contact. Two neighboring pairs of memory cells which are assigned to one active area line are separated and electrically isolated from each other by a groove which is filled with an isolating material.
Furthermore, U.S. Pat. No. 5,502,320, the disclosure of which is incorporated herein by reference in its entirety, discloses a memory cell array in which transistors are formed in continuous active area lines. The active area lines are arranged in parallel with the bit lines. Two adjacent pairs of neighboring memory cells are separated and isolated from each other by applying an appropriate voltage to isolation gate lines which are arranged between the two adjacent pairs of memory cells. The word lines and the isolation gate lines are implemented as buried word lines and buried isolation gate lines, respectively.


A method and system are disclosed that provide a significant improvement for securely selecting a subset of available cryptographic functionality in a system. This is implemented by using the highest level of cryptography available in a system to encrypt the system initialization data used to select, enable, disable, or configure cryptographic features in a crypto chip. The system decrypts the encrypted data by momentarily fully enabling the crypto chip during the boot process, and using a known, system-unique, and fixed seed to generate the private key to use for decryption. The seed used is the system's MAC address (L2 LAN address—medium access control). Alternatively, the system could include a one-time use decryption-only algorithm in the boot strap code itself.

1. Field of the Invention
This invention pertains generally to computer products that have encryption technology as part of the product being sold. More particularly this invention is directed to a system and method for selecting a particular level of cryptographic support when the base product provides multiple levels of cryptographic support.
2. The Prior Art
Cryptographic packages as offered in computer systems, or as part of a component sale, are well known. Cryptographic packages may consist of several types, including two-way encryption techniques based on DES, 3DES, and RC4; asymmetric encryption techniques used for public key encrypting such as RSA, DH, and DSA; and, authentication techniques based on SHA-1 and MD5.
All such solutions share a substantial number of components, be they implemented in software or hardware. Because all the cryptographic packages share so many components in common, they are implemented and offered as a single package from which one chooses which components, or level of cryptography, to enable or use. In a software implementation, the desired cryptographic support may be compiled during a system build or selectively invoked using various system initialization or configuration parameters. In a hardware implementation a chip is typically enabled for a certain type of cryptographic support during system initialization using system boot parameters.
The problem is how to provide a high degree of reliability on enabling or disabling certain cryptographic features (capabilities). This is important for several reasons. One reason is export control. Some countries are not allowed to receive certain levels of cryptography. Another reason is only allowing customers to use what they paid for. Since cryptographic implementations of all types have multiple levels of support built into them, enabling only some features in a highly reliable manner is a critical concern.
Software implementations have the advantage that they can be custom built. However, that solution also has overwhelmingly severe disadvantages. First, all known implementations of cryptographic features are notoriously compute intensive. If the cryptography in use is software based, and the system is to be used for anything other than just encryption and decryption, system performance will always degrade to a very noticeable degree. This is unacceptable, so software solutions are not as common except in dedicated security systems. In addition to poor performance, using different builds for different cryptographic support results in severe logistical problems as the number of releases grows. Thus, the only pragmatic solution is to use some kind of system initialization parameter.
Hardware implementations are far more common than software solutions because of their speed. Hardware implementations of cryptographic functions result in almost no discernable downgrade in overall system performance. Unlike software implementations, a hardware implementation will always have all the normally desired cryptographic capabilities built into one chip. Thus, the only solution for selecting a subset of those capabilities lies with selectively enabling or disabling them during system initialization.
Setting aside the software solution involving selective builds due to its high cost (extremely difficult logistical support, resulting in high costs, associated with different builds for a large number of small groups of customers), it is readily seen that the best commercially viable solution involves enabling or disabling cryptographic features using some kind of system initialization or configuration data.
Up to now, there has been little protection from clever people doing reverse engineering on a product to find out how and where system initialization parameters are kept and used. Thus, there is a real need for any method or system that would provide better protection of cryptographic enabling or disabling features that must be used to configure systems according to the country sold, or a customers purchasing decision.

Enabling cryptographic features in a cryptographic device using MAC addresses


Gases and liquid products of the cracking zone of a ethylene production plant fractionated in a demethanizer to from a dilute ethylene stream containing about 5 to about 40 percent of the ethylene contained in the feed. The dilute ethylene is feed to an ethylbenzene plant and reacts with impure benzene. The product ethylbenzene is normally converted to styrene.

Conventional ethylene production consists of the following key process operation:
(a) Thermal cracking, in presence of dilution steam, of C.sub.2 + hydrocarbon at about 15-25 psig and 1,500.degree.-1,600.degree. F. to form cracked gas containing ethylene in an amount of 25-40 wt % (and up to 80 wt % for net ethane feed), and other by products such as propylene, acetylene, hydrogen, methane and C.sub.3 + products. The thermal section includes cracked gas cooling, steam generation and C.sub.9 + hydrocarbon condensation. Traces of CO, CO.sub.2 and H.sub.2 S are formed in the cracking. PA1 (b) Cracked gas compression to 400-600 psig, traces of CO.sub.2 and H.sub.2 S removal, drying, and bulk C.sub.4 + product recovery by condensation at about 100.degree. F., using cooling water. PA1 (c) Acetylene conversion to ethylene via selective hydrogenation, chill down and cryogenic recovery of ethylene by fractionation at below -30.degree. F. PA1 (d) Recovery of propylene, propane and C.sub.4 + hydrocarbons by warm distillation at above 80.degree. F. PA1 (e) Cascade refrigeration of ethylene and propylene refrigerants, to support the above, down to a temperature of below -100.degree. F. PA1 (f) Methane refrigeration and or expander to reach refrigeration below -180.degree. F. PA1 (g) In case of Naphtha feed, residual liquid products from cracking such as pyrolysis fuel oil and pyrolysis gasoline, which are rich in aromatics, are selectively hydrotreated for di-olefin and olefin saturation.
Efficient cryogenic recovery of the ethylene is a key element in design of ethylene plants. The motive power for compression and refrigeration, and consequently the capital cost escalates rapidly as the rate of ethylene recovery increases. For example, the typical ethylene recovery of 99.7-99.9% requires much higher investment and 50% more refrigeration energy in the demethanizer as compared with 95% rate of ethylene recovery. Thus, reduction of the marginal refrigeration required for ethylene recovery by using 95% or lower recovery could substantially improve the overall economics of the ethylene plant, if a down stream outlet, other than fuel gas, is found for the 5% more of the unrecovered gaseous ethylene. Normally the unrecovered ethylene 0.1-0.3% is routed with the methane to the fuel gas system. However, the value of ethylene as fuel is only about 15-20% of its equivalent value as downstream product. The ethylene product is commonly used as a feedstock to many downstream processing including ethylbenzene. Production of ethylbenzene from pure ethylene against dilute ethylene feed, although somewhat advantageous from a stand point of the ethylbenzene plant alone, is not an absolute requirement and its relative cost impact is rather marginal as compared with the estimated saving in the ethylene plant.
In recent years, processes for producing ethylbenzene from dilute ethylene feed streams have been developed by Badger, a subsidiary of Raytheon, ABB Lummus Global/CDTech, Sinopec and others. The key driving forces behind these new developments are the objectives of using offgases from fluid catalytic crackings (FCC) in petroleum refining. These offgases are at 150-250 psig and typically contain 8-18 vol % of ethylene, 3-9 vol %, of propylene and 12-20% hydrogen.
Limited integration of ethylbenzene and ethylene production was experienced in a number of locations including El Paso Products (Now Huntsman Chemical) in Odessa, Tex., where rich ethylene rich stream at 40 psig is compressed to 550 psig and feeds an ethylbenzene plant.
This invention combines the known technologies as developed for producing ethylbenzene from refinery FCC offgases, and for producing ethylene by conventional cracking of hydrocarbon feeds.

Combination process for manufacturing ethylene ethylbenzene and styrene


A movement detection and control device has a lens frame holding a lens. The lens frame is movable in a direction of an optical axis of the lens. A revolving cam moves the lens frame in the direction of the optical axis. A driving source drives the cam. A pattern-rotating member having patterns for pulse generation, is rotated by the driving source. A detector detects the patterns, and generates pulse signals in response to driving by the driving source. A control circuit counts the pulse signals, and drives the driving source in a controlled manner to move the lens frame by a predetermined amount. The revolving cam is provided with a light-sealing member for intercepting the detector from generating pulse signals in an area where the cam starts or finishes its movement.

1. Field of the Invention
This invention relates to a movement detection and control device and, more particularly, to a movement detection and control device for detecting and controlling movement of a lens frame driven by a driving source.
2. Related Background Art
In a camera or equivalent apparatus for taking photographs, various proposals have been made and also put into practice in the past with respect to a mechanism and the like for automatically providing focus adjustment, exposure adjustment, and so forth.
For example, an exposure and focus adjustment device in a camera as disclosed in the published Japanese Utility Model Application Examined No. 5-31609 is constructed to permit the driving force of a rotational driving source (motor) to be selectively transmitted to a focus-adjusting mechanism and an exposure-adjusting mechanism via a differential gear mechanism. The above device is provided with a pulse-generating device, an AF switch, an AE switch, and so forth in order that unidirectional rotation of the motor provides driving in a controlled manner. The pulse-generating device is formed by both a mask plate having a plurality of slits and a photo-interruptor, thereby generating a pulse signal. The AF switch takes off a positional signal of a gear for automatic focusing from the pulse signal. The AE switch takes off a positional signal of a gear for automatic exposure from the pulse signal.
In addition, a lens mount disclosed in the published Japanese Patent Application Unexamined No. 6-242484 is a lens mount with a shutter device. The lens mount is provided with a photo-interruptor for automatic focusing, a photo-interruptor for automatic exposure, and so forth in order that bidirectional rotation of a motor provides driving in a controlled manner. The former photo-interruptor measures a moving distance of a gang of focusing lenses, while the latter photo-interruptor detects movement of a shutter vane-driving lever. The shutter vane-driving lever is driven by a plunger solenoid-driving device, and drives a shutter vane.
Turning back to the foregoing Application No. 5-31609, since a means disclosed therein requires a switch for taking off the positional signal, there exists a problem of an increase in manufacturing cost.
With further reference to the foregoing Application No. 6-242484, a means disclosed therein includes a cam ring for moving the gang of focusing lenses. The cam ring is once reversed at an initial step by the motor being rotated in one direction, whereby the cam ring is brought into abutting contact with a stopper. This state is set to be an initial position of the cam ring. The cam ring is thereafter brought into normal rotation from the initial position by the motor being rotated in the other direction. As a result, focusing drive is effected, while the photo-interruptor for automatic focusing is caused to provide detection. In short, bidirectional rotation of the motor provides driving in a controlled manner. This results in a complicated motor control circuit and a complicated sequence and the like, which may add to manufacturing costs.


A phase shifter receiving an input signal and producing two output signals having a 90.degree. phase difference from each other includes first and second input nodes for respectively receiving first and second signals having opposite phases; a first serial connection of a first resistor and a second resistor at a resistor node, the first and second resistors having the same resistance values, a first end of the first serial connection being connected to the first input node; a second serial connection of a first capacitor and a second capacitor at a capacitor node, the first and second capacitors having the same capacitance values, the second serial connection being connected between the second end of the first serial connection and the second input node; and first and second output nodes respectively connected to the resistor node and the capacitor node, producing output signals having a 90.degree. phase difference from each other. Output voltages having phases orthogonal to each other can be produced by a single current path with amplitude characteristics similar to those of the conventional 0.degree./90.degree. phase shifter using differential circuits and integrating circuits. The orthogonality is maintained over a wide frequency band as in a conventional phase shifter.

In the field of mobile communication, such as automobile telephone or portable telephone, an analog modulation system, represented by frequency modulation, has been conventionally employed. A digital modulation system has been recently utilized. Accompanying that change, production of an IC circuit for a quaternary modulator as a key device in the modulation section for performing multi-value digital modulation such as QPSK(quaternary phase shift keying) has been of increasing importance.
FIG. 21 is a diagram illustrating a transmitter and a receiver section of a portable telephone as an example of an apparatus using this quadrature modulator.
In FIG. 21, an audio signal converted to an analog signal by the phone receiver 221 is made a digital signal coded by the codec (CODEC) 220 in response to an instruction from the control section 219 and is output to the waveform generating circuit 218. The waveform generating circuit 218 is constituted by a DSP (digital signal processor) 218d, a ROM 218c, D/A converters 218a and 218b. In response to an instruction from the control section 219, it narrows the band of the digital signal input from the CODEC 220 by the DSP 218d, and decomposes the signal into I and Q signals, i.e., two signals having phases 90.degree. different from each other, using waveform data stored in the ROM 218c, and converts these signals to analog signals in the D/A converters 218a and 218b and outputs those analog signals to the quadrature modulator 216. The quadrature modulator 216 performs quadrature modulation of the analog I and Q signals output from the waveform generating circuit 218 using the local oscillator signal output from the frequency synthesizer 217. The quadrature modulated signal is up-converted to a radio frequency by the local oscillation signal output from the frequency synthesizer 215 at the modulator 214 to be output to the high output amplifier 213. The high output amplifier 213 amplifies the output signal of the modulator 214 to a high power output. The output of this amplifier 213 is output to the antenna 211 through the transmit and receive switch 224 to be radiated into space.
On the other hand, the antenna 211 and the antenna 212 constitute a so-called diversity antenna, and upon receipt of electromagnetic waves this diversity antenna supplies an input signal to the receiving part 222. The receiving part 222 amplifies the waves received by this diversity antenna and outputs the same to the demodulation section 223. The demodulation section 223 demodulates the output of the receiving section 222 and outputs the same to the CODEC 220. The CODEC 220 demodulates the digital signal demodulated by the demodulation section 223 to an audio signal and outputs the same to the phone receiver 221.
In this way, in the next generation portable telephone, i.e., so-called codeless telephone or an automobile telephone, a digital transmission system is employed. This digital transmission system does not modulate the frequency of the carrier with an audio signal as in FIG. 22(a), but modulates the phase of the carrier with the audio data as shown in FIG. 22(b).
In this digital transmission system, when phase information is carried on the carrier, the modulation is performed by using the values of (0, .pi./2, .pi., 3.pi./2) which are marked with white round mark .alpha. or the values of (.pi./4, 3.pi./4, 5.pi./4, 7.pi./4) which are marked with black round mark in FIG. 22(c), requiring a quadrature modulator.
FIG. 24 shows a block construction of a quadrature modulator including a 0.degree./90.degree. phase shifter In FIG. 24, reference numeral 1 designates an input buffer which performs waveform reforming of a signal input from the carrier wave input terminal Reference numeral 2 designates a 0.degree./90.degree. phase shifter for separating the signal wave reformed by the input buffer 1 into two signals having phases different by 90.degree.. Reference numeral 3 designates a buffer for wave reforming the output of the phase shifter 3. Reference numeral 4 designates a double balanced mixer which performs double balanced modulation of the base band signal as a signal to be modulated by the output of the buffer 3. The usual balanced mixer is only balanced to the carrier wave, and therefore, the signal to be modulated as well as the carrier wave do not appear at the output side, while a modulating signal such as an audio signal appears at the output side. On the other hand, the double balanced mixer is balanced to the carrier wave as well as to the modulated wave, and therefore only the signal to be modulated appears at the output, and neither of the carrier wave and the modulation wave appear at the output side. Further, reference character BB designates its base band signal input terminal, OUT designates an output signal terminal for the double balanced mixer 4, a, b, and c designate signal lines respectively connecting the input buffer 1 and the 0.degree./90.degree. phase shifter 2, the 0.degree./90.degree. phase shifter 2 and the buffer 3, and the buffer 3 and the double balanced mixer 4, respectively.
Next, a description is given of the operation.
The carrier wave signal input from the carrier wave input terminal IN is wave-reformed by the input buffer 1, and is output to the 0.degree./90.degree. phase shifter 2. In this 0.degree./90.degree. phase shifter 2, the input signal is separated into two series of signals which have phases shifted by 0.degree./90.degree. relative to the input signal, and they are output to the buffer 3. In the buffer 3, the wave-reforming of the input signal is performed in the same way as in the input buffer 1, and is output to the double balanced mixer 4. In the double balanced mixer 4, the base band signal input from the base band signal input terminal BB is used as a signal to be modulated to perform the double balanced modulation, thereby the modulated signal is output from the output signal terminal.
FIG. 23 is a diagram for explaining the operation of the quadrature modulator. In FIG. 23, the carrier wave input signal of cos .omega.t which is input to the 0.degree./90.degree. phase shifter 231 is converted to two signals by the 0.degree./90.degree. phase shifter 231 which are shifted in phase by 0.degree. and 90.degree., respectively, relative to the input signal of cos .omega.t, to be output to the double balanced mixers 232 and 233, respectively. In the double balanced mixers 232 and 233, the base band signals I(t) and Q(t) are respectively input as modulation signals and they are modulated by cos .omega.t and sin .omega.t, respectively, as output signals I(t)cos .omega.t and Q(t)sin .omega.t. These signals are input to the synthesizer circuit 234, thereby a quadrature modulated wave EQU e(t)=I(t)cos .omega.t+Q(t)sin .omega.t
is output.
Here, when it is supposed that I(t)=cos .phi.(t) and Q(t)=-sin .phi.(t), phase modulated waves are obtained as represented by, EQU e(t)=cos .phi.(t) : cos .omega.t-sin .phi.(t) : sin .omega.t=cos (.omega.t+.phi.(t)),
and when this .phi.(t) is given as 0, .pi./2, 3.pi./2, .pi., QPSK (quaternary phase shift keying) modulated wave is obtained.
Here, in this quadrature modulation, the balancing and the orthogonality of carriers, i.e., how close the phase difference is to 90.degree. affects the positions of the black round marks and white round marks in FIG. 22(c), and when the positions of these black round marks and white round marks in FIG. 22(c) are deviated, the quality of the modulation signal is reduced and demodulation is made difficult.
In other words, in the quadrature modulator, when the positions of the black marks and the white marks are deviated, there arises an image component of the modulation signal component, that is, an unrequited mirror image component. The mirror image component is deviated from the carrier wave by a frequency corresponding to the modulated signal, and in order to sufficiently suppress this image component, the preciseness of orthogonality of the carrier in the 0.degree./90.degree. phase shifter, that is, the phase difference of the carrier at precisely 0.degree. and 90.degree., respectively, is important.
The 0.degree./90.degree. phase shifter of such construction is conventionally constructed by using such as delay lines and microwave strip lines. However, there has been arising a necessity of realizing the 0.degree./90.degree. phase shifter also by a construction appropriate for circuit integration of a quadrature modulator in an integrated circuit. In order to realize a quadrature modulator superior in modulation characteristics, how a small-sized 0.degree./90.degree. phase shifter which is strong against variations of elements and appropriate for circuit integration, determines the performance of the IC and the yield thereof.
The phase shifter described in the following is an example of a conventional phase shifter circuit which requires no large chip area for an inductor and can be constructed of only resistors, capacitors, and transistors, and is appropriate for circuit integration.
FIG. 25 illustrates a phase shifter circuit which utilizes an all band pass type circuit as a conventional 0.degree./90.degree. phase shifter, and described in FIG. 1 of "Monolithic RC All-Pass Networks with Constant-Phase-Difference Outputs", on pp. 1533-1537 of "IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. MTT-34, NO. 12".
In FIG. 25, reference character IN1 designates a positive phase signal input terminal to which a positive phase signal of positive phase and negative phase input signals is applied, reference character IN2 designates a negative phase signal input terminal to which the negative phase signal having a phase shift of 180.degree. relative to said positive phase signal is input. Reference numeral V.sub.DD designates a power supply terminal, reference character V.sub.CS designates a constant current source bias terminal, and reference characters OUT1 and OUT2 designate output signal terminals. J1 and J2 designates a pair of differential FETs having the same gate widths, for example 30 .mu.m to 100 .mu.m, to which gates the positive phase signal and the negative phase signal are input, respectively. J3 designates a constant current FET having a drain connected to the commonly connected sources of the differential FETs J1 and J2, R3 designates a resistor connected between the source of the constant current FET J3 and the ground, R1 and R2 designate load resistors having the same resistance values, for example 1 to 3 k.OMEGA., connected between the drains of the differential FETs J1 and J2 and the power supply V.sub.DD.
Further, J4 and J6 designate source follower FETs having drains connected to the power supply terminals V.sub.DD and having gates connected to the terminals of the resistors R1 and R2 at the side opposite to the power supply terminal and which have the same gate widths. J5 and J7 designate constant current FETs having drains connected to the sources of the source follower FETs J4 and J6 and which have the same gate widths. R4 and R5 designate the constant current resistors having the same resistance values connected between the sources of the constant current FETs J5 and J7 and the ground, respectively. Here, the constant current FETs J5 and J7 are provided for increasing the impedance conversion effect due to the source follower FETs J4 and J6, that is, the effect of increasing the input impedance and decreasing the output impedance, and therefore these are not necessarily required. So, these can be omitted and the sources of FETs J4 and J6 may be directly connected to the resistors R4 and R6.
In addition, the FETs J3 to J7 all have gate widths of 50 .mu.m to 100 .mu.m and the resistors R3 to R5 all have resistance values of 200 .OMEGA. to 1 k.OMEGA..
In addition, reference characters Ra and Rb, and Ca and Cb designate resistors, and capacitances which together constitute the 0.degree./90.degree. phase shifter. The resistor Ra and the capacitor Ca are connected in series to each other and the resistor Rb and the capacitor Ca are connected in series to each other, and these two serially connected circuits 25a and 25b are connected between the sources of the source follower FETs J4 and J6, in parallel with each other. The output terminal OUT1 is taken out from the connection node between the resistor Ra and the capacitor Ca and the output terminal OUT2 is taken out from the connection node of the resistor Rb and the capacitor Cb. Reference numerals n4 and n6 designate source nodes of the source follower FETs J4, J6, respectively, and V1, V2 designate voltages of the nodes n4, n6, respectively, and Vout1 and Vout2 designate voltages of the output terminals OUT1 and OUT2, respectively.
In FIG. 25, a differential amplifier circuit 11a comprising the FETs J1, J2, J3 and resistors R1, R2, R3 is provided at a prior stage of the two source followers 11b and 11c comprising the FETs J4, J5 and the resistor R4, and the FETs J6, J7 and the resistor R5, respectively, is only illustrated as means for inputting signals having phases shifted by 180.degree. from each other to the FETs J4 and J6, respectively. The signals input to the input terminals IN1 and IN2 are not necessarily required to be of reverse phases, and either of the signal terminals can be made a reference of a constant voltage.
FIG. 26 is a diagram illustrating vectors of V1, V2(=-V1), and Vout1, Vout2 when the values of the resistors Ra, Rb, and the capacitors Ca, Cb constituting the 0.degree./90.degree. phase shifter 11d are set so that the Vout1 and Vout2 are made orthogonal to each other at the target frequency and .DELTA..phi. in the figure represents a phase difference between signals of the output voltages Vout1 and Vout2.
A description is given of the operation.
The signals input from the input terminals IN1 and IN2 are amplified by the differential amplifiers 11a, the differential outputs thereof are impedance converted to low impedances by the source follower circuit 11b and 11c, respectively, and are output to the 0.degree./90.degree. phase shifter 11d. In this phase shifter 11d, the resistance values of the resistors Ra and Rb and the capacitance values of the capacitors Ca and Cb are set so that two signals having phases orthogonal to each other at a specific frequency are output from the two outputs Vout1 and Vout2, respectively.
From FIG. 26, because the 0.degree./90.degree. phase shifter is of all-band pass type, when, for example, the center frequency is 250 MHz, the amplitudes of Vout1 and Vout2 are equal to the amplitudes of V1 and V2 over a wide band of 180 to 340 MHz, and the Vout1 and Vout 2 are represented as moving on an arc of a circle with diameters of V1 and V2 because the vectors of voltages RaIa and Ia/j.omega.Ca arising at the both ends of the resistors Ra and Rb and the capacitors Ca and Cb, respectively, are orthogonal to each other, and also the vectors RbIb and Ib/j.omega.Cb are mutually orthogonal to each other. Therefore, by setting the values of the resistances Ra, Rb, and the capacitances Ca, Cb, it is possible to output signals having phases deviated by 90.degree. from each other from the output terminals Vout1, Vout2, so that the phase difference .DELTA..phi. produced by Vout1 and Vout2 be 90.degree..
That is, in this 0.degree./90.degree. phase shifter, the voltage vectors Vout1 and Vout2 move on the arc of the circle with the originating point O of the voltage vectors V1 and V2(=-N1), and the triangle .DELTA.1 with the voltage vectors Vout1 and V1 and the triangle .DELTA.2 with the voltage vectors Vout2 and V2 become isosceles triangles. Here, when the Ra, Ca, Rb, Cb are set such that 1/.omega.Ca.multidot.tan 22.5.degree.=Ra and Rb.multidot.tan 22.5.degree.=1/.omega.Cb(.omega.=2.pi. fO : fO is a target frequency), because the angles .phi.1, .phi.2 become 22.5.degree., the .phi.21 produced by the voltage vector V1 and the Vout2 and the angle .phi.12 produced by the voltage vector V2 and the Vout1 become 45.degree.. Thereby, the angle .DELTA..phi. produced by the voltage vector Vout1 and the Vout2 are made 90.degree. and the phases of the output signals Vout1 and Vout2 are made orthogonal to each other.
Even without employing such a setting, by only appropriately setting the resistance values of the resistors Ra and Rb and the capacitance values of Ca and Cb appropriately, the output signals Vout1 and Vout2 can be made orthogonal to each other. This can be accomplished, for example, by setting the values as Ra=650 .OMEGA., Ca=0.6 p F, Rb=280 .OMEGA., Cb=0.25 pF, at frequency fO=950 MHz.
However, in this phase shifter, the Vout1 and Vout2 are generated by two serial connection circuits 25a and 25b, and the current paths generating the Vout1 and Vout2 are provided separately, the frequency band that can maintain a phase shift difference of 90.degree. cannot be made so wide, and, for example, when the center frequency is 250 MHz, the range in which the phase difference of 90.degree. can be maintained is limited to the vicinity of that frequency. In addition, the accuracy of the orthogonality of the separated signals into 0.degree. signal and 90.degree. signal components as a function of variations in the element characteristics in the resistors Ra and Rb and the capacitors Ca and Cb when the circuit is integrated is low.
FIG. 27 is a diagram illustrating an example of a phase shifter according to the prior art that can solve such a problem. In this circuit, by constituting a 0.degree./90.degree. phase shifter of differential circuits and integrating circuits, the problem of low accuracy of the orthogonality as a function of element variations in the circuit of FIG. 25 can be solved.
In FIG. 27, reference character IN designates a single signal input terminal, reference characters J11 and J13 designate source follower circuits which receive the input signal from the signal input terminal at their gates. The gate widths of the source follower FETs are equal to each other and the drains thereof are both connected to the power supply terminal V.sub.DD. J12 and J14 are constant current source FETs having gate widths equal to each other, and to the gates thereof a constant voltage is applied from the constant current source bias terminal V.sub.CS. Here, the FETs J12 and J14 are for strengthening the impedance conversion function of the source follower FETs J11 and J13 and are not necessarily required. Further, the gate widths of the FETs J11 to J14 are, for example, 30 to 50 .mu.m. The R11 and R12 designate resistors connected between the sources of the constant current source FETs J12 and J14 and the ground, respectively, and the resistance values thereof are, for example, 200 .OMEGA. to 1 k.OMEGA.. The Ca and Ra designate a capacitor and a resistor constituting the differential circuit 27a connected between the source node of the source follower FET J11 and the ground. The Rb and Cb designate a resistor and a capacitor constituting the integrating circuit 27b, and they are connected between the source node n3 of the source follower FET J13 and the ground. These resistors Ra and Rb are, for example, both 670 .OMEGA. when the target frequency is 950 MHz, and the capacitances are both, for example, 0.25 pF. The OUT1 is an output signal terminal and this is connected to the connection node of the capacitor Ca and the resistor Ra. The OUT2 is an output signal terminal connected to the connection node of the resistor Rb and the capacitor Cb. The Vi and V2 (=V1) are voltages of the nodes n1 and n3, respectively, and the Vout1 and Vout2 are voltages of the output terminals OUT1 and OUT, respectively.
A description is given of the operation.
A signal input from the signal input terminal IN is impedance converted by the source follower circuit 13a comprising FETs J11, J12, and the resistor R11 and the source follower circuit 13b comprising FETs J13 and J14, and the resistor R12, and they are output to the differential circuit 13c comprising the capacitor Ca and the resistor Ra and the integrating circuit 13d comprising the resistor Rb and the integrating circuit 13d.
FIG. 28 illustrates a vector diagram showing vectors V1, V2(=V1), Vout1, and Vout2 at frequency f=fO when the values of the resistor and the capacitor of the differential circuits 13c and the integrating circuit 13d are set so as to satisfy the following: EQU Ra=Rb=R, EQU Ca=Cb=C EQU fO=1/2.pi. RC
at the frequency fO.
In FIG. 28, .phi.1 represents the phase difference of V1 and Vout1 and .phi.2 represents the phase difference of V1 and Vout1.
At frequency f=fO, the differential circuit 27a has the same values for the absolute value for the voltage vector RaIa due to the voltage difference of the resistor Ra and the absolute value for the voltage vector Ia/j.omega.Ca due to the voltage difference of the capacitor Ca. Those voltage vectors are orthogonal and the triangle .DELTA.11 produced by both vectors and a sum vector of them is a right-angled isosceles triangle, and the output Vout1 advances in its phase .phi.01 by +45.degree. with relative to the phase of the input V1. The integrating circuit 27b has, as in the differential circuit 27a, the same values for the absolute value for the voltage vector RbIb due to the voltage difference of the resistor Rb and the absolute value for the voltage vector Ib/j.omega.Cb due to the voltage difference of the capacitor Cb which voltage. Those vectors are orthogonal and the triangle .DELTA.12 produced by both vectors and a sum vector is a right-angled isosceles triangle and the voltage Vout2 is retarded in its phase by 45.degree. with relative to the phase of the input V1. As a result, the phase difference (.theta.1+.theta.2) between those becomes 90.degree.. However, the amplitudes of the outputs Vout1 and Vout2 are reduced to lower values than the amplitude of the input V1 (=V2) due to the high pass characteristics of the differential circuit 27a and the low pass characteristics of the integrating circuit 27b. In addition, although the amplitudes of Vout1 and Vout2 are different from each other at a frequency other than f=fO, the phase difference therebetween (.theta.1 +.theta.2) is still maintained at 90.degree..
FIG. 29 is a diagram illustrating the amplitude characteristics of the output signals Vout1 and Vout2, as a function of the input frequency of the phase shifter of FIG. 27. FIG. 29 shows that the frequency at which the amplitudes of the Vout1 and Vout2 become equal to each other is only f=fO due to the high pass characteristics of the differential circuit and the low pass characteristics of the integrating circuits.
FIG. 30 shows the vector diagrams of V1 and V2(=V1), Vout1, Vout2 when the resistance values Ra (Rb) constituting the phase shifter in the circuit of FIG. 27 are increased to a value a little larger than the design value R, or when the capacitance value Ca(=Cb) of the capacitor is increased to a value a little larger than the design value C.
In FIG. 30, .theta.1 designates a phase difference between V1 and Vout1, and .theta.2 designates a phase difference between V1 and Vout1.
From FIG. 30, the angle .theta.1 is produced by Vout1 when V1 is small while the angle .theta.2 is produced by Vout2 when V2 is large, and the amplitudes of the Vout1 and Vout2 are different at f=fO while the sum of the phase difference between them, i.e., .theta.1+.theta.2, is kept at 90.degree..
The reason therefor is because the absolute value of the voltage vector RaIa for the resistor Ra constituting the differential circuit 27a and the absolute value of the voltage vector RbIb for the resistor Rb constituting the integrating circuit 27b are equal to each other, and the absolute value of the voltage vector Ia/j.omega.Ca for the capacitor constituting the differential circuit 27a and the absolute value of the voltage vector Ib/j.omega.Cb for the capacitor constituting the integrating circuit 27b are equal to each other because Ra=Rb=R, Ca=Cb=C on an assumption that V1=V2. The right-angled triangle .DELTA.11 constituted by the voltage vector RaIa, the voltage vector Ia/j.omega.Cb, and the voltage vector V1, and the right-angled triangle constituted by the voltage vector RbIb, the voltage vector Ib/j.omega.Cb, and the voltage vector V2 become congruent, and as a result, the angle .phi.1 produced by the voltage vector Ia/j.omega.Ca and the voltage vector V1, and the angle .theta.2 produced by the voltage vector Ib/j.omega.Cb and the voltage vector V2 are equal to each other. The angle .phi.32 produced by the voltage vector RbIb and the voltage vector V2 and the angle .phi.1 produced by the voltage vector RaIa and the voltage vector V1 are equal to each other, resulting in that the angle .theta.1+.theta.2 becomes necessarily 90.degree..
Therefore, this type of phase shifter can be said to have directionality over a wide range and is also resistant to variations in the elements.
In addition, as a conventional phase shifter that can maintain the phase difference between the orthogonal components while employing resistors and capacitors, there is a quadrature modulator disclosed in Japanese Published Patent Application Hei.2-127844, as one other than those illustrated in FIGS. 25 and 27.
FIG. 31 shows a construction of this quadrature modulator. In FIG. 31, reference numeral 311 designates a carrier wave input terminal, reference numeral 312 designates a first mixer for modulating a same phase component, reference numeral 313 designates a second mixer for modulating a quadrature component. The output of the first mixer 312 is connected to the modulation output terminal 316 via the resistive two-terminal circuitry 314. In addition, the output terminal of the second mixer 313 is connected to the modulation wave output terminal 316 via the capacitive two-terminal circuitry 315.
Next, the operation of this quadrature modulator will be described with reference to FIG. 32. First of all, suppose that the carrier wave which is input to the carrier wave input terminal 311 is V1=exp(j.omega.t), the base band signal which is input to the first mixer 312 is VI, and the base band signal which is input to the second mixer 313 is VQ. The output VIo of the first mixer 312 and the output VQo of second mixer 313 are respectively represented as follows: EQU ViO=VI.multidot.V1=VI.multidot.exp(j.omega.t) EQU VQo=VQ.multidot.V1=VQ.multidot.exp(j.omega.t)
In addition, the modulation wave output Vo(t) output from the modulated wave output terminal 316 is represented by the following formula if the resistance value of the resistive two-terminal circuitry 314 is R, the capacitance of the capacitive two-terminal circuitry 315 is C, and the output impedances of the first mixer 312 and the second mixer 313 are sufficiently low; EQU Vo=a1.multidot.V1+a2.multidot.VQ
here
a1=1/ (1+j.omega.CR), PA1 a2=j.omega.CR/ (1+j.omega.CR), PA1 a1=A1.multidot.exp(j.phi.1), PA1 a2=exp(j.phi.2) PA1 A1=1/ (1+(.omega.CR).sup.1/2), PA1 A2=.omega.CR/(1+(.omega.CR).sup.2).sup.1/2 PA1 .phi.1=tan.sup.-1 (-.omega.R), PA1 .phi.2=tan.sup.-1 (1/.omega.CR)
and if these a1 and a2 are expressed in phases, then
here,
The phasers of a1 and a2 move on the circle of diameter 1 as shown in FIG. 32. Then, the phase difference .DELTA..phi. between .phi.1 and .phi.2 becomes, employing a relation of EQU (a2/a1)=(A2/A1).multidot.exp(j(.phi.2-.phi.1))
as follows: ##EQU1## and, irregardless of the values of .omega., C, and R, it becomes 90.degree.. Accordingly, the phase difference between the same phase component (a1.multidot.V1) and the orthogonal component (a2.multidot.VQ) in the above-described voltage Vo=a1.multidot.V1+a2.multidot.VQ is also kept at 90.degree..
While in this circuit the phase difference between the same phase component and the orthogonal component is kept at 90.degree. independent of the value of the carrier wave frequency and the values of the circuit elements, the amplitude synthesization ratio K between the same phase component and the orthogonal phase component becomes EQU K=A2/A1=.omega.CR
and, it becomes the equi-amplitude synthesization when .omega.CR= 1.
FIG. 33 shows a phase shifter in which an FET 341 is provided in parallel with the resistor 342 as the resistive two-terminal circuitry 340, so as to enable the equi-amplitude synthesization, and the applied voltage of the amplitude synthesization ratio control terminal 343 which is connected to the gate thereof to be adjusted, whereby the amplitude synthesization ratio can be adjusted by simply employing the quadrature modulator.
FIG. 34 shows another phase shifter in which a diode 351 is connected in parallel with the condenser 352 as a capacitive two-terminal circuitry 350, so as to enable the equi-amplitude synthesization, and the cathode of the diode 351 is grounded via the choke coil 353. The applied voltage of the amplitude synthesization ratio control terminal 355 connected via the choke coil 354 to the anode of the diode 351 is adjusted, whereby the amplitude synthesization ratio can be adjusted by simply employing the quadrature modulator.
However, these prior art quadrature modulators shown in FIGS. 31 and 34 are not those used in a construction in which the input signal is initially separated into the components having phase differences of 0.degree. and 90.degree. by the 90.degree. power splitter 361, and the respective signals are amplified by the differential amplifiers 362 and 363 and modulated by the I channel double balanced mixer 364 and the Q channel double balanced mixer 365. These are synthesized by the 0.degree. synthesizer 366 and then amplified by the buffer amplifier 367 to be output. To the contrary, these quadrature modulators are applied to a 90.degree. synthesizer of a quadrature modulator in a construction in which a local oscillator input is amplified by a single differential amplifier 371, the modulated outputs are synthesized with those signals having a 90.degree. phase difference therebetween by the 90.degree. synthesizer 374, and amplified by the buffer amplifier 375, because two differential amplifiers are required in the construction of FIG. 35(a). Thus, the structures of these quadrature modulators in FIGS. 31 and 34 are clearly different from those shown in FIGS. 25 and 27 which are 90.degree. phase shifters in which the quadrature modulation signal is separated firstly by the 90.degree. phase shifter and is modulated by a mixer.
In the quadrature modulator of FIG. 35(b), there would occur an amplitude difference in the 90.degree. synthesizer at the last stage, and if no adjusting circuit is employed, this amplitude error cannot be solved. Therefore, the circuit of FIG. 31 would necessarily cause a problem in yield when it is constituted in the circuit construction as it is, and in order to avoid this, a circuit as shown in FIGS. 33 and 34 is required.
As a quadrature modulator that aims at dispensing with adjustments at the microwave band, Japanese Published Patent Application Hei.3-258056 discloses a non-adjustment quadrature modulator requiring no adjustment for quadrature PSK.
FIG. 36 shows a construction of this prior art non-adjustment modulator for quadrature PSK. Reference numeral 381 designates a local oscillator provided at outside, reference numeral 382 designates an input side EX-OR circuit which receives the I signal and the output of the local oscillator, reference numeral 383 designates a D flip-flop as a two frequency divider to which the output of the input side EX-OR circuit is input as a clock. An output signal, Q, is fed back to its D input, a signal which is obtained by two frequency divisions is output. Reference numeral 384 designates an output side EX-OR circuit which receives the Q signal and the output of the two frequency divider 384 as two inputs.
Next, a description will be given of the operation with reference to FIGS. 37(a)-37(d). The input side EX-OR circuit 382 operates as non-inverting for the output signal (1) from the local oscillator 381 when the input I=L, and operates as inverting for the signal (1) when the input signal I=H.
FIG. 37(a) shows where the state of I=L and Q=L; the output signal (1) of the local oscillator 381 which is input to the EX-OR circuit 382 as the input side gate is input as shown by (2), as a clock C of the two-divider circuit 383, remaining non-inverted. The two divider circuit 383 outputs the data of the D input at every rising of the clock C from the regular output terminal Q, and therefore, it outputs IF modulated wave as shown by (4), by dividing the input of the clock input terminal C by two, as shown by (3).
FIG. 37(b) shows where the state of I=H and Q=L; FIG. 37(d) shows where the state of I=H and Q=H, and FIG. 37(c) shows where the state of I=L and Q=H, the phases are sequentially shifted by 90.degree. at prescribed IF output as shown by the output of IF modulation wave of (4), and thus a modulator of non-adjustment for four phase PSK is realized.
However, the circuit of FIG. 36 is fundamentally different from the circuits of FIGS. 25 and 27 and also the operation frequency is limited by the flip-flop, and therefore, there arises a problem that some device is required in constructing a circuit for an actual mobile communication apparatus.
In this way, conventionally, 0.degree./90.degree. phase shifters appropriate for circuit integration which can be constituted only by resistors, capacitors, and transistors are limited to those utilizing the all-band pass circuit as shown in FIG. 25, or those which, using differential circuits and integrating circuits and utilizing the phase difference of the high pass filter characteristics and the low pass filter characteristics, separates the signals to those having phases of 0.degree. and 90.degree. phases.
However, in the circuits of FIG. 25 and 27 two current paths for output voltages orthogonal to each other are provided. When an adjustment circuit is provided only in one of the current paths so as to adjust element variations of the resistors and capacitors, influences by providing this adjustment circuit other current paths are affected, and it is required to provide similar adjustment circuits so as to cancel these influences, thereby resulting in difficulty in maintaining the orthogonality of the two output signals.


The invention concerns films having a cling layer of an elastomeric propylene-based polymer with a low heat of fusion derived from isotactic propylene type crystallinity, as determined by DSC of less than 40 J/g, optionally blended with a crystalline isotactic propylene derived polymer having a heat of fusion over 70 J/g and/or a melting point of at least 120° C. as determined by DSC, and a non-cling layer of a polyolefin. The cling layer may contain other components such as crystalline polypropylene.

The background description of WO 95/16729 is relevant here also.
Stretch/cling films have wide application, including bundling packaged food and other goods. One application of particular interest is in the bundling of goods for shipping and storage, for example, the bundling of large rolls of carpet, fabric, or the like. A film having cling properties to prevent unraveling of the film from the pallet is therefore desirable. To impart cling properties or improve the cling properties of a particular film, a number of techniques have been employed, such as the addition of tackifying additives or use of polar ethylene copolymers such ethylene acrylates in the (co) polymer. Common tackifying additives include polybutenes, terpene resins, alkali metal and glycerol stearates and oleates and hydrogenated rosins and rosin esters.
Multilayer films offer the advantage of imparting several properties not easily obtained from a single layer. See U.S. Pat. No. 4,518,654 and U.S. Pat. No. 5,114,763, which are incorporated by reference. With a multilayer film, a stretch/cling wrap can have cling properties on one side and, for example, slip properties on the other. It is desirable to have a film having cling properties without the adverse effects found with existing film structures and tackifying additives detailed above.


A clamp includes a body, a lead pin moveable relative to the body and an actuator supported by the body. The actuator is axially moveable between an extended position and a retracted position. The actuator includes a camshaft drivingly coupled to the lead pin. Axial movement of the camshaft causes the lead pin to rotate between a first positioned aligned with a first longitudinal axis and a second position aligned with a second longitudinal axis laterally offset from the first longitudinal axis.

The present invention relates generally to a clamp and, more particularly, to a fluid powered, sealed pin locating and clamping apparatus.
Powered clamps have been commonly used to secure workpieces, such as sheet metal automotive body panels, polymeric parts and the like in checking fixtures, gauging stations, welding stations, punching stations and other locations within a manufacturing environment. Many existing clamps are powered by hydraulic or pneumatic fluid pressure. For example, reference should be made to the following U.S. patents, which have been invented by Sawdon: U.S. Pat. No. 6,502,880 entitled "Pin Part Locator" which issued on Jan. 7, 2003; U.S. Pat. No. 6,378,855 entitled "Locking Pin Clamp" which issued on Apr. 30, 2002; U.S. Pat. No. 5,190,330 entitled "Powered Clamp with Parallel Jaws" which issued on Mar. 2, 1993 and U.S. Pat. No. 6,902,159 entitled "Sealed Pin Locating and Clamping Apparatus" which issued on Jun. 7, 2005; all of which are incorporated by reference herein.
Many of the previously known locating pin clamps include a mechanism which drives a finger or arm which extends outwardly from the pin and pulls down against the workpiece to hold the workpiece in place while operations such as welding and/or clinching take place. Additionally, some locating pin clamps include an aperture in the locating pin to allow the finger to extend and retract from the pin during operation. This aperture provides a path for contamination to enter into the mechanism. Because locating pin clamps are often used in harsh environments, locating pin clamp reliability may be a concern.
Furthermore, some of the known locating pin clamps release the workpiece if there is a loss of fluid pressure during clamp operation. It is desirable to prevent the clamping arm from opening and releasing the workpiece if a loss of fluid pressure were to occur. Prior constructions employing such a feature are disclosed in U.S. Pat. No. 5,871,250 entitled "Sealed Straight Line Gripper" which issued to Sawdon on Feb. 16, 1999 and U.S. Pat. No. 5,853,211 entitled "Universal Gripper" which issued to Sawdon et al. on Dec. 29, 1998. These patents are also incorporated by reference herein.
In accordance with the present invention, a clamp includes a body, a lead pin moveable relative to the body and an actuator supported by the body. The actuator is axially moveable between an extended position and a retracted position. The actuator includes a camshaft drivingly coupled to the lead pin. Axial movement of the camshaft causes the lead pin to rotate between a first positioned aligned with a first longitudinal axis and a second position aligned with a second longitudinal axis laterally offset from the first longitudinal axis.
As another feature of the present invention, the clamp includes a body, an actuator moveably supported by the body, and a clamping member drivingly coupled to the actuator. The actuator includes a pair of rollers, each roller being positioned within one of two grooves formed on an axially and rotatably moveable camshaft. Each groove includes a plurality of detents. The clamping member axially translates and rotates between an extended position and retracted position in response to movement of the actuator. The rollers are positionable in engagement with the detents to restrict movement of the clamping member in the absence of force being provided by the actuator.


An RF transceiver apparatus has transmitter circuitry receiving transmission signals at a transmitter baseband frequency and converting the signals to a transmission frequency, and receiver circuitry receiving signals at a reception frequency and converting to a receiver baseband frequency. A first digital local oscillator and a first mixer convert between the transmitter baseband frequency and a transmitter intermediate frequency. A second digital local oscillator and a second mixer convert between a receiver intermediate frequency and the receiver baseband frequency. A third mixer frequency receives a local oscillator signal for frequency conversion between the transmitter intermediate frequency and the transmission frequency. A fourth mixer frequency receives a local oscillator signal for frequency conversion between the reception frequency and the receiver intermediate frequency. A third local oscillator produces an RF oscillator signal to the third mixer and the fourth mixer to provide the local oscillator signal.

The use of superheterodyne circuits for receivers, in which the received signal is mixed with a local oscillator signal to generate an intermediate frequency signal of above audible frequency, is well known and the invention normally attributed to Edwin H Armstrong who claimed the invention in 1918. These were originally analog technologies.
With the availability and progress of silicon integrated circuit designs, complete radio transmitters and receivers have been integrated onto silicon. The superheterodyne receiver lost favor for high frequency applications due to the narrow bandwidth and high frequency required for the intermediate frequency (IF) filter being difficult to integrate onto silicon. As a result, an architecture originally developed in 1924 by Colebrook was further developed in recent times for integration onto silicon. The homodyne architecture, otherwise known as Zero IF, is shown in the transmitter configuration in FIG. 1. In these systems the local oscillator is at the transmission frequency which allows direct conversion between the baseband and transmission frequencies. The input signal can be analog or digital in this case. The advantage of this system is the ease of integration of the channel filter, which operates at the baseband frequency, at the expense of complexity. The channel filter is a simple low-pass filter, whose bandwidth is half the RF channel bandwidth.
One disadvantage of the zero IF system (among others, including system complexity, DC offsets etc) is that local oscillator phase noise, shown in FIG. 2, degrades the quality of the data. The local oscillator noise 24 is superimposed on the received baseband signals 22 after mixing. The receiver bandwidth is twice the baseband filter 20 as shown. The oscillator noise 24 degrades the baseband signal 22, so is a critical parameter of the design.
The use of an intermediate frequency circumvents the local oscillator noise problem. Typically, the intermediate frequency is set to a frequency that is high enough so that the image frequency may be removed by RF filtering. This leads to the problem that high Q circuits are required to obtain channel selectivity. Another method to circumvent the issues of a zero IF system is to set the intermediate frequency to a frequency where filters may be implemented easily, but the channel does not include the DC component.


A device for storing optical discs is disclosed. The device includes a housing, a carousel arranged in the housing for movement relative to the housing, the carousel having a plurality of storage compartments each for storing a disc, an opening in the housing through which a disc can pass, drive means for driving the carousel relative to the housing to align each of the storage compartments and a disc stored in that storage compartment in registry with the opening, and an ejection system to eject a disc from a storage compartment and through the opening in said housing. The ejection system is powered by a motor and a clutch system, and control means is provided to cause said carousel to rotate and to cause the ejection system to operate as instructed by a user.

As is well known, information stored on DVD's, CD ROM discs, music compact discs and the like are commonly used with computers and audio and video equipment. Typically, such optical discs are stored in a storage rack or box and the receiving device includes an optical drive into which a disc is inserted.
Generally, in order to use an optical disc, the operator will insert the disc into the receiving device and initiate its operation.
However, before inserting the disc into the receiving device, the operator must manually locate the relevant optical disc and insert it into the optical disc reader of the receiving device. If the receiving device is a computer, the computer can then read and/or write onto the disc and run the program in accordance with the software contained on the CD ROM. If the receiving device is of another type, the device can interact with data or software contained on the disc under the control of software or data included in the receiving device.
The handling of optical discs, particularly if an operator has a large number of optical discs, can be time consuming and bothersome because of the number of optical discs which need to be stored and then the number which may have to be manually searched through in order to provide the data, file, or other information or material the operator wishes to access.
A CD storage device aimed at solving these problems is described in International Patent Application number PCT/AU01/00631, titled "CD ROM Storage Device" filed 28 May 2001 and published 5 Dec. 2002 under international Publication Number 02/097808 A1, by applicant Project Lab Pty Ltd. With reference to FIG. 1, the Project Lab application teaches a CD storage device which includes a case 10 in which a circular storage member 12 is supported for rotation in the case. The circular storage member 12 has a number compartments 14 formed between ribs 16 each for storing a CD 18. The device includes a controlling circuit board, not shown, which can couple with a computer so that CD's can be stored and retrieved by inputting information into the computer which causes the circular storage member to rotate to present the storage compartment having the required CD at an opening 20 for discharge. The device includes an ejector for ejecting CDs from a storage compartment 14. However, in some circumstances the ejector disclosed in the Project Lab patent application has shortcomings, and improvements to the ejector system are desirable.

Storage and retrieval device for optical discs


A stroboscopic imaging interferometer system includes an environmental chamber having a novel viewing window equipped with a rigidly integrated beam splitter and piezo actuated reference mirror for illuminating a device providing an object beam and reference mirror for providing a reference beam, upon the reflection of both beams, produces interference of the object beam by the reference beam for providing absolute phase observations of the device, that may be a MEMS device under test.

The harsh environment and stringent reliability requirements of space technology require detailed knowledge of the motion of all mechanical devices. The failure modes must be well understood and catalogued. While this may be a straightforward analysis for macroscopic devices, microscopic mechanical structures require new tools to study their response under various conditions. In the existing art, static methods are generally employed and the motion of micro-electromechanical systems (MEMS) is then analytically derived. These inferential results are unacceptable for the requirements of modern aerospace applications and are often lacking in their precision when related to dynamic operation. Thorough qualification of micro-mechanical systems requires directly observed, reliable data, lacking in conventional metrology systems.
To study the motion of microscopic mechanical parts, it is not practical to load them with sensors. Non-contact measurement techniques are at a premium for dynamic MEMS device measurement. Optical methods of interrogation are ideal under these restrictions, and such schemes are well documented in the literature, offering high resolution and rapid measurement with a non-contact technique. Test products using laser-Doppler vibrometry or white light interferometry are commercially available on the market today. These products, however, have serious drawbacks. The vibrometer only yields velocity data, not absolute shape or displacement. In addition to this failing, the vibrometer measures single points at a time, requiring accurate scanning and stitching over the entire surface of the test object. The actual motion and shape of the device must then be gained inferentially through analysis and is subject to many sources of error, both in the scanning and interpretation of device measurements.
The white light interferometer has similar problems. Although it can take an image rather than a point of data at a time, the object or reference mirror must be scanned to find the interference maxima at each imaging pixel. While this does generate displacement data over a large dynamic range, the long scan time relies on very highly repeated motion. Couple this requirement to a slightly noisy environment and the data becomes riddled with potential errors.
A conventional state-of-the-art solution that addresses these issues is the stroboscopic Michelson Interferometer or, a subset of those, the Twyman-Green interferometer. The test system can achieve sub-nanometer resolution interferometricly and diffraction limited lateral resolution using microscopic objectives. Although the Twyman-Green interferometer relies on repeated motion of the device for dynamic characterization, only five to six vertical scan steps are done per time step of device motion. Several configurations have been documented in which the interferometer outputs to an imaging system. When implemented with a camera or video device, this records data from a broad area of the device so no lateral scanning is required. The conventional Michelson or Twyman-Green test system is composed of bulk optical components. These tend to include a laser light source to illuminate the device and reference mirror, an optical beam splitter, and optical microscope objectives to image the sample onto a camera. The standard configuration is such that the illuminating optical beam is split at the beam splitter. One of the two outputs of the beam splitter proceeds to the reference mirror of the interferometer and is reflected back to the beam splitter. The second output beam is directed to the device under test, which also reflects it back to the beam splitter. These beams then recombine at the beam splitter and are directed to the camera to be recorded. When the test and reference arms have a path length within the coherence length of the source, interference fringes will cover the image. The choice of optical source is non-trivial. When the source has a very high degree of coherence, the tolerances on distance are eased, but the final image will be spotted with speckle patterns and interference from stray reflections, apertures and dust. When the coherence is very low, for example in a white light interferometer, the image will be crisp but interference will only occur over very narrow displacements. To avoid constant scanning of the reference mirror, the coherence length must be greater than twice the characteristic dimensions of the device under test.
To perform measurements on micrometer scale devices and samples, the conventional Michelson test system employs a microscope objective between the beam splitter and the test sample. This system relies on the interference of nearly identical optical fields so the optical paths to the test sample and reference mirror must be closely matched. This requires a second, identical microscope objective in the reference path so that the phase fronts have identical curvature. The second objective puts even further constraints on the allowed displacement tolerances. When the reference mirror is further from the objective than the test device, the phase front will have a different curvature and the fringes will show a warped surface. This creates a very difficult problem in calibrating the system. If one were to calibrate the system by inserting an optically flat mirror in place of the test sample, one would have to assure that the test sample was the same axial distance from the microscope when testing. This exact length tolerance would depend on the details. of the system but can be expected to be on the order of tens of micrometers. Achieving such precision is not practical in a manufacturing or testing environment.
In a conventional interferometer, vibration in any part of either optical path, that is, in the microscope objective path, reference mirror path, or at the device, is translated into measurement errors. This presents a serious obstacle to high fidelity metrology. Because interferometric systems are designed to measure distances on the order of nanometers, they are also sensitive to vibrations on that length scale as well. Currently, these types of microscopic interferometers disadvantageously require floating optical tables and controlled laboratory environments. These and other disadvantages are solved or greatly reduced using the present invention.

Interferometry system chamber viewing window


A network adapter comprises a controller to change to a first mode from a second mode based on a number of transmit packets, sizes of received packets, and intervals between arrivals of the received packets. In one embodiment, the network controller further comprises a memory to buffer received packets, where the received packets are buffered for a longer period in the first mode than in the second mode.

It is becoming increasingly common to find broadband wireless networking capabilities (e.g., IEEE 802.11, 802.16e, etc.) and wired connectivity (e.g., IEEE 802.3) in mobile platforms that favor low power design. In some network environment, maintaining all network devices (wired or wireless) at a fully powered state unnecessarily consumes energy, especially when access to data is sporadic. Power management schemes are used in conjunction with network devices to extend the battery lifetime of mobile communication devices.
A network device may operate in a reduced power state (e.g., standby, sleep, hibernate, etc.) for saving power consumption. However, if the device is in a reduced power state, the device may not be able to receive a data request or data from other networked devices.

Enabling long-term communication idleness for energy efficiency


A method and a device for estimating the DC offset portion of a signal, especially of a signal containing parts with sinusoidal shape, for example a signal which results from demodulation of a frequency modulated receive signal. A method is presented for correcting the direct current offset portion (DC offset) of a first signal which includes phase shifting the first signal for obtaining a second signal and comparing the first signal and the second signal with an estimated DC offset. The estimated DC offset is adjusted if the result of the comparison is that the first signal and the second signal are on different sides of the estimated DC offset and the estimated DC offset remains constant as long as the result of the comparison is that the first signal and the second signal are on the same side of the estimated DC offset.

The invention relates to a method and a device for estimating the DC offset portion of a signal, especially of a signal containing parts with a sinusoidal shape, for example a signal which results from demodulation of a frequency modulated receive signal. After demodulation of a frequency modulated signal, the problem of carrier frequency estimation transforms into Direct Current (DC) estimation of the received signal. For simplicity only the abbreviated term DC estimation will be used in the present specification. The term tracking is used if the DC value is continuously estimated not only during the beginning of a packet but also for the remaining portion of a packet. In particular the present invention relates to a device for correcting the DC offset of a signal, for example a received radio frequency signal after demodulation.
The present invention is especially designed for systems where fast and reliable DC estimation is difficult due to the nature of the received signal, especially for received data packets in TDMA (Time division Multiple Access) and CDMA (Code Division Multiple Access) systems.
In some known systems of this kind (e.g. DECT, Digital European Cordless Telephone Standard), the DC estimation is not a problem due to a long sequence of equally distributed bits (1010101 . . . series) at the start of each data packet. The preamble is DC free and can be used for DC estimation. After the start of the packet is indicated by some control logic, the estimated DC is usually frozen and used for the rest of the packet. In the mentioned DECT standard, the preamble is long enough to apply linear methods of DC estimation, e.g. simple low pass filtering of the incoming signal by means of a R-C combination can be applied.
For systems having a shorter preamble, the DC estimation has to be faster which usually results in a lower accuracy of the estimated DC. One possibility to overcome the problem of the low accuracy of an initial estimate is not to freeze the rough DC estimate but to perform continuous tracking during the whole data packet. One difficulty with those DC tracking algorithms are sequences of equal bits that result in a signal that is basically constant. In such a case the estimated DC must not slowly drift to this constant signal. One example of a system with a short preamble is the Bluetooth™ system described in the specification of the Bluetooth™ standard. Those skilled in the art will appreciate that other wireless systems also exist, and reference herein to Bluetooth™ is not intended to be limited thereto.
Bluetooth™ wireless technology allows users to make effortless, wireless and almost instant connections between various communication devices, such as mobile phones, computers, printers, etc. Bluetooth™ provides short-range wireless connectivity and supports both point to point and point to multipoint access. The Bluetooth™ standard provides a preamble of data packets with a preamble of four bits which can be used for DC-estimation.
Bluetooth™ operates in the 2.4 GHz ISM band using a band of 83.5 MHz which locates 79 RF channels spaced 1 MHz apart. The channel is represented by a pseudo-random hopping sequence through available channels. The channel is divided into time slots where each slot corresponds to an RF hop frequency. Consecutive hops correspond to different RF hopping frequencies. The nominal hop rate is 1600 hops per second. All Bluetooth™ devices of a given piconet are time and frequency hop synchronized to the channel.
The foregoing description makes it apparent to those skilled in the art that fast and reliable DC estimation methods are necessary for operating a communication device which operates in accordance with the Bluetooth™ standard.

Signal DC offset correction method and device


The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include one or more transient termination circuits coupled to transistor inputs. For example, the transient termination circuits can be configured to reduce the transient response for some signal energy at frequencies below a baseband frequency (fB) of signals being amplified while not similarly reducing the transient response for signal energy near a fundamental frequency (f0) of the signals being amplified.

In general, amplifiers are used to increase the power of signals. For example, in some applications amplifiers can be used to convert low-power radio frequency (RF) signals into larger RF signals for driving the antenna of a transmitter. In such cases, amplifiers may be implemented as part of an overall power amplifier used by an RF transmission system.
One reoccurring issue in RF power amplifiers is unwanted transient signals that can be caused by noise and other factors. For example, unwanted transient signals can occur at the input of RF power amplifiers. These unwanted transient signals at the input of the RF power amplifier can cause excessive peak transient voltages at the output of the RF power amplifier. In some cases, these excessive peak transient voltages can lead to signal disruption or worse.
Furthermore, some techniques for reducing the possibility of excessive peak transient voltages can undesirably result in reduced amplifier performance. For example, some techniques can impair wideband operation or reduce amplifier linearity, where amplifier linearity is a measurement of how accurate the output signal is compared to the input signal applied to the input of the amplifier, particularly when generating high power signals.
Therefore, there remains a need for amplifiers with reduced susceptibility to excessive peak transient voltages, particularity for high power RF applications.

Amplifier devices with input transient termination