A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

(1) Field of the Invention
The invention relates to a pipelined processor core. More specifically, the invention relates to a versatile processor core which allows use of varied instruction fetch units without modification to the core.
(2) Related Art
Pipelined processing is generally well-known in the art. FIG. 1 shows one such typical pipelined processor. The processor core 1 includes five pipe stages 2-6. Between each stage is an implicit latch (not shown). The information is latched from one pipe stage to the next under the control of the pipe sequencer 7. The first pipe stage is an instruction pointer generator stage (IP) 2 which generates an address at which the desired instruction can be found. This address is then latched to the instruction fetch unit stage (IFU) 3 which physically fetches the instruction. Typically, the IFU has on-board memory of some kind. The on-board memory may be of the form of an instruction cache or it might be read only memory (ROM). The IFU is also coupled to the bus controller 8 which allows the IFU to access the memory 10 in the event that the desired instruction is not found in the on-board memory.
Once the instruction is retrieved either from the on-board memory or externally, the instruction is lathed to a third pipe stage instruction decode unit/register file stage (ID) 4. The ID 4 decodes the instruction and acquires any required operands from a register file. Where each pipe stage tables a single cycle, the ID expects that an instruction will arrive in the third cycle and each cycle thereafter. If the IFU 3 cannot deliver an instruction to the ID 4, it notifies the pipe sequencer 7 that it is stalled while it obtains the expected instruction. The pipe sequencer stalls all stages above. Once the instruction is delivered and decoded, the instruction and operands are then latched to the next stage, the execution unit 5 for execution of the instruction. The final pipe stage is write-back stage 6 in which results of the instruction executed in the execution unit 5 during the previous cycle are written back to the register file or the data cache 9. Branch target path 11 allows the execution unit 5 to inform the IP 2 that a branch has occurred, and provide an address at which execution should continue. In response, the information currently in the pipeline relating to instruction after the branch in the instruction stream is flushed. The pipe sequencer 7 handles common control amongst the pipe stages and insures synchronization. It is critical that the pipe sequencer knows what is occurring in the stages it controls so that synchronization is maintained and retries can be generated when expected data is not received at any particular stage.
In the event of a stall, the stage initiating the stall notifies the pipe sequencer 7, and the pipe sequencer 7 stalls all units above that stage in the same cycle. For example, if the ID 4 is unable to complete decode and register retrieval in the allotted cycle, it issues a stall instruction to the pipe sequencer 7 which immediately stalls the IP 2 and the IFU 3. This stall must be completed within the cycle or, for example, a fetched instruction will be latched to the ID 4 with a new instruction taking its place in the latch. If the ID 4 is unable to accept the instruction latched to it, that instruction is lost. The stall becomes a critical speed path which reduces the maximum frequency at which the core 1 can operate, because the ID may not identify that it does not have, e.g., a needed operand until late in the cycle and because of the number of latches required to be stalled requires time to buffer up of the stall signal to a level able to stall all stages above the stage initiating the stall.
FIG. 2 shows a block diagram of a system of an alternative pipelined processor from the prior art. Processor core 30 contains a plurality of pipe stages. Instruction pointer generation stage (IP) 32 generates an instruction pointer and control information which it places in an instruction pointer latch (IPL) 33. From IPL 33, a plurality of signals including control information and an instruction address are latched into dummy stage 38 which must be the same depth as an instruction fetch unit stage (IFU) 39 which resides outside the core boundary 31. Simultaneously with the latching of the control signals and the instruction address into the control stage 38, the instruction address is latched out on line 43 to IFU 39. IFU 39 fetches the instructions specified by the address and provides it to instruction fetch latch (IFL) 34 inside the core 30. Simultaneously, the control and instruction address arrive from the dummy pipe stage 38. Control information, instruction address, and the instruction are then latched in the instruction decode/register file stage (ID) 35. The instruction is decoded in the ID 35 and the operands retrieved. The decoded instruction and operands as well as control information are latched to execution unit 36. The information necessary for write-back is latched to the write-back stage 37 as in the prior art The latches between the ID 35 and the execution unit 36 and between the execution unit 36 and the write-back 37 unit, are not shown for clarity in the drawing. Restart line 38 is used to inform the IP 32 of the new address and to invalidate the data currently in the pipe when a branch is mispredicted. The execution unit 36 will ignore all data received until it receives the restart signal propagated through with an instruction corresponding to the branch result.
In the event of a stall, for example, in the ID 35, signal line 40 is asserted to stall IFL 34 and is propagated up to also stall IPL 33. If dummy stage 38 and IFU 39 have depths of greater than one, stall signal 40 must be propagated to dummy stage 38 and IFU 39 as well. An analogous situation arises for stalls originating lower in the pipeline. As mentioned before, this results in a critical timing path necessary for buffering up and propagating the signal to achieve the stall without loss of data. Additionally, while IFU 39 is made flexible in terms of the size of memory it may have on board, its depth is dictated by the dummy stage 38 as the two must be of equal depth in order to ensure proper synchronization of the control signals propagating down within the core 30.
Changes in application or desired use commonly necessitate a redesign of the core. Commonly, this is a result of change to the IFU. Among the things that may change as a result of cost or space concerns are size of the on-board memory and the depth of the IFU pipeline. For example, in some applications, it is desirable for cost or design time reasons to use an IFU which requires more than a single cycle to retrieve an instruction. The IFUs are circuit intensive, and the more rigorous the timing requirements for instruction retrieval, the greater the cost and design effort required to insure compliance with that timing. Thus, by expanding the timing allowed, the IFU can be designed using less senior designers and at a lower cost. While moving the IFU 39 outside the core as shown in FIG. 2 allows the size to be changed. Without core redesign, it does nothing to address changes in the depth of the IFU pipeline.
In view of the foregoing, it would be desirable to have a core suitable for use at the large variety of products and flexibly able to incorporate IFUs of varying sizes and depths without necessitating a redesign of the core.

Method and apparatus permitting the use of a pipe stage having an unknown depth with a single microprocessor core


A method for separating polyester materials from contaminants is disclosed suitable for, for example, a polyester recycling system. The method is a dry separation method and includes rapidly spinning a mixture of polyester and contaminants within a cleaning chamber. During the spinning of the mixture, the contaminants can be degraded and pass through a screen at the chamber wall while the polyester materials are not substantially degraded and can remain in the cleaning chamber. Polyester fines can also remain in the cleaning chamber. A cleaning device suitable for use in the process is also disclosed. The device can include a screen of a hardened material that can help degrade the contaminants and a plurality of rotating blades that can spin the mixture within the device and can also help to degrade the contaminant materials.

Polyesters are polymeric materials made from the esterification of polybasic organic acids with polyhydric acids. Perhaps the most commonly made and used polyester is polyethylene terephthalate (PET), which can be manufactured by reacting terephthalic acid with ethylene glycol.
Polyesters are currently being used in increasing amounts in various applications. For instance, polyesters are commonly used to make many types of beverage and food containers, photographic films, X-ray films, magnetic recording tapes, electrical insulation, surgical aids such as synthetic arteries, fabrics and other textile products.
Because polyesters can be remelted and reformed, ongoing efforts are underway to efficiently recycle as much polyester as possible after use. Before polyester can be recycled, however, it is necessary to separate the post-consumer polyester from contaminants, i.e., materials that may be found mixed with or attached to the polyester. Many recycle processes include a separation step wherein the polyester is washed with an aqueous solution in order to separate the polyester from contaminants. While aqueous washing can remove many contaminants, it does utilize a great deal of water as well as require the further step of post treatment of the wash solution to remove contaminants from the wastewater. Unfortunately, aqueous washing can also prove ineffective for removing relatively hard contaminants, such as glass, sand, and the like, which may become embedded in the polyester materials.
In an attempt to remove embedded materials from polyester substrates, melt filtration processes have been used in which the contaminated polyester is melted and then filtered in order to remove the solid contaminants. These are not terribly cost effective methods, however, and often prove economically unfeasible.
What is needed in the art is a novel method for removing contaminants from polyester materials, and in particular, from post-consumer polyester materials. In addition, what is needed in the art is a polyester recycling process in which contamination levels of treatment water are reduced as compared to previously known recycling processes.

Dry separation of contaminants from polyester materials


A wound suturing assembly and method of use employing elastically precurved suture needles for piercing a patient's tissue to suture closed a wound. The needles are ejected out of the assembly and whereupon they assume a pre-curved shape and in the process curve back to pierce the tissue a second time prior to reentering the assembly. Each needle carries a length of suture through the wound so that the sutures can be tied and the wound tightly sealed.

The present invention relates generally to an apparatus and method for the closure of wounds in body tissue, and more particularly to an apparatus and method for the suture of puncture sites in body lumens accessible through a tissue tract.
Transluminal medical procedures have seen a marked rise in popularity during the past decade due to the much reduced surgical damage to healthy tissue, recovery time, and ultimate cost to the patient associated with these procedures. Such procedures typically require an incision formed in a body lumen and the overlying tissue through which catheters, guide wires, laparoscopes, endoscopes, and similar medical devices can be inserted into the patient's vascular system. The incisions are created with instruments such as trocars, and may measure from 5 to upwards of 15 mm in diameter. After the intravascular procedure is complete, the incision must be closed and sealed as quickly as possible to prevent further bleeding.
Unfortunately, the size of the incision is usually large enough to permit profuse bleeding, but too small for the convenient application of conventional wound closure techniques such as suturing. Other methods have been proposed, including the use of collagen and other types of plugs placed outside the lumen and near the wound. Some plugs are designed to be placed directly within the lumen and secured against the inner wall of the lumen by an external suture attached to the plug. In yet other similar closure methods, a clotting agent such as a foam, gel, or powder is dispensed within the wound. These methods all tend to cause the at least partial deposition of a plug or clotting agent within the lumen, whether by design or unintentionally, and thus result in the partial occlusion of the flow of blood through the lumen near the site of the wound. This is an unfortunate side effect that can lead to complications such as thrombosis and is therefore undesirable.
Another common closure technique employs continuous pressure applied to the wound site to allow the patient's blood to clot sufficiently to seal the wound. This technique, however, is usually very time consuming for both patient and medical personnel, thus partially negating one of the main advantages of transluminal procedures. In addition, a hematoma may occur if the patient moves while the pressure is being applied and therefore additional rest and observation in the hospital is required, further driving up the cost and time associated with the procedure.
Sutures remain the preferred method of sealing wounds, but the small size of the typical wound formed during a transluminal procedure renders the application of sutures a delicate and difficult task. Traditionally the surgeon would introduce a suture needle through the tissue tract and into the body lumen, manipulate the needle with a grasping instrument into position, then urge it to penetrate and pass through the lumen wall near the wound site and pull the suture material therethrough. This procedure involves difficult manipulations and maneuvers in a small space and through a small opening, and is therefore time consuming and burdensome.
Due to the ever increasing number of transluminal procedures performed each year, a great deal of effort has been devoted to the development of quicker, safer methods for post-operative suturing of endoscopic wounds. Practically all viable methods involve the use of a specially developed device for placing sutures in the lumen and through the body tissue. Some devices employ needles to carry opposite ends of a suture through the tissue surrounding the wound, and then means for retrieving the ends of the suture from within the body lumen and out through the wound. Such means may include an expandable mesh (U.S. Pat. No. 5,496,332 to Sierra et al.), a flexible membrane capturing anchors attached to the ends of the suture (U.S. Pat. No. 5,391,182 to Chin), and an expandable bow assembly (U.S. Pat. Nos. 5,304,184 and No. 5,476,469 to Hathaway et al.). A drawback to the method employed by these devices is that the suture ends pass from within the lumen and out through the wound opening, and are thereby trapped between the tissue walls surrounding the wound when the suture is tensioned to close the opening. This suture configuration prevents the tissue walls from fully contacting each other and thus may require an extended period of time to heal. In addition, this configuration also requires that the suture knot tied by the surgeon must lie within the lumen, and therefore in most cases the surgeon cannot tie a sufficiently tight knot to prevent any further bleeding and to ensure minimal scarring of the tissue upon healing. Finally, most such devices require the surgeon to blindly capture the ends of the suture within the lumen while blood courses through the lumen with the patient's heart beat, making exact placement and capture of the suture ends difficult and imprecise.
Other suturing devices employ tubes carrying needles mounted on extendible platforms that advance out of the distal end of the tube once the distal end has been positioned within the lumen. The needles may be straight or curved, and carry sutures so that when the device is retracted from the lumen the needles pierce the side walls of the wound and thereby carry the sutures through the surrounding tissue. Devices of this type are disclosed in, e.g., U.S. Pat. No. 5,374,275 to Bradley et al., U.S. Pat. No. 5,364,408 to Gordon, U.S. Pat. No. 5,320,632 to Heidmueller, U.S. Pat. No. 5,403,329 to Hinchcliffe, U.S. Pat. No. 5,368,601 to Sauer et al., and international publications WO 94/13211 and WO 95/13021. A relatively similar device is disclosed in U.S. Pat. No. 5,431,666 to Sauer et al., wherein the device has a distal end with a suture equipped with ferules at either end placed therein. The distal end is positioned within the lumen and beneath the side walls of the wound, and sharp needles are driven through the side wall tissue to engage the ferules and pull the suture out. These devices are preferable because they create a cleaner, tighter seal of the wound, and are somewhat easier to operate because the suture ends do not have to be captured blindly within the lumen. Unfortunately, however, such devices are relatively complex and employ a significant number of moving parts. These devices are therefore relatively costly to manufacture and are also more prone to mechanical failure. In addition, such devices cannot be easily manufactured with very small diameters because of the complex mechanisms that must fit entirely within the device, especially when the needles are curved, and thus some of the devices may not be suited to suturing small diameter wounds.
The need continues to exist for a suturing method that will cleanly and tightly suture small as well as larger diameter wounds with an uncomplicated, dependable, inexpensive apparatus that is fail proof and simple to use. The present invention meets these needs.

Wound closure assembly and method of use


An aircraft nacelle comprising a first duct secured to an air intake and a second duct secured to a powerplant, the first duct comprising an exterior surface and an end portion connected to the second duct. The nacelle includes a hollow section piece in contact with the exterior surface of the first duct which extends over at least part of the circumference of that end portion of the first duct that is connected to the second duct.

The present invention relates to an aircraft nacelle incorporating a reinforced connection between an air intake and a powerplant.
An aircraft propulsion unit comprises a nacelle containing, arranged substantially concentrically, a powerplant connected by a pylon to the rest of the aircraft.
As illustrated in FIG. 1, the nacelle comprises at the front an air intake 10 that channels a flow of air towards the powerplant 12, a first part of the incoming air flow, referred to as the primary flow, passing through the powerplant to participate in combustion, the second part of the air flow, referred to as the secondary flow, being driven by a fan and flowing along an annular duct delimited by the interior wall of the nacelle and the exterior wall of the powerplant.
In the remainder of the description, the longitudinal direction corresponds to the direction of the axis of pivoting of the powerplant fan.
The air intake 10 comprises a lip 14 of which the surface in contact with the aerodynamic flows is extended inside the nacelle by an inner duct 16 of substantially circular sections and outside the nacelle by an exterior wall 18 of substantially circular sections. The powerplant comprises a duct 20 that can be positioned in the continuation of the inner duct 16.
As illustrated in FIG. 2, the air intake 10 is connected to the powerplant 12 by a connection which, at the powerplant, comprises a first annular ring flange 22 secured to a second annular ring flange 24 of a panel delimiting the duct 16 or of an intercalated component 26, referred to as a flange, connected to the panel delimiting the duct 16. The two ring flanges 22 and 24 are pressed firmly together at a junction plane 28 substantially perpendicular to the longitudinal direction, and held in this state by connecting elements 30, for example screw fasteners or rivets, which pass through the ring flanges 22, 24 and run parallel to the longitudinal direction.
From a structural standpoint, the air intake 10 comprises a first frame referred to as the front frame 32 connecting the inner duct 16 and the exterior wall 18 delimiting with the lip 14 an annular duct 34 and a second frame referred to as the rear frame 36 connecting the inner duct 16 and the exterior wall 18 near the junction plane 28.
As far as the rear frame is concerned, this reacts the bending forces, rotation forces or other forces applied to the air intake such as, for example, the weight of the air intake, and the loading induced by the aerodynamic flows.
According to one embodiment, the rear frame 36 is connected to the duct 16 directly or via an intercalated component or flange 38 (visible in detail in FIG. 2), one leg of which is connected to the duct 16, the other leg being connected to the rear frame 36.
The rear frame 36 is connected to the exterior wall 18 directly or via a T-section flange 40 (visible in FIG. 1), the rear frame 36 being connected to the upright of the T-section flange, the top of the T resting against the internal face of the exterior wall 18.
According to one embodiment illustrated in document FR-2.904.604, the rear frame comprises a first metal ring, notably made of titanium, which extends over the entire periphery and is connected to the inner duct 16 and a second ring the exterior peripheral edge of which is connected to the exterior wall 18. The first ring at its exterior peripheral edge comprises a zone of overlap with the interior peripheral edge of the second ring. The two rings are joined together by any suitable means in this region of overlap.
In the event of fan blade breakage, the duct 20 of the powerplant has a tendency to deform significantly, this duct being designed to absorb, by deforming, the energy of the broken blades. At the air intake, the inner duct 16 is made of composite material and its mechanical properties are inferior to those of the duct 20 of the powerplant, notably as far as bending strength is concerned.
Hence, in order to limit the risk of dislocation of the panel or panels that make up the inner duct 16 of the air intake, the spread of deformation from the duct 20 of the powerplant towards the inner duct 16 of the air intake needs to be limited.
One first solution is to design a rear frame and/or a connection between the air intake and the powerplant that are capable of deforming in order to absorb some of the energy and thus limit the spread of deformation towards the inner duct 16 of the air intake.
Another solution is to limit the deformation of the inner duct 16 of the air intake by making it more rigid in the zone of connection between the duct of the powerplant. Solutions have been developed for increasing the rigidity of the rear frame and/or of the connection between the air intake and the powerplant.
In order to increase the rigidity of the rear frame, document FR-2.960.856 proposes a reinforced rear frame which comprises a first metal ring the interior edge of which is connected to the interior wall of the air intake and a second ring the exterior edge of which is connected to the exterior wall of the air intake, the two rings being joined together. According to one specific feature of this rear frame, the second ring comprises at least one angular sector made of composite material with at least one box section shape and the first ring comprises a rib running around the entire periphery of the said ring.
To increase the rigidity of the connection between the air intake and the powerplant, one solution is to increase the thicknesses of the ring flanges, to increase the number of connecting elements or the dimensions thereof. However, that solution is unsatisfactory because it does not prevent deformation from occurring between the ring flange 24 and the rest of the inner duct 16 of the air intake, as a bending motion along an axis tangential to the inner duct 16 occurs between the said ring flange and the said duct.

Aircraft nacelle comprising a reinforced connection between an air intake and a powerplant


Impending rollover events are detected by recognizing a plow phase increase in lateral acceleration, coupled with a significant trip phase roll rate. The plow phase increase is recognized by modeling a typical soil trip lateral acceleration characteristic and computing a cross-correlation between the measured lateral acceleration and the modeled acceleration. The correlation is compared to a threshold that varies with the measured roll rate to reliably discriminate rollover events from near-rollover events while enabling timely deployment of suitable occupant restraints.

Various rollover detection methodologies have been developed for activating electrically deployed rollover safety devices such as air bags, side curtains, seat belt pretensioners and pop-up roll bars, and/or for activating visual, auditory or haptic warnings. Typical parameters used to detect rollover include the vehicle attitude rate of change or angular roll rate, the vehicle roll angle, the vehicle speed, the steering wheel angle, the vehicle yaw rate and the side-slip angle. For example, the U.S. Pat. No. 6,542,792 to Schubert et al., issued on Apr. 1, 2003, discloses a rollover detection algorithm that involves determining an angular roll rate vs. roll angle operating point of the vehicle, and comparing the determined operating point to one or more calibrated thresholds.
While algorithms such as the one disclosed in the aforementioned U.S. Pat. No. 6,542,792 to Schubert et al. can timely detect impending rollover events that occur relatively quickly with high roll rates, soil trip rollover events that occur when a vehicle slides sideways into soft or yielding roadside material such as soil, sand or gravel can be very difficult to detect in a timely fashion. Accordingly, what is needed is a method of reliably and timely detecting soil trip rollover events.

Soil trip vehicle rollover detection method


In a mobile communication system, a method of setting a reverse activity bit (RAB) is provided. The method comprises measuring a rise over thermal noise-measured (ROTm) representing a load degree of a reverse link; comparing the ROTm with a setup reference value (ROTm_th); setting the RAB to lower data rate of a terminal, when the ROTm is greater than the ROTm_th; enabling a base station to receive and monitor a variation state of the ROTm, when the ROTm is less than the ROTm_th; and setting the RAB to control the data rate according to the variation state of the ROTm.

1. Field of the Invention
The present invention relates to a method of setting a reverse activity bit in a mobile communication environment, and more particularly, to a method of setting a reverse activity bit for enabling subscribers in a cell or sector to receive services and to increase a reverse link capacity.
2. Discussion of the Related Art
Generally, 1xEV-DO is a system for exclusive data communication developed by Qualcomm Inc., U.S.A. in the late 1990's to provide general data communication services in non-realtime wireless mobile environments. The 1xEV-DO system adopts intrinsic resource assignment methods corresponding to the characteristics of forward and reverse links.
In a forward link, a base station continuously transmits pilot signals with a constant power. Each terminal in a cell measures intensity of each of the pilot signals to determine the channel status of the forward link. Once such a status is reported to the base station, a scheduler of the base station determines which terminal will receive an assignment of a forward link resource.
This determination is made in accordance with the forward link channel status reported from each of the terminals in every slot with time division. The scheduler operates so that more resources are assigned to the terminal with a better channel status. This maximizes total data throughput of forward link for each cell.
In a reverse link, a base station receives reverse pilot signals from terminals scattered in a cell. The base station is unable to check reverse link characteristics of the respective terminals from reception signal intensity received from each of the terminals via an antenna of the base station.
Instead, the base station measures intensity of total reception signals received via its antenna, thereby indirectly controlling a load amount in reverse link by directing reverse link resource assignment of the same level to all terminals based on the measurement value.
Each of the terminals in the cell receives reverse activity bit (hereinafter abbreviated 'RAB') by each slot from the base station, and the terminal then determines a data rate of next frame with probability based on a value of the received RAB.
If the RAB received from the base station is to lower the data rate, each of the terminals determines whether to lower or maintain the data rate of the next frame with probability according to the current reverse link data rate. If the base station directs to raise the data rate, each of the terminals determines the data rate of the next frame by the same method.
A reverse traffic channel has six kinds of transmission rates shown in Table 1.
TABLE 1Transmission rateMaximum payload(Kbps)(bits)009.623419.249038.4100276.82026153.64076
The terminal uses one of the transmission rates in Table 1 for transmission. In this case, the terminal enables to raises or lowers the transmission rate of reverse traffic channel using the information (RAB) received from the base station.
Thus, each of the terminals in the cell adjusts data rate of reverse link according to RAB set by the base station. RAB setup directly becomes a means for adjusting the load amount of reverse link.
Qualcomm Inc. has proposed two methods for setting RAB, and the first method is recommended.
The first method uses thermal noise power vs. reception signal power (hereinafter abbreviated ROTm). The ROTm is a measurement value (dB basis), which is found by subtracting thermal noise power (Rx Power_Thermal) of a base station system from total reception power (Rx Power_Total) received from an antenna of a receiving-end of base station, for judging a load status of reverse link. ROTm is periodically measured by a RF device in the base station.
If ROTm measured in a receiving-end of an access network per each slot (1.67 ms) for each sector and antenna is higher than a reference value (ROTm_th, 5 dB recommended), RAB is set to '1' to direct to lower transmission data rate of the terminal. If ROTm is lower than the reference value, RAB is set to '0' to direct to raise data rate of the terminal. A basic setup value of RAB is basically '0'.
Meanwhile, the second method uses a calculated ROT value (hereinafter abbreviated 'ROTc'). A reverse load can be found by the second method using an equation. Firstly, a ratio of reception pilot power vs. total reception power is found for each reception data rate using variables such as DataOffsetNorm, DataOffset9k6(9,600).
ROTc that means a reverse link load of a corresponding sector can be found by multiplying a total of f(DataRate) values of the entire access terminals in the sector by Ecp/Io [average energy per chip of pilot channel in antenna vs. PSD(power spectral density) of total reception signals]. Yet, such an equation fails to consider power by ACK channel. The related art method of setting RAB (reverse activity bit) in a communication system has the following problems or disadvantages.
In case of a terminal for 1xEV-DO, since data rate of next frame is determined by probability according to RAB received from a base station, the base station is unable to accurately control or determine a reception load amount in the next frame or a reception signal power of an antenna end despite setting and transmitting the RAB to the terminal.
Second, in case two terminals located close to a base station, with a moderate frame offset difference therebetween, detect RAB to increase data rate, and determine to simultaneously increase their data rates and transmission power, total reception signal power is increased. Also signal vs. noise ratio for each call is degraded, and the terminals competitively raise their transmission power by fast closed loop power control. All of the terminals in the cell will then transmit with maximum power as high as they can.
If such a situation takes place under a ROT value lower than a reference value (ROTm_th), the transmission power is unnecessarily increased. This causes extra power consumption and adversely influences the reverse link of a neighboring cell.
In order to overcome the second problem, the reference value (ROTm_th) is compared to the measured ROT value. If the reference value is lower, the number of times of RAB commands directing the terminal to lower the transmission data rate is increased before a reception capacity limit is reached. This results in reducing the reception capacity of reverse link.
Moreover, since the accuracy of ROT measured by a base station of a current mobile communication system such as 1xEV-DO system is not reliable yet, the related art method of setting RAB by simply comparing the measured ROT value to the reference value ROTm_th has various limitations in many aspects. Hence, a new method enabling to overcome such limitations is needed.

Reverse activity bit setting system and method


An MPEG decoder (100-180) can use different formats (linear tiled etc) for image data memory (150) for reference pictures when decoding subsequent pictures. Each format brings advantages and disadvantages. The disclosure illustrates that it is possible for different video sequences to have characteristics which match one image buffer format well, but not another, for example where there is a lot of motion or only a little motion between images. Advantageously, the decoder employs a parameterised image buffer format and analysis of the incoming stream and/or measured decoding performance (190) so as to dynamically choose (90, 160, 170) the best image buffer format for the current part of a stream. Cache control features can also be controlled (198) to suit the particular data received.

Digital transmission and storage systems generally use block-based compression, as used in the well known JPEG or MPEG formats, to achieve acceptable image quality within the available transmission bandwidth and storage capacity. JPEG is a video compression system based upon performing Discrete Cosine Transformation (DCT) on groups, or blocks, of pixel data. MPEG is a motion video compression system based upon the same principles, but with additional features to support motion between image frames. To achieve substantial data compression, the DCT coefficients representing each block of pixels are subjected to adaptive quanfisation and Variable Length Encoding (VLE). Blocks are also grouped together in fours, to form "Macroblocks", and chrominance (colour) components are represented with half the spatial resolution provided for luminance (brightness) component. These techniques can be applied in both still images (JPEG) and motion video (MPEG). For moving pictures, temporal redundancy between image frames is identified and significantly reduced using motion-compensated inter-frame predictive encoding.
The terminology used for describing MPEG sequences includes 'frames', which contain a complete image, and 'fields', which are half an image, arranged every other line. The unit of decoding, however, is a picture, which can be field or frame structured. An image buffer is used to store both frames and/or fields, depending upon the storage format employed.
Three image picture types, known as 'I', 'B' and 'P' pictures, are used to construct an image sequence for transmitting data across a restricted channel between an encoder and a decoder. A "channel" includes bandwidth-limited communication links and storage of imagery on mass storage media such as hard drives, Compact Disks or video tape (where it is desirable to maximise storage efficiency). 'I' picture frames are "intra" frames, which are similar in construction to a single JPEG frame and contain a complete, moderately compressed, frame of image data. 'P' picture frames are "predictive" frames and are encoded with reference to a previous 'I' or 'P' frame (known as 'key frames') within a video stream. 'B' picture frames are "bi-directional interpolated" frames which require both earlier and later reference frames in order to be encoded.
To support production of an MPEG image sequence data has to be stored in image memory. When 'B' or 'P' frames are being produced, one or two previous source I or P images must have been stored and are referenced to provide motion prediction data.
A typical arrangement for an image processor performing MPEG processing comprises modules (in hardware or software) for inputting data, converting the image between analogue and digital domains (in either direction, depending on whether the processor is an encoder or a decoder), storing the data, performing compression or decompression on the data, compensating for motion, and for outputting the data for subsequent use, such as display.
In order to provide an implementation that is reliable, efficient and providing high quality output, it must be designed to accommodate worst-case conditions which as a result of processor overload would result in frame skipping or other image artefacts that degrade image quality. Furthermore, memory bandwidth is a crucial issue for both hardware and software implementations.
In order to maximise throughput (and therefore reduce the opportunity for processor overload), processors often employ a cache memory with a very high access speed, allowing the processor to obtain data very rapidly. The cache is arranged so that as much data as possible is sourced from the cache, rather than from slower "external" memory. For software implementations in particular, cache size and traffic are often crucial performance-determining factors. Worst-case performance can be significantly affected by cache activity, as it is possible for prediction data to be sourced from widely separated parts of input images resulting in significant "cache thrashing" (significant and substantially unnecessary cache use and discarding of content).
Image memory is often provided as "paged" memory, whereby image data for a picture is stored over many pages, each of which is accessed by the processor by page access. Page access is a very rapid way of accessing data from a paged Random Access Memory (RAM), requiring only the provision by the processor of a base address, after which the data is clocked out and passed to the processor without provision of further addressing to the memory. However, page crossings are inefficient, as they require termination of the current paged memory transfer and generation of new addressing for the next set of data transfer.
It is understood in the field of MPEG image processing that when paged memory is used different storage formats provide different advantages, depending upon the content of the images being processed. Storing image data on a linear basis (for example, following a raster scan) minimises the complexity required to subsequently display the image. However, when linear storage is used for a reference frame of image data for use in motion compensation/reconstruction, retrieval of reference data may require a large number of memory page crossings. Alternatively, storing reference image data in "tiled format" (where two-dimensional blocks of pixels as used in the coding process are stored in sequence in memory) reduces the number of page crossings by taking advantage of the fact that image pixels naturally have a two-dimensional spatial relationship. With this in mind U.S. Pat. No. 5,912,676 describes a re-configurable image memory interface for storing or retrieving image data to/from the memory according to different image storage formats, such as scan line (raster), tiled or "skewed-tiled" formats. However, the present inventors have recognised that, since the content of picture sequences varies greatly in the amount and nature of motion between the frames or fields that make up each picture, it is not possible to select a configuration for the reference data memory that will be the optimum one for all sequences. Accordingly, the US patent provides a range of configurations that may be advantageous if properly selected, but does not define what is the proper configuration. Nor is it possible to define a single configuration that will be optimal in all sequences. The optimal configuration may further depend on what steps are to be performed on the image data after decoding. The need for conversion to another format for a subsequent processing stage may for example negate any saving by adopting a preferred format for a motion estimation stage.

Method and apparatus for processing image data


A turbine component tracking system is provided. The turbine component tracking system is advantageously adapted to determine the remaining life of individual turbine components based on how and where they are used as well as if and how they are repaired. The turbine system is also advantageously adapted to track and analyze design, manufacturing and repair changes or modifications performed on turbine components.

Gas turbine engines are known to include a compressor section for supplying a flow of compressed combustion air, a combustor section for burning fuel in the compressed combustion air, and a turbine section for extracting thermal energy from the combustion air and converting that energy into mechanical energy in the form of a rotating shaft.
Modern high efficiency combustion turbines have firing temperatures that exceed about 2,700° F., and even higher firing temperatures are expected as the demand for more efficient engines continues. Many components that form the "hot gas path" combustor and turbine sections are directly exposed to aggressive hot combustion gasses, for example, the combustor liner, the transition duct between the combustor and turbine sections, and the turbine stationary vanes and rotating blades and surrounding ring segments. In addition to thermal stresses, these and other components are also exposed to mechanical stresses and loads that further wear on the components. Other turbine components, such as electronic and mechanical controllers, fuel metering equipment, auxiliaries, load packages including generators and exciters, and valves similarly receive in-service wear.
It is known to perform detailed periodic scheduled maintenance of turbine components based upon benchmark manufacturer recommendations developed from engineered design parameters in view of anticipated turbine operation conditions. However, a shortcoming of this methodology is that actual turbine operating conditions often appreciably differ from the anticipated turbine operating conditions due to intentional (e.g. running the turbine at higher combustion temperatures) or unintentional (e.g. non-optimal shutdowns, trips, fast cool downs, water washing, and fuel nozzle water purges) reasons. Thus, the components commonly experience temperatures, cycles, loads, stresses, strains, etc. that are greater or less than for which they were designed. Accordingly, Type I and II errors occur in connection with the periodic scheduled maintenance, that is, maintenance is performed when the turbine components are fine (Type I) and maintenance is not performed when the turbine components need to be repaired, refurbished or replaced (Type II).
Several approaches have been taken to address this shortcoming. One approach involves developing less expensive and time consuming inspection and maintenance procedures, such as non-destructive and in-operation examination of the turbine components, for example those described in U.S. Pat. Nos. 4,746,858 and 5,140,528. Another approach involves creating individualized maintenance schedules uniquely associated with and based on the actual operating history of a particular turbine, for example that described in U.S. Pat. No. 6,343,251.
If a unique individual turbine maintenance schedule is created, a problem arises if an individual turbine component is used on more than one turbine. Another problem arises if a component type (e.g. row 1 blade) is not identical with another similar component type (e.g. row 1 blade), for example, if one row 1 blade was manufactured with one type of ceramic thermal barrier coating and another row 1 blade was manufactured with another type of ceramic thermal barrier coating, this difference is not addressed. Another problem arises if some individual component types are repaired or replaced while other individual component types are not repaired or replaced within the turbine. Oftentimes, some components are replaced that still have serviceable life in them to "reset" the clock on the repair cycle.
Accordingly, there is a need for additional approaches to reduce maintenance costs and improve upon the prior art.


A method and apparatus for controlling address power of a plasma display panel and a plasma display panel device having that apparatus, wherein the plasma display panel includes pluralities of address electrodes, scan electrodes, and sustain electrodes, the scan electrodes and sustain electrodes forming pairs and being alternately disposed. After determining an attenuation coefficient that corresponds to a sum of pixel differences between lines throughout an input video signal, output video data is modified by multiplying the attenuation coefficient to the input video data. According to such a power control of address data, power consumption is reduced since the number of times of switching address data is reduced.

Usually, a PDP shows high power consumption due to its driving characteristics. Therefore, control of its power consumption is needed according to a required load of a displayed frame. For the control of the power consumption, a power level is automatically controlled to remain under a limit.
According to the prior art, such automatic power control is only applied to a power source regarding generation of sustain pulses but not to a power source regarding generation of address data. Accordingly, power consumption regarding generation of address data has remained at a high level.
FIG. 1 illustrates image data in a full-white state. In a full-white state where every image data segment will have the value of "1", almost no fluctuation in data is introduced throughout address electrodes, and pulse switching also remains at its minimum. In addition, charging/discharging reactive power also remains small since power consumption proportionally increases with the number of times of switching. A driving signal for such a full-white state may have a waveform as shown in FIG. 2. As shown in FIG. 2, in a full-white state, it is only required to switch once for column 10 in FIG. 1.
However, image data can be of a dot-pattern as illustrated in FIG. 3 wherein image data repeatedly alternates between 1 and 0. Accordingly, a significant amout of switching is required, for example, for column 20. A corresponding driving signal may have a waveform shown in FIG. 4. As shown in FIG. 4, in a dot-pattern, data fluctuation and pulse switching will occur. As a result, power consumption increases.
As can be seen from the above description, power consumption increases as the number of different pixels between a previous line and a current line increases and also because of the increase in switching.

This patent is subject to a terminal disclaimer.

Method and apparatus for controlling address power for a plasma display panel


A voltage adder/subtractor circuit is provided, which has an improved frequency characteristic and which is operable at a low supply voltage such as approximately 1.1 V. This circuit includes a first differential pair of emitter/source-coupled first and second transistors driven by a first constant current, and a second differential pair of emitter/source-coupled third and fourth transistors driven by a second constant current having a same current value as that of the first constant current. A third constant current source/sink serving as a common load for the second and third transistors is connected to the collector/drain of the second transistor and the coupled collector/drain and base/gate of the third transistor. The third constant current source/sink supplies/sinks a third constant current having a same current value as that of the first constant current. A first input voltage is differentially applied across bases/gates of the first and second transistors. A second input voltage is applied to a base/gate of the fourth transistor. An output voltage is derived from the base/gate of the third transistor.

1. Field of the Invention
The present invention relates to a voltage adder/subtractor circuit and more particularly, to a voltage adder/subtractor circuit performing addition or subtraction of two input voltages, which has two differential pairs of bipolar or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETS) and which is formed on a semiconductor integrated circuit (IC).
2. Description of the Prior Art
FIG. 1 shows a conventional bipolar voltage adder circuit.
In FIG. 1, a first differential pair is formed by npn bipolar transistors Q101 and Q102 whose emitters are coupled together. The emitters of the transistors Q101 and Q102 are the same in size and therefore, the first differential pair is a balanced emitter-coupled transistor pair.
The coupled emitters of the transistors Q101 and Q102 are connected to a terminal of a constant current sink 101 sinking a constant current I.sub.0. The other terminal of the current sink 101 is connected to the ground. The first differential pair of the transistors Q101 and Q102 is driven by the constant current I.sub.0.
Bases of the transistors Q101 and Q102 are connected to a pair of input terminals T101 and T102, respectively. A first input voltage V.sub.1 is differentially applied across the bases of the transistors Q101 and Q102 through the pair of input terminals T101 and T102. The polarity of the voltage V.sub.1 is defined as positive when the electrical potential at the terminal T101 is higher than that at the terminal T102.
Diode-connected pnp bipolar transistors Q105 and Q107 are connected to the transistors Q101 and Q102 as their loads, respectively. A base and a collector of the transistor Q105 are coupled together to be connected to a collector of the transistor Q101. An emitter of the transistor Q105 is connected to a power supply (not shown) supplying a constant dc voltage V.sub.cc. A base and a collector of the transistor Q107 are coupled together to be connected to a collector of the transistor Q102. An emitter of the transistor Q107 is connected to the power supply.
A second differential pair is formed by npn bipolar transistors Q103 and Q104 whose emitters are coupled together. The emitters of the transistors Q103 and Q104 are the same in size as those of the transistors Q101 and Q102 and therefore, the second differential pair is also a balanced emitter-coupled transistor pair.
The coupled emitters of the transistors Q103 and Q104 are connected to a terminal of a constant current sink 102 sinking the same constant current I.sub.0 as that of the constant current sink 101. The other terminal of the current sink 102 is connected to the ground. The second differential pair of the transistors Q103 and Q104 is driven by the same constant current I.sub.0 as that of the first differential pair.
A base and a collector of the transistor Q103 are coupled together, i.e., the transistors Q103 has a diode-connection. The coupled base and collector of the transistor Q103 are connected to an output terminal T103. An output voltage V.sub.0 is derived from the coupled base and collector of the transistor Q103 through the output terminal T103. The polarity of the voltage V.sub.0 is defined as positive when the electrical potential at the terminal T103 is higher than that at the ground.
A base of the transistor Q104 is connected to an input terminal T104. A second input voltage V.sub.2 is applied to the base of the transistor Q104 through the input terminal T104. The polarity of the voltage V.sub.2 is defined as positive when the electrical potential at the terminal T104 is higher than that at the ground.
A pnp bipolar transistor Q106 is connected to the transistor Q103 at its load. A collector of the transistor Q106 is connected to the coupled collector and base of the transistor Q103. An emitter of the transistor Q105 is connected to the power supply. A base of the transistor Q106 is connected to the coupled base and collector of the transistor Q105 in the first differential pair, thereby constituting a current mirror circuit. This current mirror circuit makes a collector current of the transistor Q101 to be equal to a collector current of the transistor Q103.
A diode-connected pnp bipolar transistor Q108 is connected to the transistor Q104 as its load. A base and a collector of the transistor Q108 are coupled together to be connected to a collector of the transistor Q104. An emitter of the transistor Q108 is connected to the power supply.
The diode-connected transistors Q107 and Q108 are inserted for the purpose of making the voltages at the collectors of the transistors Q102 and Q104 equal with those at the collectors of the transistors Q101 and Q103. Thus, the operating characteristic matching for the first and second differential pairs is improved.
Ignoring the base-width modulation due to the Early effect, a collector current I.sub.c and a base-to-emitter voltage V.sub.BB of a bipolar transistor have, in general, the following relationship (1). ##EQU1##
In the equation (1), V.sub.T and I.sub.s are the thermal voltage and the saturation current of a bipolar transistor, respectively. The thermal voltage V.sub.T is defined as V.sub.T =(kT)/q!, where k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron.
Here, the following circuit analysis is made on the supposition that the dc common-base current gain factor .alpha..sub.F is set as unity (i.e., .alpha..sub.F =1) and thus, no base current flows through the transistor for the sake of the simplification of description.
Using the above relationship (1), collector currents I.sub.C1, I.sub.C2, I.sub.C3, and I.sub.C4 of the transistors Q101, Q102, Q103, and Q104 are expressed as the following equations (2), (3), (4), and (5), respectively. ##EQU2##
Since the collector of the transistor Q101 is connected to the collector of the transistor Q103 through the current mirror circuit formed by the transistors Q105 and Q106, the following equation (6) is established. EQU I.sub.C1 =I.sub.C3 ( 6)
The equation (6) means that the right side of the equation (2) is equal to the right side of the equation (4), resulting in a relationship of V.sub.1 =V.sub.0 -V.sub.2.
Consequently, the following equation (7) is obtained. EQU V.sub.0 =V.sub.1 +V.sub.2 ( 7)
The equation (7) indicates that the output voltage V.sub.0 is equal to the sum of the first and second input voltages V.sub.1 and V.sub.2. Thus, it is seen that the circuit shown in FIG. 1 has a function of adding the two input voltages V.sub.1 and V.sub.2.
FIG. 2 shows a conventional MOS voltage subtractor circuit.
In FIG. 2, a first differential pair is formed by n-channel MOSFETs M101 and M102 whose sources are coupled together. The gate-width (W) to gate-length (L) ratio (W/L) of the MOSFETs M101 and M102 are the same and therefore, the first differential pair is a balanced source-coupled transistor pair.
The coupled sources of the MOSFETs M101 and M102 are connected to a terminal of a constant current sink 111 sinking a constant current I.sub.0. The other terminal of the current sink 111 is connected to the ground. The first differential pair of the MOSFETs M101 and M102 is driven by the constant current I.sub.0.
Gates of the MOSFETs M101 and M102 are connected to a pair of input terminals T101 and T102, respectively. A first input voltage V.sub.1 is differentially applied across the gates of the MOSFETs M101 and M102 through the pair of input terminals T101 and T102 The polarity of the voltage V.sub.1 is defined as positive when the electrical potential at the terminal T101 is higher than that at the terminal T102.
Diode-connected p-channel MOSFETs M105 and M107 are connected to the MOSFETs M101 and M102 as their loads, respectively. A gate and a drain of the MOSFET M105 are coupled together to be connected to a drain of the MOSFET M102. A source of the MOSFET M105 is connected to a power supply (not shown) providing a supply voltage V.sub.DD. A gate and a drain of the MOSFET M107 are coupled together to be connected to a drain of the MOSFET M101. A source of the MOSFET M107 is connected to the power supply.
A second differential pair is formed by n-channel MOSFETs M103 and M104 whose sources are coupled together. The gate-width (W) to gate-length (L) ratio (W/L) of the MOSFETs M103 and M104 are the same and therefore, the second differential pair is also a balanced source-coupled transistor pair.
The coupled sources of the MOSFETs M103 and M104 are connected to a terminal of a constant current sink 112 sinking the same constant current I.sub.0 as that of the constant current sink 111. The other terminal of the current sink 112 is connected to the ground. The second differential pair of the MOSFETs M103 and M104 is driven by the same constant current I.sub.0 as that of the first differential pair.
A gate and a drain of the MOSFET M103 are coupled together, the MOSFET M103 has a diode-connection. The coupled gate and drain of the MOSFET M103 are connected to an output terminal T103. An output voltage V.sub.0 is derived from the coupled gate and drain of the MOSFET M103 through the output terminal T103. The polarity of the voltage V.sub.0 is defined as positive when the electrical potential at the terminal T103 is higher than that at the ground.
A gate of the MOSFET M104 is connected to an input terminal T104. A second input voltage V.sub.2 is applied to the gate of the MOSFET M104 through the input terminal T104. The polarity of the voltage V.sub.2 is defined as positive when the electrical potential at the terminal T104 is higher than that at the ground.
A p-channel MOSFET M106 is connected to the MOSFET M103 as its load. A drain of the MOSFET M106 is connected to the coupled drain and gate of the MOSFET M103. A source of the MOSFET M106 is connected to the power supply. A gate of the MOSFET M106 is connected to the coupled gate and drain of the MOSFET M105 in the first differential pair, thereby constituting a current mirror circuit. This current mirror circuit makes a drain current of the MOSFET M102 to be equal to a drain current of the MOSFET M103.
A diode-connected p-channel MOSFET M108 is connected to the MOSFET M104. A gate and a drain of the MOSFET M108 are coupled together to be connected to a drain of the MOSFET 104. A source of the MOSFET M108 is connected to the power supply.
The diode-connected MOSFETs M107 and M108 are inserted for the purpose of making the voltages at the drains of the MOSFETs M101 and M104 equal with those at the drains of the MOSFETs M102 and M103. Thus, the operating characteristic matching for the first and second differential pairs is improved.
Ignoring the channel-length modulation and the body effect, and supposing the square-law characteristic between a drain current I.sub.D of a MOSFET and a gate-to-source voltage V.sub.GS thereof, the drain current I.sub.D and the gate-to-source voltage V.sub.GS have, in general, the following relationships (8a) and (8b). ##EQU3##
In the equation (8a), .beta. is the transconductance parameter and V.sub.TH is the threshold voltage of a MOSFET. The transconductance parameter .beta. is expressed as .mu.(C.sub.ox /2) (W/L), where .mu. is the effective carrier mobility, C.sub.ox is the gate-oxide capacitance per unit area, and W and L are a gate-width and a gate-length of a MOSFET, respectively.
Accordingly, drain currents I.sub.D1, I.sub.D2, I.sub.D3, and I.sub.D4 of the MOSFETs M101, M102, M103, and M104 are expressed as the following equations (9), (10), (11), and (12), respectively. ##EQU4##
Since the drain of the MOSFET M102 is connected to the drain of the MOSFET M103 through the current mirror circuit formed by the MOSFETs M105 and M106, the following equation (13) is established. EQU I.sub.D2 =I.sub.D3 ( 13)
The equation (13) means that the right side of the equation (10) is equal to the right side of the equation (11), resulting in a relationship of V.sub.1 =V.sub.2 -V.sub.0.
Consequently, the following equation (14) is obtained. EQU V.sub.0 =-V.sub.1 +V.sub.2 ( 14)
The equation (14) indicates that the output voltage V.sub.0 is equal to the difference of the first and second input voltages V.sub.1 and V.sub.2. Thus, it is seen that the circuit shown in FIG. 2 has a function of subtracting the first input voltage V.sub.1 from the second input voltage V.sub.2.
Unlike the equation (7), the polarity of the first input voltage V.sub.1 is negative in the equation (14). This is because the MOSFET M105 is not connected to the MOSFET M101 but the MOSFET M102. The polarity of the first input voltage V.sub.1 may be readily turned to be positive by replacing the MOSFET M105 with the MOSFET M107. Therefore, it is seen that the circuit shown in FIG. 2 may be changed to a voltage adder circuit.
A voltage adder circuit and a voltage subtractor circuit form essential and frequently-used functional blocks in analog signal processing. Especially, in recent years, the need for a voltage adder/subtractor circuit that is operable at a possibly-low supply voltage and superior in frequency characteristic has been becoming stronger and stronger. From this viewpoint, the above-described conventional voltage adder and subtractor circuits in FIGS. 1 and 2 have the following problems.
Specifically, with the conventional voltage adder and subtractor circuits shown in FIGS. 1 and 2, a signal current is supplied from the first differential pair to the second differential pair through the current mirror circuit formed by the pnp bipolar transistors Q105 and Q106 or p-channel MOSFETs M105 and M106, respectively. As a result, the linear range of the frequency characteristic is unsatisfactorily narrow.
Moreover, with the conventional bipolar voltage adder circuit shown in FIG. 1, the voltages need to be approximately equal at the collectors of the transistors Q101, Q102, Q103, and Q104 forming the first and second differential pairs for the purpose of matching the operations of the first and second differential pairs. For this reason, the power supply voltage V.sub.cc is required to be considerably high.
For example, if each of the constant current sinks 101 and 102 is composed of a simplest current mirror circuit including only two bipolar transistors, it has the inter-terminal voltage of at lowest 0.2 V. Also, each of the transistors Q101, Q102, Q103, Q104, Q105, Q106, Q107, and Q108 typically has the base-to-emitter voltage of approximately 0.7 V. Therefore, the power supply voltage V.sub.cc needs to be approximately 1.6 V (=0.7+0.7+0.2) at lowest.
Similarly, with the conventional MOS voltage subtractor circuit shown in FIG. 2, the voltages need to be approximately equal at the drains of the MOSFETs M101, M102, M103, and M104 forming the first and second differential pairs for the purpose of matching the operations of the first and second differential pairs. For this reason, the power supply voltage VDD is required to be considerably high.

Voltage adder/subtractor circuit with two differential transistor pairs


The present invention is directed to a tilt-in-space wheelchair that limits the shift of the center of a gravity of a wheelchair occupant during tilting. The wheelchair comprises a main frame adapted to be supported on a surface by wheels, a seat frame for supporting a occupant, and an arc plate for slidably or rollably supporting the seat frame with respect to the main frame. The arc plate defines a first track and a second track that guide the tilting of the seat frame relative to the frame. The first track and second track may have non-constant curvatures. Further, the first track and second track may be arranged non-concentrically on the arc plate and may have different lengths.

The pressure from sitting in a single position for an extended period of time cuts off circulation to vulnerable parts of the body. As a result, patients who are bound to a wheelchair for extended periods of time may develop pressure sores or pressure ulcers. Tilt-in-space wheelchairs have been developed to transfer pressure from the seat surface to the back surface by tilting or reclining a seated patient. While conventional tilt-in-space wheelchairs are effective at shifting weight and pressure for patients who cannot otherwise do so, they are deficient in other ways. For example, some tilt-in-space wheelchairs may cause sudden shifts in the center of gravity of a seated patient. A sudden shift in the center of gravity of a patient may produce a falling sensation and a startle reflex as a result. Startle reflex may cause hypertonia in some patients, which is characterized by increased tightness of muscle tone that may lead to loss of function and deformity.
U.S. Pat. No. 7,007,965 is directed to a tilt-in-space wheelchair having a seat supported relative to a base by a rocker that has a constant curvature and is designed to maintain the center of gravity of a wheelchair occupant at a fixed location during tilting. In order for the center of gravity of the wheelchair occupant to remain at a fixed location during tilting, however, the focal point of the curve of the rocker must coincide with the center of gravity of the wheelchair occupant. Because different wheelchair occupants may have different centers of gravity that may not be easily determined, the wheelchair may need significant adjustments to ensure that the focal point of the curve of the rocker coincides with the center of gravity of the wheelchair occupant.


A method is provided in a user equipment node for dynamically selecting a random access response window value for use with random access procedures in a network. The method comprises the step of determining if a random access response window value is being signalled from the network for a first serving cell currently associated with the user equipment node. If so, the random access response window value being signalled for the first serving cell is used when performing a random access procedure in the first serving cell. If not, an alternative random access response window value for the first serving cell is used when performing a random access procedure in the first serving cell.

Current handling of the random access response window imposes unnecessary restrictions on the network and user equipment nodes (UEs).
Long Term Evolution (LTE) uses Orthogonal Frequency Division Multiplexing (OFDM) in a downlink and Discrete Fourier Transform (DFT) spread OFDM in the uplink. The basic LTE downlink physical resource can thus be seen as a time-frequency grid 101 as illustrated in FIG. 1, where each resource element 103 corresponds to one OFDM subcarrier during one OFDM symbol interval.
Referring to FIG. 2, in the time domain, LTE downlink transmissions are organized into radio frames 201 of 10 ms, each radio frame consisting of ten equally-sized subframes 2030 to 2039, each of length Tsubframe=1 ms.
Furthermore, the resource allocation in LTE is typically described in terms of resource blocks (RB), where a resource block corresponds to one slot (0.5 ms) in the time domain and 12 contiguous subcarriers in the frequency domain. A pair of two adjacent resource blocks in the time direction (1.0 ms) is known as a resource block pair. Resource blocks are numbered in the frequency domain, starting with "0" from one end of the system bandwidth.
The notion of virtual resource blocks (VRB) and physical resource blocks (PRB) has been introduced in LTE. The actual resource, allocation to a UE is made in terms of VRB pairs. There are two types of resource allocations, localized and distributed. In the localized resource allocation, a VRB pair is directly mapped to a PRB pair, hence two consecutive and localized VRB are also placed as consecutive PRBs in the frequency domain. On the other hand, the distributed VRBs are not mapped to consecutive PRBs in the frequency domain; thereby providing frequency diversity for data channel transmitted using these distributed VRBs.
Downlink transmissions are dynamically scheduled. That is, in each subframe the base station transmits control information relating to which terminals data is transmitted and upon which resource blocks the data is transmitted, in the current downlink subframe. This control signaling is typically transmitted in the first 1, 2, 3 or 4 OFDM symbols in each subframe and the number n=1, 2, 3 or 4 is known as the Control Format Indicator (CFI). The downlink subframe also contains common reference symbols (CRS), which are known to the receiver and used for coherent demodulation of e.g. the control information. A downlink system with CFI=3 OFDM symbols as control is illustrated in FIG. 3.
The release 10 of the LTE specifications (LTE Rel-10) have been standardized, supporting Component Carrier (CC) bandwidths up to 20 MHz (which is the maximal LTE Rel-8 carrier bandwidth). An LTE Rel-10 operation wider than 20 MHz is possible and appears as a number of LTE CCs to an LTE Rel-10 terminal. One way to obtain bandwidths wider than 20 MHz is by means of Carrier Aggregation (CA). CA implies that an LTE Rel-10 terminal can receive multiple CC, where the CC have, or at least the possibility to have, the same structure as a Rel-8 carrier. CA is illustrated in FIG. 4, whereby five 20 MHz CCs 4011 to 4015 are shown as being aggregated to provide a bandwidth of 100 MHz.
The Rel-10 standard of LTE support up to 5 aggregated CCs where each CC is limited in the RF specifications to have a one of six bandwidths namely 6, 15, 25, 50, 75 or 100 RB (corresponding to 1.4, 3 5 10 15 and 20 MHz respectively).
The number of aggregated CCs as well as the bandwidth of the individual CCs may be different for uplink and downlink. A symmetric configuration refers to the case where the number of CCs in downlink (DL) and uplink (UL) is the same whereas an asymmetric configuration refers to the case that the number of CCs is different in downlink and uplink. The number of CCs configured in the network may be different from the number of CCs seen by a terminal: A terminal may, for example, support more downlink CCs than uplink CCs, even though the network offers the same number of uplink and downlink CCs.
CCs are also referred to as cells or serving cells. More specifically, in an LTE network the cells aggregated by a terminal are denoted primary Serving Cell (PCell) and secondary Serving Cells (SCells). The term serving cell comprises both PCell and SCell. All UEs have one PCell and which cell is a UEs PCell is terminal specific and is considered "more important", i.e. vital control signaling and other important signaling is typically handled via the PCell. Uplink control signaling is sent on a UEs PCell. The component carrier configured as the PCell is the primary CC whereas all other component carriers are secondary serving cells.
During initial access a LTE Rel-10 terminal behaves similar to a LTE Rel-8 terminal. However, upon successful connection to the network a Rel-10 terminal may—depending on its own capabilities and the network—be configured with additional serving cells in the uplink and downlink. Configuration is based on radio resource control (RRC). Due to the heavy signaling and rather slow speed of RRC signaling it is envisioned that a terminal may be configured with multiple serving cells even though not all of them are currently used.
Random Access
In LTE, as in any communication system, a mobile terminal may need to contact the network (via the eNodeB) without having a dedicated resource in the Uplink (from UE to base station). To handle this, a random access procedure is available where a UE that does not have a dedicated uplink resource may transmit a signal to the base station. The first message (MSG1 or preamble) of this procedure is typically transmitted on a special uplink resource 501 reserved for random access, a physical random access channel (PRACH), with other uplink resources 503 being used for data transmission. This channel can for instance be limited in time and/or frequency (as in LTE), as shown in FIG. 5.
The resources available for PRACH transmission is provided to the terminals as part of the broadcasted system information (or as part of dedicated RRC signaling in case of handover, for example).
In LTE, the random access procedure can be used for a number of different reasons. Among these reasons are:                Initial access (for UEs in the LTE_IDLE or LTE_DETACHED states)        Incoming handover        Resynchronization of the UL        Scheduling request (for a UE that is not allocated any other resource for contacting the base station)        Positioning
A contention-based random access (CBRA) procedure used in LTE is illustrated in FIG. 6. The UE starts the random access procedure by randomly selecting one of the preambles available for contention-based random access. The UE then transmits the selected Random Access Preamble message 601 on the physical random access channel (PRACH) to a network node such as an eNode B in the network.
The network acknowledges any preamble it detects by transmitting a Random Access Response message 603 (MSG2) including an initial grant to be used on the uplink shared channel, a temporary Cell-Radio Network Temporary Identifier (C-RNTI), and a time alignment (TA) update based on the timing offset of the preamble measured by the eNodeB on the PRACH. The Random Access Response message 603 (MSG2) is transmitted in the downlink to the UE and its corresponding Physical Downlink Control Channel (PDCCH) message's Cyclic Redundancy Check (CRC) is scrambled with the Random Access-Radio Network Temporary Identifier (RA-RNTI).
When receiving the Random Access Response message 603 (MSG2) the UE uses the grant to transmit a Scheduled Transmission message 605 (MSG3) that in part is used to trigger the establishment of radio resource control and in part to uniquely identify the UE on the common channels of the cell. The timing advance command provided in the Random Access Response message 603 is applied in the UL transmission in the Scheduled Transmission message 605 (MSG3). The eNodeB can change the resources blocks that are assigned for a Scheduled Transmission message 605 (MSG3) by sending an uplink grant, the CRC of which is scrambled with the Temporary Cell-Radio Network Temporary Identifier (TC-RNTI).
The Contention Resolution message 607 (MSG4) then has its PDCCH CRC scrambled with the C-RNTI if the UE previously has a C-RNTI assigned. If the UE does not have a C-RNTI previously assigned, it has its PDCCH CRC scrambled with the TC-RNTI.
The procedure ends with the network solving any preamble contention that may have occurred for the case that multiple UEs transmitted the same preamble at the same time. This can occur since each UE randomly selects when to transmit and which preamble to use. If multiple UEs select the same preamble for the transmission on RACH, there will be contention between these UEs that needs to be resolved through the Contention Resolution message 607 (MSG4). The case when contention occurs is illustrated in FIG. 7, where two UEs 7011 and 7012 transmit the same preamble, p5, at the same time. A third UE 7013 also transmits at the same RACH, but since it transmits with a different preamble, p1, there is no contention between this UE 7013 and the other two UEs 7011 and 7012.
It is noted that a UE can also perform non-contention based random access. A non-contention based random access or contention free random access (CFRA) can, for example, be initiated by the eNodeB to get the UE to achieve synchronisation in the uplink. The eNodeB initiates a contention free random access either by sending a PDCCH order or indicating it in an RRC message. The later of the two is used in case of handover.
The eNodeB can also order the UE through a PDCCH message to perform a contention based random access; the procedure for this being illustrated in FIG. 8. The eNodeB transmits a Random Access Order message 801 to a UE, and a UE will transmit a Random Access Preamble message 803 to the eNodeB. Similar to the contention based random access described in FIG. 6, a Random Access Response message 805 (MSG2) is transmitted in the downlink to the UE and its corresponding PDCCH message CRC is scrambled with the RA-RNTI. The UE considers the contention resolution successfully completed after it has received the Random Access Response message 805 (MSG2) successfully.
For the contention free random access, in a similar manner to the contention based random access, the Random Access Response message 805 (MSG2) contains a timing alignment value. This enables the eNodeB to set the initial/updated timing according to the UEs transmitted preamble.
In LTE in Rel-10 the random access procedure is limited to the primary cell only. This implies that the UE can only send a preamble on the primary cell. Further a Random Access Response message 603 (MSG2) and a Scheduled Transmission message 605 (MSG3) is only received and transmitted on the primary cell. A Contention Resolution message 607 (MSG4) can, however, in Rel-10 be transmitted on any downlink cell.
In LTE Rel-11 random access procedures will be supported also on secondary cells, at least for the UEs supporting Rel-11 carrier aggregation. So far only network initiated random access on SCells is assumed.
Random Access Response Window
After a UE has sent a preamble it listens for a random access response from the network for a certain time, this time period given by the value of a random access response window. After a time equal to the random access response window has passed the UE considers the preamble transmission to be unsuccessful and resends the preamble. Each time the UE resends the preamble the UE will increase the output power used to transmit the preamble to increase the chance of a successful preamble transmission. The UE will transmit a maximum number of preambles given by a value "preamble transmission maximum".
In LTE Rel-10 with the introduction of carrier aggregation the UE is able to aggregate multiple carriers, i.e. to be configured with a PCell and SCells. For LTE Rel-11 a UE is able to perform random access procedures on SCells. In contrary to the PCell, however, there is no way of signaling the parameters necessary for performing a random access procedure on SCells. In particular, the RA response window value is currently discussed in 3GPP whether it shall be signaled for SCells or not. If it is signaled for SCells the UE would use the RA response window value for the SCell where the RA procedure is performed while if the RA response window is not signaled for SCells the UE would apply the RA response window value for the PCell when performing RA on SCells. If the UE applies a cell specific RA response window the network implementation might become more complex than the case if a UE always applies the RA response window of the PCell also for RA procedures performed on SCells. However, having cell specific RA response windows will increase flexibility. One network vendor, vendor A, might prefer to avoid this extra complexity and hence prefer to not signal RA response window values for SCells. Another network vendor, vendor B, might judge that the extra complexity is justified to obtain the added flexibility it would mean to have RA response window values for SCells. If the LTE specification is specified so that different cells are configured with different SCell RA response windows, vendor A is forced to specify RA response windows for different SCells. If the LTE specification is specified so that the UE applies the PCells RA response window also for SCell RA procedures, vendor B will not have the flexibility it wants. A disadvantage of this is that both vendor A and vendor B's needs cannot be met with current solutions.
As described above two types of RA procedures are defined; contention based random access (CBRA) and non-contention based random access or contention free random access (CFRA). These two types of RA procedures are used for different purposes and in different situations. For example CBRA is used by UEs when performing initial access to the network while CFRA is used when a UE is achieving uplink time alignment on SCells in a secondary TA group. With current solutions the UE applies the same RA response window for these two types of RA which puts unnecessary restrictions on the network and UE.

Apparatus and method for dynamically selecting a random access response window value for use with random access procedures in a network


Defective portions, such as black dot defects, in an emulsion layer of an emulsion mask such as a photomask are repaired or removed by irradiating an ultraviolet laser beam from a laser oscillator, preferably an excimer laser. The laser beam is passed through an adjustable aperture for shaping and is then projected onto defective portions in dimensional alignment, whereby the defective portions are destroyed. In order to ensure that only the defective portions are destroyed, the image of the aperture projected on the emulsion layer is observed so as not to cover the emulsion mask where defective portions do not exist. Defective portions such as white defects can also be repaired by using additional procedure together with the irradiation of the laser beam.

The present invention relates to a method and an apparatus for repairing defects in emulsion masks and the like, and, in particular, to an apparatus and a method for removing defective portions existing in emulsion masks which are a type of photomasks used in the lithographic processes that is one of the processes for the manufacture of photoelectroformed products and photoetched products used for manufacturing semiconductors and the like, and for removing defective portions existing in patterns of organic layers (hereinafter also called emulsion masks) of color filters for LCD and CCD.
In recent years, increasingly fine patterns are required in connection with higher levels of integration of IC and LSI, and the patterns of semiconductor elements have tended to have higher levels of accuracy and quality. Apart from semiconductor elements, high accuracy and high quality are also required in the case of, for example, photoetched products such as shadow masks for color televisions, print circuit boards, electrodes for various types of display tubes and the lines of optical measuring apparatus, and in the case of photoelectroformed products such as meshes for camera tubes, electron microscope meshes, and other meshes for filtering. The recent photofabrication technology has enabled the achievement of degrees of fineness and accuracy that were not possible with the conventional mechanical process method, and a high accuracy of pattern is required for the photomasks used in the photofabrication technology.
In such photomasks that require a high pattern accuracy, it is necessary to repair small defects that occur in the mask manufacturing process.
Currently, photomasks are classified by their materials, into two types of emulsion masks and hard masks. Emulsion masks have a high-resolution photographic emulsion applied to the surface of a glass substrate.
Ordinary emulsion layer of the emulsion masks can be of either a silver emulsion or a non-silver emulsion, and the thickness of the layer is usually from 2 to 6 .mu.m. Hard masks have a light intercepting metal film such as that of chrome, ferric oxide or tantalum, for example, deposited onto the surface of a glass substrate using either the vapor deposition or spattering method to form a film with a thickness of approximately 0.1 .mu.m.
The defects that can occur in the photomask manufacturing method are black defects such as black dots and the like, and white defects such as pinholes and loss, etc. The method of correcting black dots and pinholes differ according to the type of photomask.
In the case of hard masks, the specific method that is generally used to repair black dot defects such as a black spot or a protruding portion is to apply to the area other than the defects a photoresist or mask of a material that does not corrode the metal layer and to then remove the defects by etching. In the case where fine black dot defects of the order of 1 .mu.m have to be removed, then a positive resist such as the OFPR resist (product of Tokyo Oka Kabushiki Kaisha) is applied and then the light from a mercury lamp is focussed with a size of approximately 1 .mu.m onto the resist on the defect to expose the resist. The exposed resist is then removed by developing processing and then an etching liquid is used to remove the light intercept metal film.
In the case of emulsion masks, the method of repairing defects is different because the emulsion layer is thick and there is no corrosive liquid such as used in the case of metals. For example, one of the methods for repairing black dot defects is to cut out the defect using the sharp end portion of a cutter knife or the like but the application of this method is limited to those instances where accuracy is not required or where those portions having defects are not connected to or adjacent to those portions that do not have defects. This method is not suitable for repairing the photomasks used for semiconductor manufacture or for fine processing. A repairing method using a YAG laser has been proposed in order to eliminate this deficiency. (Japanese Patent Laid Open Publication No. 60-207335)
In the case of a hard mask, white defects such as a pinhole or missing portion are removed by a method that involves applying a photoresist to the entire surface of the mask, exposing the portion of the photoresist on the fault and then developing the photoresist so that only that portion of the resist that was on the defect is removed. Thereafter, in this status, by using either the vapor deposition or the spattering method, a light intercepting film of a metal such as chrome is formed. Then, separating the photoresist leaves the light intercepting film only on the defects so that white defects such as pinholes and the like are rendered light-intercepting.
Hard masks have dimensions in the order of several inches square but the size of emulsion masks is large and is in the order of 20 to 40 inches. For this reason, in the case of the emulsion masks, the series of methods described above, which use vapor deposition and spattering, require large-scale coating apparatus and large-scale vacuum apparatus and the like. Since this is difficult as far as the facilities are concerned, it is more general to cover the defect by India ink applied manually using a brush having a fine hair tip.
With the pattern repairing method described above for black dot defects, a YAG laser with a wavelength of 1060 nm and a second harmonic of 530 nm enables fine defect repair, but the portion around that portion for which removal processing was performed swells. In addition, the removal of the defect portion cannot be made linear and so there is the problem of ruggedness.
When a YAG laser is used for defect removal, the swell of the peripheral portion of the defect amounts to 50% of the thickness of the layer and this becomes a cause of improper contact in uses where contact exposure is performed, thereby causing problems for its practical use. In addition, the non-linearity of the removed portion also presents a problem of quality now that finer patterns are being required.
In addition, the previously described method for the repair of white defect has its application limited to those which do not require precision and for which the defects are not connected to or adjacent to portions that do not have defects, and it is not possible to use it for the repair in the case of photomasks used for semiconductor manufacturing or fine processing.

Method and apparatus for repairing defects in emulsion masks and the like


Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

Computer memory is a technology consisting of semiconductor devices arranged to retain digital data. It is a fundamental component of computers. Resistive random access memory (RRAM) and magnetic random access memory (MRAM) are two types of memory garnering attention.
In RRAM, the basic idea is that a resistance of a dielectric can be changed to store different states depending on the voltage applied to it. To form an array, a number of memory elements can be arranged in a configuration where parallel bitlines are crossed by perpendicular wordlines with the variable resistance dielectric placed between wordline and bitline at every cross-point. This configuration is called a cross-point cell. Unfortunately, since this architecture can lead to a large "sneak" parasitic current flowing through non selected memory cells via neighboring cells, the cross-point array has a very slow read access. An access element can be added to improve the situation, but conventional access elements consume significant area on the chip. The present disclosure relates to vertical bipolar junction transistors (BJTs) that can be used as access elements to reduce the area of individual memory cells, thereby increasing the density of the memory array.

Taiwan Semiconductor Manufacturing Co., Ltd.


A liquid tank capable of detecting liquid level when the tank is rotated. The liquid tank includes an airtight vessel to store the liquid; and at least two electrodes installed inside the airtight vessel. The distal ends of the electrodes are positioned at a central volume of the airtight vessel. A fuel cell adopting the liquid tank maintains the liquid level in the tank near 50% of the full level even when the fuel cell is rotated.

1. Field of the Invention
Aspects of the present invention relate to a liquid tank within a fuel cell system, and more particularly, to a liquid tank capable of detecting a liquid level even when the fuel cell system is rotated.
2. Description of the Related Art
In general, a fuel cell is a power generation system that directly converts chemical energy into electrical energy by the electrochemical reaction of hydrogen and oxygen. Hydrogen is supplied to the fuel cell by reforming methanol, ethanol, and natural gas, etc. Oxygen is generally supplied thereto from air by using an air pump, etc.
Fuel cells include polymer electrolyte fuel cells and direct methanol fuel cells operated at a temperature of about 100° C. or less, phosphoric acid fuel cells operated at about 150° C. to 200° C., molten carbonate fuel cells operated at high temperatures of about 600° C. to 700° C., and solid oxide fuel cells operated at higher temperatures of about 1000° C. or more, etc. These fuel cells generally operate to generate electricity in the same manner but are different in view of the types of fuels, catalysts, and electrolytes used, etc.
Among others, the direct methanol fuel cell (DMFC) uses a fuel that is a mixture of high concentration liquid methanol and water instead of using hydrogen as the fuel. The DMFC is lower in output density than fuel cells using hydrogen directly. However, the DMFC has a high energy density per volume of methanol used, and methanol fuel is easily stored. Also, the DMFC is well adapted to operate at a low output for a long time. Also, the DMFC can be compactly constructed because the DMFC needs no additional devices, such as a reformer to reform fuel to generate hydrogen, etc.
The DMFC includes a membrane electrode assembly (MEA) configured of a polymer electrolyte membrane to which an anode and a cathode are closely adhered to opposite sides. As a polymer electrode membrane, generally fluoropolymers are used. However, the methanol is rapidly soaked into the fluoropolymer membrane when the DMFC uses a high concentration of methanol as fuel causing a crossover phenomenon of transmitting non-reactive methanol to the polymer electrolyte membrane. Accordingly, in order to lower the concentration of methanol, the fuel mixture of methanol and water is supplied to the fuel cell system.
Meanwhile, the polymer electrolyte membrane fuel cell (PEMFC) uses hydrogen generated by reforming substances, such as methanol, ethanol, natural gas, etc., and has a remarkably high output, a low operating temperature, and rapid starting and response characteristics. Therefore, the PEMFC is widely applicable to transportable power sources, such as automobiles, as well as distributed power sources, such as houses or public buildings, etc., and as power sources for small mobile equipment, such as personal digital assistants (PDAs).
The PEMFC requires pure hydrogen to generate electricity. PEMFCs achieve this by using catalyst reactions, such as steam reforming (SR) and water gas shift (WGS), etc. PEMFCs also require the removal of carbon monoxide, which is a byproduct of the above hydrogen-generating methods and which poisons the catalyst of the fuel cell when included in the hydrogen.
For continuous operation of the fuel cell, the fuel mixture for both DMFCs and PEMFCs is continuously supplied. Thus, it is necessary to maintain the fuel mixture at a constant level. Generally, a conventional fuel cell includes a device to maintain the amount of the fuel in a tank at a predetermined liquid level that detects the amount of the fuel using, for example, ultrasonic waves, etc. However, the construction of such fuel cells is complicated, and the liquid level cannot be measured when the fuel cell is rotated.

Liquid tank using fuel cell system and liquid level detection device


There is provided a variable gain circuit system which is inductorless and capable of achieving a high gain and a wide band by elements for achieving variable gain to prevent decreasing a gain or deteriorating the band. The variable gain circuit includes: transistors; a resistor connected as a load of each transistor; a voltage source applying a bias voltage to each gate of the transistors; a switch selectively connecting the voltage source or a ground potential to each gate of the transistors in accordance with gain setting; and a current source connected to a common input. A drain of each transistor is connected to an input of a circuit in a subsequent stage.

Along with increase in a traffic volume of the Internet, it has been required to improve a transmission speed of a SerDes used for an information processing device such as an optical module, router/server, and a RAID. Meanwhile, as seen in Green IT, reduction in a power consumption of the information device has been advanced, and reduction in the power consumption of the SerDes has also been required.
Conventionally, as the SerDes, there has been a technique disclosed in, for example, "Equalizer Implementation for 10 Gbps Serial Data Link in 90 nm CMOS Technology.", IEEE ICM-December 2007, written by Ahmed Abd El-Fattah (Non-Patent Document 1).
Here, an example of a conventional SerDes will be described with reference to FIGS. 9 to 11. FIG. 9 is a configuration diagram illustrating an example of the conventional SerDes, FIG. 10 is a configuration diagram illustrating an example of a conventional receiver, and FIG. 11 is a circuit diagram illustrating a configuration of a conventional variable gain circuit.
In FIG. 9, the SerDes is composed of: a sending unit 704 composed of a driver 701 and a parallel/serial converting circuit 702; and a receiving unit 705 composed of a receiver 208 including a variable gain circuit 201 and a serial/parallel converting circuit 703.
In FIG. 10, the receiver 208 is composed of: the variable gain circuit 201; an equalizer circuit 202; a limit amplifier 203; input terminals 204 and 205; and output terminals 206 and 207. The variable gain circuit 201 matches an input resistance of the receiver with a characteristic impedance of a substrate wiring to suppress reflection noises and equalizes variations in an input signal amplitude due to a difference in a wiring length.
A high-frequency property and power consumption of the receiving device are influenced by the variable gain circuit.
In FIG. 11, the conventional variable gain circuit 201 has a configuration in which, resistors 1001 and 1002 and output terminals 1008 and 1009 are connected to drains, current sources 1007 and 1006 are connected to sources, and a variable resistor 1005 is inserted between sources of transistors 1003 and 1004, and a gain is varied by changing a resistance value of the variable resistor 1005. Moreover, terminating resistors 1012 and 1013 are connected to input terminals 1010 and 1011, respectively, to be matched with the characteristic impedance of the substrate wiring.