A system and a method for accessing data by a client computer system from a server computer system, the client computer system including one or more processors configured to execute computer program modules, are described. The method includes receiving, by the client computer system from an application program, a read request to read at least a portion of a data file; sending, by the client computer system to the server computer system, a request for exact data corresponding to the at least the portion of the data file requested by the application program in the read request; receiving, by the client computer system from the server computer system, a response to the request including the exact data requested by the client computer system; and providing, by the client computer system to the application program, the exact data in response to the read request.

1. Field of the Invention
The present invention pertains to a method and a system of accessing data, for example using a HTTP-based protocol.
2. Discussion of Related Art
An application program (also referred to herein as "an application"), a client program (also referred to herein as "a client") and a server program (also referred to herein as "a server") are computer software programs that run on a computer system (i.e., one or more computer systems having one or more processors). A computer system is a physical computer device such as, but not limited to, a desktop computer, a server computer, or a laptop computer; or a virtual computer device for example a Virtual Machine (VM). A computer system runs an operating system. An operating system provides access to one or more files stored on that computer system using a collection of computer software modules, also known as function calls. For example, an operating system such as Linux, can implement the published POSIX standard to provide a collection of function calls to open, close, read or write files.
Interchange of computer data using a client program and server program is a well-known technology. A client program communicates with a server program using a communication protocol over a network, for example a LAN, WAN or the Internet. Examples of a communication protocol are TCP, UDP, HTTP, HTTPS, socket-based communication, HTTP 1.1 WebDAV. A client sends a request for data to a server. Based on that request a server sends data that is a response to that request.
The client program and the server program may be running on the same computer or separate computers. A client program may be running on one or more computers. A server program may be running on one or more computers. The computers running clients and servers are connected to each other in some form over the network.
Server and client programs follow some type of communication protocol to be able to understand each other. A client asks a server about its capabilities. The server then responds with a list of services it offers. The client may utilize the services to fulfill its goals by making additional requests to the server.
The HTTP protocol is popular and a well-known standard for communicating over a computer network, for example LAN, WAN and the Internet or the World Wide Web (WWW). A current HTTP protocol version is HTTP 1.1 and is described in the IETF RFC 2616. An extension to the HTTP 1.1 protocol is HTTP 1.1 WebDAV. This protocol is described in IETF RFC 4918.
The HTTP 1.1 WebDAV protocol in its simplest form allows a computer to read from and write to web resources on a remote storage device using the WWW. A web resource can be a file. The protocol also supports the equivalent of hierarchical folder listings, file and folder metadata reporting, file and folder deleting and such features that existing traditional file-based file systems (for example, Portable Operating System Interface or POSIX-based file systems) offer, all of it over the WWW. In addition, the protocol also supports file versioning over the WWW. For example, the protocol allows for client programs to connect to remote storage solutions over the WWW and provision data at the remote location as if it were network mounted POSIX file system.
For example, the HTTP protocol supports the OPTIONS request which enables the server to provide a list of WebDAV commands that it supports and how. The WebDAV protocol implements some requests. The implementation of other WebDAV requests is optional. The PROPFIND request is used to retrieve properties and metadata from a resource. It is equivalent to getting properties and metadata about a file and getting a hierarchical directory or folder list. The MKCOL request is used to create collections. For example, a collection can be a directory or folder. The HTTP GET request is used to retrieve a complete or partial resource, for example a file, from a remote location on the WWW. The HTTP PUT request is used to store a complete or partial resource, for example a file, from a remote location on the WWW. The COPY request duplicates a resource, for example a file. For example, a detailed description of HTTP 1.1 WebDAV protocol, and HTTP 1.1 protocol can be found in IETF RFC 2616.
A storage cache or the method of storage caching is defined as a computer program component that transparently stores data on a storage device with relatively faster access or in computer memory so that future requests for the same data from a storage device with relatively slower access may be retrieved from the cache and delivered faster. If requested data is contained in the cache, the request can be fulfilled by simply reading from the cache, which can be relatively fast. Otherwise, the data can be fetched from the storage device containing the data, which can be relatively slower. A cache can be a portion of volatile computer memory (e.g. RAM), or non-volatile computer storage (e.g., solid state disk (SSD), hard disk, storage area network (SAN), or network attached storage system (NAS)).
A WebDAV client is a client program, which is a computer software program that runs on a computer system and using the WebDAV protocol for communication. The WebDAV client communicates with a WebDAV server (i.e., a server using a WebDAV protocol for communication). The WebDAV client implements a software abstraction layer between conventional file input output operations, for example POSIX function calls, implemented by an operating system on a computer system, and a WebDAV server. The WebDAV server is a computer software program that implements one or more versions of the WebDAV protocol.
A conventional implementation of a PROPFIND request may utilize storage caching of information on web resources. In this configuration, when a WebDAV client wants data about a resource, for example a file, hosted on a WebDAV server, the WebDAV client retains PROPFIND responses locally to avoid sending redundant requests to the WebDAV server when asking for data on the same resource again. In some instances, in anticipation of application programs that are running on the computer system that is also running the WebDAV client planning to ask for information on additional web resources, for example, files, a WebDAV client implementation may choose to pre-emptively request for data on those additional web resources and store them to a local cache.
A conventional implementation of an HTTP GET request by a WebDAV server is when an application makes a read request for a specific number of bytes from a specific part of a file that is being served by a WebDAV server. The WebDAV client runs on a computer system. An application program may also be running on the same computer system. The application program issues a read request to read a portion of a file. The file is located on a WebDAV server. As a result, the WebDAV client running on the computer system receives the read request. Instead of sending the read request to the WebDAV server, the WebDAV client first looks for this data in a local cache that the WebDAV client maintains. If the WebDAV client does not find the data in its local cache, the WebDAV client prepares to send a request to the WebDAV server. Instead of making the exact WebDAV GET byte-range request to retrieve only the data that is requested, the WebDAV client requests for more data, for example, the WebDAV client may send a request for the entire file to the server. This act of reading data that is not originally requested is performed in anticipation that the requesting application program and other following application programs may request other parts of the file. For example, if an application program asks for the first 8 Kilobytes from a 1024 Megabyte file, a conventional WebDAV client will send a WebDAV GET request to retrieve the entire 1024 Megabyte file. The WebDAV client would then store the 1024 Megabyte file on a local cache and only deliver the first 8 Kilobytes of this data that were originally requested by the application program. When the WebDAV client receives a subsequent read request for this file from an application program (i.e. the same application program or another application program on the same computer system), the WebDAV client on that computer system reads from the locally cached copy of the file to retrieve the requested data instead of making another WebDAV GET request to the server.
This conventional method of a WebDAV client managing read requests from an application and only issuing a GET request when data is not cached is applicable when a file is of a reasonable size, for example a few megabytes or a few gigabytes. In this case, the WebDAV client bears a one-time expense of downloading the entire file and then subsequent requests do not require further network access to the server. If the file is relatively large, for example, from several gigabytes to a few terabytes, the one-time expense (or investment) can be relatively high, as this may require a relatively large bandwidth and/or a relatively longer period of time to download the large file. A return on investment (ROI) may be even low, if the file is not needed any longer after the initial read. There are several other situations, some of which are discussed in this application where the process of explicit caching by a WebDAV client can be detrimental to system performance.
For example, consider a case where an application program acting as a WebDAV server implements a server program by using some of the methods described in the Provisional Patent Application No. 61/733,228, filed on Dec. 4, 2012, and entitled "METHOD AND SYSTEM FOR STORAGE AND DISSEMINATION OF DATA FILES AND VIRTUAL DERIVED DATA FILES", the entire content of which is hereby incorporated by reference, and that a computer software program acting as a WebDAV client implements the client program using some of the methods described in the 61/733,228 application. For example, as disclosed in the 61/733,228 application, a data file is defined as one or more bytes that exist in computer memory or on a computer storage device, such as a hard disk or a clustered storage device. A data file can be exposed to a computer program via a well-known interface, for example, an Object Storage Solution interface, or a POSIX file-system interface. One or more data files is referred as a collection of data files. The symbol D is used to indicate the one or more data files or collection of data files. A data file that is physically stored on a storage device is referred to as a first data file. A data file that is virtually presented to a consumer as if it were stored on a storage device but is not actually stored on a storage device, and is derived from the first data file, is referred to as a second virtual derived data file. A client program entrusts a server program with a first data file D that is of a known data type TD. The goal for the client is to access the first data file D at a future time. A client program may also have to access additional data of same or different data types that are derived from data file D at a future time. If the server program does not provide for such derived data or provide the ability to create such derived data, the client program ram would have to look for alternative services. If such services are not available, the client program has to generate the derived data by itself. Hence, a method for storing and retrieving data files on a storage device is provided. In one embodiment, the method allows for defining a data file virtualization policy that provides a client program with the ability to send the client program's intent to access the data stored in a first data file, as well as an intent of the client program to access data files of other data types that are derived from the first data file D. A data file virtualization policy is defined as the intent, by a client program, of accessing a first data file D, as well as derived data files D1, D2 . . . DN. One or more derived data files D1, D2 . . . DN are derived from the first data file D, and are virtual. The term virtual implies that one or more data files D1 . . . N do not physically exist on a storage device. The term virtual further implies that a directory listing of data files D1 . . . N is available to the client program. The client program believes that data files exist on the server side storage device. The term virtual further implies that a derived data file DJ (where, 1≦J≦N) is generated by the server program by reading the first data file D wholly or partially, dynamically, on-demand, when a client requests for that specific derived data file. A data file virtualization policy is denoted herein as PD or PD(1 . . . N). A client program sends a first data file D (i.e., one or more first data files D) to a server program accompanied by a virtualization policy PD that corresponds to each first data file D in the one or more data files D. The one or more data files D are of the same data type TD. When a server program receives the one or more first data files and PD, from a client program, the server program takes the one or more first data files and PD and stores it on a storage device. Using either a database or a known structure or protocol, it associates the one or more first data files with virtualization policy PD. For example, a known protocol would be for the server to save the one or more first data files and PD into the same server-side storage generated UUID for each file in the one or more first data files, into PD. In this example, a first data file D would be one of the files in the one or more first data files. A client program sending to a server program, a first data file D and an associated first data file virtualization policy PD(1 . . . N) using a computer network. D can be one data file of data type TD or it can be more than one data files of the same data type TD. A client program does not know what derived data types are supported by a server program for a data file of data type TD. Therefore, a client program may request a server program to send back a list of supported derived data types. The client program may also request a list of supported parameters for each supported derived data type. The parameters allow a client program to control the output of the derived data that will be subsequently generated on-demand by the server program. Once the list of supported parameters is known, a client program can announce its intent to request for all supported derived data types or only a subset of supported derived data types, at a future time.
In this case, the conventional method to implement a WebDAV GET request will not be efficient when one or more WebDAV GET requests are sent by a WebDAV client to the WebDAV server requesting for parts of a Virtual Derived Data File. For example, if multiple application programs running on multiple computer systems simultaneously request for different parts of the same virtual derived data file, each read request is sent to a corresponding WebDAV client running on the same computer system as the application program. If the WebDAV client uses a conventional method of implementing a WebDAV GET request, it can be shown that a WebDAV client program places unnecessary compute load on the WebDAV server program to generate parts of the virtual derived data file not originally requested by the client-side application program making the original read request. In one-time processing methods, such as some analytics algorithms for example object tracking methods, the original application program making the read request does not need more of the virtual derived data file than originally requested. Even if, in this case, the original application needs more virtual data file, it may be nearly impossible to predict what portion of that very large virtual derived data file the application may subsequently need.
Each WebDAV client program sends one or more WebDAV GET requests for a larger byte-range, including, but not limited to, asking for the whole file, from a virtual derived data file. More than one computer system having implementations of the WebDAV server may receive the multiple WebDAV GET requests for large portions of the same virtual derived data file. Each server computer system would then try to generate this virtual derived data file causing the server side computer system or systems to generate more bytes than required. These bytes from the file are retained in the WebDAV client's computer memory, and cached by the WebDAV client on a computer storage device for future use. However, the application program making the original read request to the WebDAV client, may not require that data.
If a client program issues multiple WebDAV GET requests to the server, each request asking for parts of the first data file that will not be accessed again for a period of time, the conventional method of implementing a WebDAV GET request will not be efficient. When the first data file, from which the virtual derived data file is derived, is a large data file, such as several gigabytes (e.g. 100 GB) to many terabytes (e.g. 3 TB), it may be inefficient to transfer a large portion of the file from the server to local storage attached to the computer system running the client program.
Therefore, there are several scenarios where the conventional method of implementing a WebDAV GET request may not efficient. As it can be appreciated, the example provided above is only one of many possible scenarios as there may be other scenarios that can contribute to proving that the conventional method of implementing a WebDAV GET request may not efficient under these other scenarios as well.

Method and system for accessing data by a client from a server


A biangular countersink in a skin panel to be joined to an underlying support member includes a frustoconical base portion defining a large included angle and an extremely shallow outer portion cut at a very small acute included angle. Fasteners usable with the countersink have heads with frustoconical undersides matching the deeper base portion of the countersink and rounded heads sized to fit within the shallow, acutely angled outer portion of the countersink. The combination of fastener and biangular countersink reduces annular grooves or "halos" which typically are formed around conventional flush head fasteners.

Aircraft skin panels typically are joined to underlying stringers or other supports by flush head fasteners, such as rivets. It is desirable that exposed surfaces of the skin panels be smooth for aerodynamic efficiency, for increased adhesion and uniform application of protective films and paints, and for aesthetic purposes. A glossy, smooth painted surface is more pleasing to the eye than a dimpled one.
In a conventional flush head fastener installation system, the holes for receiving rivets have frustoconical countersinks in the skin panel to receive matching fasteners having frustoconical surfaces under the heads. A perfect knife edge at the periphery of the fastener head is not possible; it necessarily is rounded. The rounded periphery of the fastener head, as compared to the frustoconical countersink, results in an annular groove or "halo" surrounding the fastener head.
For example, with reference to FIG. 1, in a known riveting system the included angle .alpha. of the underside of the head portion 10 of a rivet R is 100.degree., and the countersink 12 is cut in the skin panel 14 to match. The shank 16 of the rivet is cylindrical and, prior to formation of the upset 18, has a diameter D less than the corresponding diameter of the drilled hole 20 cut in the stringer or other support member 22 and the lower portion of the skin panel. Drilled hole 20 meets the countersink 12 at a corner 24 which typically is located closer to the abutting surfaces 26 of the outer skin 14 and underlying support 22 than to the exterior surface 28 of the skin. Prior to formation of the upset 18, the rivet can have a dome head, represented by the broken line 30 in FIG. 1, and the shank 16 is of substantially uniform circular cross-section as represented by broken lines 32. When the rivet is crushed by pressure applied by oppositely disposed anvils, the shank 16 of the rivet expands, the domed head 30 is flattened, the upset 18 is formed, and the skin panel 14 is clamped to the support 22. As noted above, since the rivet head cannot be formed with a perfect knife edge, the maximum diameter E of the rivet head is less than the diameter E' of the countersink 12 at the location where it opens at the exterior surface 28 of the skin panel. An annular groove or halo 34 of a depth F and width G is formed around the rivet head.
Dimensions F and G are at least partly functions of permissible tolerances pertaining to the rivet head at the time of manufacture. In the past, one way in which the halo problem has been attacked is to require rivet manufacturers to produce rivets with a rivet head height F of smaller and smaller dimensions. This increases the cost of the rivets, and practical limits have been reached without a completely satisfactory solution to the halo problem.
An alternative geometry disclosed in U.S. Pat. No. 4,000,680 is shown in FIG. 2 and FIG. 3. Skin panel 14 is joined to a stringer or underlying support 22 by the modified rivet R' which, prior to being crushed by the oppositely disposed anvils A, has a substantially cylindrical shank 16 of a diameter D less than the diameter D' of the hole 20 through the support 22 and lower portion of skin panel 14. As for the riveting system of FIG. 1, the rivet head has a frustoconical underside, and the countersink 12 in the skin panel is cut at an identical angle. However, in the geometry of FIG. 2 and FIG. 3, the depth F of the rivet head from the frustoconical underside to the exterior (top) of the head is deliberately formed as a cylinder coaxial with the rivet shank 16. In addition, rather than using a simple domed top, the rivet head is formed with an annular "ring dome" 36 with a depression 38 at the center. The more complicated countersink is formed by a cutter of the type shown in FIG. 4. The cutter has a nose portion 40 of a diameter D' larger than the diameter D of the shank of the rivet with which the cutter is intended to be used. An angled, frustoconical portion 42 of the cutter transitions from the diameter D' of the nose portion to the larger diameter E' of a larger cylindrical portion of the cutter.
Returning to FIG. 2, the diameter E of the rivet head is slightly smaller than the diameter E' of the outer cylindrical portion of the countersink. As seen in FIG. 3, when the rivet is crushed to form the upset 18 by the opposing anvils A, the shank 16 of the rivet expands, and the ring dome is flattened, forcing the rivet head outward to substantially fill the countersink.
The riveting system of FIGS. 2 and 3 has been reasonably effective in eliminating or at least reducing rivet haloes. However, the system is expensive, due to the complicated geometry, tight tolerances, fastener type and license fees. One reason for the tight tolerances is that an additional stress point is added at the junction 44 of the outer cylindrical portion 46 of the countersink and the frustoconical portion 48. As currently used, this junction is located at least 0.014 inch below the exterior surface of the skin panel (for shank diameters of 0.125") and even deeper for rivets of increasing diameter. For example, for rivet diameters nominally 0.312 inch (10/32") the junction 44 is at least 0.033 inch below the exterior surface of the skin panel for systems currently in use.

Fastener system using biangular countersink geometry


The invention provides a magnetic head suspension of an integrated wiring arrangement type which has an increased mechanical property and which may be produced at high yield efficiency. The invention eliminates bowing or warping from stainless steel plate subsequently constituting load beam or flexure, by obviating the step of unwinding or winding stainless steel plate. In a magnetic head suspension according to the invention, a flexure 2, having a thickness less than that of a load beam 1 and a rigidity less than that of the load beam 1, is bonded to one surface of the load beam 1, having a predetermined rigidity, through a bonding layer 14 of a flexible resin. An insulation layer 71 of a flexible resin is formed on the surface of the flexure 2 opposite to the surface facing to the load beam 1. The insulation layer 71 extends from the proximal end portion of the flexure 2 to the distal end portion of the flexure 2. A wiring arrangement 4 is formed on the insulation layer 71. The wiring arrangement 4 is connected to a magnetic head slider disposed at the distal end portion of the flexure 2.

In a magnetic head suspension employed in a conventional hard disk drive (HDD), lead wires are used as a wiring arrangement to be connected to a magnetic head slider. It is noted, however, that, in recent hard disk drives (HDD), densification of recording density and miniaturization of units are quickly proceeded. Accordingly, the magnetic head slider is also miniaturized. By this, miniaturization and lowering load are also required for a magnetic head suspension serving as a plate spring for supporting a magnetic head slider used in HDDs. It is noted, however, that rigidity of lead wires disposed on the suspension becomes not negligible in accordance with reduction in load of such magnetic head suspension. Such rigidity may influence on the floating property of the magnetic head slider.
Under the circumstances, a suspension of an integrated wiring arrangement type is developed, in which a metal layer integrally formed with the suspension, rather than lead wires, is used as a wiring arrangement to be connected to the magnetic head slider.
FIG. 13 illustrates such suspension of an integrated wiring arrangement type. The suspension includes a load beam 1 and a flexure 2. A wiring arrangement 4 to be connected to a magnetic head slider (not shown) is integrally formed with the flexure 2. Specifically, the magnetic head suspension includes a load beam 1 of stainless steel having a thickness of 60-70 micrometers a flexure 2 of stainless steel having a thickness of 20-30 micrometers, and a base plate 3 of stainless steel having a thickness of 300 micrometers. The flexure 2 is spot-welded at a plurality of welds W to the load beam 1. The base plate 3 is also connected to the load beam 1 by welding. As shown in FIGS. 13 to 15(a), (b), (c), a polyimide layer 7 is formed on the upper surface of the flexure 2, i. e., on the surface of the flexure 2 opposite to the surface facing the load beam 1. Within the polyimide 7, wiring arrangement 4 of Cu (copper) having a thickness of about 5-10 micrometers, and pads 5 and 6 are formed. The magnetic head slider is attached to the flexure 2 at its distal region 9, and the terminal of the magnetic head slider is electrically connected to the pad 5.
FIG. 14 is a perspective view illustrating the suspension shown in FIG. 13 which has been disassembled into three parts, i. e., the load beam 1, the flexure 2 and the base plate 3. The magnetic head slider is adhesively attached to the region 9 to which it is to be attached. A load is applied to the magnetic head slider in the direction toward a disk, i.e.,in the vertical direction. Thus, the distal region of the load beam 1 adjacent to the base plate 3 is narrowed in a region of load bending 10 so as to have a predetermined resiliency, and is also bent into a predetermined configuration.
The sections respectively along line A--A, B--B and C--C in FIG. 13 are respectively shown in FIGS. 15(a), 15(b) and 15(c). As shown in these drawings, the polyimide layer 7 consists of an insulation layer 71 of polyimide having a thickness of 5-10 micrometers for providing electrical insulation between the wiring arrangement 4 and the flexure 2, and a protective layer 72 of polyimide having a thickness of 3-10 micrometers for covering the wiring arrangement 4 for protection thereof. It is noted that, as shown in FIG. 15(c), the protective layer of polyimide 72 has openings P disposed over the pads 6. Thus, the surface made of Cu of each of the pads 6 is exposed through a respective opening P. The protective layer 72 of polyimide disposed on the pad 5 has the same construction, although not specifically shown. The Cu surface of each of the pads 5 and 6 is often provided with Ni/Au plating, although not specifically shown.
A method for producing a magnetic head suspension according to prior art will be explained below.
FIGS. 16(a) to 16(e) are sectional views sequentially showing such production method. As shown in FIG. 16(a), an insulation film 171 of polyimide having a thickness of 5-10 micrometers and a Cu (copper) film 104 having a thickness of 5-10 micrometers are sequentially laminated on a stainless steel plate 102 having a thickness of 20-30 micrometers, subsequently constituting the flexure, in its entire surface. Then, a resist 11 is formed on the Cu film 104 in its wiring forming region. Thereafter, and as shown in FIG. 16(b), the Cu film 104 is etched away using the resist 11 as a mask, so as to form Cu wiring arrangement 4. Then, the resist 11 Is etched away , for example, by means of an organic solvent. Thereafter, and as shown in FIG. 16(c), a resist 12 is formed on the insulation film 171 of polyimide including the area where the Cu wiring arrangement 4 is formed. Then, the insulation film 171 of polyimide is etched away by means of hydrazine, for example, using the resist 12 as a mask.
The resist 12 is removed using an organic solvent, for example. Thereafter, and as shown in FIG. 16(d), photosensitive polyimide is applied on the entire surface. Then, exposure and development are performed so as to form the protective layer 72 of polyimide for covering the wiring 4. It is also possible to form the protective layer 72 of polyimide using non-photosensitive polyimide. It is noted, however, that, in such a case, a series of additional steps is required, such as application of non-photosensitive polyimide on the entire surface, formation of mask on the polyimide layer by means of resist, etching of the polyimide layer, and removal of the resist. Such series of additional steps may be obviated when the above-mentioned photosensitive polyimide is used, so that the process is simplified.
When the protective layer 72 of polyimide has been formed, a resist pattern 13 is formed on the opposite surfaces of the stainless steel plate 102 (subsequently constituting the flexure 2), as shown in FIG. 16(e). The stainless steel plate 102 is etched away using the above resist patterns 13, 13 as a mask, so as to form the flexure 2. Subsequently, the lower resist pattern 13 is removed using an organic solvent, for example. Thereafter, the flexure 2 is welded to the load beam 1. Then, the base plate 3 is welded to the load beam 1. The load beam 1 is further bent into a predetermined configuration, so that the magnetic head suspension shown in FIG. 15(a) is obtained.
In the conventional magnetic head suspension just mentioned above, the flexure 2 is attached to the load beam 1 by means of welding. Thus, strain due to the welding operation is introduced into the load beam 1 and the flexure 2. Accordingly, mechanical property (specifically, variation in the attitude angle of the flexure 2 at the region 9 where the magnetic head slider is attached thereto, and rigidity) of the load beam 1 and the flexure 2 is degraded, whereby reliability is reduced.
In the conventional method for producing a magnetic head suspension, the polyimide layer 7 and the Cu wiring 4 are formed on the stainless steel plate 102 which has been thinned to have a thickness of 20-30 micrometers in order to increase floating property of the magnetic head slider. Thus, the stainless steel plate 102 is easily deformed during the step of forming the polyimide layer 7 and the Cu wiring 4, whereby production yield is decreased.
According to prior art, and in order to stably perform various processes, such as photolithography, etching or the like relative to the thin stainless steel plate 102, the stainless steel plate is wound around a roll. The stainless steel plate is continuously unwound from the roll onto an equipment of each of the above-mentioned processes. The stainless steel plate output from each equipment is again wound around a roll each time after each process has been completed. In this connection, it is to be noted that, when the stainless steel plate 102 is wound around a roll, bowing or warping may be remained in the flexure 2 which has been formed by etching away the stainless steel 102. Thus, mechanical property of the flexure 2 is decreased (specifically, variation in the attitude angle of the flexure is increased), so that production yield is disadvantageously decreased.
It is further noted that each step or process requires a roll equipment in order to perform the unwinding and winding operations of the stainless steel plates this essentially requires a large production line. Equipment for transferring the stainless steel plate in rolled form is required between each process, so that the length of production line is also increased.

Magnetic head suspension comprising a flexure bonded to a load beam via a flexible resin


Whether to enable a packet discarding mode is designated and, if an information processing apparatus operates in a power saving mode and the packet discarding mode is enabled, the information processing apparatus determines processing for a received packet based on a proxy response pattern, a WOL pattern, and a discard pattern, and, if the information processing apparatus operates in the power saving mode and the packet discarding mode is disabled, the information processing apparatus determines processing for the received packet based on the proxy response pattern and the WOL pattern without using the discard pattern.

Field of the Invention
The present invention relates to an information processing apparatus, a control method of the information processing apparatus, and a storage medium.
Description of the Related Art
In recent years, there are growing demands for reducing power consumption of information processing apparatuses such as printers and digital multi functional peripherals (MFPs). In order to meet such demands, for example, there is developed a known technique that shifts an information processing apparatus from a normal power mode to a power saving mode if the apparatus does not operate for a predetermined period of time. In the normal power mode, power is supplied to both of a main control unit and a communication unit of the information processing apparatus. When the mode is changed to the power saving mode, however, although power is continuously supplied to the communication unit of the information processing apparatus, power to the main control unit of the information processing apparatus is blocked. Thus, the power consumption of the information processing apparatus in the power saving mode is reduced as a whole compared to when the apparatus is in the normal power mode. Japanese Patent Application Laid-Open No. 2006-259906 discusses a technique in which, if the information processing apparatus is in the normal power mode, the main control unit responds to a received packet sent from an external apparatus whereas, if the information processing apparatus is in the power saving mode, the communication unit responds to the received packet in place of the main control unit.
According to the above-described technique, the communication unit determines whether the received packet matches a response pattern stored in advance in the information processing apparatus. If the communication unit determines that the received packet matches the response pattern, the communication unit responds to the received packet. As the response pattern, for example, a status request, which is used for polling and output by an external apparatus to the information processing apparatus at regular intervals, is set in advance in the information processing apparatus. If such a status request used for polling is set in advance as the response pattern, since the communication unit responds to the status request in place of the main control unit, the information processing apparatus can maintain the power saving mode and the power consumption of the information processing apparatus as a whole can be reduced.
If the type of the external apparatus is changed or if a version of an application which operates on the external apparatus is upgraded, the type of the status request used for polling by the external apparatus at regular intervals may be added. In such a case, according to the above-described technique, the communication unit can respond only to the status request set in advance and not to the newly-added status request. Thus, on receiving the newly-added status request, the mode of the information processing apparatus is shifted from the power saving mode to the normal power mode. Accordingly, there is an issue that the benefit from the power saving mode (reducing power consumption) cannot be fully obtained.
This issue can be solved by adding the newly-added status request to the response pattern. However, in adding a new pattern to the response pattern, it is necessary to change the hardware of the communication unit. Changing the hardware of the communication unit leads to increase in cost. Further, since it is impractical to change all the hardware of the information processing apparatuses on the market, it is not desirable to add the newly-added status request to the response pattern.

Information processing apparatus selectively enabling or disabling packets discarding feature by its network interface card


A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

Flip chip packages include a semiconductor die mounted onto a package substrate with the active side of the die facing the substrate. Conventionally, interconnection of the circuitry in the die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding (complementary) array of interconnect pads (often referred to as "capture pads") on the substrate.
The areal density of electronic features on integrated circuits has increased enormously, and chips having a greater density of circuit features also may have a greater density of sites for interconnection with a package substrate.
The package is connected to underlying circuitry, such as a printed circuit board (e.g., a "motherboard") in the device in which it is employed, by way of second level interconnects (e.g., pins, solder balls) between the package and the underlying circuit. The second level interconnects have a greater pitch than the flip chip interconnects, and so the routing on the substrate conventionally "fans out". Significant technological advances have enabled construction of fine lines and spaces; but in the conventional arrangement space between adjacent pads limits the number of traces than can escape from the more inward capture pads in the array, and the fan out routing between the capture pads beneath the die and the external pins of the package is conventionally formed on multiple metal layers within the package substrate. For a complex interconnect array, substrates having multiple layers may be required to achieve routing between the die pads and the second level interconnects on the package.
Multiple layer substrates are expensive, and in conventional flip chip constructs the substrate alone typically accounts for more than half the package cost (about 60% in some typical instances). The high cost of multilayer substrates has been a factor in limiting proliferation of flip chip technology in mainstream products.
In conventional flip chip constructs the escape routing pattern typically introduces additional electrical parasitics, because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.
In some conventional processes, flip chip interconnection is made by contacting the bumps or balls on the die with corresponding interconnect sites on the substrate circuitry, and then heating to reflow the fusible portion of the solder bumps (or to reflow the solder bumps in their entirety) to make the electrical connection. In such processes the melted solder may flow from the interconnect site along the metal of the circuitry, depleting the solder at the connection site; and where the bumps are collapsible under reflow conditions the bumps may contact adjacent circuitry or nearby bumps, resulting in electrical failure. To avoid these problems, typically in conventional flip chip packages the solder is confined by a "solder mask", consisting of a layer of dielectric material overlying the patterned metal layer at the die mount surface of the substrate, and having openings each exposing an interconnect site on the underlying circuitry. Process limitations in patterning the solder mask prevent reliably forming well-aligned and consistently dimensioned openings and, accordingly, where a solder mask is employed, substrates having fine circuitry feature dimensions as would be required for finer pitch interconnection are not attainable.
The interconnect pitch in conventional flip chip interconnects is limited in part by the dimensions of the capture pads on the substrate (typically the capture pads are much wider than the circuit elements connecting them). Recently flip chip substrate circuitry design has been disclosed, in which reliable interconnection is made on narrow circuit elements on the substrate, as for example in "bond-on-narrow pad interconnections" (BONP), as described generally in co-pending U.S. application Ser. No. 11/388,755, filed Mar. 26, 2006; and as for example in "bump-on-lead interconnections" (BOL), as described generally in co-pending U.S. application Ser. No. 110/985,654, filed Nov. 10, 2004, both incorporated herein by reference. Where a conventional solder mask is to be employed, limitations in the process for patterning the solder mask can limit pitch reduction even in some BONP or BOL substrate configurations. The exposed bondable surface of the lead may be contaminated by or covered by solder mask residue, resulting in an imperfect solder joint; or, the bondable surface of the lead may be inconsistently or only partially exposed at the interconnect site, resulting in an unreliable and inconsistent trace structure.

This patent is subject to a terminal disclaimer.


The invention relates to a tenderizing machine which is designed to tenderize deboned meat pieces. The inventive machine is equipped with two stacked tenderizing assemblies, each of the assemblies comprising an integrated pair of rotating rollers which are provided with cutting members that extend out from the periphery thereof and which are disposed close to one another, such as to define an adjustable-size opening. In addition, at least one of the rollers of each assembly is supported such that it can move away from the other roller against an opposer as the meat pieces move between said two rollers. Moreover, each of the tenderizing assemblies is equipped with respective controls for adjusting the distance between the cutting members of each pair of rollers and for selectively blocking the movement of at least one of the moving rollers of each of the assemblies.

The state of the art describes various meat mass tenderising machines applied to the explained function.
In particular, a machine is known that consists of a pair of parallel, tenderising rollers, located at a short distance and rotated in opposite directions by a motor with the said rollers fitted with a number of cutting members, such as prongs or blades emerging from their surfaces, defining an elongated aperture through which the pressed meat passes, driven by the said rollers and gravity. It has been arranged in this machine that one of the rollers is associated, by its support ends to some means of elastic load, with limited travel, so that it can move or give way, moving away from the other twin roller, mounted in a fixed manner on a bed of the machine, during the passage of the pieces of meat.
The invention proposes to improve the performance of such a machine, permitting a more efficient job on the meat mass to be treated and especially providing great variability of the operating conditions to achieve improved adaptation of the actual characteristics of each batch of meat product to be treated.


A process for controlling the concurrent production of both diesel range hydrocarbons and aviation range hydrocarbons from renewable feedstocks such as plant oils and animal oils. The process involves determining the required specification of the desired products and the desired relative yields of the product that still meet the required specifications. The necessary isomerization and selective hydrocracking zone conditions are determined in order to create a mixture of paraffins which meet the required product specifications and yields. The necessary fractionation zone conditions are determined to separate the desired products. A renewable feedstock is treated by hydrogenating and deoxygenating to provide an effluent comprising paraffins, isomerizing and selectively hydrogenating at least a portion of the paraffins at the predetermined conditions, and separating by fractionation at the predetermined fractionation conditions to generate a diesel range hydrocarbon product and an aviation range hydrocarbon product.

This invention relates to a process for controlling the production of hydrocarbons useful as transportation fuels including diesel fuel and aviation fuel from renewable feedstocks such as the glycerides and free fatty acids found in materials such as plant oils, fish oils, animal fats, and greases. The process involves hydrogenation, decarboxylation, decarbonylation, and/or hydrodeoxygenation and optionally hydroisomerization, cracking, or selective cracking, in one or more steps. Desired product specifications and yields are determined and reaction and fractionation conditions are set to achieve the specifications and yields.
As the demand for transportation fuel increases worldwide there is increasing interest in sources other than petroleum crude oil for producing diesel and aviation fuel. One such source is what has been termed renewable feedstocks. These renewable feedstocks include examples such as plant oils such as corn, rapeseed canola, soybean and algal oils, animal fats and oils such as tallow, fish oils and various waste streams such as yellow and brown greases and sewage sludge. The common feature of these feedstocks is that they are composed of glycerides and Free Fatty Acids (FFA). Another class of compounds appropriate for these processes fatty acid alkyl esters (FAAE), such as fatty acid methyl ester (FAME). These types of compounds contain aliphatic carbon chains generally having from about 8 to about 24 carbon atoms. The aliphatic carbon chains in the glycerides, FFAs, or FAAEs can be saturated or mono-, di- or poly-unsaturated. Most of the glycerides in the renewable feed stocks will be triglycerides, but some of the glycerides in the renewable feedstock may be monoglycerides or diglycerides. The monoglycerides and diglycerides can be processed along with the triglycerides.
There are reports in the art disclosing the production of hydrocarbons from plant oils. For example, U.S. Pat. No. 4,300,009 discloses the use of crystalline aluminosilicate zeolites to convert plant oils such as corn oil to hydrocarbons such as gasoline and chemicals such as para-xylene. U.S. Pat. No. 4,992,605 discloses the production of hydrocarbon products in the diesel boiling range by hydroprocessing vegetable oils such as canola or sunflower oil. Finally, US 2004/0230085 A1 discloses a process for treating a hydrocarbon component of biological origin by hydrodeoxygenation followed by isomerization.
The process herein comprises an optional pretreatment step, and one or more steps to hydrogenate, deoxygenate, hydroisomerize and optionally selectively hydrocrack the renewable feedstock, to generate both a diesel fuel component and an aviation fuel component. The specifications and relative yields of the diesel component and the aviation component are determined and the operating conditions of the isomerization and selective hydrocracking zone are determined in order to meet the specifications and yields of the products. The fractionation zone conditions are determined in order to separate the desired products at the desired yields. The diesel component and the aviation component may be suitable as fuels, used as components of blending pools, or may have one or more additives incorporated before being used as fuels.

Controlling production of transportation fuels from renewable feedstocks


The present disclosure discloses a digital television, an electronic device, and control methods thereof. The digital television includes an expansion interface, a controller and a voltage converter. The controller is connected to the expansion interface, and is connected to an external electronic device through the expansion interface. The expansion interface is connected to the voltage converter, and the controller is configured to control the voltage converter to supply power to the external electronic device through the expansion interface. The controller is further configured to control the external electronic device to be turned on or turned off and communicate with the external electronic device through the expansion interface.

Currently, most digital televisions are disposed separately from set-top boxes, and the televisions and the set-top boxes are provided with power interfaces respectively. When a television is turned on, it is necessary to turn on a set-top box at the same time for watching the television. When the television is turned off, the set-top box also needs to be turned off, which results in tedious user operations. If the set-top box is turned on for a long time, it causes a waste of unnecessary energy.

Digital television, electronic device and control methods thereof


A method and device for detecting data of a data storing unit includes an analog/digital converter for outputting a symbol signal r.sub.k by sampling an analog signal r(t) with a sampling clock, an equalizer for outputting z.sub.k by equalizing the output r.sub.k of the analog/digital converter, a data detector for detecting symbol data a.sub.k from the equalized output z.sub.k, and a clock recovering portion for correcting frequency and phase of the sampling clock, the clock recovering portion performing the correction at an edge of a symbol data a.sub.k. Therefore, it is possible to reduce errors in detecting data and to effectively detect the data with a far better performance that conventional technology and to restore a sampling clock by limiting a sampling clock recovering process to operate only at the edge of the symbol data.

The present invention relates to a method for detecting data recorded from a signal reproduced in a data storing unit and a device therefor, and more particularly, to a method for detecting data for recovering clock by limiting a sampling clock recovering process to operate only at an edge of a signal waveform in order to effectively detect the reproduced signal in case the recorded data is coded to a run length limited code whose runlength constraints are not less than one, and a device therefore
Research and development for effectively using massive information in the modern information conscious society has been rapidly advancing. As a result, remarkable developments have been achieved in various fields. Also, as societal demand to use information increases, delievering large quantities of information and reducing time for processing information, and increaing quantity of data recorded in a storing unit of a given capacity (recording density) become the biggest object in the storing field unit. There are methods for improving physical characteristics of a storage disk or precision degree of the data storing unit and for reducing data detecting errors using a signal processing technique, which can be regarded as efforts to maximize a speed and a capacity of such a data storing unit.
The data recorded in such a storing unit is the data encoded to the RLL code. This is an encoding method for preventing data symbols to be recorded from being continuously connected, in order to control timing of data sampling clock and to detect a signal. Namely, this is a runlength (d, k) code which limits the number of "0s" which continue between "1" and "l" into d in the minimum and k in the maximum. The former is for facilitating the signal detection and the latter is for timing of the data in recovering the reproduced signal. Since the characteristics of the reproduced signal are different according to the position on the disk, it is necessary to appropriately change a signal detecting method or an equalizer according to the characteristics of the signal for precise signal detection. Also, frequency and phase of the clock should be continuously adjusted so that the sampling is performed in an accurate position of a pulse during a procedure of sampling an analog signal to a symbol signal.
While, in case of an optical magnetic disk storing unit, it is possible to record the data in high density when the data is coded to the RLL code whose minimum runlength d is not less than one, considering the characteristics of a laser and a disk medium for recording the data. In a magnetic storing unit such as a hard disk driver, since it is hard to detect the data due to a nonlinear characteristic of the signal as the recording density increases, the data may be coded to the RLL code whose runlength d is not less than one in order to reduce the nonlinearity of the signal.
Generally, a channel should be modeled similarly to a real channel during recording and reproducing with respect to a storing unit. Such a channel characteristic of the unit can be expressed as (1+D).sup.n or (1-D)(1+D).sup.n, (here, n=1, 2, . . . ), according to a recording density in order to reflect the channel characteristic of the storing unit. Here, D denotes a time delay. Since interference between the recorded signals increases as the recording is performed in high density in the storing unit, the channel should be modeled with a larger n value to be expressed nearer to the real channel characteristic.
There are a decision feedback equalizer (DFE) method and a partial response maximum likelihood (PRML) method, etc, in recent data detecting methods. Among them, the DFE method is the method for changing an input signal to have only the present data value by equalizing it to a target response satisfying d.sub.k =a.sub.k and for detecting data with a normal threshold value detector. In the DFE method, it is easy to detect the data since the data is detected with the threshold detector and to control the sampling clock since the data is detected to every clock. However, in case signal interference is high, detecting performance is deteriorated since noise of a high frequency is amplified in the process of equalizing the input signal to meet d.sub.k =a.sub.k. Meanwhile, in the PRML method, the data is detected with a Viterbi decoder by changing the input signal into a target response satisfying d.sub.k =a.sub.k +a.sub.k-1 or d.sub.k =a.sub.k -a.sub.k-2 after generating inter-symbol interference (ISI) controlled between the present data and the previous data by preceding the input signal. In the recording density which has the signal interference in which the channel characteristic approximately meets n=1, it is possible to excellently detecting the data using the PRML method, however, it is hard to control the sampling clock since the data is not detected every clock.
To restore the data recorded on the storing unit, the bit clock should be restored from a reproduce signal. Such a restoration of the bit clock is for generating the clock synchronized with the bit clock and sampling it and for continuously obtaining a sample of a desired accurate value by tracking the change of the bit clock frequency of the reproduced signal. In general bit clock recovering methods, there are a method for directly extracting the bit clock by passing the reproduced signal over a narrow-band band pass filter and sampling the reproduced signal using the bit clock and a method for obtaining a sampling phase error from the sampling value obtained by sampling the reproduced signal and gradually adjusting the frequency of the sampling clock by removing the sampling phase error.
The latter method is widely used in processing the reproduced signal of the storing unit. In the latter method, the phase error of the sampling clock is detected, the sampling error is adjusted again according to the error, and a series of sampling clock recovering processes are performed to all the data patterns. Recovering the clock by sampling it every time in such a method is inefficient since, when continuous data rows of the same value are repeated, continuous sampling clock restorations are performed in the data which does not have timing information.

Method for detecting data and device therefor of data storing unit


A method and device for accessing a broad data field having a fine resolution. The user selects a scale which can be varied. The scale controls a range within the data field. By moving the range to encompass different portions of the data field, the user can scan that portion of the data field. The present invention allows the user to simultaneously select the scale while moving the range over different portions of the data field. Thus, the user can “zoom in” and “zoom out” of different portions of the data field.

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by any one of the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
Many types of data have a broad range and a fine resolution. For example, a videodisk is composed of a continuum of frames. The video disk can store up to a series of tens of thousands of frames. Thus, it has approximately five orders of magnitude. Likewise, electronic music composition requires controlling frequencies over the entire audible scale ranging from 15 to 20,000 hertz. Thus, three orders of magnitude are required to cover this range. Similarly, a five second digital audio clip may require five orders of magnitude to access each bit sample. These types of data are often linear in the sense that there are starting and ending points and many linked "frames" of data between the starting and ending points.
In order to access a videodisk, one needs frame accurate control over the entire medium. In other words, a user must be able to readily pick out one particular desired frame nestled among tens of thousands of frames. It becomes readily apparent that tasks such as adjusting key frames in an video film or manipulating audio samples, can be quite time consuming and frustrating. What is needed is a method or apparatus which lets the user find and access one particular desired piece of data which is located among a broad range of data.
In the past, this was accomplished by using scroll bars. However, scroll bars typically can handle only two orders of magnitude. Consequently, a scroll bar would need to be approximately twenty yards long in order to grant access to each frame of a video disk. This is impracticable.
Another method used in the prior art was to implement VCR-type controls. This allows the user control over the entire range of data. However, these types of controls lack selectivity. For example, it would be difficult for a user to stop precisely on one particular desired frame of a VCR tape. The user would probably either overshoot or undershoot the desired frame and would probably go back and forth searching for that particular frame. What is needed is a method that gives the user control over a broad range, while giving the user random access to any particular piece of data within that range, especially at fine resolutions.
Yet another method used in the prior art to solve this problem is to provide one control for magnification of the data and another control for scanning at the selected magnification. One product utilizing this technique is SoundEdit™ by Farallon Computing, Inc. However, this implementation has a drawback in that it requires two separate controls. A further disadvantage is that these two controls cannot be operated simultaneously. A user has to change the magnification control independently from the navigation control. Such a system results in wasted time and effort. Thus, what is needed is a method for providing the user with easy and fluid interaction over varying magnification scales while simultaneously providing the user with the capability of scanning at that magnification scale.

Abstract: In one embodiment of the present invention, a particular piece of data within the broad data field can be accessed. First, the scale is selectively varied, thereby controlling a range within the data field. Then, the range is moved to encompass portions of the data field in which the piece of data resides. Next, the scale is successively decreased while, simultaneously, points successively closer to the location are kept with the range. The scale is decreased (i.e., increasing the range's resolution) and the range is moved in this manner until the piece of data is actually accessed.


A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

In a parallel computation, data are distributed and arranged in plural processors, and a process of aggregating and exchanging the values of the computation results of the respective processors is repeated. Here, in a case where the sum of aggregated values is used in the next process, when the values are summed up during the aggregation, the amount of communication between the processors can be reduced. This parallel process is called a reduction operation. The reduction operation is particularly important in a distributed memory type parallel computer because of the high cost of data transfer between processors.
Related techniques are disclosed in, for example, Japanese Laid-open Patent Publication No. 2017-021618, Japanese National Publication of International Patent Application No. 2016-534433, and Japanese Laid-open Patent Publication Nos. 2012-058958, 2012-128808, and 2012-128809.
Related techniques are disclosed in, for example, "The Case of the Missing Supercomputer Performance: Achieving Optimal Performance on the 8,192 Processors of ASCI Q," Fabrizio Petrini et al., the ACM/IEEE Conference on Supercomputing (SC03), 2003 (Non-Patent Document 1), "Unfolding the IBM E-server Blue Gene Solution," IBM Redbooks, pp. 27-29, 2005 (Non-Patent Document 2), and "The Tofu Interconnect 2," Yuichiro Ajima et al., IEEE 22ndAnnual Symposium on High Performance Interconnects (HOTI), 2014 (Non-Patent Document 3).

Processor and information processing apparatus


The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically 'refreshed'. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Accordingly, SRAMs are a desirable type of memory for certain types of applications including portable devices such as laptop computers and personal digital assistants (PDAs).
SRAM is typically arranged as a matrix of thousands of individual memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or "latch" a bit of information. These SRAM memory cells are often arranged in rows and columns so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations.
The basic CMOS SRAM cell generally includes two n-type or n-channel (nMOS) pull-down or drive transistors and two p-type (pMOS) pull-up or load transistors in a cross-coupled inverter configuration, which act as a bistable latch circuit, with two additional nMOS select or pass-gate transistors added to make up a six-transistor cell (a 6T cell). Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation.
Each inverter of the SRAM memory cell includes a load transistor and a driver transistor. The output of the two inverters provide opposite states of the latch, except during transitions form one state to another. The pass-gate transistors provide access to the cross-coupled inverters during a read operation (READ) or write operation (WRITE). The gate inputs of the pass transistors are typically connected in common to a word line (wordline or WL). The drain of one pass transistor is connected to a bit line (bitline or BL), while the drain of the other pass transistor is connected to the logical complement of the bit line (bitline-bar or BLB).
A WRITE to a 6T cell is effected by asserting a desired value on the BL and a complement of that value on BLB, and asserting the WL. Thus, the prior state of the cross-coupled inverters is overwritten with a current value. A READ is effected by initially precharging both bitlines to a logical high state and then asserting the WL. In this case, the output of one of the inverters in the SRAM cell will pull one bitline lower than its precharged value. A sense amplifier detects the differential voltage on the bitlines to produce a logical "one" or "zero," depending on the internally stored state of the SRAM cell.
Accordingly, a consideration in the design of the transistors in the SRAM cell is the geometric parameters of the transistors. The gate length and width determine in large part the speed and saturation drive current, IDsat, also known as the maximum drive current capacity of the transistors. Appropriate values of gate length and width of the six transistors of the 6T cell must be chosen to ensure that a read operation does not destroy the previously stored datum. Inappropriate transistor parameter values in conjunction with the BL and WL voltages applied during a READ may result in a change in state of the memory cell due to random asymmetries resulting from imperfections in the manufacturing process. The necessity to guard against such READ instability places an undesirable constraint on the design parameters of the transistors in the 6T cell, limiting the ability of the designer to increase READ performance of the SRAM while keeping within area and power constraints and maintaining the ability to write into the cell.
As transistor scaling trends continue, however, it becomes increasingly difficult to design an SRAM cell that has both adequate static noise margin (SNM) and adequate trip voltage (Vtrip), because of their interdependency in cell design. For example, a design constraint of a 6T SRAM cell is that the pass gate is generally designed to be relatively weaker than the inverter driver transistor to ensure stability and adequate SNM, yet is also designed to be stronger than the inverter load transistor to enable a WRITE by providing adequate Vtrip. Also, for stability, the inverter load transistor cannot be too weak relative to the inverter driver transistor or SNM is degraded. Inverter transistors with relatively low threshold voltage (Vt), the voltage at which the transistor begins to conduct, may also degrade stability of the SRAM cell. With technology scaling to the 45 nm node and beyond, it may no longer be possible to achieve this balance in the relative strengths of the pass gate, drive, and load transistors over the desired range of temperature and bias conditions as well as process variations. Thus, the current balance in these design values often involves a trade-off that may translate to a higher incidence of data upsets and/or slower access times.
Prior art includes methods to assist the WRITE to allow the relatively weaker pass gate for good stability. This prior art includes pulling the BL below the SRAM low voltage supply, VSS, for WRITE, or providing a lower SRAM high voltage supply, VDD, to the inverters for WRITE relative to that for READ. However, the relatively weaker pass gate enabled by this prior art has the undesirable affect of degrading the read current.
Prior art also includes memory cells with separate ports for READ and WRITE that might at first seem to relax some of the constraints to allow a fast READ. However, such cells are generally relatively large. Also there is still the constraint of not upsetting the unaddressed cells in a selected row for WRITE in an array in which only a subset of the cells in a selected row are written into in a single WRITE cycle. The cells in the selected row that are not written into are subjected to bias conditions similar to that for a READ, and are subject to upset.
Accordingly, there is a need for an improved SRAM cell design that enables independent optimization of the static noise margin, trip voltage, and read current of higher speed SRAM cells, while minimizing data upsets in SRAM memory devices with a relatively compact layout.

8T SRAM cell with higher voltage on the read WL


A washing machine includes a tub for containing washing water, a drum rotatably disposed in the tub, a chamber communicating with the tub through a plurality of openings in which washing water is introduced from the tub through at least one of the plurality of openings and the introduced washing water is discharged to the tub through at least one of the remaining openings, and a water quality detector for detecting the quality of washing water in the chamber.

1. Field of the Invention
The present invention relates to a washing machine.
2. Description of the Related Art
Generally, a washing machine is an apparatus for removing pollutants from laundry, such as clothing, by the emulsification of water and detergent. The washing machine includes a tub for containing washing water and a drum rotatably disposed in the tub to contain laundry. Such washing machines may be classified into a front-loading type, in which a drum, into which clothes are introduced from front, rotates about the horizontal axis, and a top-loading type, in which a drum, into which clothes are introduced from above, rotates about the vertical axis.
The washing machine is provided with a turbidity sensor for detecting the turbidity of washing water introduced into the tub. Water streams are created in the tub due to the rotation of the drum. Since a conventional washing machine includes a turbidity sensor positioned at the bottom of the tub, variation in the value measured by the turbidity sensor is caused by sloshing of washing water, and measurement accuracy is further deteriorated owing to various causes, such as bubbling caused by detergent, turbulence caused by extraneous substances in washing water, and the like.


Method of searching for availability of an entity for purchase or reservation. The method comprises the steps of searching for an entity matching a search criteria to obtain a list of entities, wherein the or each entity comprises a parameter having a predetermined availability; automatically searching for one or more available parameters associated with the or each entity; generating a list of each entity and one or more available parameters associated therewith to generate a list of entity and available parameters; displaying the list of entity and available parameters of the or each entity for selection by a user of an appropriate combination of entity and parameter; filtering the list of entity and available parameters in order to remove one or more combination of entity and parameter; and displaying a modified list of entity and available parameter.

There are many kinds of booking system in the travel industry or in the entertainment industry, which allow a user to find a specific seat or room by means of a searching system. For instance, in the travel industry, if the user wants to book a room in a hotel through a website, the process is as follows. At first, the user has to enter one or more criteria in the required location on a website in order to launch a first request to a server to obtain a list of hotels matching the criteria. Thus the booking system displays an exhaustive list of all the matching hotels that match the criteria. If the user wants to add new criteria or to modify criteria in the request, the user has to build a successive request or requests to be sent to the server. However, processing successive requests brings many drawbacks such as degraded server performance and long response time for users.

Method and system for improving a reservation or a purchase process of an entity


A method of automatically activating a camera application implemented in a mobile device in locked mode starts with the processor receiving a first signal from an accelerometer. The device's processor activates the camera application when the processor determines that the mobile device has remained in a stationary portrait or landscape position for a period of time based on the first signal. Activating the camera application includes signaling by the processor to the display device to display a camera screen from a locked screen. The processor may also receive a second signal from a proximity sensor that detects presence of a nearby object to the mobile device. When the processor determines that there is presence of the nearby object to the mobile device based on the second signal, the mobile device remains in locked mode and the processor does not activate the camera application.

Currently, a wide range of portable consumer electronics that are not dedicated to photographic uses are equipped with cameras. These portable consumer electronics devices (or "mobile devices") may include, for example, smart phones, laptops, notebooks, tablet computers, and personal digital media players.
Since these mobile devices often include a user's sensitive personal information (e.g., emails, contact information) or installed applications that provide quick access to the user's private data (e.g., bank accounts applications), a user often locks these devices using a password or his biometrics. While this locking capability protects the user from identity theft, having to take the time to enter a password or biometrics to unlock the device may not be desirable when the user requires quick access to an application. For instance, if the mobile device is locked when the user wishes to capture a fleeting moment on camera, the user may miss the opportunity to do so since he has to take the time to enter his password or biometrics to unlock the device as well as locate and activate the camera application.

Apparatus and method for automatically activating a camera application based on detecting an intent to capture a photograph or a video


The present invention teaches a method and system for disconnecting shorted decoupling capacitors, wherein a semiconductor chip having a plurality of redundant decoupling capacitors. Each of the capacitors is coupled, by means of a link, to a bus having a predetermined voltage. Each link is accessible to light emissions, in planar view. The system comprises a tester for testing the operability of each of the capacitors. In a preferred embodiment, the tester comprises a heating element and a high voltage stress testing element. Under thermal and voltage stress, an infrared signal identifying shorted decoupling capacitors is generated by shorted decoupling capacitors. The system further comprises a sensor for sensing the infrared signal. In one embodiment of the present invention, the sensor comprises an emission microscope for multilevel inspection ("EMMI"). Each inoperable capacitor is decoupled from the bus by disintegrating the link with a laser in response to the infrared signal. In an alternate embodiment, the link is disintegrated by an acid etch comprising H.sub.2 SO.sub.4, H.sub.2 SO.sub.4 and H.sub.2 O.sub.2, or H.sub.2 PO.sub.4.

Semiconductor devices are essentially switching devices. The output drivers within these devices create an intermittent current flow through the circuit's bond wires and associated conductive traces. As such, voltage surges develop with the potential for creating logic errors. Other logic damaging transient voltages are caused by voltage fluctuations along the power line as well as the interaction of other circuit components within the system.
In order to abate the potential effect of transient voltages, decoupling capacitors are commonly employed. Referring to FIG. 1, a series of decoupling capacitors 20 are connected between a ground bus (V.sub.SS bus) 16 and a power bus (V.sub.cc bus) 14 of a semiconductor chip 10. The capacitance value of each decoupling capacitor 20 is high relatively, for example on the order of 1.6 nF to 1.8 nF, when compared with the values of the capacitors employed directly by semiconductor chip 10, for example in the range of 10 fF to 20 fF.
Several problems have arisen with regards to the failing of one or more decoupling capacitors. Decoupling capacitors are fabricated by sandwiching a dielectric layer between two conductive plates. However, in the event that a decoupling capacitor's dielectric layer fails, a short may arise, potentially destroying the semiconductor chip.
What is needed is a technique for disconnecting decoupling capacitors which have failed. Ideally, the step of disconnecting must avoid additional manufacturing and labor costs. Thus, a circuit design solution incorporated into current chip manufacturing processes is preferable. Additionally, the total chip decoupling capacitance must not be significantly altered in the event of a capacitor failure. Further, significant additional chip area must not be necessitated for disconnecting failed decoupling capacitors beyond the area required for conventional decoupling capacitors.
One solution to the shorting problem for decoupling capacitors has been proposed in U.S. Pat. No. 4,879,631 assigned to Micron Technology, Incorporated. The invention teaches placing multiple pairs of decoupling capacitors in series between the ground and power buses to dramatically reduce the possibility of destroying the semiconductor chip. However, the proposed approach of coupling two capacitors in series requires much more charge storage area to achieve the equivalent capacitance of a single capacitor. As utilizing space on semiconductor chips is costly, such a scheme is not always a feasible alternative for providing a decoupling capacitor system on the chip.
In another solution, a multitude of decoupling capacitors are connected in parallel between a V.sub.cc bus and a V.sub.ss bus of the semiconductor chip. At least one plate of each decoupling capacitor is connected to the bus by means of an electrically fusible link. The dimensions and characteristics of the electrically fusible link are such that, in the event that the decoupling capacitor associated therewith fails, the electrically fusible link will blow, thereby forming an open circuit and decoupling the capacitor from the remainder of the semiconductor chip. Thus, the decoupling of the electrically fusible link is dependent on internal stimulus in the chip's interaction, i.e. the generation of sufficient current to blow the fuse link.
Difficulties have also arisen in feasibly manufacturing an electrically fusible link. Further, the materials employed to form the electrically fusible link have shown poor sensitivity, tolerances, and a high rate of false triggers in disconnecting the decoupling capacitors. Under this approach, as no sensing mechanism is necessary to ascertain whether a decoupling capacitor has failed, several properly functioning decoupling capacitors can be accidentally disconnected from the bus. Further, by relying on an electrically fusible link, a decoupling capacitor can be disconnected from the chip at any time.

Method and system for decoupling inoperative passive elements on a semiconductor chip


A cooling airflow introducing guide portion is disposed on a portion of a connector that faces fins of a voltage regulator heatsink so as to extend in a direction of array of the fins so as to ensure a predetermined clearance relative to the fins. An air intake aperture is disposed through a portion of the rear bracket that faces the voltage regulator heatsink.

1. Field of the Invention
The present invention relates to an automotive alternator that is mounted to a vehicle, and particularly relates to a construction that cools a voltage regulator.
2. Description of the Related Art
In conventional automotive alternators, a rectifier assembly is configured into an approximate C shape, and a voltage regulator, a brush holder, and a connector are configured integrally into a regulator assembly. The voltage regulator and the brush holder are disposed so as to overlap in an axial direction of a shaft, and the connector is disposed at a position that is rotated by a predetermined angle circumferentially from the voltage regulator and the brush holder in a plane that is perpendicular to the shaft and that includes the voltage regulator and the brush holder such that an opening portion faces radially outward. The regulator assembly is disposed in a space in an opening portion of the C shape of the rectifier assembly. Thus, the size of the heatsink of the rectifier is limited by the regulator assembly and cannot be enlarged. Furthermore, ventilation resistance in the connector and ventilation resistance in the voltage regulator differ from each other, and irregularities in ventilation resistance on an intake side that includes the rectifier assembly are great.
In view of these conditions, improved conventional automotive alternators have been proposed that include a regulator assembly in which a voltage regulator and a brush holder are disposed so as to overlap in an axial direction of a shaft, and the connector is disposed in close contact with the voltage regulator radially outside the voltage regulator such that an opening portion faces radially outward (see Patent Literature 1, for example). In these improved conventional automotive alternators, because the regulator assembly is disposed in a space in an opening portion of the rectifier assembly that has a C shape, the heatsink of the rectifier can be made larger, improving cooling of the rectifier. In addition, irregularities in ventilation resistance on the air intake side that includes the rectifier assembly are reduced.
Patent Literature 1: Japanese Patent Laid-Open No. 2002-142423 (Gazette), which corresponds to U.S. Pat. No. 6,740,995 to Oohashi et al.
In improved conventional automotive alternators, the connector is disposed radially outside the voltage regulator in order to improve cooling of the rectifier. The heatsink of the voltage regulator is disposed in a plane that is perpendicular to the shaft such that ventilation channels between the fins are aligned in a radial direction. The connector is placed in close contact with a radially outer side surface of the heatsink of the voltage regulator, and is in a state that blocks radially outer openings of the ventilation channels between the fins. Thus, cooling air does not flow into the ventilation channels between the fins of the heatsink of the voltage regulator satisfactorily, making cooling performance of the heatsink poor and increasing the temperature of the voltage regulator.


Memory cell arrays are arranged on a chip. Each memory cell array has banks. Each bank has cell array blocks. A decoder section is concentrated in the middle of the chip. The decoder section has a row decoder, a word line drive circuit decoder for selecting a word line drive circuit, a sense amplifier decoder for selecting a sense amplifier, and an equalize signal decoder for selectively supplying an equalize signal. Each of these decoders outputs a select signal. The individual banks share the decoder section. Each bank has a latch circuit for latching a select signal in pulse form supplied from the decoder section and controls the memory blocks according to each select signal latched in the latch circuit. A shared sense amplifier is provided between memory blocks in each bank. A redundancy cell array is provided for each bank.

This invention relates to a dynamic semiconductor memory device with banks capable of operating independently which is applied to high-speed data transfer DRAMs (dynamic random access memories), such as synchronous DRAMs, Rambus DRAMs, and SynchLink DRAMs, which have appeared after 64-Mbit DRAMs.
It was the 16-Mbit synchronous DRAM that first used the concept of bank. FIG. 42 shows a conventional synchronous DRAM. In the synchronous DRAM, two large memory cell arrays M0, M1 are provided in a chip CP. These memory cell arrays M0, M1 are used as bank BK0, BK1 respectively. In the middle of each of the memory cell arrays M0, M1, a shared row decoder (SRDC) and a word line drive circuit (WLD) are provided. On both sides of the shared row decoder and word line drive circuit, memory blocks MBLKs are provided. Shared sense amplifiers (SS/A) shared by adjacent memory blocks are provided between the memory blocks MBLKs. Each of the memory cell arrays M0, M1 is provided with a column decoder (CDC). A peripheral circuit is provided between the column decoders. In the case of such a configuration, it is relatively easy to arrange the individual circuits. In the figures that follow, the same parts as those in FIG. 42 are indicated by the same reference symbols.
FIG. 43 shows the bank structure of a 64-Mbit synchronous DRAM. The DRAM has four banks, BK0, BK1, BK2, and BK3. In the structure, an area in which memory cell arrays are arranged in a chip is divided into four pieces. A bank is set for each area. Therefore, banks can be allocated readily to the individual memory cell arrays.
FIG. 44 shows the bank structure of a 256-Mbit synchronous DRAM. In the DRAM, a structure of eight banks, larger than the number of divisions of memory cell array, is considered to be standard. The allocation of pins is standardized as shown in FIG. 45. A set of eight I/O pins for inputting and outputting data is arranged on each side of one longitudinal end of the package and another set of eight I/O pins is arranged on each side of the other longitudinal end of the package; and a set of pins for inputting commands, including a row and address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE, and address signals Add is arranged on each side of the middle of the package. In the layout, banks of the same structure are allocated symmetrically with respect to the center line of the chip.
Specifically, in FIG. 44, an area in which memory cell arrays are arranged is divided in two equal parts. In the middle of the chip CP, a peripheral circuit 341 is provided longitudinally. In the area above the peripheral circuit 341, bank BK0 to bank BK7 are arranged in that order from left to right. In the area below the peripheral circuit 341, bank BK0 to bank BK7 are arranged in that order from right to left. With this structure, because memory blocks of the same banks are not arranged adjacently along the peripheral circuit 341, shared row decoders cannot be used. To access each bank independently, a row decoder RDC and a word line drive circuit (not shown) are provided on each side of each bank. This causes a problem: two row decoders and two word line drive circuits must be provided for adjacent banks, which requires a large area for their arrangement.
FIG. 46 shows the bank structure of a synchronous DRAM. As shown in FIG. 46, a method of allocating banks in the direction in which sense amplifiers are provided has been considered. With this structure, because memory blocks of the same banks are arranged adjacently along the peripheral circuit 341, shared row decoders SRDC can be used. At the boundaries of banks, however, shared row decoders SRDC cannot be used, two sense amplifiers S/A used for each bank must be provided at the boundaries (represented by bold lines) of the banks. As a result, a large area for providing sense amplifiers at the boundaries of the banks is needed, which makes the chip size larger in the direction in which banks are arranged.
When banks are allocated as shown in FIG. 46, a disadvantage results in that the efficiency of remedying defective rows by a flexible redundancy method decreases. The flexible redundancy method is a method of providing redundancy word lines for cell arrays.
FIG. 47A shows the flexible redundancy method applied to cell arrays to which conventional banks have not been allocated. The memory cell array represents a 16-Mbit memory cell array in which sixteen 1-Mbit cell arrays CAs are arranged. Shared sense amplifiers SS/As are provided between cell arrays CAs. Near a column decoder CDC, a redundancy cell array R/D with redundancy word lines is provided exclusively for redundancy. The redundancy cell array R/D has a capacity of, for example, about 128 Kbits. A sense amplifier S/A is provided on each side of the redundancy cell array R/D.
As described above, because one redundancy cell array R/D is provided for 16 cell arrays CAs, even if any one of the 16 cell arrays has a defective word line, the defective word line can be replaced with a redundancy word line in the redundancy cell array R/D. When such a flexible redundancy method is compared with a method of providing a redundancy word line for every 1 Mbits, the flexible redundancy method has an improved efficiency of remedying defective word lines as compared with the latter method, provided that the total number of redundancy word lines in the former method is the same as that of the latter method. For example, the total number of redundancy word lines in a case where a single redundancy word line is provided for every 1 Mbits is equal to that in a case where 16 word lines are provided for a total of 16 Mbits. When a single redundancy word line is provided for every 1 Mbits, however, if more than one failure occurs in a set of 1 Mbits, they cannot be remedied, whereas when 16 word lines are provided for a total of 16 Mbits, they can be remedied.
When banks are arranged as shown in FIG. 46, a redundancy cell array R/D must be provided for each bank to enable each bank to operate independently. Specifically, when the flexible redundancy method is applied to the structure of FIG. 46, four redundancy cell arrays R/Ds corresponding to the individual banks must be provided for the 16 cell arrays that are selected by a single column decoder, as shown in FIG. 47B. With this structure, because a sense amplifier is provided on each side of each redundancy cell array R/D, even when the total number of redundancy word lines is the same as that in FIG. 47A, the area for sense amplifiers can increase, resulting in an increase in the chip size.
As described above, when the number of banks provided in a chip is larger than the number of divisions of memory cell arrays, it is expected that it will be difficult to use shared row decoders, shared sense amplifiers, and flexible redundancy method effectively and therefore the chip size will increase.

Dynamic semiconductor memory device with banks capable of operating independently