A laser illumination device including a body, a head secured to the body, a laser generator accommodated in the head, and a rotatable output adjustment member having a graduated disk and an adjustment disk. The graduated disk defines a circle of graduated sections, at least one of which is exposed out of the head. The adjustment disk includes a plurality of through holes with different sizes, arranged in a circle. The measuring member coupled with the graduated disk rotates relative to the body to align each one of the through holes with the laser generator, to adjust the amount of laser light passing through the one of the through holes.

1. Technical Field
The present disclosure relates to laser pens, and particularly to a laser pen used for illuminating workpieces.
2. Description of Related Art
During manufacturing of portable electronic devices, some deficiencies (e.g., stains on shells, flaws in lenses, or scratch marks on display panels) need to be identified and measured. However, these deficiencies are usually too minor to be measured by typical mechanical testing devices.
Therefore, there is room for improvement within the art.

Laser illumination device with adjustable light output


In the prior art, in character recognition of a language having many characters, such as Japanese, a feature vector is extracted from an input pattern, distances between the feature vector and reference vectors are calculated, and a character corresponding to a reference vector having the smallest distance value is selected as a recognized character. However, in the character recognition of a language having many characters, since the number of the reference vectors to be compared is large, there is a limit in improvement of processing speed of the character recognition. In the present invention, reference vectors corresponding to target characters are classified into plurality of classes based on occurrence frequencies of characters. When distances between the feature vector and the reference vectors are calculated, a comparison is sequentially made from the reference vectors of a class having a high character occurrence frequency, so that the processing speed of the character recognition is improved.

1. Field of the Invention
The present invention relates to character recognition of a language having many characters, such as Japanese, Chinese, or Korean.
2. Description of the Related Art
In character recognition of a language having many characters, such as Japanese, Chinese, or Korean, there is adopted such a method that features are extracted from an input pattern to extract a feature vector, distances between the feature vector and reference vectors previously extracted for all target characters to be recognized are calculated, and a character corresponding to a reference vector having a smallest distance value is selected as a recognized character.
Japanese Patent Unexamined Publication No. Hei. 2-186490 discloses a system for performing character recognition by calculating distances between a vector extracted from a pattern of an input character and reference vectors extracted from patterns of previously stored target characters. In this system, the Euclidean distance between the vector of the input pattern and the reference vector is calculated and is compared with a predetermined threshold to perform character recognition.
Japanese Patent Unexamined Publication No. Hei. 4-286087 discloses a system for performing character recognition by extracting a feature vector from an input character pattern and calculating the Euclidean distance from a reference vector stored in a feature dictionary, in which the feature dictionary is divided into clusters for respective similar character categories, a distance between the feature vector of the input pattern and a reference vector representing each cluster is calculated, and detailed recognition processing is performed as to reference vectors of similar characters belonging to a cluster having a smallest distance.
In general, in a language having many characters, such as Japanese, Chinese, or Korean, a very large number of features, for example, several hundreds or several thousands features, are used to improve recognition accuracy. In a character recognition system based on a distance from a reference vector corresponding to each candidate character, in general, it takes a calculation time in proportion to the number of candidate characters and the number of features, so that a drop in recognition speed becomes a problem. Specifically, as a distance, there is the Euclidean distance, the weighted Euclidean distance, the city block distance, or the like,
                                              Euclidean                                                              distance                                                                          ∑                          i              =              1                        m                                                                                (                                                x                  i                                -                                  r                  i                                            )                        2                                                  weighted                                                  Euclidean                                                  distance                                                                  ∑                          i              =              1                        m                                                                                w                i                                                          (                                                      x                    i                                    -                                      r                    i                                                  )                                      2                                                                            city                                                              block                                                              distance                                                                          ∑                          i              =              1                        m                                                                                                                          x                i                            -                              r                i                                                                    Where,    X=(x1, . . . , xm): feature vector of input pattern    Rj=(Rj1, . . . , rjm): reference vector of j-th candidate character    W=(w1, . . . , wm): weight vector of feature    m: the number of features    n: the number of target characters
In any case, it takes calculation of the distance element (xi−r1)2, |x1−ri| with respect to the respective features n×m times, that is, (the number of candidate characters)×(the number of features) times.
In the foregoing Japanese Patent Unexamined Publication No. Hei. 4-286087, a calculation of the Euclidean distance is restricted to the similar character cluster, so that the processing speed is improved. However, predictions are that it is difficult to properly determine a representative vector as a standard of selection of the similar character cluster, and predictions are that recognition accuracy is lowered according to the quality of the representative vector.

Hewlett-Packard Development Company, L.P.


A tool arranged for employment in a golfing game includes a tubular housing having a spike at a first end of the housing, and a cap mounted to the second end of the housing, with the cap removably mounted relative to the second end to receive a circular tee member arranged for receiving a golf ball thereon arranged for projection through the tube for positioning upon an underlying ground surface. The cap structure includes spaced semi-cylindrical flanges in facing relationship relative to one another coaxially aligned relative to the cap and the housing for resiliently grasping a golf ball therebetween as the flanges are arranged in a spring biased relationship towards one another.

1. Field of the Invention
The field of invention relates to golfing tool structure, and more particularly pertains to a new and improved golf tool wherein the same is arranged for the positioning of a golf ball on a golf tee on an underlying golf surface and structured to arranged for the lifting of the tee subsequent to its use.
2. Description of the Prior Art
Golfing tool structure of various types have been utilized throughout the prior art, such as indicated in U.S. Pat. Nos. 4,007,928; 4,787,632; 4,475,676; 5,042,812; and 4,960,239.
The instant invention attempts to overcome deficiencies of the prior art by providing for a structure arranged for the positioning of a golf ball upon a golf tee and the subsequent lifting of the golf tee and golf ball subsequent to use.


A method for making a semiconductor structure which may be subject to small particle contaminants (12) includes pre-reacting the small particle (12) with a substrate (10) at a reaction temperature (27, 28). Pre-reacting the particle's (12) greatly reduces the particles' susceptibility to further reaction during subsequent processing, particularly gate dielectric formation. Consequently, the pre-reacted particle (13) as well as the remainder of the structure surface (11) can be covered with a high quality conformal deposited dielectric (14) which maintains a uniform thickness. Potential localized high leakage current density regions are thereby reduced. Additionally, an undesirably thin gate oxide region (70) adjacent a thick field oxide region (66) of a typical MOS structure is eliminated. Yield and reliability are thereby enhanced.

The present invention relates to semiconductor structures, and more particularly to semiconductor structures having particles on a semiconductor substrate surface.
A class of solid state devices commonly used in manufacturing integrated circuits is known as the MOS or MIS transistor. The name derives from their basic structure which employs a semiconductor substrate such as silicon or gallium arsenide called "S", a conductive gate electrode usually made of polycrystalline (poly) silicon or metal called "M", and in between the two an insulating layer called "I" which is often comprised of silicon dioxide called "O". Large chips such as multi-megabit memories utilize millions of MOS transistors, all of which must work reliably within specification limits.
It is important to note that the insulating layer in an MOS transistor is very thin, often less than 150 .ANG. thick, and it is generally formed by heating the silicon substrate in an oxidizing atmosphere. In the liquid chemicals used for etching, cleaning and washing, and in the equipment and the supply gases used for oxidation there are particulates. Some of these particulates will remain on the surface of a silicon wafer when it is ready to begin its high temperature oxidation cycle. Particulates smaller than 3500 .ANG. are not detectable by production-compatible techniques. These small particulates are still very large compared to the oxide thickness to be grown. Accordingly, a small particle on the silicon surface during a thermal oxidation cycle can cause a large localized perturbation in oxide properties.
For example, refractory particulates may simply tend to mask the oxidation process; if a particulate is subsequently removed, a thin spot in the oxide remains. Metallic particulates will tend to react with the silicon and oxygen, producing a region that is not the desired SiO.sub.2 insulator, but rather a metal-silicon-oxygen composite. If a defective region in the insulator of a device is large enough, its MOS I-V characteristic will exhibit higher leakage current than the rest of the device; this is measurable. However, in most cases the dielectric defect is so small that even though the current density flowing through it is very high compared to the rest of the MOS structure, its current is less than that carried by the remaining undefected structure. For example, a 100 .ANG. defect carrying 10.sup.4 times as much current density would be unnoticed in a 20 .mu.m.sup.2 MOS device.
Nevertheless, SiO.sub.2 exhibits a well-known wear-out phenomenon; it breaks down electrically as a result of electric current flowing through it. Breakdown depends upon how much electronic charge density, e.g. coulombs per cm.sup.3, has passed through the insulator. For steady state conditions, this equals current density times time. This is called the charge-to-breakdown, or Q.sub.BD, effect. Accordingly, an MOS chip may pass final test, but fail burn in or exhibit field failure as a result of a small particle-induced, electrically-invisible defect in the gate oxide of one of its thin dielectric MOS regions.
Consequently, what is needed is a method for minimizing the undesirable impact and consequences of small particles in semiconductor processes.

Semiconductor structure with stable pre-reacted particle and method for making


Amorphous derivatives of kaolin group minerals characterized by high specific surfaces and/or high cation exchange capacities and a .sup.27 AL MAS NMR spectrum having a dominant peak at about 55 ppm relative to Al(H.sub.2 O).sub.6.sup.3+. Such derivatives are prepared by reacting a kaolin group mineral with a reagent, such as, an alkali metal halide or an ammonium halide which converts the majority of the octahedrally coordinated aluminum in the kaolin group mineral to tetrahedrally coordinated aluminum. Such derivatives show high selectivity in its cation exchange towards the metals: Pb.sup.2+, Cu.sup.2+, Cd.sup.2+, Ni.sup.2+, CO.sup.2+, Cr.sup.3+, Sr.sup.2-, Zn.sup.2+, Nd.sup.3+ and UO.sub.2.sup.+.

The kaolin group minerals comprise kaolinite, nacrite, dickite and halloysite, and are among the most common clay minerals in nature. They have a 1:1 layered structure, that is, each layer consists of one tetrahedral silicate sheet and one octahedral sheet, with two-thirds of the octahedral sites occupied by aluminium. Kaolinite, nacrite and dickite all have the ideal chemical composition: EQU Al.sub.2 Si.sub.2 O.sub.5 (OH).sub.4
They differ from one another only in the manner in which the 1:1 layers are stacked. Halloysite, in its fully hydrated form, has the ideal chemical composition: EQU Al.sub.2 Si.sub.2 O.sub.5 (OH).sub.4 O2H.sub.2 O
and differs from the other three members of the group by including molecular water in the interlayer.
Of the kaolin group minerals, kaolinite is the most abundant and has received most attention in terms of its structure, properties and industrial applications. However, because of its close similarity with the aforementioned polytypes, many of the properties and uses described for kaolinite apply equally to the other polytypes. Consequently, for the purposes of expediency, the following disclosure will be restricted primarily to kaolinite and halloysite but it should be borne in mind, as it will be readily appreciated by those skilled in the art, that the invention applies equally to nacrite and dickite.
Naturally occurring kaolins typically have a wide range of particle sizes, particle crystallinity, minor element composition(s) and chemical reactivity for intercalation reactions. Kaolins sorted into a size range of 0.5-2.0 mm typically have a specific surface of about 5 m.sup.2 g.sup.-1 and a cation exchange capacity of 10 meq./100 gm or less. These, and other properties, such as opacity and rheology, make kaolins suitable for a wide range of uses including paper coatings and fillers, pottery, porcelain and sanitaryware production and fillers in paints and rubbers. These properties however do not allow kaolins to be readily utilised in other uses as described hereinafter. However, if their specific surface and/or cation exchange capacities could be increased, their usefulness would be increased and thus they could then be used in many other applications including use as catalysts, metal scavengers, carriers and absorbents. In view of this, there has been considerable and ongoing interest in finding a process for delaminating or increasing the surface area of the layered kaolin structure as this would have the potential of making available for reaction large surface areas between the layers. To date, delamination has not been demonstrated despite substantial research on the intercalation of kaolinite and its polytypes. Recent research by N. Lahav (1990)!, Clays and Clay Minerals 38, 219-222)! suggested a stable suspension of delaminated kaolinite which had been treated with dimethylsulfoxide and ammonium fluoride in aqueous solution. The result was inferred on the basis of change of particle size and there was no evidence of the independent existence of the kaolinite reaction product.
It is therefore an object of the present invention to provide derivatives of the kaolin group minerals which have higher specific surfaces and/or higher cation exchange capacities than the kaolin group minerals per se.


A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

The integration of high value capacitors in integrated circuits (ICs) is limited by the fact that conventional high value capacitors take up large areas of the IC chip, thus reducing device packing density and layout efficiency. Many applications require a large number of capacitors. Often the capacitors must be incorporated as discrete off-chip components, substantially increasing the bulk of the peripheral circuitry. In view of the increasing demand for compact lightweight electronic equipment, it is desirable that the number of discrete components be reduced.
The minimum dimensions of IC capacitors are determined primarily by the relatively low dielectric constant (0<10) of conventional capacitor dielectrics, e.g. SiO2 and Si3N4. Thus, as device dimensions decrease, there is increasing interest in other dielectrics having higher dielectric constants than conventional dielectric materials.
Ferroelectric (FE) and high-epsilon (HE) dielectrics (0=20 or greater) have found application in random access memory (RAM) cells since they provide for the formation of NVRAMs and DRAMs. Moreover, when used as NVRAM, ferroelectric dielectrics advantageously provide low voltage programmability, fast access times and low power consumption.
FE materials pose several integration problems. In particular, most ferroelectric materials require high temperature post-deposition oxygen anneals (600° C. or above) to achieve properties desirable for storage media. However, such high anneal temperatures can be incompatible with the CMOS devices already fabricated on the wafer. Furthermore, any subsequent forming gas or hydrogen anneals (highly desirable for CMOS devices) degrade the ferroelectric material, thus requiring additional high temperature oxygen anneals late in the processing sequence which in turn are detrimental to the CMOS circuitry.
In view of the above drawbacks with prior art methods of integrating ferroelectric capacitors with CMOS structures, there is a continued need for developing a new and improved method which is capable of providing an integrated FE capacitor/CMOS structure without subjecting the CMOS structure to high temperature steps that are typically required in the prior art for ferroelectric processing.

International Business Machines Corporation


A system for tissue approximation and fixation is described herein. A device is advanced in a minimally invasive manner within a patient's body to create one or several divisions or plications within a hollow body organ. The system comprises a stapler assembly having a tissue acquisition member and a tissue fixation member. The stapler assembly approximates tissue from within the hollow body organ with the acquisition member and then affixes the approximated tissue with the fixation member. In one method, the system can be used as a secondary procedure to reduce the size of a stoma within the hollow body organ.

1. Field of the Invention
The present invention relates generally to medical apparatus and methods. More particularly, it relates to devices and methods for approximating portions of a hollow body organ, particularly a stomach, intestine, or other region of the gastrointestinal tract, while affixing the tissue.
2. General Background and State of the Art
In cases of severe obesity, patients may currently undergo several types of surgery either to tie off or staple portions of the large or small intestine or stomach, and/or to bypass portions of the same to reduce the amount of food desired by the patient, and the amount absorbed by the gastrointestinal tract. The procedures currently available include laparoscopic banding, where a device is used to "tie off" or constrict a portion of the stomach, vertical banded gastroplasty (VBG), or a more invasive surgical procedure known as a Roux-En-Y gastric bypass to effect permanent surgical reduction of the stomach's volume and subsequent bypass of the intestine.
Typically, these stomach reduction procedures are performed surgically through an open incision and staples or sutures are applied externally to the stomach or hollow body organ. Such procedures can also be performed laparoscopically, through the use of smaller incisions, or ports, through trocars and other specialized devices. In the case of laparoscopic banding, an adjustable band is placed around the proximal section of the stomach reaching from the lesser curve of the stomach around to the greater curve, thereby creating a constriction or "waist" in a vertical manner between the esophagus and the pylorus. During a VBG, a small pouch (approximately 20 cc in volume) is constructed by forming a vertical partition from the gastroesophageal junction to midway down the lesser curvature of the stomach by externally applying staples, and optionally dividing or resecting a portion of the stomach, followed by creation of a stoma at the outlet of the partition to prevent dilation of the outlet channel and restrict intake. In a Roux-En-Y gastric bypass, the stomach is surgically divided into a smaller upper pouch connected to the esophageal inflow, and a lower portion, detached from the upper pouch but still connected to the intestinal tract for purposes of secreting digestive juices. A resected portion of the small intestine is then anastomosed using an end-to-side anastomosis to the upper pouch, thereby bypassing the majority of the intestine and reducing absorption of caloric intake and causing rapid "dumping" of highly caloric or "junk foods".
Although the outcome of these stomach reduction surgeries leads to patient weight loss because patients are physically forced to eat less due to the reduced size of their stomach, several limitations exist due to the invasiveness of the procedures, including time, use of general anesthesia, time and pain associated with the healing of the incisions, and other complications attendant to major surgery. In addition, these procedures are only available to a small segment of the obese population (morbid obesity, Body Mass Index≧40) due to their complications, leaving patients who are considered obese or moderately obese with few, if any, interventional options.
In addition to surgical procedures, certain tools exist for approximating or otherwise securing tissue such as the stapling devices used in the above-described surgical procedures and others such as in the treatment of gastroesophageal reflux disease (GERD). These devices include the GIA® device (Gastrointestinal Anastomosis device manufactured by Ethicon Endosurgery, Inc. and a similar product by USSC), and certain clamping and stapling devices as described in U.S. Pat. Nos. 5,403,326; 5,571,116; 5,676,674; 5,897,562; 6,494,888; and 6,506,196 for methods and devices for fundoplication of the stomach to the esophagus for the treatment of gastroesophageal reflux disease (GERD). In addition, certain tools, such as those described in U.S. Pat. Nos. 5,788,715 and 5,947,983, detail an endoscopic suturing device that is inserted through an endoscope and placed at the site where the esophagus and the stomach meet. Vacuum is then applied to acquire the adjacent tissue, and a series of stitches are placed to create a pleat in the sphincter to reduce the backflow of acid from the stomach up through the esophagus. These devices can also be used transorally for the endoscopic treatment of esophageal varices (dilated blood vessels within the wall of the esophagus).
There is a need for improved devices and procedures. In addition, because of the invasiveness of most of the surgeries used to treat obesity and other gastric disorders such as GERD, and the limited success of others, there remains a need for improved devices and methods for more effective, less invasive hollow organ restriction procedures.


A battery module assembly includes a plurality of cells, a plurality of cartridges including a first cartridge (a cartridge A) and a second cartridge (a cartridge B) alternately stacked with a corresponding cell therebetween, and a caulking pipe inserted into a through hole provided in a corner of each of the stacked plurality of cartridges, for assembling the plurality of cartridges. A bus bar among main elements configuring a voltage sensing assembly is disposed in a frame configuring a short side among four frames configuring the first cartridge, and a sensing wire among the main elements configuring the voltage sensing assembly is disposed in two frames configuring a short side and one frame configuring a long side among four frames configuring the second cartridge.

FIG. 1 is an exploded perspective view of a related art battery module assembly 100.
Referring to FIG. 1, the related art battery module assembly 100 includes a plurality of pouch type battery cells 200, a cell cover 310 which surrounds whole outer surfaces of a pair of battery cells (two battery cells) or three or more battery cells, and an upper frame member 400 and a lower frame member 500 which are vertically detached from each other and are coupled to each other in an assembly fastening structure.
In FIG. 1, reference numeral 223 refers to an electrode terminal, and reference numerals 600 and 601 refer to bus bars. Descriptions of the other reference numerals are omitted.
The related art battery module assembly 100 has the following problems.
First, a forming structure is processed to surround a pair of battery cells (two battery cells) or three or more battery cells, and in this case, a cell cover 310 may use a thin aluminum material so as to decreasing a size thereof. The aluminum material has a high possibility that insulating properties are damaged by water.
Second, although not shown in detail, an insert nut structure (an assembly structure) for assembling an upper detachable frame and a lower detachable frame and an insert bolt structure (a mounting structure) for mounting a battery module on an inner portion of a vehicle are needed, a battery module size increases and the number of elements increases.
Third, a lower frame member 500 is manufactured by an injection process, but a limitation of the injection process causes a phenomenon (a rib bending phenomenon) where a vertical partition wall part (rib) configuring the lower frame member 500 is inward contracted like a direction of a dotted arrow illustrated in FIG. 1.
Therefore, in order to easily insert the cell cover surrounding the battery cells into the lower frame member 500, a worker should perform a handwork of unfolding a partition wall part with hands several to tens times before working, and the handwork increases an assembly cycle time (an assembly process time).


An integrated circuit die comprises an internal signal pad arranged at a location away from a periphery of the die, a peripheral signal pad arranged proximate the periphery of the die, and a switch coupled between the internal signal pad and the peripheral signal pad. The switch is configurable in at least a first state in which the internal signal pad is not operatively connected to the peripheral signal pad, and a second state in which the internal signal pad is operatively connected to the peripheral signal pad, responsive to a control signal having one of respective first and second signal characteristics. The switch is configured in the first state during normal operation of the integrated circuit die, and is configured in the second state to permit test access to the internal signal pad via the peripheral signal pad.

Integrated circuits have to be able to send and to receive electrical signals to and from external or "off-chip" elements. This communication with off-chip elements is typically achieved through the use of buffer circuits, also commonly referred to simply as "buffers." FIGS. 1 and 2 show the layouts of conventional integrated circuits, illustrating the placement of buffer circuits therein.
With reference initially to FIG. 1, an integrated circuit die 100 includes a plurality of buffer circuits 102 arranged adjacent to its periphery as shown. Associated with each of the buffer circuits 102 is a corresponding bonding pad 104, which may be viewed as an example of what is more generally referred to herein as a signal pad.
FIG. 2 shows an integrated circuit die 100′ which includes peripherally-arranged buffer circuits 102 as in FIG. 1 but also includes an area array 106 comprising additional buffer circuits. Again, associated with each of the buffer circuits 102 is a corresponding bonding pad 104. This placement allows many more buffer circuits to be placed on a single integrated circuit die than the simple outer perimeter placement of FIG. 1. During manufacturing of a packaged integrated circuit with area array buffers, a special technique called solder bumping is often used to allow all of the bonding pads in the area array to be connected to corresponding signal paths in the structure in which the integrated circuit die is packaged.
A problem associated with use of area array buffers such as those shown in FIG. 2 is that it is difficult to gain access to internal analog signal pads during testing that occurs before the integrated circuit die is packaged. Such pre-package testing typically involves testing the integrated circuit die while it is still part of the semiconductor wafer, that is, before the wafer is cut into chips which are individually packaged, and is thus also referred to herein as wafer-level testing. The wafer-level testing is carried out using a wire-type wafer probe card comprising many short but stiff wires, referred to as test probes, that temporarily connect the peripheral bonding pads of the integrated circuit die to an associated test apparatus.
FIG. 3 illustrates the application of a set of wafer test probes 108 to a set of bonding pads associated with peripheral buffers 110 on one side of the integrated circuit die 100′. For clarity and simplicity of illustration, this figure shows only the left side of the integrated circuit die being probed, but in practice all four sides are probed at the same time using the same wire-type wafer probe card. Unfortunately, a standard wire-type wafer probe card can only contact the peripheral bonding pads, and cannot reach the bonding pads which are inside the area array.
Although there is another type of wafer probe card, known as a membrane probe card, which can reach internal bonding pads within an area array during wafer-level testing, this type of card is generally very expensive and difficult to use.
One possible alternative is to provide permanent connections between the bonding pads inside the area array to corresponding peripheral bonding pads for wafer-level testing. However, this approach is usually appropriate only for digital signal pads, since for analog signal pads the connecting wires may add unacceptable amounts of parasitic resistance and capacitance, thereby degrading analog signal performance during normal operation of the subsequently-packaged integrated circuit.
It is therefore apparent that a need exists for improved techniques for providing wafer-level test access to internal analog signal pads of an integrated circuit die, without the excessive cost and other difficulties associated with use of a membrane probe card.

Integrated circuit with controllable test access to internal analog signal pads of an area array


A memory test engine performs memory tests on an embedded memory located in a device under test (DUT) simultaneous to analog tests performed by an automatic tester. The automatic tester provides coded information to the memory test engine, which includes a description of the embedded memory within the DUT. The memory test engine operates autonomous to the automatic tester; apply addresses, data and control and comparing results of the memory test to expected values. The automatic tester and the memory test engine use the same DUT data bus; and therefore, arbitrate the use of the bus of the DUT.

1. Field of Invention
A semiconductor tester and in particular a built-off self test (BOST) for an embedded memory in a device operating simultaneous to other testing being performed.
2. Description of Related Art
Built in self test (BIST) capability occupies valuable real estate on a semiconductor chip especially for implementing a memory BIST. Economics is a prime consideration for semiconductor LCD (liquid crystal display) driver devices. Not only is the real estate that would be occupied with a BIST circuit costly, but also the need to have a tester to perform a set of tests on a semiconductor chip with a diverse set of circuitry is also costly. Testing of such a device requires a sequential set of test procedures in which the testing of the embedded memory occupies a substantial portion of the total test time. Finding ways to reduce the total test time of a device with such a diverse set of requirements is important to the reduction of total product cost.
U.S. Pat. No. 6,829,728 (Cheng et al.) is directed to a test circuit for testing embedded synchronous memories where a BIST (built-in self test) controller is used to address the memory and provide reference data to compare to the memory output. U.S. Pat. No. 6,721,904 (Ernst et al.) is directed to a BOST (built off (chip) self test) function located between a DUT (device under test) and a semiconductor tester for the purpose of testing a SDRAM. U.S. Pat. No. 6,653,855 (Mori et al.) is directed to a BOST board containing a connector, a substrate and an external self test circuit. In U.S. Pat. No. 6,587,979 (Kraus et al.) a flexible BIST is directed to being incorporated into an integrated circuit chip. In U.S. Pat. No. 6,286,115 (Stubbs) discloses a test circuit is directed an on-chip test circuit that includes a multiplexer and an interface to I/O to allow interfacing with I/O associated an embedded memory to allow testing and repairing the embedded memory. U.S. Pat. No. 6,182,257 (Gillingham) is directed to a semiconductor device with a self test circuit, which includes a test memory array, a self test controller for internally generating test and results data, and an interface for loading test data into the test memory array. U.S. Pat. No. 6,072,737 (Morgan et al.) is directed to an embedded test circuit to test an embedded DRAM of an integrated circuit chip wherein the test circuitry interfaces with a memory tester. In U.S. Pat. No. 4,873,705 (Johnson) a method and system is directed to functionally testing memories in microprocessor based units or boards under test with an interface circuit coupled to the bus structure of the unit under test.
In FIG. 1 is a diagram of prior art showing a test time sequence for testing an LCD driver chip as might be performed by automatic test equipment (ATE). DC tests are first performed as an initial screen of the chip to determine the ability of the chip to be powered and have I/O circuits free of shorts and opens. A test is then performed on the embedded array (RAM) to determine the capability of the array to properly store and read data This is then followed by analog tests to test the ability of the I/O drivers and receivers to function properly, followed by a test of the digital circuits and the chips video capability.
A built-in-self-test (BIST) circuit could be useful in reducing the test time required by an ATE particularly with respect to the embedded memory, but this would be at the cost of the additional chip size required to accommodate the BIST circuitry and the BIST would require testing. A built-off-(chip)-self test (BOST) could also be used, but an allocation of test time is still required for the embedded memory.


A recording/reproducing method and device for an automatic performing piano which not only seizes performance information according to occurrence and timing of an on-event, but also converts the performance information according to actual emission timing in each respective recording and reproducing process steps, thereby achieving accurate performance reproduction with balance and high fidelity. Since a time lag between depression of key and emission of sound varies with the intensity in depressing of the keys, this time lag is incorporated into performance information to be stored, a key drive solenoid can be actuated or terminated in immediate response to the output of key depression or release data, respectively.

This invention relates to a recording/reproducing method and device for controlling sound emission for an automatic performing piano, and more specifically to such a piano which is immune from inaccuracy of performance in sound reproduction due to the time lag of emission of sound caused by variations in intensity of depressed keys.
A conventional automatic performing piano has suffered from imbalance of sound emission timing between strong key strokes and weak key strokes. This is due to the time period from a depress-key command (on-event) to actual emission of sound during which a solenoid is energized.
Some prior art methods try to solve this problem by adopting a sound prohibited time period T.sub.1, as shown in FIG. 11, in designing the value of electric power L.sub.drv to be supplied to the solenoid for the depressed keys. In the figure, L.sub.1 is an original voltage level, L.sub.2 is a start-up voltage level, and L.sub.3 is a holding voltage level. T.sub.2 is a time period to sustain the start-up voltage level. The sound prohibited time period T.sub.1 is provided at the first stage of the application of electric power L.sub.drv in order to correct emission timing. The sound prohibited time period T.sub.1 is determined according to depression intensity data included in depression data, such that the stronger the key stroke is, the longer the duration of the sound prohibited time period T.sub.1. The maximum value of the sound prohibited time period T.sub.1 is 100 milliseconds.
In formulating or formatting recorded performance information to be later reproduced, the prior art methods and devices define the occurrence of an on-event and off-event as the timing of depression and release of a key, respectively, which are detected by key sensors 7 and 8 shown in FIG. 3. However, this method suffers from the following problem.
Since hammer systems and other mechanisms respond to strong key strokes more quickly than to weak key strokes as shown in FIG. 12A and FIG. 12B, a time period of emission delay in recording TD.sub.rec-on, which is the time lag between occurrence of an on-event t.sub.on and actual sound emission t.sub.music, shortens as the key stroke intensifies. Therefore, in recording an original performance by a performer, simultaneous occurrence of an on-event for a strong key stroke and a weak key stroke must be interpreted in actual sound emission as a strong key stroke followed by a weak key stroke as shown in FIG. 12C to reproduce the performance with fidelity and accuracy. The prior art method and device thus fails to reproduce performance with high fidelity and accuracy because of the definition of an on-event and an off-event as the actual timing of depression and release of key, respectively.
Moreover, the following problem occurs in determining the sound prohibited time period T.sub.1 simply according to depression intensity in designing a chart or amount of electric power L.sub.drv for the performance information thus recorded. Since recording is executed according to the occurrence timing of on-event shown in the graph of FIG. 13, but not to the actual and acoustic or sound emission timing shown in the second graph of FIG. 13, the recorded interval of emission INT.sub.rec between a strong key stroke and an immediately following weak key stroke is shorter than the actual interval of emission INT.sub.act.
Further, by providing the sound prohibited time period T.sub.1 again in the sound reproduction steps, the reproduced interval of emission between the two key strokes is further shortened as shown in the fourth and fifth graphs of FIG. 13. Consequently, the time period for holding emission of the former of two successive key strokes may be corroded and shortened by the sound prohibited time period T.sub.1 for the latter, occasionally resulting in failure to reproduce the sound for the former key stroke.

Method and device for preventing imbalance of sound emissions in an automatic performing piano


A packet-based or cell-based data communication system is capable of determining whether a new call is a modem call or a voice call before a modem connection is established between the two end devices. The network switches are configured to monitor for distinctive facsimile modem and data modem calling and answer signals. In response to the detection of such calling or answer signals, the data communication system selects a speech coding scheme and/or a data transmission technique for use in connection with the current call, while a conventional 64 kbps PCM transmission scheme is maintained for communications between the network and the end devices. A speech coding protocol, such as ADPCM, may be enabled for voice calls, thus conserving network bandwidth. The 64 kbps PCM scheme may be employed to facilitate high speed modem transmissions.

The present invention relates generally to data communication systems. More particularly, the present invention relates to a technique for the flexible implementation of speech coding in a data communication network in a manner that facilitates voice transmissions, data modem transmissions, and facsimile modem transmissions.
The public switched telephone network (PSTN) is primarily used to transmit bi-directional voice calls between two end users. In recent years, particularly with the increasing popularity of the Internet, the PSTN has become a universal system that handles voice calls, data modem calls, facsimile modem calls, and other calls. The data transmission scheme and certain operational parameters may vary from connection to connection, depending upon the specific type of information being transmitted during the current communication session. For example, a relatively low data rate may suffice in the context of conventional voice calls, while a relatively high data rate may be desired for certain data modem applications.
The conventional PSTN is a circuit switched network that transmits data at a rate of 64,000 bits per second (64 kbps). In accordance with well known techniques, the PSTN utilizes pulse code modulation (PCM) techniques to transmit voice calls; ITU-T Recommendation G.711 (November 1988) sets forth the functional requirements for such 64 kbps PCM transmissions. The entire content of Recommendation G.711 is incorporated by reference herein. Although voice calls can be adequately handled via the G.711 scheme, a number of speech coding techniques may be employed to conserve bandwidth resources associated with the transmission of voice calls without sacrificing the quality of the voice transmission. For example, ITU-T Recommendation G.726 (December 1990) sets forth an adaptive differential pulse code modulation (ADPCM) scheme that may be used in the context of voice calls. The G.726 ADPCM technique effectively reduces the normal PSTN data rate from 64 kbps to 40 kbps, 32 kbps, 24 kbps, or 16 kbps. As another practical example, ITU-T Recommendation G.728 (September 1992) sets forth a speech coding methodology that effectively reduces the normal PSTN data rate to 16 kbps using linear prediction techniques. Other speech coders that may be utilized in this context (and in the context of the present invention) are set forth in ITU-T Recommendation G.723.1 and ITU-T Recommendation G.729a. The G.723.1 Recommendation contemplates a 5.3 kbps data rate and a 6.3 kbps data rate, while the G.729a Recommendation contemplates an 8 kbps data rate. The entire contents of Recommendations G.726, G.728, G.723.1, and G.729a, along with any related appendices, attachments, and summaries, are incorporated by reference herein.
The PSTN rarely uses ADPCM or other speech coding techniques because such techniques can be detrimental to data and facsimile modem transmissions. Although ADPCM-encoded speech sounds essentially identical to PCM-encoded speech, modem signals, both fax and data signals, are sensitive to the coding effects of ADPCM and suffer performance degradation compared to operation over G.711. Consequently, the performance of a modem system suffers in the context of an ADPCM channel; the data rate may be reduced by up to fifty percent. Thus, in response to the universal application of the PSTN as a conduit for voice, facsimile, and data calls, and in an effort to satisfy modem users seeking high data rates, the traditional 64 kbps PCM scheme is often employed as the primary transmission protocol within the PSTN.
In view of the circuit switched nature of PSTN calls, conventional data communication systems are not able to determine, a priori, whether a new call conveys voice information, data modem information, or facsimile modem information. Accordingly, G.711 is conventionally used when a call is established in the PSTN regardless of whether the call is a voice call or a modem call. Furthermore, the PSTN architecture is configured such that the circuit is fixed for the duration of the call. Consequently, if the call is a modem call and ADPCM encoding is present in the communication channel, then the modem transmission speed will inevitably suffer. Conversely, if the call is a voice call and speech coding is not utilized in the channel, then network resources, e.g., bandwidth, may be wasted.
Prior art data communication systems may handle some intercontinental facsimile calls in a manner that addresses the effects of speech coding. This technique is commonly referred to as demod/remod. The demod/remod technique is typically utilized for facsimile transmissions across communication channels, e.g., submarine cables, that employ ADPCM encoding. As discussed above, facsimile transmissions may be adversely affected by an ADPCM channel. In accordance with the demod/remod scheme, the call is initially established such that the end devices can transmit their respective call and answer signals. If a facsimile calling tone is detected, then intermediate facsimile modems are xe2x80x9cinsertedxe2x80x9d into the connection at the ends of the ADPCM channel. Notably, the activation of the intermediate facsimile modems occurs before the end devices begin any training procedures. The intermediate facsimile modems are configured to communicate with each other over the ADPCM channel and with the respective end devices. Accordingly, the calling side intermediate modem informs the answer side intermediate modem that a facsimile call is being placed to a certain telephone number.
Once the facsimile modem connection is initialized between the answer side intermediate facsimile modem and the destination modem device, the calling side intermediate facsimile modem establishes a compatible connection with the originating modem device. Thus, the facsimile data is transmitted between the originating modem device and the calling side intermediate facsimile modem (and between the answer side intermediate facsimile modem and the destination modem device) at a relatively high data rate in accordance with the G.711 protocol. In contrast, the facsimile data can be transmitted over the ADPCM channel at a relatively low data rate, e.g., 9.6 kbps, in accordance with conventional facsimile modem methodologies. In this manner, the ADPCM channel resources may be allocated in a more efficient manner.
Although the demod/remod technique can be employed to reduce the amount of traffic across an ADPCM link, the technique only works in connection with facsimile modem transmissions because facsimile calls can be identified by a distinct calling tone. In addition, the demod/remod technique can add a significant amount of delay to the connection time and to the overall facsimile transmission time. Notably, the demod/remod procedure is not applicable to data modem calls, where a high data rate (e.g., a rate higher than the maximum rate attainable for an ADPCM channel) is often desired.
A data communication system according to the present invention is capable of flexibly configuring itself to handle voice calls, data modem calls, and facsimile modem calls in a manner that conserves network bandwidth resources. The data communication system detects the type of information to be conveyed by the current call such that an appropriate data transmission scheme can be utilized for the current call. In a practical embodiment, a 64 kbps transmission protocol, such as the G.711 PCM protocol, may be used for data modem calls to facilitate a relatively high data rate. In contrast, speech coding techniques may be utilized for voice calls to conserve bandwidth resources associated with the communication network. Unlike some prior art methodologies that are limited to facsimile applications, the techniques of the present invention can be employed to dynamically alter the data transmission scheme for voice calls and modem calls.
The above and other aspects of the present invention may be carried out in one form by a data communication system having a calling device, an answer device, and a transmission network capable of dynamically allocating bandwidth resources for purposes of transmitting calls. The transmission network includes an interface component configured to convert from a first data coding technique associated with the calling device to a second data coding technique utilized by the transmission network. The data coding conversion is performed during the initialization of a call and is performed in response to the type of call, e.g., a voice call, a data modem call, or a facsimile modem call.

Method and apparatus for the flexible use of speech coding in a data communication network


A combination mattress includes a plurality of independent barrels each having two resting faces and an outer peripheral face extending between the two resting faces. Each independent barrel has a recess extended through the two resting faces. The independent barrels are combined together with the outer peripheral faces abutting mutually.

1. Field of the Invention
The present invention relates to a mattress and more particularly to such a combination mattress wherein the user can self adjust the resilience of the combination mattress.
2. Description of the Related Art
A conventional mattress comprises two pads, a spring shelf mounted between the two pads, and a cover mounted around the outer periphery of the two pads and the spring shelf. When a user lies on the mattress, the portion of the mattress contacting the human body is deformed with the profile of the human body, then the spring shelf provides enough support force, so that the user has a comfortable sensation when lying on the mattress.
However, the resilience of the mattress is controlled by the elasticity of the spring shelf, the spring shelf can only provides a single elastic force to support the human body. Thus, if the user wishes to change the resilience of the mattress according to the requirement of the human body, he has to buy another mattress which resilience conforms to the requirement of the human body, thereby increasing the user's economic burden, and causing disturbance in use.


A method for loading instruction codes to a first memory and linking said instruction codes is proposed, whereby at least one instruction code has as parameter an address which during a loading step is not determined. This address-parametered instruction code has assigned thereto an address place. A relocation information is loaded which during a linking step effects that the address becomes determined using a starting address and a relative address offset. The then determined address is put at the address place. During the loading step, directly after loading each address-parametered instruction code with its address place, the relocation information is loaded and the address is determined in the linking step.

The invention relates to a method and a device for loading instruction codes to a memory and linking said instruction codes. More particularly the invention relates to a combined loading and linking method in a resource-constrained environment such as a smartcard, particularly a smartcard offering a Java environment, such as a Javacard.
When loading and linking machine-dependent, size-efficient code for execution in any resource-constrained code execution environment, in all settings where only parts of the overall executable object code are present during compilation, it is necessary to perform a final step of relocation or ling in which as yet unresolved references to external symbols, e.g., functions, variables, or classes, are replaced by actual addresses valid only in the particular execution context. The linkage information is kept separate from the code in the systems where this approach to code development and installation is commonly used, e.g., personal computers, workstations, or cross-development environments for embedded systems.
In environments, where the resources of computing time, communication bandwidth, and transient memory (RAM) are scarce, and where in addition, writing to persistent memory is much more expensive than writing to temporary memory, and where finally no assumptions about the integrity of the communications infrastructure can be made, new problems appear. In particular, time-efficient ways are to be found to load the code and linkage information into the runtime environment in a secure manner ensuring confidentiality and integrity of the data loaded.
The initial setting where these assumptions hold true, are smartcards that are to be updated after they have been issued to the customer. In particular, multifunction cards or JavaCards need an efficient resolution of this issue. Therefore, the term xe2x80x98JavaCardxe2x80x99 is used in the following sections inclusively, but not exclusively to denote environments of the nature outlined above.
The first problem is the overall time required to load code and linkage information into the smartcard, perform cryptographic decryption and integrity checks on the smartcard over the loaded data, and finally relocate the newly loaded code to prepare it for execution. The second major issue is the amount of temporary data requited to perform the above operations.
In conventional systems, the relocation information comprises a fix-up information and an address information. The fix-up information points to the address place after an instruction code, which instruction code has an address as a parameter to be determined during linking. The address information contains an offset and a package ID, in the case where the relocation type indicates that the address lies in a package different from the package where the address-parametered instruction code lies. A package id (also called xe2x80x9cAIDxe2x80x9d), serves as the denominator for the starting address, hence designating a package whose starting address is to be used. In the case when the package wherein the address is located is the same package as where the address-parametered instruction code lies, the starting address is already known as the starting address of this package. The address is then determined as the starting address plus the offset. Taking the peculiarities and limitations of smart cards into account, the following basic steps are thus performed to load new executable code into a JavaCard:
Receive the code into a RAM and transfer it to a persistent memory, e.g. an EEPROM.
Receive the linkage information (fix-up information and relocation tables) into the RAM and transfer it to persistent memory.
Optionally, perform decryption and cryptographic integrity checks, commonly known as MACing, of code and linkage information.
valuate the linkage information and, for each relocation entry, determine the fix-up address and according to the relocation type, compute the actual reference address and write this reference into the appropriate fix-up address in the persistent memory.
Remove the linkage information from the persistent memory to make room for further code to be loaded in the future.
This approach however, has the drawback that by performing the cryptographic operations after all data has been loaded, an inefficient number of memory copy operations has to be executed, as those operations can only be run efficiently in RAM.
By placing linkage information into persistent memory, mainly for reasons of ease of decryption and MACing purposes, a big performance penalty has to be paid, as this data has to be deleted afterwards anyway, which in itself is another expensive write operation on persistent memory.
By performing relocation after the complete code has been loaded into persistent memory, another performance penalty is incurred, since writing single bytes to persistent memory is as expensive in terms of time as writing several bytes, namely a page.
It is an object of the invention to provide a method and a device for loading instruction codes to a memory and linking said instruction codes, which takes fewer writing cycles to a memory with a relatively high write-access time. This includes the advantage that the result of a completely loaded and linked instruction code sequence is achievable aster and that the lifetime of the device is extended since due to a limited rewritability, the number of write accesses to the same memory is limited also. The effect is further improved by exploiting the effect that a write cycle to an EEPROM for 1 byte takes the same time as does a write cycle for several bytes, i.e. an EEPROM page, e.g. 64 bytes. During the conventional linking procedure, each linking step for each address needs one memory write-access, which with view to the above fact is a waste of access time. The invention exploits to a much higher degree the writing capability of each write-cycle. To this adds that an eventual decryption, using a streaming cipher and/or integrity-check can be performed also without prior writing to the EEPROM.
Furthermore, it is an object of the invention that the amount of data needed for achieving the linking is reduced in size. The amount of data to be sent to the execution environment is smaller as compared to a format where code and relocation information is not interleaved, but strictly separated. In a setting, where first the code and afterwards the relocation information is sent, it is necessary to add to each relocation entry the information for which code address the respective relocation information is valid. This so-called fix-up information is completely made obsolete by the method presented in this disclosure. Net result is a significant reduction in the amount of data sent to the execution environment, in turn leading to a reduction of the overall time necessary to execute the upload process, significantly so, if the communications speed to the execution environment is low.
Another object of the invention is to provide distinction information enabling a distinction between the instruction codes and the relocation information facilitates access to the relocation information. Using code length information which is loaded before each set of code containing the address-parametered instruction code is advantageous since immediate information is accessible for recognizing the relocation information. Furthermore the code length information can then be erased, respectively overwritten during the lining process which again saves memory space.
Still another object of the invention comprises locating the relative address offset at the address place during the loading step saves memory space because the address place is loaded as a reserved space and is only filled up with insignificant content such as zero values which take up the same space as does the address place filled with the offset value. It proves of advantage when, in the case when the address to be determined is located in a package which is different from the package location of the address-parametered instruction code, the starting address is derived from a directly addressable starting address list, such that the usually relatively long AIDs are then only stored one time and are reduced to less space-wasting addresses. Memory space is saved when the relocation information and eventual distinction information after the linking step using said relocation information is overwritten by shifting the subsequent instruction codes.
A final object of the invention is to provide a first memory where the instruction codes are loaded to and where the linking is done, preferably has a short write-access-time, such as a RAM which provides for a fast loading and linking procedure. When afterwards the instruction codes are written to a second memory with a longer write-access-time, such as an EEPROM, the usually bigger space of the EEPROM is used to store the whole linked code and the increased write-access time is then no disadvantage since the linking and eventual decryption and integrity-verification already have been performed.
A device and method for loading code via a simple protocol into a resource-constrained environment, verifying its integrity using cryptographic methods, and relocating the code to transform it into a form actually fit for immediate execution in the above environment, is proposed. The proposed method minimizes the amount of both decryption and memory-write operations required to ensure a safe transfer and installation of code.
The main idea consists of interspersing relocation information directly into the code itself and to not cleanly separate these two components. In addition, the presented load format can also efficiently be secured by cryptographic encryption and integrity protection means which can still be checked in extremely resource-constrained execution environments.
Using a cipher which can be streamed (i.e., which during decryption and MACing only relies on a few bytes of information gathered from processing previous encrypted data and never relies on information only present further forward in the encrypted data stream) enables piecewise decryption which can then be combined with integrity check and linking.
The invention uses the principle to immediately act upon the linkage information as long as it still resides in RAM and not transfer it to persistent memory until the code is linked. This becomes possible even in a secure manner, once a streaming cipher as suggested above is used. Interweaving code and linkage information in a manner that the relocation can immediately be performed in RAM, results in only filly relocated code segments needing to be written into persistent memory, i.e., EEPROM and provides that subsequent writes of single bytes at the fix-up addresses are completely removed.
The proposed solution is hence interweaving code and linkage information for streaming. Memory is divided into immutable memory (e.g., ROM), persistent memory (e.g., EEPROM), and transient memory (e.g., RAM). Only the latter two can be written from a program with access to the memory. Writing to persistent memory is much more expensive than changing data in transient memory. Writing several bytes, such as pages, in persistent memory is as expensive as writing single bytes. Cryptographic operations require transient memory to run. Transient memory is a scarce resource and heavily contested for by all application components executed on the resource-constrained system.

Method and device for loading instruction codes to a memory and linking said instruction codes

International Business Machines Corporation


An amorphous Si/SiC heterojunction color-sensitive phototransistor was successfully fabricated by plasma-enhanced chemical vapor deposition. The structure is glass/ITO/a-Si(n.sup.+ -i-p.sup.+)/a-SiC(i-n.sup.+)/Al. The device is a bulk barrier transistor with a wide-bandgap amorphous SiC emitter. The phototransistor revealed a very high optical gain of 40 and a response speed of 10 us at an input light power of 5 uW and a collector current of 0.12 mA at a voltage of 14 V. The peak response occurs at 610 nm under 1 V bias and changes to 420 and 540 nm under 7- and 13-V biases, respectively.

Recently, amorphous semiconductor photosensors prepared by a radio-frequency glow discharge method have been developed for large-area low-cost thin-film image sensors, for example, for the contact-type linear sensor of a compact facsimile machine, or for the photoreceptor of a laser beam printer.
Basically, there are two kinds of a-Si:H photosensors, namely, Schottky or the p-i-n photodiode and the photoconductor type. However, both of these kinds of photosensors suffer from low photocurrent output and low S/N ratio, due to a lack of amplification. Recently, we have demonstrated that the amorphous silicon n.sup.+ -i- (p.sup.+)-i-n.sup.+ thin-film bulk barrier phototransistor exhibits high gain and high response speed. In this specification, the successful development of a new type of glass/ITO/a-Si(n.sup.+ -i-p.sup.+)/a-SiC(i-n.sup.+)/Al heterojunction bulk barrier phototransistor with wide-bandgap a-SiC emitter is described. This is an alternative type of the recently reported glass/ITO/a-SiC(n.sup.+ -i-p.sup.+)/a-/Si(i-n.sup.+)/Al device.

Amorphous SI/SIC heterojunction color-sensitive phototransistor


A method for detecting and autonomously tracking a target object using a LIDAR sensor that continuously emits laser pulses onto the target object and generates a 3-D point cloud from measurement points reflected by the target objects at predetermined time intervals. A current relative position of the target object is calculated for six degrees of freedom of movement of the target object at the predetermined time intervals based on algorithms estimating the position. The method includes acquiring a high-resolution initializing point cloud over a plurality of predetermined time intervals, generating a reference model with a small number of measurement points from the initializing point cloud, and, in subsequent iterative steps, determining temporal position clouds and comparing the position clouds with the reference model using the algorithms. Position information of the target object is calculated, wherein the reference model is continuously adapted to the changes in the point clouds.

For relative navigation between spacecraft by means of a 3D LIDAR system, for example a LIDAR sensor, the detection and autonomous tracking of a target object ("target") is essential. The LIDAR sensor must be able to identify a target object, for example from a distance of several kilometers, and track its position. For scenarios with non-cooperative targets, such as servicing or deorbit missions, for example, distinctive identification elements, such as retroreflectors, are not available. The LIDAR sensor therefore generates point clouds, which have to be analyzed with respect to the relative position with the aid of a suitable method. Simple averaging has been shown to potentially be very inaccurate. Due to the presence of a wide range of materials in space flight with widely varying reflectivities and emission characteristics, sweeping over a target object, for example a geostationary satellite, with laser light within the framework of a servicing mission and analyzing the reflected radiation ("scan") can result in an extremely unevenly distributed point cloud. Averaging can thus lead to severe fluctuations. In theory, the magnitude of the error can reach the dimension of the target object and can, at close range, reach a point at which it is no longer tolerated by the superordinate so-called GNC system (system for the guidance, navigation and control of a spacecraft comprising the LIDAR sensor, Guidance, Navigation & Control, GNC). In the case of a scan across a geostationary satellite with a wingspan of 50 m, for example, the worst case could thus be an error of up to 25 m.
Already starting in the mid-1980s, the mathematical basis for modern pose estimation algorithms was created. These algorithms are able to determine the relative position and location of a target object from 3D point clouds. Due to the noise characteristics of a 3D LIDAR system, however, they can be used only for small distances, for example less than 50 m.
The use of LIDAR sensors for high-resolution generation of 3D point clouds is a standard method for terrestrial applications, for example for mapping, geography, archaeology, surveying. In the space sector, LIDAR sensors are used for position and distance measurement, for example for position control for approach and docking operations of supply spacecraft to the international space station. Already known, far-range LIDAR tracking algorithms are based on the detection of distinctive identification elements, such as retroreflectors, for example. These elements can be uniquely identified on the basis of their high back-reflected amplitudes. If the constellation of reflectors on the target is known, relative position information can be derived even from a distance of several kilometers. This principle cannot be used for scenarios involving non-cooperative target objects, i.e. target objects without appropriate identification elements.
For docking processes from close proximity, the position of the target object can be determined using so-called Iterative Closest Point Algorithms which adapt a mathematical reference model to the 3D point cloud, acquired by the LIDAR sensor in the course of continuously performed scans, by means of an iterative adaptation method. The mentioned algorithms are known, for example, from "Closed-Form Solution of Absolute Orientation Using Unit Quaternions", Berthold K. P. Horn in Vol. 4, No. 4/April 1987/J. Opt. Soc. Am., pages 629-642. This reference discloses algorithms, with which analytical solutions for the translation and rotation between two point clouds are determined on the basis of a simple eigenvalue calculation or singular value decomposition. To do this, however, a correspondence between the scanned points and the reference model has to first be established. The reference model is derived from a CAD model of the target object and, depending on the adaptation method, is parameterized in the form of simple points or as surface elements. Depending on the calculation specification, the corresponding points are determined via a minimization of the point-to-point distance, for example, or via a normal projection onto the reference surfaces. This is followed by the calculation of the translation and rotation. This process is iterated until a, for example square, quality function value falls below a threshold value. With each subsequent iteration, the algorithm converges more and more toward the correct solution, because the adaptation is continuously being improved. The application of this method is limited by the noise behavior of the LIDAR sensor, however, and it can be used reliably only up to a distance of approximately 50 m from the target object.

Method for detecting and autonomously tracking a target object using a LIDAR sensor


Apparatuses, systems, and methods are disclosed for emissions control. An emissions monitor module measures at least one pollutant level for an exhaust gas flow produced by a combustion source and treated by a pollution control device. The at least one pollutant level may be controllable based on at least one combustion source operating parameter and at least one pollution control device operating parameter. A control module controls the at least one combustion source operating parameter and the at least one pollution control device operating parameter based on the at least one measured pollutant level.

Combustion sources such as gas turbines, internal combustion engines, boilers, and the like are used to produce power and/or heat. A combustion source may be subject to one or more emissions limits for pollutants such as carbon monoxide (CO), combined nitric oxide (NO) and nitrogen dioxide (NO2) (collectively NOX), and the like. Combustion sources may provide various ways to control or limit emissions, using water injection, fuel/air mixture adjustment, flue gas recirculation, or the like. However, certain emission control methods may reduce fuel efficiency or power output, decrease emission of one pollutant while increasing emission of another pollutant, or increase wear on the combustion source. Additionally, emissions limits may be below even the reduced emission levels produced by control of the combustion source. Accordingly, a combustion system may include one or more pollution control devices in addition to a combustion source. Various types of pollution control devices may reduce emissions by removing and/or reacting certain pollutants from an exhaust gas flow.

Control of combustion source with at least one pollution control device


A heavy-duty flat wiper blade assembly has a wiper element and an extruded metallic frame. The frame has a bottom channel with a slot traversing its length in which the wiper element is maintained. The wiper element extends through the slot and outwardly from the bottom channel to make contact with a surface to be wiped. The frame has a closed upper channel that may include a fluid inlet opening for receiving wiper fluid into the channel and a fluid outlet opening for discharging the wiper fluid from the upper channel onto a surface to be wiped.

1. Technical Field
This invention relates generally to heavy-duty flat wiper blade assemblies.
2. Related Art
Heavy-duty flat wiper blade assemblies are known having a straight body mounting a rubber wiper element. In one known construction, the body is extruded from a plastic which is, in turn, reinforced by a metal stiffener to provide sufficient structural rigidity to the body, as shown in U.S. Pat. No. 3,107,384. In another known construction, the body is fabricated from a strip of steel which is bent into a generally U-shaped profile in cross-section and crimped along its length to the rubber wiper element to secure the wiper element. In this case, the flat steel body component is cut to length along with the wiper element prior to folding the flat steel over the wiper element.
Both such constructions are costly to manufacture and are limited in the features and advantages they can offer.
Heavy-duty flat wiper blade assemblies constructed according to the present invention overcome or greatly minimize the foregoing limitations of prior wiper blade assemblies.

Method of manufacturing a flat wiper blade assembly


A closure device for a compartment, in particular a glove compartment, which is able to be closed by a flap, in motor vehicles, wherein the flap is designed to be displaceable by a force in a reversible manner between a released position and a blocked position in the direction of the action of a force, wherein the flap has a pivoting mechanism with a lock, wherein the lock is designed to be movable into the blocked position due to the action of a force and then comes into engagement with the locking element.

It is generally known that closable compartments in a motor vehicle are intended to remain securely closed in specific loading situations. Such loading situations may, for example, occur in flaps of glove compartments in motor vehicles when an air bag is installed in the same mounting part as the glove compartment and the air bag is deployed in the event of a vehicle accident or when an occupant presses the knees against the flap in the event of a crash.
Locks triggered via sensors and actuated by a motor are known and effective but complex and associated with high costs.
A closure device for a compartment which is able to be closed by a flap, in particular a glove compartment, in motor vehicles is disclosed in EP 1449991 A2. Such closure device includes a latch and a lock clip. In the aforementioned publication, the latch and the lock clip are suspended by a holder in the form of a slip clutch which is deformable or displaceable and which causes a deformation or displacement when a release energy limit is exceeded and thus prevents the opening thereof.
A locking unit for the cover of an opening in the interior of vehicles is disclosed in WO 2005/083212 A1. Such locking unit has a housing connected to the cover or to the frame defining the opening to be covered, in which a spring-loaded rocker is pivotably mounted. The rocker cooperates with a spring-loaded locking element which is additionally able to be locked in the closed position thereof and engages behind a locking element arranged on the frame of the opening or the cover to be covered. The locking element consists of two latching elements mounted mirror-symmetrically within a common pivot axis, wherein the spring acts on at least one latching element. The spring moves the latching elements into a scissors-like open position, and at least one latching element has a stop which, when brought into contact with the locking element, moves the latching elements counter to the action of a spring force into the closed position in which the latching elements grip around the locking element from both sides and in the closed position latches a locking lug arranged on the spring-loaded rocker to one of the latching elements and, for initiating the opening movement via an actuating element, the rocker is able to be moved counter to the action of the spring and moves the locking lug out of the latching position.
It would be desirable to provide a simple closure device which prevents the opening of a flap by the action of a force in the event of a crash, without a complex construction.


A drive train assembly and monitoring system for indicating the operating condition of the drive train assembly includes a drive train assembly having a power distribution device for distributing rotative power within the drive train. A sensor is attached to a portion of the drive train assembly, the sensor being responsive to the vibration of the portion or component of the drive train assembly for generating signals indicative of the sensed vibration. A controller receives the signals from the sensor and generates an indication of the operating condition of the drive train assembly based on the vibration of the portion of the drive train assembly. Preferably the sensor is adapted to detect both the frequency and magnitude of vibration of the drive train assembly and to generate signals indicative of the sensed frequency and magnitude of vibration.

This invention relates in general to vehicle drive train components and in particular to sensing vibration or other operating conditions of various parts of vehicle transmissions and other drive train components.
In most vehicles, a transmission is provided in the drive train between the engine and the driven wheels. As is well known, the transmission includes a plurality of gears which are selectively engaged to provide a plurality of speed reduction gear ratios between the input and the output of the transmission. A plurality of control members, such as clutch collars, contained within the transmission are moved by a driver of the vehicle throughout a plurality of gear ratio positions for selecting the desired speed reduction. As a result, acceleration and deceleration of the vehicle can be achieved in a smooth and efficient manner.
Typical transmission structure includes an input shaft, a countershaft, and a mainshaft. Gears positioned between the input shaft and the countershaft drive the countershaft at a rotation speed proportional to the engine speed. Countershaft gears of different sizes are rigidly mounted on the countershaft for rotation, and these also rotate at speeds proportional to the engine speed. For example, the gears mounted on the countershaft could be forward gears one though five, plus reverse. The countershaft and the countershaft gears will always rotate at the same speed relative to each other since they are all mechanically linked together.
The countershaft gears drive another set of gears, the mainshaft gears, which are complementary to the countershaft gears. The mainshaft gears are mounted coaxially with the mainshaft, but not directly linked to the mainshaft. Since each of the mainshaft gears is rotated by meshing with the teeth of a different sized countershaft gear, each mainshaft gear is rotating at a speed different from every other mainshaft gear, but at a speed proportional to the engine speed. It is the clutch collars which cause the linkage between the rotating mainshaft gears and the mainshaft. Axial movement of one of the clutch collars causes the splines of the clutch collar to link the associated mainshaft gear with the mainshaft, thereby causing a mechanical link all the way from the input shaft to the mainshaft. The mainshaft then rotates at a speed which is proportional to engine speed.
The transmission assembly so far described can be referred to as the main section, and there is frequently provided, downstream or rearwardly of the main section, an auxiliary transmission section which includes two or more speed reduction gear ratios, thereby compounding the gear ratio options of the entire transmission assembly. The eventual output from the transmission assembly is through the output shaft, which is typically connected via a universal joint to the drive shaft.
The rotating parts in the transmission assembly, including the input shaft, countershaft, mainshaft and output shaft are all mounted for rotation on bearings. Lubrication is required for the bearings as well as for the gears themselves with their intermeshing teeth. Typically, the transmission is contained within a transmission case or housing, which facilitates containment of the lubricants. Although the countershaft and mainshaft gears are always rotating, the load or torque on the gears and on the bearings will vary with the gear selected. For example, the load on the rear countershaft bearing will be higher for a lower gear than for a higher gear.
One of the problems with vehicle transmissions is that various parts are subject to wear and eventual failure. A prime example of transmission parts that are subject to failure is any one of the numerous sets of bearings associated with the many rotating parts of a transmission. Often there are subtle changes in the vibration patterns of a vehicle transmission part as it wears out or begins to fail. Therefore it would be helpful to be able to detect changes in vibration patterns.
The changes in vibration patterns are not always perceptible to the vehicle operator prior to the actual failure of the part. It would be advantageous if the vehicle driver were alerted to these subtle changes in vibration and the associated likelihood of failure of a part of the vehicle transmission. Also, even when the vehicle driver perceives a change in the vibration pattern, it is not always possible to determine the exact source of the vibration, or even the general area or zone of the transmission causing the vibration. Therefore it would be advantageous to have a diagnostic tool which would enable the source of vibration to be pinpointed or at least localized to a specific zone or area of the transmission. Any solution to the problem of detecting or diagnosing vibration should be relatively inexpensive, simple to operate and generally maintenance free. Ideally, any transmission vibration monitoring system would make use of existing diagnostic or control equipment and data sources already on board the vehicle.

Vibration sensing and diagnostic system for vehicle drive train components


An operation portion elevates or lowers imaging units of a robot in response to the user's operation of the operation portion, and when the robot is moved from a first work stand to a second work stand which have different heights, a control unit determines whether the difference between the height of the imaging units before the moving of the robot and the height of the second work stand is present in a predetermined range, and when the control unit determines that the difference is not present in the predetermined range, a display unit controls a display device to display information that instructs a user to change the height of the imaging units via the operation portion.

1. Technical Field
The present invention relates to a robot, a robot system, a robot control device and a robot control method.
2. Related Art
A technology disclosed in JP-A-2011-51056 proposes a working robot, in which when the working robot is placed in a work place, and co-exists and cooperates with a human, the working robot can be disposed even though an obstacle is present on a floor in the vicinity of the work place, the safety of an operator can be secured when the working robot is disposed, and a large amount of change in work instruction is not required for high-precision positioning.
There is a robot that includes a camera that captures images of the top of a work stand, and performs work on the work stand based on data of the images captured by the camera. For example, in such a robot, the height of the camera is fixed with respect to the work stand. For this reason, whenever changing the height of the work stand, it is necessary to adjust the height of the robot, and it takes labor and time to adjust the height.

Robot, robot system, robot control device and robot control method


A method of workforce optimization includes acquiring video data. The video data is obtained from a plurality of video cameras in a facility comprising a plurality of departments. A customer load for each of the plurality of departments is identified. A location of each of a plurality of employees in the facility is identified. A customer-to-employee ratio is determined for each department. The determined customer-to-employee ratio for each department is provided to a computing device. At least one employee deployment notification is provided from the computing device to another computing device.

In a retail store setting, customer interactions with customer service employees can improve the customer experience and facilitate increased sales. Current methods of customer service employee deployment within a retail facility is generally based upon management experience and generalized impressions of customer flow and customer-employee interactions within various sales departments. Therefore, these determinations are highly subjective which can result in great inefficiencies in the deployment and management of customer service employees across sales departments in a retail facility.

System and method of workforce optimization


An adaptive antenna array employs selective polarization nulling and spatial nulling to receive desired signals in the presence of jamming signals. The desired signals have the same circular polarization, and the array includes at least one antenna element having an opposite circular polarization to null jamming signals having an opposite circular polarization. A gain pattern for the array is selected to minimize signals having the same circular, or linear, polarization. The gain pattern is computed based on jamming signals received when no desired signals are transmitted, or selected based on measured desired signals.

Conventional signal reception systems are degraded in signal-to-noise ratio performance because of the presence of undesired signals that enter the system by the main lobe or the side lobes of an antenna. Such signals may consist of hostile, deliberate interference or non-hostile unintentional interference. Natural noise sources almost always exist and in certain systems, received signals are reflected from xe2x80x9cclutterxe2x80x9d in the antenna field. As communication traffic by wireless and other media increases substantially, poor siting conditions and multipath beam effects add to a worsening interference environment. Newer, unlicensed radio stations using xe2x80x9cweak signalxe2x80x9d communication are particularly vulnerable to interference from other stations operating on the same frequencies. Interference with desired signals by signals on the same or very near frequency is often referred to as xe2x80x9cjammingxe2x80x9d even in cases which are non-deliberate. To insure the quality of service expectations of users of such systems, it is important that they be able to transmit and receive traffic without interference from jamming signals.
In the book by Robert A. Monzingo and Thomas W. Miller, entitled Introduction to Adaptive Arrays, John Wiley and Sons, New York, 1980, the authors describe adaptive antenna arrays that have been used as a solution to problems of signal detection in severe interference environments.
U.S. Pat. No. 5,724,666 was issued on Mar. 3, 1998 to Paul W. Dent and is entitled Polarization Diversity Phase Array Cellular Base Station and Associated Methods. The Patent describes a base station which includes a first and second antenna array receiving first and second rotational polarizations and a polarization diversity receiver connected to the first and second arrays.
In his U.S. Pat. No. 5,691,727, Adaptive Polarization Diversity System, issued on Nov. 25, 1997, Baruch Cyzs describes an adaptive polarization diversity system for radio link communication. Hans Mahler was issued U.S. Pat. No. 5,963,874 for a Radio Station Arranged for Space Diversity and Polarization Diversity Reception, Oct. 5, 1999. The patent describes antennas arranged for reception of signals with different polarization directions for achieving polarization diversity reception.
U.S. Pat. No. 4,298,873 is entitled Adaptive Steerable Null Antenna Processor and was issued on Nov. 3, 1981 to Eugene L. Roberts. The invention described in this Patent is an adaptive array system which steers a plurality of antennas to direct a null toward an undesirable source of interference, in order to reduce noise and enhance detection of signals.
Eugene J. Bruckert, et al. were granted U.S. Pat. No. 4,584,713: Signal Quality Steered Diversity on Apr. 22, 1986. The Patent discloses a circuit and technique for directing an adaptive antenna system. U.S. Pat. No. 5,649,287, issued Jul. 15, 1997, to Ulf Gxc3x6ran Forssxc3xa9n, et al., entitled: Orthogonalizing Methods for Antenna Pattern Nullfilling, discloses a method of broadcasting in a cellular communication system where common information creates orthogonal signals.
Eugene L. Roberts was granted U.S. Pat. No. 5,107,273 entitled Adaptive Steerable Null Antenna Processor With Null Indicator in April, 1992. The disclosure describes an adaptive array system which steers a plurality of antennas to direct a null toward an undesired source of interference to reduce noise and enhance detection of desired signals.
U.S. Pat. No. 4,670,885 issued to Steen A. Parl, et al. and entitled Spread Spectrum Adaptive Antenna Interference Canceller, describes an adaptive power equalizer circuit for use in a spread spectrum receiver system.
A Sidelobe Canceller with Adaptive Antenna Subarraying Using a Weighted Butler Matrix is the subject of U.S. Pat. No. 4,596,986 which was issued to Grealie A. Andrews, et al. on Jun. 24, 1986. An apparatus for nulling signals from unwanted interference sources is disclosed.
U.S. Pat. No. 4,152,702 is entitled Adaptive Antenna Lobing on Spread Spectrum Signals at Negative Signal-to-Noise Ratio. It discloses a communications system including a multiple antenna array with null steering apparatus.
What is currently needed is a method and system for discriminating against unwanted, interfering signals from a fixed source, while maintaining the antenna gain in respect of receiving desired signals. The invention provides a solution to this and other problems.
In one aspect of the present invention, a method is provided for receiving desired signals having a desired circular polarization in the presence of interfering signals, comprising receiving the desired signals and interfering signals in a first antenna having the desired circular polarization to form a first output signal, receiving the interfering signals in a second antenna having an opposite circular polarization to the desired circular polarization to form a second output signal, and combining the first and second output signals to minimize the interfering signals.
In a further aspect of the invention, the output signals are weighted prior to linearly combining the output signals to minimize the interfering signals. Weighting the output signals may include selecting a first gain for the first antenna and a second gain for the second antenna, deriving complex weights for each antenna corresponding to the selected first gain and second gain, applying the complex weights to the respective output signals, and linearly combining the weighted output signals to minimize the interfering signals.
In another aspect of the invention, receiving the interfering signals may comprise receiving the interfering signals in the first and second antennas over a period of time during which no desired signals are transmitted, and selecting the first and second gains comprises selecting the first and second gains to minimize one or more of the received interfering signals. Receiving the desired signals may alternatively comprise measuring a performance value for the desired signals, and selecting the first gain comprises selecting the first gain to maximize the performance value for one or more of the received desired signals.


The present invention relates i. a. to an immunogenic composition comprising: a) one or more antigens of avibacterium paragallinarum and one or more antigens of avian encephalomyelitis virus and one or more antigens of fowl pox virus; and b) a pharmaceutically acceptable carrier. Furthermore, the present invention relates to methods for immunizing a subject comprising administering to such subject the immunogenic composition of the present invention. Moreover, the present invention relates to methods of treating or preventing clinical signs caused by avibacterium paragallinarum, avian encephalomyelitis virus and fowl pox virus in a subject of need, the method comprising administering to the subject a therapeutically effective amount of an immunogenic composition according to the present invention.

Infectious coryza (IC) is an infectious upper respiratory disease affecting poultry. This disease is caused by avibacterium paragallinarum, which was previously known as Haemophilus paragallinarum. Some clinical signs that are commonly seen in IC are rhinitis, facial swelling or edema, anorexia, retarded growth, decreased egg production and some mortality. The disease is very important in the chicken farm industry.
The avian encephalomyelitis virus is a single-stranded RNA (ssRNA) virus belonging to the Picornaviridae family. Infection may cause neurological signs in poultry (such as ataxia, rapid tremor of the head and neck), weakness, weight loss, increased mortality and decreased egg production.
The Fowl pox virus (FPV), a DNA virus of the genus Avipoxvirus of the family Poxviridae, infects poultry. Fowl Pox virus diseases have significant economic impact worldwide, with losses resulting from a drop in egg production in layers, reduced growth rates in broilers, blindness, and in some cases death.
However, what is needed are efficacious combination vaccines which provide protection against multiple pathogens. Such combination vaccines are very desirable in order to minimize the number of vaccination handlings required to confer protection against multiple pathogens (animal welfare), to lower administration costs, and to increase acceptance and coverage rates.
However, the problem of interference complicates the development of multi-component vaccines. Specifically, interference refers to the observation that administering multiple antigens often results in a diminished response to certain antigens relative to the immune response observed when such antigens are administered individually. Interference may occur in general when administering multiple antigens. However, in particular, the phenomenon of interference is problematic when combining killed vaccines together with live vaccines since the live vaccine component may be affected by the killed vaccine component (which may comprise a pharmaceutically acceptable carrier).
Thus, there is a need for efficacious combination vaccines which provide protection against multiple pathogens.