A spread spectrum communication system includes a transmitter having: a data generator for generating a data signal; a pn generator for generating a first pn signal in accordance with a pn code clock; a modulator for modulating the pn code clock by synchronizing the data signal with a multiple N of one period of the first pn signal; a first part for detecting one period of the first pn signal; a second part for outputting a clock to the data generator in accordance with a converted period equal to a multiple N of the detected period; and an output part for transmitting a signal at an output of the pn generator, and a receiver which receives the transmitted signal, the receiver having: a second pn generator for generating a second pn signal in synchronism with the transmitted signal; a demodulator for demodulating the transmitted signal with the second pn signal; a third part for detecting one period of the second pn signal; a fourth part for outputting a timing signal in accordance with a converted period equal to a multiple N of the detected period; and a discriminator for detecting each bit of a demodulated signal in synchronism with the timing signal.

The present invention generally relates to a spread spectrum communication system, and more particularly to a spread spectrum communication system in which spread spectrum modulation is used to modulate a clock used to generate a pseudo noise code sequence. The spread spectrum communication system is applicable to wireless communications including indoor radio communications and mobile communications.
There have been proposed some types of spread spectrum (SS) communication systems as a data transmission system enabling increased immunity to noise, increased resistance to interference and security of transmitted information. Among the SS communication systems, there are a direct sequence (DS/SS) communication system and a frequency hopping (FH/SS) communication system. In the DS/SS communication, a signal modulated with information is multiplied with a pseudo noise (pn) code sequence which is generated by a pn code generator. In the FH/SS communication, a carrier frequency of the modulated signal is shifted in accordance with a prescribed pattern.
Among the SS communication systems, there is also another type of SS communication system which is more simple and more feasible than the above mentioned systems. This SS communication system utilizes clock rate modulation (CRM) for data transmission, which is disclosed in "Spread Spectrum Systems" by R. C. Dixon, John Wiley & Sons, 1976, pp. 116-117. In this CRM/SS communication, a clock input to the pn code generator is frequency-modulated in accordance with a digital data signal.
When a digital signal produced through the CRM/SS is transmitted at a transmitter of the CRM/SS system mentioned above, a pn code clock used to generate the pn code sequence is subjected to frequency shift keying (FSK) to modulate the frequency of the pn code clock with the data signal. When the transmitted signal is received at a receiver, a delay locked loop (DLL) of the receiver performs a pn signal synchronization and feedback control so as to generate a second pn code sequence synchronuously with the transmitted signal. Then, at the receiver, a demodulated signal is produced from a small control signal of a voltage controlled oscillator (OSC) of the DLL. Because this control signal is very small, amplification of the control signal and noise reduction therefrom are performed at a waveform shaper of the receiver, and a bit timing of the demodulation is taken from the amplified signal by using a phase locked loop (PLL) or the like so that data corresponding to the digital data signal is reproduced from the transmitted signal.
However, in the above mentioned CRM/SS system, it is necessary to use an expensive, somewhat complicated PLL circuit in order to accomplish the bit timing synchronization. Also, there is a problem in that fluctuations of the phase or level of the demodulated signal may occur due to noises, power changes and temperature changes at the waveform shaper and the DLL, thereby producing errors of the demodulation. Therefore, when the above mentioned CRM/SS system is used, it is difficult to accurately demodulate the transmitted signal so as to reproduce the corresponding digital data.


Methods, systems, and media for presenting a customized user interface based on user actions are provided. In some implementations, a method for presenting a customized user interface based on user actions is provided, the method comprising: receiving a request for media content from an application comprising a user interface for presenting media content that includes a plurality of user interface elements that each initiate sharing on a different platform; determining that the request was sent from the user device as a result of the user selecting a link on a first platform; and causing the application to present an additional user interface element that initiates sharing of the media content item on the first platform in addition to the plurality of user interface elements in response to determining that the request was transmitted as a result of selection of the link on the first platform.

When viewing or otherwise consuming media content, such as videos, articles, images, etc., from a site that publishes the content, users are often encouraged to share that media content with others. For example, a user can share media content with other users that are connected to the user through a social networking service, or with other members of an online community which the user participates in. Sharing is often facilitated by providing a button or other user interface element in a user interface for consuming content that initiates sharing to a specific service or community. However, the user interface elements that are presented to the user and the sites which those user interface elements correspond to are often fixed. That is, the sites that are available to the user are often selected based on the overall popularity of the sites, or based on which sites an administrator of the site publishing the media content finds the most appealing.
Accordingly, it is desirable to provide methods, systems, and media for presenting a customized user interface based on user actions.


A game device having a three-dimensional playing surface with strategically positioned points and a method of playing a game on the game device which has a three-dimensional playing surface with strategically positioned points whereby the game is played by at least two players alternately claiming the points.

The general trend in games today has gravitated toward computerized video games that are mainly single-player games where the player memorizes the steps of the game that are required to achieve the objective. The player then continuously repeats the steps to improve his/her time.
With the advent of video games came a decline in games between two or more players competing face-to-face against each other where the object is to defeat the opponent by outwitting him/her. Traditionally this was an important feature of games and such games between two people were a major means of entertainment and social interaction.
Many games today, however, are played by a single player with no other person participating or watching. At the end of the game the player receives a "score" for the points he/she has accumulated during the game. An opponent or the original player then tries to match or beat the original player's score. There is no player-to-player real-time opposition.
Some existing games such as the cubic game board (U.S. Pat. No. 4,129,303) have attempted to enhance the popularity of the game board concept by making the game three-dimensional. The playing surface, however, continues to be planar even though multiple planes are incorporated into the game device.
Another game apparatus (U.S. Pat. No. 3,046,016) transforms the traditional tic-tac-toe game into three-dimensions. The apparatus is designed strictly for this one game and requires points or "playing stations" at all intersections of the rings and additional intermittent "playing stations" between each adjacent pair of intersections. By including intermittent points which only have two adjacent points, the game complexity is diminished.
Another adaptation of the tic-tac-toe concept is a game apparatus (U.K. Patent No. 1,344,259) by Frank Fox. It is a three-dimensional representation of the British game of noughts and crosses which has at least two 3×3 arrays of contiguous areas with at least one area common to two such arrays. Each array has nine compartments (three different shapes: square, rectangular and triangular) formed by the 3×3 game board where two players alternately put crosses and circles in the compartments. The objective is to be the first player to get three crosses or three circles in contiguous compartments. The game is also called tic-tac-toe, tit-tat-toe, ticktacktoe and ticktacktoo. This game, as the others discussed above, does not have desired characteristics such as visualization of spatial relations, increased ability of players to visualize three-dimensional images and increased complexity. It also lacks a means of identifying the winning alignment on the sphere and is limited to playing patterns which are composed of 3×3 grids.


A display driver is provided which is suitable for driving dynamically a cholesteric liquid crystal display panel of a passive matrix drive type. The driver comprises a shift register for shifting a row data or column data inputted to the driver, a data latch circuit for latching the row data or column data from the shift register, and a drive voltage select/output circuit for selecting at least one of a plurality of voltage supplies and outputting a row drive voltage or column drive voltage to form an alternated drive voltage which activates picture elements of the liquid crystal panel.

As current typical LCD, STN (super twisted nematic) LCD and TFT (thin film transistor) LCD have existed. While STNLCD has a relatively low cost, the number of drive lines thereof is at most 500. The TFTLCD is also expensive to manufacture. Therefore, a problem is caused in that a large size display device can not be fabricated with these LDCs. On the other hand, the number of drive lines of the cholesteric LCD is not limited, because rewrite and refresh are carried out only when display is to be changed, and the display is held due to the memory characteristic of the LCD once it has been written. The cholesteric LCD, however has a problem such that rewriting requires excessive time.
The current cholesteric LCD necessitates more than 10 seconds to rewrite 1000 lines in the display panel. On the other hand, a page size application such as an electronic book requires less than one second for rewriting one page so as to match the time required to turn over one page of a book manually.
To this requirement, U.S. Pat. No. 5,748,277 "Dynamic drive method and Apparatus for a bistable liquid crystal display" discloses a method for rewriting a passive matrix LCD within one second, the display using cholesteric liquid crystal. The method intends to increase the rewriting speed of the display panel by utilizing a dynamic drive method and a pipeline scheme, the dynamic drive method utilizing a series of stages to control the transition of liquid crystal textures. Such a high speed rewriting scheme allows a display panel using cholesteric liquid crystal material to be used in a passive matrix drive method (i.e. a simple matrix drive method) having an addressing speed more than 1000 lines/second.
FIG. 1 shows an electronic book 10 disclosed in the U.S. Pat. No. 5,748,277. The electronic book comprises a display screen 12, a page selection switch 14, and a memory card or floppy disk 16 which can carry the information to be viewed.
FIG. 2 shows the structure of a liquid crystal panel using a passive matrix drive method disclosed in the above-described U.S. Patent. The structure thereof comprises glass plates 20 and 22, row electrodes 24, and column electrodes 26. Cholesteric liquid crystal is sandwiched between two glass substrates 20 and 22.
Picture elements are formed between opposite row and column electrodes which selectively activate the picture elements. Such activation causes the liquid crystal to exhibit various liquid crystal textures in response to different conditions of electrical fields applied thereto. The liquid crystal assumes the homeotropic texture at a higher voltage. The twisted planar texture and focal conic texture may be stable in the absence of an electric field. The transient twisted planar texture occurs when an applied electric field holding the liquid crystal in the homeotropic texture is suddenly reduced or removed. This state is transient to either the twisted planar or focal conic texture. The liquid crystal of twisted planar state reflects light in the visible spectrum depending on the pitch length of the material to allow the display of white color. The homeotropic state and focal conic state show a weak scattering condition or a transparent condition. If the back side of a picture element is colored in black, the picture element is displayed in black for the homeotropic state and focal conic state. Also, a full-color display may be implemented by stacking display layers, each of these layers reflecting red, green, or blue light. Gradation display may be realized in a cholesteric liquid crystal display panel due to a gray scale characteristic obtained by selecting a voltage and/or time duration the voltage is applied.
In accordance with a dynamic drive method, the cholesteric liquid crystal picture elements are activated in a series of steps to control their transitions during the refresh or update of the display screen. These steps include three active stages and one non-active stage, three active stages consisting of a preparation stage, selection stage, and evolution stage. The non-active stage exists before the preparation stage and behind the evolution stage, respectively. The non-active stage before the preparation stage does not transform the liquid crystal texture. The dynamic drive method using three active stages is referred to as a three-stage scheme.
The preparation stage transforms the liquid crystal to a homeotropic state. The selection stage selects either the maintaining of a homeotropic state or the transformation to a transient twisted planar state. The evolution stage evolves the liquid crystal selected so as to be transformed to the transient twisted planar state during the selection step to a focal conic state, and holds the homeotropic state of the liquid crystal selected to remain in the homeotropic state during selection stage. The final non-active stage maintains the focal conic state as it is, and transforms the homeotropic state to a stable twisted planar state.
A four-stage scheme may be implemented by adding a pre-selection stage behind the preparation stage, the pre-selection stage allowing the liquid crystal to relax to a transient twisted planar state. Adding the pre-selection stage may increase the speed for activating the picture elements.
In the drive method using a series of stages, the determination of a final liquid crystal texture of a picture element depends upon the voltage applied to the electrodes during the selection stage, with the applied voltages during other stages being the same. All of the picture elements, therefore, require the same non-active voltage, the same preparation voltage, and the same evolution voltage, so that the time may be shared during the non-active stage, preparation stage, and evolution stage by employing a pipeline argorithm. Accordingly, a plurality of electrodes may be addressed at the same time by a non-active voltage, preparation voltage, and evolution voltage.
In the above-described U.S. Patent, while applied voltages to the row electrodes and column electrodes have a vibrating bipolar square waveform, respectively, it is known that a vibrating unipolar square waveform may be used by selecting the magnitude of applied voltage and the time duration of applied voltage. Using a unipolar square waveform results in the decrease of a swing width of voltage applied to a display driver and the cost reduction of the driver. Whether the applied voltage is bipolar voltage or unipolar voltage, the voltage applied to a picture element, i.e. the voltage difference between the voltages applied to a row electrode and column electrode is a bipolar voltage. Such bipolar voltage applied to a picture element is referred to as an alternating voltage hereinafter. The reason why an alternating voltage is used is to decrease the effect of impurities dissolved in liquid crystal material and expand the life time of the liquid crystal material.

Cholesteric liquid crystal display device and display driver


The present invention relates to an apparatus for processing fluid for separating any component mixed or dissolved in a fluid and a method for producing a separated fluid. The present invention provides an apparatus for processing fluid which does not require any complicated manifolds in such a way that a plurality of cylindrical vessels each having a plurality of flow ports on the outer peripheral surface thereof at positions near both ends thereof, respectively, and incorporating therein a series of separating elements are arranged substantially parallel to one another with the flow ports of the adjoining cylindrical vessels held connected face-to-face with each other. Further, a method for producing separated fluid at a low cost can be provided by using the above-described apparatus for processing fluid.

Conventionally, a fluid processing apparatus for seawater desalination, etc. has been constructed such that as shown in FIG. 7, a plurality of unitary modules 10 each comprising a cylindrical vessel 1 incorporating therein a plurality of separating elements 2 each comprised of a piece of reverse osmosis membrane (permeable membrane). The separating element 2 is formed by spirally winding a piece of permeable membrane around a central pipe 11 through a spacer. Thus, when seawater is supplied under pressure from a supply pipe 12 into the unitary module 10, the seawater is desalted through the separating element 2 in each stage and the low-pressure fresh water after desalination is discharged from a discharge pipe 13 through the central pipe 11 while high-pressure concentrated water is discharged from a discharge pipe 14.
That is, the cylindrical vessel is divided into a high-pressure space where high-pressure seawater and concentrated water are present and a low-pressure space where the low-pressure fresh water is present, through the permeable membrane of each of the separating elements 2.
However, the conventional fluid processing apparatus has generally been constructed such that as shown in FIG. 8, a plurality of unitary modules 10 are fixedly arranged horizontally on frames 20 and supply pipes 12 and discharge pipes 13, 14 which respectively extend from both side ends of the unitary modules 10 are collected into a manifold 22 and manifolds 23, 24.
However, there has arisen the problem that since the installation of the frames 20 and the piping operation for connecting the manifolds 22, 23 and 24 at the working site are extremely complicated, the cost required for these operations becomes higher than the cost of the apparatus itself. Further, there has also arisen the problem that if the manifolds 22, 23 and 24 are attached to both ends of the unitary modules 10, the manifolds are required to be dismantled or assembled every time when each of the separating elements 2 is periodically exchanged resulting in making the maintenance operation extremely inefficient.
Moreover, where separated fluid is produced by the above-described processing apparatus, it has been usual that since high-pressure seawater or concentrated water flows through the manifolds 22 and 24, the pressure loss of these manifolds becomes significant causing the load of the related pump or the like to be quite heavy. Consequently, the availability factor of the apparatus as a whole is low and as a result, the method of producing the separated fluid by using such apparatus has been inefficient.

Apparatus for processing fluid and method for producing separated fluid


A pad capable of enhancing the fitting performance to a wearer. An absorber includes a front body portion, a back body portion, and a narrowing portion, whose width dimension is reduced, provided between the front body portion and the back body portion. A first groove extending in the front-back direction is formed in a central portion in the width direction of the absorber. A third groove extending in the width direction is formed in a central portion in the front-back direction of the narrowing portion. A second groove extending in the width direction is formed in a front side portion in the front-back direction of the narrowing portion. A fourth groove extending in the width direction is formed in a back side portion in the front-back direction of the narrowing portion.

Conventionally, it is proposed that a plurality of grooves extending in the front-back direction is formed with a predetermined interval in the width direction of an absorber, notch portions each extending toward a back side in the front-back direction are formed toward a central portion in the width direction from both side portions of a front side portion of the absorber, and notch portions each extending toward the front side in the front-back direction are formed toward a central portion in the width direction from both side portions of a back side portion of the absorber. (Patent Literature 1)
Further, it is proposed that an absorber is formed with an outer absorber and an inner absorber having a narrower width in the width direction than the outer absorber, and a plurality of grooves extending in the width direction with a predetermined interval in the front-back direction is formed to the inner side absorber. (Patent Literature 2)


Provided is a low iron loss high strength non-oriented electromagnetic steel sheet and a method for manufacturing the same. The method comprises hot-rolling a slab comprising 0.005 weight % or less of C, 4.0 weight % or less of Si, 0.1 weight % or less of P, 0.03 weight % or less of S, 0.1 to 2.0 weight % of Mn, 0.3 to 2.0 weight % of Al, 0.003 weight % or less of N, 0.005 weight % or less of Ti, the remainder being Fe and unavoidable impurities, cold-rolling the slab, and finally annealing the slab such that the fractional area of the non-recrystallization tissue at the cross sectional surface of the steel sheet is 50% or lower (not including 0%).

In recent years, as interest in the efficient use of energy has increased, there have been efforts to increase the efficiency of motors which are used in electrical systems, including large-capacity electric generators and environmentally friendly vehicles such as hybrid electric vehicles (HEVs) or electric vehicles (EVs). For example, there has been an effort to modulate the frequency of BLDC motors to obtain a higher rotating speed than that of general motors.
Particularly, in the case of motors which are used in the driving unit of hybrid vehicles or electric vehicles, it is required to obtain a large output with a limited size, and a rotating speed of 10,000 rpm or more is required. In this case, a centrifugal force which is applied to the rotator of the motor is proportional to the square of the rotating speed, and thus exceeds the yield strength of general electrical steel sheets during high-speed rotation and threatens the stability and durability of the motors. Thus, the rotator of high-speed rotating devices requires a high-strength material.
In addition, in the case of materials that are used for the rotator of motors, an eddy current loss caused by high frequency is required to be reduced in addition to increasing the strength. When a high-strength carbon steel or integral rotator is made in order to increase the strength, the eddy current loss of the rotator increases to reduce the overall efficiency of the motor.
Thus, there has been a need for studies on the electrical steel sheet manufacturing technology capable of satisfying both high-strength properties and low core loss properties. For example, a technology of increasing strength by forming structures other than ferrite in steel, a technology of increasing alloying elements such as Nb, V and C to steel, and a technology of satisfying both core loss properties and strength properties by controlling the grain size to 20 μm or more before cold rolling or additional processing have been proposed.
However, the technology of forming structures other than ferrite has shortcomings in that, because nonmagnetic abnormal structures such as pearlite, martensite or austenite are present in the steel, the core loss and magnetic flux density of the steel are rapidly deteriorated, and the efficiency of a motor employing the steel decreases rapidly. In addition, the technology of adding alloying elements such as Nb, V or Cu has shortcomings in that the magnetic properties of the steel are rapidly deteriorated, and limitations occur in some applications. Further, the effect of the technology of controlling the size of cold-rolled structures to 20 μm or more appears in processes, which are performed on conventional electrical steel sheets, and intermediate products. The results of experiments conducted by the present inventors showed that the effect of the technology was insignificant on high-strength electrical steel sheets having a large amount of non-recrystallized structures and that it is difficult to improve the magnetic properties of the steel, compared to those of a material having a grain size of less than 20 μm.

Low iron loss high strength non-oriented electromagnetic steel sheet and method for manufacturing same


The present invention produces halftone dots which shows smaller fluctuations in size and shape irrespective of variation of the positional relation between the address of screen pattern data and the recording pixels. Displacement F1 through F4 are computed at vertices of a halftone dot region VP1 through VP4. Each of the vertices is shifted to a lattice point of the scanning coordinate systems, and the X-Y coordinates of each lattice point in the scanning coordinate systems are corrected accordingly. The displacement of an arbitrary lattice point A is interpolated from the displacement F1 through F4 on the basis of the distance between each vertex and the lattice point A. As a result, the positional relation between the address of the screen pattern and the position of the recording pixels is maintained constant in the vicinity of the vertices, and this reduces the fluctuations in size and shape of the halftone dots. The center of each halftone dot region can be shifted to a lattice point in the scanning coordinate systems.

1. Field of the Invention
The present invention relates to a method of and an apparatus for generating halftone dots to reproduce a halftone image.
2. Description of the Related Art
In printing process, halftone images of four primary colors, that is, yellow (Y), magenta (m), cyan (C), and black (K), are printed with respective inks on a printing sheet to produce a color print. Each halftone image includes a large number of halftone dots which represent density variation in the image, and each halftone dot includes a number of painted pixels. The larger the number of painted pixels in a halftone dot, the larger the halftone dot; the larger the halftone dots, the darker the halftone image becomes.
The halftone image on the film is generally produced with a scanner which includes a reading unit for reading an original color image to capture color separation image signals, and a recording unit for exposing a photosensitive film to reproduce halftone images on the film. The color separation image signals represent density variations of the respective four primary colors in the original color image. The recording unit compares each image signal with specific screen pattern data, which represent threshold values, to generate an exposure control signal for each recording pixel as a result of the comparison, and exposes a halftone image on a photosensitive film while ON-OFF controlling a light beam in response to the exposure control signal.
FIG. 1 shows an example of screen pattern data for one halftone dot region, which is the maximum region of one halftone dot. In FIG. 1, one halftone dot region is made of 32.times.32 pixels, to each of which a threshold value ranging from 0 through 255 is assigned. The threshold value for each pixel is compared with the level of the image signal, and those pixels that have the threshold values no more than the level of the image signal are to be exposed. For example, when the level of the image signal is 64 over the 32.times.32 pixels, the shaded areas at the corners of the halftone dot region are exposed to make halftone dots. If the level of the image signal is 255, all pixels in the halftone dot region are exposed.
When superimposed to make a color print, the four halftone images might cause a so-called "moire". orientation angles, or screen angles, of the four halftone images are generally set at different values to prevent the moire. FIGS. 2A through 2D show halftone dot arrangements where the screen angles .theta. are set at 0 degrees, 15 degrees, 45 degrees, and 75 degrees, respectively.
The production of the four dot arrangements with different screen angles .theta. can be executed by two typical methods, that is, Rational Tangent Method and Irrational Tangent Method. Tangent of each screen angle .theta. (tan .theta.) is set at a rational number in the Rational Tangent Method, and it is set at an irrational number in the Irrational Tangent Method.
FIG. 3 is a conceptive view illustrating an arrangement of screen pattern data for the screen angle .theta. of about fifteen degrees according to the Rational Tangent method. FIG. 3 includes four halftone dot regions. U denotes a primary scanning direction and V denotes a secondary scanning direction. In the Rational Tangent Method, screen pattern data is prepared such that it is addressed along each primary scanning line. Even if a scanning line SL runs through three halftone dot regions HD1, HD2, and HD3, the screen pattern data is successively read out along the scanning line SL. The Rational Tangent Method therefore requires four sets of screen pattern data for the four screen angles, respectively, so that the screen pattern data can be addressed along the primary scanning line at each screen angle.
It is sometimes required to change a screen ruling, or the number of halftone dots per inch, of the halftone image. The screen ruling is changed by adjusting a diameter and an interval of beam spots of a light beam to be focused on the photosensitive film in the Rational Tangent Method. This, however, requires a conglicated shuttle mechanism moving in the secondary scanning direction and an expensive optical system which can change the diameter and interval of the beam spots.
The Irrational Tangent Method, on the other hand, can change the screen ruling relatively easily. The Irrational Tangent Method needs only one set of screen pattern data which are assigned to pixels in one halftone dot region as shown in FIG. 1, and reads out the screen pattern data as a function of the screen angle .theta.. FIG. 4 illustrates a method of reading out screen pattern data in the Irrational Tangent Method. X-Y coordinates indicate an address of a screen pattern memory, or a memory for storing screen pattern data, and U and V denote primary and secondary scanning directions, respectively. The U-V coordinates of an arbitrary point A are transformed into the X-Y coordinates as follows: EQU X=U*cos .theta.+V*sin .theta. (1a) EQU Y=-U*sin .theta.+V*cos .theta. (1b)
where "*" denotes multiplication. When assuming U=m*p and V=n*p, Equations (1a) and (1b) are rewritten as follows: EQU X=m*p*cos .theta.+n*p*sin .theta. (2a) EQU Y=-m*p*sin .theta.+n*p*cos .theta. (2b)
where "m" and "n" are integers and "p" denotes a pitch of recording pixels, or a side length of a recording pixel.
Since the secondary scanning coordinate v is constant on each primary scanning line, the integer "n" is also constant on each scanning line. Therefore, only the first terms of Equations (2a) and (2b) change in reading out the screen pattern data along each scanning line. According to Equations (2a) and (2b), one-pixel progress in the primary scanning direction increases the X coordinate by p*cos .theta. and the Y coordinate by p*sin .theta.. Accordingly, the screen pattern data for only one halftone dot region shown in FIG. 1 is sufficient to produce halftone dot arrangements at any screen angle in the Irrational Tangent Method. Furthermore, the screen ruling is also changeable by adjusting the pixel pitch p.
FIG. 5 shows the relationship between the arrangement of recording pixels and the address on the screen pattern memory in the Irrational Tangent Method. Recording pixels RP shown as circles are disposed along scanning lines SL1 and SL2. Addresses of the screen pattern data are positioned at the centers of the grid shown in FIG. 5. The coordinate axes of the X-Y coordinate systems run through the center of the address (0, 0) accordingly.
The scanning coordinates (U, V) for each recording pixel are transformed into the address coordinates (X, Y) according to the above Equations (2a) and (2b) . In the example of FIG. 5, screen pattern data stored at the address (0, 0) , (2, 1) , and (3, 1) are successively read out when a series of recording pixels RP disposed on the first scanning line SL1 are to be exposed. In a similar manner, when a series of recording pixels RP disposed on the second scanning line SL2 are to be exposed, screen pattern data stored at the address (0, 2) and (1, 2) are read out. In the Irrational Tangent Method, the address on the screen pattern memory does not go along the primary scanning direction U, and some addresses on the screen pattern memory are skipped in producing halftone dots. If tan .theta. is an irrational number, positional relation between a recording pixel and a corresponding address of the screen pattern memory varies at each recording pixel. Therefore the addresses which are referred to in a certain halftone dot region are generally different from those referred to in adjacent halftone dot regions.
Since the positional relation between a recording pixel and a corresponding address of the screen pattern memory varies with respect to each halftone dot region, the size of halftone dots, or the number of pixels in the halftone dots, fluctuates accordingly even if those halftone dots are produced as a function of an image signal of a constant level. FIG. 6 shows an example of plural halftone dots generated as a function of an image signal with a constant level. Lattice points in FIG. 6 correspond to the centers of recording pixels RP, and circular regions Rex represents the address range of the screen pattern data which are no more than the level of the image signal, that is, the address range in which the recording pixels are exposed. Incidentally, the coordinate axes of the U-V systems run through the center of the recording pixel at an origin O.
The screen pattern data is read out by the address corresponding to the center of the recording pixel RP, which is shown as a lattice point in FIG. 6. The screen pattern data thus read out is compared with the image signal to determine whether the recording pixel RP is exposed or not. As a result, the recording pixels whose centers are located in the region Rex are exposed, and the other pixels are not exposed. The exposed pixels are shown as shaded polygons in FIG. 6. The number of the exposed pixels in a halftone dot ranges from 9 to 12 in this example.
In the Irrational Tangent Method, variation in the positional relation between the address of the screen pattern data and the recording pixels causes fluctuations in size and shape of halftone dots. In other words, halftone dots which are produced as a function of an image signal of a constant level do not have the same area. The variation in the positional relation increases the darkness in some image areas while increasing the lightness in other image areas, thus causing uneven and unstable image reproduction.
Several methods have been proposed to suppress the unevenness of a reproduced image. A method which adds a random number to the address bas been proposed, but this method has a disadvantage of deforming halftone dots. Another method is to shift or distort each halftone dot region at random. The second method, however, could not efficiently suppress fluctuations in size and shape of halftone dots. There is still another method which changes the distribution of light quantity of a light beam. The third method, however, requires a relatively complicated optical system for changing the light quantity of the light beam.

Method of and apparatus for generating halftone dots


A driving device of a plasma display panel for performing a reset period using a ramp pulse. The driving device changes the lowest potential of the ramp down pulse in response to temperature change in order to prevent or reduce low discharge or over-discharge due to the temperature change. The amount of wall charges in the pixels are maintained substantially constant over a temperature range to provide an optimal discharge condition, making it possible to prevent the discharge error and perform the low voltage address operation, in the address period.

1. Field of the Invention
The present invention relates to a driving device of a plasma display panel, and more particularly, to a driving device of a plasma display panel for performing a reset period using a ramp pulse.
2. Description of the Related Art
The plasma display panel (PDP) is a flat panel display for displaying letters or images by exciting phosphors to emit light using a gas discharge in a plasma state. The PDP has higher brightness and luminous efficiency and wider viewing angle than a liquid crystal display (LCD) and a field emission display (FED) so that PDP has been in the spotlight as a display to replace cathode ray tubes (CRTs).
The PDP is classified into a DC type and an AC type according to the pixel structure arranged in a matrix form and the waveform of a driving voltage. In the DC type all electrodes are exposed to a discharge space so that charges directly move between corresponding electrodes; however in the AC type, at least one electrode of the corresponding electrodes is covered with a dielectric so that the charges do not directly move between the corresponding electrodes.
Also, the PDP is classified into a facing discharge structure and a surface discharge structure according to the method of constructing electrodes for discharge. In the facing discharge structure an address discharge for selecting a pixel and a sustain discharge for sustaining discharge occurs between a scan electrode (e.g., positive electrode) and an address electrode (e.g., negative electrode). However, in the surface discharge structure an address discharge for selecting a pixel occurs between an address electrode and a scan electrode crossing the address electrode, and a sustain discharge for sustaining discharge occurs between a scan electrode and a sustain electrode in parallel with the scan electrode.
Referring to FIG. 1, the PDP having the above described structure displays images in gray scale in a time division driving method by dividing a unit frame into a plurality of subfields SF1 to SF6. Each of the subfields SF1 to SF6 is driven in a reset period to make the charge state of a pixel uniform, an address period A1 to A6 to accumulate wall charges on the pixels to be driven, and a sustain discharge period S1 to S6 to sustain discharge the pixels. For such a driving method, each electrode is applied with a corresponding waveform of voltage signal (e.g., a predetermined waveform).
Although FIG. 1 shows the unit frame being divided into six subfields SF1 to SF6, the number of the subfields is not limited as such, and the image quality may improve with higher number of subfields. As a result, methods of dividing the unit frame into 10 to 12 or more subfields have been studied. Furthermore, if the number of the subfields increases, false contour, an important element of image quality, of the displayed image can be reduced to improve image quality.
Meanwhile, other elements for improving the image quality and maintaining the operating margin of the PDP may also be implemented. As one method of maintaining the operating margin of the PDP, a ramp reset method is used. Referring to FIG. 2, a ramp reset is performed in a reset period PR to prepare the pixels of the PDP for low voltage address operation by allowing a large amount of wall charges to be accumulated on the walls of the pixels using weak discharge and then allowing erasing of the rest of wall charges so that only the wall charges suitable for the low voltage address operation remain on the walls of the pixels of the PDP. The ramp reset method uses a voltage signal waveform including a ramp up pulse A and a ramp down pulse B as shown in FIG. 2.
FIG. 3 shows one example of a portion of a circuit for generating the ramp pulse as shown in FIG. 2 and shows a portion of a driving circuit for generating the ramp down pulse B by using a capacitive load in order to operate a switch as constant current source.
Referring to FIG. 3, a resistor R1 is coupled between a control signal S1 input terminal and the gate of a transistor Q1, and a capacitor C1 is coupled between the gate and the drain of the transistor Q1. A capacitor Cgd represents parasitic capacitance between the gate and the drain of the transistor Q1, and a capacitor Cgs represents parasitic capacitance between the gate and the source of the transistor Q1.
As an example, when the voltage applied to the electrodes of the PDP is Vc, the voltage of the ramp pulse linearly increases with respect to a time axis so that the differential value of the voltage Vc is a constant value when the current is constant as shown in Equation 1.
                              Vc          =                                    1              C                                                  ∫                              i                                                  ⅆ                  t                                                                                ⅆ              Vc                                      ⅆ              t                                =                                                    1                C                            ×              i                        =            Constant                                              Equation                                                  1
In Equation 1, C is the capacitance of the display panel and has a constant value. Therefore, in order to generate the ramp pulse as shown in FIG. 2, the current flowed in the display panel must be constant.
Referring to FIGS. 2 and 3, in order for the transistor Q1 to be completely turned-on, the capacitor Cgs between the gate and the source of the transistor Q1 is first charged, and the capacitor Cgd between the gate and the drain is charged, using the control signal S1. Also, the capacitor Cgs is charged by the capacitor Cgd and the capacitor C1 so that the time for the voltage across the gate and the source of the transistor Q1 to exceed the threshold voltage of the transistor Q1 to completely turn on the transistor Q1 is extended by some extent. In other words, the capacitor Cgs is first charged through a path {circle around (1)} to slightly turn on the transistor Q1 so that a gate current can flow through a path {circle around (2)}. Then the capacitor Cgs starts to discharge through the formation of path {circle around (2)}, and the transistor Q1 is kept from being fully turned-on. As such, the transistor Q1 is operated as constant current source using a negative feedback effect through the paths {circle around (1)} and {circle around (2)} to generate the ramp down pulse B. The lowest voltage of the ramp down pulse B is higher than a scan voltage Vscn-l by a voltage ΔV that is the Zener voltage of a Zener diode D1
However, a conventional driving circuit for generating the ramp down pulse B as above has problems as follows.
The temperature of the PDP rises in accordance with the time during which the PDP has been in operation. When the temperature rises, the insulation characteristics of the dielectric or the protective film of the PDP deteriorate, and this can lead to leakage of the wall charges. As a result, the wall charges can move and recombine within a discharge space more easily, and this can lead to the loss of the wall charges. Accordingly, discharge condition is affected by temperature variation. Since the conventional driving circuit generates a constant ramp down pulse, it performs a normal discharge at a certain temperature, but it can perform mis-discharge at a lower temperature or a higher temperature. In other words, when the discharge starting voltage is lower at the lower temperature, over-discharge occurs, and when the discharge starting voltage is higher at the higher temperature, low-discharge occurs. If over-discharge occurs, the wall charges are excessively erased so that discharge can occur even in pixels not selected in the prior address period; and if low-discharge occurs, a significant amount of wall charges remain in pixels so that discharge error occurs when a subsequent address operation is made.

Driving device of plasma display panel and method


Systems and methods for deskewing parallel data lines using at least one extra channel in parallel to the parallel data lines to carry data for comparing to data on the parallel data lines.

The present invention relates generally to parallel data alignment, and more particularly to synchronization of high speed parallel data transmissions.
The capabilities of information processing systems are constantly expanding. Such systems are increasingly called upon to process large amounts of information very quickly. The ability of information processing systems to act on information is dependent on the rate at which the system may receive information and the speed at which the system can process that information. In order to receive information more quickly, the systems are often provided information on parallel data lines. The information provided on the parallel data lines is generally associated together to form blocks of information. The use of parallel data lines allows a system to receive multiple pieces of information at any given moment.
A problem with parallel data lines is that transmission times across the data lines may vary, or skew, due to line lengths, process variations, aging, and environmental conditions. If the data transmission times are sufficiently different, then the information processing system may not group pieces of information received on the data lines in the proper format. The increased rate at which information processing systems process information also results in a decreased tolerance of variation in data transmission time. Thus, if information processing speeds increased by a factor of 10, such has occurred in the last several years, the allowable variation in transmission time decreases significantly.
Furthermore, information processing systems have increasingly been linked in ever greater computer networks, such as the Internet. The demand for information across these networks is tremendous, and has largely been met by ever increasing the rate in which information has passed between network nodes. For example, fiber optic transmission systems have increased data throughput such that data transmission rates have increased from 1.25 gigabits per second (Gb/s) to 2.5 Gb/s, 10 Gb/s, and are shortly expected to reach rates of 40 Gb/s. While specialized components may be able to receive data at such increased rates, the data rate is often slowed down for processing of the data by less specialized components. A common method of reducing a data rate is to deserialize, or put in parallel, received serial data. For example, serial data transmitted at 40 gigabits per second may be deserialized into a 16 bit bus operating at 2.5 gigahertz. At 2.5 Gb/s, however, skew tolerance for process variations and other factors is often minimal.


A method of fabricating an organic light emitting diode. A fluid is sprayed from a nozzle to dissolve organic material or a water-soluble material to be removed from a multi-layer structure of organic luminescent layer, hole transport layer, hole injection layer, electron transport layer and electron injection layer on a substrate. Using an air venting or pumping system such as a vacuum system, the dissolved organic or water-soluble material is removed. The multi-layer structure of organic luminescent layer, hole transport layer, hole injection layer, electron transport layer and electron injection layer can be patterned. After patterning, a step of encapsulation is performed. Thereby, the multi-layer structure is wrapped insulated from oxygen and water. The possibility for the cathode to react with oxygen or water molecules is reduced, and the device lifetime is effectively increased.

This application claims the priority benefit of Taiwan application serial no. 90116427, filed Jul. 5, 2001.
1. Field of the Invention
The invention relates in general to a method of fabricating an organic light emitting diode (OLED), and more particularly, to a method of using sprayed fluid to dissolve the organic material or water soluble material, and using a venting system such as a vacuum system to absorb the dissolved organic or water soluble material to pattern the organic material or the water soluble material.
2. Description of the Related Art
The organic light emitting diode includes an organic thin film with luminescence property sandwiched between two electrodes. While applying a voltage between 2 Volts to 10 Volts, holes are injected from anode and electrons are injected from cathode to the luminescent organic thin film. The potential generated by the external electric field causes the carriers to move and recombine within the thin film. A part of energy released by the recombination of the electron and hole pairs excites the luminescent molecules to single-excited-state molecules. When the single-excited-state molecules fall back to the ground state, a certain proportion of the energy is released in a form of photons to generate luminescence. This is the luminescence mechanism for the organic light emitting diode. Typically, the model of mobile charges is the energy band model. However, different from metal or semiconductor material having certain band width, the energy band of organic material is referred as the continuous energy band formed by electrons and holes. Applying such a model, the process of the photons being released by recombination in the energy band gap after injecting charges from electrodes is easily introduced.
FIG. 1 shows a flow chart of a method for fabricating a conventional organic light emitting diode. A transparent substrate is provided. Multiple strip like anodes are formed on the transparent substrate in step S100. The material of the anodes includes indium tin oxide (ITO). A global coating process is performed to form a multi-layer structure made up of an organic luminescence layer, hole transport layer, hole injection layer, electron transport layer and electron injection layer in step S102. Since the multi-layer structure of the organic light emitting diode has the property of easily absorbing moisture, a pattern process is required before encapsulating the multi-layer structure (S104). The pattern process includes removing a part of the multi-layer structure between the light emitting diodes, so as to define the light emitting diodes on the substrate. The multi-layer structure with the hydrophilic property is then wrapped with the encapsulation material. The penetration of water and oxygen molecules that affect the electric performance of the device is thus prevented.
Further referring to FIG. 1, a plurality of strip like cathodes are formed on the luminescent layer in step S106. The organic light emitting diode array is thus formed. After completion of the organic light emitting diode array, an encapsulation process is performed in step S108, followed by a die cutting step as denoted as S110 to cut the substrate into a plurality of organic light emitting diodes.
In step S104, the conventional method of removing the multi-layer structure includes using a tool such as cotton to wipe the edge of the transparent substrate, or using a laser to wipe the edge, so as to remove the unwanted multi-layer structure on the edge of the organic light emitting diodes. Alternatively, a mask process is performed on the substrate to form the patterned organic luminescent layer and hole transport layer.
Drawbacks exist for the manual or laser edge wiping and the mask process. The manual edge wiping consumes great labor and cost, so that a mass production cannot be achieved. The laser edge wiping and the mask process have the problem of high fabrication cost.
The invention uses a nozzle to spray a fluid that dissolves the organic or water-soluble material to be removed from the multi-layer structure made up of the organic luminescent layer, hole transport layer, hole injection layer, electron transport layer, and electron injection layer. The dissolved material is then vented or vacuumed away. The patterning of the multi-layer structure can thus be obtained. After patterning, an encapsulation step is performed to wrap the multi-layer structure made up of an organic luminescent layer, hole transport layer, hole injection layer, electron transport layer, and electron injection layer to isolate the oxygen and water molecules. The probability for the cathode to react with oxygen and water molecules is reduced, and the lifetime of the device is effectively increased.
The material to be removed with the fluid sprayed from the nozzle is not limited to organic luminescent layer, hole transport layer, hole injection layer, electron transport layer, and electron injection layer. The fluid sprayed from the nozzle can also be applied to remove other organic or water-soluble material.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Method of fabricating organic light emitting diode


A camera mount apparatus is disclosed that allows toolless rotation with integrated detent and locking features. The apparatus has the ability to rotate a camera and lens predetermined increments. In the preferred embodiment, the camera and lens are constrained together, and rotate about the optical axis. One portion of the apparatus remains fixed while another portion rotates and slides, allowing the camera and light to be rotated in a controlled fashion. The apparatus has a hand retractable pin that locks rotational movement and that is released manually to allow rotation adjustment The apparatus has spring plungers that mate to spherical indented features to provide a function to allow a positive feel when the desired angular position is achieved during rotation. The apparatus has bearing surfaces that allow rotation and provide contact of bearing material on rotational sliding faces to metal contact.

Machine vision inspection is an integral component of many industrial processes. Machine vision systems are comprised of various components including a camera, lens, lighting elements, and mounting brackets to allow proper placement inside machinery. Though machine vision has been widely adopted and accepted by industry, there has been a continuing need for improvements in mounting brackets to allow rapid and repeatable positional adjustment of the camera and/or camera and lighting for production format changeovers to allow imaging of varying positions of camera field of view.
Numerous devices for the mounting of cameras have been developed. For example, U.S. Pat. No. 3,758,205 discloses a photographic stand with a camera supporting plate positioned centrally and above the work surface, a frame carrying both the work surface and camera supporting plate and having means for holding light sources for illuminating the work surface and a rotatable camera mount on the camera supporting plate.
U.S. Pat. No. 5,714,998 discloses an inspection system for use with a moving conveyor having a video camera mounted above the conveyor and first and second prisms mounted below the camera but above the part to be inspected. The prisms are oriented to be parallel to two opposite ends of the part to be inspected. Therefore, as the conveyor moves the part below the prisms to an inspection location between the prisms, the camera provides simultaneous images of the ends of the part as well the part's upper surface.
European Patent Application No. 0 986 251 discloses an apparatus for the orthogonal (X,Y) movement which allows high-resolution color photography in both the X and Y directions, by micro-movement of the CCD sensor within a digital camera body is provided which can be used together with a rotatable mount for rotating the CCD sensor from portrait mode to landscape mode, without needing to rotate the camera base.
U.S. Pat. No. 6,986,294 discloses an automated instrument package (AIP) suited to mount on the inside ceiling of a large silo. The gimbaled AIP vertical mounting bracket rotates in an approximate 360° azimuth. An instrument housing is mounted to the vertical mounting bracket, and it rotates approximately 190° in a vertical plane. The instrument housing has at least one range finding sensor such as a scanning laser to measure the top surface contours of the bulk material. The instrument housing can also contains other sensors such as air and quality instruments including temperature, humidity, spectral recognition sensor to detect grain/material type and/or flow rate, gas detectors for sniffing off-odors/spoilage/or safety problems, and live video.
Other references that are relevant include U.S. Pat. No. 866,257; U.S. Pat. No. 4,978,986; U.S. Patent Application Publication No. 2009/0059038; and U.S. Pat. No. 8,374,498. However, none of the disclosures provided in these references are suitable for rapid and repeatable positional adjustment of the camera and/or camera and lighting for production format changeovers to allow imaging of varying positions of camera field of view in machine vision applications.

Machine vision camera mount with rotational adjustment


A power supply control device includes a control unit, and a power path that is connected to a primary external power system. If a connection state between the primary external power system and the power path is in a disconnected state, the control unit is configured to control power output of at least one power conditioner of at least one corresponding secondary external power generation unit, based on (a) an amount of power consumption of a specific load connected to the power supply control device through the power path, and (b) a power generation output of the secondary external power generation unit.

In recent years, solar photovoltaic (hereinafter, appropriately abbreviated as PV) systems using solar panels are provided at home, in buildings, and the like. Not only the power generation by sunlight, but also the power generation by wind power, natural energy such as geothermal heat, fuel energy, or microorganisms has been put into practical use.
Usually, power generated by PV is supplied to devices used in a house in a case of a residual power purchase system, and excess power is sold to a power company. However, when power failure is caused due to an earthquake or the like, the mode of the PV is manually changed into an autonomous operation mode. In the autonomous operation mode, the power generated by the PV is supplied to an emergency autonomous outlet only. By switching to the autonomous operation, electronic devices connected to the autonomous outlet can be used even in the power failure state. Types of electronic devices to be used at the time of power failure are set by the user in advance.
Further, the PV cannot generate power during night, and the like, because it generates power by sunlight. To avoid this problem, a power generation system further including a secondary battery and the like is considered. For example, Patent Literature 1 describes that power in a storage battery is output to a power line, and a power conditioner of a solar photovoltaic system is started based on the power at the time of power failure. Further, Patent Literature 1 describes that, when the storage battery is nearly fully charged, a power generation device is stopped in order to avoid excessive charging.

Power supply device, power supply system, and method of controlling power supply


A frangible flapper valve that may be closed to hydraulically isolate a portion of a wellbore tubular. The flapper valve is made of a frangible material adapted to shatter upon impact from an impact sleeve. The sleeve may be used to initially hold open the flapper valve. A latching mechanism may be used to retain the sleeve above its initial position allowing the flapper to close isolating a portion of the tubular. The latching mechanism may engage a piston to retain the sleeve at the second position. A shearable device adapted to shear under a predetermined pressure selectively connects the piston to the tubular. When the pressure within the tubular increases above the predetermined amount the shearable device releases the piston and pushes the sleeve into the closed flapper valve causing the flapper valve to shatter. A second latching mechanism may prevent further movement of the sleeve.

1. Field of the Invention
The present invention generally relates to a flapper valve that may be used to hydraulically isolate a portion of a wellbore tubular, the flapper valve being made of a frangible material that may be broken with a hydraulic impact sleeve. The flapper is movable from an open position and a closed position and may be biased to the closed position. The flapper is comprised of a frangible material, such as ceramic, that is adapted to shatter upon impact by an impact sleeve. The pressure within the tubular above the closed flapper may encourage the flapper to shatter once a crack is made in the flapper valve by the impact sleeve.
The impact sleeve may be used to initially hold open the flapper valve allowing fluid flow through the wellbore tubular. When it is desired to hydraulically isolate a portion of the wellbore tubular, the impact sleeve may be moved up the wellbore tubular to a second position allowing the flapper valve to close. A latching mechanism may be used to selectively retain the impact sleeve at the second position. For example, the impact sleeve may be connected to a collet located within the wellbore tubular. A mandrel may be inserted within the collet and may be used to raise the collet and the sleeve up the tubular to the second position. In the second position, the sleeve may be located adjacent a piston that is releasably connected to the wellbore tubular. A shearable device, such as a shear screw, may be used to releasably connect the piston to the tubular. The shearable device permits the release of the piston when the pressure within the tubular is increased to a predetermined amount.
After using the mandrel to move the sleeve to the second position, the collet may be deformed to release the mandrel. The piston may be used to hold the collet and/or the impact sleeve at the second position until it is desired to break the frangible flapper valve. The pressure within the tubular may be increased to the amount required to shear the shearable device, thus releasing the piston. The elevated pressure within the wellbore drives the piston and thus, the impact sleeve downwards towards the closed flapper valve. The impact of the sleeve against the flapper valve causes the flapper valve to shatter within the wellbore tubular. The lower end of the impact sleeve may be adapted to promote the shattering of the frangible flapper valve. Further, the lower end of the impact sleeve may be adapted to impact the frangible flapper valve about its outer edge. A second latching mechanism may be used to retain the piston and/or impact sleeve at a position within the wellbore after the frangible flapper valve has been shattered.
2. Description of the Related Art
There are a various number of sealing elements and/or valves that have been used in the oil and gas industry to isolate a portion of a wellbore tubular. Flapper valves are often a preferred sealing means because flapper type valves generally require less radial space than other commercially available valves and/or sealing means. Flapper valves are generally biased, by a spring or other resilient member, to close and hydraulically isolate a portion of the tubular when the flapper is not being held open. Prior to being closed, a mandrel or sleeve is often inserted through the flapper valve to hold open the valve. The mandrel or sleeve is then removed when it is necessary to isolate a portion of the wellbore below the flapper valve.
The closed flapper may cause a high pressure differential to be created on the opposite sides of the closed flapper making it difficult to reopen. Further, it may be difficult to grab a hold of the flapper with a tool to reopen the valve. Other flapper valves have been designed to be operated hydraulically, which increases the complexity of the valve. In order to overcome the difficulties of opening a closed flapper valve, a number of prior flapper valves have been designed to break under an elevated pressure within the wellbore tubular. These type flapper valves must be designed to hold an amount of pressure to adequately isolate a portion of the wellbore tubular, but to shatter or break upon the application of an elevated amount of pressure. However, it is difficult to predict when and at what pressure such a flapper will break.
In light of the foregoing, it would be desirable to provide flapper valve that is designed to be shattered by the impact of a sleeve within the wellbore tubular. It would further be desirable to provide a means for releasing the sleeve at a predetermined pressure within the wellbore tubular. The use of a shearable device, such as a shear pin, provides an accurate prediction of when the sleeve will be released within the wellbore shattering the flapper valve. It would be desirable to provide a flapper valve comprised of a frangible material to promote the shattering of the valve upon impact from the sleeve.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the issues set forth above.

Frangible flapper valve with hydraulic impact sleeve and method of breaking


A main beam fabrication procedure and system for making main beams for warehouse framework through feeding, auto-forwarding and flattening, punching, roller shape-forming, cutting-off and finished product collection steps, in which the punching machine comprises an upper mold holder, four upper punching dies arranged in two longitudinal rows on the bottom side of the upper mold holder and adjustable to change the transverse pitch between the two longitudinal rows of upper punching dies, a bottom mold holder, and four bottom punching dies arranged in two longitudinal rows on the top side of the bottom mold holder and adjustable to change the transverse pitch between the two longitudinal rows of bottom punching dies.

The present invention relates to a main beam fabrication procedure and relates also to a main beam fabrication system, in which the punching machine has multiple pitch-adjustable punching dies for punching punch holes on the processing plate material subject to different specifications.
Conventionally, the fabrication of a main beam for warehouse framework includes the steps plate material feeding, auto-forwarding and flattening, punching, roller shape-forming, cutting-off, and finished product collection. A main beam fabrication system for this main beam fabrication procedure comprises a feeder rack adapted to feed a plate material to an auto-forwarding and flattening mechanism, an auto-forwarding and flattening mechanism adapted to flatten the plate material fed by the feeder rack and then to forward the flattened plate material to a punching machine, a punching machine operable to punch the flattened plate material delivered from the auto-forwarding and flattening mechanism to form four rows of punch holes 211,221,222,223,224,231 on the flattened plate material 2, a roller shape-forming machine adapted to ram the plate material punched by the punching machine into a shaped beam having a front wall 22, two curved sidewalls 21, 23, and a reinforcing groove 225 formed on the middle part of the front wall 22, and a cut-off machine adapted to cut off the shaped beam thus obtained from the roller shape-forming machine into multiple pieces of finished products subject to the desired length. According to this design, the pitch of the punching dies of the punching machine is not adjustable. When changing the specifications of the main beam, different punching dies must be used. Replacing the punching dies requires much time and labor. In conclusion, the aforesaid conventional punching machine has drawbacks as follows:
1. For making different specifications (sizes) of main beams, different punching dies should be used. The replacement and calibration of punching dies require much labor and time.
2. For making a same specification main beam from a different thickness of plate material, different punching dies should be used. The replacement and calibration of punching dies require much labor and time.
The present invention has been accomplished under the circumstances in view. It is one object of the present invention to provide a main beam fabrication procedure and system, which is adjustable to make different specifications of main beams without changing the punching dies. It is another object of the present invention to provide a main beam fabrication procedure and system, which saves much labor and processing time, thereby greatly reducing the main beam manufacturing cost.
To achieve these and other objects of the present invention, the main beam fabrication procedure is adapted to make main beams for warehouse framework through feeding, auto-forwarding and flattening, punching, roller shape-forming, cutting-off and finished product collection steps, wherein the punching machine comprises an upper mold holder, four upper punching dies arranged in two longitudinal rows on the bottom side of the upper mold holder and adjustable to change the transverse pitch between the two longitudinal rows of upper punching dies, a bottom mold holder, and four bottom punching dies arranged in two longitudinal rows on the top side of the bottom mold holder and adjustable to change the transverse pitch between the two longitudinal rows of bottom punching dies.

Main beam fabrication procedure and system for making a main beam for warehouse framework


A vacuum bulb for interrupting an electrical circuit, the bulb comprising two electrical poles enabling an electrical connection to be established between the outside and interrupting contacts placed inside the bulb, the body of the bulb being dielectrically reinforced by an outside insulator disposed on the bulb between the two electrical poles, wherein the insulator is constituted by a polymer sheath heat-shrunk directly onto the body of the bulb.

Vacuum bulbs are used in electrical current-interrupter devices. A vacuum bulb is constituted by a cylinder of insulating material fitted with two facing electrical contacts. One of the contacts is stationary and the other is moving to enable the contacts to be separated or to be brought together. The contacts are connected to external conducting flanges placed on opposite faces of the bulb, which flanges enable electrical connections to be made with external lines or circuits.
The vacuum established inside the bulb provides the required dielectric strength and interrupting power in a small volume. However, it is necessary to provide a creepage distance outside the bulb of sufficient length to guarantee overall isolation between the contacts. Bulbs are then fitted with electrical insulators having fins in order to obtain creepage distances of sufficient length.
Such isolators are conventionally made of ceramics. An insulator is placed around a vacuum bulb between its flanges. The space between the bulb and the insulator is filled with a filler resin that must have very good adherence qualities and that must not shrink in order to avoid allowing a layer of air to form between the bulb and the resin or between the resin and the electrical insulator.
Ceramic insulators suffer from a certain number of drawbacks.
They are heavy, and above all they are brittle which makes them particularly sensitive to vandalism. When placed on the roof of a rail vehicle, their relatively large volume gives rise to drag.
As a replacement for ceramic material, it is known that a resin can be molded over a vacuum bulb to form an insulator. Appropriate resins include epoxies such as those sold under the trademark Araldite, after treatment to enable them to withstand ultraviolet radiation. However, such materials are also fragile, and in operation they require significant thicknesses, thereby giving rise to high weight.
Document WO 91/06106, filed in the name of Raychem Limited, discloses a high tension insulator having a polymer core which provides it with good mechanical strength and which is protected on the outside by a sheath of heat-shrink polymer which is electrically insulating and which withstands leakage currents, said sheath being provided with fins on its outside surface.
To mitigate the drawbacks of prior art vacuum bulbs provided with electrical insulation, the present invention seeks to dispose electrically insulating heat-shrink substances such as those disclosed in WO 91/06106 directly on a vacuum bulb. Such substances provide very good shock resistance because they are flexible and they enable insulators to be obtained that are compact and light in weight.

Vacuum bulb provided with electrical insulation


A data signal line driving circuit which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.

1. Field of the Invention
The present invention relates to a data signal line driving circuit for continuously sampling input signals and outputting them, and an image display apparatus which adopts the data signal line driving circuit.
2. Description of the Related Art
Hereinafter, a liquid crystal display apparatus and a data line driving circuit used therein will be described using conventional examples of an image display apparatus and a data signal line driving circuit.
An active matrix type liquid crystal display apparatus is well known. This apparatus is composed of a pixel array ARRAY, a scanning signal line driving circuit GD, and a data signal line driving circuit SD, as shown in FIG. 17.
The pixel array ARY includes scanning signal lines GL and data signal lines SL crossing the scanning signal lines GL. Each pixel PIX is provided in a matrix in each portion surrounded by two adjacent scanning signal lines GL and two adjacent data signal lines SL.
The data signal line driving circuit SD sequentially samples input video signals DAT in synchronization with a timing signal such as a clock signal CLKs, and amplifies each sampled video signal, if required, to output it to each data signal line SL.
The scanning signal line driving circuit GD sequentially selects each scanning signal line GL in synchronization with a timing signal such as a clock signal CLKg, and controls opening and closing of each switching element in each pixel PIX along the selected scanning signal line GL, there by writing each video signal (data) output to each data signal line SL into each pixel PIX and allowing data written into each pixel PIX to be held.
As shown in FIG. 18, each pixel PIX shown in FIG. 17 is composed of a field effect transistor SW which is a switching element and a pixel capacitance made of a liquid crystal capacitance CL and an auxiliary capacitance CS which is added if required.
As shown in FIG. 18, the data signal line SL is connected to one of electrodes of the pixel capacitance through a drain and a source of the transistor SW. A gate of the transistor SW is connected to the scanning signal electrode line GL, and the other electrode of the pixel capacitance is connected to a common electrode line of all the pixels. Due to a voltage applied to each liquid crystal capacitance CL, a transmittance or a reflectivity of liquid crystal is modulated, which contributes to a display.
Next, a method for sampling a video signal and outputting it to a data signal line will be described.
Examples of a method for driving a data signal line includes a dot sequential driving method and a line sequential driving method. Herein, only a dot sequential driving method will be described with reference to FIGS. 19 and 20. This description is also applicable to a line sequential driving method.
In each circuit shown in FIGS. 19 and 20, a shift register SR sequentially outputs sampling pulses while shifting them, in synchronization with a clock signal CLK (corresponding to the clock signal CLKs in FIG. 17). Sampling pulses N1, N2, N3, and N4 sequentially output from the shift register SR are sequentially supplied to respective analog switches G1, G2, G3, and G4. The analog switches G1, G2, G3, and G4 sequentially open in response to the respective sampling pulses N1, N2, N3, and N4, sequentially sampling video signals transmitted to a video signal line DAT, and sequentially outputting respective sampled video signals SL1, SL2, SL3, and SL4.
In the shift register SR, unit circuits as shown in FIG. 21 or 22 are arranged.
The unit circuit shown in FIG. 21 forms the shift register SR which shifts pulses only in one direction, and is composed of two clock control inverter circuits 201 and one inverter circuit 202.
The unit circuit shown in FIG. 22 forms the shift register SR which shifts pulses in both directions, and is composed of two clock control inverter circuits 201 and two inverter circuits 203.
Both the shift registers SR have a structure of a half-latch circuit, which latches a pulse only in one direction of a rising or falling of a clock signal and outputs a pulse width in one period of the clock signal.
In an example shown in FIG. 19, outputs of the shift register SR are directly used as the sampling pulses N1 to N4. Therefore, the continuous sampling pulses overlap each other by a half as shown in FIG. 23.
In an example shown in FIG. 20, respective overlapped portions of adjacent output pulses of the shift register SR are used as the sampling pulses N1 to N4. Therefore, the continuous sampling pulses do not overlap each other as shown in FIG. 24.
FIG. 25 shows an exemplary scanning signal line driving circuit. In this circuit, as shown in FIG. 27, a shift register SR sequentially outputs sampling pulses N1 to N4 while shifting them, in synchronization with a clock signal CLK corresponding to the clock signal CLKg in FIG. 17. This driving circuit is designed in such a manner that adjacent output pulses of the shift register SR do not overlap each other. Furthermore, by selecting an overlapped portion between the signal thus obtained and a pulse width control signal GPS from outside, each sampling pulse having a desired pulse width is obtained.
In the conventional data signal line driving circuits shown in FIGS. 19 and 20, every other sampling pulse, N1 to N4, partially overlaps with one another as shown in FIG. 23, and the continuous sampling pulses, N1 to N4, partially overlap each other as shown in FIG. 24. This is because, in the conventional circuit configuration, a sampling pulse rises when another sampling pulse falls. Furthermore, due to variation and the like in transistor characteristics in the circuit, a timing of a part of sampling pulses may be shifted. In this case, an overlapped portion of the respective sampling pulses becomes larger.
In the case where sampling pulses overlap each other, a level of a video signal to be written into a data signal line may be changed. For example, in the circuit shown in FIG. 20, when the subsequent sampling pulse N3 rises before the sampling pulse N2 is turned off as shown in FIG. 26, the video signal DAT is drawn to the data signal line SL3 corresponding to the sampling pulse N3 as well as the data signal line SL2 corresponding to the sampling pulse N2. Therefore, a level of the video signal DAT to be output to the data signal line SL2 decreases by xcex94 V. Similarly, when the sampling pulse N4 rises before the sampling pulse N2 is turned off in the circuit shown in FIG. 19, the video signal DAT is drawn to two data signal lines SL2 and SL4. Therefore, a level of the video signal DAT to be output to the data signal line SL2 decreases.
Consequently, a desired pixel potential cannot be obtained, making it difficult to obtain a normal display. In particular, when there is a variation in an overlapped portion of sampling pulses, level change values of a video signal and a pixel potential vary, which may cause roughness and a stripe pattern in an image.
The circuit shown in FIG. 25 has the following disadvantage: although a pulse width of each sampling pulse is adjusted, it is required to generate and supply the pulse width control signal GPS having a frequency twice that of the clock signal CLK; therefore, a burden on an external circuit is increased.
A data signal line driving circuit is provided, which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.
In one embodiment of the present invention, each of the sampling signals is obtained as a NAND signal or a NOR signal between a pulse signal and a signal obtained by delaying the pulse signal through a plurality of inverter circuits, whereby a pulse width of each of the sampling signals is prescribed to be small.
In another embodiment of the present invention, a capacitance is connected between the plurality of inverter circuits.
In another embodiment of the present invention, a capacitance is connected between each of the inverter circuits and either a NAND circuit or a NOR circuit.
In another embodiment of the present invention, a pulse signal is a pulse output from a shift register.
In another embodiment of the present invention, the above-mentioned data signal line driving circuit includes a shift register capable of shifting sampling pulses in both directions or in one direction, wherein each of the sampling signals is obtained by using either a NAND signal or a NOR signal between two adjacent output pulses output from the shift register, and a delay signal of the NAND signal or the NOR signal, whereby the sampling signal of either the NAND signal or the NOR signal, having a decreased pulse width, is obtained.
In another embodiment of the present invention, the above-mentioned data signal line driving circuit includes a shift register capable of shifting sampling pulses in one direction, wherein each of the sampling signals is obtained as either a NAND signal or a NOR signal between one of two adjacent output pulses output from the shift register and the other pulse which is delayed, whereby a pulse width of each of the sampling signals is decreased.
In another embodiment of the present invention, a time of the delay is about 10 nsec to about 100 nsec.
According to another aspect of the present invention, an active matrix type image display apparatus includes: a plurality of data signal lines arranged in a column direction: a plurality of scanning signal lines arranged in a row direction; a plurality of pixels arranged in a matrix surrounded by the data signal lines and the scanning signal lines; a data signal line driving circuit for supplying video data to the data signal lines; and a scanning signal line driving circuit for supplying a scanning signal to the scanning signal lines, wherein the data signal line driving circuit is a data signal line driving circuit which sequentially forms a plurality of sampling signals and continuously sampling input signals to output them, in response to the sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.
In one embodiment of the present invention, the scanning signal line driving circuit and the data signal line driving circuit are formed on the same substrate with the pixels.
In another embodiment of the present invention, active elements included in the scanning signal line driving circuit, the data signal line driving circuit, and the pixels are polycrystalline silicon thin film transistors.
In another embodiment of the present invention, the active elements are formed on a glass substrate by a process at about 600xc2x0 C. or lower.
Hereinafter, the function of the present invention will be described.
In the data signal line driving circuit of the present invention, a pulse width of each sampling signal is prescribed to be small so that the rising and falling of each sampling signal for sampling a video data signal do not overlap each other. In this structure, after a video signal is output to a data signal line, a video signal is output to the subsequent signal line. Thus, a video signal on a data signal line can be prevented from being drawn to another data signal line, and a video signal at a desired voltage level can be output to any data signal line.
In one embodiment, a NAND or a NOR between a pulse signal delayed by a plurality of inverter circuits and a pulse signal which is not delayed is obtained. In this structure, a pulse width of each sampling signal can be prescribed to be small without using a control signal from outside. Thus, a video signal at a desired voltage level can be written to a data signal line without burdening an external control circuit or the like.
In another embodiment, a capacitance is added between the inverter circuits, or between the inverter circuit and a circuit for obtaining either a NAND signal or a NOR signal. In this structure, by appropriately selecting a value of the above-mentioned capacitance, a pulse width can be controlled. Thus, a pulse width can be arbitrarily set so as not allow sampling pulses to overlap each other. Because of this, after a video signal is output to a data signal line, a video signal is output to the subsequent data signal line. This prevents a video signal on a data signal line from being drawn to another data signal line, and a video signal at a desired voltage level can be written to a data signal line.
In another embodiment, a pulse signal is an output signal from a shift register. In this structure, a sampling pulse is obtained by using two adjacent output pulses output from the shift register. These sampling pulses overlap each other by about a half, but every other sampling pulse does not overlap with one another (i.e., a sampling pulse falls completely, and then, a sampling pulse after the subsequent sampling pulse rises). Thus, a video signal on a data signal line is prevented from being drawn to another data signal line, and a video signal at a desired voltage level can be written to a data signal line.
In another embodiment, a shift register is capable of shifting sampling pulses in both directions, and by using a NAND signal (or a NOR signal) between two adjacent output pulses output from the shift register, and a delay signal thereof, a pulse width of the NAND signal (or the NOR signal) is prescribed to be small. In this structure, after a sampling pulse falls completely, the subsequent sampling pulse rises, so that adjacent sampling pulses do not overlap each other. Therefore, a video signal on a data signal line is prevented from being drawn to another data signal line, and a video signal at a desired voltage level can be written to a data signal line. Furthermore, adjacent sampling pulses do not overlap each other, so that only one data signal line is connected to a video signal line at a time during driving. Thus, a capacitance load on a video signal line can be decreased compared with that in the above-mentioned structure, and the burden on an external video signal source can be alleviated and writing performance of a data signal line driving circuit itself can be enhanced. This structure is applicable to a shift register capable of shifting sampling pulses only in one direction.
In another embodiment, a shift register is capable of shifting sampling pulses in one direction, and by generating a NAND signal (or a NOR signal) between one of two adjacent output pulses output from the shift register and a delay signal of the other output pulse, a pulse width of the NAND signal (or a NOR signal) is prescribed to be small. In this structure, after a sampling pulse falls completely, the subsequent sampling pulse rises in the same way as in the above-mentioned structure. Therefore, fluctuation of a video signal (which is caused when the video signal is drawn to the subsequent data signal line) does not affect the previous data signal line, and a video signal at a desired voltage level can be written to a data signal line.
Furthermore, in the same way as in the aforementioned structure, adjacent sampling pulses do not overlap each other. Therefore, only one data signal line is connected to a video signal line at a time during driving. Thus, a capacitance load on a video signal line can be decreased, compared with that of the above-mentioned structure. This can alleviate a burden on an external video signal source and enhance driving ability of a data signal line driving circuit itself.
Furthermore, compared with the above-mentioned structure, a circuit which generates a NAND signal (or a NOR signal) between two adjacent output pulses output from the shift register is eliminated. Thus, in the case where a scanning direction of the shift register is limited to one direction, circuit configuration can be simplified, and miniaturization of a driving circuit, reduction in a production cost, and enhancement of a production yield can be expected.
In another embodiment, the time of a delay is about 10 nsec to about 100 nsec.
A timing shift of sampling pulses caused by rising characteristics of sampling pulses and a variation in transistor characteristics are on the order of about 10 nsec. Therefore, by setting the delay time at about 10 to about 50 nsec and decreasing the sampling pulse width, fluctuation of a video signal (which is caused when the video signal is drawn to the subsequent data signal line) does not affect the previous data signal line, making it possible to write a video signal at a desired voltage level to a data signal line.
Furthermore, the image display apparatus of the present invention is provided with the above-mentioned data signal line driving circuit.
Thus, as described above, in the data signal line driving circuit, fluctuation of a video signal (which is caused when the video signal is drawn to the subsequent data signal line) does not affect the previous data signal line, and a video signal at a desired voltage level can be written to a data signal line. Therefore, a video signal at a desired voltage level can also be written to a display electrode, and an image with high display quality can be displayed.
In one embodiment, the scanning signal line driving circuit and the data signal line driving circuit are formed on the same substrate with the pixels. In this structure, the pixels for performing a display, the data signal line driving circuit and the scanning signal line driving circuit for driving the pixels can be produced on the same substrate during the same step. Therefore, the production cost and mounting cost can be reduced, and the ratio of mounting satisfactory products can be enhanced.
In another embodiment, at least the pixels and the data signal line driving circuit are disposed on a polycrystalline silicon thin film formed on an insulating substrate.
When transistors are formed of polycrystalline silicon thin films as described above, high characteristics of driving force can be obtained, compared with the case of amorphous silicon thin film transistors used in a conventional active matrix liquid crystal display apparatus. Therefore, the pixels and the signal line driving circuit can easily be formed on the same substrate.
In another embodiment, the active elements are formed on a glass substrate by a process at about 600xc2x0 C. or lower.
As described above, in the case where polycrystalline silicon thin film transistors are produced at about 600xc2x0 C. or lower, it is possible to use an inexpensive glass substrate which has a low strain temperature but permits the apparatus to be large. Therefore, a large image display apparatus can be produced at a low cost.
Thus, the invention described herein makes possible the advantages of: (1) providing a data signal line driving circuit which is capable of enhancing display quality in an image display apparatus by preventing sampling pulses from overlapping each other; and (2) providing an image display apparatus which adopts the data signal line driving circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.

Data signal line driving circuit and image display apparatus


This invention provides a peak signal detecting device by which a peak of an input signal can be accurately detected even if a noise is caused. A level slice circuit (3) outputs a level slice signal S3 which turns to High/Low depending upon whether an absolute value of a reading signal S0 is more/less than a threshold value VT1. A level slice circuit (5) outputs a level slice signal S5 which turns to High/Low depending upon whether an absolute value of a differentiated signal S1 is more/less than a threshold value VT2. A delay circuit (6) delays a leading edge of the level slice signal S5 for a period T1 and its trailing edge for a period T2 to produce a delay signal S6. At this time, this process is cancelled when the High level of the level slice signal S5 is less than T1. A gate circuit (4) outputs a conjunction of a zero cross signal S2, level slice signal S3 and delay signal S6 as a gate signal S4' (peak detecting signal).

1. Field of the Invention
The present invention relates to a peak signal detecting device for detecting a peak of an input signal.
2. Description of the Prior Art
FIG. 8 is a block diagram showing a system architecture of a conventional peak signal detecting device for detecting a peak of an input signal, such as a magnetic disc reading signal and the like. FIG. 9 is a waveform diagram showing various signals in the peak signal detecting device. As shown in FIG. 8, a reading signal S0 (see FIG. 9) is applied through an input terminal 7 to a differentiating circuit 1 and level slice circuit 3.
The differentiating circuit 1 differentiates the reading signal S0 to output a differentiated signal S1 (see FIG. 9) to a zero cross detecting circuit 2. The zero cross detecting circuit 2 takes in the differentiated signal S1, and when detecting a time when the differentiated signal S1 reaches a zero level (a time when it crosses the zero level) ordinarily at Low level, that is, a time when an inclination of the reading signal S0 becomes 0, it outputs a zero cross signal S2 (see FIG. 9) which becomes a pulse at High level for a specific period of time, to the gate circuit 4.
On the other hand, the level slice circuit 3 outputs a level slice signal S3 (see FIG. 9) which turns to High/Low depending upon whether an absolute value of the reading signal S0 is more/less than a specified threshold value VT1, to the gate circuit 4.
The gate circuit 4 receives the zero cross signal S2 and level slice signal S3 to output a gate signal S4 (see FIG. 9) which is a conjunction of the signals S2 and S3 through an output terminal 8 to the outside. Thus, the gate signal S4 reaches the High level when the differentiated signal S1 is 0 and the absolute value of the reading signal S0 is eual to or more than VT1, while the gate signal S4 is at the Low level at a time when the reading signal S0 is near zero level with an inclination 0. As a result, the gate signal S4 reaches the High level in correspondence with a time when the reading signal S0 reaches its peak, and hence, detecting the High level of the gate signal S4 allows the peak of the reading signal S0 to be detected.
However, in the conventional peak signal detecting device, when, as shown at a time t1 in FIG. 10, a noise NZ is caused at a level over the threshold value VT1 of the level slicing circuit 3 and a false extreme point is generated in the reading signal S0, the zero cross signal S2 turns to the High level while the level slice signal S3 also turns to the High level, and the gate signal S4 turns to the High level. Hence, a generating point of the noise NZ may be erroneously detected as a time of the peak, and thus, there arises the problem that an accuracy in detecting a peak time is degraded.

Mitsubishi Electric Engineering Company Limited