This invention is directed to the production of glasses exhibiting transition temperatures below 375.degree. C., preferably below 350.degree. C., and superior resistance to attack by boiling water. The glasses contain at least 10% copper, as expressed in terms of CuO, the predominant proportion of the copper being present in the Cu.sup.+2 oxidation state. The glasses consist essentially, in mole percent, of. ______________________________________ Li.sub.2 O 0-15 MgO 0-15 B.sub.2 O.sub.3 0-5 Na.sub.2 O 0-20 CaO 0-20 ZnO 0-37 K.sub.2 O 0-10 SrO 0-20 Sb.sub.2 O.sub.3 0-36 Tl.sub.2 O 0-15 BaO 0-20 CeO.sub.2 0-3 Li.sub.2 O + Na.sub.2 O + 12-30 MgO + 0-25 MoO.sub.3 0-7 K.sub.2 O + Tl.sub.2 O CaO + SrO + BaO CuO 10-50 Al.sub.2 O.sub.3 + B.sub.2 O.sub.3 0-5 RE.sub.2 O.sub.3 0-2 P.sub.2 O.sub.5 28-36 Al.sub.2 O.sub.3 0-5 WO.sub.3 0-7 MnO 0-20 ______________________________________. wherein at least two alkali metal oxides are present and up to 12% by weight fluoride may optionally be present.

Considerable research has been conducted in the past to devise inorganic glasses exhibiting low transition temperatures (Tg), thereby enabling melting and forming operations to be carried out at low temperatures with consequent savings in energy costs. More recently, it has been recognized that glasses demonstrating low transition temperatures are potentially useful materials for a host of applications including low temperature sealing glasses and glass-organic polymer composites. A very recent development disclosed in U.S. Pat. No. 5,043,369 (Bahn et al.) involves the production of glass-organic polymer alloys. Those alloys are prepared from a glass and a thermoplastic or thermosetting polymer having compatible working temperatures. Thus, the glass and the polymer are combined at the working temperature to form an intimate mixture; that is, the glass and polymer are in a sufficiently fluid state to be blended together to form a body displaying an essentially uniform, fine-grained microstructure in which, desirably, there is at least partial miscibility and/or a reaction between the glass and the polymer to promote adhesion and bonding therebetween. An article is shaped from the blend and then cooled to room temperature. Such articles exhibit chemical and physical properties comprising a composite of those demonstrated by the particular glass and polymer. For example, the alloys frequently display a combination of high surface hardness, high stiffness, and high toughness.
Glasses having base compositions within the general zinc phosphate system have been found to be especially suitable for the glass component of glass-polymer alloys. Several illustrations of recent research in that composition system are reported below.
U.S. Pat. No. 4,940,677 (Beall et al.) discloses glasses exhibiting transition temperatures below 450.degree. C., preferably below 350.degree. C., consisting essentially, in mole percent, of at least 65% total of 23-55% ZnO, 28-40% P.sub.2 O.sub.5, and 10-35% R.sub.2 O, wherein R.sub.2 O consists of at least two alkali metal oxides in the indicated proportions selected from the group of 0-25% Li.sub.2 O, 0-25% Na.sub.2 O, and 0-25% K.sub.2 O, and up to 35% total of optional constituents in the indicated proportions selected from the group of 0-6% Al.sub.2 O.sub.3, 0-8% B.sub.2 O.sub.3, 0-8% Al.sub.2 O.sub.3 +B.sub.2 O.sub.3, 0-15% Cu.sub.2 O, 0-5% F, 0-35% PbO, 0-35% SnO, 0-35% PbO+SnO, 0-5% ZrO.sub.2, 0-4% SiO.sub.2, and 0-15% MgO+CaO+SrO+BaO+MnO, consisting of 0-10% MgO, 0-10% CaO, 0-10% SrO, 0-12% BaO, and 0-10% MnO.
U.S. Pat. No. 4,996,172 (Beall et al.) describes glasses demonstrating transition temperatures below 350.degree. C. consisting essentially, in mole percent, of 30-55% ZnO, 28-45% P.sub.2 O.sub.5, 10-35% R.sub.2 O, wherein R.sub.2 O consists of at least two alkali metal oxides in the indicated proportions of 0-25% Li.sub.2 O, 0-25% Na.sub.2 O, and 0-25% K.sub.2 O, 0-4% Al.sub.2 O.sub.3, 0-10% total of at least one divalent metal oxide selected from the group of CaO, MgO, and MnO, 0-15% CuO, 0-35% PbO, 0-35% SnO, 0-35% SnO+PbO, and 0.5-5% total of Y.sub.2 O.sub.3 and/or at least one rare earth metal oxide of the lanthanide series.
U.S. Pat. No. 5,021,366 (Aitken) is directed to glasses having annealing points between 300.degree.-340.degree. C. which are fluorine-free and consist essentially, in mole percent, of
__________________________________________________________________________ Li.sub.2 O 5-10 P.sub.2 O.sub.5 30-36 Na.sub.2 O 5-15 Al.sub.2 O.sub.3 0-5 K.sub.2 O 0-6 CeO.sub.2 0-2 Li.sub.2 O + Na.sub.2 O + K.sub.2 O 15-25 SnO 0-20 ZnO 10-33 PbO 0-20 CaO 0-20 Sb.sub.2 O.sub.3 0-12 SrO 0-20 Bi.sub.2 O.sub.3 0-6 BaO 0-20 SnO + PbO + Sb.sub.2 O.sub.3 + Bi.sub.2 O.sub.3 0-20. CaO + SrO + BaO 12-25 __________________________________________________________________________
U.S. Pat. No. 5,071,795 (Beall et al.) illustrates glasses exhibiting transition temperatures no higher than 350.degree. C. consisting essentially, in mole percent, of
______________________________________ Li.sub.2 O 0-25 ZnO 25-50 Na.sub.2 O 5-20 Al.sub.2 O.sub.3 0-3 K.sub.2 O 0-12 P.sub.2 O.sub.5 25-37 Li.sub.2 O + Na.sub.2 O + K.sub.2 O 15-35 SrO 0-10 ______________________________________
to which are included 0.5-8% Cl and 0-5% F as analyzed in weight percent. Up to 10% Cu.sub.2 O, up to 3% SiO.sub.2, and up to 8% total of at least one alkaline earth metal oxide may be included.
U.S. Pat. No. 5,122,484 (Beall et al.) is drawn to glasses having transition temperatures no higher than about 425.degree. C. which were specifically designed for use as sealing frits in television picture tube applications. The glass compositions were PbO-free and consisted essentially, in weight percent, of:
__________________________________________________________________________ Li.sub.2 O 0.75-5 SnO.sub.2 0-10 Na.sub.2 O 2-10 MoO.sub.3 0-10 K.sub.2 O 2-10 WO.sub.3 0-10 Li.sub.2 O + Na.sub.2 O + K.sub.2 O 5-25 MoO.sub.3 + WO.sub.3 2-25 ZnO 29-42 Cl 0-8 (analyzed) P.sub.2 O.sub.5 38.50 SnO.sub.2 + MoO.sub.3 + WO.sub.3 + Cl 2-25. Al.sub.2 O.sub.3 0-5 __________________________________________________________________________
One inherent drawback of phosphate-based glass compositions having low transition temperatures is their reduced resistance to attack by water and mild solutions of acids and bases, when compared to silicate-based glasses. The above-described zinc phosphate glasses demonstrate relatively excellent resistance to chemical attack, when compared to other phosphate-based glasses. Nevertheless, the search has been continuous to discover new glass compositions manifesting low transition temperatures with even greater chemical durability.
Accordingly, the principal objective of the present invention was to devise glass compositions having transition temperatures below 375.degree. C., preferably between about 300.degree.-350.degree. C., wherein the chemical durability is much improved over that of zinc phosphate-based glasses.


Embodiments are directed to selecting a debit network using a quick response (QR) code and to processing a payment using a debit network selected according to information embedded in a QR code. In one scenario, a mobile computer system receives input indicating that a user has initiated a payment for various items sold by a provider of goods or services. The mobile computer system determines that the user or the provider has specified a preference indicating which debit network is to be used to process the payment. The mobile computer system then generates a QR code with the debit network selection and portions of the user's debit account information embedded in the QR code, and sends the generated QR code to a payment processing system. The payment processing system may be cloud-based, or may be run locally at the provider's point of sale.

Computers have become highly integrated in the workforce, in the home, in mobile devices, and many other places. Computers can process massive amounts of information quickly and efficiently. Software applications designed to run on computer systems allow users to perform a wide variety of functions including business applications, schoolwork, entertainment and more. Software applications are often designed to perform specific tasks, such as word processor applications for drafting documents, or email programs for sending, receiving and organizing email.
Today's smart phones use software applications to perform a wide variety of functionality. In some cases, this functionality may include the ability to pay for items using a mobile payment system. Such a mobile payment system may allow users to pay for items at a store or over the internet using their phone.

Debit network routing selection using a scannable code


A modular storage cabinet for compact disk jewel boxes that includes a plurality of connectible members to construct a cabinet of a desired architecture or configuration of choice. The cabinet of the invention will be provided to the user in disassembled form wherein the various parts or members can be assembled into a configuration of choice to hold a desired number of compact disk jewel boxes including both single and double boxes. The members include side, back, top, bottom and expander members for constructing an enclosure having a front opening into which jewel boxes may be inserted and withdrawn wherein the structure is in the form of a tower.

The use of compact disks (CDs) for the recording and playing of music and other data has become widespread. It is not uncommon for a person either in his home or at a business to accumulate dozens and even hundreds of CDs over a period of time. The CDs are always kept in a plastic jewel box, which is a container for protecting the CD against damage. The jewel boxes usually receive only a single CD, but there are many jewel boxes that will receive a pair of CDs, and those jewel boxes may be referred to as double jewel boxes.
The accumulation of a large number of CDs presents the problem of handling and storage and particularly storing so that they are readily available for use. A variety of different storage cabinets or enclosures have been provided heretofore for storage of CDs. However, those storage devices have all been of the type that are made up in advance to hold a predetermined number of CDs, and also where the structure is preconfigured.


A medical device performs a method for controlling a cardiac pacing therapy. The device determines an inter-atrial conduction time (IACT) and compares the IACT to a threshold. A controller included in the device sets a pacing interval for controlling delivery of pacing pulses to a ventricle to a first ventricular pacing interval that expires after the IACT in response to the IACT being less than the threshold and sets the pacing interval to a second ventricular pacing interval that expires before the IACT in response to the IACT being greater than the threshold.

Cardiac resynchronization therapy (CRT) is a treatment for heart failure patients in which one or more heart chambers are electrically stimulated (paced) to restore or improve heart chamber synchrony. Improved heart chamber synchrony is expected to improve hemodynamic performance of the heart, such as assessed by ventricular pressure and the rate of change in ventricular pressure or other hemodynamic parameters, thereby alleviating symptoms of heart failure. Achieving a positive clinical benefit from CRT is dependent on several therapy control parameters, such as the atrio-ventricular (AV) delay, inter-ventricular (VV) delay and pacing site(s). The AV delay controls the timing of ventricular pacing pulses relative to an atrial depolarization, intrinsic or paced. The VV delay controls the timing of a pacing pulse in one ventricle relative to a paced or intrinsic sensed event in the other ventricle. Pacing may be delivered in the right ventricle and/or the left ventricle to restore ventricular synchrony.
Atrial conduction disorders are common in heart failure. When atrial-ventricular timing is not optimal, the atrial contribution to ventricular filling can be diminished, which can reduce ventricular ejection and hemodynamic performance. Implantable devices and associated methods are needed for delivering CRT in a manner that reduces risks of atrial conduction disorders.

Bi-atrial synchronized left ventricular cardiac pacing


A process for substantially stabilizing the color of a fluid which comprises an olefin is disclosed. The process comprises contacting the fluid with a composition, which comprises aluminum, zirconium and a borate, under a condition effective to stabilize the color of the fluid.

Olefins are a class of very important chemicals. For example, an .alpha.-olefin can be used as a monomer or comonomer to produce an olefin polymer such as polyethylene. Lower olefins such as ethylene and propylene are generally produced by thermal cracking of saturated hydrocarbons. Higher olefins having 6 or more carbon atoms per molecule are generally produced by ethylene oligomerization. One example is the production of 1-hexene by catalytic trimerization of ethylene catalyzed by a composition comprising a chromium compound, a pyrrolide compound, and a metal alkyl. The trimerization process also produces decenes as by-products. Decenes are generally separated from 1-hexene by distillation and can be used as comonomers for producing olefin polymers, as synthetic lubricating oils, as detergents, as intermediates and feedstock for conversion to alcohols, or as solvent.
One problem facing the production of decenes is the association of a pyrrolide compound with the decenes because both the decenes and pyrrolide compounds have about the same or similar boiling point. Olefins containing a pyrrolide compound are subject to discoloration thereby rendering the olefins less attractive or useless. Therefore, it is highly desirable to substantially stabilize the color of an olefin.


A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3−) and a sulfate ion (OSO3−), and an acidic aqueous solution.

1. Field of the Invention
Example embodiments of the present invention relate to slurry compositions for polishing metal, methods of polishing a metal object, and methods of forming a metal wiring using the same. More particularly, example embodiments of the present invention relate to slurry compositions for polishing metal that may be used in a semiconductor manufacturing process, methods of polishing a metal object, and methods of forming a metal wiring using the same.
2. Description of the Related Art
A semiconductor manufacturing process may generally include forming a layer, e.g., an insulation layer or a conductive layer, on a substrate, planarizing a surface of the layer, etching the layer to form a pattern having a predetermined shape, or the like. For example, a conductive layer may be formed on a substrate, followed by planarizing and etching thereof to form an electrode, a wiring, or a contact plug, e.g., to electrically connect two conductive structures to each other.
A conventional planarizing process may include, e.g., an etch-back process, a reflow process, a chemical mechanical polishing (CMP) process, or the like. For example, in the CMP process, a substrate, i.e., a semiconductor wafer, coated with a conductive layer may be mechanically polished by rubbing a surface thereof against a slurry composition and a polishing pad, and may be also chemically removed by a chemical reaction between the slurry composition and the surface of the conductive layer.
A polishing efficiency of the CMP process may be determined, e.g., by a type of a CMP apparatus, components of the slurry composition, a type of the polishing pad, and so forth. For example, the slurry composition in the CMP process should be able to rapidly polish the conductive layer on the substrate. A conventional slurry composition having a high polishing rate, however, may have strong corrosive properties, so excessive portions of the conductive layer may be removed. For example, a conventional slurry composition having strong corrosive properties may excessively etch a top portion of a metal wiring layer on the substrate to generate seams in the metal wiring layer, i.e., holes on a top portion of a layer to be polished. Seams in the metal wiring layer may increase electrical resistance of the layer, so performance of the semiconductor device may be deteriorated.

Slurry compositions for polishing metal, methods of polishing a metal object and methods of forming a metal wiring using the same


An electronic device and a method of controlling the electronic device are provided. The electronic device includes a housing, a roll at least partially contained in the housing, a display configured to be rolled on the roll, the display including a display area having a size that changes according to a rotation of the roll, and the display being configured to display a screen including at least one element in the display area, a sensor configured to sense the rotation of the roll, and a processor electrically connected to the display and the sensor. In response to a size of the display area being changed according to the rotation of the roll, the processor is configured to change at least one of a size and a layout of an element included in the screen according to the size of the display area.

Field
Apparatuses and methods consistent with the exemplary embodiments relate to an electronic device and a method of controlling the electronic device, and more particularly, to an electronic device including a display that is rolled by a roll and includes a display area having a size that changes according to a rotation of the roll, and a method of controlling the electronic device.
Description of the Related Art
Display apparatuses are among the most important electronic products. In recent years, the size of electronic devices, including display apparatuses, has been reduced. However, many consumers demand large screens. Therefore, flexible displays that may be rolled into electronic devices or that have foldable screens have been actively researched and developed.
In particular, rollable displays that may be rolled into rolls have been actively researched, and electronic devices including rollable displays are expected to be commercialized soon.

Electronic device having rollable display and method of controlling the same


A stereo headset (104) with push-to-talk function can be interfaced with a wireless communication device (102) via a connector interface. The connector interface preferably includes a jack at the wireless communication device (102) and a compatible plug at the stereo headset (104). An electrical contact (310) at the connector interface can contemporaneously interconnect both electrical audio signals between the wireless communication device (102) and at least one of the speakers of the stereo headset (104) and electrical user input signals from an external push-to-talk user input device (232) to the wireless communication device (102).

Consumers of wireless communication devices, such cellular telephones, demand small, portable, and compact devices. One design feature that provides both functional advantages and such miniaturization and portability benefits is the external audio headset.
A known headset design includes a 4-pole, monaural accessory, with Push-To-Talk (PTT) function. The interface between the monaural headset and the wireless communication device includes one line each for a speaker/earpiece transducer, a microphone, a PTT button, and a common ground reference.
Although modern wireless communication devices are now capable of providing stereo audio output via internal audio speakers in the wireless communication device, unfortunately, there are no known stereo headsets that also include a PTT function on the audio headset for controlling a wireless communication device.
Additionally, in view of the consumer demands for smaller and more compact wireless communication devices, any attempt to increase the number of connector pins at an interface of the wireless communication device, such as to allow both a conventional stereo audio headset and also to add a separate PTT switch control, would not only increase the size and complexity of the interface connectors, at both the wireless device and at the headset, but it would also increase the overall cost of a product to consumers. This type of solution would increase the overall number of connector lines on an interface for both the wireless communication device and the headset. Consumer demands for miniaturization of wireless communication device solutions, and the strong consumer sensitivity to increased product costs, would detrimentally impact the commercial viability of such a wireless communication device solution.
Therefore a need exists to overcome the problems with the prior art as discussed above.

Four pole stereo headset with push to talk capability in a duplex radio


A holding device (10) for gripping a pair of spaced receptacle connectors (50) in a parallel relation, includes a plate-like body (12) having defining two side portions (14) for respectively retaining the two connectors (50) thereto. A retention member (16) is formed on each side portion (14) for grasping two sides of the corresponding connector (50). A pair of guidance channels (22) are provided at two opposite ends of the body (12) for cooperation with the end projections (54) on the connector (50). A pair of bosses (26) are respectively disposed about the corresponding channels (22) for restraining and aligning the lengthwise position of the connector (50) with regard to the holding device (10). Transverse ribs (28) are formed on the body (12) for abutment with the top surface (56) of the connector (50). Therefore, the connector (50) can be reliably and efficiently retained by the holding device (10) for moving to the specific predetermined position on the PC board through a suction nozzle of a robot arm.

1. Field of the Invention
The invention relates to the device adapted to cooperate with a suction nozzle for mounting the connector to the PC board, and particularly to the device which can reliably and efficiently hold a pair of connectors for mounting to the PC board.
2. The Related Art
U.S. Pat. No. 5,249,977 discloses a cap detachably attached to a receptacle connector so that such receptacle connector can be picked and displaced, by a suction nozzle, to a specific position on the PC board for a surface mounting soldering. Recently board-to-board connectors are popularly used for interconnecting two parallel spaced PC boards. Understandably, using a pair of connectors respectively disposed on the corresponding boards for mating with each other is not mechanically reliable because these two boards may relatively swing with each other around the lengthwise direction of these two mated connectors. Therefore, to properly and evenly connect these two spaced boards, two connectors are required to be mounted to each board and designedly to be adapted to mate with the corresponding connectors. Under this situation, the connection area between these two boards is substantially a significant rectangular region, not the original single lengthwise region which tends to have the boards vibrate with each other as mentioned before.
U.S. Pat. No. 5,558,540 discloses a duplex connector assembly including a pair of connector units for cooperation with a removable holding means for mounting to a PC board. Generally speaking, it is somewhat complicated and uneasy to mold a unitary connector assembly including two juxtaposed connector units while still precisely controlling the relative positions and dimensions. Thus, some attempts have been made to use a holding device for simultaneously gripping two parallel spaced simplex connectors and mounting to one PC board. It should be noted that different from the holding device for mounting one simplex connector on a PC board as disclosed in U.S. Pat. No. 5,249,977, using one holding device for simultaneously incorporating two juxtaposed simplex connectors requires higher precision and delicate procedure.
Therefore, an object of the invention is to provide a holding device for simultaneously gripping two spaced connectors in a parallel relation for precisely positioning on the corresponding PC board.

Holding device for mounting connector on board


A method and system for identifying and mitigating interference caused by a rogue transmission source in an Optical Camera Communication (OCC) network is disclosed. The method includes receiving information from a plurality of transmission sources. Each of the plurality of transmission sources is within a capture area of a camera. Each of the plurality of transmission sources comprises a set of light sources configured to display one of a plurality of color codes. The method further includes detecting, through the camera, an interference between a serving transmission source associated with the camera and a non-serving transmission source. The serving transmission source belongs to the plurality of transmission sources. The method further includes establishing the non-serving transmission source as the rogue transmission source, when the non-serving transmission source is not registered with a master coordinator within the OCC network.

The demand for wireless data communication is increasing at a very high rate. To keep up with this growing demand, the available Radio Frequency (RF) spectrum of below 10 GHz may not be sufficient. As an alternative, Optical Wireless Communication (OWC) involves communication over a light channel by a transmit-receive (transceiver) pair. The transceiver pair can transmit information using a Light Emitting Diode (LED) and receive information using a light sensor, such as, a photo diode or a camera.
Optical Camera Communication (OCC) may be one of the forms of OWC. The OCC involves a camera that is used to decode information received from a transmitter. The transmitter transmits the information by encoding it in a spatially arranged color codes. Thus, while information transmission is based on emitting the encoded frames in color codes, reception is based on capturing the image of the transmitted information and extracting the spatial information which could be used to decode transmitted data.
The OCC may further include a screen based transmission scheme and an LED based transmission scheme. In a screen based transmission scheme, a set of color patterns may be used to encode information that is to be transmitted. As an example of spatially arranged coding scheme used in OCC, a Quick Response (QR) code based communication may be used that displays QR codes on a display screen. In the LED based transmission scheme, the information to be transmitted is encoded by color codes emitted by a set of spatially arranged LEDs. In the present state of art, when there are two or more transmission sources in the capture area of a receiver camera in an OCC network, the interference cause under this scenario may be mitigated using a coordinator which may assign a unique guard band to each of the two or more transmission sources. The conventional techniques require each of the two or more transmission sources to be registered with a single coordinator.
However, there may be a case where a rogue transmission source (a transmission source not registered with a coordinator and deliberately causing interference with the coordinated transmission sources, in order to degrade the quality of communication), may enter an OCC network. In such cases, communication with coordinated transmission sources may be disrupted. Conventional methods are ill-equipped to deal with such situations. Hence, interference management and multi-access in the interference region within the OCC systems remains a key challenge.

Method and system for managing interference caused by rogue node in optical camera communication network


An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and drain of which is connected to an internal node; and a second transistor which is formed at the substrate, a second gate of which is connected to a second power supply terminal, one of a second source and drain of which is connected to an input/output node, and the other of the second source and drain of which is connected to the internal node. The substrate of the second transistor has an electrically floating potential.

(1) Field of the Invention
The present invention relates to input/output circuit devices, and more particularly relates to input/output circuit devices connected to semiconductor devices supplied with a higher power supply voltage than a predetermined operating voltage (design voltage).
(2) Description of Related Art
In recent years, with a sharp reduction in the size of complementary metal-oxide-semiconductor (CMOS) devices, the power supply voltage supplied to the CMOS device has been decreasing from 5 volts to 3.3 volts.
However, a plurality of electronic makers will never change the operating voltages of semiconductor devices from 5 volts to 3.3 volts in unison. It is impossible to change the operating voltages of all semiconductor devices to be connected to other semiconductor devices. Therefore, very large scale integrated circuit (VLSI) devices designed, for example, under the assumption that their operating voltage is 3.3 volts need to interface (make connection) with other semiconductor devices operating at a known operating voltage of 5 volts.
In order to interface between a semiconductor device designed to have an operating voltage of 3.3 volts and a semiconductor device designed to have an operating voltage of 5 volts, an input/output circuit or device for avoiding the adverse effect produced by the potential difference between the operating voltages is required. In other words, a further high-breakdown-voltage input/output circuit that can absorb the potential difference between the operating voltages is required, resulting in an increase in cost.
An input/output circuit device according to a known example will be described hereinafter with reference to FIG. 7. As illustrated in FIG. 7, a known input/output circuit device is composed of two cascaded n-type MOS transistors, a pull-down transistor Q1 and a cascade transistor Q2.
The gate of the pull-down transistor Q1 is connected to a signal terminal Vn to which a ground voltage Vss (=0 volt) or a power supply voltage VDD (=3.3 volts) is fed, the source thereof is grounded, and the drain thereof is connected to an internal node Vc. The gate of the cascade transistor Q2 is applied with a power supply voltage VDD, one of a source and a drain thereof is connected to the internal node Vc, and the other thereof is connected to an input/output terminal V0 applied with a voltage of 0 volt or 5 volts. The substrate potential of each of the pull-down transistor Q1 and the cascade transistor Q2 is grounded.
The pull-down transistor Q1 and the cascade transistor Q2 both usually represent transistors designed to operate at a drain-to-source voltage of 3.3 volts or less. However, in this known example, the transistors Q1 and Q2 are cascaded to each other so that the voltage applied to the input/output terminal V0, i.e., 5 volts, is divided by the transistors Q1 and Q2. This allows the application of a voltage of 5 volts to the input/output circuit device.
However, the known input/output circuit device causes the following problems when a voltage of 5 volts fed from the input/output terminal V0 is divided by the pull-down transistor Q1 and the cascade transistor Q2. In other words, when the source-to-drain voltages of the transistors Q1 and Q2 are equal to each other, the potential of the internal node Vc is approximately 2.5 volts. Therefore, the source voltage of the cascade transistor Q2 is approximately 2.5 volts. This allows the application of a substrate bias voltage, i.e., a substrate-to-source voltage of approximately 2.5 volts. As a result, the hot-carrier tolerance of the pull-down transistor Q2 is reduced, resulting in a significantly reduced reliability life of the input/output circuit device.
In order to reduce the substrate bias effect, the voltage applied from the input/output terminal V0 needs to be divided between the transistors to reduce the potential of the internal node Vc. In this case, the potential difference between the source and the drain of the cascade transistor Q2 (between the internal node Vc and the input/output terminal V0) increases, also resulting in a significant reduction in the hot-carrier tolerance.

Matsushita Electric Industrial Co., Ltd.


A damper apparatus for controlling airflow between compartments in a two compartment refrigerator having a door includes a controller for controlling opening and closing of a damper; and a door sensor connected to the controller for detecting when the door is open. If the controller determines that the door has remained closed for a set period, the controller maintains the damper in the closed position. A method for cleaning a damper in a refrigerator includes a steps of defrosting a refrigeration apparatus of the refrigerator, at least partially opening the damper, followed by waiting for a set period and then at least partially closing the damper. The steps of at least partially opening and waiting are repeated a set number of times and then a cooling operation of the refrigeration apparatus is commenced.

The present invention relates to automatic defrost controls for two compartment refrigerators, and more particularly to automatic defrost controllers including air damper control.
Refrigerators having two refrigeration compartments, including a fresh food compartment and a frozen food compartment, are well known. Many of these two compartment refrigerators have refrigeration apparatus connected to the frozen food compartment and a duct for carrying cool air from the frozen food compartment to the fresh food compartment. In order to regulate the temperature of the fresh food compartment, a damper or baffle is often provided within or adjacent to the duct. The baffle is thermostatically controlled to provide a desired temperature within the fresh food compartment.
Self defrosting refrigerators generally include a defrost heater for melting ice that has accumulated on the refrigeration apparatus. However, the operation of the defrost heater will often cause water to accumulate on or near the air duct damper. Subsequently, especially when the cooling apparatus is operated, the water can freeze and form ice that interferes with the effective operation of the damper.
In order to avoid this problem, a number of solution has been proposed. In U.S. Pat. No. 5,201,888 to Beach et al. a control moves the damper to a fully closed position while energizing the defrost heater. Thus, the formation of condensation and subsequent ice formation is reduced. However, water can still accumulate on the baffle, which later freezes, especially when the defrost heater must be operated for an extended period of time.
U.S. Pat. No. 5,375,413 to Fredell et al. discloses a two-element sliding air baffle for a refrigerator. The second baffle element is operated by a solenoid that, in a closed position, is periodically pulsed (every one minute) thereby exerting a repeated rocking or leveraging motion on the second baffle member. The rocking motion enhances the break up of any ice that has formed between the two baffle elements. However, once ice has formed, it can be very difficult to remove.
Further, energy conservation is becoming more and more important in appliances such as refrigerators. Although many energy saving measures have been developed, there are significant inefficiencies in the operation of such refrigerators.
Thus, there is a need for a refrigerator capable of preventing the build-up of ice on an air duct damper. Further, there is a need for improving the energy efficiency of refrigerators.

Automatic defrost controller including air damper control


In a wireless communication system comprising a plurality of mesh points (MPs), a method for determining a level of involvement of MPs within the system includes a first MP transmitting a network status request signal to a second MP. The second MP responds to the first MP with network status information. The first MP receives the network status information from the second MP, and determines a level of involvement in the wireless system based on the network status information.

Wireless local area networks (WLANs) are becoming more widespread as wireless technology continues to become more advanced, and variations of wireless networks may exist. For example, a traditional WLAN might be based on a structured system that includes a base station which communicates with wireless devices and routes traffic between them. Another type of wireless network is an ad-hoc network, in which a wireless device communicates with one or more additional wireless devices in a point-to-point technique where wireless devices dynamically connect to, and disconnect from, the network.
As a combination of the traditional WLAN and ad-hoc network, a mesh network may include user devices, terminals, access points (APs), and base stations, which all function as mesh points (MPs). Mesh networks have been garnering increasing support in the standards community due to characteristics such as low-effort coverage extension for WLANs, low-effort and low-complexity self-deploying WLANs, and for their high fault-tolerance and redundancy.
One characteristic of a mesh network is that MPs within the network may perform various network functions that were traditionally only performed by one particular type of wireless device within a network. As a result, MPs that are not normally utilized for particular functions may become strained by suddenly being expected to perform these additional functions. For example, a wireless device that is not normally expected to perform routing or forwarding from one device to another may experience an excessive drain on its power supply or battery when routing or forwarding from one MP to another, thereby limiting the device's functionality and useful life.
Accordingly, there is a need to control the MPs that participate in the mesh network from both the MP user's and the mesh network operator's perspective, that are not subject to the limitations of conventional methods.

Method and apparatus for determining a level of involvement of mesh points in a wireless communication system


A map generator generates a replanting map designating a particular area in a field in which it is recommended to add additional seeds. A function of the agricultural machine is then controlled based at least in part on the replanting map so as to facilitate planting additional seeds in the designated particular area.

From the perspective of many growers of crops, rainfall events are becoming more frequent and larger quantities of rain are falling. Such conditions are especially problematic for crop producers when a rainfall event occurs soon after planting because plants have only then just begun to grow. The seeds or sometimes even plants can be washed away when rainfall is heavy. Further, saturated soils can prohibit oxygen from respiring plant tissues, thereby causing an undesirable reduction in the number of plants that reach harvestability. For at least these reasons, rainfall events can negatively impact the intended density of plants within a seeded area.
Some growers attempt to replant seed in damaged areas where a reduction in the number of established plants is perceived as being likely to be below a desirable threshold. Of course, it is only worth it if the value of placing additional seed in the soil warrants the expense and effort of replanting. It can be a challenge to ascertain which areas within a damaged field are and are not ideal locations for replanting.
Choosing where in a field to replant is especially challenging for a seed machine operator that is making such judgement calls while simultaneously operating the basic navigation functions of the machine. Candidate areas for replanting are often spatially variable within the field. The topographic features in different areas are not always consistent. Rainfall quantity causes the degree of plant stand reductions to vary significantly from one area to another. Still further, it can be challenging to determine the precise transition between an area with an adequate plant per area ratio and an area where the ratio renders it desirable for replanting. Also, as equipment gets larger, it becomes increasingly more difficult to monitor the full extent of the equipment swath, and there is often considerable variability across the swath. These conditions make it even more difficult to make machine operation decisions on the fly in a way that enables precise planting control. With some or all of these considerations in mind, the operator must decide when and where to activate or deactivate (e.g., raise/lower) planter equipment. For at least these reasons, it is especially challenging for an operator of seeding equipment to optimize the replanting process.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.

Replant routing and control of a seed planting machine


A position obtainment means obtains the positions of points in the heart of a subject that are present in at least two three-dimensional volume datasets in a group of three-dimensional volume datasets that have been obtained by imaging the heart of the subject at predetermined time intervals, the points anatomically corresponding to each other, and the at least two three-dimensional volume datasets having been obtained by imaging at different time from each other. A function information obtainment means obtains, based on each of the positions of the points in the heart, which have been obtained by the position obtainment means, function information representing the function of the heart at each point within a three-dimensional space. A display means displays, based on the function information, the motion function of the heart at each of the points in an image that has the shape of the heart of the subject.

1. Field of the Invention
The present invention relates to a cardiac function analysis apparatus and method for displaying a cardiac function. Further, the present invention relates to a computer program for the apparatus and the method.
2. Description of the Related Art
Conventionally, in cardiac motion analyses using CT images obtained in a plurality of different phases (temporal phases), slice images (short-axial images) in the short-axial direction of a heart are obtained from a three-dimensional image that has been obtained in each of the phases. Then, outlines R1, R2, R3 and R4 of the cardiac muscle wall in each of the phases are extracted from the slice images at corresponding positions (please refer to FIG. 8A, which is a diagram illustrating a heart in diastole (relaxation period), and FIG. 8B, which is a diagram illustrating the heart in systole (contraction period)). Then, outlines R1 and R3 of the cardiac muscle wall (inner surface) at a cross section on a line intersecting the same position of long axis L are obtained. Further, a difference between the outlines R1 and R3 is used as an amount of the motion of the cardiac muscle wall (please refer to FIG. 8C). This processing is performed at each position of short-axial cross sections that are orthogonal to the long axis of the heart from the cardiac apex to the cardiac base. Then, the obtained result is output as a three-dimensional analysis result.
Further, as a method for displaying such a cardiac motion analysis result, a bull's-eye display method has been used. In the bull's-eye display method, when a heart is assumed to approximate an ellipsoid model, the result is displayed by concentrically arranging sliced planes that have been obtained by slicing the ellipsoid at constant intervals in a direction traversing the long axis of the ellipsoid. This display method is mainly used for function images. Further, this display method is used to display images directly obtained by cardiac muscle scintigraphy (SPECT; single photon emission computed tomography) and functions obtained from the result of analysis using CT (computed tomography) or MRI (magnetic resonance imaging) (for example, U.S. Patent Application Publication No. 20050008209).
When the aforementioned result of analysis is obtained by using the CT or MRI, the motion of the heart in a radial direction from the center of the short-axial image of the heart is observed. However, the actual motion of the heart includes rotation and twisting motion in addition to relaxation and contraction. Therefore, the aforementioned result of analysis does not reflect the function of the heart based on the actual motion of the heart.

Cardiac function analysis apparatus, method and program


A diagonal offset clock signal distribution system and method are presented that facilitate maximized placement of a diagonal offset clock signal distribution tree.

Electronic devices and systems have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. These electronic devices often include integrated circuits that perform variety of functions. In numerous implementations, operations performed by the integrated circuits are synchronized by clock signals. However, routing constraints can make clock signal distribution in conventional clock distribution systems a formidable task.

This patent is subject to a terminal disclaimer.

Clock signal distribution system and method


The orienting device of the present invention will properly orient a closure which is transferred from a hopper to be applied to a container in connection with a form, fill and seal packaging machine. The present invention will also maintain the orientation on an anvil as the anvil moves the closure from the orienting device to a container through exertion of a vacuum on the closure. The present invention also discloses a specific closure for use with an overall orienting closure system. The orienting device will have at least two channels which maintain the closure as the closure is oriented into a desired position.

1. Field of the Invention
The present invention relates to an apparatus for orienting a fitment on a container. Specifically, the present invention relates to an apparatus for orienting an orientationally sensitive fitment on a carton.
2. Description of the Related Art
Containers having spout-like closures for dispensing the contents therefrom have come into widespread use. One such type of closure includes a threaded spout extending upwardly from a container. The closure is used with a cap that threadly engages the spout. Frequently, such closures are injection molded directly onto the container material stock. Such closures may, however, be formed separate from the container and subsequently mounted thereto. For certain applications, such closures have shown significant advantages over known closure systems.
Another known type of closure includes a one-piece molded body having a hinged cap. Such one piece closures advantageously eliminate the need for a separately formed closure cap. The one-piece configuration eliminates the possibility of losing or inadvertently discarding the separate cap portion.
One drawback to using such hinged closures is that each closure must be properly oriented on its respective container because each closure cover hinges or pivots about an axis particularly located on the closure. For example, the cover portion of a hinged closure that is mounted to a gable top carton must pivot upwardly, out of the way of the contents being dispensed or poured from the container. If the cover pivots in a manner or direction other than upwardly, it may interfere with dispensing or pouring of the contents therefrom.
In another application, it may be desired to position a non-hinged closure, such as a threaded closure package, in a particular orientation on a container. Such particularized orientation of the closure may be, for example, to effect the proper positioning of indicia on the closure or closure cap relative to the container. This may be significant if the indicia contains a logo, trademark or like representation.
Known orientable closures typically have one or more flattened sides to facilitate proper orientation of the closure on the container. Inasmuch as such partially flattened closures are acceptable for hinged type closures, there are a number of drawbacks. First, such flattened sides may increase the cost to manufacture such closures. In addition, handling and positioning of such closures could require additional capital equipment for sorting, positioning and mounting the closures to containers. Moreover, such flattened closures are difficult to use in conjunction with a threaded-type closure arrangement.
Accordingly, there continues to be a need for an orientationally sensitive closure and an orienting apparatus for use with such a closure. Such a closure and apparatus should readily orient the closure for proper positioning for mounting to a container. Such a closure should include a hinged cover portion that opens away from the dispensing direction. Advantageously, such a closure may include directionally sensitive indicia, such as logos and the like, which indicia should be properly oriented on the closure.

Orienting apparatus for an orientationally sensitive closure


A revolving coin display stand for the display of proof coin sets encased in hermetically sealed plastic display cartridges is disclosed. The coin display stand is constructed so as to permit a user to view both the obverse and reverse sides of the coins by manually revolving a pivoting frame assembly 360 degrees relative to a supporting base plate. The base plate is constructed of sufficient weight to prevent the proof coin set which is permanently captured in the supporting frame from toppling over during rotation by a user. In an alternative embodiment the supporting base is provided with writing implement holders adapted to receive implements such as pens and pencils in the maimer of a traditional desk set.

1. Field of Invention
This invention relates to display devices and, more particularly, to a framed display stand for viewing proof coin sets and related items.
Despite the recent popularity of coin collecting as a hobby and avocation, numismatic enthusiasts are commonly faced with the problem of not being able to display their United States proof coin sets. This is due in part to the manner in which such coins are made available to the collector.
Since 1968 the United States Mint has offered the proof coin set in a rigid plastic display cartridge. This plastic display cartridge is known as the lens and it hermetically encapsulates the proof coins thereby protecting the same from dust, dirt and any other contaminants which may be present while handling and viewing the proof coin set. However, due to the lack of a suitable display stand, which will allow the user to view both the obverse and reverse sides of the coins, these proof coin sets are usually placed in a drawer and forgotten.
Although the United States Mint has made some display stands available for this purpose, the result has been unsatisfactory. For example, the display stands supplied by the United States Mint from 1973 to 1982 are noted for a high center of gravity which causes the coin display to topple over easily resulting in damage to the lens cartridge and to the coins as well.
Thus, there is a need for a coin display stand which is adapted to receive a standard size proof coin set and which will permit viewing of both the obverse and reverse sides of the enclosed coins.
2. Description of Related Prior Art
U.S. Pat. No. 540,660 to Rodolph E. Hansen discloses a picture exhibitor comprising a rectangular display casing that is pivotally mounted between a pair of vertical posts for the display of photographs or other pictures.
U.S. Pat. No. 488,042 to Alfred Svensson also discloses a picture exhibitor including a picture case that is mounted on a horizontally disposed shaft between a pair of vertically disposed brackets. The picture case is capable of rotation between the brackets for the display of photographs within the revolving case.
U.S. Pat. No. 642,576 to William Boydell discloses a displaying device including a rectangular, glass covered frame for the display of cards which is pivotally mounted so as to be revolvable between a pair of vertically disposed brackets.
U.S. Pat. No. 716,367 to Ernst Bekker et al. discloses a revolving photograph cabinet that may be revolved by hand or other means on studs secured to an easel or other suitable stand. A means is provided for separating an upper tier of photographs from a lower tier and at the same time to serve as a guide to permit the odd picture in the upper tier to slide to a vacant space in the lower tier at each half-revolution of the cabinet.
Finally, U.S. Pat. No. 3,312,197 to Forrest W. Smith is considered of general interest in that it discloses a facsimile coin embedded in transparent plastic where only one side of the facsimile coin is visible. This device is intended as an ornamental paper weight which may be useful to hold down papers or which may be mounted on a wall for purely ornamental purposes.


Systems and methods of powder coating glass to block light are described herein. The method includes preheating a glass item and applying two or three coats of powder, alternating with heating at desired temperatures and/or for a set time. The glass article may be a glass window or a container for holding items that must be stored or transported without being exposed to light.

Field
This disclosure relates to powder coating, and in particular to powder coating a glass item to block visible and nonvisible light from passing through the glass.
Description of the Related Art
Powder coating is a process for coating articles with a sprayed-on organic polymeric material or polymer resin in a powdered form. The powder is typically initially applied electrostatically to an article. The powder is then permanently adhered to the article by the application of heat. The heat causes the powder to melt, liquefy and coat the article. When the article cools, the powder coating cures. Powder coating is typically applied to metal articles such as fence posts, mail boxes, home appliances, patio furniture, bicycles, and other items. Powder coating is an alternative to paint.

Method of powder coating glass to block visible and nonvisible light


A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.

1. Field of the Invention
The present invention relates to a power semiconductor device.
2. Background Art
A widely known example of a power transistor for handling high current is a vertical power MOSFET.
An on-resistance of the vertical power MOSFET largely depends on an electric resistance of a drift layer (conduction layer). The electric resistance of the drift layer changes according to a dopant concentration of the drift layer. To raise this dopant concentration, it is required to consider a breakdown voltage of a pn junction between the drift layer and a base layer. This is because the dopant concentration cannot be raised higher than a limiting concentration decided according to the breakdown voltage. In this way, a tradeoff relationship is present between the breakdown voltage and the on-resistance. There is a limit decided by materials of the device to realize both improvement in the breakdown voltage and suppression in the on-resistance.
As an example of a structure for solving this problem, there is known a super junction structure where n pillar layers and p pillar layers are buried in the drift layer. In the super junction structure, a pseudo undoped layer is formed by setting an impurity amount (charge amount) of each n pillar layer equal to that of each p pillar layer. Then, a current is applied via the heavily-doped n pillar layers, thereby realizing low on-resistance exceeding the material limitation while keeping the breakdown voltage high. To keep the high breakdown voltage, it is required to control the impurity amounts of the n pillar layers and the p pillar layers with high accuracy.
In a power semiconductor device where a MOSFET is formed on a drift layer of a super junction structure, the super junction structure is formed not only in a device part but also in a terminal part. However, in this case, there is a problem that it is difficult to set a breakdown voltage of the terminal part higher than that of the device part. In this case, if avalanche breakdown occurs, electric field locally concentrates on the terminal part, possibly resulting in breakdown of the terminal part.
JP-A 2004-134714 (KOKAI) discloses an example of a semiconductor device including parallel pn connection layers, each of which includes a p-type semiconductor region and an n-type semiconductor region, wherein an impurity concentration of a central portion of each semiconductor region is set higher than that of side portions of each semiconductor region. In a semiconductor region, the central portion is arranged apart from a junction plane between the semiconductor region and its adjacent semiconductor region, and the side portions are arranged closer to the junction plane.
Further, JP-A 2006-324432 (KOKAI) discloses an example of a semiconductor device including parallel pn connection layers, each of which includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, wherein an impurity concentration of the second conductivity type semiconductor layer is 1.15 times or more as high as that of the first conductivity type semiconductor layer.


Apparatus for measuring multiple primary electric currents in a non-contact manner by utilizing multiple current transformers. Each current transformer is coupled with one of the primary electric currents. Each current transformer comprises a magnetic core and a secondary winding. The apparatus comprises: A current-sensing means for sensing current transformer secondary currents and for producing an information signal; a voltage control and selection circuit for periodically connecting each current transformer secondary winding to the current-sensing means and for periodically controlling the voltage across each secondary winding; a power supply circuit for providing operating power to the voltage control and selection circuit; and a control circuit for receiving and processing the information signal and for controlling the voltage control and selection circuit. The control circuit and the voltage control and selection circuit function to select and control the multiple current transformers for periodic measurement of the multiple primary electric currents.

This invention relates to the art of electric current measurement, and especially to the art of utilizing ordinary current transformers to measure a-c (alternating-current) current, d-c (direct-current) current, and a-c current having a d-c current component. The invention disclosed herein utilizes a common electronic control circuit to provide magnetic control for multiple current transformers, thereby providing a way to accurately measure multiple electric currents for lower cost than competing technologies.
The present invention is a development of the inventions disclosed in U.S. Pat. No. 6,160,697 to Edel, issued Dec. 12, 2000; U.S. Pat. No. 6,522,517 to Edel, issued Feb. 18, 2003; and U.S. Pat. No. 7,242,157 to Edel, issued Jul. 10, 2007. These patents will be referenced herein as "the 697 patent", "the 517 patent", and "the 157 patent" respectively.
U.S. Pat. No. 6,522,517 to Edel, issued Feb. 18, 2003, (the 517 patent) is hereby incorporated by reference, in its entirety, into this disclosure.
The 697 patent and the 517 patent disclose how a varying voltage, produced by a "controllable voltage device," may be applied to a conductive winding that magnetically interacts with a magnetic body. The varying voltage controls the voltage induced in the winding in such a way that the integral over time of the induced voltage correlates to desired changes of the induction of the magnetic body. (As used in this disclosure, the term "induction level" is synonymous with the terms "magnetization" and "magnetic flux density"). The induction level may be controlled in several ways:    (a) The induction level of a magnetic body may be caused to transition from a known induction level to a preferred induction level. (A preferred induction level of zero may be chosen to demagnetize a magnetic body).    (b) When the induction level is not known, a preferred induction level may be established by changing the induction level of the magnetic body from an unknown induction level to a known induction level and then to the preferred induction level.    (c) A preferred induction level may be maintained by causing the induced voltage across the winding to have an average value near zero (or by causing the integral of induced voltage to not exceed a predetermined value).    (d) A preferred induction level may be more strictly maintained by causing the induced voltage across the winding to continuously be near zero volts, thereby reducing the amount that the induction level fluctuates.    (e) The induction level may be made to vary with time in a preferred manner, including matching a control signal that is proportional to a reference induction level.
The varying voltage may be generated directly by an active voltage source, or the varying voltage may be generated indirectly, such as by current transformer secondary current flowing through an adjustable impedance. The key elements are a magnetic body, a conductive winding that magnetically interacts with the magnetic body, and a means of causing the induced voltage to have the appropriate waveform and magnitude.
A conductive winding that is utilized for controlling induction level may be a permanent winding that is also used for other purposes, or it may be a dedicated winding (permanent or temporary) provided solely for the purpose of controlling induction level.
These principles are most readily applied to magnetic bodies that are configured to have a relatively uniform magnetic path, such as the magnetic cores of current transformers. Using the principles of the 517 patent, the accuracy of a current transformer may be improved in three ways:    (a) By demagnetizing a current transformer, inaccuracies associated with core magnetization are removed. A demagnetized current transformer can accurately measure d-c current and a-c current that has a d-c component.    (b) By keeping the integral over time of induced voltage near zero, a current transformer is better able to measure unsymmetrical currents without quickly transitioning to saturation.    (c) By reducing the amount that the magnetic flux in the core fluctuates, inaccuracies associated with magnetizing current may be greatly reduced and the accuracy of a current transformer may be greatly improved.
Some embodiments of the present invention utilize voltage pulses to control the magnetization of a current transformer magnetic core, rather than a continuously adjustable voltage (as discussed in the 517 patent). The 157 patent discusses this type of switched-voltage magnetic control. Since the 157 patent incorporates the 517 patent by reference, the 157 patent cannot be incorporated herein by reference (per patent office rules). So, for completeness, it is necessary to include herein some of the information contained in the 157 patent.
FIGS. 1 to 9 provide prior-art background information. FIGS. 1 and 2 illustrate ordinary current transformers applied without electronic assist. FIGS. 3 to 9 illustrate ordinary current transformers applied with electronic assist in accordance with the 517 patent and the 157 patent. FIGS. 3 to 9 are similar to FIGS. 1 to 7 of the 157 patent. FIGS. 3 and 4 are also similar to FIGS. 1 and 21 of the 517 patent.
FIG. 1 illustrates a simple prior-art current transformer circuit for measuring a-c current. A current transformer CT comprises a magnetic core 12 and a secondary winding 13.
An electric power system conductor 10 has an insulating covering 11. Power system conductor 10 functions as a primary winding of current transformer CT, with only one turn, with a primary electric current J1 flowing in it. Though shown with one end disconnected, power system conductor 10 is normally connected as part of an electric power system.
For clarity, current transformer CT comprises a magnetic core 12 and a secondary winding 13 magnetically coupled to magnetic core 12; a primary (or "first") electric current J1 flows in conductor 10 which is configured as a primary winding of current transformer CT; a secondary electric current J2 flows in secondary winding 13; secondary electric current J2 is generally proportionally smaller than primary electric current J1 by a turns ratio of current transformer CT. (Generally speaking, if a current transformer secondary current is known, then the primary current is calculable as the secondary current multiplied by the turns ratio of the current transformer).
As shown in FIG. 1, secondary winding 13 and resistor R1 are connected in series, so that secondary electric current J2 flows through each of them. A ground connection 14 provides a reference for voltage measurements.
Resistor R1 is a current-sensing resistor with low resistance, and may be thought of as one possible embodiment of a "current-sensing means." Voltage V3, across resistor R1, is proportional to secondary electric current J2, and may be considered to be an information signal that contains information about secondary electric current J2. Resistor R1 functions as a current-sensing means for sensing secondary electric current J2 and provides an information signal containing information about secondary electric current J2.
Winding 13 is shown with ten turns around magnetic core 12. The actual number of turns may vary widely depending on the application. Magnetic core 12 is shown as a solid-core toroid, though wide variation in magnetic core configurations is possible and the illustration is not intended to limit the breadth of application of the invention. Of particular note is the possible use of split-core current transformers, which can be installed around existing conductors without having to thread one end of the primary conductor through the window opening of the current transformer.
A measurement circuit 15 comprises an analog-to-digital circuit 22 and a microcontroller circuit 23. Analog-to-digital converter circuit 22 has a high-impedance voltage-sensing input (connected to conductor 4) to enable sensing of voltage V3 relative to the potential of conductor 5. Analog-to-digital converter circuit 22 receives the information signal (voltage V3) via conductors 4 and 5, and converts the signal to a digital information signal for use by microcontroller 23. Analog-to-digital converter circuit 22 and microcontroller 23 communicate via an interface shown as four conductors, and this interface may vary considerably depending on the particular design.
Microcontroller 23 processes the digital signal, and typically communicates information about the measured current to other equipment or a visual display via multiple conductors 16. Microcontroller 23 may be part of a larger electric power monitor which also measures voltage, in which case microcontroller 23 may utilize the information about the electric current to calculate electric power or electric energy parameters.
FIG. 2 illustrates prior art non-contact a-c current measurement of multiple a-c currents with no electronic assist. FIG. 2 is similar to FIG. 1, except that FIG. 2 shows multiple current transformers (each labeled CT) for measuring multiple primary electric currents (each labeled J1) flowing in multiple power system conductors (each labeled 10). Many components are the same as previously shown, and these components function in the manner previously described. Multiple current-sensing resistors (each labeled R1) are now shown, one for each current transformer. Analog-to-digital converter circuit 22 now has multiple input channels, one for each current-sensing resistor. Analog-to-digital converter circuit 22 may be configured to sample each input channel continuously, or it may be configured to sample only one input channel at once. The number of current transformers and current-sensing resistors connected to a single measurement circuit 15 may vary widely, depending on the application.
FIG. 3 illustrates the general configuration of prior art current measurement utilizing electronic assist, as described in the 517 patent. A controllable voltage device 6 provides an output voltage V1 for magnetic control of current transformer CT. This configuration makes it possible to utilize ordinary current transformers to measure d-c currents and a-c currents having a d-c current component (d-c currents having one or more a-c current components are considered to be the same as a-c currents having a d-c component). Improved accuracy in the measurement of a-c currents is also possible.
Controllable voltage device 6 is connected in series with secondary winding 13 and current-sensing resistor R1, so that secondary electric current J2 flows through each of them. A control circuit 3 now is responsible for both receiving and processing the information signal (voltage V3) and controlling controllable voltage device 6. The dashed lines 60 between control circuit 3 and controllable voltage device 6 indicate control mechanisms by which control circuit 3 controls the connected device (this is the typical meaning of dashed lines connecting from a control circuit throughout this disclosure). The actual control mechanism may vary widely, depending on the particular embodiment.
Control circuit 3 has a high-impedance voltage-sensing input (connected to conductor 4) to enable sensing of voltage V3 relative to the potential of conductor 5. As before, voltage V3 across resistor R1 is proportional to secondary electric current J2. Voltage V2 is the voltage across secondary winding 13, which is the induced voltage generated by changing flux in magnetic body 12 plus any voltage drop associated with current J2 flowing through stray winding impedances. Often, the voltage drop associated with secondary current J2 flowing through stray winding impedances is small compared to the induced voltage and may be ignored in some applications. Voltage V1 is the adjustable output voltage of controllable voltage device 6. Please refer to the 517 patent for additional information.
FIG. 4 illustrates a preferred embodiment of the controllable voltage device of FIG. 3, in accordance with the 517 patent. This configuration provides a continuously adjustable bipolar voltage output (output voltage V1) for magnetic control. Many components are the same as previously shown, and these components function in the manner previously described.
Control circuit 3A has an analog-to-digital converter circuit 22 to sense secondary current J2 (as voltage V3 across current-sensing resistor R1), a microcontroller 23 for data processing and control functions, and a digital-to-analog converter circuit 24. Digital-to-analog converter circuit 24 provides an analog voltage signal on conductor 25 that controls the voltage output of controllable voltage device 6A. Analog-to-digital converter circuit 22 and microcontroller 23 communicate via an interface shown as four conductors, and this interface may vary considerably depending on the particular design. Likewise microcontroller 23 communicates with digital-to-analog converter circuit 24 via an interface shown as four conductors, and this interface may vary considerably depending on the particular design. Alternately, the analog-to-digital converter and digital-to-analog converter may be an integral part of the microcontroller.
Controllable voltage device 6A has a voltage control circuit 1A, and a power supply circuit 2A. Voltage control circuit 1A has an operational amplifier 21, with resistors R7 and R8 configured to set the gain of operational amplifier 21. Power supply circuit 2A provides operating power to operational amplifier 21. A positive d-c voltage is provided at terminal VP, a negative d-c voltage is provided at terminal VN, both relative to a common voltage terminal VG.
Control circuit 3A also requires a power supply circuit, which is not shown. These power supply circuits are well-established in the prior art.
Ground connection 14 provides a common reference potential for the various circuits and power supply. If a particular application requires that winding 13 be directly grounded on one side, then resistor R1 may be relocated and connected in series with the opposite side of winding 13. This complicates the measurement of voltage V3 across resistor R1 somewhat, but prior-art differential voltage measurement methods are adequate and may be used.
Operational amplifier 21 must be able to produce voltage in a circuit with relatively large current driven by a current source (a current transformer acts like a current source). A "power operational amplifier" will usually be required, as discussed in the 517 patent.
The type of control configuration shown in FIG. 4 (utilizing an analog-to-digital converter circuit to sense an input signal, a microcontroller to implement a control function based on the input signal, a digital-to-analog converter to produce an analog control signal, and an operational amplifier to produce a voltage proportional to the analog control signal) is well established in the prior art, so additional configuration details will not be described herein. Microcontroller 23 is configured/programmed to implement the control sequences illustrated and discussed in the 517 patent.
FIG. 5 illustrates the use of a power supply circuit 2B and voltage control circuit 1B as a controllable voltage device 6B, providing a switched-voltage output in accordance with the 157 patent. Many components are the same as previously shown, and these components function in the manner previously described. Power supply circuit 2B provides a single d-c (direct-current) voltage output V4 across two terminals: terminal VP, which has a positive polarity relative to second terminal VN. In the configuration shown, the output of power supply circuit 2B does not have any common connection with the rest of the circuit, so that output voltage V4 can be applied so as to result in a positive or negative polarity at the output of voltage control circuit 1B. That is to say, that aside from connections made by electronic switches 26 and 27, the power supply circuit is isolated from the rest of the circuit.
Voltage control circuit 1B functionally comprises two single-pole triple-throw electronic switches which operate in tandem as controlled by control circuit 3. Electronic switches 26 and 27 operate simultaneously to cause voltage V1 to have one of three values: voltage V1 having positive polarity equal in magnitude to power supply voltage V4, voltage V1 having negative polarity and equal in magnitude to power supply voltage V4, and voltage V1 having a magnitude of approximately zero volts (power supply circuit 2B not connected, and electronic switches 26 and 27 providing a low-impedance path for secondary current J2).
Stated another way, voltage control circuit 1B periodically connects power supply output voltage V4 in series with secondary electric current J2. Voltage control circuit 1B also provides a low-impedance path for secondary current J2 during time periods that power supply circuit 2B is not connected in series with secondary current J2. Voltage control circuit 1B and power supply 2B are configured to provide both positive voltage and negative voltage connected in series with secondary electric current J2, the positive voltage and negative voltage being connected one at a time.
Power supply circuit 2B and voltage control circuit 1B operate together to provide an adjustable output voltage (V1) that is effectively a bipolar pulsed voltage.
Speaking of magnetic control in general, the rate of change of magnetic flux in magnetic core 12 is proportional to the voltage induced in secondary winding 13. Generally speaking, in FIG. 5 control circuit 3 controls the voltage pulses at voltage V1 so that the average value over time of the sum of voltage V1 pulses and of voltage drops associated with secondary electric current J2 flowing through loop impedances is approximately equal to the preferred induced voltage in secondary winding 13, thereby causing the rate of change of magnetic flux to be the preferred value.
When using the term "average value over time," the time period over which the averaging occurs is significant. In the context of induced voltage calculations within this disclosure, this period of time is preferably equal to the length of time of an integral number of complete voltage pulse cycles (including any off time that is part of a full cycle). A time period spanning only one voltage pulse cycle will generally provide the most accurate control.
For optimal control, control circuit 3 utilizes characteristics of loop impedances through which secondary electric current J2 flows to optimize the control of voltage control circuit 1B for improved control of the magnetic flux of magnetic core 12. Control circuit 3 uses information signal V3 along with known characteristics of loop impedances to calculate the induced voltage generated in winding 13 by flux changes in magnetic core 12. The voltage pulses at voltage V1 are controlled so that the average value of the voltage induced in the winding is the preferred value. For accurate control, the magnitude of voltage V1 should be part of the calculation implemented by control circuit 3, either as a known voltage based on fixed power supply voltage V4 and the states of electronic switches 26 and 27, or voltage V1 may be directly measured by control circuit 3 (measurement of voltage V1 by control circuit 3 would require an additional connection not shown).
Loop impedances include stray impedances associated with winding 13, stray impedances in various connecting wires and electronic switches, and the impedance of current-sensing resistor R1.
For many applications it is desirable to minimize flux variations, in which case control circuit 3 is configured to cause the average value over time of voltage V1 pulses to be approximately equal to, and have opposite polarity as, the sum of voltage drops associated with current J2 flowing through loop impedances, thereby causing the average value of induced voltage to be near zero, thereby minimizing flux changes. This type of control is illustrated by FIGS. 9A to 9E (discussed below).
Stated another way, control circuit 3 receives voltage V3 (which is an information signal containing information about secondary electric current J2) and uses this information for controlling voltage control circuit 1B in such a way as to control changes of magnetic flux in magnetic core 12, thereby reducing the secondary current error, whereby secondary electric current J2 is caused to be more accurately proportional to primary electric current J1. Control circuit 3 operates while current transformer CT is in service.
FIG. 6 illustrates a development of FIG. 5 in which power supply circuit 2A has two voltage outputs relative to a common terminal VG (similar to FIG. 4). Many components are the same as previously shown, and these components function in the manner previously described. A positive d-c voltage is available at terminal VP, and a negative d-c voltage is available at terminal VN. Voltage control circuit 1C is now somewhat simplified (compared to FIG. 5), utilizing three single-pole single-throw electronic switches 28, 29, and 30. The configuration of FIG. 6 is functionally similar to the configuration of FIG. 5, but is easier to realize in practice, since the electronic switches are considerably simpler and the power supply no longer requires an isolated output. Voltage control circuit 1C and power supply circuit 2A together form controllable voltage device 6C.
In the configuration of FIG. 6 voltage control circuit 1C still provides just three values for output voltage V1. With just electronic switch 28 closed, voltage V1 has positive polarity equal to the voltage provided by power supply terminal VP. With just electronic switch 29 closed, voltage V1 has negative polarity equal to the voltage provided by power supply terminal VN. With just electronic switch 30 closed, a low-impedance path is provided for current J2, and voltage V1 is approximately zero volts. Only one switch is normally closed at a time. For most applications, the voltage magnitude of the power supply positive and negative d-c voltage outputs will be fixed (not adjustable) and will be approximately equal. An optional ground connection 14 provides a reference voltage level for the circuit.
FIGS. 7A to 7E illustrate the magnetic operation of an ordinary prior-art current transformer without electronic assist, similar to FIG. 1 and FIG. 2. The waveforms are based on the current transformer operating a-c primary current in sinusoidal steady-state conditions at time T1. Time T2 is a reference mark for waveform comparison. Time T3 marks a change to d-c primary current. Time T4 marks the time that the current transformer magnetic core saturates due to the d-c primary current.
FIG. 7A illustrates one possible primary current waveform for primary current J1. This is the same reference waveform as shown in FIGS. 8A and 9A. The waveform is simply a sinusoidal a-c current for two cycles, then changes to a positive d-c current at time T3.
FIG. 7B simply illustrates that voltage V1 is continuously zero for an ordinary current transformer without electronic assist.
FIG. 7C illustrates the magnetic flux density waveform Y (of magnetic core 12), with the vertical axis scaled linearly from −100% (negative saturation) to +100% (positive saturation). The current transformer burden is assumed to be resistive, so flux waveform Y is 90 degrees out-of-phase with primary current J1 (FIG. 7A) while primary current J1 is sinusoidal. The magnetic core is seen to quickly saturate when primary current J1 changes to a d-c current.
FIG. 7D illustrates the waveform of secondary electric current error J2E. The secondary electric current error is related to a build-up of a magnetic flux in magnetic core 12. For purposes of this disclosure, "secondary electric current error" is the instantaneous difference between the actual secondary electric current (J2) and an ideal secondary electric current calculated as the instantaneous primary electric current (J1) divided by the turns ratio of the current transformer (CT). FIG. 7D shows that secondary current error J2E is relatively large (when compared to FIGS. 8D and 9D with electronic assist). The error becomes 100% (when expressed as a percentage of ideal secondary current) at time T4 when the current transformer magnetic core saturates and secondary current J2 goes to zero magnitude.
FIG. 7E illustrates the waveform of secondary electric current J2. The effects of secondary current error J2E are fairly clear: the sinusoidal waveform is time shifted relative to primary current J1, and the current transformer is unable to maintain a d-c current output. A less-apparent magnitude error is also present during a-c current operation (prior to time T3).
FIGS. 8A to 8E illustrate the magnetic operation of a prior-art current transformer with electronic assist using a continuously adjustable output voltage (this is functionally similar to the configuration of FIG. 4 if control circuit 3A operates to compensate for secondary burden).
FIG. 8A illustrates one possible primary current waveform for primary current J1. This is the same reference waveform as shown in FIGS. 7A and 9A.
FIG. 8B simply illustrates that voltage V1 is continuously controlled to compensate for secondary burden. Since the burden (the sum of all loop impedances) is assumed to be resistive, voltage V1 has a waveform that is virtually the same as secondary current J2 (FIG. 8E), which, due to the high accuracy of the assisted current transformer, is virtually the same waveform as primary current J1 (FIG. 8A).
FIG. 8C illustrates the magnetic flux density waveform Y (of magnetic core 12), with the vertical axis scaled linearly from −100% (negative saturation) to +100% (positive saturation). Ideal burden compensation is assumed, so the flux density remains very close to zero.
FIG. 8D illustrates the waveform of the secondary electric current error J2E. Since secondary current error J2E is closely related to the magnetic flux density Y of the magnetic core, and the flux density remains near zero as shown in FIG. 8C, current error J2E is near zero.
FIG. 8E illustrates the waveform of secondary electric current J2. Since secondary current error J2E is near zero, the waveform of secondary current J2 is almost identical to primary current J1 (though secondary current J2 is smaller than primary current J1 by the turns ratio of current transformer CT).
FIGS. 9A to 9E illustrate the magnetic operation of a prior-art current transformer with electronic assist using a switched-voltage output (this is functionally similar to the configuration of FIGS. 5 and 6 if control circuit 3 operates to compensate for secondary burden).
FIG. 9A illustrates one possible primary current waveform for primary current J1. This is the same reference waveform as shown in FIGS. 7A and 8A.
FIG. 9B illustrates that voltage V1 is now controlled with a pulse-width-modulated type of control to compensate for secondary burden. Control circuit 3 controls voltage V1 so that its average value over a brief period of time is approximately equal to the continuous voltage shown in FIG. 8B. The pulse frequency shown was chosen for illustrative purposes; it is normally advantageous to have a pulse frequency that is fast relative to the highest frequency that is to be measured. The relatively slow pulse frequency shown exemplifies a small time lag that is inherent in a PWM control response; this is most visible immediately after time T3.
FIG. 9C illustrates the magnetic flux density waveform Y (of magnetic core 12), with the vertical axis scaled linearly from −100% (negative saturation) to +100% (positive saturation). The pulse-width-modulated voltage output provides burden compensation that is somewhat less than ideal, which results in a somewhat jagged flux waveform. However, flux still remains relatively close to zero, and flux control is still good.
FIG. 9D illustrates the waveform of the secondary electric current error J2E. Since secondary current error J2E is closely related to the magnetic flux density Y of the magnetic core (and the magnetic core does not saturate), current error J2E has a waveform that is similar to the waveform of magnetic flux Y. The current error waveform J2E is seen to be very small relative to the waveform of FIG. 7D (the case of the uncompensated current transformer).
FIG. 9E illustrates the waveform of secondary electric current J2. Since secondary current error J2E is very small, the waveform of secondary current J2 is almost identical to primary current J1.
FIGS. 9A to 9E illustrate how switched-voltage pulses may be used to approximate the burden-reducing compensation described in the 517 patent. Using similar principles, switched voltages can be utilized to approximate other operating modes described in the 517 patent:                (a) The induction level of a magnetic body may be caused to transition from a known induction level to a preferred induction level. (A preferred induction level of zero may be chosen to demagnetize a magnetic body).        (b) When the induction level is not known, a preferred induction level may be established by changing the induction level of the magnetic body from an unknown induction level to a known induction level (such as saturation) and then to the preferred induction level.        (c) A preferred induction level may be maintained by causing the induced voltage across the winding to have an average value near zero (or by causing the integral of induced voltage to not exceed a predetermined value).        (d) The induction level may be made to vary with time in a preferred manner, including matching a control signal that is proportional to a reference induction level.
Refer to the 157 patent for additional information about utilizing switched voltages for magnetic control of current transformers.

Apparatus for measuring multiple electric currents utilizing multiple current transformers


Lattice-mismatched semiconductor devices having a substrate, a first epitaxial film disposed thereon, a dielectric material, and a second epitaxial film. The first epitaxial film contains etch pits that extend from the outer surface of the first epitaxial film into the first epitaxial film. The dielectric material is disposed within the etch pits and blocks at least some of the threading dislocations in the first epitaxial film from propagating into the second epitaxial film. Semiconductor devices containing a silicon (Si) substrate or a silicon germanium (SiGe) substrate, a germanium (Ge) film disposed over the substrate, and a dielectric material. Methods for producing such semiconductor devices.

Increasing operating speeds and computing power of microelectronic devices have led to semiconductor structures having increasing complexity and functionality. Hetero-integration of dissimilar semiconductor materials, for example, III-V materials, such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium (Ge) with a silicon (Si) or silicon-germanium (SiGe) substrate, is an attractive path for future fabrication. One technique for such integration is often referred to as "heteroepitaxial growth" or "heteroepitaxy," epitaxial growth of a semiconductor material over a semiconductor substrate, for example, by chemical vapor deposition ("CVD") or molecular beam epitaxy ("MBE"), where the semiconductor material, when fully relaxed, has a different lattice constant than the underlying substrate. In particular, heteroepitaxial growth can be advantageously employed to: (i) fabricate semiconductor devices for which lattice-matched substrates are not commercially available, e.g., some types of ultra-high speed radio-frequency (RF) or optoelectronic devices; (ii) combine multiple new materials on a single wafer, e.g., Ge for p-channel field-effect transistor (FET) devices and indium gallium arsenide (InGaAs) or indium antimonide (InSb) for n-channel FET devices; (iii) improve performance of the conventional complementary metal-oxide-semiconductor (CMOS) platform by replacing Si, in active areas of some or all transistors on a wafer, with semiconductor materials with higher mobility and saturation velocity than Si, i.e., Ge and/or III-V materials; and (iv) achieve monolithic integration of semiconductor materials with large mismatch to Si with silicon microelectronics in a manner that is minimally, if at all, disruptive to the CMOS process.
Depending on the application, key considerations for using selective heteroepitaxy for fabrication of semiconductor devices include: control of defect density, surface morphology, and degree of relaxation of the desired portions of heteroepitaxial regions; ease of integration of heteroepitaxy into device manufacturing process; and reliability of electrical isolation of the defective regions from the active regions of the heterostructure.
Performance and, ultimately, the utility of devices fabricated using a combination of dissimilar semiconductor materials depend on the quality of the resulting structure. Specifically, a low level of dislocation defects is important in a wide variety of semiconductor devices and processes, because dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties, which, in turn, results in poor material quality and limited performance. In addition, dislocation defects can degrade physical properties of the device material and can lead to premature device failure.
As mentioned above, dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material (often referred to as "heterostructure") due to different crystalline lattice sizes of the two materials. This lattice-mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure. Misfit dislocations form at the mismatched interface to relieve the misfit strain. Many misfit dislocations have vertical components, termed "threading segments," which terminate at the surface. These threading segments continue through all semiconductor layers subsequently added to the heterostructure. In addition, dislocation defects can arise in the epitaxial growth of the same material as the underlying substrate where the substrate itself contains dislocations. Some of the dislocations replicate as threading dislocations in the epitaxially grown material. Such dislocations in the active regions of semiconductor devices such as diodes, lasers and transistors, may significantly degrade performance.
To reduce formation of dislocations and associated performance issues, many semiconductor heterostructure devices known in the art have been limited to semiconductor layers that have very closely (e.g., within 0.1%) lattice-matched crystal structures. In such devices, a thin layer is epitaxially grown on a mildly lattice-mismatched substrate. As long as the thickness of the epitaxial layer is kept below a critical thickness for defect formation, the substrate acts as a template for growth of the epitaxial layer, which elastically conforms to the substrate template. While lattice-matching (or near matching) eliminates dislocations in a number of structures, there are relatively few known lattice-matched systems, limiting the design options for new devices.
Thus, there is a need in the art for versatile and efficient methods of fabricating semiconductor heterostructures that constrain substrate interface defects in a variety of lattice-mismatched materials systems. There is also a need in the art for semiconductor devices utilizing a combination of integrated lattice-mismatched materials with reduced levels of substrate interface defects for improved functionality and performance. There is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than known approaches may allow.
For example, high-quality germanium (Ge) grown epitaxially on silicon (Si) continues to be of interest for many notable applications. Specifically, Ge on Si can be used as a substrate for fabrication of multijunction solar cells (e.g., high-efficiency photovoltaics), high-mobility transistors integrated on Si substrates (e.g., strained Si CMOS technology), and near infrared photodetectors, among other devices. However, difficulties exist in achieving high-quality Ge on Si, as there is a 4.2% lattice-mismatch and 116% thermal expansion coefficient (TEC) mismatch between Ge and Si. The lattice-mismatch can result in relatively high threading dislocation densities (TDDs) on the order of 108-109 cm−2 and the TEC mismatch can lead to microcracks in Ge films or their delamination as the Ge film thickness exceeds several micrometers and the material cools from a growth temperature to room temperature. Further, threading dislocations (TDs) in heteroepitaxial films often propagate to the film surface.
Conventional attempts to reduce the defect density in Ge on Si include using graded GexSi1-x buffer layers, thermal annealing, selective epitaxial overgrowth (SEG), strained-layer deflection, and aspect ratio trapping (ART). These methods have had varying degrees of success. Disadvantages associated with such methods include the need to use thick buffer layers, high temperature processing, and limited area growth.
The ART technique utilizes high-aspect-ratio holes or trenches etched through dielectric films to trap dislocations, reducing dislocation density. ART techniques can avoid the need for thick buffers and high thermal budgets that are typical of other heteroepitaxial techniques. However, the ART technique may not be effective with holes or strips with dimensions greater than 1 μm.
Thus, there is a need to provide heteroepitaxial films on lattice-mismatched substrates (such as, Ge films on Si substrates, among others) and methods for reducing defects when forming semiconductor layers/devices.

Low defect density lattice-mismatched semiconductor devices and methods of fabricating same