A circuit of a structure in which one end of a serial connection circuit of two capacitors is grounded, and the potential of another end is switched in a constant cycle is disclosed as a voltage generating circuit applicable to a half Vcc generating circuit, a substrate bias circuit, or the like. Electrical connection between a connection point between the capacitors and a predetermined load and electrical connection between the connection point and ground are controlled so that the potential of the connection point attains to be a constant potential in accordance with the ratio between the capacitance of the two capacitors in response to switching of the potential of the "another end" to a predetermined potential. As a result, a half Vcc generating circuit with reduced power consumption and layout area and a substrate bias circuit capable of biasing a semiconductor substrate to an arbitrary potential are realized.

1. Field of the Invention
The present invention relates generally to voltage generating devices and operating methods thereof and, more particularly, to a voltage generating device capable of generating a voltage at an arbitrary level with small power consumption and an operating method thereof.
2. Description of the Background Art
At present a semiconductor integrated circuit device such as a semiconductor memory device or the like is provided with a circuit which supplies a predetermined constant voltage to a predetermined part of the semiconductor integrated circuit device at least in a period in which an internal circuit of the semiconductor integrated circuit operates.
FIG. 7 is a schematic diagram illustrating a structure of a half Vcc generating circuit, which is an example of such a circuit.
A half Vcc generating circuit is generally used in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or the like for precharging a bit line or an I/O line to a potential which is half a supply potential Vcc (normally 5 V), for fixing one electrode of a capacitor constituting a memory cell to a potential which is half the supply potential Vcc, in a period in which reading and writing of data are not performed, and so forth.
FIG. 8 is an equivalent circuit diagram illustrating a structure of a memory cell of a DRAM. Referring to FIG. 8, each memory cell of a DRAM includes a MOS transistor Tr, which has a gate connected to a word line WL, a drain connected to a bit line BL, and a source, and a capacitor C. One electrode of the capacitor C is connected to the source of the transistor Tr, and another electrode is connected to a so-called cell plate, a substrate portion in which a memory cell array is formed, in common with electrodes of capacitors C of all other memory cells (not shown). The cell plate is fixed to a potential which is half a supply potential Vcc to fix the potential of one electrode of the capacitor of each memory cell.
A bit line and an I/O line transmit data of logical values "1" and "0" as rise of potential (or fall of potential) and fall of potential (or rise of potential), respectively, to a circuit or signal line in the next stage. Therefore, if the bit line and I/O line are precharged to Vcc/2, which is a potential intermediate between the supply potential Vcc and a ground potential 0 V, in reading of data, it becomes easy for the potentials of the bit line and the I/O line to change according to whether read data is of the logical value "0" or of the logical value "1".
Next, the structure and operation of a conventional half Vcc generating circuit will be described with reference to FIG. 7.
A conventional half Vcc generating circuit includes resistors 1-3, which are connected in series with each other between a supply terminal Tcc to be supplied with a supply potential Vcc and ground GND, and an N-channel MOS transistor 4 and a P-channel MOS transistor 5, which are connected in series with each other between the supply terminal Tcc and the ground GND. The gates of transistors 4 and 5 are connected to the connection point between registers 1 and 2 and the connection point between registers 2 and 3, respectively. The potential of the connection point (a node N3) between transistors 4 and 5 is used as an output voltage Vout of the half Vcc generating circuit.
Current flows from the supply terminal Tcc through resistors 1-3 to the ground GND in a period in which the supply potential Vcc is supplied to supply terminal Tcc, so that the potential of the connection point between resistors 1 and 2 is a potential lower than the supply potential Vcc by a voltage drop caused by resistor 1, and the potential of the connection point between resistors 2 and 3 is a potential lower than the potential of the connection point between resistors 1 and 2 by a voltage drop caused by resistor 2. The values of resistance of respective resistors 1-3 are set so that the potential of the connection point (a node N1) between resistors 1 and 2 is a potential (Vcc/2+Vthn) which is higher than a potential Vcc/2, which is half the supply potential Vcc, by the threshold voltage Vthn of transistor 4 and so that the potential of the connection point (a node N2) of registers 2 and 3 is a potential (Vcc/2-Vthp) which is lower than the potential Vcc/2, which is half the supply potential Vcc, by the threshold voltage Vthp of transistor 5.
Transistor 4 is brought to ON state and supplies positive charge from the supply terminal Tcc to node N3 in a case where its gate potential Vgn is higher than a potential (Vout+Vthn) which is higher than the potential Vout of node N3 by its threshold voltage Vthn, i.e. in a case where the following expression is realized. EQU Vout<Vgn-Vthn
Transistor 5 is brought to ON state and supplies negative charge from the ground GND to node N3 in a case where its gate potential Vgp is lower than a potential (Vout-Vthp) which is lower than the potential Vout of node N3 by its threshold voltage Vthp, i.e. in a case where the following expression is realized. EQU Vout>Vgp+Vthp
Therefore, in a case where the potentials of node N1 and N2 are (Vcc/2+Vthn) and (Vcc/2-Vthp), respectively, if the potential Vout of node N3 becomes higher than Vcc/2, transistor 4 is brought to OFF state while transistor 5 is brought to ON state, so that the potential Vout of node N3 is lowered. However, if the potential Vout of node N3 becomes lower than Vcc/2, transistor 5 is brought to OFF state while transistor 4 is brought to ON state, so that the potential of node N3 rises. Accordingly, the potential Vout of node N3 is controlled to be always approximately Vcc/2 by setting the gate potentials Vgn and Vgp of transistors 4 and 5 to such potentials. In a state wherein the potential Vout of node N3 is stable at Vcc/2, transistors 4 and 5 are both in OFF state, so that no current flows from the supply terminal Tcc through transistors 4 and 5 to the ground GND.
FIG. 11 is a schematic diagram illustrating a structure of a substrate bias circuit, which is another example of a circuit which generates a voltage at a predetermined level in a semiconductor integrated circuit device.
A substrate bias circuit is provided in a semiconductor integrated circuit device for preventing malfunction of a circuit and degradation of electric characteristics of a circuit due to fluctuation in the potential of a semiconductor substrate.
FIG. 13 is a schematic diagram illustrating an example of a general structure of a data providing circuit in a semiconductor integrated circuit device. Referring to FIG. 13, the providing circuit generally includes two N- channel MOS transistors 12, 13 connected in series with each other between a supply potential T.sub.DD, which is to be supplied with a supply potential V.sub.DD predetermined according to the potential level of an input/output signal, and ground GND. Potentials V1, V2 at levels complementary to each other and corresponding to data to be provided are applied from a circuit (not shown) in the preceding stage to the gates of transistors 12 and 13, respectively. The connection point between transistors 12 and 13 is connected, as an output terminal of the providing circuit, to an I/O pin (not shown).
Accordingly, in a period in which transistor 12 is in ON state, transistor 13 is in OFF state, and, conversely, in a period in which transistor 13 is in ON state, transistor 12 is in OFF state. Therefore, a high potential V.sub.DD of the supply terminal T.sub.DD or a low potential Vss of the ground GND appears onto the connection point between transistors 12 and 13 according to the output potentials v1, v2 of a circuit in the preceding stage.
If the potential of a semiconductor substrate becomes higher than the potential of the I/O pin, charge flows from an N.sup.+ region to a P well region in such a providing circuit. FIG. 14 is a diagram for explaining such a phenomenon. FIG. 14 shows a cross sectional view of the structure of transistor 12 (or 13) in FIG. 13.
Referring to FIG. 14, transistor 12 (or 13) includes N.sup.+ regions 200 and 300 formed as a drain and a source, respectively, on a P well 100 formed in a semiconductor substrate 1000 and a gate electrode 400 formed across the portion between N.sup.+ regions 200 and 300 on P well 100 with an insulating film (not shown) interposed therebetween. One N.sup.+ region 200 is connected to a supply terminal T.sub.DD (or ground GND) to receive a high potential T.sub.DD (or a low potential Vss), and the other N.sup.+ region 300 is connected to an I/O pin. Gate electrode 400 receives a signal v1 (or v2) from a circuit in the preceding stage of the providing circuit.
In a case where the potential of P well 100 is 0 V or more, if a negative potential is externally supplied to the I/O pin, for example, the PN junction formed by N.sup.+ region 300 and P well 100 is brought into a forward bias state, so that electrons e.sup.- are supplied from N.sup.+ region 300 to P well 100. If this providing circuit is used in a DRAM, for example, the electrons e.sup.- thus flowing into P well 100 cancel positive charge accumulated in a capacitor C (see FIG. 8.) in a memory cell, so that it happens that storage data in the memory cell is destructed.
In order to avoid such a phenomenon, the potential of semiconductor substrate 100, i.e. the potential of P well 100, may be held at a predetermined negative potential so that the PN junction formed by N.sup.+ region 300 and P well region 100 is not brought to the forward bias state.
FIG. 15 is a schematic diagram illustrating a structure of arbitrary one memory cell in a DRAM.
Referring to FIG. 15, when data is written, the potential of a word line WL is brought to a potential (normally a supply potential) of a high level which is considerably higher than the threshold voltage of a transistor Tr for a constant period, while the potential of a bit line BL is brought to the high level (in a case where data to be stored in a memory cell MC is "1") or a low level (in a case where the data to be stored in the memory cell MC is "0") according to the data to be stored in the memory cell MC. This causes a capacitor C to be charged or discharged. After a lapse of the constant period, the potential of the word line WL is brought to a potential (normally a ground potential) at the low level, which is sufficiently lower than the threshold voltage of the transistor Tr, so that in a case where the capacitor C is charged, charge accumulated in the capacitor C does not flow through the transistor Tr to the bit line BL.
When data is read, the potential of the word line WL is fixed at the high level for a constant period, while change in the potential of the bit line BL is detected. If charge is accumulated in the capacitor C, positive charge is supplied from the capacitor C through the transistor Tr to the bit line BL in the constant period, so that the potential of the bit line BL rises. If charge is not accumulated in capacitor C, positive charge is supplied from the bit line BL through the transistor Tr to the capacitor C in the constant period, so that the potential of the bit line BL lowers. Thus, rise of potential is caused in the bit line BL in a case where data "1" is stored in the memory cell MC, while fall of potential is caused in the bit line BL in a case where data "0" is stored in the memory cell MC, so that it is possible to discriminate data stored in the memory cell MC by detecting change in the potential of the bit line BL.
Now, in a period in which neither writing of data nor reading of data is performed, the potential of the word line WL is brought to the low level, so that the transistor Tr is brought to OFF state and cuts off the current flowing between the bit line BL and the capacitor C. However, in a case where the threshold voltage of the transistor Tr is too low, the transistor Tr is brought to ON state by only a little rise of potential in the word line WL due to some cause in a period in which neither of writing of data nor reading of data is performed, so that charge accumulated in the capacitor C leaks through the transistor Tr to the bit line BL. As a result, storage data of the memory cell MC is destructed. In order to avoid such a phenomenon, it is necessary that the threshold voltage of the transistor Tr is set high.
Now, the relation between the threshold voltage V.sub.th of an N-channel MOS transistor (See FIG. 14.) and the square root of the absolute value .vertline.V.sub.SB .vertline. of the potential V.sub.SB of a P well 100 in which the N-channel MOS transistor is represented as V.sub.th =V.sub.tho +.alpha. (.vertline.V.sub.SB .vertline.).sup.1/2. V.sub.th expresses the threshold voltage of the N-channel MOS transistor in a case where V.sub.SB =0 V, and .alpha. is a constant. Specifically, the threshold voltage of the N-channel MOS transistor is larger as the potential of the substrate in which the N-channel MOS transistor is formed is a negative potential with a larger absolute value. Accordingly, in order to suppress generation of leakage of charge from the capacitor C to the bit line BL due to fluctuate in the potential of the word line WL, a semiconductor substrate in which a memory cell MC is formed may be held at an appropriate negative potential. As described above with reference to FIGS. 13 to 15, it is necessary to bias a semiconductor substrate to a certain constant negative potential V.sub.BB in order to solve various disadvantages. A substrate bias circuit is a circuit provided for that purpose.
Next, referring to FIGS. 11 and 12, the structure and operation of a conventional substrate bias circuit will be described.
FIG. 12 is a timing chart showing potential waveforms of control signals .PHI.1, .PHI.2 supplied to the substrate bias circuit in FIG. 11.
The substrate bias circuit includes inverters 5 and 9 receiving driving signals .PHI.1 and .PHI.2 of phases opposite to each other as shown in FIG. 12 (a) and (b), respectively, a capacitor 6 and a P-channel MOS transistor 8 which are connected in series with each other between an output terminal of inverter 5 and ground GND, and a capacitor 10 and a P-channel MOS transistor 11 which are connected in series with each other between an output terminal of inverter 9 and the ground GND. The potential of the connection point (a node N5) between capacitor 10 and transistor 11 is applied to the gate of transistor 8, and the ground potential is applied to the gate of transistor 11.
The substrate bias circuit further includes a P-channel MOS transistor 7 which is diode-connected. The gate of transistor 7 is connected to the connection point (a node N4) between capacitor 6 and transistor 8. The output voltage of inverter 5 is used as back gate voltages of transistors 7 and 8. The output voltage of inverter 9 is used as a back gate voltage of transistor 11.
The output potential of transistor 7 is applied as the output potential V.sub.BB of the substrate bias circuit to a semiconductor substrate (not shown).
If the potential of the driving signal .PHI.2 is switched from a high level to a low level (a time t1 in FIG. 12 (b)) in a period in which the potential of the driving signal .PHI.1 is at the low level, the potential of node N5 is raised by coupling of capacitor 10. The back gate voltage of transistor 11 is brought to the high level to cause transistor 11 to be brought to ON state, so that node N5 is electrically connected to the ground GND. As a result, the potential of node N5 is lowered. Such fall in the potential of node N5 causes transistor 8 to be brought to ON state, so that positive charge is pulled out of node N4 through transistor 8 to the ground GND.
Next, if the potential of the driving signal .PHI.1 is switched from the low level to the high level (a time t2 in FIG. 12), the output potential of inverter 5 is brought to the low level, so that charges are discharged from capacitor 6. This causes negative charge to be supplied from capacitor 6 to node N4, so that the potential of node N4 starts to fall to be negative.
The potential of node N5 is the ground potential 0 V, so that if the potential of node N4 becomes a negative potential, transistor 8 is brought to OFF state so that node N4 is electrically separated from the ground GND. If the potential of node N4 becomes such a negative potential, transistor 7 is brought to ON state. Accordingly, negative charges are discharged from the capacitor 6 through node N4 and transistor 7 in response to switching of the driving signal .PHI.1 from the low level to the high level.
The supply of the negative charge from capacitor 6 to node N4 causes the potential of node N4 to be finally a negative potential (-Vcc) having the same absolute value as that of the supply potential Vcc. Accordingly, with such discharge of negative charges, the output potential V.sub.BB of transistor 7 becomes a potential (-Vcc+Vthp) which is higher than the negative potential (-Vcc) having the same absolute value as that of the supply potential by the threshold voltage Vthp of transistor 7.
Next, if the driving signal .PHI.1 is switched from the high level to the low level in a period in which the potential of the driving signal .PHI.2 is at the low level (a time t3 in FIG. 12), the potential of node N4 rises, so that transistor 7 is brought to OFF state. This causes node N4 to be electrically separated from the semiconductor substrate.
Next, if the driving signal .PHI.2 is switched from the low level to the high level (a time t4 in FIG. 12), the output potential of inverter 9 is brought to the low level, so that negative charge is supplied from capacitor 10 to node N5, and thus the potential of node N5 becomes a negative potential. The back gate voltage of transistor 11 is brought to the low level to cause transistor 11 to be brought to OFF state, so that all the negative charge discharged from capacitor 10 is supplied to the gate of transistor 8. The potential of node N4 is the ground potential 0 V, so that transistor 8 is brought to ON state in response to the supply of the negative charge to the gate. This causes the potential of node N4 to return to the ground potential 0 V.
By repeating the circuit operation as described above, an approximately constant negative potential (-Vcc+Vthp) is provided from transistor 7 to bias the semiconductor substrate.
As described above, a voltage generating circuit which generates a voltage at a predetermined level in a semiconductor integrated circuit device is generally a circuit such as a half Vcc generating circuit (FIG. 7) in which the gate potentials of a plurality of MOS transistors connected in series with each other are set to an appropriate potential obtained by division of resistance so as to fix the connection points between those MOS transistors to a desired potential or a circuit of a so-called charge pumping type such as a substrate bias circuit (FIG. 11) in which charging and discharging of a capacitor are performed alternately to release a constant amount of charge in constant timing so as to generate a desired voltage. However, the circuits of such structures have problems as will be described in the following.
First, problems of a circuit of the former structure will be described with reference to FIGS. 7, 9 and 10.
FIG. 9 is a cross sectional view illustrating a structure of transistor 4 in FIG. 7. FIG. 10 is a cross sectional view illustrating a structure of transistor 5 in FIG. 7.
Referring to FIG. 7, a through current flows constantly from the supply terminal Tcc through resistors 1-3 to the ground GND in a period in which the supply potential Vcc is supplied to the supply terminal Tcc, i.e. in a period in which the half Vcc generating circuit operates. Accordingly, the power consumption of the conventional half Vcc generating circuit is large, and there is a problem that inhibits the approach to low power consumption, which is been requiring in many fields including the field of semiconductor integrated circuit devices at the present time.
Although the threshold voltage Vthn of transistor 4 and the threshold voltage Vthp of transistor 5 are set so that both of transistors 4 and 5 are not brought to ON state at the same time, if the threshold voltage of transistor 4 is different from the set value Vthn, or the threshold voltage of transistor 5 is different from the set value Vthp, there is a period in which both of transistors 4 and 5 are in ON state, so that a through current flows from the supply terminal Tcc through transistors 4 and 5 to the ground GND.
For example, if the threshold voltage of transistor 4 is lower than the set value Vthn, transistor 4 is in ON state even if the potential Vout of node N3 is higher than Vcc/2. On the other hand, if the potential Vout of node N3 is higher than Vcc/2, transistor 5 is in ON state. Accordingly, both of transistors 4 and 5 are in ON state, and a through current flows between the supply terminal Tcc and the ground GND.
As described above, the conventional half Vcc generating circuit also has a problem that a through current is increased due to irregularity in the threshold voltage of a MOS transistor in manufacture, i.e. the power consumption tends to be increased.
In order to reduce the current flowing between resistors 1 to 3, the values of resistance of resistors 1 to 3 may be increased. A resistive element is provided as a so-called diffusion resistor formed by diffusing impurities of an N type or a P type on a semiconductor substrate. The value of resistance of a diffusion resistor is determined by the ratio between the lengths of two sides of a region (normally rectangular) in which impurities are diffused. The value of resistance of a resistor element is larger as the ratio of the length of the side parallel to the direction of the flow of current to the length of another side vertical to the direction of the flow of the current is larger. Therefore, in order to increase the values of resistance of resistors 1 to 3 in FIG. 7, the layout areas of these respective resistors 1-3 on the semiconductor substrate are increased. Such increase in the layout areas of the components is unfavorable because it inhibits large scale integration of a semiconductor integrated circuit device.
Furthermore, also in the view of a circuit operation of the conventional half Vcc generating circuit as will be described in the following, it difficult to reduce the current flowing between resistors 1 to 3.
It is assumed that the potential Vout of node N3 becomes a potential (Vcc/2-.alpha.) which is lower than a potential (Vcc/2) to be originally taken because of influence of the capacitance of a load to which the potential Vout is to be applied or the like. In such a case, transistor 4 is brought to ON state, so that in FIG. 9, a channel is formed between one N.sup.+ region 200 and the other N.sup.+ region 300. This causes an insulating film (not shown) under gate electrode 400 to function as a capacitor which receives the potential of node N1 at one electrode and receives the potential of the channel at another electrode. The potential of the channel is between the potential of N.sup.+ region 200, i.e. the potential Vout (Vcc/2-.alpha.) of node N3, and the potential of N.sup.+ region 300, i.e., the supply potential Vcc.
On the other hand, if the potential Vout of node N3 becomes a potential (Vcc/2+.alpha.) which is higher than the potential (Vcc/2) to be originally taken, transistor 4 is brought to OFF state, so that in FIG. 9, no channel is formed between N.sup.+ regions 200 and 300. Accordingly, in such a case, the insulating film under the gate electrode 400 operates as a capacitor which receives the potential of node N1 at one electrode and receives the potential of P well 100 at another electrode. P well 100 is biased to approximately -3 V by a substrate bias circuit or the like, for example, (in a case where the supply potential Vcc is 5 V).
Accordingly, the capacitance between the gate of transistor 4 and the drain of transistor 4 is changed by the switching operation of transistor 4 due to fluctuations in the potential Vout of node N3, so that a charge and discharge current for the capacitance between the gate and drain flows between node N1 and the gate of transistor 4. As a result, the potential of transistor 4 fluctuates from the potential (Vcc/2+Vthn) to be originally taken. Such a phenomenon occurs in transistor 5 as well.
Specifically, if the potential Vout of node N3 is higher than the potential (Vcc/2) to be originally taken, transistor 5 is brought to ON state, so that in FIG. 10, a channel is formed between P.sup.+ regions 600 and 700. Therefore, an insulating film (not shown) under gate electrode 800 operates as a capacitor which receives the potential of node N1 at one electrode and receives the potential of the channel at another electrode. In such a case, the potential of the channel is between the potential of P.sup.+ region 600, i.e. the ground potential 0 V, and the potential of P.sup.+ region 700, i.e. the potential Vout Vcc/2+.alpha.) of node N3.
On the other hand, if the potential Vout of node N3 is lower than the potential (Vcc/2) to be originally taken, transistor 5 is in OFF state, so that no channel is formed between P.sup.+ regions 600 and 700. Therefore, the insulating film under gate electrode 800 operates as a capacitor which receives the potential of node N1 at one electrode and receives the potential of N well 500 at another electrode. N well 500 is normally biased to approximately 5 V (in a case where the supply potential Vcc is 5 V).
Accordingly, the switching operation of transistor 5 due to the fluctuations in the potential Vout of node N3 changes the capacitance between the gate and drain of transistor 5. Therefore, a charge and discharge current for the capacitance between the gate and the drain flows between node N2 and the gate of transistor 5, so that the gate potential of transistor 5 fluctuates from the potential (VCc/2-Vthp) to be originally taken.
As described above, if the gate potentials of transistors 4 and 5 fluctuate, the potential of node N3 also fluctuates, so that a correct potential (Vcc/2) is not provided from the half Vcc generating circuit. In order to avoid such a problem, it is necessary to increase the current flowing from the supply terminal Tcc through resistors 1-3 to the ground GND so that the current flowing between node N1 and the gate of transistor 4 for charging and discharging of the capacitance between the gate and drain of transistor 4 and the current flowing between node N2 and the gate of transistor 5 for charging and discharging of the capacitance between the gate and drain of transistor 5 are sufficiently smaller as compared with the current flowing from the supply terminal Tcc through resistors 1-3 to the ground GND.
If the current flowing from the supply terminal Tcc through resistors 1-3 to the ground GND is sufficiently larger than such a charge and discharge current, the potential of node N1 is not fluctuated so largely by the current flowing from node N1 to the gate of transistor 4 and the current flowing from the gate of transistor 4 to node N1, and, similarly, the potential of node N2 is not fluctuated so largely by the current flowing from node N2 to the gate of transistor 5 and the current flowing from the gate of transistor 5 to node N2.
However, increase in the current flowing from the supply terminal Tcc to the ground GND, i.e. the through current, leads to further increase in the power consumption.
As described above, a voltage generating circuit of such a structure as representated by the conventional half Vcc generating circuit has a problem that it is disadvantageous to the realization of low power consumption and large scale integration.
Now, problems of the latter voltage generating circuit will be described with reference to the substrate bias circuit in FIG. 11.
The latter voltage generating circuit is constructed so that negative charge is discharged from capacitor 6 in a constant cycle to turn on diode-connected MOS transistor 7 provided for supplying the discharged negative charge to a semiconductor substrate. Therefore, the output voltage V.sub.BB of a substrate bias circuit is limited to a voltage (-Vcc+Vthp) which is higher than a negative voltage having the same absolute value of that of a signal for charging capacitor 6, i.e. the maximal voltage level Vcc of an output signal of inverter 5, by the threshold voltage Vthp of MOS transistor 7. Therefore, according to the conventional substrate bias circuit, it is impossible to bias the semiconductor substrate to an arbitrary potential.
Specifically, it is only possible to adjust the substrate bias voltage only by adjusting the threshold voltage Vthp of the MOS transistor. The threshold voltage Vthp of the MOS transistor is nearly 0.8 V, and it cannot be changed so largely even by adjusting conditions of manufacture of the MOS transistor or the like. Therefore, in a semiconductor integrated circuit device in which the supply potential Vcc is 5 V, for example, the substrate bias voltage V.sub.BB is specified to be nearly -4.2 V.
However, recently, it is proposed to use a supply potential Vcc of approximately 3 V, which is lower than 5 V, and to bias the semiconductor substrate to a negative potential higher than in the case of conventional devices in order to further enhance the operating speed of the semiconductor integrated circuit device. The operating speed of the semiconductor integrated circuit device is known to become slower as the semiconductor substrate is biased to a lower negative potential. However, it is impossible to avoid such problems as described above unless the semiconductor substrate is biased to a potential which is low to a certain extent.
For example, in a semiconductor integrated circuit device in which the supply voltage is 5 V, if the substrate bias voltage V.sub.BB is lowered to nearly -4.2 V, it is difficult to further enhance the operating speed of the device.
Accordingly, in order to avoid such problems and further enhance the operating speed of the device as well, it is currently proposed to set the supply voltage Vcc to about 3 V and set the substrate bias voltage V.sub.BB to about -1.5 V, for example.
However, according to the conventional substrate bias generating circuit, the substrate bias voltage V.sub.BB is limited to -3 V+0.8 V, i.e. about -2.5 V.
As described above, according to the latter voltage generating circuit, its output voltage is determined almost uniquely by the supply voltage Vcc, so that it is difficult to further enhance the operating speed of a semiconductor integrated circuit device.

Voltage generating device generating a voltage at a constant level and operating method thereof


A device and method for controlling the changing operation of an on-load tap changer (LTC) that interrupts current passing the current zero point of a commercial frequency are provided. The device may include a current zero point detecting unit that detects a zero point in the waveform of current passed through the LTC, a current zero point cycle measuring unit that measures the cycle of the current zero point detected by the current zero point detecting unit, a commercial frequency determining unit that generates an output signal when the cycle of the current zero point measured by the current zero point cycle measuring unit corresponds to a commercial frequency, and an actuation signal output unit that outputs an actuation signal used to have the LTC carry out tap changing operation in response to the output signal of the commercial frequency cycle determining unit.

1. Field of the Invention
The present invention relates to a device and method for controlling the changing operation of an on-load tap changer that changes the tap of a transformer.
2. Description of the Related Art
It has been well known that the on-load tap changer changes the tap of a transformer in a load operation state to change and adjust the turn ratio of secondary winding/primary winding of the transformer, in other words, changes and adjusts the transformation ratio.
The on-load tap changer is driven by a motor operation mechanism to operate. The mechanism responds to a remote actuation command from an automatic voltage regulating relay (normally provided in the main control room) that continuously monitors the voltage state of the load of the transformer or from an operator who monitors the operation state in the main control room. The mechanism then operates the on-load tap changer to regulate voltage at the secondary side of the transformer for a dropped amount in the secondary voltage if for example the voltage of the load connected to the secondary side of the transformer drops.
The operation of the on-load tap changer necessitates bridging between taps during the changing operation, and a current limiting resistor is employed in a circuit to limit the bridging current between the taps during the bridging operation. This type of device is called "resistor type on-load tap changer."
According to conventional techniques, the current interruption with the resistor type on-load tap changer is normally successful during one-tap changing operation if the following conditions are satisfied. These ideas have been adopted as a Japanese standard for on-load tap changers (on-load tap changer JEC2220) and an international standard (IEC-214), and performance testing methods, assessments and the like have been established.
1) Interrupting current for use is at a commercial frequency of 50 Hz or 60 Hz.
2) Current is interrupted at a current zero point.
If tap changing operation is carried out in the above described conditions, the on-load tap changer can normally interrupt current and successfully make a connection to a target tap.
A conventional on-load tap changer therefore regulates voltage to a prescribed level at the load side of a transformer provided that the current interruption conditions in the above 1) and 2) are satisfied. Therefore, the changing operation is carried out in response to an actuation command from the automatic voltage regulating relay or the operator as described above without monitoring for the presence/absence of a current zero point in the waveform of current actually passing through the on-load tap changer or measuring the cycle of the current zero point.
However, if the load connected to the transformer is special, for example if power is supplied to a load such as an AC electric railcar or a flicker, or if a plurality of on-load tap changing transformers are operated in parallel, the following disadvantage is encountered.
For a special load, for example, the supplied current may become current with a distorted waveform including a harmonic component and may not pass a current zero point at predetermined intervals unlike a normal commercial frequency.
If the on-load tap changer is operated by current with such a distorted waveform because of the special load, the interrupting current does not pass a current zero point in the cycle of a commercial frequency. If the cycle is prolonged in particular, the duration of arc discharge from the opening to the extinction of the arc is prolonged, so that the arc discharge could continue for not less than 10 ms that is the period tolerated for arc generation that can normally be interrupted, in other words, the arc cannot be extinguished within a normal changing period. At worst, if the arc cannot be extinguished before the main contact is closed on the next tap side, the arc current is passed, which could give rise to a serious accident such as short-circuiting between the taps.
When a plurality of on-load tap changing transformers are provided and operated in parallel with a normal load (operating at a commercial frequency) and power is supplied to the load, even slight time difference in changing operation between the on-load tap changers can generate one tap differential voltage at the parallel arrangement of transformers, and circulating current superposed with DC current is passed between the transformers arranged in parallel because of the tap differential voltage.
The on-load tap changers are adjusted by driving shafts that couple the motor operation mechanisms that drive the on-load tap changers to the on-load tap changers so that the on-load tap chargers operate in timing as similar as possible in order to reduce the time to pass of the circulating current as much as possible and the temperature rise of the transformers caused by the circulating current as much as possible.
However, it would be difficult to adjust the plurality of tap changers to be in the same timing for structural reasons, and very small time difference for changing operation is tolerated.
Therefore, the circulating current caused by the slight operation timing difference is superposed to diverted load current to each of the transformers and the resulting current is passed to each of the on-load tap changers. The superposed current includes a DC component as disclosed by JP-A-2005-12954 and therefore is transient current that does not pass a current zero point. If one preceding on-load tap changer operates and then a succeeding on-load tap changer operates to interrupt current with slight time difference from the operation of the preceding on-load tap changer during the period before the DC component is attenuated to the level of normal current that passes a current zero point, the current interruption may depart from the current interruption conditions, and the current may not be interrupted normally by the main contact on the interrupting side, which could cause current to be passed with continuous arc discharge for a significant time period. At worst, the current could continue to be passed before the main contact is closed on the next tap side, which could result in a serious accident such as short-circuiting between taps.
According to conventional techniques, however, no specific countermeasure has been suggested to prevent an on-load tap changer from interrupting current with a distorted waveform generated in an environment for a special consumer load (that generates the current waveform of a harmonic component) or current that does not pass a current zero point and is in a cycle other than that of a commercial frequency and no specific countermeasure has been suggested to prevent each on-load tap changer from interrupting transient current superposed with DC current caused by the operation timing difference between the on-load tap changers included in the transformers when the transformers are operated in parallel.

Device and method for controlling changing operation of on-load tap changer


A surge suppression circuit with a thermal cutoff includes a first surge suppressor in series with a first thermal cutoff device between a phase conductor and a neutral conductor. A second surge suppressor in series with a second thermal cutoff device is between the phase conductor and a ground conductor. A third surge suppressor is in series with a low temperature thermal cutoff device between the neutral conductor and the ground conductor. The thermal cutoff temperature of the low temperature thermal cutoff device is lower than the thermal cutoff temperature of the first thermal cutoff device.

1. Field of the Invention
The disclosure relates to electrical surge protector devices.
2. Description of the Related Art
A semiconductor device can be degraded by excessive voltage. Destructive breakdown or damage can occur in semiconductor devices when subjected to transient over-voltages that persist for only a few microseconds. Transient Voltage Surge Suppression (TVSS) devices, referred to interchangeably herein as surge suppressors and voltage-clamping devices, are commonly known for use in suppressing such over-voltage transients to protect voltage-surge intolerant circuitry. TVSS devices include nonlinear, voltage-dependent resistive elements which display electrical behavior similar to that displayed by a pair of series-connected, back-to-back zener diodes. At normal voltages, below the TVSS clamping voltage level, TVSS devices display a high resistance with a small leakage current. When subjected to large transient voltages (above the TVSS device's clamping voltage), the TVSS device may operate in a low resistance region which increases current flow through the device. When the voltage is increased, the TVSS, due to its characteristics, presents a lower resistance path to current to divert most of the current away from circuitry connected to the TVSS. The potentially destructive surge energy can be dissipated or passed through the voltage-clamping (TVSS) device.
Avalanche diode suppressors, metal oxide varistors (MOVs) and selenium surge suppressors can be utilized as TVSS devices with varying advantages and disadvantages, such as an MOV-based TVSS's inherent susceptibility to failure under certain conditions. MOV devices tend to break down when exposed to an elevated voltage over a long period of time. The breakdown can result in some leakage current through the MOV. Also, MOV components can have a tendency to explode when overheated, often with sufficient explosive power to fracture plastic housings and sheet metal enclosures within which they reside. The explosion can destroy everything within the TVSS housing and may possibly shoot hot black powder through small openings in the housing. Various techniques have been developed to protect MOVs from the causative factors leading to such explosive conditions.
One technique for protecting metal oxide varistors (MOVs) requires adding a current fuse in series with the MOV, which trips to an open state to protect the MOV when particular transient over-voltages are detected. Transients with I2 t ratings that are greater than the fuse rating, but just below the MOV rating will blow the fuse, electrically removing the MOV from the over-voltage condition. Under circumstances where the fuse displays an I2t rating such that commonly occurring transients are insufficient to blow the fuse, i.e., from a few to 10,000 amperes, but of insufficient magnitude to force the MOV to its low impedance state, the MOV may be subjected to overheating, possibly leading to thermal runaway. Steady state, abnormal over-voltage conditions below those at which the fuse will blow may also generate sufficiently high currents through the MOV leading to dangerous overheating.
A second common technique for protecting MOVs from overheating due to abnormal steady state or transient over-voltage conditions utilizes a thermal cutoff device (TCO) coupled in series with the MOV. A TCO is an electrical device that senses the temperature of a surface of an object such as an electrical circuit and trips to a high impedance state (open circuit) at a particular maximum rated temperature. When a TCO is connected in series with an MOV, the TCO senses the surface temperature of the MOV and trips to an open circuit at a particular maximum rated temperature, to cut off voltage to the MOV. Thermal cutoff devices, however, like current fuses are not without problems when used within MOV-protected circuits. In particular, it is extremely difficult, and sometimes impossible to achieve good thermal contact between a surface of the MOV and a thermal cutoff device. Consequently, the MOV may overheat to a point of thermal runaway before the critical temperature is detected and the over-voltage is cutoff from the MOV by the TCO. Further, mismatch problems also may occur between the time constant of the thermal cutoff (i.e., time to open) and the heating/time characteristics of the MOV even when good temperature detection is possible, to render accurate MOV protection unreliable. Both current fuses and thermal cut off devices permanently open upon occurrence of an event and, therefore, must be replaced after such event.
Transient Voltage Suppressors that include MOV-protected circuits may be subjected to over-voltage conditions to determine whether the MOV circuits can fail in a safe manner, that is, without causing damage to equipment or harm to people. In particular, a "Limited current abnormal over-voltage" test involves applying twice-rated normal operating voltage but limits the current to a value below the trip point of any over-current protection device in the power supply line. The test can result in the non-violent heating of the MOVs.
A surge suppression circuit can include three MOV-protected circuits one for each pair of power terminals: Phase and Neutral terminal pair, Phase and Ground terminal pair, and Neutral and Ground terminal pair. The surge circuit may be subjected to a "Limited current abnormal over-voltage" as part of a testing procedure. For example, an over-voltage test is applied across the Phase and Ground terminal pair (as well as the Neutral and Ground terminal pair). This test generates a leakage current that flows through the MOV because of the internal capacitance of the MOV. To prevent the leakage current from flowing to the Ground terminal, a TCO is electrically connected in series with, and physically adjacent, the MOV to detect the leakage current and open the circuit. When an over-voltage test is applied across the Phase and Neutral terminal pair, a leakage current flows from the MOV associated with the Phase and Neutral terminal pair. In this case, the leakage current also flows to the MOV connected across the Neutral to Ground terminal pair.


A printing head module includes a bracket, a plurality of printing heads, a pivot shaft, a wiper unit, and a control unit. The bracket includes a plurality of through holes. The printing heads are parallelly aligned with each other, each of the printing heads a nozzle for extruding the modeling material. The pivot shaft connected to the bracket is adapted to rotate the printing heads to a target position. The wiper unit includes a holder, a plurality of wipers, and a wiper opener. The holder is connected to the pivot shaft to be rotated with the bracket and the printing heads. The wipers rotatably connected to the holder and disposed correspondingly to the openings. The wiper opener is disposed at the target position to interfere with the wiper rotated to the target position, so as to drive the corresponding wiper to rotate to the opening position.

1. Technical Field
The technical field relates to a printing head module, and more particularly to a printing head module having a wiper unit.
2. Description of Related Art
With advancement in computer-aided manufacturing (CAM), a three dimensional printing technology (3-D printing technology) has been developed in the manufacturing industry, thereby rapidly fabricating products from an original design concept. The 3-D printing, in fact, is a general term of a series of rapid prototyping (RP) techniques, and the basic principle thereof, and the concept thereof is a laminate manufacturing, wherein a rapid prototyping machine is used to form cross-sectional shapes of a workpiece in the X-Y plane through scanning, shift intermittently at a layer thickness in the Z coordinates, and ultimately form 3-D objects. The 3-D printing technology is unrestrictedly applicable for the geometric shapes and the RP technology produces excellent outputs in particular for complex parts, which saves efforts and processing time significantly. As a result, the digital 3-D printing technology is capable of presenting an object of a digital 3-D model designed by means of computer-aided design (CAD) software under a shortest time requirement for the user to touch and actually feel the geometry of the model, or even to do possible functional test thereof.
When a printing head module is disposed with a plurality of printing heads, the printing heads are alternatively operated during the 3-D printing process. However, as the printing head is switched from one to another, often there is still residual modeling material left on the nozzle tips of the printing head which just finishes the printing task. Accordingly, the residual modeling material left on the nozzle tips of those printing heads might drop on the printing surface, which cause the contamination issues on the printing objects. Therefore, the printing quality of the 3-D printing process with multiple printing heads is decreased.

This patent is subject to a terminal disclaimer.

Cal-Comp Electronics & Communications Company Limited


A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. The control unit controls said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle.

A sample-and-hold circuit is an electronic circuit for sensing the level of a physical quantity during a short first time interval (sampling phase or observation phase) and maintaining a state indicative of the measured signal during a second time interval (hold phase) which may be longer than the first time interval. The physical quantity may, for instance, be a voltage or an electrical current. The first time interval may, in principle, be arbitrarily short, whereas the second time interval may be arbitrarily long. The level measured during the first interval may, in many cases, be considered the instantaneous level of the physical quantity in question. The measured level may also be referred to as a sample.
The state which represents the measured level may, for instance, be the electrical charge of a capacitor or a digital state. The second time interval, i.e., the period during which the sample-and-hold circuit indicates the measured level, can be used to read out the sample-and-hold circuit, i.e., transfer information representing the measured level to another device or control another device in dependence on the measured level. The second time interval can notably be used to digitize the measured level, i.e., generate a digital representation of the measured level. To this end, an analog to digital converter (ADC) may be connected to an output of the sample-and-hold circuit.
The sample-and-hold circuit may be arranged to sample the received input signals repeatedly at many instances, for instance, at a constant or variable sampling rate. The sample-and-hold circuit may thus generate a discreet set of sample values based on the received continuous or discontinuous input signal.
A sample-and-hold circuit may notably be integrated in various types of sensing devices. A sensing device may, for instance, include a capacitive, inductive, or resistive sensor element arranged to generate alone or in conjunction with other electronic components a sensor signal that may be fed to the sample-and-hold circuit.

Sample-and-hold circuit and capacitive sensing device that includes the sample-and-hold circuit


A semiconductor device includes a substrate and a semiconductor layer formed on the substrate. The substrate has: a flat region provided in a main surface thereof; a first indentation region provided in a portion of the main surface different from the flat region and formed with first recesses; and a second indentation region provided between the first indentation region and the flat region, formed with second recesses, and having a lower probability of occurrence of growth nuclei than the first indentation region and a higher probability than the flat region in the case where a crystal of a semiconductor is grown on the main surface.

(a) Fields of the Invention
The present invention relates to semiconductor devices and their fabrication methods.
(b) Description of Related Art
In growing a semiconductor layer on a substrate, crystal growth of the semiconductor may be conducted on an indented surface of the substrate. For example, a crystal of a semiconductor layer is grown on a substrate with fine indentations, whereby the crystallinity of the formed semiconductor layer is improved. This provides a semiconductor device with excellent characteristics (see, for example, Japanese Unexamined Patent Publication No. 2002-289540).
For a semiconductor light emitting diode (LED), a photonic crystal having two-dimensionally periodic indentations in an emitting surface thereof can be provided to improve the light-extraction efficiency of the diode. The photonic crystal can be formed easily by growing a semiconductor layer on a substrate having two-dimensionally periodic indentations (see, for example, Japanese Unexamined Patent Publication No. 2006-049855).

Semiconductor device and method for fabricating the same


Curable film-forming compositions comprising acrylic polyols, aminoplast and carbamoyl triazines are disclosed. The compositions are useful as clear coats in composite color-plus-clear coatings.

The present invention relates to curable film-forming compositions containing polyols cured with aminoplasts and carbamoyl triazines.
Of increasing concern in many geographic areas is the encounter with acidic precipitation. Coatings, particularly automotive original equipment coatings that are resistant to such environmental conditions like those that are resistant to etching by atmospheric acid precipitation ("acid etch resistance") are becoming increasingly desirable. Original equipment manufacturers are requiring that coating systems demonstrate acid etch resistance.
In addition to the requirement of acid etch resistance, original equipment coatings must also demonstrate mar and abrasion resistance; i.e., the appearance of the coating must not be detrimentally affected when the coating is contacted with an abrasive material. Mar and abrasion resistance is a desirable property particularly due to the popularity of commercial car washes where brushes are often used to wash car bodies.
A number of commercial coating compositions which demonstrate acid etch resistance do not provide adequate mar and abrasion resistance. Microparticulate materials such as silica, metal sulfides, and crosslinked styrene-butadiene have been added to coating systems to improve mar resistance, but gloss and distinctness of image of the systems is adversely affected due to light scattering at the particle surfaces.
Recently, triisocyanato or tricarbamoyl triazines have been developed as crosslinking agents for coating compositions containing active hydrogen-containing materials. These coating compositions also exhibit acid etch resistance, but mar resistance may be inadequate. The triazine compounds are disclosed in U.S. Pat. Nos. 4,939,213 and 5,084,541. However, these references do not disclose the use of triazines in combination with aminoplasts as crosslinking agents to improve both mar and acid etch resistance of a cured coating.
U.S. Pat. No. 5,574,103 discloses coating compositions comprising polyols, aminoplasts, and carbamoyl triazine compounds. However, the reference does not disclose improved mar and acid etch resistance of cured coatings, nor does it disclose amounts of aminoplast to triazine in the coating composition necessary to improve both mar and acid etch resistance.
It would be desirable to provide a curable composition for use as a coating which avoids the marring problems of the prior art coating systems, while exhibiting excellent acid etch resistance and appearance properties.

Curable-film forming compositions having improved mar and acid etch resistance


A indicating power cord system including a housing and an elongated extension cord having a first end connected to the housing and a second end having a plug coupled thereto for being releasably inserted in a standard electrical receptacle to receive power therefrom. Next provided is an electrical outlet positioned on the housing for being electrically connected to a block heater of a vehicle. The electrical outlet is electrically connected to the extension cord with a relay contact and associated relay coil connected therebetween. The relay contact has a closed unbiased orientation upon the lack of receipt of current by the relay coil and an open biased orientation upon the receipt of current by the relay coil. Also included is a thermistor positioned on the heater block of the vehicle. The thermistor can be connected to the relay coil for providing current thereto upon the engine block reaching a predetermined temperature. Further provided is a power consumption level indicator for signalling the amount of power being delivered to the block heater of the vehicle, if any.

1. Field of the Invention
The present invention relates to a indicating power cord system and more particularly pertains to indicating the approximate level of power consumption of an appliance and allowing the optional automatic controlling the delivery of power to the appliance.
2. Description of the Prior Art
The use of block heater monitors is known in the prior art. More specifically, block heater monitors heretofore devised and utilized for the purpose of indicating the status of power flow to an appliance such as a block heater are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
By way of example, the prior art includes U.S. Pat. No. 5,207,594 to Olson; U.S. Pat. No. 4,583,086 to Andrews et al; U.S. Pat. No. Des. 319,609 to Brown; U.S. Pat. No. 5,097,249 to Yamamoto; U.S. Pat. No. 4,983,955 to Ham, Jr. et al. and U.S. Pat. No. 4,558,310 to McAllise.
In this respect, the indicating power cord system according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of indicating the approximate level of power consumption of an appliance and allowing the optional automatic controlling the delivery of power to the appliance.
Therefore, it can be appreciated that there exists a continuing need for a new and improved indicating power cord system which can be used for verifying the delivery of power to an appliance, indicating the approximate level of power consumption of the appliance and allowing the optional automatic controlling the delivery of power to the appliance. In this regard, the present invention substantially fulfills this need.


An airstream deflector apparatus including an elongated body formed of a rigid material and having a parting shape, that is a shape in which a forward facing edge is formed by symmetrical planes to present a streamlined shape which will divert the oncoming airstream to each side. In one form, the body is provided with a pivotable coupling attachment which attaches to a forward portion of the bicycle rack in front of the bicycle itself. When there is no bicycle on the rack, the pivotable coupling between the deflector body and the bicycle rack permits the body to be pivoted downward toward the rear of the vehicle into a stored position.

This invention relates to rooftop carriers for bicycles. More particularly it relates to a wind deflecting device mountable on the carrier or on a bicycle for protecting a bicycle carried on a carrier from the oncoming airstream and from insects and debris.
One particular carrier system is that made by the Thule Company, a well-known Swedish company which manufactures a system having a variety of mounting means for bicycles. The mounting means of particular interest are the upright and fork mount. In the upright type, a bicycle with its wheels attached is fixed upright to the carrier. In the fork mount type, the bicycle is fixed in the upright position, but its front wheel is removed and the front of the bicycle is fixed through the fork by means of what is called a "false axle" or skewer.
One of the primary problems encountered by bicyclists when carrying their bicycles on the roof of a vehicle is the damage and unsightliness and general disagreeableness of insects, dust, exhaust and road spray, impacting the bicycle during travel. Also, there is some lesser frequency of impingement of debris such as pebbles which can cause either cosmetic or functional damage to the bicycle.
It would be of considerable value to have a device for protecting bicycles while in transit from being struck by insects, debris, etc. which is upright in use but which may be pivoted downward and collapsed to a storage position when no bicycle is present on the rack or in the presence of a bicycle when the protective function is not desired or when quick access to the bicycle is desired. In addition, the device would provide for reduction in air resistance by a streamlined shape.


An improved process is disclosed for depositing a layer of metal on a semiconductor wafer wherein a shadow ring normally engages the end edge of the front surface of the wafer to inhibit deposition of the metal on the backside of the wafer and a barrier or nucleation layer is deposited on the unshielded portion of the front surface of the wafer prior to the deposition of the metal layer thereon, and wherein gases used to form the metal layer may contact and react with underlying materials on the front surface of the wafer beneath the shadow ring. The improvement in the process comprises depositing the barrier layer over the entire front surface of the wafer while the wafer and the shadow ring are spaced apart; and then depositing the metal layer on the front surface of the wafer, while engaging the shadow ring with the wafer to inhibit deposition on the backside of the wafer; whereby the deposition of the barrier layer over the entire front surface of the wafer will shield underlying materials on the front surface of the wafer beneath the shadow ring from reaction with one or more of the gases used in the deposition of the metal layer.

1. Field of the Invention
This invention relates to an improved CVD process for depositing a metal layer on a semiconductor wafer. More particularly, this invention relates to an improved CVD process for depositing a metal layer on a semiconductor wafer wherein reaction is inhibited between the metal deposition gases and materials already on the wafer under a shadow ring used to inhibit deposition of the metal on the backside and end edge of the wafer.
2. Description of the Related Art
In the deposition of a metal layer, such as a tungsten layer, on the surface of a semiconductor wafer, a problem was previously encountered with undesired deposition of the metal on the backside and end edge of the wafer, due to the migration of the deposition gases, from above the wafer, around the end edge of the wafer to the backside of the wafer.
These deposition gases are usually admitted to the CVD chamber from a gas inlet or "showerhead" located adjacent the top of the CVD reactor, i.e., above the wafer which is conventionally mounted horizontally in the reactor with the upper or front surface, onto which the metal layer is to be deposited, facing toward the incoming deposition gases.
To solve this problem of undesired deposition on the backside of the wafer, it was previously proposed to use a shadow or shield ring which surrounds the wafer and has a central opening slightly smaller than the OD of the wafer so that the shadow ring may be lowered onto the wafer to engage the peripheral edge of the front surface of the wafer, leaving the front surface available for deposition while effectively blocking migration of the deposition gases around the end edge of the wafer to deposit on the backside of the wafer. An opening is further provided in the shadow ring adjacent the end edge of the shadow ring through which a purge gas is upwardly flowed from beneath the shadow ring. This flow of purge gas acts as a further inhibiter or shield to prevent the deposition gases from reaching the backside of the wafer.
While this method and apparatus does inhibit the unwanted deposition of metal materials on the backside of the wafer, its use has created certain other problems, in particular when certain metals are deposited on the semiconductor wafer.
For example, when a layer of tungsten is deposited on a semiconductor wafer, it is common to provide an underlying layer of titanium nitride as an adhesion or "glue" layer which facilitates the bonding of the tungsten metal to the underlying substrate. To further facilitate the deposition of a satisfactory tungsten layer thereon, it is also common to deposit a nucleation layer of tungsten at a low pressure, e.g., of less than 10 Torr, over the titanium nitride layer prior to the main deposit of tungsten, from WF.sub.6 gas at a pressure of about 80 Torr. This nucleation layer is deposited using a reaction of WF.sub.6 with SiH.sub.4.
However, it has been found that when a shadow ring is used to shield the backside of the wafer from deposition of tungsten thereon, some of the WF.sub.6 gas, from the higher pressure main deposition, may migrate under the shadow ring. This can cause problems because materials in some forms of titanium nitride, e.g., unreacted titanium, may react with the WF.sub.6 gas, resulting in an undesirable peeling of one or both of the tungsten/titanium nitride layers.
This problem does not occur in the main (unshielded) portion of the front surface of the wafer because the low pressure nucleation layer of tungsten, applied prior to the main deposition, further acts as a barrier layer through which the WF.sub.6 gas from the main deposition cannot penetrate to reach the underlying titanium nitride. This tungsten barrier layer is formed without reaction between the titanium nitride layer and the WF.sub.6 gas used to form the tungsten nucleation layer because the deposition of the tungsten nucleation layer is carried out using a mixture of WF.sub.6 and SiH.sub.4 gases which react very quickly to form tungsten so that little, if any, unreacted WF.sub.6 gas is available to penetrate into the underlying titanium nitride layer.
However, since the tungsten nucleation layer is deposited at a lower pressure than the main tungsten deposition, the gases forming the tungsten nucleation layer do not migrate under the shadow ring as easily as do the subsequent higher pressure tungsten deposition gases. The result is that the WF.sub.6 gas flowing into the reaction chamber during the main tungsten deposition can migrate under the shadow ring and then penetrate into the underlying (and unprotected) titanium nitride layer on the front surface of the wafer beneath the shadow ring, resulting in the undesired peeling and particle formation.
It should be further noted that not all of the front surface of the wafer beneath the shadow ring at the periphery of the wafer is covered by titanium nitride. There are also small areas of exposed oxide representing regions where wafer clamps contacted the front surface of the wafer during the titanium nitride formation. Therefore, even if one could somehow protect the wafer from backside deposition in some other manner, i.e., eliminating the shadow ring, deposition of a thick (e.g., 1-2 micron) layer of tungsten over the oxide portions would also result in undesirable peeling of the tungsten layer at those points.
It would, therefore, be desirable to provide a process of forming a metal layer, such as a tungsten layer, over a semiconductor wafer in a manner which would protect the backside of the wafer from deposition, yet not result in an undesirable peeling of material deposited on the front side of the wafer beneath the shadow ring.

Metal chemical vapor deposition process using a shadow ring


In a lens device, plastic lenses having circular outer periphery are placed in a plastic lens-barrel having an octagonal or more complex polygonal inner surface in such a way that the outer peripheral surfaces of the lenses are press contacted to the inner surface of the polygonal shape. This lens device has press contact portions that are pressed by the lens outer peripheral surface and the lens-barrel inner surface in the vicinity and in both sides of gate traces where optical axis displacement is large so as to suppress the displacement of the gate trace by the press contact portions.

1. Field of the Invention
The present invention relates to a lens device where a lens used for a camera or the like is inserted and fixed in a lens-barrel.
2. Description of Related Art
A digital camera, a mobile phone camera and so on use a lens device in which one or a plurality of lenses are inserted and fixed in a lens-barrel. Such a lens device is manufactured by performing core alignment so as to align the optical axes of a lens and a lens-barrel and the optical axes of a plurality of lenses and then inserting and fixing the lenses into the lens-barrel.
In such a lens device, a plastic lens, a plastic lens-barrel and so on are used because they are low cost and easy to form a desired shape.
The plastic lens and lens-barrel, however, are subject to expansion and shrinkage due to temperature or humidity change. Thus, even if core alignment is performed when inserting and fixing the lens into the lens-barrel to assemble them, the misalignment of the optical axes between a lens and a lens-barrel or between lenses can occur upon temperature or humidity change, which results in deterioration in optical properties.
In order to solve the above problem, Japanese Unexamined Patent Application Publication No. 04-204408 proposes a lens device with a plastic lens and a lens-barrel for holding the lens. The lens device has at least three protrusions that are formed on the inner surface of the lens-barrel to project toward the center axis (optical axis) of the lens-barrel so as to hold the lens with their ends in contact with the periphery of the lens. The diameter of the circle which the protrusion ends inscribe is smaller than the outer diameter of the lens that is supported by the protrusions. Further, the rigidity of the lens-barrel is smaller than the rigidity of the plastic lens. The lens device thereby prevents the decentering or distortion of the lens under change in dimension due to environments such as temperature and humidity.
According to this proposed technique, the center of the lens always receives the force that corresponds to the center of the lens-barrel, thereby preventing the decentering and holding the lens at a given position in the lens-barrel. It is, however, still unable to suppress the misalignment between the lens and the lens-barrel and between the lenses sufficiently.


A programmable gain amplifier includes a sampling circuit, a source follower, a first capacitor and an error amplifier. The sampling circuit is configured to perform correlated double sampling on an input signal using a reference voltage. The first capacitor is connected between the sampling circuit and the source follower. The error amplifier is connected between an input terminal of the source follower and an output terminal of the source follower. The error amplifier is configured to reset a voltage of the output terminal of the source follower to the reference voltage during a source follower reset operation.

At least one example embodiment of the inventive concepts relates to a complementary metal oxide semiconductor (CMOS) image sensor (CIS), and more particularly, to an image sensor including a programmable gain amplifier and/or devices including the same.
A conventional programmable gain amplifier is a circuit that includes a plurality of capacitors having different capacitances and amplifies an input signal using the capacitance ratio between the capacitors. The amplified input signal is output to an analog-to-digital converter (ADC). When the ADC is used in a system requiring the settling of an input stage, the power consumption of the system may increase due to the limited operating speed of the programmable gain amplifier.

Programmable gain amplifier and devices including the same


The invention relates to a process for clearing a mobile telephone Subscribe-identify Module (SIM) card for a mobile telephone customer for a set performance parameter or for changing a performance parameter for which the SIM card is cleared. To accelerate the clearance of SIM cards, the invention proposes a process characterized by the following steps:

The present invention relates to a process for clearing a mobile telephone Subscribe-Identify Module (SIM) card for a mobile telephone customer for a performance parameter or for changing a performance parameter for which the SIM card is cleared.
The invention furthermore relates to a device to execute a process for clearing a mobile telephone Subscribe-Identify Module (SIM) card for a mobile telephone customer for a performance parameter or for changing a performance parameter for which the SIM card is cleared, whereby the customer can dial this device via a terminal.
Such processes and devices are known in prior art in various embodiments. If a mobile telephone customer wants to use a mobile telephone in a mobile telephone network, he must first acquire a mobile telephone and a SIM card. The SIM card has a small memory chip on which [information] can be stored, for example, the card number of the SIM card, information to identify the customer and several names with dial numbers. To be able to operate the mobile telephone in the mobile telephone network, the SIM card must first by cleared by a mobile telephone network operator. In the context of this clearance, the SIM card is assigned to a specific customer, the customer""s address and banking information is stored with the mobile telephone network operator, the customer""s creditworthiness is verified, the performance parameters desired by the customer (tariff, roaming, connection itemization in the invoice, etc.) are determined and a mobile telephone number by which the customer can subsequently be reached in the mobile telephone network is assigned to the SIM card. If the SIM card is inserted into the mobile telephone, the customer can call from the mobile telephone and receive calls via his mobile telephone number.
According to the known process, clearance of the SIM card is typically executed in the following steps. First, the customer completes a mobile telephone agreement with a dealer and signs it. The agreement contains information on the customer""s identification, address and banking information. The mobile telephone agreement also includes the card number of a SIM card, which is to be cleared for the customer. Furthermore, a mobile telephone number is indicated, which is to be assigned to the SIM card and under which the customer can subsequently be reached in the mobile telephone network. Finally, the performance parameters desired by the customer are determined in the agreement. The completed agreement is then forwarded to the mobile telephone network operator, typically via fax. There, the information is manually stored by the network operator""s personnel, the customer""s creditworthiness is verified, the specified dial number is assigned to the SIM card and the SIM card is cleared for the desired performance parameters. The mobile telephone network operator typically requires one to two business days to complete these transactions to clear the SIM card. Significantly faster clearance of a SIM card would be advantageous, however.
The clearance of SIM cards and the changing of the performance parameters of the mobile telephone agreements with the mobile telephone network operator should take as little time as possible. For this purpose the network operator has to reserve a certain number of employees, which constitutes a considerable cost factor.
The process for clearing a mobile telephone SIM card according to prior art is not carried out directly by the mobile telephone network operator but via one or several dealers each of which receives a commission for contract signature. As a result, the costs for entering into a mobile telephone agreement are quite high.
On the other hand, the direct sale of mobile telephone agreements by the mobile telephone network operators via their own dealer network would be very complex and at least as expensive as the sale via one or several external dealers since their own dealer network would typically first have to be set up. Thus, the direct sale by the mobile telephone network operator via its own dealer network would not be apt to reduce the costs for concluding a mobile telephone agreement.
The interposition of several dealers bars the mobile telephone network operator from direct access to the customer. Thus, marketing campaigns on the part of the mobile telephone network operator must take the circuitous route through one or several dealers.
Based on the aforementioned disadvantages of the prior art, one object of the present invention is to design and further develop a process of the initially mentioned type, which will accelerate the clearance of SIM cards, reduce the costs for clearance and provide the mobile telephone network operators direct access to their customers without significant additional complexity or costs.
To attain this object, the invention proposes a process of the initially mentioned type characterized by the following steps:
dialing a communications network by the customer via a terminal,
establishing a connection to the communications network,
determining the customer""s identity,
going through a computer-assisted dialog comprising at least the determination of the card number of the SIM card,
transmitting the customer""s identity, the card number of the SIM card and the performance parameter to a mobile telephone network operator via a data transmission connection, and
entering the transmitted data into a database of the network operator.
The process according to the invention assumes that the mobile telephone network operators will bring the SIM cards into circulation free of charge. This could be done, for example, within the context of a marketing campaign or through newspaper inserts.
The process according to the invention puts a potential customer into the position of being able to clear a received SIM card for specific services or performance parameters independently without the intermediation of dealers. Likewise, the process according to the invention permits the customer independently to change the established services or performance parameters at any time.
This is made possible in that the potential customer dials a communications network via his terminal. This communications network preferably has a central component, which controls certain network functions of the communications network. In communications technology such a communications network is also known as an intelligent network. The terminal is preferably embodied as a telephone or as a computer. The communications network can be dialed via a telephone network or via a computer network. The computer network is preferably embodied as the Internet. If the communications network is embodied as an intelligent network, the central component within the communications network is dialed via the terminal and a connection to the central component is established. To be able to dial the intelligent network via a computer network, the communications network must have a computer that is integrated with the computer network. The intelligent network is then accessed by calling up the Internet address of the computer of the communications network.
To dial the communications network, the potential customer either selects a communications network telephone number or the address of the communications network computer. After the connection to the communications network has been established, the identity of the potential customer is first determined. Then, a computer-assisted dialog is gone through. As a minimum, the card number of the SIM card is determined in the context of this dialog. It is feasible, however, that the communications network also receives any other information within the context of the computer-assisted dialog. Subsequently, the customer""s identity, the SIM card number and the performance parameter are transmitted via a data transmission connection to the mobile telephone network operator. Finally, the transmitted data is stored in a database of the network operator.
The process according to the invention permits a significant acceleration in the clearance of SIM cards. Since the customer can clear his SIM card independently and can change the performance parameters set for his cleared SIM card independently, the mobile telephone network operator can save personnel that is currently assigned to perform these activities. This permits a cost reduction for SIM card clearance and administration. By eliminating the intermediate dealer, the mobile telephone network operators ultimately obtain direct access to their customers without significant additional complexity and without significant extra costs. This makes it possible to conduct specific marketing campaigns without time delays due to the intermediate dealers.
If the communications network is embodied as an intelligent network, the customer""s identity is preferably determined in the central component of the communications network. The computer-assisted dialog is then executed on the central component of the communications network and/or the customer""s identity, the card number of the SIM card and the performance parameter are transmitted from the central component to the mobile telephone network operator.
According to an advantageous further development of the present invention, a mobile telephone number is assigned to the SIM card upon clearance. In the future the customer can then be reached at this telephone number within the mobile telephone network.
According to a preferred embodiment of the invention, it is proposed that the customer""s identity be manually transmitted by the customer himself via the connection to the communications network. For example, the customer can enter information regarding his identity by means of the telephone keypad, which he used to set up a connection to the communications network, and transmit this information to the communications network. It is also feasible for the customer to enter the information regarding his identity on a corresponding page on the Internet using a computer keyboard and to transmit this information to the communications network.
As an alternative, it is proposed that the identification number of the terminal be automatically transmitted via the connection to the communications network and that the customer""s identity be determined by the central component of the communications network from the identification number. Automatically, in this case, means that transmission occurs without any action by the potential customer. This embodiment is particularly interesting for those network operators that operate a fixed network in addition to the mobile network. To clear his SIM card, the customer of the mobile telephone network can then use his fixed network telephone of the same network operator. Since the potential mobile telephone customer is already a fixed network customer of this network operator, information on the identity of the fixed network customer is already stored in a database of the network operator. From the identification number of the fixed network telephone, which is automatically transmitted to the communications network, the communications network can then take the information on the identity of the fixed network customer from the database and use it as the information on the identity of the mobile telephone customer.
Likewise, when setting up a connection via a computer network, the customer""s identification number within the computer network can be automatically transmitted to the communications network. From the customer""s identification number, the communications network can then determine the information on the customer""s identity, for example, from a database.
According to a preferred embodiment of the invention, the customer himself manually transmits the card number of the SIM card via the connection to the communications network. The card number is transmitted via a telephone, a computer, or some other input device using a keyboard, voice control or in some other manner.
Alternatively, it is proposed that the card number of the SIM card be automatically transmitted via the connection to the communications network. In this embodiment, the potential customer can use his mobile telephone with the still uncleared SIM card to set up a connection to the communications network. Telephoning within a mobile telephone network without a SIM card, or with a still uncleared SIM card, is possible in principle (e.g., the emergency number 112 [Germany""s equivalent of 911] can be dialed from a mobile telephone even without a SIM card). If a call is made within the mobile telephone network with a non-cleared SIM card, the mobile telephone network can cause the calling mobile telephone to transmit the card number stored on the SIM card or the mobile telephone network itself can access the stored card number. Of course, this presumes that the card number is stored on the memory chip of the SIM card and that the content of the memory chip can be accessed from outside via the mobile telephone network. In this embodiment, manual entry of the card number may be eliminated.
According to a particularly advantageous further embodiment of the invention, it is proposed that the customer conduct the computer-assisted dialog using voice commands or the Dial Tone Multi-Frequency (DTMF) method. For this purpose, the communications network must have means to convert voice commands or touch tones to the corresponding commands. The voice commands or touch tones are transmitted via the connection established between the telephone and the communications network and only in the communications network, preferably by the central component of the intelligent network, are they converted into the corresponding commands to execute the computer-assisted dialog. Voice commands or the DTMF method can also be used to enter the information regarding the potential customer""s identity and the card number of the SIM card.
According to a preferred embodiment, at least one query to verify the customer""s identity is performed in the context of the computer-assisted dialog. This query can consist, for example, of a request for a personal identification number (PIN) or other personal data such as the identification card number, etc.
Advantageously, at least one query is conducted in the context of the computer-assisted dialog to determine a performance parameter. This makes it possible initially to set the desired services/performance parameters during clearance of the SIM card. If a SIM card has already been cleared, the set performance parameters can be conveniently and quickly changed.
According to an advantageous further development, the invention proposes that a Short Message Service (SMS) message or electronic mail (e-mail) be used to inform the customer of the successful clearance of the SIM card or the successful change of a performance parameter. This message advantageously transmits the set performance parameters to the customer. Likewise, if the SIM card is not cleared or if the performance parameters are not changed, the customer can be informed of the problems that occurred during clearance or during the change.
A further object of the present invention is to design and further develop a device of the initially cited type to permit accelerated clearance of SIM cards so as to save clearance costs and to provide the mobile telephone network operator with direct access to its customers without significant additional complexity and without significant extra costs.
To attain this object, the invention proposes a device of the initially mentioned type with
means to establish a connection from the terminal to the device,
means to determine the customer""s identity,
means to go through a computer-assisted dialog that comprises at least the determination of the card number of the SIM card,
means to transmit the customer""s identity, the card number of the SIM card and the performance parameter to a mobile telephone network operator via a data transmission connection, and
means to enter the transmitted data into the database of the network operator.

Abstract: selecting a communications network via a terminal,

Abstract: determining the customer""s identity,

Abstract: going through a computer-assisted dialog that comprises at least the determination of the card number of the SIM card,

Abstract: transmitting the customer""s identity and the card number of the SIM card to a mobile telephone network operator via a data transmission connection, and

Abstract: entering the transmitted data in a database of the network operator.


The present disclosure provides a roller pin for a fuel pump. The roller pin includes a cylindrical body made of a first material extending between a first end and a second end. The roller pin includes an intermediate portion disposed between the first end and the second end of the cylindrical body. The intermediate portion is formed by depositing a second material on the cylindrical body. The roller pin further includes a longitudinal groove extending along the intermediate portion.

Typically, a cam follower used in a high-pressure fuel pump or a valve drive of an internal combustion engine includes a cam roller rotatably supported on a roller pin. The cam roller and the roller pin may be manufactured from carburized heat-resistant steel alloy. The roller pin includes a load bearing surface. Due to close tolerances, the cam roller and the roller pin experience a frictional force between them which may result in wear of the abutting surfaces, and in some cases this may lead to a failure of the roller pin and/or the cam roller. Alternatively, a roller pin manufactured from a friction resisting material such as bronze reduces the frictional forces between the abutting surfaces. However, due to pliability of bronze, the life of the roller pin may be affected at the load bearing surface of the roller pin. Moreover, a roller pin may be manufactured by attaching a layer of bronze over a steel body of the roller pin by known processes such as welding, but prolonged operation of the roller pin results in uneven wear of the roller pin at the load bearing surface.
U.S. Pat. No. 6,042,778 discloses a sliding bearing which is multilayered, self-lubricating and maintenance-free. The bearing includes a metallic supporting body; and a layer of sintered bronze which is provided on the metallic supporting body and which has pores filled with polytetrafluoroethylene (PTFE) to provide a PTFE-impregnated sintered bronze layer, the PTFE being uniformly distributed and serving as a solid lubricant, and the PTFE-impregnated sintered bronze layer having a sliding surface composed of the PTFE particles but no PTFE cover layer.

Roller pin for cam actuated roller assembly


Provided is a method, system, and program for enabling access to a plurality of services. A plurality of service class implementations is provided for services from different vendors, wherein each service class implementation provides an implementation of methods and objects from a same abstract service class. A service object is constructed for one service in response to at least one called method from one of the service class implementations. The service object includes information on resources of the service. Method calls are received from one service class implementation requesting information on service resources for one named service. The requested information is accessed from the service object for the named service to return to the method call.

1. Field of the Invention
The present invention relates to a method, system, and program for enabling access to a plurality of services.
2. Description of the Related Art
A workflow program allows businesses and other organizations to define their business operations as a computer model known as a workflow. A workflow defines a series of processes to be performed by users at a client computer. The user activities at the client computers may involve updating an electronic form, reviewing information, etc. After one user in the workflow performs a specified action, the work item or other information is then routed to one or more further nodes where further action may be taken. For instance, an on-line purchase of a product may involve numerous steps, such as receiving the customer order, routing the customer order to the credit department to process the bill and then routing the order to the shipment department to prepare the shipment. Once the shipment is prepared, the product may be shipped and information on the purchase is then transferred to the customer service department to take any further action. Each of these processes may be defined as nodes in a workflow. A workflow program would then route the customer order to the business agents designated to handle the job. For instance, the initial order would be received by the order department and then routed to a person in shipping and billing. Once the bill and package are prepared, a further invoice may be forwarded to shipping. After shipping sends the package, the shipping agent may then enter information into the invoice and forward the electronic invoice to customer service for any follow up action.
A workflow is designed using workflow software, such as the International Business Machines (IBM) MQSeries Workflow software product. Different vendors provide proprietary platforms for implementing workflows. Once a user designs a workflow model using a particular vendor product, they are often restricted to that vendor platform because their application programs are tied to the particular vendor implementations.
For these reasons, there is a need in the art to provide techniques for integrating products from different vendors in a federated environment.

Method, system, and program for enabling access to a plurality of services

International Business Machines Corporation


An apparatus for wireless relaying comprises: a transmission unit for generating a wireless signal; an amplification unit for amplifying and outputting the wireless signal; a conversion unit for converting the wireless signal into a digital signal; and an adjustment unit for adjusting the amplification ratio of the amplifying unit so that the difference between an output level value of the digital signal and a predetermined target power is lower than a predetermined numerical value.

1. Technical Field
The present invention relates to an apparatus for wireless relaying (access point) that provides a near field communication service.
2. Description of the Related Art
With the popularity of mobile communication devices, such as smartphones, notebook computers, etc., apparatuses for wireless relaying have been increasingly installed at more locations than ever in order to provide near field communication services. There can be a plural number of apparatuses for wireless relaying installed and operated in an arbitrary area, and a user terminal can select one of the plural apparatuses for wireless relaying to use a near field communication service.
However, when there are plural apparatuses for wireless relaying within a particular area, interference may occur in a wireless signal transmitted by each apparatus for wireless relaying. Accordingly, the apparatuses for wireless relaying should be installed at respective locations for which the coverage area of each apparatus for wireless relaying is considered. However, since the coverage area of the common apparatus for wireless relaying is inconsistent, there may be areas where a service by the apparatus for wireless relaying is available, or the coverage areas may be excessively overlapped to cause interferences, or some particular area may need to have an excessive number of apparatuses for wireless relaying installed therein.

Apparatus and method for wireless relaying