Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

The present invention relates generally to clock and data recovery (CDR) systems and more specifically to improving interpolator linearity in CDR systems.
Clock and data recovery (CDR) operations are performed in many communication circuits. Digital communication receivers sample an analog waveform and then detect the data that the waveform represents. The phase of the analog waveform is typically unknown and there may be a frequency offset between the frequency at which the original data was transmitted and the nominal receiver sampling clock frequency. The CDR function is used to properly sample an analog waveform using a reference clock to correctly recover the data.
FIG. 1 shows a block diagram of a prior art CDR circuit 100. The CDR circuit 100 receives as input a reference clock 140 and an analog data stream 104 that represents digital bits (i.e., 1s and 0s), and provides as output a recovered clock 110 and recovered data 106. The data stream 104 is often a differential waveform as represented by waveform 108. The differential waveform 108 has multiple so-called "eyes" 112 which represent the maximum and minimum amplitude of the data stream 104 during a time interval. The waveform 108 has transition points, such as transition points 120, 124, that indicate the transition from one eye to the next. Each eye also has a respective midpoint (e.g., midpoint 116 of eye 112).
The CDR circuit 100 includes a series of latches 134 that are clocked from a clock signal 126 to sample the data stream 104 at the midpoint 116 of the eye 112. The midpoint 116 of the eye 112 is typically sampled because the CDR circuit often has the best chance of correctly identifying whether the waveform is representing a digital 0 or a digital 1 at that instant in time. The CDR circuit 100 determines each transition point (e.g., transition point 120 and 124) and the midpoint 116 of the eye 112.
Due to imperfections and nonlinearities in the transmission device or transmission medium, or offset between the transmit and receive frequencies, the data signal may shift in time during the transmission relative to the clock signal. This shifting in time may result in the differential waveform 108 moving (back and forth or in one direction over time with respect to the reference clock 140) as it is being received by the CDR circuit 100.
The CDR circuit 100 determines this time shifting in order to ensure that the CDR circuit 100 samples each eye 112 of the waveform 108 at its midpoint 116. The CDR circuit 100 determines the transition point 120 and 124 and midpoint 116 of each eye 112 and then changes the phase of an output signal 126 of an interpolator 128 of the CDR circuit 100, via a control signal 130. The CDR circuit 100 samples the input data stream 104 at points determined by the phase of the output signal 126 of the interpolator.
To change the phase of the output signal 126, input clock signal 140 is delayed, creating a new clock signal 144. These clock phases are connected to each input 132, 136 of the interpolator 128. In other words, one input clock signal 144 is delayed with respect to the other input clock signal 140. These two input signals provide the minimum phase and the maximum phase for the interpolator 128.
As the phase of the interpolator 128 is changed, however, the input impedance of each input 132, 136 of the interpolator 128 also changes. This variation in input impedance results in an amplitude variation of the input clock signals 140, 144. This, in turn, results in an undesirable change in the phase of the input clock signals 140, 144 relative to each other.
Thus, the prior art interpolator (and, therefore, CDR circuit) does not change phases in a smooth, linear manner. Instead, the phase of the prior art interpolator's output signal 126 changes as a result of an impedance variation with respect to the interpolator's inputs. As a result, the input data stream 104 may not be sampled correctly.

Method and apparatus for improving linearity in clock and data recovery systems


An arc discharge lamp, such as a metal halide arc discharge lamp, has an extended life by reducing loss of the metallic portion of the fill. At least one component of the fill reacts with fused silica in the arc tube or diffuses through the arc tube walls. The fill will generally comprise a sodium halide, at least one additional metal halide, and an inert starting gas. A borosilicate glaze which is vitreous and light-transmissive is provided on the wall of the arc tube. The borosilicate glaze is comprised of a borosilicate glass containing at least one metal oxide selected from aluminum, scandium, yttrium, and the rare earth elements. The borosilicate glaze may further contain additional rare earth elements or transition metals to alter the light or energy emission of the lamp by absorbing select wave lengths. For instance, titanium, ceria, cobalt, chromium, iron or neodymium, or combinations of the foregoing, may be added.

The present invention relates generally to high-intensity, metal halide arc discharge lamps having fused silica arc tubes filled with a mixture including sodium halides and at least one additional metal halide, and optionally mercury. More particularly, it relates to a borosilicate glaze present on the inner surface of the arc tube, the outer surface of the arc tube, or both the inner surface and the outer surface of the arc tube, for extending the useful life of the lamp by reducing the loss of the metallic portion of the fill and the corresponding undesirable buildup of free halogen in the arc tube which results from sodium ion diffusion through the fused silica arc tube or metal halide reaction with the fused silica arc tube.
Metal halide arc discharge lamps having a construction typical of this type of lamp are shown, for example, in U.S. Pat. Nos. 4,047,067 and 4,918,352 (electroded), and 5,032,762 (electrodeless). Metal halide lamps of this type generally contain a filling of light emitting metals including sodium and rare earth elements in the form of halides, commonly the iodide, and optionally mercury, in arc tubes composed of, for example, fused silica, alumina, and crystalline synthetic sapphire.
The lifetime of such lamps is frequently limited, however, by the loss of the metallic portion of the metal halide fill during lamp operation due to sodium ion diffusion and/or reaction of the metal halides with the fused silica arc tube and the corresponding buildup of free halogen in the arc tube. The term xe2x80x9cfree halogenxe2x80x9d as used herein refers to volatile forms of halogens or halogen containing molecules created in the normal operating lamp as a result of sodium ion diffusion through the arc tube wall or metal halide reaction with the fused silica arc tube. Such resulting free halogen products could include iodine gas (I2) or silicon tetra iodide (SiI4), respectively.
The mobility of the sodium ion is such that the arc tubes are somewhat permeable to it. During lamp operation, sodium will diffuse through the arc tube wall to the cooler region between the arc tube and the outer jacket of the lamp and deposit on the outer jacket and on arc tube support structure where present. The lost sodium is thus unavailable to the discharge and can no longer contribute its characteristic emission so that the light output gradually diminishes and the color shifts from white toward blue. The arc becomes constricted as sodium is lost and, in a horizontally operating lamp particularly, may bow against the arc tube wall causing it to soften, leading eventually to non-passive failure. Also, loss of sodium causes the operating voltage of the lamp to increase, often rising to the point where the arc can no longer be sustained, ending the life of the lamp.
An additional source of loss of the metallic portion of the fill and corresponding buildup of free halogen during lamp operation is the chemical reaction of metal halides in the fill with the silicon dioxide, SiO2, of the inner surface of the fused silica arc tube producing, for example, metal silicate crystals on the arc tube wall and free silicon tetra iodide. This results in a color shift in the lamp, arc tube wall darkening and/or cracking, plus lumen loss.
Thus, the industry has been searching for ways to prevent or minimize sodium loss by diffusion through the fused silica arc tubes of metal halide arc discharge lamps, as well as to reduce or prevent reactions of the ionizable, light-emitting metal halide species in the fill with the fused silica walls of the arc tubes. Attempts to solve these problems have included providing aluminum silicate and titanium silicate layers on the outside surface of the arc tube, as in U.S. Pat. Nos. 4,047,067 and 4,017,163, respectively. U.S. Reissue Pat. No. 30,165 discloses vitreous metal phosphates and arsenates as coatings for the inner surfaces of ceramic and silica arc tubes. U.S. Pat. No. 3,984,590 discloses aluminum phosphates and U.S. Pat. No. 5,032,762 discloses beryllium oxide as coatings for the inner surfaces of arc tubes.
Despite the coating advances of the prior art, the problems of loss of the light-emitting, metal halide portion of the fill by diffusion or reaction and the corresponding buildup of free halogen in the arc tube have not been heretofore satisfactorily solved.
Accordingly, the present invention provides a means for reducing loss of the metallic portion of the fill of an arc tube of a metal halide arc discharge lamp as a result of diffusion and/or reaction and hence provide a means for reducing the corresponding buildup of free halogen, thereby extending the useful life of the lamp.
This invention also provides a means to decrease UV emissions from the lamp by providing a glaze containing a UV absorbing species.
The present invention further provides a means to alter light or energy emission from the lamp by absorbing select wavelengths, i.e. UV or IR.
The present invention is directed to an improved arc tube and an improved metal halide discharge lamp including the improved arc tube having the aforesaid means.
The present invention is an improved arc tube of fused silica for an arc discharge lamp. Such an arc discharge lamp could be a metal halide arc discharge lamp, including a fill for the arc tube capable of initiating and sustaining an electric arc discharge, wherein at least one component of the fill reacts with the fused silica or diffuses through the arc tube walls. The fill will generally comprise a sodium halide, at least one additional metal halide, and an inert starting gas. The improved arc tube will generally comprise a tube of fused silica having an inner wall defining an arc chamber, the inner wall, the outer wall, or the outer and inner walls, of the tube having provided thereon a borosilicate glaze which is vitreous and light-transmissive. The borosilicate glaze is comprised of a borosilicate glass containing at least one metal oxide selected from aluminum, scandium, yttrium, and the rare earth elements. The borosilicate glaze may further contain additional rare earth elements or transition metals to alter the light or energy emission of the lamp by absorbing select wave lengths. For instance, titanium, cerium, cobalt, chromium, iron or neodymium may be added. Of course, combinations of the foregoing may also be added to obtain desired emissions. The borosilicate glaze has been found to effectively extend the useful life of metal halide arc discharge lamps by reducing loss of the metallic portion of the fill through diffusion and/or reaction, and thus reducing the corresponding buildup of free halogen. In a broader sense, the invention relates to a fused silica article having a glaze of such borosilicate on at least a portion of a surface thereof.
The present invention additionally provides a metal halide arc discharge lamp assembly, having an arc tube of fused silica for containing a plasma arc discharge, and having a borosilicate glaze provided on the inner surface, the outer surface, or both the inner surface and the outer surface of the arc tube, the borosilicate glaze being vitreous and light-transmissive, and being comprised of a borosilicate containing at least one metal selected from aluminum, scandium, yttrium, and the rare earth elements. The borosilicate glaze may further contain additional rare earth elements or transition metals to alter the light or energy emission of the lamp by absorbing select wave lengths. For instance, titanium, cerium, cobalt, chromium, iron or neodymium may be added. Of course, combinations of the foregoing may also be added to obtain desired emissions. As obvious to those skilled in the art, such a borosilicate glaze would improve the arc tube in both an electroded metal halide arc discharge lamp and a high intensity discharge electrodeless lamp which operates by radio or microwave frequency.
The present invention additionally provides the process of protecting a fused silica arc tube of a metal halide arc discharge lamp, the lamp containing a fill including sodium halide, at least one additional metal halide, and an inert starting gas disposed within the arc tube from loss of the metallic portion of the fill through diffusion and/or reaction, and a corresponding buildup of free halogen in the arc tube. The process comprises providing the inner surface, the outer surface, or both the inner surface and the outer surface of the arc tube with a borosilicate glaze which is vitreous and light-transmissive, and which is comprised of a borosilicate containing at least one metal selected from the group consisting essentially of aluminum, scandium, yttrium, and the rare earth elements. The borosilicate glaze may further contain additional rare earth elements or transition metals to alter the light or energy emission of the lamp by absorbing select wavelengths. For instance, titanium, cerium, cobalt, chromium, iron or neodymium may be added. Of course, combinations of the foregoing may also be added specific to desired emissions.

High temperature glaze for metal halide arctubes


A method for assessing fatigue damage and a fatigue life based on a crystal plastic welding process model. According to the new method, consideration is given to the effects of the crystal slip system and the polycrystal plastic strain on the welding process performance of the material. A welding process damage and fatigue life assessment model is established on the mesoscopic scale. The effect of microscopic characterizations of materials on the welding process performance, as well as on the fatigue damage and life of welded joints, can be studied from the mesoscopic point of view. The relationship between the welding process and the evolution of the material performance can be determined by the macro-mesoscopic coupling calculation model to further determine the effect and degree of welding processes on the fatigue damage and life of materials.

With advancements in welding technologies, it is now practicable to realize the engineering and manufacture of large component applications. Currently, welding is widely used in various industries. The engineering practice and research, however, have found that fatigue crack initiation and fatigue failures of a welded component typically occur at welded joints having the weakest mechanical properties. Therefore, there is significant scientific and engineering value in research pertaining to welding processes and their effect on mechanical properties. A focus of this effort involves fatigue behavior.
In general, weldability, reliability and fatigue of welded joints are studied through experimental testing. However, the experimental testing method is difficult to effectively analyze the welding and fatigue failure processes because of restrictions on the experimental conditions and costs that are associated with testing. Moreover, the research involving material stress-strain analysis, fatigue and crack initiation and propagation has not been adequately developed on a microscopic scale.

Method for assessing fatigue damage and a fatigue life based on a crystal plastic welding process model


A capability is provided for statelessly recognizing Transmission Control Protocol (TCP) keep-alive packets. A server receives a TCP SYN packet including an initial client sequence number and selects an initial server sequence number for the TCP connection based on the parity of the initial client sequence number and a parity rule. A server receives a TCP packet from a client and uses a parity rule for determining whether to manipulate a TCP response packet to be sent by the server to the client responsive to the received TCP packet (to ensure that the next TCP packet to be sent by the client is not incorrectly identified as a TCP keep-alive packet). A network device receives a TCP packet and uses a parity rule to determine whether the TCP packet is a TCP keep-alive packet. The parity rule is indicative of an expected parity of TCP keep-alive packets.

There are various situations in which it may be necessary or desirable to deploy multiple servers to support connections with client devices. The connections may include any types of connections suitable for supporting client/server transactions, such as Transmission Control Protocol (TCP) connections or other types of connections. Additionally, in at least some situations, it may be necessary or desirable to balance the connections across multiple servers using one or more load balancers. Disadvantageously, however, typical physical load balancers are inflexible and cannot be scaled up or down dynamically based on load, and typical software-based load balancers are stateful and do not handle addition or removal of servers gracefully.

Stateless recognition of keep-alive packets


Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel filter design is used to perform sample rate conversion. The filter may be combined with another digital filter. Two embodiment may be used to achieve this function. In a first embodiment, the filter may be clocked at a first (i.e., input) data rate (i.e., before rate conversion). In a second embodiment, the filter may be clocked at the second (i.e., output) data rate (i.e., after rate conversion). In both cases, the filter's basic structure remains essentially the same, but some extra terms are added to handle the rate conversion. The present application is directed toward a sample-rate conversion filter using the output data rate clock as the filter clock.

Sample-rate conversion (SRC) refers to the process of translating a sequence of discrete data samples with a certain sampling rate into another sequence with a different sampling rate, while preserving the information contained in the original sequence. Sample rate conversion can be a relatively simple technique where the two sample rates are related by a fairly small integer ratio. For example, if the ratio of sample rates is 4:5, the input signal only needs to be upsampled by a factor of four and then, after appropriate filtering, down-sampled by a factor of five.
FIG. 1 illustrates an example of such a Prior Art sample rate conversion technique. In this Prior Art embodiment, input data may be upsampled by a factor of M in upsampler 110, to produce an upsampled data stream. Upsampling may comprise the process of creating new intermediate samples by inserting samples of value zero as intermediate values. Upsampled data may be filtered in low pass filter 120, which may comprise a digital filter. The resultant data may be downsampled by a factor of N in downsampler 130 which may decimate unwanted data samples. Downsampling may comprise decimating (eliminating) intermediate sample values to create a new sample set at the desired output sample rate.
Low pass filter 120 may be used to eliminate spectral "images" produced when upsampling. Such images are illustrated in FIG. 2. Referring to FIG. 2, the sample data at rate fs is illustrated, along with image data produced during upsampling at sample rates 2fs and 3fs. FIG. 3 illustrates how filtering may be used to eliminate undesirable images while preserving desirable data, as illustrated in FIG. 4 to produce sample rate converted data as illustrated in FIG. 5.
In the example given above for a ratio of sample rates of 4:5, M would equal 4 and N would equal 5. Such a Prior Art sample rate conversion technique may be suitable for relatively simple rate conversions. However, not all scenarios where sample rate conversion is desired have such simple sample rate ratios. For example, when converting by more drastic ratios (e.g., 124:359) the amount of processing required to upsample and then downsample may be prohibitive.
As compared to the simpler scenario where the sampling rates are related by a relatively simple ratio, the term "asynchronous sample-rate conversion" is often used to signify situations where the ratios are rather ill-defined numbers such that their least common multiple is a very large number. Asynchronous sample rate conversion is particularly applicable in cases where data is at the "same" sampling rate, but created with a different clock crystal, and thus at a slightly different sampling frequency. Thus, one set of data might have a sample rate of a "fast" 48 KHz and another might have a sample rate of a "slow" 48 KHz. Such ratios like this that are close to 1:1, but not exact, fall into the category of "asynchronous sample-rate conversion." Asynchronous sample-rate converters are commonly used when bridging two systems that are on different sampling rates and/or master operating clocks.
Additionally, in the field of audio, there are various standards that utilize different sampling rates such as 32 KHz, 44.1 KHz, 48 KHz, and so on, and sample rate converters are commonly used to interconnect different systems with the different standards.
There are times when a digital data stream needs to be converted to a different sampling frequency and in addition, be filtered in some way. One way to accomplish this task would be to have a sample rate conversion block followed by (or preceded by) a filter block. Such a setup would look like one of the block diagrams illustrated in FIG. 10. In the two Prior Art embodiments of FIG. 10, an input signal u(k) 1710 may be fed to a sample rate converter 1720 and a digital filter 1730, in either order depending upon which side of the SRC the filtering is performed. Sample rate converter 1720, as discussed previously herein, alters the sample rate of the digital input data u(k) to a different sampling rate than the input signal, and may be either synchronous or asynchronous. Digital filter 1730 may perform a number of digital filtering operations as desired by a user to alter the input signal. Output signal y(k) is thus suitably filtered and converted for a desired end use.
Applications for such sample rate conversion and digital filtering are relatively common, particularly in the digital audio arts. The Prior Art solutions of FIG. 10, while intuitive, require separate components and/or software for the digital filtering and sample rate conversion steps. Given that both functions may be required in a number of applications, it would be advantageous to combine both functions into one system, to reduce the complexity of hardware and/or software.

Sample rate conversion combined with filter


The four types of the controllable idle time current mirror circuits are presented with an improvement in productivity, performance, cost, chip area, power consumption, and design time. The controllable idle time current mirror circuits basically include a sensing block, triggering transistors, current mirror, current source, a n-bit control circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensing gate, the triggering transistors provide a current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. Time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all controllable idle time current mirror circuits provide a controllable reduction in the difference between the initial condition and the expected condition in order to solve many drawbacks simultaneously. In addition, all the controllable idle time current mirror circuits within applied systems control how fast the applied systems come into regulation or lock. Thus, all the controllable idle time current mirror circuits presented achieve a fast controllable lock-in time, a short controllable start-up time, a controllable reduction in power and time, a significant reduction in design simulation time, an improvement in productivity, and a higher performance.

Switching regulators, phase-looked loops, delay-locked loops are vitally important devices. Switching regulators are building blocks used extensively in power systems, industry, motor, communication, networks, digital systems, consumer electronics, computers, and any other fields that high efficient voltage regulating functions. Phase-looked loops and delay-locked loops are building blocks used extensively in communication, networks, digital systems, consumer electronics, computers, and any other fields that require frequency synthesizing and synchronization.
Switching regulators (i.e., DC-TO-DC converters) can provide output voltages which can be less than, greater than, or of opposite polarity to the input voltage. Prior Art FIG. 1 illustrates a basic architecture of a conventional switching regulator 100. The conventional switching regulator 100 basically consists of an oscillator, a reference circuit, an error amplifier, a modulator including a comparator, resistors, and a control logic circuit. Control technique of switching regulators has typically used two modulators: a pulse-width modulator and a pulse-frequency modulator. The output dc level is sensed through the feedback loop including two resistors. An error amplifier compares this sampled output voltage and the reference voltage. The output of the error amplifier is compared against a periodic ramp generated by the saw tooth oscillator. The pulse-width modulator output passes through the control logic to the high voltage power switch. The feedback system regulates the current transfer to maintain a constant voltage within the load limits. In other words, it insures that the output voltage comes into regulation. However, it takes a long time until the regulated output reaches the equilibrium after the system starts. Since a power supply of a core processor is connected to one of the outputs of switching regulators in most system applications, even the core processor should stand by until it receives the regulated output from the switching regulator, too. Therefore, unfortunately, the conventional switching regulator 100 can not be efficiently implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit since power and time are wasted until the output voltage of the switching regulator comes into regulation. In most switching regulator applications, it is highly desirable to control all switching regulators to start differently according to power sequence such as core-up-first and core-down-last. In addition, the slow start-up of the switching regulator increases design simulation time.
Thus, what is desperately needed is a cost-effective switching regulator that can attain a short controllable start-up time with an improvement in productivity, cost, chip area, power consumption, and design time. The present invention satisfies these needs by providing controllable idle time current mirror circuits utilizing a current mirror and a sensing gate, too.
The phase-looked loop is a very versatile building block suitable for a variety of frequency synthesis, clock recovery, and synchronization applications. Prior Art FIG. 2 illustrates a basic architecture of a conventional phase-locked loop. The conventional phase-locked loop 200 typically consists of a phase-frequency detector (or a phase detector), a charge-pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider in a loop. However, to understand phase-locked loops, phase-locked loops without any frequency dividers in a loop will be considered here. The phase-frequency detector (or a phase detector) is a block that has an output voltage with an average value proportional to the phase difference between the input signal and the output of the voltage-controlled oscillator. The charge-pump either injects the charge into the low-pass filter or subtracts the charge from the low-pass filter, depending on the outputs of the phase-frequency detector (or a phase detector). Therefore, change in the low-pass filter's output voltage is used to drive the voltage-controlled oscillator. The negative feedback of the loop results in the output of the voltage-controlled oscillator being synchronized with the input signal. As a result, the phase-locked loop is in lock.
In the conventional phase-locked loop of Prior Art FIG. 2, lock-in time is defined as the time that is required to attain lock from an initial loop condition. Assuming that the phase-locked loop bandwidth is fixed, the lock-in time is proportional to the initial difference frequency between the initial input signal frequency and the voltage-controlled oscillator's frequency as follows:
            (                        ω          in                -                  ω          osc                    )        2        ω    0    3  where ωin is the input signal frequency, ωosc is the voltage-controlled oscillator's frequency, and ω0 is the loop bandwidth. It should be noted that the lock-in time depends upon a loop bandwidth. If the loop bandwidth of a phase-locked loop is very wide, the lock-in time is very fast.
Most systems require different types of switching regulators, different types of phase-looked loops, and different types of delay-looked loops, which must be integrated on the same chip or board. For example, if two different phase-locked loops which have different bandwidths are used together on the same chip or board, they will result in different lock-in times. In addition, if an output signal of a phase-looked loop is assumed to be used as the input signal of another phase-looked loop, the output signal can not be accurate until both phase-looked loops are locked. Most reliable systems require a fast controllable lock-in time so that different phase-looked loops are locked quickly and synchronously. However, the conventional phase-locked loops including Prior Art FIG. 2 have recently suffered from slow uncontrollable lock-in time in most system applications. As a result, time and power of phase-looked loops are unnecessarily consumed because they are all slow-locking phase-locked loops. In addition, a conventional fast-locking phase-locked loop of Prior Art FIG. 3 is illustrated to overcome the slow-locking problem. The conventional fast-locking phase-locked loop consists of a digital phase-frequency detector including a 6-bit counter, a proportional-integral controller, a 10-bit digital-to-analog converter, and a voltage-controlled oscillator. Unfortunately, the conventional fast-locking phase-locked loop 300 is costly, complicated, and inefficient because additional blocks such as proportional-integral controller and 10-bit digital-to-analog converter take much more chip area and consume much more power. The conventional fast-locking phase-locked loop of Prior Art FIG. 3 has following disadvantages: requirement of complicated stability analysis, bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. In addition, the conventional fast-locking phase-locked loop 300 of Prior Art FIG. 3 can not provide controllable lock-in time. Therefore, the conventional fast-locking phase-locked loop 300 can not be widely implemented in system-on-chip (SOC), integrated circuit (IC), monolithic integrated circuit, and discrete circuit.
Thus, what is desperately needed is a cost-effective phase-locked loop that can attain a fast controllable lock-in time with an improvement in all aspects. The present invention satisfies these needs by providing the controllable idle time current mirror circuits.
Delay-looked loops are typically employed for the purpose of synchronization. Prior Art FIG. 4 illustrates a basic architecture of a conventional delay-locked loop. A conventional delay-locked loop 400 typically consists of a phase detector, a charge-pump, a loop filter, and a voltage-controlled delay line. In delay-locked loops, the phase detector is a block that has an output voltage with an average value proportional to the phase difference between the input signal clock and the output clock at the end of delay line. The charge-pump either injects the charge into the loop filter or subtracts the charge from the loop filter, depending on the outputs of the phase detector. Therefore, change in the loop filter's output voltage will affect the delay time of the voltage-controlled delay line. If delay different from integer multiples of clock period is detected, the closed delay-locked loop will automatically correct it by changing the delay time of the voltage-controlled delay line.
It was just stated that most recent systems require different types of switching regulators, different types of phase-looked loops, and different types of delay-looked loops which must be integrated on the same chip or board. For example, if two delay-locked loops which have different bandwidths are used together, they will result in different lock-in times. In particular, if an output signal of a phase-looked loop is assumed to be used as the input signal of a delay-looked loop, the output signal of the delay-looked loop can not be accurate until the phase-locked loop are locked. Most reliable systems require a fast controllable lock-in time so that both phase-looked loops and delay-looked loops are locked synchronously and quickly. However, most conventional delay locked-loops including the conventional delay locked-loop 400 have suffered from slow-locking, harmonic locking, and uncontrollable locking. As a result, time and power of delay-looked loops are unnecessarily consumed until the delay-locked loops are locked. To overcome the slow-locking problem, a conventional fast-locking delay-locked loop of Prior Art FIG. 5 is illustrated. The conventional fast-locking delay-locked loop 500 basically consists of an analog phase detector, a charge-pump, a loop filter, a voltage-controlled delay lines, a digital phase detector, a 2-bit successive-approximation register (SAR), and a DCDL. Unfortunately, the conventional fast-locking delay-locked loop 500 is costly, complicated, and inefficient to be implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit because additional blocks such as DCDL and 2-bit successive-approximation register (SAR) take much more chip area and consume much more power. In addition, the conventional fast-locking delay-locked loop of Prior Art FIG. 5 might improve the lock-in time, but certainly results in the following penalties: uncontrollable lock-in time, bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. Thus, the conventional fast-locking delay-locked loop 500 can not be widely implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit.
Thus, what is desperately needed is a cost-effective delay-locked loop that can attain a fast controllable lock-in time with an improvement in productivity, cost, chip area, power consumption, and design time. At the same time, what is desperately needed is a cost-effective circuit that enables both phase-locked loops and delay-locked loops to achieve fast controllable lock-in time, and enables switching regulator to achieve a short controllable start-up time with an improvement in all aspects. Lock-in time of phase-locked loops or start-up time of switching regulators can be termed "idle time". The present invention satisfies these needs by providing controllable idle time current mirror circuits, too.
In summary, unfortunately the conventional switching regulator 100 of Prior Art FIG. 1, the conventional phase-locked loop 200 of Prior Art FIG. 2, the conventional fast-locking phase-locked loop 300 of Prior Art FIG. 3, the conventional delay-locked loop 400 of Prior Art FIG. 4, and the conventional fast-locking delay-locked loop 500 of Prior Art FIG. 5 are very inefficient to be implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit. In addition, those integrated circuits 100, 200, 300, 400, and 500 have taken a long time to be simulated and verified before they are fabricated. Also, many other additional drawbacks are described as follows: First, the conventional phase-locked loops 200 and conventional delay-locked loop 400 have suffered from a very long time required to attain lock. Hence, time and power are unnecessarily consumed until the conventional phase-locked loop 200 or the conventional delay-locked loop 400 is in lock. Second, the conventional phase-locked loop 200 has suffered from harmonic locking and the conventional delay-locked loop 400 has suffered from failing to lock. Especially harmonic locking is that the phase-locked loop locks to harmonics of the input signal when a multiplier is used for the phase detector. Third, the conventional switching regulator 100 has suffered from long time to require the output voltage to be regulated. Fourth, simulation time in designing these integrated circuits is absolutely proportional to time required the loops to lock, time to require the output voltage of the switching regulators to be regulated, and number of blocks to be designed and verified. Hence, this long simulation time adds additional cost to the integrated circuit (IC) and serious bottleneck to design time-to-market. Fifth, the conventional locked loops and the conventional switching regulators do not have common analog building block to reduce the number of different blocks that need to be designed and verified. As a result, regularity and productivity can not be achieved. Sixth, the conventional fast-locking phase-locked loop 300 and conventional fast-locking delay-locked loop 500 might improve the lock-in time, but definitely results in uncontrollable lock-in time, bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. Seventh, since lock-in time of phase-locked loops and delay-locked loops and start-up time of switching regulator take different time due to uncontrollable idle time, power and time of most systems are unnecessarily consumed until all systems are in lock or come into regulation and thus power-management of most systems can not be performed.
Thus, what is finally needed is a cost-effective circuit that can make a fast controllable lock-in time for phase-locked loops and delay-locked loops, make a short controllable start-up time for switching regulators, manage power and time consumption for all systems until loops are in lock or until the output voltage of switching regulators comes into regulation, reduce significantly design time for better time-to-market, and improve productivity by reusing the same cost-effective circuit design for the systems such as switching regulators, phase-locked loops, and delay-locked loops to be implemented in system-on chip (SOC), integrated circuit, monolithic circuits, and discrete circuit. The present invention satisfies these needs by providing four embodiments.

Controllable idle time current mirror circuit for switching regulators, phase-locked loops, and delay-locked loops


An apparatus has an input terminal configured to receive an input signal, a network coupled to the input terminal and configured to provide a plurality of amplified input signals, and a directional coupler coupled to the network and configured to couple at least one of the plurality of amplified input signals to an output terminal.

In radio communication systems operating with digital modulation arts amplifiers are required that provide multiple gain steps and that keep the noise figures of the amplified output low. Such Low Noise Amplifiers (LNA) also require input and output return losses independent of the gain step and high linearity also for the low gain modes. Controlling the gain of the Low Noise Amplifier by using current steering techniques shows the disadvantage of higher noise figures occurring in the low gain and medium gain modes than in the high gain modes. Throwing away some of the signal current by dumping to power supply, as is done in some designs of Low Noise Amplifiers for the low and medium gain modes, decreases the signal power, and hence degrades the noise figure by reducing the signal to noise ratio at the output of the Low Noise Amplifier. Cascade Low Noise Amplifiers change the current for the common base transistor by shunting and as a result the output return loss and the linearity degrade.
An approach has to be found that allows independent selection of the gain and the linearity of each state without effecting significantly the other parameters.

Apparatus for coupling at least one of a plurality of amplified input signals to an output terminal using a directional coupler


The invention relates to a heater (1) for use in a room of a dwelling, preferably with a convection surface (3) and, in the case, for example, of a hot-water heater, with a water tank with an inlet and an outlet aperture. To obtain a design more advantageous concerning the use, the heater according to the invention has a separate closed storage chamber (7) containing a latent heat storage medium (8), the storage chamber (7) being heatable by radiation, convection or electrically.

The present invention relates to a heater for use in a room of a dwelling, having a convection surface and in the case, for example, of a hot water heater, a water tank provided with an inlet opening and an outlet opening.
Many embodiments of such heaters are known, for example, as plate heaters or as ribbed radiators, each of which has a considerable radiation surface, In addition, heaters which are optimized with respect to the transmission of heat by convection are also known. They consist, for instance, of fin-like sheet-metal elements which are located closely alongside of each other and are, for instance, arranged in a row on a pipe which passes axially through said sheet-metal elements.
Furthermore, heaters for night storage heating are also known in which a heat storage medium, generally a stone body of high thermal capacitance, is heated during the night by, for instance, electric energy and then gives off heat throughout the day to the room which is to be heated by radiation and convection.
In the case of these known heaters, there can be noted either only a small heat capacity or discomfort as a result of high storage temperatures. In said night storage heaters, the temperature of the heat storage furthermore decreases with increasing liberation of heat. While initially, at high temperatures, there may also, for instance, be a burning of dust and the giving off of odors, this system passes only for a comparatively short period of time through a condition in which heat which is found comfortable is given off.
A certain "tiled stove effect" is sought in the case of such heaters. Heat is to be given off continuously by radiation and convection from surfaces which do not have too high a temperature. Even when there is no further feeding of energy to the heater, as a result, for instance, of the reduction at night in the case of central heating systems, a release of heat which does not drop below the limit of comfort is to be given off still for a certain period of time. This applies in the same way to a temporary priority switching of the heating system to the heating of hot water.
In water heating systems this cannot be obtained due to the fact that the heat-storage capacity is, as a rule, slight. In modern heating systems, the heat storage capacity is particularly low as a result of very small filling volumes. It has also already been proposed to hang in front of heaters ceramic tiles which have a certain, although to be sure slight capacity. They, it is true, provide a certain improvement but they are by far not satisfactory.


Provided is a drive transmission switching mechanism that can switch and drive two circulation units by one motor in response to a switching operation of a paper sheet transport direction. A paper sheet storage unit includes a first circulation unit 100 and a second circulation unit 200 that respectively receive transported paper sheets upon reception of a drive force from a single motor 302 and feed paper sheets stored therein, a sorter 310 that sorts paper sheets to either one of the circulation units, and a drive transmission switching mechanism 400 that transmits a drive force from the motor to either one of the circulation units. The drive transmission switching mechanism is activated in conjunction with an operation to change the posture of the sorter, thereby switching and transmitting the drive force to either one of the circulation units.

As a banknote processing device installed in a banknote handling device such as a vending machine having a function of providing various articles and services by receiving an input banknote, a game-medium lending machine in a game hall, a ticket machine, a cash machine, and a money changer, a circulation-type banknote processing device capable of receiving, storing, and dispensing banknotes of a plurality of denominations has been known.
The circulation-type banknote processing device is provided with a banknote storage unit for storing therein banknotes prepared for payout beforehand and banknotes input during operation by denomination, or in a state of mixed denominations.
There are a circulation-type banknote storage unit having a function of storing banknotes and discharging banknotes to outside as change, and a banknote storage unit for collection (a collection box) that collects all the banknotes in the banknote processing device at the closing time or the like, as the banknote storage unit.
As a configuration of the circulation-type banknote storage unit, such a type has been known in which banknotes are stored between tapes overlapped spirally (helically) and wound around an outer periphery of a circulation drum, like "banknote handling device" disclosed in Patent Literature 1. Further, in the patent literature, there is described a circulation-type banknote storage unit that can store banknotes of different denominations by providing two circulation drums in parallel in one circulation-type banknote storage unit.
However, since it is required to provide a drive motor for each circulation drum, two motors are required in one circulation-type banknote storage unit, thereby causing problems such as an increase in size and weight of each circulation-type banknote storage unit, a decrease in the number of banknotes stacked in each circulation drum, and cost increase.

Drive transmission switching mechanism, paper sheet storage unit, and paper sheet processing device


An image processing apparatus eliminates a detection error in a color offset detecting operation due to a periodic fluctuation in a speed of a conveying belt which conveys a transfer sheet on which color component images are transferred and superimpose to form a multi-color image. A plurality of image forming units are arranged along the conveying belt, each of the image forming units transferring a color component image on the transfer sheet and also transferring a register mark on the conveying belt. A register mark detecting sensor located along the conveying belt detects the register mark on the conveying belt. A distance between the register mark detecting sensor and one of the plurality of image forming units adjacent to the register mark detecting sensor is a multiple of an integer of a circumference of the drive roller. A distance between adjacent ones of the plurality of image forming units is a multiple of an integer of the circumference of the drive roller.

1. Field of the Invention
The present invention relates to a multi-color image forming apparatus such as an electrophotographic apparatus and, more particularly, to a multi-color image forming apparatus in which a plurality of color component images are sequentially transferred and superimposed on a recording medium carried by a conveying belt.
2. Description of the Related Art
In an image forming apparatus such as a multi-color printer or a multi-color copy machine, a plurality of image forming units are serially arranged along a conveying belt, the image forming units form color component toner images corresponding to yellow, magenta, cyan and black. Each of the color component images are transferred and superimposed on a transfer sheet conveyed by a conveying belt so that a multi-color or full-color image is formed. In the above-mentioned image forming apparatus such as an electrophotographic apparatus, it is required to accurately superimpose color component images without an offset with respect to each other so as to form a high-quality color image.
Japanese Laid-Open Patent Application No. 6-18796 discloses an image forming apparatus which corrects a color offset with respect to a reference color (black, for example) by forming register marks corresponding to color component images on a conveying belt and detecting the register marks by a CCD sensor.
Additionally, Japanese Laid-Open Patent Application No. 8-123129 discloses an image forming apparatus similar to the image forming apparatus disclosed in the above-mentioned patent document. The image forming apparatus disclosed in Japanese Laid-Open Patent Application No. 8-123129 further comprises a stain preventing member which prevents formation of a stain on the register marks.
Each of the above-mentioned conventional image forming apparatuses is structured as shown in FIG.1. That is, an image forming unit 20Y, an image forming unit 20M, an image forming unit 20C and an image forming unit 20K are arranged along a conveying belt 35 which is drivingly engaged with a drive roller 36 and an idle roller 37. The image forming units 20Y, 20M, 20C and 20K form a yellow toner image, a magenta toner image, a cyan toner image and a black toner image, respectively.
Additionally, a paper supply cassette 40 which stores transfer papers is provided under the conveying belt 35. A paper supply roller 41 which feeds the transfer paper is provided on an end portion of the paper supply cassette 40. A register roller 42 which feeds the transfer paper to the conveying belt 35 is provided near the image forming unit 20Y. A fixing roller 43 and a pressing roller 44 which fix a toner image formed on the transfer paper are provided near the drive roller 36.
The image forming unit 20Y comprises a photosensitive drum 1Y, a charger 30Y, an optical writing unit 31Y, a developing unit 32Y, a transfer unit 33Y, and a cleaning unit 34Y. The charger 30Y charges the photosensitive drum 1 so that an electrostatic latent image is formed on the photosensitive drum 1Y by the optical writing unit 31Y. The developing unit 32Y develops the latent image as a yellow (Y) toner image. The Y toner image is transferred to transfer paper. The cleaning unit 34Y removes toner remaining on the photosensitive drum 1Y.
Similarly, the image forming unit 20M comprises a photosensitive drum 1M, a charger 30M, an optical writing unit 31M, a developing unit 32M, a transfer unit 33M, and a cleaning unit 34M. The image forming unit 20C comprises a photosensitive drum 1C, a charger 30C, an optical writing unit 31C, a developing unit 32C, a transfer unit 33C, and a cleaning unit 34C. The image forming unit 20K comprises a photosensitive drum 1K, a charger 30K, an optical writing unit 31K, a developing unit 32K, a transfer unit 33K, and a cleaning unit 34K.
In the above-mentioned structure, a position offset sensor 45 is provided near the drive roller 36. The position offset sensor 45 detects register marks formed by the image forming units 20Y, 20M, 20C and 20K. A discharger 38 is provided on the downstream side of the position offset sensor 45 so as to discharge the conveying belt 35. A cleaning unit 39 is provided near the idle roller 37 so as to remove toner remaining on the conveying belt 35.
In the above-mentioned conventional image forming apparatus, the Y toner image is transferred onto a transfer paper by the image forming unit 20Y so that the Y toner image is transferred in synchronization with the conveyance of the transfer paper by the transfer belt 35. The transfer paper having the Y toner image is conveyed to a position corresponding to the image forming unit 20M. Then, a magenta (M) toner image is transferred and superimposed on the Y toner image by the image forming unit 20M. Similarly, a cyan (C) toner image is transferred and superimposed on the M toner image and, then, a black (K) toner image is transferred on the M toner image. Accordingly, a multi-color or full-color image is formed by the superimosingly transferred Y toner image, M toner image, C toner image and K toner image being superimposed. The multi-color image is fixed on the transfer paper by being passed through a portion between the fixing roller 43 and the pressing roller 44.
In the above-mentioned image forming process, register marks corresponding to each color of the image forming units 20Y, 20M, 20C and 20K are formed and developed on an area of each of the photosensitive drums 1y, 1M, 1C and 1K, respectively. The register marks are transferred to the conveying belt 35 in synchronization with a transfer operation of each of the Y, M, C and K toner images by the respective transfer units 33Y, 33M, 33C and 33K. Then, the register marks in each color are read by the position offset sensor 45 so as to detect an offset of the register marks corresponding to Y, M and C with respect to K. A writing position of each of the optical writing units 31Y, 31M, and 31C is adjusted so as to correct the offset detected by the position offset sensor 45.
In the above-mentioned conventional image forming apparatus, since the endless conveying belt 35 is driven by the drive roller 36, speed of the conveying belt 35 periodically fluctuates due to an eccentricity of the drive roller 36 or an eccentricity of rotational force transmitting parts such as a gear for transmitting a rotational force to the drive roller 36.
When such a periodic fluctuation occurs in the speed of the conveying belt 35, the register marks are formed at positions slightly offset from accurate positions in which the register marks are to be formed since the operation of forming the register marks is performed on the assumption that the conveying belt 35 is moving at a constant speed. Accordingly, the register marks are detected by the position offset sensor 45 at slightly offset positions. Thus, there is a problem in that an accurate detection of the offset in the positions of the register marks cannot be performed due to the periodic fluctuation in the speed of the conveying belt 35.
A description will now be given of another conventional image forming apparatus in which a color offset is corrected by detecting a position offset of a register mark corresponding to each color component image.
FIG. 2 is an illustration of a structure of a conventional color image forming apparatus. In FIG. 2, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted. The color image forming apparatus shown in FIG. 2 has the same structure with the image forming apparatus shown in FIG. 1 except for the position offset sensor 45 being replaced with a register mark detecting sensor 14 located on the same side where the image forming units 20Y, 20M, 20C and 20K are located.
In the color image forming apparatus shown in FIG. 2, a recording paper (transfer sheet) 10 is fed onto the conveying belt 35 from the paper cassette 40. The recording paper 10 is secured on the conveying belt 35 by an electrostatic force, and conveyed to the image forming unit 20Y so that an yellow toner image is formed on the recording paper 10. Thereafter, a magenta toner image, a cyan toner image and a black toner image are sequentially and formed and superimposed by the respective image forming units 20M, 20C and 20K. After the black toner image is formed by the image forming unit 20K, the recording paper 10 is passed through the fixing unit comprising the fixing roller 43 and the pressing roller 44 so that the toner image on the recording paper 10 is fixed, and then the recording paper 10 is ejected to a paper eject tray (not shown in the figure). It should be noted that operations of the optical writing units 31Y, 31M, 31C and 31K are controlled by a control unit 53 so that the Y, M, C and K toner images are accurately formed on the respective photosensitive drums 1Y, 1M, 1C and 1K.
FIG. 3A is a perspective view of a part of the color image forming apparatus shown in FIG. 2. In FIG. 3A, a direction indicated by an arrow B (hereinafter referred to as direction B) is perpendicular to a moving direction of the conveying belt 35 indicated by an arrow C (hereinafter referred to as direction C). That is, the direction B corresponds to a primary scanning direction, and the direction C corresponds to a secondary scanning direction. In the color image forming apparatus, if a distance between the image forming units 20Y, 20M, 20C, and 20K or an angle of each of the image forming units 20Y, 20M, 20C and 20K is shifted from a correct position, this causes a color offset (an offset in a registration of color component images) in the output image and results in deterioration of the output image quality. Accordingly, in the color image forming apparatus, each of the image forming units 20Y, 20M, 20C and 20K forms a register mark 15 on the conveying belt 35 so that an offset in a registration of color component images can be detected. The correction is performed based on the offset in the registration of each of the color component images by detecting the register mark 15 formed by each of the image forming units 20Y. 20M, 20C and 20K. The register mark 15 and the register mark detecting sensor 14 are shown in FIG. 3A. The register marks 15 are formed on each side of the conveying belt 35. Thus, the register mark detecting sensor 14 is provided on each side of the conveying belt 35 on the downstream side of the image forming unit 20K so as to detect the register marks 15 formed on the conveying belt 35.
FIG. 3B is a perspective view of the register mark detecting sensor 14. Each of the register marks 15 comprises a mark extending in the direction B perpendicular to the direction C of the movement of the conveying belt 35 and a mark inclined a predetermined angle (for example, 45 degrees) with respect to the direction B. Each of the register mark detecting sensors 14 is located in a position where the register marks 15 can be detected. Hereinafter, a description will be give to one of the register mark detecting sensors 14 since they are identical to each other. The register mark detecting sensor 14 detects a time when the register mark 15 passes the position of the register mark detecting sensor 14. The register position offset of each register mark 15 is obtained based on the time of passage of each register mark 15.
The register mark detecting sensor 14 comprises a light-emitting diode (LED) 14-1, a slit plate 14-2 and a light-receiving element 14-3. The LED 14-1 is located on the side of the conveying belt 35 where the register mark 15 is formed so as to project a light to the register mark 15. The slit plate 14-2 and the light-receiving element 14-3 are located on the opposite side of the conveying belt 35, that is, an inner side of a loop formed by the conveying belt 35. The slit plate 14-2 has a slit having a shape the same as that of the register mark 15 so that the light projected from the LED 14-1 passes therethrough. The light-receiving element 14-3 receives the light passing through the slit of the slit plate 14-2. Accordingly, the light-receiving element 14-3 receives the light projected from the LED 14-1 when the register mark 15 is not present. On the other hand, the light-receiving element 14-3 receives a reduced light when the register mark 15 passes directly above the slit plate 14-2. The light-receiving element 14-3 detects the time when the register mark 15 passes by a difference in the amount of received light.
FIG. 4A is an illustration showing a positional relationship between the register mark detecting sensor 14 and the register mark 15 comprising a pair of marks K1 and K2 formed by the image forming unit 20K (black) and a pair of marks C1 and C2 formed by the image forming unit 20C (cyan). When the mark K1 or C1 is aligned with the slit extending in the direction B, or when the line mark K2 or C2 is aligned with the slit inclined with respect to the direction B, an amount of light received by the light-receiving element 14-3 is minimized. FIG. 4B is a time chart showing a peak of a detection signal output by the register mark detecting sensor 14. The peak indicates a time when the amount of light received by the register mark detecting sensor 14 is minimized. Accordingly, time TK1, TK2, TC1 and TC2 correspond to time when the corresponding marks K1, K2, C1 and C2 pass the register mark detecting sensor 14.
An offset of a register position of the cyan toner image with respect to a reference color toner image (black, in this case) can be obtained by the following relationship, where V0 is a speed of movement of the register mark 15, that is, a speed of movement of the conveying belt 35; and T0 is a time difference between the time when the mark K1 is detected and the time when the mark C1 is detected. It should be noted that an angle of the marks K2 and C2 with respect to the respective mark K1 and C1 is 45 degrees.
An amount E of the offset of a position of the cyan tone image in the primary scanning direction (direction B) with respect to the reference color toner image (black) is represented by the following relationship. EQU E={(TC2-TC1)-(TK2-TK1)}.times.V0 (1)
An amount F of the offset of the position of the cyan toner image in the secondary scanning direction (direction C) with respect to the reference color toner image (black) is represented by the following relationship. EQU F={(TC2-TC1)-T0)}.times.V0 (2)
A description will now be given of a more specific example. It is now assumed that the cyan marks C1 and C2 are spaced from the respective line marks K1 and K2 by a distance of 30 mm in the secondary scanning direction so that the mark K2 (black) does not cross the mark C1 (cyan). Accordingly, if the marks C1 and C2 are shifted toward the marks K1 and K2 by the distance of 30 mm, the line marks C1 and C2 coincide with the respective marks K1 and K2. That is, the cyan marks C1 and C2 do not have a position offset with respect to the black marks K1 and K2.
In FIGS. 4A and 4B, if V0=100 mm/sec; TK1=0 sec; TK2=0.1 sec; TC1=0.3 sec; TC2=0.4 sec; and T0=0.3 sec, this means that a distance between marks K1 and K2 is 10 mm; a distance between marks K1 and C1 is 30 mm; and a distance between marks K1 and C2 is 40 mm. In this condition, an amount of offset of position in the primary scanning direction and the secondary scanning direction can be calculated by the above relationships (1) and (2) as follows. EQU E={(0.4-0.3)-(0.1-0)}.times.100=0 mm EQU F={(0.3-0)-0.3}.times.100=0 mm
As appreciated from above, no offset of position is present in both the primary scanning direction and the secondary scanning direction.
FIGS. 5A and 5B correspond to FIGS. 4A and 4B, respectively, in a case when an offset of position is generated in both the primary scanning direction and the secondary scanning direction. It should be noted that, in FIGS. 5A and 5B, the offset of position is emphasized for the sake of easy recognition.
In FIGS. 5A and 5B, if V0=100 mm/sec; TK1=0 sec; TK2=0.1 sec; TC1=0.301 sec; TC2=0.4015 sec; and T0=0.3 sec, this means that a distance between marks K1 and K2 is 10 mm; a distance between marks K1 and C1 is 30.1 mm; and a distance between marks K1 and C2 is 40.15 mm. In this condition, an amount of offset of position in the primary scanning direction and the secondary scanning direction can be calculated by the above relationships (1) and (2) as follows. EQU E={(0.4015-0.301)-(0.1-0)}.times.100=0.05 mm=50 .mu.m EQU F={(0.301-0)-0.3}.times.100=0.1 mm=100 .mu.m
As appreciated from the above, the amount E of the offset of position in the primary scanning direction is 50 .mu.m, and the amount F of the position offset in the secondary scanning direction is 100 .mu.m.
As mentioned above, the position offset of each color register mark with respect to the reference color register mark can be calculated by detecting the time when each register mark 15 passes the register mark detecting sensor 14. Accordingly, an appropriate correction can be performed for a timing of the image forming operation so as to achieve an accurate registration of the register position.
The above mentioned calculation of the amount of position offset is based on the assumption that the speed V0 of movement of the conveying belt 35 is constant. However, in practice, there is a fluctuation in the speed of movement of the conveying belt 35 due to a fluctuation in a rotational speed of the drive roller or an eccentricity of the circumference of the drive roller with respect to the rotational axis thereof. If the speed of the conveying speed fluctuates, an error may be generated in the calculated amounts E and F of the offset of position.
FIG. 6 is a graph of a speed V of movement in which a periodic fluctuation is generated. In FIG. 6, an average speed V0 of movement of the conveying belt 35 is 100 mm/sec, and a periodic fluctuation of about .+-.0.2 mm/sec is generated.
Consideration is given to a case in which the above-mentioned marks K1, K2, C1 and C2 are detected when the periodic fluctuation is generated in the speed of movement of the conveying belt 35 as shown in FIG. 6. A positional relationship between the marks K1, K2, C1 and C2 is the same as that shown in FIG. 4A. That is, the distance between marks K1 and K2 is 10 mm; the distance between marks K1 and C1 is 30 mm; and the distance between marks K1 and C2 is 40 mm. Thus, if the marks C1 and C2 are shifted toward the marks K1 and K2 by the distance 30 mm, the marks C1 and C2 coincide with the respective marks K1 and K2.
In FIG. 6, a time t when the mark K1 is detected zero (t=0), the speed V(t) of movement of the conveying belt 35 is represented by the following relationship. EQU V(t)=V0+V1.times.cos (.omega.t) (3)
Where, V0=100 mm/sec; V1=0.2 mm/sec; and .omega.=2.pi./1.2 rad/sec.
Additionally, a length L(t) of the conveying belt which passes the register mark detecting sensor 14 can be calculated by integrating the speed of movement L(t) with respect to the time. The result of the integration is as follows. EQU L(t)=V0.times.t+(V1/.omega.).times.sin (.omega.t) (4)
With respect to the time when the marks K2, C1 and C2 are detected, the time should satisfy the condition such as L(t)=10 mm; L(t)=30 mm; and L(t)=40 mm. For example, this condition is satisfied if TK1=0 sec; TK2=0.09981 sec; TC1=0.29962 sec and TC2=0.39967 sec. Additionally, the amount of position offset is obtained by the relationships (1) and (2) as follows. EQU E=0.024 mm=24 .mu.m EQU F=-0.038 mm=-38 .mu.m
As mentioned above, although the register marks shown in FIG. 4A are supposed to have no position offset in either the primary scanning direction or the secondary scanning direction, there is a detection error due to a fluctuation in the moving speed of the conveying belt that cannot be neglected. That is, there is a problem in that an error is generated due to a fluctuation in the moving speed of the conveying belt when an amount of position offset is calculated by detecting the register mark on the conveying belt.

Image forming apparatus eliminating influence of fluctuation in speed of a conveying belt to correction of offset in color registration


Provided is a polymer prepared by using a vegetable oil-derived component and favorably used as a polylactic acid resin-softening agent that is effective in softening the polylactic acid resin while preserving the transparency of the polylactic acid resin and simultaneously resistant to bleeding out (extraction) of itself from the polylactic acid resin. Also provided are a resin mixture of the resin composition and a polylactic acid resin as well as a film or sheet prepared by using the resin mixture.

Recently, such as in plastic waste treatment problem and environmental problem, it is prompted intensive studies for application of polylactic acid resins that is prepared from a vegetable-derived raw material and superior in biodegradability widely as a general-purpose polymer. There are many studies conducted on polylactic acid resin compositions. However, the polylactic acid resin is generally a hard and brittle polymer. For that reason, for use of the homopolymer as it is as a general-purpose polymer in various applications, there are many problems left in individual applications.
In particular, when the polylactic acid resin is to be used as processed into film or sheet, hardness and brittleness of the resin causes a big problem. Various studies are in progress to solve the problem. In particular, widely known are a softening method by addition of a plasticizer such as polyethylene glycol and a method of overcoming brittleness for example by addition of an aliphatic polyester. Combined use of these methods permitted wider use of the polylactic acid. However, the polyethylene glycol, which is used as plasticizer, causes a concern about adverse effect on environment. In addition, there is also a problem that addition of an aliphatic polyester makes the resulting polylactic acid resin opaque.
In addition to the resin modification methods, newly proposed were methods of changing the additive used in the polylactic acid resin to a low-environmental-load material such as vegetable oil-derived component or natural oil-derived component (Patent Documents 1 to 3). These methods are lower in environmental load than traditional methods and improved the heat resistance and the shock resistance of the polylactic acid resin. However, these methods are not those for softening or for prevention of bleeding out (extraction). In these methods, only a vegetable oil-derived component or a natural oil-derived component is blended with the polylactic acid resin. Accordingly, the polylactic acid resin, when processed into film or sheet, does not have a function to prevent bleeding out (extraction) sufficiently.    Patent Document 1: JP-A No. 11-116785    Patent Document 2: JP-A No. 2003-002921    Patent Document 3: JP-A No. 2006-077126

Polymer and a film or sheet containing the same

Abstract: The polymer (C) according to the present invention has an epoxidized vegetable oil segment (A) and a polylactic acid segment (B). The resin mixture according to the present invention is a mixture of the polymer (C) and the polylactic acid resin (D) at a (C)/(D) ratio of 10/90 to 50/50 (weight ratio).


A tool holder. The tool holder includes a back plate and a tubular tool support assembly. The tubular tool support assembly has opposite first and second ends. The first end is attached to the back plate such that when the back plate is held in a vertical plane the tubular tool support assembly extends at a downward angle away from the front face surface of the back plate. The tubular tool support assembly defines upper and lower downward sloping sides of which the upper side comprises a plurality of handle bar sections each comprising upper and lower tube sections and a middle tube section therebetween. At least one lower tube section is aligned in a horizontal plane when the back plate is aligned in a vertical plane, and at least one lower tube section forms part of a tool support hook.

As noted in U.S. Pat. No. 3,985,324, issued Oct. 12, 1976 to Larson, garden tools such as rakes, shovels, hand hoes and the like are often stored in locations where the tools may become a hazard to persons in their vicinity. Unwary or careless people may step on a sharp or pointed tool end, or brush against a precariously balanced implement. These encounters invariably cause aggravation, and can cause serious injury leading to otherwise avoidable medical bills and risk to life, limb and property.
To eliminate such hazards, many people hang such tools on hooks, pegs, nails, or other wall mounts. However, the amount of wall surface available for hanging such tools is often limited, and it is common practice to store a number of tools in stacked relationship upon the same hook or peg. Stacked and hung tools are also hazardous since the endmost tool may fall from the stack, and since the supportive mount may be unable to carry the aggregate weight of these tools. Thus, there is a need for new and/or improved tool holders.


A communication connector including a plug and jack configured to lessen potential for crosstalk caused by unintended mode conversion coupling along wire pairs connected to tine pair 2 (tines T1 and T2) and tine pair 4 (tines T7 and T8). In the plug, twisted pair 2, connected to tine pair 2, and twisted pair 4, connected to tine pair 4, exchange lateral positions with one another thereby reducing differential voltage therebetween and unwanted transmission line mode conversion coupling. In the jack, cross-members and insulators laterally exchange longitudinal routing of the jack tine pair 2 with the jack tine pair 4 for those portions extending away from the plug engagement area of the jack. In particular, the longitudinal routing between tine T1 and tine T8 are laterally exchanged and longitudinal routing between tine T2 and tine T7 are laterally exchanged.

1. Field of the Invention
The present invention is generally related to communication connectors and their components, including telecommunications connectors.
2. Description of the Related Art
Conductors that are not physically connected to one another may nonetheless be coupled together electrically and/or magnetically. This creates an undesirable signal in the adjacent conductor referred to as crosstalk.
By placing two elongated conductors (e.g., wires) alongside each other in close proximity, a common axis can be approximated. If the opposing currents in the conductors are equal, the magnetic field 'leakage' from the conductors will decrease rapidly as the longitudinal distance along the conductors is increased. If the voltages are also opposite and equal, the electric field that is primarily concentrated between the conductors will also decrease as the longitudinal distance along the conductors is increased. This compact pair arrangement is often sufficient to avoid crosstalk if other similar pairs of conductors are in close proximity to the first pair of conductors. Twisting the pairs of conductors will tend to negate the residual field couplings and allow closer spacing of adjacent pairs. However, if for some reason the conductors within a pair are spaced far enough apart, undesired coupling and crosstalk may occur.
The structure of many conventional communication connectors is governed by standards including the RJ-45 type connector by FCC part 68 and the TIA/EIA 568 standards. Conventional telecommunications connectors typically include a communication plug and a communication jack configured to receive the plug. The jack typically provides an access point to a network, a communications device, and the like. Each of the plug and jack include a plurality of conductors or contacts. When the plug is received inside the jack, the contacts of the plug engage the corresponding tines of the jack.
The communication plug is typically physically connected to one end of a communication cable. The communication cable may be a 4-pair flexible cord, and the communication plug may be coupled thereto to create a patch cord. The cable (e.g., a patch cord) allows a communications device to communicate with the network, device, and the like connected to the jack. A convention for communication cables includes four twisted-wire pairs (also known as "twisted pairs"), which are each physically connected to the communication plug. Following this convention, a communication plug has eight contacts (P-T1 to P-T8) each connected to a different wire of the four twisted pairs (referred to as "twisted pair 1," "twisted pair 2," "twisted pair 3," and "twisted pair 4" herein). Each twisted pair serves as a differential signaling pair wherein signals are transmitted thereupon and expressed as voltage and current differences between the wires of the twisted pair. A twisted pair can be susceptible to electromagnetic sources including another nearby cable of similar construction. Signals received by the twisted pair from such electromagnetic sources external to the cable's jacket are referred to as "alien crosstalk." The twisted pair can also receive signals from one or more wires of the three other twisted pairs within the cable's jacket, which is referred to as "local crosstalk" or "internal crosstalk."
The wires of the twisted pairs 1-4 are connected to the plug contacts P-T1 to P-T8 to form four differential signaling pairs: a first plug pair 1, a second plug pair 2, a third plug pair 3, and a fourth plug pair 4. The twisted pair 2 is connected to the plug pair 2, which includes the adjacent plug contacts P-T1 and P-T2. The twisted pair 4 is connected to the plug pair 4, which includes the adjacent plug contacts P-T7 and P-T8. The twisted pair 1 is connected to the plug pair 1, which includes the adjacent plug contacts P-T4 and P-T5. The twisted pair 3 is connected to the troublesome "split" plug pair 3, which includes the plug contacts P-T3 and P-T6. The plug contacts P-T3 and P-T6 flank the plug contacts P-T4 and P-T5 of the plug pair 1. The plug pairs 2 and 4 are located furthest apart from one another and the plug pairs 1 and 3 are positioned between the plug pairs 2 and 4.
A challenge of the structural requisites of conventional communication cabling standards relates to the fact that the two wires of twisted pair 3 are connected to widely spaced contacts P-T3 and P-T6 of the communication plug which straddle contacts P-T4 and P-T5 to which two wires of the twisted pair 1 are connected, while the wires of the twisted pair 2 are connected to contacts P-T1 and P-T2 and the wires of the twisted pair 4 are connected to contacts P-T7 and P-T8. This places the twisted pair 2 and the twisted pair 4 on either side of the twisted pair 3. This arrangement can cause the signal transmitted on twisted pair 3 to impart different voltages and/or currents onto twisted pair 2 and twisted pair 4 effectively causing differential voltages between the composite of both wires of twisted pair 2 and the composite of both wires of the twisted pair 4 as an undesired cable mode conversion coupling that unfortunately may enhance alien crosstalk elsewhere that is referred to hereafter as a "modal launch" or "mode conversion."
Within the communication jack of the communication connector, the jack tines are positioned in an arrangement corresponding to the arrangement of the plug contacts P-T1 to P-T8 in the conventional communication plug. Likewise, the conventional communication cabling standards establish four differential signaling pairs: jack tine pair 2, which includes adjacent communication jack tines J-T1 and J-T2; jack tine pair 4, which includes adjacent communication jack tines J-T7 and J-T8, jack tine pair 1, which includes adjacent communication jack tines J-T4 and J-T5; and a troublesome "split" jack tine pair 3, which includes communication jack tines J-T3 and J-T6. The jack tines J-T3 and J-T6 of the jack tine pair 3 flank the jack tines J-T4 and J-T5 of the jack tine pair 1. Further, the jack tine pairs 2 and 4 are located furthest apart from one another and the jack tine pairs 1 and 3 are positioned between the jack tine pairs 2 and 4.
The "split" jack tine pair 3, with the relatively wide spacing of its jack tine J-T3 with respect to its jack tine J-T6, is especially problematic.
For illustrative purposes, the differential signal carried by the wires and associated fields of the twisted pair 3 through a conventional communication connector will now be described. First, the differential signal is associated with the wires of the twisted pair 3 into the communication plug. Within the communication plug, the wires of the twisted pair 3 are untwisted and spaced apart to connect to the split plug contacts P-T3 and P-T6. The differential signal is conducted by the split plug pair 3 to the split jack tines J-T3 and J-T6. Within the communication jack, the jack tines J-T3 and J-T6 extend inwardly toward one another to place themselves in close proximity to one another. Conductors (e.g., wires) may be connected to the jack tines J-T1 to J-T8 to carry the signal from the communication jack to a destination (e.g., a network, a device, a cable, and the like). The wires connected to the jack tines J-T3 and J-T6 of the jack tine pair 3 may be twisted together to form a twisted pair to further reduce unwanted crosstalk.
In the conventional communication connector, the mode of coupling of present concern is where the wires of twisted pair 3 are split apart within the plug (as the positions of P-T3 and P-T6 are approached) and/or the jack (J-T3 and J-T6). This splitting of wires of twisted pair 3 creates selective capacitive coupling from the two opposing signals on twisted pair 3 and increases the aperture defined by the area between the wires of pair 3 thus causing an increase of magnetic coupling between twisted pair 3 and the composite sets of wires comprising twisted pair 2 and twisted pair 4 where twisted pair 2 is treated as a two-stranded or "composite" wire as is twisted pair 4. As a result, a small "coupled" portion of the differential signal originating on twisted pair 3 appears as two opposite common, or "even," mode signals on the two-wire composites of twisted pair 2 and twisted pair 4.
Thus, where the two-wire composites of twisted pair 2 and twisted pair 4 are treated equally, the signal transmitted on twisted pair 3 may impart opposite voltages and/or currents onto twisted pair 2 and twisted pair 4, respectively, which causes differential voltages between the composite of the two wires of twisted pair 2 and the composite of the two wires of twisted pair 4. This is the coupling, and thus a "launch," of an undesired cable mode conversion that may increase undesired alien crosstalk elsewhere along the transmission path comprised of the plug, the jack and their respective cables.
This transmission path of the plug, the jack and their respective cables can thus be viewed as comprised of a plug in which some of the conductors are located in close proximity to one another and others are spaced farther apart, the interface between a portion of the plug and a portion of the jack and typically the site of origin of undesired mode conversion coupling, and the jack wherein conductors are located in close proximity to one another. This conventional arrangement of the transmission path may cause a "modal launch" that extends from the communication connector into the communication cable connected to the plug and/or the destination connected to the jack.
Within the communication jack, the modal launch effectively treats the jack tine pair 2 (i.e., jack tines J-T1 and J-T2) as a single two-stranded "paired" conductor PC-J1 that is distantly juxtaposed with the jack tine pair 4 (i.e., jack tines J-T7 and J-T8) as its opposite single two-stranded "paired" conductor PC-J2. In other words, the jack tines J-T1 and J-T2 of the jack tine pair 2 combine to form the first single "paired" conductor PC-J1 and the jack tines J-T7 and J-T8 connected to the jack tine pair 4 combine to form the second single "paired" conductor PC-J2. As a result, a "composite" differential pair is created inside the communication jack by the wider spaced apart first and second 'paired' conductors PC-J1 and PC-J2. The wider spacing of first and second 'paired' conductors PC-J1 and PC-J2 will unfortunately enhance vulnerability and sourcing of unwanted crosstalk among other cables situated in the vicinity, such as in a same cable tray, conduit, etc.
As noted, within the communication plug, the modal launch effectively treats the twisted pair 2 as a single two-stranded "paired" conductor PC-P1 that is distantly juxtaposed with the twisted pair 4 as its opposite single two-stranded "paired" conductor PC-P2. Again, the wires of the twisted pair 2 combine to form the first single "paired" conductor PC-P1 and the wires of the twisted pair 4 combine to form the second single "paired" conductor PC-P2. As a result, a "composite" differential pair is created in a communication cable by the wider spaced apart first and second 'paired' conductors PC-P1 and PC-P2. The wider spacing of the first and second 'paired' conductors PC-P1 and PC-P2 will unfortunately enhance vulnerability and sourcing of unwanted crosstalk among other cables situated in the vicinity, such as in a same cable tray, conduit, etc.
Within the plug-jack interface, the typical site of origin of undesired mode conversion coupling, of the communication connector, where the conductors (e.g., the wires of the twisted pair 3, the plug contacts P-T3 and P-T6, and the jack tines J-T3 and J-T6) are spaced apart from one another, the spaced apart conductors may couple (capacitively and/or inductively) with the other conductors of the communication connector. For example, within this plug-jack interface portion of the communication jack, the jack tine J-T3 is adjacent the first paired conductor PC-J1 and the jack tine J-T6 is adjacent the second paired conductor PC-J2. In the plug-jack interface portion of the communication jack, the jack tine J-T3 is capacitively coupled to the first paired conductor PC-J1 and the jack tine J-T6 is capacitively coupled to the second paired conductor PC-J2. A magnetic field forms between the split jack tines J-T3 and J-T6 that induces inductive coupling between split tines and the first and second paired conductors PC-J1 and PC-J2. Within the plug-jack interface portion of the communication plug, a similar result occurs.
A conventional approach to addressing this capacitive and inductive coupling is to cross the split conductors in the plug-jack interface, ideally at a location near a midpoint of the plug-jack interface from which mode conversion coupling occurs. For example, the split conductors may be crossed within the communication jack, the communication plug, or both.
If the split conductors are crossed inside the communication jack, a first portion of the jack tine J-T3 is adjacent the first paired conductor PC-J1 and a second portion of the jack tine J-T3 is adjacent the second paired conductor PC-J2. Likewise, a first portion of the jack tine J-T6 is adjacent the second paired conductor PC-J2 and a second portion of the jack tine J-T6 is adjacent the first paired conductor PC-J1. In other words, any charge in the jack tines J-T3 and J-T6 is adjacent to a portion of each of the first and second paired conductors PC-J1 and PC-J2, thereby substantially negating the effect of the capacitive coupling between the split jack tines and the first and second paired conductors PC-J1 and PC-J2.
Further, by crossing the jack tines J-T3 and J-T6, the direction of the magnetic field formed between the first portions of the jack tines is opposite that of the magnetic field formed between the second portions, which substantially negates the inductive coupling between the split jack tines and the first and second paired conductors PC-J1 and PC-J2. In other words, mode conversion coupling is reduced by removing or subtracting away an equal amount of adverse coupling from each of the first and second paired conductors PC-J1 and PC-J2. A similar result may be obtained by crossing the jack tines J-T3 and J-T6 within the plug-jack interface portion of the communication plug.
Thus, a need exists for communication plugs and communication jacks configured to reduce cross-talk. A further need exists for a communication connector configured to reduce cross-talk caused by unwanted inter-modal coupling between the conducting elements of the connector. The present application provides these and other advantages as will be apparent from the following detailed description and accompanying figures.

Telecommunications connector configured to reduce mode conversion coupling


The present invention provides piezoelectric ceramics having a thickness of 100 μm or less, surface flatness of 20 μm or less and maximum surface uneveness of 3 μm or less in arbitrary surface region, wherein in-plane variation in dielectric constant is 5% or less of an average dielectric constant. The piezoelectric ceramics are applied to an actuator used for a painting head because of small surface flatness and less in-plane variation in piezoelectric constant.

1. Field of the Invention
The present invention relates to piezoelectric ceramics and a method of manufacturing the same, an actuator and a method of manufacturing the same, and a printing head and an ink jet printer and, more particularly, to piezoelectric ceramics and an actuator (i.e., multilayer piezoelectric pile) that are suitable for piezoelectric sensors, for example, acceleration sensor, knocking sensor, AE sensor or the like, fuel injector, printing head for ink jet printer, piezoelectric resonator, oscillator, ultrasonic motor, ultrasonic oscillator and filter, and can be advantageously used particularly for a printing head that utilizes vibration of 2-dimensional vibration of expansion and contraction or linear vibration in longitudinal direction or in the direction of the thickness, and a method of manufacturing the same, and a printing head and an ink jet printer.
2. Description of Related Art
Piezoelectric ceramics have been used in, for example, piezoelectric actuator, filter, piezoelectric resonator (oscillator included), ultrasonic oscillator, ultrasonic motor and piezoelectric sensor.
Among these devices, the piezoelectric actuator is used as the positioning piezoelectric actuator for an X-Y stage of semiconductor manufacturing equipment, the actuator for the printing head of ink jet printer or the like, by making advantage of the very high response of the piezoelectric pile to electrical signals, in the order of 10−6 seconds. The ink jet printing head is mounted to various printers wherein characters or images are printed by discharging a drop of ink from a fine ink outlet orifice, recorders, facsimiles, or ink jet printers such as printer used for formation of patterns in the fields of textile printing and ceramic industry.
Piezoelectric ceramics employed in these applications have hitherto been manufactured by directly interposing a ceramic green sheet having several hundreds of μm between a pair of setters made of a porous sintered body, followed by firing.
There is also proposed a method of adjusting flatness of the sintered body in a range from 30 to 100 μm by arranging spacers on a setter base made of the porous material, arranging a setter cover on the spacers to form space, arranging a green sheet in the space, and firing the green sheet while keeping the space formed between the green sheet and the setter cover in a range from 30 to 100 μm (see, for example FIG. 3 of Japanese Unexamined Patent Publication No. 2002-281453).
When the ceramics body thus obtained is applied to a piezoelectric material, since smoothness of ceramics can be set to a given value or less, it is made possible to avoid breakage when an actuator is fixed onto the plane such as metal plate so as to fix into a printer. Therefore, it is preferably used as the actuator for the printing head of ink jet printer or the like, the positioning piezoelectric actuator for and X-Y stage.
However, according to the method of firing the green sheet while interposing between porous materials described in Japanese Unexamined Patent Publication No. 2000-281453, a component that is easy to evaporate through pores is evaporated and significant in-plane variation in composition occurs in case of obtaining an actuator having a thickness of 100 μm or less. It is difficult to control the surface state of the porous material, the resulting piezoelectric ceramics have increased flatness. Furthermore, deposition of particles degranulated from the setter increases flatness and surface roughness of the sintered body.
According to the method of firing the thin green sheet described in Japanese Unexamined Patent Publication No. 2000-281453, a space between the setters and the green sheet is at least 30 μm. Therefore, in case of obtaining an actuator having a thickness of 100 μm or less, flatness of ceramics increases relative to the thickness.
In case of large flatness, since piezoelectric ceramics are stretched so as to correct its curved state into a planar state when an actuator is fixed to a supporting substrate, residual stress is distributed unevenly across the piezoelectric actuator. In the case of an actuator having a thickness of 100 μm or less, comprising a piezoelectric substrate and a plurality of displacement elements provided on the piezoelectric substrate, its piezoelectric constant varies drastically depending on the displacement elements.
Therefore, there have been required to develop piezoelectric ceramics having small flatness and less in-plane variation in piezoelectric constant, and an actuator that has small flatness and also exhibits less in-plane variation in d constant even after bonding on the supporting substrate.
With recent development of multimedia, a non-impact type recording apparatus that employs an ink jet system or a heat transfer system has been developed in place of an impact type recording apparatus, and thus it has been spreading in the fields of various industries and domestic field.
Among these non-impact type recording apparatuses, a recording apparatus that employs an ink jet system has a bright future because of case of multi-gradation and coloration as well as 1 w running cost.
As shown in FIG. 9(a), a printing head that employs an ink jet system has such a structure that a plurality of channels are arranged in parallel as ink flow passages 23a and an actuator is provided on flow passage members 23 formed with partition walls 23b as a wall that partitions the respective ink flow passages 23a (see FIG. 1 of Japanese Unexamined Patent Publication No. 11-34321).
That is, an actuator is bonded with flow passage members 23 so that individual electrodes 26 are disposed right on ink flow passages 23a as openings of flow passages members 23 in an actuator wherein a common electrode 26 are formed on the other side and a plurality of displacement elements 27 are provided.
With such a configuration, a voltage is applied between the common electrode 25 and the individual electrodes 26, thereby to vibrate the displacement elements 27, and thus ink in ink flow passages 23a is compressed and a drop of ink is discharged from ink outlet orifices 28 that open at the bottom of the flow passages members 23.
As shown in FIG. 9(b), a lot of individual electrodes 26 are arranged in parallel on a piezoelectric layer 24 at equal distances to form a printing head provided with a lot of displacement elements 27, thereby making possible to contribute to realize high speed and high accuracy of an ink jet printer.
It has recently been developed about an ink jet printer with high speed and high accuracy. As a result, the displacement element 27 having a close relation with discharge of ink, especially the piezoelectric layer 24 requires thickness reduction and piezoelectric characteristic with high accuracy. Specifically, a photoelectrically actuator with less variation in characteristic is required.
For the purpose of making the thickness of the ceramic layer and the piezoelectric layer uniform, there is made a trial of previously decreasing an amount of a solvent in a slurry for formation of a tape to around ⅓ of the amount of the prior art thereby to reduce variation in thickness during drying, making the thickness of the slurry uniform by passing through a plurality of rolls and subjecting the slurry to the drying step, thus reducing variation in green sheet having thickness of 500 μm (Japanese Unexamined Patent Publication No. 2000-232035).
However, according to the method of decreasing the amount of the solvent described in Japanese Unexamined Patent Publication No. 2000-232035, the slurry for formation of a tape has high viscosity and the tape thus formed has large thickness. Usually, a thick tape having a thickness of several hundreds of micrometers is merely formed because of less shrinkage caused during drying, and a thin tape having a thickness of 50 μm, especially several tens of micrometers can not be formed. To the contrary, the amount of the solvent contained in the slurry for formation of a tape must be increased so as to form a thin tape, and thus variation in thickness occurs during the drying step. Consequently, a thin tape with less variation in thickness can not be formed.
Therefore, a thin laminated piezoelectric pile having a thickness of 100 μm or less with less in-plane variation in thickness is required.

Method of manufacturing piezoelectric ceramics