The present inventions relates to a solid composition and an aqueous dispersion comprising nanoparticles of the anti-retroviral drugs lopinavir and ritonavir. The solid composition and aqueous dispersion additionally comprise a mixture of a hydrophilic polymer and a surfactant. The surfactant is selected from vitamin-E-polyethylene glycol-succinate (Vit-E-PEG-succinate), a polyoxyethylene sorbitan fatty acid ester, N-alkyldimethylbenzylammonium chloride, sodium deoxycholate, dioctyl sodium sulfosuccinate, polyethyleneglycol-12-hydroxystearate, polyvinyl alcohol (PVA), and a block copolymer of polyoxyethylene and polyoxypropylene, or a combination thereof. The hydrophilic polymer is suitably selected from polyvinyl alcohol (PVA), a polyvinyl alcohol-polyethylene glycol graft copolymer, a block copolymer of polyoxyethylene and polyoxypropylene, polyethylene glycol, hydroxypropyl methyl cellulose (HPMC), and polyvinylpyrrolidone, or a combination thereof. The present invention also relates to processes for preparing both the solid composition and the aqueous dispersion, as well as to their use in therapy for the treatment and/or prevention of retroviral infections such as human immunodeficiency virus (HIV).

Human Immunodeficiency Virus (HIV) is a major cause of morbidity and mortality in both the developed and the developing world. HIV is a retrovirus that causes acquired immunodeficiency syndrome (AIDS) in humans, which in turn allows life-threatening infections and cancers to thrive as the immune system progressively fails.
HIV infection typically occurs through the transfer of bodily fluids, such as blood, semen, vaginal fluid, pre-ejaculate, or breast milk, from one individual to another. HIV may be present within these bodily fluids as either the free virus, or as a virus present within the infected immune cells. HIV-1 tends to be the most virulent form of HIV, and is transmitted as a single-stranded enveloped RNA virus which, upon entry into a target cell, is converted into double-stranded DNA by reverse transcription. This DNA may then become integrated into the host's DNA where it can reside in a latent from and avoid detection by the immune system. Alternatively, this DNA may be re-transcribed into RNA genomes and translated to form viral proteins that are released from cells as new virus particles, which can then spread further.
Treatments of HIV, particularly HIV-1, commonly involve combination therapy with a co-formulation of lopinavir (LPV) and ritonavir (RTV). Such co-formulations are currently sold commercially as either film coated tablets or an oral solution both under the trade name Kaletra®. Lopinavir and Ritonavir are both protease inhibitors (PI) widely used in antiretroviral therapy. However, Ritonavir is no longer commonly used for its own antiretroviral activity but rather to boost the activity of other protease inhibitors, such as Lopinavir. In particular, Ritonavir is used to inhibit liver enzymes (e.g. cytochrome P450-3A4-CYP3A4) responsible for metabolising protease inhibitors such as lopinavir. Such metabolism inhibition allows for higher blood plasma concentrations of protease inhibitors such as Lopinavir, thereby allowing lower doses of Lopinavir to be administered. This in turn reduces the adverse side effects associated with high doses of Lopinavir.

Although current co-formulations of lopinavir and ritonavir are effective in prolonging life expectancy in HIV suffers, there remain a number of drawbacks associated with the currently available formulations.
Lopinavir acts on an intracellular target, so the ability of lopinavir to penetrate and accumulate within cells is a prerequisite for effective treatment (Owen and Khoo, Journal of HIV Therapy, 2004, 9(4), 53-57). One particular problem with the current formulations of lopinavir and ritonavir is that the penetration of lopinavir into cells is variable and inadequate both within and between patients. As cellular penetration and accumulation of the drug is necessary in order to effectively treat the HIV infected cells, there is a need for combination formulations of lopinavir and ritonavir that exhibit good levels of cellular accumulation, particularly in immune cells (e.g. macrophages and CD4+ lymphocytes).
In addition, the distribution of lopinavir throughout the body is also not uniform with current LPV/RTV co-formulations, and certain target tissues and sanctuary sites, such as the brain and the testis, suffer from poor exposure to the lopinavir. This can lead to sub-therapeutic levels of the drug reaching certain tissues, with the consequential effect that HIV infected cells residing in these tissues may not be adequately treated. Furthermore, resistance to lopinavir is becoming an increasing problem (Goshn et al., AIDS, 2009, 11, 165-173) and exposure to sub-therapeutic levels of lopinavir in these tissues increases the risk that lopinavir-resistant strains of HIV can arise and reseed the blood. Resistant strains of HIV are also transmittable meaning that individuals can be newly infected with resistant virus. There is, therefore, a need for LPV/RTV formulations that provide an improved distribution of lopinavir throughout the body, and in particular to sanctuary sites for the virus.
A further problem with current LPV/RTV co-formulations is that it is necessary to administer large doses of lopinavir each day (typically the adult dose is 400 mg/100 mg lopinavir/ritonavir twice daily), despite the "boost" effect provided by ritonavir. As a consequence, a patient will need to consume a large tablet or capsule of LPV/RTV or multiple smaller dosage tablets or capsules in order to obtain the required dosage. This can inevitably lead to problems with patient compliance. Furthermore, lopinavir treatment is also associated with a number of adverse side effects, which represent a major problem for patients, especially over prolonged periods (Delaugerre et al., Antimicrob. Agents Chemother., 2009, 53(7), 2934-2939). For these reasons, there is a need for more effective formulations of LPV/RTV, which in turn may enable the required dosage of lopinavir to be reduced. Lower doses could have an effect on the number and/or size of the tablets/capsules that need to be consumed by the patient, as well as prevalence of the adverse side effects.
A further problem with current LPV/RTV co-formulations is that the ratio of lopinavir/ritonavir is relatively low (typically 4:1) and thus doses of ritonavir are high. Ritonavir itself gives rise to adverse side effects and, in addition, detrimentally affects the efficacy of many other medications. This can lead to difficulties when certain other drugs are co-administered with ritonavir.
There is also a need for dosage forms that permit the dosage to be easily varied on a patient-by-patient basis depending on factors such as the age (including paediatric dosing) and weight of the patient, as well as the severity and stage of the infection.
It is therefore an object of the present invention to provide improved LPV/RTV co-formulations that address one or more of the drawbacks associated with the current LPV/RTV co-formulations.
In particular, it is an object of the invention is to provide a LPV/RTV co-formulations exhibiting good cell penetration and a more optimum and effective distribution throughout the body.
Another object of the present invention is to provide a LPV/RTV co-formulation with a high drug loading.
Another object of the present invention is to provide a formulation which permits lower overall dosage levels of either or both of lopinavir and ritonavir in HIV treatments.


An available network address is acquired from a network address resource pool associated with the application system according to determination that a workload at a set of network ports of the application system meets a predetermined extension condition, the network address resource pool comprising network addresses configured to be assigned to the application system. A network port available at the application system is selected. A communication channel for accessing the application system is established based on the network address and the network port. According to determination that an access request for accessing the application system is received from an access device, the access request is responded to by using the communication channel. The communication channel provided by the application system to the access device can be dynamically adjusted in real time according to a workload related to data access of the application system.

With the development of computer technologies and network technologies, a variety of application systems have emerged at present. For example, in an application system that provides storage services, users can store data to and/or retrieve data from the application system. In an application system that provides computing services, users can provide input data to the application system and retrieve computing results. When a large number of users access an application system, the bandwidth available to each user will be reduced, which leads to a decrease in a data transmission speed and a longer waiting time for the users. In this case, how to access the application system more effectively has become a hot topic of research.

Method, device, and computer program product for accessing application system


According to one embodiment, a player may accumulate occurrences of a bonus symbol over at least two outcomes. The player may be allowed a bonus if a running count of the occurrences is at least equal to a predetermined number. According to another embodiment, a player may accumulate occurrences of matched lottery numbers over a plurality of lottery outcomes (e.g., lottery number drawings) and/or a plurality of lottery entries. The player may be allowed a bonus if a running count of occurrences of matched numbers is at least equal to a predetermined number.

Instant, or "scratch-off", lottery games are well known and widely practiced. Such instant lottery games are games that allow a player to purchase a chance to win one of a set of prizes. For example, for $1 a player may purchase a chance to win $10,000, $1,000, $100, or two (2) extra chances to win a prize. Such games typically involve the sale to a player of a paper or cardboard game ticket. A typical instant lottery game ticket includes a background section and a play section. The background section typically includes the name of the game, instructions for playing the game, information describing the game, and information describing how to win an award. The play section of such a ticket typically includes one or more play areas which contain an outcome. The outcome comprises a combination of symbols (e.g. alphanumeric characters or icons) that are initially hidden from the player. The outcome is typically hidden by an opaque covering material, such as a layer of latex. The player reveals the outcome by scratching off (such as with a coin) the covering layer over the symbols.
Certain outcomes or combinations of symbols in instant lottery games correspond to respective prizes. Which combinations of symbols correspond to which prizes is typically displayed to the player on the background area of the ticket. Thus, a player that purchases such an instant lottery ticket knows whether or not he has won a prize as soon as the covering layer is scratched off. If the outcome revealed by the player matches a combination of symbols that corresponds to a prize, the player may exchange the ticket with the winning outcome for the prize corresponding to the combination of symbols revealed on the ticket. For example, if the player purchased the instant lottery ticket from a convenience store and the corresponding prize is $25, the player may return to the convenience store and exchange the winning ticket for the $25. The convenience store may then turn in the exchanged ticket to the authority administering the lottery to recoup the $25 provided to the player. For larger prizes the player may need to turn in the ticket directly to the authority administering the lottery game.
Recently electronic instant lottery games have been gaining popularity. An example of such an electronic instant lottery game is disclosed in U.S. Pat. No. 5,871,398. U.S. Pat. No. 5,871,398 discloses an off-line remote lottery system which enables a player to purchase instant-type lottery game outcomes from a central computer. The player views the outcomes on a remotely located gaming computer, such as a Personal Digital Assistant (PDA). In such electronic versions of an instant lottery game each outcome is essentially a 'ticket' which the player purchases.
Both the traditional and the electronic instant lottery games offer opportunities for improvement. For example, the instant lottery game is played in a very short amount of time (i.e. the amount of time it takes a player to scratch off the latex covering and reveal the outcome). Once the player reveals the outcome the game is over. If the outcome does not correspond to a prize this feels very discouraging to the player, who may feel that the money that was spent on the purchase of the ticket vanished in an instant without providing a sufficiently entertaining experience. Such a feeling may discourage a player from purchasing another ticket. Also, the loyalty of a player who purchases tickets frequently or purchases a plurality of tickets is not recognized or rewarded in the prior art instant lottery systems, which may discourage a player from continuing to purchase tickets. At the very least the player is not encouraged to continue to purchase tickets for a particular instant lottery game or from a particular instant lottery game authority. Improvements to the prior art systems of instant lottery games are needed to overcome such disadvantages.

This patent is subject to a terminal disclaimer.

Methods and apparatus for lottery game play aggregation


A fuel supply for a fuel cell including a fuel container and an impurity removal cartridge connected to the fuel container, where both the fuel container and the impurity removal cartridge are integrated into a single unit.

During the past several years, the popularity and viability of fuel cells for producing large and small amounts of electricity has increased significantly. Fuel cells conduct an electrochemical reaction with chemicals such as hydrogen and oxygen to produce electricity and heat. Fuel cells are similar to batteries, but fuel cells can be "recharged" while providing power and are much cooler and cleaner than devices that combust hydrocarbons. Fuel cells provide a DC (direct current) voltage that may be used to power motors, lights, computers, or any number of electrical appliances. There are several different types of fuel cells, each using a different chemistry. Fuel cells are usually classified by the type of electrolyte used. The fuel cell types are generally categorized into one of five groups: proton exchange membrane (PEM) fuel cells, alkaline fuel cells (AFC), phosphoric-acid fuel cells (PAFC), solid oxide fuel cells (SOFC), and molten carbonate fuel cells (MCFC).
Each of the fuel cells mentioned above uses oxygen and hydrogen to produce electricity. Ambient air typically supplies the oxygen for a fuel cell. In fact, for the PEM fuel cell, ordinary air may be pumped directly into the cathode of the fuel cell. However, hydrogen is not as readily available as oxygen. Hydrogen is difficult to generate, store, and distribute for a number of reasons and is generally handled with appropriate precautions to reduce potential safety hazards.
One common method for producing hydrogen for fuel cells is through the use of a reformer. A reformer is fed hydrocarbons or other fuels from which hydrogen is produced. The hydrogen produced by the reformer can then be fed to a fuel cell and processed with oxygen to produce the desired electricity. The use of a reformer allows for the production of hydrogen from propane, butane, or a number of other readily accessible natural gases that serve as the hydrogen fuel source.
Since many common hydrocarbon gases are not readily detectible by human senses, odorizing agents such as sulfur are typically included with the hydrocarbons as a safety feature. If a leak of the hydrocarbons occurs, the leak may be readily detected by smelling the odorizing agent. In some instances, sulfur can occur as a natural constituent of the gaseous fuels. However, many consumer grade hydrocarbons produce undesirable byproducts such as SOx and NOx. These by-products are not only pollutants but may also damage the reformer of a fuel cell system. Sulfur, in particular, must be removed from the fuel being fed to the reformer or damage may occur to the electrode catalyst.
One possible solution to prevent sulfur from reaching the reformer and subsequently the electrode catalyst is to use deodorized fuels as the hydrogen source. However, by deodorizing the fuels used to generate hydrogen, it becomes impossible to smell a fuel leak. If a leak goes undetected because it is imperceptible, the hazards and potential damage that may be caused by the leak are greatly increased. This would likely result in additional shipping, storage, and usage restrictions on the fuel, thereby increasing the fuel cost.

Integrated fuel container and impurity removal cartridge

Hewlett-Packard Development Company, L.P.


A score-keeping ring toss game comprising a target and a target switch member which transitions from an open state to a closed state when the target is rung by a ring-shaped member. A proximity switch member comprising a plurality of concentric circles around the target is provided wherein the proximity switch member produces a closed circuit if the ring-shaped member misses the target and engages the plurality of concentric circles. The target switch member and the proximity switch member are coupled to a control unit for determining if the target switch member has transitioned to the closed state or whether the proximity switch member has produced the closed circuit for producing an output signal on a first output path or a second output path. The output signal is accumulated and displayed for each player.

Ring toss games played on the lawn are well known. Each player or team takes a turn tossing a washer or the like (hereinafter referred to as washer) in an attempt to ring the target with the washer. Points are accumulated as each player rings the washer around the target or comes within close proximity to the target. As is evident, the washer game is similar to the horseshoe game.
Several devices have been patented which are aimed at ring toss games, such as those described in U.S. Pat. No. 4,120,499, by Stazzone; U.S. Pat. No. 4,203,592, by Quatkemeyer; U.S. Pat. No. 4,982,966, by Teafatiller; U.S. Pat. No. 4,989,880, by Gettemeier et al.; U.S. Pat. No. 5,018,745, by Dunse; U.S. Pat. No. 5,040,801, by Weymuth; and, U.S. Pat. No. 5,067,727, by Crompton. While each of the above ring toss games function as desired, none of them automatically keep score. A ring toss game which automatically keeps score is highly desirable for those who are lazy. Additionally, because the players must stand a significant distance from the target, the players often get frustrated when they have to repeatedly walk to the target to determine if the washer came in close enough proximity to the target in order to get points. Furthermore, the players must remember the accumulated score while playing the game or maintain a written tally of the points accumulated during the game.
It can be readily seen that there exists the continuing need for a score-keeping ring toss game which automatically keeps score for each player or team and varies the amount of points given for each toss based on at least two conditions.


A digital camera and an image editing system capable of inputting information corresponding to each photographed image every time a picture is taken. When an editing mode transfer switch is depressed in a photographing mode, a memo setting screen is displayed Then, if a text-based input title is selected, a soft keyboard is displayed, and text data is inputted from a touch panel on the by operating a touch pen so as to edit a memo. Then, the operation returns to the photographing mode, and a shutter button is depressed, so that image data is fetched from a imaging element to be stored in a memory card as an image file. At this time, memo information is stored in a header of the file format. When transmitting the image file, the file is also sent together with the memo information.

1. Field of the Invention
The present invention relates to a digital camera and an image editing system using this digital camera.
2. Description of the Prior Art
Recently, digital cameras have been in widespread used in place of analog cameras. The advantages of the digital cameras are as follows.                Images photographed can be directly viewed on a display device such as a liquid crystal display (LCD) of a camera, and the like.        Images unsuccessfully photographed can be cancelled.        Images photographed can be stored in a personal computer (hereinafter referred to as "PC") to be processed and edited by digital processing with ease.        Printing of images is available by means of the PC, and the images can be transmitted as digital files.        By transferring photographed images to the PC, digital images can be stored without degradation.        Multimedia images such as moving images and sounds can be handled.
For these reasons, the digital cameras have increasingly been used with the spread of PC. Further, in the digital cameras, the number of pixels is increased as technology of CCD advances. For example, digital cameras having 2.0 mega pixels to 3.0 mega pixels or more have been on sale. Thus, the digital cameras have come in widespread use not only in a consumer market but also in a business market.
An example of a digital camera used in a car insurance company in a business market will be described below.
In the car insurance company, the following business flow will take place when a vehicle is insured.                1) The vehicle is photographed (to obtain about ten prints) by the digital camera (so as to confirm damage and the like).        2) Data on the vehicle (vehicle type, insurance number, and the like) are described or recorded.        3) Photographs of the vehicle are displayed on the PC to be edited, and then editing such as attaching the insurance number to the image is performed.        4) An external medium including the photographed images and the data are mailed or transmitted by e-mail to a person in charge of estimate.        5) The photographed images are stored in a database of the PC. At this time, the insurance number and the like are inputted.
Conventionally, in the photographs a date and a photographer's name can be included. That is, in a set-up mode, settings of the date and the photographer's name are inputted, and then a position of the photograph for such information to be entered, namely an upper right position, an upper left position, a lower left position, or a lower right position is set, so that the date and the photographer's name are entered into the photographed image.
However, once data including the date, the photographer's name, or the like is set, it will not to be changed at each time of photographing. So, data corresponding to each photographed image cannot be inputted.
Conventionally, as mentioned in the above-mentioned business example, photographed images are grabbed or captured into a personal computer, and then an insurance number for business or a scene number is inputted with the aid of image editing application software on the personal computer.


An expandable sealed container is formed of first and second panels, each formed of at least first and second sheets. The first sheet of each of the panels is formed of a polyvinyl fluoride film and the second sheet is formed of a flexible vinyl. In one embodiment, one surface of the polyvinyl fluoride film is treated to receive an adhesive to adhesively join the polyvinyl fluoride sheet to the vinyl sheet. The opposed second surface is capable of receiving a heat seam to form a complete peripheral seal about the container. In one configuration, the polyvinyl fluoride film sheets of each pair of sheets are facing each other and receive the heat seam. Alternately, the vinyl layers are disposed innermost to receive the heat seam. Further, a polyvinyl fluoride film having both surfaces treated to receive an adhesive is adhesively joined to the outermost surface of the vinyl sheet. The heat seam is formed about the periphery of the vinyl sheets.

1. Field of The Invention
The present invention relates, in general, to sealed, expandable containers and, more specifically, to gas containers formed of multiple sheet layers.
2. Description of the Art
Expandable sealed containers or bags are employed in numerous applications, such as for collecting and temporarily storing gas emissions for motor vehicles before the collected emissions are analyzed by test equipment. Such containers are expandable to a constant volume to collect a known quantity of gaseous emissions.
Such expandable containers typically include a fitting sealingly mounted through one sidewall which is connectable to an external gas source and discharge device for receiving external gases and for discharging such gases from the container. The fitting directs the gas into the container for storage as well as allowing the stored gas to be completely evacuated from the container. The fitting and the sealed container are typically made of an inert material, such as a fluorinated carbon plastic sold under the registered trademarks TEFLON and TEDLAR.
In constructing such an expandable container, single thickness or ply sheets are overlaid on each other and sealingly connected at their peripheral edges by a conventional heat seam or seal.
TEDLAR polyvinyl fluoride film (PVF) is ideally suited for a number of applications due to its resistance to many chemicals, ultraviolet radiation, etc. In expandable container applications, polyvinyl fluoride film is used in a surface characteristic allowing heat sealing. Other formulations of TEDLAR polyvinyl fluoride film cannot be heat sealed. TEDLAR polyvinyl fluoride film is available in at least two formulations labeled "A" TEDLAR and "B" TEDLAR. "B" TEDLAR is treated on both side surfaces to enable adhesive to adhere to the sheet thereby permitting the bonding of the polyvinyl fluoride film or sheet to another sheet or material layer. For example, TEDLAR PVF film is laminated by an adhesive to flexible and reinforced vinyl fabrics for a number of indoor and outdoor applications including signs, awnings, and protective covers. The fabric or filaments are typically disposed inside of the PVF material layers to provide strength and stability to the material stock. The PVF film is disposed outermost over the vinyl fabric for ultraviolet protection and easy cleanup.
However, "B" TEDLAR which is treated on both surfaces for receiving adhesive is not heat sealable thereby preventing the use of this material in expandable bags formed of multiple sheets which are heat sealed at their peripheral edges. "A" TEDLAR PVF film has only one surface treated for receiving an adhesive. The other surface is "strippable" so as to be heat sealable to like "A" TEDLAR PVF films. Thus, it would be desirable to provide a sealed, expandable container which makes use of the advantages of a multiple ply stack of polyvinyl fluoride film and other materials while at the same time being easily heat sealable to form a sealed interior container. It would also be desirable to provide a sealed container formed of multiple ply sheets in which at least one sheet is a polyvinyl fluoride film and the at least one other sheet is a flexible vinyl.
In certain applications, the noise generated by the crinkling of the expandable container as it expands and contracts is objectional. Thus, it would be desirable to provide an expandable sealed container which is constructed to generate less objectional noise during expansion and contraction of the container.


A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state. A resistive divider circuit, including at least two resistors connected in series with each other at a tap, is connected in series with the source-drain circuit of the static current control transistor. The tap of the resistive divides circuit is connected to the input node of the pulse generation circuit to supply the flip signal.

1. Technical Field of the Invention
The present invention relates to power on reset circuits or other circuits configured to generate a one-shot pulse
2. Description of Related Art
Reference is now made to FIG. 1 wherein there is shown a schematic diagram of a prior art power on reset circuit 100. At the heart of the circuit 100 is a latch 102 formed by transistors Q1–Q4. More specifically, p-channel transistors Q1 and Q2 are connected in a cross-coupled relationship wherein the gate of one transistor is connected to the drain of the other transistor. The sources of transistors Q1 and Q2 are connected to Vdd. The gate of transistor Q1 is further connected to Vdd through a capacitor C1, and the gate of transistor Q2 is further connected to ground (GND) through a capacitor C2. The latch 102 further includes a pair of n-channel transistors Q3 and Q4. The drain of transistor Q3 is connected to the drain of transistor Q1 at a first latched node 104 of the latch 102, while the source of transistor Q3 is connected to ground. The drain of transistor Q4 is connected to the drain of transistor Q2 at a second latched node 106 of the latch 102, while the source of transistor Q4 is connected to ground. The gates of transistors Q1 and Q3 are connected together and to the second latched node 106. The gates of transistors Q2 and Q4 are connected together and to the first latched node 104.
The circuit 100 further includes a p-channel transistor Q5 and an n-channel transistor Q6 source-drain connected in series between Vdd and ground. The gate of transistor Q5 is connected to a feedback node 120 and is further connected to Vdd through a capacitor C3, while the gate of transistor Q6 is connected to Vdd
The connected drains of transistors Q5 and Q6 are connected at an input node 122 to the gate of n-channel transistor Q7 and are further connected to ground through a capacitor C4. The source of transistor Q7 is connected to ground, and the drain of transistor Q7 is connected to the second latched node 106 within latch 102.
The first latched node 104 of the latch 102 is connected to the input of a first CMOS inverter 108, and the output of the first CMOS inverter 108 is connected to the input of a second CMOS inverter 110. The output of the second CMOS inverter 110 is connected to Vdd through a capacitor C5 and is further connected to the input of a third CMOS inverter 112. The output of the third CMOS inverter 112 is connected to the input of a fourth CMOS inverter 114. The output of the fourth CMOS inverter 114 is connected at feedback node 120 to the gate of transistor Q5 and is further connected to the input of a fifth CMOS inverter 116, whose output provides the power on reset (POR) signal.
The circuit 100 further includes n-channel transistors Q8–Q10. The transistor Q8 is source-drain connected between latched node 104 and Vdd. The gate of transistor Q8 is connected to ground through a capacitor C6, and is connected to both the gate and drain of transistor Q9 and also to the source of transistor Q10. The source of transistor Q9 and the gate and drain of transistor Q10 are connected to Vdd.
The circuit of FIG. 1 is used to generate a single pulse at power on of Vdd. This single pulse can be used in many applications including initializing latches, nodes and kick starting oscillator circuits.
Reference is now additionally made to FIG. 3 wherein there is shown a waveform trace illustrating operation of the circuit of FIG. 1. As Vdd ramps up and exceeds the Vtp level of the latch 102, the latched nodes 104 and 106 assume a certain state relationship. For example, the transistors Q1–Q4 can be dimensioned in such a way as to set latched node 104 low and latched node 106 high as the circuit begins to power up. With latched node 106 high and latched node 104 low, the set of CMOS inverters 108–114 will set feedback node 120 low and thus turn on transistor Q5. Through the CMOS inverter 116, the POR output signal will go high (as shown at reference 130 in FIG. 3). Transistor Q5, which is now on, then fights against turned on transistor Q6 to pull input node 122 high and charge the capacitor C4. When input node 122 then exceeds Vtn as it goes high (following an RC time constant induced delay), transistor Q7 turns on and drags latched node 106 from the high towards the low state. This causes latch 102 to trip and drive latched node 106 low and send latched node 104 high. With latched node 106 low and latched node 104 high, the set of CMOS inverters 108–114 will set feedback node 120 high and thus turn off transistor Q5 (and therefore cut-off the static current flowing through transistors Q5 and Q6 to minimize power drain). Through the CMOS inverter 116, the POR output signal will then go low (as shown at reference 132 in FIG. 3). Input node 122 then returns low and turns off transistor Q7 thus preserving the latched states of the latch 102.
Some companion circuits used with the circuit 100, such as, for example, a low current oscillator, require that the POR signal transition from high to low at about Vdd=1.2 V for the worst case condition (considering process and temperature variation). It is recognized by those skilled in the art that the Vdd voltage level transition point for the POR signal from high to low (reference 132) is dependent on the ratio of transistors Q5 and Q6. In a common application of the circuit 100 of FIG. 1, the ramped-up Vdd voltage level is typically 3.3 V or 5.0 V. Since Vdd has to power up to a minimum of 3.0 V in these technologies, the window to generate the transition of the POR signal (at the trip point, reference 132) by properly setting the ratio of transistors Q5 and Q6 is quite wide. For example, the trip point could be relatively easily set through proper ratio setting anywhere from 1.2 V to 2.9 V.
A problem, however, arises when the circuit of FIG. 1 is considered for use in a technology wherein Vtn or Vtp voltages are less than 0.5 V and the ramped-up Vdd voltage level is 1.3 V. Operation of the circuit 100 with a ramped-up Vdd voltage of 1.3 V is specifically illustrated in FIG. 3. The window to generate the trip point in this scenario is very tight with respect to Vdd, and more specifically is from the Vtp voltage level to 1.2 V. With the circuit of FIG. 1, however, and given consideration to all process corners and temperature ranges (for example, −40 to +125 degrees Centigrade), it is not possible to generate at trip point (reference 132) at greater than a ramping-up Vdd voltage level of about 0.64 V (which is Vtp plus 150 mV when Vdd is ramped-up to 1.3 V due to transistor voltage linearity). If the companion circuit, such as a low current oscillator, requires that the POR signal transition from high to low at a greater voltage level than 0.64 V, say about Vdd=1.2 V for the worst case condition to kick start the oscillator, then the circuit of FIG. 1 cannot be used.
A need accordingly exists for a POR circuit that solves the foregoing problem. A need also exists for a POR circuit that is suitable for operation with technologies using a ramped-up Vdd voltage of about 1.3 V, and further is capable of having a POR signal trip point from high to low be settable (perhaps selectable) and in particular be capable of being set to about 1.2 V.


A lighted plier hand tool apparatus including a pivoting hub device containing a first opening, an opposed second opening, and a passage therethrough extending from the first opening to the second opening. The plier hand tool apparatus further includes a first plier member and a second plier member. Each plier member includes a respective handle portion, a jaw portion, and an intermediate pivot portion therebetween. Each respective pivot portion defines a respective bore section formed for aligned receipt of the hub device therein. Such receipt interconnects the first and second plier members together to enable relative pivotally movement of the respective jaw portions at a work area between an opened condition and a closed condition. The hand tool apparatus further includes an illumination device having an illumination portion outputting a light beam from one end of an elongated body section. The body section of the assembly is formed and dimensioned for receipt in the passage of the hub device such that the illumination portion terminates at the work area for illumination thereof.

Poorly lit work environments will always pose additional risks to any personnel operating hand tools. This problem is particularly troublesome for industrial application where equipment that is located next to other components that can easily be damaged or that present a hazard to the technician, such as exposed high-voltage sources or heavy equipment.
While external lighting is an obvious solution, it may not always be practical due to space and power source limitations where such tools are to be applied. For example, the external light may require it to be connected to an outlet by an extension cord and that the technician hangs in a position to illuminate the component. Such outlets, of course, are not always located near the equipment that is to be serviced. Furthermore, the light may relatively large so that technicians may not normally carry them when inspecting and adjusting equipment.
Several hand tools have been developed that contain their own light source, instead of depending upon the need for external lighting. The advantage of this approach is that the beam of light contained in the tool generally can be directed at the work area where the technician is performing the work without any additional manipulation and maneuvering of the light source.
One significant problem with most of these lighted hand tool approaches is that either the light generated by the tool is of lower intensity and insufficient, or the addition of the light impair the use of the tool. Generally, a lower intensity light results from the necessity of reducing the power consumption in an effort to reduce the size of the power source, and hence, reduce the tool bulkiness and footprint. In other designs, a lower light intensity is caused by the diffusion of the light when it is required to pass through obstructive structure of the tool itself. Accordingly, there is a need for improved lighted hand tool, such as a lighted plier hand tool, that has a high intensity light source with a low power consumption that will provide illumination directly to the desired work area or object to be grasped by the plier hand tool.


An in-plane switching mode liquid crystal display device includes a first substrate; a gate line disposed in a first direction on the first substrate; a data line disposed in a second direction on the first substrate, the data line crossing the gate line to define a pixel region; pixel electrodes and common electrodes disposed in the first direction in the pixel region, the pixel electrodes and the common electrodes generating an in-plane electric field within the pixel region; first and second common lines disposed parallel to the data line at right and left sides of the pixel region; a first common electrode connection line connecting at least two common electrodes and forming a first common electrode overlapping region by overlapping the first common line; and a second common electrode connection line connecting at least two other common electrodes and forming a second common electrode overlapping region by overlapping the second common line, wherein the first common electrode overlapping region and the second common electrode overlapping region have substantially the same area.

1. Field of the Invention
The present invention relates to a liquid crystal display device and more particularly, to an in-plane switching mode liquid crystal display device and a method for fabricating the same.
2. Description of the Related Art
A liquid crystal display (LCD) device is commonly used as a flat panel display device because it provides high quality images and consumes low power. The LCD device is formed by attaching face to face a thin film transistor array substrate and a color filter substrate with a uniform gap between the two substrates, and forming a liquid crystal layer between the two substrates. Pixels are arranged on the thin film transistor array substrate in a matrix. A thin film transistor, a pixel electrode and a capacitor are formed in each pixel region. A common electrode, an RGB color filter, and a black matrix are formed on the color filter substrate. An electric field is generated between the common electrode and the pixel electrode and applied to the liquid crystal layer. The RGB color filter implements colors.
Alignment films are formed at facing surfaces of the thin film transistor array substrate and the color filter substrate. The alignment films are rubbed to arrange the liquid crystal layer in a specific direction. Liquid crystals rotate due to a dielectric anisotropy when the electric field is applied to the liquid crystal layer between the pixel electrode formed in each pixel region and the common electrode formed on the entire surface of the color filter substrate. The rotation of the liquid crystals causes individual pixel regions to transmit or block light for displaying letters or images.
However, such a twisted nematic mode LCD device has a narrow viewing angle. Therefore, research is actively ongoing in developing an in-plane switching (IPS) mode LCD device to solve the viewing angle problem. In an IPS mode LCD device, liquid crystal molecules are aligned nearly parallel to a substrate.
FIG. 1A is a plane view of a pixel region of the related art IPS-LCD device. FIG. 1B is a cross-sectional view taken along line I-I′ of FIG. 1A. Referring to FIGS. 1A and 1B, a gate line 1 and a data line 3 are arranged horizontally and vertically on a transparent first substrate 10 to define a pixel region. Although N gate lines 1 and M data lines 3 cross each other to define N×M pixels in an actual LCD device, only one pixel is illustrated in the drawing to simplify the description.
A thin film transistor 9, including a gate electrode 1a, a semiconductor layer 5 and source/drain electrodes 2a and 2b, is disposed at the crossing of the gate line 1 and the data line 3, and the gate electrode 1a and the source/drain electrodes 2a and 2b are respectively electrically connected to the gate line 1 and the data line 3. A common line 4 is arranged parallel to the gate line 1 within the pixel region, and at least one pair of electrodes switching liquid crystal molecules, namely, a common electrode 6 and a pixel electrode 7 are arranged parallel to the data line. The common electrode 6 is formed simultaneously with the gate line 1 and electrically connected to the common line 4. A gate insulation layer 8 is formed over an entire substrate 10 including the common electrode 6. The pixel electrode 7 is formed on the insulation layer 8 simultaneously with the source/drain electrodes 2a/2b and electrically connected to the drain electrode 2b of the thin film transistor 9. A passivation film 11 is formed over the entire substrate including the source/drain electrodes 2a and 2b. A pixel electrode line 14 overlapping the common line 4 and electrically connected to the pixel electrode 7 forms a storage capacitance (Cst) with the insulation film 8 interposed between the common line 4 and the pixel electrode line 14.
A black matrix 21 for preventing light leakage to the thin film transistor 9, the gate line 1 and the data line 3, and a color filter 23 are formed on a second substrate 20, and an overcoat film (not shown) is applied on the color filter 23 to flatten the color filter 23. Alignment films 12a and 12b are applied to facing surfaces of the first substrate 10 and the second substrate 20. The alignment films 12a and 12b determine an initial alignment direction of the liquid crystals. A liquid crystal layer 13 is formed between the first substrate 10 and the second substrate 20 in order to control transmittance of light by a voltage applied to the common electrode 6 and the pixel electrode 7.
The Related Art IPS-LCD device having the above-described structure improves viewing angle because the common electrode 6 and the pixel electrode 7 are placed on the same substrate and generate an in-plane electric field. However, the IPS-LCD device has the following problems. Because the common electrode 6 and the pixel electrode 7, which is formed of an opaque metal, are placed within the pixel region where an image is displayed, and brightness degraded.
Furthermore, an in-plane electric field is not normally formed within the pixel region because of signal interference between the data line 3 and the pixel electrode 7. The aperture is reduced when the width of the common electrode 6 adjacent to the data line 3 is increased to prevent signal interference between the data line 3 and the pixel electrode 7. Specifically, a data signal supplied to the data line 3 may affect the pixel electrode 7 adjacent to the data line 3, which causes a distortion of the electric field. Particularly, if the pixel electrode 7 is formed parallel to the data line 3 as shown in FIG. 1A, the data line 3 causes strong signal interference with the pixel electrode 7. To shield the signal interference from the data line 3, a width of the outermost common electrode 6 adjacent to the data line 3 is increased. Accordingly, the aperture ratio is reduced.

In-plane switching mode liquid crystal display device having first and second common electrode connection lines and first and second pixel electrode connection lines being formed on the same layer


A method and system for diagnosing any combination of persistent and intermittent faults. The behavior of a system under test is obtained by measuring or probing the system at a particular location(s). The predicted behavior of a modeled system corresponding to the system under test is investigated by drawing inferences based on at least conditional probabilities, prior observations and component models. The predictions are compared to their corresponding points in the system under test. A determination is made if a conflict exists between the measured behavior and the predicted behavior, and the conditional probabilities are adjusted to more and more accurately reflect the action fault(s) in the system under test. The conflicts or deviations between the obtained predicted behavior and the actual behavior are used to isolate the components of the system causing the faults.

Model-based diagnosis (MBD) involves model-based testing in which test cases are derived in whole or in part from a model that describes some, usually functional, aspects of the system under test. The model is usually an abstract, partial representation of the system under test-desired behavior. The test cases derived from this model are functional tests on the same level of abstraction as the model.
Model-based diagnosis is diagnostic and system-directed. Particularly, it starts with the observed misbehavior and works back toward the underlying components that may be broken.
Model-based diagnosis may be employed in a variety of arenas, including detecting faulty system behavior, identifying faulty components, repairing of the system, and reconfiguring of the system. Other areas to which MBD may be applied, include debugging cognitive models, designing experiments to build improved models of gene pathways, troubleshooting power grids, troubleshooting manufacturing lines, identifying faults in spacecraft, airplanes, and debugging programs, among other uses.
However, an issue related to the diagnosis of systems using MBD as well as other testing approaches, such as "ad hoc" hand-coded rules, machine learning of patterns, D-algorithm searching, and analytical redundancy relationships, among others, is the inability to accurately diagnose intermittent faults.
Experience with diagnosis of automotive systems and reprographic machines shows that intermittent faults are among the most challenging kinds of faults to isolate. Such systems raise many modeling complexities. The approach to isolating these intermittent faults is presented in the context of logic systems. However, it is to be appreciated the present concepts may be employed in many other environments.
Presently, the main approach used to attempt to find intermittent faults is to stress the system under test, in an attempt to convert the intermittent faults to persistent failures, and then diagnose those failures. However, these approaches tend to lead to increased system failures of the overall system.
Therefore, it is desirable to employ a system and method which finds or isolates intermittent faults but does not stress the system under test, and thereby avoid increased system failures.


The invention described herein is a method, system, and computer program product for the design and fabrication of the surfaces of an object. The process begins by using a CAD process to design surfaces of the object. In particular, the surfaces are modeled using developable surfaces only. The intersections of the developable surfaces are then calculated. Any excess surface area of the developable surfaces is then trimmed. The boundaries of each developable surface are abstracted to produce a two-dimensional planar model of each developable surface. From each planar model, a full-sized two-dimensional shape can then be fabricated in proportion to the planar model. Each fabricated shape can then be bent in accordance with the corresponding developable surface of the CAD model. Finally, the edges of the fabricated shapes are attached as determined by the calculated intersections of the developable surfaces of the CAD model.

1. Field of the Invention
The invention described herein relates to computer-aided design (CAD) and to fabrication.
2. Related Art
Computer aided design (CAD) is now widely used in a variety of industries. For example, CAD technology is used by the electronics industry to design chips, by the automotive industry to design mechanical components, and by architects to render building designs. The popularity of CAD is due in part to its ability to facilitate rapid and economical design. Moreover, in many CAD applications, the resulting design can be easily saved and converted into a final product. The fabrication of circuit boards is an example of this.
In other fields, however, the conversion of a computer-aided design to a final product is less practical. In particular, the fabrication of large three-dimensional solids that have been designed with a CAD process can be difficult. Existing fabrication methods, such as stereo lithography and laser sintering, are capable of precisely constructing three-dimensional solids directly from a CAD process, but the capabilities of these fabrication methods are limited. Such fabrication processes generally build a solid using an iterative layering process. Such processes can operate, for example, by using heat to solidify successive layers of resin at points determined by the CAD process. This results in the desired three-dimensional solid. Such processes may alternatively build an object by successively layering particulate matter, such as metal shavings, and bonding the particles at locations determined by the CAD process. These processes are limited, however, in the size of the solid that can be built. While they can generally produce an arbitrary three-dimensional shape, they are not typically able to build an object larger than a two foot cube. Moreover, these methods are slow. Construction of a two foot cube can take 24 hours. These processes are also expensive, and the equipment tends to be difficult to maintain. In general, these processes are more useful for construction of models, i.e., prototyping, rather than for production of full-scale objects.
There is a need, therefore, for a method by which large three-dimensional objects can be designed using a CAD process, such that the resulting design lends itself to ready fabrication. Fabrication based on such a design must be relatively fast and inexpensive.
The invention described herein is a method, system, and computer program product for the design and fabrication of an object comprised of one or more surfaces. A process begins by using a CAD process to design surfaces of the object. In particular, the surfaces are modeled using developable surfaces only. The intersections of the developable surfaces are then calculated. Any excess surface area of the developable surfaces is trimmed. The boundaries of each developable surface are abstracted to produce a two-dimensional planar model of each developable surface. From each planar model, a full-sized two-dimensional shape can then be fabricated in proportion to the planar model. Each fabricated shape can then be bent in accordance with the corresponding developable surface of the CAD model. Finally, the edges of the fabricated shapes are attached as determined by the calculated intersections of the developable surfaces.
Features and Advantages
The invention has the feature of allowing the computer-aided design of arbitrarily large surfaces and shapes. The invention has the additional feature of using developable surfaces to model the surfaces of an object.
The invention has the advantage of modeling the surfaces of an object so that the ultimate fabrication of the surfaces can be done precisely. The invention has the further advantage of providing a means for ready attachment of the edges of fabricated shapes.

Modeling and fabrication of objects represented as developable surfaces


A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer; depositing a second hard mask layer on the first hard mask layer; depositing a third hard mask layer on the second hard mask layer and completing formation of the dual damascene structure by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material. In one particular embodiment the second hard mask layer is an amorphous carbon layer and the third hard mask layer is a silicon-containing material.

The present invention relates to the fabrication of integrated circuits. Some specific, embodiments of the invention pertain to a method for forming a dual damascene structure in an integrated circuit in which the etched dielectric layer(s) include one or more porous low dielectric constant films.
As semiconductor device sizes have become smaller and integration density increases, many issues have become of increasing concern to semiconductor manufacturers. One such issue is that of interlevel "crosstalk." Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer, and arises when two or more layers of metal with intervening insulating or dielectric layers are formed on a substrate. Crosstalk can be reduced by moving the metal layers further apart, minimizing the areas of overlapping metal between metal layers, reducing the dielectric constant of the material between metal layers and combinations of these and other methods. Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer. As device geometries shrink, the conductive lines become closer together and it becomes more important to better isolate them from each other.
Another such issue is the "RC time constant" of a particular trace. Each conductive trace has a resistance, R, that is a product of its cross section and bulk resistivity, among other factors, and a capacitance, C, that is a product of the surface area of the trace and the dielectric constant of the material or the space surrounding the trace, among other factors. If a voltage is applied to one end of the conductive trace, charge does not immediately build up on the trace because of the RC time constant. Similarly, if a voltage is removed from a trace, the trace does not immediately drain to zero. Thus high RC time constants can slow down the operation of a circuit. Unfortunately, shrinking circuit geometries produce narrower traces, which results in higher resistivity. Therefore it is important to reduce the capacitance of the trace, such as by reducing the dielectric constant of the surrounding material between traces, to maintain or reduce the RC time constant.
Hence, in order to further reduce the size of devices on integrated circuits, it has become necessary to use insulators that have a lower dielectric constant than the insulators of previous generations of integrated circuits. To this end, semiconductor manufacturers, materials suppliers and research organizations among others have been researching and developing materials for use as premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers in integrated circuits that have a dielectric constant (k) below that of silicon dioxide (generally between about 3.9–4.2) and below that of fluorine-doped silicate glass (FSG, generally between about 3.4–3.7). These efforts have resulted in the development of a variety of low dielectric constant films (low k films). As used herein, low k films are those having a dielectric constant less than about 3.0 including films having a dielectric constant below 2.0.
Some approaches to developing such low k films include introducing porosity into known dielectric materials to reduce the material's dielectric constant. Dielectric films when made porous, tend to have lower dielectric constants (the dielectric constant of air is normally 1.0). One particular class of porous low k films includes mesoporous silica materials. One known method of forming such mesoporous silica films is referred to as the sol gel process, in which high porosity films are produced by hydrolysis and polycondensation of a metal oxide.
The sol gel process is a versatile solution process for making ceramic material. In general, the sol gel process involves the transition of a system from a liquid "sol" (mostly colloidal) into a solid "gel" phase. The starting materials used in the preparation of the "sol" are usually inorganic metal salts or metal organic compounds such as metal alkoxides. The precursor solutions are typically deposited on a substrate by spin on methods. In a typical sol gel process, the precursor is subjected to a series of hydrolysis and polymerization reactions to form a colloidal suspension, or a "sol." Further processing of the "sol" enables one to make ceramic materials in different forms. One method of forming such mesoporous low k films is described in U.S. application Ser. No. 09/823,932, filed on Mar. 29, 2001 in the name of Robert P. Mandel et al. and assigned to Applied Materials, Inc., the assignee of the present case. The Ser. No. 09/823,932 application is hereby incorporated by reference in its entirety.
Concurrent with the move to intermetal dielectric layers having a dielectric constant lower than silicon oxide, many semiconductor manufacturers are using copper rather than aluminum in the formation of their multilevel interconnect structures. Because copper is difficult to etch in a precise pattern, however, the traditional deposition/selective etch process used for forming such interconnects has become disfavored. Accordingly, a process referred to as a dual damascene process, is used by most semiconductor manufacturers to form copper interconnects. In a dual damascene process, a blanket intermetal dielectric layer is deposited and then subsequently patterned and etched to define both the interlayer vias and the interconnect lines. Copper or another conductive material is then inlaid into the defined pattern and any excess conductive material is removed from the top of the structure in a planarization process, such as a chemical mechanical polishing (CMP) process.
The etching of the dielectric layer in such a dual damascene process typically includes two separate lithography steps. One step defines the trenches and another the vias. Photoresist and organic bottom antireflective coating (BARC) films have been found to penetrate the pores of porous low k films so dual damascene lithography techniques for porous low k films typically include the use of a hard mask between the ELK material and the photoresist. One such scheme that has been proposed includes the use of two separate hard masks as shown in FIGS. 1a through 1h.
FIGS. 1a through 1h illustrate one method used in the fabrication of a trench-first dual damascene scheme using a dielectric layer 10 formed over a substrate 2. Substrate 2 may include an already formed conductive line 4, e.g., a copper line, a surrounding dielectric material 6 and a barrier layer separating the two. Dielectric layer 10 may be a single layer or a multilayer dielectric stack. Dielectric layer 10 shown in FIG. 1aincludes multiple layers: a barrier layer 12, a via dielectric layer 14 and a porous low k layer 16. Formed over dielectric layer 10 are a first hard mask layer 20, a second hard mask layer 22, a bottom antireflective coating 24 and a photoresist layer 30.
As shown in FIG. 1a photoresist layer 30 is patterned and etched using a metal wiring pattern to form an opening 32. The metal wiring pattern is then transferred into hard mask layer 22 using an appropriate etching process (FIG. 1b). Any remaining photoresist layer 30 is then stripped along with antireflective coating 24 (FIG. 1c). Next, a new bottom antireflective coating 40 and photoresist layer 42 is formed over the substrate such that antireflective coating 40 fills in etched opening 32 (FIG. 1d).
As shown in FIG. 1d, photoresist layer 42 is then patterned and etched according to a via pattern to form an opening 34. The via pattern is then transferred into dielectric stack 10 using photoresist layer 42 as the pattern (FIG. 1e) and afterwards, photoresist layer 42 and antireflective layer 40 are stripped leaving a partially formed via 50 and a larger opening 32 (FIG. 1f). Next, the desired trench 52 and via 50 are etched into low k dielectric layer 10 (FIG. 1g) and barrier layer 12 is etched through to complete the etched via formation (FIG. 1h). Once the formation of via hole 50 and trench 52 are completed, the structure can be filled with copper or another conductive material. The filled structure is then subjected to a planarization step, such as a CMP step, to complete the formation of the interconnect structure. In the completed structure the top of the just-formed conductive line is essentially even with the top of dielectric layer 10.
While the above described process can be used to successfully form dual damascene structures for some integrated circuits, it not without its limitations. For example, hard mask layer 22 described in the above process is typically required to have a thickness in the range of 1500 Å to 5000 Å in order to remain in place during the etching steps shown in FIGS. 1f, 1g and 1h. Such a relatively thick layer is required for the scheme because etch chemistry selectivity issues and physical sputtering. If the layer is too thin, it will be etched entirely away during the etching steps shown in FIGS. 1f–1h, which in turn may cause the complete loss of hard mask layer 20 during the subsequent CMP process. The loss of hard mask layer 20 during CMP may in turn cause the CMP slurry to intrude into the porous low k dielectric material causing material and defect issues. Similarly, hard mask layer 22 is subject to sputtering effects during the etching processes shown in FIGS. 1f–1h. If the layer is too thin, such sputtering may result in the corner chopping and critical dimension loss in the underlying etched features (via 50 and trench 52). This in turn may result in shorting of conductive lines and/or other problems.
The requirement of such a relatively thick hard mask layer 22 however leads to lithography issues. For example, via opening 34 is patterned inside, or at least partially inside, previously etched and subsequently filled opening 32. The topography created by this hard mask trench etch/fill process may present depth of focus issues during the subsequent lithography process of photoresist layer 42. This is especially true as such dual damascene schemes for low k films are expected to be used in processes that include minimum feature sizes of 0.15 microns and smaller thereby using radiation wavelengths of 193 nm or less for the lithography steps.
FIG. 2, is a simplified cross-sectional drawing of a substrate showing the possible topography of antireflective layer 40 and photoresist layer 42 just prior to the etching of opening 34 shown in FIG. 1d. Photoresist layer 42 includes areas 60 that are to be developed by exposing the corresponding portions of the photoresist layer to appropriate radiation. As shown in FIG. 2, antireflective coating 40 is generally not planar having a recessed portion 62 in an area corresponding to particularly large opening 32 of hard mask layer 22 and raised portions 64 corresponding to areas of the substrate having small trenches or no trenches at all. The uneven topography of layer 40 results in a similarly uneven topography for photoresist layer 42 and a height difference 70 between the top surface of layer 42 in areas 64 as compared to the top of layer 42 in area 62.
The size of height difference 70 is in part due to the thickness of hard mask layer 22. A thinner hard mask layer 22 enables the formation of more planar layers 40 and 42. When height difference 70 is greater than or close to the depth of focus (DOF) of the radiation used to pattern layer 42, portions of layer 42 may not be properly exposed during the patterning process. This, in turn, may result in underdeveloped photoresist and incorrectly dimensioned vias and/or vias that are not opened uniformly all across the wafer.
Accordingly, it can be seen that improvements and/or alternative schemes for forming dual damascene structures using porous low dielectric constant films are desirable.

Method of forming a dual damascene structure utilizing a three layer hard mask structure


A VLC mode judgment section performs judgment on whether or not a received group (Last, Run, Level) exists in a VLC table and then performs judgment on which one of a first escape mode, a second escape more and a third escape mode is suitable. According to a judgment result of the VLC mode judgment section, an FLC processing section or a coding mode selection section performs variable-length coding using selected one of the received group (Last, Run, Level), a group generated in the first escape mode, and a group generated by the second escape group or fixed-length coding using a third escape mode.

1. Field of the Invention
The present invention relates to a variable-length coding method, a variable-length coding device and an imaging system, which are realized in the MPEG mode, for coding picture data or the like.
2. Description of the Prior Art
Technologies for compressing picture data at a high compression rate have been advanced and used for digital cameras and digital video cameras.
For example, as a method for compressing moving picture data, the MPEG (moving picture experts groups) method standardized by ISO has been known in general. The MPEG method is characterized in that coding using an intraframe correlation (which will be hereafter referred to as "intracoding") or coding using an interframe correlation (which will be hereafter referred to as "interceding") is performed for each block (which will be hereafter referred to as "macroblock") including a plurality of pixels and constituting a frame.
In the above-described types of coding, specifically, DCT (discrete cosine transform) which is a quadrature transform is performed to data in a macroblock and then quantization and variable-length coding are performed thereto, thereby compressing picture data.
In variable-length coding (VLC processing) using VLC (variable-length code), assuming that Run indicating the number of zero coefficients before a non-zero coefficient, Level indicating a non-zero coefficient value, and Last indicating whether or not the non-zero coefficient is the last coefficient form a group (coefficient series), a DCT coefficient obtained as a result of DCT is coded by uniquely allocating a code to the group (Last, Run, Level). In MPEG compression, a variable-length coding is performed using a VLC table defined for the purpose of allocation of a unique code.
When variable-length coding is performed using a VLC table but a VLC corresponding to the group (Last, Run, Level) is not defined in the VLC table, coding is performed with application of the following three escape modes.
In a first escape mode, NewLevel is obtained as a new Level for the group (Last, Run, Level) by subtracting LMAX which is a maximum value of Level corresponding to Last and Run in a VLC table from an absolute value of Level and then putting the sign of Level to a result of the subtraction. Then, VLC processing is performed again, this time, to a group (Last, Run, NewLevel) using the VLC table.
The following is an equation for obtaining NewLevel.NewLevel=sign(Level)×(|Level|−LMAX)where sign (Level) is the sign of Level and |Level| is an absolute value of Level.
In a second escape mode, NewRun is obtained as a new Run for the group (Last, Run, Level) by subtracting a value obtained by adding 1 to RMAX which is a maximum value of Run corresponding to Last and Level in the VLC table from a value of Run. Then, VLC processing is performed again, this time, to a group (Last, NewRun, Level) using the VLC table.
The following is an equation for obtaining NewRun.NewRun=Run−(RMAX+1)
In a third escape mode, the group (Last, Run, Level) is transformed to FLC (fixed length code).
FIG. 31 is a flow chart schematically showing the order in which process steps are performed and a flow of information (signal) in each process step.
First, VLC processing is performed to a group (Last, Run, Level) and, if the group is successfully coded, a code (effective code) is output (Step S1).
Whether or not the output code is an effective code is judged (Step S2) and, if it is judged that the output code is an effective code, the code is output and coding is completed (Step S3).
If coding is not completed in Step S1, whether or not the first escape mode has been already performed using LMAX is judged (Step S4).
If the first escape mode has not been performed, NewLevel is obtained by calculation using the equation for obtaining NewLevel to generate a group (Last, Run, NewLevel) (Step S5) and then the VLC processing of Step S1 is performed again. Whether or not the output code is an effective code is judged (Step S2) and, if it is judged that the output code is an effective code, the code is output and coding is completed (Step S3).
If coding is not completed in Step S4, whether or not the second escape mode has been already performed using RMAX is judged (Step S6).
If the second escape mode has not been performed, NewRun is obtained by calculation using the equation for obtaining NewRun to generate a group (Last, NewRun, Level) (Step S7) and then the VLC processing of Step S1 is performed again. Whether or not the output code is an effective code is judged (Step S2) and, if it is judged that the output code is an effective code, the code is output and coding is completed (Step S3).
If coding is not completed in Step S6, transform (FLC processing) is performed to the group (Last, Run, Level) to obtain FLC (fixed-length code) (Step S8). Then, a result of the FLC processing is output and coding is completed (Step S3).
As described above, in VLC processing in the known MPEG compression, with a cycle in which an output result is obtained using a VLC table assumed to be 1 cycle, three cycles are required to obtain FLC. That is, in the case of data needing FLC processing to be performed for many times, many processing cycles are required, so that the problem of reduction in processing speed arises.
As a method for realizing coding with fewer cycles even for data needing FCL processing to be performed for many times, a processing method with procedures shown in FIG. 32 has been proposed (see, for example, Japanese Patent Publication No. 3573735).
In this method, separate processing steps for FLC processing are parallelly performed. That is, VCL processing for a received group (Last, Run, Level), VLC processing for a group (Last, Run, NewLevel) newly generated by calculation using the equation for obtaining NewLevel in the first escape mode, VLC processing for a group (Last, NewRun, Level) newly generated by calculation using the equation for obtaining NewRun in the second escape mode, and FLC processing for the group (Last, Run, Level) in the third escape mode are performed in parallel.
In a system which realizes processing according to the above-described method, three separate VLC processing are parallelly performed, and therefore three VLC tables in total are provided in the system.
For outputs by the above-described three VLC processing as well as outputs by some other VCL processing, a single output is selected according to predetermined priorities.
According to this method, if a processing cycle of a VLC table is assumed to be 1 cycle, coding can be completed in 1 cycle.
However, in the above-described method in which three VLC processing are performed in parallel, a processing cycle of coding is reduced but three parallel VLC tables have to be provided. Therefore, a circuit size in a coding system for realizing this method is unexpectedly increased.

Variable-length coding method, variable-length coding device and imaging system

Matsushita Electric Industrial Co., Ltd.


A method and apparatus is disclosed for continuously monitoring the resistance of a grounding conductor to neutral conductor circuit of a power distribution system. The apparatus compares a parameter of a damped sinusoidal waveform from a shock excited resonant circuit coupled to the grounding conductor and neutral conductor at a branch circuit outlet of the power distribution system with a predetermined parameter from the same resonant circuit discharging into an external circuit having a predetermined resistance. The apparatus indicates an undesired grounding conductor resistance.

Improper grounding of power distribution systems can have adverse effects upon the performance and maintenance of complex telecommunications systems, computer networking systems, and other electronic equipment. Such power distribution systems commonly consist of 120 volt, 60 hertz alternating current supplies in the U.S. and other western hemisphere countries, and 220 volt, 50 and 60 hertz supplies in Europe.
The power distribution systems which provide power to telephone switchboards, personal computers, facsimile machines, copy machines and other equipment are typically single phase, three conductor systems. Two of the conductors, a "high potential" or "hot" conductor and a "neutral" conductor, are current carrying. The third conductor, a "grounding" conductor, is typically bonded to the neutral conductor at the main service entrance of a building or at a major power distribution panel. At this point, the neutral and grounding conductors are also bonded to an "earth ground", which is typically a copper rod driven into the earth. Therefore, substantially no voltage should exist between the neutral conductor and any other conductor which is connected to earth, such as water pipes, metallic building structures, ventilating ducts, etc. The hot conductor will have a voltage potential with respect to such objects equal to the rated supply voltage.
In the United States, the National Electrical Code and the standards of Underwriters Laboratories (U.L.), and their counterparts in virtually all other countries, require that the metallic enclosures of any electrical utilization equipment be firmly bonded to the grounding conductor of a power distribution system.
A variety of "power protection" devices have been developed to safeguard electronic equipment from damage or system malfunction resulting from problems with the power distribution system. Among these are standby power supplies to supply power in the event of a power outage or malfunction. Other devices protect against transient voltage surges caused by lightning and power switching phenomena, or filter out high frequency "noise". Voltage regulators keep supply voltage within safe operating range for the equipment in the event of voltage sags or swells (i.e. surges) in the power distribution system.
Another problem associated with the power distribution system occurs when the resistance of the grounding conductor becomes unreasonably high. This may result from deterioration of the grounding conductor. Such deterioration can result from a number of causes including physical damage to the electrical conduit from construction work or impact of material handling equipment, slow deterioration from rust or exposure to corrosive chemicals, or loose connections caused by vibration or constant bumping of floor outlets by cleaning equipment. These problem do not usually occur with the neutral conductor which is protected by an outer casing. Therefore, the monitoring of the resistance between the neutral and grounding conductor is usually a good indication of the condition of the grounding conductor.
It is well accepted in the telecommunications and computer networking environment that a low resistance grounding system is a practical necessity. The connection of data lines between computers or other equipment which are separated by a considerable distance requires that the separated units be powered from different branch circuits in the power distribution system. If the "local" grounding conductors are at different potentials with respect to earth, the potential difference can be combined with data signals between the equipment to cause data errors or even damage to sensitive electronic devices driving and receiving the data signals Therefore, good installation practice stresses the importance of having lo resistance grounding conductors from each equipment site to a common earth point in the power distribution system.
The resistance of the ground path for a particular power distribution system branch circuit can be verified by measuring the resistance between the neutral and grounding conductors at an outlet of the branch circuit. Typically, this measurement may require that the power be shut-off to that branch circuit because a low resistance ohmmeter can be disturbed by line noise or voltage between the neutral and grounding conductors.
Other prior art methods of testing the condition of the grounding conductor have employed an indicator circuit connected between the hot conductor and the grounding conductor. To comply with U.L. shock hazard leakage requirements, the impedance of such circuits is necessarily high. Therefore, a grounding conductor path that is also a fairly high resistance will still indicate a satisfactory grounding conductor. Most such indicator circuits will show a satisfactory ground with a grounding conductor's path resistance of tens of thousands of ohms. All such circuits will indicate a satisfactory ground with resistance as high as 1000 ohms.
U.S. Pat. No. 3,810,003 discloses a technique for determining resistance of the grounding conductor path by measurement made at a power distribution system branch circuit outlet. The measurement is accomplished by intermittently pulsing a fairly high current (about 10 amperes) through the grounding conductor (i.e. a deliberate ground-fault current). The current flows through the hot conductor and the grounding conductor. The voltage drop through the grounding conductor can then be measured at the outlet between the neutral and grounding conductors. Since no pulse current is flowing in the neutral conductor, it will be at the potential of the junction of the neutral and grounding conductor at a power distribution panel. At the outlet, the potential of the grounding conductor will be raised by the voltage drop through the grounding conductor caused by the current pulse. Thus, the resistance of the grounding conductor can be measured utilizing the relationship R=V/I. This technique can be used to test the grounding conductor resistance. However, while proposals have been made of utilizing this device to continuously monitor the resistance of a grounding conductor, neither it nor an ohmmeter can be used as a continuous monitoring device since neither can meet the U.L. leakage current safety requirement of 3.5 milliamperes. This leakage requirement is the maximum current which may flow between the grounding and neutral conductors in the event such conductors are accidentally reversed at an outlet.
Moreover, the 3.5 milliampere leakage current limit is too low to make that current useful for detecting a variation of several ohms in the current path because it would require resolving a voltage change of the order of 10 millivolts. This is impractical because there is always some voltage appearing between the neutral and grounding conductors from noise, transient surges or load-current drop in the resistance of the neutral conductor. For instance, a 1000 watt, 70% power factor typical computer load can result in peak current through the neutral conductor of over 30 amperes. This would cause a 3 volt drop in the neutral conductor with a resistance of only 0.1 ohm. Since this voltage is added to the small measuring current voltage drop in the grounding conductor, it would obscure the 10 millivolt or less change that must be detected. Thus, a monitoring device which measures the voltage drop through the grounding conductor and is confined to the branch circuit outlet to be monitored, cannot operate within the applicable safety standards.
U.S. Pat. No. 4,973,912 discloses a method and device for contactless measurement of resistance arranged in the secondary circuit of a transformer. The time constant for a decaying sinusoidal response is employed to determine a value of an unknown resistance. The device comprises an excitation circuit for exciting a tuned circuit containing an unknown resistance to be measured and a time constant waveform analyzer to determine the time constant of the resulting response to the excitation signal. The patent suggests that various methods may be employed to measure the time constant. However, a method of counting the peaks of the decaying sinusoidal response until the voltage reaches a certain value is specifically taught. The device is utilized to monitor the resistance of the firing cap of the automotive airbag system located in the steering wheel of the vehicle. There is no teaching or suggestion that this device is useful as a monitoring apparatus for the grounding to neutral circuit resistance of a power distribution system or how it could be associated with the hot, grounding and neutral conductors of such a system.
The unique method of the present invention can continuously and reliably monitor the resistance of a grounding conductor while coupled to a power distribution system circuit. Furthermore, this method may be embodied in an apparatus which complies with the applicable safety U.L. and other standards.

Apparatus and method for continuously monitoring grounding conductor resistance in power distribution systems


An aircraft luggage locker is disposed in a compartment under a seat cushion which pivots about a horizontal axis. The locker includes a rack to receive luggage has a back wall from which extends a bottom wall and an opening at the end opposite the back wall. The rack is movable between a lying down position in which the back is in a generally vertical plane, the bottom wall is in a generally horizontal plane, and the opening is facing a wall of the compartment, and an inclined position in which the bottom wall is inclined to the horizontal and the opening of the rack is in a raised position relative to the back. Movement of the rack between the lying down position and the inclined position is a combination of a movement in translation in a horizontal plane and rotation about a horizontal axis perpendicular to the direction of movement in translation of the rack.

1. Field of the Invention
The present invention relates to an aircraft luggage locker.
2. Description of the Prior Art
Aircraft passengers' carry-on luggage is usually placed in an overhead luggage locker above the seats. This conventional arrangement is also encountered in other forms of transportation, for example buses and trains.
Although widely used, in an aircraft this place for luggage has a number of disadvantages. Given the shape of an aircraft cabin, whose cross section is usually the shape of a circular arc, little room is left above the heads of seated passengers. On rising, passengers must therefore take care not to bump their head against the luggage lockers.
Aircraft cabins are usually relatively low in height and providing overhead luggage lockers closed by a hinged flap makes the space inside an aircraft cabin seem cramped.
There are strict safety requirements in an aircraft. Luggage must be stowed away and there must be no risk while in flight of it escaping from its stowage. Furthermore, there are standardized luggage dimensions that must be adhered to. It is therefore necessary to provide stowage able to accommodate a standard piece of luggage. The stowage must also be easily accessible. It is also necessary to provide space for equipment such as life vests.
An object of the present invention is to provide a new aircraft luggage locker that conforms to the constraints to be complied with in this aeronautical application and frees up the space above seated passengers.


An apparatus and method for extracting energy is provided. In one aspect the method includes using chemical reactions to generate vibrationally excited molecules, such as high-quantum-number-vibrationally-excited gas molecules in a region. The vibration energy in the vibrationally excited molecules is converted into hot electrons when the excited molecules contact a conductor. A geometry is provided so that the excited molecules may travel, diffuse or wander into a conductor before loosing a useful fraction of the vibrational energy. Optionally, the generating and the converting process may be thermally separated, at least in part. The short lived hot electrons are converted into longer lived entities such as carriers and potentials in a semiconductor, where the energy is converted into a useful form.

The fuel cell is a clean and efficient electrochemical energy conversion method that typically converts chemical reaction energy of reactant gases directly and efficiently into electricity. The power per mass or per volume exhibited by a fuel cell system, however, is typically at least an order of magnitude lower than that of mechanical engines. Further, the volume needed for a fuel cell using liquid, storable fuels to generate the power of a given battery is typically significantly larger than that of the battery. This means that the present form of fuel cells cannot replace the battery regardless of the fuel cell efficiency, because there is no room for fuel.
In addition, the type of fuel cell with the highest known power per mass, the solid oxide fuel cell, operates at temperatures of 600 to 800 Celsius. Operation at this temperature presents materials problems as a result. In principle, this fuel cell would exhibit the power density required to operate in the volume of a battery it would displace. Thermal issues, however, have dominated and prevented realization of this goal.
The alternative to a high performance fuel cell is a rotating mechanical device. However, mechanical engines generating electricity must typically use coil and magnet devices to convert mechanical energy into electrical energy and are therefore relatively heavy, with power densities less than 2 watts per gram.
Therefore, there is a need to have a method and system for converting chemical energy directly and efficiently into electricity and to have methods that do not require high temperatures and materials and that do not require relatively heavy mechanical devices.
A chemical reaction typically creates highly vibrationally excited specie, which reaction may be stimulated by catalysts, injection of autocatalysts, or other means. A substantial fraction of the excitation energy may be transferred to an energetic electron in a metal when the excited specie comes in contact with the metal. See Huang, Yuhui; Charles T. Rettner, Daniel J. Auerbach, Alec M. Wodtke, Science, Vol. 290, 6 Oct. 2000, pp 111–113, "Vibrational Promotion of Electron Transfer."
According to results of experiments, vibrationally excited anions may absorb an electron and re-emit an electron into the lattice, carrying with it most of the excitation energy. By analogy, cations may emit an electron and reabsorb it, emitting a hole into the lattice, with the hole carrying the energy. The electron or hole is the hot carrier.
Recent experimental observations and theoretical developments in surface science confirmed that even relatively weakly electronegative gas molecules vibrating with an energy almost sufficient to break their chemical bonds (vibration quantum number in excess of order 15) can deposit a majority of the vibration energy into an electron of the metal surface during a single, brief contact (of order 0.1 picoseconds) with that surface. Research and observations associated with understanding this observation support the theory of prompt, multi-quantum energy transfer to a single electron from a vibrationally excited chemical specie.
Typically, more than half of the vibrational mode energy will be transferred directly into an electron of the metal surface with an energy greater than approximately 5 vibrational quanta. The result is that an electron in a metal surface may carry away a substantial, useful fraction of the vibrationally excited molecule energy as a hot electron, also referred to as a hot carrier.
In the metal, the hot electron may travel into a semiconductor. The hot electron becomes converted into an excitation or potential difference in the semiconductor where it may be converted into other useful forms such as an electrical potential driving a current in an external circuit, an inverted population of semiconductor excitations, or hot carriers transported to other locations for use.
The hot electron may be converted into a potential in a semiconductor. For example, U.S. Pat. No. 6,222,116 collects such hot electrons directly without mechanical means, and converts them directly into electricity when the vibrationally excited chemical product specie is formed on or within a few molecule dimensions of the reaction surface of its device. The device described in this patent generates useful electricity by causing the reactions rates to be sufficiently high to energize the semiconductor converter into maintaining a useful forward bias.
A removal of spent reaction products through desorption from a hot-electron collection surface may enhance this high reaction rate. De-energized molecules desorbing may leave behind a clean site for more reactions. Allowing these de-energized molecules to migrate away from the conducting surface may initiate further reaction with more oxidizers and fuels.
Accordingly, there is a need to have a method to produce vibrationally highly excited specie directly from chemical reactions and where the conversion of the electrical energy of the excited specie may take place at a location different from in the thermal sense and separated from the creation of the excited specie. Further, there is a further need to have reactions take place in a volume, not just a surface, to increase the rate of reaction compared to that on a surface.

Gas specie electron-jump chemical energy converter


A new pneumatic mattress for providing a lightweight inflatable resting surface. The inventive device includes a tubular perimeter member having a pair of end portions and a pair of side portions extending between the end portions of the tubular perimeter member. A number of tubular cross members are extended between the side portions of the tubular perimeter member. The lumens of the tubular cross members are in fluid communication with the lumen of the tubular perimeter member.

1. Field of the Invention
The present invention relates to air mattresses and more particularly pertains to a new pneumatic mattress for providing a lightweight inflatable resting surface.
2. Description of the Prior Art
The use of air mattresses is known in the prior art. More specifically, air mattresses heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art air mattresses include U.S. Pat. No. 5,303,435; U.S. Pat. No. 5,437,068; U.S. Pat. No. 4,541,135; U.S. Pat. No. 3,959,835; U.S. Pat. No. 3,408,107; and U.S. Pat. No. 2,788,533.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new pneumatic mattress. The inventive device includes a tubular perimeter member having a pair of end portions and a pair of side portions extending between the end portions of the tubular perimeter member. A number of tubular cross members are extended between the side portions of the tubular perimeter member. The lumens of the tubular cross members are in fluid communication with the lumen of the tubular perimeter member.
In these respects, the pneumatic mattress according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of providing a lightweight inflatable resting surface.