A system and a method is provided for fitting an aircraft cabin with modular sidewall panels, window reveals, and foam insulation blocks in an integrated manner. The system comprises a sidewall panel which may have one or more openings therethrough to receive a window reveal held by snap-fit fastenings. The bezel of the window reveal may be held by snap-fit fasteners for easy removal to allow removal and cleaning of the inner dust cover disassembly of the sidewall panel. Foam insulation blocks may be molded to fit in the cavity between the outer wall of the aircraft and the sidewall panels, held in place by compressive pressure between the frames of the airframe. The outer extent of the window reveal is tapered inwardly to guide the window reveal to mating contact with an outer window assembly in the aircraft fuselage without further adjustment of the sidewall panel.

The present invention generally relates to interior assemblies for aircraft, and more particularly to a system of sidewall panels, window assemblies, and insulation structures for installation upon a cabin wall within the interior of an aircraft.
Fabrication of a commercial aircraft typically consists of building an airframe (sometimes referred to as a primary structure or fuselage) consisting of a series of vertically oriented frames, or ribs, that encircle a cabin area for transporting personnel and cargo. The outboard side of the frames is covered with an outboard wall or skin and the inboard side of the frames in the cabin area may similarly be covered with sidewall trim panels. Along the outboard wall and between the frames, other aircraft components such as insulation, electrical conduits, ventilation ducting, control mechanisms, and the like may be installed, so that they may be enclosed between the outboard wall and the sidewall trim panels. Provisions must also be made for windows that must extend through the space between the inner and outboard walls.
The outboard wall is fixedly attached to each frame by standard means well known to the industry, such as by rivets, so that structure and rigidity is provided for the airframe, but the sidewall trim panels must be removable to allow access to these other aircraft components in the space between the sidewall and outboard wall. To facilitate removal and installation of the sidewall trim panels, elaborate systems of special fasteners, insulation supporting mechanisms, window reveals, and outer window assemblies have been devised to allow access to the aircraft components within the space. Therefore, current inner sidewall systems have been constructed piecemeal of many numerous components, and this has made installation and removal expensive in terms of number of sidewall parts and time required to remove and replace them.
In general, the inner sidewall system may include four basic components, namely, sidewall panels, window reveals, insulation between the inner sidewall and the outboard wall, and a fastening arrangement to allow each component to be installed, removed, and replaced while minimally affecting the other components. However, each component of an inner sidewall system has its own set of design issues.
The sidewall trim panels of commercial passenger aircraft are typically configured as a number of generally curved vertical panels that extend between the floor and storage bin of the aircraft in a side-to-side manner along either interior wall of the aircraft. Insulation is located behind the sidewall trim panels to reduce the amount of noise and vibration resulting from such external sources as the aircraft engines or turbulent air flow to the cabin. This noise and vibration is further reduced by mounting the sidewall trim panels against rubber shock absorbers which are also known as "shock mounts", and which are affixed to the frames of the aircraft. However, the sidewall trim panels must be held securely against the shock mounts so that any vibration of the airframe does not cause these panels to vibrate against the frame, shock mounts, and other interior components.
In addition to these habitability factors of reduced noise and vibration, it is desirable that the panels and insulation be installed and removed easily and rapidly. This is true not only during the initial construction of the aircraft, but also later on when maintenance is being performed. A number of air conditioning ducts and electrical wiring harnesses are typically routed behind the panels, and these ducts and wiring must be accessible by removing the sidewall trim panels.
In many conventional passenger aircraft, the sidewall trim panels have tabs that extend outwardly from the vertical edges of the panels. The panels are secured by horizontal bridge fasteners which are inserted over the tabs of adjacent sidewall trim panels and which are connected to the frames via the shock mounts by screw fasteners. A decorative vertical trim strip may be inserted between the edges of the adjacent panels and over the tabs to provide a pleasing appearance to the cabin. Behind the panels are located the shock mounts that are riveted to the frame. The shock mounts include threaded receptacles for securing the bridge fasteners to the aircraft. Insulation is installed behind the sidewall panels and secured to the vertical frames of the airframe.
Since the shock mounts are conventionally prelocated by being riveted to the aircraft frames prior to attaching the panels or insulation, it is sometimes difficult to properly secure the panels to the aircraft. This is because either the tabs of the adjacent panels do not properly align with each other to permit simultaneous engagement by the bridge fasteners, or because the tabs do not align with the position of the bridge fastener; the position of the bridge fastener being fixed by the location of the mounting holes in the prelocated shock mount. Furthermore, the lengthwise gap between the edges of the adjacent panels may be too small to accommodate a vertical trim strip, or the projecting screw fasteners may prevent the trim strip from being easily inserted in the gap.
Windows are generally constructed with an outer window assembly that becomes a part of the airframe and a window reveal that is attached through a hole in a sidewall trim panel and mated to the outer window assembly. This mating of the window reveal with the outer window assembly allows the window reveal to be removed without requiring removal of the outer window assembly. Current aircraft designs include the use of different hardware fastener mechanisms for attaching a window reveal to an aircraft sidewall panel. A typical window reveal may include a dust cover and other ancillary items such as shades. The most common of these assemblies require the combination of hardware fastener mechanisms, typically brackets, gaskets, and adhesives to affix the reveal to an aircraft's fixed outboard wall or skin. The brackets are affixed, via the adhesive, to the sidewall trim panel. The window reveal is then affixed to the brackets. In other installations, the window reveal is affixed to the sidewall trim panel using both mechanical affixing and adhesive affixing. The placement of both the fasteners and the window reveal must be precise within the sidewall trim panel so that the window reveal can be easily mated up to the opposing outer window assembly when the panel and window reveal are installed. This installation of the numerous brackets can be very labor intensive and time consuming; the sidewall must first be sanded and the adhesive must then be applied and allowed to cure for an extended period, before the window reveal can be affixed to the brackets. Further installation often requires specially designed tools or locating jigs. In addition, fuel economy can be negatively affected as the brackets and adhesives add weight to the aircraft, which in turn adds to the operating cost of the aircraft. In addition, the brackets can be very pliable and weak or brittle. They may therefore be subject to increased maintenance and replacement costs.
Additionally, because there is quite a variation in affixing mechanisms between various airplane models, standardization of the window assemblies across airplane models is difficult. Difficult access to whole or part of the window assembly makes standard window maintenance, like cleaning, expensive and time consuming. This is because maintenance must be done by removing the whole window assembly or accessing the whole sidewall.
The system of fasteners and brackets must be consistently and uniformly attached to the frames and the sidewall trim panels so that they correctly align. The brackets must be precisely placed within close tolerances on the frames and outboard surface of the sidewall trim panel in a very exacting manner, so that the sidewall trim panel may be accurately aligned. To achieve these close tolerances, one of two methods is generally used; either special locating jigs must be utilized or else slots must be incorporated into the sidewall trim panel so that it can be adjusted both up/down and fore/aft for precise fit. Such methods must be used since the brackets cannot be precisely placed when they are affixed by adhesives. This alignment operation is very tedious and exacting, and it leads to significant assembly costs because installers must take substantial time and care to precisely affix and adjust the brackets.
The installation and placement of insulation within the inter-sidewall space can also be difficult and time-consuming. It is well known in the art that an insulation layer is required between the sidewall panels and the outboard wall for purposes of retaining heat within the aircraft cabin, reducing vibration, and reducing external noise. Heretofore, bats of woven insulation or bags of limp fiberglass have been affixed to the exterior wall and fuselage of the aircraft cabin and held in place with brackets and clips inserted through the insulation material, so that they may be held in place until the sidewall trim panels can be installed over the insulation materials. However, one disadvantage of this process is that the initial installation of such insulation involves extensive technician time in order to create and seal numerous penetrations in the insulation, to place the numerous brackets required for holding the insulation, and to attach the insulation to the brackets. Furthermore, the entire length of the cabin must be fitted with the insulation layer before any of the sidewall trim panels are installed. Another disadvantage is that, because of the limp nature of traditional insulation, many penetrations must be made for supporting brackets, which in turn can cause numerous gaps in the insulation. These gaps greatly diminish the ability of such insulation to reduce noise since they create flanking paths though which noise may efficiently transmitted. Still another disadvantage is that the numerous brackets increase the weight of the aircraft and must themselves be affixed to the frames and exterior wall of the fuselage, which further increases technician time. When the insulation layer must be removed for maintenance at some point along the cabin wall, the technician must again spend a significant amount of time removing and reinstalling the insulation layer.
The prior art addresses numerous aspects of the different sidewall components in isolation. For example, U.S. Pat. No. 6,227,491 discloses a modular window unit that may be affixed to an interior sidewall trim panel of an aircraft. The window unit is centered in an opening of the sidewall trim panel by means of a centering lug located at the bottom center portion of the window unit and is assisted by tabs located on each bottom corner of the window unit. The tabs serve as an axis for holding the window unit to the bottom portion of the opening in the panel and rotating the top portion into the opening, to be detachably connected there by opposing snap fastenings on either side of the upper opening. The disclosure does not discuss how the sidewall trim panels are attached to the outer wall of the aircraft, nor does it describe the details of wiring and insulation that must be operationally inserted between the outer wall and inner sidewall trim panel.
U.S. Pat. No. 4,739,955 discloses an aircraft sidewall trim panel and insulation retainer for affixing the panel to the inboard frame of an aircraft. An aircraft panel is described that is secured at its lower side to a longitudinal dado panel running the length of the cabin and at its upper edge to an upper fixed portion of the cabin structure, such as a longitudinally extending row of storage bins. The panel is made of a resilient bendable material that is flexed against special shock absorbing retainers by the upper and lower edges of the panels. The retainers maintain the panel at a spaced distance from the aircraft frame members by use of an elastometric plug held by the retainer against the outer panel surface, in order to prevent vibration of the sidewall panel. The retainer also holds bats of insulation in place between the panel and the outer wall of the aircraft.
Thus, there exists a need to provide a system and method of configuring an aircraft interior sidewall that may be easily installed and removed for maintenance without requiring excessive time or equipment. There is also a need for a sidewall that allows aircraft components between the interior sidewall and the exterior sidewall to be accessed without having to remove an excessive number of adjacent aircraft components from their installed position. Finally there is a need for a system of sidewall panels, insulation, window assemblies and supporting brackets that minimizes gaps and effectively controls noise transmission.

Integrated window belt system for aircraft cabins


The invention is directed to a cross-linked gel-like polyvinyl-based composition of matter having unique elasticity. The composition is capable of being used as a kneading compound, as well as being moldable, stretchable, and bouncing, for use in play activities. The composition is based on a cohesive polyvinyl alcohol/polyvinyl pyrrolidone nonadhesive and substantially nondrying binder composition that is appropriate for child use. The invention is also directed to a method of making the instant polyvinyl-based composition of matter.

Through the years, play compositions of different types have been provided by practitioners in the toy arts to amuse children and adults and to aid in the development of manual skills and dexterity, as well as creativity. While the variety of such play material compositions is virtually endless, all generally involve the use of free-forming or malleable materials, such as oil base or water base gums and gel compounds which may be manipulated and shaped by the user. Certain materials have been provided which are moldable and tend to retain their shapes, such as modeling clay or the like. Others, however, have been provided which are looser and more free-flowing, such as novelty play materials and compositions. Still others are gel-like and provide interesting characteristics, such as shaking or quivering similar to gelatin dessert products.
Regardless of the type of play compositions used, it has remained imperative that such materials be safe for young children. Safety requirements have evolved through the years as safety concerns have grown. Generally, safety requirements mandate that play material compositions be nonirritating to the skin or eyes or the like, and be nontoxic if ingested. Additional requirements have been expected of these materials to avoid damage to clothing, upholstery fabric, or carpeting.
Play compositions having molding or modeling characteristics by which a child can represent people or objects are well known and generally comprise products of mineral origin, i.e., clay products, or vegetable origin, i.e., starch products. These particular materials are, in general, nonelastic and nonstretchable over significant lengths. Additionally, these modeling clays are messy and frequently have oils and other staining ingredients which are difficult to remove from carpets and fabrics. Elastomeric silicone-based play compositions are known and are essentially designed to be stretched, as well as to be rolled into a ball which has a high degree of elasticity or "bounce" under suddenly applied stress. However, silicone-based modeling compositions or puttys are generally known to have an unpleasant feel and have limited stretch capabilities, thereby limiting the material to a narrow field of play activity. Moreover, silicone puttys cannot be readily removed from fabric and carpets and, therefore, are not preferred materials for use by children.
Polyvinyl-based play compositions are known in the art as being child-user friendly. Specifically, polyvinyl alcohol has been found to be harmless if accidentally ingested, has no unpleasant odor or feel, and is readily removable from carpet or fabrics. However, most polyvinyl-based play or modeling compositions require the use of fillers to give physical integrity to the materials so as to enable the retention of detail or shape. Such polyvinyl-based play compositions are not elastic enough for ductility or stretchability and have minimal resiliency and bounce.
Recognizing the need to provide a more versatile play material, the present invention was configured. Specifically, there was significant interest in providing a play material that is kneadable, moldable, and elastic; that can be used for long periods of time without drying to the point that it becomes unusable; that would not be harmful if accidentally ingested; and that exhibits a bright, glistening and shiny colorful appearance with no unpleasant odor. It was further sought to have a play material that has bounce characteristics and is stretchable; which can be cleaned up and removed from carpets and fabrics with water; and which can be molded and retain detail until it is reformed. It was also important to produce a composition exhibiting all of the above properties while being moderate in cost.

Polyvinyl-based kneading and molding play composition


An analogue to digital converter (ADC) of the recirculating type is described. In one embodiment, the ADC is composed of three storage and residual determination units, which, in cooperation with an operational amplifier, and suitable comparator means, are operable to re-present residual signals for analogue to digital conversion. To enhance settling at the beginning of a cycle, the first storage and residual determination unit is used once, with remaining recirculation being conducted between the other two storage and residual determination units.

Pipeline ADCs are today commonly used for applications requiring 10 to 16 bits resolution at 1 MHz to 100 MHz sample rates, for example for digitising the outputs of CCD or CMOS linear or area image sensors or for digitising analogue video signals. A basic pipeline ADC includes several stages in cascade. Each stage uses a comparator to extract the most significant bit, and then the stage subtracts an analogue signal corresponding to the extracted bit, and amplifies the remaining residue, for use by the next stage. Commonly, more than one bit per stage is extracted, by using multiple comparators. Also, certain arrangements allow over-ranging of the input of each stage to accommodate comparator offsets so that, provided that each stage subtracts an accurate amount and gives an accurate analogue gain, the eventual digital output conversion remains accurate. These ADCs are commonly implemented in CMOS using switched-capacitor technology. However, other techniques, such as switched current, have also been used.
In practice, especially where the input signal amplitude can vary widely, as with an image sensor or communications link, a common implementation has the ADC preceded by an amplifier with controllable gain, termed a Programmable Gain Amplifier (PGA). This gain is often digitally controllable, but may be controlled by other means, such as voltage control or current control in some systems.
The PGA is controlled to amplify or attenuate the input signal so that it is of an amplitude that uses up a substantial proportion (as much as practicable) of the full-scale input range of the ADC. In this way the ADC thermal noise referred to the signal source is proportionately kept as low as possible relative to the signal source, and so its impact is minimised; likewise, the signal presented to the ADC is maximised. Thus, using a PGA, it is possible to make use of the full effective resolution of the ADC.
So as not to degrade the performance of the ADC, the PGA should be at least as linear as the ADC. The PGA should also be operable to settle linearly and quickly into the input impedance of the ADC, and to maintain this settling behaviour over a wide range of programmed gain values. Again, CMOS switched-capacitor technology is often used for this PGA, though alternatives such as op amp circuits using multiple-tapped resistor ladders, or bipolar multiplier cells or other voltage-controlled amplifiers, are also possible.
The PGA op amp can often present greater design challenges than the ADC op amps. It is required to have enough gain-bandwidth to settle accurately in typically half a sample period at maximum gain (say 20 dB or even greater), but has to remain stable when configured with higher feedback factors to give closed loop gain less than unity. It is also necessary for the input-referred noise of the PGA op amp to be low, even when amplifying a small input signal, and the capacitors or resistors around it will be of low impedance to minimise noise. Therefore the operating current will often be as much as all of the amplifiers in the ADC. While the op amps in the ADC also have to settle inside half a sample period, they can be optimised for a fixed closed-loop gain, and will only receive amplified input signals, so can be higher noise and drive higher-impedance circuitry, so power minimisation will be less critical. Also the PGA has to settle to the full resolution of the ADC, whereas the ADC op amps only have to settle to the resolution of the following stage.
For example, for a sample rate of 10 Ms/s, the sample period will be 100 ns. Thus, the PGA will need to settle to within the ADC resolution (say 14 bits) in 50 ns, which is half of this sample period. Assuming a single-pole settling model, this implies settling to 10 time constants in 50 ns, i.e. with a time constant of 5 ns, or a closed-loop bandwidth of 30 MHz. If the PGA is set to a gain of 10, this thus requires an op amp with open-loop gain-bandwidth of approximately 300 MHz, but stable at closed loop gain <<1.
In practice, allowing for clock under-lap, the available settling time may be less than 50 ns, and slewing, clock injection effects, or other second-order effects may require an even faster op amp.
This is inherently more difficult to achieve than in an ADC, which has a closed loop gain of, for example, 2, thus requiring a gain bandwidth of 60 MHz and only needing to be stable for constant gain A=2.
An n-bit pipeline ADC extracting one bit per stage requires n separate stages, each including an op amp, comparators, and a switched-capacitor array. This uses significant silicon area, each stage adding to die cost, but these ADCs are often required in high-volume consumer equipment, where manufacturing cost is very important. Also each stage consumes power, whereas many applications such as Digital Cameras are battery-powered portable equipment, so low power is important. Pipeline ADCs extracting more than one bit per stage have fewer stages, but each is more complex, consuming more area and more power per stage, so the net saving in terms of power and area is limited.
Thus, it would be desirable to obtain the performance of a pipeline ADC, with improved use of the active area of a solid state device. It would further be desirable to obtain the performance of a pipeline ADC with improved power consumption.
In the event that improved use of active area of a solid state device can be achieved, with improved power consumption, it could, in certain circumstances, be desirable to sacrifice this improvement in these performance criteria to the benefit of improved performance in terms of other performance criteria, such as noise, resolution and/or linearity.
For a given manufacturing technology, there comes a performance threshold at which it becomes increasingly difficult for a designer to get higher speed or better performance, without consuming a lot of extra power or requiring complicated and area-consuming topologies or requiring exceptional skill and the invention of novel circuit techniques. However, using common 0.35 μm CMOS, it is quite possible for a person reasonably skilled in the art to design an op amp capable of use in implementing an ADC operating up to 30 Ms/s at (say) 12 bits resolution, without hitting this performance threshold.
For applications at lower sample rates, say 3 Ms/s, one possibility is to use the same comfortably designed 30 Ms/s amplifier in successive 30 Ms/s clock cycles to implement the processing of successive stages, rather than dedicating an amplifier to each stage, just operating at 3 Ms/s. This results in a circuit architecture similar to cyclic (also termed recirculating, or algorithmic) ADCs. For a given sample rate, this requires faster settling, since all the processing for n stages needs to be squeezed into one sample clock cycle. The main problem is that the PGA now has to drive the input capacitors in a small fraction of the 3 Ms/s sample rate.
Examples of circuit designs comparable with specific embodiments from the state of the art will now be described, with discussion of their features, operation and certain disadvantages.
FIG. 1a shows a switched-capacitor PGA 10 driving a 1-bit per stage switched-capacitor pipeline ADC 20, extracting 1 bit per stage. One stage 22 of the pipeline ADC is illustrated in detail, and a second stage schematically, it being understood that further stages are to be added to the output to this stage until the desired resolution is reached.
The switched capacitor PGA 10 comprises an op amp 12 whose non-inverting input is tied to ground. One terminal of a variable input capacitance Ca1 is connected to an input on which an input signal Vin is received in use, via a switch Sw1. Another switch Sw3 lies between the same end of the input capacitance Ca1 and ground. A further switch Sw4 connects the other terminal of the input capacitance Ca1 to ground, and a further switch Sw2 connects that latter terminal to the inverting input of the op amp 12.
In use, switches Sw1 and Sw4 close on receipt of a clock signal φ1, as marked, and switches Sw2 and Sw3 close on receipt of another clock signal φ2.
The system is driven by these two-phase, non-overlapping clocks φ1, φ2, whose timing diagrams are illustrated in FIG. 1b. Because the clocks are non-overlapping, actions dependent on one of the clock signals being high are completed before actions dependent on the other of the clock signals being high, as the two clock signals are never simultaneously high. For convenience in the following description, the phase wherein φ1 is high is expressed as 'phase φ1' and the phase wherein φ2 is high is similarly expressed as 'phase φ2'.
A second feedback capacitance Ca2 is connected between the output of the op amp 12 and the inverting input and a switch Sw5, which also closes in phase φ1, is connected across this feedback capacitance Ca2.
The illustrated first stage 22 of a pipeline ADC 20 comprises a further op amp 24, whose non-inverting input is tied to ground. The stage also comprises first and second input capacitors C1a and C1b respectively, and a flash ADC 26 and a DAC 28 in the usual manner. The flash ADC compares its input against one or more reference levels, which may include ground. It may be regarded as a set of one or more comparators. The output of the flash ADC 26 is connected to the input of the DAC 28 and also comprises the output of the bit extracted from the ADC stage 22. The output of the DAC 28 feeds back, via a switch Sw9, which switches in phase φ1, to one end of the first input capacitor C1a. The same end of the first input capacitor is connected, via a switch Sw8, which switches in phase 42, to the input to the stage 22, which receives a signal Vsig output from the input PGA 10.
One terminal of the other input capacitor C1b is connected, via a phase φ2 switch Sw7, to the same input of the stage 22. That terminal is also connected, via a further phase φ1 switch Sw6, to the output of the op amp 24.
The other terminal of the first input capacitor C1a is connected, via a phase φ2 switch Sw13, to ground, and, via another phase φ1 switch Sw12, to the inverting input of the op amp 24. Similarly, the other terminal of the second input capacitor C1b is connected, via a phase φ2 switch Sw11, to ground, and, via another phase φ1 switch Sw10, to the inverting input of the op amp 24.
The inverting input is further connected to the output of the op amp 24, via a phase φ2 switch Sw14; the stage input Vsig feeds into the flash ADC 26 via another phase φ2 switch Sw15. In this example, this is a 1-bit flash ADC, functionally equivalent to a simple comparator, which senses whether the input voltage Vsig is greater or less than ground. Its digital output drives a DAC 28, in this case a simple 1-bit DAC, delivering a conversion result signal or voltage Vdac equal to +Vref or −Vref depending on the polarity of Vsig.
With reference to the timing diagram of FIG. 1b, switches Sw1, Sw4 and Sw5 of the PGA are driven closed by the first clock signal φ1. Switches Sw2 and Sw3 are driven closed by the second clock signal 42, as illustrated in FIG. 1a.
Operation of the input PGA will now be described. In phase φ1, input capacitance Ca1 is charged between Vin and ground by closing switches Sw1 and Sw4 as shown. Meanwhile capacitance Ca2 is discharged by the closed switch Sw5 across its terminals, and the op amp inverting input is driven to a virtual earth by the op amp 12 via the short circuit formed by this switch Sw5.
In the other phase φ2, when the phase φ1 switches are open, the input side of Ca1 is grounded by closing the appropriate switches Sw2 and Sw3, and the op amp forces the other end of Ca1 (connected thereto by the closing of the phase φ2 switch Sw2) to virtual ground by passing its charge onto Ca2. By charge conservation on the common node of Ca1 and Ca2, the op amp output Vsig=(Ca1/Ca2)*Vin. The gain of the PGA 10 is programmed by varying Ca1 and Ca2—in a practical implementation each of these would usually be implemented by banks of parallel capacitors selected by CMOS switches.
Operation of stage 1 of the ADC will now be described. In phase φ2, the op amp 12 of the input PGA also charges up the ADC input capacitors C1a, C1b to Vsig via the phase φ2 switches Sw7, Sw11, Sw8 and Sw13. This is the familiar sampling step of pipeline ADCs.
In stage 1 of the ADC, during phase φ2, the op amp 24 is reset by switch sw14 to discharge parasitics on its inverting input to ground.
Then, switches Sw7, Sw11, Sw8, Sw13 and Sw14, previously closed, are opened, retaining Vsig stored on capacitors C1a and C1b. This is the 'hold' step, and thus this arrangement is the familiar 'sample and hold' aspect of the ADC.
In the next phase 1, the Vsig end of C1a is switched to Vdac by means of the phase φ1 switch Sw9, and the Vsig end of C1b is connected to the op amp output Vout1 by means of the corresponding phase φ1 switch Sw6. The other ends of these capacitors are connected to the virtual earth created at the op amp inverting input via switches Sw10 and Sw12 respectively.
The total charge on the plates of C1a and C1b opposite from those connectable to the stage input is thus Vdac*C1a+Vout1*C1b. However the total charge on these plates at the end of the previous phase φ2 is Vsig*(C1a+C1b). Equating these charges gives:Vdac*C1a+Vout1*C1b=Vsig*(C1a+C1b)
In this example C1a is selected to be equal to C1b, so:Vdac+Vout1=2*VsigSoVout1=2*Vsig−VdacFor example, if Vsig=+Vref, then Vdac=+Vref, and Vout1=+Vref.If Vsig=+10 mV, then Vdac=+Vref, so Vout1=20 mV−Vref.If Vsig=−10 mV, then Vdac=−Vref, so Vout1=−20 mV+Vref.
The transfer characteristic is shown in FIG. 2a. This residue signal 2*(Vsig+/−Vref/2) charges up the input capacitors of the ADC second stage in φ1, ready to give its output in turn at the next phase φ2.
This arrangement has the disadvantage that, unless the input offset of the flash ADC comparator is less than 1LSB (for 14 bits, Vref=1V, 1LSB=1V/16384=60 μV, which is impractical in terms of offset voltage and overdrive required for reasonable response time), the extreme outputs of stage 1 will exceed or not get to the full-scale input range of the subsequent processing, so the whole pipeline ADC will exhibit missing or duplicate codes as the input is swept over the signal range. The effect of this on the transfer characteristic is illustrated in FIG. 2b.
To avoid this, a well-known modification to this arrangement replaces the single comparator in the flash ADC 26 by a pair of comparators with thresholds +/−(Vref/2), which can be regarded as a two-threshold comparator, and the two-level DAC by a three-level DAC with three possible conversion results or outputs:Vdac={−Vref, 0, +Vref}.
The transfer function for this modification is illustrated in FIG. 2c. If there is a comparator error, the output of the corresponding pipeline stage will exceed +/−Vref, but since the useful input range of the following stage is now extended past +/−Vref, this merely alters the codes generated downstream to compensate, and so reasonable errors in the comparators can be corrected for. This technique is known as the Digital Error Correction (DEC). DEC also relaxes the comparator input overdrive specification, since there is a wide band of "don't care" levels for the comparator, for instance +/−(Vref/10) or 100 mV, rather than 1LSB or 60 μV. Thus, a simple comparator is adequate yet will still react swiftly to the larger overdrive, and so can be designed to sample the input almost at the end of φ2, and be ready to drive the DAC at the start of non-overlapping clock φ1, thereby allowing the PGA op amp (or the ADC op amp, in the case of later stages of a multi-stage converter) the maximum time to settle, i.e. almost half of the input signal sample period.
A further modification, as mentioned above, is to extract two or more bits per stage, using a higher-resolution flash ADC (or multi-threshold comparator) and DAC giving fewer, but more complex stages, and thus introducing an extra degree of freedom in the optimisation of power, area and performance. To illustrate this variant, FIG. 3 shows an ADC stage comprising a capacitor bank structure 40 for extracting 2 bits per stage.
In the capacitor bank structure, five capacitors C1a, C1b, C1c, C1d and C1e are provided. A first terminal of each of four of the capacitors (C1a through C1d) is connected to Vdac via a switch (Sw29, Sw26, Sw25, Sw22 respectively) closed in a first clock phase φ1. The same terminal of each of the said four capacitors (C1a though C1d) is connected to Vsig via a switch (Sw28, Sw27, Sw24, Sw23 respectively) closed in a second clock phase φ2.
The other terminal of each of the said four capacitors is connected to the inverting input of the op amp 24, as is a terminal of the fifth capacitor C1e, each via a respective switch (Sw39, Sw36, Sw35, Sw32, Sw30) closed in the first clock phase φ1. Said five capacitor terminals are also connected to ground via respective switches (Sw38, Sw37, Sw34, Sw33, Sw31) closed in the second clock phase φ2.
The opposite terminal of the fifth capacitor C1e is connected to the output of the op amp 24 via a switch Sw20 closed in the first clock phase φ1. That output is also connected to ground, via a switch Sw21 closed in the second clock phase φ2.
A reset switch Sw40 is connected across the output and the inverting input of the op amp, closed during a reset phase φR.
The stage input Vsig feeds into the flash ADC via another phase φ2 switch Sw41, whose digital output drives a DAC, delivering a conversion result signal or voltage Vdac.
In this example, the flash ADC levels are −¾*Vref, −¼*Vref, +¼*Vref, and +¾*Vref, and the capacitor array consists of 4 equal input capacitors C1a, C1b, C1c, C1d, and a fifth capacitor C1e, which is thus grounded in the first clock phase φ2, then switched in feedback in the alternate clock phase φ1, while the input capacitors are connected to the DAC, whose output is one of {−Vref, −Vref/2, 0, +Vref/2, +Vref}.
The DAC illustrated in FIG. 3 may comprise a resistor potential divider to generate these levels. Alternatively, to avoid this potential divider, the switching of C1a, C1b, C1c, C1d in phase φ1 may be modified by adding extra switches controlled by the DAC control word, to switch them to +Vref and −Vref in combinations of (4,0) (3,1) (2,2) (1,3) (0,4) to generate net charge corresponding to −Vref, −Vref/2, 0, +Vref/2, and +Vref (i.e. −Vref*Ctot, −Vref/2*Ctot, . . . , where Ctot=C1a+C1b+C1c+C1d) according to the DAC control word. These switches may either be extra series switches directly controlled by the DAC control word, or may be the switches Sw29 etc. as shown, connected directly between +/−Vref and the respective capacitors, but controlled by bits derived from the DAC word and gated with the appropriate clock phase.
Whereas the examples described above, with reference to FIGS. 1 to 3, all rely on the provision of several stages to construct an ADC of desired resolution, it would be advantageous to reduce the number of op amps and capacitor banks to reduce chip area and total power consumption, especially for desired sample rates well within the speed capabilities of the technology.
"Efficient Circuit Configurations for Algorithmic Analog to Digital Converters" (K. Nagaraj, IEEE Trans. on Circuits and Systems II vol. 40 No. 12 Dec. 1993) describes a recirculating ADC arrangement in which banks of capacitors are used to store residual voltages, for re-presentation to conversion means.
FIG. 4 shows a similar arrangement, providing the same simple function as the ADC 20 illustrated in FIG. 1, but using only one amplifier and flash ADC. The schematic is similar to FIG. 1, but a second capacitor bank C2a, C2b is added.
Thus, as illustrated in FIG. 4, the output of the DAC 28 feeds back, via switch Sw59, which switches in phase φ1, to one end of the first input capacitor C1a. The same end of the first input capacitor is connected, via a switch Sw58, which switches in phase φ2, to a node A connected to the input to the stage 22 (which receives a signal Vsig output from the input PGA 10) via a switch Sw51 closed in a sub-phase φ2x of the phase φ2, and to the output of the op amp 24 via a switch Sw50 closed in a sub-phase φ2y of the phase φ2.
One terminal of the other input capacitor C1b in that bank is connected, via a phase φ2 switch Sw57, to the same node A of the stage 22. That terminal is also connected, via a further phase φ1 switch Sw56, to the output of the op amp 24.
The other terminal of the first input capacitor C1a is connected, via a phase φ2 switch Sw68, to ground, and, via another phase φ1 switch Sw69, to the inverting input of the op amp 24. Similarly, the other terminal of the second input capacitor C1b is connected, via a phase φ2 switch Sw67, to ground, and, via another phase φ1 switch Sw66, to the inverting input of the op amp 24.
The other capacitor bank C2a, C2b is clocked in anti-phase to the original ADC input bank C1a, C1b. This arises because the output of the DAC 28 feeds back, via switch Sw55, which switches in phase φ2y, to one end of the first input capacitor C2a of that bank. The same end of the first input capacitor C2a is connected, via a switch Sw54, which switches in phase φ1, to the output of the op amp 24.
One terminal of the other input capacitor C2b in that bank is connected, via a phase φ1 switch Sw53, to the output of the op amp 24. That terminal is also connected, via a further phase φ2y switch Sw52, to the output of the op amp 24.
The other terminal of the first input capacitor C2a is connected, via a phase φ1 switch Sw64, to ground, and, via another phase φ2y switch Sw65, to the inverting input of the op amp 24. Similarly, the other terminal of the second input capacitor C2b is connected, via a phase φ1 switch Sw63, to ground, and, via another phase φ2y switch Sw62, to the inverting input of the op amp 24.
A switch Sw60 presents the voltage at node A to the Flash ADC 26 in phase φ2 while, in phase φ1, the voltage on the output of the op amp is presented to the Flash ADC 26, by means of a switch Sw61.
A reset switch Sw70 across the op amp is also provided.
FIG. 5a shows a suitable clocking scheme, here illustrating only a 6-bit conversion for simplicity.
The underlying principle of operation is that capacitors C2a, C2b sample the output of the op amp in one phase, this output being based on the charge currently on C1b resulting from charge on C1a corresponding to the DAC output or conversion result signal Vdac and charge previously on C1a and C1b due to the previous op amp output. Then, in the next phase, C1a, C1b sample the op amp output based on the previous op amp output stored on C2a, C2b and the updated Vdac. This continues in a recirculating manner until the required degree of resolution has been reached.
Operation of the arrangement of FIG. 4 will now be described, with reference to FIG. 5a which shows a suitable clocking scheme.    a) In a first phase (φ2x) of the conversion cycle, Vsig charges up C1a and C1b, via an additional switch Sw51 interposed on the stage input. The flash ADC samples this Vsig, and latches its output for later use by the DAC. At the end of this phase, C1a, C1b are disconnected, to store the sampled Vsig.    b) Then, the op amp is reset by φR. For this first phase, this action could be performed simultaneously with the above φ2x phase, since the op amp output is not used, but on subsequent phases, this would short out a desired op amp output. Thus, in the illustrated example, phase φR comprises a signal which, for all cycles, closes the reset switch after completion of each of phases φ1, φ2x, and φ2y, as illustrated in FIG. 5a.     c) In the next phase, φ1, a residue 2*(Vsig+/−Vref/2) appears on the op amp output. This arises in a similar way to that described in relation to FIG. 1, with C1b acting as a feedback capacitor and C1a driven by the DAC, itself driven by the previously latched flash ADC output. The flash ADC samples the op amp output signal, and again latches its output for later use by the DAC. The op amp output is fed round to charge C2a and C2b. Then all capacitors are isolated again at the end of this phase.    d) Then the op amp is reset (by closing switch φR), ready for the next phase.    e) In the next phase φ2y, C2b acts as a feedback capacitor, C2a is driven by the DAC according to the previous flash ADC output, and the op amp delivers the next residue to C1a, C1b via switch Sw50 (with the Vsig switch sw51, closed in φ2x, being open in this phase).    f) Then, again, the op amp is reset (φR), ready for the next phase φ1.    g) In the next phase φ1, configured as (b), the next residue appears at the op amp, and is fed back to C2a, C2b. The cycle then continues from (d) until a desired number of bits is extracted.    h) Once the desired number of bits has been extracted, the entire process is restarted from step (a) with a new sample of Vsig.
The cycle described above with regard to FIG. 4 includes a reset every phase, analogous to the op amp reset in FIG. 1. However it is not necessary to reset every cycle. In an ideal implementation of this embodiment, it will be understood that it is only necessary to reset the op amp at the very start of operation, for example on power-up, since the op amp inverting input will settle back to very close to virtual earth voltage before the end of each phase, at which time the capacitors on that node are disconnected, leaving the inverting input voltage unchanged, still at the voltage to which it was reset, and hence not requiring further resetting.
However, incomplete settling of the op amp, in conjunction with parasitic capacitances on that node, may lead to some residual virtual earth signal charge propagating from one phase to the next. Assuming settling to less than 1LSB at the output, and parasitic capacitances smaller than the signal capacitances, this effect will be negligible during a few conversions, but over thousands of conversions the resulting errors might accumulate. Also, there is the possibility of other second-order effects, such as some pumping of charge by switch clock feed-through. Further, there will be some small but non-zero leakage currents associated with real switches on this node.
Therefore, it is typically convenient to reset once every complete conversion, during clock phase φ2x, in which case the clocking arrangement of FIG. 5b is possible, giving almost a complete half-sample-period for each phase rather than only a quarter-sample-period. For a conversion of N bits, N/2 clock cycles are required. So, a 12-bit 5 Ms/s converter would require a clock of 6×5 Ms/s=30 Ms/s, and op amp settling in less than 1/(2*30 Ms/s)=16.7 ns, the same as a more conventional 30 Ms/s multi-stage pipeline converter.
It will be appreciated that the comparators in the flash ADC need to sample every half-cycle. Typically such a flash ADC will contain clocked comparators, which need a reset phase before each cycle. It would be possible to use two flash ADCs in parallel, resetting each on alternate phases. Alternatively, and preferably, given that the ADC will respond with adequate accuracy very quickly as discussed above, ADC clocks, shown as φRS, can be introduced. The flash ADC is then reset when φRS is low, it is operable to sample at the rising edge of φRS, and to latch data into the DAC control word on the falling edge of φRS. Clock φRS rises at or shortly before the falling edge of φ2 and falls at or shortly before the rising edge of φ1.
It is noted that the above scheme can be readily extended to allow comparator offset correction, by DEC as described above, by setting the flash ADC comparator levels to +/−Vref/2 and Vdac to {−Vref, 0, Vref}.
In the arrangement of FIG. 4, the preceding PGA still only has the width of φ2x (16.7 ns in this example), to settle into the ADC input capacitors. As discussed above, it is desirable to maximise the time available for the PGA amplifier to settle, to reduce its required gain-bandwidth requirement and hence its area and power requirements.
Some improvement could be obtained by stretching the on-time of the initial phase comprising φ2x but, for a given input sample rate, this implies decreasing the time for the remaining conversion phases, so only limited improvement is available without reducing the available settling time for the later stages to well below 16.7 ns.

Abstract: Another embodiment presents a recirculating ADC stage which comprises a plurality of capacitor banks operable to be switched into and out of connection with other components of the ADC stage, in order to recirculate residual values for calculation of further bits of a digital output. Each bank comprises a plurality of capacitors, and cooperating switching means for connecting each bank in turn with the other components. The switching means are controlled by timing signals, wherein the switching means for each capacitor in each capacitor bank interpose the same number of switches between that capacitor and fed-back signals to that capacitor as to other capacitors of that bank.


A system according to the principles of the present disclosure includes a coolant valve, a valve control module, and a fault diagnostic module. The coolant valve includes a first valve chamber, a second valve chamber, and a partition disposed between the first and second valve chambers. The coolant valve further includes a first end stop disposed on a first outer perimeter surface of the first valve chamber and a second end stop disposed on a second outer perimeter surface of the second valve chamber. The valve control module rotates the coolant valve in a first direction and in a second direction that is opposite from the first direction. The fault diagnostic module diagnoses a fault in the coolant valve based on a measured position of the coolant valve as the coolant valve is rotated in the first and second directions.

The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
An internal combustion engine combusts air and fuel within cylinders to generate drive torque. Combustion of air and fuel also generates heat and exhaust. Exhaust produced by an engine flows through an exhaust system before being expelled to atmosphere.
Excessive heating may shorten the lifetime of the engine, engine components, and/or other components of a vehicle. As such, vehicles that include an internal combustion engine typically include a radiator that is connected to coolant channels within the engine. Engine coolant circulates through the coolant channels and the radiator. The engine coolant absorbs heat from the engine and carries the heat to the radiator. The radiator transfers heat from the engine coolant to air passing the radiator. The cooled engine coolant exiting the radiator is circulated back to the engine.

System and method for diagnosing a fault in a partitioned coolant valve


Orally disintegrating or dissolving edible strips for use as a matrix for retaining and delivering nutrients, flavors and medicinal compounds are made from new liquid film casting compositions comprising a major proportion of gelatin. The particularly low melting range for hydrated gelatin produces films that leave virtually no residue upon dissolving in the mouth and can be used in the form of thicker films and strips than known edible films.

Orally disintegrating or dissolving edible materials are currently used in a large variety of applications as a matrix for conveniently holding and using nutrients, flavors and medicinal compounds such as breath fresheners. The slow-dissolving edible strips currently in use are typically produced from pullulan, sodium alginate, starches, carrageenans or combinations of these ingredients. All of these are suitable film forming materials which dissolve adequately, but they tend to leave an undesirable gummy residue in the mouth that remains for a greater or lesser period of time after the film structure has broken down and the matrix has released its contents.
I have found that gelatin, widely used in a number of candy applications, is unusually suitable as the major film component of edible film materials, for use as edible dissolving strips.
Gelatin, in particular high bloom gelatin, is an excellent film former and can readily be cast into film form. Unique among the hydrocolloids, gelatin melts at approximately 37° C., with the result that an edible strip composed primarily of gelatin dissolves and melts in the mouth without leaving any of the unpleasant residue associated with polysaccharide films. A consequence of the unique melting property of gelatin is that films can be made thicker than films composed of other materials used for this purpose. Typical polysaccharide films in edible dissolving strips are less than 35 microns in thickness, whereas gelatin-based films can be used for this purpose with thicknesses as great as 85 microns. The thicker films do tend to dissolve more slowly, but still melt into their gelatin content, resulting in a pleasant sensation in the mouth.


A customer premises equipment (“CPE”) device for use with a cable signal provided by a cable system. The CPE device includes an antenna and a signal processing system. The antenna receives an interfering radio frequency (“RF”) signal generated by one or more external wireless signal sources as a copy signal. The signal processing system receives the interfering RF signal, the cable signal, and the copy signal, modifies the copy signal to produce a processed copy signal, and combines the cable signal, the interfering RF signal, and the processed copy signal to produce a combined signal. The signal processing system also monitors error rate values of the combined signal, and adjusts the copy signal such that the copy signal at least partially cancels the interfering RF signal in the combined signal thereby reducing the error rate values of the combined signal.

1. Field of the Invention
The present invention is directed generally to systems and methods for reducing or eliminating effects of interfering radio frequency signals on cable customer premises equipment devices.
2. Description of the Related Art
It has been reported that cable customer premises equipment ("CPE") devices, such as cable set-top-boxes, cable modems, and embedded multimedia terminal adapters ("EMTAs"), are experiencing problems functioning properly in the presence of wireless telephones because wireless telephones introduce interfering radio frequency ("RF") signals into the CPE devices. While many CPE devices include shielding that helps reduce such interfering wireless signals inside the CPE devices, the amplitudes of some strong wireless signals (e.g., RF signals used by wireless Long Term Evolution ("LTE") cellular telephones) are large enough to cause signal-processing problems in the CPE devices. Further, retail grade cable and RF splitters used by some people in their homes can be highly susceptible to RF interference. Thus, cable and RF splitters may receive interfering signals and function as a point of ingress into CPE devices for interfering signals.
Currently available methods of dealing with problems caused by interfering RF signals involve either abandoning the use of some frequencies (e.g., those experiencing significant RF interference) by a cable system, and/or increasing the shielding of the CPE devices. Abandoning the use of some frequencies is undesirable because doing so reduces data bandwidth and the number of video channels available to customers. Unfortunately, increasing the shielding of the CPE devices simply does not provide enough isolation from the interfering RF signal in some cases.
Therefore, a need exists for CPE devices configured to operate in the presence of strong wireless signals. CPE devices configured to significantly reduce interfering signals in the CPE devices would be particularly desirable. The present application provides these and other advantages as will be apparent from the following detailed description and accompanying figures.

This patent is subject to a terminal disclaimer.

Method for canceling interfering wireless signals in cable customer premises equipment devices


An amplifier includes an input matching network; at least one transistor; an input lead coupled to the at least one transistor; a ground terminal coupled to the transistor; an output lead coupled to the at least one transistor; an output matching circuit coupled to the output lead and to the at least one transistor; and a baseband impedance enhancement circuit having at least one reactive element coupled to the input matching network. The baseband impedance enhancement circuit is configured to reduce resonances of a baseband termination.

Radio Frequency (RF) power circuits are used in a variety of applications such as base stations for wireless communication systems and the like. The signals amplified by the RF power circuits often include signals that have a high frequency modulated carrier having frequencies in a 400 megahertz (MHz) to 6 gigahertz (GHz) range. The signals amplified by the RF power circuits often include a baseband signal that modulates a carrier typically at a relatively lower frequency and, depending on the application, can be up to 300 MHz or higher.
The RF power circuits can typically include a transistor die to amplify the RF signal. Examples of transistor dies that are used in RF applications include metal-oxide semiconductor field-effect transistors (MOSFETs), laterally-diffused metal-oxide semiconductor (LDMOS) devices, and high electron mobility transistor (HEMT) devices. These devices typically have relatively low characteristic impedances (for example, 2 ohms or less).
Input and output impedance matching circuits are typically used to match the RF power circuits to external transmission lines that provide RF signals to and from an RF power transistor. These external transmission lines have characteristic impedances that are typically about 50 ohms. However, the characteristic impedances could be any value as determined by a designer, needed for a particular application and/or system, and/or the like.
The input and output matching circuits typically include inductive and capacitive elements that are used to provide impedance matching between the input and output of the RF power transistor. The input and output matching circuits provide impedance matching for the signal frequencies that are amplified by the RF power transistor, such as those in the 400 MHz to 6 GHz range.
The RF power circuit operation can be improved by terminating RF signals as much as possible in the baseband frequency that is below the fundamental frequency and by terminating higher order harmonics of fundamental signals as much as possible that are above the fundamental frequency range. However, the baseband termination of an amplifier can still have resonances that impede the ability of digital predistortion (DPD) operation for linearity across a given band.
Accordingly, there is a need for implementing a RF power amplifier (RFPA) with a baseband impedance enhancement circuit configured to improve baseband impedance, improve digital predistortion (DPD) operation, correct for and/or improve linearity across a given band, and/or other baseband impedance enhancements.

Radio frequency amplifier implementing an input baseband enhancement circuit and a process of implementing the same


System and method for generating a synthetic full backup. A request to perform an incremental backup may be received at a target computer. The incremental backup may be performed on the target computer in response to the request. The target computer may maintain information identifying files that are encountered in the incremental backup. The information may be configured to be used to construct a synthetic full backup. A request to perform a synthetic full backup may be received. The information may be requested. The synthetic full backup may be constructed using the information from the target computer. A synthetic full backup index may be constructed for the synthetic full backup using records from old indexes for each file in the synthetic full backup. The synthetic full backup may be transferred to a backup image. The synthetic full backup index may be stored.

1. Technical Field
This disclosure relates generally to data backup systems, and, more specifically, to a distributed system and method for generating a synthetic full backup.
2. Description of the Related Art
Computer systems, and their components, are subject to various types of failures which may result in the loss of data. For example, a storage device used in or by the computer system may experience a failure (e.g. mechanical, electrical, magnetic, etc.) which may make any data stored on that storage device unreadable. Erroneous software or hardware operation may corrupt the data stored on a storage device, destroying the data stored on an otherwise properly functioning storage device. Any component in the storage chain between (and including) the storage device and the computer system may experience failure (e.g. the storage device, connectors (e.g. cables) between the storage device and other circuitry, the network between the storage device and the accessing computer system (in some cases), etc.).
To mitigate the risk of losing data, computer systems typically replicate (or make backup copies of) data stored on various storage devices. A variety of techniques are available for backing up data. For example, for a given set of data (such as the data on a particular computer system, e.g., one or more file systems and/or volumes) a full backup backs up the entire data set. This leads to the backup data set typically being stored in a single location, which simplifies restore operations. However, in systems with relatively few changes compared to the overall number of files, performing full backups can be relatively resource (e.g., time and network bandwidth) inefficient. In addition, the storage cost of maintaining multiple full backups is significant.
In order to reduce overall storage requirements for data backup, incremental backups are sometimes employed. An incremental backup typically only backs up files that have changed since the last backup (e.g., full or incremental) was taken. In systems with relatively few changes compared to the overall number of files, the time needed to take an incremental backup is typically substantially less than that needed for a full backup. However, performing a series of incremental backups can lead to data being stored in disparate locations, which can cause management of this data to become more complicated over time. Restores also often take longer in such situations, as information must be collected from different locations and longer and longer series of incremental backups. Because of this, it is desirable to periodically have full backups. However, since full backups typically consume significant network bandwidth and cut into the time available to perform incremental backups, improvements in backup systems that address the existing problems with incremental and full backups are desirable.


In accordance with the method of the present invention, a graph using an information processing apparatus is made. It includes: entering written signs in the form of characters, symbols, and/or graphicals in a document, the written signs serving as descriptors that specify a format of a graph represented by ordinary writings; recognizing unitary descriptors having a unitary meaning from the entered written signs and recognizing composite descriptors from a plurality of the unitary descriptors corresponding to a plurality of those written signs having an association with one another according to predetermined association rules; and producing graph definition data defining contents of the unitary descriptors and/or composite descriptors.

The present invention relates to an information processing apparatus for making a graph.
Supported by powerful hardware resources, in particular, highly advanced semiconductor devices, a recent information processing apparatus (computer-based system) incorporates object-oriented architecture and software that reduce the burden of users. For example, the apparatus can present a desired graph that is selected by a user from graph forms preset in the system.
To this end, the system first presents, on a display screen, a data table from a tabular document memory. From the data table display screen, a user points to desired data items. Then, a menu screen of "make graph" (not shown) is called. From the menu screen, the user selects or enters a desired condition or value for respective graph formatting items (e.g., graph type, size). The system uses the selected condition of the graph formatting items to make an object graph of the data items selected from the data table screen and displays or prints it out.
Currently, graph forms having wide varieties are desired by users in their request for diversified and sophisticated document presentations. In view of the essential function of graphs, i.e., "visualize data", a graph may be represented in an infinite number of ways. It is highly desired to provide a graph making system which can present a desired graph having desired layout, form, size, color, patterns etc., selected from all possible graph representations. Another important feature of the desired graph making system is ease of use without the need for users to learn a number of manual instructions since graph making systems are used by general end users. It is, thus, desired to provide a graph making system which can efficiently present a desired graph with a simple operation procedure.
The prior art system can only make a graph within the limits of a predetermined graph form menu, thus limiting the freedom or options on the part of users. A recently proposed graph making system incorporates a graph correcting feature which corrects a graph after it has been made and output. The graph correcting feature is limited, however, in variation and requires a complicated procedure involving a number of manual operations.
Thus, it is not so helpful to general end users.


A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

As is known in the art, GaN HEMT devices require insulating buffer layers for optimal performance. Unmodulated current flowing deep in the buffer layer will degrade output power and efficiency. FIG. 1 illustrates a typical GaN HEMT structure grown on an insulating SiC substrate. An aluminum nitride (AlN) nucleation layer is first grown on the substrate since gallium nitride, grown directly on SiC will exhibit a significant conductivity spike at the GaN/SiC interface. AlN has a very large bandgap (6.3 eV) which facilitates high resistivity.
However, even with an AlN layer we have observed conductivity spikes in HEMT material. FIG. 2 shows a doping-thickness plot of a sample which had an AlN nucleation layer with thickness of 1350 Å. The plot exhibits a conductivity spike deep in the material at a depth of 104 Å or 1 μm. The reverse bias leakage current was also measured on this sample using a mercury probe system. As shown in FIG. 3, the leakage current was significant (20 amperes/cm2) at −80 volts. The AlN in the sample shown in FIG. 1 was grown with an Al/N ratio of approximately 1.57, where the ratio Al/N is the ratio of Al to reactive nitrogen, it being noted that much more nitrogen flux is used compared with the aluminum flux, but only a small portion of the nitrogen flux is reactive. This ratio of Al to reactive nitrogen indicates that there was approximately 57% excess on the growth surface of aluminum to reactive nitrogen. It has been empirically found that Al to reactive nitrogen ratios greater than 1 (aluminum-rich) result in improved films.
FIG. 4 shows the SIMS (secondary ion mass spectroscopy) profile of the sample of FIG. 1. The N-type conduction spike is caused by silicon from the SiC substrate which is migrating through the AlN layer and piling up at the AlN/GaN interface. GaN is easily doped by silicon which results in the conductivity. The sample shown in FIG. 1 contains a 1350 Å AlN layer grown with Al/N=1.57. The profile shows silicon from the SiC substrate migrating through the thick AlN layer and piling up at the GaN/AlN interface.
We believe that the mechanism for such rapid silicon diffusion through the thick AlN layer is due to the excess aluminum on the surface which reacts with the SiC substrate. At our growth temperature of approximately 750° C., aluminum is a liquid.Al(liquid)+SiCAl4C3+Al(liquid+Si)  (1)Since silicon is now in a liquid state, it can rapidly move through the AlN film which is grown with excess aluminum.
Now that we have discovered the source of the doping (silicon) and mechanism for the rapid dopant migration, a structure is provided having a two-step AlN nucleation layer. In the old process the silicon concentration in the AlN peaked at greater than 1×1020 cm−3. In the process according to the invention, the silicon concentration peaked at less than 3×1018 cm−3. Thus, in accordance with the invention the AlN is substantially free of silicon.
In accordance with the invention, it has been demonstrated that good AlN material quality may be obtained with the entire AlN layer being conventionally grown by molecular beam epitaxy (MBE) with an Al to reactive nitrogen ratio greater than 1 (aluminum-rich).
In one embodiment, an initial AlN layer is grown with an Al to reactive nitrogen ratio less than 1 (nitrogen-rich) so that there is no free aluminum to react with the SiC surface. Once the SiC surface has been completely covered by AlN, the Al to reactive nitrogen ratio is increased to greater than 1 (aluminum-rich) for the rest of the layer to improve the material quality. The initial layer can be thin (30–200 Å) since its function is to cover the SiC surface. By making this layer thin, the roughness associated with growing AlN nitrogen-rich is minimized. The second AlN layer grown Al-rich improves the material quality.
In accordance with the invention, a semiconductor structure is provided having a substrate, a first AlN layer having an Al to reactive nitrogen ratio less than 1 disposed on the substrate, and a second AlN layer having an Al to reactive nitrogen ratio greater than 1 disposed on the first AlN layer.
In one embodiment, the substrate is a compound of silicon and wherein the first AlN layer is substantially free of silicon.
In accordance with the invention, a method is provided for forming a semiconductor structure comprises: growing a layer of AlN on a substrate comprising a compound of silicon with the reactive nitrogen flux greater than the aluminum flux; and changing the aluminum and reactive nitrogen fluxes such that the aluminum flux is greater than the reactive nitrogen flux.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.

Gallium nitride high electron mobility transistor structure


An adjustable anchor wing is provided for an agricultural bagging machine which not only acts as an anchor against premature movement of the machine as the bag is being filled, but also controls the density of the material being packed in an agricultural bag. The adjustable wing is supported by a pair of longitudinally movable cables with the cables being connected to the wing to enable the wing to be moved from a fully retracted position to a fully extended position.

1. Field of the Invention
This invention relates to an agricultural bagging machine and more particularly to an adjustable anchor wing for an agricultural bagging machine.
2. Description of the Related Art
Agricultural feed bagging machines have been employed for several years to pack or bag silage or the like into elongated plastic bags. Two of the earliest bagging machines are disclosed in U.S. Pat. Nos. 3,687,061 and 4,046,068. In the prior art bagging machines, silage or the like is supplied to the forward or intake end of the bagging machine and is fed to a rotor or the like which conveys the silage into a tunnel on which the bag is positioned so that the bag is filled. As silage is loaded into the bag, the bagging machine moves away from the filled end of the bag in a controlled fashion so as to achieve uniform compaction of the silage material within the bag. In U.S. Pat. No. 4,337,805, silage is forced by means of a rotor from the intake chamber of the machine through the output chamber of the machine and into the agricultural bag with a backstop structure yieldably engaging the closed end of the agricultural bag to resist the movement of the bagging machine away from the filled end of the agricultural bag as silage is forced into the bag. The structure of the '805 patent includes a pair of drums rotatably mounted on the bagging machine with a brake associated therewith for braking or resisting the rotation of the drum with a selected brake force. A cable is wrapped around the drum and is connected to the backstop.
Although the cable drum and backstop structure of the '805 patent and other similar machines do function generally satisfactorily, the cables, which are positioned on opposite sides of the bag, can create openings or holes in the bag which will adversely affect the fermentation process within the bag. A further disadvantage of the cable drum and backstop structure of the devices such as shown in the '805 patent is that the cables must be rewound after the filling of an individual bag. A further disadvantage of the cable drum and backstop structure of the machine such as disclosed in the '805 patent is that a dangerous condition exists should one of the cables break.
In an effort to overcome some of the disadvantages of machines such as disclosed in the '805 patent, an attempt was made in U.S. Pat. No. 4,621,666 to achieve the desired bagging operation while eliminating the need for the cable drum and backstop structure. In the '666 patent, the wheels on the bagging machine were braked to provide the desired resistance to the filling of the bag. Although the brake system of the '666 patent apparently met with some success, it is believed that machines such as disclosed in the '666 patent experience slippage difficulties in wet field conditions which adversely affect the bagging operation. It is also believed that the brake means alone on the bagging machine such as those disclosed in the '666 patent do not achieve the desired compaction of the silage material within the bag.
In applicant's U.S. Pat. No. 5,297,377, a bagging machine is described which has the capability of enabling the density of the silage material to be selectively controlled without the need of an elaborate braking system. In applicant's U.S. Pat. No. 5,297,377, a density control means is described which included a plurality of cables which are positioned in the flow of the silage material being bagged. In order to vary the density of the material in the machine of the '377 patent, more or less cables are employed based on the material being packed. For example, corn silage flows easy and would require more cables while alfalfa packs hard and would use less cables.
In applicant's U.S. Pat. No. 5,425,220, a density control means is described which includes a pair of intersecting cables positioned in the flow of the silage material being bagged. In order to vary the density of the material in the machine of the '220 patent, the relationship of the intersecting or crisscrossing cables is varied. In applicant's U.S. Pat. No. 5,671,594, a fixed beveled press plate is disclosed for use with a density control cable.
Although the use of the density control cables in applicant's previous patents such as U.S. Pat. No. 5,671,594 has met with success, the adjustment of the cable sloop takes approximately ten feet of machine movement before the adjusted cable loop becomes completely effective.

Adjustable anchor wing for an agricultural bagging machine


A method for enhancing allocation of fluid flow rates among a plurality of wellbores coupled to surface facilities is disclosed. The method includes modeling fluid flow characteristics of the wellbores and reservoirs penetrated by the wellbores. The method includes modeling fluid flow characteristics of the surface facilities. An optimizer adapted to determine an enhanced value of an objective function corresponding to the modeled fluid flow characteristics of the wellbores and the surface facilities is then operated. The objective function relates to at least one production system performance parameter. Fluid flow rates are then allocated according to the optimization.

Petroleum is generally produced by drilling wellbores through permeable earth formations having petroleum reservoirs therein, and causing petroleum fluids in the reservoir to move to the earth's surface through the wellbores. Movement is accomplished by creating a pressure difference between the reservoir and the wellbore. Produced fluids from the wells may include various quantities of crude oil, natural gas and/or water, depending on the conditions in the particular reservoir being produced. Depending on conditions in the particular reservoir, the amounts and rates at which the various fluids will be extracted from a particular well depend on factors which include pressure difference between the reservoir and the wellbore. As is known in the art, wellbore pressure may be adjusted by operating various devices such as chokes (orifices) disposed in the fluid flow path along the wellbore, pumps, compressors, fluid injection devices (which pump fluid into a reservoir to increase its pressure). Generally speaking, changing the rate at which a total volume of fluid is extracted from any particular wellbore may also affect relative rates at which oil, water and gas are produced from each wellbore.
Production processing equipment, known by a general term "surface facilities", includes various devices to separate oil and water in liquid form from gas in the produced petroleum. Extracted liquids may be temporarily stored or may be moved to a pipeline for transportation away from the location of the wellbore. Gas may be transported by pipeline to a point of sale, or may be transported by pipe for further processing away from the location of the wellbore. The surface facilities are typically designed to process selected volumes or quantities of produced petroleum. The selected volumes depend on what is believed to be likely volumes of production from various wellbores, and how many wellbores are to be coupled to a particular set of surface facilities. Depending on the physical location of the reservoir, such as below the ocean floor or other remote location, it is often economically advantageous to couple a substantial number of wells, and typically from a plurality of different reservoirs, to a single set of surface facilities. As for less complicated installations, the surface facilities coupled to multiple wells and reservoirs are typically selected to most efficiently process expected quantities of the various fluids produced from the wells. An important aspect of the economic performance of surface facilities is appropriate selection of sizes and capacities of various components of the surface facilities. Equipment which is too small for actual quantities of fluids produced may limit the rate at which the various wellbores may be produced. Such condition may result in poor economic performance of the entire reservoir and surface facility combination. Conversely, equipment which has excess capacity may increase capital costs beyond those necessary, reducing overall rate of return on investment. Still another problem in the efficient use of surface facilities can arise when some wellbores change fluid production rates. As is known in the art, such changes in rate may result from natural depletion of the reservoir, and from unforeseen problems with one or more wellbores in a reservoir, among others. Sometimes, it is possible to change production rates in other wellbores coupled to the surface facilities to maintain throughput in the surface facilities. As is known in the art, however, such production rate changes may be accompanied by changes in relative quantities of water, oil and gas produced from the affected wellbores. Such relative rate changes may affect the ability of the surface facilities to operate efficiently.
One way to determine expected quantities of produced fluids from each wellbore in each reservoir is to mathematically simulate the performance of each well in each reservoir to be coupled to the surface facilities. Typically this mathematical simulation is performed using a computer program. Such reservoir simulation computer programs are well known in the art. Reservoir simulation programs, however, typically do not include any means to couple the simulation result to a simulation of the operation of surface facilities. Therefore, there is no direct linkage between selective operation of the various wellbores and whether the surface facilities are being operated in an optimal way.
One system that attempts to couple reservoir simulation with surface facility simulation is described in, G. G. Hepguler et al, Integration of a field surface and production network with a reservoir simulator, SPE Computer Appl. vol. 9, p. 88, Society of Petroleum Engineers, Richardson, Tex. (1997). A limitation to the system described in the Hepguler et al reference is that it is unable to generate a corrective action with respect to the surface facilities which may arise out of infeasibility. Infeasibility is defined as the production system operating outside a constraint or limit, for example, defining a maximum allowable water production which is lower than an expected water production from reservoir simulation. Another limitation in the Hepulger et al system is that there is poor convergence in an optimization routine in the system. Other prior art optimization systems are described, for example in M. R. Palke et al, Nonlinear optimization of well production considering gas lift and phase behavior, Proceedings, SPE production operations symposium, p. 341, Society of Petroleum Engineers, Richardson, Tex. (1995). This reference deals primarily with optimizing gas lift systems and does not describe any means for optimizing surface facility use in conjunction with optimizing reservoir production.
A method for optimizing production allocation between wellbores in a reservoir is described in, Zakirov et al, Optmizing reservoir performance by automatic allocation of well rates, Conference Proceedings, 5th Math of Oil Recovery, Europe, p. 375 (1996). The method described in this reference does not deal with optimizing the use of surface facilities in conjunction with optimizing reservoir production.
It is desirable to have a simulation system that can enhance or optimize, both reservoir production and surface facility operation simultaneously, while also being able to assist in isolating and rectifying causes of the production system operating outside constraints.

Method for enhancing production allocation in an integrated reservoir and surface flow system


A fault tolerant control system delivers an embedded functional safety core and a distributed control engine with an onboard communication link in an industrial process control environment. The fault tolerant control system includes a process control workstation connected to a first network and a fault tolerant safety controller connected to a second network, wherein a process controller module, a safety controller module and a field device system integration module are co-located on a power interface board.

In a process control system, such as a distributed control system (DCS), fault tolerance enables continued operation in the event components within the system fail, or in the event the system experiences transient faults from various sources. One aspect common to fault tolerant systems involves the concept of redundancy, which can be simply defined as back up components that become operational when a failure occurs, allowing the system to continue to operate as intended. A safety instrumented system (SIS) is known in the art for continuing operation in a "safe state" to avoid adverse safety and health consequences through the use of a fault tolerant controller. Such fault tolerant controllers are often used in hazard protection systems (i.e., systems that regulate nuclear plant operation, turbomachinery, fire and gas sensing systems, and the like).
The control components of known fault tolerant controllers employ parallel control and extensive diagnostics to ensure uninterrupted process operation. One example of a fault tolerant controller is the TRICON controller available from Invensys Systems, Inc. The TRICON controller has a triple modular redundant (TMR) architecture that employs three isolated, parallel control systems and extensive diagnostics integrated into one system. The system uses two-out-of-three voting to provide high integrity, error-free, uninterrupted process operation with no single point of failure. Fault tolerant controllers of this type interface with, among various other components, modules of the process control system that have control functionality as well as communication functionality.
Any improvements that increase the efficient interoperation (in terms of protocol support, applications, or graphical user interface navigation of the system) of the SIS with the process control system, while simultaneously preserving safety functionality, are highly desirable. Various improvements related to minimizing the number of hardware components required to implement a fault tolerant controller, as well as allowing the controller to interface efficiently with the process control system, have been attempted without complete success.