An apparatus and method for protecting a wood chip destructuring device from damage due to tramp material. The destructuring device includes a pair of destructuring rolls operating a pre-established distance from each other and an infeed chute for delivering a stream of wood chips to pass through a region between the destructuring rolls. Said protection system includes a sensing unit and a control unit to detect tramp material present in the chip stream. If tramp material is detected in the wood chip flow, the protection system operates to further separate the destructuring rolls so that the surfaces of the destructuring rolls will not be damaged by the tramp material as the flow of material passes between the destructuring rolls.

1. Field of the Invention
The present invention relates to a destructuring apparatus in which wood chips are passed between closely operating rolls with compressive forces being exerted on the chips by the rolls, and relates more particularly to protecting the working surfaces of the closely operating rolls through the use of an apparatus to detect the existence of tramp material contained within the flow of wood chips, such that when tramp material is detected the closely operating rolls adjust to allow the flow of wood chips and tramp material to pass.
2. Description of the Prior Art
In a typical papermaking process, logs are debarked and chipped and the wood chips are treated to release individual cellulose fibers for the preparation of paper making stock.
One device for treating the chips to enhance liquor penetration and subsequent pulping operations is a wood chip cracking apparatus disclosed in U.S. Pat. No. 4,953,795, wherein chips are passed between closely operating rolls with compressive forces being exerted on the chips by the rolls. Another form of chip processing device is a chip slicer which includes a rotor operating within a drum, wherein oversized chips are forced against knives and sliced to acceptable thickness.
Common to chip processing devices is a conduit for handling the chips being led to the chip processing device and for controlling a uniform supply of wood chips to the chip processing device. Also common to all chip processing devices is the risk that tramp material, e.g., metal, stones, dirt, debris, etc., is contained within the chip flow stream, and such tramp material has a devastating effect on the chip processing apparatus, breaking knives or damaging operating surfaces to the extent that the machine must immediately be shut down, and the resultant damage repaired and/or equipment replaced.
A device for preventing damage to destructuring apparatuses due to the presence of tramp material is disclosed in U.S. Pat. No. 5,263,651, wherein an apparatus is provided capable of handling a continual flow of wood chips to a chip processing machine and automatically bypassing or shunting tramp material without interrupting the continuous machine operation and automatically restoring normal wood chip stream flow to the mechanism after a limited predetermined time.
One objective of the apparatus disclosed in U.S. Pat. No. 5,263,651 is to provide a method or apparatus for treating wood chips which prevents damage to treating and destructuring apparatus due to the presence of tramp material. The invention disclosed in U.S. Pat. No. 5,263,651 operates in such a manner that when tramp material is detected, the chip flow is diverted from the chip processing apparatus. Good chips flow to the chip processing apparatus and chips with tramp material flow to a dumping bin. In this way, the flow of chips to the chip processing apparatus is interrupted when tramp material is detected, thus preventing damage to the destructuring apparatus due to the presence of tramp material. Essentially, the safety device of U.S. Pat. No. 5,263,651 operates as a separator. Importantly, because the safety device diverts the flow of chips when tramp material is detected, the fiber contained in the wood chips that are diverted from the processing equipment is lost.

Protection system for a wood chip destructuring device


Low refrigerant charge in a refrigeration system is detected by monitoring the oscillation of the thermal expansion valve. This monitoring is accomplished with a sensor which senses the oscillation of the expansion valve and produces a signal indicative of the valve oscillation. The sensor signal is fed to a monitoring controller which produces a low charge signal whenever the amplitude of valve oscillation falls below a predetermined level, thus indicating low charge conditions. The sensor is preferably a temperature sensor situated at either the outlet or the inlet of the evaporator. The system further comprises a validity evaluation controller for determining when valve oscillation is a valid indication of low charge. The validity evaluation controller analyzes a number of system operating characteristics which affect valve oscillation. If the analysis of these characteristics suggests that valve oscillation will produce a valid indication of low charge, then the validity evaluation controller will activate the monitoring controller. Otherwise, the monitoring controller will not be activated.

This invention relates generally to detecting low refrigerant charge in refrigeration systems under thermal expansion valve control, particularly automotive air conditioning systems, and more particularly concerns monitoring the oscillation of the thermal expansion valve to determine when a low charge condition exists. As used herein, the term "refrigeration system" refers to refrigerators, air conditioners or any other system which produces a refrigeration effect. However, the present invention is most applicable to air conditioning systems for automobiles.
In typical automotive air conditioning systems, refrigerant tends to leak through hose permeation and the rotating compressor shaft seal. Refrigerant leakage causes many problems. First, the release of refrigerants into the environment is believed to cause environmental damage. For this reason, enactment of a federal environmental protection law requiring low charge detection systems for automobiles is anticipated. Second, when the refrigerant charge becomes insufficient, the reliability and cooling performance of the system suffer. Thus, a refrigeration system with a low charge is inefficient and wasteful of energy. Furthermore, low charge causes increased compressor operating temperatures while lowering mass flow rate. Reduced mass flow rate can result in insufficient flow of lubricating oil to the compressor. The lack of oil combined with high temperatures eventually causes compressor failure. Thus, there is much interest in developing means for detecting low charges.
There are a number of known ways to detect low charge, but many of these present certain disadvantages. For instance, determining low charge by measuring refrigerant inventory will not always be accurate because the optimum inventory level varies in accordance with many variables such as compressor speed, ambient and interior temperatures, blower speed, and component volumes. Other systems employ a low pressure cut-off switch which deactivates the compressor when system pressure falls below a predetermined threshold. However, since system pressures fluctuate greatly during proper operation (25-46 psi is typical), the predetermined threshold pressure must be set very low, such as 10-20 psi. As a result, the low pressure cut-off switch is effective to indicate only a severe loss of charge resulting from a ruptured hose or complete shaft seal failure. This switch will not detect marginal low charge conditions.
One way of detecting low charge which avoids the above problems is to measure the superheat at the evaporator exit. Superheat is the amount of temperature above the saturation temperature of the refrigerant. For air conditioning systems under thermal expansion valve control, the evaporator exit exhibits a small amount of superheat (typically 0.degree.-10.degree. F.), but if the system charge drops below a sufficient level, excess evaporator exit superheat will develop. It is well known to use excessive evaporator exit superheat as an indication of insufficient charge. For instance, U.S. Pat. No. 4,677,830 to Seiji Sumikawa et al. discloses providing a pressure sensor and a temperature sensor near the evaporator exit. An electronic control unit converts the measured pressure to a corresponding saturation temperature of the refrigerant. The difference between the measured temperature and the corresponding saturation temperature (i.e., the superheat) is then compared to a predetermined reference value to determine whether there is a sufficient quantity of refrigerant. If an insufficient charge is detected, the compressor is rendered inoperative by a signal from the electronic control unit.
In such superheat-based low charge detectors, evaporator exit superheat cannot be measured by simply sensing evaporator exit temperature. Instead, another parameter, usually system pressure or evaporator inlet temperature, must also be sensed so that the evaporator exit superheat can be mathematically derived from the evaporator exit temperature. This requires additional sensing equipment which adds cost to the detection system. Furthermore, a high degree of evaporator exit superheat can exist even with a full charge under some conditions. For example, during startup or rapid acceleration, the expansion valve does not open fast enough to control the sudden increase in the compressor flow rate and excess evaporator exit superheat develops. Therefore, excessive superheat at the evaporator exit is not always an indication of low charge in air conditioning systems under thermal expansion valve control. Thus, direct measurement of evaporator exit superheat will sometimes produce false indications of low charge.

Low refrigerant charge detection by monitoring thermal expansion valve oscillation


A mobile radio system includes a base station and a plurality of mobile radio apparatuses, with each mobile radio apparatus including a control CPU for controlling the mobile radio apparatus and monitoring the state of the hardware of the mobile radio apparatus, a transmitter unit for transmitting data in the form of radio waves, and a CPU monitor unit. The control CPU regularly monitors and checks for any abnormalities in the hardware of the mobile radio apparatus, the CPU monitor unit regularly monitors and checks for any abnormalities in the control CPU. If there is an abnormality, a disabled transmission output acceptance signal is supplied to the transmitter unit to inhibit or suppress the output of radio waves, thereby avoiding interference to the system caused by unnecessary radio wave transmission from an abnormal mobile radio apparatus.

1. Field of the Invention
The present invention relates to a mobile radio system equipped with means for suppressing an output of interference radio waves in the technical field of mobile radio.
2. Description of the Related Art
FIG. 3 is a schematic diagram showing the structure of a conventional mobile radio transmitter. In FIG. 3, reference numeral 1 represents data to be transmitted, reference numeral 2 represents a transmitter unit, and reference numeral 3 represents an antenna. Data 1 is supplied to the transmitter unit 2, and is modulated and transmitted as a radio wave output 4 from the antenna 3. Reference numeral 5 represents a control CPU which supplies a transmission output control signal 6 to the transmitter unit 2. The transmission output control signal controls the on/off state of transmission, transmission power level, and the like.
A method of controlling the radio wave output of the mobile radio apparatus constructed as indicated above will now be described. Referring to FIG. 3, if there is data 1 to be transmitted, the control CPU 5 controls the transmission on/off state, transmission power level, and the like of a transmission power amplifier and the like in the transmitter unit 2. The data modulated at the transmitter unit 2 is transmitted as the radio wave output 4 from the antenna 1 at a predetermined transmission power level.
In the above-described manner, the control CPU controls the radio wave output of the conventional mobile radio apparatus described above.
With such a conventional mobile radio apparatus, however, if the control CPU controlling the transmission power of the mobile radio apparatus crashes or the hardware of the mobile radio apparatus breaks down, there is a possibility of transmitting radio waves at an unexpected timing or at an unexpected power level. For example, in a mobile radio system using CDMA (code division multiple access), users in one area are assigned the same carrier. Therefore, the radio wave output of one mobile radio apparatus may become interference to another mobile radio apparatus. It is therefore necessary for each mobile radio apparatus to control its transmission power correctly. If a mobile radio apparatus transmits its radio wave output at a power level larger than the predetermined level, another mobile radio apparatus may possibly be interfered with by the high-power radio wave output. In such a case, the number of users in one area must be reduced. The mobile radio system may become unable to operate if a mobile radio apparatus becomes defective and transmits too large a radio wave output.
The above-described problems are also associated with a parent-child communication system (JP-A-3-240328) in which any abnormality between a parent apparatus and a child apparatus is monitored.

Mobile radio system with control over radio wave output if a malfunction is detected

Matsushita Electric Industrial Co., Ltd.


A silicon carbide substrate having a main surface angled off in an off direction relative to a {0001} plane is prepared. A protruding first alignment mark is formed on the main surface of the silicon carbide substrate. A second alignment mark is formed on the first alignment mark by forming a silicon carbide epitaxial layer on the first alignment mark. The first alignment mark includes a first region and a second region, the second region being in contact with the first region and extending from the first region in the off direction. The second alignment mark includes a first portion formed on the first region and a second portion formed on the second region. An alignment step includes the step of capturing an image of the first portion while not including the second portion, and recognizing an edge of the first portion based on the image.

1. Field of the Invention
The present invention relates to methods of manufacturing silicon carbide semiconductor devices.
2. Description of the Background Art
In recent years, silicon carbide has been increasingly employed as a material for a semiconductor device in order to allow a higher breakdown voltage, lower loss and the use in a high-temperature environment and the like of the semiconductor device. Silicon carbide is a wide band gap semiconductor having a band gap wider than that of silicon which has been conventionally and widely used as a material for a semiconductor device. By employing the silicon carbide as a material for a semiconductor device, therefore, a higher breakdown voltage, lower on-resistance and the like of the semiconductor device can be achieved. A semiconductor device made of silicon carbide also has the advantage of exhibiting less performance degradation when used in a high-temperature environment than a semiconductor device made of silicon.
For example, Japanese Patent Laying-Open No. 2011-100928, Japanese Patent Laying-Open No. 2013-65650 and Japanese Patent Laying-Open No. 2009-170558 describe semiconductor devices made of silicon carbide.

Method of manufacturing silicon carbide semiconductor device


A nonvolatile ferroelectric memory device has an improved cell array structure where one main bit line is connected in common to a plurality of sub bit lines, thereby reducing the layout area of the memory and facilitating the process. The nonvolatile ferroelectric memory device having a common main bit line comprises a plurality of cell array blocks, a plurality of sense amplifiers, a main amplifier unit, and a data bus unit. The plurality of cell array blocks, which include main bit lines shared by a plurality of sub bit lines each adjacent left and right to the main bit line, induce a sensing voltage of the main bit line depending on a voltage applied to the plurality of sub bit lines by cell data.

1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a nonvolatile ferroelectric memory device having a multi bit line structure where the main bit line is shared by a plurality of sub bit lines to improve a cell array structure, thereby reducing the number of main bit lines, and layout area of the memory and making the layout process easier.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as 'FeRAM') has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as 'DRAM') and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
FIG. 1 is a circuit diagram illustrating a cell array block having a conventional multi bit line structure.
In each sub cell array, main bit lines MBL are connected one by one to the sub bit lines SBL in parallel.
When a sub bit line selecting signal SBSW1 is activated, corresponding NMOS transistors N5 and N10 are turned on, so that loads of main bit lines MBL<0> and MBL<1> are burdened at levels of one corresponding sub bit line SBL<0> or SBL<1>. Also, when a sub bit line pull-down signal SBPD is activated, NMOS transistors N3 and N8 are turned on, so that the sub bit line SBL<0> or SBL<1> is regulated at a ground voltage level.
A sub bit line pull-up signal SBPU is to regulate power which is supplied to the sub bit lines SBL<0> and SBL<1>, and sub bit line selecting signals SBSW2_L and SBSW2_R are to regulate signal flow between the sub bit line pull-up signal SBPU and the sub bit lines SBL<0> and SBL<1>, respectively.
For example, when a high voltage is required to be generated in a low voltage, a voltage higher than a power voltage VCC is supplied as the sub bit line pull-up signal SBPU. Then, when the sub bit line selecting signal SBSW2_L is activated, a NMOS transistor N4 is turned on, so that the high voltage is supplied to the sub bit line SBL<0>. A plurality of cells each comprising a NMOS transistor and a ferroelectric capacitor are connected to the sub bit line SBL<0> and SBL<1>, respectively.
A NMOS transistor N1 is connected between a ground voltage terminal and a NMOS transistor N2, and a NMOS transistor N6 is connected between the ground voltage terminal and a NMOS transistor N7. Each of the NMOS transistors N1 and N6 receives a main bit line pull-down signal MBPD. The NMOS transistor N2, connected between the NMOS transistor N1 and the main bit line MBL<0>, has a gate connected to the sub bit line SBL<0>. The NMOS transistor N7, connected between the NMOS transistor N6 and the main bit line MBL<1>, has a gate connected to the sub bit line SBL<1>. When the main bit line pull-down signal MBPD is activated, each of the NMOS transistors N2 and N7 regulates the amount of current leaked from the main bit line MBL<0> and MBL<1> depending on data values of the sub bit lines SBL<0> and SBL<1>, thereby inducing sensing voltages of the main bit lines MBL<0> and MBL<1>. That is, voltages of different levels applied to the sub bit lines SBL<0> and SBL<1> vary channel resistance of the NMOS transistors N2 and N7 depending on cell data, thereby regulating the sensing voltages of the main bit lines MBL<0> and MBL<1> to have different levels.
A sense amplifier senses and amplifies a voltage difference of the main bit lines which is generated through the above-described principle.
FIG. 2 is a cross-sectional diagram illustrating a main bit line and a sub bit line which have the structure of FIG. 1.
Main bit lines MBL<0>˜MBL<3> are connected one by one to sub bit lines SBL<0>˜SBL<3> to be paired off.
In this multi bit line structure, the sub bit line SBL is formed of poly silicon or tungsten metal. On the other hand, the main bit line MBL is formed of Al or Cu. However, since thick metal is used to reduce resistance, the width and space of the metal become larger than those of other layers.
As the size of the cell becomes smaller, the space between the main bit lines becomes also smaller. As a result, the technology of securing a space for formation of main bit lines is required.


A chip storage and insertion guide includes a generally rectangular plastic housing with a top wall, side walls and end walls. The end walls define guide posts for insertion into matching apertures in a printed circuit board. The side walls are configured so that the pins of a new chip are bent inwardly slightly as the chip is gently forced into the rectangular guide until it is flush against the inside of the top wall. A handle portion of a pivoted arm mechanism extends transversely across the top wall at each end of the housing. Pivot arms at each end of the handle extend down the side walls and are attached thereto with pegs pivotally engaged in notches formed in the side walls. When the two arm mechanisms are pivoted outwardly, a shoulder portion of each arm moves upwardly to align a camming surface with the lower edge of the side walls thereby enabling the chip to be inserted in the socket of the printed circuit board. When the two arm mechanisms are pivoted inwardly, the camming surfaces move downwardly below the lower edge of the side walls to either disengage a mounted chip, or to prevent insertion of the chip until the posts are properly inserted in the apertures in the circuit board. The handle portions enable the user to easily grasp and manipulate the chip insertion guide.

Dual in-line package (DIP) chips, which include EPROM chips, typically are factory installed in electronic devices, such as computers or computer peripherals. Installation of an DIP chip requires care to avoid damage to the chip and to the bendable mounting pins which generally are arrayed in two parallel rows, one on each side, as found in an EPROM chip. To correctly install a new EPROM chip on, for instance, a printed circuit board, the mounting pins are first checked for alignment; second, any non-aligned pins are gently bent into alignment; and, third, the two rows of outwardly extending pins typically are bent inward slightly to facilitate insertion of the pins into the appropriate socket on the printed circuit board.
Factory installation techniques are designed to avoid damage to the delicate pins. Additionally, the correct orientation of the chip on the board is shown generally by including a notch at one end of the chip and a mating notch at one end of the socket. Recently, computer components with user replaceable EPROM or other chips have appeared on the market. This has the distinct advantage of permitting field upgrade to the computer component; and, in many cases, a user can perform the upgrade. However, installation by the unsophisticated may damage the chip, or damage or break the pins. A heretofore unsolved need exists for a uncomplicated and inexpensive guide to enable an average computer user to install a computer chip without damage thereto.


A self-refreshing memory has a refresh timer that generates refresh requests at a certain rate, and a refresh address counter that generates refresh addresses by counting the refresh requests. A refresh test circuit receives test signals from automatic test equipment that cause it to disable the refresh timer, reset the refresh address counter, then enable the refresh timer for a certain interval. At the end of this interval the refresh test circuit disables the refresh timer again and generates an output signal such as a serial data signal indicating the current refresh address, or a pass-fail signal indicating whether the refresh address is equal to or greater than a preset pass value.

This invention relates to a self-refreshing semiconductor memory with circuits for testing the refresh timer.
Generally referred to as a pseudo-static random-access memory or a virtual-static random-access memory, a self-refreshing memory has dynamic memory cells that require periodic refreshing, and also has circuits that refresh the memory cells at intervals controlled by a built-in timer. The growing demand for a self-refreshing memory, which combines the ease of use of a static random-access memory (SRAM) with the low cost of a dynamic random-access memory (DRAM), has made it necessary to produce and test self-refreshing memory devices in large quantities. One of the tests that must be performed is a test of the built-in timer, to verify that it generates refresh request signals at a rate fast enough to refresh all memory cells before loss of data occurs. If the built-in timer is suitably programmable, the results of this test can also be used to adjust the timer to the optimum rate, so that current is not wasted by refreshing more often than necessary.
One prior-art method of performing this test is to output the refresh request signals at a test pin and measure their frequency. A disadvantage of this method is that automatic memory test equipment is not normally designed for frequency measurements, so the test must be carried out with a separate instrument such as a frequency counter. The inability to use automatic test equipment makes this test method impractical for volume production.
Another prior-art method is to write a certain data pattern in the memory device, then pause for an interval longer than the data retention time of the memory cells, then read the data from all memory cells. If the built-in timer is producing refresh requests at the necessary rate, the same data should be read as was written into the memory cells. The test is normally performed twice, using different data patterns. Although this test can be carried out by automatic test equipment, it has the disadvantage that if the memory capacity is large, it takes considerable time to read and write all memory cells. In the case of a sixteen-megabit memory, for example, a two-pattern test takes fifteen seconds.

Self-refreshing memory with on-chip timer test circuit


According to the invention, an improved copper filling in the slots (4) of a permanently-stimulated synchronous motor (2) may be achieved, whereby such a motor is disclosed, comprising a stator (1), with parallel-edged slots (4), provided with a winding system of flat wires (5), whereby the flat wires (5) each enclose a tooth (3) and are embodied as a tooth coil (6). The flat wires (5) are wound edgewise such that the narrower side of the flat wire (5) faces the tooth (3) and each tooth coil (6) comprises at least two layers of flat wires (5).

The invention relates to a permanent magnet synchronous machine with a stator, which has parallel-flanked slots, which are provided with flat-wire windings, the flat-wire winding in each case surrounding a tooth and being in the form of a tooth-wound coil.
In order to reduce skin effects and therefore the amount of heat entering the electrical machine, it is known to wind coils comprising a twisted or stranded conductor bundle comprising individual round wires. Disadvantages here are the increased manufacturing complexity and the reduction in the copper filling factor in the slot of the electrical machine.
In order to avoid the abovementioned disadvantages, the coil can also be produced from copper pressed cable, but this results in increased costs for the coil.
EP 1 255 344 A1 has disclosed a coil arrangement which is constructed from flat wire.

Permanent magnet synchronous machine with flat-wire windings


A packaging container with an opening and closing lid, an opening is cut in an edge of the lid-raising member of a rear-side plate on a side of a lid-raising member of the inner case. A stopper is formed on part of the incision opening. An upper end edge of the stopper is an incision edge of the opening arranged at the lowest position of descent of an outer-case locking member and lower than a height position of inner-case locking member. The stopper approaches the outer-case locking member as the inner case moves upward. The outer-case locking member has at least a part of a stopper-corresponding portion in contact against the incision edge being the stopper, so that the outer-case locking member, which moves downward relative to the upward movement of the inner case, is in contact against the part that is the lowest position of descent thereof.

Conventionally, there are many packaging containers made from paper that store individually-packaged bar-shaped or plate-shaped chocolate snacks, cigarette tobaccos, etc. so that they can be taken out from a removal portion of the packaging containers. Among such packaging containers, ones that store the cigarette tobacco include packaging containers that are made from paper and cover the removal portion with an opening and closing lid.
As the above-described packaging container with the opening and closing lid, which is used for cigarette products, many packaging containers of a type, wherein an upper portion of the packaging container is formed as the opening and closing lid and the opening and closing lid is directly opened and closed by hand, are distributed on the market (see Patent Literature 1). Further, besides the above-described packaging container, there are packaging containers that are formed by an outer case having a rectangular cylindrical shape with open top and bottom ends or a bottomed rectangular parallelepiped outer case, in which an upper portion thereof is open as an insertion and removal opening, and by an inner case housed in the outer case having an opening and closing lid. Then, a number of packaging containers have been proposed in which the opening and closing lid opens and closes as the inner case is raised and lowered.
In a type of the packaging container in which the opening and closing lid opens and closes as the inner case is raised and lowered, a lid-raising member is provided that is connected to the opening and closing lid, and also the outer case is provided with a locking member that is folded back inward from the insertion and removal opening. Then, as the inner case moves upward, the lid-raising member also moves upward while being in sliding contact with an inner surface of the outer case and engages with the locking member of the outer case. Further, as a result of the inner case moving upward in a state in which the engagement between both of the members is maintained, the opening and closing lid is pulled by the lid-raising member and opens by setting a hinge portion as a center. Further, with respect to closing of the opening and closing lid, a structure is provided in which, when the opening and closing lid is lowered so as to enter inside the outer case, an upper portion of the lid-raising member (on a side of the opening and closing lid) or a rear plate portion of the opening and closing lid is pushed and raised up while being in contact against an opening edge of the insertion and removal opening of the outer case, thereby the opening and closing lid closes (Patent Literatures 2, 3, and 4, for example).

Packaging container with opening and closing lid


Computing systems and technical methods that transform data structures and pierce opacity difficulties associated with complex machine learning modules are disclosed. Advances include a framework and techniques that include: i) global diagnostics; ii) locally interpretable models LIME-SUP-R and LIME-SUP-D; and iii) explainable neural networks. Advances also include integrating LIME-SUP-R and LIME-SUP-D approaches that create a transformed data structure and replicated modeling over local and global effects and that yield high interpretability along with high accuracy of the replicated complex machine learning modules that make up a machine learning application.

Computer systems are often analogized to biologic systems. Even the World Wide Web is taken from the biological analogy of a spider connecting different points together with its gossamer web. Innovation has striven to create artificial intelligence, and analogized that intelligence to a human brain. Machine learning has been called an application of artificial intelligence that provides an electronic computing system the ability to automatically learn and improve from experience without being explicitly programmed. Thus, the term "application" is used in a context to indicate that the innovation is directed to more than math, but to a technical application that provides improved computing systems. Aside from any such use of literary analogies, computing systems are not biologic (or living) and are not living in the sense that humans are. Computing systems are not abstract, but are real—and deal with real machines and systems. Machine learning concerns computing solely in a technical environment to which problem situations are structured through models. The data structures associated with machine learning are distinct from the manner in which a human thinks, and the processing of data structures associated with machine learning is not an exercise in abstract thinking, nor divorceable from the technical environment.
Further, and often, machine learning systems must deal with data at volumes and speeds that the term "mere automation" does not apply in the sense that a machine is merely doing that which a human may do (this is commonly referred to as "Big Data"). As Big Data has become more usual in technical efforts, traditional techniques that may seek to apply simple statistical methods have encountered limitations in the art. Machine learning applications provide some means to overcome limitations with flexibility of modeling and creating data structures to reflect that modeling. It is to be appreciated that improvements in analysis, predictive performance, augmented feature engineering of technical systems may be advanced with fast and efficient machine learning techniques. Not only has machine learning applications proliferated, the complexity of machine learning applications also proliferates, creating issues with input to output traceability. The growing complexity and difficulty to understand, follow or interpret computing results leads to an opaqueness associated with such technical tools. The framework and techniques of the present innovation disclosed in this application aim at resolving or alleviating the opaqueness issue. The technical reality does not limit the usefulness of referring to computing systems with anthropic terms, especially discussing systems involved with machine learning and improvements to machine learning systems which may include (but not be limited to) actions that computers may long been incident to, such as the individual elements that courts have indicated to be abstract ideas. Ordered combinations of individual elements provide innovation that merits patent protection. In that light, even though machines and systems of machines, and critically, innovations concerned with machines and systems of machines are often much more easily grasped and understood when anthropic terms are used, terms like "learning," "predicting," "determining" and the like are to be understood in their technical sense in this application.

Resolving opaqueness of complex machine learning applications


An exercise machine includes a pair of support members having front ends connected to a crank unit for turning along with the crank unit and rear ends moving along a reciprocating path due to the guidance of a pair of guide members. A pair of foot members are each mounted on the respective support member. Each foot member moves through a substantially elliptical path, and each foot member at least partially overhangs the other foot member during at least a portion of travel along the substantially elliptical path.

1. Field of the Invention
This invention relates to an exercise machine, more particularly to an elliptical exercise machine with partially overhanging foot members which permits a user's feet to be placed in a more natural position.
2. Description of the Related Art
The benefits of regular exercise to improve overall health, appearance and longevity are well documented in the literature. Elliptical cross trainers have become one of the most popular exercise machines on the market because of their proven ability to simultaneously exercise both the upper and lower body at the same time, thereby increasing the efficiency of the exercise. Because elliptical cross trainer machines guide the motion of the feet through a smooth, predominantly elliptical-shaped closed-loop path, elliptical cross trainers also offer a smooth, low-impact exercise, minimizing the risk of injury to the back, knees, hips, and ankles.
However, because elliptical cross trainers define the travel path of the user's feet rather than the exerciser defining their own foot motion, there can be discrepancies between the natural motion of the human body and the motion imposed on the exerciser by the elliptical cross-trainer machine.
As one example, stride length is one variable that is defined by elliptical cross trainers. Some people, based on their height or preferences, may want an exercise machine that provides a short stride length, while others may want a longer stride length. Many elliptical cross trainers have been optimized to target a stride length that appeals to a majority of users. Other elliptical cross trainers have adjustable stride length so that a user may increase or decrease the stride length to their individual preferences.
Another variable is stride width, or the spacing between the insoles of the feet. When a person is standing, a comfortable stance is to place the feet approximately shoulder width apart. However, while walking or running, a person tends to decrease their stride width so that they place their feet closer to the centerline of the body. In other words, during walking or running, the stride width narrows, converging toward one foot being placed in-line with the other. This is more akin to walking a tightrope. However, traditional elliptical cross-trainers have, to date, always maintained a relatively large stride width. Unlike a treadmill, where a user can define their own foot motion, and therefore can walk with a natural stride width, an elliptical trainer defines the foot motion for the user, forcing the user to maintain the stride width of the machine.
For exercise equipment, a measurement of this machine-defined stride width is known as Q-Factor. For example, a Q-Factor measurement for a bicycle would traditionally be defined as the distance between the vertical plane defined by the inside edge of the left pedal and the vertical plane defined by the inside edge of the right pedal. Similarly, in the case of an elliptical cross trainer, Q-Factor has traditionally been defined as the distance between the vertical plane defined by the inside edge of the left foot support platform and the vertical plane defined by the inside edge of the right foot support platform.
Because an elliptical cross trainer moves each foot support platform through a substantially elliptical closed loop path, and because the foot platforms must not interfere with each other or with any other component of the elliptical trainer during this travel, the Q-Factors for traditional elliptical trainers have always been positive numbers to prevent interferences. However, this forces a wide stance upon the exerciser, forcing a user to move their feet within two widely-spaced parallel planes. This wide stride width is unnatural.
An object of the present invention is to provide an exercise machine with all of the benefits of a traditional elliptical cross trainer, while allowing the user to chose a very narrow stride width.
Another object of the present invention is to provide an elliptical cross trainer with foot support platforms that move through a closed-loop path without interfering with one another, while having foot support platforms spaced so close to one another that a portion of each foot support platform crosses the centerline of the machine.


A mobile device 500 comprises a display portion 502 including a display screen, a first keypad portion 501, a second keypad portion 502, and at least one input device 508, 510-524, 531-544 associated with at least one of the first keypad portion 501, the second keypad portion 502, and the display portion 504. The first and second keypad portions 501, 502 are independently rotatably coupled to the display portion 502 to provide a plurality of operational configurations for the device 500. The first keypad portion 501 may be positioned on an upper level of the device 500 and the second keypad portion 502 may be positioned on a lower level of the device 500, with the display portion 502 being positioned in the middle of the device 500. The first keypad portion 501 may be superimposed over at least part of the display portion 502.

Different standard keyboard arrangements are known. The most widely used English-language alphabetic key arrangement is the QWERTY arrangement. Other types of standard English-language alphabetic key arrangements include the QWERTZ arrangement, the AZERTY arrangement, and the DVORAK arrangement. Each of these arrangements, when presented as a full-size keyboard, utilizes 26 keys for 26 different characters.
Numeric characters are often presented along with alphabetic characters on keyboards of communication devices, such as telephones. One standard setting body, the International Telecommunications Union ("ITU"), has established phone standards for the arrangement of alphanumeric keys. One such standard, corresponds to ITU Standard E.161, entitled "Arrangement of Digits, Letters, and Symbols on Telephones and Other Devices That Can Be Used for Gaining Access to a Telephone Network" (also known as ANSI TI.703-1995/1999 and ISO/IEC 9995-8:1994). According to this standard, ten keys are used to present the alphabetic characters A-Z and the numbers 0-9. In order to enter alphabetic characters, the user may be required to tap the keys multiple times until the desired character appears on a display screen, among other known entry techniques.
Mobile communication devices that include a combined alphabet entry keyboard and a telephony keyboard are known. Examples of such mobile communication devices include mobile stations, cellular telephones, wireless personal digital assistants (PDAs), two-way paging devices, and others. Combining a traditional-style text-entry keyboard (e.g., a QWERTY-style keyboard) with a traditional-style telephony keyboard on the same mobile communication device typically involves undesirable ergonomic and/or non-intuitive user interface compromises. Furthermore, a certain keypad configuration that is desirable for one application will not always be desirable for a second or third application. The size of the keyboard is often limited by the size of the device, making the keyboard more difficult to use. It is thus desirable to have fewer but larger keys to perform alphanumeric and telephony functions.

Pivoting, multi-configuration mobile device


A vehicular suspension system is provided which includes upper and lower arms connected to a vehicle body in such a manner as to pivot in an up-and-down direction. The upper arm and the lower arm retain upper and lower portions of a knuckle, respectively. The suspension system includes retention mechanisms for retaining the upper and lower arms in such a manner as to allow the upper and lower arms to shift in a lateral direction of the vehicle body, and conversion mechanisms for converting pivotal movements of the upper and lower arms in the up-and-down direction into displacements of the upper and lower arms in the lateral direction of the vehicle body.

Suspension systems of the type described are known from, for example, JP-A-2-57413. A suspension system disclosed in JP-A-2-57413 is provided as a double wishbone suspension including upper and lower arms retaining knuckles in such a manner as to allow pivotal movements of the knuckles. The suspension system of this type will be explained with reference to FIG. 16.
FIG. 16 is a view schematically showing a right half of a vehicle body 201 of a vehicle 200 including conventional right and left double wishbone suspensions (only right one shown and designated at 210).
The suspension 210 suspends a right wheel 214 from the vehicle body 201. The suspension 210 includes upper and lower arms 211, 212, connected to a right side of the vehicle body 201 in such a manner as to pivot up and down, and a knuckle 213 connected to respective distal ends of the upper and lower arms 211, 212.
When the vehicle 200 turns leftward, a damper or a spring of the right suspension 210 is compressed while a damper or a spring of the left suspension is stretched because the vehicle 200 is subjected to a centrifugal force. As a result, the vehicle 200 causes a body roll, namely, the vehicle body 201 leans rightward such that the right side of the vehicle body 201 is lowered while a left side of the vehicle body 201 is lifted up. It is to be noted that, when the vehicle 200 turns leftward, the right wheel 214 is an outside wheel while a left wheel (not shown) is an inside wheel.
The body roll of the vehicle 200 is geometrically defined by arrangement of suspension links (suspension arms). The vehicle body 201 rolls on a roll center RC2.
As shown in FIG. 16, the right wheel 214 has a contact point Pg2 contacting a ground surface GL. A roll center height Hr2 is defined as a distance between the ground surface GL and the roll center RC2. A line Li2 passes through the point Pg2 and the roll center RC2. The line Li2 is inclined at an angle θ2 relative to the ground surface GL.
When the right wheel 214 pivots upward relative to the vehicle body 201, the contact point Pg2 of the right wheel 214 is shifted laterally outwardly of the vehicle body 201. The contact point Pg2 then moves about the roll center RC2 in an arcuate line Lg2 extending upwardly outwardly of the vehicle body 201. This results in relatively great roll center height Hr2.
A cornering force (sideways force) CF2 is produced at the contact point Pg2 of the right wheel 214. The cornering force CF2 includes a component (called "horizontal component") Fs2 directed towards the roll center RC2 and a component (called "vertical component") Fg2 directed towards the ground surface GL. These two components Fs2, Fg2 each correspond in magnitude to the angle θ2. The component Fs2 is applied to the suspension 210. A reaction force of the component Fg2 acts in such a direction as to lift up the wheel 214. The component Fg2 can be generally expressed by the following equation:Fg2=CF2×sin θ2.
Since the angle θ2 is relatively great, the component Fg2 is great, too. That is, the reaction force becomes large. It is necessary to reduce the reaction force acting in such a direction as to lift up the wheel 214.
The suspension 210 is disposed to provide a wheel alignment designed such that a tire of the right wheel 214 is disposed perpendicular to the ground surface GL. In other words, the wheel 214 is arranged to provide an increased negative camber when the suspension 210 shifts upwardly.
However, since links of the double wishbone suspension 210 are arranged in such a manner as to provide the increased negative camber of the wheel 214, the roll center height Hr2 is rendered large. This results in a large component Fg2. That is, a large reaction force of the large component Fg2 acts on the right wheel 26 in such a direction as to lift up the right wheel 26. Thus, a pressure applied from the ground surface GL to the tire of the right (outside) wheel 214 is abruptly increased while a pressure applied from the ground surface GL to a tire of the left (inside) wheel is abruptly decreased. As a result, a load applied to the right wheel 214 is abruptly increased. A total grip of the tires of the right and left wheels would be abruptly decreased since the tire has a property of providing a very small grip when an excessively large load is applied to the tire. Thus, it is difficult to provide optimized tire grips. Moreover, it is difficult to improve a damping function of the suspension 210 when the vehicle 200 makes a left turn.
The reason why the above problem occurs is that, when the suspension 210 shifts upwardly, the upper arm 211 draws an upper part of the tire of the wheel 214 inwardly of the vehicle body 201 while the lower arm 212 retains or pushes a substantially central portion of the tire of the wheel 214 outwardly of the vehicle body 201 such that the contact point Pg2 of the wheel 214 is displaced laterally outwardly of the vehicle body 201 and then moves in the acuate line Lg2.
To address the problem, there is a need to provide: (1) a suitable camber for efficient contact between a wheel and a ground surface; and (2) an appropriate roll center height determining how much a load applied to each of right and left wheels is varied during turning of a vehicle.


The present invention describes a method and apparatus for implementing a mobile receiver (10) that combats multiple access interference (MAI) in a code division multiple access (CDMA) spread spectrum system. Such capability is required by mobile receivers to support high data rate applications such as the ones provided by HSDPA and 1xTREME. A receiver (10) combining equalization and interference cancellation (IC), according to the invention, avoids the shortcomings of either equalization or IC and provides superior performance relative to prior art methodologies. The approach proposed by this invention for the operation of the mobile receiver is to first perform equalization (12) of the received signal (r) and then use the resulting decisions to perform IC. Combining equalization and IC yields a complexity that is smaller to that obtained by implementing conventional IC with a Rake receiver for the same performance.

Code division multiple access (CDMA) has been extensively used in such applications as cellular and satellite communications. CDMA signals increase the spectrum required for the transmission of a particular data rate by modulating each information symbol with a spread spectrum code having a rate larger than the data rate. The same spreading code is used for each information symbol. Typically, the spreading code comprises of a few tens or a few hundreds elements, called chips. To decrease the correlations among spreading codes assigned to different users and thereby reduce the interference among different users, the data stream after spreading is typically scrambled with a pseudonoise (PN) code that is generated serially and cyclically and has a larger period than the spreading code. Examples of such CDMA signal spreading are the schemes used by the IS-95/CDMA2000 and 3GPP systems.
With CDMA, the signals from all users simultaneously occupy the same frequency band. The receiver discriminates the multiple signals by exploiting the properties of the spreading and scrambling codes that are applied to the signal of each user. The receiver attempts to match in time with the codes of the desired signal a replica of those spreading and scrambling codes. Only then the demodulation result is meaningful; otherwise it appears noise-like. Thus, if the arriving signals have different codes or different code off-sets, they can be discriminated at the receiver.
In the forward link of cellular communication systems, i.e. the communication from base stations to mobile terminals, the wireless channel may introduce multipath propagation. Even if the signals transmitted by the base station are spread using orthogonal codes (Walsh codes), the multipath propagation will destroy the orthogonality and produce multiple-access interference (MAI).
Interference cancellation (IC) attempts to suppress the MAI by estimating and subtracting the interference from the received signal, as disclosed in U.S. Pat. No. 5,553,062 to Schilling. Because the capacity of CDMA systems is typically MAI limited, estimating and canceling the MAI will increase the capacity. Alternatively, IC can reduce the symbol or frame error rate thereby allowing communication with higher data rates.
Equalization also attempts to suppress the MAI by restoring the orthogonality of the transmitted signals at the receiver. This is accomplished by inverting the effects introduced by the channel due to multipath propagation, as disclosed in "Multiple Access Interference Suppression with Linear Chip Equalizers in WCDMA Downlink Receivers", K. Hooli, et. al, pp. 467-471, Globecom 1999.
Conventional IC schemes use knowledge of the spreading and scrambling codes used to transmit the signals, the decisions from a Rake receiver, and a channel estimate to reconstruct the components of the received signal and remove the interference, as disclosed in U.S. Pat. No. 5,553,062 to Schilling. The Rake receiver is however highly suboptimal in the presence of interference, particularly for higher order data modulations such as QAM. The data decisions provided by the Rake have poor reliability and when used by IC to reconstruct the interference they can result in significant performance degradation since the estimated received signal components are not very accurate. Subsequent cancellation of the estimated interference can therefore result in worse performance than the one of the Rake receiver since additional interference may be introduced due to erroneous decisions.
Conventional equalization methods try to either adapt to a known signal, such as the common pilot signal transmitted in the downlink of CDMA systems, or attempt to estimate or adapt to the channel impulse response and then use it to reverse the impact of multipath propagation on the received signal. Examples of well-known equalizers based on adaptation are the NLMS and its variants while equalizers based on channel inversion are the MMSE and its variants, as disclosed in "Multiple Access Interference Suppression with Linear Chip Equalizers in WCDMA Downlink Receivers", K. Hooli, et. al, pp. 467-471, Globecom 1999. Although outperforming the Rake receiver in interference environments, equalization methods perform worse than IC when interference from signals transmitted to other mobile users in the same cell is low to moderate and generally have similar performance to IC in high interference environments.

Combined equalizer and spread spectrum interference canceller method and implementation for the downlink of CDMA systems


The present invention amplifier circuit for connection to input and output devices, e.g. speakers includes input amplifier; positive power supply input; negative power supply input; first bias input means; second bias input means; a first differentiator/summer, receiving signals from the input amplifier, from the positive power supply input and from the first bias input means; a second differentiator/summer, receiving signals form the input amplifier, from the negative power supply input and from the second bias input means. There are PMOS and NMOS devices receiving signals from respective differentiator/summers, receiving power form the positive and negative power supply inputs and receiving signals from respective A. C. signal paths. Thus, there are first and second A. C. signal paths, each receiving signals from the input amplifier and sending resultant signals to the PMOS and NMOS devices, respectively; and an output terminal receiving signals from said PMOS and NMOS devices. Each differentiator/summer acts to assure that the gate tracks the source of its MOS device so that the gate-source potentials of the MOS devices are unaffected by changes in the potential of the power supply; and they send signals to the MOS devices respectively only upon potential differences in signals between the bias input means and the input amplifier signals. The first A. C. signal path and the second A. C. signal path provide parallel paths to the MOS device respectively to bypass the differentiator/summers, when signals from the input amplifier exceed a preset frequency.

1. Field of the Invention
The present invention relates to an amplifier circuit in which all of the advantages of power MOSFETs are realized without compromise. It is directed to an amplifier circuit of the common source push-pull output stage with MOSFETs and with enhanced efficiency based on support controlling components for high-frequency and low-frequency signals.
2. Information Disclosure Statement
Audio amplification has been evolving for decades and, with the advent of newer and better electronic components, improved amplifiers move in the direction of what sounds to the human ear to approach perfection. Nonetheless, various new problems arise from enhanced designs and in the inclusion of newly developed electronic components. The following background information and prior art is exemplary of the evolution of audio amplifiers to the present day.
Linear power amplifiers, such as those used in audio amplifiers, traditionally employ an output stage of what is known as the push-pull configuration. In such a configuration, a pair of semiconductor devices is arranged in a series fashion between a positive power supply feed and a negative power supply feed. The point at which the two semiconductor devices adjoin serves as the output terminal. The semiconductor devices are then driven so as to alternately conduct, thus causing the potential at the output node to rise and fall between the two power supply connections.
MOS transistors (Metal Oxide Semiconductor) are frequently used in a push-pull linear output stage. The MOS device has three electrodes: a gate terminal for receiving a controlling signal, a source terminal for establishing a return path for said controlling signal, and a drain terminal for establishing a conductive path to the source terminal; the degree of conductivity being controlled by said controlling signal. Significant quantities of capacitance exist between these electrodes; the controlling signal must charge and discharge these capacitances to modulate the conductivity of the path existing between the source and drain electrodes.
Returning to the discussion of the push-pull linear output stage, a MOS device of a positive type (PMOS) and a MOS device of a negative type (NMOS) are generally used; the contrary nature of their electrode polarities facilitate implementation in the push-pull configuration. There are two ways of arranging this connection. One is the "source follower" configuration. In this implementation, the source terminals of the respective PMOS and NMOS transistors are interconnected to form the output node. Positive power is fed to the drain terminal of the NMOS device, and negative power is fed to the drain terminal of the PMOS device. The chief drawback to this configuration is that as the output potential is modulated the source terminals "follow" the modulation, hence upsetting the potential difference between the source and gate terminals. Such a configuration requires that the drive signal potential exceed the desired output potential in both the positive and negative direction. This is necessary to insure that sufficient potential difference exists between the gate and source terminals to sustain conductivity from drain to source.
The advantage of this configuration is that the above-described "bootstrapping" phenomenon lessens the burden which the interelectrode capacitances pose on the driver stage. Another benefit is that the potential existing between the gates of the respective MOS devices is of a relatively small magnitude, making it easy to establish a single path to both gates; a necessary step in completing the circuit architecture. Hence, speed and linearity are enhanced.
The second way of arranging the push-pull connection is known as the "common source" configuration. In this implementation, the drain terminals of the respective PMOS and NMOS transistors are interconnected to form the output node. Positive power is fed to the source terminal of the PMOS device, and negative power is fed to the source terminal of the NMOS device. The bootstrapping phenomenon exhibited by the source follower arrangement is eliminated, because excitation of the common source output stage does not cause a corresponding disruption of the source terminal potentials of the respective MOS devices. Hence, relatively small signal potentials are sufficient to cause large output modulations.
The chief drawback is that the interelectrode capacitances of the MOS devices are not bootstrapped, and pose a significant burden on the driver stage. Furthermore, a large potential exists between the gate terminals of the MOS devices, making it difficult to establish a single path to both gates. These drawbacks tend to compound one another, since the driver stage is burdened by both the current requirement and the potential difference between the MOS gates. Consequently, speed and linearity are diminished.
U.S. Pat. No. 4,464,634, issued to Juan F. Velezquez, describes an "Audio Power Amplifier", which utilizes an input amplifier stage and an output amplifier stage. The output power amplifier stage utilizes a P-channel MOSFET and an N-channel MOSFET having interconnected drain electrodes forming an output signal terminal. A driver circuit is provided which operates in a transconductance mode wherein the output current through the MOSFETs is directionally proportional to the input voltage applied to the output amplifier stage. Feedback paths are used between the output power amplifier stage and the input amplifier stage as well as between the output and input of the input amplifier stage.
U.S. Pat. No. 4,467,288, issued to James C. Strickland, describes an amplifier utilizing an input amplifier, an output amplifier and a cooperative combination of negative and positive feedback loops that removes substantially all distortion and error in the amplified output, according to the inventor. Negative feedback loops are provided around the output amplifier and the input/output amplifier combination to provide degenerative error reduction. The negative feedback loop around the MOSFET output stage identifies the error component and inversely superposes an inverted signal. In other words, the precorrection is precisely controlled to effect virtually complete serial cancellation of the to-be-introduced error as the signal is propagated through the amplifier.
U.S. Pat. No. 4,483,016, issued to Peter A. Hochstein and Kelvin Shih, describes an "Audio Amplifier", using a differential amplifier stage, a primary amplification stage, bipolar supply connections for supplying electric current, the primary amplification stage including at least two MOSFETs in common source connection between the power supply connections and a circuit transducer output, along with a level shifting driver stage connected to ground.
U.S. Pat. No. Re. 31,749, which is a reissue of a U.S. Pat. No. 4,100,502, issued to Osamu Yamashiro, describes an amplifier circuit with a complementary inverter which includes a P-channel metal-insulator-semiconductor FET connected to a first source potential, an N-channel metal-insulator-semiconductor FET connected to a second source potential with the gate of the two FETs with a common linear input, respective load resistors connected to the drains of the FETs, an output being derived from the interconnection of the load resistors or from the drains of the FETs, and a bias resistor between the gate and the drain of each of the complementary FETs, the input being supplied to the gate of the FETs through respective capacitors. The FETs are individually biased so that the circuit may serve as a Class B push-pull amplifier of low power consumption.
U.S. Pat. No. 4,743,860, issued to James M. Dziagwa, sets forth a power amplifier circuit having a first and second series of capacitors with a junction between them which are coupled across a floating, double ended power supply. A speaker is coupled between the junction and the ground and first and second complementary conductivity power MOSFETs are connected between a first power supply output and a ground and between a second power supply output and a ground, respectively. The MOSFETs are driven by an amplified audio input signal and alternatively connect to one or the other supply output to ground to alternately charge and discharge the capacitors, causing alternating current to flow through the speaker.
An article in Volume 63, Number 4 of Radio Electronics., April, 1992, entitled "High Power Hi-Fi Audio Amp For Your Car", at Page 31 et seq., describes an audio amplifier in which output swings of an operational amplifier drive a current source and a current sink for the purpose of translating and applying said output swings to an NPN transistor and a PNP transistor, respectively. The voltage drop between the bases of said NPN and said PNP transistor are determined by a voltage multiplier. FET output transistors are then driven into conduction by said NPN transistor and said PNP transistor.
Notwithstanding the above prior art and the state-of-the-art as understood, it appears that the present invention concept wherein capacitors are used as a high-frequency signal path and a separate path is provided for the low-frequency signal component with D. C. bias, by its own circuit, is neither taught nor suggested.

Linear amplifier circuit for audio equipment


In a process for producing silicon semiconductor wafers, a silicon single crystal is pulled using the Czochralski method and is processed to form semiconductor wafers, a ratio V/G of pulling rate V and axial temperature gradient G at a growth front during the pulling of the single crystal being controlled in such a manner that agglomerated vacancy defects above a critical size are formed in the single crystal, the agglomerated vacancy defects, in a region of the semiconductor wafer that is of relevance to electronic components, shrinking during production of the components such that the size in this region no longer exceeds the critical size. Silicon semiconductor wafers with agglomerated vacancy defects in the relevant device region preferably contain agglomerated vacancy defects having an inner surface which is at least partially free of an oxide layer and a size of less than 50 nm.

1. Field of the Invention
The invention relates to a process for producing silicon semiconductor wafers with defined defect properties in terms of agglomerated vacancy defects. The invention also relates to silicon semiconductor wafers having these defect properties.
2. Background Art
It is known that single-crystal silicon may have grown-in defects, which are undesirable since they interfere with the functioning of electronic components which are integrated in the silicon, and may even cause functional failure of such devices. Defects of this type are in particular agglomerates of point defects, a distinction being drawn in this context between vacancies and silicon interstitials. If point defects of this type reach supersaturated levels, they tend to collect to form agglomerates. Agglomerated vacancy defects (voids) are often referred to in the literature as COP defects (crystal originated particles), LPDs (light point defects), LLS (localized light scatterers), LSTD (laser scanning tomography defects) or FPD (flow pattern defects). Silicon interstitials are referred to as "A defects" (A-swirl-defects) or Lpit's (large etch pits), if the agglomerates, on account of their size, are already forming secondary defects in the form of dislocations, and "B defects" if secondary defects of this type have not yet occurred.
It is also known that the point defects are formed during the production of the single crystal, and in this context the ratio V/G of the pulling rate V and the axial temperature gradient G at the growth front of the crystal are the defining parameters. If the ratio V/G is above a critical value ξc, which nowadays is currently assumed to be approximately 0.134 mm2min−1K−1, point defects of the vacancy type dominate, whereas at a ratio V/G below the critical value ξc, silicon interstitials dominate. During cooling of the single crystal, the point defects which have formed reach supersaturated levels and can accumulate to form larger groupings. It is known that the size of the agglomerated vacancy defects is influenced to a crucial extent by the cooling rate q at which the single crystal is cooled from approximately 1100° C. to lower temperatures, specifically in such a manner that the defect size decreases with increasing cooling rate, whereas the density of these defects rises. Since the cooling rate q is approximately directly proportional to the axial temperature gradient G, it is therefore also possible to influence the size of the agglomerated point defects by suitably controlling the ratio V/G during pulling of the single crystal, and if the axial temperature gradient G is known, it is possible to draw conclusions as to the size of the agglomerated vacancy defects which form. Agglomerated vacancy defects are generally octahedral in form. Details on the size of defects of this type describe a volume of a sphere corresponding to the defect volume.
The radiant heat emitted from the edge of the single crystal causes the axial temperature gradient G to rise toward the edge of the single crystal. A direct consequence of this radial dependency of the axial temperature gradient G(r) on the radial position r of the single crystal and of the abovementioned dependency of the size of the agglomerated vacancy defects on the axial temperature gradient G is that the size of these defects is not constant in the vacancy zone of a semiconductor wafer, but rather decreases from the center toward the edge of the semiconductor wafer, whereas the density of the defects increases in the same direction.
The axial temperature gradient G can be calculated accurately using computer codes (for example FEMAG from FEMAGSoft S.A., Belgium), which means that it is possible to control the ratio V/G by controlling the pulling rate. At the same time, given knowledge of the axial temperature gradient G, the radial distribution of the incorporated vacancies and therefore in turn the radial variation in the mean size of the agglomerated vacancy defects can be calculated. Formulae which were developed by Voronkov (Voronkov, V. V. and Falster, R. (1999) J. APPL. PHYS., 86, (11) 5975 and Voronkov, V. V. and Falster, R. (1998) J. CRYSTAL GROWTH, 194 76) form the theoretical basis for these calculations. These formulae allow, for example, experimentally verifiable predictions to be made as to the concentration of incorporated vacancies, the concentration of agglomerated vacancies and the size of these agglomerates.
The presence of agglomerated vacancy defects start to become a problem, given an increasing integration density of electronic components and the associated reduction in size of the structures used to form them, if the size of these defects is in the region of the feature size of the components.
To solve this problem, it has already been proposed that the ratio V/G be controlled in such a manner that no agglomerated point defects are formed, since the supersaturation of the point defects which this requires is not reached. However, control of this type, in particular when producing silicon semiconductor wafers with large diameters of 200 mm and above, can only be realized with considerable difficulties, since on account of the dependency of the axial temperature gradient G on the radial position r, only a narrow process window within which V/G may vary is available. As demonstrated by an accurate calculation based on the Voronkov formulae, the V/G range in which there is no agglomeration of vacancies in the vacancy-rich zones is extremely narrow and therefore not technically accessible. Similar considerations apply to the B defects on the Si interstitial-rich side. Only the formation of Lpit's can be avoided by a greater V/G range, since for this purpose a critical size of the interstitial aggregates has to be exceeded.
Another way of solving the problem consists in dissolving agglomerated vacancy defects by means of a heat treatment of the semiconductor wafers in a region close to the surface. A heat treatment of this type is likewise complex and, in particular if it is carried out in an oxidizing atmosphere, cannot be fully realized (Ji Wook Seo and Young Kwan Kim, JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 149 (7) G379-G383 (2002)). According to current opinion as expressed in the prior art, a two-stage mechanism is active during the heat treatment; in the first stage, an oxide layer is removed from the inner surface of the agglomerated vacancy defects. This requires the oxygen to diffuse out of the region close to the surface, thereby eliminating the oxygen supersaturation which is present there. Only after that can the agglomerated vacancy defects be dissolved by recombination with silicon interstitials and by outdiffusion of vacancies. Although the production of a thermal oxide layer on the semiconductor wafer promotes the formation of silicon interstitials, an oxidizing heat treatment of the semiconductor wafers aimed at achieving this is considered unfavorable compared to a heat treatment in a nonoxidizing atmosphere, such as argon, since it impedes the elimination of the oxide layer from the inner surface of the agglomerated vacancy defects which is required in the first step.

Process for producing silicon semiconductor wafers with defined defect properties, and silicon semiconductor wafers having these defect properties


A shielding needle assembly is provided with a hub having a needle cannula with a puncture tip extending from a forward end thereof, and a shield member in telescoping association with the hub. A drive member biases the hub and the shield member away from each other for relative telescopic movement between a first position in which the puncture tip extends from a forward end of the shield member, and a second position in which the puncture tip is encompassed within the shield member. A pivoting lever maintains the hub and the shield member in the first position against the bias of the drive member with the needle cannula exposed for use. The lever is pivotable during contact with a patient's skin surface such as during venipuncture, thereby releasing the hub and the shield member from the first position and permitting the drive member to bias the hub and the shield member toward the second position.

Field of the Invention
The present invention relates to blood collection sets for safe and convenient handling of needles used in blood collection procedures. More particularly, the present invention relates to a blood collection set including a safety shield for protecting users from a used needle tip.
Description of Related Art
Disposable medical devices having medical needles are used for administering medication or withdrawing fluid from the body of a patient. Such disposable medical devices typically include blood-collecting needles, fluid handling needles, and assemblies thereof. Current medical practice requires that fluid containers and medical needles used in such devices be inexpensive and readily disposable. Existing blood collection devices often employ some form of durable, reusable holder on which detachable and disposable medical needles and fluid collection tubes may be mounted. A blood collection device of this nature may be assembled prior to use and then discarded after use.
A blood collection device or intravenous (IV) infusion device typically includes a needle cannula having a proximal end, a pointed distal end, and a lumen extending therebetween. The proximal end of the needle cannula is securely mounted in a plastic hub defining a central passage that communicates with the lumen extending through the needle cannula. A thin, flexible thermoplastic tubing is connected to the hub and communicates with the lumen of the needle cannula. The end of the flexible plastic tubing remote from the needle cannula may include a fixture for connecting the needle cannula to a fluid collection tube holder or other receptacle. The specific construction of the fixture will depend upon the characteristics of the receptacle to which the fixture is to be connected.
In order to reduce the risk of incurring an accidental needle-stick wound, protection of used needle cannulas becomes important. With concern about infection and transmission of diseases, methods and devices to enclose or cover the used needle cannula have become very important and in great demand in the medical field. For example, needle assemblies often employ a safety shield that can be moved into shielding engagement with a used needle cannula to minimize risk of an accidental needle stick.
Prior art devices in this area often include flexible wings, which are used as means for securing the needle assemblies to the body of a patient during a medical procedure. Winged needle assemblies typically include a barrel or body portion, a wing portion mounted to the body portion, and a needle cannula. The wing portion can be used to manipulate the assembly during insertion and withdrawal of the needle cannula from the patient. The wing portion is also used to stabilize the assembly against the patient's skin, by providing a surface area for taping, attachment, etc. to the patient to prevent movement of the assembly.
U.S. Pat. No. 7,294,118 to Saulenas et al. discloses a retractable push-button needle assembly, in which a needle is attached to a hub and extends through a barrel. A push-button actuator extends from the hub and is in interference engagement with the barrel. Activation is accomplished with a user actively pushing the push-button into the barrel, thereby causing the needle to retract within the barrel under power of a spring disposed between the hub and the barrel.
Needle assemblies may also incorporate passively activated safety features. In such devices, the needle shielding feature is passively actuated upon normal usage of the device. For example, the activation of the safety feature may automatically occur, such as upon removing an outer safety packaging cover and after releasing the user's grip on the device after insertion of the needle into the patient's injection site. The safety feature may be a safety shield that is propelled toward the needle tip, or a force that is exerted on the needle to retract the needle into the body of the device. U.S. Pat. No. 6,682,510 to Niermann discloses a passive safety blood collection set which includes a tip guard slidably movable along a needle cannula. The tip guard is mounted to a needle hub through a pair of collapsible leaves, which are collapsed onto themselves and held in place by a packaging cover. In use, the practitioner holds the leaves in the collapsed or folded state to remove the cover, and then releases the leaves enabling them to unfold to propel the tip guard distally.
Such passively actuated devices typically involve a relative axial force between the needle and the shield for activation of the safety feature. If this relative axial force is greater than a resisting force supplied by the friction between the needle and the patient's tissue, the needle may be self-ejected from the patient during activation of the safety feature.

Passively shielding needle assembly with skin sensor


The present invention is a method for fracturing a zone to collect fluids from the zone through a wellbore. The method introduces into the wellbore a series of fracturing fluids to fracture the sediments either above or below the bottom of the wellbore. A fracture extends from the wellbore into the sediments which can include a plurality of producing zones.

The conventional process to produce fluids, such as oil and/or gas, from one or more subterranean zones is to drill a well into the zones. The zones are hydraulically fractured to increase the zone's permeabilities by providing fractures in the zones along which fluids can travel. The increased permeabilities increase the recovery of oil and/or gas by the well.
The process of hydraulically fracturing a target zone is composed of numerous steps. In the most common process, the steps include cementing a production casing in a well, loading an explosive device such as a perforating gun, lowering the device into the well by a wireline or similar device to the depth of the target zone, perforating the production casing in the well by triggering the explosive device, introducing a fluid into the target zone through the perforations to hydraulically fracture the target zone, and introducing a proppant into the fracture to restrict closure of the fracture after the fluid is removed from the well. The lengths of the fractures are typically limited to the target zone to prevent undesired fluids from other zones from flowing into the target zone along the fractures, to prevent the loss of the desired fluid into adjacent thief zones, and to prevent the commingled production of fluids from different zones. Thus, the casing is cemented in the wellbore not only for wellbore support but also to isolate the target zone from other zones. This technique is especially adapted for use in fracturing discrete, continuous zone-type deposits of the type shown in FIG. 1 from the well 50. The sandstone layer 54 a,b in such deposits is relatively thin (e.g., less than 200 feet) and is therefore easily targeted for fracturing by this technique.
The technique is not effective in recovering oil and/or gas from thick deposits, such as many tight-sands gas deposits. Gas contained in such deposits is much more difficult to recover than the gas in the continuous zone-type deposits exemplified in FIG. 1 due to their differing geologic characteristics distributed over great vertical heights. As shown in FIG. 2, the gas in tight sands deposits is contained in isolated, discontinuous sandstone stringers 58 of varying shapes and sizes which are in poor fluid communication with one another and are spaced over a vertical depth of typically more than about 500 feet and frequently over several thousand feet. Due to their highly heterogeneous nature, tight sands deposits include not one but a plurality of gas reservoir zones spaced over this large vertical depth interval. Due to the extreme thickness of tight sands deposits, the above-described conventional fracturing technique is of limited effectiveness in fracturing the numerous stringers 58 to permit the gas in the stringers to flow into the well 62. To fracture a multiplicity of such zones, the steps described above could be repeated for the larger stringers 58 and not the smaller stringers 58 due to cost prohibitions, thereby resulting in high well completion costs but also decreased oil and/or gas recoveries.
The fracturing technique described above is also not effective for fracturing zones located at greater depths than the bottom of the well. To employ the conventional fracturing technique, the well must be drilled to the depth of the target producing zone. This is often impractical and/or uneconomical for deep zones and/or for existing wells that for various reasons were originally drilled shallower than a desired target zone.
As a result of the high cost to drill and complete a well according to the above-noted technique, it is uneconomical to produce the oil and/or gas in many zones, especially zones located at depths below the bottom of the well or contained in the very thick tight sands deposits. Consequently, many oil and/or gas deposits are deemed uneconomic and therefore not recoverable.


A method for generating a synthetic seismogram. In one implementation, a ray tracing may be performed on a subsurface. The ray tracing may generate a plurality of rays. A first seismic wavefront may be reconstructed by triangulating a first plurality of control points that correspond to the plurality of rays. Each control point may represent an end point of a ray at the first seismic wavefront. The plurality of rays may be propagated to a second seismic wavefront. The second seismic wavefront may have a hole associated with at least one missing ray at the second seismic wavefront. A plurality of points on a circle may be defined that correspond to a second plurality of control points defining the hole. The second seismic wavefront may be reconstructed based on the plurality of points on the circle.

1. Field of the Invention
Implementations of various technologies described herein generally relate to methods and systems for generating synthetic seismograms.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Seismic data signals are typically acquired by measuring and recording data during a seismic survey. A seismic survey may be performed by repeatedly firing an impulsive seismic energy source at the surface of the earth, sea or seafloor and recording the received signals at a set of receivers. The receivers may typically be situated at the same surface as the source, but laterally displaced on regular grid positions. However, there may be situations where a non-regular distribution of the receivers is preferred or where the source and the receivers may be positioned at different depth levels. In a typical seismic survey, the source and the receivers may be displaced at fixed intervals (e.g., 25 meters) and in a certain direction (e.g., the "inline" direction).
During the seismic survey, the cycle of firing the source and recording the received signals may be repeated a plurality of times. When firing the seismic source, a pressure wave may be excited and propagated into the subsurface. The pressure wave reflects off interfaces between various earth layers (such as, rock, sand, shale, and chalk layers) and propagates upwardly to the set of receivers, where the particle velocity of the wave vibrations or the pressure oscillations of the wave may be measured and recorded.
The strength of the reflected wave is proportional to the amount of change in elastic parameters, e.g., density, pressure velocity, and shear velocity, at the respective interfaces. Consequently, the data recorded by the receivers represents the elastic characteristics of the subsurface below the receivers.
The seismic survey provides a seismogram that can be used to model images of the subsurface. Images of the subsurface may be derived by determining a velocity model of the subsurface. The velocity model is determined within a recursive process that generates synthetic seismograms, and compares the synthetic seismograms to the seismogram from the survey. The velocity model is updated until the synthetic seismogram is similar to the actual survey seismogram.
The synthetic seismogram may be generated as numerous reconstructed wavefronts. The reconstructed wavefronts may be 3-dimensional models of the pressure wave as the pressure wave travels through the subsurface. Typically, the reconstructed wavefronts are modeled using polygon triangulation.


A WiFi system comprising two or more access points operating in the same network and a plurality of nodes. Each node is in communicative association with each access point. A plurality of nodes transmits data in a scheduled communication with a first access point of the two or more access points and subsequently re-transmits some or all of the data in a scheduled communication with a second access point of the two or more access points.

Communication in industrial environments often demands high reliability, low latency, and good scalability. Traditionally, wired technologies like fieldbus systems and industrial Ethernet have served the communication requirements of industrial applications. However, such solutions usually incur high installation and maintenance costs. Wireless technologies provide a low-cost alternative with a number of additional benefits such as fast installation and commissioning, higher flexibility, mobility support, and increased personal safety. Wireless technologies are expected to play a crucial role in realising the vision of the fourth industrial revolution.
IEEE 802.11-based wireless local area networks (WLANs), also known as Wi-Fi networks, are presently deemed ineligible for industrial communication due to two main limitations. First, legacy WLANs lack determinism as access to the networks is random and not guaranteed. Moreover, legacy WLANs cannot guarantee that a particular desired latency is achievable. This is due to the underlying channel access mechanism at the medium access control (MAC) layer which is based on IEEE 802.11 distributed coordination function (DCF) i.e., carrier sense multiple access with collision avoidance (CSMA/CA). The randomness associated with channel access procedure prohibits deterministic delay guarantees. Second, legacy WLANs are not reliable enough for industrial communication. This is mainly due to collisions arising from contention-based medium access. Moreover, techniques like time slotted channel hopping (TSCH), which are desirable in fulfilling the stringent requirements of industrial communications, cannot be easily applied.
Wi-Fi offers a number of benefits as compared to conventional IEEE 802.15.1 and IEEE 802.15.4 solutions which are frequently employed in industrial environments. First, Wi-Fi supports much higher data rates which directly translate to reduction in transmission latency. Second, with Wi-Fi based Physical (PHY) layer, higher payload can be transmitted per timeslot. This provides the opportunity of implementing robust channel coding techniques for enhanced reliability without incurring additional latency. Third, the PHY layer in conventional Wi-Fi standards is based on orthogonal frequency division multiplexing (OFDM) which is much more robust to multi-path fading. Fourth, Wi-Fi provides higher coverage than 802.15.1-based or 802.15.4-based solutions.

Reliable and deterministic Wi-Fi for industrial control applications


A location classifier generates location information based on textual strings in input text. The location information defines potential geographical relevance of the input text. In determining the location information, the location classifier may receive at least one geo-relevance profile associated with at least one string in the input text, obtain a combined geo-relevance profile for the document from the at least one geo-relevance profile, and determine geographical relevance of the input text based on the combined geo-relevance profile.

A. Field of the Invention
Systems and methods described herein relate to search engines and, more particularly, to techniques for classifying text as relevant to geographic regions.
B. Description of Related Art
The World Wide Web ("web") contains a vast amount of information. Locating a desired portion of the information, however, can be challenging. This problem is compounded because the amount of information on the web and the number of new users inexperienced at web searching are growing rapidly.
Search engines attempt to return hyperlinks to web pages in which a user is interested. Generally, search engines base their determination of the user's interest on search terms (called a search query) entered by the user. The goal of the search engine is to provide links to high quality, relevant results (e.g., web pages) to the user based on the search query. Typically, the search engine accomplishes this by matching the terms in the search query to a corpus of pre-stored web pages. Web pages that contain the user's search terms are "hits" and are returned to the user as links.
In an attempt to increase the relevancy and quality of the web pages returned to the user, a search engine may attempt to sort the list of hits so that the most relevant and/or highest quality pages are at the top of the list of hits returned to the user. For example, the search engine may assign a rank or score to each hit, where the score is designed to correspond to the relevance or importance of the web page.
Local search engines are search engines that attempt to return relevant web pages within a specific geographic region. When indexing documents for a local search engine, it is desirable to be able to, when appropriate, automatically associate documents, or sections of documents, with specific geographic regions. For example, a web page about a restaurant in New York City should be associated with New York City. In many cases, geographically specific web pages include postal addresses or other geographic information that unambiguously associates the web page with the geographic region. In other cases, however, the web page may be related to a specific geographic region but yet may include only partial postal address information or include other terms that may not be easily recognized as being associated with a specific geographic location. This makes it difficult to determine the geographic region with which the web page is associated.

Classification of ambiguous geographic references


A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that t the states of m.sub.1 and m.sub.2 active storage elements each are decoded to provide a partial address to identify one of the N switching elements to be turned to its "on" state. The sum of m.sub.1 and m.sub.2 is less than N.

1. Field of the Invention
The present invention relates to user re-programmable interconnect architectures, which employ active devices as re-programmable interconnect elements whose programmed state is stored in an active storage element (typically a static RAM cell). More particularly, the present invention relates to such architectures employing fewer storage elements than reprogrammable interconnect elements and which employ decoding to activate individual interconnect paths.
2. The Prior Art
User-programmable interconnect integrated circuit architectures are known in the art. These architectures typically comprise a set of interconnect conductors in an integrated circuit which a user may programmably connect to one another by the use of programmable elements.
The prior art contains examples of such architectures using one-time programmable interconnect elements, such as antifuses. A typical example of an architecture employing one-time programmable antifuse elements is disclosed in U.S. Pat. No. 4,758,745. The prior art contains examples of such architectures using re-programmable interconnect elements, such as active switching devices, each of whose programmed state (i.e., "on" or "off") is stored in an associated active storage element (typically a static RAM cell). A typical example of such an architecture is disclosed in U.S. Pat. No. 4,870,302.
While prior art user re-programmable interconnect architectures have found application in a number of different devices, such as field-programmable gate array devices, they are inherently limited by the amount of area which must be taken up on the integrated circuit die to accommodate the active switching device, usually an N-channel pass transistor or a CMOS pass transistor pair, and its associated active storage element. Because of this area utilization necessary to accommodate the interconnect mechanism, the size of practically-realizable re-programmable interconnect architectures is limited.
Bipolar crosspoint switch implementations of such user-programmable interconnect integrated circuit architectures are known in the art. For example, H. Shin et al, A 5Gb/s 16.times.16 Si-Bipolar Crosspoint Switch, 1992 IEEE ISSCC, pp. 228-229, describe a bipolar n by n crosspoint switch which requires n n:1 multiplexers. While such circuits are practically implementable in bipolar technology for reasonably small values of n (i.e., about less than n=256), such crosspoint architectures implemented in CMOS technology are not practical, since they would occupy more chip area than a fully populated matrix with one or more RAM cells used to drive each switch in the matrix as described above. In addition, in the architecture described in the Shin et al. paper, the number of crosspoints is necessarily quadratic in the number of objects (i.e., I/O pins or logic cell inputs and outputs) being switched. This attribute of this architecture severely restricts the number of objects which may be interconnected using a single reasonably sized integrated circuit die.
Time/space switch programmable architectures, such as that disclosed in S. Carpenter et al., "A 146 Mb/s Time Space Switch Chip," 1988 IEEE ISSCC, pp. 112-113, are also known in the art. The number of RAM cells used in such architectures is at least twice the number of switches being used to pass or block data at any given time.
It is an object of the present invention to provide a user re-programmable interconnect architecture in which the active switching device and its associated active storage element occupy less die area than in previous re-programmable interconnect architectures.
It is a further object of the present invention to provide a user re-programmable interconnect architecture in which N switching elements may be controlled by fewer than N active storage elements.

Reprogrammable interconnect architecture using fewer storage cells than switches