A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.

1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to methods of testing an integrity of a material layer provided in a semiconductor structure.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, e.g., transistors, capacitors and resistors, formed on and in a substrate. These elements are connected internally by means of electrically conductive lines to form complex circuits, such as memory devices, logic devices and microprocessors. To accommodate all the electrically conductive lines required to connect the circuit elements in modern integrated circuits, the electrically conductive lines are arranged in a plurality of levels stacked on top of each other. To connect electrically conductive lines provided in different levels, contact vias are formed in dielectric layers separating the levels from each other. These vias are then filled with an electrically conductive material.
A method of forming an electrically conductive line according to the state of the art will now be described with reference to FIGS. 1a and 1b. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of the method of forming an electrically conductive line according to the state of the art. A semiconductor substrate 101 is provided. The semiconductor substrate 101 may comprise a plurality of circuit elements and, optionally, electrically conductive lines in lower interconnect levels. The semiconductor substrate 101 further comprises a first dielectric layer 102 formed thereon. A trench 107 is formed in the dielectric layer 102. A trench fill 111 comprising an electrically conductive material, e.g., a metal, such as copper, is provided in the trench 107. The trench fill 111 forms an electrically conductive line. A diffusion barrier layer 110 separates the trench fill 111 from the first dielectric layer 102. Thus, a diffusion of the material of the trench fill 111 into the first dielectric layer 102 can be prevented and adhesion between the trench fill 111 and the dielectric material of the first dielectric layer 102 can be improved. The semiconductor substrate 101 can be formed by means of methods known to persons skilled in the art comprising advanced techniques of deposition, oxidation, ion implantation, etching and photolithography.
An etch stop layer 103 is formed over the semiconductor substrate 101. In addition to the surface of the first dielectric layer 102, the etch stop layer 103 covers an exposed top surface of the trench fill 111. On the etch stop layer 103, a second dielectric layer 104 is formed. The second dielectric layer 104 may comprise the same material as the first dielectric layer 102. The etch stop layer 103 and the second dielectric layer 104 may be formed by means of methods known to persons skilled in the art, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and spin coating.
A trench 109 and a contact via 108 are formed in the second dielectric layer 104. This can be done by photolithographically forming a mask (not shown) which exposes a portion of the surface of the second dielectric layer 104 at the location where the contact via 108 is to be formed. Then, an etching process is performed. To this end, the semiconductor structure 100 is exposed to an etchant adapted to selectively remove the material of the second dielectric layer 104, leaving the etch stop layer 103 essentially intact. Thus, the etching process stops as soon as the etch front reaches the etch stop layer 103.
The etching process may be anisotropic. In anisotropic etching, a rate at which material is removed from the etched surface depends on the orientation of the surface. In an anisotropic etching process, the etch rate of substantially horizontal portions of the etched surface being substantially parallel to the surface of the semiconductor substrate 101 is significantly greater than the etch rate of inclined portions of the etched surface. Thus, substantially no material below the mask is removed and the via 108 obtains substantially vertical sidewalls. Thereafter, the mask is removed, which can be done by means of a resist strip process known to persons skilled in the art, and the trench 109 is formed. Similar to the formation of the contact via 108, the trench 109 can be formed by photolithographically forming a mask on the semiconductor structure 100 and performing an anisotropic etching process.
Subsequently, a portion of the etch stop layer 103 exposed at the bottom of the contact via 108 is removed. The exposed portion of the etch stop layer 103 may be removed by means of an etching process adapted to selectively remove the material of the etch stop layer 103, leaving the materials of the second dielectric layer 104 and the trench fill 111 substantially intact.
A diffusion barrier layer 105 is deposited on the semiconductor structure 100. In particular, the diffusion barrier layer 105 covers the sidewalls and the bottom of the trench 109 and the contact via 108. This can be done by means of known methods such as CVD, PECVD and/or sputter deposition. Then, a layer 106 of an electrically conductive material, e.g., copper, is formed on the diffusion barrier layer 105. To this end, methods of electroplating known to persons skilled in the art may be employed.
The diffusion barrier layer 105 may comprise materials such as titanium nitride, tantalum and/or tantalum nitride which may prevent a diffusion of the electrically conductive material of the layer 206 into the second dielectric layer 104 and other portions of the semiconductor structure 100. In particular, in methods of forming an electrically conductive line according to the state of the art wherein the electrically conductive material comprises copper, the diffusion barrier layer 105 may prevent a diffusion of copper into circuit elements such as field effect transistors formed in the semiconductor structure 100. This may help avoid adverse effects of the presence of copper on the functionality of the field effect transistors.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the method of forming an electrically conductive line according to the state of the art. The surface of the semiconductor structure 100 is planarized, for example, by means of a known chemical mechanical polishing (CMP) process. In the planarization, portions of the diffusion barrier layer 105 and the layer 106 outside the trench 109 and the contact via 108 are removed and a planar surface of the semiconductor structure 100 is obtained. Residues of the layer 106 in the trench 109 form an electrically conductive line. Residues of the layer 106 in the contact via 108 provide an electrical contact between the electrically conductive lines in the trench 109 and the trench 107.
A problem of the above-described method of forming an electrically conductive line according to the state of the art is that the diffusion barrier layer 105 may comprise one or more pores 112. During the formation of the layer 106 of electrically conductive material, the presence of the pore 112 may induce an insufficient filling of the contact via 108 with the electrically conductive material such that a void 113 is created in the layer 106.
If the semiconductor structure 100 is operated after the completion of the manufacturing process, the void 113 may increase the electrical resistance of the electrically conductive line formed in the contact via 108. Additionally, the presence of the void 113 may increase the likelihood of electromigration and/or stress migration occurring.
As persons skilled in the art know, the term "electromigration" denotes a current-induced transport of atoms in conductors. Electrons moving in an electrical field exchange momentum with the atoms. At high current densities, the momentum imparted to the atoms forms a net force which is high enough to propel atoms away from their sites in the crystal lattice. Thus, the atoms pile up in the direction of electron flow. The likelihood of electromigration is dependent, inter alia, on temperature, wherein moderately high temperatures increase the likelihood of electromigration occurring.
Moreover, undesirable material transport in semiconductor structures may be caused by mechanical stress which can be created, for example, due to different thermal expansion coefficients of materials present in the semiconductor structure 100. Such stress may relax via a diffusion of atoms in the electrically conductive line. The diffusion of atoms entails a transport of material. This phenomenon is denoted as "stress migration."
In the void 113, there is a surface of the material of the layer 106. At the surface, there is a greater likelihood of electromigration occurring than in other portions of the electrically conductive line in the contact via 108 and/or in the trench, since the material at the surface of the layer 106 is not confined by the barrier layer 108 and/or other elements of the semiconductor structure 100. In the course of time, electromigration and/or stress migration may negatively affect or even destroy the electrically conductive line formed in the contact via 108.
Therefore, it is desirable to develop methods of forming a diffusion barrier layer which eliminates or at least reduces the likelihood of the formation of pores. Methods which allow testing the integrity of a diffusion barrier layer are helpful for this purpose.
In the state of the art, it has been proposed to investigate a diffusion barrier layer by means of transmission electron microscopy. For this purpose, a sample comprising a thin section of a semiconductor structure similar to the semiconductor structure 100 described above is employed. A problem of this technique, however, is that the preparation of samples adapted for transmission electron microscopy, as well as transmission electron microscopy itself, are difficult to perform and are time-consuming. This may restrict the number of contact vias which can be investigated in an economically feasible manner, and may impose difficulties in implementing routine or in-line processes for testing the integrity of the diffusion barrier layer.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.

Method of testing an integrity of a material layer in a semiconductor structure


A method of registration in a telecommunications system by a mobile station, which system includes a home location register for maintaining subscriber data and supports a first network, such as GSM, and a second network, such as GPRS. The home location register maintains the mobile subscriber data and a message is sent to the home location register for requesting the mobile subscriber data. The home location register maintains an access parameter which indicates whether the mobile subscriber is entitled to use the first network, the second network or both networks. In response to said message for requesting the subscriber data, the home location register sends the mobile subscriber data and also the access parameter. The network element that requested the mobile subscriber data uses said access parameter for restricting the access of the mobile subscriber only to a circuit-switched network and/or to a packet-switched network.

The invention relates to reduction of signalling load when a multi-mode (e.g. GSM/GPRS) mobile station registers in a packet radio network, such as GPRS. The invention is described in connection with a dual-mode telecommunications system which supports two different networks. To clarify the description, it is assumed that the first network is a circuit-switched network (such as GSM) and the second network is a packet-switched network (such as GPRS). Instead of the GSM network, or in addition to it, derivatives of the GSM, such as DCS, may also be used.
A General Packet Radio Service (GPRS) is a new service in the GSM. It is one of the items that is being standardized in GSM phase 2+ in the ETSI (European Telecommunication Standard Institute). The GPRS operational environment consists of one or more sub-network service areas that are interconnected using a GPRS backbone network. A sub-network comprises a number of packet data service nodes, which are here called GPRS support nodes (or agents) and each one of which is connected to the GSM mobile network so that it can provide packet data service for mobile data terminals via several base stations, i.e. cells. An intermediate mobile network provides circuit-switched or packet-switched data transmission between a support node and the mobile data terminals. Different sub-networks, in turn, are connected to an external data network, for example to a Public Switched Packet Data Network PSPDN. The GPRS service can thus be used for effecting packet data transmission between mobile data terminals and external data networks, when the GSM network functions as an access network. One feature of the GPRS service network is that it operates almost independently of the GSM network. One of the requirements set for the GPRS service is that it must operate together with different types of external PSPDN networks, such as the Internet and X.25 networks. In other words, the GPRS service and the GSM network should be able to serve all users, irrespective of the type of data networks that they wish to be connected to via the GSM network. This means that the GSM network and GPRS service must support and process different network addressing methods and data packet formats. The data packet processing also comprises routing of the packets in a packet radio network. In addition, the users should be able to roam from their home GPRS network to a visited GPRS network.
FIG. 1 illustrates a typical arrangement in a GPRS network. It should be understood that the architecture of the GPRS networks is not as mature as that of the GSM networks. All GPRS terms should therefore be understood as being descriptive terms rather than limiting ones. A typical mobile station forming a mobile data terminal consists of a mobile station MS of a mobile network and of a portable computer PC connected to the data interface of the MS. The mobile station may be, for example, a Nokia 2110, manufactured by Nokia Mobile Phones Ltd., Finland. By means of a PCMCIA type Nokia Cellular Datacard, manufactured by Nokia Mobile Phones Ltd., the mobile station can be connected to any portable personal computer PC whatsoever that has a PCMCIA card slot. The PCMCIA card thus provides the PC with an access point that supports the protocol of the telecommunications application used in the PC, such as the CCITT X.25 or Internet Protocol IP. Alternatively, the mobile station can directly provide an access point that supports the protocol used by the PC application. Further, a mobile station 3 and a PC 4 can be integrated to form a single unit, within which the application is provided with an access point that supports the protocol used by it. An example for such a mobile station with an integrated computer is a Nokia Communicator 9000, manufactured by Nokia Mobile Phones Ltd., Finland.
Network elements BSC and MSC are previously known from a typical GSM network. The arrangement of FIG. 1 comprises a separate Serving GPRS Support Node SGSN. The support node controls certain operations of the packet radio service on the network side. The operations include the logging on and off the system by the mobile stations MS, updating of the routing areas of the mobile stations MS, and routing of the data packets to correct destinations. In the present application, the term 'data' should be understood in the wide sense to mean any information whatsoever transmitted in a digital telecommunications system. The information can comprise speech encoded into digital form, data communication between computers, telefax data, short segments of program code, etc. The SGSN node can be located at a base station BTS, at a base station controller BSC or at a mobile switching centre MSC, or it can be separate from all these elements. The interface between the SGSN node and the base station controller BSC is called a GB interface. An area managed by one base station controller BSC is called a Base Station Subsystem BSS.
The intermediate mobile network provides packet-switched data transmission between a support node and mobile data terminal equipment. Different sub-networks, in turn, are connected to an external data network, for example to a PSPDN, via specific Gateway GPRS Support Nodes GGSN. Packet data transmission between mobile data terminals and external data networks is thus effected by means of the GPRS service, while the GSM network functions as an access network. Alternatively, the gateway node GGSN can be replaced with a router. In the following, the term 'gateway node GGSN' is also to be understood as referring to a structure in which the gateway has been replaced with a router.
In FIG. 1 the GPRS network connected to the GSM network comprises a number of serving GPRS support nodes and one gateway GPRS support node GGSN. The different support nodes SGSN and GGSN are interconnected via an intra-operator backbone network. It is to be understood that a GPRS network may comprise any number of support nodes SGSN and gateway nodes GGSN.
Each support node SGSN manages a packet data service in the area of one or more nodes in a cellular packet radio network. To achieve this, each support node SGSN is connected to a certain local part of the GSM system, typically to a mobile services switching centre, but in some situations it may be preferable to connect it directly to a base station subsystem BSS, i.e. to a base station controller BSC or a base station BTS. A mobile station MS in a cell communicates with a base station BTS over a radio interface and further through a mobile network with the support node SGSN to the service area of which the cell belongs. In principle, the mobile network between the support node SGSN and the mobile station MS only transmits packets between these two. For this purpose, the mobile network can offer either a circuit-switched connection or packet-switched data packet transmission between a mobile station MS and a serving support node SGSN. An example for a circuit-switched connection between a mobile station MS and an agent is presented in WO 95/08900. An example for packet-switched data transmission between a mobile station MS and an agent is presented WO 95/20283. It should be noted, however, that a mobile network provides only a physical connection between a mobile station MS and a support node SGSN, and that its exact operation and structure are not relevant to the present invention.
An intra-operator backbone network 11 interconnecting the operator's SGSN and GGSN can be implemented, for example, using a local area network. It should be noted that it is also possible to implement the operator's GPRS network without an intra-operator backbone network, for example, by implementing all the features in a single computer, but this does not cause any changes in the call set-up principles according to the present invention.
A gateway GPRS node GGSN connects the operator's GPRS network to the other operators' GPRS networks and to data networks, such as an inter-operator backbone network 12 or an IP network. An Interworking Function IWF can be arranged between the gateway node GGSN and the other networks, but usually the GGSN is simultaneously the IWF. The inter-operator backbone network 12 is one through which the gateway nodes GGSN of different operators can communicate with one another. The communication is needed to support the GPRS roaming between the different GPRS networks.
The gateway node GGSN is also used for storing the location information of the GPRS mobile stations. The GGSN also routes mobile-terminated (MT) data packets. The GGSN also contains a database that associates the mobile station's network address, for example in an IP network or an X.25 network (or simultaneously in more than one network), and the mobile station identifier in a GPRS network. When the mobile station roams from one cell to another within the area of one support node SGSN, location updating is needed only in the support node SGSN, and the gateway node GGSN need not be informed of the change of location. When the mobile station roams from a cell of one support node SGSN to a cell of another SGSN within the area of the same or a different operator, location updating is also performed in the (home) gateway node GGSN so as to store the identifier of the new, visited support node and the identifier of the mobile station.
A home location register HLR is also used to authenticate subscribers at the beginning of a GPRS session. It contains a definition between a subscriber's PDP (Packet Data Protocol) address (addresses) and the subscriber's IMSI (International Mobile Subscriber Identity). In a GSM network a subscriber is identified on the basis of the IMSI. In FIG. 1 the HLR is connected through an SS7 (Signalling System 7), for example to a mobile switching centre MSC and an intra-operator backbone network. Between the SS7 signalling system and the intra-operator backbone network there can be a direct connection or an SS7 gateway. In principle, the HLR can exchange packet-switched messages with any GPRS node whatsoever. The HLR's method of communication and its connection to the GPRS network are not, however, essential to the invention.
In the above arrangement, packet-switched data (in short: packet data) can be transmitted to a mobile station over an air interface, when the mobile station, controlled by the network, has first been directed to a correct kind of channel, i.e. to a packet data transmission channel. A mobile station that supports packet data transmission can either be suited only to the transmission and reception of packet data ('GPRS only') or also to the transmission of conventional circuit-switched speech and other services ('multi-function terminal').
A 'GPRS only' mobile station can be in one of three different states in the sense of the present application: a ready, a standby, or an idle state. A mobile station in the ready state is connected to a data transmission channel and is ready to transmit and/or receive data packets. A mobile station is the standby state mode listens to a packet data paging channel, and after receiving its paging identifier the mobile station switches to the ready state. A mobile station in the idle state does not support transmission nor reception of packet data.
A multi-function terminal operates in the ready and standby states in the same way as the 'GPRS only' terminal, but in idle state it supports conventional circuit-switches services.
When packet data is sent to a mobile station, the data will be routed to the correct GSM network by routing it via the gateway node GGSN to the support node SGSN in which the location of the mobile station is known. If the mobile station is in the standby state, its location is known with the accuracy of a Routing Area RA. Correspondingly, if the mobile station is in the ready state, its location is known with the accuracy of a cell.
FIG. 2 illustrates registration of a mobile station in the system. FIG. 2 is taken from the ETSI specification GSM 03.60 (version 5.2.0). The previous support node SGSN and centre MSCNLR of the mobile station are called "the old ones" and their present counterparts are called "the new ones".
In step 2-1 the mobile station sends an ATTACH REQUEST message. Steps 2-2 to 2-5 are neither necessary nor essential to the invention, and thus they will not be described here. In step 2-6a the new SGSN sends an UPDATE LOCATION message to the home location register HLR, which in step 2-6b cancels the location (CANCEL LOCATION) from the old SGSN. In step 2-6c the old SGSN acknowledges (=ACK). In step 2-6d the new SGSN receives subscriber data from the home location register in a message INSERT SUBSCRIBER DATA and sends an acknowledgement in step 2-6e. In step 2-6f the new SGSN receives an acknowledgement to the update location message which was sent in step 2-6a.
In step 2-7a the new SGSN sends a LOCATION UPDATING REQUEST to the new centre MSCNLR. Steps 2-7b to 2-7g correspond to steps 2-6a to 2-6f. In step 2-7h the new SGSN receives an acknowledgement to the location updating request sent in step 2-7a from the new centre. In step 2-8 the new SGSN informs the mobile station of the fact that the attach request sent in step 2-1 has been accepted. The following steps are not essential to the invention, and thus they will not be explained more closely.
A problem related to the arrangement described above is that the GPRS side of the system has no subscriber-specific information on whether a certain subscriber has access to the service on the GSM side (MSC/VLR). When a mobile station PC/MS registers in the system, a combined GPRS/non-GPRS IMSI attach operation and possibly a location area/routing area (LA/RA) update to the visitor location register MSCNLR are carried out. This causes unnecessary signalling to the MSCNLR via the Gs interface and further to the home location register HLR via the MAP-D interface if the subscriber is only a GPRS subscriber.
A parallel problem arises when the GSM side of the system has no subscriber-specific information on whether a certain subscriber has access to the service on the GPRS side (SGSN). This causes unnecessary signalling if the VLR has lost the subscriber data. In the case of a mobile-terminating call, a page has to be always sent to each SGSN node since the MSCNLR does not know whether the subscriber has a GPRS service or not.


A momentary diagnostic for determining correct operation of a cam profile switching system of an internal combustion engine by calculation of changes in cylinder bank to bank air mass flow ratios: operating said engine in one condition of the cam profile switching system; providing for a first cylinder subset the inlet fuel flow and the corresponding oxygen content of the exhaust flow, and calculating the mass of air passing through the first cylinder subset in a defined time period; providing for a second cylinder subset the inlet fuel flow and the corresponding oxygen content of the exhaust flow; calculating the mass of air passing through the second cylinder subset in said defined time period; comparing the mass air flow the oxygen content for the first and second cylinder subsets to give a standard ratio; momentarily forcing the cam profile switching system of one of said cylinder subsets to an alternative condition; re-calculating providing the corresponding mass of air oxygen content passing through the first and second cylinder subsets; and comparing said recalculated air flows oxygen contents to give a revised ratio; and comparing said standard ratio and revised ratio.

Systems have been proposed for providing variation of camshaft condition, particularly for vehicles, so as to enhance the operating characteristics of the engine. In one example, a camshaft has dual profiles giving respective low and high inlet valve lift, and thus allowing a range of valve timing to enhance engine economy and performance. The relevant profile is selected, typically by a microprocessor based engine control unit (ECU), according to driver demand and other relevant parameters.
Many arrangements for switching cam profile have been proposed. One solution provides a dual tappet for each inlet valve. Each tappet operates on a low lift cam profile when engine is operated at low loads, but when engine is operating at high loads a high lift mode can be activated by a high pressure oil feed to engage a high lift cam profile, on demand.
The ECU controls other vehicle systems, particular systems for minimizing exhaust emissions, and for that purpose a diagnostic is required to confirm that the desired camshaft condition has been effected. In the example given above, it is not sufficient merely to monitor the presence or absence of a high pressure oil supply to a tappet, since the tappets themselves may malfunction.
It has accordingly been proposed to monitor the constituents of the engine exhaust, in particular the oxygen content, to confirm that the measured value lies within a range associated with the demanded camshaft condition. The ECU may for example include a look-up table giving the corresponding values for each camshaft condition by reference to fuelling and/or engine rpm.
U.S. Pat. No. 7,621,175 discloses a method of detecting degradation of a cam profile switching system in a Vee engine, which method compares the exhaust constituents of the two cylinder banks during a forced change of cam condition for one bank of the engine. If, for example, the oxygen concentration in the two exhaust streams is unchanged, it may be concluded that the cam profile switching system has degraded in the bank subjected to the forced change. Typically the alternative cam condition has not been adopted due to a malfunction in an electrical or hydraulic circuit.
In this arrangement, the forced change can be applied periodically to each bank, and for a short time during a suitable engine operating condition.
It would be advantageous to have an alternative diagnostic able to detect correct functioning of a varied camshaft condition.

Diagnostic for engine cam profile switching system


Hierarchical multiprocessors systems with common level expansion modules. The invention includes an architecture for such multiprocessor system. One facet of such multiprocessor system including a memory control system for minimizing duplicate read requests comprising: a plurality of processing systems; a bus connecting the processing systems; a memory for storing variables; circuitry operable for receiving read requests through the bus from other processing systems; a memory for queuing incoming read requests, wherein the memory for queuing incoming read requests is connected to the circuitry operable for receiving read requests; a memory for queuing outgoing read requests, wherein the memory for queuing outgoing read requests is connected to bus and the memory for storing variables; and circuitry for comparing the incoming read requests to the queued read requests, wherein the circuitry ignores duplicates of a first read request prior to the first read request leaving the memory for queuing outgoing read requests.

1. Field of the Invention
The present invention relates to electronic computers, and, more particularly, to control in multiprocessor systems.
2. Description of the Related Art
Attempts to understand the functioning of the human brain have led to various "neural network" models in which large numbers of simple computing elements ("neurons") are interconnected (by "synapses") to form a connectionist machine. As with all connectionist machines, neural networks use fine-grained parallelism to perform complex functions at very high speed. This high effective computing bandwidth can be applied to compute-bound problems such as finite-element analysis, image processing, adaptive signal processing, constrained optimization, associative memory, and artifical intelligence.
Neural network models roughly presume each neuron can exist in one of two states (quiescent and firing) with the state determined by the states of directly-connected neurons (e.g., if enough directly-connected neurons are firing, then the original neuron should switch to or be in the firing state). The models may be simple feedforward layered structures with an input layer of neurons, one or more hidden layers of neurons, and an output layer of neurons. Other models have feedback among the neurons and correspondingly more involved behavior.
The structure of any neural network can be defined by directed graphs as illustrated in FIG. 1. The vertices of the graph represent the computing elements and have associated parameters, and the edges of the graph define the communication paths among the computing elements and also have associated paramenters. Also, input and output paths connected to each vertex are shown. A vertex and its associated parameters define a neuron (labelled N.sub.j) and an edge with its associated parameters define a synapse (labelled S.sub.ij for the path from N.sub.j to N.sub.i) between neurons. The synapses are not just communication paths, but also modify the signals propagated between neurons. If we assume that a synapse value of zero (e.g., S.sub.ij =0) corresponds to an absence of connection between neurons (e.g., from N.sub.j to N.sub.i), then any neural network configuration may be represented more generally by a complete graph of N neurons together with N.sup.2 synapses. Most neural networks do in fact have on the order of N.sup.2 connectivity, so the number of parameters required to define a network state increases as a power of the size of the model.
The output of a neuron is a function of its internal state plus the inputs it receives from its synaptic connections. Each neuron is defined to receive an external input, serve as an external output, or be externally inacessible (hidden). Neurons need not operate synchronously, have uniform connectivity, nor obey the same rules for change of state. The state of a neuron by a simple numerical value or by more complex data structures.
For example, J. Hopfield, Neural Networks and Physical Systems with Emergent Collective Computational Abilities, 79 Proc. Natl. Acad. Sci. USA 2554 (1982) describes a neural network model with N neurons each of which has the value 0 or 1 (corresponding to the quiescent state or to the firing state, respectively), so the state of the network is then an N-component vector V=[V.sub.1, V.sub.2, . . . , V.sub.N ] of 0's and 1's which depends upon time. The neuron interconnections are described by a matrix S.sub.i,j defining the influence of the j.sup.th neuron on the i.sup.th neuron. The state of the network evolves in time as follows: each neuron i has a fixed threshold .theta..sub.i and readjusts its state V.sub.i randomly in time by setting V.sub.i equal to 0 or 1 depending on whether ##EQU1## is negative or positive. All neurons have the same average rate of readjustment, and the readjustments define a dynamical flow in state space.
With the assumption that S.sub.i,j is symmetric, the potential function ##EQU2## can be used to show that the flow of the network is to local minima of the potential function. Further, with a given set of uncorrelated N-component vectors U.sup.1, U.sup.2, . . . , U.sup.8, a S.sub.i,j can be defined by ##EQU3## and with the thresholds equal to 0, these U.sup.k are the fixed points of the flow and thus stable states of the network. This is a type of "outer product storage" of the vectors U.sup.1, U.sup.2, . . . , U.sup.8. Such a network can act as a content-addressable memory as follows: the memories to be stored in the network are used to construct the U.sup.k and hence S.sub.i,j, so the stored memories are fixed points of the flow. Then a given partial memory is input by using it to define the initial state of the network, and the state will flow usually to the closest fixed point/stable state U.sup.k which is then the memory recalled upon input of the partial memory.
Further analysis and modified network models appear in, for example, J. Hopfield et al, Computing with Neural Circuits: A Model, 233 Science 625 (1986) and J. Hopfield, Neurons with Graded Response Have Collective Computational Properties like Those of Two-State Neurons, 81 Proc. Natl. Acad. Sci. USA 3088 (1984).
Synapses are usually modified by a recursive algorithm that depends upon the local response of the network to a set of external inputs. After this "training" phase, the network can be used to perform a function by presenting certain neurons with input data and then allowing the network to evolve as previously described. Most algorithms allow very high internal parallelism during the "compute" phase and reach a near steady state in just a few propagation delays of information through the network.
For example, J. Anderson, Cognitive Capabilities of a Parallel System, NATO Advanced Research Workshop (Mar. 3, 1985) describes the Brain State in a Box (BSB) neural network model which includes outer-product storage, Widrow-Hoff learning, and a ramped-threshold recall algorithm. That is, the matrix of interconnection strengths, S.sub.i,j, is modified to learn a new vector V.sub.j by ##EQU4## where .eta. is a learning constant and N is number of neurons. The learning constant is roughly the inverse of the number of times the matrix must be trained on a given vector before it fully learns the vector. The smaller the learning constant, the finer the resolution of the average direction for a learned state but the more times the input vectors must be trained. The learning procedure saturates when .DELTA.S.sub.i,j is close to zero, which implies that the vector is close to being an eigenvector of the matrix with an eigenvalue near 1.
Recall of a learned (stored) vector given an input vector U.sub.j is by the following iterative process that converges towards an eigenvector: ##EQU5## where the "Limit" function clamps the values in the range from -1 to 1. The constants .gamma. and .beta. measure the feedback and signal decay in the algorithm. This synchronous recall algorithm replaces the dynamical flow of the Hopfield model. The usual applications of the BSB neural network such as data bases with words and letters encoded as their ASCII representations require binary neurons as in the first Hopfield model.
A problem with neural networks is the lack of efficient nonbiological hardware. Further, the simulation of neural networks with standard digital computers demands extreme computing power. For example, consider a neural network composed of 256 by 256 fully interconnected neurons (large enough to assign one neuron to each pixel in a low-resolution video camera image) would contain over four billion synaptic connections. A real-time simulation of the processing of a single video frame by this network would require a minimum computing rate of over 250 billion synapse operations per second. And the number of parameters needed to define a neural network tends to grow as a power of the network size, and the communication cost in parallel processor computers overwhelms the computer.

Multiprocessor system and architecture with a computation system for minimizing duplicate read requests


A method of halftoning a sample value from an intensity range including the steps of providing threshold arrays having threshold values from distinct ranges, one of which is the same as the intensity range, selecting the one with the same range as the intensity range and using the selected threshold array to halftone the sample value. Embodiments may include the following features. The threshold arrays are a first one having a first threshold value range and a second one having a second threshold value range that has more levels than does the first threshold value range. The first threshold array is built by scaling each value in the second threshold array down to the range of the first threshold array. The scaling is done by dividing by 257 and rounding up to the next whole number. The first threshold array has a threshold value range of zero to 255 and the second threshold array has a threshold value range of zero to 65535 or zero to 4095. Tone correction is performed using a transfer function mapping an 8-bit input sample value to a tone-corrected output sample value having more than 8 bits.

The invention relates to the use of halftone threshold arrays on digital output devices, and more particularly to threshold arrays for increased levels per color component.
A continuous tone image does not print well on most printing devices, so the image is usually printed as pattern of dots based on a grid. The grid generally consists of an array of halftone cells, each of which represents one section of continuous tone in the original image. When reproducing a halftoned image using a digital recording device, a halftone cell consists of a number of device pixels. In a device that produces only black and white pixels, some of the display pixels of each halftone cell are turned black to form dots that are relatively larger or smaller to represent darker or lighter portions of the original continuous tone image. In a dark halftone cell, most of the pixels are black, while in a light halftone cell, most of the pixels are white. A complete grid of the original image is composed of many such halftone cells, each of which has an independent density of displayed pixels and therefore a different apparent darkness when viewed from a distance.
A conventional method of selecting which dots to turn black works as follows. For a given halftone cell, the original image is sampled at each display pixel location in the halftone cell to obtain a sample value. This sample value is represented digitally as a number in a fixed range, typically zero to 255. The sample value is then compared to a threshold value at the display pixel location and the display pixel is turned white if the sample value is greater than the threshold value, and black otherwise. The threshold values, in turn, are supplied by a threshold array, which provides a threshold value for each pixel in the halftone cell. This process is carried out for each halftone cell of the image.
The term threshold array is commonly used to denote a set of generic pixels, each of which has a "threshold value". The device plane is tiled with copies of the threshold array, so that each device pixel is mapped to one generic pixel and its threshold value. After the desired sample value for the device pixel is computed--from the image being halftoned, for example--it is compared to the threshold value. If the sample level is greater than the threshold value, the device pixel is left white; otherwise, it is marked black.
A threshold array is much like a sampled image: it is generally a rectangular array of pixel values defined entirely in device space. It can be built algorithmically, by use of a spot function, for example, or it can be built by hand. The sample values occupy some number of bits: in a typical system, the sample values occupy 8 bits that represent gray levels ranging from zero for black and 255 for white.
The scheme generalizes to monochrome devices with multiple bits per pixel. For example, with 2 bits per device pixel, each device pixel can directly represent one of four different gray sample levels. For each device pixel that is to be painted with some in-between gray level, the corresponding pixel of the threshold array is consulted to determine whether to use next-lower or next-higher directly-representable gray level. In this situation, the samples of the threshold array do not represent absolute gray values, but rather gradations between two adjacent representable gray levels.
Halftoning is also used to approximate continuous-tone colors by a pattern of pixels that can achieve only a limited number of discrete colors. The input to the halftone function includes continuous-tone color components in the device's native color space. The output includes pixels representing colors the device can reproduce. Some devices can reproduce continuous-tone colors directly. These are known as "contone" devices. For such devices, halftoning is not required and color components can be transmitted directly to the marking engine of the device.
A halftone defined in this way can also be used with color output devices whose pixels consist of component colors that are either completely on or completely off. Most color printers, but not color displays, work this way. Halftoning is applied to each color component independently, producing shades of that color. The red, green, and blue values, for example, are created independently as gray levels, and a threshold array is applied to each color.
Further information on halftoning may be found in U.S. Pat. Nos. 5,285,291 and 5,305,118, as well as in such standard reference works as Foley, van Dam et al., Computer Graphics, Addison-Wesley (2d ed. 1992), pp. 568-573, and Adobe Systems Incorporated, Adobe PostScript.RTM. Language Reference Manual, Addison-Wesley (2d ed. .COPYRGT.1990), pp. 309-319.

Device for injecting high energy laser beam into optical fiber


A method is provided for limiting double-frequency internal power distortion in a power system. The method includes receiving an input voltage from a voltage source at a power converter from which an output power is provided to an electrical load, measuring the output power having a waveform with a steady-state component and a double-frequency transient component, executing computer-readable program code, via processing circuitry, to determine a compensating waveform equal in amplitude to the double-frequency transient component, and that is anti-phase to the double-frequency transient component, and causing the power converter to generate the compensating waveform such that the waveform and the compensating waveform superpose, and the double-frequency transient component of the waveform and the compensating waveform destructively interfere, leaving the steady-state component that is delivered to the electrical load.

Single-phase power converters routinely experience strong double-frequency internal power flows. These power flows may induce extra losses and component stress, so suppressing these power flows would be highly desirable. Load power under single-phase conditions typically contains a steady (DC) component and a fluctuating double-frequency (AC) component. With many loads, a simple DC plus 2-f model fully characterizes the energy flow. However, this disclosure may further be applied to the average plus harmonic frequency component of more complex loads.
In a traditional single-phase inverter design lacking double-frequency ripple power suppression, the DC voltage level of the intermediate storage device (typically a capacitor) may be controlled to an average level that supports AC voltage modulation of the inverter. In such a design, some fraction of the double-frequency ripple power component may flow to the DC energy source.
The voltage of the intermediate DC device may be controlled to a useful level. In the simplest approach, that average voltage may be controlled to be a constant value. Then, double-frequency ripple power may be transmitted to the DC voltage source. This induces added losses and component stress at that source. A preferable alternative would draw energy from the source as a steady flow without ripple.
In traditional approaches, the double-frequency ripple power flows may be cancelled by circuit-based methods. Such methods involve physical construction of additional external circuit components which exchange energy to compensate the power ripple. This approach can be inflexible and add extra components during manufacturing. In other traditional approaches, a power converter may be controlled to suppress the double-frequency ripple power component at the DC source by controlling the output current injected into the grid to cancel the source ripple. This disclosure, in contrast, presents a ripple-power suppression technique that is entirely internal to the power generating device, having no consequences to any external connections.

Suppressing double-frequency ripple power in single-phase power converters


An electrostatic discharge protection circuit for an integrated circuit and a method for electrostatic discharge protection thereof are disclosed. The integrated circuit includes a power source, a ground, a signal input, and a signal output. The integrated circuit further comprises one or more essentially identically configured electrostatic discharge protection circuits, configured to provide electrostatic discharge protection between any two of the power source, the ground, the signal input, and the signal output. A method of providing electrostatic discharge protection includes providing one or more essentially identically configured electrostatic discharge protection circuits coupled between and providing electrostatic discharge protection for any two of the power source, the ground, the signal input, and the signal output. The disclosed integrated circuit and method provide advantages of simplifying the integrated circuit design and reducing design time.

Protection against electrostatic discharge (ESD) is very important for integrated circuits (ICs), and a lot of researches have been carried out in this area of IC design. ESD may occur in the normal use, transportation and storage of electronics, and during the assembly and manufacturing of IC components. ESD occurs in unpredictable ways, and may lead to damages, defects and even total losses of the IC. In contemporary IC design and fabrication, special attention needs to be paid for the design of ESD protection circuits.
In current integrated circuits design, different ESD protection circuits are usually arranged respectively between a power supply and a signal input, between the signal input terminal and the ground, between the power supply and a signal output, and between the signal output and the ground to provide ESD protection. However, with integrated circuits becoming more and more powerful, more than one power supply domains often co-exist within a single integrated circuit. Accordingly, in order to achieve ESD protection, such an integrated circuit with multiple power supply domains will require more diversified ESD protection circuits. As a result, a lot of time needs to be consumed for the design of ESD protection circuits in integrated circuits. In view of this, it is desirable to design a novel low-voltage ESD protection circuit, integrated circuit and method of ESD protection thereof to resolve the above issues.

Low-voltage electrostatic discharge (ESD) protection circuit, integrated circuit and method for ESD protection thereof


A battery holder for attachment to a printed circuit board includes a base, a positive conductor, a negative conductor and a top. The base is to be fixed to the printed circuit board and the two conductors are fixed to the base. The top includes a window for viewing the polarity of the battery and is selectively attached to the base by a series of latches.

All devices that use batteries require at least one battery holder. The battery holder is the structure or system that holds the battery in a fixed position and provides an electrical connection between the battery and the device.
Existing battery holders are not necessarily concerned with saving space and may be large and bulky. In the context of a printed circuit board, space is very limited and minimizing both area and height are very important.
Additionally, existing battery holders completely enclose the battery. Thus, in order to ascertain the polarity of the battery, one must either open the battery holder or remove the battery from the battery holder. This is problematic when working with printed circuit boards that require different polarities for different applications.
U.S. Pat. No. 6,062,901 issued to Jia-Hung Liu et al. on May 16, 2000 discloses a button battery holder for application to a printed circuit board. The holder comprises a closed bottom, side walls and positive and negative terminals. At least one of the side walls includes an access opening. The two terminals are secured to the holder and extend through corresponding slits in the bottom of the holder. The holder of Liu et al does not provide a minimal height and does not provide visual access to the polarity of the battery.

Battery holder for printed circuit board


A magnetic circuit for coaxial speaker includes a first magnetic unit, at least one second magnetic unit arranged around the first magnetic unit and at least one third magnetic unit arranged around the at least one second magnetic unit. The magnetic pole arrangement of the second magnetic unit is reversed to the magnetic pole arrangement of the first magnetic unit and the third magnetic unit, enabling a first magnetic loop to be established between the first magnetic unit and the at least one second magnetic unit and a second magnetic loop to be established between the at least one second magnetic unit and the at least one third magnetic unit. The magnetic circuit is practical for use in the inner and outer drivers of a coaxial speaker, providing uniform magnetic field distribution, and facilitating speaker miniaturization.

1. Field of the Invention
The present invention relates to a magnetic circuit for use in a coaxial speaker, and more particularly, to a magnetic circuit that shares a common magnetic loop and is capable of providing a uniform magnetic field distribution, improving the voice coil driving efficiency and effectively reducing the overall size of the speaker.
2. Description of the Related Art
With increasing competitiveness in today's electronic product market, is becoming more competitive, every manufacturer requirements on the specifications of speaker for electronic products have become more critical than ever. Not only hope the speaker size to be more compact size to fit thin electronic product design, but also want the speaker to provide a wide range of audio output. It is therefore often necessary to install a second driver, promoting the creation of coaxial speaker.
Various coaxial speakers are known. For example, a conventional coaxial speaker 80 as shown in FIG. 1, which comprises a low range driver 81 and a mid-high range driver 82. The low range driver 81 and the mid-high range driver 82 respectively comprise an independent diaphragm 83 and an independent magnetic circuit 84. The mid-high range driver 82 is coaxially mounted in the center of an accommodation area within low range driver 81. However, because the two drivers are respectively disposed at different elevations and have different sizes, the overall thickness of this design of coaxial speaker 80 is greatly increased. Obviously, this design of coaxial speaker does not meet the requirements of the electronic market. Further, the magnetic lines of force of the magnet are emitted from the N pole to pass through the two opposite lateral sides of the magnet to the S pole thereof. However, a regular magnetic circuit simply uses the magnetic field at one lateral side of the magnet, as shown in FIG. 2, and a severe magnetic flux leakage can occur at the opposite lateral side. Therefore, an improvement in this regard is necessary.

Magnetic circuit and coaxial speaker using the same


A vehicle body frame structure for a two-wheeler provides a sufficient distance between exhaust pipes and a front wheel, to facilitate the arrangement of a heat-discharging member such as a radiator or an oil cooler, or other auxiliary components, to increase heat-discharging property by increasing the capacity of the heat-discharging member, and improving flexibility in design such as the shape or the layout of the vehicle body frame and the exhaust pipes. In a two-wheel vehicle having an engine mounted to a vehicle body frame, the engine having exhaust pipes extending forwardly and downwardly and a pair of left and right down tubes extending substantially downwardly from a head pipe provided at the front end of the vehicle body frame, the vehicle body frame includes a first cross member for connecting the left and right down tubes, and the first cross member is formed with arcuate recesses for allowing part of the exhaust pipes to pass therethrough.

1. Field of the Invention
The present invention relates to a vehicle body frame structure for a two-wheeler.
2. Description of Background Art
In the related art, a vehicle body frame structure for a two-wheeler is known wherein an exhaust pipe, provided at the front of an engine, is located in the vicinity of the vehicle body frame. See, for example, Japanese Patent No. 3,370,888.
Referring now to FIG. 15 attached hereto which corresponds to FIG. 1 in Japanese Patent No. 3,370,888 the following description is provided. Note, that the latter half of the drawing is omitted, and the components are renumbered.
FIG. 15 is a side view of a vehicle body frame structure for a two-wheeler in the related art, showing a pair of left and right down pipes 302, 302 (only the reference numeral 302 designating the nearer one is shown in the drawing) extending substantially downwardly from the head pipe 301 and provided at the front end of the vehicle body frame. A plurality of exhaust pipes 304 extend downwardly from the front of an internal combustion engine 303 so as to curve therefrom. A front wheel 306 is mounted to the head pipe 301 via a front fork 307.
The above-described down pipe 302 requires a great rigidity for supporting the weight of the internal combustion engine 303 and suppressing vibrations of the internal combustion engine 303. Thus, a structure of connecting the left and right down pipes 302, 302 with a cross pipe is employed. When the left and right down pipes 302, 302 are connected with the cross pipe, it is necessary to pay attention to interference between the cross pipe and the exhaust pipes 304. When an attempt is made to secure a clearance between the cross pipe and the exhaust pipes 304 disposed in front of the cross pipe, the distance between the exhaust pipes 304 and the front wheel 306 is reduced.
In addition, for example, it is difficult to dispose a heat-discharging member such as a radiator, an oil cooler, or other auxiliary components between the front wheel 306 and the exhaust pipes 304. More specifically, a large sized auxiliary component cannot be disposed therebetween. In particular, in the case of the internal combustion engine 303 having an in-line four-cylinder engine and thus requiring a large lateral width, since the distance between the left and right down pipes 302, 302 increases, a greater rigidity is required. However, since it is also necessary to take the interference with the plurality of exhaust pipes 304 into consideration, the vehicle body frame and the exhaust pipes 304 are further restrained in flexibility in design relating to their shapes and locations.
A vehicle body frame structure for a two-wheeler employing pipe members is known. For example, see Japanese Patent No. 3194288 (P. 2–3, FIG. 1)
Referring to FIG. 28 shown below which corresponds to FIG. 1 of Japanese Patent No. 3194288 will be described. The components are renumbered.
FIG. 28 is a perspective view showing a vehicle body frame structure for a two-wheel vehicle in the related art, showing that a vehicle body frame 1300 includes a pair of left and right top tubes 1302, 1302 extending rearward from a head pipe 1301 and curving downward, and a pair of left and right down tubes 1304, 1304 extend downwardly from the head pipe 1301 and curve rearward.
The down tubes 1304 are formed of a round pipe member.
In a two-wheeler, one of the portions which limits an angle of inclination of the vehicle body, that is, a bank angle, is the above-described down tubes 1304 which are located at the lower portion of the vehicle body.
Therefore, for example, the positions of the down tubes 1304, 1304 may be moved upwardly or inwardly as a considerable countermeasure. However, since there is an engine inside the vehicle body frame 1300, the above-described movement is difficult. Though it is also possible to eliminate the down tubes 1304, the strength of the vehicle body frame will decrease.

Vehicle body frame structure of two-wheeler


A remover solution composition for resist which comprises (a) a salt of hydrofluoric acid with a metal-free base, (b) a water-soluble organic solvent, and (c) water and optionally (d) an anticorrosive, and has a pH or 5 to 8. A method for removing resist which comprises the steps of (I) forming a resist layer on a substrate having a metal film, (II) light-exposing the resist layer through a mask pattern and subsequently developing the resist layer to form a resist pattern, and (III) dry-etching the substrate using the resist pattern as a mask and then removing the unnecessary resist and modified resist film with the remover solution composition.

Semiconductor elements such as IC's and LSI's and liquid-crystal panel elements are produced by evenly applying a photoresist to an electroconductive film of a metal, e.g., aluminum, copper, or an aluminum alloy, formed on a substrate or to an insulating film, e.g., SiO.sub.2 film, formed on a substrate, light-exposing the resist layer or drawing an image thereon with an electron beam, subsequently developing the resist layer to form a resist pattern, selectively etching the electroconductive metal film or insulating film using the pattern as a mask to form a fine circuit, and then removing the unnecessary resist layer with a remover solution.
Conventionally used resist remover solutions for removing resist include organic sulfonic acid-based remover solutions containing an alkylbenzenesulfonic acid as an essential component and organic amine-based remover solutions containing an organic amine, e.g., monoethanolacine, as an essential component. However, the organic sulfonic acid-based remover solutions have a drawback that since they contain a highly toxic organic solvent, such as a phenol compound or chlorobenzene, not only use of the remover solutions results in poor working efficiency and poses an environmental problem, but also the remover solutions are apt to corrode electroconductive metal films on substrates and the like. In contrast, the organic amine-based remover solutions are less toxic than the organic sulfonic acid-based remover solutions, do not require a troublesome wastewater treatment of the organic sulfonic acid-based remover solutions, are effective in removing modified films resulting from treatments such as dry etching, ashing, ion implantation, and the like, and are highly inhibited from corroding substrates having provided thereon Al, Cu, and the like. Because of these advantages, the organic amine-based remover solutions are currently used extensively.
However, as a result of the recent trend toward severer conditions for treatments such as dry etching, ashing, ion implantation, and the like in processes for producing semiconductor elements or liquid-crystal panel elements, these treatments have come to modify originally organic resist films to films having inorganic properties. The modified films cannot be sufficiently removed even with organic amine-based remover solutions. Another drawback of organic amine-based remover solutions is that since they are used at a relatively high temperature of 60 to 130.degree. C., there is a danger that the flammable organic compounds contained therein volatilize and catch fire. Consequently, the removing treatment is generally performed in an inflammation-preventive apparatus, and requires much equipment cost. In addition, since this prior art removing treatment using the organic amine-based remover solution takes much time, the remover solutions becomes unsatisfactory for use in the production of semiconductor elements and liquid-crystal panel elements in which a high throughput (the number of wafers treated per unit time) is required. Remover solutions usable at a low temperature (room temperature) are disclosed in JP-A-64-88548 and JP-A-5-259066 (the term "JP-A" as used herein means an "unexamined published Japanese patent application"); however, both of them contain an organic amine and water and hence has drawbacks of insufficient removing performance and a strong tendency to corrode substrates.
Under these circumstances, the present: inventors proposed in JP-A-8-202052 a remover solution composition for resist which is free from the above drawbacks and comprises hydrofluoric acid optionally containing ammonium fluoride, i.e., so-called buffered hydrofluoric acid, a water-soluble organic solvent, and an anticorrosive. However, since the above remover solution composition for resist contains hydrofluoric acid, it is not quite safe for the human body and is difficult to handle. Furthermore, since the above composition is acidic, it is apt to corrode peripheral devices including remover solution feed facilities which connect a removing tank to a remover container. Other drawbacks of the above composition include the necessity of troublesome treatments of exhaust and wastewater of the remover solution composition for resist.

Remover solution composition for resist and method for removing resist using the same


Methods, software and a system for providing an efficient layout of digital content are presented. A plurality of digital content is received and rendered in a plurality of layouts. Each of the plurality of layouts comprises the plurality of digital content arranged in a plurality of cells within the layout. The white space area is calculated a white space area for each of the plurality of layouts. The white space area comprises a cumulative area calculated from an area within each of the cells not contained by the respective digital content. A layout is selected, from the plurality of layouts, for rendering within a layout region, based on the white space area.

Conventional computerized devices, such as personal computers, laptop computers, and the like utilize graphical user interface in applications such as operating systems and graphical editors (i.e., web page editors, document editors, etc.) that enable users to quickly provide input and create projects using "What You See Is What You Get" (WYSIWYG) technology. In general, using a graphical user interface, a user operates an input device such as a mouse or keyboard to manipulate digital content on a computer display. The digital content is often represented as icons, and the user can operate an input device such as a mouse to move a mouse pointer onto an icon (i.e. graphically overlapping the icon on the graphical user interface). By depressing a mouse button, the application (such as the operating system desktop) selects the icon, and if the user maintains the mouse button in a depressed state, the user can drag the icon across the graphical user interface. By releasing the mouse button, the icon is placed on the graphical user interface at the current position of the mouse pointer.
Using graphical user interface technology, users can create projects by dragging and dropping digital content (i.e., graphical objects, text, text boxes, images, etc) into the project. Projects such as a storyboard, magazine, catalog, etc., may have individual sections of the projects that each have a layout. For example, a project designer specifies a layout of each of the individual pages that comprise the pages of a catalog. The layout is, essentially, the placement of each of the digital content within the individual page of the catalog. Typically, layout tools provide a preview feature that dissects the layout region into a grid of evenly sized cells, allowing the project designer to place the digital content within each of the cells in the layout. Each of the digital content is resized proportionally to fit into the respective cell. The remaining portion of the cell not filled by the proportionally resized digital content is called white space area.

Methods and apparatus for efficient layout of digital content


A system and process for displaying and redisplaying an HTML document that conforms to the limitations of a viewer's browser. The system comprises a browser, a script, and a document object model (DOM). The script comprises a data structure and an interpretation code. The DOM is a document model representing a Web page's elements, such as text, images, URL links, etc. The process includes using the script to create a document data structure that describes the essential information in the document and using the interpretation code to interpret the data structure in a fashion that allows it to manipulate the DOM for the purpose of rendering the document in the browser. The data structure can be modified and the corresponding HTML can be subsequently regenerated in response to user events so that after initially being created, the document can be updated to reflect changes to the viewer's browser. if the viewer resizes the browser, the page elements can be automatically resized.

1. Technical Field
The invention relates generally to the Internet communication technology. More particularly, the invention relates to a system and method for delivering and rendering scalable Web pages.
2. Background of the Invention
Authors of World Wide Web (WWW) documents all share a common and frustrating problem: the viewers of their documents have highly diverse viewing environments—especially with regard to the physical dimensions of the window a document is displayed in. This is problematic, especially if authors desire to produce documents with specific layout requirements. Hypertext Markup Language (HTML), the document format for WWW, provides very little in the way of scalable page elements. Many elements, text in particular, are fixed at specific sizes. When viewed on browsers with a large display resolution, text appears quite small when compared to displays with low resolution. Furthermore, even those elements that support some form of scaling are difficult to control because of the rudimentary manner in which the scaling support is provided. All this makes development of a consistent layout for WWW documents rather difficult.
One way for a document author to combat this problem is through the use of dynamic scripting languages such as JavaScript. These languages provide a way to detect information about a viewer's environment and modify the document accordingly. Unfortunately, the native document object code (DOM) provided by these languages is rather problematic. In the case of Netscape Navigator 4, not all of the page elements are accessible. Many elements are "write-only" or "read-only", making it impossible to use the native structure as a reliable place to store document information.
Conversely, Internet Explorer (4 & 5) has a DOM that can be, at times, overly complex, making it difficult to constrain the degree to which a document should be modified.
Adding to the WWW author's problem is the fact that the DOMs used by Netscape Navigator and Internet Explorer are dramatically different in nature. Supporting both browsers requires the development of different scripts that can interact with the individual DOMs.
What is desired is to develop a browser independent document data structure which enable page authors to freely access and modify all relevant aspects of the document without having to worry about limitations of the browser DOMs.

System and process for delivering and rendering scalable web pages

AOL LLC, a Delaware limited liability company


P-chiral bisphospholane ligands and methods for their preparation are described. Use of metal/P-chiral bisphospholane complexes to catalyze asymmetric transformation reactions to provide high enantiomeric excesses of formed compounds is also described.

There is a growing trend in the pharmaceutical industry to market chiral drugs in enantiomerically pure form in order to provide desired positive effects in humans. Production of enantiomerically pure compounds is important for several reasons. First, one enantiomer often provides a desired biological function through interactions with natural binding sites, but another enantiomer typically does not have the same function or effect. Further, it is possible that one enantiomer has harmful side effects, while another enantiomer provides a desired positive biological activity. To meet this demand for chiral drugs, many approaches for obtaining enantiomerically pure compounds have been explored such as diastereomeric resolution, structural modification of naturally occurring chiral compounds, asymmetric catalysis using synthetic chiral catalysts and enzymes, and the separation of enantiomers using simulated moving bed (SMB) technology.
Asymmetric catalysis is often the most efficient method because a small amount of a chiral catalyst can be used to produce a large quantity of a chiral target molecule. Over the last two decades, more than a half-dozen commercial industrial processes have been developed that use asymmetric catalysis as the key step in the production of enantiomerically pure compounds with a tremendous effort focused on developing new asymmetric catalysts for these reactions (Morrison J. D., ed. Asymmetric Synthesis, Academic Press: New York, 1985:(5); Bosnich B., ed. Asymmetric Catalysis, Martinus Nijhoff Publishers: Dordrecht, Netherlands, 1986; Brunner H., Synthesis, 1988:645; Scheffold R., ed. Modern Synthetic Methods, Springer-Verlag: Berlin Hedelberg, 1989;115(5); Nugent W. A., RajanBabu T. V., Burk M. J., Science, 1993;259:479; Ojima I., ed. Catalytic Asymmetric Synthesis, VCH: New York, 1993; Noyori R., Asymmetric Catalysis In Organic Synthesis, New York: John Wiley & Sons, Inc., 1994).
Chiral phosphine ligands have played a significant role in the development of novel transition metal catalyzed asymmetric reactions to produce enantiomeric excess of compounds with desired activities. The first successful attempts at asymmetric hydrogenation of enamide substrates were accomplished in the late 1970's using chiral bisphosphines as transition metal ligands (Vineyard B. D., Knowles W. S., Sabacky M. J., Bachman G. L., Weinkauff D. J., J. Am. Chem. Soc., 1977;99(18):5946–5952; Knowles W. S., Sabacky M. J., Vineyard B. D., Weinkauff D. J., J. Am. Chem. Soc., 1975;97(9):2567–2568).
Since these first published reports, there has been an explosion of research geared toward the synthesis of new chiral bisphosphine ligands for asymmetric hydrogenations and other chiral catalytic transformations (Ojima I., ed. Catalytic Asymmetric Synthesis, VCH Publishers, Inc., 1993; Ager D. J., ed. Handbook of Chiral Chemicals, Marcel Dekker, Inc., 1999). Highly selective rigid chiral phospholane ligands have been used to facilitate these asymmetric reactions. For example, phospholane ligands are used in the asymmetric hydrogenation of enamide substrates and other chiral catalytic transformations.
BPE, Duphos, and BisP ligands are some of the most efficient and broadly useful ligands developed for asymmetric hydrogenation to date. Burk M. J., Chemtracts 11(11), 787–802 (CODEN: CHEMFW ISSN:1431-9268. CAN 130:38423; AN 1998:698087 CAPLUS) 1998; Burk M. J., Bienewald F., Harris M., Zanotti-Gerosa A., Angew. Chem., Int. ed., 1998;37(13/14):1931–1933; Burk M. J., Casy G. Johnson N. B., J. Org. Chem., 1998;63(18):6084–6085; Burk M. J., Kalberg C. S., Pizzano A., J. Am. Chem. Soc., 1998;120(18):4345–4353; Burk M. J., Harper T. G. P., Kalberg C. S., J. Am. Chem. Soc., 1995;117(15):4423–4424; Burk M. J., Feaster J. E., Nugent W. A., Harlow R. L., J. Am. Chem. Soc., 1993;115(22):10125–10138; Nugent W. A., RajanBabu T. V., Burk M. J., Science (Washington, D.C., 1883-) 1993;259(5094):479–483; Burk M. J., Feaster J. E., Harlow R. L., Tetrahedron: Asymmetry, 1991;2(7):569–92; Burk M. J., J. Am. Chem. Soc., 1991;113(22):8518–8519; Imamoto T., Watanabe J., Wada Y., Masuda H., Yamada H., Tsuruta H., Matsukawa S., Yamaguchi K., J. Am. Chem. Soc., 1998;120(7):1635–1636; Zhu G., Cao P., Jiang Q., Zhang X., J. Am. Chem. Soc., 1997; 19(7):1799–1800. For example, a Rhodium/Duphos complex can be used to selectively form (S)-(+)-3-(aminomethyl)-5-methylhexanoic acid, known as pregabalin, which is used as an anti-seizure drug. The S-enantiomer, which is produced in an enantiomeric excess, is preferred because it shows better anticonvulsant activity than the R-enantiomer. Yuen et al., Bioorganic & Medicinal Chemistry Letters, 1994;4:823.
The success of BPE, DuPhos, and BisP transition metal complexes in asymmetric hydrogenations is derived from many factors. For example, substrate to catalyst ratios of up to 50,000/1 have been demonstrated. Also, high rates of substrate conversion to product using low hydrogen pressures have been observed with catalysts made from these ligands.
BPE, Duphos, and BisP have shown high enantioselectivities in numerous asymmetric reactions. Improved reaction of BPE, Duphos, and BisP is attributed to, among other factors, rigidity in their C2-symmetric structure. If the spatial area of a metal/phosphine ligand structure, such as BPE, is divided into four quadrants, as shown in Scheme 1, alternating hindered and unhindered quadrants are formed.

This structural feature creates areas of hindrance in the metal complexes and produces desired stereochemical results in asymmetric hydrogenation reactions. However, there are a variety of reactions, such as catalysis of simple olefins, in which these ligands are not very efficient in terms of activity and selectivity.
Further, there are many characteristics associated with these ligands, which may limit their application. For example, the chiral center of these ligands is not directly bonded to the metal center. This may reduce the effectiveness of enantioselectivity in asymmetric reactions because the chirality of the ligands helps direct the stereochemistry during the reaction of a target molecule with the metal/chiral ligand complex. Therefore, bonding a chiral atom closer to the metal center may increase the formation of enantiomeric excesses. Also, bulky substituents in the unhindered regions may limit the availability and reactivity of the metal center to the target molecule.
Improved chiral phosphine ligands are needed that can further improve the production of enantiomerically active forms of compounds through asymmetric catalysis. Thus, there is a need to develop methods for the production of and to synthesize compounds that bond a chiral phosphine atom directly to a metal center and remove prohibitive substituents from the ligand to improve enantioselectivity in asymmetric reactions.

Synthesis of P-chiral bisphospholane ligands and their transition metal complexes for use as asymmetric hydrogenation catalysts


A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

1. Field of the Invention
The present invention relates generally to computer systems having multiple processors with caches. In particular, the present invention relates to a system and method for implementing cache tags in a memory for maintaining cache coherence.
2. Description of the Background Art
The use of multiple processors is a recent trend in computer design. Each processor may work on a separate portion of a problem, or work on different problems, simultaneously. The processors used in the multi-processor architectures generally each have cache. A cache is a relatively small group, when compared to shared memories, of high speed memory cells that are specifically dedicated to a processor. A processor's cache is usually on the processor chip itself or may be on separate chips.
Processors use caches to hold data that the processor has recently accessed. A memory access is any action, such as a read or a write, where a processor receives, modifies, or receives as well as modifies the contents of a memory location. Generally, a processor can access data in its cache faster than it can access data in the main memory of the computer. Furthermore, by using data in its cache, a processor does not use the bus of the computer system to access data. This leaves the bus free for use by other processors and devices.
A particular problem associated with the use of caches is that the data becomes "stale." A first processor may access data in the main memory and copy the data into its cache. The first processor may then modify the data in its cache. At the instant when the data in the cache of the first processor is modified, the corresponding data in the memory is stale. If a second processor subsequently accesses the original data in the main memory, the second processor does not find the most current version of the data. The most current version is in the cache of the first processor. The second processor, however, needs the most current version of the data. A prior art solution to this problem is for processors to eavesdrop on the bus. When the first processor detects the main memory access by the second processor for data that the first processor holds in its cache, the first processor inhibits the main memory and supplies the data to the second processor. In this way, a processor always receives the most current version of the data.
This prior art solution suffers from a number of problems. Computer architectures are moving to multiple-processor, multiple-bus configurations. The busses are coupled through an interface. For efficiency purposes, many signals on a bus are not transmitted across the interface to other busses. Among signals, which are not transmitted across the interface, are memory access signals where the path between source and target devices does not cross the interface. Many other devices also do not transmit all signals that they receive. For example, cross-bar switches, which concurrently connect multiple pairs of source and target ports, limit the transmission of memory access signals to the data path between source and target. When devices do not transmit all memory access signals over its data path, it is impossible for processors, which are not the source and target, to eavesdrop on memory accesses and therefore, impossible to determine when the data is stale. Thus, this prior art solution is not effective in systems that use devices that do not transmit all memory access signals.
Decreases in access time of main memories and increases in the size of caches have created other problems with eavesdropping. Eavesdropping on the bus assumes that a processor can inhibit the main memory and place the data on the bus faster than the main memory can access the data. Memories may, however, cache copies of recently accessed data within themselves; in which case, they often can provide data before a processor can inhibit the memory. Also, caches have become larger. Generally, larger memories, whether main memories or caches, require more time to access. Processors, with large caches, cannot access the larger cache fast enough to make the prior art solution workable unless other memory access are delayed while eavesdropping is performed. Such a delay would significantly degrade the performance of the processor.
Memory tags have been used to overcome some of these problems. A memory tag is associated with a memory address whose data is held in a cache. When a processor copies the data at that address into its cache, a memory tag is updated to identify the processor in whose cache the data is held. If a second processor attempts to access the data in the memory, the processor will receive the memory tag. Memory tags remove the need for eavesdropping. The memory tags are held in a separate memory device called a tag storage. When a processor reads or writes data to a memory address, both the tag storage and the memory address are accessed. The memory address is accessed for the data, and the tag storage is accessed for the possibility of a memory tag. If the accesses are performed sequentially, two accesses greatly slow the operation of the memory. If done in parallel, the tag storage greatly complicates the design of the memory controller. The width of the tag storage differs from the width of the main memory, in one embodiment the tag storage is 20 bits wide and the main memory is 64 bits wide. The different sized memories require complicated modifications to the memory controller. Furthermore, the tag storage requires changes in the bus width and requires additional circuit chips that occupy space, consume power, and add to the expense of the computer system.
Referring now to FIG. 1, a block diagram of a prior art memory 23 is shown. The prior art memory 23 comprises a data storage 40, a tag storage 42, and a memory controller 25. The data storage 40 comprises a plurality of memory lines. Each memory line comprises one or more words and has an unique address. A first memory line 44 has address 0, and a second memory line 46 has address 1. Each address indicates a complete memory line. The remaining memory lines of the data storage 40 are addressed similarly so that a last memory line 48 has address N-1, where N is the total number of memory lines in the data storage 40. Each word has a fixed bit size. A word may be any number of bits long, but currently is preferably 64 bits long or other powers of 2. A memory line 44, 46, 48 may include any number of words, but within the data storage 40 each memory line 44, 46, 48 has the same number of words. The tag storage 42 comprises a tag cell for each memory line of the data storage 40. Each tag cell has an address that corresponds to a memory line of the data storage 40. A tag cell 50 has an address 0 and corresponds to the first memory line 44. Similarly, a tag cell 52 has an address 1 and corresponds to a second memory line 46, and a tag cell 54 has address N-1 and corresponds to a final memory line 48. Each tag cell 50, 52, 54 is more than one bit wide and contains data that indicates if the data held in the corresponding memory line 44, 46, 48 is valid data or if a processor holds the data. Data is valid, or "fresh," if no processor holds the data in its cache. Fresh data may also be referred to as "unowned" data. Data is referred to in this application as "owned" and is not fresh if a processor holds a copy of the data in its cache. If a processor owns the data, the tag cell 50, 52, 54 contains an indicator for indicating that the data is owned and a tag that identifies the processor that owns the data.
Any memory operation that requires the data held at an address is referred to as an access. The basic operations are ReadOwned and WriteReturn. ReadOwned and WriteReturn will be discussed in detail below. Other operations may also be performed. The processor that is executing an operation is referred to as the accessing processor. Every memory access requires an operation on the addressed memory line 44, 46, 48 and the assigned tag cell 50, 52, 54. This is true whether the memory access is a ReadOwned or a WriteReturn. If the access is a ReadOwned, the data storage 40 must be read, and the tag storage 42 must be read to determine if the data is fresh. If the memory access is a WriteReturn, the appropriate address must be written to and the assigned tag cell 50, 52, 54 must be set to indicate fresh data.
The memory controller 25 is a state machine for controlling the operation of the memory 23. The memory controller 25 is coupled to processors and other devices of a computer system by a bus 31. Data, control, and address signals are transmitted to the memory 23 on the bus 31. The memory controller is coupled to the data storage 40 by a line 27 and is coupled to the tag storage 42 by a line 29. In this application, a line refers to one or more wires. When the memory controller 25 receives a memory access signal, it must perform an operation on both the data storage 40 and the tag storage 42. For example, if the memory controller 25 receives a ReadOwned command on the bus 31 for a memory location in the data storage 40, the memory controller 25 first asserts a signal on line 27 for the data storage 40 to transmit the contents of the first memory line 44 to the memory controller 25. For purposes of this example, it will be assumed that the memory address was 0 for the first memory line 44. The data storage transmits the data on line 27. The memory controller 25 simultaneously asserts a signal on line 29 for the tag storage 42 to transmit the contents of tag cell 50 to the memory controller 25. The memory controller 25 determines if the data, received from the tag storage 42, indicates that the data contained in memory line 44 is owned. If the data contained in memory line 44 is unowned, the memory controller outputs the data onto the bus 31. If the data is owned, the memory controller 25 outputs the tag contained in the tag cell 50. Other memory accesses such as WriteReturn also require an operation on both the data storage 40 and the tag storage 42. This prior art memory 23 is slow and requires more complicated memory controller lines 27, 29.
As can be seen from the above example, there is a continuing need for a faster system and method for ensuring that processors receive fresh data and for identifying processors holding cached data. This system and method should not require modifications to other devices of a computer system.

System for an method of efficiently controlling memory accesses in a multiprocessor computer system