The present invention relates to a method and apparatus for efficiently configuring information during a process in which a terminal records channel measurement information in a mobile communication system. Disclosed is an operation of a terminal for accurately indicating to a base station whether or not a serving cell or neighbor cells are measured in configuring channel measurement information. In addition, disclosed is a method in which a terminal adjusts the frequency of recording in consideration of the importance of the measured information.

Field of the Invention
The present invention relates to a method and apparatus for configuring information efficiently in logging channel measurement information in a mobile communication system. In more particular, the present invention discloses a terminal operation of indicating to a base station whether the measurement has been performed to a serving cell or neighbor cells for configuration of the channel measurement information. Also, the present invention proposes a method for a terminal to adjust the frequency of log in consideration of the importance of the measurement information.
Description of the Related Art
Typically, the mobile communication system has been developed for the user to communicate on the move. With the rapid advance of technologies, the mobile communication system has evolved to the level capable of providing high speed data communication service as well as voice communication service. Recently, the 3GPP, as one of the next generation mobile communication standardization organizations, is in the progress of standardization of Long Term Evolution-Advanced (LTE-A). LTE-A is one of the high speed packet-based communication technologies supporting data rate higher than that of the current mobile communication technology under the objective to complete the standardization in late 2010.
With the evolvement of the 3GPP standard, many discussions are being conducted for optimizing the radio network in addition to the effort for increasing data rate. In the initial radio network configuration or optimization stage, a base station or a base station controller should collect radio environment information related to its own cell coverage, and this process is called Drive Test. Since the conventional drive test is performed in such a way that an operator carries the test apparatuses on a vehicle while performing the measurement task repeatedly for long time. The measurement result is used to configure the system parameters of the base stations or base station controllers. Such a conventional drive test increases total costs and time of the radio network optimization and maintenance. Study on minimization of drive tests and enhancement of radio environment analysis process and manual configuration is being conducted in the name of MDT (Minimization of Drive Test). In order to accomplish the aforementioned purposes, the UE measures radio channels and reports the radio channel measurement information to the eNB periodically at an interval or immediately in response to a specific event or after a predetermined time has elapsed from the time point when the radio channel measurement information has been recorded, instead of performing the drive test. In the following description, the process for the UE to transmit the radio channel measurement information and other supplementary information to the eNB is called MDT measurement information report. In this case, the UE reports the channel measurement result immediately right after the completion of channel measurement in a state where the communication is available with the eNB but deters the report in a state where the communication is not available with the eNB until the connection to the eNB is recovered. The eNB uses the MDT measurement information received from the UE for cell coverage optimization. In LTE-A, basic MDT measurement information report operations are classified according to the UE RRC state as shown in table 1.
TABLE 1UE MDT measurement UE RRC stateinformation report operationIdle modeLogging and deferred reportingConnected modeImmediate reportConnected modeLogging and deferred report
Table 1 shows the basic MDT information report operation depending on the RRC state of the UE.
In table 1, if the UE is not communicating with the eNB, the UE is in the idle mode and, otherwise, in connected mode. In the case of MDT, the channel information measured by the UE is supposed to be transmitted through RRC signaling such that, although the UE is in the idle mode, it is not necessary to transition to the connected mode for information transmission. In this case, the UE logs the channel measurement information and defers the transmission of the information until it transitions to the connected mode.
Although if necessary it is possible to transmit the channel measurement information to the eNB immediately even in the connected mode, the UE can defer the transmission of the measurement information logged in the idle mode until it transitions to the connected mode. The eNB requests for the measurement information report such that the corresponding UE transmits the logged measurement information.
The UE in the idle mode logs channel measurement information periodically or when a certain event triggering channel measurement information log occurs. The exemplary channel measurement information log-triggering events are as follows.
(1) Periodic downlink pilot measurement
(2) Serving Cell becomes worse than threshold
(3) Transmit power headroom becomes less than less than threshold
(4) Paging Channel Failure
(5) Broadcast Channel failure
(6) Random access failure
(7) Radio link failure report
It is expected that the MDT measurement and log information configuration method is defined by taking notice of the conventional RRC measurement method. However, unlike the conventional RRC measurement method perform with the assumption of the existence of a serving cell, the MDT measurement is performed regardless of the existence of serving cell. This is because since the MDT measurement information is supposed to be used for cell area optimization other than supporting mobility the UE has to measure the signals from the adjacent eNBs even in service coverage hole. In the RRC measurement procedure, the measurement result report includes the serving measurement result and neighbor cell measurement results. If this operation mechanism is applied to the MDT measurement report without modification, it may fail logging the serving cell measurement information in a certain case, resulting in confusion. There is therefore a need to define a detailed operation for this.
The convention RRC measurement method is provided with an algorithm for limiting the cell measurement range in order to minimize the power consumption of the UE in the idle mode. The RRC measurement aims to check the signal qualities of the neighbor cells as well as the serving cell in order for the UE to attach to the best cell. If the condition of the serving cell lower than a predetermined threshold and a neighbor cell has the better signal quality, the UE attempts access to the corresponding cell. If the signal quality of the serving cells is equal to or higher than the threshold, there is no need of checking the signal condition of neighbor cells consuming UE power unnecessarily. Accordingly, if the signal strength of the serving cells is equal to or greater than a predetermined threshold, no neighbor cell signal measurement is performed in the RRC measurement method. The UE selects the neighbor cell for measurement in stepwise manner using two threshold values of Sintrasearch and Snonintrasearch.
FIG. 1 shows a UE measurement operation in the idle mode according to two threshold values. If the Reference Signal Received Power (RSRP) 115 of the serving cell is greater than Sintrasearch 105, the UE does not measure the signals of neighbor cells. This is because the current serving cells has the signal quality good enough. Otherwise, if the RSRP of the serving cell is equal to or less than Sintrasearch 105 and greater than Snonintrasearch 110, the UE measures the signals of the neighbor cells operating on the same frequency of the serving cell. if the RSRB of the serving cell is less than Snonintrasearch 110, the UE measures the signals of cells operating on other frequencies and other systems.
The MDT measurement method is likely to be designed to operate in similar manner to the RRC measurement method and employ the two threshold values of Sintrasearch and Snonintrasearch, as they were, to reduce power consumption of the UE. However, since the MDT measurement is focused on the cell area optimization other than mobility support, there is no need of knowing why there is no measurement result of the neighbor cells in the log unlike the conventional RRC measurement. This means that there is a need of the information indicating the reason of the absence of measurement result, i.e. whether the measurement result is absent due to the signal strength of the serving cell which is good enough or the measurement to the neighbor cells is not performed actually.
Meanwhile, the location information is one of the important elements in MDT measurement. It fails to receive GPS-based location information, the UE measures a set of the received signal strengths from neighbor eNBs and sends the measurement result to the serving eNB. The eNB calculates an approximate measurement location using the triangulation with the received signal strength set received form the UE. If the RSRP of the serving cell is greater than Sintrasearch, there is no chance to measure the neighbor cells and thus it is impossible to measure and log a set of the signal strengths of the neighbor cells for use in location information acquisition. At this time, since the MDT measurement without location information degrades the usability, it is not preferred to perform logging periodically and thus increase the UE and signaling overheads.

Method and apparatus for recording channel measurement information in a mobile communication system


A method and apparatus of controlling an uplink transmit power are provided. A maximum power reduction (MPR) is determined based on resource allocation. The resource allocation comprises a number of contiguous resource blocks in a channel bandwidth which is divided into a first region, a second region and a third region. The MPR is determined according to the number of the contiguous resource blocks in the first region and the third region, and the MPR is determined according to the starting index in the second region. The MPR in the third region increases as the number of the contiguous resource blocks decreases.

1. Field of the Invention
The present invention relates to wireless communication and, more particularly, to an apparatus and method for controlling an uplink transmit power in a wireless communication system.
2. Related Art
Wireless communication systems are widely spread all over the world to provide various types of communication services such as voice or data. In general, the wireless communication system is a multiple access system capable of supporting communication with multiple users by sharing available system resources (e.g., bandwidth, transmit (Tx) power, etc.). Examples of the multiple access system include a code division multiple access (CDMA) system, a frequency division multiple access (FDMA) system, a time division multiple access (TDMA) system, an orthogonal frequency division multiple access (OFDMA) system, a single carrier frequency division multiple access (SC-FDMA) system, etc.
The proliferation of wireless communication systems has created system interoperability problems, degrades efficiency of spectrum utilization, and increases the cost of communication services. Spurious emissions are emissions which are caused by unwanted transmitter effects such as harmonics emission, parasitic emissions, intermodulation products and frequency conversion products. The spurious emissions may cause interference between adjacent frequency bands.
3rd generation partnership project (3GPP) long term evolution (LTE) is a part of an evolved-universal mobile telecommunications system (E-UMTS). The evolved-UMTS Terrestrial Radio Access (E-UTRA) is the air interface of 3GPP LTE. E-UTRA employs the OFDMA in downlink and employs the SC-FDMA in uplink. E-UTRA supports various frequency bands. Some E-UTRA band may be adjacent to other system's frequency band. In the adjacent E-UTRA band, the spurious emissions by a transmitter may cause interference with the other system's frequency band.
A public safety band (PSB) is a regulated spectrum exclusively to public safety. The PSB may be defined in a 700 MHz or 4.9 GHz band. Police departments, fire departments, emergency medical services and other emergency responders may rely on point-to-point and point-to-multipoint communications systems operating in the PSB. The integrity and reliability of many of these public service networks are critical in emergencies.
When an E-UTRA band is adjacent to the PSB, the interference due to the spurious emissions may be caused. To guarantee the reliability of the PSB, a transmit power needs to be adjusted by taking into account for the spurious emissions.


A voltage regulator circuit has a first amplifier stage with input and output terminals, a feedback terminal, a pole-inducing transistor, and a compensating network coupled to the output terminal. A second amplifier stage has an input coupled to the first amplifier output, first and second current mirrors, and a pass transistor.

Low drop-out (LDO) voltage regulators are implemented in a variety of circuit applications to provide regulated power supplies. Increased regulator performance is especially being demanded in mobile battery-operated products such as cellular phones, pagers, camcorders, and laptop computers. For these products, regulators having a high power supply rejection ratio (PSRR) to yield low noise and ripple are needed. Regulators of this type are preferentially fabricated in standard low-cost CMOS processes, making them difficult to realize with the required performance characteristics.
A journal publication entitled "A Low-Noise High PSRR, Low Quiescent Current, Low Drop-out Regulator" by Hafid Amrani et al. states that regulators with high PSRR require a first stage amplifier with a large gain-bandwidth product. The gain-bandwidth product of an amplifier is the product of the amplifier's dc gain and its cutoff frequency, which for LDO applications is typically 1 MHz or lower. The required first stage amplifier performance can be achieved by a large dc gain, or by a high cutoff frequency.
A first journal publication entitled "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator" by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using a current efficient buffer and a current boosted pass device to realize a low quiescent current LDO regulator for low voltage operation.
A second journal publication entitled "Optimized Frequency Shaping Circuit Topologies for LDOS" by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using pole-zero doublet generation to increase the bandwidth for dynamic load regulation.
A third journal publication entitled "Active Capacitor Multiplier in Miller-Compensated Circuits" by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using Miller capacitor multipliers to reduce the silicon area consumed by a voltage regulator.
The main drawbacks of these proposed methods are:
1. The current efficient buffer circuit requires NPN bipolar transistors to avoid creation of a parasitic pole at the output of an error amplifier within the circuit.
2. The structure based on the pole-zero doublet can be stabilized if the dc open-loop gain is relatively small (e.g., 50 dB for a high current load). However, since the dc value of the PSRR is proportional to the inverse of the open-loop gain of the regulator, the dc value of the PSRR for this design cannot exceed 50 dB.
3. The Miller compensation method creates an internal pole. To make the cutoff frequency of the PSRR as high as possible, the pole of the first stage has to be as high as possible. Thus, the PSRR performance of this circuit structure is compromised. The noise performance of the regulator is also reduced.
With reference to FIG. 1, a low drop-out (LDO) regulator circuit 100 as known in the prior art comprises a first amplifier stage 110 and a second amplifier stage 120. The first amplifier stage 110 includes PMOS transistors P112, P116, and P118, diode-connected NMOS transistor N116 and NMOS transistor N118. The second amplifier stage 120 includes diode-connected PMOS transistors P122 and P126, PMOS transistor P124, diode-connected NMOS transistor N124 and NMOS transistors N122 and N126. The second amplifier stage 120 further includes PMOS power transistor P128. Resistive divider circuit comprising a resistor R1 and a resistor R2 is coupled to an output controlled voltage node VOUT. The ratio of the resistor R1 to the resistor R2 controls a proportion of the potential on the output controlled voltage node VOUT which is fed back to the first amplifier stage. By varying the resistor R1 and the resistor R2, the output voltage of the regulator circuit 100 can be programmed. A current load IL is coupled to the output controlled voltage node VOUT, representing an electrical load being powered by the regulator circuit 100 and requiring a consistent operating voltage. An external decoupling capacitance CL with an associated equivalent series resistance (ESR) RS is connected in parallel with the current load IL. Skilled artisans will recognize that a plurality of applications exist, such as the operation of microprocessor circuits, mixed signal circuits, memory circuits, and others, which can replace the generic current load IL attached to the regulator circuit 100 in practical use.
An analysis of the regulator circuit 100 operation now follows the assumptions and methods in the cited journal publications. A low-valued equivalent series resistance (ESR) RS is assumed for the external decoupling capacitance CL, which improves the transient ripple of the regulator. A zero introduced by the external decoupling capacitance CL and the equivalent series resistance (ESR) RS into the system transfer function is therefore at a higher frequency than the unity gain frequency (UGF) of the open-loop, and does not alter the stability of the regulator circuit 100.
As described in the journal article by Hafid Amrani et al., a dominant pole p1 of the regulator response is determined by the external decoupling capacitance CL as:
                              p          1                =                                            gd                              P                                                                                128                                      +                          (                              1                                                      R                                                                                1                                    +                                      R                                                                                2                                                              )                                            2                        Π                                                                                C              L                                                          (        1        )
In formula (1), gdP128 represents the output admittance of PMOS power transistor P128. The output admittance gdP128 can be expressed as a function of the current load IL and a channel modulation parameter, λ, of PMOS power transistor P128:gdP128=λ*IL  (2)
For a current load IL that is much larger than
      (                  1                  R                                                              1          *          R                                                              2                    *              1        λ              )    ,the pole frequency can be approximated as:
                              p          1                ≈                              λ            *                          I              L                                            2                        Π                                                                                C              L                                                          (        3        )
For a typical CMOS process, λ is of the order of 0.1 V−1 and typical low-noise regulator applications employ a resistive divider such that (R1+R2) is of the order of 100 kΩ. Under these conditions, formula (3) is valid for load currents which are large in comparison with approximately 100 μA. Thus, for a current load IL of 1 mA or more, the dominant pole of the open-loop transfer function increases with increasing current.
The dc gain, GDC, of the open-loop transfer function of the regulator circuit 100 can be expressed as:
                                                                        G                DC                            =                                                                    gm                                          P                                                                                118                                                                                gd                                              P                                                                                118                                                              +                                          gd                                              N                                                                                118                                                                                *                                                                            k                      1                                        *                                          k                      2                                                        a                                *                                                      gm                                          N                                                                                122                                                                                gd                                              P                                                                                128                                                              +                                          1                                                                        R                                                                                1                                                +                                                  R                                                                                2                                                                                *                                                      R                                                                                2                                                                              R                                                                                1                                        +                                          R                                                                                2                                                                                with                                            :                                                                        (        4        )                                          gm                      N                                                                          122                          =                              2            *                          K              n                        *                                                            I                  L                                *                a                                                              k                  1                                *                                  k                  2                                                      *                                          W                                  N                                                                                122                                                            L                                  N                                                                                122                                                                                (        5        )
In formulae (4) and (5), gm represents the transconductance of the associated subscripted transistor name, e.g., gmP118 represents the transconductance of PMOS transistor P118. Analogously, gd represents the output admittance of the associated subscripted transistor name, e.g., gdP118 represents the output admittance of PMOS transistor P118. The parameters k1 and k2 represent width ratios of current mirror transistors, such that k1=WP124/WP122 and k2=WN126/WN124, where W indicates the channel width of the associated subscripted transistor name.
The variable L in formula (5) represents the channel length of the associated subscripted transistor name, i.e., LN122 is the channel length of the NMOS transistor N122. The parameter Kn in formula (5) is the transconductance parameter for the NMOS transistors, and can be further represented as Kn=μn*Cox, where μn is the carrier mobility for electrons and Cox is the capacitance per unit area of the gate oxide. The parameter α is a fraction of the current load IL flowing in PMOS transistor P126. It is also equal to a width ratio of the diode-connected PMOS transistor P126 and the PMOS power transistor P128. Both the diode-connected PMOS transistor P126 and the PMOS power transistor P128 are designed with the same channel length to facilitate current matching, i.e., LP126=LP128 and α=WP126/WP128.
Using the approximation given by formula (3), and combining formulae (2) and (5) into (4) gives GDC as a decreasing function of IL:
                              G          DC                =                                            gm                              P                                                                                118                                                                    gd                                  P                                                                                118                                            +                              gd                                  N                                                                                118                                                              *                                                    2                *                Kn                *                                                                            k                      1                                        *                                          k                      2                                                        a                                            λ                                *                                    R                                                                                2                                                      R                                                                                1                            +                              R                                                                                2                                              *                      1                                          I                L                                                                        (        6        )
A second pole p2 is introduced into the regulator open-loop response as a result of the large output impedance of the first amplifier stage 110 and an input capacitance CN122, associated with the second amplifier stage 120. The second pole p2 value can be expressed as:
                              p          2                =                                            gd                              P                                                                                118                                      +                          gd                              N                                                                                118                                                          2                        Π                                                                                C                              N                                                                                122                                                                        (        7        )
The capacitance CN122 is determined by the gate-to-source capacitance and Miller gate-to-drain capacitance of the NMOS transistor N122 according to:
                              C                      N                                                                          122                          =                                                                              Cgs                                      N                                                                                122                                                  +                                                      Cgd                                          N                                                                                122                                                        *                                                                                k                                                                                1                      *                      k                                                                                2                                        a                                    *                                                            K                      n                                                              K                      p                                                        *                                                            W                                              N                                                                                122                                                                                W                                              P                                                                                128                                                                              *                                                            L                                              P                                                                                128                                                                                L                                              N                                                                                122                                                                                (        8        )
In formula (8) Kp=μp*Cox is the transconductance parameter for PMOS transistors, μp is the carrier mobility for holes, and Cox is the capacitance per unit area of the gate oxide. CgsN122 is the gate-to-source capacitance for NMOS transistor N122 and CgdN122 is the gate-to-drain capacitance for NMOS transistor N122.
Formula (8) shows that CN122, and thus p2, are not a function of current load IL, whereas the dominant pole p1 and the dc gain GDC depend upon IL. In standard CMOS processes, pole p2 is typically at a frequency lower than 100 kHz, and therefore below the unity gain frequency. This makes the system transfer function second order and unstable. As previously mentioned, and discussed in the journal article by Hafid Amrani et al., to maintain adequate power supply rejection ratio (PSRR) performance, the regulator circuit 100 configures the first amplifier stage 110 with high dc gain. For maximum stability, the pole P2 is preferably as high in frequency as possible. The approach employed in the regulator circuit 100 is to add a zero in the feedback loop to stabilize the system. The zero is implemented by means of zero stabilizing resistor R115 and zero stabilizing capacitor C115 at the output of the first amplifier stage 110. The resistor R115 and the capacitor C115 series configuration create a pole-zero doublet (pc, zc) in the open-loop transfer function. The zero zc is placed after the unity gain frequency (UGF) such that the open-loop gain crosses the 0 dB axis with a −20 dB per decade slope. The zero stabilizing capacitor C115 is chosen to have a low value to reduce the frequency of the pole p2 of the first amplifier stage 110 according to:
                              p                                                              2                =                              1                          2                            Π                                *                      1                                                                                C                                          N                                                                                122                                                        +                                      C                                                                                115                                                                                gd                                          P                                                                                118                                                        +                                      gd                                          N                                                                                118                                                                                +                              R                                                                                115                *                C                                                                                115                                                                        (        9        )
The pole-zero doublet (pc, zc) can be expressed as:
                    zc        =                  1                      2                        Π                                                                          C                                                                          115            *            R                                                                          115                                              (        10        )                                pc        =                  zc                                (                          1              +                                                                    C                                                                                115                                                        C                                          N                                                                                122                                                                      *                                  [                                      1                    +                                                                  (                                                                              gd                                                          P                                                                                118                                                                                +                                                      gd                                                          N                                                                                118                                                                                )                                            *                      R                                                                                115                                                        ]                                                      )                                              (        11        )
Like pole p2, pc and zc are independent of the current load IL. Comparison of formulae (9), (10), and (11) shows that p2<zc<pc. Therefore, the regulator is stable regardless of the value of the current load IL. The system transfer function becomes locally a first order transfer function.
In addition to the discussions supra, the first journal publication by Gabriel A. Rincon-Mora and Phillip E. Allen explains that a third pole p3 is realized by the gate node of the PMOS output transistor P128. By application of a boost technique described in the first publication, pole p3 can easily be increased in frequency beyond the unity-gain frequency (UGF) of the open-loop system such that pole p3 does not alter system stability. To apply the boost technique in the regulator circuit 100 a fraction of the current load IL is sourced into the bulk terminal (not shown) of the diode-connected PMOS transistor P126. Typically, the current fraction is between 1/1000 and 1/100. By sourcing current into the bulk terminal of the diode-connected PMOS transistor P126, the threshold voltage of the diode-connected PMOS transistor P126 and the PMOS power transistor P128 is effectively lowered, producing an increase in the conductance of PMOS power transistor P128 and an increase in the associated pole p3 frequency. Additionally, the current mirrors of ratio k1 and k2 are implemented to reduce the current in the NMOS transistor N122. Reduction of the current in the NMOS transistor N122 enables the W/L ratio WN122/LN122 to be reduced, thereby reducing the CN122 capacitance. Reference to formula (7), supra, shows that reduction in the CN122 capacitance raises the pole p2 frequency. The higher pole p2 frequency enables zc to be increased in frequency, permitting a reduction in zero stabilizing resistor R115 and zero stabilizing capacitor C115 values.
The architecture of the regulator circuit 100 results in the gate node of PMOS power transistor P128 acting as a low impedance net due to the action of the diode-connected PMOS transistor P126 according to the relation:
                              gm                      P                                                                          126                          =                  a          *                                    2              *              Kp              *                              I                L                            *                                                W                                      P                                                                                128                                                                    L                                      P                                                                                128                                                                                (        12        )
The boost technique consists of increasing α, thereby increasing gmP126. The third pole value can be expressed as a function of current load IL:
                              p                                                              3                =                              1                          2                            Π                                *          a          *                                                    2                *                Kp                *                                                      W                                          P                                                                                128                                                                            L                                          P                                                                                128                                                                                Cgs                                      P                                                                                128                                                  +                                  Cgd                                      P                                                                                128                                                                                *                                    I              L                                                          (        13        )
In formula (13), CgsP128 is the gate-to-source capacitance of PMOS power transistor P128 and CgdP128 is the gate-to-drain capacitance of the PMOS power transistor P128.
The PMOS power transistor P128 operates in the saturation region, so the following relations apply:
                              Cgs                      P                                                                          128                          =                              2            3                    *          Cox          *                      W                          P                                                                                128                                *                      L                          P                                                                                128                                                          (                  14                                                              A                )                                          Cgd                      P                                                                          128                          =                              1            3                    *          Cox          *                      W                          P                                                                                128                                *                      L                          P                                                                                128                                                          (                  14                    B                )
Applying formulae (14A) and (14B) to formula (13) gives:
                              p                                                              3                =                              1                          2                            Π                                *                      a                          Cox              *                              L                                  P                                                                                128                                                              *                                                    2                *                Kp                                                              W                                      P                                                                                128                                                  +                                  L                                      P                                                                                128                                                                                *                                    I              L                                                          (        15        )
Formula (15) shows that the third pole p3 is an increasing function of the current load IL. The current ratio α is preferentially large enough to ensure p3 is higher than the unity-gain frequency (UGF) of the open-loop, so that p3 does not alter the regulator stability. Increasing the current ratio a requires a compromise between the phase margin and the current efficiency performance of the regulator circuit 100.
To recapitulate the analysis, supra, transfer function pole p2, zero zc, and pole pc have been shown to be independent of IL by formulae (9), (10) , and (11) respectively. However, the dc gain GDC is a function of
  1            I      L      as shown by formula (6), and the dominant pole p1 is a function of IL as shown by formula (3). The unity gain frequency (UGF) of the open-loop varies with a factor of √{square root over (IL)} as:
                    UGF        =                              (                                          G                DC                            *              p                                                                                1                        )                                          (                                          p                                                                                2                            zc                        )                                              (        16        )
Formula 16 implicitly shows that the unity gain frequency (UGF) and hence the regulator stability, depends on the current load IL. It becomes difficult to maintain stability when large variations in current load IL are desired.
What is needed, therefore, is a method of realizing a high performance regulator which takes advantage of CMOS fabrication processes in order to provide low noise, stable operation, and low-ripple voltage regulation without requiring tradeoffs between current efficiency and stability.

Standard CMOS low-noise high PSRR low drop-out regulator with new dynamic compensation


An electroplating apparatus can form a plated film having a more uniform thickness and good film quality over an entire surface of a substrate having a conductive layer (seed layer) whose resistivity is equal to or higher than that of copper. The electroplating apparatus includes: a substrate holder for holding a substrate; a sealing member for contact with a peripheral portion of a surface of a substrate, held by the substrate holder, to seal the peripheral portion; a cathode contact for contact with a conductive layer formed in the surface of the substrate, held by the substrate holder, to feed electricity to the conductive layer; and a housing having therein an anode to be immersed in a plating solution, and a porous structure disposed at an open end facing the substrate held by the substrate holder, said porous structure defining a plating chamber in the housing; wherein the plating chamber is divided into rooms by a partition plate and the porous structure, and the anode is comprised of a plurality of divided anodes, each divided anode being disposed in each room of the plating chamber so that each divided anode can pass an independent plating current.

1. Field of the Invention
The present invention relates to an electroplating apparatus and an electroplating method, and more particularly to an electroplating apparatus and an electroplating method useful for filling fine interconnect pattern formed in a surface of a substrate (surface to be plated), such as a semiconductor wafer, with a metal, such as copper, to form embedded interconnects.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as a material for forming circuits on a semiconductor substrate, there is an eminent movement towards using copper (Cu) which has a low electric resistivity and high electromigration resistance. Copper interconnects are generally formed by filling copper into fine interconnect recesses formed in a surface of a substrate. There are known various techniques for forming such copper interconnects, including chemical vapor deposition (CVD), sputtering, and plating. According to any such technique, a copper film is formed in a substantially entire surface of a substrate, followed by removal of unnecessary copper by chemical mechanical polishing (CMP).
FIGS. 28A through 28C illustrate, in a sequence of process steps, an example of forming such a substrate W having copper interconnects. First, as shown in FIG. 28A, an insulating film (interlevel dielectric film) 2 of SiO2 or low-k material is deposited on a conductive layer 1a in which semiconductor devices are formed, which is formed on a semiconductor base 1. Contact holes 3 and trenches 4 for interconnect recesses are formed in the insulating film 2 by the lithography/etching technique. Thereafter, a barrier layer 5 of TaN, TiN or the like is formed on the surface, and a seed layer 7 as an electric supply layer for electroplating is formed on the barrier layer 5.
Then, as shown in FIG. 28B, copper plating is performed onto the surface of the substrate W to fill the contact holes 3 and the trenches 4 with copper and, at the same time, deposit a copper film 6 on the insulating film 2. Thereafter, the copper film 6, the seed layer 7 and the barrier layer 5 on the insulating film 2 are removed by chemical mechanical polishing (CMP) so as to make the surface of the copper film 6 filled in the contact holes 3 and the trenches 4 for interconnects and the surface of the insulating film 2 lie substantially on the same plane. Interconnects composed of the copper film 6 are thus formed in the insulating film 2, as shown in FIG. 28C.
When carrying out electroplating of a surface of a substrate, as shown in FIG. 29, a cathode contact 200 brings into contact with a peripheral region of an conductive layer, such as a seed layer 7, formed on a surface of a substrate W, and a plating solution 204 is filled into between the substrate W and an anode 202 disposed opposite the substrate W. A plated film is deposited on the conductive layer of the substrate W by passing a plating current between the cathode contact 200 and the anode 202 from a power source 206.
Semiconductor wafers and liquid crystal substrates for LSI's tend to increase in area year by year. In line with this tendency, the substrates are posing problems. In detail, as the area of the substrate W increases, the electric resistance (sheet resistance) of the conductive layer, such as a seed layer 7, ranging from the cathode contact 200 on the periphery of the substrate W to the center of the substrate W also increases. As a result, a potential difference produces in-plane of the substrate W, causing a difference in the plating rate. FIG. 29 is an electrical equivalent circuit diagram of general electroplating, and the following resistance components exist in this circuit:
R1: Power source wire resistance between power source 206 and anode 202, and various contact resistances
R2: Polarization resistance at anode 202
R3: Resistance of plating solution 204
R4: Polarization resistance at cathode contact
R5: Resistance of conductive layer (sheet resistance)
R6: Power source wire resistance between cathode contact and power source 206, and various contact resistances
As can be seen from FIG. 29, when the resistance R5 of the conductive layer becomes higher than the other electric resistances R1 to R4 and R6, the potential difference arising between both ends of this resistance R5 of the conductive layer increases, and accordingly, a difference occurs in the plating current. Thus, the plated film growth rate lowers at a position distant from the cathode contact 200. If a film thickness of the conductive layer is small, the resistance R5 further increases, and this phenomenon appears conspicuously. This phenomenon, called terminal effect, means that the current density differs in-plane of the substrate W, and the characteristics of a plated film itself (resistivity, purity, burial characteristics, etc. of the plated film) are not uniform in-plane.
As a method for avoiding these problems, it is conceivable to increase the thickness of the conductive layer or decrease the electric conductivity of the conductive layer. However, the substrate is subject to various restrictions even in manufacturing steps other than plating. For example, when a thick conductive layer is formed on a fine pattern by sputtering, voids easily occur inside the pattern. Thus, it is impossible to easily increase the thickness of the conductive layer or change the film type of the conductive layer.
In order to solve above problem, the applicant has proposed a plating apparatus wherein a high resistance structure 208, which has lower electric resistivity than the electric resistivity of the plating solution, is disposed between an anode 202 and a substrate W, as shown in FIG. 30. With this structure, an electric equivalent circuit diagram is shown in FIG. 30, and a resistance Rp of the high resistance structure 208 is added as compared to the electric equivalent circuit diagram shown in FIG. 29. Therefore, if a value of the resistance Rp of the high resistance structure 208 becomes high, a value ((R2+R3+Rp+R4)/(R2+R3+Rp+R4+R5)) comes near one, the influence of the resistance R5, i.e., a resistant factor (sheet resistance) of the conductive layer becomes low.
A copper seed layer, formed by, e.g., sputtering, CVD, ALD or electroless plating, is generally used as the seed layer 7; and such a copper seed layer is becoming thinner year by year with the progress toward finer interconnects. For example, a thickness of a copper seed layer in the field region of a substrate is around 600 angstrom in the manufacturing of a 65 nm-generation semiconductor device. A thickness of a copper seed layer is expected to be not more than 500 angstrom in a 45 nm-generation. In the next generation and the following generation, it is expected that a thickness of a copper seed layer will be not more than 300 angstrom, or that copper will be plated directly on a surface of a barrier layer of, e.g., ruthenium without forming a copper seed layer.
The electric resistance (sheet resistance) of a current copper seed layer having the above thickness is not more than 1 Ω/sq. The terminal effect, which depends on the sheet resistance of such a seed layer, can be reduced by interposing a resistor body between a substrate, which is connected to a cathode contact and serves as a cathode, and an anode, or by decreasing the acid concentration of a plating solution so as to increase the resistance of the plating solution itself. This can prevent a copper plated film from becoming thinner in the central portion of the substrate than in the peripheral portion, enabling the formation of a copper film having a uniform thickness on the surface of the substrate.
The applicant has proposed the use of divided anodes in any desired shape or the use of an insoluble anode (see Japanese Patent Laid-Open Publication Nos. 2002-129383 and 2005-213610). The applicant has also proposed to apply a voltage between an anode and a surface (conductive layer) of a substrate when placing the substrate into a plating bath, the voltage being such as to provide an average cathode current density of 1 to 30 mA/cm2 for the surface (conductive layer) of the substrate (see Japanese Patent Laid-Open Publication No. 2004-218080). It has also been proposed to control a thickness of a plated film by electrical control using a switching mechanism that includes a number of power sources or resistances.

Electroplating apparatus and electroplating method


Systems and methods are discussed for providing a continuous monitoring system for high-speed links. Data packets are passively read in a high-speed environment. Concurrent streams are created to handle the high-speed data packets and to manipulate subsets of data packets in modules for output to various applications or destinations. The modules can include algorithms or filters created for various tasks.

Today, the Internet backbone consists of inter-connected networks of major ISPs, government, academic institutions and large private networks. High bandwidth optical links connect these networks at 'peering' points. Monitoring these high-speed links can give us a wealth of data. Monitoring has applications in traffic accounting, capacity provisioning, anomaly detection, and fault diagnosis.
In today's Internet, viruses, worms and DDOS attacks are commonplace. Intrusion Detection Systems and Antivirus software detect and stop the spread near the leaf nodes of the victim. It is very beneficial to stop this unwanted traffic even before it reaches the victim's network. On a high-speed backbone network, we have the opportunity to see traffic from multiple networks. This means we have more data available to us and can detect the anomaly well before a small-network administrator. Traditionally, changes in network patterns are used to detect such anomalies.
An important requirement for a service provider is to offer higher availability and fault-tolerance. It is well known that when things go wrong in a network, the traffic can change drastically. For example, an unusual sequence of packets might indicate a router mis-configuration. If we could detect these changes well in advance, we can take preventive measures to ensure that service is not interrupted.
Many traffic engineering problems need accurate measurements of metrics like network demand and heavy-hitters over multiple links. Intra-domain routing protocols like ISIS and OSPF need traffic matrices to assign link weights for optimal routing. These traffic accounting requirements are different from network resource usage measurements. Here, we are interested more in per-customer accounting instead of the network resource as a whole. In addition, this information can be useful in detecting changes in the network usage of customers and offering a better service.
Measuring the usage of network resources can be very useful for network management. Common metrics to measure over the link would involve byte and packet counts, change in packet rate and changes in byte rate. This information, augmented with the statistics from the routers, can give a detailed view of the network health.
With the heightened security focus of governments, ISPs will soon have to comply with laws imposed by governmental bodies. Some laws will require that networks be "wire-tap" friendly and easy to monitor.
Most tier-2 and tier-3 ISPs share each other's networks to carry traffic. This sharing is bound by Service Level Agreements (SLA) between the networks. There is no easy way to enforce or check the adherence to these SLAs at all times. However, one way to do it would be to monitor the traffic on the links.
Most of the tasks (queries) mentioned above are continuous, i.e. they keep examining streams of data continuously instead doing a one-time analysis. Network operators would be interested in running such queries at different points in the network.

CMON: an “always-on” monitoring platform for high-speed links


A process for forming an easy open lid comprising a central panel having a score strip with a score thereon, a crimping edge and a ring enabling the lid to be opened by perforation of the score. The score on the lid is formed from a metal lid outline supported by an anvil by displacing a punch of angle alpha thereover and causing an asymmetrical flow of metal between the punch and the anvil during the displacing. This reduces the risk of crack formation in the metal at the bottom portion of the score or beneath the score.

1. Field of the Invention
The present invention relates to the field of easy-to-open containers and receptacles, and more specifically to easy-to-open metal lids.
2. Description of Related Art
Easy-to-open lids have a generally peripheral score, as in the case of containers for food products--illustrated in FIGS. 1a to 1c. FIGS.1a and 1b correspond to easy-to-open lids with a counter-dish. Alternatively, easy-to-open lids have a score defining a weak portion of the panel of the lid, as in the case of a drinks can lid.
The scores are defined by their profile and the thickness of residual metal under the score, which is also called the "residual".
A profile is defined by the angle alpha of the score and by the calculated width P at the bottom of the score. A typical score is shown diagrammatically in FIG. 2 together with its angle alpha and the width P, a score in which the angle alpha is equal to 60.degree. and the width P is 40 .mu.m being denoted symbolically by "60P40 ".
There is an ever-increasing demand for easy-to-open lids having simultaneously a greater ease of opening and a greater degree of security in production and use. However, these demands are at the present time to a large degree contradictory insofar as a greater ease of opening is generally obtained by reducing the residual. This reduction is however accompanied by much less production security (accuracy of larger tools, smaller safety margin), and above all by the very serious risk of cracks developing at the bottom of or underneath the score, resulting in leakages either directly, or by the action of pressure during packaging, typically involving sterilisation, or after packaging, due to the corrosive action of the packaged product.
Furthermore, the presence of weak residuals and/or cracks makes the lids more susceptible to perforations caused by shock during handling of the packaged products, in particular from the packaging of the product up to its final use by the consumer.
FIG. 7 illustrates a cross-section of a score after crimping and sterilisation, showing at the bottom of the score typical cracks that the present invention aims to suppress if not entirely, then at least to a very great extent. FIG. 7 also shows starting points or foci of cracks underneath the score.
The problem is to find a way of reliably and economically manufacturing easy-to-open lids having a weak residual in which the bottom of the scores does not exhibit cracks at the end of the production stage nor after packaging of the product being packed, so as to present, despite a weak residual, a satisfactory behaviour to mechanical stresses and corrosion.

Method for making easy-open lids with improved scoring


In an example of a method disclosed herein, a polycarbonate with a hydrophilic surface is formed. An ether substituted dichlorosilane, phosgene, and a Bisphenol reactant are polymerized to form a polycarbonate including a hydrolyzable silane in its backbone chain. The hydrolyzable silane includes an alkoxy group attached to a silicon atom. The alkoxy group on the hydrolyzable silane is converted to a more hydrophilic functional group to form the polycarbonate with the hydrophilic surface.

Polycarbonates are thermoplastic polymers that are easily worked, molded, and/or thermoformed, and thus are used in a variety of applications. Some of these applications include electronic components, construction materials, automotive components, aircraft components, lenses, mirrors, and lamps. The versatility of polycarbonates is accredited to the many unique properties of the polymer. These properties include, for example, high impact-resistance, low scratch-resistance, high transparency to visible light, and no electrical conductivity.

Methods for forming a polycarbonate with a hydrophilic surface


One embodiment of a thermal interface material includes a plurality of carbon nanotubes each having a first end and an opposite second end, a heat current collector covering one of the first ends and the second ends of the carbon nanotubes, and a macromolecular material filled in spaces between the carbon nanotubes and heat current collector. A method for manufacturing a thermal interface material is also provided.

Electronic components such as semiconductor chips are becoming progressively smaller with successive new product releases, while at the same time heat dissipation requirements thereof are increasing. Commonly, a thermal interface material is utilized between the electronic component and a heat sink in order to efficiently dissipate heat generated by the electronic component.
A conventional thermal interface material is made by diffusing particles with a high heat conduction coefficient in a base material. The particles can be made of graphite, boron nitride, silicon oxide, alumina, silver, or other metals. However, a heat conduction coefficient of this kind of thermal interface material is now considered to be too low for many contemporary applications, because it cannot adequately meet the heat dissipation requirements of modern electronic components.
An article entitled "Unusually High Thermal Conductivity of Carbon Nanotubes" and authored by Savas Berber (page 4613, Vol. 84, Physical Review Letters 2000) discloses that a heat conduction coefficient of a carbon nanotube can be 6600 W/m·K (watts/meter·Kelvin) at room temperature.
A kind of thermal interface material which conducts heat by using carbon nanotubes has been developed. The thermal interface material is formed by injection molding, and has a plurality of carbon nanotubes incorporated in a matrix material. A first surface of the thermal interface material engages with an electronic device, and an opposite second surface of the thermal interface material engages with a heat sink. The second surface has a larger area than the first surface, so that heat can be uniformly spread over the larger second surface. However, the thermal interface material is generally formed by injection molding, and is relatively thick. This increases a bulk of the thermal interface material and reduces its flexibility. Furthermore, the carbon nanotubes are disposed in the matrix material randomly and multidirectionally. This means that heat does not necessarily spread uniformly through the thermal interface material. In addition, the heat does not necessarily spread directly from the first surface engaged with the electronic device to the second surface engaged with the heat sink.
To overcome the above-described problems, a method for producing a thermal interface structure having aligned carbon nanotubes has been developed. In a batch process, a capacitor is immersed in a bath of a slurry of thermoplastic polymer containing randomly oriented carbon nanotubes, and capacitor plates are adjusted to a desired spacing between them to provide a particular film thickness. Prior to curing of a preform of the thermal interface structure, the preform is energized to create an electrical field to orient the carbon nanotubes in a uniform direction in the polymer. Upon curing, the carbon nanotubes are embedded in the polymer in the desired alignment.
However, even though the thermal interface structure's thermal conductivity may be enhanced, it still may not be satisfactory for some applications. It is believed that one important reason limiting the thermal conductivity is the existence of thermal interface resistance where adjacent carbon nanotubes in any given heat conduction path within the thermal interface structure adjoin each other. In particular, where a heat conduction path comprises a plurality of such thermal interface resistance junctions, the overall thermal resistance along the entire heat conduction path may be significant.
What is needed, therefore, is a thermal interface material with good thermal conductivity. What is also needed is a method for manufacturing such kind of thermal interface material.

Thermal interface material and method for manufacturing same


Present invention is relative to a golf head. The golf head includes a main part. The main part that is made of metal includes a body portion and a neck portion. A hitting part, which is made of metal that is harder than the main part, has a face portion and a bottom portion. The bottom portion that extrudes from the bottom of the face portion is modeled with the face portion integral whole. The hitting part connects with the body portion of the main part by the rim. The back of the face portion and the top of the bottom portion, which closes to the face portion, suspend in midair. The connective position of the body portion and the rear of the bottom portion crosses the central line of the bottom of the golf head and is partial to rear.

1. Field of the Invention
The present invention relates to golf head and more particularly to a golf head structure that uses hard metal to make the main part and models the face and bottom by soft metal integral whole.
2. Description of the Related Art
In prior art, a golf head that is made of soft metal (like soft carbon steel) has the advantage of easy control and it is also easily to adjust the angle of the neck portion. But, the disadvantage is that the grooves on the face damages easily by hitting the ball hardily and the bottom wears down by grinding the ground. It is a practical solution by strengthening the face. For example, using hard metal to make a hitting plate and fixed it on the face. However, this is harmful to the control of the ball. The solution is making the face into a cup shape. The cup shape face has advantages of better bending elasticity and control. The wear-resisting character of the bottom can be improved by using hard metal. But, the face and the bottom are usually made and placed individually in prior art. So, the front bottom of the main part has no protection and damages easily.


The invention relates to an identification document (21) comprising a non-transparent core (6), and one or more layers of a transparent material (14) arranged on at least a back (13) or a front surface (12) of said core. In order to achieve an identification document where forgery attempts are visibly detectable, the identification document (21) has a translucent security element in a region (7) where the thickness of the non-transparent core (6) material is smaller as compared to the thickness of the non-transparent core material in other parts of said core (6).

1. Field of the Invention
This invention relates to an identification document and in particular to a security element of such a document, which makes forgery even more difficult.
2. Description of Prior Art
Identification documents are manufactured as multilayer documents wherein information needed in the document is written to the document by laser engraving or printing, for instance. In this way, it is possible to provide the document with the necessary information such that the information is not located on the outer surfaces of the document, but instead deep inside the document on layers which cannot be reached unless the document is broken into parts. An identification document typically consists of a non-transparent core surrounded by one or more transparent surface layers.
In order to avoid forgery, the document is manufactured in such a way that it should be impossible to break the document into parts. However, if a forger for some reason manages to break an identification document into parts, the identification document needs to have a construction that ensures that the forgery can be detected due to visible marks.

Identification document and a method of producing


A method of evaluating the exposure property of data to a wafer in which errors in the production of a photomask and the formation of patterns caused by defocus in the transfer of data to the wafer are considered. Accordingly, errors in the production of the photomask and deformation of patterns caused by defocus can be evaluated in the stage of design data. Oversize processing and undersize processing are given to pattern data of the object of the process by figure operation for the whole pattern data within errors of the production of the photomask according to the specification thereof, and simulation is used as a reference to the original pattern data of the object of the process, the oversize data in which oversize processing is given to the pattern data and the undersize data in which undersize processing is given to the pattern data, in which the wafer exposure simulation is carried out under the condition of zero focus, or under each exposure condition of zero focus, a given value minus defocus or a given value plus defocus. The exposure property of data to the wafer is evaluated from the results of the wafer exposure simulation.

In recent years, progress in high density circuits and the miniaturization of semiconductor devices has been made in the production of semiconductor device. A photomask (it is also called a "reticle") is used and figures having a length shorter than exposure wavelength of an aligner used in the production of a semiconductor have been written on a wafer by the exposure of the wafer since the latter half of 1990's.
In this case, a difference between a pattern formed on a photomask and a pattern formed on a semiconductor wafer is generated by the diffraction phenomena of light. For example, patterns of design data shown in FIG. 3(a) become patterns on a wafer as shown in FIG. 3(b).
Namely, the pattern formed on a semiconductor wafer is different from the design data by the diffraction phenomena of light and so distorted.
This is called generally the optical proximity effect.
In order to change the pattern formed on a semiconductor wafer into an objective shape considering the distortion of a pattern formed on a wafer by the optical proximity effect, a photomask having a corrected pattern different from the design data is produced by adding corrections to the design data so as to change the shapes of patterns on a photomask into shapes different from the design data. The technique of forming the pattern adapted to objective design data on a wafer using the photomask having corrected patterns is called optical proximity correction (OPC).
An example of the application of the technique of optical proximity correction is shown in FIG. 9.
FIG. 9, FIG. 9(a2), FIG. 9(b2), FIG. 9(c2) and FIG. 9(d2) show the shapes of patterns in the case of patterns being formed on a wafer using pattern data shown in FIG. 9(a1), FIG. 9(b1), FIG. 9(c1) and FIG. 9(d1), respectively.
Pattern data shown in FIG. 9(a1) are design data, wherein patterns formed on a wafer corresponding to patterns 910 form patterns having either a thin width or short length because of the optical proximity effect.
FIG. 9(b1) shows data in which OPC is applied to design data (FIG. 9(a1)).
In this case, numeral 920 designates OPC patterns, wherein it is assumed that there is no defocus in the wafer exposure or the exposure of data to the wafer.
As a result, patterns formed on wafer corresponding to patterns 910 form patterns 912 shown in FIG. 9(b2) so that patterns 912 approach the shape of patterns of the objective design data as compared with patterns shown in FIG. 9(a2).
FIG. 9(c1) shows patterns of data in which OPC 920 is applied to design data 910 in the same manner as shown in FIG. 9(b1). However, when there is defocus in the wafer exposure, patterns formed on a wafer are deformed, for example, into patterns shown in FIG. 9(c2).
In the wafer exposure, considering the flatness of the wafer and the thickness of the resist, there can be a defocus of about 300 nm ordinarily.
Accordingly, an OPC technique in which supplementary patterns for increasing the defocus latitude is applied to design data is also applied as a part of the OPC technique for the purpose of the correction of shapes.
For example, as shown in FIG. 9(d1), OPC patterns 920 and supplementary patterns 930 (also called assist bars or merely OPC patterns) for increasing the defocus latitude are applied to design data 910 so that the defocus latitude can be increased.
In this case, even if there is a defocus, patterns formed on a wafer come into shapes approaching patterns of the design patterns (patterns 910 shown in FIG. 9(a1)) in the same manner as in the case of the defocus shown in FIG. 9(b2).
Namely, according to the use of OPC pattern 930 for the improvement of defocus latitude shown in FIG. 9(d1), patterns 914 formed on a wafer have the shape as shown in FIG. 9(d2), even if there is a defocus in the exposure of data to the wafer so that the deformation of the pattern caused by the diffraction of light is corrected as compared with the case shown in FIG. 9(c2). As a result, the defocus latitude is improved.
Accordingly, the improvement of the yield of products in the production of a semiconductor can be expected.
As mentioned hereinbefore, a difference between patterns in design data and shapes of patterns formed on a wafer is generated by the optical proximity effect in the process of the miniaturization of semiconductors. Therefore, in recent years, the wafer exposure simulation is employed as the effective means for the evaluation of design data, namely the evaluation of data to which OPC has been applied.
Referring to FIG. 10, a conventional method of evaluating pattern data by the wafer exposure simulation is explained.
In FIG. 10, S210 to S260 designate steps of the process.
First, the wafer exposure simulation is mentioned.
The wafer exposure simulation is done by means of device 10 provided with software for simulating shapes of patterns formed on a wafer on the basis of patterns 21 of design data as shown in FIG. 11 (the device is called a wafer exposure simulator), wherein the wafer exposure simulator is usually provided with a display and input and output terminals.
The wafer exposure simulation is ordinarily comprised of two steps of optical simulation (it is also called an optical model simulation) and resist-simulation (the resist-simulation is also called a development simulation, and one of the process model simulations). Further, there is also a case where the wafer exposure simulation is comprised of three steps of optical model simulation, resist-simulation and etching process simulation (the etching process is one of the process model simulations).
In the optical simulation, there is a condition of image formation which is determined exclusively by the wavelength of the source and number of apertures of the source (NA), and σ (σ indicates coherency and is also designated by "sigma"). Aberration and vibration of the aligner are considered selectively for optical simulation in the optical simulation.
In the resist-simulation, simulation of the development process (resist process) is carried out on the basis of the result determined exclusively by optical simulation. However, since the number of parameters is too many, calibrating test patterns and process models obtained by writing test patterns on a wafer by the exposure of data to a wafer into measuring the length of the written patterns in a simulation model is employed.
Simulation of an etching process can be carried out in the same manner as in a simulation of a development process (resist process). Therefore, the simulation of an etching process can be omitted under certain circumstances.
First, test mask 280 is formed on the basis of test pattern data 270 (S271) at S272. Then, simulation model B (designated by numeral 290 at S280) is formed through the transfer of pattern data to a wafer or the exposure of pattern data to a wafer through test mask 280 (S273) and measurement (S274) of the length of the written pattern on a wafer by the wafer exposure.
Zero defocus is ordinarily assumed for a wafer.
The wafer exposure simulation is carried out using the formed simulation model B (290) and data with OPC in which OPC is applied to design data designed for the circuit of a semiconductor device as pattern data 210 of the object of process 210, by means of the wafer exposure simulator 250, so that the shapes of patterns formed on a wafer are evaluated and proved.
Simulation model B (290 at S280) is used as a reference to pattern data 210 of the object of the process. The wafer exposure simulation is carried out at a given defocus (usually zero defocus), by which shapes of patterns formed on a wafer are evaluated.
In this case, simulation model B 290 is comprised of a group of dimension data obtained by writing patterns on a wafer by the exposure of data to the wafer through test mask 280 which is a photomask for tests produced on the basis of test pattern data 270 under the condition of the wafer exposure with a given defocus (usually zero defocus), measuring the dimensions of given transferred patterns to a wafer and relating dimension data of test pattern data 270, dimension data of test mask 280 and dimension data of patterns on the wafer at the correspondent positions with each other for the respective conditions of the wafer exposure.
Contents to be evaluated here are the evaluations of the shapes of patterns formed on a wafer. Differentials 23a, 23b between patterns 21 of data to be processed and the shapes of patterns 23 formed on a wafer on the effect of simulation are measured, as shown in block 23 of FIG. 11. In case of the differentials being larger than a prescribed value, correction is made in the step of design.
The exposure property of data to the wafer evaluated made according to conventional simulation is made using ideal design patterns and assuming that there is no error in the production of a photomask and that ideal zero defocus is set for the wafer exposure.
Therefore, errors in the production of the photomask and deformation of patterns caused by defocus in the wafer exposure could not be evaluated from the wafer exposure simulation.
Conventional methods of the evaluation of the exposure property of data to a wafer are satisfactory when the dimensions of the patterns formed on a wafer are more than about ⅔ of the exposure wavelength. However, when miniaturization progresses further, errors in the production of the photomask and deformation of the patterns caused by defocus become serious.
With high density circuits and the miniaturization of semiconductor devices progressing in recent years, in the evaluation of the exposure property of data to a wafer with conventional simulations, there was a problem that errors in the production of a photomask and deformation of patterns caused by a defocus in the exposure of data to wafer cannot be evaluated by the wafer exposure simulation because ideal design patterns are used assuming that the produced photomask has no error in the production of the photomask and that ideal zero defocus is set in the condition of the wafer exposure.
Corresponding to the above-mentioned problem, it is an object of the present invention to provide a method of evaluating the exposure property of data to a wafer in which errors in the production of a photomask and deformation of patterns caused by a defocus in the exposure of data to a wafer are considered.
Accordingly, the present invention aims at evaluating errors in the production of a photomask and the deformation of patterns cased by a defocus in the exposure of data to a wafer in the stage of design data.

Method of evaluating the exposure property of data to wafer


A cutting insert has: an upper surface; a lower surface; a side surface, having a first surface and a second surface disposed opposite each other between the upper surface and the lower surface; and a first cutting edge. The lower surface has a plurality of slots extending from a side of the first surface to a side of the second surface. In addition, when viewed from a side of the lower surface, if the angle between a ridge line on which the upper surface and the first surface intersect and an imaginary extension line of the plurality of slots is defined as θ1, and the angle between a ridge line on which the lower surface and the first surface intersect and the imaginary extension line is defined as θ2, then θ2>θ1.

Milling tools are known in the art for cutting workpieces such as metals in cutting machining. For example, International Publication 2006/041353 (patent document 1) has disclosed a cutting insert used in a milling tool. The cutting insert disclosed in patent document 1 has an upper surface, a lower surface, a first side surface, a second side surface opposite the first side surface, a first cutting edge positioned on a portion on which the upper surface and the first side surface intersect, a second cutting edge positioned on a portion on which the upper surface and the second side surface intersect, and slots positioned on the lower surface and sandwiched by a plurality of protrusions. The plurality of protrusions extend parallel to each other from one side of the opposite second side surface to the other side. Patent document 1 represents an attempt to securely fix the cutting insert to a holder by means of the slots sandwiched by these protrusions.
When viewed from a side of the lower surface, the cutting insert disclosed in patent document 1 has the following feature: the angle between the second cutting edge and an imaginary extension line of the protrusion is equal to the angle between a ridge line on which the opposite second side surface and the lower surface intersect and the imaginary extension line of the protrusion.
Given that the above angles are equal, when these angles are relatively small, securely fixing the cutting insert to a holder may be difficult. Conversely, when these angles are relatively large, the cutting insert can be securely fixed to the holder. However, when the angles are relatively large, performing slope machining and the like may be difficult.

Cutting insert, cutting tool, and method for manufacturing cutting-machined product


An electrical connector device includes first and second cable winding members one of which is co-rotatable with a rotatable side and the other of which is fixed to a stationary side. The first and second cable winding members are arranged with their respective centers being spaced apart from each other. An flexible cable is fixed at its one end to the first cable winding member and at its other end to the second cable winding member. The flexible cable is wound around the first winding member to form a loose winding of a plurality of turns therearound so that relative rotation between the first and second cable winding members is allowed by means of radially expanding and contracting behavior of the cable winding around the first cable winding member.

1. Field of the Invention
The present invention relates to an electrical connector device which provides electrical connection between relatively rotatable components, i.e. between components located on a rotatable side and a stationary side.
2. Description of the Prior Art
It has been known to use a slip-ring assembly for providing electrical connection between electrical devices arranged on a side of a rotary shaft and a stationary side, respectively. Specifically, a brush is fixedly provided on the stationary side and arranged to slide on a slip-ring which is fixedly provided along circumference of the rotary shaft, so as to maintain the electrical connection therebetween.
However, in this prior art, since the electrical connection is maintained by the mechanical sliding relationship between the slip-ring and the brush, short circuits due to metal powder caused by the sliding action therebetween as well as imperfect or defective contacts therebetween due to invasion of dust are likely to occur, which can not be effectively avoided. Accordingly, a problem has been raised on reliability particularly when it is used, such as, in a triggering circuit for an airbag provided in an automotive steering wheel, where a reliable transmission of a triggering current is extremely required.
In order to solve this problem, there has been proposed another type of the electrical connector device as disclosed in, such as, Japanese First (unexamined) Patent Publication No. 57-165982 which is equivalent to U.S. Pat. No. 4,502,746. In the electrical connector device of this type, an electrically conductive member is loosely wound around a rotary shaft with its one end fixed to the rotary shaft and with its other end fixed to a stationary side so as to ensure the electrical connection therebetween.
FIG. 9 shows an electrical connector device similar to the latter prior art, for briefly explaining the concepts incorporated in the latter prior art. In FIG. 9, FIG. 9(A) shows a transverse cross section of the electrical connector device and FIG. 9(B) shows a vertical cross section thereof.
A stationary member 72 of an annular-cylindrical shape is provided surrounding a rotary shaft 71 to define an annular space therebetween. A flexible cable 73 is arranged in the annular space as being loosely wound around the rotary shaft 71. One end of the cable 73 is fixed to the rotary shaft 71 and electrically connected to a first terminal 74 for connection to an electric device arranged at a location for co-rotation with the rotary shaft 71. The other end of the cable 73 is fixed to the stationary member 72 and electrically connected to a second terminal 75 for connection to an electric device arranged on the side of the stationary member 72.
With this arrangement, when the rotary shaft 71 rotates in a counter-clockwise direction, the rotary shaft 71 pulls the cable 73 so that the cable winding is contracted onto the rotary shaft 71, while, when the rotary shaft 71 rotates in a clockwise direction, the rotary shaft 71 pushes the cable 73 so that the cable winding expands to be loosened. In this manner, the rotary shaft 71 is allowed to rotate within a limited number of revolutions or turns.
In this latter prior art, however, since an overall length of the cable 73 is determined depending on a diameter of the rotary shaft 71 and a required limited or maximum number of revolutions of the rotary shaft 71, when the diameter of the rotary shaft 71 increases, the length of the cable 73 as well as the size of the stationary member 72 which accommodates the cable 73 therein, inevitably increase, respectively.


An image forming apparatus includes an image forming unit that prints an image on a medium, a transporting unit that transports the medium in a first direction and a second direction, which is the opposite to the first direction, and a sensor that is placed a predetermined distance away from the transporting unit in the second direction to detect the medium. The image forming apparatus aligns the print start location of the medium with an image forming line of the image forming unit by detecting an end of the medium in the second direction using the sensor.

1. Field of the Invention
The present invention relates to an image forming apparatus and a method of using the same. More particularly, the present invention relates to an image forming apparatus that prints an image by matching a print start location of a medium with an image forming line, and a method of forming an image using the same.
2. Description of the Related Art
When printing an image on a medium, the image needs to be located accurately at a predetermined location of the medium. In particular, a medium for printing photographs includes a printing area on which an image is printed and a non-printing area on top and bottom of the printing area. The non-printing area may also be formed on both side edges of the printing area. The printing area and the non-printing area are typically divided via perforated or dotted lines. An image is printed slightly larger than the printing area, and if the non-printing area is torn or cut along the perforated or dotted lines, a borderless printed image just like a developed photograph is obtained. In this case, the image has to start printing exactly from a print start location of the medium if the image is to be borderlessly printed without any loss. Additionally, even in a general printing process, the image has to be printed starting precisely from the print start location of the medium to print the image without any loss. If the image is printed before the print start location, the top region of the image can be lost and if the image is printed below the print start location, the bottom region of the image can be lost.
When printing a color image, a medium is repeatedly moved back and forth to superimpose cyan, magenta, and yellow images. If the print start locations of the cyan, magenta, and yellow images are not identical, the cyan, magenta, and yellow images will not accurately overlap with one another, thereby resulting in a poor quality color image.
Accordingly, a need exists for an improved image forming apparatus and a method that provides quality color images without image loss.

Image forming apparatus and method of using the same