A method and device for detecting DCI are provided. The method includes: obtaining intermediate data in DCI blind detection, the intermediate data including descrambled data, decoded data and detected RNTI values; determining data to be processed from the decoded data based on a matching result of the detected RNTI values and configured RNTI values; performing encoding, rate matching and modulation on the data to be processed to obtain modulated data; calculating confidence levels of the configured RNTI values based on the modulated data and the descrambled data; and when a maximum confidence level of the configured RNTI value is greater than a predetermined threshold of confidence level, determining that the data to be processed contains detected DCI. The probability of DCI misdetection may be reduced, and further the accuracy of uplink and downlink data on a mobile terminal and system stability may be ensured.

In an LTE system, downlink data receiving at a mobile terminal includes Physical Downlink Control Channel (PDCCH) receiving. A PDCCH carries Downlink Control Information (DCI) of one or more mobile terminals. The DCI generally includes downlink scheduling and allocation information used in demodulating and decoding a Physical Downlink Shared Channel (PDSCH) when a mobile terminal receives the PDSCH, scheduling authorization information of sources and transmission format used in the mobile terminal transmitting data in a Physical Uplink Shared Channel (PUSCH), acknowledgement information transmitted in a shared channel, and uplink physical channel power control information.
A mobile terminal can blindly detect DCI in a received PDCCH based on a Radio Network Temporary Identifier (RNTI) value which is configured for the mobile terminal, decode the DCI and make configuration for receiving a PDSCH or sending a PUSCH based on the decoded PCI.
When receiving the PDCCH and blindly detecting the DCI, the mobile terminal needs to perform a Cyclic Redundancy Check (CRC) on a demodulation result in each search space, and match the demodulation result to the configured RNTI value. If the demodulation result matches the configured RNTI value, the corresponding DCI is determined to be DCI actually sent to the mobile terminal. According to LTE specifications, a mobile terminal can match 22 search spaces at most and one search space can detect data of one or two DCI length. That is, CRC and RNTI matching may be performed 44 times at most.
However, in LTE specifications, a 16-bit CRC is employed to save bits transmitted in a PDCCH. Too few CRC check bits may result in a certain degree of mismatching. Theoretically, a misdetection of DCI may occur every 1.5 seconds if RNTI matching is performed 44 times in each sub frame.
The misdetection of DCI may further lead to wrong configuration for reception of PDSCH or transmission of PUSCH, which will cause received downlink data to be discarded or downlink data to be wrongly transmitted and received. This, in turn, may result in package loss and reduce the throughput of the mobile terminal system. Besides, the wrong configuration may also cause the system abnormal and reduce the reliability and stability of the mobile terminal system.
In some technologies, a determination process is performed on whether DCI obtained by blind detection is valid or not. If it is determined that invalid information exists in parameters configured in a PDSCH or a PUSCH, the DCI is filtered out to avoid system instability resulted from abnormal configuration. However, it still happens that some DCI obtained by misdetection cannot be filtered out, especially when DCI obtained by misdetection is valid in itself, while the DCI is not the information that a base station actually sends to a mobile terminal.
In some technologies, in order to filter DCI, a threshold is set for a distance on a state machine shortest path output from convolutional decoding when DCI demodulation is performed. However, by this method, it often happens that the DCI that a base station actually sends to a mobile terminal is filtered out, while the DCI obtained by misdetection is retained.
Therefore, new DCI detection methods are needed to reduce the probability of DCI misdetection.

Method and device for detecting downlink control information

SPREADTRUM COMMUNICATIONS (SHANGHAI) CO., LTD.


Various embodiments include apparatuses for performing maintenance on a gas turbine bearing area, along with related methods. One apparatus can include: a set of rails sized to couple with the gas turbine and rest coaxially with a bearing adjacent the gas turbine, the set of rails for supporting a portion of a housing of the bearing; a first platform spanning between the set of rails; a lifting device coupled to the first platform for engaging an inlet bellmouth of the gas turbine; and a second platform suspended from the set of rails sized to accommodate an operator.

Conventional turbines, such as gas turbines, generally include three sections: a compressor section, a combustor section and a turbine section. The compressor section compresses ambient air, and provides that compressed air to the combustion section where it is combined with fuel to generate a heated working fluid (gas). The heated gas is provided to the turbine section, where it impacts turbine blades to drive rotation of the turbine rotor shaft.
The rotor shaft is sometimes coupled with a dynamoelectric machine such as a generator (e.g., via a coupled shaft), which converts the rotational energy of the turbine into electrical energy. In other cases, the rotor shaft is coupled with an accessory box or other system. In either case, the rotor shaft is coupled with an external shaft (e.g., from the accessory box or dynamoelectric machine). This coupling is surrounded and protected by a thrust bearing. The thrust bearing can provide mechanical support to the shafts, and dissipate thrust from the turbine during operation. The thrust bearing is located adjacent the inlet bellmouth of the turbine's compressor section, and is protected by a bearing housing. The bearing area also includes a journal bearing, which withstand radial loads applied to the rotor. Additional components within the bearing housing area can include lift oil piping, thermocouple wiring, and other instrumentation.
When performing maintenance on the shafts or the thrust bearing, conventional approaches require completely removing the inlet bellmouth in order to access the bearing (and shafts) under the housing. The inlet bellmouth is formed in two halves around the turbine shaft, and is interconnected with other components in the compressor section. Because of the significant weight of the bearings (e.g., up to 225 kilograms per half), conventional approaches require clearance in order to manipulate these components. Conventional approaches for maintenance on the bearing area, including thrust and journal bearings, involve the use of an overhead crane that lifts the upper half of the inlet bellmouth to remove it from the assembly. As such, maintenance approaches that require complete removal of the inlet bellmouth are expensive, cumbersome and time-consuming.

Turbine bearing maintenance apparatus and method


The present invention provides a pressure sensing device for sensing pressure which is adapted to provide an electrical indication of a sensed pressure. The pressure sensing device has a top lamination, a middle lamination, and a bottom lamination. A pressure sensor is located within an aperture defined in the middle lamination. First and a second electrical connectors, being exposed by the aperture, make electrical connection with the pressure sensor when pressure or compression is applied to the pressure sensing device. An output electrical signal indicative of the applied pressure is produced when the pressure sensor has electrical contact with the electrical conductors.

As is well known in the art, some types of pressure sensor devices are configured to develop an electric potential proportional to an applied pressure. Several forms of these pressure sensors are packaged into pressure sensor devices designed for surface mounting to circuit boards. Typically, the pressure sensor devices are connected to the circuit board by a clamping device.
In order to measure the electric potential in the pressure sensor device, at least two electrical conductors connected to the pressure sensor device will be needed. One type of pressure sensor device requires an electrical conductor to be connected on each side of the pressure sensor. Another type of pressure sensor device requires an electrical conductor to be connected on one side of the pressure sensor. The electrical conductors are usually connected by soldering, glueing or clamping wires to the pressure sensor device.
However, problems may occur when the circuit board is subjected to vibrations or environmental conditions, such as moisture. The vibrations may cause the wires to suffer fatigue and break. The clamping device may also suffer fatigue and dislocate from the circuit board, due to the vibrations. Additionally, pressure sensor devices usually need to remain dry in order to operate properly. The clamping devices will not ordinarily keep moisture off the pressure sensor device.
Since, additional steps are typically required to surface mount pressure sensor devices, the production costs for circuit boards generally increases. Additionally, the clamping device increases the number of components required to produce the circuit board, which potentially increases the overall cost of the circuit board.
The present invention is directed to overcoming one or more of the problems as set forth above.


A magnetic device including memory cells is provided. Each memory cell can store multiple bits corresponding to multiple data storage layers. Desired spacing(s) and desired junction angle(s) for the data storage layers are determined in each memory cell. The desired junction angle(s) and the desired spacing(s) correspond to spin transfer switching currents for the data storage layers having. A magnetoresistive stack including plurality of layers for each of the memory cells is deposited. The memory cells include the data storage layers. A data storage layer layers is spaced apart from nearest data storage layer(s) by a distance corresponding to the desired spacing(s). A mask corresponding to the memory cells is provided on the layers. The memory cells are defined such that each memory cell has the desired junction angle(s) and the desired spacing(s) and such that the data storage layers for each of the memory cells is self-aligned.

Magnetic memories, particularly magnetic random access memories (MRAMs), have drawn increasing interest due to their potential for high read/write speed, excellent endurance, non-volatility and low power consumption during operation. An MRAM can store information utilizing magnetic materials as an information recording medium. One type of MRAM is a spin transfer torque random access memory (STT-RAM). STT-RAM utilizes magnetic junctions written at least in part by a current driven through the magnetic junction. A spin polarized current driven through the magnetic junction exerts a spin torque on the magnetic moments in the magnetic junction. As a result, layer(s) having magnetic moments that are responsive to the spin torque may be switched to a desired state. Further, multiple memory cells may be included in a single memory stack.
For example, FIG. 1 depicts a conventional multi-bit magnetic memory cell 10 as it may be used in a conventional STT-RAM. The conventional memory cell 10 stacks multiple conventional magnetic tunneling junctions (MTJs) 12 and 22. MTJ 12 includes a conventional antiferromagnetic layer 14, a conventional pinned layer 16 having magnetization 17, conventional tunneling barrier layer 18, and conventional free layer 20 having changeable magnetization 19. The MTJ 22 includes a conventional antiferromagnetic layer 24, a conventional pinned layer 26 having magnetization 27, conventional tunneling barrier layer 28, and conventional free layer 30 having changeable magnetization 29. The free layers 20 and 30 are the data storage layers. Stated differently, the free layers 20 and 30 have changeable magnetizations 19 and 29 the orientation of which determines the state of the memory MTJ 12 and 22, respectively. Each MTJ 12 and 22 is separated by a nonmagnetic, metallic spacer 21. Each MTJ 12 and 22 may also be considered to correspond to a separate magnetic memory cell. Also shown is conventional seed layer 11. The conventional memory stack might also include contacts (not shown) as well as a selection device (not shown), such as a transistor. In operation, the conventional MTJs/memory cells 12 and 22 are switched using different switching currents. Each conventional MTJ/memory cell 12 and 22 also has two stable states. Thus, the combination of the MTJs/memory cells 12 and 22 in the memory stack 10 may store two bits (e.g. logical states 00, 01, 10, and 11).
The conventional memory stack 10 is typically formed by depositing all of the layers 14, 16, 18, 20, 21, 24, 26, 28, and 30. A portion of the layers 14, 16, 18, 20, 21, 24, 26, 28, and 30 is covered by a mask and the MTJ 12 or 22 is defined. The mask is removed and another mask corresponding to the other MTJ 22 or 12 and the other MTJ 22 or 12 defined. For example, a mask covering a smaller area may be provided and the MTJ/memory cell 22 defined. A larger mask may then be provided and the MTJ/memory cell 12 defined.
Although the conventional memory stack 10 and MTJs 12 and 22 function, other methods for forming a multiple bit memory cell 22 are desired.

Method and system for providing multiple self-aligned logic cells in a single stack


A micropositioner affording the ability to precisely move the tip of an ultrasonic bonding tool relative to a miniature workpiece such as a microcircuit includes a pantograph-like input manipulator mechanism coupled by a single ball joint coupling to a follower mechanism which supports an ultrasonic transducer support housing from which a transducer and bonding tool attached thereto protrudes. In the preferred embodiment, the input manipulator includes a longitudinally outwardly protruding control arm having a control knob at the outer longitudinal end thereof, for grasping between the thumb and fingers of a human operator. The control arm is coupled to the outer lateral end of a four-bar parallelogram linkage comprising part of a pantograph mechanism, while the inner lateral end of the pantograph mechanism is pivotably connected through vertically and horizontally disposed pivot support bearings to a support structure. Motions of the input control ball are followed by, a ball joint attached to the pantograph mechanism, and coupled by the ball joint to the follower mechanism. By a suitable choice of spacings between the pivot axes of the pantograph mechanism support bearings and ball joint, the tip of the bonding tool is made to move in coordinate directions of a second coordinate system containing the tool tip in precisely scaled fractions of corresponding motions of the control knob in a first coordinate system thereof. In the preferred embodiment a tool support plate supporting the transducer housing is longitudinally slidably mounted to a tool support guide plate, which is in turn pivotably supported by a yoke having a yaw pivot bearing allowing lateral motion of the tool tip. The yoke is pivotably mounted by a pitch pivot bearing to the support structure, thereby permitting pivotal motion in a vertical plane of the yoke, tool support plate and tool tip. Preferably, the longitudinal slide axis of the tool tip, and the pivot axes of the rear pitch and yaw pivots all intersect at a common point, thereby assuring completely orthogonal motions of the tool tip in three orthogonal coordinate directions that are precisely scaled fractions of corresponding control knob motions.

A. Field of the Invention
The present invention relates to apparatus useful for moving a tool or similar implement into contact with a workpiece. More particularly, the invention relates to a micropositioner apparatus for positioning the tip of an ultrasonic or similar wire bonding tool at precisely determinable locations relative to a microcircuit or similar workpiece, moving the tip into contact with the workpiece to form a bond, and withdrawing the tip upon completion of a bond, all by manual operation of a manipulator input mechanism comprising part of the micropositioner.
B. Description of Background Art
The invention of the transistor in 1948 may well have been the most important technological development of the 20.sup.th century. Substitution of transistors for vacuum tubes made it possible to construct computers of substantially reduced size and cost, much greater speed and data handling capability, and greatly reduced power consumption than vacuum tube computers. In the latter part of the 1950's, transistors were introduced to a wide variety of military, industrial and consumer products.
In the early 1960's, integrated circuits were introduced. Integrated circuits contain a number of transistors and interconnecting circuit elements which together comprise an operable electronic circuit, such as a logic element, amplifier, or memory element. While the first integrated circuits contained just a few transistors, integrated circuits are now being manufactured which contain tens or even hundreds of thousands of transistors on a single semi-conductor die or chip.
Integrated circuits are fabricated from thin slices of a semi-conducting material such as silicon, germanium, or gallium arsenide. The slices are cut into small squares or rectangles referred to as chips or dice, ranging in size from squares about 100 mil. (0.100 inch) on a side to several hundred mils on a side. Transistors, diodes, resistors and interconnecting circuit paths are formed on the clip or die by diffusing impurities into selected regions of the chip, and by depositing various conducting paths and insulating layers onto the chip.
After a semi-conductor chip or die has been fabricated as described above, it must be attached to a base or carrier forming part of a package or container to protect the delicate die from damage. Prior to packaging, conductive pads providing input and output ports to the die must be electrically interconnected to more robust leads or terminals which extend outward through a container or package used to enclose the die. These interconnections are customarily made using fine aluminum or gold wires which are ultrasonically or thermosonically welded to the pads and leads by a bonding tool that applies ultrasonic energy, or a combination of heat and ultrasonic energy, to a bonding site. Since the connection pads of a microcircuit are extremely tiny and closely spaced, great precision is required in positioning the tip of a bonding tool relative to the microcircuit.
In response to a perceived need for an apparatus capable of precisely positioning the tip of an ultrasonic transducer used to form wire bonds on microcircuit chips, the present inventor invented a micro-positioner apparatus employing a novel pantograph-type manipulator input mechanism. That apparatus which was disclosed in the inventor's U.S. Pat. No. 3,474,685, that issued on Oct. 28, 1969, has proven to be highly effective in performing its intended function, and wire bonding apparatus employing the novel design concepts of the pantograph mechanism disclosed in that patent are used widely throughout the industry. However, the present inventor has found that certain aspects of the micro-positioner disclosed in the U.S. Pat. No. 3,474,685 patent might be improved upon. For example, the allowable working or throat depth of the ultrasonic tool tip would preferably be larger. Also, the use of offset pivotable mountings for the transducer tool plate would desirably be minimized, thereby minimizing the requirement for springs to counter balance unbalanced forces exerted in supporting the tool plate by offset mountings. Moreover, it would be desirable to have a micropositioner apparatus in which various ultrasonic transducers and other bonding tool accessories such as wire spooling mechanisms, some of which might be substantially heavier than conveniently supportable by prior art micropositioners, could be used. Such a need arises, for example, in bonding the heavier wires required for connection to various electronic components such as wound coils. In view of the foregoing considerations, the present invention was conceived of.


An n.sup.- well region is formed at a surface of a semiconductor substrate. A MOS transistor of high breakdown voltage having a drain region and a source region is formed at the surface of the n.sup.- well region. The n.sup.- well region has an impurity concentration peak right below the drain region. Accordingly, a semiconductor device having a high breakdown voltage insulation gate type field effect transistor that can suppress increase of a depletion layer when high voltage is applied across the drain, that can reduce the electric field intensity across the drain, and that has superior breakdown voltage, and a fabrication method thereof, are obtained.

1. Field of the Invention
The present invention relates to a semiconductor device having an insulation gate type field effect transistor of high breakdown voltage, and a method of fabricating such a semiconductor device.
2. Description of the Background Art
A semiconductor device having a MOS (Metal Oxide Semiconductor) transistor of high breakdown voltage will first be described as a conventional insulation gate type field effect transistor of high breakdown voltage.
FIG. 8 is a sectional view schematically showing a structure of a semiconductor device having a conventional MOS transistor of high breakdown voltage. Referring to FIG. 8, an n.sup.- well region 102 is formed at a surface of a p type substrate 1. A MOS transistor 10 of high breakdown voltage is formed at the surface of silicon substrate 1 in n.sup.- well region 102.
High breakdown voltage MOS transistor 10 includes a drain region 3, a source region 4, a gate insulation layer (silicon oxide film) 5, and a gate electrode layer 6. Drain region 3 and source region 4 are formed at the surface of n.sup.- well region 102 with a distance therebetween. Gate electrode layer 6 is formed on the region sandwiched by drain region 3 and source region 4 with gate insulation layer 5 thereunder.
Drain region 3 includes a p.sup.++ region 3a, a p.sup.+ region 3b in contact with p.sup.++ region 3a at the side of source region 4, and a p.sup.+ region 3c in contact with p.sup.++ region 3a at the side opposite to source region 4. This p.sup.++ region 3a has an impurity concentration substantially equal to that of source region 4. P.sup.+ regions 3b and 3c have an impurity concentration lower than that of source region 4.
A field insulation layer 7 is formed on p.sup.+ region 3b. The end portion of gate electrode layer 6 extends upon field insulation layer 7. Field insulating layer 7 is formed to enclose the circumference of high breakdown voltage MOS transistor 10 to electrically isolate MOS transistor 10 from other elements.
In this conventional structure, n.sup.- well region 102 has a P (phosphorous) impurity concentration distribution as shown in FIG. 9. Referring to FIG. 9, the P (phosphorous) impurity concentration is highest at the surface of the substrate, i.e., 2.times.10.sup.16 (atoms/cm.sup.3). The impurity concentration becomes lower as a function of depth into the substrate. The P (phosphorous) impurity concentration becomes equal to the B (Boron) concentration (1.0.times.10.sup.15 (atoms/cm.sup.3)) of a 10 (.OMEGA..cndot.cm) p type silicon substrate, whereby a pn junction is formed at the depth of approximately 5 .mu.m.
A method of fabricating a semiconductor device having a conventional MOS transistor of high breakdown voltage will be described hereinafter.
FIGS. 10-12 are sectional views of such a semiconductor device corresponding to sequential steps of a fabrication method thereof. Referring to FIG. 10, a silicon oxide film 11, for example, is formed on p type silicon substrate 1. A resist pattern 12 of a predetermined configuration is formed on silicon oxide film 11 by a conventional photolithographic technique. Using this resist pattern 12 as a mask, P (phosphorous) ions are implanted under the condition of 150 (keV) and 5.0.times.10.sup.12 (cm.sup.-2). Following removal of resist pattern 12, a heat treatment is applied at 1200.degree. C. for 360 minutes to diffuse and activate the impurities. Then, silicon oxide film 11 is removed.
Referring to FIG. 11, n.sup.- well region 102 having the impurity concentration peak in the proximity of the surface is formed at the surface of p type silicon substrate 1 by the above heat treatment.
Referring to FIG. 12, field insulation layer 7, and p.sup.+ regions 3b and 3c under field insulation layer 7, are formed at the surface of p type silicon substrate 1.
Then, following formation of gate insulation layer 5 and gate electrode layer 6 shown in FIG. 8, p.sup.+ regions 3a and 4 are formed by ion implantation. Thus, a MOS transistor 10 of high breakdown voltage is formed at the surface of n.sup.- well region 102.
Such a high breakdown voltage MOS transistor 10 is used for the driver of a fluorescent character display tube, for example. Recently, the demand for a clearer display is great. The need arises for a driver MOS transistor 10 of higher breakdown voltage.
However, the problem is that it is difficult to improve the breakdown voltage of MOS transistor 10 according to the impurity concentration distribution of the conventional n.sup.- well region 102. This will be described in details hereinafter.
FIGS. 13 and 14 show the spread of a depletion layer generated when a high voltage is applied across the drain of a conventional high breakdown voltage MOS transistor.
Referring to FIG. 13, application of -V to p.sup.++ region 3a under the state where source region 4, gate electrode layer 6, and p type silicon substrate 1 are at the ground potential causes the spread of depletion layer 120 from the pn junction between the drain region and n.sup.- well region 102. As this -V is increased, depletion layer 120 mainly spreads towards the deeper side of the substrate as shown in FIG. 14 to reach the pn junction between n.sup.- well region 102 and p type silicon substrate 1. As a result, punch through will occur between the drain region and p type silicon substrate 1. In the conventional case, it was difficult to improve the breakdown voltage since punch through easily occurs when a high voltage is applied across the drain region.
As shown in FIG. 9, n.sup.- well region 102 has an impurity concentration peak in the proximity of the substrate surface. Therefore, the impurity concentration gradient at the end portion of drain region 3 in FIG. 8 becomes steeper to result in higher electric field intensity. The breakdown voltage corresponding to avalanche breakdown could not be improved.

Semiconductor device having insulation gate type field effect transistor of high breakdown voltage


The apparatus for driving a backlight includes a plurality of lamps each of which has first and second electrodes, a transformer for receiving an AC waveform to provide high voltage AC waveform to drive the plurality of lamps, a detection circuit for generating a detection voltage corresponding to the high voltage AC waveform, an accumulation operation unit for accumulating the detection voltage from the detection circuit and generating a shutdown signal voltage, and a controller for receiving an input voltage to provide the AC waveform to the transformer and for receiving the shutdown signal voltage to shutdown the plurality of lamps in response to the shutdown signal voltage.

1. Field of the Invention
The present invention relates to a backlight, and more particularly, to apparatus and method for driving a backlight. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for preventing malfunction of a shutdown circuit.
2. Discussion of the Related Art
Generally, a liquid crystal display (referred to as "LCD") has the characteristics of light weight, thin profile, low power consumption. Because of these characteristics, the LCD has been used for many applications. For example, the LCD is used in televisions, computer monitors and other types of video devices. The LCD generates images according to video signals by controlling the transmission of light through the LCD. Thus, an LCD requires a light source, such as a backlight, because the LCD itself does not emit light.
The types of light sources used for a backlight include a halogen cathode fluorescent tube and a cold cathode fluorescent tube (CCFL). The CCFL is a light tube that emits light through a cold emission phenomenon such that electrons are emitted from the surface of a cathode when strong electric fields are applied across the light tube. The CCFL is used in applications that require low heat emission, high brightness, long lifetime and full color. A backlight that uses a CCFL can either be a light waveguide type backlight, a direct incident type backlight or a reflection type backlight.
The CCFL can either be an internal electrode fluorescent lamp in which electrodes are formed inside the light tube or an external electrode fluorescent lamp in which electrodes are formed outside the light tube. Such fluorescent lamps are driven by a high voltage AC waveform. The high voltage AC waveform for driving the fluorescent lamps is obtained by a DC voltage from a DC voltage source being converted to a low voltage AC waveform by an inverter and then the low voltage AC waveform is stepped up to a high voltage AC waveform by a transformer.
FIG. 1 illustrates a schematic block diagram of an apparatus for driving a backlight according to the related art. As shown in FIG. 1, the apparatus for driving a backlight of the related art includes a plurality of lamps 10, each of which has first and second electrodes. A transformer 20 provides a high voltage AC waveform to drive the plurality of lamps 10 in parallel. A shutdown circuit 30 generates a shutdown signal voltage Vsd based on the high voltage AC waveform output from the transformer 20. A controller 40 converts an input voltage Vin into an AC waveform that is provided to the transformer 20 and performs shutdown of the AC waveform being provided to the transformer 20 in response to the shutdown signal from the shutdown circuit. When the AC waveform being provided to the transformer 20 is shutdown, the high voltage AC waveform is shutdown to the plurality of lamps 10.
The plurality of lamps 10 emits light in response to the high voltage AC from the transformer 20. The first electrode of each of the plurality of lamps 10 is commonly connected to an output lead N1 of the transformer 20, and the second electrode of each of the plurality of lamps 10 is electrically grounded to the earth. A first capacitor Ca is electrically located between each first electrode of the plurality of lamps 10 and the output lead N1 of the transformer 20, and a second capacitor Cb is electrically connected between each second electrode of the plurality of lamps 10 and the ground source. The first and second capacitors Ca and Cb balance currents among the plurality of lamps 10 to prevent non-uniformity of brightness among the plurality of lamps 10.
The transformer 20 includes a primary coil L1 receiving an AC waveform from the controller 40 and a secondary coil L2 commonly connected to the plurality of lamps 10. The transformer 20 raises the AC waveform input via the primary coil L1 such that a high voltage AC waveform can be induced in the secondary coil L2 according to a winding ratio of the first coil L1 and secondary coil L2. Therefore, the high voltage AC waveform induced in the secondary coil L2 is output via the output lead N1 to the first electrode of each of the lamps 10.
The controller 40 converts an input voltage Vin provided from an external source into an AC waveform and then provides the AC waveform to the primary coil L1 of the transformer 20. The controller 40 includes at least one switching element (not shown) for converting the input voltage Vin to the AC waveform and a switching controlling unit (not shown) for controlling the switching element. The switching element is switched according to a switching control signal of the switching controlling unit to convert the input voltage Vin to the AC waveform and then to provide the AC waveform to the primary coil L1 of the transformer 20. The switching controlling unit generates such a switching control signal to control the switching element, and turns off the switching element according to the shutdown signal provided from the shutdown circuit 30, to cut off the high voltage AC waveform provided to the primary coil L1 of the transformer 20, thereby performing shutdown of the apparatus for driving a backlight.
The shutdown circuit 30, which is electrically connected to the output lead N1 of the transformer 20, generates a shutdown signal Vsd, in response to the high voltage AC waveform which is provided to the plurality of lamps 10, and then provides the shutdown signal to the controller 40. Namely, the shutdown circuit 30 generates the shutdown signal voltage Vsd to perform shutdown of the apparatus for driving a backlight in response to voltage variations caused by abnormal operation of the plurality of lamps 10.
FIG. 2 illustrates a detailed circuit diagram illustrating a shutdown circuit of FIG. 1. As shown in FIG. 2, the shutdown circuit 30 includes a voltage detection circuit 32 located between the output lead N1 of the transformer 20 and the ground source, and a comparator 34 located between the voltage detection circuit 32 and the controller 40. The voltage detection circuit 32 includes first and second capacitors C1 and C2, which are serially connected between the output lead N1 and the ground source, and first and second diodes D1 and D2, which are located between a voltage divider node N2 and the comparator 34, in which the voltage divider node N2 is between the first and second capacitors C1 and C2. The first and second capacitors C1 and C2 serve to smooth the voltage corresponding to the high voltage AC waveform output from the output lead N1 of the transformer 20, and to perform voltage division such that a divided voltage can be output to the voltage divider node N2.
The anode of the first diode D1 is electrically connected to the voltage divider node N2 and the cathode thereof is connected to the comparator 34. The cathode of the second diode D2 is connected to the voltage divider node N2 and the anode thereof is connected to the ground source. Such first and second diodes D1 and D2 rectify the voltage of the voltage divider node N2 and provide the rectified detection voltage to the comparator 34.
The comparator 34 includes first and second input leads, in which the first input lead is electrically connected to the cathode of the first diode D1 to input the detection voltage Vsen thereto, and the second input lead is electrically connected to the ground source to input voltage Vref thereto. Such a comparator 34 compares the detection voltage Vsen provided through the first input lead to the reference voltage Vref provided through the second input lead and then generates the shutdown signal voltage Vsd, which is provided to the controller 40. More specifically, the comparator 34 generates an OFF state shutdown signal if the detection voltage Vsen is greater than the reference voltage Vref or an ON state shutdown signal if the detection voltage Vsen is less than the reference voltage Vref. Such a shutdown circuit 30 detects voltage variation of the high voltage AC waveform, which is provided to the lamps 10, and then provides an OFF state shutdown signal to the controller, if each of the plurality of lamps 10 is normally driven. On the other hand, if each of the lamps 10 is abnormally driven, such as an open operation, the shutdown circuit 30 provides an ON state shutdown signal to the controller 40.
The apparatus for driving a backlight according to the related art converts the input voltage Vin to a high voltage AC waveform using the switching element of the controller 40 and the transformer 20, and then provides the AC high voltage to the plurality of lamps 10 in parallel such that each of the lamps 10 can be lit. While the plurality of lamps 10 is driven in parallel by the high voltage AC waveform, the detection voltage Vsen responds to the voltage variation of the high voltage AC waveform output from the transformer 20 and the shutdown circuit 30 provides the ON state shutdown signal to the controller 40 if the detection voltage Vsen is greater than the reference voltage Vref. Therefore, the controller turns off the switching element in response to the ON state shutdown signal such that the apparatus for driving a backlight can be shut down.
The detection voltage Vsen detected by the shutdown circuit 30 is affected by the electrical states of the plurality of lamps 10, such as open, short, and abnormal light. However, the detection voltage Vsen may be sensitive to peripheral temperature and/or changes of characteristics of circuit elements, which are included in the shutdown circuit 32. Therefore, although the plurality of lamps 10 are operating normally, the detection voltage Vsen can be affected by a peripheral temperature change and/or change of characteristics of the circuit elements in the shutdown circuit 32 such that the shutdown circuit 30 recognizes the plurality of lamps 10 to be in an abnormal state and then generates the ON state shutdown signal to shut down the backlight when the backlight should not be shut down. In another circumstance, when one of the plurality of lamps 10 is opened, the detection voltage Vsen can be affected by a peripheral temperature change and/or change of characteristics of the circuit elements in the shutdown circuit 32 such that the shutdown circuit 30 recognizes the plurality of lamps 10 to be operating normally and then generates the OFF state shutdown signal to maintain operation of the backlight when the backlight should be shut down. Consequently, the apparatus for driving a backlight of the related art has disadvantages in that it cannot correctly detect a state of the plurality of lamps 10 due to malfunction of the shutdown circuit 30, which is caused by change of peripheral temperature or change of characteristics of circuit elements in the shutdown circuit 32.

Apparatus and method for driving backlight


A lead-on-chip semiconductor device package is formed by attaching a lead frame having a single adhesive layer to a semiconductor chip. Electrode pads of the chip are electrically connected by bonding wires and mechanically connected by the adhesive layer to the lead frame, and then encapsulated by an encapsulant such as molding compound. The adhesive layer is formed from a liquid adhesive having a certain viscosity. The adhesive material is continuously applied to spaces between adjacent inner leads as well as the top surface of the leads and then cured. The leads are disposed at the same intervals and include some side leads with a larger width in order to form the adhesive layer with a uniform thickness. Thermoplastic resins are preferably used as the adhesive, but thermosetting resins may be used as well. In the case of thermoplastic resins, the temperature of a cure step is about 200.degree. C. and that of chip attachment step is about 400.degree. C.

1. Field of the Invention
The present invention generally relates to lead-on-chip semiconductor device packages, and more particularly, to a method and a resulting structure for attaching a semiconductor chip and the lead frame with a liquid adhesive layer.
2. Description of the Related Art
As the integration density of a semiconductor integrated circuit (IC) device increases, so does the size of the semiconductor chip. However, efforts continue in order to reduce the size of the semiconductor chip packages to meet the demand for smaller devices. To meet this need for package miniaturization, various packaging technologies have been developed. One of them is the lead-on-chip (LOC) package technology, in which a plurality of leads are disposed on and attached to an active surface of a semiconductor chip.
A primary advantage of the LOC package is that a chip mounting area, also known as a die pad or a lead frame pad, is not required since the chip is attached to the leads. Accordingly, the ratio of the size of the semiconductor chip to the size of the package is quite high. Other advantages of the LOC package include a high lead frame design flexibility, enhanced electrical performance, and the like.
A conventional LOC semiconductor device package is depicted in FIGS. 1, 2A and 2B. FIG. 1 shows a conventional LOC package 50 in a partially cut away perspective view; FIG. 2A illustrates, in an exploded perspective view, the spatial relationship between a semiconductor chip 10, an adhesive tape 30, and a lead frame 20, in the LOC package 50 shown in FIG. 1; and FIG. 2B is a more detailed view of the adhesive layer portion E of FIG. 2A.
With reference to FIGS. 1, 2A and 2B, the conventional LOC package 50 is constructed so that a plurality of inner leads 22 of the lead frame 20 are attached to an active surface of the semiconductor chip 10. Adhesion between the lead frame 20 and the semiconductor chip 10 is generally accomplished by multiple pieces of the adhesive tape 30. The adhesive tape 30 may comprise three layers, namely, a base film 32 and two adhesive layers 34, 36 formed respectively on each side of the base film 32. The base film 32 is typically a polyimide film and the adhesive layers 34, 36 are typically thermosetting epoxy resin layers. The semiconductor chip 10 has a plurality of electrode pads 12 which are centrally formed on the active surface. The inner leads 22 are spaced apart so that the central electrode pads 12 are exposed between the respective groups of inner leads 22, one on each side of the pads 12, and the inner leads 22 are electrically connected to the electrode pads 12.
Each of the inner leads 22 of the lead frame 20 is brought in close proximity to corresponding ones of the electrode pads 12, which are located along the center of the semiconductor chip 10, and thus the lead frame 20 can be electrically connected to the semiconductor chip 10 by means of short bonding wires 40.
A package body 52 is formed by encapsulants such as epoxy resins in order to protect the semiconductor chip 10, the inner leads 22, and the bonding wires 40 from hostile environments. After encapsulation, the dam bars 26 and lead frame salvage 28 shown in FIG. 2A are removed, and then outer leads 24, which extend from the package body 52 as shown in FIG. 1, are formed into an adequate shape for surface-mounting of the package 50 onto an external system board (not shown). Tie bars 27 support the package 50 during the shape-transformation of the outer leads 24.
The assembly process of the conventional LOC package 50 can be described as follows. First, a suitably sized three-layer adhesive tape 30 is positioned under the inner leads 22 of the lead frame 20, and the semiconductor chip 10 is then positioned under the three-layer adhesive tape 30. The adhesive tape 30 is attached to the inner leads 22 of the lead frame 20 by the first adhesive layer 34, and then the semiconductor chip 10 is attached to the adhesive tape 30 by the second adhesive layer 36, by applying pressure to the tape 30 at a predetermined temperature. Subsequent process steps, such as wire bonding interconnection, encapsulation, and outer lead frame forming are successively conducted.
However, the conventional LOC package suffers some drawbacks. One problem is the structure of adhesive tape itself. Since the adhesive tape consists of three layers, four interfaces exist between the semiconductor chip and the lead frame. The interfaces between two heterogeneous materials can produce thermo-mechanical stresses, and easily cause mechanical failures of the package such as cracks or delaminations. Moreover, the high water absorption property of the adhesive tape can degrade the reliability of the LOC package.
Another problem is found in the production process for the adhesive tape. The three-layer adhesive tape is made by successive sequences: first, adhesive materials are coated on one side of the base film 32 and cured to a so-called B-stage (i.e., a semi-solid state), and then also coated on the other side of the base film 32 and cured. Accordingly, the tape production process is complicated and the adhesive tape 30 is difficult to handle since it has adhesive layers on both sides thereof.
Moreover, the adhesive tape 30 contains an expensive inner polyimide film core, which consequently results in high production costs.

Lead-on-chip semiconductor device package having an adhesive layer formed from liquid adhesive and method for manufacturing the same


An object of the present invention is to provide a practical method for machining a sculptured surface. One of the characteristics of a concrete method for machining a sculptured surface so as to accomplish the object is that a patch table of a sculptured surface as surface information data for sculptured surface machining is configured so that a tool path can be generated using the inverse offset method for various surfaces such as a Bezier surface or a Ferguson surface and another characteristic is that over cutting during tool path generation on the basis of the inverse offset operation can be corrected.

The present invention relates to a method for machining a sculptured surface of a metallic, ceramic, or plastic material, and, more particularly, to a method for machining a sculptured surface suited to improving the machining accuracy and efficiency using the inverse offset method which is effective as a tool path generation method.
The conventional tool path generation method of the sculptured surface machining method for various tool shapes has not been perfected, though a solution has been proposed only for the spherical tool shape.
It has been proposed to reduce offset surfaces for various tool shapes and the "inverse offset method" for solving tool interference processing with necessary accuracy, "Machining System based on Inverse Offset Method", Journal of Precision Engineering, Kondo, et al, Vol. 54, No. 5, May 19, 1988, pp 167-172.
The concept of the inverse offset method is shown in FIG. 14 , in an offset surface can be generated by the enveloping surface of a cutting edge when an inverse tool moves on a surface with a required shape.
In the above prior art, the offset surface generation principle for the sculptured surface no consideration is given to the configuration of a final sculptured surface machining system; the correction method for generation of an offset surface on the basis of the inverse offset method; the actual machining accuracy of sculptured surface machining and an actually required memory reduction method for realizing a machining system in a computer; and the selection method for an appropriate tool, and there are problems imposed for realizing an actual machining system.

Method and system for machining a sculptured surface


A method of inhibiting hydrates in a fluid comprising water and gas comprising adding to the fluid an effective hydrate-inhibiting amount of a composition comprising one or more copolymers of N-alkyl (alkyl)acrylamide monomers and one or more cationic monomers selected from acid and alkyl chloride quaternary salts of N,N-dialkylaminoalkyl (meth)acrylates and N,N-dialkylaminoalkyl (meth)acrylamides.

Modern oil and gas technologies commonly operate under severe conditions during the course of oil recovery and production. For instance, high pumping speed, high pressure in the pipelines, extended length of pipelines, and low temperature of the oil and gas flowing through the pipelines. These conditions are particularly favorable for the formation of gas hydrates, which can be significantly hazardous for oil productions offshore or for locations with cold climates.
Gas hydrates are ice-like solids that are formed from small nonpolar molecules and water at lower temperatures and at increased pressures. Under these conditions, the water molecules can form cage-like structures around these small nonpolar molecules (typically dissolved gases such as carbon dioxide, hydrogen sulfide, methane, ethane, propane, butane and iso-butane), creating a type of host-guest interaction also known as a clathrate or clathrate hydrate. The specific architecture of this cage structure can be one of several types (called type 1, type 2, type H), depending on the identity of the guest molecules. However once formed, these crystalline cage structures tend to settle out from the solution and accumulate into large solid masses that can travel by oil and gas transporting pipelines, and potentially block or damage the pipelines and or related equipment. The damage resulting from a blockage can be very costly from an equipment repair standpoint, as well as from the loss of production, and finally the resultant environmental impact.
The petroleum industry gives particular attention to clathrate hydrates because the conditions are often favorable for the formation of hydrates and subsequent blockages. There are many instances where hydrate blockages have halted the production of gas, condensate, and oil. Obviously, the monetary consequences for each of these instances are amplified when considering the volumes of production in deepwater applications where tens of thousands of barrels of oil are routinely produced daily and the shut-ins can take months to remedy. Additionally, restarting a shutdown facility, particularly in deep water production or transportation facility, is extremely difficult because of the significant amounts of time, energy, and materials, as well as the various engineering implementations that are often required to remove a hydrate blockage under safe conditions.
The industry uses a number of methods to prevent blockages such as thermodynamic hydrate inhibitors (THI), anti-agglomerates (AA), and kinetic hydrate inhibitors (KHI). The amount of chemical needed to prevent blockages varies widely depending upon the type of inhibitor that is employed. Thermodynamic hydrate inhibitors are typically used at very high concentrations (glycol is often used in amounts as high as 100% of the weight of the produced water), while KHI's and AA's are used at much lower concentrations (0.3-0.5% active concentration) and are typically termed low dose hydrate inhibitors (LDHIs).
Commonly it is accepted that KHI's interfere with the growth of the clathrate hydrate crystal, thus preventing the formation of the hydrates.
While AA's allow the crystal to form and then disperse the small crystal, KHI's prevent the formation of hydrate crystals by disrupting the crystal growth. It is commonly accepted that AA's act as dispersants of the hydrate crystals into the hydrocarbon phase, and therefore have a limitation that the liquid hydrocarbon phase must be present. Typically the liquid hydrocarbon to water ratio should be no greater then one to one to ensure that there is enough hydrocarbon to contain the dispersed hydrate crystals. Unfortunately, this limitation reduces the opportunity in the oilfield as many wells increase the amount of water produced very rapidly after the water breakthrough is observed.
There are several important factors to consider when evaluating the capabilities and performance of a hydrate inhibitor, but the most significant and directly relevant of these are the two factors subcooling and the hold time. Subcooling refers to the degree to which the temperature of the system can be lowered below the theoretical hydrate formation temperature at a given pressure, and is often referred to in terms of a ΔT value. The hold time refers to the amount of time that this sub-cooled system can be kept hydrate-free in the presence of a particular KHI. Thus a good KHI should have a large ΔT subcooling temperature, and be capable of long hold times at that temperature.

This patent is subject to a terminal disclaimer.

Method of controlling gas hydrates in fluid systems


A system and method for enabling the behavior of temporal expressions to be analyzed for the evaluation of such expressions. The process of evaluating such expressions ultimately results in the construction of a finite state machine, such that the set of non-deterministic functions for describing the behavior of dynamic and relativistic systems is reduced to such a system. The behavior of the finite state machine can then be examined and analyzed. The present invention is useful for such applications as the examination of the temporal behavior of a DUT (device under test), as well as for examining the behavior of dynamic systems.

The present invention relates to a system and method for temporal language evaluation, and in particular, to such a system and method in which expressions constructed with the temporal language are evaluated for design verification.
Design verification is the process of determining whether an integrated circuit, board, or system-level architecture, exactly implements the requirements defined by the specification of the architecture for that device. Design verification for a device under testing (DUT) may be performed on the actual device, or on a simulation model of the device. For the purposes of explanation only and without intending to be limiting in any way, the following discussion centers upon testing which is performed on simulation models of the device.
As designs for different types of devices and device architectures become more complex, the likelihood of design errors increases. However, design verification also becomes more difficult and time consuming, as the simulation models of the design of the device also become more complex to prepare and to test.
The problem of design verification is compounded by the lack of widely generalizable tools which are useful for the verification and testing of a wide variety of devices and device architectures. Typical background art verification methods have often been restricted to a particular device having a specific design, such that the steps of preparing and implementing such verification methods for the simulation model must be performed for each new device.
The process of verifying a design through a simulation model of the device is aided by the availability of hardware description languages such as Verilog and VHDL. These languages are designed to describe hardware at higher levels of abstraction than gates or transistors. The resultant simulated model of the device can receive input stimuli in the form of test vectors, which are a string of binary digits applied to the input of a circuit. The simulated model then produces results, which are checked against the expected results for the particular design of the device. However, these languages are typically not designed for actual verification. Therefore, the verification engineer must write additional programming code in order to interface with the models described by these hardware description languages in order to perform design verification of the device.
Examples of testing environments include static and dynamic testing environments. A static testing environment drives pre-computed test vectors into the simulation model of the DUT and/or examines the results after operation of the simulation model. In addition, if the static testing environment is used to examine the results which are output from the simulation model, then errors in the test are not detected until after the test is finished. As a result, the internal state of the device at the point of error may not be determinable, requiring the simulation to be operated again in order to determine such internal states. This procedure consumes simulation cycles, and can require the expenditure of considerable time, especially during long tests.
A more useful and efficient type of testing is a dynamic testing environment. For this type of environment, a set of programming instructions is written to generate the test vectors in concurrence with the simulation of the model of the DUT and while potentially being controlled by the state feedback of the simulated device. This procedure enables directed random generation to be performed and to be sensitive to effects uncovered during the test itself on the state of the simulation model of the device. Thus, dynamic test generation clearly has many advantages for design verification.
Within the area of testing environments, both static and dynamic testing environments can be implemented only with fixed-vector or pre-generation input. However, a more powerful and more sophisticated implementation uses test generation to produce the environment.
One example of such a test generator is disclosed in U.S. Pat. No. 6,182,258, filed on Feb. 6, 1998, incorporated by reference as if fully set forth herein. This test generation procedure interacts with, and sits as a higher level over, such hardware description languages as Verilog and VHDL. The test generation procedure is written in a hardware-oriented verification specific object-oriented programming language. This language is used to write various tests, which are then used to automatically create a device verification test by a test generator module. A wide variety of design environments can be tested and verified with this language. Thus, the disclosed procedure is generalizable, yet is also simple to program and to debug by the engineer.
This language features a number of elements such as structs for more richly and efficiently describing the design of the device to be simulated by the model. Unfortunately, the disclosed language and resultant test generation environment does not include features for testing the state of the device over time. Such testing is performed by sampling the values for various variables at different times, either according to some triggering event or at predetermined times, and is termed xe2x80x9ctemporal coveragexe2x80x9d. Temporal coverage is a collection of coverage information based on the occurrence of some pattern in time, with the pattern itself being defined according to a temporal language. Temporal coverage differs from automatic coverage, which is triggered by the appearance of a line of code or other static event, in that temporal coverage is driven by the occurrence of events in time. Temporal coverage enables the behavior of the device to be monitored over time during the testing period, particularly since a circuit or other DUT cannot be exhaustively simulated, such that all relevant states are tested. Analysis of the coverage enables the designer to determine which states of the device require further testing. Such analysis can be facilitated with abstract state machines.
Various temporal languages are known in the background art, yet the construction and evaluation of expressions in such languages for the purpose of temporal coverage for design verification has so far proven to be highly limited. In particular, there is a requirement in design verification for describing and monitoring the behavior of concurrent systems such as digital hardware or communication protocols. Currently, such behavior is commonly characterized in the background art (as discussed in standard texts on the subject such as that of Emerson A., in The Handbook of Theoretical Computer Science, Elsevier, 1990) according to sequences of configurations of the system under consideration, or according to sequences of events occurring within the system. However, a more useful solution to this problem would enable both methods to be used when specifying behavior in temporal expressions.
The task of evaluating temporal expressions in a programming system is more complicated than that of evaluating logical or arithmetic expressions since a sequence of states, or snapshots of the program memory, must be considered, rather than a single state. Temporal expression evaluation commences at some point during program execution, and continues over a number of cycles of a clock defined by the program until the expression either succeeds or it fails. Success indicates that the preceding sequence of program states complies with, or satisfies, the mathematical definition of the temporal expression; failure indicates the converse.
Typically, the evaluation of a temporal expression is performed by using an abstract state machine, or automaton. These automata preserve only the minimum necessary information at each state, and in the transitions between states, rather than a complete snapshot of the program memory. Programming languages such as C or Verilog provide mechanisms for constructing automata that may represent temporal behavior by explicitly enumerating their states and the transitions between states. Other languages such as those based on the temporal logics CTL and LTL allow one to specify temporal behavior in a non-procedural declarative style by writing down a formula. Temporal e is a language of this latter kind (see for example SMVxe2x80x94xe2x80x9cSymbolic Model Checkingxe2x80x9d Ken McMillan, Kluwer Academic Press 1993; Sugarxe2x80x94xe2x80x9cRule Base: an industry oriented formal verification toolxe2x80x9d I. Beer et al. Proceedings DAC, ACM June 1996).
Since a temporal expression, or formula, represents the behavior implicitly it is necessary to devise a mechanism to recognize or implement that behavior. For temporal logics like CTL and LTL the common approach is to construct an automaton from the text of the formula via a procedure known as a tableau constructionxe2x80x94so called because the tree like structure the procedure builds is known as a proof tableau in formal logic. For LTL and CTL the construction always gives rise to a finite automaton, but the details vary considerably because the procedures depend intimately on the mathematical semantics of the language concerned. For references to the background art see for example the work of Clarke et al. in Proceedings of Computer-Aided Verification, Springer-Verlag, 1994.
While LTL and CTL are targeted at formal verification, the e temporal language is primarily directed at simulation. While still applicable to formal verification, this language has proven to be easier and more intuitive to use, particularly for simulation, but still lacks a construction scheme.
The system and method of the present invention enables the behavior of temporal expressions to be analyzed for the evaluation of such expressions. The process of evaluating such expressions ultimately results in the construction of a state machine having a finite control structure. This state machine may optionally be deterministic, but alternatively may be non-deterministic. The behavior of the state machine can then be examined and analyzed. The present invention is useful for such applications as the examination of the temporal behavior of a DUT (device under test), as well as for examining the behavior of dynamic systems such as communication protocols in telephonic systems or internet applications, embedded software in command and control devices, and so on.
According to the present invention, a method for analyzing a temporal expression is provided, the method comprising: parsing the temporal expression to form a hierarchical tree, each node of the hierarchical tree containing a subexpression of the temporal expression; propagating a sampling event to each node of the hierarchical tree according to at least one Sampling rule; and determining each transition from each node of the hierarchical tree to a successor node according to at least one transition Step rule to analyze the temporal expression.
Hereinafter, the term xe2x80x9ccomputing platformxe2x80x9d refers to a particular computer hardware system or to a particular software operating system. Examples of such hardware systems include, but are not limited to, personal computers (PC), Macintosh(trademark) computers, mainframes, minicomputers and workstations. Examples of such software operating systems include, but are not limited to, UNIX, VMS, Linux, MacOS(trademark), DOS, FreeBSD, one of the Windows(trademark) operating systems by Microsoft Inc. (USA), including Windows NT(trademark), Windows95(trademark) and Windows98(trademark).
The method of the present invention could also be described as a plurality of instructions being performed by a data processor, such that the method of the present invention could be implemented as hardware, software, firmware or a combination thereof. For the present invention, a software application could be written in substantially any suitable programming language, which could easily be selected by one of ordinary skill in the art. The programming language chosen should be compatible with the computing platform according to which the software application is executed. Examples of suitable programming languages include, but are not limited to, C, C++ and Java.

System and method for analyzing temporal expressions


Provided is a method of removing noise from digital moving picture data reducing the number of frames used in a temporal filtering operation and able to detect motion between frames easily. The method comprises a method of spatial filtering, a method of temporal filtering, and a method of performing the spatial filtering and the temporal filtering sequentially. The spatial filtering method applies a spatial filtering in a YCbCr color space, preserving a contour/edge in the image in the spatial domain, and generating a weight that is adaptive to the noise for discriminating the contour/edge in the temporal filtering operation. The temporal filtering method applies temporal filtering based on motion detection and scene change detection, compensating for global motion, the motion detection considering the brightness difference and color difference of the pixels compared between frames in the temporal filtering operation, and a weight that is adaptive to the noise for detecting the motion in the temporal filtering operation. The spatial filtering method is preferably performed first, and the temporal filtering method is performed with the result of the spatial filtering.

This application claims the priority of Korean Patent Application No. 2003-90032, filed on Dec. 11, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to digitally encoding a moving picture, and more particularly, a method of removing noise in digital moving picture data.
2. Description of the Related Art
Since digital moving picture data takes up a large of data, the data should be compressed in order to be transmitted and stored efficiently. Thus technologies for improving the reproduced image quality of a video signal and improving data compression rate are essential for enhancing the competitiveness of related products. Compression algorithms such as moving picture experts group (MPEG)-2 have been adopted as compression methods in digital multimedia products requiring high definition, such as high definition TV (HDTV) and digital versatile discs (DVDs).
Due to the technical limits of practical image input systems, of transmission channels, and of transmitters and receivers that handle the moving picture data, noise is inevitably generated during the obtaining, transmitting and receiving of the moving picture data.
The noise can be defined as a set of pixels whose brightness changes abruptly in time and which are spatially distributed randomly (they do not form a set of meaningful geometrical shapes). Mosquito noise is a type of random noise that occurs along edges in images that have been compressed using DCT.
If we plot the intensity curve in temporal space, of the image brightness at a given spatial position, a noise pixel can be observed as an abrupt transition in the intensity curve. A straightforward approach to reduce noise is to use some kind of temporal averaging filtering techniques to remove these abrupt transitions. However, a fast moving pixel (e.g., part of a moving object in a scene) also shows a similar behavior to noise, i.e. the intensities of a fast moving pixel change very sharply during a short time period. Simple averaging techniques will result in a blur or even lost of the motion objects in the restored scene. Thus separating the motion effects from noise effects becomes a challenge.
In principle, three categories of pixels need to be dealt with: static pixels, moving pixels, and noisy pixels. A basic difficulty is to avoid treating moving pixels as noisy pixels. If motion estimation fails for fast motion pixels, such as the fast moving object in a scene, then it will incorrectly filter these pixels as if they were noise related. If we could correctly classify pixels into the three categories then we may be able to avoid some expensive computation (avoid motion estimation for static pixels) as well as improve the filtering.
The noise included (e.g., compressed) in an image (frame) sequence, (in the digital moving picture data), degrades the reproduction image quality and the compression rate because the noise is recognized as a (radio frequency) component of a signal. Noise increases the bandwidth required for digital representation of images. Since the noise is recognized also as data, the valid picture data must be compressed more in order to satisfy a given bit rate; however, further compression causes increased coding artifacts such as blocking artifacts.
The compression rate of the image sequence can be improved greatly and the image quality can be improved by compressing the data (according to the MPEG-2 method) after the noise is removed in advance using an effective noise reduction algorithm. There are conventional noise reduction algorithms such as spatial filtering, temporal filtering, and spatio-temporal filtering.
Because spatial filtering is based on a stationary model, a contour of the reproduced image cannot be preserved after noise is removed. Although an additional contour-adaptive filter may be used, such are not very effective in a case where a threshold for discriminating a contour line is fixed as a constant without regard to the degree of noise, or in a case where a color spot is generated. A color spot is generated because different characteristics of channels, which construct a color filter array (CFA) on a charge-coupled device (CCD) sensor, caused by different brightness are processed in the same way regardless of the brightness.
Although spatial filtering is an effective way of removing noise when a still image is processed. if a video image sequence is filtered using the spatial filtering method, the degree of noise removal can differ for each frame. The differences in the degree of noise removal can be represented as a flickering phenomenon when the video data is reproduced as a video image sequence. Thus, in order to improve the performances of the conventional spatial filtering process, the threshold value for determining the contour line according to noise energy (more specifically, noise energy variance) should adaptively change, and in order to remove the color spots and flickering phenomenon, a temporal filtering method is used in addition to the spatial filtering operation.
In temporal filtering, a motion compensation method is used. However, in order to take the motion compensation into consideration, the motion of a subject should be estimated for each frame, the filtering should be performed along a motion trace, and more calculation operations are additionally required to estimate the motion.
A temporal filtering method based on a motion detection algorithm has been used to reduce the error in motion compensation and to reduce calculation load. The efficiency of this temporal filtering based on a motion detection algorithm is largely dependent upon the robustness of the motion detection algorithm. However, since the motion in the color image is determined by brightness difference according to the typical motion detection algorithm, the algorithm cannot recognize motion indicated by color difference. Thus, when the brightness difference between the subject and background is not large enough, errors in detecting the motion may occur.
In order to solve the above problems, there is a method of detecting motion by detecting differences in magnitudes (brightness) and angles (color) of RGB vectors by consideration of vector characteristics of the color image. This method can be used regardless of the calculation load and memory capacity when an input signal of the system is an RGB signal or the algorithm is processed by software; however, there is a limit to this method's practicality when the algorithm is processed using hardware.
The YCbCr domain (hereinafter, referred to as the YCbCr color space) is the most commonly used color coordinate system as it is useful for compatibility with monochrome video and interoperability with professional video processing equipment. Luminance (Y) contains most of the spatial information to which the human eye accords importance due to its sensitivity to detail. The chrominance channels (Cb, Cr, blue-difference and red-difference respectively) add color information. Where most of the input signals are signals of such YCbCr form, input signals of YCbCr form have to be converted into RGB color space signals in order for the RGB vector calculation operation to be performed. In addition, since non-linear calculation is required to calculate an inverse function of a cosine or a sine function for calculating the difference of RGB vector angles (colors), the hardware's complexity increases.
When motion is detected using the differences in angles (color) of RGB vectors, it is difficult to set a threshold value to be used as a reference to discriminate the detected signals. The threshold value greatly affects the performance of filtering, and thus, if the threshold value is too large, an artifact such as a motional residual image can be generated, and if the threshold value is too small, the noise is not removed. For example, in the motion detection methods using the differences in angles (color) of the RGB vectors, when an input value of a cosine function is nearly 0 (zero), a difference between output values is small, and thus the threshold value should be set precisely down to decimal points to detect the movements effectively. In order to overcome the difficulties in determining the threshold value and remove the noise effectively, relatively large numbers of frames must be processed. Thus, a large capacity of memory is required, and the hardware complexity increased.
Besides the above problems, in the temporal filtering based on motion detection, a threshold value of motion detection should adaptively change according to scene detection. Otherwise, if a general sequence including scene data is processed using only motion detection, in a case where the brightness or the colors of the pixels included in adjacent frames of different scenes are similar to each other, the different scenes may be filtered and different scenes can be mixed in a filtered frame. Therefore, to improve the performances of conventional temporal filtering based on motion detection, a scene change detection algorithm should be additionally used.
The conventional spatio-temporal method of filtering combining the above two filtering methods is a way that expands the spatial filtering to the temporal domain. Although noise can be removed effectively, the method includes the limitations of both temporal filtering and spatial filtering.

Method of removing noise from digital moving picture data


A mail box access replacement cover assembly for use on existing and new masonry mounted mail boxes having a mail box and newspaper insert. A two-part adjustable assembly is secured on the masonry support surface aligned to overlie the mail box and newspaper tube openings respectively. A decorative replacement access door for the mail box and paper receiving tube are respectively secured to the assembly by decorative cover fill plate selectively positioned therebetween.

1. Technical Field
This invention relates to masonry mounted mail boxes and specifically mail box access doors and newspaper tube receptacles typically found therein.
2. Description of Prior Art
Prior art masonry mounted mail boxes are usually formed from bricks or stone in the form of a free standing pillar with a regulation metal mail box inserted therein. Additionally, a newspaper receiving tube is provided below the mail box insert. Heretofore such standard metal mail box inserts rust and eventually fail as well as being unsightly over time. Aluminum and plastic mail boxes are available for new construction and mail box covers have been developed to provide a decorative overlay for a standard mail box, see U.S. Pat. Nos. 4,375,869, 5,035,356, 5,346,125, 5,946,838 and 6,123,257 and U.S. Patent Publication 2005/0067480 A1.
In U.S. Pat. Nos. 4,375,869, 5,035,356, 5,346,125 and 5,946,838 a variety of mail box covering assemblies are shown that provide for a number of different structural and decorative ways to cover a standard mail box such as wood slats and/or removable designer decorative panels see in U.S. Pat. Nos. 4,375,869 and 5,346,125.
A masonry mail box assembly with a replaceable insert can be seen in U.S. Pat. No. 6,123,257 which provides for a liner within a masonry support with a mail box inserted therein.
U.S. Patent Publication 2005/0067480 discloses a removable decorative mail box cover for the door thereof.

Mail box cover access and insert for masonry mail boxes


A system and method for specifying custom qualifiers for explain tables allows a user to designate selected explain tables for which the user wishes to view statements. A query explain program is provided and configured with an explain table qualifier designation module for receiving a user designation of a query explain table to reference. The user selects a function of the query explain program to perform and then designates the qualifier of the query explain table to be referenced. The function is then performed in conjunction with the contents of the selected query explain table.

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
1. The Field of the Invention
The present invention relates generally to computer-implemented database systems. More specifically, the present invention relates to a system and method for specifying custom qualifiers for explain tables in a computer-implemented database system.
2. The Relevant Technology
Databases are computerized information storage and retrieval systems. A Relational Database Management System (RDBMS) is a database system which uses relational techniques for storing and retrieving data. Relational databases are organized into tables consisting of rows (tuples) and columns of data. A database typically includes many tables, and each table includes multiple rows and columns. The tables are conventionally stored in direct access storage devices (DASD), such as magnetic or optical disk drives, for semi-permanent storage.
Generally, users communicate with an RDBMS using a Structured Query Language (SQL) interface. The SQL interface allows users to create, manipulate, and query a database by formulating relational operations on the tables, either interactively, in batch files, or embedded in host languages such as C and COBOL. SQL has evolved into a standard language for RDBMS software and has been adopted as such by both the American National Standards Institute (ANSI) and the International Standards Organization (ISO).
The SQL standard provides that each RDBMS should respond to a particular query in the same way, regardless of the underlying database. However, the method that the RDBMS actually uses to find the requested information in the database is left to the RDBMS. Typically, there is more than one method that can be used by the RDBMS to access the requested data. The RDBMS, therefore, attempts to select the method that minimizes the computer time and resources (i.e. cost) for executing the query.
The RDBMS determines how to execute the SQL statements. The set of steps created by the RDBMS for executing the SQL statements is commonly referred to as the xe2x80x9caccess path.xe2x80x9d In other words, the access path is a sequence of operations used by the RDBMS to obtain the data requested by the SQL query. Depending on the access path, an SQL statement might search an entire table space, or, alternatively, it might use an index. The access path is the key to determining how well an SQL statement performs. The description of the access path is stored in a plan table, which typically stores the access path data for a plurality of SQL statements.
In addition to determining the access path, some databases estimate the cost for executing each SQL statement. The estimated costs are typically stored in a statement table (as in the case of DB2(copyright) for OS/390(copyright)) or a similar table within the database. Like the plan table, the statement table stores the estimated statement costs for a plurality of SQL statements.
Databases also typically include statistics for such database objects as table spaces, indexes, tables, and columns. For example, in the case of a table, the statistical data may include the number of pages that contain rows of the table, the number of rows and columns in the table, as well as various other statistical data. The statistics are typically derived from the RDBMS xe2x80x9ccatalog,xe2x80x9d which is an object that describes the entire database.
The above-described access path data, statement cost data, and object statistics data (referred to collectively as xe2x80x9cquery explain dataxe2x80x9d) assist the user in analyzing and improving the performance of SQL statements. For example, a query with a higher-than-average statement cost might alert the user to inefficiencies in the access path. By viewing the access path data, the user can selectively make changes to the query and/or the database, such as by adding an index in order to avoid a table space scan. The object statistics data similarly assists the user by describing the structure and organization of the database.
Unfortunately, analyzing SQL query performance is currently too time-consuming and complex for the average user. Typical systems include hundreds or thousands of query statements. Identifying the one or more statements that need to be improved can be a difficult task. In conventional systems, the user must manually locate the relevant query explain data in a plurality of tables, e.g. the plan table, the statement table, the function table, and the catalog tables, which can be tedious and time-consuming.
Moreover, each of the tables typically stores information corresponding to many different statements and objects. Consequently, the tables are often very large, making it difficult to locate the desired data. Likewise, the tables are often cryptic and hard to understand, even for database experts. For example, the plan table typically includes sixty or more columns and hundreds or thousands of rows. The access path data is stored in a tabular format, which, although easily understood by the RDBMS, is often too complicated to be effectively analyzed.
Furthermore, the query statements to be filtered are typically included in a number of packages and plans. A package is a collection of query statements found in a single application program. A plan is also a collection of query statements, but may include statements from one or more application programs. In large-scale database systems, the number of plans and packages is correspondingly large. Thus, a difficulty arises when trying to locate a particular package or plan for purposes of analyzing the query statements contained therein.
Similarly, query explain tables can become extremely large. Accordingly, different query explain tables may be used for each package or for each plan. In one arrangement commonly used, each individual user within a database system is assigned a unique label and all packages and plans generated by the user employ one or more query explain tables unique to the user. The label given the user is known as a high level qualifier. The high level qualifier is generally a part of a naming system or convention in which a portion of the label, typically the beginning portion, references the maker or user, and subsequent portions identify the type of the component being labeled.
Currently under this arrangement, query explain tables assigned to a user are automatically assigned the user""s high level qualifier at the time of binding of the query explain tables. When a user wishes to reference query explain data, the query explain program determines who the user is, typically by requesting that the user designating his high level qualifier, and automatically calls up query explain tables and other query explain data corresponding to the user""s high level qualifier.
Problems arise when the user wishes to name a query explain table with a labels other than the user""s high level qualifier. Current query explain programs do not have the flexibility to allow a user to do so, nor do they allow a user to individually access user-named tables. Additionally, if a user wishes to examine query explain data generated by another user, for instance, where a system administrator desires to ascertain where slowdowns in a database are occurring, the user is unable to individually reference the query explain tables generated by others while logged in under the user""s own account. Accordingly, when a user wishes to reference explain tables that were not generated under the user""s high level qualifier or other user code, the user is forced to log out and log in under the account corresponding to the user code of the tables that are desired to be referenced.
In accordance with the above discussion, it should be readily appreciated that a need exists for a query explain system that allows users to designate the labels of query explain tables. What is similarly needed is a manner of allowing users, from within a query explain program, to reference a selected query explain table other than the default table using the particular high level qualifier or other label of the query explain table.
The present invention solves the foregoing problems by providing a system, method, and article of manufacture for specifying a custom qualifier for a query explain table. In disclosed embodiments, query explain tables are assigned custom qualifiers, and users are allowed to reference any query explain tables for which they are granted access privileges by specifying the qualifier or other identifier of the query explain table the user wishes to access.
In one aspect of the invention, an apparatus for accessing a user-selectable query explain table includes therein modules of operational data and executable code for execution by the processor. In one embodiment, the modules include a query explain program for relaying information regarding query execution to a user. Preferably, the query explain program is configured to access one or more query explain tables generated in accordance with operation of the database system.
Preferably, the modules also comprise an explain table qualifier designation module communicating with the query explain program and configured to receive a user designation of a selected query explain table to be accessed by the query explain program. The modules may also comprise an explain table access module configured to access the selected query explain table in response to the user designation.
In one embodiment, the user designation of the selected query explain table comprises the designation of a high level qualifier uniquely identifying the selected query explain table. The high level qualifier may identify a maker of the explain table.
Additionally, the explain table qualifier designation module may comprise a window accessible from the query explain program. Preferably, the window comprises a control mechanism for receiving the user designation of a selected query explain table.
The query explain table may comprise a plan table, a statement table, a function table, or other types of query explain data. The query explain table is preferably accessed by the query explain program for a plurality of different functions including displaying query access path data to the user.
In another aspect of the invention, a method of accessing a user-selectable query explain table includes a step of receiving within a query explain program a user designation of a selected query explain table generated in accordance with operation of the database system. The method also preferably comprises referencing the selected query explain table in response to receiving the user designation of the selected query explain table.
The method may also comprise generating the selected query explain table and assigning the query explain table a user-generated high level qualifier. In one embodiment, the query explain table is selected from the group consisting of a plan table, a statement table, and a function table. Additionally, referencing the selected query explain table may comprise automatically referencing the selected query explain table in order to achieve a function of the query explain program. The function may comprise displaying query access path data to the user.
The method may further comprise generating a graphical user interface (GUI) window accessible from the query explain program, the GUI window comprising a control mechanism for receiving the user designation of a selected query explain table. In one embodiment, receiving a user designation of a selected query explain table comprises receiving a high level qualifier uniquely identifying the selected query explain table. Additionally, the high level qualifier may designate a maker of the query explain table.
In yet another aspect of the invention, an article of manufacture comprises a program storage medium readable by a processor and embodying one or more instructions executable by the processor to perform the above-described method for filtering a plurality of groups of query statements according to associated identification data.
These and other objects, features, and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

System and method for specifying custom qualifiers for explain tables

International Business Machines Corporation


Techniques are disclosed for a link state routing protocol adjacency state machine. The adjacency state machine ensures that first and second logical links using different networking protocols are established on a single physical link between two network devices prior to indicating adjacency between the network devices. In some examples, the adjacency state machine determines that both the first and second links are active in response to determining that hello messages are generated by both network devices for both links. In some examples, the adjacency state machine determines that both the first and second logical links are active upon expiration of a predetermined time corresponding to a time required for a duplicate address detection (DAD) operation to complete. In some examples, the first and second logical links use Internet Protocol version 4 (IPv4) and Internet Protocol version 6 (IPv6), respectively.

A computer network is a collection of interconnected computing devices that exchange data and share resources. In a packet-based network, such as the Internet, the computing devices communicate data by dividing the data into small blocks called packets, which are individually routed across the network from a source device to a destination device. The destination device extracts the data from the packets and assembles the data into its original form. Certain devices within the network referred to as routers use routing protocols to exchange and accumulate topology information that describes the network. This allows a router to construct its own routing topology map of the network. Upon receiving an incoming data packet, the router examines keying information within the packet and forwards the packet in accordance with the accumulated topology information.
Many routing protocols use flooding-based distribution mechanisms to distribute topology information to routers within the network. These routing protocols may rely on routing algorithms that require each of the routers to have synchronized routing topology information. For example, Open Shortest Path First (OSPF) and Intermediate System to Intermediate System (IS-IS) routing protocols are link state protocols that use messages conveying link state representations to ensure the routing topology is synchronized with respect to available interfaces, metrics and other variables associated with network links. For example, OSPF utilizes Link State Advertisements (LSAs) while IS-IS uses Link State Protocol Data Units (PDUs) to exchange information. Messages used to convey link state representations in accordance with a link state routing protocol are generally referred to herein as link state advertisements (LSAs), and OSFP LSAs and IS-IS LS PDUs are examples of such LSAs.
A router operating in accordance without a link state routing protocol may flood link state advertisements throughout the network such that every other router receives the link state advertisements. In network topologies where routers are connected by point-to-point connections, each router floods link state advertisements to adjacent routers reachable on each interface to ensure synchronization. In networks using multi-access media, such as an Ethernet network, the routers within the network flood the link state advertisements to all other routers. In either case, the receiving routers construct and maintain their own network topologies using the information received via the link state advertisements. These link state advertisements may include information identifying constraints employed for selecting a path through a network in accordance with a link state protocol.
A router operating in accordance with link state routing protocol may use different networking protocol versions. For example, a router may use Internet Protocol version 4 (IPv4). IPv4 is a 32-bit logical addressing system that enables the forwarding of packets from a source host to the next router that is one hop closer to the intended destination host on another network. As another example, a router may use Internet Protocol version 6 (IPv6). IPv6 is intended to replace IPv4 and provides a larger address space (e.g., 128 bits) compared to the 32-bit address space employed by IPv4, permits hierarchical address allocation, and simplifies multicast addressing. Many networks are replacing IPv4 with IPv6 because of the numerous advantages IPv6 provides. IPv6 is not inter-operable with IPv4. However, many networks provide backwards compatibility with IPv4 by requiring network devices to concurrently support the processing and forwarding of network traffic addressed using either the IPv4 or the IPv6 networking protocols. As such, the router may obtain and allocate, for a link, both an IPv4 address and an IPv6 address, advertising the link via the link state routing protocol each time the IPv4 address and the IPv6 address is allocated.

Link state routing protocol adjacency state machine


Hardware circuitry defines logic for both Sbox generation and inverse Sbox generation via generating a multiplicative inverse matrix as a truth table for data. The hardware circuitry receives input plain text to be encrypted. The hardware circuitry divides the input plain text to be encrypted. The hardware circuitry feeds multiplicative inverse values generated from the input plain text to a transformer module for performing affine to encrypt the plain text data. The hardware circuitry receives encrypted data to be decrypted. The hardware circuitry divides the encrypted data to be decrypted. The hardware circuitry feeds multiplicative inverse generated from the encrypted data to the transformer module for performing inverse affine to decrypt the encrypted data.

Hardware security is becoming more important and more sophisticated over time as a result of the increased transmission of data using computing systems in everyday life (and the corresponding rise of more sophisticated illicit efforts to gain access to these data transmissions). For example, the increased prevalence of digital transactions that include sensitive information (such as financial information) are increasingly under attack by sophisticated criminals. Toward this end, hardware security often includes security measures that abide by advanced encryption standard (AES). AES includes specifications for encrypting data as set by the United States National Institute of Standards and Technology (NIST). AES relates to using ciphers such as block ciphers, which include deterministic algorithms to encrypt blocks via symmetric keys. Specifically, AES relates to using a member of the Rijndael block cipher.

Combined SBox and inverse SBox cryptography

International Business Machines Corporation