The present invention relates to a programmable mask used in a photolithography process for fabricating a biomolecule array and a method of fabricating a biomolecule array using the same and, more particularly, to a programmable mask which can increase a contrast ratio of transmittance versus shielding of light incident to a liquid crystal which constitutes each pixel by irradiating parallel ultraviolet (“UV”) light generated from an external parallel light exposure device to a certain cell and using a vertically aligned liquid crystal panel or an LC panel having no spacer, and a method of fabricating a biomolecule array using the same.

1. Field of the Invention
The present invention relates to a programmable mask used in a photolithography process for fabricating a biomolecule array and a method of fabricating a biomolecule array using the same and, more particularly, to a programmable mask which can increase a contrast ratio of transmittance versus extinction of light incident to a liquid crystal which constitutes each pixel by irradiating parallel ultraviolet ("UV") light generated from an external parallel light exposure system to a certain pixel and using a vertically aligned liquid crystal panel or an LC panel having no spacer, and a method of fabricating a biomolecule array using the same.
2. Discussion of Related Art
A region comprised of one kind of biomolecule in a biomolecule array formed on a substrate is hereinafter referred to as a cell for convenience and clarity.
Researches on work for performing simultaneously various kinds of experiments using the biomolecule or polymer array have been heavily performed. The biomolecule array includes a polypeptides array, a nucleic acid (DNA, RNA) array, etc. One of the most important things for such a research is to effectively form a low-cost and high-purity array on a substrate.
A typical method of fabricating the biomolecule or polymer array includes a spotting method in which a micro robot moves three-dimensionally to selectively drop a biochemical material onto a desired location, a photolithography method which selectively irradiates light to a desired location to change a surface so that a coupling reaction between the surface and the biomolecule occurs at a certain location, and an electronic addressing method which adjusts electrode voltage of a microelectrode array such that a biomolecule is fixed only to a certain electrode.
The spotting method includes a contact printing method which stains with a solution as a marker is stamped on a paper, and a non-contact printing method which drops a solution. The contact printing method is performed in order of loading, printing and washing by an XYZ robot. Since a pin having a groove formed on its end like a point of a fountain pen is used, it is possible to control sample volume with reproducibility, and loading a sample once makes it possible to print several times. However, there is a disadvantage in that it is a limitation to increasing the number of arrays per unit area. The non-contacting printing method includes a dispensing method and an ink-jet printing method. The dispensing method is a method which drops a solution as in a micropipette, and the ink-jet printing method is a method which gives fine pressure to an ink reservoir to spout a solution out. The ink-jet printing can finely adjust a sample solution to a nano liter level, thereby increasing the number of arrays per unit area. However, since each sample solution needs the ink reservoir and the number of the ink reservoir to be mounted to the robot is limited, the ink-jet printing method can be used only in the case of fabricating an array using a small number of sample solutions.
The electronic addressing method is a method which fixes a biomolecule using a voltage control function of a microelectrode array, and includes a method which moves the biomolecule with an electric charge to an electrode surface to cause physical chemical coupling, and a method which fixes the biomolecule inside a thin film when the thin film is formed by electrochemical deposition (Consnier, "Biomolecule immobilization on electrode surfaces by entrapment or attachment to electrochemically polymerized films. A view" Biosensors & Bioelectronics 14. pp. 443˜456 (1999)). For example, since a DNA has a strong negative charge, if an electrode has a positive charge, the DNA moves toward the electrode. At this time, if the physical chemical coupling is formed between the DNA and the electrode, the DNA is fixed to the electrode (U.S. Pat. No. 5,605,662). However, the electronic addressing method has problems in that it is more difficult to apply when the number of arrays is many, and it basically needs a microelectrode array. Besides, a method which electrochemically varies pH around the electrode to selectively fix a location of the biomolecule was developed. Using this concept, Combimatrix Corporation has suggested a method which location-selectively synthesizes an oligonucleotide to a microelectrode (U.S. Pat. No. 6,090,302, smith et al.). However, this method also has problems in that yield of each reaction is low and purity of each cell is low.
As a conventional method of fabricating a biomolecule array, a method using a liquid crystal display ("LCD") type programmable mask which can control transmittance of light instead of a photo mask and a micromachined mirror array has been suggested (U.S. Pat. No. 6,271,957, KR Patent No. 2001-0002915). However, all of the conventional methods described above just suggest only a concept using an LCD without any description on LCD requirement for patterning biomolecules, i.e., an LCD type to improve a contrast ratio which is most important in transmittance and extinction of light, and incident UV-light requirement, i.e., any statement that parallelism of incident light is important. Furthermore, U.S. Pat. No. 6,271,957 suggests only a simple concept without any statement that a spacer degrades improvement of contrast.
A biomolecule array is formed on a substrate by the photoreactions repeatedly caused by controlling light transmittance of each pixel of the LCD type programmable mask. It is ideal that a light extinction rate of a pixel which light should be shielded is close to zero (0). In this case, contrast will be infinite, and if such an LCD is employed, a programmable mask will be ideal, and an ideal DNA microarray will be fabricated.
However, since ideal contrast does not exist, a programmable mask which satisfies the followings is needed to get the maximum contrast ratio.
First, in order to increase the contrast ratio, parallel UV-light which is vertically irradiated to an LCD panel is needed. Second, in order to increase the contrast ratio, a liquid crystal should be aligned vertically. Third, in order to increase the contrast ratio, an LCD panel having no spacer should be used.
In order to form the biomolecule or polymer array as described above, an LCD type programmable mask which can resolve the above problems should be used.

Programmable mask and method of fabricating biomolecule array using the same

Electronics and Telecommunications Research Institute


Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.

The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for performing concept analysis operations utilizing accelerators.
Everyday life is dominated by information technology and systems for obtaining information and knowledge from collections of data. For example, search engines operate on large collections of data to obtain information related to a search query. Question and Answer (QA) systems, such as the IBM Watson™ QA system available from International Business Machines (IBM) Corporation of Armonk, N.Y., operate on a corpus of documents or other portions of information to answer natural language questions. Moreover, many social networking services represent their users, communications, and the like, as large data sets. Many times it is important to perform knowledge extraction, reasoning, and various other analytics on these large scale data sets so as to facilitate the operation of the systems, e.g., answer questions, return search results, or provide functionality within the social networking services. For example, many social networking services help individuals identify other registered users that they may know or have a connection with. Such functionality requires analyzing a large set of data representing the users of the social networking service.
In facilitating searching of information in large sets of documents, such as searches of the web pages on the Internet (or the "web"), search engines are employed which rank results based on various factors. One such search engine is the Google™ search engine which uses a ranking algorithm referred to as "PageRank." PageRank exploits the linkage structure of the web to compute global "importance" scores that can be used to influence the ranking of search results.
Recently, an effort at Stanford University, as part of their Stanford Global Infobase Project, has developed an algorithm for allowing users to define their own notion of importance for each individual query. This algorithm, referred to as personalized PageRank, provides online personalized web searching with personalized variants of PageRank based on a private, personalized profile.

This patent is subject to a terminal disclaimer.

Concept analysis operations utilizing accelerators

International Business Machines Corporation


A method of filtering image data is described. In one embodiment, the method includes storing in line buffers image data corresponding to a plurality of rows of an image; filtering image data on one row of multiple of rows; and filtering image data on another row of the multiple rows without changing the image data stored in the line buffers between filtering image data on the one row and filtering image data on the another row.

The present invention relates to image filtering. More specifically, it relates to mirror-mode edge handling in image filtering.
Filtering image data typically involves applying a filter thereto. FIG. 1 illustrates the conceptual application of a filter to image data. In FIG. 1, image data 105 (which may also herein be referred to as image 105 or image frame 105) has a filter 110 applied thereto. Image data 105 represents an image frame and includes five rows and six columns of pixels. The five rows in image data 105 include rows j0 to j4. The six columns in image data 105 include columns i0 to i5. Each pixel in image data 105 is identified by its row and column position. For example, pixel i2,j1 is the pixel on row j1 at column i2. Filter 110 is a two dimensional filter that includes filtering coefficients c0 to c9, as shown in FIG. 1. Filter 110 may also herein be referred to as a kernel window.
Filtering the image data involves filtering each pixel of the image data by the filter. The filtering typically begins on the first row of the image data, e.g., on row j0 of image data 105. More specifically, the filtering typically begins on the pixel on the first column of the first row, e.g., i0,j0, and proceeds in raster order to the other columns, i.e., from left to right, on that row. Thereafter the filtering proceeds to the next row, e.g., row j1, whose pixels are also processed from left to right. This continues until all the rows of the image data are filtered.
Filtering a pixel of an image data typically involves conceptually centering the kernel window around the pixel and applying filtering coefficients of the filter to the respective pixels over which they are positioned. For example, in FIG. 1, filter 110 is centered around pixel i2,j2, at which position it filters pixel i2,j2 of image data 105. The result of filtering pixel i2,j2 by filter 110 is (i1j1)×c0+(i2j1)×c1+(i3j1)×c2+(i1j2)×c3+(i2j2)×c4+(i3j2)×c5+(i1j3)×c6+(i2j3)×c7+(i3j3)×c8. After filtering pixel i2,j2, filter 110 would be applied to pixel i3,j2 and the result of the filtering would be (i2j1)×c0 (i3j1)×c1+(i4j1)×c2+(i2j2)×c3+(i3j2)×c4+(i4j2)×c5+(i2j3)×c6+(i3j3)×c7+(i4j3)×c8. It is to be noted that the resulting sum for filtering a pixel data typically need not be averaged as such averaging factor is typically already taken into account in the filtering coefficient of the filter, e.g., the c0 to c8 in the example of FIG. 1.
In the situation illustrated in FIG. 1, the kernel window covers only pixels within the image data area, i.e., the kernel window is entirely within the image. However, when filtering pixels at or near the edges or boundaries 106, 107, 108, and 109 of an image data area, part of the kernel window would typically fall outside of the image data area, which may herein be referred to as the filter being off the image data. This would result in a lower filtering value for such pixels, thus producing artifacts around the edges of the filtered image. In order to reduce such artifacts, the pixel data around the edges is mirrored about the edges.
FIG. 2 illustrates filtering of image data using mirroring. In FIG. 2, image data 205 is filtered using filter 210. In FIG. 2, the first row of pixels below horizontal boundary 206 (i.e., pixels in row j0) are mirrored above horizontal boundary 206. Similarly, the first column of pixels to the right of vertical boundary 209 (i.e., pixels in column i0) are mirrored to the left of vertical boundary 209. In fact, not only pixels to the right of vertical boundary 209, but pixels to the right of a line containing vertical boundary 209 are mirrored to the left of such a line. Similarly, the mirroring about boundary 206 is also extended along a line containing boundary 206. In FIG. 2, filter 210 is positioned above image data 205 (and its associated mirrored data) for filtering pixel i0,j0. The result of such filtering is (i0j0)×c0+(i0j0)×c1+(i1j0)×c2+(i0j0)×c3+(i0j0)×c4+(i1j0)×c5+(i0j1)×c6+(i0j1)×c7+(i1j1)×c8.
In FIG. 2, the mirroring applies to only the first row (row j0) and the first column (column i0) because the filter 210 is a 3 by 3 filter which at most would extend one row or column outside the image data area when filtering pixels along boundaries 206 and 209. If a larger filter were used, e.g., a 5 by 5 filter, then the first two rows (i.e., rows j0 and j1) would be mirrored about horizontal boundary 206 and the first two columns (i.e., columns i0 and i1) would be mirrored about vertical boundary 209.
In filtering image data, line buffers are typically used to store image data. Generally, the number of lines (or rows) in the line buffers is equal to the number of rows in the filter used. Thus, for example, if the filter is one such as filter 210 shown in FIG. 2, then three-lines (or three-rows) of line buffers would be used to store image data to be filtered. Each line (or row) of the line buffers would store one row of image data. For example, when filtering pixels in row j0 of image data 205, the first, second, and third lines of the line buffers would be storing data from rows j0, j0, and j1, respectively. When filtering pixels in row j1 of image data 210, the first, second, and third lines of the line buffers would be storing data from rows j0, j1, and j2, respectively. Further, when filtering pixels in row j2 of image data 210, the first, second, and third lines of the line buffers would be storing data from rows j1, j2, and j3, respectively. One way to efficiently manage data in the line buffers as the filtering transitions from row j1 to row j2 is to move data in each line of the line buffers up by one row and to fill the last line with data from a new row, i.e., row j3. This is relatively simple for the row j1 to row j2 transition. However, it can be more complicated for some row transitions where the filter covers mirrored rows above or below horizontal boundaries of the image data, particularly mirrored rows below the lower horizontal boundary, e.g., lower horizontal boundary 208 in FIG. 2.
Thus, there is a need for efficiently managing image data in line buffers, particularly when filtering pixels that involves use of mirrored image data.

Efficient implementation of mirror-mode edge handling in image filtering


A membrane dispenser includes a basic body having its intermediate circumference provided with a position-limiting recess to partition the basic body into a holding member at a rear portion and a dispensing member with a comparatively large diameter at a front portion. A position-limiting member is fitted in the position-limiting recess, and a brake sleeve is fitted on both the holding member and the position-limiting recess, which are engaged in the brake sleeve by the position-limiting member, letting the basic body able to rotate pivotally on the position-limiting member. In using, simply hold the brake sleeve and timely apply a radial force to the brake sleeve to force the basic body to stop rotating and let a membrane reel stop releasing membrane for facilitating adjusting of membrane strapping tightness, simple in structure and convenient in operating and using.

1. Field of the Invention
This invention relates to a membrane dispenser, particularly to one able to timely stop a membrane reel from rotating and releasing membrane for facilitating adjustment of membrane strapping tightness, able to achieve excellent effect of membrane strapping.
2. Description of the Prior Art
A conventional membrane dispenser, as shown in FIG. 1, includes a basic body 1 having two circular holders 2 respectively and pivotally disposed at the opposite sides to face each other. A membrane reel 3 has opposite ends of its inner center respectively and pivotally assembled on the two circular holders 2 to enable the membrane reel 3 to be actuated to rotate between the two circular holders 2. However, the two holders 2 of the conventional membrane dispenser can only let the membrane reel 3 to rotate freely thereon, but cannot control tightness of the membrane released; therefore, during carrying out membrane strapping, it is necessary for a user to pay attention all the time to a strapping condition and manually adjust membrane strapping tightness. Thus, strapping tension of the membrane cannot be expanded effectively and an article strapping process becomes complicated, necessary to take much labor and time in membrane strapping.
For improving above-mentioned drawbacks, another conventional membrane dispenser, which can be manually operated with less force and convenience, enabling membrane strapping tension to be expanded, is disclosed in a U.S. Pat. No. 5,203,517. Such a membrane dispenser, as shown in FIG. 2, includes a solid columnar shaft 4 having its top end mounted with a wheel hub 5 properly inserted in an inner center of a membrane real 3. The solid columnar shaft 4 has a lower intermediate section disposed with a plurality of elongate projections 6 and secured with a brake sleeve 7 that cannot be rotated on the columnar shaft 4. Further, the columnar shaft 4 has its upper and lower side abutting the brake sleeve 7 respectively fitted thereon with a bearing 8 able to rotate on the columnar shaft 4 and its lower end fitted with a flexible grip sleeve 9. In using, when the solid columnar shaft 4 is driven to rotate in the bearings 8 and actuate the membrane reel 3 to carry out strapping, a radial force can be timely applied to the grip sleeve 9 to let the grip sleeve 9 push against the brake sleeve 7 to stop the columnar shaft 4 from rotating and force the membrane reel to stop releasing membrane and at this time, a user can carry out adjusting of membrane strapping tightness to let membrane strapping tension expanded effectively. However, the brake sleeve 7 has to be provided for pushing against the elongate projections 6 of the solid columnar shaft 4, and the two bearings 8 are necessary to be installed for actuating the solid columnar shaft 4 to rotate, thus complicating the structure of the membrane dispenser.


An intelligent switch system, a so-called squib, for providing power to sensitive equipment, such as missiles, rockets and the like, comprises a pair of serially connected power switches which are separately and sequentially enabled and which will not deliver power from their input to their outputs unless both switches turn on. These switches are controlled by an electronic microcontroller that is normally left unpowered, except when a trigger input is temporarily applied to the microcontroller.

The present invention relates to squibs and, more particularly, to electronically controlled digital squibs. Squibs are electrical switches with a built-in, ultrasecure mechanism to prevent accidental turn on of the switch.
Rockets, missiles, space platforms, drilling equipment, remote robotic controls and the like, have triggerable systems or devices which, when triggered or launched, result in significant events that cannot be easily reversed or stopped. Therefore, very elaborate steps are taken in the design of squibs to assure foolproof operation without any chance for accidental triggering of the switching device.
Conventional squibs are expensive, elaborate and electromechanical, as well as chemical, devices which sometimes include explosive components that destroy a trigger prevention protector when it is decided that the squib is to be enabled. It would be advantageous to obtain a squib that avoids the drawbacks of conventional squibs, including relative to the complexity, construction and cost thereof and obtain a squib with enhanced programmability and versatility features.


Various embodiments of a grounds maintenance vehicle are disclosed. The vehicle includes a frame and a control tower disposed at or near a rear end of the frame. The control tower includes a support structure that defines an interior space of the control tower and a nonplanar removable skin connected to the support structure. The removable skin includes a front side disposed over a front side of the support structure and a lateral side disposed over at least one of a left side or a right side of the support structure. A portion of at least one of the front side or lateral side of the removable skin is disposed above an uppermost surface of the prime mover. Further, the removable skin is adapted to be at least partially removed from the support structure to facilitate additional access to the interior space of the control tower.

Riding grounds maintenance vehicles such as lawn mowers and the like are used by homeowners and professionals to care for lawns and other surfaces. These vehicles include a prime mover, e.g., internal combustion engine or electric motor, to power not only an implement (e.g., cutting deck) attached to the vehicle but also a traction drive system, the latter adapted to propel the vehicle over a ground surface.
Landscape contractors sometimes prefer stand-on mowers. Such mowers typically include a standing platform located behind the mower's rear wheels and a tower forward of the platform to support various hand controls.
One benefit of stand-on mowers is that they are often shorter than conventional riding mowers and, consequently, may be more maneuverable under certain mowing conditions. Typically, stand-on mowers utilize an engine having a horizontally- or vertically-oriented drive shaft to provide power, e.g., via endless belts, to both the cutting deck and to the traction drive system. Each drive wheel may utilize its own hydrostatic pump, and each pump may be independently controlled to provide the mower with a very small turning radius and, in some instances, a zero-turning-radius (ZTR) where the mower can spin about a midpoint between the two drive wheels. Some components of the mower may be located within or proximate the tower.

Grounds maintenance vehicle with removable control tower skin

EXMARK MANUFACTURING COMPANY, INCORPORATED


A memory testing apparatus is provided which can determine at high speed whether to relieve a failure of an IC memory or not. In case an IC memory is tested by the memory testing apparatus and a decision as to whether to relieve a failure of the IC memory or not is rendered, a failure cell 1 is provided for receiving a failure signal from a logical comparator 14 and an address signal from a pattern generator 23, said address signal being used for taking a failure signal in the failure cell. The failure cell 1 stores therein only failure addresses of the IC memory and is constructed by an address hold register 3, an address comparator 5, and a controller 8. A failure cell array 2 comprising a plurality of these failure cells connected in cascade is used to limit data for creating a failure map to only failure occurrence addresses and to store the data therein. Thus, the time for reading out the data stored in the failure cell array 2 to an arithmetic part 15 is reduced.

Storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a lowering of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being lowered, various failure relieving procedures or processes have been taken wherein a failure or defect element is replaced by a substitute or alternative element.
FIG. 12 generally shows an entire circuit arrangement of a prior conventional memory testing apparatus, and FIG. 13 is an illustration of the inside of an IC memory for explaining an analysis method for failure relief. As shown in FIG. 13, an IC memory includes a main element 17 which is a main storage portion, and four substitute elements 18, 19, 20 and 21 disposed around the main element 17 (in this example, at the lower side and the right side of the main element). The main element 17 has, in this example, the total of 64 storage elements in the form of a matrix of 8 rows.times.8 columns. As shown in the figure, rows are denoted by A, B, C, . . . , H, respectively, and columns are denoted by a, b, c, . . . , h, respectively, for brief explanation. Each of intersecting points or areas Aa, Ab, Ac, . . . , Hh of rows and columns of the main element 17 forms a unit element which is a unit storage element of the IC memory.
The substitute elements 18, 19, 20 and 21 are previously provided in the IC chip for a failure relief and each substitute element comprises a plurality of unit storage elements. In this example, four substitute elements are shown. However, the number of substitute elements and the disposed locations in the IC chip may be arbitrarily selected as the case may be.
Assuming that the IC memory shown in FIG. 13 was tested by a memory testing apparatus shown in FIG. 14 to be described later, and as a result, failures or defects were found in, for example, four unit elements Bb, Be, Df and Fe as shown in FIG. 13 by oblique lines, the row B including the failure unit elements Bb and Be, the column f including the failure unit element Df, and the row F including the failure unit element Fe are removed from the main element 17 so that no failure unit element exists in the main element 17.
Then, the substitute element 18 is substituted for the row B, the substitute element 19 is substituted for the row F, and the substitute element 20 is substituted for the column f. In such a way, by replacing a row or rows and/or a column or columns each including one or more failure unit elements by such substitute elements, the IC memory can be relieved such that all of the addresses thereof can be used even if the IC memory has one or more failure unit elements in the main element 17 thereof.
As described above, in order to relieve an IC memory of a failure element or elements, "information for indicating at which address or addresses a failure unit element or elements exist" which is called a failure map is necessary, and hence, as shown in FIG. 12, a memory testing apparatus having a failure analysis memory (failure memory) 16 for storing therein failure information (data) is used.
This memory testing apparatus comprises a timing generator (TMG GEN) 22, a pattern generator (PTN GEN) 23 and a waveform shaping device (WAVE SHAPE) 24 whereby a predetermined test pattern signal is generated and is applied to a memory under test (IC memory under test) MUT to write predetermined data in the memory under test MUT (hereinafter referred to as MUT). The data written in the MUT are read out therefrom later to supply to a logical comparator (LG COMPA) 14 as a response output signal.
The pattern generator 23 supplies a test pattern signal to an MUT via the waveform shaping device 24 and also supplies an expected value pattern signal (EXP SIG) directly to the logical comparator 14. Further, the pattern generator 23 supplies an address signal (ADR SIG) to the failure analysis memory (FAIL MEM) 16, the address signal specifying the same address as that of an address signal added to both the test pattern signal and the expected value pattern signal.
The logical comparator 14 compares a response output signal read out from an MUT with an expected value pattern signal outputted from the pattern generator 23 and detects as to whether there is an anti-coincidence or mismatch between both signals. That is, when the response output signal does not coincide with the expected value pattern signal, the logical comparator 14 writes in the failure analysis memory 16 a failure signal or data (FAIL SIG) indicating a location of a failure cell (unit element) in the main element 17 of the MUT. The address of the failure analysis memory 16 into which the failure data is written is the same address as the MUT address at which the anti-coincidence has occurred, and the address signal specifying that MUT address is supplied directly to the failure analysis memory 16 from the pattern generator 23, as mentioned above.
The failure analysis memory 16 is provided with a memory having at least the same storage capacity as that of the MUT and the memory is initialized before starting a test. For example, the memory of the failure analysis memory 16 is initialized by writing logical "0s" in all of the addresses thereof. When a failure signal is generated from the logical comparator 14 during a test of an MUT, a mark is written in an address in the memory of the failure analysis memory 16 specified by the above address signal. That is, for example, a logical "1" is written in that address.
In such a way, failure address information of an MUT specifying the addresses of the MUT associated with the failures which occurred during a series of tests is stored in the failure analysis memory 16. The failure data stored in the failure analysis memory 16 are read out therefrom after all of the tests for an MUT are completed. When such failure data are utilized for relieving an MUT of its failure memory element for instance, a failure map is created, which is read out into an arithmetic and logic (hereinafter referred to as arithmetic) or computing part (ALU) 15 to determine a row or rows and/or a column or columns to be relieved.
On the other hand, in a usually utilized testing method such as a marching method or a galloping method or the like, since a plurality of reading tests are performed on the same address of an MUT in a series of tests, a plurality of failure signals may be generated with respect to the same address signal. However, regarding the failure of the same address, a plurality of marks are repeatedly written in the same address one over another so that only information required for the failure relief can be stored.
As described above, the failure analysis memory 16 has at least the same storage capacity as that of an MUT. Whenever a failure signal is generated, a logical "1" is written in the same address location of the failure analysis memory 16 as that of the unit element which has generated the failure signal. Therefore, the failure analysis memory 16 must have at least the same storage capacity as that of an MUT as well as operate at the same operating rate or speed as that of the MUT. For that reason, a conventional failure analysis memory has been constructed by using memory elements called static RAM (SRAM) which can operate at high operating rate. However, since an SRAM is expensive and in addition, an SRAM having large storage capacity cannot be produced, there is a problem that a failure analysis memory having a large storage capacity must be constituted by using a large number of SRAMs.
Consequently, an attempt for using a dynamic RAM (DRAM) which operates at low operating rate or speed, but is inexpensive has been made to construct a failure analysis memory. FIG. 14 shows a circuit construction of a failure analysis memory contemplated in case a DRAM is used.
A method can be contemplated wherein a switching circuit MP and a plurality of memory banks BK#1, BK#2, BK#3, . . . , BK#N are provided in a failure analysis memory 16, and each time a failure signal (failure data) is generated, the switching circuit MP switches the memory banks BK#1-BK#N from one memory bank to next succeeding memory bank to supply the failure signal to the one memory bank thereby distributing the failure data into the plurality of memory banks BK#1, BK#2, BK#3, . . . , BK#N in regular sequence to store therein. This method is generally called an interleave method. By employing this interleave structure, the memory banks BK#1-BK#N can be used each of which operates at an operating rate or speed which is 1/N of that of an MUT.
In case the interleave structure shown in FIG. 14 is employed, an address signal having an address at which a failure signal is generated and the failure signal are randomly supplied to each of the memory banks BK#1-BK#N, and therefore, each of the memory banks BK#1-BK#N requires the same memory capacity as that of an MUT. As a result, when an interleave structure of N phases is arranged, each memory bank must have the memory capacity of N times larger than that of an MUT. Accordingly, there is a shortcoming that the amount of usage of memory elements is increased in proportion to the number of phases N of interleave structure.
In addition, when a failure map which is the information necessary for a relief operation is read out of the failure analysis memory 16 to the computing part 15, in order to obtain the information required to determine whether a relief is necessary or not, the data the number of which is equal to that of all of unit elements constituting an MUT must be read out of the failure analysis memory 16. A long time is necessary for this operation. Consequently, there is a disadvantage that it takes a long time to determine whether a relief is necessary or not, resulting in worse in operation or work efficiency.

Memory testing apparatus using a failure cell array


A cooling circuit includes a valve device (1, 1', 1") for a separate heat exchanger (42), especially of an internal combustion engine (48). To achieve a combined pressure limitation and pipe or hose break valve, a valve body (6, 35, 50), upon reaching a coolant throughput for maximum heat transfer in heat exchangers (42) located downstream, is actuated as a function of delivery pressure into an engaged position with a valve seat (5, 51). A throttle passage (7, 36, 52) maintains a coolant throughput that corresponds to maximum heat transfer. In the event of a pipe or hose break, the valve body (6, 35, 50) serving as part of a pipe or hose break is locked in a closed position.

The invention relates to a valve device for a heat exchanger located in a bypass in a cooling circuit, especially of an internal combustion engine. A valve body actuated as a function of delivery pressure against the resistance of a return spring relative to a valve seat to limit a line cross section, as well as a throttle passage serving for a predetermined coolant throughput are located in a housing of the valve device for through-flow-regulated pressure limitation.
A valve device of the type generally described above is known for example from German patent document DE 196 27 655 A, which is used for a heating device for a vehicle. The valve device is located in a bypass for heat exchangers to keep the feed pressure of the hot water at a constant level in each heat exchanger. In addition, the valve body used in the valve device has a throttle passage for the purpose of maintaining a hot water circulation in the bypass when the valve body is closed.
Another valve device of the type generally described above is known from European patent document EP-A 0 302 264. The subject of this reference is intended to provide maximum heat transfer in the heat exchanger located downstream, especially when the internal combustion engine is at idle. This is accomplished by the fact that the coolant throughput is almost not throttled at all when the engine is at idle. No additional information for higher pump pressures is provided.
The goal of the invention is to improve on the valve device of the type generally described above in such fashion that the feed and delivery pressures are limited when a coolant throughput is reached that produces maximum heat transfer in the heat exchanger with flow continuing through the heat exchanger. A delivery-dependent effective safety device is combined with this through-flow-regulated pressure demand.
This goal is achieved by providing a valve device for a heat exchanger located in a bypass cooling circuit of an internal combustion engine, comprising: a housing communicated with the bypass cooling circuit; a valve seat located in said housing, said valve seat defining a line cross section; a valve body disposed in said housing to be movable between a closed position engaged with said valve seat and an open position spaced from said valve seat, said valve body defining a throttle passage; a return spring arranged to bias said valve body toward said open position; said valve body being moved into said closed position by a delivery pressure of a coolant flow for a maximum heat transfer in the heat exchanger, said throttle passage having a cross-section adapted to said maximum heat transfer, wherein said valve body, in the event of a break in the bypass cooling circuit, serves as part of a break valve that is held in a closed position independently of the delivery pressure via a locking device, with a sealing element that suppresses the coolant flow.
This goal is achieved by providing a valve for a fluid line, comprising: a valve housing; a sliding sleeve slidably disposed in said housing, said sliding sleeve being slidable between an upstream position and a downstream position, said sliding sleeve defining a valve seat; a spring arranged between said sliding sleeve and said valve housing, said spring biasing said sliding sleeve toward said upstream position; a valve body disposed in said sliding sleeve to be movable between an open position and a closed position, said valve body defining a sealing seat which engages said valve seat in said closed position, said valve body defining a throttle passage; a return spring arranged between said valve body and said sliding sleeve, said return spring biasing said valve body toward said open position; a sealing element arranged downstream of said valve body, said sealing element sealing said throttle passage when said valve body is in said closed position and said sliding sleeve is in said downstream position.
In so-called thermomanagement systems with separate heat exchangers for heating and cooling, with the valve device according to the invention the flow through the respective heat exchanger can advantageously be limited continuously as a function of its maximum necessary coolant throughput for optimum heat transfer. With this individual pressure limitation for each individual heat exchanger in the bypass, it is also advantageously ensured that each heat exchanger at most has only the coolant throughput necessary for optimum heat transfer and therefore all of the heat exchangers in the cooling circuit, depending on their design, are supplied with the required maximum quantity of coolant when the valve body that limits the pressure is closed. As a result, the engine itself, especially with heat exchangers connected in parallel in the coolant circuit and additional heat exchangers also included in the circuit, is provided with more coolant for its own heating or cooling. With this pressure limitation set according to the invention for the coolant throughput for maximum heat transfer, with a coolant throughput through the throttle passage that corresponds to the respective throttle characteristic of the heat exchanger in question, in the event of a further increase in coolant throughput in the cooling circuit the heat exchanger is protected against an additional pressure rise and its operating safety is thus increased.
The valve device according to the invention, in addition to the pressure limitation achieved by using through-flow regulation, also serves as a first pipe or hose break valve known of itself for example from German patent document DE-8 1 172 918 whose through flow shutoff function in a motor vehicle with a liquid-cooled engine with heat exchangers included in bypasses in its cooling circuit for various purposes, in the event of a pipe or hose break, cuts off the affected bypass circuit from the rest of the cooling circuit, with the vehicle advantageously continuing to be operable.
In a first embodiment of the invention, the valve device is equipped with a pipe or hose break valve in such fashion that the valve body made with the throttle passage is slidably movably mounted in a sliding sleeve that contains the valve seat. The sleeve is mounted in the housing between the pipe and hose stubs, with the valve body abutting the valve seat essentially tightly as a function of delivery pressure, against a compression spring in tight contact with the housing. With the additional striking movement of the sliding sleeve triggered as a function of the delivery pressure by a tube or hose break, an elastic element in a fixed location downstream in the pipe or hose stub closes the throttle passage.
To maintain the function of a pipe or hose break valve especially when the delivery pressure or coolant throughput is low, it is proposed in another embodiment that when the throttle passage closes, a locking device operates that holds the valve body and the sliding sleeve in a tight closed position.
The improved safety valve according to the invention described above ensures that when a line break takes place downstream from the valve device in the bypass, a further escape or loss of coolant from the cooling circuit that is usually equipped with a circulating pump is avoided in conjunction with a check valve that serves in the bypass return as a pipe or hose break valve. Thus, in particular, a cooling circuit of an engine continues to function with the exception of the heat exchanger cut off by a broken line section.
In an embodiment of a combined pressure-limiting and safety valve designed differently from the valve device described above, it is proposed that in a housing, a diaphragm that separates a return chamber from a divided forward chamber with a partition that has a valve opening is in a driving connection with a valve body that controls the valve opening on the outflow side, with throttle passages and a valve plate that closes the valve opening in the event of a pipe or hose break on the feed side, and that a check valve is located in a return stub of the housing on the heat exchanger side.
A third valve device according to the invention is advantageously designed simply so that the valve body itself, in the event of a line break, serves as a pipe or hose break valve and thus only one separate pipe or hose break valve is necessary in the bypass in the other line.
With the design of the valve device advantageously first described in terms of construction cost and space, to achieve the safety function when a pipe or hose breaks, a corresponding delivery pressure is necessary in the cooling circuit. With the second design of the valve device that is slightly more expensive to build, the safety function is ensured by a closing spring that acts on the diaphragm on the return chamber side.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Valve device for a heat exchanger located in a bypass in a cooling circuit, especially of an internal combustion engine

Bayerische Motoren Werke Aktiengesellschaft


A decorative article includes: an iridescent film translucent or transparent overlaid on a substrate member which may be a color sheet, and a filler layer formed beneath the substrate member, whereby upon molding or welding of the iridescent film, the substrate member and the filler layer to form three-dimensional decorative feature having protrusions and recesses on an upper or outer surface of the decorative article to reveal the iridescent colors as reflected by the iridescent film in cooperation with a background color or contrast color of the substrate member for forming shimmer multiple colors for enriching the decorative effect. The article overlaid with the iridescent film will prevent scratching, fading or oxidation defects as found in a conventional electroplated decorative item.

A conventional logo, mark or decorative item such as formed on a footwear or a commercial product may be electroplated with gold, silver or other colors for enriching ornamental effect.
However, the electroplated product has the following drawbacks:
1. By electroplating metal on a decorative item may increase the production cost. PA1 2. The surface metal film as deposited on the decorative item may be scratched, faded, or damaged to lose its decorative feature. PA1 3. The electroplating process may produce waste water containing poisonous heavy metal, being hazardous to human health and influencing environmental protection. PA1 4. The electroplating process is quite limited, especially for the basic working piece having complex geometric configuration, curvatures or structures, thereby increasing the processing complexity or even being unable for electroplating. PA1 5. The electroplated product may have weak water and weather resistance, easily losing their brightness and gloss and thereby decreasing their decorative effect.
The present inventor has found the drawbacks of the conventional decorative item by electroplating method, and invented the present decorative article overlaid with iridescent film.

Decorative article overlaid with iridescent film


A power control and commutation network for a brushless DC motor includes a first section proximate the motor and a second section remote from and connected to the first section by a pair of conductors. Included in the first section is a servo control amplifier defining a main motor power supply and, in the second section, a polyphase brushless DC motor, a commutation module, an auxiliary power supply for the module, motor rotor position sensors and a switching network, the motor stator coils being connected through the switching network to the conductors. The amplifier may have an amplitude modulated DC output and the output of a high frequency oscillator in the second section is AC coupled to the conductors and the auxiliary power supply with its input is AC coupled between the conductors. Alternatively, the amplifier is PWM and the auxiliary power supply includes a rectifier with an input connected across the conductors and a voltage regulator controlling the output voltage.

The present invention relates generally to improvements in electric motor control networks and it relates particularly to an improved brushless DC motor control network.
The use of DC brushless motors is highly desirable in many applications. Such motors obviate the need for electromechanical commutation brushes while permitting continuous motor speed and/or torque adjustment and regulative while eliminating the drawbacks of the brush-type DC motor. They are highly versatile and adaptable, rugged, reliable and stable under many ambient conditions. However, it is frequently desirable to locate the motor voltage supply remote from the motor and in the conventional brushless DC motor control networks necessitates the need for a large number of long conductors extending from the area of the motor voltage supply to the other components of the network in the area of the motor.


Both a system and method is provided for implementing a wiring change with respect to an electrical component detachably connected to a solderless PWB module. The system comprises at least one unused via on the PWB, an insulator used for electrically disconnecting a selected contact pad of the component from a contact pad disposed on the PWB, and a metallic strip mounted on a substrate for electrically connecting the selected component contact pad to the unused via. In one embodiment of the system, the substrate used to support the conductive strip is the compliant, insulative sheet material used in the interface that normally interconnects the pads of the electrical component with the pads of the PWB module. Alternatively, a separate "smart" layer formed from a thin insulative sheet material may be used to support the conductive strip. The "smart" layer has an array of conductive regions disposed through its thickness which maintains the contact between the pads of the PWB and the pads of the electrical component. However, when a change is desired, these conductive areas may be abraded off, and a copper strip connector may be provided on the surface of the "smart" layer between the disconnected component contact pad and an unused via by conventional photo-resist techniques.

This invention generally relates to solderless printed wiring board modules, and is specifically concerned with a system and method for implementing a wiring change with respect to any electrical component detachably connected to a PWB.
Solderless printed wiring board modules are known in the prior art. Such modules comprise a printed wiring board (PWB) having one or more arrays of contact pads (known as "footprints" in the art), a heat-conductive guide plate assembly having a plurality of apertures that are registrable with the pattern of contact pad arrays on the PWB, each aperture being matable with an electronic component, and an interface formed from a piece of compliant, insulative sheet material that is receivable within one of the apertures of the guide plate. The interface includes a plurality of resilient electrical connectors (called "button connectors" in the art) that are registrable with the contact pads of the PWB When the interface is dropped into one of the apertures of the guide plate. Each of these button connectors is formed from a small, springy cylinder of randomly compressed, thin gauge copper-beryllium wire that has been gold plated. Each of these connectors is frictionally received within a through-hole present in the interface.
In operation, the interface is first dropped into one of the apertures of the guide plate assembly. The shape of the outer edge of the compliant sheet material forming the interface is matable within the aperture in the guide plate, and the button connectors are registrable with the contact pads of the PWB such that the lower end of each of the connectors engages one of the pads in ,the PWB. An electrical component is next dropped into the aperture of the guide plate. The shape of the outer edge of the electrical component is likewise matable with the aperture in the guide plate assembly such that its contact pads become aligned with the upper ends of the button connectors held by the interface. When the electrical component is compressed downwardly toward the PWB, each of the resilient button connectors provides a positive, spring contact between the pads of the PWB, and the corresponding pads of the electrical component. Such a PWB module is disclosed and claimed in U.S. Pat. No. 4,933,808, invented by Messrs. Robert Bourdelaise, David Harris and Roald Horton, and assigned to the Westinghouse Electric Corporation.
Such solderless PWB modules provide a great many advantages over conventional, soldered printed wiring board modules. The elimination of the soldering operation between the pads of the electrical components and the printed wiring board eliminates up to 67 percent of the required assembly time, and further greatly reduces the possibility of component damage due to overheating. Such solderless PWB modules may provide a higher degree of reliable interconnection between the electric-al components and the printed wiring boards, as there is no possibility of defective connections occurring as a result of solder splattering or defective solder joints. Because of the need for inspecting finished solder joints, soldering encouraged perimeter-type connections to be made between the electrical component and the printed wiring board, where the finished connections could be seen. In instances where the electrical component had a large density of leads projecting out around its perimeter, the margin for error became very small for the proper soldering of each of these leads to its respective contact pad on the PWB as the distance between the leads became small. By contrast, the advent of solderless PWB modules which utilizes a sheet-like interface that holds an array of small, springy button connectors to create electrical contact between the pads of the component and the PWB made it much more practical to spread these connections out in an area array pattern, where the connections are uniformly spaced apart from one another throughout the entire area under the component, as opposed to locating these connections to only around the perimeter, thereby reducing the probability of an assembly error. The elimination of soldering in solderless PWB modules also advantageously obviates the need to use fluorocarbon solvents which contribute to the degradation of the ionosphere. Finally, such solderless PWB modules have much more effective heat sink properties than their prior art counterparts, and are far easier to test, repair and replace components on.
Unfortunately, until the advent of the present invention, there was no known way to implement wiring changes in such solderless PWB modules. This is a significant limitation, as it adversely effects the high degree of versatility and flexibility enjoyed with such modules.
It is therefore an object of the present invention to provide both a system and a method for implementing a wiring change with respect to an electrical component detachably connected to a solderless PWB modules that is both fast, efficient and easy.
It is a further object of the invention to provide such a system and technique that obviates or at least minimizes the need for any soldered connections within the PWB module, in order that the advantages associated with the elimination of soldering might be substantially preserved.
Still another object of the invention is to provide a system and method for making wiring changes in PWB modules that utilizes inexpensive components and techniques.
Finally, it is an object of the invention to provide a system and method in which more than one wiring change may be made on more than one occasion in a fast, simple and economical manner both between electrical components such as surface mounted components and PWBs as well as between two or more PWBs of different modules.
As used herein, the term "electrical component" includes not only surface mounted components (SMCs) such as packaged integrated circuits, and individual components such as capacitors, transistors, diodes or the like, but also the PWBs of other modules.

System and method for implementing wiring changes in a solderless printed wiring board module


A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.

1. Field of the Invention
The present invention relates to a method and an apparatus for measuring a delay time. More particularly, the present invention relates to a method and an apparatus for measuring a delay time caused by crosstalk.
2. Description of Related Art
As the process of semiconductor integrated circuits (IC) progressively advances, the integration of the IC is increased and correspondingly the line width of the IC reduces. Therefore, the influence caused by the interference or the crosstalk in the connecting lines of the IC get more and more obvious with the increasing integration of the IC. In general, the crosstalk in the IC is usually caused by inductance or capacitance between two adjacent conductors, conductive layers, conducting wires, transmission lines, or connecting lines. In the IC, when a signal or energy is transmitted on a transmission line, the energy may influence another adjacent transmission line by coupling to the adjacent transmission line via the mutual inductance or the mutual capacitance between the two transmission lines. Conventionally, the crosstalk may be classified into near end crosstalk and far end crosstalk according to the distance between the two transmission lines. Particularly, when the density or length of the wiring of the layout of the IC increases, the influence of the crosstalk may be more obvious. For example, the crosstalk phenomenon of a connect line or bus line with a long length is generally serious.
In the IC, when a signal is transmitted on a transmission line, and a crosstalk phenomenon is generated between the transmission line and another adjacent transmission line, the transmission time of the signal may be influenced by the crosstalk, i.e., the transmission of the signal may be delayed by a delay time. At this moment, the delay time may influence the timing of the signals of the IC and generates an error, or even may result in some error of the timing, operation or function of the IC. Thus, the performance or the reliability of the IC may be adversely influenced, or sometimes may even lead to IC failure. Therefore, a crosstalk measuring method or a measuring device for effectively measuring or detecting the influence of the crosstalk, for example, for measuring the delay time, is very important.

Method and apparatus for measuring delay time


A connecting device includes a tubular coupler which has an inner tubular wall that surrounds an axis and that engages a wall-mount water supplying pipe, a hollow adapter which has a surrounding wall turnable relative to an outer tubular wall of the coupler about the axis, and an outlet port extending radially relative to the axis for coupling with a shower head assembly, and a retaining member which is disposed to be kept in slidable contact with an end wall of the coupler so as to prevent removal of the adapter from the coupler.

1. Field of the Invention
This invention relates to a connecting device for a shower head assembly, more particularly to a connecting device for connecting a shower head assembly to a wall-mount water supplying pipe.
2. Description of the Related Art
Referring to FIG. 1, a conventional adapter 1 for connecting a shower head assembly 3 to a wall-mount water supplying pipe 2 is shown to have an internally threaded surface 101 which engages threadedly an externally threaded surface 201 of the pipe 2, and an outlet port 103 which extends radially of the pipe 2. A tubular connector 102 is disposed to fluidly communicate the outlet port 103 with a hose 301 of the shower head assembly 3. However, in assembly, since the outlet port 103 is turned with the screwing of the internally threaded surface 101 to the externally threaded surface 201, the outlet port 103 and the tubular connector 102 may not be positioned at a predetermined lower position parallel to the wall, thereby adversely affecting the appearance. In order to position the outlet port 103 at the predetermined lower position, the internally threaded surface 101 is not fully engaged with the externally threaded surface 201, thereby resulting in a clearance therebetween and leakage of water through the clearance.

Connecting device for connecting a shower head assembly to a wall-mount water supplying pipe


A method for driving a thin film transistor-liquid crystal display using line inversion includes the steps of applying a gate driving pulse to a gate of the thin film transistor; applying a data signal, varied between low and high data signal levels, to one of a drain and a source of the thin film transistor, the other of the drain and the source connected to a first terminal of a pixel of the liquid crystal display; and applying a common voltage, varied between low and high common voltage levels, to a second terminal of the pixel, the level of the common voltage being inverted with respect to the level of the data signal to drive the pixel in varying directions corresponding to a positive field and a negative field, and the gate driving pulse for a gate low level being varied between the positive field and the negative field.

1. Field of the Invention
The present invention relates to a method for driving a thin film transistor-liquid crystal display (hereinafter referred to as a TFT-LCD), and more particularly, to a method for driving a TFT-LCD panel using a line inversion driving method.
2. Discussion of the Related Art
A TFT-LCD panel has a pixel array made of a plurality of pixels. FIGS. 1A and 1B show an equivalent circuit diagram for each pixel. Each pixel of the pixel array is connected to a cross point between a scanning line and a data line which meet at a right angle. FIG. 1A is an equivalent circuit diagram of pixels using a storage-on-gate type arrangement in which an auxiliary capacitor C.sub.s for voltage maintenance is formed on the next gate or the previous gate, irrespective of a common electrode. FIG. 1B is an equivalent circuit diagram in which a pixel electrode C.sub.LC and an auxiliary capacitor C.sub.s are connected to a common electrode.
As shown in FIG. 1A, a gate line (e.g., a scanning line or a word line) connected to a gate of a thin film transistor (TFT) applies a driving voltage V.sub.gn to the gate of the TFT. A video data signal V.sub.sig is applied to the drain of the TFT. One terminal of the pixel electrode C.sub.LC is connected to a source of the TFT. The other terminal of the pixel electrode C.sub.LC is connected to a common voltage V.sub.com. One terminal of the auxiliary capacitor C.sub.s for maintaining voltage is connected to the pixel electrode C.sub.LC in parallel. Finally, the other terminal of the auxiliary capacitor C.sub.s applies the next scanning line voltage V.sub.gn-1.
As shown in FIG. 1B, a scanning line driving voltage V.sub.gn is applied to the gate of a TFT. A video data signal V.sub.sig is applied to the drain of the TFT. One terminal of the pixel electrode C.sub.LC and the auxiliary capacitor C.sub.s are connected to a source of the TFT. The other terminals of the pixel electrode C.sub.LC and the auxiliary capacitor C.sub.s are connected to a common voltage V.sub.com.
When driving such pixel arrays, if a voltage is applied to a liquid crystal pixel in only one way, degradation of the liquid crystal is accelerated. To avoid this degradation, a video data voltage applied to the liquid crystal periodically oscillates between two levels having opposite polarities. In this case, the polarity of the data voltage should be inverted every field. There are preferably two methods: a field inversion driving method for inverting the polarity of a driving voltage of all pixels of the panel in every field, and a line inversion driving method for alternately inverting the polarity of the driving voltage of every pixel line connected to one scanning line. When inverting the voltage polarity according to the above two methods, a pixel voltage applied to a pixel electrode connected to a drain of the TFT should be positive or negative with respect to the common voltage V.sub.com.
To apply the data voltage to a pixel of the panel, the TFT should be turned on by applying a driving voltage to a gate of the TFT. FIGS. 2 and 3 show a method for driving a gate voltage at a gate of the TFT, for driving a data voltage at a drain of the TFT, and for driving a common voltage applied to a node of V.sub.com. FIG. 2 shows a driving method using gate voltage having two levels. FIG. 3 shows a floating gate driving method for floating a gate driving voltage used in a cell array of a storage-on-gate type arrangement in order to maintain a constant phase difference between the gate driving voltage and the common voltage.
In the method for driving a TFT-LCD panel using a line inversion driving method, a polarity of V.sub.sig should be opposite that of V.sub.com every line. In a single pixel, such polarity characteristics are presented such that polarities of V.sub.sig and V.sub.com are alternately inverted with respect to each other.
FIG. 2 shows a gate pulse driving method in which a low level of a gate voltage maintains a constant voltage level. Since a pixel voltage V.sub.p is higher than V.sub.com in timing pulse period (a), and the pixel voltage V.sub.p is lower than V.sub.com in timing pulse period (d), there is a difference between a gate to source voltage V.sub.gs and a drain to source voltage V.sub.ds in each time period. That is, there is a positive field and a negative field. Herein, the positive field shows that the pixel electrode is charged as a positive voltage higher than V.sub.com as shown in timing pulse period (a). Further, the negative field shows that the pixel electrode is charged as a negative voltage lower than V.sub.com as shown in timing pulse period (d).
Likewise, FIG. 3 shows a gate pulse driving method in which a low level of the gate voltage is floated. Since a pixel voltage V.sub.p is higher than V.sub.com in timing pulse period (a), and the pixel voltage V.sub.p is lower than V.sub.com in timing pulse period (d), there is a difference between drain to source voltages V.sub.ds in each time period, thereby causing a positive field and a negative field.
FIGS. 4A and 4B show an example of a voltage of each node of a TFT for each timing pulse period using a gate according to FIG. 2. Reference characters (a)-(f) in FIGS. 4A-5B represent the time periods in FIGS. 2 and 3. Accordingly, V.sub.p "0.5V(c)" represents a pixel voltage in timing pulse period (c).
FIG. 2 is an example showing that a voltage difference between a gate to source voltage and a source to drain voltage occurs. As shown in FIG. 2, a difference between V.sub.gs of a positive field and V.sub.gs of a negative field increases over the period between timing pulse periods (b) and (c), when the scanning line connected to the pixels is sequentially selected.
To display an entire screen as a color of a constant brightness and to achieve the same color and brightness of every pixel while displaying the entire screen, three signals are employed. That is, a gate driving pulse is shown as a rectangular wave signal ranging from -15V to +10V, data signal V.sub.sig is shown as a second rectangular wave signal ranging from -2.8V to +1.2V, and a common voltage V.sub.com is shown as a third rectangular wave signal ranging form -3.8V to +1.2V.
As shown in FIG. 4A, when a positive field is applied to the pixel and a gate driving pulse of -15V is in timing pulse period (a), the TFT is turned on by applying a voltage of +10V. When a data voltage of +0.8V is applied to a drain, a voltage drop of 0.3V occurs and then +0.5V is applied to the pixel electrode. Therefore, -3.8V is applied to V.sub.com, and a voltage difference 4.3V is charged to the pixel electrode which is a capacitor between a pixel electrode and a common electrode.
In a timing pulse period (b) in which a second scanning line is selected, a gate driving pulse is -15V, a data signal V.sub.sig is -2.8V, and a common voltage V.sub.com is +1.2V. V.sub.p of a pixel electrode is higher than V.sub.com by +4.3V, that is, V.sub.p is expressed as 4.3V +1.2V=5.5V, thus V.sub.p becomes a high state.
In a timing pulse period (c) in which a third scanning line is selected, the gate driving pulse is -15V, the data signal V.sub.sig is +0.8V, and the common voltage V.sub.com is -3.8V. Thus, V.sub.p of the pixel electrode becomes a low state of +0.5V, since V.sub.com is -3.8V.
As shown in FIG. 4B, when a negative field is applied to pixel and an initial gate potential is -15V is in a timing pulse period (d), the TFT is turned on by applying a voltage of +10V to the gate. When a data voltage of -2.8V is applied to a drain, a voltage drop of 0.3V occurs and then -3.1V is applied to the pixel electrode. Therefore, +1.2V is applied to V.sub.com, a voltage difference 4.3V is charged to the pixel electrode like the preceding positive field. However, the pixel electrode is charged by a more negative field than the node of V.sub.com.
In timing pulse period (e) in which the next scanning line is selected. The gate driving pulse is -15V, the data signal V.sub.sig is +0.8V, and the common voltage V.sub.com is -3.8V. Thus, V.sub.p of the pixel electrode is expressed as (-3.8V)+(-4.3V)=-8.1V, thus V.sub.p becomes a low state.
In timing pulse period (f) in which the next scanning line is selected, the gate driving pulse is -15V, the data signal V.sub.sig is -2.8V, and the common voltage V.sub.com is +1.2V. Thus, V.sub.p of the pixel electrode becomes a high state of -3.1V.
Under these operations, in the case of timing pulse period (b) of the positive field shown in FIG. 4A, each voltage between terminals of TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-15 -5.5]=-20.5V, a drain to source voltage V.sub.ds is expressed as [-2.8-5.5]=-8.3V, and a gate to drain voltage V.sub.gd is expressed as [-15-(-2.8)]=-12.2V.
In the timing pulse period (c), the gate to source voltage V.sub.gs is expressed as [-15-0.5]=-15.5V, the drain to source voltage V.sub.ds is expressed as [-0.8+0.5]=-0.3V, and the gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
Next, in the case of timing pulse period (e) of the negative field shown in FIG. 4B, each of the voltage between terminals of TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-15-(-8.1)]=-6.9V, a drain to source voltage V.sub.ds is expressed as [0.8-(-8.1)]=8.9V, and a gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
In timing pulse period (f), the gate to source voltage V.sub.gs is expressed as [-15-(-3.1)]=-11.9V, the drain to source voltage V.sub.ds is expressed as [-2.8-(-3.1)]=0.3V, and the gate to drain voltage V.sub.gd is expressed [-15-(-2.8)]=-12.2V.
As described above, there is a voltage difference between the nodes of the TFT while scanning both the positive field and the negative field. For example, a V.sub.gs of -20.5V in the time pulse period (b) of the positive field is changed to a V.sub.gs of -6.9V in time pulse period (e) of the negative field, V.sub.ds ranges from -8.3V to -8.9V, and V.sub.gd ranges from -12.2V to -15.8V.
In addition, a V.sub.gs of -15.5V in time pulse period (c) of the positive field is changed to a V.sub.gs of -11.9V in time pulse period (f) of the negative field, V.sub.ds ranges from -0.3V to -0.3V, and V.sub.gd ranges from -15.8V to -12.2V. As a result, these voltage variations cause unstable leakage current in the TFT, and the unstable leakage current is periodically generated when scanning in the positive field and the negative field, thereby causing a 30 Hz flicker.
FIGS. 5A and 5B show each node voltage of a TFT using the floating gate driving method shown in FIG. 3, in which even though a voltage difference of V.sub.gs between the positive field and negative field is decreased, a voltage difference of V.sub.ds is still high.
In the floating gate driving method, in the case of timing pulse period (b) for selecting the next scanning line, a gate driving pulse is -10V as a high level, data signal V.sub.sig is -2.8V as a low level, and a common voltage V.sub.com is 1.2V as a high level.
In timing pulse period (c) for selecting the next scanning line, the gate driving pulse is -15V as a low level, and the data signal V.sub.sig is +0.8V as a high level, the common voltage V.sub.com is -3.8V as a low level.
As shown in FIG. 5A, when a positive field is applied to pixel in timing pulse period (b), the gate driving pulse is -10V as a low level, the data signal V.sub.sig is -2.8V as a low level, and the common voltage V.sub.com is +1.2V as a high level. Thus, V.sub.p of the pixel electrode becomes a high state of 5.5V.
In timing pulse period (c), the gate driving pulse is -15V as a low level, the data signal V.sub.sig is +0.8V as a high level, and the common voltage V.sub.com is -3.8V as a low level. Thus, V.sub.p of the pixel becomes a low state of +0.5V.
As shown in FIG. 5B, when a negative field is applied to a pixel in a timing pulse period (e), the gate driving pulse is -15V as a low level, the data signal V.sub.sig is +0.8V as a high level, and the common voltage V.sub.com is -3.8V as a low level. Thus, V.sub.p of the pixel becomes a low state of -8.1V.
In timing pulse period (f), the gate driving pulse is -10V as a high level, the data signal V.sub.sig is -2.8V as a low level, and the common voltage V.sub.com is +1.2V as a high level. Thus, V.sub.p of the pixel becomes a high state of -3.1V.
In the case of timing pulse period (b) of the positive field shown in FIG. 5A, each voltage between terminals of the TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-10-5.5]=-15.5V, a drain to source voltage V.sub.ds is expressed as [-2.8-5.5]=-8.3V, and a gate to drain voltage V.sub.gd is expressed as [-10-(-2.8)]=-8.2V.
In the timing pulse period (c) shown in FIG. 5A, the gate to source voltage V.sub.gs is expressed as [-15-0.5]=-15.5V, the drain to source voltage V.sub.ds is expressed as [0.8-0.5]=0.3V, and the gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
In the case of timing pulse period (e) of the positive field shown in FIG. 5B, each voltage between the terminals of the TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-15-(-8.1)]=-6.9V, a drain to source voltage V.sub.ds is expressed as [0.8-(-8.1)]=8.9V, and a gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
In timing pulse period (f) shown in FIG. 5B, the gate to source voltage V.sub.gs is expressed as [-10-(-3.1)]=-6.9V, the drain to source voltage V.sub.ds is expressed as [-2.8-(-3.1)]=0.3V, and the gate to drain voltage V.sub.gd is expressed as [-10-(-2.8)]=-7.2V.
There is no variation of V.sub.gs in the floating gate driving method. However, there is a voltage variation in V.sub.ds and V.sub.gd because V.sub.ds is expressed as V.sub.ds(b) -V.sub.ds(e) =-8.3-8.9 =-17.2 and V.sub.gd is expressed as V.sub.gd(b) -V.sub.gd(e) =-8.2-(-15.8)=7.6V.
As described above, such voltage variations between the terminals of a TFT causes the screen to flicker. The flicker can be explained by FIG. 6 which shows the characteristics of current versus voltage in the TFT.
As shown in FIGS. 6 and 7, leakage current occurs in an OFF-region according to a graph of source-to-drain current I.sub.ds. As the absolute value of V.sub.gs increases, the leakage current increases. Therefore, there is a difference of gate-to-source voltages V.sub.gs between time periods of the positive field and the negative field. Because a difference of leakage current occurs, a light transmittance is varied by a root-mean-square (rms) voltage difference between the positive field and the negative field, thereby causing a 30 Hz flicker.
FIG. 7 depicts the above operations. Although a liquid crystal voltage (position A; reference number 71) which is fully charged in the positive field is identical with another liquid crystal voltage (position B; reference number 73) which is also fully charged in a negative field, there is a voltage difference after one field, since an electric charge included in the pixel electrode is greatly discharged or minutely discharged. Accordingly, a voltage difference between a position C (72) and a position D (74) of FIG. 7 is greatly generated, thereby generating a difference between rms voltages of two fields and causing flicker.

Method for driving a thin film transistor liquid crystal display device using varied gate low levels


Bidirectional, non-interfering transmission of broadband services on a single fiber is accomplished by simultaneously combining wavelength-division, time-division, and subcarrier multiplexing on the downstream and upstream transmissions. High speed electrical data signals are time-division multiplexed at the exchange into a composite signal which modulates a standard diode laser operating at a first wavelength. Data signals from an individual subscriber are modulated onto a subcarrier designated solely for the particular subscriber which, in turn, modulates a laser operating at a second wavelength. Extraction and insertion of the upstream and downstream transmissions at the subscriber and exchange locations is accomplished with wavelength selective couplers.

Broadband integrated digital services are possible in network architectures having fiber in the subscriber loop. Many different network designs have been proposed to handle the broadband service such as BISDN. While passive optical network designs are becoming a network characteristic of choice, the strategy governing communication between the subscriber and the exchange or central office is far from settled. Most proposed strategies involve the use of a single multiplexing technique such as either time-division (TDM) or wavelength-division (WDM) or subcarrier (SCM) multiplexing.
One exemplary network was reported by McGregor et al. in Journal of Lightwave Technology, Vol. 7, No. 11, pp. 1752-8 (1989) involving the use of TDM for both downstream (exchange to subscriber) and upstream (subscriber to exchange) data transmission and WDM to separate the downstream transmission from the upstream transmission. This network utilized bidirectional transmission over a single optical fiber by requiring the presence of 10 .mu.s time guard bands around the data for each transmission direction. The time guard bands prevented upstream and downstream data collisions. A wavelength independent, three-port optical connector at the exchange end of the network facilitated the insertion and removal of data.
Even though the prototype described in the article utilized one fiber for bidirectional transmission, improvements to the prototype included the use of separate fibers for each transmission direction. This improvement offered the dual effects accomodating optical reflections in practical optical distribution plants and eliminating the need for time guard bands. In this dual fiber architecture, McGregor et al. suggested the use of subcarrier multiplexing over the upstream fiber. Unfortunately, the improvements required a duplication of optical fiber installations to support each separate transmission direction. Additionally, the number of splices, connectors, and couplers doubled over the single, bidirectional transmission fiber network. As such the proposed network is incapable of being deployed over existing optical fiber installations without significantly increased costs.

Bidirectional lightwave transmission system


The present invention relates generally to modified Bacillus thuringiensis (Bt) insecticidal crystal proteins, also referred to as mutant toxins, with enhanced toxicity against a variety of insect genera, particularly mosquitos. The invention provides modified Bt Cry4Ba proteins, or mutant toxins, which have toxicity-enhancing sequence modifications at one or more positions within the amino acid sequence of the protein. The invention also provides polynucleotides encoding modified Cry4Ba proteins. The invention also provides insecticidal compositions comprising mutant toxins with a new or broadened insecticidal spectrum, and insecticidal compositions comprising polynucleotides encoding the modified Cry4Ba proteins.

Malaria, dengue, and West Nile Fever are currently the most mentioned mosquito-borne diseases affecting humans. An estimated 1.2 billion clinical attacks of malaria occur each year in Africa. According to the latest consensus of scientists and health workers, malaria kills up to 2.7 million persons each year. Ninety percent of these cases and deaths occur in Africa, and a large portion of them involve children under the age of five. Approximately 1.7 million African children die yearly due to malaria-linked illnesses. Meanwhile, it is estimated that about 50-100 million dengue fever cases occur annually, including a few hundred thousand cases of the life-threatening form (dengue hemorrhagic fever).
Transmission of mosquito-borne diseases occurs through inoculation whereby infected blood-feeding mosquitoes bite target organisms, such as humans, and transfer the disease pathogen into the target's bloodstream. A variety of mosquito species, including Aedes aegypti (dengue, yellow fever), Anopheles quadrimaculatus (malaria), Culex quinquefasciatus (West Nile virus) and Cx. pipiens (West Nile virus) are vectors of blood-borne pathogens that cause disease in humans and other mammals. For example, dengue, yellow fever are transmitted by Aedes aegypti, malaria is transmitted by Anopheles quadrimaculatus (malaria), and West Nile virus is transmitted by Cx. quinquefasciatus and Cx. Pipiens.
Control of insect pests such as mosquitoes is achieved using a variety insecticidal materials. Some insecticidal materials include proteins that are made by the bacterium Bacillus thuringiensis. Bacillus thuringiensis (Bt) is a ubiquitous facultative anaerobic, Gram-positive, motile, spore-forming bacterium that produces proteins that accumulate as crystals within the bacterial cell. These insecticidal crystal proteins are toxic to a number of insects, mainly insects in the orders Coleoptera, Diptera, and Lepidoptera. Pesticidal formulations containing Bt crystal proteins have been used extensively in commercial agriculture, forest management, and mosquito control. Bt is a member of the B. cereus (Bc) group that includes B. cereus, B. anthracis, and B. mycoides. Bt has been classified according to its cellular, cultural, biochemical, and genetic characteristics. However, serotypic and specific biochemical characteristics have been found to be inconsistent. Bt can only be differentiated from Bc by the production of one or more of the insecticidal crystalline (Cry) proteins that are toxic to invertebrates.
Bt is accepted as a source of environment-friendly biopesticide. Farmers have applied Bt as an insecticidal spray for control of lepidopteran and coleopteran pests for more than 30 years. The United States Environmental Protection Agency has considered Bt sprays to be so safe that it has exempted them from the requirement of a tolerance (a standard for a maximum permissible residue limit on food).
The mechanism of action of the Bt crystal proteins involves solubilization of the crystal in the insect midgut to yield a solubilized prototoxin, proteolytic processing of the prototoxin by midgut proteases to yield a Cry toxin, binding of the processed Cry toxin to midgut receptors, and insertion of the Cry toxin into the apical membrane to create ion channels or pores. The introduction of channels or pores permits the free flow of fluids into the cells, which eventually leads to bursting of the cells and death of the insect.
Of the many known Cry proteins, most have limited range of toxicity against insects, and are often quite specific for only one or a few insect genera. Importantly, the known Cry proteins exhibit only limited toxicity to the range of mosquito genera that are responsible for disease in humans and other mammals. Accordingly, it would be desirable to provide Bt Cry proteins that have enhanced toxicity to insects, and more particularly to one or more genera of mosquitoes that are associated with human disease.

Insecticidal Cry4Ba proteins with enhanced toxicity

The Ohio State University Research Foundation


An electric spinning pliers apparatus includes a housing, a plier head coupled to a rotatable shaft, and a head-operating handle. The housing may have a wire sleeve stripper, an iris door, one or more controls, and an indicator light. The electric spinning pliers apparatus utilizes the wire sleeve stripper to cut an outer sleeve of a group of wires, exposing individual wires. Each individual wire may be stripped by the iris door, while the plier head may grasp and rotate, via a motor, each of the individual wires into a single unit. The plier head may then twist a wire nut on the twisted wires.

In the construction industry, there are many individuals that still use conventional pliers or their hands to perform certain tasks. For example, many still use conventional pliers or their hands to twist standard wires for rebar, electrical wires, wire nuts, and for removing wire sleeves. Using conventional pliers or hands to twist wires every day for years can take a toll on a user's wrists. In fact, the repetitive and constant motion of using pliers or hands to twist wires can cause severe arthritis, tendinitis, carpal tunnel, and, in some cases, early retirement due to loss of physical ability to perform the job. Even with this knowledge, electricians and other construction workers still use these rudimentary tools to complete their tasks as there is no suitable alternative.
Further, electricians and other construction workers use a number of tools to complete a task. Some of these tools may be pliers, wire strippers, cordless drills, screw guns, a razor blade utility knife, etc. Electricians may be burdened by carrying numerous tools every day. While the repetitive wire twisting motion may cause damage to wrists, carrying too many tools can become taxing on an electrician's back and joints. In addition, electricians must keep track of each of these tools every day and at every worksite, which may become difficult with the number of tools that an electrician uses. Without each of these tools, an electrician would be severely hindered in successfully and efficiently completing a job.
Accordingly, there remains a need for an all-in-one device that strips and twist wires, is compact and easy to carry, replaces the many tools used by electricians, and helps reduce wrist injury. The present disclosure seeks to solve these and other problems.


A lamp current balance and feedback system and related method are disclosed for balancing the input and output currents of a lamp by making use of a lamp current balance and feedback mechanism. The operation of the lamp current balance and feedback mechanism includes coupling the input current of the lamp for generating a first balance current by a first transformer, coupling the output current of the lamp for generating a second balance current by a second transformer, coupling the first and second transformers for substantially equalizing the first and second balance currents, generating a feedback signal based on the first or second balance current by a feedback circuit, generating a pulse width modulation signal based on the feedback signal by a pulse width modulation signal generation circuit, and driving the input and output currents of the lamp based on the pulse width modulation signal by a driving circuit.

1. Field of the Invention
The present invention relates to a backlight system and related method, and more particularly, to a backlight system and related method based on a lamp current balance and feedback mechanism.
2. Description of the Prior Art
Because liquid crystal display (LCD) devices are characterized by thin appearance, low power consumption, and low radiation, LCD devices have been widely applied in various electronic products such as computer monitors, mobile phones, personal digital assistants (PDAs), or flat panel televisions. In general, the LCD device comprises liquid crystal layers encapsulated by two substrates and a backlight system for providing a light source. The operation of an LCD device is featured by varying voltage drops between opposite sides of the liquid crystal layers for twisting the angles of the liquid crystal molecules of the liquid crystal layers so that the transparency of the liquid crystal layers can be controlled for illustrating images with the aid of the backlight system.
The backlight system of an LCD device is normally disposed at the lower or lateral sides of the LCD panel of the LCD device. The backlight system in conjunction with various optical devices (such as diffusers and prisms) is able to provide a high-intensity and uniform light source for the LCD panel. That is, based on the voltage drops between opposite sides of the liquid crystal layers of the LCD panel with the aid of the uniform light source, the luminance and chromaticity of panel pixels can be controlled precisely so that the LCD device is capable of displaying high-quality images.
Please refer to FIG. 1, which is a structural diagram schematically showing a prior-art backlight system. As shown in FIG. 1, the backlight system 100 comprises a driving circuit 160, a transformer 120, a capacitor 180, and a lamp 140. The lamp 140 of the backlight system 100 is driven based on single-side driving mode. The transformer 120 comprises a first winding (primary winding) 121 and a second winding (secondary winding) 122. The driving circuit 160 is utilized to provide an AC driving voltage to the first winding 121 of the transformer 120. The second winding 122 of the transformer 120 in conjunction with the capacitor 180 performs a resonant operation for generating an AC voltage Vx having a high peak-to-peak voltage. The AC voltage Vx is then utilized to drive the lamp 140 for lighting. It is well-known that the length of the lamp 140 is increased with the panel size of liquid crystal display devices, and the peak-to-peak voltage of the AC voltage Vx should be also increased for driving the lamp 140 having greater length. Consequently, the current leakage of the lamp 140 becomes more serious resulting from the greater AC voltage Vx. Furthermore, the capacitor 180 and the transformer 120 are a costly high-voltage capacitor and a costly high-voltage transformer respectively for providing the greater AC voltage Vx. In view of the aforementioned shortcomings concerning the prior-art backlight system 100, it is obvious that backlight systems based on single-side driving mode cannot meet future demands for LCD devices having large panel size.
Please refer to FIG. 2, which is a structural diagram schematically showing another prior-art backlight system. As shown in FIG. 2, the backlight system 200 comprises a first driving circuit 260a, a second driving circuit 260b, a first transformer 220a, a second transformer 220b, a first capacitor 280a, a second capacitor 280b, and a lamp 240. The lamp 240 of backlight system 200 is driven based on double-side driving mode. The first driving circuit 260a is utilized to provide a first AC driving voltage to the first winding 221 of the first transformer 220a. The second driving circuit 260b is utilized to provide a second AC driving voltage to the first winding 223 of the second transformer 220b. The second winding 222 of the first transformer 220a in conjunction with the first capacitor 280a performs a resonant operation for generating a first AC voltage Va having a high peak-to-peak voltage. The second winding 224 of the second transformer 220b in conjunction with the second capacitor 280b performs a resonant operation for generating a second AC voltage Vb having a high peak-to-peak voltage. Therefore, both the first capacitor 280a and the second capacitor 280b should be costly high-voltage capacitors. The first AC voltage Va is furnished to the first end of the lamp 240. The second AC voltage Vb having opposite phase relative to the first AC voltage Va is furnished to the second end of the lamp 240. That is, the lamp 240 is driven based on the first AC voltage Va and the second AC voltage Vb having phase opposite to each other.
Due to production inaccuracy, aging or other factors, parameter discrepancy may occur to different elements, such as the capacitance deviation between the first capacitor 280a and the second capacitor 280b or the winding deviation between the first transformer 220a and the second transformer 220b, and therefore the currents furnished to the first and second ends of the lamp 240 may not have same current value. In addition, the current leakage of the lamp 240 is likely to occur under high-voltage operation because of parasitic capacitors corresponding to the lamp 240 regardless of the lamp 240 being a cold-cathode fluorescent lamp (CCFL) or an external electrode fluorescent lamp (EEFL). Consequently, the current inconsistency at the first and second ends of the lamp 240 is likely to occur in the operation of the backlight system 200. That is, the lamp 240 of the backlight system 200 is not able to generate uniform light output, and therefore display panels using the backlight system 200 cannot display images accurately.

Backlight system having a lamp current balance and feedback mechanism and related method thereof