The present invention relates to a method for producing an antenna comprising a conductive wire, formed by a wire, made of a conductive material, whose path has a helical shape. In accordance with the invention, such a method is characterized in that a print is formed in relief on one side of an element of an electrically insulating material such that the helical shape is generated by depositing the conductive material in this print.

An antenna is a unit for transmitting and/or receiving electromagnetic radiation. It is used in numerous communication systems that require one or more of these radiating units.
When several antennas are associated for a single common function, the set of these antennas is known as a network of antennas. A network of antennas provides certain advantages in relation to one antenna, such as providing greater directivity, the equivalent radiating aperture of a network being greater than that of a single antenna within this network.
Helical antennas, i.e. antennas formed by a conductive wire whose path describes a helix, are used in many systems such as mobile phones, sources for the focal points of a concentrating system or the major antenna networks.
FIG. 1a shows the projection of a helical antenna 100 onto a plane comprising the longitudinal axis 104 of the antenna and FIG. 1b shows the projection view of the antenna 100 on a plane perpendicular to the longitudinal axis 104 of the antenna.
FIG. 1b enables the interior 105 of the helix to be defined as the volume generated by the cylinder of an axis and radius equal to the axis and radius of the helix, the exterior 107 of the helix being the volume surrounding the interior 105.
A helical antenna 100 comprises one or more conductive wire segments 102 of a helical or spiral form. Each segment 102 can be defined by its length 108 according to the longitudinal axis 104, by the number of turns 110, by the cross-section 112 of the wire, by the pitch 114 of the helix, by the angle of inclination 116 of the helix (angle between a tangent to the helix and a plane perpendicular to the axis 104 of the antenna), by the radius 106 of the helix and by the nature of the conductive material forming the wire.
Moreover, it must be noted that these parameters can be variable or constant along the axis 104 of the helix, and particularly along a segment 102.
Such a helical antenna 100 has several operating modes that depend on various parameters such as its radius 106, its angle 116 of inclination of the turns 110 and its pitch 114.
According to a first polarisation mode, a helix can be polarised along its longitudinal axis 104 (linear polarisation) in a mode called normal, this linear polarisation being used particularly in mobile phones.
According to a second mode, a helix can also be polarised in a circular manner (circular polarisation in a mode known as axial) around the helix axis when the helix radius is in the order of the wavelength of the waves to be transmitted or received, this circular polarisation being generally used, for example, for the helical antennas present at the focal points of parabolic antennas used to receive and transmit electromagnetic waves coming from satellites.
In this latter case, the quality of the circular polarisation depends on the number of turns 110, whereas the directivity depends on the length 108 of the antenna.
It is known that a helical antenna is manufactured according to several distinct methods, these methods being described hereafter:
A first manufacturing technique consists in conferring a helical profile on a conductive wire by forming, in a manner analogous to the manufacture of a spring.
A second manufacturing technique consists in winding a conductive wire around an insulating element such as a plastic tube or a foam block, the insulating element being used to support the helix.
The insulating element can subsequently be left or removed if the strength of the helical antenna is great enough to retain its shape without the support.
A third technique consists in printing one or more conductive lines diagonally on a substrate, for example, a sheet of an insulating element that is folded onto itself, thus forming a helix whose angle of inclination is the angle of the diagonal on the substrate.
Moreover, when antennas are manufactured individually, it may be necessary to group these antennas into a network, in which case these antennas must be linked together by a rigid conductive element and a driver circuit.
These methods for manufacturing antennas have various drawbacks. Hence, the forming technique requires sufficient rigidity from the conductive element whereas the manufacturing methods according to the second and third techniques, i.e. by winding around a support or by folding a substrate, are relatively complex and costly to implement, particularly owing to the required deformation of the conductive wire (for winding) or the substrate (for folding).
Finally, these known methods only apply to the manufacture of individual antenna of such a sort that grouping several antennas into a network requires other specific operations, thus increasing the cost of manufacturing a network.
During these operations specific to grouping antennas into a network, it must be noted that each antenna must be connected to the entire network with a mechanical rigidity sufficient to retain, over a long period, the polarisation characteristics of the antenna network in its entirety, which is particularly complex and costly.
Now, it is known that, in a network, the antennas must keep their directions with respect to each other and with respect to the driver circuit, so that the driver circuit can maintain its performances.


A solid state microwave switch having a plurality of adjacent parallel fingers covered with an oxide layer. One end of a finger is an N+ source region while the other end is an N+ drain region, with a current conducting N region between them. The oxide layer is covered with a gate layer to which a gate signal is applied for control of current between the N+ regions through the N region. The gate layer is highly resistive and has a sheet resistance on the order of millions of ohms per square. The length from the source to drain region is around 2 xcexcm, and the fingers are spaced with a pitch of around 1 xcexcm.

1. Field of the Invention
The invention in general relates to miniature switches and more particularly to a switch useful in radar and other high frequency applications.
2. Description of Related Art
A variety of MEMS (microelectromechanical systems) switches are in use, or proposed for use, in radar, as well as other high frequency circuits for controlling RF signals. These MEMS switches are popular insofar as they have a relatively high off impedance and a relatively low on impedance, with a low off capacitance, leading to desirable high cutoff frequencies. Additionally, the MEMS switches have a small footprint and can operate at high RF voltages.
These MEMS switches generally have electrostatic elements which are attracted to one another upon application of a control signal. This may possibly lead to short and long term variability in the switching voltage due to, for example, uncontrolled electrostatic charging effects. In addition, the manufacturing yield and potential need for hermetic sealing of the MEMS switches are of concern.
Traditionally, many RF circuits utilize solid state switch elements for RF signal control. For example, electronic RF switches in common use include the GaAs (gallium arsenide) based PMEMT (pseudomorphic high electron mobility transistor) and the GaAs pin diode. Both of these devices can operate at high cutoff frequencies and can achieve switching rates measurable in tens of nanoseconds.
For some applications however, the GaAs PHEMT has an objectionably high resistance when closed and a relatively low cut-off frequency, for example, 600 GHz (Gigahertz). The pin diode exhibits a higher cut-off frequency of around 2 THz (Terahertz), however it, along with the GaAs PHEMT, can exhibit an objectionably high capacitance in the off state. For this reason these RF switches are often operated with a separate shunt inductor resonant with the capacitance, at the operating frequency.
This added inductor advantageously increases the impedance of the switch in the off condition, however this arrangement objectionably lowers the operating bandwidth of the overall switch device.
In an ideal switch, during operation the switch impedance would be infinite when open (Zoff), to prevent signal flow, and zero (Zon) when closed to allow signal flow without adding any undesired impedance. That is, the ideal Zoff/Zon would be equal to infinity. This however is not possible and a practical acceptable value would be on the order of 100 or 200. Most variable capacitive MEMS type and solid state switches do not achieve this high isolation ratio.
This Zoff/Zon ratio is also related to the ratio of the cutoff frequency Fcc to the operating frequency Fo. That is:
Zoff/Zon=Fcc/Foxe2x80x83xe2x80x83Eq. (1)
Basically, the higher the cutoff frequency Fcc the higher the operating frequency Fc can be while still maintaining a desired off/on impedance ratio of 100 or higher. For example, with a Fcc=1 THz, the operating frequency can be as high as 10 GHz. Devices with higher cutoff frequencies would accommodate even higher operating frequencies, particularly suited for radar and other high frequency circuits.
It is a primary object of the present invention to provide a solid state switch having a cutoff frequency in the THz range, and which is highly reliable, is reproducible, economical and has a small footprint. Additionally, the switch of the present invention can achieve a Zoff/Zon ratio of 100 or greater at 10 GHz or more. Further, the switch allows realization of cutoff frequencies as high as 5 THz as a result of its unique fabricatable geometry.
An RF switch in accordance with the present invention includes a plurality of parallel semiconductor fingers each having first and second ends, with one of the ends constituting a source region and the other end constituting a drain region. Each finger has a width no more than around 5000 xc3x85. An oxide layer is formed on the outside of the finger and a high resistance gate layer is deposited on the oxide layer. This gate layer has a sheet resistance ranging from around 100,000 to millions of ohms per square. Respective electrical contacts are in electrical communication with the gate layer and source and drain regions.

Solid state RF switch with high cutoff frequency


A backlight assembly includes a receiving container receiving a light guide plate and a lamp and a fixing member holding the light guide plate. The fixing member supports an incident face of the light guide plate, into which a light emitted from the lamp is incident, thereby preventing movement of the light guide plate towards the lamp. Thus, the backlight assembly may fix the light guide plate to the receiving container without reforming the light guide plate, so that the backlight assembly may supply light having uniform brightness to a liquid crystal display panel to improve its display characteristics.

1. Field of the Invention
The present invention relates to a backlight assembly and a liquid crystal display ("LCD") apparatus having the same. More particularly, the present invention relates to a backlight assembly having improved display characteristics and a display apparatus having the backlight assembly.
2. Description of the Related Art
In general, a liquid crystal display ("LCD") apparatus displays an image using optical and electrical properties of liquid crystal, such as an anisotropic refractive index, an anisotropic dielectric constant, etc.
The LCD apparatus requires a backlight assembly to apply a light to an LCD panel since its display panel is not self-emissive.
The backlight assembly includes a lamp that generates the light, a light guide plate that guides the light to the LCD panel from the lamp, a reflecting sheet disposed under the light guide plate to reflect light leaking from the light guide plate, an optical sheet that improves a brightness of light exiting from the light guide plate, and a receiving container that receives the lamp, the light guide plate, the reflecting sheet, and the optical sheet.
Recently, efforts have been made regarding the LCD apparatus having high brightness in order to improve display quality of the LCD apparatus. As an example of a light guide plate for providing high brightness, a prism light guide plate has been developed. The prism light guide plate includes a fine-pitch prism pattern formed on a lower face thereof. Thus, although only one prism sheet is disposed on the backlight assembly, the LCD apparatus enhances brightness of the light.
However, since the prism light guide plate has the prism pattern formed on the lower face, a dark area or a brightness line occurs at the prism pattern. Further, the prism pattern is easily damaged when the prism light guide plate moves.

Backlight assembly and display apparatus having the same


Aspects of a method and system for tunneling MACSec packets through non-MACSec-enabled nodes are provided. In this regard, aspects of the invention may be utilized for transmitting MACSec Ethernet packets over MACSec and/or non-MACSec-enabled network nodes. In one embodiment of the invention, additional header information may be inserted into a MACSec packet before transmitting the MACSec packet to a non-MACSec-enabled node. Accordingly, aspects of the invention may remove the additional header information from a packet received from a non-MACSec-enabled node to distinguish the packets comprising inserted additional header information, which may comprise a distinguishing Ethertype.

A computer network is a collection of two or more computing nodes, which are communicatively coupled via a transmission medium and utilized for transmitting information. Most networks adhere to the layered approach provided by the open systems interconnect (OSI) reference model. The OSI reference provides a seven (7) layer approach, which includes an application layer, (Layer 7), a presentation layer (layer 6), a session layer (Layer 5), a transport layer (Layer 4), a network layer (Layer 3), a data link layer (Layer 2) and a physical layer (Layer 1). Layer 7 through layer 5 inclusive may comprise upper layer protocols, while layer 4 through layer 1 may comprise lower layer protocols. Some networks may utilize only a subset of 7 layers. For example, the TCP/IP model, or Internet Reference model generally utilizes a fiver layer model, which comprises an application layer, (Layer 7), a transport layer (Layer 4), a network layer (Layer 3), a data link layer (Layer 2) and a physical layer (Layer 1). These five layers can be broken down into a fairly specific set of responsibilities or services, which they provide.
Layer 7, the application layer, is typically responsible for supporting network applications such as web browsers and email clients, and is typically implemented in software in end systems such as personal computers and servers. Typical layer 5 protocols comprise HTTP to support the World Wide Web, and SMTP to support electronic mail.
Layer 6, the presentation layer, is typically responsible for masking any differences in data formats that may occur between dissimilar or disparate systems. The presentation layer specifies architecture independent data transfer formats and may enable encoding, decoding, encryption, decryption, compression and/or decompression of data.
Layer 5, the session layer, is typically responsible for managing user session dialogues. In this regard, the session layer may be enabled to control establishment and/or termination of logical links between users. The session layer may also be enabled to provide handling and reporting of upper layer errors.
Layer 4, the transport layer, is typically responsible for passing application layer messages between the client and server sides of an application. In this regard, the transport layer may be enabled to manage end-to-end delivery of messages in the network. The transport layer may comprise various error recovery and/or flow control mechanisms, which may provide reliable delivery of messages. By far the two most common Layer 4 protocols are transmission control protocol (TCP) and user datagram protocol (UDP), which are used in the Internet.
Layer 3, the network layer, is typically responsible for determining how data may be transferred between network devices. Data may be routed according to unique network addresses. In this regard, the network layer may route, for example, datagrams between end systems. Internet Protocol (IP), for example, defines the form and content of the datagrams and is implemented in Layer 3 in combination with any number of routing protocols which may be implemented in the various nodes (devices such as bridges and routers) along a datagram's path from one end system to another.
Layer 2, the data link layer, is typically responsible for moving a packet of data from one node to another. The data link layer defines various procedures and mechanisms for operating communication links and may enable, for example, the framing of packets within the network. The data link layer may enable detection and/or correction of packet errors. The Ethernet (IEEE 802.3) protocol is one common link layer protocol that is used in modern computer networks.
Layer 1, the physical layer, is typically responsible for defining the physical means, which may comprise optical, electrical and/or mechanical means for communicating data via network devices over a communication medium. The converting the bit stream from Layer 2 into a series of physical signals for transmission over a medium. Layer 2 technologies such as Ethernet may implement a number of Layer 1 protocols depending on whether the signal is to be transmitted over twisted-pair cabling or over-the-air for example.
At Layer 2, today's enterprise networks are based predominantly on IEEE 802.3 Ethernet technology. While Ethernet offers ubiquitous and inexpensive connectivity to the Enterprise, it is not particularly strong in controlling access to that network. Although IEEE has attempted to improve access control for wired Ethernet with the IEEE 802.1x standard, this standard did not receive widespread adoption due to a number of reasons. One of these negative factors related to IEEE 802.1x deployment was the fact that 802.1x only validated the users as they signed onto the network and it adhered to the one device per port model. There was no per-packet validation, neither was there any standardized method of implementing access control while supporting more than one device per port. Vendors did provide non-standardized means to provide the latter, but the former remained unimplemented.
IEEE standards 802.1ae, 802.1af, and 802.1ar form the basis of a new architecture for network access control for Ethernet networks. These three standards form a replacement for the existing IEEE 802.1x based access control mechanisms. The IEEE 802.1ae (MACSec) standard defines the data link layer encryption and authentication mechanisms. IEEE 802.1af (currently under development) defines the control plane and keying protocols for 802.1ae. IEEE 802.1ar (currently under development) defines how the network and the devices connected to the network identify and validate each other's identities.
MACSec integrates security into wired Ethernet by identifying the devices connecting to a LAN and classifying the devices as authorized or unauthorized. Exemplary network devices that may be identified and classified comprise computers, wireless access points, servers, VOIP telephones, routers, switches, bridges and hubs.
Although MACSec may provide greater network security and reliability, upgrading an existing network to be MACSec compatible may present problems. In this regard, MACSec provides network protection at the data link layer by encrypting the data of an Ethernet frame, inserting a header (SecTAG) between the source MAC address and the encrypted data, and appending an integrity check value (ICV) after the encrypted data. Consequently, because the SecTAG of a MACSec frame occupies the bit positions normally used for one or more virtual local area network (VLAN) tags in a traditional Ethernet frame, non-MACSec-enabled network nodes may be unable to process MACSec frames, as the SecTAG may be improperly parsed as a VLAN tag.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Method and system for tunneling MACSec packets through non-MACSec nodes


Wafer processing apparatus for batch processing of wafers comprises a turntable, having a polishing surface thereon, capable of rotation about a turntable rotation axis. A pressure plate is constructed for simultaneously holding multiple wafers with a polish face of the wafers facing the polishing surface of the turntable. A polisher head capable of applying a normal force to the pressure plate is provided to drive the pressure plate toward the turntable so that the polish face of the wafers engages the polishing surface of the turntable for polishing of the wafers. A force distributing member intermediate the polisher head and the pressure plate is constructed for uniformly distributing the force applied by the polisher head to the pressure plate.

This invention relates to apparatus for batch processing wafers of semiconductor or similar type material, and more specifically to such apparatus which permits batch processing of the wafers with improved uniformity, throughput and yield.
Polishing an article to produce a surface which is highly reflective and damage free has application in many fields. A particularly good finish is required when processing an article such as a wafer of semiconductor material in preparation for printing circuits on the wafer by an electron beam-lithographic or photolithographic process. Flatness of the wafer surface on which circuits are to be printed is critical in order to maintain resolution of the lines, which can be as thin as 1 micron or less.
Flatness is quantified using a number of measuring methods. For example, "Taper" is a measurement of the lack of parallelism between the unpolished back surface and a selected focal plane of the wafer. "TIR", or Total Indicated Reading, is the difference between the highest point above the selected focal plane and the lowest point below the focal plane, and is always a positive number. "FPD", or Focal Plane Deviation, is the highest point above, or the lowest point below, the chosen focal plane and may be a positive or negative number. "TTV", or Total Thickness Variation, is the difference between the highest and lowest elevation of the polished front surface of the wafer. Presently, flatness of the polished surfaces of wafers is not significantly improved, and may be worsened, by the polishing process. In batch processing using currently known polishing apparatus, there will be a significant number of wafers which fail to meet flatness and polishing specifications after polishing, thus adversely affecting yield in commercial production.
Conventional batch polishing machines include a disc-shaped polishing pad mounted on a turntable for driven rotation about a vertical axis passing through the center of the pad. The wafers are fixedly mounted on a pressure plate above the polishing pad and forced into polishing engagement with the rotating polishing pad. A polishing slurry, typically including chemical polishing agents and abrasive particles, is applied to the pad. In order to achieve the degree of polishing needed, a polisher head is driven against the pressure plate by a hydraulic cylinder to apply a substantial normal force to the plate for pressing the wafers into polishing engagement with the pad.
Batch wafer processing using the conventional batch polishing machine described above has a number of associated disadvantages. For example, the wafers tend to become tapered toward their peripheral edges during batch polishing. Also, where the surface of the polisher head and/or the pressure plate contains non-uniformities, such as where the surface contains dirt build-up or contains irregularities (e.g., bumps, cavities, etc.) caused during manufacture or subsequent damage, the driving force of the polisher head is non-uniformly transferred to the pressure plate. This results in non-uniform pressure between the wafers and the polishing pad, causing a deterioration of the flatness and parallelism of the wafers and a lack of consistency between wafers of the same batch.
Moreover, during the polishing process, the coefficient of friction between the polishing pad and the wafers is quite high, oftentimes in the vicinity of two. This friction causes substantial temperature increases, including in the polisher head, which can result in deformation of the polisher head surface. This leads to the same non-uniform force transfer problems discussed above. To minimize this risk, water or other coolant must be circulated in the polisher head to continually cool the polisher head surface and reduce the deformation of the surface. This circulation system thus increases the complexity and cost of manufacturing the conventional polishing apparatus.
It is known to provide fiberglass or felt rings between the polisher head and the pressure plate to overcome the tapering of the peripheral edges of the wafers during batch processing. The ring has a diameter smaller than the pressure plate and polisher head diameter so that the driving force of the polisher head is transferred to the pressure plate in an annular pattern inward of the edges of the pressure plate. This causes the pressure plate to bend upward slightly at its edges, thereby reducing the tapering of the wafers at the edges of the wafers. However, because they are solid, the material from which the ring is constructed cannot be redistributed to other portions of the ring when it is deformed (e.g., compacted) by non-uniformities in the surfaces of the polisher head and pressure plate. Thus, a localized force is transferred through the ring to the pressure plate, causing non-uniform pressure driving the wafers against the polishing pad. In addition, these rings cannot be produced with a sufficiently uniform compressive strength and thickness to transmit a uniform pressure over the entire area of contact between the polisher head and the pressure plate.
The problems of yield associated with batch processing are somewhat alleviated by single wafer processing, in which each wafer has its own polisher head. In my previously issued U.S. Pat. No. 5,193,316, I disclosed a fluid filled bag that can be used for processing a single wafer and reduces the effect of surface non-uniformities. The bag is generally equal in size to the wafer and is placed between the wafer and an individual piston head that forces the wafer against the polishing surface so that non-uniformities of the piston surface do not negatively affect polishing of the wafer. Single wafer processing also eliminates the problems of forces transmitted through the pressure plate from one wafer to another. However, this fluid filled bag cannot be used for batch polishing, such as by being placed between the polisher head and the pressure plate, because a uniform transfer of force from the polisher head over substantially the entire surface of the pressure plate would result in tapering of the peripheral edges of the wafers in the same manner as described above with respect to the conventional polishing apparatus. In addition, single wafer polishing has a very low throughput because only a single wafer per pressure plate is polished at a time.


An in-vehicle battery system comprises a first power storage module including a lead-acid battery, and a second power storage module including a power storage portion having a higher energy density than that of the lead-acid battery. The lead-acid battery and the power storage portion are electrically connected in parallel to a power generating portion which converts a regenerative energy to electric power. The first power storage module and the second power storage module are provided in an engine room of a vehicle. The second power storage module is disposed more distantly than the first power storage module from an engine.

Generally, in a vehicle having an internal-combustion engine as a driving source, a lead-acid battery which supplies power to various electric loads of a starter motor or the like, is installed. The lead-acid battery is inexpensive, compared with a high performance storage battery having a high output and a high energy density of a nickel hydride storage battery, a lithium ion storage battery, or the like. However, the lead-acid battery is low in a durability of frequent charging and discharging. Especially, in the vehicles having the idle stop function (the idle reduction function), as the lead-acid battery is frequently discharged, it is considered that the lead-acid battery is early degraded. Further, in the case that the lead-acid battery is charged by a power generation of an alternator from a regenerative energy of the vehicle, as the lead-acid battery is frequently charged, it is considered that the lead-acid battery is earlier degraded. Against this, only replacing the lead-acid battery with the high performance storage battery largely increases costs.
In contrast, a vehicle battery device including a generator of an alternator or the like, a lead-acid battery which is charged with power generated the generator, and a second storage battery which is electrically connected in parallel to the lead-acid battery and is charged with power generated the generator and has a high output or energy density compared with the lead-acid battery, have been known (refer to patent literature 1). In this way, by having the second storage battery of a high performance in addition to the lead-acid battery, a degradation of the lead-acid battery is suppressed, and in addition it is inexpensive. Namely, for example, the high performance storage battery preferentially caries out power supply to the electric loads during the idle stop and a regenerative charging, and then the degradation of the lead-acid battery can be decreased. On the other hand, the inexpensive lead-acid battery preferentially carries out power supply for a long time at the time of parking the vehicle or the like, and then the high performance storage battery can be made a low capacity, and costs can be suppressed.


A liquid level sensor for measuring liquid levels in underground and above ground containers includes a frame formed to have an elongate hollow tubular configuration that encloses a cavity. A cam pivot has an end extending into the cavity from a first inner wall portion of the frame. A cam is arranged to be pivotal about the end of the cam pivot. A float is placed in the cavity. A spring is arranged to bias the cam arm into contact with the float to force a side portion of the float into a locked position in frictional engagement with the second inner wall portion of the frame. A cam actuator pivotally mounted in a lower end portion of the frame exerts a force on the cam arm to release the float from the locked position when the lower end of the frame contacts the container bottom.

This invention relates generally to measuring liquid depth and particularly to measuring liquid level in containers located, both above and below ground.
U.S. Pat. No. 4,802,363, which issued Feb. 7, 1989 to one of the present inventors, discloses an apparatus for measuring liquid level, which although satisfactory for some uses, is inconvenient for some situations that arise in measuring liquid levels. The device disclosed in U.S. Pat. No. 4,802,363 has a rectangular float that is centered in a rectangular tube. Using this device requires rotation of a handle to unlock the float so that it can float to the liquid surface. The rectangular bar that actuates this locking action must be precisely centered along the full length of the rectangular tube in order to assure that a false lock will not occur. If this center rectangular bar becomes even slightly bent, twisted or concentrically displaced due to rough usage, it can cause the measuring float to be jammed in the tube and give an erroneous reading.

Mechanically self actuated liquid level sensor


A circuit breaker comprising a first dc line electrically connectable to first incoming and first outgoing dc lines, wherein the first dc line comprises a first fault-interrupting switch contact system and a first switching aid network. The first switching aid network comprises first and second rectifier strings, wherein each rectifier string comprises one or more series connected reverse blocking power electronic devices that define a first H-bridge rectifier. The first switching aid network further comprises a snubber string, the snubber string comprising at least one series connected power electronic devices capable of being turned on by gate control and a capacitor. The first switching aid network further comprises a pre-charge string comprising at least one series connected power electronic devices capable of being turned on by gate control and a resistor, and a surge arrester connected between the first and second dc output terminals of the first H-bridge rectifier.

At present, there are no known circuit breaker switch contact systems that can interrupt high levels of direct current and then immediately withstand a high re-applied high dc voltage between contacts. It is known for circuit breaker switch contact systems to be able to carry high levels of direct current and to be able to block high direct current (dc) voltage but not for such circuit breaker switch contact systems to transit from the former to the latter state.
Line commutated static power converter (LCC) based HVDC transmission networks are known and any requirement to interrupt direct current in the HVDC transmission line under normal load and fault current circumstances has typically been provided by two means. First, by phase control of the LCC rectifier at the power transmitting end of the transmission line. Second, by using heating, ventilation, and air conditioning (HVAC) switchgear to interrupt the ac supply to the LCC rectifier.
LCC system usage has generally been confined to point-to-point HVDC transmission networks because the means by which LCCs interrupt HVDC transmission line fault current makes it mandatory to reverse the transmission line voltage. Such voltage reversals will affect all terminals in an LCC-based multi-terminal HVDC network and the exceptional LCC-based multi-terminal HVDC networks have therefore been designed on the basis that the control systems of the LCCs at all terminals must have protection features that are coordinated in a manner that prevents power flow between two fully functional terminals when a third terminal suffers a fault. An additional aspect of such voltage reversals is that the HVDC line insulation performance is adversely affected by voltage reversals and all known line insulation systems that are compatible with such voltage reversals are subject to cost and/or size penalties.
Force commutated voltage source converter (VSC) based HVDC transmission networks are also known and provide a number of power system benefits which include a bidirectional power flow capability that is achieved with a unidirectional and substantially constant HVDC transmission voltage. Known VSC topologies have an inability to limit and interrupt rectifying mode dc link current and HVAC switchgear has been used to interrupt the ac supply to the VSC in rectifying mode. One potential advantage of known VSC topologies is that their unidirectional and substantially constant HVDC transmission voltage would be beneficial to multi-terminal HVDC transmission networks wherein reversible power flow between any and all terminals is a requirement. However, given the inability of known VSC topologies to limit and interrupt rectifying mode dc link current, and also given the non-availability of circuit breaker switch contact systems that can interrupt high levels of direct current and then immediately withstand a high re-applied high dc voltage between contacts, all terminals of such multi-terminal HVDC transmission networks would suffer a discontinuity of power flow while several steps take place. Such steps include: HVAC switchgear at all terminals are opened to clear fault current; HVDC off load isolators are opened to isolate the HVDC terminals of the faulty terminal; HVAC pre-charging switchgear at all terminals are closed in order to allow the HVDC transmission voltage to be re-instated and corresponding VSCs to be re-synchronised with their HVAC network; and HVAC switchgear at all terminals are closed in order to allow the re-instatement of HVDC power flow.
Appropriate power system design processes would be used to enable the duration of this discontinuity of power flow to be minimised but a duration of at least one second might be expected.
Another critical aspect of power system design would be that of HVDC transmission line fault current limitation, it being the case that the HVDC fault current magnitude would be the summation of the contributions from the respective terminals. The thermal effect of such an HVDC fault current scenario upon cable and switchgear ratings would be significant.
Multi-terminal HVDC transmission networks have been proposed as the principal method of overcoming the effects of the inherent discontinuity and inconvenient location of energy devices (e.g. wind turbines, subsea turbines, and other renewal energy devices that extract energy from waves or tidal flows) or other power sources, and at the same time these networks would increase security of power supply to the loads that are fed by each terminal. Requirements are emerging for extensive and complex interconnection of remotely sited power sources and loads and, taking into account the known limitations of HVAC transmission networks, it is recognised that a multi-terminal HVDC approach would be most appropriate if the above mentioned obstacle of HVDC current interruption was removed. Accordingly, many methods of overcoming this obstacle, i.e. satisfying the requirement to interrupt current in HVDC circuits, have been proposed but none have yet reached practical feasibility.
The series and/or parallel connection of many circuit breaker switch contact systems in a manner that reduces the volt-amp rating of individual switch contact systems is known not to be viable at the ratings of interest (typically >100 kV and >1000 A) and so these methods have generally employed the principle of hybridisation of a switch contact system, that is able to carry high levels of direct current and is able to block high dc voltage but is not able to transit from the former to the latter state, with another circuit that performs the current interruption. The following aspects of hybridisation are known, either in the context of ac current interruption or dc current interruption:
The connection of a passive resonant circuit in parallel with a circuit breaker switch contact system in order to cause momentary reversals of current in the open and arcing switch contact system. Such an arrangement is inherently capable of operating with dc current in both polarities and having low power losses.
The connection of a spark gap switched passive resonant circuit in parallel with a circuit breaker switch contact system in order to cause momentary reversals of current in the open and arcing switch contact system. Such an arrangement is inherently capable of operating with dc current in both polarities and having low power losses.
The connection of a power semiconductor switched and pre-charged passive resonant circuit in parallel with a circuit breaker switch contact system in order to cause momentary reversals of current in the open and arcing switch contact system. Such an arrangement is not capable of operating with dc current in both polarities but power losses are low.
The connection of a gate commutated power electronic switching device in parallel with a circuit breaker switch contact system, the power electronic switching device being set to turn on before the switch contacts open and turn off after switch contacts open, thereby causing the switch contacts to open with a very low voltage between contacts (the on state voltage drop of the power semiconductor device). Such an arrangement is capable of operating with dc current in both polarities when a gate commutated switching device is provided for each polarity or when such a gate commutated device is incorporated within a diode bridge rectifier, and the system has low power losses.
The connection of an inverse parallel connected pair of gate commutated switching device in series with a capacitor, this series circuit being connected in parallel with a circuit breaker switch contact system, the parallel circuit being connected in series with a series resonant network comprising inductance and capacitance and being tuned to resonate at line frequency. The power electronic switching device is set to turn on before the switch contacts open and turn off after switch contacts open, thereby causing the switch contacts to open with a low and increasing voltage between contacts (the sum of the on state voltage drop of the power semiconductor device and the voltage across the capacitor, the latter voltage being defined to be sufficiently low to prevent re-strike of the ac rated circuit breaker switch contact system and not increasing to a particularly high voltage level since the capacitor is exposed to an ac current waveform). This arrangement is only capable of operating with ac current and the system incurs the power losses associated with the series resonant network.
The connection of a gate commutated power electronic switching device in series with a circuit breaker switch contact system, the power electronic switching device being entirely responsible for interruption of current, the series connected switch contact system being used for off load isolation purposes and being reliant upon the prior operation of the power electronic switching device or ac switchgear as described above. Such an arrangement is capable of operating with dc current in both polarities when a gate commutated switching device is provided for each polarity and the system has high power losses.

GE Energy Power Conversion Technology Ltd.


In one embodiment one or more service provider work product of a knowledgebase can be processed according to one or more methods. A knowledgebase can be provided that includes a work product of one or more service provider. According to one method one or more work product of a knowledgebase can be processed.

The service sector of the world economy has grown dramatically in importance over the past century, as compared to the industrial and agricultural sectors. It is estimated that commerce in services now accounts for approximately two-thirds of world GDP, and four-fifths of U.S. GDP.
However, trade in services is not necessarily as efficient or as reliable as trade in the other sectors. In particular, service trade suffers from (1) inefficiencies and a lack of reliability relative to the "matching" of service buyers with service providers, and (2) problems that are inherent to the human performance of services even when matches are optimal—namely high cost, limited repeatability, delivery times that may be longer than desired, and the relatively high potential for error.
In recent years a number of Internet-/web-based "marketplaces" or "service exchanges" have appeared, enabling providers and consumers of services to more efficiently meet and carry out service-related transactions. These systems have in many cases proven to be very useful, providing both service providers and service consumers with a better means of meeting transactional counterparts, and carrying out services work, than was previously available.
However significant inefficiencies and drawbacks particular to the approach common to conventional web-based service exchanges remain. For example, web-based services marketplaces in use today tend to rely fundamentally on descriptions provided by service providers as to the services they can offer, their degree of expertise, and so on. For this reason the systems are susceptible to the problem of exaggeration by service providers.

Knowledgebase with work products of service providers and processing thereof


A load sensor-equipped operation apparatus. An operational member is movably operated. A reaction force member receives an operating force from the operational member, and a reaction force corresponding to the operation force. At least one pivotal connecting portion is interposed between the operational member and the reaction force member, pivotably connecting a pair of a first member and a second member relative to each other to transmit the operating force. A load sensor, which electrically detects the operating force, includes a shaft-like member, a main body member disposed to be relatively displaced in a direction perpendicular to an axis of the shaft-like member, a deformable member bridging the shaft-like member and the main body member, and a strain detecting element secured to the deformable member, which detects deformation of the deformable member. A transmittal link connects the first member to one of the shaft-like member and the main body.

1. Field of the Invention
The present invention relates to an operating apparatus such as a vehicle operating pedal apparatus, and in particular to improvements to a load sensor-equipped operating apparatus that includes a load sensor which electrically detects operating force.
2. Description of Related Art
A load sensor-equipped operating apparatus is known which includes (a) an operational member which is movably operated; (b) a reaction force member that receives the operating force of the operational member transmitted thereto, and on which a reaction force corresponding to the operating force is acted; (c) at least one pivotal connecting portion which is located between the operational member and the reaction force member, and connects a pair of the members pivotably relative to each other to transmit the operating force; and (d) a load sensor which electrically detects the operating force. Patent Document 1 discloses a vehicle brake pedal apparatus as one example of this type of load sensor-equipped operating apparatus. In this apparatus, a push rod (reaction force member) protrudes from a master cylinder, and is connected axially-movably relative to a connecting pin which protrudes from a side of an operational pedal. A sensor detects displacement of the push rod which is displaced against bias force of a spring relative to the connecting pin.
Patent Document 1: U.S. Pat. No. 5,563,355
However, in the apparatus disclosed in Patent Document 1, the push rod is required to have an elongated hole to allow it to move axially relative to the connecting pin. For this reason, normal push rods cannot be used as they are. In addition to this, since the push rod is pivoted relative to the connecting pin when the operational pedal is depressed, the spring biasing the push rod and the sensor detecting the displacement are also required to be pivotable relative to the connecting pin. As a result, firstly, the structure of the apparatus becomes complicated. Secondly, since the push rod, the spring and the sensor are located on the side of the operational pedal, they are required to have a rigid structure which ensures a stably operative state. In particular, this requirement is important for a brake pedal and the like. Consequently, this type of apparatus is large-size and becomes expensive as a whole.
In relation to this, although not publicly known, a technology has been conceived which provides compact arrangement of a load sensor or load detecting sensor at the connection point of a clevis pin as shown in FIG. 16. An operating pedal apparatus 200 for a vehicle service brake is shown in FIG. 16. FIG. 16(a) is a front view of the operating pedal apparatus 200, and FIG. 16(b) is an enlarged cross-sectional view taken along a line XVIA-XVIA in FIG. 16(a). A plate-like operational pedal 16 is attached to a pedal support 12 which is integrally secured to a vehicle, to be pivotable about an axis of a substantially horizontal supporting shaft 14. A depression portion (pad) 18 is located at the lower end of the operational pedal 16 which is depressed by a driver when the braking operation is required, and an operating rod 22 of a brake booster is connected to the middle part of the operational pedal 16 via a pivotal connecting portion 20.
The pivotal connecting portion 20 includes a U-shaped clevis 24 which is integrally secured to the ends of the operating rod 22 by a screw connecting or the like, and a clevis pin 26 which is located in the operational pedal 16 in parallel to the support shaft 14. The operating rod 22 and the operational pedal 16 are pivotably connected relative to each other about an axis of the clevis pin 26. Both end portions or opposite end portions of the clevis pin 26 protrude from both sides of the operational pedal 16, and are locked into the U-shaped clevis 24 by a snap ring, a retaining pin or the like so as not to drop off from the clevis 24.
An output in accordance with the operating force of the operational pedal 16 is transmitted to the operating rod 22 via the pivotal connecting portion 20. A reaction force corresponding to the output is applied to the operational pedal 16 by a brake booster. That is, this operating rod 22 corresponds to a reaction force member. In a by-wire type operating pedal apparatus in which a wheel brake is electrically controlled, a reaction force member which is acted upon by a given amount of reaction force by a reaction force mechanism or the like is connected to the pivotal connecting portion 20 instead of the operating rod 22.
A sensor attaching hole 202 with a diameter larger than the clevis pin 26 is located at the connecting position of the operational pedal 16 where the operational pedal 16 is connected to the clevis pin 26. A load sensor 30 is arranged in the annular space between the sensor attaching hole 202 and the clevis pin 26. The load sensor 30 includes a cylindrical deformable member 32 which detects the load applied in the radial direction thereof. The load sensor 30 additionally includes a cylindrical annular member 34 arranged on an outer periphery side of the deformable member 32, and a shaft-like member 36 arranged on an inner periphery side of the deformable member 32. The annular member 34, corresponds to a claimed main body member, is integrally assembled to the sensor attaching hole 202 at a constant orientation (phase) by press fitting, or by a bolt, a leaf spring or the like. One axial end of the deformable member 32 (the upper end in FIG. 16(b)) is integrally retained to the annular member 34 by welding or the like.
The other axial end of the deformable member 32 (the lower end in FIG. 16(b)) is integrally retained to the shaft-like member 36 by welding or the like. The clevis pin 26 is inserted into an insertion hole 38 which is arranged in the axial part of the shaft-like member 36. The clevis pin 26 is rotatable relative to both the insertion hole 38 and the clevis 24. The clevis pin 26 rotates relative to one of the insertion hole 38 and the clevis 24 that has lower friction when the operational pedal 16 is depressed. Note that a bearing or a bushing may be arranged between the clevis pin and the insertion hole or the clevis in order to reduce friction.
The annular member 34 and the shaft-like member 36 are thus connected by the deformable member 32. When substantially no load is applied from the outside in a radial direction, i.e., in a direction perpendicular to the axis, the members 32, 34 and 36 are retained substantially concentrically to the axis of the clevis pin 26. When a load is applied in a radial direction between the annular member 34 and the shaft-like member 36 by the reaction force of the operating rod 22 with depression of the operational pedal 16, the deformable member 32 is shear-deformed. As a result, the annular member 34 on the operational pedal 16 side displaces relative to the shaft-like member 36 in the direction to be closer to the operating rod 22 (leftward in FIG. 16). An annular space is provided between the annular member 34 and the shaft-like member 36 to allow both the relative radial displacement therebetween, and the shear deformation of the deformable member 32.
The deformable member 32 is made of a metal material such as a ferritic stainless steel alloy which can be elastically deformed by being applied a load in a radial direction, and is shear-deformed in accordance with the operating force with depression of the operational pedal 16. A strain detecting element such as a strain resistance element attached on the outer or inner peripheral surface of the deformable member 32 to detect the shear strain of the deformable member 32 is connected to a control circuit portion of the vehicle via a wire harness 56. Depressing operating force is detected based on the electrical signal which is outputted from the strain detecting element.
In the vehicle operating pedal apparatus 200, at the pivotal connecting portion 20 that transmits the operating force applied to the operational pedal 16 to the operating rod 22, the sensor attaching hole 202 is provided in the operational pedal 16 pivotably connected by the clevis pin 26 to the operating rod 22. Owing to the cylindrical load sensor 30 arranged in the annular space between the sensor attaching hole 202 and the clevis pin 26, rotational moment such as torsion is suppressed, so that the operating pedal apparatus 200 can be constructed simple and compact as a whole. In addition to this, for peripheral members such as the operating rod 22 and the clevis 24, similar members used in conventional pedal apparatuses can be used, which constructs the apparatus at low cost.
However, even in the vehicle operating pedal apparatus 200, when the operational pedal 16 is pivoted about the support shaft 14 by a depressing operation, the operating rod 22 and the operational pedal 16 are also pivoted about the axis of the clevis pin 26. For this reason, the acting position of the load which is applied to the deformable member 32, in other words, the relative displacing direction between the shaft-like member 36 and the annular member 34, varies. This variation may cause variation in the detection value. The size, arrangement and the like of the strain detecting element is set to allow detection of the deformation of the deformable member 32, irrespective of such variation in the deformation position of the deformable member 32. Nevertheless, the deformation position of the deformable member 32 continuously moves in the circumferential direction, and deformation mode thereof is complicated and is likely to vary. For this reason, depending on relative spatial relationships between the operating rod 22 or the operational pedal 16, ensuring high detection accuracy may be difficult.
The present invention has been made in consideration of the above situations, and its object is, in a load sensor-equipped operating apparatus including a load sensor provided in a pivotal connecting portion, to improve the detection accuracy of the load sensor. The load sensor electrically detects operating force based on relative displacement between a shaft-like member and a main body member (annular member 34 in FIG. 16) in a direction perpendicular to an axis of the shaft-like member.

This patent is subject to a terminal disclaimer.

Load sensor-equipped operating apparatus


An electronically controlled pedal assembly with hysteresis includes a housing having a front wall and an arcuate friction wall having a radius of curvature centered on a pedal arm pivot point and extending from an edge of the front wall. The pedal assembly also includes a pedal arm rotatably supported at the pedal arm pivot point by a mounting means operatively connected to the housing, and a hysteresis generating means pivotally mounted to the pedal arm. The pedal assembly further includes a spring positioned between the housing and the hysteresis generating means, such that the spring biases the hysteresis generating means against the housing, so that depression of the pedal arm compresses the spring while generating an increasing frictional hysteresis force between the arcuate friction wall and the hysteresis generating means that is translated back through the pedal arm, and release of the pedal arm reduces the frictional hysteresis force.

1. Field of the Invention
The present invention relates generally to electronic controls for vehicles, and more particularly, to an electronically controlled pedal with a hysteresis device.
2. Description of the Related Art
Vehicles, and in particular automotive vehicles, utilize a foot-operated device, such as a brake pedal or a throttle control pedal, also referred to as an accelerator pedal, to control the movement of the vehicle. Conventional brake systems include a brake pedal for transmitting a braking force from the vehicle operator to the wheels of the vehicle. Similarly, conventional throttle control systems include a throttle pedal to transmit a signal from the vehicle operator to a controller to control acceleration and movement of the vehicle. Recent innovations in electronics technology have led to increased use of electronic controls for vehicle systems, such as the throttle system or the brake system.
In an electronically controlled throttle control system, the pedal arm is attached to a position sensor, which senses the relative position of the pedal arm and transmits a signal to a controller to operate the throttle. The electronically controlled brake system operates in a similar manner. However, since the pedal arm is not attached to a mechanical device, such as a rod or cable, there is no resistance to depression of the pedal, and the pedal returns to a nominal position quicker than with a mechanical system. This resistance is referred to as hysteresis. Hysteresis is advantageous because it provides the driver with a better "feel" of the pedal. Without a predetermined amount of hysteresis in the pedal, the driver may experience increased foot fatigue from the rapid adjustment of the pedal, especially when driving over a long period of time. In the past, a mechanical device was utilized to simulate the resistance to depression produced by a brake rod or a throttle cable in conventional pedal system, and return the pedal to its resting position. For example, European Patent No. EP 0748713 A2 discloses the use of a spring to return the pedal to its resting position. Another example of a mechanical device is a friction pad connected to an extension of the pedal arm to develop hysteresis during depression of the pedal. However, previously known hysteresis devices are complicated and utilize many parts.
At the same time, various position sensing devices are known in the art to sense the relative position of the accelerator pedal as the operator depresses or releases the accelerator pedal in controlling movement of the vehicle. One example of a position sensing device is a potentiometer. Another example of a position sensing device is an induction sensor. While these types of sensors work well, they are relatively expensive and may be difficult to package within the confined interior environment of the vehicle.
Thus, there is a need in the art for a hysteresis device for use with an electronically controlled pedal that has a minimal number of component parts and is cost-efficient to produce.

Electronic throttle control with hysteresis device


There is provided an electrolytic processing device including: a processing electrode to be brought into contact with or close to a workpiece; a feeding electrode for supplying electricity to the workpiece; an ion exchanger disposed in at least one of spaces between the workpiece and the processing electrode, and between the workpiece and the feeding electrode; a power source for applying a voltage between the processing electrode and the feeding electrode; and a liquid supply section for supplying a liquid to the space between the workpiece and at least one of the processing electrode and the feeding electrode, in which the ion exchanger is present. A substrate processing apparatus having the electrolytic processing device is also provided.

1. Field of the Invention
This invention relates to an electrolytic processing device and a substrate processing apparatus provided with the electrolytic processing device, and more particularly to an electrolytic processing device useful for processing a conductive material present on a surface of a substrate, especially a semiconductor wafer, or for removing impurities adhering to a surface of a substrate, and a substrate processing apparatus provided with the electrolytic processing device.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as a material for forming interconnection circuits on a substrate such as a semiconductor wafer, there is an eminent movement towards using copper (Cu) which has a low electric resistance and high electromigration resistance. Copper interconnects are generally formed by filling copper into fine recesses formed in a surface of a substrate. There are known various techniques for forming such copper interconnects, including CVD, sputtering, and plating. According to any such technique, a copper film is formed on substantially an entire surface of a substrate, followed by removal of unnecessary copper by performing chemical mechanical polishing (CMP).
FIGS. 85A through 85C illustrate, in sequence of process steps, an example of forming such a substrate W having copper interconnects. As shown in FIG. 85A, an insulating film 2, such as a silicon oxide film/a film of silicon oxide (SiO2) or a film of low-k material, is deposited on a conductive layer 1a in which electronic devices are formed, which is formed on a semiconductor base 1. A contact hole 3 and a trench 4 for interconnects are formed in the insulating film 2 by performing a lithography and etching technique. Thereafter, a barrier layer 5 of TaN or the like is formed on an entire surface, and a seed layer 7 as an electric supply layer for electroplating is formed on the barrier layer 5.
Then, as shown in FIG. 85B, copper plating is performed onto a surface of the substrate W to fill the contact hole 3 and the trench 4 with copper and, at the same time, deposit a copper film 6 on the insulating film 2. Thereafter, the copper film 6 on the insulating film 2 is removed by performing chemical mechanical polishing (CMP) so as to make a surface of the copper film 6 filled in the contact hole 3 and the trench 4 for interconnects and a surface of the insulating film 2 lie substantially in the same plane. An interconnection composed of the copper film 6 as shown in FIG. 85C is thus formed.
Components in various types of equipment have recently become finer and have required higher accuracy. As sub-micro manufacturing technology has commonly been used, properties of materials are largely influenced by a processing method. Under these circumstances, in such a conventional machining method that a desired portion in a workpiece is physically destroyed and removed from a surface thereof by a tool, a large number of defects may be produced to deteriorate properties of the workpiece. Therefore, it becomes important to perform processing without deteriorating properties of materials.
Some processing methods, such as chemical polishing, electrolytic processing, and electrolytic polishing, have been developed in order to solve this problem. In contrast with conventional physical processing, these methods perform removal processing or the like through chemical dissolution reaction. Therefore, these methods do not suffer from defects, such as formation of an altered layer and dislocation, due to plastic deformation, so that processing can be performed without deteriorating properties of materials.
Chemical mechanical polishing (CMP), for example, generally necessitates a complicated operation and control, and needs a considerably long processing time. In addition, a sufficient cleaning of a substrate must be conducted after a polishing treatment. This also imposes a considerable load on slurry or cleaning liquid waste disposal. Accordingly, there is a strong demand for omitting CMP entirely or reducing a load upon CMP. Also in this connection, it is to be pointed out that though a low-k material, which has a low dielectric constant, is expected to be predominantly used in the future as a material for an insulating film of a semiconductor substrate, the low-k material has a low mechanical strength and therefore has difficulty in enduring stress applied during CMP processing. Thus, also from this standpoint, there is a demand for a technique that enables flattening of a substrate without applying any stress thereto.
Further, a method has been reported which performs CMP processing simultaneously with plating, viz. chemical mechanical electrolytic polishing. According to this method, mechanical processing is performed to a growing surface of a plating film, causing a problem of denaturing of a resulting film.
In a case of the above-mentioned electrolytic processing or electrolytic polishing, processing proceeds through an electrochemical interaction between a workpiece and an electrolytic solution (aqueous solution of NaCl, NaNO3, HF, HCl, HNO3, NaOH, and the like). Since an electrolytic solution containing such an electrolyte must be used, contamination of a workpiece with the electrolyte cannot be avoided.
In recent years, metals of the platinum group or their oxides have become candidates for an electrode material for use in forming a capacitor, which utilizes a high dielectric or ferroelectric material, on a semiconductor substrate. Among them ruthenium, because of its good film-forming properties and good processibility for patterning, is being progressively studied as a feasible material.
A ruthenium film can be formed on a substrate generally by performing sputtering or CVD. In either method, deposition of the ruthenium film on an entire front surface of a substrate, including a peripheral region, is performed. As a result, a ruthenium film is formed also in the peripheral region of the substrate and, in addition, a back surface of the substrate is unavoidably contaminated with ruthenium.
The ruthenium film formed on or adhering to the peripheral region or back surface of the substrate, i.e. a non-circuit region of the substrate, is not only unnecessary, but can also cause cross-contamination during later transfer, storage and various processing steps of the substrate whereby, for instance, performance of a dielectric material can be lowered. Accordingly, during a process for forming a ruthenium film or after peforming some treatments of a formed ruthenium film, it is necessary to completely remove unnecessary portions of this ruthenium film. Further, in a case of using ruthenium as an electrode material for forming a capacitor, a step for removing part of a ruthenium film formed on a circuit region of a substrate is needed.

Electrolytic processing device and substrate processing apparatus


Embodiments disclosed herein relate to systems, methods, and computer program products for a system for monitoring application development standards. The system, method, and computer program product are configured to access application code on a server associated with a network, wherein the application code is installed on the server; scan the application code to identify applications that are integrated into the application code; identify products in the application code based on the scan, wherein the products are identified based on a textual analysis of the application code; compare the products identified in the application code to a list of non-allowed products; identify non-allowed products in the application code based on the comparison of the products to the list; determine an allowed product as an alternative to the non-allowed product; and provide a report to a user comprising the non-allowed product and the alternative allowed product.

Employees or computer users associated with an institution often install applications on computers, servers, or processing devices without first confirming with the system administrator or other IT professional regarding the appropriateness and efficiency of the application. In some situations, this installed software causes issues with the functioning of the computer, with other applications installed on the computer, or with the network itself. In other situations, installation of an application on a computer raises licensing issues with the provider of the application. In these situations, it may be best practices to uninstall the application from the server. Nevertheless, the employees often desire the functionality provided by the application and would like if an acceptable substitute could be implemented to replace the removed application.
While systems administrators attempt to monitor installation of programs on servers associated with the system, in large systems this is extremely difficult to do because of the number of users and/or systems. The system administrator may not know what software is installed or even what is not allowed. Even if the system administrator knows what is not allowed, the system administrator may not know an acceptable substitute for the software that is removed.
Thus, there is a need for a system and method that can assist users in monitoring and remediating application development standards to remove non-allowed applications and recommend acceptable alternatives.

Process for reporting and remediating application development standards


In a magnetic recording and/or reproducing apparatus applied to an external storage of computers, a recorded file can be searched easily. A recording track is helically formed on a magnetic tape to record file data, and management data are recorded at the beginning of the magnetic tape, and a search pattern is recorded on the recording track along the longitudinal direction at a location of the magnetic tape that corresponds to the management data of the beginning of the magnetic tape.

Heretofore, a previously proposed magnetic recording and/or reproducing apparatus has employed the ID-1 format data recorder (ANSI x34.175-1990 19 mm Type (D-1 Recorded Instrumentation), in which helical recording tracks are sequentially formed on a magnetic tape to record and reproduce desired data with high density.
FIG. 11 illustrates a magnetic tape 1 that includes a plurality of tracks recorded by the ID-1 format data recorder. Magnetic tape 1 is wrapped around a rotary drum and rotated at a predetermined speed. The magnetic tape 1 is run at a predetermined speed, so that recording tracks TRs (TR1, TR2, TR3, TR4, TR1, TR2, . . . ) are helically and sequentially formed by a magnetic head mounted on the rotary drum. In this manner, desired data are recorded onto recording track TR1.
Also at this time, the data recorder forms recording tracks TA, CTL, and TC, which extend along the longitudinal direction of magnetic tape 1. Recording track TA is located at the upper portion of magnetic tape 1, and recording tracks CTL and TC are located at the lower portion of magnetic tape 1. The data recorder records the track set ID of the recording track TR in the recording track CTL.
The track set ID contains absolute position information, and it is recorded from the beginning of the magnetic tape 1, at locations that are in between the predetermined synchronizing signals that correspond to each set of 4 recording tracks (TR1 . . . TR4).
The recording tracks TA, CTL, and TC contain user management data which permits high density data recorded on magnetic tape 1 to be searched easily.
In the data recorder, when information is recorded on the recording track TR, the recorded information includes a parity code of a product code. The parity code is used for error detection and correction, thereby enhancing the reliability of data recorded on and reproduced from magnetic tape 1.
That is, as shown in FIG. 12, after the data recorder takes in a predetermined unit of data (comprising 36,108 bytes and hereinafter designated as data field DATA), it divides the data field DATA into 306 blocks, and adds to each block a Reed-Solomon error detecting and correcting code.
Furthermore, the data recorder divides each block into a first and second field, FIELD0 and FIELD1, and then adds a Reed-Solomon error detecting and correcting code (designated as C1) so as to orthogonalize with the C2 code in each of the fields FIELD0 and FIELD1.
Thereby, in the data recorder, the reproduced data are error-corrected by using the C1 and C2 codes, thereby improving the bit error rate.
Further, when the data field DATA, including the C1 and C2 codes, is recorded onto the magnetic tape 1, the data recorder interleaves the data field DATA in recording track TR. Thereby, the data field DATA can be reproduced reliably, even in the presence of a drop-out.
In other words, in the data recorder, assuming that the data field DATA has been supplied as a sequence designated by arrows a1, a2, . . . , an-1, an, an+1, an+2, . . . ax-1, and ax, the data field DATA is recorded in a different sequence as shown by arrows b1, b2, . . . bn-1, bn, in order to interleave the above data field DATA.
Furthermore, the data recorder adds to each data field DATA a synchronizing signal SYNC and a sync block data ID (hereinafter referred to as "sync block"). During the recording of the data field DATA, the data recorder also adds a preamble and a postamble to the data field DATA.
During reproduction of magnetic tape 1, the synchronizing signal SYNC, the sync block data ID, and the data DATA are reproduced with reference to track sync data included in the preamble, which allows the magnetic recording and/or reproducing apparatus to deinterleave the data field DATA with reference to the above synchronizing signal SYNC and the sync block data ID.
If a drop-out occurs in magnetic tape 1, this deinterleave-processing prevents errors that exceed the error-correcting capability of the C1 and C2 codes from concentrating on one part of the reproduced data.
By reproducing, in this manner, data arranged in the ID-1 format, a bit error rate of about 10.sup.-10 can be achieved, which is satisfactory for practical use as a data recording and/or reproducing apparatus mainly for measurement.
If this bit error rate can be improved to about 10.sup.-15, then the magnetic recording and/or reproducing apparatus can store the data of computer systems used at banks, etc., for example, thus expanding the utility of this type of data recorder.
Further, since this type of data recorder can record high-density data, an improvement of the bit error rate will facilitate the management of the magnetic tape by collectively recording a plurality of files onto a magnetic tape.
However, the drawback to the collective recording of a plurality of files in this manner is that the search for particular files become difficult.
One possible solution is to retrieve data by performing a high-speed search on the high-density tape. However, since the magnetic head helically crosses respective recording tracks, the desired data cannot be reliably reproduced when high-speed searching is used. Thus, this method of retrieving data is insufficient for the previously proposed data recorder.

Magnetic recording and/or reproducing apparatus having a search pattern and data arranged in a longitudinal track for facilitating a high speed search


A process or forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.

1. Field of the Invention
The present invention relates to a process for forming an integrated circuit comprising non-volatile memory cells and peripheral transistors of at least two different types.
Specifically, the present invention relates to a process providing for the implementation in a monocrystalline silicon substrate of at least one matrix of memory cells. In each memory cell a floating gate and a control gate, both electroconductive, are mutually electrically insulated by means of an intermediate dielectric multilayer. There is also provided simultaneous formation, in zones peripheral to the matrix, of at least first and second MOS transistor types.
The present invention also relates to an integrated circuit of the above mentioned type comprising non-volatile memory cells having an intermediate dielectric multilayer and at least two types of peripheral transistors.
2. Discussion of the Related Art
As is known in the field of electronic semiconductor technology, in order to reduce the area of integrated circuits there is a tendency towards ever greater integration scales with a reduction of component sizes. This has led to improvement of the quality of the materials used and to optimization of the processes for their formation.
The present invention relates to the field of the development of the techniques of formation of dielectric materials in a single integrated circuit, and in the formation of layers of different thickness and composition which perform different functions. On one hand the dielectric materials act as insulators providing electrical insulation of conductive layers and creating a barrier against contaminating substances coming from the outside environment, while on the other hand the dielectric materials act as active dielectrics allowing the passage of charges between layers of conductive materials.
In order to improve the quality and functionality of the above mentioned dielectrics it has been proposed in relatively recent times to provide multiple superimposed layers, in particular using layers of silicon oxides and/or silicon nitrides.
In the specific field of application of the present invention there are provided integrated memory circuits including, in addition to a plurality of memory cells arranged in one or more matrixes, external or peripheral circuits in which components are structurally similar to the cells and are provided by the same technology. Specific reference is made to MOS transistors.
Non-volatile memories, to which specific reference is made in the present invention, comprise different classes of devices or products which differ from each other by the structure of the individual memory cell and the type of application. Specifically reference is made to read-only memories which can be electrically programmed and erased (Erasable Programmable Read Only Memories) and specifically EPROM, EEPROM or FLASH. These types of memories can be distinguished from one another as some of them are both erasable and electrically programmable, while others require, e.g., ultraviolet light to be erased. For data storage, memory cells comprise in all cases a floating-gate MOS transistor integrated on a substrate usually of monocrystalline silicon. The amount of charge contained in the floating gate determines the logical state of the cell. Non-volatile memory cells are programmed in a discrete number of logical states allowing memorization of one or more bits per cell. In standard cells, for example, programming is provided in two logical states, written and erased, with memorization of one bit per cell.
The floating gate of electroconductive material, normally polysilicon, i.e. polycrystalline silicon or "poly", is completely surrounded by insulating material. In particular, over the floating gate a dielectric layer, so-called intermediate dielectric or interpoly, insulates the floating gate from an overlying control gate also of electroconductive material. The control gate can consist alternatively of a single polysilicon layer or of a double polysilicon-silicide layer and is coupled electrically to a programming terminal.
As known to those skilled in the art, the interpoly dielectric is particularly critical in terms of charge retention. Development of the technology has revealed as particularly advantageous the use of a multilayer intermediate dielectric. This preserves the insulating characteristics of the intermediate layer while avoiding the problem of loss of charge from the floating gate to the control gate, whether over the long term or when a high programming potential is applied to the control gate. In particular, as known to those skilled in the art, this class of intermediate dielectrics comprises a triple layer of silicon oxide, silicon nitride and silicon oxide, the so-called ONO. As described e.g. in U.S. Pat. No. 5,104,819, after formation of an underlying silicon oxide layer and deposition of silicon nitride, an upper silicon oxide layer is formed by deposition instead of by the conventional oxidation of the underlying nitride. This type of dielectric achieved has good charge retention capability and increased capacitive coupling between floating gate and control gate.
Regarding the so-called external or peripheral transistors, they are incorporated in circuits outside the memory cell matrix, e.g., logical, or matrix control circuits. Specifically in the framework of the present invention, reference is made, as indicated above, to MOS transistors.
MOS transistors include an active dielectric, the so-called gate dielectric, placed between the substrate and a gate of electroconductive material, normally polysilicon. The thickness of this dielectric determines the type of transistor formed, in terms of electrical properties. In the same circuit is sometimes integrated two types of transistors of the external circuitry having gate dielectrics of different thicknesses. Usually the active dielectric consists of a silicon oxide layer formed at a high temperature by oxidation of the substrate.
To minimize the number of production process steps of the entire integrated circuit it is known to make the memory cells and peripheral transistors simultaneously, as mentioned above. Specifically, the present invention falls within a class of processes in which the polysilicon layer making up the gate of the peripheral transistors corresponds to the formation process step in which the control gate polysilicon layer of the memory cells is formed. In these processes the intermediate dielectric of the memory cells and the gate dielectric of the transistors of the circuitry are also formed simultaneously.
A known process, in which it is necessary to form two types of peripheral transistors with differentiated gate oxide thickness, comprises essentially the following steps:
formation of a first polysilicon layer of the floating gate and of the intermediate dielectric, after formation of a gate silicon oxide layer of the cells; PA1 removal of the above mentioned layers from the zones in which the transistors of the circuitry are formed; PA1 formation, by means of high-temperature substrate oxidation, of a silicon oxide layer in the areas in which the peripheral transistors are to be formed; PA1 removal of the silicon oxide layer from the areas of the second transistor type; PA1 formation, again by substrate oxidation, of another silicon oxide layer in the areas of both types of transistor; and PA1 formation of a second polysilicon layer of the control gate of the cells which also constitutes the gate of the peripheral transistors. PA1 removal from the zones peripheral to the matrix of the above mentioned layers; PA1 formation of a first silicon oxide layer over the substrate in the areas of both types of transistors; PA1 removal of the first silicon oxide layer from the areas assigned only to the transistors of the second type; PA1 deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and PA1 formation of a second silicon oxide layer in the areas of both types of peripheral transistors.
Recently, in the framework of the research for new types of dielectrics using MOS transistors, there was proposed use of a gate dielectric comprising, in addition to a silicon oxide layer achieved by high-temperature thermal oxidation, an overlying layer also of silicon oxide but achieved by deposition. The benefits of such a composite dielectric are described for example in an article entitled "Thin CVD stacked gate dielectric for ULSI technology" by HsingHuang Tseng et al, IEDM Technical Digest, page 321-324, 1993.
In patent U.S. Pat. No. 5,104,819 mentioned above there is disclosed formation of a memory cell matrix having ONO type interpoly dielectric and peripheral transistors with gate dielectric including another deposited silicon oxide layer. The deposited silicon oxide layer of the intermediate dielectric multilayer of the cells also constitutes the gate dielectric upper layer of the peripheral transistors and is formed successively over a first gate thermal silicon oxide layer.
This manufacturing process however only permits formation of a single type of peripheral transistor. In addition the silicon oxide deposited to complete the gate dielectric is not good quality if its deposition is not followed by a so-called thermodynamic annealing process, as indicated to be necessary in the above mentioned article.
The object the present invention is to conceive a process for the formation of non-volatile memory cells and peripheral transistors permitting achievement of a gate dielectric and an intermediate dielectric of good quality, in order to achieve an integrated circuit having characteristics of great reliability and functionality.
Another object is to provide this circuit while minimizing the number of process steps and thus the production costs.
Another object is to provide a process which is particularly flexible and usable, for example, in the simultaneous formation of peripheral transistors having different gate dielectrics.

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC


A tin-silver electrolyte and methods of depositing tin-silver alloys on a substrate.

The present invention is directed to a tin-silver electrolyte. More specifically the present invention is directed to a tin-silver electrolyte that enhances tin-silver alloy deposition on a substrate.
Tin-silver alloy deposition processes have been used in a number of applications requiring attachment of electronic components to printed circuit boards by soldering or reflowing. During assembly, sufficient heat is applied to melt tin-silver alloy deposits and upon cooling, a metallurgical bond between the component and circuit board is formed. Eutectic tin-silver contains 96.5% tin and 3.5% silver, and becomes liquidus at a temperature of 221° C. A number of references disclose electrolytes for depositing silver-tin alloys, including U.S. Pat. No. 5,514,261 and DE patent application 4,330,068.
The electrodeposition of tin-rich alloys of tin-silver is difficult given the large difference in reduction potential between the two metals. Furthermore, the preferential reduction of tin is made more difficult by the fact that silver exists in solution as a monovalent ion, whereas tin is either divalent or tetravalent, and thereby requires two or four times the amount of current for reduction to occur, relative to silver. In addition, an appreciable amount of silver is included in solution to allow for the practical operation of the electrolyte on a production scale. Accordingly, there remains a need in the art for electrolytes that enhance the deposition of tin-silver alloys on a substrate.


The present invention provides methods and compositions for drug screens to identify and characterize agents that are agonistic or antagonistic to activation of the promoter region of the NAG-1 gene. Activation of the NAG-1 gene is associated with the apoptotic elimination of cancer cells both in vitro and in vivo. The invention also provides novel promoter region sequences of the NAG-1 gene.

Nonsteroidal anti-inflammatory drugs (NSAIDs) are widely used in the treatment of inflammatory disease. Their anti-inflammatory effects are believed to result from their ability to inhibit the formation of prostaglandins by prostaglandin H synthase (COX). Two isoforms of prostaglandin H synthase, COX-1 and COX-2 have been identified. COX-1 is constitutively expressed in many tissues, while the expression of COX-2 is regulated by mitogens, tumor promoters, and growth factors. High expression of COX-2 has been reported in human colorectal tumors and tumors from other tissues, suggesting a role for this enzyme in regulating tumor growth. NSAIDs are effective in reducing human and rodent colorectal, and possibly, breast and lung cancer. In addition, retrospective and prospective studies link NSAID usage to a reduced risk for colorectal cancer death. NSAIDs are effective in reducing the number and size of polyps in animal models, and epidemiological studies indicate that use of NSAIDs provide a 40–50% reduction in mortality from colorectal cancer.
Our understanding of the mechanisms by which NSAIDs exert their anti-tumor effect is not clear. One possible mechanism is altered arachidonic acid (AA) metabolism, since NSAIDs inhibit the formation of prostaglandins by COX-1 and COX-2. Recent data suggest that inhibition of COX by NSAIDs may increase the cellular pool of AA, resulting in the hydrolysis of sphingomyelin to ceramide, which promotes apoptosis. Some data link NSAID chemoprevention in colorectal cancer cells to prevention of angiogenesis and induction of apoptosis. COX appears to regulate angiogenesis induced by colon cancer cells and NSAIDs appear to limit tumor growth. In epithelial cells of the intestinal crypt, elevated COX-2 expression appears to attenuate apoptosis. Some evidence links NSAID-induced apoptosis to inhibition of COX, but other data suggest a prostaglandin-independent mechanism for the induction of apoptosis. PPARγ agonists also have anti-tumorigenic activity and stimulate apoptosis. For example, ligand activation of PPARγ inhibits proliferation of breast cancer cells, and the addition of PPARγ ligands to cancer cells induces apoptosis. PPARγ agonists also inhibit the growth of transplantable tumors in a nude mouse model.
As is evident from the foregoing, NSAIDs, and the pathways they activate, have great potential for use in the war against cancer. However, as is also evident from the above, insufficient information has been available regarding the NSAID-induced or associated anti-cancer pathways, to help identify agents that are potentially advantageous as cancer treatments. What is needed are novel reagents and methods that can be used to screen for compounds that show promise as anti-cancer agents.

Non-steroidal anti-inflammatory drug activated gene with anti-tumorigenic properties

The United States of America as represented by the Department of Health and Human Services


A non-aqueous electrolyte containing propylene carbonate and 1,3-propanesultone as additives can reduce the amount of a gas evolved during storage at a high temperature of a non-aqueous electrolyte secondary cell comprising the electrolyte, a non-aqueous electrolyte containing at least one compound selected from the group consisting of vinylene carbonate, diphenyl disulfide, di-p-tolydisulfide and bis(4-methoxyphenyl)disulfide as comprising the electrolyte, and a non-aqueous electrolyte containing a combination of the above-two types of additives can provide a non-aqueous electrolyte secondary cell exhibiting excellent retention of capacity and storage stability.

In recent years, there has been a rapid advancement in the development of potable and cordless electronic apparatuses. With the development, there has been an increasing demand for small-size, light-weight, thin, and high energy density secondary batteries that serve as the power supply for these apparatuses.
In particular, since non-aqueous electrolyte secondary batteries, such as lithium ion secondary batteries and lithium polymer secondary batteries, have a high voltage and high energy density and can be made thin, the development thereof is on the increase.
For the positive electrodes of non-aqueous electrolyte secondary batteries, various kinds of lithium-containing composite oxides capable of absorbing and desorbing lithium by charging and discharging are generally used as active materials.
On the other hand, for the negative electrodes of non-aqueous electrolyte secondary batteries, there are ones containing metal lithium as an active material; and ones containing a metal compound or a carbon material capable of absorbing and desorbing lithium by charging and discharging. At present, carbon materials are often used for the negative electrodes.
Normally, on the surface of a negative electrode using a carbon material, an SEI (Solid Electrolyte Interface) film is formed by the reaction between an electrolyte and the negative electrode, and the chemical stability of the negative electrode is maintained by this film. However, during storage of the battery at high temperature, the film cracks easily, and there arises the problem that the negative electrode and the non-aqueous solvent in the electrolyte react with each other in the cracked portion and generate a gas.
In a lithium polymer secondary battery, in order to reduce the size, weight and thickness, a bag-shaped outer packaging material made of a laminated sheet comprising resin films and a metal foil sandwiched therebetween is often used in place of a metal case used for a lithium ion secondary battery. In this case, even when a small amount of a gas is generated, there will be problems, such as an increase in the thickness of the battery, leakage of the electrolyte and deterioration of the charge and discharge characteristics, due to an increase in the internal pressure of the battery.
Moreover, there is a problem that a carbon material easily separates from a negative electrode during charging of a battery. It is considered that this is caused by distortion of the carbon material due to a gas generated during an electrochemical reduction of a non-aqueous solvent at the interface between the carbon material in the negative electrode and the non-aqueous electrolyte.
Furthermore, when binders contained in a positive electrode and negative electrode are swollen with an electrolyte during charge/discharge cycle and storage of the battery, there arises the problem that the impedances of the electrodes increase and the battery capacity decreases gradually.

Non-aqueous electrolyte and non-aqueous electrolyte secondary battery

Matsushita Electric Industrial Co., Ltd.


In certain embodiments, the system is configured to remove from or fragment materials in a vessel by inserting a catheter into a vessel, wherein the distal tip of the catheter is placed at the surgical site and a liquid spray is applied to materials to remove or fragment (as defined herein) the materials. In certain embodiments, the system comprises a liquid spray emanating from a fragmentation lumen and across a fragmentation opening.

1. Field
Certain technologies herein disclosed generally relate to medical devices, and more particularly, relate to medical devices for removal of materials such as a thrombus, or blood clot, from a blood vessel.
2. Description of the Related Technology
A thrombus, or a blood clot, is generally the product of blood coagulation typically due to, for example, poor circulation resulting from an extended sedentary activity. In the early stages of thrombus formation, a thrombus generally has a consistency that is soft, and/or spongy. Over time, a thrombus becomes more tough and fibrotic due to a phenomenon known as the clotting cascade wherein fibrotic tissues increasingly begin to grow into the thrombus. Among other things, a thrombus will decrease blood flow through the affected vessel or in some instance cut-off the flow of blood thereby resulting in the death of tissue supplied by the vessel. Additionally, an embolus is created if a thrombus dislodges from a vessel wall and becomes free-floating. In some cases, an embolus can cause an embolism, or an occlusion of a blood vessel, resulting in, for example, stroke, heart attack or pulmonary embolism.

Methods and apparatus for thrombectomy system