A multiport switch circuit which performs transfer according to flow control and a protocol with an ordering rule specified, wherein the circuit for avoiding packets from clogging is realized in a small size. A packet receiving side circuit has a packet selection output circuit to suppress a circuit size by decreasing the number of transfer data paths, and the packet selection output circuit performs output of selected packets according to a priority packet type selection instruction signal in addition to output of a receiving order packet according to a receiving order output instruction signal to make it possible to avoid clogging caused because the packets made to wait for transmission by the flow control cannot be overtaken by another packet type according to the ordering rule.

The present invention relates to a switching device or a transfer processing apparatus for performing the flow control of multiple packet types and each of the packet types and the transfer of the packets according to a common protocol specifying ordering rules among the packet types, and more particularly to a switch circuit comprising three or more ports.
PCI Express is a name of a bus which is standardized as a succeeding standard of the PCI so as to be a standard expansion bus available for the computers in general and particularly a data transfer bus which is characterized by high-speed data transfer and serial transfer which enable full-duplex transmission at 2.5 Gbps or more in one direction.
The PCI Express covers mainly three types of packets such as Posted, NonPosted and Completion. The Posted is mainly used to reply to a write request, the NonPosted is mainly used to reply to a read request, and the Completion is used to reply to a read request.
To transfer packets, a transmitter RAM and a receiver RAM are used. To transmit the packets from the transmitter RAM to a communication path, flow control is performed to recognize the available state of the receiver RAM on a part of the transmitting side and to control the packet transmission timing in order to prevent the receiver RAM of a destination device from overflowing. The receiving side notifies the remainder capacity of the receiver RAM to the transmitting side when the packet is read from the transmitter RAM or on a timely basis. The transmitting side compares the remainder capacity of the receiver RAM notified from the receiving side with a transmission-scheduled packet size, and if the remainder capacity of the receiver RAM is smaller than the transmission-scheduled packets, the packet transfer is waited until the receiver RAM has an available space. By controlling as described above, the receiver RAM is prevented from overflowing.
In a case where the flow control is performed for each packet type, the ordering rules specify whether or not a packet type, which is held in a waiting state by the flow control, can be overtaken by the following packet type. Typical examples include "Posted must overtake another NonPosted" and "NonPosted should not overtake Posted." They are used in order to prevent a deadlock or to keep consistency of data.
For example, it may be assumed that a write is performed from the CPU to the memory, a read is performed from the CPU to the memory, and comparison is performed between the write data previously performed and the read data returned from the memory. If a write request Posted from the CPU is overtaken by a read request Non-Posted, the comparison cannot be performed properly. To prevent such a situation, the ordering rules are specified between the packets.
In a switch circuit comprising three or more ports for performing the transfer of packets according to the PCI Express protocol, a packet type which is in a transfer waiting state according to the flow control might not be overtaken by another packet type according to the ordering rules. Therefore, another packet type, which is not directly subjected to a transfer waiting state by the flow control, also falls in a transfer waiting state.
Where the transfer waiting state is caused by the flow control, the flow control to one packet type having a particular device as a destination has an effect on another packet having the same device as a destination and also on a packet having another device as a destination. Thus, the switch circuit as a whole is clogged because of the packets which are made to be in a transfer waiting state by the flow control.
As a method of preventing the clogging of the switch circuit as a whole due to the above-described packet transfer waiting state, there is a method that when the packets received through individual ports are transferred to another port, the packets are temporarily stored in an intermediate RAM. For example, JP-A-07-264242 has proposed a method that a low-speed large-scale RAM and a high-speed small-scale RAM are adopted as the intermediate RAMs to improve packet transfer efficiency. As another method, provision of a transfer data path in the switch circuit for each packet type allows to transfer without an influence of another packet type.
JP-A-2001-320385 has proposed a method that the packets received by a receiver unit according to the PCI standard are stored in a RAM according to each priority determined for each packet type, a transmission request is sent to the transmitter unit, the replay of a transmission permission signal from the transmitter unit is checked, and the packets are transferred. Use of this method enables to transfer a high priority packet type with a transmission request cancelled if the transmission permission signal to a low priority packet type is not replied.
JP-A-2003-18188 has proposed a method that packets are divided depending on packet types and stored in RAMs, and the priority sequences of the individual RAM outputs are changed by a logical flow control mechanism, so that when a high priority packet is made to wait for transfer, the transfer of a packet having the same destination as that of the packet in a transfer waiting state and a packet addressed to another device is free from any influence.
But, when the switch circuit has therein the intermediate RAM as shown in FIG. 9 of the above-described related art, e.g., JP-A-07-264242, the clogging of the switch circuit due to the flow control and the ordering rule can be prevented, but there is a problem that the transfer speed of the switch circuit becomes slow at all times because of routing through the intermediate RAM even if there is no occurrence of the transfer waiting by the flow control in comparison with a case not being routed via the intermediate RAM.
Where a transfer data path within the switch circuit shown in FIG. 10 is provided for each packet type, the packets can be transferred without being influenced by the transfer waiting state of another packet type but there is a possibility that the order of the packets transferred to the transmitter RAM of the switch circuit is different from the order of reaching the receiver RAM of the switch circuit. Therefore, it is necessary to manage the arrival sequence of the receiving packets on a part of the transmitter RAM, and an additional control circuit is required.
In either case, the logical scale of the switch circuit becomes large, and the number of ports mountable in a unit area becomes small. Reduction of the logical scale of the switch circuit which tends to have a multiport is an important proposition, and measures are demanded to be taken with the logical scale suppressed.


Hepatocyte growth factor stimulates proliferation and differentiation of hematopoietic cells, most preferably burst-forming unit-erythroid cells. The hepatocyte growth factor may be obtained from cells transformed with human gene sequences coding therefor. Pharmaceutical compositions useful to induce the proliferation and differentiation of hematopoietic cells may contain hepatocyte growth factor as an active principle in admixture with a suitable carrier. The pharmaceutical compositions may additionally contain stem cell factor as an active principle.

Hepatocyte Growth Factor (HGF, the same abbreviation having also been used to define a completely different substance, i.e. hemopoiesis Growth factor) described by Nakamura et al., 1989, and by Hiyazawa et al., 1989), also known as Scatter Factor (Naldini et al., 1991a; Weidner et al., 1991), has the unique feature of combining mitogenic and motogenic activities on its target cells. HGF is mitogenic for hepatocytes (Michalopoulos, 1990) and other epithelial cells, such as kidney tubular epithelium, melanocytes and keratinocytes (Kan et al., 1991; Rubin et al., 1991; Halaban et al., 1992; Matsumoto et al., 1991). In these cells, HGF also promotes "scattering" (Stoker et al., 1987; Gherardi et al., 1989; Weidner et al., 1990, 1991; Naldini et al., 1991a) and matrix invasion (Weidner et al., 1990; Naldini et al., 1991a), and has chemotactic properties (Morimoto et al., 1991; Giordano et al., 1993). The factor stimulates extracellular matrix (ECM) degradation, by enhancing the synthesis of enzymes involved in ECM proteolysis (Pepper et al., 1992; Boccaccio et al., 1994). HGF acts as a morphogen in neuro-ectodermal development in vivo (Stern et al., 1990), and induces three-dimensional organization of epithelial cells in vitro (Montesano et al., 1991). The factor also promotes the progression of carcinoma cells toward malignant invasive phenotypes (Weidner et al., 1990).
The receptor for HGF is the tyrosine kinase encoded by the MET proto-oncogene (Naldini et al., 1991a, 1991b; Bottaro et al., 1991), a 190 kDa heterodimer of an extracellular 50 kDa .alpha. subunit, disulfide-linked to a transmembrane 145 kDa .beta. subunit (Park et al., 1987; Giordano et al., 1989a) Both subunits derive from glycosylation and proteolytic cleavage of a 170 kDa single chain precursor (Giordano et al., 1989b).
The HGF receptor is expressed in adult epithelial tissues, including liver, intestine and kidney (Prat et al., 1991a; Di Renzo et al., 1991). It has been reported to be expressed in early stages of development of epithelial organs (Sonnenberg et al., 1993), and it is often overexpressed in epithelial cancer (Prat et al., 1991a; Di Renzo et al., 1991). We have shown that the receptor is also expressed in endothelial cells and that HGF is a potent angiogenic factor both in vitro and in vivo (Bussolino et al., 1992; Grant et al., 1993). The HGF receptor is also known to be expressed in some populations of blood cells, such as macrophages, but the meaning of such an expression, which is barely detectable in the absence of activation, has not been elucidated (Galini et al., 1993).
EP-A-0,492,614 discloses the use of HGF as a growth enhancer for epitheliocytes, whereas WO 93/08821 discloses the use of HGF for the prevention of the side-effects of chemotherapeuticals.
Now it has been found that the hepatocytes growth factor induces proliferation and differentiation of multipotent and erythroid hematopoietic progenitors.
Hematopoietic cell growth and differentiation is under the control of a complex network of cytokines, which act on their target cells via specific receptors (Metcalf, 1984; Clark and Kamen, 1987). Erythropoiesis is a complex process in which a specific genetic program is primed (commitment) and executed (maturation). Although much is known about maturation, most of the molecular events occurring during the commitment phase are still obscure. Growth and differentiation of erythroid precursor are regulated by humoral factors and by largely uncharacterized cell-cell interactions with bone marrow stroma, the so-called hematopoietic microenvironment. Erythropoietin has long been considered the major factor required for erythropoiesis (Koury and Bondurant, 1990), other factors being far less specific (IL-3, GM-CSF, TGF-.beta.; Gasson, 1991; Miyajima et al., 1993; Sporn and Roberts, 1992). HGF represents a novel example of a humoral factor specifically active on erythropoiesis.
Recently, the synergism between HGF, IL-3 and GF, IL-3 and GM-CSF in promoting the growth of uncharacterized colonies from unfractionated murine bone marrow (Kmiecik et al., 1992) has been described. From said work, however, no conclusions about the effect of HGF alone could be deduced; moreover, the results obtained using bone marrow cell suspensions (including lymphocytes and monocytes-macrophages) could be ascribed to an indirect effect, mediated by the production of hematopoietic cytokines by accessory cells.
The synergism between HGF, IL-3 and GM-CSF, in fact, has not been confirmed by the authors of the present invention on isolated colonies of human hematopoietic cells.

Hepatocyte growth factor--induced proliferation and differentiation of erythroid cells


In an operation method of a multi-flow passage device, and a multi-flow passage of the present invention, blockage detection of a reaction flow passage can be readily performed and cleaning of the reaction passage can be easily performed.

1. Field of the Invention
The present invention relates to an operation method of a multi-flow passage device, and a multi-flow passage device.
2. Description of the Related Art
Conventionally, as a method for manufacturing a desired reaction product by contacting fluid reactants (raw material fluids) and mixing them, a method with the use of a multi-flow passage device referred to as a so-called micro-channel reactor is known.
The micro-channel reactor includes a substrate formed with fine grooves on the surface, and the fine grooves formed on the surface of the substrate act as a reaction flow passage for mixing raw material fluids. In the multi-flow passage device, by passing raw material fluids to be reacted through the reaction flow passage, area of contact between the raw material fluids to be reacted per unit volume is dramatically increased, which results in enhancement of mixing efficiency of the raw material fluids. The micro-channel reactor is used for such an application as manufacturing of chemical compounds or medicines.
For example, Japanese Patent Laid-Open No. 2008-168173 discloses an example of a micro-channel reactor among multi-flow passage devices. The micro-channel reactor includes a first introduction passage for allowing a first reactant (a first raw material fluid) necessary for the reaction to flow in the reactor; and a second introduction passage that joins at the halfway point in the flow direction of the first introduction passage and allows a second reactant (a second raw material fluid) to flow. Then, the first reactant flowing through the first introduction passage and the second reactant flowing through the second introduction passage are brought into a chemical reaction in a confluent passage of the both passages, and the generated reaction product is carried to outside of a reaction flow passage via the first introduction passage.
Meanwhile, the multi-flow passage device having such a structure as the micro-channel reactor may be used as a heat exchanger for heating and cooling a target fluid.
When the first raw material fluid and the second raw material fluid are introduced into the reaction flow passage of the micro-channel reactor as shown in Japanese Patent Laid-Open No. 2008-168173, there is fear that the reaction flow passage may be blocked because it is formed by very fine grooves. Therefore, in the actual circumstances, for example, prior to introducing the first reactant or the second reactant into the reaction flow passage, existence of blockage of the reaction flow passage must be confirmed by purposely passing a fluid for inspection therethrough. If the reaction flow passage is blocked, the substrate constituting the reaction flow passage must be disassembled for cleaning the entire reaction flow passage. That is, in the micro-channel reactor of Japanese Patent Laid-Open No. 2008-168173, the measures for detecting blockage (referred to as blockage detection) and cleaning are not taken in the reaction flow passage, so that blockage detection and cleaning of the reaction flow passage were quite difficult.
The present invention is an invention achieved in consideration of the above problem, and has an object to provide an operation method of a multi-flow passage device, and a multi-flow passage device that are capable of readily performing blockage detection of a reaction flow passage and also capable of easily performing cleaning of the reaction flow passage.

Operation method of multi-flow passage device, and multi-flow passage device

Abstract: The operation method of the multi-flow passage device of the present invention is an operation method of a multi-flow passage device 1 formed with a reaction flow passage 20 for producing a reaction product S by allowing raw material fluids Q, R to flow and making chemical reaction, the method including steps of: partitioning the reaction flow passage 20 into a plurality of sections; and allowing the raw material fluids Q, R to flow in the reaction flow passage 20 and measuring pressure of the raw material fluids Q, R or the reaction product S flowing through the respective sections to determine blockage of the sections based on the pressure loss of the respective sections.


A protective coating is made by polymerizing at ambient temperatures a silicon-oxygen bond compound selected from a group consisting of oxysilanes having side groups selected from the group consisting hydrogen and alkyl, aryl, hydroxyalkyl, alkoxyalkyl and hydroxyalkoxyalkyl groups containing up to six carbon atoms, where there are at least two hydrolyzable side groups for polymerization, and where the number of repeating units of the oxysilane is in the range of from 1 to 5, and/or silicone intermediates with side groups selected from the group consisting of hydrogen, the hydroxy group and alkyl, aryl and alkoxy groups having up to twelve carbon atoms and having an average molecular weight of up to 5000. The polymerization is catalyzed by a basic compound selected from a group consisting of mercaptans, silane substituted amines, polyamides, polyimides, amidoamines, and aliphatic amine compounds and aromatic amine compounds; and an organotin compound. Carbinols with at least two carbon bonded hydroxy groups per carbinol may also be included in the coating composition.

Protective coatings are needed to protect a variety of substrates from premature deterioration and failure due to the particular environment in which they are used. Such substrates include concrete, steel and other industrial building or structural materials that are typically used in environments well known for their corrosive, chemical, mechanical, thermal and atmospheric degradation. Such applications include steel structures used in industrial chemical processing plants, oil refineries, power plants, offshore drilling platforms and the like. To be effective in such applications, the protective coating should protect against a variety of conditions. It must be a corrosion barrier; must be weatherable, that is, resistant to ultraviolet light and other components of sunlight as well as environmental constituents; must be heat resistant; and must be chemically resistant.
The performance of a protective coating is greatly dependent on the resin system used as the binder for the composition. Coating binders have historically been chosen from the following categories of resins: epoxy, polyurethane, silicone, silicate, acrylic, vinyl, alkyd, chlorinated rubber and the like. Some of these generic classes require a high level of organic solvent to dissolve them and cannot be used in light of today's raised environmental consciousness. Accordingly, the state-of-the-art in high performance coatings is defined primarily by epoxy, polyurethane, silicone and silicate binders.
Each of these resins are known for their individual unique characteristics. For example, an epoxy resin binder provides the properties of enhanced corrosion and chemical resistance. A polyurethane resin binder provides enhanced weatherability and appearance. A silicone resin binder provides enhanced heat resistance and weatherability. Silicate resin binders, when combined with zinc dust, provide long-lived corrosion resistance. However, each resin of this current class of binders is also characterized as having limited performance potentials in certain areas. Epoxy resin binders tend to cure slowly at temperatures below 10.degree. C. and have poor weatherability properties. Polyurethane resin binders are moisture sensitive, derived from toxicologically hazardous polyisocyanates, and known to retain their appearance for only three to seven years. Silicones require baking or high heat curing to achieve full performance and are marginal film formers.
True advancements in the state-of-the-art for protective coatings require substantial improvements in weathering (primarily ultraviolet resistance), heat resistance, chemical resistance, and corrosion control. Polysiloxane chemistry offers the potential for providing many of these advancements. Polysiloxane is defined as a polymer consisting of repeating silicon-oxygen atoms in the backbone that imparts several advantages over previously used carbon-based polymer binders; one of these advantages being an enhanced chemical and thermal resistance due to the silicon-oxygen bond. Polysiloxane's polymer linkage is also transparent to ultraviolet light making it resistant to ultraviolet degradation. Finally, polysiloxane is not combustible and is resistant to a wide range of chemicals and solvents, including acids.
Exemplary of polysiloxane coating compositions is that described by Law et al. in U.S. Pat. No. 4,113,665. Law discloses a process for making chemically resistant coatings by reacting, in an acid medium, trialkoxysilanes and silicone intermediates. The Law invention represented a major advancement in polysiloxane based coatings technology because it provided a means of providing ambient temperature curing of polysiloxane compositions. Unlike conventional silicone compositions, the Law patent provided a process for achieving the full chemical and heat resistance properties of silicone based materials without the need for high temperature curing.
Although the process disclosed in the Law patent provided the improvement of ambient temperature curing, it has certain inherent limitations. The use of an acid catalyzed reaction requires a prehydrolysis step that necessitates a considerable input of energy for an extended period of time, thereby increasing the manufacturing cost of such products. The acid catalyzed production of polysiloxane produced protective coatings poorer than desired, were limited to either semi-gloss or flat finishes. Such an acid catalyzed composition must be marketed as a two-part product. The use of such a two-part product requires that each part be combined immediately before application. Often it is desirable to have a coating composition in a single container for field applications where mixing of two parts may not be reliable.
It is, therefore, highly desirable to provide a high performance protective coating binder composition affording improved protection from corrosion and attack by chemicals, solvents, weathering, and heat where the binder can be manufactured economically and cured at ambient temperature. It is further desired that the binder produces a protective coating having a high-gloss finish with a relatively low viscosity that can be supplied in a one-package system and applied without a large degree of organic solvent thinning.


A router organizes an IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary. The router then iteratively partitions the IC area into progressively smaller tiles while selecting a route for each net passing between tiles when possible without altering any previously routed net. The router thereafter iteratively merges the tiles into progressively larger tiles while selecting a route for each previously unrouted net residing wholly within a single tile, altering routes of previously routed nets when necessary to accommodate the selected route. When selecting each route for any connection of a net, the router seeks to minimize a cost function of congestion factors of all GRC boundaries.

1. Field of the Invention
The invention relates to a method for routing nets within an integrated circuit (IC) layout by iteratively partitioning the layout into progressively smaller tiles, routing each net crossing a tile boundary after each partitioning without altering any previously routed net, then iteratively partitioning the layout into progressively larger tiles, routing each previously unrouted net crossing a tile boundary after each partitioning, altering existing net routes when necessary.
2. Description of Related Art
IC fabricators provide cell libraries describing a set of standard cells that an IC designer can incorporate into an IC design. Each standard cell is an IC component of proven design such as, for example, a transistor, a logic gate, an input/output port, or a more complicated device such as a memory. An IC designer typically develops an IC design in the form of a "netlist", a data file describing the IC as a collection of instances of cells and indicating which terminals of the cells are to be interconnected by signal paths ("nets"). The IC designer employs a computer-aided placement and routing tool employing placement algorithm that processes the netlist to produce a placement plan indicating a position of each cell instance within the IC and a routing algorithm to produce a routing plan indicating a route for each net interconnecting cells instances. Placement and routing is typically an iterative process; if the routing algorithm fails to find a route for each net, the placement algorithm modifies the placement plan and the routing algorithm and again attempts to find a route for each net. An efficient routing algorithm that is more likely to find a route for each net when possible for a given placement plan, and which does so quickly, can greatly reduce the processing time needed for placement and routing.
FIG. 1 illustrates a simple routing algorithm that divides the IC layout area into an array of rectangular tiles 30 (step 10) as shown in FIG. 2A. A router implementing the routing algorithm then processes the netlist to define a set of connections for each net (step 12). A "connection" is a signal path between two cell terminals. For example, a net connecting only two cell terminals consists of a single connection while a net connecting four cell terminals consists of three connections. FIG. 2A shows an unrouted net 31 consisting of two connections 31A and 31B connecting terminals of three cells 32, 33 and 34. After defining all connections (step 12), the router selects one of the unrouted nets (step 14) and a first connection of that net (step 16), and then determines a global route for that connection (step 18). For example FIG. 2B shows that with net 31 selected at step 14 and connection 31A selected at step 16, a global route is selected for connection 31A. A "global route" for a connection is simply a list of the particular tiles through which the net is to pass that does not indicate the exact ("detailed") route of the connection through any individual tile. The router will typically look for a route that minimizes a routing cost function related to the density of connections crossing the individual tile boundaries. The routing cost function is designed so that routing a connection in a way that minimizes the cost function and increases the likelihood that the router will be able to successfully route all nets that have not yet been routed. After selecting the global route for a connection at step 18, the router establishes a detailed route for the connection defining the structures on each layer of the IC within each tile included in the global route (step 20). For example, FIG. 2C shows a detailed route for connection 34.
When there is a next connection of the selected net to be routed (step 22), the router selects the next connection (step 16) and then globally routes the next connection (step 18). FIG. 2D shows a global route for connection 31B of net 31 of FIG. 2A. At step 20, the router then tentatively establishes a detailed route for the connection and then refines the detailed routing to eliminate any redundancy. For example after establishing a tentative detailed route for connection 34B as illustrated in FIG. 2E, the algorithm refines the routing of connections 34A and 34B as shown in FIG. 2F by eliminating redundant routing in three of the tiles so that the follow the same path 34C where possible, thereby reducing congestion within the tiles and at tile boundaries. The router continues to repeat steps 16-20 until all connections of the selected net have been routed. When there is a next net to be routed (step 24) the algorithm selects the next net and repeats steps 14-22 to route all of its connections. The process continues until at step 24 the router has routed all nets.
As the number of nets the algorithm has routed increases, the available routing space decreases, and the algorithm of FIG. 1 becomes less likely to successfully route additional nets. To increase the likelihood of success, a prior art, multi-level "Λ-shaped", routing framework as illustrated in FIG. 3 carries out routing in several stages. The IC's floorspace is initially divided into an array 40A of relatively small tiles and a router separately routes each tile of the array 40A to find a detailed route for each net that resides completely within that tile. Nets crossing boundaries of tiles 42 are ignored and remain unrouted. At a next stage of the process the IC tiling is coarsened so that each set of four tiles 42 of array 40A are merged to create a single larger tile 44 of a tile array 40B. The router repeats the routing algorithm of FIG. 1 for each tile 44 but only the unrouted nets residing wholly within any individual tile 44 are routed; unrouted nets crossing boundaries of tiles 44 are ignored. Thus for each tile 44, connections for the unrouted nets residing wholly within that tile 44 are identified (step 12), and each such connection of each net is globally routed and detailed routed with respect to smaller tiles 42 (steps 14-24). When the algorithm is unable to route a net residing wholly within any given tile 44, it simply notes that it failed to route that net, and continues to route additional nets. At the next stage of the process, IC tiling is again coarsened so that each set of four tiles 44 of array 40B are merged to create a single larger tile 46 of a tile array 40C. In this simple example, the algorithm reaches the coarsest (single tile) stage in only two coarsening steps, but an IC layout may initially be divided into more tiles requiring more coarsening stages to reach the coarsest, single tile stage. The router then repeats the routing algorithm of FIG. 1 for tile 46 to determine a global and then a detailed route for each net crossing a boundary of a tile 44.
At this point, the algorithm will have attempted to route every net and will likely have succeeded in routing most of them. The algorithm then begins a series of uncoarsening stages. During the first uncoarsening stage, the algorithm divides the IC into an array 40D of four tiles 47 and finds a route for local nets within any tile 47, rerouting previously routed nets within that tile when necessary to provide a path for the net being routed. The algorithm then again un-coarsens the tiling to produce a new tile array 40E wherein each tile 47 of array 40D is divided into four smaller tiles 48. The algorithm then finds a route for each unrouted local net residing wholly within any tile 48, rerouting other local nets wholly within the tile as necessary to eliminate excessive congestion at tile boundaries. The routing process ends after the algorithm has reached the finest tiling level and has routed all nets.
The path delay through a net increases with its length, and nets can form signal paths that may be subject to restrictions on path delays. It is therefore helpful to route nets interconnecting widely spaced cells in as direct a manner as possible in order to limit the nets' contributions to signal path. Since the prior art Λ-shaped framework of FIG. 3 first routes shorter nets without considering the routing resource requirements of later routed longer nets, wrong routing choices with respect to short, local nets during the early stages of the process make routing of the more timing critical longer nets more difficult and can complicate and lengthen the refinement process carried out during the later stages of the process.
Prior art "grid-based" routing algorithms that route nets along pre-established grid lines treat all wires as having the same width and required spacing between wires. However grid-based routing algorithms are not suitable for routing modern ICs, where nanometer-scale optical fringing and other effects can influence net width and spacing, particularly since optical proximity correction (OPC) and phase-shift mask (PSM) procedures have been developed to adjust width and spacing of individual wires to correct for these influences. "Gridless" routing systems are preferable because they do not restrict wire routing to pre-established grid lines and can accommodate variations in wire width and spacing.
What is needed is a gridless routing algorithm that gives priority to routing longer signal paths but which, when routing any net, takes into account estimated routing resource requirements of all unrouted nets to minimize the impact on the routing resources that will be required by the later routed nets.

V-shaped multilevel full-chip gridless routing


The present disclosure provides antibodies and antigen-binding fragments capable of binding PAR2. In some embodiments, the anti-PAR2 antibodies or antigen-binding fragments thereof bind PAR2 in a pH-dependent manner. The disclosure further provides methods for making and using the antibodies and antigen-binding fragments.

Chronic pain is a condition that can affect anyone and imposes a burden on patients, health care systems, and economies. Approximately 100 million people in the United States suffer from chronic pain and the total annual incremental cost of health care due to pain, including medical costs and the economic costs of lost time and wages, is estimated to be between $560 and $635 billion dollars (Institute of Medicine of The National Academies, 2011). Yet, in a survey of chronic pain sufferers, more than half felt they had little to no control over their pain (2006 Voices of Chronic Pain Survey, American Pain Foundation). Pain can be caused by a variety of conditions and diseases, from cancer, to diabetes, to arthritis, and can be classified into categories: nociceptive, neuropathic, and mixed type pain. Nociceptive pain is defined by stimulation of nerve fibers (e.g. by thermal, mechanical, or chemical stimuli) while neuropathic pain is pain caused by diverse causes such as nerve damage, diseases, and, importantly, inflammation. Inflammation, the process by which organisms recruit immune cells and release immune factors to the site of an injury or infection, can thus be both a helpful process of damage repair and a cause of pain.
Many treatments for pain inhibit inflammation. Two common classes of anti-inflammatory pain therapeutics are steroidal anti-inflammatory drugs and non-steroidal anti-inflammatory drugs (NSAIDs). Steroidal anti-inflammatory drugs typically suppress prostaglandins and leukotrienes, the products of inflammation. Such drugs are reliable and potent, but carry the risk of severe side effects, including, for example, reduced bone density, weight fluctuations, immune system suppression, and growth/puberty irregularities (Irving, P. M. et al. (2007) Aliment Pharmacol Ther. 26(3):313-329; Goodman et al. J Am Acad Orthop Surg. 2007 August; 15(8):450-60). NSAIDs inhibit cyclooxygenase-1 and/or 2 (COX-1 and/or COX-2), which themselves catalyze the reaction of arachidonic acid into prostaglandins. Chronic pain and inflammation can require prolonged treatment, and prolonged inhibition of COX enzymes can lead to gastrointestinal tract problems, such as gastric bleeding and ulcers. Given the risks associated with such anti-inflammation pain treatments, there is a need for alternative approaches for treating pain.
G-Protein Coupled Receptors (GPCRs) are a family of membrane proteins that share a common structural motif of seven transmembrane domains connecting an N-terminal extracellular domain and a C-terminal intracellular domain (Granier et al, Nat Chem Biol. 2012 August; 8(8): 670-673). GPCRs sense extracellular signals such as photons, hormones, chemokines, etc. and activate intracellular G proteins. Many families of GPCRs exist, such as the Frizzled, Rhodopsin, Secretin, Adhesion, and protease activated receptor (PAR) families (Zhang et al. Nature. 2012 Dec. 20; 492(7429): 387-392; Zhang et al. Mol Cells. 2015 October; 38(10):836-42). While the various GPCR families share overall structural features, they exhibit different functions, bind to different ligands, and are activated by different mechanisms. Activation of the PAR family of GPCRs has been associated with inflammation and nociception (Gieseler et al Cell Commun Signal. 2013; 11: 86).
Four PAR receptors have been identified: PAR1, PAR2, PAR3, and PAR4 (Macfarlane et al. Pharmacol Rev. 2001 June; 53(2):245-82; Gieseler et al Cell Commun Signal. 2013; 11: 86). PAR2 activation has been shown to amplify inflammation and nociception, making its inhibition an attractive target for anti-inflammatory pain therapies. PARs, unlike other GPCRs, are activated by proteolytic cleavage of their extracellular domains, which reveals an N-terminal sequence that acts as a tethered-activating ligand. PAR2, in particular, is cleaved and activated by trypsin and tryptase.
PAR2 expression has been detected in vascularized tissues, airways, osteoblasts, cardiovascular tissue, keratinocytes, exocrine glands, leukocytes, mast cells, intestinal epithelium, kidney, neurons, pancreas, and a variety of smooth muscle types (Macfarlane supra). PAR2 has also been implicated in a variety of diseases or conditions associated with neurogenic inflammation, nociception and transmission of pain. PAR2 may be activated by several host and pathogen-derived serine proteases (e.g., trypsin, mast cell tryptase, tissue kallikreins, or members of the coagulation cascade TF-FVIIa and FVa-FXa).
Monoclonal antibodies have been shown to be useful in a variety of therapeutic applications and many antibody therapeutics are currently on the market (Maggon, Curr Med Chem. 2007; 14(18):1978-87; Brekke and Sandlie, Nat Rev Drug Discov 2: 52-62, 2003). The most common type of antibody in circulation in the blood stream is immunoglobulin G (IgG). The usefulness of an IgG antibody for therapeutic purposes depends on several factors, including the specificity of the antibody for its target, the strength of its binding to the target, as well as how efficiently the antibody can be produced and how quickly the antibody is cleared from the serum (the serum half-life of the antibody). The serum half-lives of antibodies are frequently regulated by FcRn (neonatal Fc receptor), which binds to the Fc domain of immunoglobulin G (IgG). In vivo, IgGs are thought to be taken up non-specifically by fluid-phase pinocytosis (Pyzik et al, J Immunol. 2015 May 15; 194(10):4595-603). Once in the endosome, IgG binds to FcRn, which sorts the IgG into recycling endosomes and back to the cell surface, away from lysosomes and away from degradation. While the recycling rate of IgG has been estimated to be 44% of the fractional catabolic rate, antibody therapeutics can still be depleted in a matter of days post-administration (Kim, Jonghan, et al. Clin. Immunol. 122.2 (2007): 146-155).
Pain associated with inflammation is often a chronic condition. Minimizing the dosage and the frequency of administration of a therapeutic molecule is desirable. Thus there is a need for new anti-inflammation pain therapeutics. Standard monoclonal antibodies are attractive candidates, but in some cases can be limited by their serum half-lives. As such, alternative treatments may be desired.

Nucleic acids encoding anti-PAR2 antibodies and uses thereof


A method and apparatus for measuring a parameter of a wet gas flow is provided, wherein the apparatus includes a differential pressure based flow meter configured to determine a first volumetric flow rate of the wet gas flow. Additionally, the apparatus includes a sonar based flow meter configured to determine a second volumetric flow rate of the wet gas flow. Furthermore, the apparatus includes a processing device communicated with at least one of the differential pressure base flow meter and the sonar based flow meter, wherein the processing device is configured to determine the parameter (e.g., wetness, volumetric gas flow rate, and volumetric liquid flow rate) of the wet gas flow using the first and second volumetric flow rates.

A fluid flow process (flow process) includes any process that involves the flow of fluid through pipes, ducts, or other conduits, as well as through fluid control devices such as pumps, valves, orifices, heat exchangers, and the like. Flow processes are found in many different industries such as the oil and gas industry, refining, food and beverage industry, chemical and petrochemical industry, pulp and paper industry, power generation, pharmaceutical industry, and water and wastewater treatment industry. The fluid within the flow process may be a single phase fluid (e.g., gas, liquid or liquid/liquid mixture) and/or a multi-phase mixture (e.g. paper and pulp slurries or other solid/liquid mixtures). The multi-phase mixture may be a two-phase liquid/gas mixture, a solid/gas mixture or a solid/liquid mixture, gas entrained liquid or a three-phase mixture.
In certain flow processes, such as those found in the oil and gas industries, it is desirable to separate the liquid (e.g., oil and/or water) and the gas (e.g., air) components of the fluid. This is typically accomplished using a separator, which is an item of production equipment used to separate liquid components of the fluid stream from gaseous components. The liquid and gas components flow from the separator in separate legs (pipes), with the leg containing the gas component referred to as the "gas leg" and the leg containing the liquid component referred to as the "liquid leg". Each of the legs typically includes a flow meter to determine the volumetric flow rate for each of the gas and the fluid components, respectively, wherein the volumetric flow rate for the gas leg is commonly measured using an orifice plate.
As is well known in oil and gas production, the carry-over of liquid into the gas leg of the gas/liquid separator commonly occurs, wherein the liquid typically takes the form of a mist comprised of small liquid droplets, commonly know as wet gas. This is undesirable because the liquid carry-over can result in a host of undesirable events depending in large part on the degree of carry-over that takes place. As such, in order to minimize the amount of liquid carry-over most separators have mist catchers designed to recover the liquid carried over. Unfortunately however, accurate measurements of the amount of liquid carry-over have not been obtainable because there currently exist no devices and/or methods for accurately determining the amount of liquid carried over into the gas leg. As such, there is a need for an apparatus and method to accurately measure the amount of liquid carry-over.

Wet gas metering using a differential pressure based flow meter with a sonar based flow meter


An oil-fill pressure transducer including a flexible member configured to protect an isolation diaphragm and sensing element. The pressure transducer includes a sensing element mounted to the header, an isolation diaphragm mounted on the front side of the header, and adjacent to the sensing element such that an oil-fill cavity is defined between the sensing element and the isolation diaphragm. The flexible member is disposed adjacent to the isolation diaphragm and a retention member is disposed adjacent to the flexible member. A cavity in communication with the retention member is configured to transmit pressure media to the isolation diaphragm via the flexible member. The flexible member can include thru-holes. The flexible member may compress under an applied positive pressure change. The flexible member may temporarily separate from at least a portion of the isolation diaphragm under an applied negative pressure change.

Pressure transducers are often utilized in gas turbine engines and other systems to measure the pressure of the media such as fluids, gasses, etc. In certain pressure measurement applications, it may be desirable to measure the pressure level of the media while avoiding or minimizing the damage of the transducer due to pressure ripples and/or fluctuations. Pumping equipment, for example, can cause pressure ripples in the measurement media that can adversely impact the measurement accuracy and/or lifespan of the pressure transducer.
An oil-filled capsule surrounding the pressure sensing element can protect the sensor from debris and enable the transducer to be used with almost any pressure media. However, when there are rapid pressure pulsations on the order of 1000's of psi per millisecond, especially in liquid media, such pressure changes can cause unwanted effects such as cavitation and suction near the oil fill isolation diaphragm. Since the diaphragm is typically very thin, such phenomena can cause the isolation diaphragm to rip or rupture and fail.
An internal cavity and/or other mechanical properties of the pressure transducer can result in a structure with a resonant frequency. Subjecting the pressure transducer to pressure ripples having frequencies that match the transducer's structural resonances can damage or reduce the lifespan of the pressure transducer. In these cases, a filter assembly may be placed at the inlet end of the transducer to eliminate the higher frequency ripples and leave static and quasi-static pressures intact. As discussed in U.S. Pat. Nos. 7,975,552, 9,500,533, 9,709,450, and 9,752,948, each assigned to Kulite Semiconductor Products, Inc. and incorporated herein by reference as presented in full, various filters have been designed for coupling with a pressure transducer to reduce resonances near the frequency of the pressure ripple.
U.S. Pat. No. 10,330,553, also assigned to Kulite Semiconductor Products, Inc. and incorporated herein by reference as presented in full, discloses mechanical filtering, for example, that can attenuate certain pressure oscillation frequencies, and block particulates. Such filtering techniques work well for certain applications and pressure media, but they can also cause an increase in the size of the transducer size, increase the likelihood of clogging, and can change the transducer frequency response.
Since pressure ripple frequencies can change from system to system, pressure transducers that are specifically designed for each unique system can be costly, impractical, and can lack the flexibility needed for a wide range of applications. Thus, there is a need for a pressure transducer assembly that can be utilized with multiple systems and applications to protect against rapid pressure pulsations.

Oil fill transducer with rubber disc for dynamic protection


A system for collecting, storing, and/or analyzing data received from one or more inputs comprising a property information database, a profile preference database, and one or more modules for accessing the databases. The system may receive data from a multiple listing service, internet source, and/or drone. The system may calculate and store a predicted property value and/or compare the predicted property value to a stored listed property price. A real estate offer and/or orders for an inspection, appraisal, contractor walkthrough, preliminary title report, or loan applications may be generated and/or sent to an entity based, at least in part, on information stored in the property information database and/or the profile preference database.

Real estate brokers spend substantial amounts of time and resources collecting and analyzing information about properties so they can price and market the properties accurately. Much of the property information a real estate broker collects as it prepares to sell a property is uploaded to a multiple listing service (MLS), so that it can be shared with other brokers representing potential buyers. For instance, property information may be uploaded to the California Regional Multiple Listing Service (CRMLS), the Metropolitan Regional Information System (MRIS), and/or other services using Internet Data Exchange (IDX) or the Real Estate Transaction Standard (RETS).
However, real estate is unlike other major asset classes because each piece of property is unique. Furthermore, potential buyers can be equally idiosyncratic, each having their own histories, needs, biases, and intentions for purchasing property. The unusual nature of real estate transactions often leads to notoriously "high-friction" costs, meaning the transaction itself has a multitude of costs and fees associated with it, e.g., brokerage fees and commissions, research costs, time, etc.
It can be difficult for brokers to anticipate what information will satisfy each potential buyer's needs, so real estate brokers would like as much information as possible about the properties they are attempting to sell. However, the time spent physically examining properties can be expensive. Therefore, brokers are often forced to limit the amount of information they collect and risk failing to satisfy a potential buyers' property information needs with the immediacy that potential buyers require.

Data collection, storage, and processing system using one or more inputs


According to some embodiments, a method is performed by a wireless device for transmitting uplink data. The method comprises determining a predetermined configuration according to which to transmit uplink data and one or more repetitions of the uplink data. The method further comprises determining a cyclic shift for one or more reference signals transmitted with the uplink data and the one or more repetitions of the uplink data. The method further comprises transmitting the uplink data, the one or more repetitions, and the one or more references signals to a network node. The uplink data and the one or more repetitions are transmitted according to the predetermined configuration. The one or more references signals are transmitted according to the cyclic shift.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used. All references to a/an/the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and/or where it is implicit that a step must follow or precede another step. Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever appropriate. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following description.
1. Long Term Evolution (LTE)
LTE uses OFDM in the downlink and discrete Fourier transform (DFT)-spread OFDM in the uplink. In the time domain, LTE downlink transmissions are organized into radio frames of 10 milliseconds (ms), each radio frame consisting of ten equally-sized subframes of length Tsubframe=1 ms.
Furthermore, the resource allocation in LTE is typically described in terms of resource blocks (RB), where a resource block corresponds to one slot (0.5 ms) in the time domain and 12 contiguous subcarriers in the frequency domain. A pair of two adjacent resource blocks in time direction (1.0 ms) is known as a resource block pair. This is also denoted as a TTI (Transmission Time Index).
Downlink transmissions are dynamically scheduled, i.e., in each subframe, the base station transmits control information about to which terminals data is transmitted and upon which resource blocks the data is transmitted, in the current downlink subframe. This control signaling is typically transmitted in the first 1, 2, 3 or 4 OFDM symbols in each subframe and the number n=1,2,3 or 4 is known as the Control Format Indicator (CFI) indicated by the physical CFI channel (PCFICH) transmitted in the first symbol of the control region. The control region also contains physical downlink control channels (PDCCH) and possibly also physical HARQ indication channels (PHICH) carrying ACK/NACK for the uplink transmission.
The downlink subframe also contains common reference symbols (CRS), which are known to the receiver and used for coherent demodulation, e.g., of the control information. A downlink system with CFI=3 OFDM symbols as control signaling is illustrated in FIG. 2. In a Rel-8 TTI, one such portion of the DL transmission is termed as one TTI.
In uplink, the data channel is sent (PUSCH) as well as the (short) physical uplink control channel ((S)PUCCH).
2. Short Transmission Time Index (TTI)
DL and UL transmission can also be carried out when configured to operate with the short TTI feature. The feature introduces two new basic transmission durations over the air interface (in addition to 1 ms duration), either of slot length or of subslot length.
A slot is defined by 7 OFDM symbols duration (defined as one LTE Rel-8 slot), while,
A subslot is defined by either 2 OFDM symbols or 3 OFDM symbols duration. The reason to have varying length of the subslot across the subframe is the split of a subframe into 14 symbols, and the design principle that a subslot is not to cross a slot boundary (leaving a slot of 7 symbols to be split into an integer number of subslots)
Due to the PDCCH region in the beginning of the first slot, the second slot will have more resources available for data.
The DL subslot pattern is dependent on the first symbol in the DL the PDSCH is allowed to map to, while the UL subslot pattern is fixed, see FIG. 3. The subslot number per subframe is denoted 0 to 5. In some DL subframes there might only be 5 subslots available for data transmission (in which case the subslot number is defined from 1 to 5).
3. Repetitions in Uplink (UL)
In typical operation, one subframe/slot/subslot transmission is transmitted per dynamic grant or per configured semi-persistent scheduling (SPS) configuration. Retransmissions are based on HARQ (feedback from the receiving end) after round-trip time after the first transmission.
An alternative to this operation is to configure K-1 repetitions. That is, the UE will instead send K transmissions without any feedback from the receiving end. These repetitions are typically, but not necessarily, configured to be transmitted consecutively in time.
4. Flexible Demodulation Reference Signal (DMRS)
A shorter transmission duration for PUSCH implies larger overhead of reference signals and lower spectral efficiency. To reduce the DMRS overhead for subslot based PUSCH transmission, DMRS sharing and DMRS multiplexing are supported. More specifically, when the same UE is scheduled on multiple consecutive subslots, DMRS sharing is supported to reduce the DMRS overhead by not transmitting DMRS within each subslot, as depicted in FIG. 4. Up to three consecutive subslots within a slot can share the same DMRS position. For instance, the DMRS is included in the first subslot and the following 2 subslots only contain data symbols. To guarantee phase coherency between the subslots sharing the same DMRS, the same bandwidth and same power should be used for all subslots sharing the DMRS.
In case different UEs are scheduled in consecutive subslots, the DMRS position can be shared between those consecutive subslots, as depicted in FIG. 4.
The following DMRS placement options exist for subslot-PUSCH. The DMRS placement can be indicated by an UL grant in subslot #n-x which schedules subslot-PUSCH in subslot n, where x is processing time configured for a PUCCH group.
TABLE 1UL DMRS placements for subslot PUSCHDMRS position pattern indicated by a UL grant scheduling PUSCH insubslot nsubslot 0subslot 1subslot 2subslot 3subslot 4subslot 5R D DR DR DR DR DR D DD D RD RD DD RD RD DD D | RD DD D | RD D | RNote:"|" denotes the boundary of subslot n
Based on the patterns listed in Table 1, different configurations of DMRS sharing can be achieved by, e.g., scheduling PUSCH transmissions in subslots 0, 1 and 2 to the same UE with patterns RDD, DD and DD, respectively; or scheduling PUSCH transmissions in subslots 0 and 1 to the same UE with patterns DDR and DD, respectively.
In case of semi-persistent scheduling (SPS), the possible DMRS positions are based on Table 2.
TABLE 2UL DMRS placements for subslot PUSCH and SPSsDCI field(1-bit)sTTI 0sTTI 1sTTI 2sTTI 3sTTI 4sTTI 50 (no sharing)R D DR DR DR DR DR D D1R D DD D | RR DD D | RR DR D DR: Reference symbolD: Data|: sTTI border
There currently exist certain challenges. The current solution is designed for transmission of one sTTI per dynamic grant. Unless dynamic indication is used for every repetition, the presence of DMRS can't be controlled. Thus, for configured or indicated repetition of the same data K times, multiple DMRS will be inserted, at least one for each repetition, adding to the overhead and making the code rate higher than necessary.
Viewing Table 1 as a baseline, one can see that for any given subslot scheduled, the lowest number of data symbols will be one. That is, if a UE is scheduled a single subslot, there will only be one data symbol, since DMRS must also be included. Looking at the table for multiple blind repetitions, the corresponding number of symbols for two and three transmissions in total (i.e. one or two blind repetitions) is 3 and 4 data symbols. This is still substantial overhead that impacts the reliability of the data transmission.
Certain aspects of the present disclosure and their embodiments may provide solutions to these or other challenges. For example, a set of DMRS patterns may be defined for which may be pre-configured or dynamically indicated for data repetition in UL. In some embodiments, the presence and position of DMRS in the sTTI may be used to infer the sequence number in the repetition.
There are, proposed herein, various embodiments which address one or more of the issues disclosed herein. According to one embodiment, a wireless device may determine a reference signal pattern for data repetition in an uplink. The wireless device may transmit uplink data to a network node with K-1 repetitions. One or more reference signals are included in the transmitted uplink data according to the determined reference signal pattern. K is an integer equal to or greater than 2. According to another embodiment, a base station may receive uplink data from a wireless device with K-1 repetitions. One or more reference signals are included in the received uplink data according to a reference signal pattern. The base station may determine an uplink channel quality from the wireless device based on the one or more reference signals. K is an integer equal to or greater than 2.
Certain embodiments may provide one or more of the following technical advantages. For example, in certain embodiments, the code rate can be reduced without increasing overhead, which enables data transmissions with low block error rate (BLER). As another example, the proportion of data symbols may be increased, thereby allowing for guaranteed transfer rate even with the repetition sequence. As yet another example, overhead may be reduced by reducing DMRS overhead. Further, certain embodiments may allow a network node to find the sequence index of the transmission, which may help in finding the rest of the sequence.

Code rate enhancement for uplink data repetition


A flash memory writing method for writing data into a flash memory storage system is provided. In the present method, a big data usage number and a small data usage number are counted for each logical unit in the flash memory storage system, so as to respectively represent the numbers of writing a big data and a small data into each the logical unit. When a host system writes new data into a logical unit in the flash memory storage system, the new data is written through different writing processes according to the big data usage number and the small data usage number of the logical unit. Thereby, the data writing efficiency is improved and the lifespan of the flash memory storage system is prolonged.

1. Technology Field
The present invention generally relates to a flash memory writing method, and more particularly, to a flash memory writing method which can write data through different writing processes according to a usage pattern of each logical block in a flash memory and a flash memory storage system and a flash memory controller using the same.
2. Description of Related Art
Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand to storage media for storing digital contents has increased drastically. Flash memory is one of the most adaptable storage media to be carried around and used for storing digital files due to its characteristics such as data non-volatility, low power consumption, small volume, and non-mechanical structure.
Conventionally, a flash memory storage device is mainly used for storing user data. For example, a user may use a flash drive for storing digital files or use a memory card as the storage medium of a portable device, such as a digital camera or a MP3 player. Such a flash memory storage device is usually used for storing digital data of large quantity (for example, data above 64 Kb or 128 Kb). Along with the development of flash memory technology, the storage capacity of flash memory storage devices has increased while the cost thereof has decreased. Thus, many computer manufacturers start to use solid state drive (SSD, which has a flash memory as its storage medium) as the primary disk in computer systems.
Based on the physical characteristics of flash memory, the memory cells in a flash memory can only be programmed in a single direction (i.e., each bit in a memory cell can only be programmed from "1" to "0"). Thus, before writing a new data into a memory cell of a flash memory, the data previously stored in the memory cell has to be erased first.
Regarding the design of a flash memory storage system, physical blocks in the flash memory storage system are usually grouped into a plurality of physical units. Each physical unit has at least one flash memory cell, wherein the flash memory cell is composed of at least one transistor (such as a metal oxide semiconductor field effect transistor (MOSFET) or other logic circuit) and stores at least one bit. These physical units are grouped into a data area and a spare area. Physical units in the data area store valid data written by write commands, and physical units in the spare area are used for substituting the physical units in the data area when the write commands are executed. To be specific, when a flash memory storage system receives a write command from a host and is desired to write new data into a physical unit to be updated in the data area, the flash memory storage system selects a physical unit from the spare area and writes both the valid old data copied from the physical unit to be updated in the data area and the new data into the physical unit selected from the spare area. Then, the flash memory storage system links the physical unit containing the new data to the data area and erases the physical unit ro be updated and links it to the spare area. In order to allow the host to successfully access the physical units which are alternatively used for storing data, the flash memory storage system provides logical units to the host. Namely, the flash memory storage system reflects the alternation of the physical units by recording and updating mapping relationships between the logical units and the physical units in the data area in a logical address-physical address mapping table. Thereby, the host simply writes data into a provided logical unit while the flash memory storage system accesses the corresponding physical unit according to the logical address-physical address mapping table.
Based on the operation mechanism of flash memory storage system described above, when a flash memory storage system is used as a primary hard disk of a computer system, because the computer system frequently writes and updates data in small quantities (for example, data less than 4 Kb or 8 Kb), erasing operations will be frequently performed to the physical units in the flash memory storage system in order to write data alternatively into the physical units. However, the physical blocks for forming a physical unit can only be erased for a limited number of times (for example, 10,000 times at most). Thus, the lifespan of a flash memory storage device will be greatly shortened by frequently erasing the physical units thereof.

Flash memory writing method and storage system and controller using the same


A dental flosser for cleaning the spaces between the teeth is provided. The dental flosser includes a hollow interior casing of roughly E-section having a narrow end and a wide end, a first and a second support for supporting in proper tense of a segment of the floss, a first receiving space for receiving a coiled up floss, a L-shaped second receiving space for receiving a cutting unit, an enlarged circular interior abutting a rectangular interior inside the second support in addition with a pair of accesses for rotatably engaging a rotatable abutment therein. A segment of floss winds on a plurality of first posts and the top of the abutment and engaged with a plurality of second slotted posts inside the narrow end of the casing, and then drawn out from the first support and wind in a slot at, lower end of the abutment, inside the second support for rotatably adjusting the proper tense of the floss. A clip-on cap covers the narrow end of the casing for preventing the floss from stained with external contaminations.

The present invention relates to dental apparatus and more particularly to a structure improved dental flosser which includes a rotatable abutment, a cutting unit and a clip-on cap so that the tension of the floss is adjustable, the used segment of the floss is cutaway and the floss is kept from external contamination.
The dental flosser becomes more popular than the toothpick in the modern market because it protects the enamel surface of the teeth. FIG. 1 shows an original type of the dental flosser which is composed of a pair of parallel supports 1 and 2, a handle 3 and a segment of floss 4 tensionally secured between the support 1 and 2. So that the users grip the handle 3 and clean the spaces between their teeth. This dental flosser is usually sold in gross package. Each time, the user picks one of them and casts away after it is used so as to waste materials.
FIG. 2 shows an improved dental flosser which comprises a hollow elongate body, a pair of supports 5 parallel projected from a narrow end including a longitudinal slot 6 relative to the body in their free ends, a retaining rod 7 abutting the foot of the inner support 5, a recess 8 in an under side wall and a roller 9 integrating with a ratchet gear rotatably disposed in a wide end of the body for winding the floss thereon. In practice, the floss is drawn out through the recess 8 and abuts on the under side of the body and then secures to the retaining rod 7 after passing through the slots 6 of the supports 5 respectively. The floss is then tensioned by a counterclockwise rotation of the roller 9 so that the ratchet gear is checked from clockwise rotation. This type of dental flosser has an advantage of repeated application. However, it has also several disadvantages set forth as follows:
a) the tension of the floss between the supports 5 is unadjustable so that if the floss is too tense, it will hurt the gum of the teeth, PA1 b) for preventing the floss from breakaway, the floss adapted to this type of dental flosser must be rather thick so that a thick floss is difficult to insert into the spaces between the teeth, unless it damages the enamel surface of the teeth, and PA1 c) a great segment of floss exposed to the outside of the body oughts to be stained with the external contaminations.
The present invention is arisen to militate and/or obviate the aforediscussed disadvantages and provides a qualified dental flosser to the users.

Dental flosser having a substantially E-shaped hollow casing


A banknote temporary storage unit of a banknote processing device includes a box body, and further includes a controllable telescopic rod having one end configured to be fixed at a transaction port of the banknote processing device and a telescopic end articulated to the box body. The box body is slidably arranged at the transaction port, and in the case that the controllable telescopic rod is at a terminal of a telescoping stroke of the controllable telescopic rod, the box body is located outside the transaction port, and a banknote dispensing space in the box body is in a visible area.

With the continuous development of economy, the processing amount of banknotes is continuously increased, and the requirement for processing capacity of the banknote processing device is increased accordingly. At present, main functions of the widely used banknote processing device include banknote withdrawing, banknote depositing, bank transfer and etc. In the process for realizing the above functions, the banknote processing device generally needs to store the banknotes to be withdrawn or deposited in a banknote temporary storage unit. After all the banknote to be withdrawn or deposited is processed, a gate of the banknote processing device is opened to allow the user to take out the banknotes, or the banknotes are conveyed to other part of the banknote processing device.
The banknote temporary storage unit is generally mounted inside a housing of the banknote processing device. In the withdrawal operation, after the gate of the banknote processing device is opened, the user may see the banknotes in the banknote temporary storage unit and take out the banknotes. However, since the banknote temporary storage unit is away from the user and has a relatively small angle with respect to the vertical direction, the user would not see the banknotes in the banknote temporary storage unit clearly, which may cause part of the banknotes is left behind by the user in the withdrawal performance, and the left banknotes would be taken out by other users, thus rights and interests of the user cannot be protected.
In addition, after the gate of the banknote processing device is opened, the user needs to put the hand into the banknote temporary storage unit, and if the control unit of the banknote processing device is disabled, the gate may be closed even when the hand of the user is still in the banknote temporary storage unit. Thus, the hand of the user will suffer a force from the gate, which may injure the user. Due to the above situation, the user would be afraid when operating the banknote processing device. Thus, the above structure of the banknote processing device is less user-friendly.
Thus, an important technical problem to be solved presently by those skilled in the art is to better protect rights and interests of the users.

Paper currency processing device and paper currency temporary storage device

GRG Huitong Financial Services Co., Ltd.


The present invention provides a method and system to implement a distributed array using the distributed property as an attribute attachable to an array. The present invention maintains the top level array implementation so as to avoid making the top level users to learn how to use a brand new class for creating and manipulating distributed arrays.

MATLAB® is a product of The MathWorks, Inc. of Natick, Mass., which provides engineers, scientists, mathematicians, and educators across a diverse range of industries with an environment for technical computing. MATLAB® is an intuitive high performance language and a technical computing application that provides mathematical and graphical tools for mathematical computation, data analysis, visualization and algorithm development. As a desktop application, MATLAB® typically runs on a single computer. However, there is a limit to the complexity and the size of a problem that a single computer can solve. For example, for a data intensive program utilizing a few 1000 by 1000 arrays, there might not be enough processing power on the single computer to manipulate these arrays, or the program might take days to complete execution. Furthermore, there might not be enough memory on a processor to store one or more of the arrays needed for a data intensive program.
With many engineering and scientific problems requiring larger and more complex modeling, many scientists and engineers are interested in using parallel computing to solve their problems. Therefore, it is desirable to provide a user-friendly technique to employ parallel computing in a technical computing environment.

Distributed arrays in parallel computing environments


A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.

1. Field of the Invention
The present invention generally relates to semiconductor devices and manufacturing methods of the same, and more specifically, to a semiconductor device having a projection electrode (bump) for outside connection and an organic insulation film and a manufacturing method of the same.
2. Description of the Related Art
Recently, a flip chip connection structure using a projection electrode for outside connection, called a bump, has been widely applied for high density mounting of a package and a semiconductor element.
In a case where solder is selected as a material of such a bump, the bump can be formed by a plating method or a printing method.
A barrier metal layer is formed on the electrode layer by using an electrolytic plating method in order to prevent the solder from being diffused on the semiconductor element, and the soldering bump is formed on the barrier metal layer by a plating method. See Japanese Laid-Open Patent Application Publications No. 2004-200420 and No. 9-191012, for example.
In this case, a surface of the semiconductor element is covered with an organic insulation film such as polyimide for device protection. The surface of the electrode layer is also selectively covered with the organic insulation film.
A manufacturing process of the bump by using the relating art plating method in a manufacturing process of the semiconductor device is shown in FIG. 1.
In a bump forming process by using the related art plating method, first, as shown in FIG. 1-(a), a wiring layer made of silicon (Si) and an electrode layer (electrode pad) 3 are provided on an upper surface, namely a circuit element forming surface, of a semiconductor substrate 1 made of silicon (Si) via an insulation film (insulation layer) made of silicon oxide, for example.
An upper part of the semiconductor substrate 1 including the wiring layer and the electrode layer 3 is covered with an inorganic insulation film (passivation film) 2 made of silicon nitride (SiN) or the like.
In addition, an organic insulation film 4 such as a polyimide resin layer or the like is provided on the inorganic insulation film 2. The organic insulation film 4 is formed for surface protection of the semiconductor element and for easing stress concentrated on a base of the bump 9 when the semiconductor element is mounted on a wiring board 11 (See FIG. 3).
An opening is formed in the inorganic insulation film 2 and the organic insulation film 4 as corresponding to an expected forming position on the electrode layer 3 of the soldering bump 9 so that a pad is exposed.
Illustration of an active element such as a transistor, and a passive element such as resistor element or capacity element formed on the semiconductor substrate 1, an isolation area for insulation-isolating between these elements, an interlayer insulation layer, an inter-element mutual wiring layer, or the like is omitted in FIG. 1.
Next, as shown in FIG. 1-(b), a power supply layer 5 as a plating electrode is formed, by sputtering method, on whole surfaces of the electrode layer (electrode pad) 3 and the organic insulation film 4 on the semiconductor substrate 1.
Next, a photo resist layer 6 is applied on the power supply layer 5 by a spin coating method and exposure, developing and curing processes are performed, so that, as shown in FIG. 1-(c), the opening corresponding to the expected forming position on the electrode layer 3 of the soldering bump 9 is formed in the photo resist layer 6.
Next, an electrolytic plating process is performed, so that, as shown in FIG. 1-(d), a barrier metal layer 7 is formed in the opening in the photo resist layer 6 so that the diffusion of solder in the soldering layer 9 into the electrode layer is prevented.
Next, an electrolytic plating process is made by using the photo resist layer 6 as a mask, so that, as shown in FIG. 1-(e), a tin-silver (Sn—Ag) soldering layer 9 is formed on the barrier metal layer 7. At this time, the soldering layer 9 is formed so as to extend on the photo resist layer 6.
Next, as shown in FIG. 1-(f), the photo resist layer 6 is removed by using release liquid. Furthermore, an unnecessary part of the power supply layer 5 is removed by wet etching wherein the soldering layer 9 is used as an etching mask.
After that, the soldering layer 9 is made molten by reflow heating so that, as shown in FIG. 1-(g), the soldering layer 9 is formed in a substantially spherical shape. In other words, a spherical-shaped soldering bump (soldering ball) 9 is formed on the electrode layer 3 of the semiconductor substrate 1.
In a case where the bump is manufactured by using the printing method, after the barrier metal layer 7 is selectively formed in the opening in the photo resist 6 shown in FIG. 1-(d), as shown in FIG. 2-(a), the photo resist layer 6 is removed by using the release liquid and the wet etching process using the etching liquid is applied to the power supply layer 5.
After that, as shown in FIG. 2-(b), a pattern (not illustrated) for printing is made so that the tin-silver (Sn—Ag) soldering layer 9 is formed on the barrier metal layer 7, and the soldering plating layer 9 is made molten by reflow heating. As a result of this, as shown in FIG. 1-(g), the spherical-shaped soldering bump (soldering ball) 9 is formed on the electrode layer 3 of the semiconductor substrate 1.
An example of a method of mounting the semiconductor element 10 where the bump 9 made of tin-silver (Sn—Ag) soldering is formed on the semiconductor substrate 1, on the printed board 11 is shown in FIG. 3.
As shown in FIG. 3-(a), the semiconductor element 10 where the bump 9 is formed on the semiconductor substrate 1 is mounted on the printed board 11 by a flip chip bonding method. In other words, where the surface of the semiconductor element 10 has the bump 9 formed facing downward, the semiconductor element 10 is mounted on an upper surface, namely a wiring surface of the printed board 11. Here, ball bumps 12 for outside input/output are formed on a lower surface of the printed board 11
Next, as shown in FIG. 3-(b), in order to improve connection reliability, underfill 13 is applied between the semiconductor element 10 and the printed board 11 and cured, so that connection between the semiconductor element 10 and the printed board 11 is reinforced.
Last, as shown in FIG. 3-(c), a passive element 14 such as a condenser or the like is provided in the periphery of the semiconductor element 10 on the printed board 11 and a heat radiation plate 15 for radiating heat generated by the semiconductor element 10 is provided at an upper part of the semiconductor element 10, so that the semiconductor device is formed.
In the meantime, details of forming of the power supply layer 5 on the electrode layer (electrode pad) 3 and the organic insulation film 4 discussed with reference to FIG. 1-(b) and details of the wet etching process for the power supply layer 5 discussed with reference to FIG. 1-(f) and FIG. 2-(a) are discussed with reference to FIG. 4 through FIG. 6.
Here, FIG. 4 is a view for explaining an electrode layer (electrode pad) and a power supply layer on an organic insulating protection film. FIG. 5 is a view for explaining the status of a surface of the organic insulating protection film in processes shown in FIG. 4. FIG. 6 is a view for explaining the status of a surface of the organic insulating protection film in a process for removing the power supply layer by a wet etching process.
In order to form the power supply layer 5 on the electrode layer (electrode pad) 3 and the organic insulation film 4, first, as shown in FIG. 4-(a), a dry etching (RF etching) process is applied to the whole surfaces of the electrode layer (electrode pad) 3 and the organic insulation film 4 by using argon (Ar) gas so that a natural oxide film on the surface of the electrode layer (electrode pad) 3 is removed.
By such a dry etching process, as shown in FIG. 5-(a), a modified layer is generated on a surface layer of the organic insulation film 4. The etching amount of the surface of the organic insulation film 4 at this time is small and the maximum surface roughness of the organic insulation film 4 is approximately 4 nm. Therefore, the surface roughness of the organic insulation film 4 is not dramatically changed by this process.
Next, a metal forming the power supply layer 5 is deposited on the surface of the organic insulation film 4 including the modified layer 20 by sputtering.
More specifically, as shown in FIG. 4-(b), a titanium (Ti) layer 5-1 is formed on a surface of the organic insulation film 4 including the modified layer 20 by sputtering. By such a sputtering, as shown in FIG. 5-(b), titanium is embedded in the surface of the modified layer 20.
Next, as shown in FIG. 4-(c), a copper (Cu) film 5-2 is formed on the surface of the titanium (Ti) film by sputtering. At this time, as shown in FIG. 5-(c), since the copper film 5-2 is deposited on the titanium film 5-1, the copper film 5-2 does not directly come in contact with the organic insulation film 4 and therefore does not influence the surface of the organic insulation film 4.
In the process shown in FIG. 1-(f) in the case of the plating method or in the process shown in FIG. 2-(a) in the case of the printing method, the power supply layer 5 (the titanium film 5-1 and the copper film 5-2) formed on the organic insulation film 4 is removed by the wet etching process.
Next, with reference to FIG. 6, the status of the surface of the organic insulation film 4 in the process whereby the power supply layer 5 is removed by the wet etching process is discussed.
Where the copper film 5-2 is deposited on the titanium film 5-1 as shown in FIG. 6-(a), first, the copper film 5-2 is removed by wet etching as shown in FIG. 6-(b). Since the copper film 5-2 is deposited on the titanium film 5-1, it is possible to easily remove the copper film 5-2.
Next, as shown in FIG. 6-(c), the titanium film 5-1 deposited on the modified layer 20 is removed by wet etching. While the titanium film 5-1 provided on the surface of the modified layer 20 is easily removed, titanium embedded in the surface of the modified layer 20 remains even after the titanium film 5-1 provided on the surface of the modified layer 20 is removed.
FIG. 7 is a view of the soldering bump 9 formed on the semiconductor element 10 of the semiconductor device manufactured by the related art manufacturing method including the above-discussed processes. FIG. 7-(b) is an expanded view of a part surrounded by a broken line in FIG. 7-(a).
Referring to FIG. 7, in the semiconductor element 10 manufactured by the above-discussed processes, the titanium film 5-1, the copper film 5-2 and the barrier metal layer 7 are formed on the organic insulation film 4 in this order. The bump 9 is formed on the barrier metal layer 7.
Titanium 5-1 embedded in the surface of the organic insulation film 4 and remaining as a metal residue is normally not observed by a metal microscope, an electron microscope, or the like. However, approximately 10 atm % of this titanium 5-1, as a maximum, is detected by analysis using X-ray Photoelectron Spectroscopy (XPS). The surface roughness of the organic insulation film 4 is approximately 4 nm as a maximum, which is substantially equal to the surface roughness of the organic insulation film 4 formed on the inorganic insulation film 2 shown in FIG. 1-(a).
Thus, in the semiconductor device manufactured by the related art method, the titanium 5-1 forming the power supply layer 5 remains embedded in the surface of the organic insulation film 4 of the semiconductor element 10 as the metal residue.
However, such a metal residue obstructs adhesion between the organic insulation film 4 and the underfill 13 (See FIG. 3) filling in between the semiconductor element 10 and the printed board 11 for reinforcing the connection between the semiconductor element 10 and the printed board 11. As a result, the reliability of the connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11 may be degraded.
On the other hand, as discussed above, the surface roughness of the organic insulation film 4 is approximately 4 nm as a maximum, which is substantially equal to the surface roughness of the organic insulation film 4 formed on the inorganic insulation film 2. Therefore, the surface roughness of the organic insulation film 4 is too small to obtain sufficient adhesion with the underfill 13.
Accordingly, the reliability of the connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11 may be degraded.
Thus, in order to ensure a reliable connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11, it is necessary to both remove the metal residue remaining embedded in the surface of the organic insulation film 4 and make the surface roughness of the organic insulation film 4 large so that sufficient adhesion with the underfill 13 can be obtained.
If the organic insulation film 4 in the vicinity of the bump 9 is removed for the above-mentioned purpose, when the semiconductor element 10 is mounted on the printed board 11, stress is concentrated on the organic insulation film 4 in the vicinity of the bump 9. As a result, cracks may be generated in this part, and therefore the reliability of the connection between the semiconductor element 10 and the printed board 11 after the semiconductor element 10 is mounted on the printed board 11 may be degraded.

Semiconductor device and manufacturing method of the same


A cutting chuck for use with a cutting blade and for holding a semiconductor wafer in place during a dicing process and a die pick for picking the segmented semiconductor wafer from the chuck. The chuck includes a surface for supporting the wafer and several ports in the surface connected to a vacuum source. Preferably, the cutting chuck includes a housing having a base and a wall. A vacuum chamber is provided within the housing and on top of the base. A porous layer is located in housing and above the vacuum chamber. A surface layer is above the porous layer and contains ports connecting the surface supporting the wafer to the vacuum chamber via the porous layer. In a most preferred embodiment, the chuck is removeably attached to the vacuum source via a check valve. The cutting chuck may also include recesses in the surface to prevent impingement on the cutting chuck by a cutting blade during wafer dicing. The die pick includes a pick head having a surface for contacting the plurality of die sawn from a wafer. The surface includes a plurality of ports that are in fluid communication with a vacuum source. The die pick picks the plurality of die from the chuck for further processing.

1. Field of the Invention
The present invention is directed generally to a method and apparatus to hold integrated circuit chips on, and remove the chips from, a cutting chuck without the use of an adhesive or a wafer frame. More particularly, the invention is directed to a method and apparatus using differential pressure to both hold the chips on the cutting chuck and to remove the chips from the cutting chuck.
2. Description of the Background
Integrated circuits have touched almost every aspect of society, such as children's games and toys, engine computers in automobiles, personal computers in homes and offices, and controllers in industrial processes. Better ways to fabricate integrated circuits are constantly being sought.
Integrated circuits are fabricated on semiconductor wafers, and the each wafer typically contains between 50 and 1,000 individual integrated circuits, depending on the size of the wafer and the size of the individual integrated circuits. Between the integrated circuits are spaces, known as "street indices", which separate the individual integrated circuits on the wafer. Street indices are as small as possible, and are typically four mil to six mil wide. In a process known as "dicing", wafers are cut along the street indices to form separate integrated circuits, known as "dice". A street index which has been cut is known as a "street". When the dicing process is completed, the streets form a grid which defines the dice cut from the wafer.
The dicing process is performed with a cutting assembly having a circular cutting blade. The design and use of the cutting assembly and cutting blade are well known in the prior art, and such devices may be obtained from Disco Hi Tec America, Inc., located in Santa Clara, Calif. The cutting blades are about one mil thick and spin at speeds between 30,000 and 60,000 revolutions per minute. Cutting blades are often nickel-plated with a diamond grit cutting edge to insure smooth, clean cuts, with minimal fraying and splintering.
Wafers are placed on a smooth, level surface, known as a "cutting chuck", where they are diced by the cutting blade. During the dicing process, the cutting blade will occasionally protrude below a wafer and into the underlying cutting chuck. The contact between the cutting blade and cutting chuck accelerates the wear on the cutting blade, and often breaks the cutting blade and results in damage to the cutting chuck.
It is well known in the prior art to use a wafer frame and adhesive tape to maintain dice in place during the dicing process. The wafer frame is generally flat and defines an opening which is larger than the wafer. The adhesive tape is attached to the wafer frame and stretched across the opening. A wafer is secured to the adhesive tape within the opening, and the frame is secured, for example by a vacuum, to the cutting chuck for dicing. After the dice have been cut, the frame, along with the adhesive tape and the dice, are removed from the cutting chuck. The dice are separated from the adhesive tape, the adhesive tape is removed from the frame, and the frame is reused. The adhesive tape is known as "sticky back" and is usually a polymer-based film, such as polyvinyl chloride ("PVC"), with an adhesive coating on one side. The adhesive tape is usually about 3 mils thick. The dice stick to the adhesive, so that when the wafer is cut the dice remain in place on the cutting chuck and are not scattered. Because a cutting blade extends slightly below the wafer, the cutting blade is exposed to the adhesive tape. The adhesive binds to the cutting blade, causing accelerated blade wear and "gumming-up" the cutting blade. A gummed-up cutting blade reduces the effectiveness of the cutting blade, increases friction between the cutting blade and the wafer, and increases the tendency of the cutting blade to bind and breaking. Heat is generated from friction between the cutting blade and both the wafer and the sticky-back. The faster the cutting blade is moved through the wafer, the more heat is generated, and that heat is increased when the cutting blade is gummed-up. In addition, the risk of the cutting blade binding increases as the temperature of the cutting blade increases. Furthermore, the integrated circuits may be damaged by the heat. As a result, the heat generated by the dicing process, and all of the undesirable side effects of the heat, limits the rate at which the cutting blade can be moved across a wafer. As the rate of the dicing processes decreases, the amount of time required to dice a wafer increases.
The accelerated wear and damage caused to cutting blades from contact with the chuck and the adhesive requires that they be replaced after dicing only about five or six wafers. Worn cutting blades lack the sharpness to cleanly cut a wafer, and cutting blades exposed to adhesives have rough sides and an irregular cutting surface formed from hardened adhesive picked up during previous cuts of a wafer. The continued use of a worn cutting blade may result in damaged or totally destroyed wafers caused by a cutting blade breaking and spraying debris across the wafer. Replacing cutting blades is expensive not only in terms of the costs of the cutting blade, but also in terms of down time of the dicing process and interruption of the fabrication process while an old cutting blade is being removed and a new cutting blade is being installed.
After the dicing process is completed, the dice need to be tested and the good dice separated from the bad. The wafer frame, along with the associated adhesive tape and dice, may be removed from the chuck and placed at a testing station, or the testing may be done on the cutting chuck. During testing, each die is individually tested to determine whether it is functional, and if so, whether it meets the specifications set for the chip. Information regarding which die are good and which are bad, along with other test data, is stored in a memory device. Since there are almost always some bad dice, a die pick is used to selectively remove only the good dice for further processing. The bad dice remaining on the adhesive tape are discarded.
The construction of die picks are well known in the prior art. Die picks include a moveable suction device which develops a pressure differential relative to the ambient pressure around the die pick. The suction device has a single, small suction opening or port, so that it engages only one die at a time. The suction device is maneuvered against a single good die and a suction is used to engage the die. Once engaged, the die pick moves the die to another station and releases it for further transport or processing.
As stated above, wafers often yield as many as 1,000 dice. As a result, a large number of dice must be removed by the die pick. Because die picks move only a single die at a time, they are a bottleneck in the process of fabricating semiconductor chips. For example, a conventional die pick typically requires between one half of a second and one second to remove one die from a group of dice and place it on another processing station. If five hundred dice need to be moved by the die pick, a delay of between 250 and 500 seconds occurs while the dice are being removed.
Thus, the need exists for an improved method and handling assembly which reduces the amount of time required to separate good dice from bad dice. In particular, the need exists for a handling assembly which can remove all of the good dice in a single operation.
Furthermore, the need exists for an improved cutting chuck which reduces the amount of wear and damage to a cutting blade. In particular, the need exists for a cutting chuck which does not interfere with a cutting blade during dicing, and which prevents contact between a cutting blade and adhesives currently used to secure a wafer during dicing.

Apparatus to hold and remove an integrated circuit chip on a cutting chuck