An increase in a dynamic random access memory (DRAM) chip area is minimized by dividing data lines into multiple sections, arranging global data lines parallel to the data lines and placing them in a hierarchical structure. The switches connecting the data lines and the global data lines are arranged separately or in alternate positions to further reduce the chip area. The influence of noise due to the length of data lines is reduced. Sense amplifier drive circuits are controlled to selectively apply voltages to the sense amplifiers depending upon the length of the path from each sense amplifier to a particular memory cell.

In recent years, DRAMs have made a significant advance in terms of circuit integration and a 1 Gb DRAM development chip has already been made public. The biggest challenge faced in realizing such large capacity DRAMs is an increase in power consumption. The power consumption of DRAMs includes the power consumption by memory arrays and peripheral circuits. Normally, the former accounts for the major portion of the DRAM's power consumption. The power consumed by the memory arrays is due to the parasitic capacitors Cd of data lines that are charged or discharged. As the capacity of memory arrays increases, the number of data lines charged and discharged simultaneously increases, thus increasing the power consumption of the memory arrays.
Finding a method of hierarchically structuring the data lines and dividing them into multiple parts to reduce the Cd charge/discharge power or to increase the number of readout signals from memory cells is drawing increased attention. A method of keeping the chip area from increasing when the number of divisions of data lines is increased is detailed as a BMGB (bidirectional matched global bit line) method in an IEEE publication entitled "1993 Symposium on VLSI Circuits Digest of Technical Papers", pp. 91-92 (1993).
FIG. 16 shows a memory array of the BMGB method described in FIG. 1(b) of the above-mentioned publication. Memory cells (MC's) are connected to the intersections between the word lines (W) and the data lines (D) and have a cell arrangement that is of a folded data line structure. At each data line D, there is provided a data line connection switch (QT). A global data line pair (GD-GDB) is provided parallel to data lines D. Three global data line pairs (GD0-GD0B to GD2-GD2B) are aligned in the direction of data lines and are connected with each other by global data line separation switches (QM0, QM0B, QM1 and QM1B). The global data line pairs are connected to the sense amplifiers (SA0, SA1) at both ends as shown.
The connection relation between the data lines D and the global data lines GD is as follows. The pairs D0-D0B and D1-D1B are connected at their right ends to QT0 and QT1, which in turn are connected to GD0-GD0B and GD1-GD1B, respectively. D2-D2B and D3-D3B are connected at their left ends to QT2 and QT3, which in turn are connected to GD1-GD1B and GD0-GD0B, respectively. That is, in this example, data line connection switches (QTs) and global data line separation switches (QMs) are concentrated in the switch block SWB. Other data lines are similarly connected to global data lines.
FIG. 16 shows the switch control when reading data from memory cells (MC) at the intersections between W0 and D0 and D1. Only QT0 and QT1 are turned on, with other data line connection switches (QT) turned off. QM0-QM0B are turned off, with QM1-QM1B turned on. This connects D0-D0B to SA0 through GD0-GD0B, and D1-D1B to SA1 through GD1-GD1B and GD2-GD2B.
This method reduces the length of data lines connected to the sense amplifiers to 1/4 compared to that of the normal array configuration and also reduces the parasitic capacitance Cd to 1/4. On the other hand, this configuration connects extra parasitic capacitance of global data lines. Data lines have a large number of memory cell transistors connected thereto and thus have a large parasitic capacitance whereas global data lines have a simple wiring configuration using a wiring layer located above that of data lines and have a relatively small parasitic capacitance. Hence, the total parasitic capacitance connected to the sense amplifiers is smaller than the parasitic capacitance of the conventional method. This allows reduction in the charge/discharge power consumption of the array and an improved signal to noise (S/N) ratio.
FIG. 23 shows conventional twisted global data lines according to FIG. 2 of the above-mentioned IEEE publication, in which the global data lines are twisted to reduce coupling noise between global data lines. In the figure, the present inventors assumed that the length of global data lines corresponds to 1024 word lines and the length of data lines to 128 word lines. The sense amplifier blocks (SB) include CMOS sense amplifiers. Data lines and data line connection switches are not shown.
As shown in the figure, global data lines connected to SB0 and SB1 are twisted in an area between QM0 and QM2, and global data lines connected to SB2 and SB3 are twisted in an area between QM6 and QM8, shifted one column from the first area. Other global data lines are arranged by repeating the configuration of FIG. 23 as a unit in the direction of word lines.
The following is a discussion of the problems in the prior art as discovered by the present inventors:
(1) The first problem is related to the area needed for the switch. FIG. 17 shows a plan view (example layout) of a concrete integrated circuit that realizes the switch block SWB of the BMGB system of FIG. 16. It is assumed that switches QT and QM can each be realized by a single MOS transistor. In the figure, ACT represents an active region where MOS transistors are formed; FG a gate electrode; CONT a connection region (through-hole region) where a conductive layer forming data lines and ACT are connected; and TC1 a connection region where a conductive layer forming data lines and a conductive layer forming global data lines are connected. In the layout of FIG. 17, an ideal layout rule is assumed in which the minimum fabrication dimension is represented by F and the lithography deviation between layers is zero. This layout rule allows the switch portion of the array of FIG. 16 to be formed in an area 8 F long in the word line direction and 13 F long in the data line direction, the total length of the switch portion being 26 F. This layout, however, has a problem that there are many intersections of wires, making the layout difficult to form and increasing the area. Further, it is necessary in forming wiring to use narrow diffusion layers at intersections, thus increasing resistance of the switch portion. PA1 (2) The second problem is one of signal delay and power consumption when global data lines become long. In the array of FIG. 16, when the chip increases in capacity and the array size becomes large, the global data line becomes long, giving rise to a problem of signal delay and increased power consumption at the global data line. PA1 (3) The third problem has to with the signal to noise (S/N) ratio when the global data line becomes long. The imbalance in the length of the global data lines (GD) connected to SA0 and SA1 deteriorates the S/N. For example, in FIG. 16, when a word line W0 is selected, the data line pair D0-D0B is connected to SA0 through a GD0-GD0B pair while the data line pair D1-D1B are connected to SA1 through GD1-GD1B and GD2-GD2B pairs. This system has a unique S/N problem as described below. PA1 (4) A fourth problem has to do with coupling noise between global data lines. With the global data line twisting method shown in FIG. 23, an imbalance occurs in the coupling capacitance in the worst case and noise cannot be canceled out completely. PA1 (1) The semiconductor memory of this invention includes: a unit memory array having: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line separation switches; and sense amplifiers; PA1 wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by two serially connected global data line separation switches, and of two pairs of data lines arranged in the first direction, a first pair of data lines are connected through a data line connection switch to a connecting point between the global data line and the global data line separation switch and a second pair of data lines are connected through a data line connection switch to a connecting point between two global data line separation switches. PA1 (2) The semiconductor memory of this invention includes a unit memory array as defined in (1), PA1 wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one global data line separation switch, two pairs of data lines arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for two pairs of data lines arranged in the first direction are located on the opposing sides of the data lines. PA1 (3) The semiconductor memory of this invention includes a unit memory array as defined in (1), PA1 wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one global data line separation switch, two pairs of data lines arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for two pairs of data lines arranged in the first direction are located on the same sides of the data lines and shifted from each other in the second direction. PA1 (4) In the semiconductor memory described in (1) to (3), when reading data from two pairs of data lines arranged in the first direction or writing data into these data lines, a first data line connection switch between the first data line pair and the first global data line pair is turned on to connect the first data lines to a first sense amplifier, a second data line connection switch between the second data line pair and the second global data line pair is turned on to connect the second data lines to a second sense amplifier, and one or two global data line separation switches connected between the first global data line pair and the second global data line pair are turned off. PA1 (5) The semiconductor memory described in (1) to (3) further includes: column switches; column selection lines wired so that their longitudinal direction is set parallel to the second direction and used to control the column switches; a substrate; a first wiring layer; and a second wiring layer; wherein the column switches are formed on the substrate, the data lines are formed in the first wiring layer, the global data lines and the column selection lines are formed in the second wiring layer, the first wiring layer is interposed between the substrate and the second wiring layer, the global data lines are wired at a pitch of one global data line for every two data lines, and the column selection lines are wired at a pitch of one column selection line for every four or more data lines. PA1 (6) The semiconductor memory described in (1) to (3) further includes: column switches; column selection lines wired so that their longitudinal direction is set parallel to the second direction and used to control the column switches; a substrate; a first wiring layer; a second wiring layer; and a third wiring layer; wherein the column switches are formed on the substrate, the data lines are formed in the first wiring layer, the global data lines are formed in the second wiring layer, the column selection lines are formed in the third wiring layer, the distance from the substrate to the wiring layers increases in the order of the first wiring layer, the second wiring layer and the third wiring layer, the global data lines are wired at a pitch of one global data line for every two data lines, and the column selection lines are wired at a pitch of one column selection line for every four or more data lines. PA1 (7) The semiconductor memory of the present invention includes: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line separation switches; sense amplifiers; sense amplifier NMOS drive lines; sense amplifier PMOS drive lines; and a sense amplifier drive circuit; wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one or two global data line separation switches, the sense amplifier drive circuits comprise a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor, the first and second NMOS transistors have their sources connected to a first power supply and their drains connected to the sense amplifier NMOS drive line, the first and second PMOS transistors have their sources connected to a second power supply and their drains connected to the sense amplifier PMOS drive line, a current drive power of the first NMOS transistor is greater than that of the second NMOS transistor, and a current drive power of the first PMOS transistor is greater than that of the second PMOS transistor. PA1 (8) In the semiconductor memory described in (7), when loads of the sense amplifiers are large, the first NMOS transistor and the first PMOS transistor are turned on to connect the sense amplifier NMOS drive line to the first power supply and the sense amplifier PMOS drive line to the second power supply, and when loads of the sense amplifiers are small, the second NMOS transistor and the second PMOS transistor are turned on to connect the sense amplifier NMOS drive line to the first power supply and the sense amplifier PMOS drive line to the second power supply, in order to vary the current drive power of the sense amplifier drive circuit. PA1 (9) The semiconductor memory of this invention includes a unit memory array as defined in (1), wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different sense amplifiers, global data lines arranged in close proximity of each other in the second direction are connected to each other by one or two global data line separation switches, and when the sense amplifiers are activated after activating the word lines with the data line connection switches turned on, the resistance of the data line connection switches is increased. PA1 (10) In the semiconductor memory described in (1) to (9), the memory cell comprises one MOSFET as a switch and an information storing capacitor. PA1 (11) the semiconductor memory of this invention comprises: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line sense amplifiers; and data line sense amplifiers; and global data line separation switches; wherein a plurality of global data lines are arranged in the second direction, two pairs of global data lines arranged at the ends are connected with different global data line sense amplifiers, adjoining global data lines are connected to each other by the global data line separation switch, the data lines are connected to the data line sense amplifiers, the memory cell comprises one MOSFET as a switch and an information storing capacitor, the data line sense amplifier includes a MOSFET of the same conduction type as that of the memory cell MOSFET, and the global data line sense amplifier includes a MOSFET of a conduction type different from that of the memory cell MOSFET. PA1 (12) In the semiconductor memory described in (11), the data line sense amplifier has a current-to-voltage conversion function. PA1 (13) The semiconductor memory of this invention includes a unit memory array having: word lines wired so that their longitudinal direction is parallel to a first direction; data lines wired so that their longitudinal direction is parallel to a second direction perpendicular to the first direction; memory cells arranged at intersections between the word lines and the data lines; data line connection switches; global data lines wired so that their longitudinal direction is parallel to the second direction; global data line separation switches; and sense amplifiers; wherein two global data lines are parallelly arranged in close proximity of each other in the first direction to form a global data line pair; wherein two sets of a global data line separation switch or two sets of two global data line separation switches connected in series are arranged in the first direction to form a global data line separation switch pair; wherein a first global data line pair, a first global data line separation switch pair, a second global data line pair and a second global data line separation switch pair are arranged in the second direction in that order in close proximity of each other in order to form a first global data line group; wherein third and fourth global data line pairs are arranged in close proximity of the first and second global data line pairs in the first direction and third and fourth global data line separation switch pairs are arranged in close proximity of the first and second global data line separation switch pairs in the first direction in order to form a second global data line group; wherein the first and second global data line groups are combined to form a unit global data line group; wherein the unit global data line group is repetitively arranged in the first and second directions and additional global data line pairs are arranged in close proximity of those global data line separation switch pairs in the second direction which are located at the ends of these unit global data line groups with respect to the second direction, to form a memory array; PA1 wherein when connecting the global data line pairs arranged in their close proximity on both sides in the second direction, the first and fourth global data line separation switch pairs connect ends of those global data lines whose first direction positions are the same; wherein when connecting the global data line pairs arranged in their close proximity on both sides in the second direction, the second and third global data line separation switch pairs connect ends of those global data lines whose first direction positions are different; wherein if the global data line group arranged repetitively in the second direction is taken as a global data line column, the sense amplifiers are connected to at least two global data line pairs of each global data line column almost at the center of the global data lines. PA1 (14) The semiconductor memory of this invention includes a unit memory array as defined in (13), PA1 wherein the first to fourth global data line separation switch pairs, when connecting the global data line pairs arranged in close proximity on both sides thereof in the second direction, connect ends of those global data lines whose first direction positions are the same; wherein the second and third global data line pairs exchange their second direction positions at virtually the center of the global data lines and the first and fourth global data line pairs do not exchange their second direction positions; wherein if the global data line group arranged repetitively in the second direction is taken as a global data line column, the sense amplifiers are connected to at least two global data line pairs of each global data line column almost at the center of the global data lines. PA1 (15) In the semiconductor memory described in (13) or (14), of two data line pairs arranged in the first direction, a first data line pair is connected through a data line connection switch to a connecting point between the global data line and the global data line separation switch, and a second data line pair is connected through a data line connection switch to a connecting point between two global data line separation switches. PA1 (16) In the semiconductor memory described in (13) or (14), two data line pairs arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for the two data line pairs arranged in the first direction are located on the opposing sides of the data lines. PA1 (17) In the semiconductor memory described in (13) or (14), two data line pairs arranged in the first direction are connected through data line connection switches to different global data line pairs, and data line connection switches for the two data line pairs arranged in the first direction are located on the same sides of the data lines and shifted from each other in the second direction.
Suppose that the parasitic capacitance for each data line D is Cd, that the parasitic capacitance for a part of a global data line GD equal in length to D is Cgd and that the memory cell capacitance is Cs. The parasitic capacitance connected to an input GD0 to SA0 is Csa0(t)=Cs+Cd+Cgd, because the memory cell is connected. The parasitic capacitance connected to an input GD0B is Csa0(b)=Cd+Cgd, because the memory cell is not connected. Similarly, the parasitic capacitance connected to an input GD1 to SA1 is Csa1(t)=Cs+Cd+3Cgd and the parasitic capacitance connected to an input GD1B is Csa1(b)=Cd +3Cgd. Here, noise Vn(0) and Vn(1) induced by imbalance in memory capacitance between the input pairs for SA0 and SA1 are given as follows (as presented in "Ultra-LSI Memory" by Kyoo Itoh, Published by Baifukan, 1994, page 205): EQU Vn(0)=A.multidot.Cs.multidot.K0/(Cd+Cgd)! (1/2) (1) EQU Vn(1)=A.multidot.Cs.multidot.K1/(Cd+3Cgd)! (1/2) (2)
In these equations (1) and (2), A is a proportional constant, and K0 and K1 are amplification velocities for SA0 and SA1, respectively. When the parasitic capacitance for the global data line Cgd cannot be ignored, there is a possibility of Vn(0) increasing very greatly compared with Vn(1). This is because Cd+Cgd<Cd+3Cgd and when SA0 and SA1 are driven with the same driving force, SA0 with a smaller parasitic capacitance is amplified faster, resulting in K0>K1.
There is also a possibility that other noise or coupling noise from D0-D0B to D1-D1B may increase. This is because, if there is a difference in the amplification speed between SA0 and SA1, the D0-D0B pair is amplified rapidly to a large amplitude and the D1-D1B pair slowly so that the capacitance coupling noise to the D1-D1B pair whose signal is still small cannot be ignored.
Consider a case where, in FIG. 23, QM0 and QM5 are turned off and other global data line separation switches are turned on, which represents a worst case for sense amplifiers (SA) in SA1 and SB1 in which the read signal form the memory cell is the smallest. Suppose that under the condition that all global data lines are precharged to 1 V and floating, SA in SB1 is activated to amplify the sense amplifier node I1 to 2V and I1B to 0V. At this time, consider the coupling noise that global data lines connected to I3 and I3B receive. As to I3, GD9 receives a negative coupling from GD4B and GD6 receives a positive coupling from GD1. However, because the length of GD9 corresponds to that of 128 word lines and the length of GD6 to that of 256 word lines, the positive coupling is two times larger than the negative and thus the positive noise for 128 word lines remains intact. Next, as for I3B, GD8B receives a negative coupling from GD3B and GD7B receives a positive coupling from GD2. In this case, both GD8B and GD7B have the same length of 256 word lines and therefore the positive and negative couplings are canceled out. Because the noise differs between I3 and I3B, the operation margin for SA in SB3 deteriorates.
Conversely, let us consider the coupling noise that the global data lines connected to I1 and I1B receive when SA in SB3 is activated to amplify the sense amplifier node I3 to 2V and I3B to 0V. As to I1, GD2 receives a negative coupling from GD7B and GD1 receives a positive coupling from GD6. In this case, both GD2 and GD1 are 256 W long and their positive and negative couplings are canceled out. Next for I1B, GD4B receives a positive coupling from GD9 and GD3B receives a negative coupling from GD8B. Because GD4B is 128 W long and GD3B is 256 W long, the negative coupling is two times larger and thus the negative noise for the length of 128 W remains intact. Therefore, in this case, too, the noise differs between I1 and I1B, degrading the margin of operation of SA in SB1.
In a DRAM of a hierarchical data line structure, the object of the present invention is to (1) provide a circuit system which reduces the size of switches when forming data lines in hierarchical structures so that the chip area can be kept from increasing when the number of divisions of data lines is increased; (2) suppress increases in signal delay and power consumption in the global data lines; (3) offer an operation system that prevents deterioration of the S/N even when there is an imbalance in parasitic capacitance between global data lines; and (4) reduce the coupling noise between the global data lines.

Semiconductor memory having a hierarchical data line structure


Quantification of a condition of a selected item using a neural network is disclosed. A device defines a good hypertube in a neural state space based on good item state points obtained from one or more items that exhibit desired operating characteristics, and a bad hypertube in the neural state space based on bad item state points obtained from one or more items that exhibit undesirable operating characteristics. A current item state hyperpoint is determined in the neural state space based on a current item state point of the selected item. A condition of the selected item is quantified as a function of a location of the current item state hyperpoint with respect to at least a portion of the good hypertube and with respect to at least a portion of the bad hypertube.

Many large-scale distributed organizations, such as package delivery services, airlines, and the military, need to continually maintain relatively complex machines. Increasingly, machines are being equipped with sensors that sense and measure various attributes of the machines, such as temperature, oil pressure, vibrations, and the like. Humans can analyze such data and then make determinations regarding the condition of the machine. However, such analyses can be very complicated, time-consuming, and expensive.

Quantifying a condition with a neural network


A cogeneration method and device by turbine, particularly by gas turbine, uses a compression section, at least one expansion section, and a combustion chamber. A combustion agent including oxygen is compressed in the compression section; in the combustion chamber, one combustion step is carried out under pressure with a mixture of combustion agent compressed with a fuel; at least some of the hot gases obtained by pressurized combustion are used to effect an exchange with an external facility; and at least one postcombustion step is carried out of a mixture of hot gases coming from combustion with a fuel, prior to the exchange, and at least one other postcombustion step of a mixture of hot gases, coming from the exchange, with a fuel, in order to obtain hot gases that are sent to the expansion section.

The present invention relates to a method and a device for cogenerating heat and work.
It relates in particular to a cogeneration method implemented by means of a turbine, particularly a gas turbine.
More specifically, the method consists of using the hot combustion gases generated by the gas turbine to exchange heat with an industrial facility to produce an endothermic reaction for example.
Prior cogeneration methods consisted of using the hot combustion gases leaving the turbine, which are generally at a pressure close to atmospheric pressure, to generate for example steam under pressure by heat exchange produced in an exchanger traversed by these hot gases and through which a fluid such as water flows. These systems can feed a steam distribution system that can supply various industrial facilities such as the heating of distillation column reboilers.
The drawback of such a method is that the temperature of the hot gases is insufficient to heat industrial facilities operating at relatively high temperatures, for example greater than 500° C.
Moreover, direct utilization of the hot gases leaving the gas turbine is difficult since the pressure loss at the outlet of the gas turbine must remain very low, since these gases are leaving at a pressure close to atmospheric pressure and any pressure loss, even a relatively small loss, greatly interferes with gas turbine performance.
The proposal has also been made of using such hot combustion gases, as better described for example in French Patent Application No. 2,825,995 or in French Patent Application No. 2,675,498 by the applicant, to ensure reforming of a gas feedstock, but the drawback is that when the hot gases are sent to the turbine after heat exchange, they have given off heat and are substantially cooled. This being the case, the mechanical power produced by the turbine is significantly less. Moreover, the initial dimensions of the turbine and of the blades on an expansion turbine are not adapted to the new conditions under which the pressurized hot gases sent to it/them are admitted.

Cogeneration method and device using a gas turbine comprising a post-combustion chamber


A first erase test is performed by applying an erase pulse to series of memory cells which are included in a memory cell array and which are divided into a plurality of groups until the appearance of a group for which the determination that erase is completed is made. A second erase test is performed on other series of memory cells including the series of memory cells on the basis of the number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first.

The following sampling erase test is proposed as a semiconductor memory erase test. In this sampling erase test, the number of erase pulses by which erase is completed for a part of memory cells in a memory cell array is found and erase is performed in a remaining area on the basis of the number of erase pulses.
The following erase test method is proposed as an EEPROM (Electrically Erasable Programmable Read-Only Memory) erase test method. In this erase test method, an erase test is repeated in a part of a storage area until the determination that erase is performed normally is made, the width of an erase pulse is set on the basis of the number of repetitions, and an erase test is performed in a remaining large part of the storage area by the use of the pulse width.    Japanese Laid-open Patent Publication No. 08-31189    Japanese Laid-open Patent Publication No. 2000-207897    Japanese Laid-open Patent Publication No. 2001-273792
It is assumed that the number or width of erase pulses obtained by performing an erase test in a part of a storage area is considered as a verification threshold at the time of performing verification in a remaining part of the storage area. If erase is completed for a memory cell before this verification threshold is reached, then the determination that the memory cell is normal is made.
There may be a memory cell in a part of a storage area which needs a long time for erase, compared with the other memory cells. In this case, the number or width of erase pulses obtained is influenced by the memory cell. As a result, a verification threshold becomes high and a verification standard is relaxed at the time of performing verification in a remaining part of the storage area. In this case, a memory cell which is originally bad cannot be detected and the reliability of a semiconductor memory decreases.

Semiconductor memory test method and semiconductor memory


A matrix arithmetic circuit includes an address generator, a first multiplier, a second multiplier, and an accumulator. The address generator generates addresses of first, second, and third memories to read out matrix elements from the first, second, and third memories at predetermined timings. The first multiplier multiplies the first and second matrices. The second multiplier multiplies the multiplication result from the first multiplier and the third matrix. The accumulator accumulates the multiplication result from the second multiplier to obtain an arithmetic result.

The present invention relates to an arithmetic circuit and, more particularly, to an arithmetic circuit for executing matrix multiplication.
FIG. 3 shows a conventional arithmetic circuit for consecutively executing matrix multiplication twice. Output ports DO of first and second memories 13 and 14 in which matrices X and Y are respectively stored are respectively connected to first and second input ports IA and IB of a first multiplier 9. An output port DO of a third memory 15 in which a matrix Z is stored is connected to a first input port IA of a second multiplier 11. Output ports Al, A2, A3, and A4 of an address generator 17 are respectively connected to address input ports A1 of the fourth, second, first, and third memories 16, 14, 13, and 15. An output port OZ of the first multiplier 9 is connected to an input port IX of a first accumulator 10. An output port OY of the first accumulator 10 is connected to an input port DI of the fourth memory 16. An output port Do of the fourth memory 16 is connected to a second input port IB of the second multiplier 11. An output port OZ of the second multiplier 11 is connected to an input port IX of a second accumulator 12. An output OY of the second accumulator 12 is connected to an output terminal 18.
Such an arithmetic circuit is designed to perform multiplication based on the matrices X, Y, and Z in the following manner. Elements of the matrices X and Y are respectively read out from the first and second memories 13 and 14, and a multiplication of X.times.Y is performed by using the first multiplier 9 and the first accumulator 10. The product of X.times.Y is then written in the fourth memory 16. In addition, an element of the matrix Z and elements of the product of X.times.Y are respectively read out from the third and fourth memories 15 and 16, and a multiplication of (X.times.Y).times.Z is performed by the second multiplier 11 and the second accumulator 12, thus executing matrix multiplication twice. This calculation method will be described in detail below.
Assume that the matrices X, Y, and Z are N.times.N matrices and are respectively constituted by elements given by following equations (1) to (3): ##EQU1##
In this case, each matrix element as a matrix multiplication result is represented by equation (4): ##EQU2## where (n-1).gtoreq.l and m (integer).gtoreq.0.
If the product of X.times.Y is X', the second multiplication is: ##EQU3##
In the prior art, two consecutive matrix multiplications are performed by independently operating equations (4) and (5). The arithmetic circuit is designed to perform such calculations in the following manner. The calculation result of equation (4) obtained by the first multiplier 9 and the first accumulator 10 is temporarily stored in the fourth memory 16. Thereafter, the calculation result of equation (4) read out from the fourth memory 16 and the matrix Z read out from the third memory 15 are operated on the basis of equation (5).
In the above-described conventional arithmetic circuit, however, since two matrix multiplications are independently executed, a memory for storing an intermediate product of (X.times.Y) is required. In addition, since multipliers and accumulators are required in pairs, the number of elements and power consumption are increased. Therefore, in a semiconductor IC, the chip area is undesirably increased. Furthermore, unless calculation of a matrix element of the first matrix multiplication (X.times.Y) is completed, the second multiplication cannot be started, the operation time is undesirably prolonged.


The present disclosure provides methods and systems for automatically controlling power supply from an electrical power supply system to a user location based on payment status. The method performed by a central control unit includes determining a payment status of the electrical power supply system at the user location. The payment status is determined based at least on a time credit associated with the electrical power supply system. The method further includes facilitating control of the power supply from the electrical power supply system to the user location based on determining the time credit. The power supply to the user location from the electrical power supply system is uninterrupted, if the time credit is greater than a predefined threshold value. The power supply to the user location from the electrical power supply system is disconnected, if the time credit is less than the predefined threshold value.

Alternating current (AC) supply is used for powering electrical appliances at a customer location. The AC supply is generally received from the electrical utilities which provide electricity supply to the customer and/or user locations. In some cases, the user locations may be equipped with independently managed local power source or renewable energy resources (such as solar energy by employing photovoltaic (PV) panels) which is used as an auxiliary power source at the user locations. The use of the local power source leads to less dependence on the electrical energy supplied by the electrical service providers or electrical utilities. Further, the use of local power source for generating electricity at the user locations also reduces billing amount owed to the user.
However, purchasing and installation cost of the local power source at the user location is high which prevents the users with mid-to-low income to afford the local power source for generating electricity at the user locations. In other words, the mid-to-low income group users may not be able to pay the full amount at one instance to purchase and install the local power source. Further, countries with electricity supply concerns lack financial systems that provide loans for purchasing appliances to mid-to-low income residential and commercial users. Also, they do not include feasible provisions for an upfront payment to purchase standalone systems or the local power source to power appliances that require AC supply to operate. To overcome this problem, the mid-to-low income residential or commercial users may be provided with financial support by lending them loans to purchase the local power source. However, even after such assistance, the users may be delinquent in paying the loan amount associated with the purchase of the local power source. Thus, the collection of loan amount from the users is a cumbersome process and remains a practical challenge. Hence, it is important to devise means for encouraging users to make payments who have been provided financial assistance in deployment of the local independent power source and who are delinquent in paying the loan amount against such deployment and/or any other defined payment terms related to the deployment or consumption of the electrical supply generated from the local power source.
Therefore, there is a need for techniques that can overcome one or more limitations stated above in addition to providing other technical advantages.

Method and system for automatically controlling electrical power supply based on payment status


A filtering apparatus calculates a median of image data that includes nine pixel values arranged in a window of 3*3. First, an input circuit receives as an input the image data, divides the data into groups each having three pixels, and outputs. The pixel values of each group are sorted in accordance with magnitude order, by a plurality of sorters. After sorting, the maximum values among the pixel values of the groups are determined by a plurality of shifters and a plurality of maximum value determiners, and the determined pixel values are removed from the corresponding groups. As a result, four largest pixel values are removed from the three groups. A last sorter extracts and outputs the maximum pixel value (median) from the remaining five pixel values.

1. Field of the Invention
The present invention relates to a filtering apparatus for filtering digital signals, a data driven type information processing apparatus, a filtering method, a filtering program and a machine-readable recording medium having the filtering program recorded thereon. More specifically, the present invention relates to a filtering apparatus for filtering digital signals, a data driven type information processing apparatus, a filtering method, a filtering program and a machine-readable recording medium having the filtering program recorded thereon, for median filtering that removes noise from noisy image data.
2. Description of the Background Art
In image related fields, median filtering process as a method of removing noise from an input image is an important function, an d higher speed of the filtering process is strongly desired.
In the median filtering process, for each pixel of the input image, a window (local area) having the size of K×L with the pixel of interest being at the center is considered, and a central value (median) of luminance data (hereinafter referred to as a pixel value) of K×L pixels is provided as the pixel value of each pixel in of the output image.
Conventionally, in the median filtering process using a 3×3 window, nine pixel values in the window are sorted and the central value of these pixels is calculated.
FIG. 15 shows an exemplary configuration of a conventional median filtering apparatus. The median filtering apparatus shown in FIG. 15 includes sorting circuits 801 to 803, 805, 806, 808, 809 and 811 sorting the input data in ascending or descending order and outputting the result, selectors 804, 807 and 810, maximum value determiners 812 to 814, and minimum value determiners 815 to 817.
An operation of the median filtering apparatus shown in FIG. 15 will be described, taking an example in which a central value of nine pixel values A0 to A2, B0 to B2 and C0 to C2 in a window having the size of 3×3 is calculated.
First, nine pixel values A0 to A2, B0 to B2 and C0 to C2 are divided in advance into three groups G1 to G3 each having three pixel values, and the groups G1 to G3 are input to sorting circuits 801 to 803, respectively.
Sorting circuits 801 to 803 each sorts the three pixel values of the group input thereto and outputs the result of sorting to selector 804. The maximum pixel value represented by the result of sorting is output to maximum value determiner 812, and the minimum value represented by the result of sorting is output to minimum value determiner 815.
Maximum value determiner 812 receives as inputs the maximum pixel values of groups G1 to G3, compares the input pixel values with each other, determines the largest pixel value among the input pixel values, and outputs the result of determination to selector 804. Minimum value determiner 815 receives as inputs the minimum pixel values of groups G1 to G3, compares the input pixel values with each other, determines the smallest pixel value among the input pixel values, and outputs the result of determination to selector 804.
Selector 804 receives as inputs nine pixel values as the result of sorting from sorting circuits 801 to 803, removes therefrom the largest and smallest pixel values represented by the results of determination received from maximum value determiner 812 and minimum value determiner 815, and outputs the result. By this operation, two pixel values are removed from the input nine pixel values, and hence, seven pixel values are output.
Then, selector 804 divides the seven pixel values into three groups having three pixels, three pixels and one pixel, respectively, and outputs these groups. Specifically, the groups consisting of three pixels are output to sorting circuits 805 and 806, respectively, and group 818 consisting of one pixel is output to selector 807, maximum value determiner 813 and minimum value determiner 816. Sorting circuits 805 and 806 sort the pixel values of the input groups respectively, and output the results of sorting to selector 807. The maximum pixel values and the minimum pixel values as represented by the results of sorting are output to maximum value determiner 813 and to minimum value determiner 816, respectively.
Maximum value determiner 813 receives the three pixel values input thereto, compares the input pixel values with each other, determines the largest pixel value among the input pixel values, and outputs the result of determination to selector 807. Minimum value determiner 816 receives the pixel values input thereto, compares the input pixel values with each other, determines the smallest pixel value among the input pixel values, and outputs the result of determination to selector 807.
Selector 807 receives as inputs six pixel values as the result of sorting from sorting circuits 805 and 806 and receives one pixel value of group 818, removes therefrom the largest pixel value and the smallest pixel value represented by the results of determination given from maximum value determiner 813 and minimum value determiner 816, and outputs the result. By this operation, two pixel values are removed from input seven pixel values, and hence, five pixel values are output.
Thereafter, selector 807 divides the five pixel values into a group consisting of three pixel values and a group consisting of two pixel values, and outputs the group consisting of three pixel values to sorting circuit 808 and outputs the group consisting of two pixel values to sorting circuit 809. Sorting circuits 808 and 809 sort the pixel values of the input groups, respectively, output the result of sorting to selector 810, output the maximum pixel values and minimum pixel values as represented by the results of sorting to maximum value determiner 814 and minimum value determiner 817, respectively.
Maximum value determiner 814 compares input pixel values with each other, determines the largest pixel value among the input pixel values, and outputs the result of determination to selector 810. Minimum value determiner 817 compares input pixel values with each other, determines the smallest pixel value among the input pixel values, and outputs the result of determination to selector 810.
Selector 810 receives as inputs five pixel values as the results of sorting from sorting circuits 808 and 809, removes therefrom the largest and smallest pixel values as represented by the results of determination by maximum value determiner 814 and minimum value determiner 817, and outputs the result to sorting circuit 811. By this operation, two pixel values are removed from the input five pixel values, and hence three pixel values are output.
Sorting circuit 811 sorts the three pixel values input from selector 810, and outputs the pixel value at the center of the series of pixel values given as the result of sorting as the median.
In the above described median filtering process, in order to calculate the central value of nine input pixel values, the input pixel values are divided into three groups each consisting of three pixel values and sorting process is performed in each group, and the largest and smallest two pixel values are removed by a selector in accordance with the result of sorting, so as to reduce the number of pixel values as the object of processing. This process is repeated to reduce two by two the number of pixel values as the object of processing, and the central value is eventually obtained. Here, sorting is necessary every time the largest and smallest values are to be removed, and in the example shown in FIG. 15, eight sorting circuits are necessary. Further, three maximum value determiners and three minimum value determiners are necessary. As the sorting circuits, maximum value determiner and minimum value determiner employ comparators, a total of 36 comparators are necessary in the circuitry of FIG. 15 as a whole. Consequently, the circuit scale of the median filtering apparatus becomes large, and the number of pipelines increases when the median filtering process using such a median filtering apparatus is executed along with pipeline processing. Accordingly, it has been difficult to realize high-speed median filtering process.
A filtering apparatus described in Japanese Patent Laying-Open No. 6-61788 includes a register file, which has a plurality of registers and has data, constants and initial values read and written in accordance with the single write and single read rule, and a group of operators having a multiplier and an addition-shift combined operator. Therefore, a basic filtering operation in FIR filtering process and IIR filtering process can be represented as a minimum instruction unit, and the filtering process can be executed at high speed.
Further, the number of entries of the register file corresponds to the number of taps, and therefore, the number of entries can be set by a program, and a filter of an arbitrary configuration can easily be implemented.
This configuration, however, can cope with the FIR and IIR filters only, and only a program-based solution is available to realize the median filtering process.

Apparatus and method of filtering digital information


An injector needle/armature assembly stroke is controlled so as to minimize opening and closing impact forces. The controlled motion eliminates or significantly reduces the problems associated with valve bounce, providing less acoustic emission, reduced wear, improved spray characteristics and better flow regulation. The current applied to the electromagnetic coil of the injector in accordance with a modified injector timing pulse waveform serves to reduce impact velocities at each end of the armature stroke. The waveform can be optimized for a class of injectors with a pulse width modulated waveform, repeatedly re-energizing and de-energizing the electromagnetic coil in accordance with an optimized on/off pulse train.

The present invention relates to fuel injectors and, in particular, to a method and apparatus for controlling an injector needle stroke to minimize opening and closing impact forces.
An electromagnetic fuel injector utilizes a solenoid assembly to supply an actuating force to a fuel metering valve. Typically, a plunger style armature supporting a fuel injector needle reciprocates between a closed position, where the needle is closed to prevent fuel from escaping through the discharge orifice, and a fully open position, where fuel is discharged through the discharge orifice.
When the solenoid is energized, the solenoid armature, and thus the injector needle, is magnetically drawn from the closed position toward the fully open position by a solenoid generated magnetic flux. Typically, the solenoid is energized until the armature reaches its fully opened position and a period of time thereafter to discharge a desired amount of fuel. As the armature reaches the top of its stroke, it impacts an armature stop generating impact noise and resulting in the armature bouncing against the armature stop. This bouncing has detrimental effects on flow characteristics of the fuel.
When an appropriate amount of fuel has been discharged from the injector, the solenoid is de-energized, and the armature and injector needle are urged toward the closed position by the force of a spring. Similar to the top of the armature stroke, when the armature reaches the bottom of its stroke and the injector needle is seated to close the discharge orifice, the velocity of the injector needle generates impact noise against the seat and is subject to significant bouncing. The occurrence of such bouncing will typically result in an extra amount of unscheduled fuel being injected from the fuel injector into the engine, and this extra fuel can have an adverse effect on fuel economy and engine exhaust constituents.
Various means for eliminating such bouncing have been proposed, including those found in commonly assigned U.S. Pat. Nos. 4,878,650, 5,033,716 and 5,139,224.

Armature motion control method and apparatus for a fuel injector


Systems and methods for the execution and operation of compute instances and tasks to perform batch jobs on behalf of customers of a computing resource service provider. Batch jobs can be subdivided into job fragments that can be concurrently executed by compute resources instantiated by the computing resource service provider. The computing resource service provider utilizes control mechanisms in the form of a maximum concurrent job fragment thresholds to mitigate the potential impact of resource constraints associated with larger batch jobs.

Generally described, computing devices utilize a communication network, or a series of communication networks, to exchange data. Companies and organizations operate computer networks that interconnect a number of computing devices to support operations or provide services to third parties. The computing systems can be located in a single geographic location or located in multiple, distinct geographic locations (e.g., interconnected via private or public communication networks). Specifically, data centers or data processing centers, herein generally referred to as "data centers," may include a number of interconnected computing systems to provide computing resources to users of the data center. The data centers may be private data centers operated on behalf of an organization or public data centers operated on behalf, or for the benefit of, the general public.
To facilitate increased utilization of data center resources, virtualization technologies allow a single physical computing device to host one or more instances of virtual machines that appear and operate as independent computing devices to users of a data center. With virtualization, the single physical computing device can create, maintain, delete, or otherwise manage virtual machines in a dynamic manner. In turn, users can request computer resources from a data center, including single computing devices or a configuration of networked computing devices, and be provided with varying numbers of virtual machine resources.
To further facilitate increased utilization, compute instances are often configurable to meet various computing needs of the customers of the computing resource service provider and can be rapidly deployed to perform various tasks in support of these computing needs. However, compute instances are often used for short-lived transient jobs and can only be instantiated for a limited time before terminating. Thus, it can be difficult for a customer to execute large batch jobs quickly and reliably using compute instances. Relying on remote program execution over multiple virtual machine instances and remote data storage may be difficult, as customer are required to manage various applications running on multiple virtual machine instances. Further, such applications may not be portable to other computing systems or scalable to meet an increased need for resources.

Batch job execution using compute instances


A package delivery system can be implemented to forcefully propel a package from an unmanned aerial vehicle (UAV), while the UAV is in motion. The UAV can apply a force onto the package that alters its descent trajectory from a parabolic path to a vertical descent path. The package delivery system can apply the force onto the package in a number of different ways. For example, pneumatic actuators, electromagnets, spring coils, and parachutes can generate the force that establishes the vertical descent path of the package. Further, the package delivery system can also monitor the package during its vertical descent. The package can be equipped with one or more control surfaces. Instructions can be transmitted from the UAV via an RF module that cause the one or more controls surfaces to alter the vertical descent path of the package to avoid obstructions or to regain a stable orientation.

Historically, package delivery systems rely on a spoke-hub distribution model. For example, to ship a package between an origin and destination, a vehicle has to pick-up the parcel and deliver it to a sorting center before commencing a final delivery destination. This model works well for reducing the cost of shipment when it is possible to aggregate packages that share a big part of the journey from origin to destination. However, it becomes inefficient, if the ability to aggregate packages is diminished because of a lack of proximity between delivery destinations. Further inefficiencies are apparent when transportation infrastructure itself does not allow for direct routes between an origin and destination.
The use of Unmanned Aerial Vehicles (UAV) can overcome some of these inefficiencies by leveraging more flexible aerial transportation paths between destinations, rather than relying on rigid road infrastructure. Flexible flight plans allow for more direct delivery routes, and in some cases, an aggregation of more packages that share delivery destinations that are in close proximity to one another. However, the use of UAVs presents their own inefficiencies. In order to deliver a package to a destination, a UAV is required to 'drop off' the package. Traditionally, this involves the UAV landing at the destination, releasing the package, and then taking off to its next destination. The sequence of landing and taking off for each package delivery creates time and energy resource inefficiencies, which negate at least a portion of the benefit of adopting a network system of UAVs.

Maneuvering a package following in-flight release from an unmanned aerial vehicle (UAV)


When a lever (48) is rocked either rightwardly or leftwardly while the lever (48) is rocked forwardly and the vehicle is moving forwardly, the vehicle is steered in the direction in which lever (48) is rocked. When the lever (48) is rocked either rightwardly or leftwardly while the lever (48) is rocked backwardly and the vehicle is moving backwardly, the vehicle is steered in the direction in which lever (48) is rocked. For the above operation, a valve body (44) comprising a pilot valve (420) and a change valve (421) is coupled to the lever (48). The lever (48) is rocked rightwardly or leftwardly, and pressure oil supplied through the pilot valve (420) actuates a rotary direction changing valve (25). When the lever (48) is rocked backwardly, the change valve (421) switches the direction in which the pressure oil is supplied through the pilot valve (420) to the reverse direction.

A crawler type Vehicle is disclosed in Japanese Published Unexamined Patent Application No. 59-501501. This vehicle is equipped with a planetary steering differential device and uses a single steering lever device to control rightward/leftward and forward/backward steering of the vehicle.
The known single steering lever device comprises a grip and an upright pivotal movement supporting portion. The grip is grasped by the operator's palm and tilted upwardly, and has a device for transmitting torsional rotary motion. The upright pivotal movement supporting portion has a device for transmitting pivotal movement, which supports the grip so that it can rock on a fixed upright axis within a lateral plane. The former torsional rotary motion transmitting device is coupled through a mechanical link to a forward/backward change valve of a speed change gear so that the crawler type vehicle is driven forwardly or backwardly or is in neutral. The latter pivotal movement transmitting device is coupled through the mechanical link to a change valve. The change valve changes the direction in which a steering hydraulic motor rotates. The steering hydraulic motor inputs rotary power of differential steering to the planetary steering differential device. The crawler type vehicle can be driven straight or pivoted rightwardly/leftwardly.
Steering the vehicle using the former device is easy since the desired movement of the vehicle is obtained by rotating the operator's wrist in the direction in which the vehicle is to move, that is, when the grip is moved forwardly while the grip is being rotated, the vehicle moves forwardly, whereas when the grip is moved backwardly while the grip is being rotated, the vehicle moves backwardly. However, pivoting the vehicle using the latter device has a disadvantage.
That is, even when the grip is rocked backwardly and then is rocked rightwardly or leftwardly for pivoting the vehicle, the rocking direction does not agree with the pivoting direction. The problem of the conventional art is that the vehicle does not pivot in the direction in which the lever is rocked.


A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input node and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

1. Field of the Invention
This invention relates to the field of fingerprint image sensing and detection; i.e., to the detection of a fingerprint""s minutiae such as ridge endings and bifurcations. More specifically, this invention relates to a multipixel, capacitance type fingerprint sensor.
2. Description of the Related Art
As is well known, the fingerprint of a human is composed of lines or ridges, which have both branching parts or bifurcations and abrupt endings or end points. These branching parts, bifurcations, endings, and end points are also known as minutiae. Fingerprints are identified by the locations of, and the relationships among, these minutiae.
The present invention relates to an improved capacitance sensor that operates to sense or detect fingerprint minutiae. The use of capacitance type sensors is generally known.
For example, the publication SENSORS AND ACTUATORS, January, February 1989, no.1/2, at pages 141-153, contains an article entitled INTEGRATED TACTILE IMAGER WITH AN INTRINSIC CONTOUR DETECTION OPTION that was presented at the Fourth International Conference on Solid-State Sensors and Actuators (Transducers ""87), Tokyo, Japan, Jun. 2-5, 1987. This article describes an integrated capacitive tactile imaging sensor that comprises a multi-layer construction having a bottom ceramic support, a 9row/9-column array of square aluminum electrodes that are contained on a silicon wafer integrated circuit, a flexible and isolating intermediate layer that is made up of natural rubber, a thin conductive rubber layer, and a top protective layer. In this device, capacitance depends upon local deformation of the natural rubber layer. The 81 individual aluminum electrodes of this device provide capacitive measurement of an indentation pattern within the natural rubber layer, this indentation being caused by a pressure distribution that acts on the top protective layer.
The use of a capacitance type sensor to sense the minutiae of a human fingerprint is also known.
For example, the publication IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 1, JANUARY 1997, pages 19-20, contains an article entitled NOVEL FINGERPRINT SCANNING ARRAYS USING POLYSILICON TFT""S OF GLASS AND POLYMER SUBSTRATES. This article describes a two-dimensional (2-D), 200xc3x97200, capacitance sensing array that is made up of 40,000 individual pixels. Each pixel of the array includes two thin film transistors (TFTs) and a capacitor plate. Each array pixel resides at the intersection of an array-row and an array-column, and each array pixel is individually addressable by way of row-driver circuits and column-driver circuits.
Considering the two TFTs, hereinafter called TFT-A and TFT-B, that are associated with a given pixel, the drain electrodes of TFT-A and TFT-B are connected to the pixel""s capacitor plate, the gate electrode and the source electrode of TFT-A are connected to a row-conductor that is associated with the pixel, the gate of TFT-B is connected to the following row-conductor, and the source of TFT-B is connected to a column-conductor that is associated with the pixel.
A thin (0.1 micrometer) silicon nitride insulator overlies the capacitor plate of each array pixel. When the ridge of a fingerprint lies directly over the capacitor plate, a capacitor is formed between the capacitor plate and the finger. This capacitor is charged when a row-pulse (8 to 10 VDC, and of 10 to 100 micro second duration) is applied to the pixel by way of the row-conductor that is associated with this pixel and TFT-A. This stored charge is thereafter transferred onto the pixel""s column-conductor through TFT-B when a row-pulse is applied to the following row-electrode.
Also of interest is the publication 1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE that contains an article beginning page 200 entitled A 390DPI LIVE FINGERPRINT IMAGER BASED ON FEEDBACK CAPACITIVE SENSING SCHEME. This article describes a single-chip, 200xc3x97200 element array, 2-metal digital CMOS technology, sensor that is based upon feedback capacitance sensing, and that operates to detect the electrical field variation that is induced by the finger""s skin surface. In each element of the array , two horizontally spaced metal plates are separated from the overlying and adjacent portion of the finger""s skin surface by passivation oxide. Since the distance between the skin and the sensor""s surface identifies the presence of the fingerprint""s ridges and valleys, an array of elements provides a complete fingerprint pattern.
In each element of the array, the two metal plates are respectively connected to the input and the output of a high-gain inverter, to thereby form a charge-integrator. In operation, the charge-integrator is first reset by shorting the input and output of the inverter. A fixed amount of charge is then sinked from the input, causing the output voltage to swing inversely proportional to a feedback capacitance value that is inversely proportional to the distance to the fingerprint""s ridges and valleys. The array of cells, or sensors, thus provides the complete fingerprint pattern. The fingerprint image disappears when the finger is removed from the array.
U.S. Pat. No. 4,353,056, incorporated herein by reference, is of interest in that it relates to a capacitance type fingerprint sensor wherein a finger is pressed onto the sensor""s surface in order to read the ridges and valleys of the fingerprint. The sensor-surface has a large number of capacitors of a small physical size associated therewith. Two sensors are described. In a first type of sensor, an electrical insulator carries a number of flexible and horizontally spaced curved metal electrodes, two adjacent metal electrodes of which comprise one capacitor. A protective insulating film overlies the electrical insulator, and when a finger is brought into physical contact with this protective insulating film, the metal electrodes are physically deformed, thereby selectively changing the capacitance of the large number of capacitors in accordance with the fingerprint""s ridge/valley pattern. In a second type of sensor, the top surface of a rigid support carries a number of horizontally spaced and flat metal electrodes in a fixed position. Placed above the plane of the metal electrodes is the sequential arrangement of a flexible insulator, a flexible electrode, and a flexible protective membrane. A capacitor is formed between the top flexible electrode and each of the lower and fixed-position flat metal electrodes. When the end of a finger is brought into contact with the flexible membrane, the flexible electrode becomes wavy in accordance with the fingerprints""ridges/valleys pattern.
In addition, U.S. Pat. No.5,325,442, incorporated herein by reference, relates to a capacitance type fingerprint sensor having a sensing pad that comprises a planar array of row/column sensing elements having a pitch of about 100 micrometers. Each sensing element is located at the intersection of a row conductor and a column conductor. A plurality of these sensing elements make up an array of regularly spaced, and relatively equal, size rectangles.
Each sensing element of this patent includes a first ungrounded, physically buried, and planar metal capacitor plate that is dielectric-spaced from an electrically grounded finger surface that forms a second capacitor plate, as shown in the circuit of this patent""s FIG. 2. In FIG. 7a-7b of this patent, the finger-engaging surface includes exposed and grounded metal film conductors 53 that physically engage the finger to ensure operation of the FIG. 2 circuit by reliably grounding the finger, to thereby reliably ground the above-described second capacitor plate.
The sensing elements are fabricated using photolithographic processes, and each individual sensing element includes a Thin-Film-Transistor (TFT) in the form of a Field-Effect-Transistor (FET). Each FET gate is connected to a row conductor, each FET source is connected to a column conductor, and each FET drain is connected to a sensing electrode.
In one embodiment, each sensing element comprises a sensing capacitor that is formed between a sensing electrode and the finger. In another embodiment, each sensing element includes an electrically isolated and conducting pad that is physically engaged and electrically grounded by the finger.
While prior devices, as above described, are generally useful for their limited intended use, a need remains in the art for a capacitance type fingerprint sensor wherein the fingerprint pattern of an ungrounded fingertip is sensed, and wherein the construction and arrangement of the sensor minimizes, or prevents, an electrostatic charge that may be carried by a human body from disturbing the operation of a capacitance type fingerprint sensor.
As is well known, a capacitive sensor array of the general type that finds utility in fingerprint pattern recognition/detection systems includes a generally planar array of many row/column arranged and individual capacitive sensing cells, wherein each individual sensing cell comprises one pixel of the array.
In a type of sensor array with which this invention finds utility, each sensing cell generally includes one or more generally topmost-level, dielectric-covered, and ungrounded metal capacitor plates. An ungrounded fingertip that forms another capacitor plate is placed on the top dielectric surface of the array, and cells that are physically contacted by a fingerprint ridge experience increased capacitance, as compared to those cells that are spaced a short distance below a fingerprint valley.
The present invention finds utility with a construction and arrangement wherein each such cell includes an amplifier circuit whose output/input are feedback-interconnected by a compound-capacitor circuit that is made up of the ungrounded one or more generally topmost-level and dielectric-covered metal capacitor plates, and the ungrounded fingertip that forms another capacitor plate.
In this particular type of ungrounded output/input feedback circuit configuration, the electrostatic charge that is sometimes carried by a human body may be sufficiently high to break through the sensor""s upper-most passivation layer or dielectric layer that covers all cells, and/or to exceed the gate oxide breakdown voltage of a sensing circuit that is connected to the one or more dielectric-covered metal capacitor plates.
The present invention improves the electrostatic discharge (ESD) performance of such a capacitive sensor array by physically surrounding, but not physically contacting, each individual dielectric-covered capacitor plate with a metal-grid-work, metal-mesh-lines, or a metal-pattern, that is connected directly to system ground potential.
Examples of such a grounded metal-pattern include, but are not limited to, a metal-pattern that occupies generally the same horizontal plane as the capacitor plate(s) to be protected from electrostatic charge, a metal-pattern that occupies a generally horizontal plane that is located vertically above the horizontal plane occupied by the capacitor plate(s) to be protected from electrostatic charge, a metal-pattern that occupies a generally horizontal plane that is located vertically below the horizontal plane occupied by the capacitor plate(s) to be protected from electrostatic charge, and a metal-pattern that occupies a horizontal plane that is located vertically below the horizontal plane occupied by the capacitor plate(s) to be protected from electrostatic charge and includes a plurality of metal fingers that extend vertically upward to generally surround the capacitor plate(s). In the spirit of this latter example, grounded metal-patterns within the spirit and scope of this invention need not be physically continuous grounded metal-patterns.
In accordance with this invention, the grounded ESD protecting metal grid/mesh/pattern may be placed in the same physical dielectric-covered level, or plane, as the above-described one or more metal capacitor plates, or the grounded ESD protecting grid/mesh/pattern may be placed on a somewhat higher physical and dielectric-covered level. It is critical to this invention that the grounded ESD protective grid/mesh/pattern of this invention be physically and electrically isolated from the upper dielectric surface that the fingertip touches. In this way, the fingertip is not undesirably grounded by physical contact with this upper dielectric surface. Grounding of the fingertip is undesirable in this type of capacitance sensing array since a grounded fingertip would also ground a portion of the amplifier""s output/input feedback circuit, thus rendering the amplifier essentially inoperative.
The present invention finds particular utility when the grounded protective grid thereof is provided as a portion of a solid state capacitive sensor for a fingerprint recognition system that includes a periodic array of integrated circuits (ICs) and dielectric-buried capacitor plates; for example, wherein each array pixel includes a signal-inverting circuit whose output and input are respectively connected to one of a pair of generally topmost disposed, dielectric-buried, and generally coplanar metal capacitor plates. In this construction and arrangement, the fingertip that is being subjected to fingerprint pattern sensing/recognition is physically placed on, or very closely adjacent to, a top-most disposed dielectric or passivated surface of the solid state sensing structure. The presence of an ungrounded fingertip skin ridge across a cell""s pair of dielectric-buried coplanar metal plates operates to induce capacitive coupling between the pair of capacitor plates, relative to, for example, and an adjacent cell whose buried capacitor plates cooperate with an ungrounded fingertip skin valley. The entire fingerprint pattern can thus be digitized by sensing the differences in adjacent cell capacitive values.
The ESD immunity of such a solid state array may be relatively poor, since in this type of circuit configuration, it is usual to connect the cell""s buried and ungrounded capacitor plates to transistor gates and/or to connect the cell""s ungrounded and buried capacitor plates to system ground potential by way of reverse biased diodes. In this type of construction and arrangement, the electrostatic charge sometimes carried by a human body and its fingertip, which may be in the range of several kilo volts (kV), may be sufficiently high to break through the solid state cell""s upper dielectric/passivation layer, and thus raise the potential at ungrounded circuit nodes that are associated with the buried capacitor plates so as to exceed the gate oxide breakdown voltage of the transistor gates that are connected to these capacitor plates. In addition, if the fingertip""s electrostatic induced voltage buildup across the above mentioned ground connecting diodes exceeds the oxide breakdown voltage, the gate oxide can be ruptured, thus damaging the associated array cell.
In order to improve the ESD immunity of such a solid state array, the present invention operates to surround each capacitor plate with a grid, or mesh of metal lines, that are connected directly to system ground potential. In accordance with this invention, this new and unusual grounded grid/mesh of metal lines may be placed, buried, or routed in the same horizontal plane as that occupied by the capacitor plates, or the grid/mesh of metal lines may be placed, buried, or routed in a higher horizontal plane than the plane occupied by the buried capacitor plates. In this second case, the grid/mesh of metal lines occupies a plane that is physically closer to, but remains dielectric-isolated from, the fingertip than is the plane of the buried capacitor plates.
An object of this invention is to provide electrostatic discharge protection for a capacitive type fingerprint pattern sensing array that has a number of individual skin-distance sensing cells that are arranged in a closely spaced physical configuration, wherein the array includes a dielectric layer having an upper surface on which an ungrounded fingertip having a fingerprint pattern is placed. Each sensing cell includes an amplifier having an ungrounded input mode, an ungrounded output node, and ungrounded output-mode-to-input-node negative feedback circuit. This negative feedback circuit includes the capacitive effect of a fingertip of the upper surface of the dielectric layer, and this negative feedback is therefore sensitive to the fingertip""s unique fingerprint pattern. More specifically, this negative feedback is provided by the series electric effect of (1) a first capacitor plate that is located or buried vertically under the upper surface of the dielectric layer and connected to the ungrounded input node, (2) a second capacitor plate that is located, or buried, vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and connected to the ungrounded output node, and (3) the ungrounded fingertip that is placed in vertical spatial relation with the first and second capacitor plates. Continuous, or discontinuous, grounded metal paths are now provided vertically under the upper surface of the dielectric layer, or buried within the dielectric layer, to thereby spatially surround the first and second capacitor plates in an electrical sense. This metal path is connected to ground potential, to thereby protect the input and output nodes from electrostatic potential that may be carried by the fingertip, and in a manner that does not disturb the ungrounded state of the fingertip.
These and other objects, features and advantages of this invention will be apparent to those of skill in the art upon reference to the following detailed description of preferred embodiments thereof, which description makes reference to the drawing.

Electrostatic discharge protection of a capacitve type fingerprint sensing array


An MMR system for publishing comprises a plurality of mobile devices, an MMR gateway, an MMR matching unit and an MMR publisher integrated into a network with an advertiser, an ad broker, and an MMR service bureau. The MMR matching unit receives an image query from the MMR gateway and sends it to one or more of the recognition units to identify a result including a document, the page and the location on the page. The MMR service bureau uses the result to retrieve advertising or other links associated with the location on the page. The list of results and links are sent back to the MMR gateway for presentation on the mobile device. The present invention also includes a number of novel methods including a differentially weighting links associated with an MMR document.

1. Field of the Invention
The invention relates to techniques for creating a mixed media document that is formed from at least two media types, and more particularly, to registering an image and other data in a Mixed Media Reality (MMR) system that uses printed media in combination with electronic media to retrieve mixed media documents and associated advertisements.
2. Background of the Invention
Document printing and copying technology has been used for many years in many contexts. By way of example, printers and copiers are used in commercial office environments, in home environments with personal computers, and in document printing and publishing service environments. However, printing and copying technology has not been thought of previously as a means to bridge the gap between static printed media (i.e., paper documents), and the "virtual world" of interactivity that includes the likes of digital communication, networking, information provision, advertising, entertainment and electronic commerce.
Printed media has been the primary source of communicating information, such as newspapers and advertising information, for centuries. The advent and ever-increasing popularity of personal computers and personal electronic devices, such as personal digital assistant (PDA) devices and cellular telephones (e.g., cellular camera phones), over the past few years has expanded the concept of printed media by making it available in an electronically readable and searchable form and by introducing interactive multimedia capabilities, which are unparalleled by traditional printed media.
Unfortunately, a gap exists between the electronic multimedia-based world that is accessible electronically and the physical world of print media. For example, although almost everyone in the developed world has access to printed media and to electronic information on a daily basis, users of printed media and of personal electronic devices do not possess the tools and technology required to form a link between the two (i.e., for facilitating a mixed media document).
Moreover, there are particular advantageous attributes that conventional printed media provides such as tactile feel, no power requirements, and permanency for organization and storage, which are not provided with virtual or digital media. Likewise, there are particular advantageous attributes that conventional digital media provides such as portability (e.g., carried in storage of cell phone or laptop) and ease of transmission (e.g., email).
One particular problem is that a publisher cannot allow access to electronic versions of content using printed versions of the content. For example, for the publisher of a newspaper there is no mechanism that allows its users who receive the printed newspaper on a daily basis to use images of the newspaper to access the same online electronic content as well as augmented content. Moreover, while the publisher typically has the content for the daily newspaper in electronic form prior to printing, there currently does not exist a mechanism to easily migrate that content into an electronic form with augmented content.
A second problem is that the above difficulties have led to further difficulties associated with advertising linked to electronic media and defining when and how to display such advertising.
For these reasons, a need exists for techniques, methods and systems that enable the use of mixed media reality systems in the area of mass media printed publishing.

Mixed media reality retrieval of differentially-weighted links


A semiconductor laser including a semiconductor substrate, a back reflection layer formed over the semiconductor substrate, a first clad layer formed over the back reflection layer, an active layer formed over the first clad layer, the active layer having a width smaller than that of the first clad layer, and a second clad layer formed over the active layer. The second clad layer has a flat upper surface and a width identical to that of the first clad layer. A front reflection layer is formed over the second clad layer. The semiconductor laser also includes impurity diffusion regions of a first conductivity type and a second conductivity type. The impurity diffusion regions extend from the upper surface of the second clad layer to predetermined depth portions of the first clad layer and are in contact with opposite side portions of the active region, respectively. First and second electrodes adapted to oscillate laser beams are formed over the first and second conductivity type impurity diffusion regions. A third electrode adapted to discharge laser beams and a fourth electrode adapted to discharge laser beams are formed over the front reflection layer and beneath the bottom surface of the semiconductor substrate, respectively.

1. Field of the Invention
The present invention relates to a semiconductor laser and a method for manufacturing the same.
2. Description of the Prior Art
Semiconductor lasers have been highlighted as a light emitting source for optical fiber communication and optical information processing since continuous oscillation at room temperature of GaAlAs based semiconductor lasers was reported in 1970. It is not too much to say that such semiconductor lasers have been developed according to technical requirements in optical fiber communication.
Following the development of GaAlAs based semiconductor layers oscillating at a wavelength range of 0.7 .mu.m to 0.9 .mu.m, the development of InGaAsP based semiconductor lasers oscillating at a long wavelength range has been also promoted according to an increase in the minimum loss wavelength of optical fibers, for example, by 1.1 .mu.m to 1.6 .mu.m.
In addition to such semiconductor lasers for communication, on the other hand, another type of semiconductor lasers have been manufactured in mass, which oscillate at 0.7 .mu.m, for processing optical information of laser printers, compact discs and video optical discs. Applications of various industrial semiconductor lasers have also extended rapidly.
Semiconductor lasers have a higher efficiency over other types of lasers and achieve modulation at high speed. They are also advantageous by virtue of their very miniature constructions.
The semiconductor lasers can have a wavelength of emitted light selected variously within a wide wavelength range from the wavelength of visible light to the wavelength of far infrared ray. Their life is also assured up to several decades.
Recently, the disadvantage of the semiconductor lasers having poor interference over other types of lasers has been compensated and the optical output of semiconductor lasers is also on an increasing trend. In this regard, the semiconductor lasers are expected to be substituted for gas lasers and solid state lasers in a field involving no requirement of high energy.
Now, the operational principle of the above-mentioned semiconductor lasers will be described and the construction of a conventional semiconductor laser will be also described.
Semiconductor lasers are made of a compound semiconductor such as GaAs or InP which has a direct transition type energy band structure. As voltage is forwardly applied to a P-N junction of such a semiconductor, current flows through the semiconductor. This current flow causes electrons in the N-region and holes in the P-region to flow toward the opposite regions and to be recoupled together and thus emit light.
At a small quantity of current flow, the recoupling of electrons and holes are achieved irregularly. As a result, any induced emission of light required for operating the semiconductor laser is not achieved since occurring optical waves have no correlation with one another. At a large quantity of current flow, an inverted electron distribution is formed near the P-N junction, as shown in FIG. 1. The inverted electron distribution means that more electrons at a lower energy level are distributed, over a higher energy level. At such an inverted electron distribution, light is inducibly emitted by virtue of the electron-hole recoupling. In this case, the region at which the inducible emission of light caused by the inverted electron distribution is called an active region or a gain region.
As a gain larger than a loss of a resonator is generated upon an increase of current applied, the laser is oscillated. The current providing the gain required for oscillating the laser is called a threshold current which is the important dimension for determining the performance of the usable condition of semiconductor laser.
In a semiconductor laser, the resonator for obtaining the oscillation of optical waves uses mainly the crystal sectional surfaces (namely, the surfaces of cleavage) of the semiconductor itself.
A discussion will be now made for an efficient structure capable of reducing the threshold current in the semiconductor laser. If the recoupling of carriers (namely, electrons and holes) is achieved at a region involving no inverted electron distribution, that is, outwardly of a gain region, the light emitted due to the recoupling can not contribute to the inducible emission.
In such a double hetero (DH) structure, an active layer (GaAs) having a small energy gap is interposed between clad layers (GaAlAs) having a large energy gap. A semiconductor laser having such a DH structure is a simple diode in which its one hetero-junction is a P-N junction. As current flows forwardly through the diode, the holes in the N-type clad layer flow into and are then implanted in the active region.
Since the active layer has a small band gap as shown in FIG. 2, the clad layers disposed at opposite surfaces of the active layer form energy barriers which function to restrain implanted carriers in the active region. Accordingly, the density of carriers in the thin active region is very high and the recoupling of carriers for emitting light is mainly achieved in the active layer.
The refractive index of GaAs constituting the active layer is higher than that of GaAlAs constituting the clad layers. Light has a property of concentrating on the region having a large refractive index. In the DH structure, accordingly, light is focused on the active layer, so that densities of carriers and optical waves in the active layer are very high, thereby enabling the threshold current to be reduced.
Furthermore, the threshold current can be further lowered by restraining the carriers and the optical waves in a direction perpendicular to the active layer in the narrow active region. To this end, a metal electrode having a narrow strip shape is formed as shown in FIG. 2, to control the flow of current spatially. As shown in FIG. 2, opposite side surfaces of the metal electrode are formed roughly, so as to prevent the light concentration. Such a structure is called a strip type hetero structure. It is often called a gain transmission type structure since light is guided to a gain region in which the density of carriers is high.
In addition, there is a method for restraining optical waves in a direction parallel to the active layer. In this connection, FIG. 3 shows a buried type hetero structure which is commonly used in communication lasers. As shown in FIG. 3, the structure has a shape that a GaAs active layer is surrounded at its opposite sides by N-type GaAlAs layers.
As above-mentioned, the GaAs layer forms a waveguide path since it is surrounded at its upper, lower, left and right portions by the GaAlAs layers having a refractive index lower than that of the GaAs layer.
As shown in FIG. 3, opposite side surfaces of the waveguide are formed roughly, so as to prevent the light concentration. This type of waveguide is called the refractive index waveguide type.
Such a DH structure has an advantage of a low threshold current. Also, it has a stable oscillation transverse mode characteristic and is advantageous for communication and a information processing.
For using semiconductor lasers in signal processing, a switch characteristic for intermittently controlling the emission of laser is generally required.
In continuous oscillation type conventional semiconductor lasers shown in FIGS. 2 and 3, the supplying of current a to semiconductor laser is switched for switching the laser beam emission. Such a method is difficult to process signals having a frequency of several MHZ or greater, due to the limitation of a drive circuit of the semiconductor laser.
In this connection, a semiconductor layer having a structure shown in FIG. 4 has been proposed by Y. Kan et al in 1986 (IEEE J. QUANTUM ELECTRON, QE-22, 1837, 1986). In such a semiconductor, an electric field is applied to an active layer which is, in turn, excited by external light, for example, He--Ne laser beams, thereby causing the laser to be oscillated.
At this time, the oscillated laser is sensitively affected by the applied electric field and thereby does not oscillate at a bias voltage V1 of -5 V. Accordingly, when charges are filled in a hetero junction, upon applying current to the semiconductor laser, the frequencies of processible signals oscillated are limited to several MHZ, as shown in FIGS. 2 and 3. However, when the oscillation of laser is controlled by the electric field, it is possible to process signals having a frequency of up to several Tera HRZ.
The structure and operation of the semiconductor laser proposed by Y. Kan et al will now be described in conjunction with FIGS. 4 to 6.
FIG. 4 is a sectional view of the structure of a semiconductor laser. As shown in FIG. 4, the semiconductor laser comprises a semitransparent electrodes 1 as an uppermost layer and an Au/Cr electrode 2 as a lowermost layer. These layers serve to cause a current flow into the semiconductor laser. The semiconductor laser has at its middle portion a GaAs active layer 3 having a thickness of 120 .ANG.. Over upper and lower surfaces of the active layer, a pair of GaAlAs clad layers 4 and 5 having a thickness of 0.3 .mu.m are formed, respectively. Between the semitransparent electrode 1 and the GaAlAs clad layer 4, a N-GaAlAs layer 6 is formed which has an impurity concentration of 3.times.10.sup.17 cm.sup.-3 and a thickness of 1.5 .mu.m. On the other hand, a P-GaAlAs layer 7 having an impurity concentration of 3.times.10.sup.8 cm.sup.-3 and a thickness of 2 .mu.m is formed between the Au/Cr electrode 2 and the GaAlAs layer 5. Finally, a GaAs substrate 8 is formed at a predetermined portion between the semitransparent electrode 1 and the N-GaAlAs layer 6.
FIG. 6 shows an energy band structure corresponding to the structure of FIG. 4. As an electric field is applied to the semiconductor laser, electrons presented in a conduction band and holes presented in a valence band move opposite directions with respect to the electric field, thereby causing the recoupling rate therebetween to be reduced. As a result, the oscillation is stopped and the laser emission is cut off. That is, the oscillation is stopped when the bias voltage V1 is -5 V, as shown in FIG. 5.
When the electric field, namely, the bias voltage V1 disappears, the electrons and holes return to their original positions. Accordingly, the oscillation occurs again and thus laser beams are emitted.
As apparent from the above description, Kan's technique makes it possible to switch rapidly the emission of laser beams from the semiconductor laser by oscillating the laser at its active layer using He--Ne laser beams and applying an electric field in a direction perpendicular to the active layer or removing the electric field.
In all of the above-mentioned conventional semiconductor lasers, however, the oscillation is achieved by crystal sectional surfaces (namely, the surfaces of cleavage) formed perpendicular to the active layer and the emission of laser beams is achieved in a direction parallel to the surface of cleavage. As a result, the conventional semiconductor lasers can be suitably used only for the manufacture of unit semiconductor lasers. They are unsuitable for the manufacture of semiconductor lasers of an integrated type in which unit semiconductor lasers are arranged in two dimensions. In these semiconductor lasers, consequently, it is impossible to process simultaneously a plurality of signals such as video signals.

Semiconductor laser and method for manufacturing the same