A method for use with a computer system includes assembling a group of volume units to represent at least a portion of a three-dimensional (3-D) object and compressing each volume unit onto a pixel plane to form an associated indication of the volume unit. The indications are used to form a first image of a view of the portion(s) of the 3-D object on a display of the computer system. The view of some of the volume units are changed leaving the view of the remaining volume units unchanged. The indications that are associated with the remaining volume units are used to form a second image of the portion(s) of the 3-D object on the display.

The invention relates to volume rendering.
For purposes of rendering an image of a volume for display on a computer, the volume may be represented by a finite number of points, and each of these points may be associated with a scalar or a vector value (a time varying value, for example) that represents a density of the volume at that point. In the case where sampling is used to obtain the values, the points that represent the computer-rendered volume may not be aligned with the actual points at which the samples were taken. Instead, each point of the computer-rendered volume may be a point of a uniform grid, and the value that is associated with the point may be obtained via trilinear interpolation of data that is sampled near the corresponding point of the actual volume. Procedures other than sampling may be used to derive the values, such as a procedure that uses one or more polynomial functions.
In general, volume rendering creates a view of the volume from a particular point of view (or two, for stereo display), while allowing image manipulations, such as false color and transparency manipulations. For certain three-dimensional (3-D) graphics applications (medical and geological applications, as examples), it may be desirable for displays of scalar or vector density volumes to be updated at rates fast enough to support real time interaction. This interaction may include traditional activities, such as rotation, cutting or clipping. However, the interaction may also include subtler interactions, such as volumetric deformations and morphing transformations to adjust and design shapes or to simulate tissue motion in surgery, as examples.
As an example, if a graphics application simulates surgery, a controller may be used to move a displayed scalpel. In this manner, the displayed scalpel must respond quickly in response to movement of the controller to prevent overshoot of the displayed scalpel. As an example, the difference in time from when the controller moves to when the scalpel moves in response may need to be less than approximately 100 milliseconds.
Current volume rendering schemes may use a central processing unit-based (CPU-based) approach in which a CPU executes software to perform the volume rendering. However, CPU-based processing may be too slow to support desired interaction rates. For example, some current volume rendering schemes may use a technique called xe2x80x9cray castingxe2x80x9d to form an image of a volume. With ray casting, the appearance of an opaque or translucent 3-D object is determined by tracing a ray from a viewpoint of the image to (and if necessary through) the object or from behind the object to the viewpoint. However, traditional approaches to ray casting may be slowed primarily by the nature of their memory accesses to volume elements (called xe2x80x98voxelsxe2x80x99), accesses that may nullify the performance benefits that are otherwise gained by a cache. This inefficient use of the cache may be improved by processing small rectangular blocks, or sub-blocks, of the volume at a time, but rectangular block organization may be an obstacle to fast morphing transformations.
Other volume rendering schemes may include techniques called splatting, 3-D texture mapping and shear-warp factorization. However, none of the above-described schemes may be fast enough to support morphing and/or display of the volume at desired interaction rates without relying on specialized graphics hardware and/or a substantial amount of pre-processing.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems stated above.
In one embodiment, a method for use with a computer system includes assembling a group of volume units to represent at least a portion of a three-dimensional (3-D) object and compressing each volume unit onto a pixel plane to form an associated indication of the volume unit. The indications are used to form a first image of a view of the portion(s) of the 3-D object on a display of the computer system. The view of some of the volume units is changed, leaving the view of the remaining volume units unchanged. The indications that are associated with the remaining volume units are used to form a second image of the portion(s) of the 3-D object on the display.


A signal-processing arrangement includes a conversion circuit CONV which converts an input signal Sin into sub-ranging signals Sc(1)..Sc(N) corresponding to different amplitude sub-ranges of the input signal Sin. Each sub-range signal is supplied to a respective one of an array of sampling circuits SC(1)..SC(N) which supplies successive samples thereof to a processing circuit PROC for processing in accordance with operations which may constitute or include A/D conversion. Such an arrangement is particularly suitable for use in a television receiver, multimedia or other video image display apparatus, and various types of disc-players and tape-recorders.

1. Field of the Invention
The invention generally relates to a signal-processing arrangement and method in which a sampling operation is carried out. Such a signal-processing arrangement may be, for example, a video data acquisition and conversion chain incorporating an analog-to-digital (A/D) converter. Such a signal-processing arrangement may also be, for example, an A/D converter as such.
2. Description of the Related Art
The article "Fully Bipolar, 120-Msample/s 10-b Track-and-Hold Circuit" by P. Vorenkamp and J. P. M. Verdaasdonk, IEEE JSSC, Vol. 27, No. 7, July 1992, pp. 988-992 describes a prior-art video data acquisition and conversion chain. At the input of the chain an analog video signal is applied. The analog video signal is filtered and fed into a track-and-hold (T/H) circuit which carries out a sampling operation. The sampled analog video signal is fed into a data conversion and processing module consisting of an A/D converter, a digital signal processor (DSP), and a digital-to-analog (D/A) converter. The cited article mentions that the T/H circuit, which is used as a presampler in front of the A/D converter, improves the high-frequency performance of the A/D converter.
U.S. Pat. No. 4,831,379, issued May 16, 1989(attorney's docket PHA 1,137) assigned to a related assignee, describes a prior-art A/D converter which comprises an array of 64 input amplifiers. Assuming that i is an integer ranging from 0 to 63, each amplifier Ai amplifies the difference between an analog input voltage and a corresponding reference voltage VRi to produce an amplified output voltage VAi. The amplified output voltages VA0-VA63 are processed in a folding array and an interpolation circuit to produce complementary signals VD0/VDN0 . . . VD31/VDN31 from which signals an output code.


A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall. After removal of the polymer and residual photoresist, the source/drain implant is performed, followed by removal of the polysilicon lip by RIE using the cap oxide as a mask. The LDD implant is then performed.

(1). Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned-polysilicon-gate field effect transistors with lightly doped drains.
(2). Description of Prior Art
It has been determined that hot carrier effects will cause unacceptable performance degradation in n-channel MOS field effect transistors(MOSFETs) built with singly diffused drain structures if their channel length is below about 2 microns. This degradation is due primarily to high electric fields occurring in the drain region which cause the formation of hole-electron pairs by impact ionization. To overcome this problem the lightly-doped-drain (LDD) structure is widely used. A discussion of hot carriers and the formation of the LDD structure may be found in Wolf, S., "Silicon Processing for the VLSI Era", Vol. 2, Lattice Press, Sunset Beach, Calif., (1990), p 348ff. FIG. 1 shows a cross section of the LDD structure. The MOSFET 18 is formed on wafer 20 by first forming a field oxide 22 which surrounds the device. The silicon oxide gate insulator 24 is then grown by thermal oxidation of the silicon surface and a gate electrode 26, usually of doped polysilicon is defined by photolithographic techniques. Using the gate electrode as a mask, an ion-implantation forms the lightly-doped region 28 aligned to the gate electrode. A layer of insulative material, typically silicon oxide, is next deposited by low-pressure-chemical-vapor-deposition (LPCVD). This layer is then etched by a unidirectional technique, typically reactive-ion-etching (RIE) whereby silicon oxide sidewalls 30 are formed along the edges of the polysilicon gate electrode. The width of the sidewalls 30 corresponds roughly to the original thickness of the insulative layer. A second ion-implant is then performed at a higher dose to form the main portions 32 of the source/drain regions of the device. Both implantation are perfectly self-aligned to the gate electrode an require no photolithographic steps. By having reduced doping in the region 28 immediately at the edge of the channel region, the doping gradient is less abrupt. This results in a lower electric field and consequently a reduction of hot carrier generation.
A function of the oxide sidewall 30 is to provide spacing around the gate electrode to locate the source/drain implant away from the edge of the gate. After the implant is completed, an inter level dielectric (ILD) layer is deposited over the structure and contact openings are made to access the elements of the MOSFET. The oxide sidewall 30 becomes part of that ILD layer.
Although the just described method for forming the LDD structure using a silicon oxide sidewall is the most commonly used and easiest understood, other variations have been purported wherein the sidewall is fashioned of different materials. Hodate et. al. U.S. Pat. No. 5,518,940 forms the sidewall spacer of photoresist. The photoresist is selectively electro-deposited on the top and sides of the polysilicon gate electrode by application of a voltage to the electrode while the substrate wafer is submersed in an electrolyte. The application is the manufacture of liquid crystal displays. Such electro-deposition procedures are not compatible with current integrated circuit manufacturing processes.
Hodate points out several disadvantages of the oxide sidewall formation process. One is the non-uniformity of RIE plasma over large substrate areas. Another is a dependence of the sidewall thickness on the thickness of the polysilicon gate electrode.
Beinglass U.S. Pat. No. 4,975,385 describes a method of forming an LDD structure by using spacers of polysilicon which are selectively deposited on the edges of the polysilicon gate electrode after the LDD implantation. Only the edges (sidewalls) of the polysilicon gates are exposed during this deposition and a specified LPCVD process is used to deposit only on these exposed sidewalls. After the deposition the second high dosage source/drain implantation is made. The polysilicon sidewalls are not subsequently removed and become part of the structure. They therefore are prone to participate as part of the gate electrode affecting the resultant channel.
Reactive ion etching of patterns in insulative layers such as silicon oxide with halocarbon gases is typically accompanied by the formation of polymer deposits along the walls of the openings. It is also widely believed that the ability to achieve anisotropic etching of these materials in chloro-fluorocarbon gas mixtures is the direct result of the formation of these polymers. The polymer layer protects the sidewalls from chemical reaction while the etch front is kept clear of the polymer by ion bombardment. Unidirectional etching is thereby accomplished.
When pattern etching is completed steps are taken to remove the polymeric deposits before proceeding, usually by wet chemical dissolution. The task of removing both polymer and residual photoresist is accomplished by a combination of oxygen plasma ashing and the use of stripper solutions. Park et. al. U.S. Pat. No. 5,451,291 discusses the formation of via openings over aluminum using such combinations.
The growth of polymer along the sidewalls of the opening being etched can be well controlled both by the selection of etchant gases as well as adjustment of the RIE parameters. Thus the final thickness of the polymer deposit on the sidewall can also be pre-determined.

Procedure for forming a lightly-doped-drain structure using polymer layer

Chartered Semiconductor Manufacturing Ltd.


A textile or the like hanger having a plurality of releasably fastenable toothed suspender clips, a support rod, and support brackets. Each suspender clip has a cradle hook portion for hanging the clips on the rod.

Display of rugs and carpets, particularly oriental and Persian rugs, on walls or the like has become popular as such textiles are increasingly recognized not only for their utilitarian function but also as pieces of art. These rugs and carpets tend to be large pieces, often measuring, 5 ft. by 7 ft. or larger, and consequently have considerable weight.
Curtain rods and holders have been long known for suspending fabrics and cloth to cover windows and the like. See, for example, U.S. Pat. No. 1,884,414 issued to Vroom; U.S. Pat. No. 551,124 issued to Krah; U.S. Pat. No. 606,442 issued to Bullis; and U.S. Pat. No. 597,551 issued to Atkins. Generally, curtain or drapery material is considerably lighter in weight than carpets and rugs, and generally, holes or specially constructed pleats are made in the material so that rings or hooks can be inserted and then attached to rods.
Other clamping or holding devices for supporting objects such as flexible sheets, charts, blueprints, placards and the like are also known. See, for example, U.S. Pat. No. 2,622,300 issued to Marziani (hanger for blueprints); U.S. Pat. No. 4,629,075 issued to Hutten (mounting strip for flexible sheet material); and U.S. Pat. No. 4,830,322 issued to Gary (chart holder). Such suspending devices are geared to hanging objects that are substantially light in weight and are not suitable for hanging a rug or carpet.
The hanging of rugs and carpets is a formidable task because of their considerable weight and because as art pieces, owners have generally not relished making holes in the carpets in order to hang them. Often times, to avoid making holes in the carpets, loops of material are attached to an edge and then slid onto a rod secured to a wall at the appropriate height. Such additions, of course, tend to detract from the carpet piece. Moreover, because of the substantial weight of the carpets, problems have arisen with the rod for holding the carpet. The rod must have substantial rigidity to hold the rug without bending with its weight.
Thus, a problem, largely unattended in the art, is the lack of a simple, inexpensive way to hang rugs and carpets without damaging the pieces and in which the rugs and carpets are firmly yet releasably gripped.


A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously. The device is configured to generate the at least one output clock signal depending on the differently delayed clock signals with a settable phase relationship to the non-delayed input clock signal, wherein the phase relationship is settable independently of the delay provided by the delaying means. It is particularly provided that the phase relationship between the delayed output clock signal and the non-delayed input clock signal is automatically controlled to a desired phase relationship independently of the delay supplied by the delaying means.

In physical interfaces for memory applications, e.g. for so-called DDR memories, various kinds of signals are used to transmit data from or to the memory and to control the memory. These are especially control clock signals, data signals and sampling signals, so-called strobe signals, and also command and addressing signals. For effective communication between the memory and the interface it is necessary to set the phase relationships of these signals mutually or relative to an external clock signal.
To set the desired phase relationships between the signals it is common to use so-called delay locked loops. These are delay-locked loops which compare a clock signal with a delayed clock signal and automatically control the delay in such a way that the phase relationship of the clock signal and the delayed clock signal adopts a fixed value. A delay-locked loop can especially also delay in a controlled manner clock-type signals which do not have full periodicity, i.e. are only periodic in sections.
Examples of delay-locked loops of this kind are illustrated in FIGS. 8(a) and (b). The delay-locked loop of FIG. 8(a) receives a clock signal 1 as input signal. The clock signal is delayed by a delaying means 82 by a specific amount of time which can be set by a control signal 88. The output signal of the delaying means 82 thus forms a delayed clock signal. The delayed clock signal is compared by comparison means 84 with the non-delayed clock signal 1 in respect of the relative phase position. An output signal of the comparison means 84, generated on the basis of the comparison of the clock signal 1 with the delayed clock signal, is fed to the delaying means 82 as the control signal 88 via a loop filter 86.
An alternative form of delay-locked loop is illustrated in FIG. 8(b). This corresponds in respect of the delaying means 82, the comparison means 84 and the loop filter 86 to the delay-locked loop already described above using FIG. 8(a). However, the difference in this case is that two clock signals 1, 1a are fed to the delay-locked loop and their phase relationship is set by the delay-locked loop. This is achieved in that clock signal 1 is delayed by the delaying means 82 in order to generate the delayed clock signal, while the delayed clock signal is compared by the comparison means 84 with clock signal 1a, which thus has the function of a reference clock signal. The difference between the delay-locked loops of FIGS. 8(a) and (b) is consequently that in one case the phase relationship is set in respect of the non-delayed clock signal 1, while in the other case the phase relationship is set in respect of the reference clock signal 1a. The reference clock signal 1a can, for example, be derived externally from clock signal 1.
It is normally necessary with memory interfaces not only that a specific phase relationship is set, but that the phase position can also be set individually in each case for the different signals. In this connection it is known to configure a device for generating clock signals with controlled delay on the so-called master-slave principle. It is usual in such cases to use a delay chain with several delay stages or elements as delaying means. In a master delay loop the delay of the delaying means is firstly adjusted in such a way that there is a fixed phase relationship between the output signal of the delaying means and the non-delayed clock signal or the reference clock signal. The actual generation of the delayed clock signals is done by slave delay loops which are constructed identically to the master delay loop, but do not have their own control loop. The control signal of the master delay loop is then used as control signal for the delaying means of the slave delay loop. A delayed output clock signal is generated in that signals are tapped from the individual delay steps of the delaying means via a multiplexer. The delayed clock signals tapped in this way normally correspond to a fixed fraction of the delay set by the master delay loop. In this way it is possible with the slave delay loops to select the desired phase relationship between the clock signal or reference clock signal and the respective delayed signal individually. It is further possible to locate the generation of delayed clock signals flexibly, for example near the place where the delayed clock signal is being used.
FIG. 9 shows schematically a circuit block, configured on the master-slave principle, for generating and synchronising data and sampling signals in a memory interface for a memory device. The circuit block comprises a master delay-locked loop 100′, to which a clock signal to be delayed is fed as input signal. The master delay-locked loop 100′ delays the clock signal 1 by a specific amount of time, a defined phase relationship being set between the clock signal 1 and the delayed clock signal. To set the defined phase relationship the master delay-locked loop 100′ internally generates a control signal via which delaying means 110′ of the master delay-locked loop 100′ are controlled. The control signal of the master delay-locked loop 100′ is available at a signal output of the master delay-locked loop 100′ and is used to control a slave delay-locked loop 300.
The delaying means 110′ of the master delay-locked loop 100′ and of slave delay-locked loop 300′ are formed by identical delay chains with several delay elements 115′. The control signal which is generated by the master delay-locked loop 100′ controls in particular the delay supplied by one of the delay elements 115′ of the delaying means 110′. By tapping at the outputs of the individual delay elements 115′ of the delaying means 110′ both of the master delay-locked loop 100′ and of the slave delay-locked loop 300′, delayed clock signals can be tapped, which after adjustment of the master delay-locked loop 100′ have different delays, which correspond in each case to a defined fraction of the period length of the clock signal 1. The output signals of the individual delay elements 115′ are fed to multiplexers 120′, 320′, which generate output clock signals 3a, 3b, 3c by selecting the different delayed clock signals.
The phase relationship of the output clock signals 3a, 3b, 3c to the non-delayed clock signal is set by appropriate driving of the multiplexers 120′, 320′. For this values for the desired phase relationship are selected from lists stored in a memory 150′, 350′ and transmitted to a control register 130′, 330′. These values feed an appropriate control signal to the multiplexer 120′, 320′.
Output clock signal 3a acts as input signal for a sampling signal generating block 50′ which generates a sampling signal 3′ on the basis of output clock signal 3a. Output clock signal 3b is fed to a synchronisation block 60′ which synchronises write data signals 6, to be written into the memory, with output clock signal 3b, in order in this way to generate a memory data signal 4 synchronised with output clock signal 3b for write processes.
The master delay-locked loop 100′ generates output clock signals 3a, 3b, on the basis of the non-delayed clock signal 1. The slave delay-locked loop 300′, on the other hand, uses the sampling signal 3′ as input signal. A delay of the not fully periodic sampling signal 3′ is possible owing to the use of delay-locked loops. A desired phase relationship between the sampling signal 3′ and output clock signal 3c is set for read processes by slave delay-locked loop 300′. Output clock signal 3c is fed to a synchronisation block 70′ which generates a read data signal 5 synchronised with the clock signal 1 on the basis of a data signal 4 received from the memory. For this the clock signal 1 is additionally fed to the synchronisation block 70′.
For bi-directional use the arrangement of FIG. 9 is provided with switching means 40′ by which signal connections, the use of which is not necessary for the intended application, i.e. for a write or a read process, can be interrupted. Feeding of the sampling signal 3′ to slave delay-locked loop 300′ and connection of the data memory signal 4 to the synchronisation block 70′ are interrupted during write processes, for example.
FIG. 10 shows a further circuit block constructed on the master-slave principle for a memory interface and used for generating and synchronising control clock and command and addressing signals. The clock signal 1 is fed to a slave delay-locked loop 400′ constructed similarly to slave delay-locked loop 300′ of FIG. 9. Output clock signals 7, 8 of the circuit block are again generated via a multiplexer 420′, to which differently delayed clock signals tapped at the individual delay elements 115′ of the delaying means 110′ of the slave delay-locked loop 400′ are fed. The multiplexer 420′ is driven corresponding to the arrangement in FIG. 9 by a control signal generated by a list stored in a memory 450′ and a control register 430′. By means of this circuit block addressing and command signals 11, 12, 13 are conducted to the memory as addressing and command signals 11′, 12′, 13′ synchronised with the clock signal 1 via flip-flop elements 460 driven by the clock signal 1. The output clock signals 7, 8 of slave delay-locked loop 400′ act as control clock signals for the memory. The task of slave delay-locked loop 400′ is in this case to guarantee that the control clock signals 7, 8 are synchronised with the addressing and command signals 11′, 12′, 13′ at the location of the memory. A defined phase relationship to the sampling signal 3′ and the memory data signal 4 is further necessary. In order to be able to guarantee the required signal strengths at the location of the memory the output signals of the circuit block illustrated in FIG. 10 are output via buffers or line drivers 45′.
The previously described use of the master slave principle for generating and synchronising clock, sampling and data signals and also command and addressing signals guarantees independent selection of the phase relationship for the individual output clock signals 3a, 3b, 3c, 7, 8. A problem with this known solution for setting the delay of clock signals is, however, that the desired phase relationship is preset purely statically, preferably based on an expected value for differences in delay of the individual signals. In this way problems arise in particular if the pulse-duty ratio of the clock signal 1 is subject to fluctuations. Only deviations of the phase relationships which are considerably smaller than the length of a symbol, i.e. typically of a period length of the clock signal 1 may occur. However, this requirement cannot necessarily be guaranteed, in particular for high-frequency memory media. If there are greater fluctuations of the phase shift this leads to a loss of data which can be compensated for only by complex clock and data recovery mechanisms.
A general problem in delay-locked loops is that they react sensitively to errors in the pulse-duty ratio, a so-called duty cycle distortion, which may occur both in the input-side clock signal and within the delaying means. It is further necessary that a clock signal with a high spectral purity and low noise is used as input signal.
Both analog and digital signals can be used as control signals for the delaying means. In the case of analog control signals, however, there is the problem of great sensitivity with respect to interference towards scattering in by internal or external interferers. In this case there are resulting undesired deviations or additional noise within the delaying means. Neither can these problems be avoided by embodying the control loop in differential switching technology. Especially problematical is the use of analog control signals in an arrangement constructed on the above-described master-slave principle. In this case in some circumstances the control signal has to be transmitted to the slave delay loop over a greater distance. This gives rise to increased susceptibility to interference and noise.


A heat dissipation system includes a chassis, a number of heat absorbing boxes, a number of pipes, a first water tank and a second water tank received in the chassis, a number of fins sandwiched between the first water tank and the second water tank, a number of fans aligning with the fins, and a water pump connected between the first water tank and the second water tank. Each heat absorbing box includes a water inlet and a water outlet, and heat from electrical components is gathered by the boxes, transferred to the water tanks, and the fans blow air through the fins to dissipate the gathered heat.

1. Technical Field
The present disclosure relates to a rack-mount server with a heat dissipation system.
2. Description of Related Art
An ordinary rack-mount server includes a plurality of server units generating a large amount of heat in operation. If the heat is not removed rapidly, it will cause damage to the server units. Typically, the heat is dissipated out of the rack-mount server by the system fans. However, dissipating heat by the system fans is slow and inefficient.

Heat dissipation system and rack-mount server using the same

HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.


A deck panel for reinforced concrete slabs is disclosed. The deck panel is formed by integrating a plurality of deck girders with a deck plate into a single structure. In each of the deck girders, a single lattice member is welded to upper and lower steel bars. The lattice member has a zigzag configuration with both a plurality of holding rib parts and a plurality of horizontal foot parts. The lattice member is positioned relative to the upper and lower steel bars in a way such that the holding rib parts, individually having a foot part, are alternately positioned on opposite sides of the upper and lower steel bars. A vertical fixing steel bar is welded to each end of the deck girder with both the top end of the fixing steel bar being welded to the upper steel bar and the middle portion of the fixing steel bar being welded to the lower steel bar.

1. Field of the Invention
The present invention relates, in general, to a deck panel for reinforced concrete slabs and, more particularly, to a deck panel formed by welding a plurality of deck girders onto a deck plate prior to being laid on iron beams or reinforced concrete beams, thus accomplishing both a concrete slab forming work and a surface finishing work at the same time while conserving the material of the slab structure and increasing the welding strength of the deck panel.
2. Description of the Prior Art
As well known to those skilled in the art, a reinforced concrete structure is formed using both concrete as a compression member and a plurality of steel bars as tension members, thus having a complex construction. In order to form such a reinforced concrete structure, a plurality of cast panels are arranged on a support surface with a desirable gap being defined between the cast panels. Thereafter, a plurality of steel bars are appropriately arrayed inside the gap. After arraying the steel bars inside the gap between the panels, concrete is poured into the gap and is hardened for a time so that the concrete is integrated with the steel bars into a single reinforced concrete structure. After the reinforced concrete structure is completely hardened, the cast panels are removed from the structure one by one, thus providing a desired reinforced concrete structure. Such a reinforced concrete structure is typically and preferably used as a building structure.
The typical process of forming such a reinforced concrete structure must include several steps of arraying the cast panels, such as wood panels, on a support surface and arraying a plurality of steel bars inside the gap between the panels. The process also includes a panel separation step of removing the cast panels from a reinforced concrete structure after the structure is completely hardened. That is, the process of forming a reinforced concrete structure using the cast panels includes a plurality of steps so that the process is time consuming.
Typically, the cast panels strongly adhere to the surfaces of the reinforced concrete structure and so it is very difficult to remove the panels from the structure. In addition, the cast panels cause uneven surfaces to remain on the reinforced concrete structure, thus causing the structure to be subjected to an additional surface finishing work. The cast panels are typically formed of a low strength material such as wood so that the panels may be unexpectedly damaged or broken when they are forcibly removed from a reinforced concrete structure. Such damaged panels cannot be repeatedly used so that they force the owner to purchase new ones at excessive costs and generate a large amount of waste panels.
In an effort to overcome such a problem experienced in the process of forming a reinforced concrete structure using the cast panels, a panel-free process, using a finishing member being integrated with concrete into a reinforced concrete structure, is proposed.
A deck plate process, which uses a corrugated deck plate in place of such cast panels, is a representative example of the known panel-free process. In such a deck plate process, a deck plate is simply laid on beams and so the process is free from the steps of arraying and removing the cast panels. Another advantage of the deck plate process resides in that the deck plate provides a safety working platform for workers thus eliminating the need for a typical safety net from the construction area. Such a deck plate remarkably simplifies the process of forming a reinforced concrete structure and shortens the construction time.
However, such a typical deck plate process is only free from the steps of arraying and removing the cast panels, but the deck plate process still requires the use of steel bars in order to provide a desired reinforcing strength of a concrete slab structure and securely integrate the flat deck plate with concrete, thus failing to radically simplify the process of forming a reinforced concrete structure.
In order to overcome the problems experienced in the typical deck plate process, several technologies are proposed and used.
FIG. 1 shows an embodiment of typical deck panels used in the process of forming a reinforced concrete slab structure. In order to form the deck panel of FIG. 1, three steel bars, one upper steel bar 12 and two lower steel bars 14, are welded to each other using two oppositely-arranged lattice members 15, thus forming a deck girder 10. A plurality of deck girders 10 are, thereafter, welded to a deck plate 20, thus forming a deck panel. In order to form a reinforced concrete slab using such a deck panel, the deck panel is laid on beams H prior to pouring concrete onto the deck panel. When the concrete is completely hardened, the concrete is securely integrated with the deck panel into a single reinforced concrete slab. In this case, the deck plate 20 forms a surface finishing member of the resulting reinforced concrete slab, thereby allowing the process to be free from any additional arrangement of steel bars, shortening construction time, conserving construction costs and improving work efficiency while forming reinforced concrete slabs.
However, the above deck girder 10 is formed by welding one upper steel bar 12 and two lower steel bars 14 to each other using two lattice members 15. The deck girder 10 thus regrettably wastes such lattice members 15. In addition, the three steel bars 12 and 14 and the two lattice members 15 have to be welded to each other into a deck girder 10, thereby deteriorating work efficiency and increasing construction costs while forming reinforced concrete slabs. Another problem of the above deck panel resides in that the deck girder 10 forms a space between the two lattice members 15. Since concrete cannot easily flow into the space, it is necessary to forcibly push the concrete into the space, thus reducing work efficiency while forming reinforced concrete slabs.
FIG. 2 shows another embodiment of typical deck panels used in the process of forming a reinforced concrete slab structure. In order to form the deck panel of FIG. 2, one upper steel bar 12 is welded to one lower steel bar 14 using one longitudinal lattice member 15, thus forming a deck girder 10. In the deck girder 10, the top bent portions of the lattice member 15 are welded to the upper steel bar 12, while the bottom bent portions are welded to the lower steel bar 14. A plurality of deck girders 10 are, thereafter, welded to a deck plate 20 and are reinforced by a plurality of transverse lattice members 17, thus forming a deck panel. In comparison with the deck panel of FIG. 1, the deck panel of FIG. 2 conserves the lattice members 15 and allows concrete to easily flow onto the deck panel. However, in the above deck panel, the longitudinal lattice member 15 has to be welded to the upper and lower steel bars 12 and 14 at several points, thereby reducing work efficiency while forming a reinforced concrete slab. In addition, the welding junction between the deck girder 10 and the deck plate 20 is small in area and reduces the welding strength of the deck panel. The above deck panel is also provided with a plurality of transverse lattice members 17 for reinforcing the deck girders 10, thus consuming the material of the lattice members 17 and reducing work efficiency and welding strength while welding the deck girders 10, transverse lattice members 17 and deck plate 20 to each other into a deck panel.

Deck panel for reinforced concrete slabs


The present invention relates to a vector comprising a polynucleotide encoding a modified glutamine synthetase (GS), and a method for preparing a target protein employing the same. More particularly, the present invention relates to a modified GS having an increased sensitivity to a glutamine synthetase (GS) inhibitor, a polynucleotide encoding the modified GS, a vector comprising the polynucleotide, a transformant comprising the vector, and a method for preparing a target protein using the transformant.

Recombinant proteins can be expressed in different types of host cells including prokaryotic and eukaryotic cells. However, glycoproteins, such as antibodies and Fc fusion proteins, consist of a polypeptide linked to a carbohydrate moiety which influences the safety and efficacy thereof, and thus they are usually expressed in animal cells that are capable of glycosylation during post-translational modification. In the production of recombinant protein drugs, the difference in their sugar chains with those of human (native) glycoproteins is associated with immunogenicity of the protein drugs. Thus, it is important to produce glycoproteins having sugar chains identical or similar to those of human glycoproteins.
Until recently, animal cells such as hybridoma, mouse myeloma, and CHO cells have been commonly used in the expression and production of recombinant protein drugs. The protein expression in these animal cells is appropriate for producing proteins similar to human proteins, but there are disadvantages of a significantly low expression yield and difficulty in scale-up of the production. In particular, therapeutic antibodies need to be produced in kilogram quantities, and thus animal cell culturing is not suitable for a large-scale production of the therapeutic antibodies. Therefore, for a high level expression of a target gene in the host cells, the target gene needs to be integrated into a transcriptionally active region of the genome when the target DNA is randomly introduced to the animal cell. The introduced foreign gene replicates along with the genome of the host cell. However a homologous recombination technique for integration of the gene into transcriptionally active regions is not generalized for common use yet.
Another method for increasing the expression rate of randomly integrated DNA is by amplifying the integrated gene, and this method needs the step of cloning the gene into the vector engineered with gene amplification system. A DHFR system (Takeshi omasa, gene amplification and its application in cell and tissue engineering, J. Bios. and Bioe (2002), Vol. 94, No. 6, 600-605) is a common gene amplification system, and this system increases the protein expression level by co-amplification of a target gene and DHFR using methotrexate (MTX) which is an inhibitor of dihydrofolate reductase (DHFR). DHFR is an enzyme involved in nucleotide biosynthesis, and thus inhibition of DHFR activity can effectively interrupt DNA synthesis which is essential for cell maintenance, thereby leading to cell death. Therefore, only those clones having exogenous DHFR gene inserted in their genome can survive under this condition. Furthermore, when the concentration of MTX being added is increased and a strong promoter is used, DHFR gene can be amplified to hundreds to thousands of copies. That is, the more MTX, a DHFR inhibitor, is added to the cell culture, in order for them to survive they increase the expression of DHFR along with the introduced target gene. Consequently, several copies of DNA will be incorporated, leading to the generation of various molecular variants.
A DHFR system using CHO cell line has been reported and commercialized as an expression system for various protein drugs, verifying its safety and efficacy in use. However, the DHFR system has a disadvantage in that it requires several months to isolate a single cell line that shows the expression level higher than the normal level. In addition, when the cell becomes resistant to MTX, even with an increase in MTX concentration, the target gene cannot be amplified anymore. Furthermore, in the CHO DUKX cells used for DHFR system, revertants may appear easily. As a result, there has been a high demand for the development of a high-level gene expression system for protein production other than the DHFR system.
GS system is a high-level gene expression system that was first developed by Celltech (U.S. Pat. No. 5,122,464), and it overcame the limitations of the DHFR-based gene expression system, that is, low time-efficiency for isolating the single cell line of interest and low productivity of target protein. The GS system utilizes glutamine synthetase (GS) which is an enzyme involved in the sole synthetic pathway for producing glutamine from glutamate and ammonia, based on the fact that animal cells cannot grow properly in the glutamine-deficient condition. The GS system has advantage in that it requires less number of DNA copies per cell compared to the DHFR system and allows for the selection of single cell line having high expression rate at the early stage of screening. Consequently, an increasing number of organizations adopt the GS system as a protein drug expression system. NS0 cell line and CHO cell line are the most commonly used cell lines for GS system. Between two, NS0 cell line which is a mouse myeloma cell line cannot express sufficient amount of GS, and thus in the glutamine-deficient condition, those cells where the target gene is inserted into their genome can be easily selected. Unlike the NS0 cell line, a CHO cell line can express sufficient amount of GS that they can survive even in the glutamine-deficient medium. However, if the CHO cells are treated with a high concentration of GS-specific inhibitor such as methionine sulphoximine (MSX), the cells cannot survive only with the endogenous GS activity, and thus only those cells introduced with the vector comprising the GS gene and the gene for a target protein can survive. Through the above mechanism, the cells inserted with the gene for target protein can be isolated, and the target protein can be produced at high yield. In other words, as more GS-specific inhibitor is added to the cells, in order for them to survive, they will amplify exogenous GS gene as well as the target gene which is introduced together with the GS gene, thereby increasing the amount of target protein in the cell. However, even this GS system has a limitation in production amount when the cells transfected with the vector comprising the genes for target protein and GS are treated with the GS-specific inhibitor for producing the target protein. Also when the cells were cultured for a long time, the production amount of the target protein was reduced. Due to these limitations, there has been a high demand for the development of a modified GS protein that responses more sensitively to the GS inhibitor and thus can amplify the target gene introduced with GS to the greater level.

Expression vector comprising a polynucleotide encoding a modified glutamine synthetase and a method for preparing a target protein employing the same


An emergency lighting arrangement preferably includes plural emergency light units connected to an on-board power supply network of an aircraft, and plural emergency current sources that each include at least one capacitor. Each emergency light unit includes an emergency light emitting element and a control unit that automatically connects the capacitor of the emergency current source to the emergency light emitting element upon the failure of the on-board power supply network. Preferably, the emergency current source including the capacitor is integrated into the emergency light unit. The emergency light unit may further include normal operation light emitting elements selectively connected by the control unit to the on-board power supply network. The control unit switches between normal operation of the normal light emitting elements and charging of the capacitor, and emergency operation in which the capacitor discharges through the emergency light emitting element.

A conventional emergency lighting arrangement in an aircraft includes a number of emergency lights arranged distributed in the aircraft, as well as one or more emergency current supply units having rechargeable batteries that supply electrical current to the emergency lights in the event of a failure of the on-board electrical power supply network of the aircraft. Such emergency current supply units are conventionally known under the name Emergency Power Supply Units (EPSUs), for example from references and sources such as http://www.diehl-dle.com/en/frm.html or http://www.pageaerospace.com.
Depending on the storage capacity of the rechargeable batteries, such a conventional emergency current supply unit can supply electrical power to a certain limited number of the emergency lights. Typically, several or many emergency lights are connected to a single emergency current supply unit by suitable cabling. The rechargeable batteries must be regularly tested and occasionally replaced or exchanged due to their limited operating lifetime, which leads to a considerable inspection and maintenance effort and time expenditure. Also for this reason, the battery-powered emergency current supply units can only be installed at certain locations within the aircraft, namely locations that allow an easy access for the purpose of testing, inspection and replacement of the batteries, for example behind a maintenance panel or door.
A further disadvantage of the conventional arrangement is that the battery-powered emergency current units have a relatively high weight, for example because the batteries have a relatively high ratio of weight to storage capacity. Furthermore, when a plurality of emergency lights are to be connected to a single emergency current supply unit, this requires a complicated cabling arrangement that adds to the total system weight. Nonetheless, such a cabling arrangement is necessary to ensure a remaining adequate functionality of as much of the emergency lighting arrangement as possible, for example after the occurrence of an assumed cabin rupture that may break or interrupt at least some of the emergency current supply cables.
The US Patent Application Publication US 2003/0026092 A1 discloses a portable rechargeable blinking light, that is particularly adapted to be installed or mounted as a convenience light or lamp in a motor vehicle. A capacitor is provided as an independent current supply, whereby the supply of electrical current from the capacitor to the light emitting element can be switched on or off as desired by the user by means of a switch provided for this purpose.

Emergency lighting arrangement with decentralized emergency power supply for an aircraft


A control apparatus for controlling gas flow in a molecular region including a housing, having a through-channel, and a control plate displaceable in its plane between an open position, in which the plate is located sidewise of the through-channel, and a closed position, in which the control plate crosses the through-channel, the control plate having a circumferential edge at least a portion of which is received in a groove circumscribing the through-channel, with the received portion having a profile which is offset backward or projects out with respect to the cross-sectional profile of the through-channel, and with the received portion having a diminished cross-sectional profile in comparison with the remaining edge portion.

The present invention relates to a control apparatus for controlling gas flow in a molecular region and including a housing having a through-channel and a groove circumscribing the through-channel along a predetermined circumferential extent of the through-channel, and a control plate displaceable in its plane between an open position, in which the plate is located sidewise of the through-channel, and a closed position, in which the control plate crosses the through-channel, which control plate has a circumferential edge at least a portion of which is received in the circumscribing groove in the closed position of the control plate.
The molecular gas flow takes place in a vacuum region with a pressure of 10-6 bar of lower. The molecular gas flow also plays a certain role in the transient region, the pressure in which is below 10-3 bar. The region of the molecular gas flow is characterized in that the mean free path lengths of the molecules are inversely proportional to the pressure. The mean free path lengths is a measure of probability of a collision of a molecule with another molecule of its environment. The mean free path lenghts define paths of separate molecules between two collisions. The mean free path lengths are rather substantial in the above-mentioned vacuum region.
In the material processing technology, there exists a need to control or regulate such a molecular gas flow and as continuously as possible over a large region. However, up to the present, all attempts to control the molecular gas flow did not bring the desired results.
Accordingly, an object of the invention is to provide a control apparatus for controlling gas flow in a molecular region which would insure a continuous control of a molecular gas flow over a large region.

Control apparatus for controlling gas flow in a molecular region


A solid titanium catalyst component comprising (a) magnesium, (b) titanium, (c) a halogen, (d) a polyether, (e) a hydrocarbon and (f) an electron donor other than the polyether (d) as essential components is provided. Also a process for preparing a solid titanium catalyst component for olefin polymerization, comprising the steps of contacting a halogenated magnesium compound with a compound selected from the group consisting of an alcohol, an ether and an ester in a hydrocarbon solvent to obtain a magnesium compound solution, contacting the magnesium compound solution with a polyether and contacting the resultant solution with a liquid titanium compound is provided. Further, a catalyst for olefin polymerization comprising the above-mentioned solid titanium catalyst component, an organoaluminum compound catalyst component and an electron donor, and a process for polymerizing an olefin using the catalyst for olefin polymerization are also disclosed. By the use of the catalyst for olefin polymerization, an olefin (co)polymer having uniform particle size, less dust quantity, high bulk density and high stereoregularity can be obtained with excellent polymerization activity.

Known in the art is a catalyst comprising an active magnesium halide and, carried thereon, a titanium compound for use in the production of an olefin polymer, including a homopolymer of ethylene or an .alpha.-olefin and a copolymer of ethylene and an .alpha.-olefin. In particular, such a known catalyst for olefin polymerization is, for example, comprised of a solid titanium catalyst component comprising magnesium, titanium, a halogen and an electron donor, and an organometallic compound catalyst component.
Various proposals have been made on the process for preparing the above-mentioned solid titanium catalyst component comprising magnesium, titanium, a halogen and an electron donor as essential components. It is also known in the art that a polymer having a high stereoregularity can be produced in high yield by polymerizing an .alpha.-olefin having at least three carbon atoms in the presence of the solid titanium catalyst component.
The conventional process for preparing the solid titanium catalyst component includes a process comprising contacting a hydrocarbon solution of a halogenated magnesium compound with a liquid titanium compound to form a solid product. It also includes a process comprising producing a hydrocarbon solution of halogenated magnesium and titanium compounds, followed by formation of a solid product in the presence of at least one electron donor selected from the group consisting of polycarboxylic acids, monocarboxylic esters, polycarboxylic esters, polyhydric compound esters, acid anhydrides, ketones, aliphatic ethers, aliphatic carbonates, alkoxylated alcohols, alcohols having an aryloxy group, organosilicon compounds having an Si--O--C bond and organophosphorus compounds having a P--O--C bond.
In this connection, it is known that the selection of a polycarboxylic acid (e.g., phthalic anhydride) as the electron donor leads to preparation of a solid titanium catalyst component with which an olefin (co)polymer having uniform particle size and less dust quantity can be obtained.
The present inventors have made investigations with a view toward developing a Ti catalyst for olefin polymerization with which an olefin (co)polymer having uniform particle size, less dust quantity and high bulk density can be produced. As a result, they have found that the (co)polymer having uniform particle size, less dust quantity and high bulk density can be produced by the use of a catalyst for olefin polymerization containing a solid titanium catalyst component which comprises, as essential components, (a) magnesium, (b) titanium, (c) a halogen, (d) a compound having at least two ether linkages existing through a plurality of atoms, (e) a hydrocarbon and (f) an electron donor other than the compound (d). Based on this finding, the present invention has been accomplished.

Solid titanium catalyst component for olefin polymerization, process for preparing the same, catalyst for olefin polymerization and process for olefin polymerization


A speed control system is provided for a motor vehicle, including units for calculating a drive torque or a brake torque as a function of a pre-definable target speed, the target speed being pre-defined by the single actuation of an operable control element. A sustained actuation of the control element is used to pre-define a target acceleration, instead of a target speed. The drive torque or brake torque are calculated from the target acceleration.

The invention relates to a speed control system for a motor vehicle including a unit for calculating a drive torque or brake torque as a function of a pre-definable target speed, wherein the target speed is pre-defined by the single actuation of an operable control element.
Currently, there exist a variety of speed control systems in motor vehicles that are actuated by operating a control element. Automatic speed control systems may be designed, for example, as so-called adaptive cruise control (ACC) systems.
For example, German patent document DE 43 38 098 C2 discloses a control lever, which is mounted, like a conventional blinker lever, in the region of the steering wheel and which is intended for a speed controller in a motor vehicle. To select various functions, which include, among other things, setting a target speed, retrieving a stored target speed, and turning off the speed control system, the control lever can be moved manually in directions that are perpendicular to each other.
German patent document DE 199 61 720 C2 discloses a method for controlling the speed of a motor vehicle with a drive motor and a brake, wherein the speed control is activated by the driver in order to maintain the driving speed of the vehicle at a pre-defined target speed.
The object of the invention is to provide an improved speed control system.
The invention meets this need by providing a speed control system for motor vehicles having a unit for calculating a drive torque or brake torque as a function of a pre-definable target speed, wherein the target speed is pre-defined by the single actuation of an operable control element. A sustained actuation (db) of the control element (BE) pre-defines a target acceleration (as), instead of a target speed (vs). The drive torque (Ma) or brake torque (Mb) are calculated from the target acceleration. Advantageous further developments of the invention are described and claimed herein.
The inventive speed control system for a motor vehicle includes a unit for calculating a drive torque or brake torque as a function of a pre-definable target speed, the target speed being pre-defined by the single actuation of an operable control element, wherein a sustained actuation of the control element pre-defines a target acceleration, instead of a target speed, the drive torque or brake torque being calculated from the target acceleration.
The speed control system of the invention offers the advantage that the driver may choose between a target speed input or a target acceleration input. If the driver wants to raise or reduce the current speed to a new speed value, the driver operates the control element once, or multiple times, in order to pre-define the corresponding target speed. For example, a one-time single actuation in the positive direction pre-defines a target speed that is raised or reduced by 1 km/h with respect to the current speed. Multiple single actuations pre-define a target speed that, according to the number of single actuations, is raised or reduced by multiples of 1 km/h with respect to the current speed.
If, in contrast, the driver intends to accelerate or decelerate, he may pre-define, according to the invention, a target acceleration by way of a sustained actuation of the control element. The driver's input of a target acceleration offers the additional advantage that the vehicle experiences, in a repeatable manner, the same acceleration or deceleration independently of the current load resistance. For example, when driving downhill, the driver is not surprised by an acceleration that is higher than would be the case for a deceleration input or drive input without acceleration. When pre-defining the target acceleration, a defined target acceleration is fixed directly into the vehicle's memory. Whereas when pre-defining the target speed, the acceleration is the indirect product of the difference between the target speed and the actual speed, thus the current speed. When pre-defining the target acceleration, the target speed is not pre-defined, rather the driver operates the control element as long as he wants to accelerate or decelerate the vehicle. The driver may be given the possibility of experiencing a prospective "flowing" with the traffic, where the vehicle reaction may be reproduced and controlled directly by the driver, since the driver is actively and directly tied into the control of the vehicle.
The control element may be constructed, for example, as a control lever on the steering wheel. A single actuation results from, for example, depressing or pulling once the control element for a short period of time. In contrast, a sustained actuation results from, for example, depressing or pulling the control element for a pre-defined period of time. A single actuation of the control element pre-defines, as a function of the direction of actuation, a target speed that is raised or reduced with respect to the current speed.
Similarly, a sustained actuation pre-defines a positive or negative target acceleration, as a function of the direction of actuation. The control element may also be constructed, for example, as a toggle switch, instead of a control lever.
Since, upon releasing the control element from the sustained actuation, there is no longer any suitable target speed, as a function of which the drive torque or brake torque may be calculated, once the control element is released, the current speed or a speed, which deviates by a pre-defined value from the current speed, is pre-defined in an advantageous manner as the target speed. The deviation from the current speed should deviate in terms of amount only negligibly from the current speed; and the direction should be pre-defined in such a manner that if the vehicle was accelerated beforehand, this direction is greater than the current speed; and if the vehicle was decelerated beforehand, this direction is less than the current speed. The deviation offers the advantage that the change in the acceleration or the deceleration is effected in a comfortable manner for the driver with an asymptotic transition into continuous drive.
The target acceleration may be a permanently pre-defined value. The target acceleration may be pre-defined in an advantageous manner as a function of at least one parameter. For example, the target acceleration may be pre-defined as a function of the current vehicle speed or other operating parameters of the vehicle. The higher the current vehicle speed, the smaller the target acceleration should be in terms of amount. It is also contemplated to pre-define the target acceleration, among other things, as a function of the driving style of the driver. The target acceleration may be pre-defined from a characteristic or a family of characteristics.
In calculating the drive torque or the brake torque, the load resistances, such as for a mountain trip or a valley trip or the aerodynamics of the vehicle, are considered in an advantageous manner in order to set as accurately as possible the target speed.
The control element may be operated in an advantageous manner on several control levels. Therefore, a single actuation of the control element pre-defines a control level-specific target speed; and a sustained actuation pre-defines a control level-specific target acceleration.
Control elements with several control levels are already used in the area of automatic speed control. Therefore, if, for example, the control element is operated on a first level, the target speed is raised or reduced by 1 km/h. In contrast, if the control element is operated on a second control level, the target speed is raised or reduced, for example, by 5 km/h or 10 km/h. Consequently a further development of the invention makes it also possible to pre-define a number of different target accelerations on the various control levels by use of a sustained actuation of the control element.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Speed control system and method for a motor vehicle

Bayerische Motoren Werke Aktiengesellschaft


An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire set of assertions that need to be checked out. Advantageously, bit extraction and injection is used in CSS assertion checking to permit use of relatively small registers for the assertion checking of each subset of assertions.

This invention relates to integrated circuits and, more particularly, to functional testing and debugging of integrated circuit designs.
Some present day designs of integrated circuits (ICs) comprise a plurality of module, or core, designs (and associated design layouts) that are interconnected within the integrated circuit to create a whole. Such ICs are sometimes referred to as "systems on a chip" (SoCs). The designed SoCs may include core designs that the party designing the integrated circuit has created before, core designs purchased from another party, and core designs that are created specifically for the designed SoC; sometimes is referred to as user defined logic (UDL) block. In connection with the previously created designs, it is recognized that there may exist outputs and/or inputs that are not needed for the specific SoC design undertaken, and those effectively constitute points of access of the core—in addition to the functionally employed inputs and outputs—that may be used for testing the core as well as the entirety of the SoC design.
The aforementioned Ser. No. 10/425,101 patent application discloses a beneficial design approach for SoCs, where each core is encompassed with a wrapper that includes a functionally reconfigurable module (FRM). A wrapper is a collection of elements, including circuit interface elements between essentially every input terminal of the core and circuitry outside the core, and between essentially every output terminal of the core and circuitry outside the core. The FRM can be configurably connected to any of the circuit interfaces, and can also be configured to realize any function. Spare leads are additionally included to permit connectivity from the FRM directly (i.e., not through the circuit interface elements) to circuitry outside the wrapper. The circuitry outside the core can be another wrapper, a UDL block, inputs of the IC, or outputs of the IC.
FIG. 1 depicts an arrangement in accord with the disclosure presented in the aforementioned patent application where an SoC includes core 10 that is wrapped by wrapper 11, core 20 that is wrapped by wrapper 21, and core 30 (a UDL block) that is wrapped by wrapper 31. Illustratively, core 10 has three inputs and four outputs (12, 13, 14, and 15). Core 20 has four inputs, three outputs (22, 23, and 24), and UDL 30 has three inputs and two outputs (32, and 33) that are connected to the SoC output terminals of the IC. The blocks labeled "I" are the aforementioned circuit interface elements.
Each interface element that provides a signal to a core is adapted to configurably provide either an incoming signal (the signal shown in the FIG.) or a signal provided by the associated FRM (not shown in the FIG.). Similarly, each interface element that outputs a signal from a wrapper is adapted to configurably provide either an output of the core (the signal shown in the FIG.) or a signal provided by the associated FRM (not shown in the FIG.).
In is noted that in the illustrative SoC of FIG. 1, core 20 has one output (25) that is available but is not needed for the FIG. 1 SoC design. This intends to illustrate the above-mentioned notion that an obtained core layout that had been previously designed might have inputs and/or outputs that were needed for the application for which the core was designed but in the FIG. 1 application those might not be needed.
In addition to the necessary signal connections between wrappers 11 and 21, and between wrappers 21 and 31, including spare leads, the FIG. 1 SoC includes manager circuit 40 through which control is exercised over the SoC. It accepts a test clock, a control signal, and information through a serial Scan-in input. It receives Scan-out (SO) information (serially) from the SoC via lead 42 and is adapted to output that information, as directed by control 40, on the lead SCAN OUT. In turn, subject to desired processing within manager 40, the manager applies the test clock signal to each of the wrappers, Not shown in FIG. is a clock distribution system that allows the test clock to replace the functional system clock(s). The manager 40 could be compatible with, for example, the JTAG controller specified in the "Standard Test Access Port and Boundary-Scan Architecture," IEEE Standard P1149.1, 1990.
In addition, the serial SI input of manger 40 is applied to wrapper 11. The SO output of wrapper 11 is connected to the SI input of wrapper 21. The SO output of wrapper 21 is connected to the SI input of wrapper 31, and the SO output of wrapper 31—which is the Scan-out signal of the FIG. 1 SoC—is connected to the manager 40. These connections establish a serial communication mechanism among the wrappers and the manager 40, which can be used to configure the FRMs or to send data to, and receive data from, the circuits configured in the wrappers. This communication mechanism could be compatible, for example, with the mechanism described in "Standard for Embedded Core Test" IEEE Standard P1500, 2003. Alternative communication means, such as a special-purpose debug bus, are also possible, and their nature is not essential for the disclosed innovation.
A useful technique for checking the design of integrated circuits (ICs) is called assertion checking. In assertion checking, a collection of conditions is identified that are expected to hold true at any time during the operation of a properly working SoC. The model of the SoC being tested can thus be simulated by application of various input test vectors, and its signals are checked against the collection of assertions. The signals checked by an assertion may include any internal signal. When an assertion "fires," indicating that the asserted condition that should be met is not met, simulation can stop and the party performing the testing can attempt to analyze the reason for the assertion's failure.
While assertion checking in simulation is a widely used technique, and a simulation run may use hundreds of assertions, employing assertions for debugging hardware is much more constrained.
In general, any assertion can be implemented in hardware, e.g., within the manufactured SoC, but this is a costly approach because it permanently reduces the amount of "real estate" that is available for the normal operation of the SoC. Moreover, in addition to the effective cost associated with appropriated chip "real estate" to implementing hundreds of assertions in the SoC, this solution is not flexible, since the functional problems occurring in silicon often require the implementation of new assertions.
A more economical solution involves using additional hardware to observe many internal signals, run-time programmable logic to select a subset of these, and a run-time programmable assertion logic checking the selected subset of signals, and a clock-control logic to stop the operation of the SoC when an assertion fires. Such a system is illustrated in the paper "Silicon Debug: Scan Chains Alone Are Not Enough" by Gert Jan van Rootselaar and Bart Vermeulen, published in the Proc. International Test Conf., 1999. However, this solution does not provide the desired flexibility, since new signals and new conditions to be checked cannot be added at run-time. As an aside, in this paper the assertions are referred to as "breakpoints." The described system is an example of at-speed debug, where the tested SoC is exercised in its normal operational mode, with a clock that is at the normal operational speed. The clock is not stopped while the assertions are checked, unless an assertion fires, i.e., fails.
An SoC may have several clock domains, each one having a different system clock signal. Firing of an assertion may stop one or all the functional clocks. In the following, clock stopping may refer to either case.
Usually all the functional registers of an SoC are setup so they can work as scan chains in test mode. Typically, a scan chain has a serial input (SI), a serial output (SO), and a scan-enable control input (SE). When SE is asserted, the register operates as a scan chain, otherwise data are loaded in parallel. (Other scan design techniques exists, but their operation is similar.) SE is typically shared between all registers in the same clock domain. For manufacturing test, the scan chains are separately operated to scan in test data and to scan out the captured data. The same scan chains are also used for debug—when the functional clock has been stopped as a result of an assertion firing (or for any other reason), the internal state of the hardware can be examined (manually or by software) by scanning out all the scan chains. For this operation the test clock shown in FIG. 1 as TEST CLK replaces the system clock, and all the scan chains are connected together in a single chain, connected to the pins SCAN IN and SCAN OUT of the test controller 40 of FIG. 1. Scanning back in the scanned-out state allows restoring the state to restart the normal operation from the last state; the scan-out and the scan-in operations may proceed concurrently by connecting the scan-out pin back to the scan-in pin to achieve a circular scan. If desired, the scanned-out state can be modified before the scan-in, so that the normal operation will restart from a different state. This mode of debug is called single-step debug.
Single-step debug is typically done manually under user control only at several points during the test, because performing scan-out and scan-in operation after every test vector would require too much time. To illustrate, if the test has 100,000 vectors, and the SoC has 500,000 flip-flops, and the test clock runs at 10 MHz, doing a full-scan dump at every cycle would make the entire test run in about two hours. Hence with the current state of the art, one cannot check assertions involving flip-flops on scan-chains, unless these flip-flops are made directly observable (allowing checking through at-speed assertion checking).

Assertion checking using two or more cores


The invention relates to a Bismaleimide-Triazine resin (BT resin ) and production method thereof and in particular, a series of novel BT resin prepared by reacting a novel bismaleimide with various aromatic cyanate esters. By combining said novel bismaleimide monomer with various proportions of cyanate esters having different structures, BT resins having various processing temperature conditions can be formulated, which, after polymerizing and crosslinking, can provide materials with various thermal stability, dielectric constants, and mechanical properties for various applications.

1. Field of the Invention
The invention relates to a bismaleimide-triazine resin and a production method thereof and in particular, to a series of novel BT resins prepared by reacting a novel bismaleimide monomer with various aromatic cyanate esters.
2. Description of the prior art
There are not so many types of BT resins known in the art and those are made predominantly by combining diphenylmethane bismaleimide with bisphenol A cyanate resin in various mole ratios. The present invention consists of preparing a series of novel BT resins by using novel bismaleimides with various aromatic cyanate esters.
U.S. Pat. No. 4,110,364 (Mitsubishi, Japan, 1978 ), disclosed a BT resin synthesized from bismaleimide and cyanate ester. As shown in FIG. 1, cyanate ester itself can be cyclotrimerized in to a triazine structure (10), or it can be copolymerized with a maleimide to form a pyrimidine structure(11), where R1 in FIG. 1 is as shown in FIG. 2, R2 is as shown in FIG. 3, and where R in FIG. 2 and 3 may be H, lower alkyl group (C1-C7 ), cycloalkyl(C4-C7 ), phenyl and the like, and m=0-4.
BT resin has excellent elevated temperature characteristics, solvent resistance, low water absorption, and low dielectric constant. Such resin compositions can be blended with other thermosetting resins and other reactive diluents such as o-diallyl phthalate, triallyl cyanurate or triallyl isocyanurate, to modify such BT resin.
Many BT resins known in the art are made predominantly from diphenylmethane bismaleimide and bisphenol A cyanate resin in various proportions. BT resins comprise solid, liquid and solution types, are applicable in a variety of processing uses such as laminating, preformed insulating sheet structural materials, coating, filling and the like, and can be used in multi-layer printed circuit boards and as encapsulants.

Bismaleimide-triazine resin and production method thereof

National Science Council of Republic of China


A telecommunications system includes a packet based network. The system includes a packet ingress node for packets having a QOS in communication with the packet based network. The system includes an ATM ingress node for an ATM network. The ATM ingress node receiving the packets from the packet ingress node through the packet based network, segmenting the packets into cells and identifying the QOS associated with each cell. The system includes an ATM network in communication with the ATM ingress node. The system includes an ATM egress node which receives cells from the ATM ingress nodes. The ATM egress node in communication with the ATM network. The ATM egress node reassembles the cells back into the packets. The ATM egress node in communication with the packet based network. The system includes a plurality of VCs corresponding with QOS between the ATM ingress node and the ATM egress node through the ATM network. The ATM ingress node sending each cell to the ATM egress node along the VCs whose QOS corresponds to the QOS of each cell. The system includes a packet egress node for the packets in communication with the ATM egress node through the packet based network, which receives the packets from the ATM egress node. A method for sending packets.

More and more network service providers are using MPLS in their next generation networks. MPLS is seen as a convergence technology where IP, Frame Relay, ATM can be carried over a single network thereby resulting in savings in operating expenses. Service providers are also using MPLS for providing new services such as L3 VPNs [E. Rosen, Y. Rekhter, "BGP/MPLS VPNs", Internet Draft, draft-ietf-13vpn-rfc2547bis-01.txt, September 2003, incorporated by reference herein].
One of the main strengths of MPLS as opposed to plain IP is its rich Traffic Management/Traffic Engineering (TM/TE) features [RFC3031: Multiprotocol Label Switching Architecture, IETF Standards Track RFC, January 2001; RFC2702: Requirements for Traffic Engineering over MPLS, IETF Standards Track RFC, September 1999, both of which are incorporated by reference herein]. One of the important MPLS TM features is MPLS DiffServ [RFC3270: MPLS Support of Diff-Serv, IETF Standards Track RFC, May 2002; RFC3564: Requirements for Support of Differentiated Services-aware MPLS Traffic Engineering, IETF Informational RFC, July 2003, both of which are incorporated by reference herein]. Via MPLS, it is possible to set up a tunnel (Label Switched Path—LSP) between two hops that does not follow the traditional IP next-hop routing. MPLS DiffServ allows you to reserve bandwidth for LSPS, to define per-hob-behavior (PHB) treatment for packets using this LSP, etc. [RFC3270: MPLS Support of Diff-Serv, IETF Standards Track RFC, May 2002; RFC2475: An Architecture for Differentiated Services, IETF Informational RFC, December 1998; RFC3260: New Terminology and Clarifications for Diffserv, IETF Informational RFC, April 2002, all of which are incorporated by reference herein.]
There are two types of LSPs in MPLS DiffServ: L-LSP and E-LSP. In the case of L-LSP, the PHB treatment of a packet is inferred from the label value whereas in E-LSP, the treatment is derived from the EXP encoding within the shim header. E-LSPs allows up to 8 different PHBs per LSP (since EXP is a 3-bit wide field [RFC3021: MPLS Label Stack Encoding, IETF Standards Track RFC, January 2001, incorporated by reference herein]). In general, E-LSPs are more widely deployed than L-LSPs.
Various works has been done in the past to support MPLS over ATM. RFC3035 [RFC3035: MPLS using LDP and ATM VC Switching, IETF Standards Track RFC, January 2001, incorporated by reference herein] introduces the concept of Label-Controlled ATM (LC-ATM) where the top label of an LSP is encoded within the Virtual Path/Virtual Circuit Identifier (VPI/VCI) of the ATM cell header. These VPI/VCI values are exchanged by MPLS Label Distribution Protocols like RSVP-TE and LDP [RFC3035: MPLS using LDP and ATM VC Switching, IETF Standards Track RFC, January 2001; RFC3209: Extensions to RSVP for LSP Tunnels, IETF Standards Track RFC, December 2001; RFC3036: LDP Specification, IETF Standards Track RFC, January 2001, all of which are incorporated by reference herein]. RFC3038 [RFC3038: VCID Notification over ATM link for LDP, IETF Standards Track RFC, January 2001, incorporated by reference herein] proposes a technique to associate a unique end-to-end identifier (VCID) with ATM Virtual Circuits (VCs), which can be used to bind MPLS "streams" to existing ATM VCs. In addition to these, Ships-In-Night (SIN) proposes to have both ATM and MPLS control planes working side by side on the same switch without any interaction between them. The work is also underway to have a full MPLS/ATM control plane interworking (e.g., see ATM-MPLS Network Interworking Signaling Specification 1.0, ATM Forum Standard, August 2003, incorporated by reference herein).
In all these approaches, supporting L-LSPs over ATM is straightforward. You usually have one L-LSP mapped into an ATM VC with an appropriate queuing/scheduling treatment to match L-LSPs PHB. RFC3270 [RFC3270: MPLS Support of Diff-Serv, IETF Standards Track RFC, May 2002, incorporated by reference herein] presents protocol extensions to support this.
There is, however, no easy way of supporting E-LSPs over LC-ATM interfaces and is considered unsupported by RFC3270 [RFC3270: MPLS Support of Diff-Serv, IETF Standards Track RFC, May 2002, incorporated by reference herein]. Since EXP bits are stored within the packet that is segmented into cells at the ingress ATM node of the network, transit ATM switches have no idea which PHB to apply to for an incoming cell. To further complicate this situation, most of the existing legacy ATM switches give only one queuing/scheduling treatment to cells belonging to a single VC.
To overcome this problem, the present invention provides a novel solution where E-LSPs can be supported over legacy ATM switches. This solution does not require any new hardware features and can be achieved just by a software upgrade. Only basic ATM functionality support at the hardware such as switching based on standard ATM header and support for standard ATM service classes [ATM Forum Standards.Available: http://www.atmforum.com/standards/approved.html; D. E. McDysan, D. L. Spohn, ATM: Theory and Applications, McGraw-Hill Series on Computer Communications, both of which are incorporated by reference herein] is assumed. This is a cost effective way of supporting E-LSPs over existing legacy ATM networks without any new investment in hardware for network service providers.
The problems in supporting E-LSPs over ATM can be summarized as follows:                1. How to determine PHB treatment of cells in a VC, given that the corresponding EXP encoding is not known, and        2. How to give different PHB treatments (i.e., scheduling, queuing) to cells belonging to same VC.
To address the first problem, one can think of somehow encoding EXP bits to ATM header. Possible solutions for this approach could be (refer to ATM Forum Standards. Available: http://www.atmforum.com/standards/approved.html; D. E. McDysan, D. L. Spohn, ATM: Theory and Applications, McGraw-Hill Series on Computer Communications, both of which are incorporated by reference herein, for ATM header description and definitions of CLP, PTI, GFC, UNI/NNI, and other ATM related terms):                Using certain PTI values along with CLP bit to carry EXP encoding information, or        Using top two bits of GFC (in UNI interface)/VPI (at NNI interface) along with CLP bit to encode EXP bits, or        Some other cell-header based encoding technique.
In all these methods, one will be changing the meaning of ATM cell header and restricting the underlying ATM functionality (e.g., certain PTI or GFC/VPI values cannot be used). They all also imply that one will need new ATM switching hardware to support new header formats.
As another alternative solution, one can think of having a SAR (segmentation/reassembly) at each node. Once the cells are reassembled, EXP bits can be recovered from the underlying packet. There could be some ATM switches capable of doing this. However, a vast majority of the existing hardware platforms will not support SAR at every node. Such a method will also increase the jitter/delay unnecessarily within the ATM network.
None of these possible solutions address the second problem. For it, one will need specialized ATM hardware where queuing/scheduling decisions are made at cell level (not at VC level). (This problem can be resolved if SAR is done at every node and the scheduling/queuing is done at packet level, not at cell level. However, this solution still needs specialized hardware and SAR is not typical on ATM switches as mentioned before.) Additionally, this ATM scheduling/queuing hardware should be sophisticated enough to ensure cells from different packets within the same VC are not interleaved (i.e., scheduling of traffic within VCs should be done at individual packet boundaries). (Please notice that this will increase delay/jitter since all of the cells belonging to a packet will be transmitted all at once, in a bursty fashion. Additionally, incoming traffic will be buffered at least until the last cell of a packet is received even when there is no congestion in the network.) There are few existing ATM switches that can provide this level of sophistication.

Method and system for sending E-LSP packets having QoS across a cell ATM based network


The invention relates to a fiber-optic pressure detector comprising a mat having an optical fiber running therethrough along a path with no fiber-fiber crossovers, which fiber is associated with a light source and a light receiver. The light receiver receives light flux transmitted by the optical fiber from the source, thereby showing up any changes to which the flux is subjected because of deformation to the optical fiber caused by a pressure force being applied to the mat, thereby enabling said force to be detected. The optical fiber is mounted on a support sheet made of plastic, and it passes back-and-forth through the support sheet via through holes, said support sheet being sandwiched between two other sheets of greater or lesser rigidity depending on the sensitivity desired for the detector mat.

A detector mat of this kind is known in which the optical fiber is directly interposed between the two main sheets, one of which provides a furrow for receiving the optical fiber, for the purpose of guiding the fiber along the path which it is to follow.
Such a structure is difficult to implement and leads to a manufacturing cost that is not cheap.
In addition, the known detector mat is designed so that the optical fiber never comes into contact with sharp-edged elements, and thus suffers deformation only by being curved with a large radius of curvature (greater by several order of magnitudes than the diameter of the fiber) and also never suffers from microcurvature on such sharp edges, which could damage the integrity of the optical fiber. Unfortunately, although the fiber is thus protected from localized mechanical damage that could shorten its life, this is achieved at the cost of reducing its sensitivity because of the absence of any microcurvatures that could add their contribution to generating variations in light flux. That detector mat therefore provides sensitivity which is poor, and insufficient for reliably detecting small pressure forces.

Sandwiched fiber-optic pressure detector


A context fusing system and methodology includes the steps of receiving context data from a plurality of information sources; computing a quality measure for each input context value; organizing context values into one or more clusters, and assigning a single context value and a single quality measure to each cluster; and, selecting one or more clusters according to one or more criteria and aggregating the context values and quality measures of selected clusters to generate a single context value and single quality measure. The single context value and single quality measure are usable by a context aware application to avoid conflict and ambiguity among different information sources providing the context data.

1. Field of the Invention
The present invention relates generally to context-aware applications for computer systems, and more particularly to a novel context fusing system and methodology for supporting context-aware devices and applications.
2. Description of the Prior Art
Pervasive computing applications are increasingly relying on the context of the user whom the application is designed to support. Contextual information is derived from a variety of sources and enables the application to provide the user with qualitatively better service. For instance, context awareness can be seen as key to such pervasive computing features as personalized access, intention inference, resource opportunism, and system proactivity. The net result of improved context awareness is a reduced demand for human attention by the application.
Context awareness is made possible by the ubiquity of sensors of different kinds. For instance, several sources of location information are typically available—consider the rapidly expanding use of cellular phones (some of which are already enabled for location tracking in order to help emergency rescue teams), GPS receivers, wireless LAN computers, wireless PDAs such as the Blackberry device, electronic calendars, and active badges. Despite this abundance of contextual information, one key problem remains: resolution of conflicts and ambiguities among different information sources.
As a motivating example, the following scenario is considered: A user's car is equipped with a GPS tracking device which periodically beacons the car's location to a central server. The user also carries a wireless PDA which beacons its location to the same server. Now, if the car was last reported seen in "San Francisco" 5 minutes ago and the PDA was last reported seen in "San Jose" 10 minutes ago, which location report should the system pick as the most current and accurate? In other words, which context is the user currently in? Surely the user cannot have moved from San Jose to San Francisco in 5 minutes.
In Paul Castro and Richard Muntz, "Managing Context Data for Smart Spaces," IEEE Personal Communications, Vol. 7, No. 5, (October 2000), pp. 44-46, a context fusion service that uses evidential reasoning techniques, is described. However, this service has a number of disadvantages. First, it works with a pre-determined set of context sources only and does not support dynamically added sources. Second, it requires a separate training phase in order to obtain the probability distribution of input context values. Third, both input and output context values must be quantized into discrete values.
Asim Smailagic and David Kogan, "Location Sensing and Privacy in a Context Aware Computing Environment," IEEE Wireless Communications, October 2002, teaches a method for fusing location data in a wireless LAN environment based on a combination of triangulation and mapping. The method also requires a pre-determination of context (location) sources and a separate training phase. In addition, it handles homogeneous location data only.
Another method for fusing location data is described in Jussi Myllymaki and Stefan Edlund, "Location Aggregation from Multiple Sources," Proceedings of International Conference on Mobile Data Management, Singapore, 2002. The method ranks location reports from different sources and selects the most probable one based on factors such as time, user associativity and device mobility. Besides being location-specific, this method does not consider the relationships between input values and is not able to improve the precision of input values.
Therefore, a need exists for a general fusion technique that can accurately fuse context data from a dynamic set of sources.
It would be highly desirable to provide a context fusion system and software architecture for supporting pervasive computing devices.

Method and apparatus for fusing context data

International Business Machines Corporation


In a rotor portion, a magnet formed in a cylindrical shape, a first magnet holder that holds an impeller-attachment-portion-side end portion of the magnet, a second magnet holder that holds a magnetic-pole-position-detection-element-side end portion of the magnet, a back yoke disposed inside the magnet, a sleeve bearing disposed inside the back yoke, and a position detection magnet that is provided on a surface of the second magnet holder at a side opposite to the side at which the magnet is attached and allows a magnetic flux of the position detection magnet to be detected by the magnetic-pole-position detection element are assembled integrally together with a thermoplastic resin, and the impeller attachment portion is formed of the thermoplastic resin.

Pumps including a brushless motor which includes a cylindrical magnet that is externally coated with resin and a Hall element that detects positions of magnetic poles of the magnet have been proposed. The brushless motor generates a rotating magnetic field by applying a current to coils in accordance with a signal from the Hall element that has detected the positions of the magnetic poles of the magnet (see, for example, Patent Literature 1).

Pump, refrigeration cycle apparatus, and method for manufacturing pump


A bonding layer 3 is formed over a piezoelectric material substrate, and the bonding layer is made of one or more materials selected from the group consisting of silicon nitride, aluminum nitride, alumina, tantalum pentoxide, mullite, niobium pentoxide and titanium oxide. A neutralized beam is irradiated onto a surface of the bonding layer and a surface of a supporting body to activate the surface of the bonding layer and the surface of the supporting body. The surface of the bonding layer and the surface of the supporting body are bonded by direct bonding.

A surface acoustic wave device is known which functions as a filter device or oscillator used in mobile phones or the like and an acoustic wave device such as a lamb wave device or film bulk acoustic resonator (FBAR) using a piezoelectric thin film. As such an acoustic wave device, a device produced by adhering a supporting body and a piezoelectric substrate propagating a surface acoustic wave and by providing interdigitated electrodes capable of oscillating the surface acoustic wave on a surface of the piezoelectric substrate is known. By adhering the supporting body whose thermal expansion coefficient is lower than that of the piezoelectric substrate onto the piezoelectric substrate, the change of size of the piezoelectric substrate responsive to a temperature change is reduced so that the change of the frequency characteristics as the surface acoustic wave device is reduced.
For example, it is proposed, in patent document 1, a surface acoustic wave device having a structure produced by adhering a piezoelectric substrate and silicon substrate with an adhesive layer composed of an epoxy adhering agent.
Here, it is known that, in bonding a piezoelectric substrate and silicon substrate, a silicon oxide film is formed on a surface of the piezoelectric substrate, and a silicon substrate and the piezoelectric substrate are bonded through the silicon oxide film (patent document 2). In the bonding step, a plasma beam is irradiated onto the surfaces of the silicon oxide film and silicon substrate to activate the surfaces, followed by the direct bonding (plasma activation method).
Further, it is known that a surface of the piezoelectric substrate is made a roughened surface, a filler layer is provided on the roughened surface to provide a flattened surface, and the filler layer is adhered onto a silicon substrate through an adhering layer (patent document 3). According to this method, an epoxy-based or acryl-based resin is used for the filler layer and adhering layer, and the bonding surface of the piezoelectric substrate is made the roughened surface to reduce the reflection of bulk waves and to reduce spurious waves. Further, as the adhesion is performed after the roughened surface is filled and flattened, air bubbles are hardly included in the adhering layer.