The present invention relates to communications systems incorporating peripheral devices such as a push-to-talk (PTT) or similar and interface cables to connect these to a headset and/or a communication device such as a man worn two-way radio, vehicle intercom system, mobile phone, etc. In particular, the invention relates to such interface cable having an integrated functionality. The basic idea of the invention is to use an interface between a first and a second device in a voice communication system, which interface is specific to the second device and holds digital information allowing the first device to identify or adapt to the second device. This allows the first device to automatically adapt its settings and/or functionality to, and thus to function with, several different second devices without any need for updating, re-configuration, or user intervention. Thus the first device can be hot swapped or hot plugged with different second devices simply by using a cable specific to each particular second device.

In digital data communication between computers and electronic devices, the connection as well as the discovery of a new device in a system has become subject to a number of possible interface standards such as USB and FireWire specifying both the connector of the interface as well as the communications protocol to be used. These standards have led to extensive possibilities for hot swapping (replacing components without system interruption) and hot plugging (adding components to expand the system without system interruption).
For voice communication devices such as radios, intercoms, or phones, the interfacing with peripheral devices (here e.g. headsets or push-to-talk (PTT) devices) has been designed and produced specifically to one brand and type of device. This means that the user is "locked" in his one configuration for the life span of the equipment. If another radio or mobile phone is required, a new peripheral device is typically also needed. Hence, hot swapping, or indeed swapping at all, is not possible.
With the increasing computing power, new functions and requirements have been added to many voice communication devices which means that having just as standard connector (plug/socket) will not suffice, as many devices have different ways of interfacing (connection detection method, impedances, signal levels, control signals, etc.). Thus, a headset or a PTT device will have to be adapted to whatever radio system it is to be connected to, otherwise the system will not operate satisfactory and communication will not be clear and un-distorted.
INVISIO (www.invisio.dk) has provided a "hot swap cable" system utilizing the fact that a special cable is typically required between the PTT and the radio, since each radio has special interface connectors. The PTT can identify the cable and thereby the brand/type/model to which particular radio it is connected, and can adjust its settings to match the radios requirements. Even in this solution, the PTT can only match specifications of radios known beforehand.
Other technical fields where peripheral devices from a range of producers are to be connected and where no standard has yet been agreed upon face similar challenges.
Patent specification U.S. Pat. No. 8,086,781 discloses an intermediate device connecting to a host device, e.g. a media player, mobile phone, PDA, handheld computer, laptop computer, desktop computer, etc., and an accessory, e.g. a headset with earphone and microphone, stereo headphones, microphone, remote control, keyboard, mouse, etc.
The intermediate device function more or less like a docking station and e.g. converts commands from a 'host-side' command protocol into an 'accessory-side' command protocol or the other way around and thus translates between the different formats. It does not disclose that information relating to identification of and/or settings for the host device is stored in the intermediate device and does not disclose that such information is transmitted to the accessory to enable it to communicate with the host device.
The intermediate device connects with the host device and accessory using standardised connectors and procedure e.g. like USB or FireWire and is not a device-specific interface specific to a particular host device.
Hence, an improved way of connecting peripherals to components would be advantageous in fields where there are no standards for connection and communication, e.g. like there otherwise is for plug and play interfaces such as USB or FireWire. In particular, a way of connecting peripherals that allows automatic configuration of the peripheral to the component would be advantageous.


Sports glove drying devices. In one embodiment, an accessory allows attachment of gloves to a vehicle. The aerodynamic drag of the wind against the vehicle during the vehicle""s movement speeds up the drying of the gloves. In a further embodiment, an accessory for adhering to a vehicle, existing tags or so forth, allowing any surface to be utilized for drying the gloves. In further embodiments, the accessory includes a receptacle for interchanging promotional material therein. In a preferred embodiment, the accessories are used with golf gloves and can be attached to a golf cart. In alternate embodiments, the accessories can be used with any other sporting activity using gloves, such as bicycling, baseball, or so forth.

The present invention relates to devices for drying gloves used in sporting activities, such as golf, bicycling, and so forth.
Currently, specialty gloves are used in a variety of sporting activities. Golfers, for example, use special golfing gloves during play to improve their grip upon golf clubs. Similarly, bicyclers also utilize gloves during races to more firmly and comfortably grasp their bicycle""s handlebars. Although these two sports are described for illustration purposes, athletes likewise utilize sporting gloves to improve their play and comfort in a variety of other sports as well.
During the course of the athletic event, the gloves frequently become wet from the sweat on the athlete""s hands. Upon placement of the glove in the athlete""s bag, that wet or moist glove is prone to become stiff, uncomfortable, unpleasant, crumpled and/or wrinkled, negatively impacting upon the tactile sensitivity of the hand, ruining the appearance of the glove, and making it more difficult to place the glove on the hand in subsequent uses.
Several devices have been provided in the art to address this problem with respect to golf gloves, to dry the golf gloves of an athlete. U.S. Pat. No. 5,177,881 issued on Jan. 12, 1993 to Moore (xe2x80x9cthe Moore patentxe2x80x9d), and U.S. Pat. No. 5,86,925 issued on Feb. 2, 1999 to McGee (xe2x80x9cthe McGee patentxe2x80x9d) both disclose accessory devices for facilitating the drying of golf gloves during use. The McGee patent, for example, discloses a combined xe2x80x9cbag tagxe2x80x9d and glove drying apparatus which allows golfers to hang their gloves from the outside of a golf bag during play. The Moore patent discloses an accessory device for attachment of a golf glove directly to the golfer him or herself, either to the belt or clothing. Each of these devices, however, are limited in their purpose and utility, including the devices they can be attached to, and the rate at which the glove can be dried.
It is an object of the present invention to provide an improved device for drying sports gloves.
It is a further object of the present invention to provide devices for drying sports gloves which aerodynamically utilize the movement of a vehicle to improve the speed and efficiency of drying the glove.
It is a further object of the present invention to provide devices for drying sports gloves which can be integrated with existing tags and sports accessory devices.
It is a further object of the invention to provide a new form of sports advertising, including a new method and medium for marketing sports items, and for conveying advertising and promotional information.
The present invention can be utilized in conjunction with any type of gloves desired, whether gloves used in golf, baseball, football, soccer, fencing, weightlifting, scuba diving, or so forth.
Further objects of the invention will become apparent in conjunction with the disclosure herein.
In accordance with the present invention, devices are provided enhancing the ability of an athlete to quickly air dry his or her gloves after use.
In one embodiment of the invention, attachment devices are provided which allow the gloves to be attached to a moving vehicle (such as a golf cart or bicycle), exploiting the aerodynamic drag of the wind against the glove during movement of the vehicle to improve the speed and efficiency of drying.
In a preferred embodiment of the present invention, improvements are provided enhancing the ability of an athlete to quickly dry his or her gloves by attachment of the glove to a vehicle, while also providing promotional information from a sponsor or other entity. In one embodiment, the gloves can be attached to a golf art. In an alternate embodiment, a cyclist""s gloves can be attached to his or her bicycle. In further alternate embodiments, the invention can be used by athletes in other sports, whether soccer, basketball, baseball, or so forth, wherein the athlete attaches his or her gloves to an object, preferably to a moving vehicle, or to an existing tag, or any other surface to air dry the gloves.
Further in accordance with the invention, a method is provided for drying sports gloves by using a moving vehicle. In a preferred embodiment, a method is provided for drying sports gloves by using a golfer""s golf cart.
In a further embodiment of the invention, attachment devices are provided which allow existing tags of sports facilities to be readily modified for attachment of a glove thereto without needing replacement of the entire tag. In a further embodiment, the attachment device also provides promotional information from a sponsor or other entity.
Further objects and features of the invention will become apparent in conjunction with the disclosure herein.


An industry standard width composite paper web includes one layer comprising a plurality of narrow web portions derived from trim rolls of paper which are laminated to a second carrier web of the selected standard width. In an alternate embodiment, the carrier web itself may comprise a plurality of narrow trim roll web portions. The web portions comprising each layer may be spaced from one another slightly, and the gaps between web portions in both layers must offset laterally with respect to one another to maintain composite web integrity.

The present invention relates to composite material webs and, more particularly, to a composite web of standard width made by joining a plurality of narrower width trim roll webs without a lateral overlap in the adjacent edges of the trim roll webs.
In the many processes of paper converting, standard width rolls of paper are often slit longitudinally to narrower widths for utilization in the manufacture of products requiring the narrower width paper. For example, a standard 96" (2400 mm) roll may be slit to provide a required 60" (1500 mm) web. This process to provide the required narrower width web leaves a 36" (900 mm) roll which is commonly referred to as a "trim roll". Unless there is a coincident requirement for a product utilizing a web width equal to the trim roll, the trim roll paper has little value and often such rolls are merely recycled. Trim rolls are, therefore, available on the open market at prices significantly below the price of standard width rolls.
Paper is the primary cost item in many if not most items produced in the paper converting industry, such as the manufacture of corrugated paperboard. Therefore, a process for utilizing trim roll paper in any paper converting process would be highly advantageous. However, the difficulty faced in adapting trim roll paper webs to converting processes is that production equipment is typically made to handle standard widths. Also, the availability of trim roll paper web materials is not dependable and it cannot be predicted with any certainty what trim roll widths will be available in a given area at a particular time.
It is known in the prior art to join the webs of two or more trim rolls by joining their adjacent lateral edges with an overlapping splice as shown in prior art FIGS. 1 and 2. Trim roll webs 10 and 11 are positioned with their adjacent edges 12 overlapping. Glue is applied to the adjacent edges in the area of the overlap to provide a longitudinal splice 13. This arrangement produces a web having a double thickness portion at the splice which makes such a web completely unsuitable for most converting operations, including most applications in the production of corrugated paperboard.


Cross-linked polymeric gels or films are prepared by dissolving in a suitable solvent a linear polymer or polymers at least one of which is predominantly (at least 80%) made from monomers containing pendant amidocarbonyl or oxycarbonyl groups. For the cross-linking reaction are present either hydroxyl groups, present as either pendant groups from the polymer, or as low molecular weight polyols; or amino groups, present as either pendant groups from the polymer, or as low molecular weight diamines or polyamines. Either no catalyst is present or a strongly acidic catalyst (which may also be a pendant group on a polymer) is used. The solvent is removed by coagulation and/or drying and the dry material is heat-cured, thus cross-linking and insolubilizing the polymer or polymers.

The present invention relates to novel solid polymeric compositions, their preparation and cross-linking, and their uses.
A well-established method for improving the physical properties and solvent resistance of linear polymers is cross-linking, in which the individual polymer chains are joined at many points to yield an interconnected network. The cross-links may be ionic in character, as in complexes of poly-acids with poly-bases, but covalent or chemical cross-linking is stronger, more resistant to hydrolysis, and more versatile in its applications.
The most common way of achieving covalent cross-linking is to use a polyfunctional monomer in the polymerization reaction itself (e.g., divinylbenzene together with styrene). Since cross-linked polymers cannot be dissolved, melted or cast, the polymerization must be carried out in the final physical shape required. Problems often arise in the preparation of films and membranes when catalysts must be introduced or inhibitors such as oxygen excluded from the polymerization reaction. Furthermore, the monomers themselves are often too toxic, volatile, or fluid to be conveniently processed in this manner. All of these factors make the manufacturing process difficult and costly.
It is thus often preferably to prepare a linear polymer or polymers, dissolve them in an appropriate solvent, spray or cast in the final form required, and only then introduce the cross-links. A familiar example of such post-cross-linking is the vulcanization of rubber, in which linear polyisoprene is mixed with sulfur, molded and then heat-cured. Another example is the cross-linking of various unsaturated polymers by light to produce plates for photoengraving.
Although many polymers will form loosely cross-linked gels upon heating, the mechanism is often obscure and the cross-linking difficult to predict or control. The present invention provides a post-cross-linking method unique in its mechanism, in the range of polymers to which it applies, an in its practicality and wide range of application. It is believed to proceed via the alcoholysis of pendant amide or ester groups on the polymer with hydroxyl groups to produce a new ester linkage between polymer chains, or the amidolysis (or aminolysis) of pendant amide or ester groups on the polymer with amino groups to produce a new amide linkage between polymer chains, or the reaction of pendant carboxyl groups on the polymer with hydroxyl or amino groups to produce new ester or amid linkages. Depending on the nature of the reaction and the leaving group involved, the use of an acid or base catalyst or not catalyst at all is employed to obtain optimal cross-linking.
Alcoholysis or amides and esters is a well-known reaction in the organic chemistry of small molecules, where it generally is run in solution at reflux temperature with strong acid or base catalysts. It is one of several mechanisms postulated by Kopecek and Bazilova to account for unusually high molecular weights obtained in the solution polymerization of N-(2-hydroxypropyl) methacrylamide (European Polymer Jornal, 1973, vol. 9, pp. 10-11.) These authors considered only the possibility of dimerization, not actual cross-linking, and did not report any insolubilization taking place. The unusual feature of the alcoholysis, aminolysis and transamidation reactions described in this invention is their occurrence in the solid state in the absence of solvent, a phenomenon entirely unexpected and heretofore unreported.
Similarly, amidolysis of amides and esters is a well known reaction in the organic chemistry of small molecules, generally performed at elevated temperatures, sometimes with a base catalyst, other times with an acid catalyst or no catalyst at all depending on the nature of the solvent and the leaving group. The novel post-cross-linking techniques taught by this invention have many unique advantages, particularly in the manufacture of synthetic membranes. Conventional membranes for reverse osmosis (RO) and ultrafiltration (UF) are made of polymers that are insoluble in the fluid acted on by the membrane (water, in most cases). Typically, a linear polyamide, polysulfone, or cellulose acetate is cast from an organic solvent and coagulated in water. Although such membranes are rigid and physically strong, they are hydrophobic in nature and tend to foul through adsorption of hydrophobic particles and solutes in the feed stream. Such fouling is a major problem in industrial use of membranes, making frequent cleaning or costly pretreatment necessary.
Strongly hydrophilic polymers, particular those where in at least 80% of their constituent units are highly polar so the linear polymer is highly soluble in water, which include those having a fixed positive or negative charge on each unit or an uncharged species with a similarly high affinity for water such as acrylamide, have been shown to resist such adsorptive fouling. However, they either dissolve in water or, unless substantially cross-linked, form a soft gel. Useful membranes may be formed of such polymers only by a high degree of cross-linking, so they swell not more than 3-5 times by weight when soaked in water. Since the pore structure of such membranes is generally created by coagulation and since monomers are essentially uncoagulable, the best practical route is post-cross-linking of the coagulated linear polymer. Using the techniques taught by this invention, highly cross-linked UF membranes of controlled porosity may be cast from very hydrophilic polymers. The intricate pore structure of these coagulated membranes is preserved by solid state post-cross-linking. Furthermore, charged functionalities such as sulfonate or quaternary ammonium may be incorporated to yield a cross-linked interpolymer membrane of the type described by Gregor (U.S. Pat. N. 3,808,305), where the fixed charges serve to reject charged colloidal particles and, to a lesser extent, dissolved salts.
A typical and commonly employed hydrophilic support medium is cross-linked polyacrylamide (PAM) beads of different sizes and different degrees of cross-linking, the latter acting to control pore size. PAM contains a hydrocarbon skeletion to which are attached pendant amidocarbonyl groups which contain an amide ammonia nitrogen, one readily replaced by certain other nitrogen compounds, thus permitting the formation of several derivatives having useful properties. A typical, earlier study by Inman and Dintzis (Biochemistry, 1969, vol. 8, pp. 4074-4082.) showed that commercially available beads made of cross-linked copolymers of acrylamide and N, N'-methylenebisacrylamide could be treated by several different reactions to make useful products. These authors performed the direct aminoethylation of the beads as well as the preparation of a number of derivatives from these beads including those of the: hydrazide; trinitrophenyl; 2,4 dinitrosophenylaminoethyl; succinylhydrazide; sulfoethyl; p-hydroxyphenethyl. Also, these authors found it was possible to effect the coupling of primary amines via the general acyl azide procedure employing, in this case, the hydrazide derivative. These authors also achieved coupling to proteins such as to serum albumin via the acyl azide reaction, and to trypsin via the treatment of the hydrazide derivative with cold nitrous acid, followed by treatment with a suitable solution of trypsin. These authors also converted the aminoethyl derivative of PAM with p-nitrobenzoylazide, followed by triethylamine and washing with DMF to form the p-nitrobenzamidoethyl derivative which was then converted to the p-aminobenzamidoethyl derivative. The latter, after treatment with nitrous acid was employed for the coupling of bovine serum albumin via the diazonium intermediate. These authors then employed some of these derivatives as immobilized enzymes and as immunoadsorbents.
The materials which can be prepared by the teachings of the subject invention constitute, particularly useful and powerful tools for the techniques of modern biochemistry and molecular biology. Often these require a sequential and laborious laboratory procedure which usually must be carried out over a period of several days. Often one starts with substantial quantities of material, but very soon this is reduced to a dilute solution containing a small amount of material, of which a very small fraction is the desired component. The classical biochemical techniques which involve salt precipitation, desalting and successive column chromatography, with a final concentration often achieved by freeze-drying and subsequent procedures, results in both an extremely laborious and time-consuming procedure and usually a loss or denaturization of the very substance which is desired as an end product of the entire process.
As a typical example, in the isolation of transcription factors, one first usually uses a large column which can be cross-linked heparin, .alpha.hydroxy-apetite or a phosphocellulose, for the purpose of concentrating the DNA binding proteins which have an affinity for these columns. The next step is to elute the active material, usually by the use of different salt gradients and test each eluted fraction for specific activity. Once an active fraction is isolated, it can be separated by using gel permeation chromatography to visualise the amount and approximate molecular weight of the protein in that fraction, and finally a certain band is isolated which contains substantial amounts of the activity of the proteins which constitute a transcription factor. Since none of these preparatory procedures produces a single band of the desired, purified protein, in virtually all circumstances the final purification procedure required consists of growing antibodies to the protein desired and employing these antibodies in an affinity chromatography system to finally obtain the pure protein. Since a desired component is a low molecular weight material such as a polypeptide present in a group of highly similar polypeptides, the problem is a particularly difficult one.
All of these procedures, involving as they do for the most part hydrophobic materials or surfaces to which the desired proteins may be adsorbed and lost, suffer from that disadvantage.

Homopolymers and copolymers of acrylamide N-substituted acrylamide or N-substituted methacrylamide solid state cross-linked with polyamines or polyols


A process for renewing the refractory lining of a ladle for casting steel and of similar metallurgical vessels. While the ladle (10) is still hot, the slag (S) still adhering to the inner surface (26) is melted off from the remaining lining (2) with the aid of a high-temperature burner (9) operating under reducing conditions and allowed to run out of the ladle (10) in the molten condition. After cooling, the glassy surface of the remaining lining (2) is roughened. The new refractory lining (30) is then applied by casting, with the aid of a template.

1. Field of the Invention
The invention relates to a process for renewing a refractory lining in a ladle and an apparatus for accomplishing the process.
2. Description of the Related Art
To an increasing extent nowadays, metallurgical vessels are no longer being lined (faced) with refractory bricks. Instead, a casting technique is used in which a refractory casting material, generally a thixotropically acting casting material, is introduced into the interspace between a template or mold which determines the desired clear interior space of the ladle or other type of metallurgical vessel and the vessel wall to be lined. Due to its thixotropic behavior, the material flows very well under the action of vibrations (generally of the template or mold), even in the case of low water contents, and fills every cavity.
German Offenlegungsschrift 3,741,073 has already disclosed a process in which, at the end of the life of a metallurgical vessel, that is to say after the inner layers of the casting material which have been exposed to the molten metal have worn away, instead of breaking out completely the remainder of the refractory lining, which is of course still serviceable, only the remaining slag residues and the slag-penetrated surface layers of the old lining are superficially removed. This does not involve the production of a geometrically regular surface but an operation in which a so-called slag-stripping robot with tools mounted on movable arms, rolling on the surface and having projecting sintered-carbide studs acts on the surface under the action of vibrations and removes or at least roughens it to the desired extent. During this operation, however, the tools follow the largely existing contour of the old lining. The template is reintroduced into the metallurgical vessel having the old lining cleaned in this way, and the interspace between the template and the old lining is then filled again with thixotropic casting material under the action of vibrations. In this way, it is possible to save up to 50% of the expensive lining material. The preceding machining of the surface of the old lining results in a good bond with the newly applied refractory material.
The known process, however, proves to be too expensive in certain cases. This is the case when the skull, i.e. the slag layer, is so thick that the time involved in removing it and the associated wear of the tools are too great to keep the process cost-effective. In addition, the remaining portion of the refractory lining is subjected to high mechanical stresses by the prolonged action of the tools and cracks can thus arise.

Process and apparatus for renewing the refractory lining of foundry ladles

Intocast GmbH Feuerfestprodukte und Giesshilfsmittel


A thermostatic expansion valve has a valve shell, e.g., housing, with a high-pressure refrigerant passage and a low-pressure refrigerant passage. The high pressure refrigerant passage has a valve hole and a valve member that changes the valve hole opening rate. A pressure-operating chamber, which has an air-tight chamber and an equalizing chamber separated by a diaphragm, drives the valve member. This pressure-operating chamber, which is attached to the valve shell to detect the temperature, detects the temperature of gaseous phase refrigerant. The valve shell has a hole or opening extending through its outer wall. A plug member seals the hole after a heat-sensitive gas, which senses the temperature of the gas-phase refrigerant passing through the expansion valve, is introduced into the housing through the opening. The plug member is seated on the peripheral edge of the opening and welded to the opening peripheral edge by projection welding. An anti-corrosive material is applied to cover the welded area.

1. Field of the Invention
This invention relates to a thermostatic expansion valve for use in refrigerating systems of car air conditioners.
2. Description of Related Art
As shown in Japanese Laid-open Patent No. 6-185833, a conventional thermostatic expansion valve generally comprises a valve shell that has a high-pressure refrigerant passage through which liquid refrigerant to be reduced in pressure travels and a low-pressure refrigerant passage through which vapor-phase refrigerant travels. A valve hole is formed midway of the high-pressure refrigerant passage. A valve member is disposed to move to and away from the valve hole to change the opening rate of the valve hole. A pressure-operating housing includes a diaphragm for driving the valve member through a driving rod to control movements of the valve member. An air-tight chamber is partitioned by the diaphragm and filled with heat-sensitive gas, and mounted on the valve shell to detect the temperature of gaseous-phase refrigerant. A plug member shuts an outer wall opening provided in an outer wall of the pressure-operating housing after heat-sensitive gas is fully introduced into the air-tight chamber through the outer wall opening.
In the conventional thermostatic expansion valve above, the plug member, which has a flange portion, is typically fixed to the housing outer wall in such a manner that a portion of the spherical surf ace of the plug member is in direct contact with the opening edge of the housing outer wall and is secured thereto by projection welding. The flange portion of the plug member 16 is fixed to the housing outer wall by a solder-welding portion to seal the opening. In this method, the projection welding is used only for provisional fixture of the plug member, and the seal of the opening is established by the soldering.


An interface for detecting connected peripheral devices. The interface comprises a jack and a control unit determining the power requirements of peripheral devices, the control unit detecting the potential of two specified nodes upon connection of the device. If power is required, the control unit supplies the power and performs related commands according to device identification received from the connection. If no power is required, the control unit measures a resistor-capacitor (RC) equivalent value inside the peripheral device, and compares the measured RC values with RC values in a database.

1. Field of the Invention
The present invention relates to interface detection, and more particularly to interface detection for connection of peripheral devices.
2. Description of the Related Art
Currently, electronic devices normally have simple connections with such peripheral devices as earphones. Peripheral devices, can involve complex design, increasing with variety of functions and requiring specialized connection. For example, data transmission, such as video or high quality audio, requires additional eight-or twelve-port connectors with more pins to interface with the electronic device, increasing the size of the connectors, the cost, including shielding for pins, and others.

Interface for peripheral device detection


While firing a number of phases of a multi-phase switching voltage regulator in a sequence, a determination is made as to which one of the phases has the lowest phase current. Then, the next phase, to be fired in the sequence, is selected as the one that has been determined to have the lowest phase current. Other embodiments are also described and claimed.

Over the last several decades, significant advancements have been made in personal computer (PC) microprocessor architecture and fabrication techniques, to improve performance and control costs. With each successive generation, an increasing number of functions have been integrated into a processor integrated circuit die. This increase in density has been enabled by shrinking the size of the constituent transistor elements, thereby allowing more transistors per unit area on the die. Performance improvements have been obtained by for example increasing the clock frequency at which certain functions of the processor operate. As a result, each successive generation of such processors is more powerful from a total performance standpoint, and has increasing overall power consumption.
The power consumption of a processor is proportional to a product of its power supply voltage and current. Successive generations of processors with increasing transistor density operating at higher speeds (e.g., higher dock frequency) demand a lower power supply voltage but higher power supply current. For example, in the early days of microprocessors offered by Intel Corp. of Santa Clara, Calif., transistor count per die was in the low 100,000s, processor clocks were running at around 100 MHz, supply voltages were at 5V DC, and supply current was no more than 10 A (depending on the activity level of the processor). With more recent Pentium class processors, transistor count per die is well above 1 million, clocks are in the GHz range, the power supply voltage needs to be dropped to about 1.2V DC or less, while current draw (at high activity levels) easily surpasses 100 A.
The supply voltage needs to be regulated to stay within a certain range, in the presence of operating temperature variations and as the processor transitions between different activity levels. However, the smaller supply voltages have resulted in tighter ranges being required, in the face of large current swings. This has led to many challenges in providing low cost power delivery for advanced processors.
To ensure reliable power delivery for its microprocessor families, Intel has set voltage regulator design guidelines. A voltage regulator (VR) is an electronic circuit that draws current a power source, to feed the processor and maintain a well-regulated power supply voltage for the processor. The VR maintains a setpoint voltage (e.g., at a so-called "Vcc" node of the processor), using a feedback control loop that repeatedly senses deviations from the setpoint, and corrects for them by increasing or decreasing the amount of current drawn from the source. For greater power conversion efficiency, switching-type regulators are used that draw current from the source using transistor or similar devices that turn on and off at high rates and stay on for relatively short pulses. The setpoint voltage is maintained by suitably controlling the pulse widths or duty cycle.
Conventional switching VRs for high performance processors have more than two phases or paths to the power source, through which current is drawn to maintain the supply voltage. The multiple phases help reduce the magnitude of voltage and current ripple, which enables the use of smaller phase inductors and power transistor switches, as well as smaller filtering and decoupling components at the output of the VR. In addition, a multi-phase switching VR can be made to respond quickly to deviations from the setpoint voltage (both voltage droops and voltage spikes), thereby helping maintain the smaller supply voltages within tighter tolerance bands.
Conventional multi-phase VRs have a fixed phase-firing order. The phases are all fired at the same frequency, but time shifted relative to each other. For example, a 100 kHz two-phase regulator will have both phases switching at 100 kHz, with the assertion edges of the two phases separated by five microseconds (one-half the switching period). This approach, however, is problematic when the load current to the VR (for example, the power supply current to a processor) is in essence synchronized to the switching frequency. For instance, a periodic load of five microseconds high current, five microseconds low current creates a serious current imbalance in the two-phase 100 kHz VR. If left unchecked, the current imbalance may quickly reach the per-phase current-limit and usually lead to some form of automatic shutdown of the VR which causes a catastrophic error during operation of the computer system.
There are conventional schemes to reduce the fatal current imbalance, where such schemes typically rely heavily on bulk capacitance at the output, to reduce the need for temporal alignment of current into the VR versus current out of the VR. In one case, a phase current is compared with an average current (that represents the average current amongst all of the phases), and the duty cycle is controlled on that basis to minimize the difference of current in each phase.

Multi-phase voltage regulator with phases ordered by lowest phase current


An inspection apparatus includes: first and second stage parts on which a housing container housing substrates is mounted; first and second inspection parts having an imaging unit imaging the substrate; a first transfer region provided with a first transfer mechanism performing a first operation of transferring the substrate between the first stage part and the first inspection part; and a second transfer region provided with a second transfer mechanism performing a second operation of transferring the substrate between the second stage part and the second inspection part. In plan view, the first and second stage part are at positions not overlapping with each other, the first and second inspection part are at positions not overlapping with each other, and the first and second transfer region are at positions different from each other so as to perform the first and second operation in parallel.

Japanese Laid-open Patent Publication No. 2016-212008 discloses a substrate inspection method in a substrate treatment system including a plurality of treatment apparatuses performing predetermined treatments on the substrate. This inspection method acquires a first substrate image by imaging the surface of the substrate before treatment in the treatment apparatus, extracts a predetermined feature amount from the first substrate image, and selects, from a storage storing a plurality of inspection recipes set corresponding to feature amounts in different ranges, an inspection recipe corresponding to the feature amount extracted from the first substrate image. This inspection method acquires a second substrate image by imaging the surface of the substrate after treatment in the treatment apparatus, and determines the presence or absence of a defect of the substrate based on the selected inspection recipe and the second substrate image.

Inspection apparatus and substrate transfer method


The specification discloses preferred circuits and methods for performing a block write in a video random access memory circuit (VRAM). The VRAM has a plurality of memory registers, an address bus, and a data bus. The VRAM also has a multiple write register circuit with a plurality of write registers. During write register load cycles, data is written from the data bus to individual write registers which are specified by addresses received on the address bus. During a block write cycle, data is written from an individual write register to a selected block of memory registers; the block having a predefined number of memory registers within a row. The block of memory registers is specified by memory register base address received on the address bus. The memory register base address is the address of the first memory register in the block of memory registers. An individual write register from which data is written to the block of memory registers is selected during a block write cycle by an address received on the data bus.

As a preliminary matter, this invention concerns circuits that use voltages to represent binary logic values. Particular circuits may use varying voltage levels to represent the two binary logic values. Accordingly, the words "high" and "low" in this specification refer generally to voltages corresponding to the true and false binary logic values, respectively, within a given sub-circuit. Signals are generally considered "active" when they are high. However, a "*" following the signal name indicates that the signal has negative or inverse logic: the signal is considered active when low. These conventions will be used in the following written discussion. In the drawings, negative logic signals are indicated with a bar over the signal name.
Dual-port RAMs, commonly referred to as video RAMs or VRAMs, offer dramatic speed improvements over standard dynamic RAMs (DRAMs). VRAMs are particularly effective in video display systems and in other applications where high-speed data buffering is required.
A VRAM has an array of dynamic memory cells or registers. The array is accessed through either conventional DRAM control signals or through a serial access memory (SAM). A SAM is essentially a long shift register which receives a block of data from the dynamic memory array and shifts the data out serially through a "serial" port.
VRAMs are particularly useful as frame buffers for video systems. In such video systems, a graphics processor supplies randomly-addressed display frame data to a VRAM memory array as it would to conventional DRAM. The VRAM supplies a serial stream of sequentially-addressed display frame data to color lookup tables and digital-to-analog converters. The serial transfer does not interfere with the graphics processor's random access of the VRAM memory array.
VRAMs and their applications in video systems are well-known. For instance, Micron Technology, Inc., distributes a "1991 MOS Data Book," of which section 3 is hereby incorporated by reference, containing detailed descriptions of Micron's line of VRAMs.
Various features have been incorporated in VRAMs to speed data transfer to and from an associated graphics processor or microprocessor. An article published in Electronic Design, Nov. 23, 1989, entitled "Speed Memory, Ease Timing Requirements With VRAM Functions," by Mailloux, et al., describes many of these features, and is also incorporated by reference.
A "block write" function is an example of a feature provided in VRAMs to enhance speed of memory writing. The block write function is useful in a VRAM video frame buffer to quickly clear a large area of frame buffer memory or to create a background for a display window. Instead of writing to just one register the block write function allows simultaneous writing to a block of memory registers. Such a block may comprise an arbitrary or predefined number of memory registers or a logical unit of memory registers such as an entire row of memory registers.
Two types of block write functions are discussed in the following specification. The term "block writing" refers generally to both. The first type of block write function, referred to herein as a "selective block write," allows simultaneous writing to a selected block of four memory registers within a single row of memory registers. The second type of block write function, referred to herein as a "flash block write," allows simultaneous writing to an entire row of memory registers.
The selective block write and flash block write functions may also be used in conjunction with other VRAM features such as the masked write functions described below.
FIG. 1 is a block diagram of a prior art VRAM circuit, designated by the reference numeral 10, which includes both types of block write functions. Additional circuits and signals, not shown, are of course necessary to the operation of VRAM 10, as those familiar with this technology will recognize. Such circuits and signals are omitted here for the sake of simplicity, and to focus the reader's attention on VRAM elements which relate more specifically to the invention.
VRAM 10 comprises dynamic random access memory (DRAM) circuits similar in structure and function to those found in conventional DRAM devices, such as referred to in Section 1 of Micron's 1991 MOS Data Book. A DRAM array 12 in VRAM 10 comprises an array of dynamic memory cells forming eight-bit memory registers for storing binary-coded data. DRAM array 12 is arranged logically as eight planes, each plane having addressed rows and columns of memory cells. Each eight-bit memory register is made up of memory cells from the eight planes having the same row and column addresses. DRAM array 12 thus forms addressed rows and columns of eight-bit memory registers.
A microprocessor (not shown) accesses VRAM 10 through a data bus 14, a multiplexed address bus 16, row and column address strobe signals RAS* and CAS*, a special function signal DSF, a mask enable/write enable signal ME*/WE*, and by using other conventional control signals which are not shown. Address bus 16 receives individual address signals A0 through A8 from the microprocessor. Data bus 14 produces and receives individual data signals DQ1 through DQ8.
A row address latch/buffer 20 and a row decoder 22 receive a row address signal from multiplexed address bus 16, decode a row address therefrom, and address or activate the corresponding row of DRAM array 12. A column address latch/buffer 24 and a column decoder 26 receive a column address signal from address bus 16, decode a column address therefrom, and address or activate the corresponding column of DRAM array 12. During block write cycles, column decoder 26 simultaneously addresses and writes to a block of memory registers comprising either an entire addressed row of memory registers or a consecutively-addressed block of four memory registers within an addressed row.
Data bus 14 receives memory register data during a write cycle from the microprocessor and supplies it to column decoder 26 for writing to DRAM array 12. Column decoder 26 produces memory register data from DRAM array 12 at data bus 14 during read cycles.
A write register 34 receives data from data bus 14 during write register load cycles. Write register 34 supplies block write data to column decoder 26. A bit masking circuit 55 and a column masking circuit 56 receive mask data from data bus 14 as will be explained more fully below with reference to FIG. 2. Bit masking circuit 55 and column masking circuit 56 supply mask data to column decoder 26 through a decoder logic circuit 57.
VRAM 10 includes a serial access memory or SAM 36. SAM 36 is a single row of eight-bit memory registers, with columns corresponding to the columns of DRAM array 12. SAM 36, when appropriately activated, simultaneously transfers data between its memory registers and the memory registers of a row of DRAM array 12.
A SAM address counter 38 is associated with SAM 36 to generate sequential SAM column addresses. A SAM decoder 40 receives the generated addresses. SAM decoder 40 has a serial data bus 41 connected to produce and receive serial data signals SDQ1 through SDQ8. SAM decoder 40 is responsive to the sequential SAM column addresses from SAM address counter 38 to transfer data between the corresponding column of SAM 36 and serial data bus 41. A SAM address latch/buffer 42 receives a beginning SAM column address signal from address bus 16 and initializes SAM address counter 38 accordingly.
Various additional control circuits and signals initiate and synchronize VRAM operations. However, since this invention is concerned primarily with the block write functions of VRAM 10, and since VRAM circuits and operational details are well documented, they are not described further here. Reference may be made to the data sheets and specifications previously mentioned regarding VRAMs for a more detailed description of timing and control requirements, including control signal requirements for transferring data into SAM 36 from DRAM array 12 and for serially transferring such data out through SAM decoder 40.
FIG. 2 is provided to simplify the explanation of the selective block write function in VRAM 10. FIG. 2 is thus a conceptual diagram of the selective block write function, rather than a representation of physical elements within VRAM 10.
DRAM array 12 is shown as eight two-dimensional planes of memory cells. Together, the planes form rows and columns of eight-bit memory registers as already described. Individual memory cells are not shown, with the exception of an arbitrarily selected block of four consecutively-addressed memory cells 52 in each plane. Memory cells 52 are shown as an example of addressing during a selective block write cycle.
Write register 34 is an eight-bit static memory register. In a typical selective block write application, write register 34 is first initialized during a write register load cycle. Subsequently, data from write register 34 is written to blocks of memory registers within DRAM array 12, such as block 52, during block write cycles.
During a selective block write cycle, a row address and a column address are provided to VRAM 10 through multiplexed address bus 16. VRAM 10 latches the row address from A0 through A8 at the falling edge of RAS*, and the column address from A2 through A8 at the falling edge of CAS*, similar to a normal write cycle. A0 and A1 of the column address are disregarded during the selective block write cycle. The row address and column block address form a memory register base address which is the address of the first memory register of a block of four adjacent memory registers within a row. Memory cells 52 are shown in FIG. 2, in each of the logical planes of DRAM array 12, as an example of four adjacent memory registers within a row being simultaneously addressed for writing during a selective block write cycle.
Data is then written simultaneously from write register 34 to the block of adjacent memory registers through bit masking circuit 55 and column masking circuit 58. Data is not written from data bus 14.
Bit masking circuit 55 allows individual bits to be masked from writing so that a memory write may be performed on specified bits without altering the remaining bits. Bit masking circuit 55 contains a bit mask register 61 and eight corresponding bit enable gates 59. Bit mask register 61 is loaded with a bit mask code from data signals DQ1 through DQ8 during a bit mask register load cycle. Each bit of bit mask register 61 corresponds to a bit of write register 34. A bit value of zero indicates that the corresponding write register bit is to be masked. A bit value of one indicates that the corresponding write register bit is to be written to DRAM array 12.
Column or register masking circuit 56 allows specification of a column of register mask code. The column mask code is latched in a column mask register 60 from data signals DQ1 through DQ4 at the latter of WE* and CAS* going low during the selective block write cycle. Each bit of column mask register 60 corresponds to one of the four adjacent column locations. A bit value of zero indicates that the corresponding column is to be masked. A bit value of one indicates that the corresponding column is to be written from write register 34.
FIG. 3 a conceptual diagram of the flash block write function. A flash write is very similar to a block write, except that an entire row of memory registers is selected and written to simultaneously.
As in a selective block write cycle, write register 34 is first initialized during a write register load cycle. Subsequently, data from write register 34 is written to rows of memory registers within DRAM array 12.
Write register 34 provides an eight-bit data word during flash write cycles. The eight bits are routed through bit masking circuit 55 before being supplied to DRAM array 12. A row address is provided to VRAM 10 through multiplexed address bus 16. VRAM 10 latches the row address from A0 through A8 at the falling edge of RAS*. Memory register row 53 is shown in FIG. 3, in each of the logical planes of DRAM array 12, as an example of a register row being simultaneously addressed for writing during a flash write cycle.
Bit masking circuit 55 functions during a flash block write cycle as already described above to mask individual bits in each memory register from being written.
As a background, FIG. 4 illustrates the required sequence and relative timing of control signals to perform a normal write cycle to a single memory register within DRAM 12. DSF remains low throughout the entire write cycle. RAS* goes low to signal the presence of a valid row address signal at A0 through A8. ME*/WE* and CAS* go low to signal a valid column address at A0 through A8. At the latter of ME*/WE* and CAS* going low the data on DQ1 through DQ8 is written to the addressed memory register.
FIG. 5 illustrates the required sequence and relative timing of control signals to perform a write register load cycle, wherein write register 34 (FIGS. 1-3) is loaded from DQ1 through DQ8. The write register load cycle is similar to a normal write cycle, with address signals A0 through A8 being "don't cares," since there is no need to specify a memory address. DSF and ME*/WE* are both high as RAS* goes low to signal initiation of the write register load cycle. CAS* is lowered during the write register load cycle to indicate the presence of valid write register data at DQ1 through DQ8. DSF must remain high throughout the write register load cycle.
FIG. 6 illustrates the required sequence and relative timing of control signals to load bit mask register 61. This sequence is similar to a load write register cycle, except that DSF must be low when CAS* goes low. The bit mask register data is loaded from DQ1 through DQ8 at the falling edge of CAS*. Address signals A0 through A8 are "don't cares," since there is no need to specify a memory address. DSF and ME*/WE* are both high as RAS* goes low to signal initiation of the write register load cycle.
FIG. 7 illustrates the required sequence and relative timing of control signals to perform a selective block write cycle, wherein a block of four consecutively-addressed memory registers within a row of DRAM array 12 are simultaneously written with data from write register 34. As RAS* goes low, ME*/WE* is high and DSF is low to signal initiation of a selective block write cycle. DSF additionally must be high as CAS* goes low. RAS* going low also signals to VRAM 10 the presence of a valid row address at A0 through A8. ME*/WE* and CAS* are lowered to signal the presence of a valid column block address at A2 through A8. The contents of write register 34 are written to the addressed block of memory registers at the latter of CAS* and ME*/WE* to go low. A0 and A1 are ignored in forming the column block address during a selective block write cycle. A column mask code must be presented at DQ1 through DQ4 as CAS* goes low. DQ5 through DQ8 are unused during selective block write cycles.
FIG. 8 illustrates the required sequence and relative timing of control signals to perform a flash block write cycle in VRAM 10, wherein an entire row of memory registers within DRAM array 12 are simultaneously written with data from write register 34. As RAS* goes low, ME*/WE* is high and DSF is high to signal initiation of the flash write cycle. RAS* going low also signals to VRAM 10 the presence of a valid row address at A0 through A8. As ME*/WE* and CAS* are lowered, a column mask code is presented by data signals DQ1 through DQ4. Additionally, a column block address is presented by data signals A2 through A8 as ME*/WE* and CAS* go low. At the latter of CAS* and ME*/WE* to fall, data is written from the selected write register to the selected row of memory registers.
DRAMs and VRAMs typically incorporate, in addition to the block write functions, other functions which speed writing and reading of memory registers, such as a page writing and static column addressing. The invention described below, however, is concerned with providing an enhancement to block writing, wherein data may be written during a block write cycle from a selected one of several write registers. Such an enhancement speeds memory operations by eliminating the need to perform a write register load cycle when it is desired to change the value written during block write cycles. Data may be preloaded in a plurality of write registers and an individual write register selected during the block write cycle itself.

Multiple register block write method and circuit for video DRAMs


A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during transmission. Optionally, a cyclical redundancy check (CRC) length indicative data, pointer data, and other data is inserted within the IPG to further insure appropriate delineation of data frames within a data stream.

The ever-increasing need for greater bandwidth in core, enterprise, and local-area networks has driven the popular Institute for Electrical and Electronic Engineers (IEEE) 802.3 Ethernet standard to continuously push the transmission speeds for simple, low-cost, point-to-point networking. As transmission rates increase, the design of the Physical Layer protocols dramatically impacts the cost and complexity of both component and system implementation.
Beginning with the Fast Ethernet standard (IEEE 802.3u), the physical layer was partitioned into several sublayers, each of which encapsulates largely independent functionality. The Physical Coding Sublayer (PCS) is responsible for frame delineation, frame formatting, and line coding. Key characteristics of the PCS for high-speed transmission are that it should 1) offer a low-overhead, robust frame delineation; 2) utilize a low-overhead data encoding that does not unnecessarily burden front-end receiver circuitry; 3) be amenable to implementation in commodity silicon technology; and 4) take into account system-level implementation and integration issues such as electromagnetic interference mitigation.
In the so-called Gigabit Ethernet Standard (IEEE 802.3z), an 8 b/10b block code is used for both line coding and frame delineation. The 8b/10b coding scheme offers several desirable properties, namely a large code space having many unused codes (so that errors are reliably detected), good transition density, run-length limiting and DC-balancing. These advantages are offset by the 25% overhead. For example, for serial transmission at a bit rate of 10 Gbits/s, the 25% overhead of 8 b/10 b coding requires optical and electrical components that operate at 12.5 GHz. Currently, components with this capability are neither low cost nor manufacturable in high volume and yield. Further, the deterministic nature of the block code gives rise to serious electromagnetic interference (EMI) generation when the input symbol stream is constant or highly repetitive, as is the case when the link is idle and long sequences of IDLE characters are transmitted.
An improved point-to-point data link protocol is described by Doshi et al. in an article entitled "A Simple Data Link Protocol for High-Speed Packet Networks," published in the Bell Labs Technical Journal January–March 1999 on pages 85–104 and incorporated herein by reference in its entirety. The described simple data link (SDL) protocol provides for the framing of asynchronous protocol data units (PDUs) using a length indicator and pointer scheme whereby a pointer in the header of one packet or data frame is used to identify the start of a next packet or data frame. The SDL utilizes a length indicator field and a header cyclic redundancy check (CRC) to delineate frames. Unfortunately, in the case where packet length information is not available, an entire packet must be stored, thereby increasing latency. This may not be acceptable in some applications, such as "cut-through" packet switching.

Simple link protocol providing low overhead coding for LAN serial and WDM solutions


A water faucet and method therefor includes a spout for the water faucet which is used to control whether water is dispensed from the water faucet or not dispensed therefrom. The spout of the water faucet in its natural, untouched position functions to prevent water from flowing through the water faucet for external use. If the spout is raised or lowered, there is a flow of water through the water faucet because of a valve located within the spout and a base member holding the spout at a bottom portion thereof.

In the past, various water faucets have been produced and used by consumers in their offices or homes which have used different techniques to control water flow through the water faucet spouts. Most of the water faucets that were manufactured and sold in the past utilized both hot and cold, separate water control valve members in the form of water control units or knobs that were individually controlled to turn on or off the flow of water through the spout of the water faucet. These water control units or knobs were usually located spaced from the water faucet's spout in a convenient location on or adjacent to the sink to permit easy access thereto and use thereof by the hands of a person desiring to turn on (and subsequently off) the water faucet.
In order to facilitate the operation of controlling water flow through a water faucet and to eliminate the use of two separate water control units or knobs, a single water control unit or knob was developed which was generally centrally disposed adjacent to, but separate from the spout of the water faucet. One type of such a single water control unit or knob is known as the MOEN water controlled water faucet system. The MOEN water faucet permits water to flow out of the faucet when the single control unit or knob is elevated and returning the knob to its original low position causes the water flow out of the faucet to cease. Hot or cold water selection is achieved by rotation of the single control unit or knob to the right for cold water or to the left for hot water.
The use of the prior art water faucet systems including the MOEN water faucet system requires the use of both hands to turn the water faucet and simultaneously position a glass, cup or other container under the spout of the prior art water faucet system to receive water therefrom.
In recent years, people have become greatly concerned about obtaining purified or filtered water for drinking or other purposes i.e. food preparation, etc. because of possible contamination of water sources used to deliver water to consumers thereof. For example, pollutants from industrial plants near a water source that is going to a large population area have created great concerns to a health conscious public.
As a result, a significant water treatment industry has been developed to provide people with purified or filtered water. Carbon and other types of filtration systems have been developed to insure delivery of high quality water to consumers. Accordingly, water systems in homes and businesses have been created or modified to incorporate water filtration or purification devices to significantly increase the quality of the water that is to be used.
For these purified or filtered water systems, special faucets were developed to produce the external flow of water to be used by the consumers. These special faucets generally did not have both hot and cold water options from the same faucet, but were primarily concerned with the delivery of high purity water.
The subject invention is primarily directed to an improved water faucet especially useful for producing a flow of purified or filtered water.
Accordingly, a need existed for a much simpler water faucet system especially useful for delivering high purity water that is capable of operation using only one hand to control the flow of water, that would permit the flow of water out of the water faucet to be stopped by merely removing a person's hand from contact with the water control unit of the water faucet system, and that would even permit a person to use the same one hand to both turn the water on and to simultaneously pour water into a cup, glass or container.
A major problem with prior art water faucet systems was the fact that a positive action was needed to both turn on and turn off the water faucet. Consequently, we have all seen situations at various times and at different locations where the person turning on the water faucet forgot to turn it off thereby resulting in a loss of significant amounts of water. Since water is a valuable asset and, in some areas, a very scarce and precious commodity, it is extremely important to protect this commodity by insuring that a water faucet is turned off after a person's use thereof.
Thus, there is a great need for a water faucet systems that is naturally or automatically turned off when a person discontinues use of the water system to avoid continued flow and loss of water and thereby effecting significant water savings. Such a water faucet system operable by only one hand of a person is highly advantageous and desirable in addition to being simple to use.

Water faucet with spout to control water flow and method therefor