A magnetoresistive (MR) head having a double self-aligned contiguous junction includes an MR sensor structure with a biased guide joined thereto. The guide is formed using a first resist mask applied over the MR sensor structure. A guide biasing structure is formed using the first resist mask and a second resist mask applied over the first resist mask and the guide. The first resist mask is configured to form a double self-aligned contiguous junction between the MR sensor structure and the guide and guide bias structure. In this manner, the position of the guide biasing structure is carefully controlled so that it does not overlap the MR sensor structure.

1. Field of the Invention
The present invention is directed generally to magnetic heads for data storage applications, and more particularly, to thin film magnetic heads having flux-guided-MR or yoke-MR read sensors and methods for forming such heads.
2. Description of the Related Art
MR (magnetoresistive) sensors made by thin-film processes have been widely used in recent years for magnetic storage applications, particularly in disk drives. One of the properties of these sensors is that they vary in electrical resistance when placed in magnetic fields, such as the magnetic domains that represent recorded information on magnetic storage media. In disk drive applications, an MR read head having an MR sensor therein is carried on a slider mounted on a suspension. The suspension, in turn, is mounted to an actuator. The suspension mechanically biases the slider toward a surface of the disk. When the disk rotates, the loading is counterbalanced by a cushion of air (an "air bearing") generated by the rotating disk. The actuator moves the head to selected information tracks on the rotating magnetic disk. The resistance of the MR sensor changes in proportion to the change in magnetic field intensity caused by rotation of the disk. When a sense current is conducted through the MR sensor, the current changes in proportion to the change in resistance. Changes in the sense current are processed by a processor to produce playback signals corresponding to the information stored on the magnetic disk.
An MR sensor includes a stripe of MR material sandwiched between a pair of very thin insulative gap layers which are, in turn, sandwiched between a pair of magnetically conductive shield layers. Magnetic flux reaching the MR sensor extends through the gap layers to the shield layers. The MR sensor has front and back edges extending parallel to air bearing surface (ABS) of the slider on which it is carried. The MR sensor further includes a pair of side edges extending perpendicular to the ABS. The magnitude of magnetic flux that reaches the MR sensor is at a maximum at the front edge thereof. This magnitude decays along the MR stripe height and into the shields with a characteristic decay length. A boundary condition requires the flux magnitude to be zero at the back edge. When the stripe height of the MR sensor from the front to the back edge is less than the decay length, the flux loss along the height of the MR sensor is linear.
The MR sensor, which has a layer of magnetic material, is typically stabilized by a pair of hard bias (or exchange bias) layers adjacent its side edges. The hard bias layers longitudinally bias the MR sensor parallel to the ABS and stabilize the MR sensor from a multi-magnetic domain state to a single magnetic domain state. Accordingly, upon the termination of flux incursions into the MR sensor, the sensor always returns to a stabilized single magnetic domain state. Without longitudinal biasing, the domain walls of multimagnetic domains shift positions within the sensor, causing Barkhausen noise. This decreases the signal to noise ratio.
In some MR heads, the front edge of the MR sensor is exposed at the ABS and interfaces with the air bearing. To increase the amount of magnetic flux sensed by the MR sensor, and the intensity of the readback signal, a flux guide is connected to the back edge of the MR sensor and extends away from the ABS. In other MR heads, the MR sensor is recessed from the ABS. A second flux guide is connected to the front edge of the MR sensor and extends to the ABS. The second flux guide carries flux from the ABS to the MR sensor.
Recessed MR sensors are being pursued as attractive alternatives to MR sensors positioned at the ABS. Although the signal strength is reduced when the MR sensor is removed from the ABS, significant advantages achieved in the mechanical, electrical and chemical properties of the head may provide an acceptable tradeoff in many applications. From a mechanical standpoint, decreasing flying heights become possible and thermal asperity problems are minimized because there is less likelihood that the MR sensor will be damaged should the head contact the disk surface. From an electrical standpoint, the front flux guide insulates the current-carrying MR sensor and reduces the possibility of electrostatic discharge between the sensor and the disk. From a chemical standpoint, removal of the MR sensor from the disk means there is less chance that corrosion of the sensor will damage the disk. It therefore becomes possible to use less corrosion resistant materials for the MR sensor, which may provide performance benefits and reduce manufacturing costs.
For high density, post 1 Gbit/sq. in. trackwidths, it is generally accepted that the flux guides in recessed and nonrecessed heads need to be stabilized with hard bias (or exchange bias) by pinning the two sides of the flux guides with magnetically matched plugs in a fashion similar to the hard bias (or exchange bias) layers adjacent the MR sensor. Proper magnetic stabilization of MR heads thus requires the use of proper bias matching to both the MR sensor and the flux guides. The flux guide to sensor thickness ratio can be as large as twenty (20), particularly in yoke-MR heads, where one of the shields is used as a flux guide. As such, two separate depositions of hard bias material at different thicknesses are typically required.
One of the challenges of building a flux-guided-MR or yoke-MR sensor is the alignment of various edges with respect to each other to optimize flux guiding efficiency and proper bias matching. FIGS. 1A-1C show a sequence for building an MR sensor, which in the example is shown as having a sensor element that is recessed, but which could also have a nonrecessed sensor for purposes of the present discussion. Both the sensor element, which is made from a magnetoresistive material "MR," and the flux guide elements, which are made from a flux guide material "FG," are stabilized with separate longitudinal bias regions made from hard bias materials "HB1" and "HB2," respectively. Exchange bias could also be used. The structure shown in FIGS. 1A-1C is common for both yoke-MR heads, where one of the shields provides the flux guides and the other shield provides a return pole above the illustrated structure (i.e. in the z-axis direction), and flux-guided MR heads, where separate flux guides are employed and the illustrated structure is embedded between two shields. In FIG. 1A, an MR sensor layer 2 is deposited on a substrate 3, followed by two HB1 hard bias layers 4 and 6 formed along the sides of the MR sensor layer 2. In FIG. 1B, a pair of FG flux guides 8 and 10 are deposited on the substrate adjacent the front and rear edges of the MR sensor 2 and the hard bias layers 4 and 6. In FIG. 1C, two HB2 hard bias layers 12 and 14 are formed on the flux guide 8 and two HB2 hard bias layers 16 and 18 are formed on the flux guide 10. The critical point in the process is achieving y-direction alignment of the flux guide hard bias material layers 12-18 relative to the flux guides 8 and 10 on one hand, and the MR sensor 2 on the other. Misalignment of the HB2 hard bias layers causes either an overlap of the hard bias material into the MR sensor area or an absence of hard bias material in the flux guide area, resulting in the overbias of the sensor or an underbias of the flux guide material. The misalignment is illustrated by the structure shown in FIG. 1D.
The prior art method of making junctions between head components thus does not precisely position a hard bias layer at the edge portions of the flux guide and the MR sensor. The reason for this is because the prior art employs two resist masking steps. Under the best of conditions the alignment of a critical edge of the resist mask from a benchmark on a wafer is within +/-0.1 um. Another problem arises from unpredictable shrinkage of the resist. The location of the critical edge of the resist due to shrinkage varies +/-0.1 um. Even when windage is employed to attenuate the shrinkage problem, shrinkage is still variable from wafer to wafer. For any wafer containing multiple MR heads with flux guides and hard bias layers constructed according to the prior art, the yield will thus be unacceptably low because of the variability in hard bias layer alignment.
Accordingly, one cannot rely on photolithographic alignment for hard bias positioning in MR heads. An improved process is needed to ensure proper hard bias alignment and thereby improve the magnetic stabilization of the sensor and flux guides. What is required is an efficient method for closely controlling the deposition of the hard bias layers with consistent accuracy in order to improve manufacturing yields.

Double self-aligned insulated contiguous junction for flux-guided-MR or yoke-MR head applications

International Business Machines Corporation


Current data for a geographic area is accessed. The current data comprises at least one of (a) current traffic data for the geographic area, (b) current incident data for the geographic area, or (c) current weather data for the geographic area. Based on the current data, autonomous driving instructions are determined for the geographic area. A notification comprising the autonomous driving instructions is provided such that the notification is received by a vehicle apparatus located within the geographic area or expected to enter the geographic area based on a route being traversed by a vehicle corresponding to the vehicle apparatus. The vehicle apparatus is onboard the vehicle and is configured to control the vehicle in accordance with the autonomous driving instructions.

Generally, vehicles with autonomous, self-driving capabilities rely on sensor information/data captured by sensors onboard the vehicle and map information/data stored in memory onboard the vehicle to determine driving strategy decisions. However, as vehicles with autonomous, self-driving capabilities become more common, having each vehicle determine its own driving strategy decisions may lead to traffic inefficiencies. Moreover, by basing driving strategy decisions on offline information/data such as the sensor information/data and the onboard map information/data, the vehicle may be lacking information/data that may lead to more efficient and safe driving strategy decisions.


An apparatus for protecting an auto from hijacking, comprises a nozzle for mounting in a position adjacent a driver's door for directing a spray of a disabling substance into an area at about face level at the driver's door, a source of pressurized disabling fluid, a conduit for connecting the source of fluid to the nozzle for delivering a selected quantity of the fluid to the nozzle, and a remote control switch operative from the driver's seat of the auto for initiating the dispensing of a quantity of the fluid via the nozzle.

The present invention relates to defensive systems and pertains particularly to an improved system for defense against auto hijacking.
There has been a recent rash of auto thefts wherein the auto is taken from the possession of the driver with a gun or other weapon. These thefts or hijackings, currently termed carjacking, usually take place at street intersections and in parking lots, usually at gunpoint. This provides the thief with a readily operable vehicle without having to break into the car and hot-wire it. However, it subjects the driver to a high risk of violence which may result in injury or even death.
Many citizens, in order to protect themselves, are arming themselves with weapons, such as knives and guns. However, this has a tendency to increase the risk of violence and injury to the victim.
It is desirable that an effective and reasonably safe means for defense against carjacking be available.


A magnetic memory cell including a data storage layer having an easy axis and a reference layer having an orientation of magnetization which is pinned in a direction that is off-axis with respect to the easy axis. This structure increases the signal obtainable during read operation on the magnetic memory cell notwithstanding the effects of magnetizations in the edge domains of the data storage layer. In addition, this structure allows high MRAM densities to be achieved using square-shaped memory cell structures.

1. Field of Invention
The present invention pertains to the field of magnetic memories. More particularly, this invention relates to a magnetic memory cell with a reference layer having off-axis orientation.
2. Art Background
A magnetic memory such as a magnetic random access memory (MRAM) typically includes an array of magnetic memory cells. Each magnetic memory cell usually includes a data storage layer and a reference layer. Typically, the logic state of a magnetic memory cell depends on the relative orientations of magnetization in its data storage and reference layers.
The data storage layer of a magnetic memory cell is usually a layer or film of magnetic material that stores alterable magnetization states. These alterable magnetization states typically include magnetizations which form in a direction that is parallel to what is commonly referred to as the easy axis of the data storage layer. A data storage layer also usually includes magnetizations which form near its edges including edges that are perpendicular to its easy axis. The magnetizations which form near the perpendicular edges are commonly referred to as edge domains. The resulting orientation of magnetization in the data storage layer is a result of the effects of the magnetizations along the easy axis and the effects of perpendicular magnetizations in the edge domains.
The reference layer of a magnetic memory cell is usually a layer of magnetic material in which magnetization is fixed or "pinned" in a particular direction. In a typical prior magnetic memory cell, the reference layer is formed so that its magnetization is pinned in a direction which is parallel to the easy axis of the data storage layer. As a consequence, the orientation of magnetization in the reference layer of a prior magnetic memory cell is typically parallel to the easy axis of the data storage layer.
A magnetic memory cell is typically in a low resistance state if the orientation of magnetization in its data storage layer is parallel to the orientation of magnetization in its reference layer. In contrast, a magnetic memory cell is typically in a high resistance state if the orientation of magnetization in its data storage layer is anti-parallel to the orientation of magnetization in its reference layer.
A prior magnetic memory cell is usually written by applying external magnetic fields that rotate the orientation of magnetization in the data storage layer from one direction to the other along its easy axis. This causes the magnetic memory cell to switch between its high and low resistance states. The logic state of the magnetic memory cell may be determined during a read operation by measuring its resistance.
Unfortunately, the effects of the edge domains in such a magnetic memory cell usually cause the resulting orientation of magnetization in the data storage layer to move away from its easy axis. This usually reduces the difference between the high and low resistance state of the magnetic memory cell and decreases the signal obtained during read operations. Such a decrease in signal usually increases the bit error rate in an MRAM.
One prior solution for minimizing these negative effects of edge domains is to form the data storage layer as a rectangle with an elongated dimension along its easy axis. Such a structure usually increases easy axis contribution to the resulting orientation of magnetization in the data storage layer in comparison to contributions from the edge domains. Unfortunately, such a rectangular configuration usually requires more energy to flip the orientation of magnetization in the data storage layer during write operations, thereby causing an increase in power consumption in a MRAM that uses such a structure. In addition, such rectangular magnetic memory cells usually limit the overall memory cell density that may be obtained in an MRAM.

Magnetic memory cell with off-axis reference layer orientation for improved response


A combination multi-level rack includes two side racks, at least an object holding member, and a fastener. Two sides of each of the side racks are provided with a longitudinal part, respectively, and a transverse part combined with the longitudinal parts. Four corners of the holding member are provided with a combining member, respectively. Each of the combining members has an engaging groove and a combining part disposed on a lateral side of the engaging groove, and the engaging groove engages the transverse part. The fastener removably engages the combining part with the longitudinal part. Therefore, the object holding member is stably combined to the two side racks.

1. Field of the Invention
The present invention relates to combination multi-level racks, and more particularly, to a combination multi-level rack easy for adjusting the height for objects storing.
2. Description of the Related Art
A conventional multi-level rack has plural levels of space longitudinally disposed for placing or storing objects. Such racks are often provided in indoor at working places.
Referring to FIG. 1 and FIG. 2 illustrating the perspective view and exploded view of a conventional multi-level rack, a multi-level rack 1 comprises a couple of side racks 2 and at least a board 3, wherein the four corners of the board 3 are provided with a coupler 4 disposed through a self-tapping screw 8, respectively, so as to provide a supporting effect. Therein, two sides of each side rack 2 are provided with two vertical rods 5, respectively, with one horizontal rod 6 transversely welded between the two sides of the side rack 2; also, the horizontal rod 6 defines an interval between the two corresponding vertical rods 5. The coupler 4 is provided with a U groove 7 for being engaged between the two vertical rods 5 on the upper edge of the horizontal rod 6. In addition, the coupler 4 slightly opens a gap between the two vertical rods 5 on two sides of the side racks 2, so as to fix the board 3 on the two side racks 2.
However, when the multi-level rack is being assembled, the coupler 4 is needed to be coupled between the two vertical rods 5 first, and the board 3 is subsequently in aligned and fastened with the coupler 4. When the process is accomplished, the side rack 2 is slightly opened by the board 3 to achieve a lateral fixing status, whereby the height of the board 3, especially disposed on the multi-level rack 1, is not allowed to be adjusted for meeting different user demand. Moreover, if the height of the board 3 is to be adjusted, the coupler 4 needs to be separated with the board 3. After repeated disassembling and reassembling process, screw hole of the board 3 is unavoidably expanded to impose negative affect upon the combination strength of the components. Therefore, such multi-level rack 1 needs to be improved.


A tablet cutting apparatus including a cutter (22) for notching a tablet, a receiver plate (39) for supporting the tablet from the bottom, and a divider roller (23) for dividing the tablet into two halves along the notch formed by the cutter (22). The tablet is held between the divider roller (23) and the receiver plate (29). Thus, after notching the tablet by the cutter (22), the tablet is divided into two by the receiver plate (39) and the divider roller (23), and thereby the tablet is precisely split into halves.

The present invention relates to a tablet packing apparatus and, more particularly, to a tablet packing apparatus having a function of cutting a tablet into halves for delivering it to a child patient or for the like purpose.
In the case that the patient is a child, if one tablet is prescribed for one dose, the dose is too much for the child. Therefore, if has been customary practice to cut the tablet into halves to prescribe one half of the tablet. In such a case, although it is common to manually divide the tablet into two parts, there has been proposed an arrangement such that one tablet is divided into halves by a tablet splitter (as disclosed in Japanese Patent Publication No. 6-7715, for example).
With manual cutting, however, there is disadvantages that operating efficiency is very poor, and that it is difficult to split the tablet accurately into halves.
Even when the tablet splitter is used, a tablet having no split line formed on the surface thereof can hardly be split accurately into halves. Furthermore, it is necessary that tablet splitting and subsequent packing must be separately carried out. This involves troublesome work, resulting in poor operating efficiency.
It is an object of the present invention to provide a tablet cutting apparatus which can precisely split a tablet into halves.
In order to accomplish the above object, a tablet cutting apparatus according to the present invention is provided and the tablet cutting apparatus, comprises:
a cutter for notching a tablet;
a receiver plate for supporting the tablet from bottom; and
a divider roller for dividing the tablet into two halves along the notch formed by the cutter, the tablet being held between the divider roller and the receiver plate.
In the tablet cutting apparatus having the above described construction, after notching the tablet by the cutter, the tablet is divided into two by the receiver plate and the divider roller, whereby the tablet is precisely split into halves.
Preferably, the tablet cutting apparatus may further comprise a transport portion for transporting the tablet at positions of the cutter and the receiver plate, and a tablet positioning portion for positioning the tablet at a predetermined position confronting the cutter. In this case, the tablet positioning portion may have inclined surfaces adapted to abut the tablet from opposite sides in rectangular relation to the direction of tablet transport in such a way as to press the tablet downward. The tablet positioning portion may include a solenoid for positioning the tablet at the predetermined position by protruding a plunger thereof from the inclined surface.
Preferably, the divider roller may be formed with an escape groove centrally of the outer periphery thereof so that the escape groove is opposed to the notch formed by the cutter, and the upper surface of the receiver plate may comprise a cylindrical surface with a curvature bulging upward.
Preferably, the tablet cutting apparatus may further comprise a cleaner device which includes a hood for covering the cutter and the divider roller from above, the cleaner device operates to suck powder that is generated from the tablet via the hood.
Preferably, the tablet cutting apparatus may further comprise a split guide plate for guiding split half tablets divided by the receiver plate and the divider roller to different places, respectively.
Preferably, the tablet cutting apparatus may further comprise a memory for storing a cutting condition according to the kind of tablet, and a controller for reading the cutting condition corresponding to the kind of the tablet to be cut from the memory and controlling operation of the cutter according to the cutting condition.


A thumbscrew apparatus for fastening a first device to a second device. In a first embodiment, the apparatus comprises a screw attached to the second device and a first cylinder screwed onto the screw for fastening the first device to the second device. The first cylinder has an outboard end with a one-way slot feature that allows a screwdriver to be used to loosen the first cylinder while inhibiting the use of the screwdriver to tighten the cylinder. In a second embodiment, the shaft of the screw has a first portion smaller in diameter than a second portion. The first portion also has a thread pitch smaller than that of the second portion. A second cylinder contained within the first cylinder is screwed onto the second portion of the shaft while the first cylinder is screwed onto the first portion. A pin is used to lock the first cylinder to the second cylinder such that both cylinders are turned at the same revolution. However, since the pitch of the second portion of the shaft is greater than that of the first portion, the second cylinder moves faster along the axis of the screw than the first cylinder. Hence, when both cylinders are being turned in the loosening direction, the second cylinder pushes the screwdriver out of the one-way slot of the outboard end of the first cylinder before the first cylinder reaches the end of its travel.

1. Field of the Invention
The present invention relates generally to a fastening device for securing an adapter card to a computer system and, more particularly, to a thumbscrew assembly for fastening the adapter card to the computer system.
2. Description of the Related Art
Modern computer systems are commonly designed to accommodate adapter cards. The adapter cards are added to the computer systems by being inserted each into a socket in the systems' motherboard. Often times, the cards are grounded by being fastened to the chassis of the computer systems using a thumbscrew. Most thumbscrews are integrated in the metal cover of the computer system. In addition, the thumbscrews often have a slotted head to facilitate the use of a screwdriver for tightening and loosening purposes. When a screwdriver is used to loosen a thumbscrew, there is always a likelihood that it will also be used to unscrew the thumbscrew. As is well known, it is very easy to exert more force than necessary when using a screwdriver. As a result, the thumbscrew may be overtightened, stripping its threads or be broken off by applying too much force after the thumbscrew has traveled to the end of its threads. When any one of the above occurs, the entire metal cover of the computer system has to be replaced, a relatively expensive remedy.
Thus, there is a need in the art for an apparatus that prevents a thumbscrew from being overtightened or broken.


The present invention has a recording head of jetting ink drops to record, a carriage adapted to be loaded an ink container storing ink to be fed to the recording head in a removable state, and a communication unit of communicating with a storage element for the ink container installed in the ink container. The communication unit can communicate with the storage element for the ink container when the ink container is not loaded on the carriage. Accordingly, the communication unit can communicate with the storage element for the ink container before mounting the ink container on the carriage.

As an example of this kind of ink jet printer, Japanese Patent Laid-Open Publication 279344/1990 discloses a printer which has a storage means installed in an ink jet printing head with an ink chamber. The storage means holds operation conditions of the printing head and ink information. The printer is operated on the basis of information which is read from the storage means in an electrically non-contact state using a read/write head installed in the printer so that the printing head is operated optimally. The printing bead of the printer in this example stores ink in the ink chamber and is mounted in a carriage in a removable state so as to have a so-called ink cartridge function.
In this example, information on the printing head and ink can be transferred to the printer in a non-contact state, so that no electrical contact is required and there is no possibility that ink may be adhered to the exposed contact, causing a defective contact. Further, to maintain the contact between the contacts, there is no need to enhance the accuracy of mechanical positions.
In the conventional printer mentioned above, although information on the printing head and ink can be read and written in a non-contact state, data cannot be read and written into the storage means from the printer when the printing head having the ink chamber is not mounted on the carriage.
Incidentally, when the number of kinds of recording apparatus is increased, it is difficult for the same ink cartridge to cover a plurality of recording apparatus. Accordingly, the kind of ink cartridge becomes different for each recording apparatus and a suitable combination of recording apparatus and ink cartridges becomes complicated. Therefore, a user cannot easily judge the compliance between recording apparatus and ink cartridges, and after all, a problem arises that until the point of time when an ink cartridge is opened and actually mounted on a carriage of a recording apparatus, the user cannot judge whether the ink cartridge is suitable to the recording apparatus or not.
When the ink cartridge is mounted on the carriage, the seal for sealing the ink feed port of the ink cartridge is broken by the ink feed needle installed on the carriage side. Then, regardless of whether the recording apparatus is suitable to the ink cartridge or not, the ink in the ink cartridge is consumed by a predetermined amount, with the result that, when the ink cartridge is not suitable, unnecessary consumption of ink is caused.
The present invention was developed to solve the aforementioned problems and is intended to provide an ink jet recording apparatus which is able to communicate with a storage element installed in an ink container before mounting the ink container on a carriage.


A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.

1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming reduced resistance local interconnect structures and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits fabricated using MOS technology, field effect transistors (FETs), such as planar field effect transistors and/or FinFET transistors, are provided that are typically operated in a switched mode, i.e., these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In general, as a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the "packing density," i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first lower end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end is connected to a respective metal line in the metallization layer by a conductive via. Such vertical contact structures are considered to be "device-level" contacts or simply "contacts" within the industry, as they contact the "device" that is formed in the silicon substrate. The contact structures may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other applications, the contact structures may be line-type features, e.g., source/drain contact structures.
In some cases, the second, upper end of the contact structure may be connected to a contact region of another semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. These local interconnect structures typically connect circuit elements, e.g., transistors, resistors, etc., that are formed on different spaced-apart active regions that are electrically isolated from one another. Such local interconnect structures are generally line-type structures that are formed in the interlayer dielectric material below the metallization system of the product.
As the critical dimensions of the circuit elements in the device level decreased, the dimensions of metal lines, vias and contact elements were also reduced. In some cases, the increased packing density mandated the use of sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels that are positioned above the device contact level, metal lines (M1 and above) and vias (V0 and above) having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required packing density in accordance with the density of circuit elements in the device level.
In sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, an interlayer dielectric material is formed first and is patterned so as to define contact openings which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements, i.e., the source/drain region or the gate structure of a transistor.
FIG. 1A is a cross-sectional view of an integrated circuit product 10 comprised of a plurality of transistor devices formed in and above a semiconductor substrate 12. A schematically depicted isolation region 13 has also been formed in the substrate 12. In the depicted example, the transistor devices are comprised of an illustrative gate structure 14, i.e., a gate insulation layer 14A and a gate electrode 14B, a gate cap layer 16, a sidewall spacer 18 and simplistically depicted source/drain regions 20. At the point of fabrication depicted in FIG. 1A, a layer of insulating material 17A, 17B, i.e., the interlayer dielectric, has been formed above the product 10. Other layers of material, such as contact etch stop layers and the like, are not depicted in the attached drawings. Also depicted are illustrative source/drain contact structures 21 which include a combination of a so-called "trench silicide" (TS) structure 22 and a so-called "CA contact" structure 24. Also depicted is a gate contact structure 26 which is sometimes referred to as a "CB contact" structure. The CB contacts 26 are formed so as to contact a portion of the gate electrode 14B of the gate structure 14. In a plan view, the CB contacts 26 are positioned above the isolation region 13, i.e., the CB contacts 26 are not positioned above the active region defined in the substrate 12. The source/drain contact structures 21 are typically formed as line-type structures that extend across the entire width or a significant portion of the active region in the gate-width direction of the transistor devices.
In one embodiment, the process flow of forming the TS structures 22, CA contacts 24 and CB contacts 26 may be as follows. After a first layer of insulating material 17A is deposited, TS openings are formed in the first layer of insulating material 17A that expose portions of underlying source/drain regions 20. Thereafter, traditional silicide is formed through the TS openings followed by forming tungsten (not separately shown) on the metal silicide regions and performing a CMP process down to the top of the gate cap layer 16. Then, a second layer of insulating material 17B is deposited and contact openings for the CA contacts 24 are formed in the second layer of insulating material 17B that expose portions of the underlying tungsten metallization. Next, the opening for the CB contact 26 is formed in the second layer of insulating material 17B and through the gate cap layer 16 so as to expose a portion of the gate electrode 14B. Typically, the CB contact 26 is in the form of a round or square plug. Thereafter, the CA contacts 24 and the CB contact 26 are formed in their corresponding openings in the second layer of insulating material 17B by performing one or more common deposition and CMP process operations, using the second layer of insulating material 17B as a polish-stop layer to remove excess material positioned outside of the contact openings. The CA contacts 24 and CB contact 26 typically contain a uniform body of metal, e.g., tungsten, and may also include one or more metallic barrier layers (not shown) positioned between the uniform body of metal and the layer of insulating material 17B. The source/drain contact structures 21 (TS contacts 22, CA contacts 24) and the CB contact 26 are all considered to be device-level contacts within the industry.
Also depicted in FIG. 1A is the first metallization layer—the so-called M1 layer—of the multi-level metallization system for the product 10. A plurality of conductive vias—so-called V0 vias—are provided to establish electrical connection between the device-level contacts—CA contacts 24 and the CB contact 26—and the M1 layer. The M1 layer typically includes a plurality of metal lines that are routed as needed across the product 10. The M1 lines 30 and the V0 structures are typically comprised of copper, and they are formed in a layer of insulating material 19 using known damascene or dual-damascene techniques. Additional metallization layers (not shown) are formed above the M1 layer, e.g., M2/V1, M3/V2, etc. As depicted, the device-level contacts are all positioned at a level that is below the level of the V0 structures.
FIG. 1B depicts another illustrative arrangement of device-level contacts that may be employed on the product 10. Relative to the example depicted in FIG. 1A, in FIG. 1B, the V0 structures have been omitted and the CA contacts 24 and the CB contact 26 have been extended vertically. In this example, the device-level contacts 24, 26 are all positioned at a level that is below the level of the metal lines in the M1 layer.
FIG. 1C depicts another illustrative arrangement of conductive structures that may be employed on the product 10. In this example, a local interconnect structure 32—a so-called M0 line—is formed in the second layer of insulating material 17B at the same time the CA contacts 24 and the CB contact 26 are formed, and it is formed of the same materials of construction as the CA contacts 24 and the CB contact 26. Use of the local interconnect 32 can be beneficial for several reasons. For example, as depicted in FIG. 1C, due to the presence of the local interconnect 32, the spacing 33 between the V0 vias 28 that are conductively coupled to the CA contacts 24 may be increased, i.e., the left-most V0 via 28 may be shifted to the left due to the existence of the local interconnect 32. In this example, the device-level contacts 21, 26 as well as the local interconnect 32 are all positioned at a level that is below the level of the V0 structures 28.
FIG. 1D is a plan view of a portion of an integrated circuit product that depicts further examples of where a local interconnect structure (M0) may be employed. As shown therein, a first transistor 10A is formed above a first active region (Active 1) while second and third transistors (10B, 10C) are formed above a second active region (Active 2). The spaced-apart active regions are electrically isolated from one another by isolation material (not shown). As depicted therein, line-type CA contacts (CA) are formed above each of the source/drain regions (S/D Region), while CB contacts (CB1-CB3) are formed for each of the gates structures (Gates 1-3). As mentioned previously, the CB contacts are positioned above the isolation material. As depicted, a first local interconnect structure (M0-1) is coupled to a CA contact of transistor 10A and to CB2 contact for Gate 2 of the second transistor 10B. By using the first local interconnect structure (M0-1), the distance 35 between the CB2 contact and the CA contacts on the second transistor 10B may be maintained at an acceptable distance to avoid shorting. A second local interconnect structure (M0-2) is coupled to CB1 contact for Gate 1 of the first transistor 10A and to CB3 contact for Gate 3 of the third transistor 10C. Due to the presence of the second local interconnect structure (M0-2), Gate 1 can be coupled to Gate 3 without shorting to Gate 2.
While all of the various formations of device-level contact structures and local interconnect structures discussed above are possible, another problem that is present with such conductive structures is the overall resistance of the device-level contacts, and particularly the local interconnect structures. The present disclosure is directed to various methods of forming reduced resistance local interconnect structures and the resulting semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.

Methods of forming reduced resistance local interconnect structures and the resulting devices


A touch sensor integrated type display device includes gate lines and data lines that cross over each other, pixel electrodes, first electrodes, second electrodes and shielding portions. The pixel electrodes are formed in areas defined by crossings of the gate lines and the data lines. The first electrodes at least partially overlap the pixel electrodes and are formed in parallel with the data lines. The second electrodes are formed in parallel with the gate lines between the pixel electrodes neighboring each other with the gate lines interposed therebetween. The shielding portions extend from the second electrodes in the spaces formed by the first electrodes arranged with the data lines interposed therebetween.

Field of the Invention
The present disclosure relates to a display device, and more particularly, to a touch sensor integrated type display device which is capable of recognizing a user's touch.
Discussion of the Related Art
Recently, various input devices such as a keyboard, a mouse, a trackball, a joystick, and a digitizer have been used to configure an interface between users and home appliances or various kinds of information communication equipment. However, such input devices as a keyboard, a mouse, etc. require the user to learn to use them and take up space. Therefore, the demand for input devices that are convenient and easy to use and reduce erroneous operations is growing more and more. In response to this demand, a touch sensor for enabling a user to input information by directly touching the screen with their hand or a pen was suggested.
The touch sensor is simple to use, has less malfunctions, and enables the user to input without using an additional input device. In addition, the touch sensor can be applied to various display devices because it enables the user to operate it quickly and easily through content displayed on the screen.
Touch sensors can be classified into add-on type and on-cell type. In the add-on type, a display device and a touch panel having a touch sensor are separately manufactured, and the touch panel is attached onto an upper substrate of the display device. In the on-cell type, a touch sensor is directly formed on the surface of an upper glass substrate of a display device.
However, the add-on type sensor has a structure in which the completed touch panel is mounted on the display device and has various problems, such as increased thickness or reduced visibility due to low brightness of the display device.
In addition, the on-cell type touch sensor has a structure in which a touch panel is formed on the upper surface of the display device and can have a reduced thickness compared to the add-on type but still has the problem of the increase in entire thickness due to a driving electrode layer, a sensing electrode layer, and an insulation layer for insulating the driving electrode layer and the sensing electrode layer, which constitute the touch sensor. As such, the number of processes and the manufacturing cost in the on-cell type touch sensor increase.
Accordingly, the need for a display device capable of solving the related art problems has arisen.

Touch sensor integrated type display device


The present invention is directed to a fiber optic sensor for analyzing pH which comprises (a) a fluorescence-based fiber optic sensor; and (b) a fluorescent dye-polymeric matrix in contact with the sensor, wherein the fluorescent dye is seminaphthorhodaflor-1-isothiocyanate, the polymer is a hydrogel selected from the group consisting of polyhydroxyethylmethacrylate, polyvinylpyrrolidone, cellulose, dextrans, and polysaccharides, and the dye is chemically bonded to the polymer. The present invention is also directed to a fiber optic sensor for analyzing carbon dioxide which comprises (a) a fluorescence-based fiber optic sensor; and (b) a fluorescent dye-polymeric-silicone elastomeric matrix in contact with the sensor, wherein the matrix comprises a fluorescent dye-polymeric premixture in a silicone elastomer, and the fluorescent dye is selected from the group consisting of seminaphthorhodaflor-1-carboxylate (SNARF-1C), seminaphthorhodaflor-1-isothiocyanate (SNARF-1C-ITC), seminaphthorhodaflor-1-dextran conjugate (SNARF-1C-Dex), 10-diethylamino seminaphthorhodaflor-1-carboxylate (SNARF-2C), and seminaphthorhodaflor-1-carboxylate 10-acetate (SNAFL-1C diacetate), the polymer is a hydrogel selected from the group consisting of polyhydroxyethylmethacrylate, polyvinylpyrrolidone, cellulose, dextrans, and polysaccharides, and the silicone elastomer is a polydimethyl siloxane selected from the group consisting of hydroxy, epoxy, and vinyl terminated polydimethyl siloxanes.

Optical pH and carbon dioxide sensors are an active area of research [Leiner, Marc J. P., Wolfbeis, Otto S. In Fiber Optic Chemical Sensors, Wolfbeis, Otto S., Ed., Chapter 8, CRC Press: Boca Raton, 1991]. Recently, several pH sensitive seminaphthorhodaflor dyes have been reported which can be excited in the green part of the spectrum and have emission from both the acid and base tautomers [Whitaker, James E., Haugland, Richard P., Prendergast, Franklyn G. Anal. Biochem., 1991, 194, 330-44]. Fiber optic sensors fabricated with these seminaphthorhodaflor dyes have many advantages over conventional sensors. For example, such sensors may use inexpensive green light emitting diodes and the ratio between the emission from the base peak and the isosbestic point, in contrast to the emission from the base peak alone, is impervious to many effects associated with luminescence-based optic fiber sensors such as bending loss, connector loss, photobleaching, etc. Consequently, fiber optic sensors fabricated with seminaphthorhodaflor dyes inherently have much lower drift than current fluorescent sensors.

Emission based fiber optic sensors for pH and carbon dioxide analysis


A mower path assistance system to encircle an obstacle projecting from a ground surface, including a barrier mat formed with a barrier mat aperture enclosed by the barrier mat and having a barrier mat aperture diameter, a perimeter edge, and a barrier mat installation slit extending from the perimeter edge to the barrier mat aperture, wherein the barrier mat is deformable around the barrier mat installation slit to create a pathway having a pathway width through which the obstacle may pass from the perimeter to the barrier mat aperture. The barrier mat has a plurality of edges with axes that intersect at obtuse angles.

The present invention relates generally to methods and devices for creating a safe working environment around vertical projections and obstructions and for preventing vegetation. More particularly, the invention is directed to methods and devices for covering the ground area immediately surrounding such projections to eliminate the need for the mower to perform a full 360 circle around the projection and maintain a substantially parallel mowing path, and reduce the growth of vegetation, while reducing the risks associated with mowing near such obstructions. Fire hydrants, mail box posts, fence posts, guy wires, and other similar ground-anchored structures generally require a mower to deviate from a traditional mower path consisting largely of parallel opposed direction mowing paths. Such deviations, particularly when they require the mower to slow down and make a full 360 degree circle around an obstacle, significantly reduce the efficiency of mowing project adding significant time and danger associated from such maneuvers. After all, the natural tendency is to try to mow as close to the obstruction as practical so as to reduce the amount of post-mowing trimming that is required. Obviously, trying to mow within inches of an obstruction while moving at a high speed is prone for accidents, which can be life threatening. Further, such obstacles are often located in areas where vegetation grows around the base of the structure. Vegetation around the ground-anchored structures must routinely be maintained to prevent the overgrowth of vegetation. Due to the above problems associated with vegetation growth around ground-anchored structures, routine maintenance must be performed to control the growth, which generally consists of a secondary step of trimming around the obstacle after mowing around the obstacle. There are several problems associated with these prior art methods for controlling vegetation around the ground-anchored structures. The secondary step of trimming around the ground-anchored structure to control vegetation growth results in substantial labor and other costs, as does the deviation from the parallel path mowing plan. In addition, damage can be caused to the structures themselves or to mower and equipment which collides with the ground-anchored structures which may be partially concealed by vegetation growth. The cost of repairing or replacing mowers due to damage caused by concealed ground-anchored structures can be substantial, as is the risk of injury. Additionally, problems are also encountered by the use of herbicides to control vegetation around such obstacles. The harmful chemicals may result in environmental damages and concern and potentially getting to the ground water. Herbicides may also be corrosive and can cause damage to the ground-anchored structures. The present invention provides a barrier system and method to reduce vegetation growth around posts, guy wires, trees, and other lawn obstacles and reduce vegetation growth around such projections, while improving mower safety.


A voltage with a predetermined pattern is applied to liquid crystals to drive the liquid crystals during a unit drive period of the liquid crystals and an application pattern according to the gradation data is set taking into account a value obtained by integrating the amount of transmitted light of liquid crystals at various points in time when each application pattern is applied to the liquid crystals. This allows a fine gradation display even if the liquid crystals are driven by only ON/OFF of a maximum rated voltage. As a result, it is possible to drive the liquid crystals at high speed and produce a multi-gradation display.

An active matrix type liquid crystal display apparatus producing a multi-gradation display is known in the prior art. This multi-gradation display is performed by selecting one reference voltage corresponding to the gradation display data from among as many reference voltages as display gradations using an analog switch and driving the liquid display apparatus at the selected reference voltage.
FIG. 1 is a block diagram showing a conventional liquid crystal drive apparatus for driving an active matrix type liquid crystal display apparatus. This liquid crystal drive apparatus is provided with first latch 1, second latch 2 and decoder 3 for every vertical pixel line of the liquid crystal display apparatus.
First latch 1 reads 3-bit gradation data D0 to D2 that specify 8 gradations for each vertical pixel line during one horizontal scanning period. That is, this gradation data D0 to D2 are latched by first latch 1 and held for only one horizontal scanning period.
Second latch 2 supplies gradation data D0 to D2 held in first latch 1 to decoder 3 in next one horizontal scanning period. Decoder 3 decodes gradation data D0 to D2 from second latch 2 and outputs decoded signals S0 to S7 to control terminals of analog switches A0 to A7 respectively.
These analog switches A0 to A7 selectively output reference voltages V0 to V7 supplied to the input terminal in association with decoded signals S0 to S7. That is, one of reference voltages V0 to V7 is selected by decoded signals S0 to S7 and output as a liquid crystal drive voltage.
Reference voltages V0 to V7 correspond to gradation levels as shown in FIG. 2. Therefore, a reference voltage is selected based on the gradation data, the reference voltage is output to the liquid crystal panel as a voltage to be applied, and in this way the amount of transmitted light corresponding to the applied voltage is obtained allowing a gradation display.
However, the conventional liquid crystal drive apparatus is not sufficient to drive liquid crystals at high speed. In line with widespread use of the Internet there is a growing demand for high-speed transmission of large-volume data such as images in recent years and multi-gradations are also required to be implemented. Displaying moving pictures in particular requires high-speed drive and a multi-gradation display of liquid crystals.

Liquid crystal drive apparatus and gradation display method


The invention relates to an enclosure structure of electronic equipment such as a rack-mount disk array apparatus, and its object is to increase the number of apparatus units to be mounted and facilitate replacement thereof. The enclosure structure of electronic equipment of the invention having an enclosure mounted in a rack in a withdrawable manner, is arranged such that it comprises a plurality of wiring panel portions that partition the inner space of the enclosure in the fore-and-aft direction, the plurality of wiring panel portion being disposed spanning over the inner surface portions of the enclosure; and a movable frame portion that rotationally moves apparatus units connected to the wiring panel portions together with the wiring panel portions, the movable frame portion providing a support to the apparatus units in such a manner as to be attachable to and detachable from the wiring panel portions.

1. Field of the Invention
The present invention relates to an enclosure structure of electronic equipment such as a rack-mount disk array apparatus.
2. Description of the Related Art
Reference is made to FIG. 1 to describe a conventional rack-mount disk array apparatus. In a disk array apparatus 2, there is provided a back panel 6 at the middle portion of an enclosure 4 mounted to the rack, with a plurality of hard disk units 8 provided on the front surface portion of the back panel 6 and a plurality of interface (I/F) units 10 and power supply units 12 provided on the rear surface portion of the back panel 6. The hard disk units 8 are mounted from the front surface side of the enclosure 4 for replacement thereof.
Japanese Patent Application Laid-Open Publication Nos. 2003-36669, 2002-343075, 08-137631 and 06-215553 are available as patent documents related to such an enclosure structure of electronic equipment such as such disk array apparatus.
In Japanese Patent Application Laid-Open Publication No. 2003-36669, there are disclosed electronic equipment and a rack housing the electronic equipment in which, for easy replacement of hard disk devices in a rack-housed server unit, the server unit is configured with outer and inner cases, with a movable portion capable of moving downward attached to the inner case and hard disk devices housed in two rows, and in which, in the case of replacement of hard disk devices located toward the back, the inner case is drawn out, and further the movable portion is lowered so as to expose the end surfaces of the hard disk devices located toward the back. In such a configuration, all hard disk devices can be replaced from the front surface side, with no need to detach the server unit from the rack at the time of replacement.
In Japanese Patent Application Laid-Open Publication No. 2002-343075, there is disclosed a disk array that allows easy performance of tasks such as replacement and addition of hard disk units and prevents occurrence of shorting failure as a result of contact between signal cable and slim enclosure. In this disk array, a plurality of slim enclosures, each equipped with a hard disk unit, are housed in a rack so as to be slidable, with the slim enclosures provided with a tray having a front opening for allowing entry of the hard disk unit so as to be freely attachable/detachable and a connector for connecting the hard disk unit that has entered from the front opening. The tray is supported so as to be movable to the disk attachment/detachment position that brings the front opening away from the bottom plate of the slim enclosure and to the use position that brings the front opening close to the bottom plate.
In Japanese Patent Application Laid-Open Publication No. 08-137631, there is disclosed a disk array apparatus in which 2.5-inch or smaller hard disks can be installed using the form factor of 5.25-inch or 3.5-inch hard disk of a conventional disk array apparatus. As its configuration, four 2.5-inch hard disks are arranged three-dimensionally in a slot corresponding with the form factor of 5.25-inch hard disk of disk array apparatus. In the event of a failure of a hard disk, one pulls out the slot by grabbing the handle at the front of the slot, pulls out the faulty hard disk by grabbing the handle located toward the front, replaces the faulty hard disk with a new one, inserts the new hard disk into the slot by reversing the procedure for withdrawal and puts the slot back into the disk array apparatus to complete hot-swap.
In Japanese Patent Application Laid-Open Publication No. 06-215553, there is disclosed an easy-to-install-and-detach disk drive carrier assembly that is equipped with a 3.5-inch disk head assembly (HDA) and an electronic card pack in a detachable manner.
Incidentally, description will be given of hard disk units mounted in such a disk array apparatus with reference to FIGS. 2A and 2B. FIG. 2A shows a case in which 3.5-inch hard disk (HDD) units are mounted in a rack, whereas FIG. 2B shows a case in which 2.5-inch hard disk-units are mounted in the same rack. In these disk array apparatuses 2, size reduction of hard disk units 8, mounted in the enclosure 4, for example, from 3.5-inch type to 2.5-inch type, will result in a reduced storage capacity per unit height of the rack if the same unit arrangement is used as in the conventional apparatus.
In a disk array apparatus 2A shown in FIG. 2A, the size of the 3.5-inch hard disk units 8 mounted in a rack 14 is 3U, thus making the height 36U due to a 12-stage configuration. Here, 1U=44.45 mm (1.75 inches) based on EIA standard. Letting the number of the hard disk units 8 installed in the direction of width of the rack 14 be 15, the storage capacity of each of the hard disk units 8 be, for example, 300 GB, and the storage capacity per the rack 14 in this case be M1, then the storage capacity M1 is:M1=12×15×300 [GB]=54,000 [GB]
In this case, the storage capacity per 1U or M1/36U is:M1/36U=54,000 [GB]/36U=1,500 [GB]
In contrast, in a disk array apparatus 2B shown in FIG. 2B, the size of 2.5-inch hard disk units 18 mounted in a rack 16 is 2U, thus making the height 36U similarly due to an 18-stage configuration. Letting the number of the hard disk units 18 installed in the direction of width of the rack 16 be 24, the storage capacity of each of the hard disk units 18 be, for example, 73 GB, and the storage capacity per the rack 16 in this case be M2, then the storage capacity M2 is:M2=18×24×73 [GB]=31,536 [GB]In this case, the storage capacity per 1U or M2/36U is:M2/36U=31,536 [GB]/36U=876 [GB]
Thus, if the 3.5-inch hard disk units 8 are changed to the 2.5-inch hard disk units 18, the storage capacity per the rack 16 is low, despite increased number of the hard disk units 18, because the storage capacity of each of the hard disk units 18 is low, thus resulting in 50 percent reduction in storage capacity per 1U. In addition, unless the storage capacity of the 2.5-inch hard disk units 18 increases, it is impossible to complement the decrease in storage capacity by increased number of units alone when the 3.5-inch hard disk units 8 are changed to the 2.5-inch hard disk units 18. It is therefore necessary for the disk array apparatus 2B to implement a structure that allows mounting of additional hard disk units in the apparatus and replacement thereof.
With regard to such a problem, there is no disclosure in Japanese Patent Application Laid-Open Publication Nos. 2003-36669, 2002-343075, 08-137631 and 06-215553, nor is there any description of means for solving the problem.

Enclosure structure of electronic equipment, and disk array apparatus


A polymorphic threat manager monitors an incoming email stream, and identifies incoming email messages to which executable files are attached. The polymorphic threat manager characterizes incoming executable files according to at least one metric. For example, the polymorphic threat manager can decompose an executable file into fragments, hash some or all of these, and use the hashes as characterization metrics. The polymorphic threat manager subsequently de-obfuscates executable files, and creates corresponding characterization metrics for the de-obfuscated images. The characterizations of executable files before and after de-obfuscation are compared, and if they differ sufficiently, the polymorphic threat manager determines that the file in question is polymorphic. The characterization metrics of such an executable file after de-obfuscation can be used as a signature for that file.

Mass-mailing worms are some of the most prevalent and troublesome threats to Internet users today. Worms like Netsky, Beagle, MyDoom, and most recently, Sober, have caused millions of dollars in damage and cleanup costs. To make matters worse, the increasing availability and quality of runtime packers and other obfuscation tools are making it easier for worm writers to automate the creation of new variants of a worm, making analysis more complicated and time consuming.
Generated signatures can be utilized in order to detect and block malicious code. However, existing signature generation methodologies do not account for oligomorphic or polymorphic malicious executable images, which can change their external form each time they replicate. The existing signature generation methods do not detect the fact that these different forms are instantiations of the same worm. Therefore, such methods create a different signature for each new replica of the worm. This can overwhelm any agent (such as a centralized correlation server) processing the detection and management of malicious code.
What is needed are methods, systems and computer readable media for generating robust signatures that can commonly identify a polymorphic worm in its various forms.


Two or more set-top boxes are installed in a household. A communications link, preferably a physical link, is provided between or among the set-top boxes. One of the boxes is designated as a “master” box while the other box or boxes are “slaves.” The slave box will use the communications link to communicate in a secured and encrypted manner with the master box. If that communication is severed, e.g., if an attempt is made to move the slave box to another household to provide unauthorized service in that household, the slave box will stop working when it can no longer communicate with the master box.

The cable and satellite television industry provides customers with the ability to view a wide variety of television programming for a fee, usually paid monthly. Providing cable or satellite television programming is typically accomplished through a "set-top box." A set-top box is a box of electronics that is connected between the cable or satellite television system and the user's television set. The electronics in the set-top box allow the user to receive the television programming from the cable or satellite system on the connected television set. Subscribers are provided with a set-top box when registering or subscribing with the cable or satellite television provider.
Set-top boxes are also conditional access devices which may allow the display of certain cable/satellite television programs only under certain conditions. For example, a set-top box can be programmed to provide access to specific premium channels if the subscriber pays an additional fee. Access to such premium channels can be restricted through the set-top box if the subscriber has not paid the additional fees.
However, a single set-top box will typically only allow one program to be viewed at a time. Consequently, if a household would like to be able to view two different programs on two different television sets, they have generally been required to purchase a second set-top box and pay twice the monthly subscription fee.
If faced with paying a second full subscription fee, most subscribers will decide instead to get by with a single set-top box and pay only a single subscription fee. This is true even through the subscribers would prefer to have the ability to watch multiple programs simultaneously. Thus, subscribers are actually purchasing fewer services than they really desire because the incremental cost of an additional subscription for a second set-top box is too high. Consequently, from a business model standpoint, many cable and satellite television system operators would like the ability to provide a household with a second set-top box so that multiple programming can be accessed simultaneously without having to charge two full subscription fees.
However, there are dangers to the system operator if secondary set-top boxes are offered at a reduced subscription rate. This danger arises from the potential dishonesty of customers who obtain services that are not properly paid for. For example, suppose the first set-top box within a household has a $40 per month fee and the second has a $10 per month fee. In such a case, a dishonest customer could purchase a second set-top box and give it to his or her neighbor who previously did not have the service. The result is that the provider is collecting $50 per month for service to the two households, when the provider should be collecting $80 per month for service to two separate households.
Moreover, in the past, there have been problems with the dishonesty of the installer: the person who sets up a set-top box when a subscriber first subscribes to the service. Methods exist to prevent an installer from dishonestly giving away cable/satellite service without registering the users of the service in the single set-top box scenario. However, if the installer is allowed to sell and set-up multiple set-top boxes in a single household, it becomes substantially more difficult to ensure that the installer is not dishonestly providing service to those who may be paying off the installer directly for such service.
Consequently, there is a need in the art for a secure means and method of providing multiple set-top boxes to a single subscriber without having to charge a full subscription fee for each such set-top box and while preventing secondary set-top boxes from being used to provide services to those who are not paying the appropriate fees.

Method and system for providing security within multiple set-top boxes assigned for a single customer


An etching solution which contains hydrogen fluoride (HF) and exhibits an etching rate ratio: etching rate for a boron-glass film (BSG) or boron-phosphorus-glass film (BPSG)/etching rate for a thermally oxidized film (THOX) of 10 or more at 25° C.

Conventionally, as etchants for silicon wafers and the like have been used buffered hydrofluoric acids comprising HF (50% by weight) and NH4F (40% by weight) at such a ratio that can achieve a desired etch rate.
However, the buffered hydrofluoric acids etch not only doped oxide films such as BSG films, BPSG films, phosphosilicate glass (PSG) films, arsenic silicate glass (AsSG) films and the like, but also undoped oxide films such as USG including TEOS (oxide obtained by CVD method using tetraethoxysilane gas) films, THOX and the like. Therefore, the buffered hydrofluoric acids can not selectively etch the doped oxide films.
An object of the present invention is to provide an etching solution and an etching method for selectively etching oxide films doped with impurities relative to TEOS and THOX.

Etching solution, etched article and method for etched article


In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

1. Field of the Invention
This invention is related to the field of interrupts, and more particularly to delivering interrupts over a communication fabric in a system such as a system on a chip (SOC).
2. Description of the Related Art
Computing systems generally include one or more processors that serve as central processing units (CPUs), along with one or more peripherals that implement various hardware functions. The CPUs execute the control software (e.g. an operating system) that controls operation of the various peripherals. The CPUs can also execute applications, which provide user functionality in the system. Additionally, the CPUs can execute software that interacts with the peripherals and performs various services on the peripherals behalf.
The peripherals can cause the CPUs to execute software on their behalf using interrupts. Generally, the peripherals issue an interrupt to the CPU, typically by asserting an interrupt signal to an interrupt controller that controls the interrupts going to the CPU. The interrupt causes the CPU to stop executing its current software task, saving state for the task so that it can be resumed later. The CPU can load state related to the interrupt, and begin execution of an interrupt service routine. The interrupt service routine can be driver code for the peripheral, or may transfer execution to the driver code as needed. Generally, driver code is code provided for a peripheral device to be executed by the CPU, to control and/or configure the peripheral device.
In some cases, the peripheral writes data to memory to be operated upon by the interrupt service routine ("interrupt code") and/or the driver code. Accordingly, the peripheral may transmit the write operations and assert the interrupt to the CPU. This procedure creates a race condition between the write operations propagating to memory and the execution of the interrupt code/driver code. More particularly, the write operations may not have reached the point of "globally visibility" to the CPU. If the writes are globally visible, the data written by the write to memory will be returned by a read of the same memory location, even if the writes have not actually reached memory yet. If the code begins executing before the writes are globally visible, the code may read the previous values from memory (prior to the writes), which could lead to erroneous operation.

Race-free level-sensitive interrupt delivery using fabric delivered interrupts


A composite construction element or panel system for use in construction of multi-storey structures, either as a prefabricated panelized system or as a modular system. The composite construction element comprises two mass timber subpanels joined at a distance to form a hollow core, through which various building services (e.g. HVAC or electrical systems) and/or insulation may be integrated. When used as a modular system, after assembly, the two subpanels become one structural entity of increased structural capacity while providing a hollow core to provide/deliver desired building services.

Mass timber is increasingly used in prefabricated construction due to the possibility of including surface finishes and services in manufacturing, and the possibility of transporting finished panels or modules to a construction site for quick assembly. A particular benefit is the use of mass timber for the structural system of mid-rise (4-16 storeys) buildings due to its fire ratio and structural strength. Especially voluminous modules, consisting of a floor, a ceiling, and walls, with a high degree of prefabrication, make the construction process more efficient and are therefore considered desirable to manufacturers for certain types of construction projects. Such modules can also allow for a quick building envelope enclosure; among various advantages, this can also reduce the risk of water/weather damage to the structure.
Conventionally, prefabricated modules are transported to a construction site and then stacked on top of each other to await assembly. During this stacking, the floor of each module is stacked upon the ceiling of the module below, thus causing ceilings and floors to be doubled-up. Since the modules have to also support their own weight during transport, storage and assembly, this method usually results in redundant material use, especially since the ceiling and floor from two stacked modules are not structurally connected. Similar redundancy exists for the walls. Accordingly, it is contemplated that there could be significant advantages and cost savings to be had in avoiding such redundancy.
In addition, it is contemplated that a prefabricated panel system, in which said prefabricated panel system is configured to facilitate the provision and distribution of various building "services" (for example, such as: heating, ventilation or air conditioning ("HVAC") services, electrical service distributions, lighting, fire safety equipment, communications services, etc.) may also provide significant advantages.

Panel system for modular building construction


The invention discloses a method and system for synchronizing external data to an internal timing signal. External data is received in conjunction with a clock input. The clock input has first set of values and a second set of values. The clock input is compared to an internal timing signal having a frequency that is a multiple of the clock input. The internal timing signal is shifted by adjusting the count of a counter if the clock input transitions from the first set of values to the second set of values within a predetermined range of the internal timing signal.

When performing high frequency parallel to serial conversions, it is necessary to load parallel data into a shift register without corrupting the data. One problem that arises is the timing associated with loading the parallel data into the shift register. Typically, the parallel data is received at a known frequency that is related to the frequency of the serial data produced. For example, in an eight bit parallel to serial converter, the frequency of the serial data is eight times that of the parallel data. However, although the frequency of the incoming parallel data is known, its phase relationship with respect to a timing mechanism for clocking the parallel data into the shift register is not known. Due to this unknown phase relationship, the parallel data may be received by the shift register at the same instant that the parallel data is changing state. If that occurs, the data may be corrupted. Therefore, a need has arisen for a method and apparatus for synchronizing external data to an internal timing signal.

Method and apparatus for synchronizing external data to an internal timing signal


In a method which is performed using a communication network and uses a derivative to reduce a money debt such as a housing loan debt, a loan debt, a nation/public/corporate bond debt, a lease debt, or a payment obligation including insurance benefits, a derivative corresponding to a period of the debt and a condition is set up by a bond, a stock, a currency, an exchange, an interest rate, a spot such as a commodity and/or an index, and a price singly or by combining them, and in case of necessity, the derivative is divided into small lots to conform to an amount of the debt and the condition, this is purchased by a debtor of the debt at a relatively small premium, and when the derivative produces a profit, this is sold to realize the profit, alternately, reference is made to a present value of the debt and when a profit is produced in the money debt, a swap is made to realize the profit, and the debt is reduced by the profit.

The present invention relates to a contract in which in a contract with a risk due to the fluctuation of the economical environment produced by various causes, for a debt of a debtor using a loan or a lease for financing over a relatively middle and long period, such as housing acquisition, an equipment fund for business or a working fund, or a debt of an issuer of a nation bond, a public bond, and a corporate bond (hereinafter referred to as a nation/public/corporate bond), and a debt (hereinafter referred to as a debt) such as payment obligation including payment to an insured person in life insurance and nonlife insurance (hereinafter referred to as insurance), the debt is reduced or extinguished, or a part of or all of the credit or investment is collected and a profit is obtained, and further, relates to a social invention in which a creditor, such as a financial institution, a nation/public/corporate bond buyer, a lease trader, or a lender for an insured person or the like, is enabled to perform risk hedging, so that the rights and duties of safe long-term credit and debt can be kept.
Incidentally, any of the following financial terms used in the invention are described in respective pages of "KINYUU JITSUMU DAIJITEN" (edited by KINZAI INSTITUTE FOR FINANCIAL AFFAIRS, INC., issued on Sep. 19, 2000), and are widely generally used in the financial industry. For example, payment (p. 353), present value (p. 476), loan (p. 1775), housing loan (p. 802), option (p. 163), swap (p. 944), volatility (p. 1587), risk (p. 1731), and the like are described.
On looking back upon the 20th century, there is a case where both a creditor and a debtor are ruined by abrupt change of the macro economy. During good times (time of inflation), although there is a fear that depression (time of deflation) gradually occurs, in the present circumstance, means for taking measures against the risk is not provided at the side of the debtor when for example, a housing fund is borrowed. The same applies to the case where the time of deflation is changed to the time of inflation.
With respect to the risk when the macro economical environment is changed, when the macro economy is abruptly changed by, for example, long-term depression, degradation of the balance of international payments, financial failure due to excessive issuance of nation bonds or public bonds, collapse of money credit by failure of economy and currency policy, the failure of extreme resource distribution, or the like, the lending risk and borrowing risk of the creditor and debtor are abruptly increased, the economy itself is abruptly reduced, and it is conceivable that the creditors and especially many debtors have problems.
In the case where the micro economical environment is changed and the interest rate rises, the debtor and the creditor have the following situation.
(a) Under the inflation economy, in the case where various prices rise suddenly, and the income in proportion to them does not follow, for example, a debtor such as a housing fund loan debtor has trouble in payment of the debt. Especially, the debtor adopting the variable interest rate is required to pay high interest, and the payment of the loan becomes difficult.
(b) Under the deflation economy, general demand is decreased, and many enterprises have difficulty in management or are ruined, so that the employment is decreased or the income is decreased, and the loan debtor such as the housing fund loan debtor becomes insolvent. For example, under the financial crisis which occurred in New York in 1929, the unemployment rate reached 25%. Besides, when the guarantee value is abruptly decreased by the deflation, in the case where the debtor becomes unable to pay the principal and/or interest, there occurs a state where the guarantee can not be changed to money, and substantially an excessive liability state occurs. Further, for the loan debtor adopting the fixed interest rate, the payment of the high interest is continued, and it is conceivable that finally, it becomes unable to pay the principal and interest, and the agreed repayment becomes impossible.
Further, under the deflation economy, since the debtor delays the repayment, goes bankrupt, or becomes insolvent, bad debts extremely increase, not only the interest but also the principal can not be collected, and there is a fear that the creditor is also ruined. Besides, the value of the hypothecated asset is also decreased, and it becomes difficult to exchange the hypothecated asset to money.
Japan in the 1990s underwent these cases, the bad asset of financial institutions exceeded 100 trillion yen, and the problem of the failure of the financial institutions developed. On the other hand, since the government must take pump-priming measures, it is difficult to avoid the increase of the interest rate due to this, and the housing loan over 20 to 30 years has a high risk of future rising interest rates.
Although there are many derivatives (financial derivatives) to avoid such an economical risk, there is no patent document in which in the case where a commoner (consumer) as a debtor and a general business owner (enterprise) perform financing, the risk of rising interest rates is hedged by a blanket or small-lot derivative corresponding to the debt amount so as to support the debtor. Besides, at present, in an investment, credit, debt, or credit and debt with conditions, which is intended for a commoner, a risk hedge using a derivative has not been performed.
In "NEW FINANCIAL SYSTEM—PREPARATION FOR FUTURE HUGE RISK" (written by Robert J. Shiller, Professor of Yale University) issued by Nihon Keizai Shinbun, Inc. before the application (Feb. 9, 2004) of the invention, as a new method of insurance to avoid the drop risk of the house price of a housing acquisition person (housing loan debtor) by home-equity insurance, it is disclosed that claim for insurance is settled on the basis of a house price index (p. 180), and it is emphasized that the social necessity for countermeasures to a drop in house prices has been especially intensified in recent years. Although its direction is quite common to the invention, the concept and specific method described here are based on the risk hedge using the insurance and its method against a future drop in house prices, which is different from the invention.
Besides, although following patent documents 1 and 2 describe methods of avoiding a financial risk relating to debt redemption, the risk of the loan debtor is not targeted, and further, with respect to a method of avoiding a risk that the profit of a creditor is decreased by the refunding of a loan debtor according to the change of economical situation or by the repayment before the deadline, subrogated performance such as trust is used, and there is no concept that the burden of the loan debtor is reduced or extinguished by using the present value of the debt discounted by a yield curve.
Besides, a credit arises from the debt, and the creditor is also required to safeguard the credit with a risk. The credit at the creditor side includes housing loan lending credit, lease credit, lending credit to a juristic person over a relatively long period, and reinsurance credit in an insurance company.
Patent document 1 JP-A-2002-342579
Patent document 2 JP-A-2002-358428

Debt reduction method and device thereof


A packaging object supplying apparatus for supplying a packaging object to a packaging unit for packaging the packaging object into a predetermined fashion and specifically, a packaging object supplying apparatus comprising a packaging object combining portion for forming a combination of the packaging objects by combining two or more kinds of the packaging objects by a predetermined quantity in a predetermined array and a packaging object introducing portion for introducing the packaging objects combined by the packaging object combining portion to the packaging unit, a boxing apparatus comprising foldable box body supplying means, opening forming means, box body holding means, packaging object loading means, and lid forming means, a box body supplying apparatus for supplying a box body to the boxing apparatus.

1. Field of the Invention
The present invention relates to a packaging object supplying apparatus, box body supplying apparatus, boxing apparatus, packaging system and packaging method and particularly to a packaging object supplying apparatus for supplying two or more kinds of packaging objects to the packaging unit in a predetermined array, a box body supplying apparatus capable of treating boxes of various sizes and shapes with single equipment, a boxing apparatus having the box body supplying apparatus and a packaging system capable of automatically packing small boxes of various shapes and sizes into corrugated board boxes according to a predetermined pattern.
2. Description of the Related Art
Usually, a film cartridge containing a photographic roll film is incorporated in a plastic film case and the film case is sold in a form of a carton which is a sack carton made of coated board.
Although conventionally, a carton generally adopts a small box type in which one film case is accommodated in each small box, recently, production number of a package so-called multi-small box type package in which two or more film cases are accommodated therein have increased.
A small box with a single film-type package is a standard packaging style for a film cartridge and its production amount is large with a small deflection in its quantity. Thus, a small box with a single film-type package can be automatically manufactured.
On the other hand, as for a multi-small box type-package, although production amount for one packaging style is not so large, there is a huge deflection in production quantity between different packaging styles. Further, this type has various packaging styles depending on the quantity of the film cases accommodated therein, presence/absence of a header which is a tab-like member and position thereof.
Therefore, it is difficult to manufacture a multi-small box type-package automatically and thus, packages of this type often are manufactured by hand or a semi-automatic packaging machine. Therefore, there is such a problem that its production efficiency is not raised.
Although conventionally, a packaging unit capable of coping with various styles of the multi-small boxes has been demanded, there are following problems in realizing such kind of packaging unit.
(1) Sack cartons used for the conventional multi-small box, that is, small boxes made of coated board are separated into two types; a type in which a film case is loaded from opening portions on both ends, and a type in which a film case is loaded from an opening portion on the side face thereof. A cartoner, which is a packaging unit for packaging the film case in the sack carton, cannot cope with two kinds of the sack cartons easily.
(2) In a conventional multi-small box, bar code sizes and printing positions are not made uniform.
(3) Even among multi-small boxes in which the same number of film cases are loaded, there is a difference in header positions and sizes.
(4) Multi-small boxes are often gathered together in a specified number and shrink-packaged. Upon shrink packaging, the multi-small box needs to be assembled in a different pattern in accordance with a presence/absence of its mount paper, header position, size, number of film cases loaded therein and the like.
(5) When the multi-small boxes are packaged in a corrugated board box, they need to be packaged in a different pattern in accordance with a packaging style of the multi-small boxes.
Among the above-described problems, it is considered the problem (1) and the problem (2) can be solved by making uniform the direction of loading the film cases in the sack carton and unifying the size and printing position of the bar code to be printed on the multi-small box.

Packaging object supplying apparatus, box body supplying apparatus, boxing apparatus, packaging system and packaging method


Provided are a method and an apparatus for a User Equipment (UE) for multiplexing at least one uplink channel and an uplink signal and for controlling the transmission power for an uplink channel and an uplink signal. A method of a UE for controlling an uplink transmission power may include setting the uplink maximum transmission power for each of a plurality of cell groups including one or more serving cells; and allocating the transmission power for an uplink channel and an uplink signal based on at least one of: the uplink maximum transmission power, a total sum of the transmission power of one or more uplink channels and an uplink signal transmitted in each of the plurality of cell groups, and the total maximum transmission power of the UE, and the uplink channel includes a PUCCH or a PUSCH, and the uplink signal includes a SRS.

1. Field of the Invention
The present disclosure relates to a method and apparatus for enabling a User Equipment (UE) to multiplex an uplink channel and an uplink signal and to control transmission power for an uplink channel and an uplink signal. Particularly, the present disclosure relates to a method of a UE for multiplexing and transmitting various uplink channels and uplink signals in a dual connectivity environment where transmission and reception are performed by different Base Stations (BSs), a method of controlling the transmission power of various uplink channels and uplink signals, and an apparatus thereof.
2. Description of the Prior Art
Due to advances in communication systems, various wireless terminals have been introduced to consumers, such as companies and individuals. A current mobile communication system has been affiliated with 3rd generation partnership project (3GPP), for example, Long Term Evolution (LTE), LTE-Advanced (LTE-A), and the like. Such a mobile communication system may be capable of transmitting and receiving, at a high speed, a large amount of various data such as multimedia data, image data, and, radio signal, as well as a voice data. Accordingly, there is a demand for developing technology that enables transmitting and receiving a large amount of data at high-speed, as fast as a wired communication network. For efficiently transmitting a large amount of data, transmission of data using a plurality of cells was introduced.
A technology has been introduced for deploying a plurality of small Base Stations (BSs) having a relatively narrow coverage, such as a small cell, so as to transmit a large amount of data at a high speed, and to reliably transmit and receive data in an environment where a plurality of User Equipments (UEs) are concentrated in a predetermined BS.
Also, dual connectivity has been introduced. The dual connectivity enables a UE to communicate using the small cell and an existing macro cell. In the dual connectivity situation, a UE may perform wireless communication with a plurality of BSs.
However, the UE uses a limited uplink transmission power to transmit an uplink channel and an uplink signal. Thus, there are demands i) for discussing a method of multiplexing and transmitting various uplink channels and uplink signals, ii) for discussing a method of distributing the limited transmission power of UE to a plurality of BSs that form dual connectivity, and iii) for defining standards for distributing transmission power to various channels and uplink signals transmitted in parallel. That is, the UE may not transmit an uplink channel and an uplink signal using dual connectivity if it fails to solve the problem associated with the standards for distributing transmission power with respect to each uplink channel and each uplink signal and for transmitting an uplink channel and an uplink signal. Furthermore, the BS may not accurately receive the corresponding uplink channel and the corresponding uplink signal.

Method of controlling the transmission power of uplink channels and signals and apparatuses thereof