There is provided a distortion measuring device including a Brillouin scattered light spectrum recording unit which records a spectrum of Brillouin scattered light generated in an optical fiber as a result of supplying incident light, a peak frequency approximating unit which acquires an approximated peak frequency at which the recorded spectrum takes a maximal value, a peak frequency deriving unit which derives a peak frequency at which the spectrum takes the maximal value within a range of a frequency determined based on a magnitude of the spectrum at the approximated peak frequency, amid a distortion deriving unit which derives distortion of the optical fiber based on the derived peak frequency.

1. Field of the Invention
The present invention relates to measurement of distortion of an optical fiber.
2. Description of the Prior Art
Conventionally, Brillouin scattered light is coherently detected by supplying an optical fiber with pulsed light generated by pulsing continuous wave light to acquire Brillouin scattered light from the optical fiber (refer to FIG. 8 of Japanese Laid-Open Patent Publication (Kokai) No. 2001-165808). The coherent detection is carried out by multiplexing the Brillouin scattered light and intensity-modulated light obtained by applying intensity modulation to the continuous wave light at a predetermined frequency, for example. It should be noted that the intensity-modulated light includes a carrier light component and side band light components of optical frequency.
A signal corresponding to the Brillouin scattered light is extracted by a filter form a result of the coherent detection thereby obtaining a power spectrum of the Brillouin scattered light. It should be noted that the power spectrum of the Brillouin scattered light is acquired while the predetermined frequency is being changed. Moreover, a peak frequency where the power of the Brillouin scattered light takes the maximum value is acquired by fitting a predetermined function (such as a Lorentzian function) to the power spectrum of Brillouin scattered light. A value of distortion of the optical fiber is obtained based on the peak frequency.
FIG. 12 shows an example of a distortion distribution of an optical fiber FIG. 12 is a chart associating the distortion with the distance from an incident end of the optical fiber according to prior art. According to the distortion distribution shown in FIG. 12, the optical fiber has a point A presenting a small distortion, and a point B presenting a large distortion. When pulsed light is supplied to the optical fiber having the distortion distribution shown in FIG. 12, there is obtained a power spectrum of Brillouin scattered light as shown in FIG. 13.
FIG. 13 is a chart associating the optical power with the optical frequency of the Brillouin scattered light according to prior art. As shown in FIG. 13, there is obtained a power spectrum "a" due to the point A and a power spectrum "b" due to the point B. In order to measure the distortion at the point B, it is necessary to acquire a peak frequency fb of the power spectrum "b".
However it is difficult to precisely acquire the peak frequency fb. FIG. 14 shows an actually-measured peak frequency fp acquired by fitting the predetermined function (such as a Lorentzian function) to the power spectrum of the Brillouin scattered light according to the prior art shown in FIG. 13.
In FIG. 13, the power spectrum is shown as a solid line. However, the data of the power spectrum is actually discrete as shown in FIG. 14, and thus requires fitting. The result of the fitting to the power spectrum is influenced by the power spectrum "a" in addition to the power spectrum "b". As a result, the actually-measured peak frequency fp where the result of the fitting takes the peak is displaced from the peak frequency fb. It is thus difficult to precisely measure the distortion of the optical fiber at the point B.

Distortion measuring device, method, program, and recording medium


A system and method for managing performance metric information is provided. Baseline performance metrics, such as network bandwidth capabilities, of various client computing devices may be obtained. The baseline performance metrics can be used to separate client computing devices into one or more groups. Based on the groupings, subsequent performance metrics associated with the one or more monitored groups can be collected in a manner to mitigate performance latencies associated with the baseline performance metric. The subsequent performance metrics can be processed to determine which metrics correspond to a potential performance problem.

Generally described, computing devices, such as personal computers, can access various content via a communication network, such as an intranet or the Internet. In a typical environment, a computing device executes a software application; such as a browser software application, that is configured to communicate over the communication network to acquire content from other computing devices (e.g., content providers) connected to the communication network. In a more complex embodiment, the browser software application on the client computing device can also execute additional software code, such as scripts, etc., provided by a content provider that are designed to facilitate a user experience while accessing content. In a similar light, content providers on the communication network can correspond to a variety of network-enabled services that are designed to facilitate access to content for computing devices and/or the user experience associated with the access of the content.
For many content providers, such as commercial content providers, the user experience associated with computing devices accessing content, such as the time required to access and render content on the display screen, can be a key factor to the operation of the content provider. Nevertheless, in a typical computing system, identifying whether the typical user experience regarding the time to access content is outside of the scope of acceptable standards and an accompanying cause for associated delays can be difficult. This is especially true in systems in which one or more computers are connected via a network.
In one aspect, a diminished user experience regarding the time to access content can be associated with latencies caused by the execution of the additional code by the browser software application on a client computer. In another aspect, a diminished user experience regarding the time to access content can be associated with latencies caused by the software code executing on a content provider computer. In both of the above-mentioned aspects, the latencies caused by the software code may be previously unknown to the content provider. In still a further aspect, a diminished user experience regarding the time to access content can be associated with communication bandwidth latencies caused by the individual connection to the communication network by each computing device (e.g., dial-up, DSL, cable modem, etc.). Although user experience regarding the time to access content can be measured from a start time associated with a content access request by a computing device until a finish time associated with the display of the content on the same computing device, current methodologies cannot isolate latencies associated with a content provider (e.g., latencies caused by the executable code on either the computing device or the content provider) from latencies associated by the computing devices network connection.

Monitoring computer performance metrics utilizing baseline performance metric filtering


In a DRAM having two I/O lines commonly provided for reading and writing data and an amplifying circuit for providing a read data signal by amplifying potential difference between the two I/O lines, a potential difference control circuit 8 is provided which includes detecting circuits each having a parallel connected circuit of two MOS transistors each being diode-connected, and a switch circuit which is rendered conductive only at data reading.. Since the maximum value of the potential difference between the two I/O lines during data reading is controlled to several times that of the threshold voltage of a MOS transistor, the time necessary for equalizing the I/O lines at data reading can be reduced. Consequently, the speed of change of the output potential of the amplifying circuit changing to the potential corresponding to the data stored in the memory cell MC is increased, and therefore the access time is reduced.

1. Field of the Invention
The present invention relates to a semiconductor memory device and operation method thereof and, more specifically, to a semiconductor memory device and operation method thereof in which data stored in a memory cell is read by utilizing potential difference between two bit lines.
2. Description of the Background Art
Generally, in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), memory cells are arranged in a plurality of rows and columns, and two bit lines are provided corresponding to each column of the memory cells.
In data reading, potential of one of the two bit lines corresponding to the column including the memory cell from which data is to be written rises, and potential of the other one lowers. Potential of which one of the two bit line rises (or lowers) depends on the data stored in the memory cell. Therefore, a signal provided by amplifying the potential difference between these two bit lines is regarded as the data stored in the memory cell.
FIG. 10 is a schematic block diagram showing the whole structure of a conventional DRAM. A general structure and operation of the conventional DRAM will be described with reference to FIG. 10.
In the following description in this specification, a low-active signal is represented by a reference character with "/", and a signal line transmitting the low-active signal is represented by a reference character with "/".
A memory cell array 61 includes memory cells MCs arranged in a plurality of rows and columns, a plurality of word lines WL provided corresponding to the plurality of rows, and two bit lines BL and /BL provided corresponding to each of the plurality of columns. All bit line pairs BL and /BL are connected to a sense amplifier group 60 and a bit line equalizer 59.
The operation of the DRAM when data is read from memory cell array 61 is as follows.
When data is read from memory cell array 61 address buffer 54 takes and buffers external address signals A0-An and applies column address signals CA0-CA(n-1) designating one of the memory cell columns in memory cell array 61, row address signals RA0-RA(n-1) designating one of the memory cell rows of the memory cell array 61, and a signal An of the most significant bit of the external address signals A0-An to column decoder 57, row decoder 58 and I/O control circuit 53, respectively.
Each word line WL is commonly connected to all memory cells MCs arranged in the corresponding row, and each bit line BL, /BL is commonly and alternately connected to the memory cells MCs arranged in the corresponding column.
Row decoder 58 decodes row address signals RA0-RA(n-1) from address buffer 65, and activates to a high level one word line provided corresponding to the row of the memory cells designated by the row address signal out of the word lines WL in memory cell array 61. Consequently, it becomes possible to exchange data signal between each memory cell MC connected to the activated word line WL corresponding to the row address signal and the bit line BL or /BL connected to the memory cell MC. The potential of the bit line BL or /BL connected to the memory cell MC changes dependent on the data stored in each memory cell MC connected to the one word line WL.
Sense amplifier group 60 includes a plurality of sense amplifiers (not shown) provided corresponding to all bit line pairs BL, /BL in memory cell array 61. Each sense amplifier amplifies potential difference between two bit lines BL and /BL constituting the corresponding bit line pair BL, /BL.
I/O gate.multidot.I/O line 62 includes a pair of I/O lines transmitting signals of complementary potential levels, and an I/O gate constituted by a plurality of transfer gates provided between the I/O line pair and the respective sense amplifiers in sense amplifier group 60.
Column decoder 67 decodes column address signals CA0-CA(n-1) from address buffer 54 and outputs a signal for controlling the transfer gate such that only the sense amplifier connected to one pair provided corresponding to the column of the memory cells designated by the column address signal out of the bit line pairs BL, /BL in memory cell array 61 is electrically connected to the I/O line pair.
An I/O line potential control circuit 5 amplifies potential difference between two I/O lines constituting the I/O line pair and applies it to data output buffer 56.
Data output buffer 56 amplifies an output signal from I/O line potential control circuit 5 and externally outputs the resulting signal as read data from memory cell array 61.
The operation of writing data to memory cell array 61 will be described.
Address buffer 54, column decoder 57, row decoder 58 and I/O gate.multidot.I/O line 62 operate in the same manner as in data reading from memory cell array 61.
A data input buffer 55 amplifies an externally input data signal and applies the same to I/O line potential control circuit 5.
I/O line potential control circuit 5 amplifies an output signal from data input buffer 55 and applies complementary potentials to the two I/O lines constituting an I/O line pair.
These two I/O lines are connected electrically to only one sense amplifier provided corresponding to the pair corresponding to one column of the memory cells designated by column address signals CA0-CA(n-1) out of the bit line pairs BL, /BL in memory cell array 61. Therefore, the complementary potentials on the two I/O lines are transmitted to the two bit lines BL and /BL provided corresponding to one column of memory cells designated by column address signals CA0-CA(n-1) through one sense amplifier.
In memory cell array 61, only one word line WL provided corresponding to one row of memory cells designated by row address signals RA0-RA(n-1) has been activated. Therefore, potential of either one of the two I/O lines is supplied to one bit line BL or /BL connected to one (selected) memory cell MC which is arranged at an intersection of one column designated by column address signals CA0-CA(n-1) and one row designated by row address signals RA0-RA(n-1). Consequently, the external input data signal is written to the selected memory cell MC through the bit line BL or /BL which is connected thereto.
In the DRAM, data stored in each memory cell MC becomes extinct as time passes. In order to avoid such phenomenon, a so-called refreshing is carried out in which the same data as stored in each memory cell MC is automatically rewritten at every prescribed time period. The length of the prescribed period is shorter than the time necessary for the stored data of each memory cell to become extinct.
A refresh control circuit 51 and a refresh counter 52 are circuits provided for refreshing.
Refresh control circuit 51 instincts refresh counter 52 to output internal address signals Q0-Q(n-1) to.
Refresh counter 52 successively generates sets of address signals Q0-Q(n-1) representing respective addresses of the memory cells MCs in memory cell array 61 at every prescribed time period under control by refresh control circuit 51, when neither data writing to the memory cell MC of the address designated by external address signals A0-An nor data reading from the memory cell MC of the address designated by external address signals A0-An is carried out.
I/O control circuit 53 activates either one of data input buffer 55 or data output buffer 56 while it is receiving the signal An of the most significant bit from address buffer 54, and inactivates both data input buffer 55 and data output buffer 56 while it is not receiving the signal An of the most significant bit.
More specifically, in a period when external control signal /WE is at a low level, that is, when data is to be written to memory cell array 61, I/O control circuit 53 activates data input buffer 55. In the period when external control signal /WE is at a high level, that is, when data is to be read from memory cell array 61, I/O control circuit 53 activates data output buffer 56.
A particular circuit operation of address buffer 54 when neither data writing nor data reading to and from the memory cell MC designated by external address signals A0-An is to be carried out will be described.
Instead of external address signals A0-An, address signals Q0-Q(n-1) generated by refresh counter 52 are taken by address buffer 54. Address buffer 54 buffers the same and provides the resulting row address signals RA0-RA(n-1) and column address signals CA0-CA(n-1) to row decoder 58 and column decoder 57, respectively.
Column decoder 57, row decoder 58, sense amplifier group 60 and I/O line potential control circuit 5 carry out the same operation as in data reading from memory cell array 61 responsive to external address signals A0-An and the same operation as in data writing to memory cell array 61 responsive to external address signals A0-An, every time the output signal from address buffer 54 changes. Therefore, data stored in all memory cells MC in memory cell array 61 are successively refreshed in accordance with the addresses.
In such periods, the signal An of the most significant bit is not applied to I/O control circuit 53 from address buffer 54, and therefore data input buffer 55 and data output buffer 56 are inactive.
A bit line equalizer 59 electrically connects two bit lines BL and /BL constituting each bit line pair to equalize the potentials to an intermediate potential between high and low levels when neither data writing nor data reading based on external address signals A0-An and on address signals Q0-Q(n-1) generated by refresh counter 52 is carried out.
Similarly, in such a period, I/O line potential control circuit 5 electrically connects two I/O lines so as to make even the potentials thereof.
A clock generator 50 generates clock signals for controlling refresh control circuit 51, address buffer 54, column decoder 57, row decoder 58 and the like based on external control signals /RAS, /CAS, and /WE such that these circuits operate in the above described manner.
FIG. 11 is a partial circuit diagram showing the internal structure of the I/O gate.multidot.I/O line 62. FIG. 11 shows, as a representative, only a circuit portion provided corresponding to arbitrary two columns of memory cells in memory cell array 61.
Referring to FIG. 11, all sense amplifiers 610 are connected to a common sense amplifier driving circuit 620 in sense amplifier group 60.
Sense amplifier driving circuit 620 is controlled by a trigger signal .phi.s from clock generator 50 of FIG. 11 and drives all sense amplifiers 610 when data is to be written to memory cell array 61 and when data is to be read from memory cell array 61.
Each sense amplifier 610 is a differential amplifier connected to the two bit lines BL and /BL which are connected to the corresponding column of the memory cell.
I/O gate is constituted by an N channel MOS transistor T1 connected between each bit line BL and one of the two IO lines, and an N channel MOS transistor T2 connected between each bit line /BL and the other one of the I/O line /IO.
Gates of transistors T1 and T2 which are respectively connected to two bit lines BL and /BL provided corresponding to the same column of memory cells are connected to column decoder 57 of FIG. 10 through the same signal line CY. Column decoder 57 decodes column address signals CA0-CA(n-1) from address buffer 54 of FIG. 10, and sets to the high level only one of the signal lines CY which is connected to the gates of transistors T1 and T2 provided corresponding to the column of memory cells designated by the column address signals, and sets others to the low level. Consequently, only the two transistors T1 and T2 provided corresponding to the one column of the memory cells are turned ON, and two bit lines BL and /BL provided corresponding to the column of the memory cells are electrically connected to the two IO lines, that is, IO and /IO.
An I/O line equalizer 500 and an amplifying circuit 510 are included in I/O line potential control circuit 5 of FIG. 10. Twc I/O lines IO and /IO are both connected to I/O line equalizer 500 and amplifier circuit 510.
FIG. 12 is a circuit diagram showing the structure of I/O line equalizer 500.
Referring to FIG. 12, I/O line equalizer 500 includes two N channel MOS transistors T3 and T4 respectively connected between power supply Vcc and two I/O lines IO and /IO, and a P channel MOS transistor T5 and N channel MOS transistor T6 connected parallel to each other between two I/O lines IO and /IO.
A control signal /.phi..sub.w output from clock generator 50 of FIG. 10 is commonly applied to the gates of transistors T3 and T4.
Control signals .phi..sub.EQ and /.phi..sub.EQ having complementary potentials output from clock generator 50 of FIG. 10 are applied to the gate of transistor T5 and to the gate of transistor T6, respectively.
FIG. 13 is a circuit diagram showing a structure of amplifying circuit 510 of FIG. 11.
Referring to FIG. 13, amplifying circuit 510 is a current mirror type amplifier including a P channel MOS transistor T7 and N channel MOS transistors T9 and T11 connected in series between power supply Vcc and the ground Vss, and a P channel MOS transistor T8 and N channel MOS transistor T10 connected in parallel to transistors T7 and T9.
Gates of transistors T7 and T8 are connected to a node of transistors T7 and T9.
Gates of transistors T9 and T10 are connected to the two I/O lines IO and /IO of FIG. 11, respectively.
A control signal .phi..sub.P output from clock generator 50 of FIG. 10 is applied to the gate of transistor T11.
When data is written to memory cell array 61, an output potential of data input buffer 55 of FIG. 10 is applied to a connected point (a node N4) between transistors T8 and T10. When data is read from memory cell array 6, a potential .phi..sub.OUT of this node N4 is supplied as an output from the amplifying circuit 510 to data output buffer 56 of FIG. 10.
Circuit operation for reading data from memory cell array 61 of the DRAM will be described in greater detail with reference to FIGS. 11 to 15.
FIGS. 15(a) to 15 (l) comprise a timing chart showing potential changes at some nodes in the DRAM during data reading.
For convenience of description, output signal lines of bit lines, word lines, memory cells, sense amplifiers, transistors constituting the I/O gate and of column decoder 57 shown in FIG. 11 are denoted with reference characters in parenthesis ( ).
A circuit operation for successively reading data from memory cells MC1 and MC2 of FIG. 11 will be described as an example.
First, by row decoder 58, potential of one word line WL1 out of the word lines in memory cell array 61 is raised to a high level as shown in FIG. 14(a). Consequently, dependent on the data stored in each of the memory cells connected to the one word line WL1, potentials on bit lines connected to the memory cell changes.
FIG. 14 is a schematic diagram showing the structure of sense amplifier 610 and of memory cell MC. An arbitrary one column of memory cells is shown as a representative in FIG. 14.
Referring to FIG. 14, each memory cell MC includes an N channel MOS transistor TR and a capacitor C connected in series between the corresponding bit line BL or /BL and a low potential source such as the ground. The gate of transistor TR in each memory cell MC is connected to a word line WL corresponding to the memory cell MC. In each memory cell MC, the potential at the node of transistor TR and capacitor C corresponds to the data stored in the memory cell MC. More specifically, the stored data in each memory cell MC has the logic value of "1" and "0" when the potential at the node between the transistor TR and the capacitor C included therein is at a high level and at a low level, respectively.
Therefore, when one word line WL attains to a high level, the transistor TR is turned ON in each of the memory cells MC connected to the word line WL. Therefore, the potential of the bit line BL or /BL connected to each of memory cells MC out of the memory cells connected to the word line WL which store data "1" slightly increases because of the charges supplied from the capacitor C of the corresponding memory cell MC. The potential of the bit line BL or /BL connected to each of the memory cells MC connected to the word line WL which store data "0" slightly lowers because of the charges drawn to charge capacitor C of the corresponding memory cell MC.
In this manner, if a memory cell MC stores data "1", the potential of the bit line BL or /BL connected to this memory cell MC slightly increases in response to the rise of the potential of the word line WL connected to the memory cell MC. On the contrary, if the memory cell MC stores data "0", the potential of the bit line BL or /BL connected to the memory cell MC slightly lowers in response to the rise of the potential of the word line WL connected to the memory cell MC. In the period when neither data writing nor data reading is carried out to and from the memory cell array 61, the bit lines BL and /BL provided corresponding to each column of memory cells are set to the equal potential by the bit line equalizer 59 of FIG. 10. Therefore, when data is to be read, a slight potential difference is generated between the two bit lines BL and /BL provided corresponding to each column of memory cells in response to the rise of the potential of one word line WL.
Sense amplifier 610 includes a P channel MOS transistor 310 and an N channel MOS transistor 320 having their gates connected to the bit line BL, and a P channel MOS transistor 330 and an N channel MOS transistor 340 having their gates connected to the bit line /BL.
Transistors 310 and 320 are connected in series between signal lines 350 and 360 connected to sense amplifier driving circuit 620 of FIG. 11. Similarly, transistors 330 and 340 are connected in series between these signal lines 350 and 360.
In data reading, sense amplifier driving circuit 620 supplies supply potential and the ground potential to the signal lines 350 and 360, respectively, so as to drive all sense amplifiers 610.
Referring to FIG. 14, when the potential of bit line BL slightly increases at data reading, transistor 320 becomes a shallow conductive state (with large resistance value) in sense amplifier 610. Consequently, a voltage drop occurs at the gate connecting point of transistors 330 and 340 and at node N2. In response to the voltage drop, transistor 330 is also rendered to a shallow conductive. Consequently, voltage rises at gate connecting point between transistors 310 and 320 and at node N1. Because of the rise of potential, transistor 320 is rendered deep conductive, and lowers the potential at the gate connecting point of transistors 330 and 340 and at node N2 to the ground potential supplied to the signal line 360. In response, transistor 330 is also rendered to deep conductive, and the potential of node N1 rises to the supply potential supplied to the signal line 350. The potential at node N2 of transistors 310 and 320 and the potential at node N1 of transistors 330 and 340 are the outputs from sense amplifier 610.
In this manner, the potential of bit line BL is raised to the supply potential by means of sense amplifier 610, while the potential of bit line /BL is lowered to ground potential by the sense amplifier 610. Namely, the potential difference generated between bit lines BL and /BL is enlarged by means of the sense amplifier 610 to the difference voltage between the supply potential and the ground potential.
When the potential of bit line BL lowers slightly at data reading, transistor 310 in sense amplifier 610 is rendered shallow conductive in response, thus raises the potential of the gate connecting point of transistors 330 and 340. In response, transistor 340 is also rendered shallow conductive, and the potential at the gate connection point of transistors 310 and 320 lowers. Consequently, transistors 310 and 340 are rendered deep conductive, the potential of node N1 is lowered to the ground potential, and the potential at node N2 is raised to the supply potential.
In this manner, the potential of bit line BL is decreased to the ground potential by means of the sense amplifier 610, while the potential of bit line /BL is raised to the supply potential by means of the sense amplifier 610. Namely, in this case also, the slight potential difference generated between bit lines BL and /BL is enlarged to the difference voltage between the supply potential and the ground potential.
Referring to FIG. 11, assume that the data stored in memory cell MC1 and the data stored in memory cell MC2 are "1" and "0", respectively.
In response to the rise of the potential of the word line WL1 (See FIG. 15(a), potentials at bit lines BL1 and BL2 slightly rises and lowers, respectively, from the equalized potential, as shown in FIGS. 15(b) and (c). The potentials on bit lines /BL1 and /BL2 are maintained at the intermediate potential immediately after the rise of the potential on word line WL1, as shown in FIGS. 15(b) and (c).
Control signal .phi..sub.S attains to a high level immediately after the rise of the potential of the word line WL1 (see FIG. 15(d)). Sense amplifier driving circuit 620 drives all sense amplifiers 610 while the potential of the control signal .phi..sub.S is at the high level.
Therefore, the potentials on bit lines BL1 and /BL2 are raised to the supply potential in response to the rise of the potential of the control signal .phi..sub.S. The potentials of bit lines /BL1 and BL2 are decreased to the ground potential in response to the rise of the potential of the control signal .phi..sub.S.
After the control signal .phi..sub.S attains to the high level, the potentials of signal lines CY1 and CY2 are successively set to and maintained for a prescribed time period at a high level, as shown in FIGS. 15(f) and (g).
While the potential of signal line CY1 is at the high level, transistors T1-1 and T2-1 are ON. Therefore, potentials on I/O lines IO and /IO are determined by the potentials on bit lines BL1 and /BL1, respectively.
Similarly, while the potential of signal line CY2 is at the high level, transistors T1-2 and T2-2 are ON, and therefore potentials on I/O lines IO and /IO are determined by the potentials on bit lines BL2 and /BL2.
The potential of control signal /.phi..sub.W is always at the high level during data reading, as shown in FIG. 15(e). The potential of the control signal .phi..sub.EQ is maintained at the high level while the potential of any one of the output signal lines of column decoder 57 is at the high level as shown in FIG. 15(h), and accordingly, the potential of the control signal /.phi..sub.EQ is maintained at the low level while the potential of any one of the output signal lines of the column decoder 57 is at the high level as shown in FIG. 15(i).
Therefore, in data reading, the transistors T3 and T4 are ON in I/O line equalizer 500, and transistors T5 and T6 are OFF only when one of the output signal lines of column decoder 57 is at the high level.
Therefore, the I/O lines IO and /IO are fixed to the potential (Vcc-Vth) lower than the supply potential by the threshold voltage V.sub.TH of transistor T3 or T4, regardless of the output potentials of the sense amplifiers, when the potentials of the output signal lines of column decoder 57 are not at the high level. Therefore, immediately before the potential on signal line CY1 attains to the high level, the potential on the I/O line IO is lower than the potential of bit line BL1 by the threshold voltage Vth mentioned above, and potential of I/O line /IO is higher than the potential of bit line /BL1. Similarly, immediately before the potential of signal line CY2 attains to high level, the potential of I/O line IO is higher than the potential of bit line BL2 and the potential between I/O and IO is lower than the potential of bit line /BL2 by said threshold voltage V.sub.TH.
Therefore, when the potential of signal line CY1 attains to the high level, the potential on I/O line IO begins to rise to the supply potential because of the charges entering from bit line BL1, while the potential on I/O line /IO begins to lower toward the ground potential because of charges flowing out to bit line /BL1 (see FIG. 15(j)).
When the potential of signal line CY1 returns to the low level, transistors T5 and T6 turn ON in I/O line equalizer 500, and therefore, the potential of I/O line IO begins to lower, while the potential of I/O line /IO begins to rise. Finally, the potentials of I/O lines IO and /IO become equal to each other.
When the potential of signal line CY2 attains to the high level, transistors T5 and T6 are again turned OFF in I/O line equalizer 500. Therefore, because of the charges flowing out from the bit line I/O line IO to the bit line BL2, the potential of I/O line IO begins to lower to the ground potential, while the potential of I/O line /IO begins to rise because of the charges flowing in from bit line /BL2 to I/O line /IO.
When the potential of signal line CY2 returns to the low level, transistors T5 and T6 in I/O line equalizer 500 are again turned on. Therefore, the potentials of I/O lines IO and /IO rises and lowers, respectively, and finally, they are fixed at a potential lower than the supply potential by the respective threshold voltages V.sub.TH of transistors T3 and T4.
As shown in FIG. 15(k), control signal .phi..sub.P is kept at high level for a prescribed time period after any one of the output signal lines of column decoder 57 attains high level.
Namely, after the potentials of I/O lines IO and /IO begin to change dependent on the potentials on bit lines BL1 and /BL1 and after the potentials of I/O lines IO and /IO begin to change dependent on the potentials on bit lines BL2 and /BL2, transistor T11 turns ON in the amplifying circuit 510.
Referring to FIG. 13, when transistor T11 turns ON, one of the transistors T9 and T10 turns on dependent on the magnitude of the gate potentials of transistor T9 and T10, and thus supplies a current flowing through transistor T11 to the ground V.sub.SS.
More specifically, when the gate potential of transistor T9 is higher than the gate potential of transistor T10, transistor T9 turns on and supplies a current whose magnitude corresponds to the difference between these gate potentials to transistor T11. When the gate potential of transistor T10 is higher than the gate potential of transistor T9, transistor T10 turns ON and supplies a current whose magnitude corresponds to the difference between these gate potentials to transistor T11.
When transistor T9 turns on, the potential at node N3 lowers because of the current flowing through transistors T9 and T11 to the ground V.sub.SS. When the potential of node N3 becomes lower than the threshold voltage V.sub.TH of transistor T8, transistor T8 is rendered conductive and therefore, a current flowing from power supply V.sub.CC to the node N4 is generated. Meanwhile, since transistor T10 is OFF, the potential of node N4 is at the supply potential.
When transistor T10 is rendered conductive, the potential at node N4 lowers because of the current flowing from node N4 through transistors T10 and T11 to the ground V.sub.SS. Thus the potential at node N4 attains to a low level.
When control signal .phi..sub.P is at the low level, transistor T11 is OFF. Therefore, regardless of the gate potentials of transistors T9 and T10, potentials at nodes N3 and N4 are approximately at the supply potential.
Therefore, when the control signal .phi..sub.P attains a high level after the potential of signal line CY1 attains high level, the potential .phi..sub.OUT of node N4 is kept at the potential (supply potential) at which it has been kept, as shown in FIG. 15(l), since the gate potential of transistor T9 (potential of the I/O line IO) is higher than the gate potential (potential of I/O line /IO) of transistor T10. When the potential of the control signal .phi..sub.P attains to high level after the potential of signal line CY2 attains to the high level, the potential .phi..sub.OUT of node N4 begins to lower to a low potential as described above and shown in FIG. 15(l), since the gate potential of transistor T10 is higher than the gate potential of transistor T9.
Thereafter, when control signal .phi..sub.P returns to the low level, transistor T11 is turned off in the amplifying circuit 510, and thus the potential .phi..sub.OUT of node N4 returns to the supply potential.
In this manner, when the potential of the I/O line IO is increasing, the output potential .phi..sub.OUT of the amplifying circuit 510 attains to the high level, and when the potential of the I/O line IO is decreasing, it attains to the low level. Namely, when control signal .phi..sub.P is at the high level, the amplifying circuit 510 operates to output a potential whose level corresponds to the data stored in the selected memory cell MC1, MC2.
The length of the period in which the output signal line CY of column decoder 57 is maintained at the high level is set longer than the period from the potential difference between I/O lines IO and /IO begins to start until it reaches the maximum value V.sub.O.
As described above, in the conventional semiconductor memory device in which two bit lines are provided corresponding to each column of memory cells and data stored in a memory cell of the column of the memory cell is read utilizing the potential difference between the two bit lines, read data is provided by amplifying, by an amplifier, the potential difference generated between two. I/O lines when two I/O lines are connected to the two bit lines corresponding to the selected column of the memory cells.
Therefore, the earlier the timing of starting operation of the amplifier and the higher the speed of change of the output potential are in the amplifier, the shorter becomes the time from selection of one memory cell by the row decoder and the column decoder to the stabilization of the output potential of the amplifier corresponding to the data stored in the memory cell, that is, the shorter becomes the access time in data reading.
For example, in the DRAM shown in FIGS. 10-15, the earlier becomes the timing of the control signal .phi..sub.P to attain high level, the earlier the amplifying circuit 510 starts its operation. Therefore, the potential .phi..sub.OUT of the node N4 in the amplifying circuit 510 begins to change dependent on the potential difference between the I/O lines IO and /IO at an earlier timing.
More specifically, referring to FIG. 15, if the period from the time when potential of I/O line IO attains lower than the potential of I/O line /IO in response to the rise of the potential of control signal .phi..sub.EQ after the potential of CY2 attains high level, to the time when the potential of control signal .phi..sub.P attains to the high level, becomes shorter, the output potential .phi..sub.out of amplifying circuit 510 lowers more quickly to the potential corresponding to the data stored in memory cell MC2.
In the amplifying circuit 510, after the potential of control signal .phi..sub.P attains to the high level and the speed of change of the potential .phi..sub.out at node N4 is high, then the period .tau.2 becomes shorter in which period the amplifying circuit 510 starts its operation in response to the potential difference between the I/O lines IO and /IO generated by the control signal .phi..sub.EQ attaining high level after the potential of signal line CY2 has attained to the high level, and outputs a low level potential.
The speed of change of the output potential .phi..sub.out of the amplifying circuit 510 is also affected by the potential difference between I/O lines IO and /IO at the start of operation of the amplifying circuit 510.
More specifically, referring to FIG. 13, when transistor T11 is turned on with the gate potential of transistor T10 being sufficiently larger than the gate potential of transistor T9, the potential at node N4 quickly lowers to the low level, since a large current flows from node N4 through transistors T10 and T11 to the ground V.sub.SS. However, when the transistor T11 is turned ON with the gate potential of transistor T10 being slightly higher than the gate potential of transistor T9, the potential at node N4 lowers slowly to the low level, since a small current flows from node N4 through transistors T10 and T11 to the ground V.sub.SS.
In a conventional DRAM, during a period in which any one of the output signal lines of column decoder is at the high level, the potential difference between two I/O lines is very large. Therefore, the potential difference between the two I/O lines at the start of operation of the current mirror amplifier becomes small. This phenomenon will be described in detail with reference to FIGS. 11 to 13 and 15.
In both periods in which the signal line CY1 is at the high level and the signal line CY2 is at the high level, the potential difference between I/O lines IO and /IO reaches a very large value of the difference voltage V.sub.O between the supply potential and the ground potential, as shown in FIG. 15(j). Therefore, when the signal line CY1 attains the low level and then control signal .phi..sub.EQ attain the low level, it takes long to exchange charges between I/O lines IO and /IO through transistors T5 and T6. Consequently, the time .tau.1 necessary for the potentials of the I/O lines IO and /IO to be equal to each other becomes longer.
In the period when the signal line CY2 is at the high level, the potentials of the I/O lines IO and /IO must be the ground potential and the power supply potential, respectively, in response to the rise of control signal .phi..sub.EQ, contrary to the period in which the output signal line CY1 of the column decoder 57 is at the high level. However, since the time T1 necessary for the potential difference between I/O lines IO and /IO to reach zero from the fall of the potential of signal line CY1 is long, it takes long for the potential of the IO line IO and of /IO to reach the ground potential and to the power supply potential, respectively, in response to the rise of the control signal .phi..sub.EQ after the potential of signal line CY2 attains the high level.
Therefore, at the time when the control signal .phi..sub.P has risen to the high level after the potentials of the signal line CY2 and the control signal .phi..sub.EQ have both attained to the high level, the potential difference .DELTA.V between I/O lines IO and /IO is not large enough but still small. Therefore, in response to the rise of the control signal .phi..sub.P for reading data from memory cell MC2, the output potential .phi..sub.out of amplifying circuit 510 does not lower quickly but attains to the low level taking a long period of time T2.
As described above, when the data stored in the first and second memory cells which are read continuously are different from each other, if the time .tau.1 necessary for equalizing the potentials of the I/O lines IO and /IO is long, then the potential difference .DELTA.V between the I/O lines IO and /IO at the start of the operation of the amplifying circuit 510 for reading data from the second memory cell become small, and as a result, it takes long to read data from the second memory cell.
In order to avoid such phenomenon, the timing of rise of the control signal .phi..sub.P, that is, the timing of starting the operation of amplifying circuit 510 should be delayed to the time when the potential difference between the I/O lines IO and /IO becomes sufficiently large. By this method, the speed of change of the output potential .phi..sub.out of the amplifying circuit 510 is increased. Therefore, the time T2 necessary for the output potential .phi..sub.out of the amplifying circuit 510 to reach the potential corresponding to the data stored in the second memory cell from the rise of the control signal .phi..sub.P for reading data from the second memory cell becomes shorter. However, the time from when the potential of signal line CY2 attains to high level to when control signal .phi..sub.P attains to the high level for reading data from the second memory cell becomes longer. Therefore, the access time in data reading cannot be improved by this method.

Semiconductor memory device with restricted potential amplitude of data lines and operation method thereof


The opto-ceramics and optical elements of the present invention are transmissive to visible light and/or to infrared radiation. They consist of a crystal combination in which individual crystallites have a cubic structure of the type Y2O3 and are made from In2O3 or a mixture of oxides of the type X2O3 in which X=Y, Lu, Sc, Yb, In, Gd, or La. Also mixtures of X2O3 with oxides having different stoichiometries, such as zirconium and hafnium oxide, are possible, as long as the cubic structure of the opto-ceramic is maintained. The optical elements prepared from the opto-ceramics are particularly suitable for mapping optics, such as objectives having reduced chromatic aberrations, in particular with approximately apochromatic mapping behavior. The optical elements of the present invention may be used in lens systems in combination with lenses of glass, but also with other ceramic lenses.

1. The Field of the Invention
The present invention relates to opto-ceramics and refractive, transmissive or diffractive optical elements prepared from them. The opto-ceramics and optical elements are transmissive for visible light and/or for infrared radiation. The opto-ceramics consist of a crystal combination in which the single crystallites have a cubic structure of the type Y2O3, comprising alternatively the oxide In2O3 or a mixture of two or more oxides of the type X2O3, wherein X is selected from the group consisting of Y, Lu, Sc, Yb, In, Gd and La.
Also mixtures of X2O3 with oxides having a different stoichiometry, such as zirconium and hafnium oxide, are possible, as long as the cubic structure of the opto-ceramic is maintained.
In the following the ceramic is also referred to as an opto-ceramic. According to the present invention, an opto-ceramic (or ceramic) is, as mentioned above, a highly transparent, polycrystalline single-phase material comprising an oxide. Opto-ceramics are to be understood as a particular subgroup of ceramics. "Single phase" means that more than 95% by weight, preferably at least 97% by weight, more preferably 99% by weight, and most preferred 99.5 to 99.9% by weight are in the crystalline form of the intended composition.
The optical elements, which may be prepared from the opto-ceramics, are particularly suitable for use in mapping optics, for example objectives having reduced chromatic aberrations, in particular with approximately apochromatic mapping behavior. The optical elements made of transparent ceramic may be used in lens systems in combination with lenses of glass, but also with other ceramic lenses, in particular also in digital cameras, mobile phone cameras, in the field of microscopy, microlithography, optical data storage or other applications in the field of consumer or industrial applications.
2. The Related Art
The main aim in the development of mapping optics is to attain sufficient optical quality with a compact optical set-up, which is as lightweight as possible. In particular for applications in the field of digital image detection in electronic apparatuses, such as digital cameras, objectives of mobile phones and the like, the mapping optic has to be constructed very small and lightweight. In other words, the total amount of mapping lenses must be minimal. This requires transparent materials with high refractive index and a dispersion which is as low as possible to thus allow the design of very compact mapping optics having approximately apochromatic mapping behavior.
In the case of microscopy, nearly diffraction-limited mapping optics is necessary for the ocular as well as the objective.
In the field of defense, transparent optics are required which have high transmittance in the visible (380 to 800 nm) and also in the infrared spectral range up to 8,000 nm, ideally up to 10,000 nm and, in addition, which are resistant against influences from outside, such as mechanical action, shock, temperature, change of temperature, pressure etc.
For many other technologies the same applies, for example for digital projection and for display techniques. But also in predominantly monochromatic applications, such as the optical storage technologies, compact systems can be realized by means of materials having high refractive index.
At the moment, the development of mapping optics is limited by the optical parameters of the available materials. By the available techniques of glass melting and glass forming, only such kinds of glasses having high quality can be produced which are below a line which approximately passes through the points defined by Abbe number=80/refractive index=1.7 and by Abbe number=10/refractive index=2.0 in an Abbe diagram plotting the refractive index against the Abbe number. This imaginary line is shown in FIG. 2a by a dotted line. In more detail, glasses having a refractive index of between about 1.9 and about 2.2 and an Abbe number in a range of between about 30 and 40 tend to be unstable, so that it is very difficult to produce such glasses in large amounts and with sufficient quality. Also glasses having a refractive index of between about 1.8 and about 2.1 and an Abbe number in a range of between about 30 and 45 tend to be unstable.
The definitions of refractive index (refractive number) nd, Abbe number vd and relative partial dispersion (for example Pg,F) are in principle well known for a person skilled in the art and are defined and described in more detail in specialized literature in the prior art. In the sense of the present invention, the terms are used according to the definitions in "The Properties of Optical Glass"; Hans Bach, Norbert Neuroth (Eds.), Berlin (i.a.): Springer, 1995.—(Schott series on Glass and Glass ceramics: Science, Technology, and Applications; 1); XVII, p. 410-2., corr. print. 1998, XVII, p. 414.
In addition to refractive index and Abbe number, the relative partial dispersion plays an important role in the selection of an optical material. If it is desired to prepare approximately apochromatic optics, materials having approximately the same relative partial dispersion, but a high difference in the Abbe number must be combined. If the partial dispersion Pg,F is plotted against the Abbe number (FIG. 2b), most glasses are on one line (the "normal line"). Therefore materials are desired having behavior with a different combination of Abbe number and relative partial dispersion.
At the moment materials, which are above the before mentioned imaginary line in an Abbe diagram, are exclusively single crystals or polycrystalline materials. However, the production of single crystals by means of the known crystal drawing processes is extremely costly and has enormous limitations with respect to chemical composition. Furthermore for most applications crystals cannot be produced close to the final format, so that this results in an enormous effort of post-processing. Although polycrystalline ceramics can be produced within a broader range of compositions, normally they have insufficient optical qualities, in particular with respect to the homogeneity of the refractive index and the transparency. Till today, only few ranges of compositions and structure types are known, in which transparent ceramics having sufficient optical quality can be produced.
Therefore, polycrystalline ceramics have only been used to a limited extent in optical applications till today. Thus for example, the Japanese Patent Publication JP 2000-203933 discloses production of polycrystalline YAG by means of a special sintering process. Recently, also the production of polycrystalline YAG of optical quality as a laser host material has been achieved, for example for doping with laser-active ions, for example Nd.
In U.S. Pat. No. 6,908,872 translucent ceramics are described which use barium oxide as an oxide, which has to be present in the ceramic. The thus obtained ceramics have a perovskite structure and are para-electric. However, ceramics containing such barium-containing phases having perovskite structure often have insufficient optical mapping quality. This is a result of the tendency of many perovskites to form distorted ferro-electric crystal structures and thus to loose their optical isotropy. Inter alia, this results in undesired double refraction of the crystals, from which the ceramic is built, and, in addition, the transmittance in the range of blue light (about 380 nm) is insufficient.
U.S. Pat. No. 3,640,887 describes production of opto-ceramics on the basis of cubic oxides of the stoichiometry X2O3 ("sesquioxides"). In an exemplary way, only optically active oxides are mentioned which are colored because of absorption bands in the visible (wavelengths of ca. 380 nm to 800 nm). As a sintering aid, i.a., ThO2 is used. This one is not desired due to toxicity, respectively radioactivity. The like belongs to U.S. Pat. No. 3,545,987.
U.S. Pat. No. 4,761,390 discloses a cover plate that substantially consists of a Y2O3 ceramic.
Also U.S. Pat. No. 4,755,492 describes a transparent ceramic Y2O3 as well as its production from powders, which are produced by oxalate precipitation processes. The applications relate to discharge vessels for high-pressure discharge lamps.
U.S. Pat. No. 4,098,612 describe transparent ceramics of mixed oxides of Y2O3 and Al2O3 for discharge vessels. Al2O3 may be contained in an amount of up to 5% by weight, which results in the absence of a cubic structure. The like belongs to transparent ceramic Y2O3 having high contents of La2O3 from U.S. Pat. No. 4,147,744. U.S. Pat. No. 4,571,312 and U.S. Pat. No. 4,747,973 describe opto-ceramics of the system Y2O3—Gd2O3 which, doped with lanthanides that are optically active in the UV-VIS (ultraviolet-visible range), are used as optically active scintillation materials for medical techniques.
JP 2003-128465 and WO 06/03726 describe production of opto-ceramics on the basis of Sc2O3 and Lu2O3. To them are added optically active additives and thus, they are of interest for laser systems.
US 2006/061880 and US 2006/062569 describe the combination of optical mapping systems consisting of at least one lens of ceramic and additional lenticular components of glass, but advantageous effects of the ceramic (owing to e.g. a convenient dispersion behavior) for the whole system is not mentioned. The ceramic lens with extremely high refractive index (nd=2.08) is in direct contact with a glass lens (nd=1.62). Particularly thus costly measures have to be taken to avoid the problem of light scattering associated with the high difference in nd. Thus e.g. in US 2006/062569, the ceramic lens must be connected with a glass lens, the light scattering must be reduced and distributed homogenously over the image detector by a special arrangement of this glass-ceramic-putty member in the optical mapping system.

This patent is subject to a terminal disclaimer.


An apparatus and a method are described for forming a chemical modulation of a substance present in a fluid stream, which utilize a movable device, such as a movable heater, to induce changes in the retention of a chemical substance flowing through the modulator tube. The modulator tube has an inlet, a first portion in communication with the inlet, a second portion in communication with said first portion, and an outlet in communication with said second portion. The method involves causing a chemical modulation by moving retention alteration device relative to a modulator tube.

Prior art devices have used moving retention alteration means, such as a moving heater, to form a chemical substance into a single chemical pulse within a tube. Such apparatus is described by DeFord in U.S. Pat. Nos. 3,043,127 and 3,057,183. Many devices employing moving members for injecting substances onto chromatographic columns are known. All such devices form chemical substances into substantially a single chemical pulse so long as deleterious chromatographic practices resulting in accidental peak splitting are avoided. These prior art devices suffer a disadvantage in that a substance is formed only into a single chemical pulse in a tube.
Another class of prior art devices is the comprehensive multidimensional gas chromatograph of Phillips and Liu. described in U.S. Pat. Nos. 5,196,039 and 5,135,549. These devices suffer a disadvantage in that resistive heaters used to form substances into multiple chemical pulses in a tube have shown a tendency to burn out in practice, and to present difficulties with manufacture.
The present invention solves the aforementioned problems.

Apparatus and method for chemical modulation

Board of Trustees of Southern Illinois University on Behalf of Southern Illinois University at Carbondale


Applicators for HDR brachytherapy for topical skin treatment which employ multiple channels for radioisotope sources, oriented by the applicator generally parallel to each other and to a desired treatment area skin surface. These applicators provide good radiation exposure uniformity. Filtration of undesirable low energy radiation may be employed using an attached filter element. The applicators are particularly adapted for the treatment of squamous and basal cell skin cancers or other skin lesions. The applicators may provide two or more source guides in various sizes and shapes are described.

Radiation treatment is very effective for the treatment of squamous cell and basal cell skin cancers for human patients. Historically, superficial 250 KV external beam radiation provided a good tool for such treatment with excellent control and cosmetic results. However, such equipment is no longer available, and is bulky, expensive, and requires highly skilled operators.
Currently, superficial radiation treatment with electron beams is provided for treating certain skin cancers through a long course of multiple therapy sessions (fractional therapy) which may require daily therapy for several weeks and the depth of the radiation dose for such therapy is usually several centimeters. Such a fractional course is long, expensive, and inconvenient to patients. In addition, cosmetic results from electron beam radiation therapy to the skin are often compromised due to irradiation of subcutaneous tissue underlying the desired treatment site which does not need to be targeted therapeutically.
In brachytherapy procedures, catheters or guide tubes are used which are, in some procedures a guide tube is used which is positioned externally at a desired orientation relative to a patient's skin area to be treated. A radioisotope source is loaded into the guide tube and is moved robotically inside the guide tube to topically expose tissue surrounding the source to a desired radiation dose and is thereafter withdrawn. This is referred to as high dose rate or HDR brachytherapy. This procedure is distinguished from low dose rate or LDR brachytherapy in which a radioisotope source is implanted for exposure over a long period (months or years) or implanted permanently. The radiation exposure dose of brachytherapy is intended to cause radiotoxicity and destroy targeted human tissue, for example cancerous skin cells.
In HDR brachytherapy for treating skin cancer, an applicator component is used which forms a fixture for supporting and orienting a brachytherapy guide tube and further for shielding radiation exposure along ray paths not providing desired exposure of the skin area to be treated. A brachytherapy treatment machine is used to accurately position the radioisotopes source in the guide tube during a treatment session. Typically the position of the radioisotope source is moved within the guide tube after stopping at dwell positions. A control wire inside a flexible brachytherapy guide tube is attached to the guide tube which is in turn mounted to the applicator. The brachytherapy treatment machine moves the radioisotope source to desired dwell positions on a time schedule within the applicator by moving the control wire.
Single channel brachytherapy applicators for treating skin cancers are known. These devices employed a single guide tube for the radioisotope source. The use of single channel brachytherapy applicators results in uneven radiation distribution to skin surface and superficial depth, resulting in a very high dose in the center area of the applicator as compared to peripheral regions in the treatment field area. Due to limitations of such devices, treatment of skin cancer has been limited due to lack of good applicators with standardized radiation distribution limited to several millimeters in depth. Another known system utilizes a single channel source oriented in a vertical orientation, which is also not conducive to uniform dose distribution pattern; this results in a very uneven dose distribution, relative low dose at center of applicator surrounded by a high dose zone then a very low dose at periphery of treatment area.

Skin HDR brachytherapy multichannel applicators and methods of brachytherapy treatment


Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.

Example embodiments of the present disclosure relate to a method of fabricating a semiconductor device, and in particular, to a method of fabricating a semiconductor device using a double pattering technology.
As a design rule of a semiconductor device decreases, it may be necessary to form fine patterns, allowing for the realization of highly-integrated semiconductor devices. For example, a double patterning technology (DPT) may be used to form a fine pattern, whose dimension can be smaller than the minimum feature size that can be achieved by a photolithography process. There is a difference in desired function and property between various semiconductor devices, and thus, it is useful to develop a double patterning technology capable of forming fine patterns with different widths.

Method of fabricating semiconductor device

Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do


An input pointer includes two top-surface switches and a rotary switch on the top surface of the main body, a protrusion on an imaginary center line on the bottom surface of the main body, and two bottom-surface switches at the sides of the protrusion. The two top-surface switches and the rotary switch are turned ON when pressed by a user's finger, whereas the bottom-surface switches are turned ON when the main body is tilted about the protrusion.

1. Field of the Invention
The present invention relates to input devices used as pointing devices and to input pointers for use in input devices.
2. Description of the Related Art
As computers have become more multifunctional in recent years, there is a growing need for pointing devices, functioning as computer input devices, that are capable of carrying out more functions of the computer. For example, some mice, the most widely used pointing devices, are provided with switches on the lateral surfaces of the main body, as well as on the top surface.
Many switches disposed adjacent to one another on a mouse, however, are more likely to cause the user to press an incorrect switch, which decreases the mouse operability. For this reason, there has been a demand for a mouse which is provided with many switches while still maintaining easy operability.
One possible approach for preventing the operability of a mouse from decreasing is to provide switches at sites other than the top surface and the lateral surfaces of the mouse so that the switches are not disposed close to one another. A mouse provided with a switch on the bottom surface is described in, for example, Japanese Unexamined Patent Application Publication No. 10-11211 (pages 2 to 3 and FIG. 1).
The mouse in Japanese Unexamined Patent Application Publication No. 10-11211, however, cannot have a switch disposed on the top surface of the main body due to its structure, and thus only a small number of switches are available with this mouse. More specifically, to operate the mouse in Japanese Unexamined Patent Application Publication No. 10-11211, the main body of the mouse needs to be tilted by pressing the left-front shoulder portion or the right-front shoulder portion of the mouse. The front portion of the mouse refers to the portion in contact with the user's fingertips, where switches are generally arranged. Thus, if a switch were arranged on the top surface of the main body of the mouse in Japanese Unexamined Patent Application Publication No. 10-11211, the switch on the top surface would also be pressed when the switch on the bottom surface is pressed. This means that the structure of the mouse in Japanese Unexamined Patent Application Publication No. 10-11211 does not assume that a switch is arranged on the top surface. Therefore, a method employed with the above-described mouse, that is, a method for providing switches on the bottom surface of the mouse does not achieve an object of providing a mouse with many switches while still maintaining high operability.
This is the reason there has been a growing need for pointing devices that are highly operable although provided with many switches for carrying out many functions of the computer.


A system and method for analyzing bodily fluid include a sample holder holding a bodily fluid sample, an image capture device generating an image of the bodily fluid sample comprising a plurality of fields of view. An image processor is programmed to determine a biofilm in the bodily fluid sample from the image, determine a biofilm area or volume within each of the plurality of fields of view to form a plurality of biofilm areas, determine a total biofilm area or total biofilm volume by adding the plurality of biofilm areas, determine a first value corresponding to a comparison of the total biofilm area or the total biofilm volume and a total volume of the bodily fluid sample, and classify the first value into a classification. An analyzer, using the classification, displays an indicator on a display for indicating the classification of the biofilm within the bodily fluid sample.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Biofilms are found, for example, on the surface of stones in rivers and ponds, in water pipelines, as dental plaque on teeth and on surgical implants. Microorganisms within biofilms appear to be less susceptible to biocides than their planktonic counterparts. The extracellular polymer and/or nutrient limitation associated with the position of organisms in the biofilm may alter sensitivity. Biofilms allow for the rapid spread of genetic material between the component microorganisms. Biofilm formation can have serious implications in industrial, environmental, medical and public health situations
It is important for doctors to be able to determine presence of biofilm a person may have. In addition, knowing the severity of the biofilm is also desirable. The use of cultures, antibodies, antigens or genetic material are often used in various tests.
Different types of bodily fluids may be examined such as blood, sputum, urine, stool, tissue, cerebral spinal fluid and mucus from the nose, throat or genital area.
Conventional analysis of bodily fluids may not be adequate for screening biofilms present in Lyme disease and other treatment resistant infections. Lyme disease is a blood borne disease with spirochete or biofilm present in Lyme disease samples. The identification of Lyme disease is often difficult.

Method and system for identifying objects in a blood sample


An automobile includes a plurality of frame-integrated hydraulic jacks includes a trunk mounted control panel in electrical communication with a power source and a plurality of jacks each being located beneath the automobile frame adjacent each wheel of the automobile. A plurality of flashing illumination is disposed upon the base of each jack and are in electrical communication with the control panel. The control panel permits a user to selectively raise or lower the automobile by the actuation of the plurality of jacks.

Over the course of a lifetime, almost every automobile will get at least one (1) flat or punctured tire. Quite often, fixing this situation usually involves accessing the underside of the automobile or lifting the vehicle in order to remove the flat tire, all the while performing this work along the side of a potentially busy road or highway. Usually this task is accomplished via assistance of a car jack which is included with most vehicles. The use of the jack typically involves the use of physical exertion through a lever or screw system to develop the power necessary to raise the vehicle to a height sufficient to remove the damaged tire and replace it with a spare or new tire.
Sometimes, the physical exertion required to operate the automobile's jack is beyond that which the operator of the automobile is capable. In those situations, the service of a tow truck is required to perform the necessary repairs or to tow the automobile somewhere where the proper equipment and maintenance personnel are available. Additionally, should the tire changing occur at night, the individual performing the tire changing task runs the serious risk of being hit by another automobile due to low or no viability. Likewise, depending upon the location of the stranded automobile, it may pose a significant road hazard to other motorists who may not see the stranded automobile in sufficient time to stop and avoid a collision. Such collisions are more than capable of producing significant property damage, injury or even death.
Many efforts have been made to address this problem such as U.S. Pat. No. 6,991,221, U.S. Pat. App. Pub. No. 2014/0217342, U.S. Pat. App. Pub. No. 2007/0013537 and U.S. Pat. No. 9,126,568. However, these devices are unsatisfactory in both desired effect and ease of operation. Accordingly, there exists a need for a means by which a damaged tire or tires can be removed and replaced at any roadside location, without the use of physical exertion, while illuminating the vehicle being changed. The development of the automobile with frame with integrated illuminated hydraulic jacks fulfills this need.


An actuating mechanism and method for sequentially translating a sheath member relative to an elongate member such as a balloon catheter movably inserted through the sheath includes a coupling structure constructed to enable selectively coupling or uncoupling of a drive member to the sheath member in order to drive translation of the coupled sheath member in one or more translation increments and to enable uncoupling of the drive member following each of said increments of retraction. In a particularly beneficial method of sheath retraction from a portion of an angioplasty balloon catheter on which a stent is mounted, the method includes coupling a drive structure to the sheath and driving translation of the coupled sheath relative to the catheter to expose the stent-mounted portion of the catheter, and then repeating the translational drive of the coupled sheath to further translate the sheath and expose a further incremental portion of the catheter, in order to produce sequential one-way movement of the sheath in controlled increments to attain exposure of the balloon catheter and the stent mounted thereon without disturbing its position.

The present invention relates to surgical angioplasty balloon instruments and procedures. More particularly, the present invention relates to an instrument, mechanism and procedure for retracting or withdrawing a protective sheath surrounding a balloon catheter having an angioplasty stent applied thereto, prior to implanting of the stent, following retraction of the protective sheath.
In order to improve the effectiveness of vascular angioplasty in relieving blockage or repairing cardiovascular damage, stainless steel mesh stents of tubular configuration have been developed for implantation into the vascular wall of a patient. The stent is introduced by a balloon catheter, the stent being carried by the expandable balloon portion of the catheter, which is expanded to attain expansion and implantation of the stent. The catheter and stent are protected by a surrounding sheath which is maintained in place over the stent during introduction to the implantation site, and which is then retracted to expose the stent prior to the expansive implantation procedure. The protective sheath prevents any potential slippage of the stent relative to the deflated balloon before and during the introduction and location of the stent at the implantation site. In addition, the sheath will cover the stent as it passes through the patient's vascular system, such that mesh material or edges of the stent are covered during introduction, which edges or portions could lead to abrasion or damage of the vascular tissue during introduction. Once the precise implantation site has been reached, the protective sheath must be carefully retracted to expose the stent for expansion and implantation. Unintended re-advancement of the sheath can cause its forward end to catch on the stent and produce slippage on a deflated balloon, resulting in displacement of the stent from the correct vascular implantation site. These and other disadvantages are eliminated by the mechanism, instruments and method in accordance with the present invention.


An auto focusing device for a camera includes a focus detecting section which detects a focused state of an image taking lens an AF mode setting section sets an AF mode of the camera to either a first AF mode or a second AF mode. An auxiliary light emitting section emits an auxiliary light to the object in association with the focus detecting operation by the focus detecting section if the object has a low luminance. An emission control section limits the number of times that the auxiliary light emitting section emits the auxiliary light to the object to one per a predetermined number of operations by the focus detecting section if the AF mode setting section has set the AF mode to the second AF mode.

1. Field of the Invention
The present invention relates to an auto focusing device for a camera and a method used in the auto focusing device for the camera for determining whether or not to emit an auxiliary light, and in particular, to an auto focusing device for a camera which detects a focus by emitting an auxiliary light to an object if the focus cannot detected.
2. Description of the Related Art
A large number of techniques are known with which if a focus cannot be detected, an auxiliary light is emitted to an object to detect the focus.
For example, with what is called single auto focusing, once the camera is focused, a focus detecting operation is locked. With this technique, an auxiliary light may be emitted if the results of the last auto focusing indicate that the focus cannot be detected owing to a low luminance. However, with what is called continuous AF which continuously performs a focus detecting operation after focusing or AF used for what is called continuous image taking in which images are continuously taken, when an auxiliary light similar to that used in the single AF is emitted, the light may become too intense depending on conditions for the object. That is, during the continuous AF or continuous image taking, when light emission control is performed which is similar to that used for the signal AF, the auxiliary light may be too glaring or batteries may be significantly consumed.
In view of these circumstances, various proposals have been made for auxiliary light emission control used for the continuous AF or continuous image taking.
For example, Jpn. Pat. Appln. KOKAI Publication No. 63-172226 proposes a technique to prohibit emission of an auxiliary light in a continuous image taking mode. Further, Jpn. Pat. Appln. KOKAI Publication No. 63-172227 proposes a technique to switch an AF mode to a single AF mode when an auxiliary light is emitted in a continuous AF mode. Moreover, Japanese Patent No. 2713870 proposes a technique with which once the camera is focused in the continuous AF mode, emission of an auxiliary light is prohibited during subsequent AF operations.

Auto focusing device for camera and method used in auto focusing device for camera for determining whether or not to emit auxiliary light


Disclosed are organic amine salts of azilsartan, a preparation method and use thereof. In particular, disclosed are organic amine salts of azilsartan, their preparation method, the pharmaceutical composition comprising the compound in a therapeutically effective quantity, and their use for the manufacture of antihypertensive medicaments.

Hypertension is a common cardiovascular disease, the main clinical syndrome of which is the arterial pressure is elevated persistently, and it often causes lesions of the heart, brain, kidneys and other vital organs and the corresponding consequences. China is one of the countries affected by hypertension in the world. In the past few decades, the estimated number adults with hypertension has increased from 30 million in 1960 to 59 million in 1980, and reached to 94 million people in 1991. The number is more than 200 million currently. Among the 3 million cardiovascular patients that die every year, 50% are associated with hypertension. In the United States, ⅓ of adults are suffering from hypertension. It is extremely urgent to develop effective antihypertensive drugs with less adverse reactions.
According to the mechanism of the drug, conventional antihypertensive drugs can be classified into central antihypertensive drugs, ganglion blockers, sympathetic nerve endings inhibitors, adrenergic blockers, vasodilators, diuretics, angiotensin converting enzyme inhibitors (ACEI), angiotensin receptor antagonists. Renin-angiotensin system (RAS) is a group of hormones or precursors interacting or regulating with each other secreted by kidney and liver, including renin, angiotensinogen, angiotensin I (Ang I), angiotensin II (Ang II), angiotensin-converting enzyme (ACE) and angiotensin receptor etc., in which Ang II is one of the strongest vasoconstrictors, having numerous biological activities.
Azilsartan medoxomil (the structure of formula A) is an angiotensin II receptor antagonist drug for treating hypertension developed by Takeda, which belongs to angiotensin II receptor antagonist drug (Sartans). Azilsartan medoxomil potassium salt, Edabi® as the trade name, was approved by the FDA. This drug is an oral medicament which can be used alone or in combination with other antihypertensive agents for the treatment of hypertension and related complications. Azilsartan medoxomil has a more significant effect in lowering blood pressure. Compared with losartan and olmesartan medoxomil, Azilsartan medoxomil is more efficient in reducing blood pressure (WHITE W B. Effects of the angiotensin receptor blocker azilsartan medoxomil versus olmesartan and valsartan on ambulatory and clinic blood pressure in patients with stages 1 and hypertension J. Hypertension, 2011, 57(3):413-420). Azilsartan medoxomil is a pro-drug, which can be rapidly hydrolyzed into Azilsartan and take action during absorption in the gastrointestinal tract. Azilsartan (the structure of formula B), the chemical name of which is 1-[[2′-(4,5-dihydro-5-oxo-1,2,4-oxadiazol-3-yl) [1,1′-biphenyl]-4-yl]methyl]-2-ethoxy-1H-benzimidazol-7-carboxylic acid, decreases blood pressure by selectively blocking the binding of angiotensin II to vascular smooth muscle AT1 receptor to block the vasoconstrictive effect of angiotensin II in vivo.

EP1992110668, U.S. Pat. No. 5,243,054A, and US20050187269 disclose the preparation method of Azilsartan and its analogues; Chinese patent CN100503605C discloses Azilsartan medoxomil potassium salt and the preparation and pharmacodynamic effect thereof; WO2010075347 discloses the pharmaceutical application and pharmacological activity of Azilsartan medoxomil and Azilsartan medoxomil potassium salt; CN101381366B discloses Azilsartan and Azilsartan medoxomil potassium salt.
However, subsequent research indicates that as there is a carboxyl group in the molecular structure of the direct active ingredient Azilsartan, the in vivo absorption is poor and it affects the efficacy of the drug, so Azilsartan is not easy to prepare into pharmaceutical dosage forms. In order to improve the bioavailability, Azilsartan has to be prepared into an ester by chemical modification, i.e. Azilsartan medoxomil, but its bioavailability is still not satisfied and its molecular structure becomes complex by such modification, which increases difficulty in synthesis and cost of production.

Organic amine salts of Azilsartan, preparation method and use thereof

Jiangsu Hansoh Pharmaceutical Group Co., Ltd.

Jiangsu Hansoh Medicine Institute Co., Ltd.


A system for collecting the flow of sand or sediment in a current comprising a catch basin, comprising a base structure having a bottom and a plurality of angled side walls, said bottom having at least one aperture, an external pipe affixed at a first end to the at least one aperture, at least two guides affixed to one or more ends of the catch basin to direct sand and sediment into the catch basin, each of said guides comprising a chute with curved sidewalls extending substantially parallel to the flow of current and a pumping system affixed to the second end of the external pipe to remove the sediment or sand from the basin.

Sand and sediment tends to accumulate in locations such as the entrances to harbors due to the deposit of sand and sediment by tidal flow of water. The existence of sandbars can create serious environmental and navigational hazards. Such accumulations require at least periodic dredging at great expense and disruption of water traffic.
The present invention is directed to a novel system which eliminates the accumulation of the sand or sediment that would normally be deposited on the bottom of an inlet, into a permanently located catch basin from which the sand/sediment can be continuously or periodically removed by water pumps capable of moving water and sand.
A number of U.S. patents have been devoted to the problem of preventing beach erosion and the like. U.S. Pat. No. 4,498,806 discloses a beach erosion jetty configuration wherein the jetties are curved to stop or prevent a vacuum effect which causes beach erosion. Swift currents running in or out of inlets create a Venturi effect that pulls sand-laden waters from nearby and sometimes distant shorelines. In accordance with the present invention, jetties are provided with curved ends that negate the loss of precious sand. Such curved jetties function as erosion control devices and actually stop and prevent erosion.
U.S. Pat. No. 4,023,369 discloses an apparatus and method carried out thereby for preventing formation of sand bars from sand or silt at the outlet of a body of water emptying from inland into another body of water, such as a lake or the sea and the like. At least one elongated gutter is provided at the outlet of a body of water from inland to another or receiving body of water, such as a lake or the sea. The gutter is disposed above the level of the water in the outlet and may or may not extend through the mouth of the outlet into the receiving body of water. Water is pumped into the gutter to an overflow condition so that it spills over the edges, and by gravity falls and creates a splash erosion condition.
U.S. Pat. No. 4,031,009 discloses a pre-cast reinforced concrete catch-basin of larger than conventional catch-basin dimensions, which includes a solid horizontal bottom wall with a solid, hollow, cylindrical side wall upstanding therefrom to about half the height of the catch-basin. The lower half thus forms a sealed, unapertured, undrained sump receptacle for collecting drain water and silt and allowing sand to settle out. The hollow, cylindrical, upper half contains leaching openings which extend through from the inside to the outside of the wall, from top to bottom, for discharging cleared water to the surrounding, stone-lined earth without plugging or clogging and without polluting nearby wells, brooks, etc.
U.S. Pat. No. 6,481,926 discloses a method and apparatus for land reclamation which includes utilizing groyne-like structures, including spaced stanchions to which are mounted porous screens and wherein the screens are vertically adjustable as material is deposited during the reclamation process. In some embodiments, the screens are carried by sleeves slidable on spaced stanchions. In other embodiments, the screens may be sectional and carried by multiple sleeves.
U.S. Pat. No. 5,174,681 discloses a permeable breakwater for submerged offshore or seawall retentive installation that includes a base and permeable opposed sides terminating at an upwardly projecting permeable wave wall. The breakwater is located offshore to cause moderate to heavy waves to break further offshore, thereby dissipating their energy before reaching the beach.
U.S. Pat. No. 5,888,020 discloses a sub-tidal platform adapted to be placed under water in front of a beach comprising a support structure having at least two upwardly extending, spaced-apart side walls extending along vertical planes. Each side wall has a bottom adapted to rest on a generally horizontal surface and a sloping, upwardly extending edge which is at an acute angle with respect to the bottom. A plurality of interconnecting members extends between the side walls for maintaining them in an upright position. The interconnecting members are positioned adjacent to the sloping edge of the side walls. A plurality of gates are pivotally connected to the interconnecting members of the support structure for controlling fluid flow through the space between the side walls. The gates open in response to incoming fluid flow through the gates and close in response to outgoing fluid flow in the opposite direction. The gates, when in their closed position, combine to form a sloping wall which substantially blocks the flow of fluid through the space between the side walls and deposits fluid-carried material in the space formed by the side walls and the sloped wall.
While there have been a number of prior art systems directed toward preventing beach erosion, there has not been a systems that adequately addresses the problem of preventing sand bar creation in inlets. There has not been a system that provides a simple, yet inventive basin which accumulates sand and sediment.
It is therefore an object of the present invention to provide a system which functions to prevent the accumulation of sediment in inlets and the like.
It is a further object of the present invention to provide a system for collecting sand and sediment, comprising singular or multi-piece casing.
It is an object of the present invention to provide a system which permits the removal of sand and sediment by means of a pump and piping.
These and other objects of the present invention will become apparent from the detailed description which follows.


Different colors are prepared for inner shapes that define different design ballistic patterns. Wear resistant coatings of the different colors are applied over outer surfaces of tube bodies having the design ballistic patterns corresponding to the colors of the wear resistant coatings to allow the design ballistic patterns to be identified by the colors of the wear resistant coatings.

1. Field of the Invention
The present invention relates to a choke tube attached to a muzzle of a barrel of a shotgun.
2. Description of the Related Art
A screw-in choke tube of a shotgun includes a tube body composed of carbon steel or stainless steel. A hard coating, such as a TiN film (titanium nitride film), a CrN film (chromium nitride film), a TiAlN film (titanium aluminum nitride) and a TiCN film (titanium carbide nitride film), is applied over the inner surface (the barrel) of the tube body in some proposed devises. This coating is effective to improve the wear resistance on the inner surface. Such coating for gun is, for example, disclosed in JP-A 08-313195, its title being "hunting rifle having hard film on internal surface of muzzle of its barrel".
The choke tube has a different ballistic pattern depending on the inner shape thereof. Therefore, a plurality of choke tubes having a variety of inner shapes are prepared to achieve different design ballistic patterns such that the user can select a desired design ballistic pattern.
Even if the choke tubes have different design ballistic patterns, however, they are designed to exhibit the same appearance as commodities in general. In this case, the design ballistic patterns are identified by character information, such as trade names and model numbers, described on outer surfaces. Accordingly, it is difficult for the user to simply identify the design ballistic patterns that are respectively set for the choke tubes.
This may lead to the following consideration. Namely, different colors are prepared for respective inner shapes of the choke tubes having different design ballistic patterns. The colors corresponding to the design ballistic patterns associated with the inner shapes of the choke tubes may be printed on the outer surfaces of the tube bodies. In such the case, application of colors in a post-process elevates work costs. In addition, a printing process, capable of achieving stable fixture against heat during shooting, causes an increased price as a problem.
The inventor has paid attention to colors of wear resistant coatings applied to the choke tubes, which differ depending on materials of the wear resistant coatings. In consideration of the above situation, the present invention has a subject matter to color-code outer surfaces of choke tubes based on design ballistic patterns set for the choke tubes, not depending on coloring in a post-process. In addition, the present invention has an object to identify the design ballistic patterns simply by the colors applied to the choke tubes.


A papermaking refiner has two stationary disks mounted to the support structure of a fixed housing. A rotating disk is mounted on a shaft which extends through the housing. The support structure allows stock to circulate on both sides of the disk support structure, thus balancing fluid pressures on both sides of the fixed disk and preventing thermal gradients for reduced deflection of the disks. The incoming stock is centrifugally accelerated in a shroud which separates and traps tramp metal or the like before the stock passes to the refiner disks. The shroud has passageways which allow the rotating fluid to enter a reservoir which surrounds the drive shaft and feeds the gaps between the rotor and the stationary plates.

The present invention relates in general to refiners for treating paper pulp fibers to condition the fibers prior to delivery to a papermaking machine and to refiners for handling stock having a consistency of about 3 to about 6 percent fiber by weight.
Disc refiners are used in the papermaking industry to prepare paper pulp fibers for the forming of paper on a papermaking machine.
Paper stock containing three to six percent dry weight fibers is fed between closely opposed rotating discs within the refiner. The refiner discs perform an abrading operation on the paper fibers as they transit radially between the opposed moving and non-moving refiner discs. The purpose of a disc refiner is to abrade the individual wood pulp fibers.
Processing of fibers in a low consistency refiner may be performed on both chemically and mechanically refined pulps and in particular may be used sequentially with a high consistency refiner to further process the fibers after they have been separated in the high consistency disk refiner.
In operation, a low consistency disc refiner is generally considered to exert a type of abrasive action upon individual fibers in the pulp mass so that the outermost layers of the individual cigar-shaped fibers are frayed. This fraying of the fibers, which is considered to increase the freeness of the fibers, facilitates the bonding of the fibers when they are made into paper.
Paper fibers are relatively slender, tube-like structural components made up of a number of concentric layers. Each of these layers (called "lamellae") consists of finer structural components (called "fibrils") which are helically wound and bound to one another to form the cylindrical lamellae. The lamellae are in turn bound to each other, thus forming a composite which, in accordance with the laws of mechanics, has distinct bending and torsional rigidity characteristics. A relatively hard outer sheath (called the "primary wall") encases the lamellae. The primary wall is often partially removed during the pulping process. Raw fibers are relatively stiff and have relatively low surface area when the primary wall is intact, and thus raw fibers exhibit poor bond formation, with the result that paper which is made of raw fibers has limited strength
It is generally accepted that it is the purpose of a pulp stock refiner, which is essentially a milling device, to partially remove the primary wall and break the bonds between the fibrils of the outer layers to yield a frayed surface, thereby increasing the surface area of the fiber multi-fold.
Disc refiners typically consist of a pattern of raised bars interspaced with grooves. Paper fibers contained in a water stock are caused to flow between opposed refiner discs or plates which are rotating with respect to each other. As the stock flows radially outwardly across the refiner plates, the fibers are forced to flow over the bars. The milling action is thought to take place between the closely spaced bars on opposed discs.
Disk refiners have proven to be cost effective devices with high throughput which can readily operate over a range of stock flows. Nevertheless, improvements in disk wear life and other means of reducing maintenance remain desirable.


A replacing-type upper cover plate structure of notebook computer is disclosed. It includes a cover plate having an embedded element, and a containing frame having a groove bonding with the embedded element. The replacing-type upper cover plate structure, through a preferred module bonding mode, makes the upper and the lower shell tight-fit to bond for achieving the efficacy of protecting the interior and exterior elements of the cover plate. In the meantime, since the replacing mode of the cover plate is simple, convenient, and fast, thereby, the invention can improve the users' working efficiency to meet the humanized requirement.

1. Field of the Invention
The invention relates to a replacing-type upper cover plate structure of notebook computer, and more particularly, to a humanized design of replacing-type cover plate structure of notebook computer making use of a preferred bonding mode of the cover plate to make the module completely tight-fit to bond while easy to assemble and disassemble, and can change its appearance to meet the users' requirement.
2. Description of the Prior Art
Following the change with each passing day and month in the progress of the information science and technology, the relation between the contemporary men and the computer is getting closer than ever. Therefore, the function and conveniency of the computer, especially the notebook computer, is important accordingly. Particularly, since one always carries the notebook computer hustle and bustle on an errand bound while going to work, taking bus, having business trip, or presenting a brief etc, at this moment, the notebook computer has to provide the conveniency to carry it along, and in the meantime, to meet the humanized requirement for fast assembling and disassembling.
FIG. 1 is a schematic diagram of the fastening mode of hooking of the prior art. As shown in FIG. 1, the notebook computer comprises an upper cover plate 11 and a body 12. The upper cover plate 11 is used to apply to a notebook computer for fixing its liquid crystal display (LCD). Wherein the upper cover plate has a first connecting rod 13 and a second connecting rod 14 connected with the first connecting rod 13. The second connecting rod 14 contains a square hole 15. In addition, the body 12 contains a fillister 16 and there is bump 17 inside the fillister 16. The bump 17 is fastened to the square hole 15 of the second connecting rod 14 in order to hook the upper cover plate 11 and the body 12. The whole set of cover-body module, by the use of this mode, can be tightly bonded. On the other hand, when the first connecting rod 13 is pushed by an outside force, the second connecting rod 14 will be pushed together. Then, the upper cover plate 11 will unhook the body 12 and the notebook computer can be opened.
The assembly and disassembly of the connecting rods are difficult because they relate to the actions of taking out and hooking up of the rods, which causes the process becomes more complicated and inconvenient for users. Moreover, the fact that the edges of the cover plate structure of the prior art are not quite tightly bonded is apt to cause the intrusion of the contaminated articles.

Replacing-type upper cover plate structure of notebook computer