A flow measurement cartridge assembly for measuring liquid flow in a partially filled channel and a method for measuring liquid flow using the cartridge assembly, the cartridge assembly comprising: a frame for insertion into a discharge opening of the channel; a level detector secured in the frame for determining a liquid level in the channel; and at least one flow measurement device secured in the frame.

The systems heretofore used in the art for measuring the flow of water or waste water in a partially filled pipe or other channel have typically relied upon combinations of pressure cells and velocity sensors which are individually installed within the channel. In order to determine the depth of the flow in the partially filled channel, the pressure cell is mounted on the bottom of the channel to measure the amount of hydrostatic pressure head produced by the flowing fluid. Once the depth of fluid flow is known, the cross-sectional area of the flowing stream can be determined based upon the known cross-sectional shape and dimensions of the channel. The rate of fluid flow is then calculated by multiplying the cross-sectional area of the fluid flow by the flow velocity.
Unfortunately, the pressure cell systems heretofore used in the art have significant shortcomings. The accuracy of the pressure cell system depends upon the pressure cell being mounted precisely on the bottom of the channel and upon the pressure cell and the velocity sensor(s) being in precise vertical and horizontal alignment. Precisely mounting and aligning the pressure cell system components in the field is difficult and time consuming. In addition, considerable time and effort is required when using the prior art pressure cell systems for field calibration, validation, programming, and channel profiling. Moreover, the pressure cells used in these systems are highly susceptible to fouling and sediment build-up which affects the accuracy of the sensor and eventually renders the sensor inoperable. Consequently, the pressure cell must be frequently removed and cleaned.
One type of velocity sensor preferred for use in partially filled channels is a chordal, transit-time sensor comprising a pair of piezoelectric elements which are mounted on opposite sides of the channel. The elements must be beneath the fluid flow for operation and are typically mounted at a height of at least one-quarter, more preferably about one-third, of the vertical inside diameter of the channel. Transit-time velocity sensors are effective for determining the chordal velocity of the fluid across the entire path of the fluid flow. In addition, the sensor elements are highly resistant to fouling and are not susceptible to drift problems, variable water surface problems, or non-uniform particle distribution problems which are frequently encountered with other systems. The transit-time velocity sensor elements are also designed to prevent accumulation of rags, branches, and other debris.
Unfortunately, as indicated above, it has heretofore been difficult and time consuming to mount and precisely align the velocity sensor elements with each other and with the pressure cell for proper operation and accuracy.
As an alternative to the use of transit-time velocity sensors, trapezoidal flume structures have sometimes been used for measuring fluid flow in partially filled channels. Based upon the depth of flow through the trapezoidal flume, the rate of fluid flow can readily be determined using known flume equations recognized by the U.S. Bureau of Reclamation. Trapezoidal flumes are generally effective over a broad range and have a flat bottom design which is generally effective for preventing the accumulation of sediment or debris.
Although trapezoidal flume structures are resistant to fouling and sediment accumulation, the proper installation and alignment of these systems in the field is difficult and time consuming and typically requires that the operation of the water or waste water system in question be disrupted for a considerable period of time.
It is also known in the art that an ultrasonic transducer installed in the top of a partially filled pipe or other channel can be used to determine and monitor the fluid level in the channel by transmitting an ultrasonic signal directly downward onto the fluid surface. However, in addition to being difficult to properly install and align, the ultrasonic sensor systems heretofore known in the art have not been capable of operation, or have only been capable of limited operation, in many channel systems. Ultrasonic sensors typically require a minimum signal transmission distance of about 12 inches or more. Thus, in order to operate an ultrasonic level sensor in a partially filled channel, it has heretofore been necessary for the liquid level in the partially filled channel to remain at least one foot below the ultrasonic transducer. These systems therefore have generally not been acceptable for use, for example, in pipes having diameters of less than about 24 inches or in applications where the liquid level will sometimes rise to within at least one foot of the top of the channel.
Thus, a need currently exists for a flow measurement system for partially filled channels which is accurate over a broad range of flows and is not susceptible to fouling or sediment buildup. A need particularly exists for a system of this type which can be quickly and easily installed in existing or new channel systems while ensuring that all of the system components are properly and precisely oriented and aligned. There is also a need for a system for measuring flows in partially filled channels which can be installed and activated substantially without the need for field calibration, flow profiling, and field programming and which does not require a significant amount of field validation.


A yacht (10) includes a mast (12) that is mechanically connected to a keel (14) via a bearing (16), located in the base of hull (18) of the yacht (10). A sail foil (30) is pivotally mounted to the top of the mast (12) via a rotating bearing (34). In use, as the wind forces the sail foil (30) and mast (12) to leeward, a corresponding movement to windward is induced in the keel (14) and thus the yacht's hull (18) can remain substantially horizontal with respect to surrounding flat water.

Conventional monohull yachts use a fixed keel and a separate mast and sail plan supported by a number of stays. As the mast is basically fixed in a generally vertical orientation, when a conventional yacht is sailed into the wind, the boat tends to tilt (or heel) to angles of around 15.degree. from the horizontal (ie. due to the action of the wind on the sails of the yacht).
It is known that yachts sail fastest when the hull is maintained approximately in a horizontal orientation, and various attempts have been made in the art to reduce the tilting (or "heeling") of yachts. For example, sail shapes have been changed to quickly release wind from the sail to minimise heeling. Current yacht designs attempt to change the shape of the main sail by displacing the mast towards the bottom of the boat whilst at the same time bending upwardly the bow and stern of the yacht. Considerable force is required to effect such alteration and a large amount of stress is induced in the sail craft to achieve such configurations.


A power converting device including a pulse width modulation circuit, a switch unit, a power output unit and a voltage start unit is provided. The pulse width modulation circuit increases a start voltage in a soft start mode and is operated under the start voltage to generate a pulse width modulation signal. The switch unit is for receiving an input voltage, and forming a charge path and a discharge path alternately according to the pulse width modulation signal. The power output unit converts the input voltage to a core voltage in accordance with the charge path and the discharge path. The voltage start unit is for detecting the start voltage, and for transmitting a control signal to interrupt the formation of the discharge path when the start voltage is smaller than the core voltage.

1. Field of the Invention
The present invention relates to a power converting device and particularly to a power converting device which uses a voltage start unit and a pulse width modulation circuit for performing operations.
2. Description of Related Art
In the design of a server system, application specific integrated circuits (ASICs) are commonly-used integrated chips. Integrated chips perform operations by using an input voltage and a core voltage in the server, and the server converts the input voltage into the core voltage through a power converting device. It is noted that, in order to conform to the logical design of the server, generally the sequence of providing the input voltage and the core voltage is specifically restricted, and the timing of providing the input voltage needs to be earlier than the core voltage.
In view of the above, FIG. 1 illustrates a partial circuit diagram of a conventional server. As shown in FIG. 1, a power converting device 110 switches a conductive state of a switch SW11 and a switch SW12 through a pulse width modulation circuit 111. As the switch SW11 and the switch SW12 are switched, a current flowing through an inductance L11 and a capacitor C11 is changed, so as to convert an input voltage VIN1 to a core voltage VCORE1. On the other hand, the input voltage VIN1 and the core voltage VCORE1 are supplied to and used by an application specific integrated circuit 120 of a conventional server 100. Herein, an inner transistor of the application specific integrated circuit 120 forms a circuit structure equivalent to diodes D11 and D12, and the circuit structure is electrically connected between two terminals of the power converting device 110.
However, the input voltage VIN1 received by an input terminal TM11 of the power converting device 110 may leak to an output terminal TM12 of the power converting device 110 through the diodes D11 and D12. Consequently, when the power converting device 110 is in a soft start mode, the input voltage VIN1 is discharged through the inductance L11 and the switch SW12, as the switches SW11 and SW12 are switched. In the meantime, the levels of the input voltage VIN1 and the core voltage VCORE1 are pulled down simultaneously, which results in the malfunction of the power converting device 110.

Soft start unit for a power converting device


A driving assistance device: acquires presentation target information; controls a presentation of the presentation target information; calculates a recognition requisite time which is required for a driver to recognize the presentation target information when the presentation target information is presented; calculates a degree of risk which endangers a safety of the driver; calculates a given driving time according to the degree of risk which endangers the safety of the driver; and calculates a safe driving requisite time, which is a time required for the driver to drive safely, according to the degree of risk which endangers the safety of the driver. In a non-presented state of the presentation target information, when the given driving time becomes longer than a sum of the safe driving requisite time and the recognition requisite time, the driving assistance device presents the presentation target information.

It is crucial for safety that a driver's line of sight is directed to a road in a vehicle moving direction while driving. However, even when the driver is driving, the driver may be tempted to browse information (for example, news information or radio channel information) which is not directly related to a driving operation to be taken. In view of such concerns, it is normal to determine whether a vehicle is moving or not moving, and information is presented without any limitation when the vehicle is not moving whereas information is presented with limitation when the vehicle is moving. According to a configuration proposed to present information with limitation (see, for example, Patent Literatures 1 and 2), the limitation is relaxed or an information presentation method is changed by determining a level of psychological readiness of the driver when making an operation other than a driving operation.

Driving assistance device and driving assistance program product


There is provided a method of testing a first device using a tester. The method includes receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further include generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data.

1. Field of the Invention
The present invention relates generally to communication devices. More particularly, the present invention relates to the testing of communication devices.
2. Background Art
Monitoring the quality of service (QoS) of a communication path has typically relied upon sporadic bit-error-rate (BER) testing. Today, communication devices go through BER testing prior to incorporation into communication networks to ensure an acceptable QoS. BER testing plays a vital role in successful development and manufacturing of communication devices. BER testing verifies compatibility with network requirements and can provide priceless diagnostic information during the critical integration testing.
BER testing is commonplace in data communication systems, and in such systems, Pseudo Random Bit Sequence (PRBS) is traditionally transmitted through the device under test (DUT) and looped back, and an error detector at the tester counts any unexpected bit as an error. Such loop-back testing is important in characterizing a DUT by a tester, screening the DUT for IEEE compliance, looking for receiver side BER on the DUT. PRBS is usually generated by applying a polynomial to a binary sequence, e.g. applying a number of XOR (exclusive OR) operations to a binary shift register, and a PRBS generator may be able to generate a PRBS with maximum pattern length of 2n−1, where n=7, 9, 11, 15, 20, 23, 31, and having N Mbits of programmable or user-defined pattern. PRBS testing is a standard and accepted method of testing due to the DC balanced and transition density of the sequence. By varying the PRBS polynomial, one can further stress the DUT.
FIG. 1 illustrates conventional testing system 100 utilizing tester device or system 110 for testing DUT 150. The approach of FIG. 1 may typically be referred to as parallel loop-back for looping back the recovered data to the transmitter through the use of FIFOs. As shown in FIG. 1, tester device 110 includes pattern generator 130, which generates a pre-defined pattern or Tx Data 132, such as a PRBS pattern. Tester device 110 also includes a transmitter or TX1 131, which transmits Tx Data 132 over a communication line, such as a wired line, wireless line or optic line, according to a local clock or C1 127, which is generated by a clock generator or (phase locked loop) PLL1 125 based on a crystal frequency or X1 120.
At the other end, the communication line is connected to DUT 150, such that DUT 150 receiver or RX2 174 receives Tx Data 132 based on a recovered C1 127 clock as Rx Data 172, and DUT 150 is configured in loop-back test mode to send Rx Data 172 to DUT 150 transmitter or TX2 171 for transmission to tester device 110, over the communication line, using the recovered C1 127 by DUT 150. Although DUT 150 includes a clock generator or (phase locked loop) PLL2 165 for generation of a local clock or C2 167 based on a crystal frequency or X2 160, C2 167 is not used by conventional testing system 100, because there is a difference in crystal frequencies X1 120 and X2 160.
Continuing with FIG. 1, tester device 110 receiver or RX1 134 receives transmitted Rx Data 172 by TX2 171, which is transmitted by DUT 150 using the recovered C1 127, shown as C1′ 173 to indicate a frequency offset between C1 127 and the recovered clock at RX2 174. Next, RX1 134 provides the received data to error detector 140, which compares the received data with Tx Data 132, provided by pattern generator 130, to detect errors and generates BER 145. However, at least one problem with the approach of conventional testing system 100 is that the recovered clock or C1′ 173 has a frequency offset with respect to C1 127, and this frequency offset causes additional non-existent bit errors due to at least the finite size of the FIFOs.
Another conventional approach is shown in FIG. 2, which illustrates conventional testing system 200 utilizing tester device 210 for testing DUT 250. The conventional approach of FIG. 2 attempts to cure the problems in the conventional approach of FIG. 1 by using a second PLL or PLL 280 at DUT 250, as explained below. As shown in FIG. 2, tester device 210 includes pattern generator 230, which generates a pre-defined pattern or Tx Data 232, such as a PRBS pattern. Tester device 210 also includes a transmitter or TX1 231, which transmits Tx Data 232 over a communication line, such as a wired line, wireless line or optic line, according to a local clock or C1 227, which is generated by PLL1 225 based on a crystal frequency or X1 220.
At the other end, the communication line is connected to DUT 250, such that DUT 250 receiver or RX2 274 receives Tx Data 232 based on a recovered C1 227 clock as Rx Data 272, and DUT 250 is configured in loop-back test mode to send Rx Data 272 to DUT 250 transmitter or TX2 271 for transmission to tester device 210, over the communication line, using C1 127 that is generated by additional PLL 280 based on the recovered clock or C1′ 273. Although DUT includes PLL2 265 for generation of a local clock or C2 267 based on a crystal frequency or X2 260, C2 267 is not used by conventional testing system 200, because there is a difference in crystal frequencies X1 220 and X2 260. However, a clock generator or (phase locked loop) PLL3 280 is added to DUT 250 for the purpose of adjusting C1′ 273 using X2 260 to generate C1 227 at DUT 250, and TX2 271 transmits RX Data 272 based on C1 227 generated at DUT 250.
Tester device 210 receiver or RX1 224 receives transmitted Rx Data 272 by TX2 271, which is transmitted by DUT 250 using C1 127 generated at DUT 250. RX1 234 provides the received data to error detector 240, which compares the received data with Tx Data 232 provided by pattern generator 230 to detect errors, and generates BER 245.
Conventional testing system 200 of FIG. 2, however, suffers from a number of drawbacks. For example, PLL3 280 increases the area of the chip in addition to increasing the power consumption, and may also cause a coupling problem with PLL 265.
Accordingly, there is a need in the art to overcome the foregoing shortcomings in the conventional approaches and introduce a reliable and efficient approach to loop-back testing in communication devices.

Method and system for testing devices using loop-back pseudo random data


A method of removing harmful gas is performed by a manner that a mixture of photocatalyzer and active carbon with air containing harmful gas and the mixture of photocatalyzer and active carbon are mixed in a chamber so as to drift the mixture in the air, the drifting mixture reacting with the harmful gas in illumination by lighting means, and the mixture catching said harmful gas so as to remove said harmful gas.

The present invention relates to a method for removing harmful constituents from a gas, and respectively to a method for removing NOx and SOx of low density from air.
Regarding the harmful gas removal apparatus, various oxidation or reduction catalyzers to treat discharged gas from motor vehicles, power plants or the like have been developed. Those harmful gas removal apparatus are constructed to be operable for high density harmful gases of several hundreds ppm and at high temperatures of several hundreds to 1000.degree. C. In design, the removal of low density harmful gases of several ppm from the air is not taken into consideration.
A method of removing trace amounts of harmful gas from air has been developed (e.g., Published Unexamined Japanese Patent Application No. Hei. 1-218622). Also a ventilation system for car road tunnels using harmful gas removal method has been developed (e.g., Published Unexamined Japanese Patent Application No. Hei. 3-233100).
The harmful gas removal method is based on the fact that when a mixture of titanium dioxide (TiO.sub.2) and active carbon or a mixture of the former and iron series metal oxide (Fe.sub.2 O.sub.3, NiO, ZnO, etc.) is illuminated with light, NOx and SOx of low density can efficiently be removed at room temperature. This method is able to remove low density harmful gases of several ppm or less in the air without any additional process, for example, a heating process, at low cost.
In this method, it could be considered that titanium dioxide or iron series metal oxide as the photocatalyzer is activated by light applied thereto. The activated photocatalyzer cooperates with the active carbon to convert the harmful gas to another material, for example, NOx to nitric acid ions (NO.sub.3.sup.-) and SOx to SO.sub.4.sup.2-, and catches the converted material. The mixture of the photocatalyzer and active carbon (referred to simply as photocatalyzer herein after) is gradually deteriorated in its activity since reactive product is deposited thereon. However, after the reactive product is washed away from the photocatalyzer by water, and the photocatalyzer is dried, the photocatalyzer can be used again.
In these harmful gas removal methods the photocatalyzer, as shaped grains, is fixed on the adhesive-coated surface of a fixed member, and thus, the photocatalyzer is brought into contact with harmful gas in a fixed state.
An apparatus for realizing the harmful gas removal method as just mentioned is illustrated in FIG. 5. As shown, a photocatalyzer layer 2 is layered on one side of the inner wall of an upright reactive chamber 1. Light sources 3 for illuminating the photocatalyzer layer 2 are provided on the other side of the inner wall. A series of nozzles 4 and a heater 5 for drying the photocatalyzer layer 2 are disposed along the photocatalyzer layer 2 within the reactive chamber 1. A washing water tank 7 is placed under the reactive chamber 1, with a valve 6 interconnecting them.
The gas subjected to the treatment is fed into the reactive chamber 1 through an inlet 8 formed at the top of the chamber. Within the chamber, the gas comes in contact with the photocatalyzer layer 2 by which the harmful gas is removed from the gaseous body. The gas thus cleaned is discharged from an outlet 9 formed in the lower portion of the chamber. When reactive product is deposited on the photocatalyzer layer 2 and the activity of the layer deteriorates to a certain degree, the feeding of the gas is stopped. The photocatalyzer layer 2 is washed by water spouted out of the nozzles 4, and then dried by the heater 5. The water dropping from the photocatalyzer layer is collected in the tank 7 through the opened valve 6. The thus collected water, if necessary, is processed for harmful contents removal and discharged as waste water.
The harmful gas removal apparatus thus constructed has the following problems.
(1) The regaining process of restoring the deteriorated photocatalyzer layer by the washing and drying operations must be performed within the reactive chamber since the photocatalyzer layer is fixed in the chamber. When the washing device (nozzles 4 in the above example) and the drying device (heater 5) are installed within the reactive chamber, these devices must be laid out so as not to interrupt the air flow and the passage of light from the light sources 3. Thus, proper arrangement of these devise results in complexity of the apparatus. PA0 (2) The fixed side of the photocatalyzer layer in contact with the inner wall of the chamber is not subjected to reaction with the harmful gas. And it is very difficult to uniformly illuminate the wall of the chamber on which the photocatalyzer layer is fastened with light from the light sources. Accordingly, the reaction process is inefficient. PA0 (3) To increase the contact area of the photocatalyzer, the surface area of the fixed member must be increased. The result is apt to increase the size of the harmful gas removal apparatus. It is difficult to increase the contact area of the photocatalyzer while reducing the apparatus size. PA0 (4) The reaction process must be stopped during the photocatalyzer regaining process. PA0 (5) Removal of the deteriorated photocatalyzer and placement of fresh photocatalyzer are not easy.


The present invention is directed to an oxindole derivative represented by formula (1): ##STR1## (wherein R represents a methyl group or a methoxy group), and pharmaceuticals containing the compound. The compound exhibits excellent granulation inhibiting activity while providing minimal liver toxicity and is useful as a pharmaceutical in the prevention and treatment of articular rheumatism, arteriosclerosis, hepatocirrhosis, etc., and also in the prevention and treatment of arthrosis deformans, psoriasis, gout, nephritis, angiitis, inflammatory intestinal diseases (ulcerative colitis, Crohn's disease), bronchitis, and chronic granulomatosis, etc.

Fibrosis of cells that brings about functional disorders of various organs and tissue is a great clinical problem in the alleviation of inflammation and the curing of wounds in organs or tissue. In joints, fibrosis of cells causes articular rheumatism, and in the liver, progress of cellular fibrosis leads to hepatic cirrhosis, causing jaundice and hypoproteinemia and eventually leading to liver failure. In blood vessels, fibrosis of vascular walls causes loss of elasticity of the walls, leading to arteriosclerosis. The first step of fibrosis is granulation, and therefore, it is considered that articular rheumatism,-hepatic cirrhosis, arteriosclerosis, etc. would be successfully treated if granulation could be inhibited.
In the development of pharmaceuticals, compounds having liver toxicity are problematic for successful development. In Nature No. 283, 397-398 (1980), it is reported that increased production of peroxisome, which causes hepatomegaly, is a carcinogenetic factor.
Therefore, there is strong demand for pharmaceuticals which exhibit excellent granulation inhibiting activity with minimal liver toxicity and which are thus advantageously used in clinical situations.
Analogs of a 3-(bis-substituted phenylmethylene)-oxindole derivative, which is the compound of the present invention, are disclosed in Ber., 96 (1963), 3328-37, Japanese Patent Publication (kokoku) No. 43-3195, and in U.S. Pat. No. 3,428,649. Of the analogs, 3-[bisphenylmethylene]-oxindole (compound a) of the following formula, disclosed in Ber., 96 (1963), 3328-37 is particularly close to the compounds of the present invention. However, that compound is merely disclosed as a synthesis intermediate, and no pharmacological activity is described at all. ##STR2##
Japanese Patent Publication (kokoku) No. 43-3195 discloses, as a synthesis intermediate, an oxindole derivative represented by the following formula (2): ##STR3## (wherein each of R.sup.1 and R.sup.2 represents lower alkyl, aryl, or pyridyl; and R.sup.3 represents a hydrogen atom or lower alkyl).
However, the disclosure of 3-(bis-substituted phenylmethylene)oxindole derivative in that publication is in fact directed only to specific compounds in which R.sup.3 is a methyl group and R.sup.1 and R.sup.2 are both unsubstituted phenyl groups, and to use as synthesis intermediates.
Accordingly, the object of the present invention is to provide a novel oxindole derivative which exhibits excellent granulation inhibiting activity while providing minimal liver toxicity and which is thus advantageously used as a pharmaceutical.

3-(bis-substituted phenylmethylene) oxindole derivatives


A video projector (1) comprises a projection lens (18) which projects an image on a screen (S), a zoom ring (19) which varies a magnification ratio of the projection lens (18), a drive wheel (32) which is partially protruded from a bottom face of a housing (2), and a plurality of gears (310, 311, 312) that constitutes a power transmission mechanism (31) between the drive wheel (32) and the zoom ring (19). When the video projector (1) is moved in an anteroposterior direction to the screen with rotating the drive wheel (32), the zoom ring (19) is turned in conjunction with the rotation of the drive wheel (32) through the power transmission mechanism (31). Since the magnification ratio of the projection lens (18) is varied with the turning of the zoom ring (19), the size of the image projected on the screen is varied without a direct operation of the zoom ring (19) by a user.

1. Field of the Invention
The present invention relates to a video projector which projects images on an external screen.
2. Description of the Related Art
Conventionally, a video projector, which projects images on an external screen on the basis of image signals outputted from a personal computer, for example, has a function to vary a magnification ratio to enlarge images depending on a size of a screen or a distance from the video projector to the screen. As for a relatively inexpensive video projector, for example, a user can change the magnification ratio to enlarge images by turning a zoom ring located around a projection lens which projects images.
In the relatively inexpensive video projector described above, the user should operate the zoom ring around the projection lens to vary the size of the images projected on the screen even when the video projector is in use. In operating the zoom ring, the user often blocks the image projected on the screen in front of the projection lens unintentionally, and thus, it is so inconvenient as to make the other user who watches the image feel discomfort. Such a problem can be solved by using a video projector in which an image zooming can remotely be operated, for example. It, however, is too expensive to apply such a configuration to the inexpensive video projector with simple configuration.
A conventional video projector described in, for example, Japanese Laid-Open Patent Publication No. 2005-333460 comprises movable wheels which are driven by a motor so as to adjust a location of a projected image by controlling and changing a location and an attitude of a projector body. However, the conventional video projector described in 2005-333460 has a complex configuration to drive the movable wheels, and thereby, it causes expensiveness. Thus, such a configuration of movable wheels cannot be applied to the relatively inexpensive video projector, and the above problem cannot be solved.
Another conventional video projector described in, for example, Japanese Laid-Open Patent Publication No. 2004-29356 is configured to vary a size of an image projected on a screen by moving a projector body forward and backward. However, during use of the video projector, an installation location can often be changed little, and in such a situation, the image cannot be adjusted to be an intended size without varying a magnification ratio of the projection lens. Moreover, depending on a purpose of use of the video projector, the size of the image projected on the screen is not often wished to be changed when the installation location of the video projector is changed. In this case, as for the conventional video projector described in 2004-29356, the user should operate the zoom ring, so that the above problem is not still be solved.

Video projector having a power transmission mechanism between a drive wheel and a zoom ring


A computerized method and system for solving non-linear Boolean equations is disclosed comprising at least partially solving a Boolean function; developing at least one inference regarding said Boolean function and saving said inference to a state machine; and accessing said inference from said state machine to develop at least one heuristic for determining whether said Boolean function is satisfiable.

In math and physics, "linear" means "simple" and "non-linear" means "complicated". The theory for solving linear equations is very well developed because it is simple enough to solve and only one solution exists. Non-linear equations can in general not be solved exactly (they have multiple solutions) and are the subject of much on-going research. Here is a brief description of how to distinguish a linear equation from a non-linear equation: In a linear equation, the variables (and their derivatives) must always appear as a simple first power. Here are some simple examples to illustrate this principle:
x+5=10 is linear and the equation is satisfied if and only if x takes the value 5. On the other hand, 5+x232 6 is non-linear because x2 is not a first power. The solution to this equation entails two values for x, namely −1 and +1 and this solution is harder to find than in the previous case.
In Boolean logic, equations have an analogous meaning but the operations of or (denoted ) and and (denoted ) replace the operations of plus (denoted +) and times (denoted ×), the connective ≡replaces the connective =, and Boolean variables can only take two values, namely true (also referred to as value 1) and false (also referred to as value 0), instead of any number as in the case of mathematics and physics. Analogously, non-linear Boolean equations are far harder to solve than linear Boolean equations and often, if there is one solution, there are many solutions.
There are two current competing methods for solving systems of non-linear Boolean equations. The first is via the use of Binary Decision Diagrams (BDDs). The second, is via Conjunctive Normal Form (CNF) Satisfiability checkers, e.g., POSIT, GRASP, zCHAFF, SATO, WALKSAT, etc. A BDD is intended as a compact representation of a Boolean function. A Boolean function has several input variables and one output variable. Every input variable may either be independently assigned value 0 or 1 or may be left unassigned. The output takes either value 0 or 1 or has undetermined value depending on the values assigned to the input variables. The input assignment patterns causing the output to have value 0 or 1 or undetermined may be listed in a table called a truth table. A truth table corresponds uniquely to a particular Boolean function.
A BDD is a mathematical abstraction which describes a truth table in an alternative and compact form. A BDD consists of a number of nodes, one distinguished as the root, one as the 0 node and one as the 1 node, representing function variable values, and arcs leading away from nodes, except the 0 and 1 nodes, representing values given to input variables. In this formalism 0 represents false and 1 represents true. The 0 and 1 nodes together represent the 0 and 1 values, respectively, which the function may take. A path from root to the 1 node signifies an assignment of values to input variables which causes the function's output variable to have value true and a path to the 0 node signifies an assignment causing an output value of false. Principal attributes of BDDs leading to their wide use are: 1) a BDD can be a compact, efficiently computed representation for a Boolean function and 2) operations for combining BDDs, such as conjunction (the  operator), can be fairly efficient provided the number nodes in the resulting BDD is not great.
BDDs are typically applied to non-linear equations as follows. A non-linear equation is a Boolean function. Variables named in a non-linear equation are its input variables. Thus, each equation may be represented by a BDD. Solving a system of non-linear equations means finding an assignment of values to all variables named in the system which causes each equation to have value 1. An equation, which has value 1, due to an assignment, is satisfied by that assignment. Since a system of non-linear equations is a Boolean function, a system may be solved if its corresponding BDD can be computed. Starting from the easily computed BDDs for each equation and using the rich set of operations available to BDDs, a BDD solver combines BDDs until one is left: that which represents the entire system. If that point can be reached, the system is solved. Observe that purely BDD techniques involve no guessing and checking of assignments.
By contrast, Satisfiability checkers, or SAT solvers, solve a restricted class of non-linear Boolean equations referred to as CNF formulas (see below for a description) by guessing, checking, discarding, and guessing again input variable values until either all possible combinations are exhausted or until an assignment is found which satisfies all equations. A SAT solver starts with all variables unassigned and attempts to extend the set of currently assigned input variables, one at a time, until it can be determined that all equations are satisfied or that all possible assignments to remaining unassigned variables will not satisfy all equations. In the former case a satisfying solution to the system is found. In the latter case one or more of the last variables to be assigned are reassigned or unassigned and the search for satisfying extensions is continued. If all possible extensions from the starting case, where all variables are unassigned, fail to satisfy all equations then the SAT solver reports no satisfying solution is possible.
BDD solvers are limited in the size of problems that they can solve, e.g., hundreds of variables and thousands of equations, depending on the problem domain. The principle problem plaguing BDD solvers is that as BDDs are being combined, they can get extremely large before completion, even if the final BDD is very small.
SAT solvers can solve problems with tens of thousands of variables and hundreds of thousands of equations, depending again on the problem domain. However, good performance seems to depend heavily on search heuristics, which choose the order in which variables are assigned values. Heuristics pertain to a trial-and-error method of problem solving used when an algorithmic approach is impractical. But the management of highly intelligent heuristics requires a great deal of overhead using conventional data structures and high overhead cancels the potential gains offered by such heuristics.
BDD and SAT solvers have (separately) been applied to a variety of problems. Many of these are a subclass of a general class of expressions called Layered Boolean Formulas (LBF).
A formula is one of the LBF class of expressions if it is given as 1) a list F={f1, f2, . . . , fm} of m Boolean functions whose inputs are taken from a set V={v1, v2, . . . , vn} of n Boolean variables; and 2) a list O=<o1, o2, . . . , om> of m Boolean values, one for each function, which specify the values the functions' outputs need to have if the expression is considered satisfied. The problem that needs to be solved, given an LBF Ø, is to determine whether there exists a list of Boolean values <b1, b2, . . . , bn> which the variables of V can be set to (that is, variable vi takes value bi for all 1≦i≦n) to satisfy the expression Ø (that is, makes all function outputs of F consistent with O) and if such a list exists (called a solution) output one.
The LBF class of expressions includes Conjunctive Normal Form (CNF) formulas, some Quantified Boolean Formulas (QBF), and Trace formulas. In a CNF formula each Boolean function fi is a conjunction of Boolean variables and complemented Boolean variables (a complemented Boolean variable just has a value opposite that of its variable counterpart) and each oi is 1. For example, f1 might be expressed as v1v3v8 which is a conjunction of two variables and one complemented variable (v3) and has value 0 if v1 and v8 have value 0 and v3 has value 1; has value 1 if v1 or v8 have value 1 or v3 has value 0; and has undetermined value otherwise. Boolean functions in a Trace formula typically use the equivalence operator ≡ and a few other operators such as ite which means if-then-else. For example, f1 of a Trace formula might be expressed asv≡ite(v1, v2, v3);This function has value 0 if either
1) v1 and v3 have value 0 and v has value 1; or
2) v1 and v have value 0 and v3 has value 1; or
3) v1 and v2 have value 1 and v has value 0; or
4) v1 and v have value 1 and v2 has value 0.
It has value 1 if either
1) v1 and v3 have value 0 and v has value 0; or
2) v1 has value 0 and v3 and v have value 1; or
3) v1 and v2 have value 1 and v has value 1; or
4) v1 has value 1 and v2 and v have value 0.
It has undetermined value otherwise.
A QBF expression is more complicated. Instead of asking whether there exists a list of Boolean values that satisfy Ø, the problem is to ask whether, for every possible combination of values that some of the V variables can have, there exists some combination of values that the remaining V variables can have with the result that Ø is satisfied, and if so, what is one such combination of values.
Before the 1990s, Binary Decision Diagrams (or BDDs) were considered the best way to deal with LBFs arising from practical problems. Unfortunately, on real LBFs, the number of nodes of "intermediate" BDDs (those that are formed while combining BDDs) can get to be enormous before realizing the final BDD which solves the problem and which can be quite small.
An alternative is to convert the BDDs to a conjunction of clauses, that is expressions of the form s1 s2 s3, and solve the conjunction of all conjunctions of clauses using a SAT solver. Before the 1990s this was infeasible because SAT solvers performed a form of tree search, that is SAT solvers did not effectively remember and reuse what had been learned in early parts of the search process. This sharply contrasts with BDDs which reuse portions of paths leading to the 1 node and 0 node, respectively. But the 1990s saw major improvements in the design of SAT solvers including conflict resolution, a form of remembering learned facts which we call lemmas, lookahead for inferences, better search heuristics, and exploitation of problem symmetry to prune away large portions of the search space. With these improvements SAT solvers can now compete with and in some cases significantly exceed the performance of BDD tools.
Formulas such as these arise in a variety of formal verification problems including microprocessor verification, illegal transition checking, and interconnect synthesis, among others. Consider microprocessor verification first. A circuit for use in a computer or other electronic device is designed from a formal specification of its functionality. This specification is written in some human understandable form such as make a noise at noon on cloudy days only. But an implementation of this statement as a circuit must be in a machine understandable form involving input and output variables. For example, let time represent time-of-day, let weather represent a type of weather condition, let noise represent whether a noise is made. Then the circuit to build may be expressednoise≡(time=12:00)(weather=cloudy).
The output of this circuit has either logic value true or false depending on the values of its input variables, namely noise, time, and weather. For example, if input values are sunny for weather, 12:00 for time, and true for noise, then the circuit outputs false. Observe that a formal specification may also have a logic value of true or false depending on some conditions. For example, the specification above has value false if a noise is made on a sunny day. If a circuit is to function as expected, its output logic values must be consistent with the logic values of the associated specification for corresponding input variable/specification conditions, that is, the specification and the circuit design should be functionally equivalent.
The microprocessor verification problem is to prove, using a computer program, that a given formal specification is logically equivalent to a given circuit expression. This is accomplished by using a special language for writing specifications which can efficiently be transformed into a conjunction of logic expressions. To determine whether the conjunction of expressions, S, is functionally equivalent to a circuit design, D, the expressions representing D and S are combined as follows:(DS)(DS)
This equivalence expression always has value false if and only if D and S are functionally equivalent.
A SAT solver (computer program) checks all possible combinations of input values to see whether a given equivalence expression always has value false. But all SAT solvers operate on CNF formulas. Thus, equivalence expressions must be translated to CNF before being solved by a SAT solver. Translation has two undesirable side-effects: 1) the length of the equivalence expression in CNF may be much greater; 2) variables which are understood in the context of the equivalence expression may lose that property as they become scattered in the translation. Continuing with the above example, consider attempting to show thatnoise≡(time=12:00)(weather=cloudy)is equivalent tonoise≡ite(weather=cloudy, time=12:00, weather=cloudy)
The later expression may have come from the special formal specification language. Current solvers cannot directly deal with the equivalence expression. Rather, a straightforward translation of the equivalence expression to CNF might give(noise (time=12:00)(weather=cloudy))(noise (time=12:00)(weather=cloudy))(noise (time =12:00)(weather=cloudy))(noise (time=12:00)(weather=cloudy))(noise (time=12:00)(weather=cloudy))(noise (time=12:00)(weather=cloudy))(noise (time=12:00)(weather=cloudy))(noise (time=12:00)(weather=cloudy))
A SAT solver will take this expression as input and attempt to solve it by searching for a solution. Although this example omits some trivial simplifications that could result in a reduced translated expression (and that most SAT solvers perform), it illustrates that the approach used by SAT solvers when inputs are extremely large results in a complexity of the translated expression that is much greater than the original expression, variables tend to get scattered throughout the translated expression, and the relationship between variables becomes blurred.

Method and system for non-linear state based satisfiability

The United States of America as represented by the National Security Agency


A camper shell mounting rail is formed from two pieces, one of which retains one side of the lower terminus of the side-wall of the camper shell, and the other piece retains the other side. Fasteners such as rivets or screws enter the mounting rail from the bottom and secure the two pieces together, while, at the same time, clamping the sidewall of the camper shell between the two pieces.

This invention relates a mounting rail for mounting camper shells to the beds of vehicles. More specifically, the invention provides a convenient and aesthetically favorable mounting rail for attaching camper shells to the tops of sidewalls of pickup truck beds, using a limited amount of hardware, without violating the structural integrity of the camper shell wall, and having concealed fasteners.
Camper shells have long been utilized to convert the harsh environment which is often found in the back of pickup trucks and the like, to a relatively less harsh environment. The manner of attaching the camper shell to the bed of the truck or the like, has an important bearing on whether unwanted environmental factors are effectively eliminated from the interior chamber formed by the vehicle and the camper shell. Additionally, numerous stress forces caused by such factors as air movement, vibration, resonance, vehicular movement, etc., mandate an attachment which effectively secures the camper shell to the tops of the sidewalls of pickup trucks and the like. Highway safety further dictates that all camper shells on moving vehicles be securely fastened. The high cost of vehicles, which often serve as status symbols, creates a desire to secure the camper shell in an aesthetically pleasing manner. This may be accomplished by eliminating visible hardware and surplus lines and surfaces.
Multiple lines and surfaces also present a collection point for soil, wax, or other substances not desired to be accumulated on the exterior of a vehicle or camper shell. Multiple lines can cause snagging, deflection, or wear upon cleaning equipment such as cloths, buffing equipment or other provisions to clean or care for an automobile.
A number of systems are currently in use to secure camper shells to the tops of the beds of pickup trucks. One system utilizes a mounting rail with a horizontal member which may be fastened to the top of the sidewall of the pickup truck, and a vertical member which is screwed or otherwise fastened to one or more corresponding vertical members of the shell. This system has several disadvantages. First, the vertical member if the camper shell is weakened at the critical attachment area by the damage made by the screws protruding through it. This violation of the camper shell can create points at which stress fractures can form and eventually lead to the total failure of the attachment. Second, the head of the screw or other fastener is either exposed to the external environment, or must be covered with trim. Third, the protruding point and/or threads of the screw or other fastener are either exposed to the internal environment of the camper shell or must be covered by yet another component; usually an inverted "U" channel. The screw or fastener protrudes through one wall of the inverted "U" channel, and the remaining walls conceal the protruding fastener. Fourth, the external portion of the fasteners and/or their cover are exposed to tampering, vandalism, or an increased risk of damage.
Another system uses a construction involving a horizontal rail, an outside corner, and an inner tube. The inner tube is simultaneously fastened to the rail and the outside corner, with the rim of the shell clamped between the tube and the outside corner. This system utilizes three independent components which must be aligned and fastened simultaneously. This presents the hazard that one or more components will come out of alignment during the fastening process, thus creating an unsightly error and necessitating that one or more components be discarded as waste, and the process repeated.
For the foregoing reasons, there is a need in the prior art for a mounting rail for mounting camper shells to a the tops of sidewalls of pickup trucks and the like, which reduces the number of components, conceals fasteners, protects the structural integrity of the camper shell wall, and is simple and easy to install.


The invention relates to a boot (1) comprising a leg (2) in rubber combined with a textile lining (4), the lining (4) comprising a first textile layer (6) able to evacuate moisture (10) and a second textile layer (7) intended to be in contact with the foot (5) of a user, forming a layer to protect the foot against moisture. The first textile layer (6) is made by using a resilient fabric with a thickness greater than 3 mm, and the second textile layer (7) is bamboo viscose based.

A boot generally comprises a lining in order to increase the user's comfort. Considering the fact that the leg is made of an impermeable material, the user's foot sweats and sweat tends to accumulate in the boot.
Moisture thus generally accumulates in the textile lining, which is uncomfortable for the user.
In order to remedy this disadvantage, document U.S. Pat. No. 4,430,811 proposes a boot in which the lining comprises a first textile layer that is able to evacuate moisture and a second textile lining intended to be in contact with the user's foot, forming a layer to protect the foot against moisture.
As the first layer has a thin thickness, an intermediate layer of foam must be inserted between the textile lining and the rubber leg in order to increase the user's comfort, which increases the complexity of the boot.
In addition, because of its thin thickness, the first layer tends to be progressively crushed after long periods of use of the boot, such that the moisture evacuation function is no longer properly ensured.
Lastly, the material used to make the second layer does not sufficiently protect the foot against moisture.


A wood preservation composition comprising an unexpectedly efficacious combination of a boron compound and bifenthrin is disclosed. A method of preserving wood, as well as the preserved wood, are also disclosed.

Boron compounds have long been used in the wood preservation industry for the preservation of wood from termite attack. However, many boron compounds have a degree of solubility in water such that upon exposure of treated wood to environmental conditions, the compound can, under some conditions, leach from the wood, causing wood treated with boron compounds to demonstrate a preservation efficacy which is less than would be expected from the calculated retention immediately following treatment with the compound. For example, wood which has been exposed to damp environments is known to suffer from a reduced preservation efficacy, possibly due to leaching of the boron compound to the environment.

Borate compositions for wood preservation


The present subject matter provides a method of manufacturing an electrode for a fuel cell, in which nanocarbons are grown on the surface of a substrate for a fuel cell using a process of simultaneously gasifying a platinum precursor and a carbon precursor, and simultaneously core-shell-structured platinum-carbon composite catalyst particles are highly dispersed between nanocarbons The subject matter also provides an electrode for a fuel cell, manufactured by the method. This method is advantageous in that an electrode for a fuel cell having remarkably improved electrochemical performance and durability can be manufactured by a simple process.

1. Technical Field
The present subject matter relates to a method of manufacturing an electrode for a fuel cell and an electrode for a fuel cell manufactured by the method. More particularly, the present subject matter relates to a method of manufacturing an electrode for a fuel cell, in which nanoparticles of carbon or "nanocarbons" are grown on the surface of a substrate for a fuel cell using a co-gasification process of a platinum precursor and a carbon precursor, and simultaneously core-shell-structured platinum-carbon composite catalyst particles are highly dispersed between nanocarbons, thereby obtaining an electrode for a fuel cell having improved electroconductivity, activity and durability, and to an electrode for a fuel cell, manufactured by the method.
2. Description of the Related Art
Recently, with the exhaustion of crude oil and the increase of oil prices, the development of novel energy sources different from conventional energy sources has been required, and thus the necessity for developing fuel cells has been increased. However, although research into fuel cells has been conducted for several decades, the commercialization of fuel cells has proceeded slowly because the production cost of an electrode catalyst for a fuel cell was high and the durability of the electrode catalyst is very low. Therefore, research into improving the performance and durability of an electrode for a fuel cell has lately been attempted actively and variously. Generally, research results, such as high dispersion of a platinum catalyst, prevention of electrode corrosion and catalyst detachment by the reformation of a carbon support, improvement of durability by controlling the properties of carbon bonded with metal particles, and the like have been proposed. However, to date, remarkable research results have not been presented, and solutions for basically improving the performance and durability of a platinum catalyst also have not been presented.
Korean Patent Registration No. 10-823502 describes related art.

Method for manufacturing electrode for fuel cell comprising nanocarbon and core-shell-structured platinum-carbon composite and the electrode for fuel cell manufactured by the same


Methods and apparatus for simultaneously displaying multiple-contexts in a page-oriented viewing architecture utilize the concept of page pinning in which a portion of a first document context is displayed as a fixed frame overlayed on or placed beside the display of a second document context. A user may navigate within the second document context while viewing the portion of the first document context as a pinned page on the display. Thus, a single navigational focus is maintained even though multiple contexts are displayed in the page-oriented architecture. Page pinning may be used to view two non-contiguous locations in a single electronic document or to view two pages of respective different electronic documents. The invention contemplates the use of a pinned page to hold a particular context while a command set is executed from a command document viewed as the second context. The invention also contemplates the use of a pinned index page to provide a collection of links for permitting a user to navigate to different contexts, including pages within a main document or to other documents. Finally, the invention contemplates the user of a pinned page to provide the equivalent of an “always on top window” display.

With the proliferation of portable hand-held electronic devices, such as personal digital assistants (PDA's) and other personal electronic devices, there has been considerable effort invested in the simplification of a user's experience in viewing electronic content. Generally, a primary goal of such efforts has been to provide systems for presenting information to a user in a manner that is intuitively simple, yet which provides for efficient access to and navigation of electronic documents.
Known multiple-window architectures have limited appeal to those attempting to provide an intuitively simple system for presenting information to a user. While such architectures permit a user to display multiple contexts of electronic documents, they complicate the user's experience of electronic content. For example, the many menus, toolbars, scroll bars and command dialogues associated with known multiple-window architectures detract from the user's ability to maintain an understanding of which content is the current focus of the system. That is, multiple-window architectures provide a multi-space navigational environment in which each display context is provided with its own set of navigational controls and therefore, these architectures lack the simplicity maintained by a single navigational focus. In a user interface without a single navigational focus, there may be a multiplicity of navigational controls on the screen, some which affect one frame, some which affect another, and possibly some that effect navigation between different of the frames. Because each frame needs its own navigational controls, many identical controls are duplicated and different frames may implement similar navigational features in different ways, or implement features in one frame that are not available in others, all depending on which application is running in each frame. This creates both clutter as well as conceptual difficulty for users. Thus, it is difficult for a user to maintain a clear understanding of which of a number of navigational environments displayed is the currently active one. This complicates the user's experience and often results in unnecessary duplication of sets of navigational controls.
In contrast to multiple-window architectures, page-oriented architectures offer simplicity derived from the maintenance of a single navigational focus at all times. These architectures treat all electronic content as a document that can be paged through sequentially. Thus, the navigational focus is always very apparent to the user. Today's web browsers exhibit qualities of page-oriented architectures insofar as web pages are viewed individually in series as the user navigates to different electronic document pages. Because they mimic the navigational paradigm of a printed book and provide no confusion as to the current navigational focus, page-oriented architectures provide users with a very familiar and simple system for navigating electronic documents.
One drawback of strict page-oriented architectures, however, is that they do not permit the simultaneous viewing of multiple contexts of electronic documents. Multiple contexts would include, for example, non-contiguous pages of a single electronic document, or pages of two different electronic documents. To illustrate this drawback of strict page-oriented architectures, today's browsers do not permit simultaneous viewing of multiple contexts without resort to a multi-tasking, multiple-window environment in which more than one instance of the browser can be executed. Resort to multiple-window environments, however, results in a loss of the benefits of the single navigational focus of the page-oriented architecture.
It would therefore be desirable to provide apparatus and methods for displaying electronic documents that permits the simultaneous viewing of multiple contexts of electronic documents, while maintaining only a single navigational focus. It would also be desirable to provide apparatus and methods for displaying electronic documents which eliminates the complexity inherent in prior art systems that provide a navigational focus for each of the multiple contexts being displayed to the user.
Another drawback of multiple-window architectures is that such architectures do not always provide for the creation of a single navigational history. Each window maintains either its own navigational history, or else no history (this depends on the application). Furthermore, the features and user interface for accessing and navigating history differs among applications. For example, if the user runs two instances of a browser, each window has its own back/forward history chain. If a user had visited documents 1, 2, and 3 in Window A and 4, 5, and 6 in Window B, there would be no way to use the back/forward buttons in Window A to get to document 4, 5, or 6, because 4, 5, and 6 are not in its navigation history. To allow access to documents not in history, some browsers provide an address bar where document addresses can be entered, and a search command that can locate certain categories of documents (web pages).
Known applications provide other kinds of navigational facilities. One is a short list of recently used documents that are kept under a "File" menu. Another is the list of documents currently opened by that application, which is kept under a "Window" menu. Both the File and the Window menu can thus be used in lieu of forward/back buttons to navigate among recently viewed documents. And of course, the lists of documents under these menus in different applications will be different, depending on which documents the user has recently opened within each window. Some applications also provide a File Open command where the names of documents can be entered; this is analogous to but different from the browser address bar.
Thus, given a display of multiple windows, with the focus on one current window, should the user wish to display a recently visited document, they must remember which window it had been opened in and put the focus on that window before they attempt to actually navigate to that document. They must also deal with the different features and user interfaces that the different applications provide for accomplishing this navigation. Thus, it would be desirable to provide apparatus and methods for displaying electronic documents that provides a single navigational history and a single, consistent user interface and set of features for performing navigation between documents.

Methods and apparatus for displaying multiple contexts in electronic documents


A V-H transfer section is formed by the following steps: N+-type impurities are first ion-implanted in such a manner that they spread out into an area larger than a channel of a vertical transfer register. An electrode of the vertical transfer register and electrodes of a horizontal transfer register are then formed. Thereafter, P+-type impurities are implanted into the electrode of the vertical transfer register and the electrodes of the horizontal transfer register in a self-alignment manner.

The present invention relates to a process for manufacturing a solid-state image pick-up device. More particularly, the invention relates to a process for manufacturing a charge transfer section, used in a solid-state image pick-up device, for transferring charges from vertical transfer registers to a horizontal transfer register.
As a solid-state image pick-up device, on the whole, becomes smaller, the dimensions of the individual elements of the device accordingly decrease. As an example of the downsizing of the elements of the device, the channel width of a charge transfer section for transferring signal charges from vertical transfer registers to a horizontal transfer register (hereinafter referred to as "the V-H transfer section") is decreased.
FIG. 8 is an elevational view of a conventional V-H transfer section. FIG. 9 is a cross sectional view along line Y-Y' of FIG. 8. Referring to FIGS. 8 and 9, a vertical transfer register 81 is comprised of channels 83 and electrodes 84-1 and 84-4 (only the electrode 84-4 is shown in FIG. 8) that are driven in, for example, four phases. The channels 83 are formed by ion-implanting N+-type impurities into the upper top surface of a silicon substrate 82. The four-phase electrodes 84-1 to 84-4 are disposed above the channels 83 and are sequentially arranged in the transfer direction. On the other hand, a horizontal transfer register 85 includes a channel 86 and electrode pairs 87-1 and 87-2, driven in, for example, two phases, each pair forming a storage electrode ST and a transfer electrode TR. The channel 86 is formed by ion-implanting N+-type impurities into the obverse surface of the silicon substrate 82. On the other hand, the electrode pairs 87-1 and 87-2 are disposed above the channel 86 and are sequentially arranged in the transfer direction. In each of the electrode pairs 87-1 and 87-2, the storage electrode ST (indicated by the one-dot broken line in FIG. 8) is formed of a first polysilicon layer, while the transfer electrode TR (designated by the two-dot broken line in FIG. 8) is formed of a second polysilicon layer.
Further, the transfer electrode TR of the first phase (.phi.H1) electrode pair 87-1 extends until the fourth-phase (.phi.V4) electrode 84-4 along the channel 83 of the vertical transfer register 81. The extending portion TR' of the transfer electrode TR projecting from the channel 86, together with the channel 83 positioned under the portion TR', form a V-H transfer section 88 for transferring signal charges from the vertical transfer register 81 to the horizontal transfer register 85.
In the V-H transfer section 88 constructed as described above, the channel width is determined by the manufacturing precision of the channel 83 and the transfer electrode TR of the first-phase (.phi.H1) electrode pair 87-1 of the horizontal transfer register 85. More specifically, in consideration of the matching precision of the channel 83 to the extending portion TR' of the transfer electrode TR of the first-phase (.phi.H1) electrode pair 87-1 during manufacturing of the V-H transfer section 88, the channel 83 should be formed within the edges of the transfer electrode TR, away from each edge across a predetermined distance (margin) A so that it does not project from the extending portion TR'.
As described above, in the conventional solid-state image pick-up device, the channel width of the V-H transfer section 88 depends on the manufacturing precision of the channel 83 and the transfer electrode TR of the first-phase electrode pair 87-1 of the horizontal transfer register 85. Thus, considering manufacturing precision, the channel width of the V-H transfer section 88 cannot be increased to a great degree. Under this restriction, if the individual elements of the solid-state image pick-up device are decreased along with the downsizing of the overall device, the channel width of the V-H transfer section 88 inevitably should be made smaller. However, an excessively smaller channel width of the V-H transfer section 88 degrades the transfer efficiency of signal charges from the vertical transfer register 81 to the horizontal transfer register 85. This imposes a restriction of the downsizing of the solid-state image pick-up device.

Process for manufacturing a solid-state pick-up device


A seismic isolation mechanism includes a seismic isolation apparatus which is installed at one end in a vertical direction on a superstructure and installed at another end 4 in the vertical direction on a floor serving as a foundation or a substructure to isolate the vibration of the superstructure with respect to the floor; a first attenuation damper which is connected to the superstructure and connected at another end a portion of the seismic isolation apparatus to attenuate the vibration of the superstructure with respect to the floor; and a second attenuation damper.

In Patent Document 1, a seismic isolation mechanism is proposed for damping horizontal vibrations in a structure, in which a seismic isolation apparatus for damping horizontal vibrations is provided between the structure and a foundation thereof, and the seismic isolation apparatus has a transmitting member which transmits to the seismic isolation apparatus the relative displacement of the structure to the foundation in the horizontal direction and allows the relative displacement in the vertical direction.
In Patent Document 2, a vibration damper is proposed which is used by being interposed between two relatively displaceable members of a building to damp the vibration of the building, and in which one damper for attenuating the vibration between the two members is connected in series to another damper which when the load applied to the one damper from the two members has exceeded a fixed value, blocks the transmission of the load to the one damper.

This patent is subject to a terminal disclaimer.


A method of manufacturing a semiconductor device provides a semiconductor substrate with a gate and a number of source/drain regions on the semiconductor substrate. A layer containing a strain-inducing element is provided over the number of source/drain regions. The strain-inducing element is driven from the layer containing a strain-inducing element into the number of source/drain regions. A number of source/drains is formed in the number of source/drain regions.

Electronic products are used in almost every aspect of life, and the heart of these electronic products is the semiconductor, or integrated circuit. Semiconductor devices are used in everything from airplanes and televisions to wristwatches.
Semiconductor devices are made in and on wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of semiconductor dies, each worth as much as hundreds or thousands of dollars.
Semiconductor dies are made up of hundreds to billions of individual components. One common component is the transistor. The most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor technology is a Complementary Metal Oxide Semiconductor (CMOS) technology.
The principal elements of CMOS technology generally consist of a silicon substrate having trench isolation regions surrounding n-channel or p-channel transistor areas. The transistor areas contain polysilicon gates on a silicon oxide dielectric, or gate oxides, over the silicon substrate. The silicon substrate adjacently opposite the polysilicon gate is doped to become conductive. The doped regions of the silicon substrate are referred to as "shallow source/drain regions," or "source/drain extension regions" which are separated by a channel region in the substrate beneath the polysilicon gate. An oxide or nitride spacer, referred to as a "sidewall spacer," on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain regions, which are called "deep source/drain regions." The shallow and deep source/drain regions are collectively referred to as source/drain regions.
To complete the transistor, a dielectric layer is deposited to cover the polysilicon gate, the spacer, and the silicon substrate. To provide electrical contacts for the transistor, openings are etched in the dielectric layer to the polysilicon gate and the source/drain regions. The openings are filled with metal to form electrical contacts. To complete the integrated circuits, the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
In operation, an input signal to the gate contact to the polysilicon gate controls the flow of electric current from one source/drain contact through one source/drain region through the channel to the other source/drain region and to the other source/drain contact.
Metal oxide semiconductor field effect transistor (MOSFET) devices are well known and widely used in the electronics industry. The carrier mobility of a MOSFET device is an important parameter because of its direct influence on the drive current and switching performance. In standard MOSFET technology, the channel length and gate dielectric thickness are reduced to improve current drive and switching performance. However, reducing the gate dielectric thickness can compromise device performance because of the associated increase in gate leakage current.
In has been shown that in p-channel MOSFETs, a buried silicon-germanium channel region under compressive stress enhances hole mobility in the channel region. Accordingly, a higher drive current can be obtained resulting in faster operating MOSFETs.
One existing strained channel silicon semiconductor includes strained silicon (Si) on a relaxed Silicon/Germanium (SiGe) substrate to obtain the stresses needed. However, these devices have the disadvantages of self-heating and a tight thermal budget window. A higher strain also is required for pMOS transistors to obtain enhanced hole mobility.
One proposed solution involves etching a recess in the area of the source/drain regions and depositing SiGe or silicon/germanium/carbon (SiGeC) in the recess to strain the channel of the transistor. This method involves an additional etching step that adds to the cost of manufacturing the devices.
Another proposed solution involves forming germanium (Ge) on an insulator by oxidation of SiGe on an insulating material, such as an oxide. This approach employs Ge as the channel of the transistor. This approach requires an insulating layer that also adds to the cost of manufacturing the devices.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

Method of manufacturing a semiconductor device with a strained channel

Chartered Semiconductor Manufacturing Ltd.


Airbridge structures and processes for making air bridge structures and integrated circuits are disclosed. One airbridge structure has metal conductors 24 encased in a sheath of dielectric material 249. The conductors extend across a cavity 244 and a semiconductor substrate 238. In one embodiment, the conductors traversing the cavity 244 are supported by posts 248 that extend from the substrate. In another embodiment, oxide posts 258 extend from the substrate to support the conductors.

The present invention relates to integrated circuit air bridge structures and methods of fabricating such structures which facilitate the formation of the integrated circuits and components thereof at the substrate level. The invention is especially suitable for use in providing integrated circuits which are hermetically sealed so as to protect the integrated circuits and any components, such as interconnecting conductors air bridges, inductors or capacitors, against damage or contamination from outside the device.
In order to reduce interconnect capacitances in high performance and high frequency processes, air bridges are often used. A typical air bridge is formed using a second layer of interconnect metal deposited and patterned over a sacrificial material. The sacrificial material is later removed to leave a metal lead surrounded by air rather than a dielectric, such as oxide. The capacitances to the substrate and to other metal lead is thus reduced since air has a lower dielectric constant than do solid insulators such as silicon dioxide or silicon nitride.
However, traditional air bridge manufacturing techniques and structures have several disadvantages. The length of an air bridge is often limited by flexure of metal between two vias. So, relatively long air bridges can only be manufactured by stitching together multiple lengths of short air bridges. Another problem is that circuits fabricated with air bridges cannot be passivated. In a normal process, a passivation layer is deposited on top of an integrated circuit. Typical passivation layers are silicon oxide or silicon nitride. However, for air bridge structures, the passivation layer has to be omitted otherwise the passivation layer will fill the air under the bridge and thereby increase the capacitance of the air bridge or damage the bridge itself.
Accordingly, there has arisen a need for air bridges that can be made of longer lengths of metal than are available in air bridges of the prior art and also for air bridges that can be incorporated into integrated circuits where such circuits have a passivation layer.
It is the principal object of the present invention to provide improved integrated circuit air bridge structures which may be fabricated at the substrate level and which are passivated in the course of fabrication thereby avoiding the need for ceramic packaging or encapsulation, as well as to methods for fabrication of such structures.
It is a still further object of the present invention to provide improved integrated circuit air bridge structures which may be fabricated at the substrate level without materially increasing the volume occupied by the integrated circuit and any components.
It is a still further object of the present invention to provide improved integrated circuit air bridge structures having air bridges or other components made out of conductive elements (e.g., inductors or capacitors), wherein sufficient spacing is provided between the air bridges of the components and the active integrated circuit so as to reduce the effect of parasitic capacitance between the conductive elements and the circuits and adversely affecting the high frequency response of these circuits, as well as to methods of fabricating such structures.
The invention may attain one or more, but not necessarily all, of the foregoing objects.
Briefly described, an integrated circuit structure in accordance with the invention provides an air bridge fabricated on the same die as the integrated circuit to which the air bridge is connected.
The invention provides an on-silicon air bridge that is compatible with single substrate and bonded substrate structures. The invention provides an air bridge structure on a semiconductor substrate or a device substrate. The device or semiconductor substrate may have one or more integrated circuits or semiconductor devices formed therein. The air bridge structure comprises an elongated metal conductor that is encased in a dielectric sheath. At least a portion of the sheath is exposed to ambient atmosphere. In one embodiment, the entire sheath is exposed to atmosphere. However, other embodiments expose a substantial portion of the sheath to ambient atmosphere in order to reduce the dielectric coupling between the sheath and the semiconductor substrate. In a typical construction, the encased conductor crosses a cavity in the substrate. The encased conductor is supported in its transit across the cavity by posts that extend from the lower surface of the cavity. The support posts comprise dielectric material, substrate material, or both.
In its broader aspects, the air bridge structure is made by forming a dielectric layer over semiconductor substrate. Next, an elongated conductor is formed over the dielectric layer and is encased in dielectric material. Then, portions of the substrate or the dielectric layer, or both, are removed to expose the encased elongated conductor to air. The method contemplates using sacrificial materials located between the encased conductor in the substrate. Removing the sacrificial material forms an air bridge cavity. The methods of the invention also include removing portions of the substrate in order to form the air bridge cavity.
Particular embodiments of the invention include a cavity formed in the substrate and/or in the dielectric layer on the substrate. The encased conductors extend across the cavity and enter and exit the dielectric layer overlying the cavity.
The invention may also be used with bonded substrates. In a bonded substrate structure, a device substrate is bonded to a handle substrate, typically with an oxide bonding layer. An air bridge structure is formed in the device substrate in several ways. Those skilled in the art will appreciate that trench isolation is a common step used in the formation of devices and bonded substrates. The air bridge of the invention is compatible with the trench forming steps that are typically used in bonded substrates. In one bonded substrate embodiment, trenches are formed down to the oxide bonding layer. The trenches are coated with a dielectric, filled, and planarized. The dielectric layer covers the planarized trenches and elongated conductors are patterned on the dielectric layer over the air bridge trenches. Another dielectric layer covers the patterned conductors in order to encase them in a dielectric. Then the substrate is further patterned and etched to remove material from between the filled air bridge trenches. The final structure provides air bridge conductors encased in a dielectric that is spaced from the bonding oxide layer.
Bonded substrate structures are used to form inductors. In one embodiment, elongated conductors are encased in a dielectric layer that is disposed over a device substrate region located between isolating trenches. Vias are opened in the dielectric layer and substrate material is removed to form an air bridge cavity beneath the encased conductors. Two air bridge cavities may be formed near one another and separated by a third cavity. Over each air bridge cavity conductors are patterned in a continuous, spiral path of metal in order to form an inductors. The third cavity is filled with ferromagnetic material.
Two further embodiments of the invention use a sacrificial layer for forming a cavity beneath an elongated, encased conductor. In one embodiment, a sacrificial layer of polysilicon is formed over a first dielectric layer that is on the semiconductor substrate. An encased conductor is formed over the sacrificial layer. Vias are opened to the sacrificial polysilicon and the polysilicon is removed to leave an air bridge cavity beneath the encased conductor and between the encased conductor and the silicon substrate. In an alternate embodiment, the dielectric layer on the surface of the substrate is partially removed before the sacrificial polysilicon is deposited. The sacrificial polysilicon is removed along with portions of the underlying substrate. The latter provides an enlarged air bridge cavity beneath the encased conductor.
The foregoing and other objects, features and advantages of the invention as well as presently preferred embodiments thereof and the best known techniques for fabricating integrated circuit structures in accordance with the invention will become more apparent from a reading of the following description in connection with the accompanying drawings.

Integrated circuit air bridge structures and methods of fabricating same

Abstract: In another embodiment, trenches 101 are made in a device substrate 110 bonded to a handle substrate 100. The trenches are filled with a dielectric and a conductor pattern is formed over the filled trenches. The substrate material between the conductors is then removed to leave a pattern of posts 116, 114, 112 that included dielectrically encased conductors 106.

Abstract: In another bonded wafer embodiment, conductors 204 are encased in a dielectric above a sacrificial device region. The device region is isolated by suitably filled trenches. Vias 224, 226 in the dielectric 205 allow removal of the substrate material to form a cavity 208 beneath the conductors 204.

Abstract: Other embodiments included a conductor 42 encased in dielectric that is formed above a region from which sacrificial polysilicon is removed to form a cavity 66. It is still another embodiment the conductor 42 is enclosed in a dielectric above a cavity 66a from which device material is removed.


A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Semiconductor devices are used for integrated circuits in a variety of electrical and electronic applications, such as computers, cellular telephones, radios, and televisions. One particular type of semiconductor device is a semiconductor storage device, such as a random access memory (RAM) device. Many RAM devices include many storage cells arranged in a two-dimensional array with two sets of select lines, wordlines and bitlines. An individual storage cell is selected by activating its wordline and its bitline. RAM devices are considered "random access" because any memory cell in an array can be accessed directly if the row and column that intersect at that cell are known.
A commonly used form of RAM is known as a dynamic RAM (DRAM) device. Dynamic random access memory has memory cells with a paired transistor and capacitor, wherein the capacitor requires periodic refreshing. One particular type of DRAM device is a synchronous DRAM (SDRAM) device, in which the memory cells are accessed synchronously. Synchronous dynamic random access memory often takes advantage of the burst mode concept to greatly improve performance by staying on the row containing the requested bit and moving rapidly through the columns. To achieve a high speed operation, a double data rate (DDR) architecture is often used, during which two data transfers are made per clock cycle, one upon the rising edge of the clock and the other upon the falling edge.
Normally multiple DRAMs are connected in parallel to the data lines to achieve high memory capacity with low cost. One issue that arises with high speed operation is the need to properly terminate bus lines. Each chip along a bus line will cause an impedance discontinuity, which can cause reflections and other noise such as distortion and ringing. To minimize these affects, the bus will be terminated with a resistor, with the goal of having uniform impedance along the line. A technique known as on-die termination (ODT) can be used to terminate the bus on the chip itself rather than on the circuit board.
Although the termination resistors on the circuit board reduce some reflections on the signal lines, they are unable to prevent reflections resulting from the stub lines that connect to the chips. A signal propagating from the controller to the components encounters an impedance discontinuity at each stub leading to the chips on the module. As a result, a reflection will be generated at each stub independent of the termination setting. It is desired, however, to minimize the impact of these reflections.


The invention provides a fixing unit including a fixing roller and a pressure roller pressed against the fixing roller inside a housing, for holding and conveying a sheet carrying an image formed by a developer between the fixing roller and the pressure roller thus to fix the image onto the sheet, including a removal section that removes an unfixed developer adhered to the fixing roller or the pressure roller, and an air vent located close to the removal section.

1. Field of the Invention
The present invention relates to a fixing unit including a removal unit that removes unfixed developer adhered to a fixing roller or a pressure roller, and to an image forming apparatus including such a fixing unit.
2. Description of the Related Art
An image forming apparatus based on electrophotography forms a desired toner image on a photoconductive drum, and after transferring the toner image on the photoconductive drum to a paper, fixes the toner image onto the paper by a fixing unit. The fixing unit usually includes a pair of heaters. A typical example of the pair of heaters is a fixing roller and a pressure roller disposed so as to be pressed against each other with a paper feeding path held therebetween. This type of fixing unit holds the paper between the fixing roller and the pressure roller, and applies heat and pressure to the paper to thermocompressively fix the toner image onto the paper, thus completing image forming on the paper.
In such a fixing unit, since at least either of the fixing roller or the pressure roller contacts the toner applied to the paper, the toner may adhere to the fixing roller or the pressure roller during the fixing process. Besides, the toner that has adhered to either of the fixing roller or the pressure roller often adheres to the other, via the contact interface therebetween.
To avoid this, for example Japanese Patent Application Laid-Open No. 05-119661 proposes a fixing unit provided with a brush type cleaner disposed so as to contact the fixing roller, to thereby remove the toner adhere thereto.
FIG. 1 is a schematic cross-sectional view showing an internal structure of a conventional fixing unit provided with a cleaner. The fixing unit shown in FIG. 1 includes a fixing roller 201 and a pressure roller 202 inside a housing 200 which constitutes a frame of the apparatus. The fixing roller 201 is a hollow cylindrical-shaped roller including a heater lamp 201a therein, which maintains a predetermined temperature of the roller surface. The pressure roller 202 is a cylindrical-shaped roller pressed against the fixing roller 201, so as to provide a fixing nip of a predetermined width with the fixing roller 201. When a paper P to which a toner T has adhered is conveyed to the fixing unit, the fixing roller 201 and the pressure roller 202 applies heat and pressure to the paper P while feeding the paper P held therebetween, to thereby fix the toner image on the paper.
On the circumferential surface of the pressure roller 202, an oil supplier 203, a cleaning roller 204 and a separating blade 205 are disposed. The oil supplier 203 applies an oil to the surface of the pressure roller 202 via an oil applicator 203a, for smooth separation of the paper P from the pressure roller 202. The cleaning roller 204 includes a core metal 204a and a brush portion 204b radially implanted on the core metal 204a, to serve to remove the unfixed toner stuck to the pressure roller 202. The separating blade 205 is pressed against the circumferential surface of the pressure roller 202, to peel off from the pressure roller 202 the paper P on which the toner has been fixed. The paper P separated from the pressure roller 202 passes through a paper guide 206 and is discharged outward by a discharge roller 207.
The conventional fixing unit thus constructed utilizes the brush portion 204b of the cleaning roller 204 to remove the toner stuck to the pressure roller 202 after the fixing process. However, since a portion of the toner adheres to the brush portion 204b, the toner adheres again to the pressure roller via the mutual contact point, when the cleaning roller 204 has made one rotation.
Besides, the brush 204b is generally made of a flexible synthetic resin. Accordingly, when the brush portion 204b removes the unfixed toner, a portion of the toner may be flipped by the tip of the brush portion 204b, thus to splash inside the housing 200. The toner that has splashed not only contaminates the interior section of the housing 200, but also often adheres to the pressure roller 202 and the paper P being conveyed, which leads to degradation in the printed image quality.

System for collecting an unfixed developer with an airflow


A method of regulating an amount of NH3 stored in a catalyst of an exhaust after-treatment system includes determining a mass of NH3 into the catalyst based on a dosing rate of a dosing agent that is injected into an exhaust stream upstream of the catalyst and determining a mass of NH3 out of the catalyst. An accumulated mass of NH3 within the catalyst is calculated based on the mass of NH3 into the catalyst and the mass of NH3 out of the catalyst. The dosing rate is regulated based on the accumulated mass of NH3 within the catalyst.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Internal combustion engines combust an air and fuel mixture to generate drive torque. The combustion process generates exhaust that is exhausted from the engine to atmosphere. The exhaust contains nitrogen oxides (NOx), carbon dioxide (CO2), carbon monoxide (CO) and particulates. NOx is a term used to describe exhaust gases that consist primarily of nitrogen oxide (NO) and nitrogen dioxide (NO2). An exhaust after-treatment system treats the exhaust to reduce emissions prior to being released to atmosphere. In an exemplary exhaust after-treatment system, a dosing system injects a dosing agent (e.g., urea) into the exhaust upstream of a selective catalytic reduction (SCR) catalyst. The exhaust and dosing agent mixture reacts over the SCR catalyst to reduce the NOx levels released to atmosphere.
The dosing agent reacts with NOx on the SCR catalyst to accomplish the NOx reduction. More specifically, the dosing agent breaks down to form ammonia (NH3), which is the reductant utilized to react with the NOx. The following exemplary, chemical relationships describe the NOx reduction:4NO+4NH3+O2→4N2+6H2O4NH3+2NO+2NO2→4N2+6H2O3NO2+4NH3→3.5N2+6H20
To perform the above-described NOx reduction, the SCR catalyst stores NH3 therein. For an SCR catalyst to perform effectively, the NH3 storage level must be maintained at an adequate level. More specifically, the NOx reduction or conversion efficiency is dependent upon the NH3 storage level. In order to maintain high conversion efficiency under various operating conditions, the NH3 storage must be maintained. However, as the temperature of the SCR catalyst increases, the NH3 level must be reduced to avoid NH3 slip (i.e., excess NH3 being released from the SCR catalyst), which can reduce the conversion efficiency of the catalyst.

Excess NH3 storage control for SCR catalysts


A method of pre-treating steel-hybrid circuit board substrates or carrier plates before the application of coatings that are to be burnt in or fired. In prior art steel-hybrid circuit boards of this type, the burning-in of the coatings in a kiln produces undesirable warping of the circuit boards due to the different coefficients of thermal expansion of the materials employed for the coatings and for the carrier plates, unless relatively thick steel-hybrid circuit board carrier plates are employed. This warping is avoided, while still permitting the use of steel hybrid circuit boards of a lesser thickness, by pre-treating the steel-hybrid circuit board carrier plates to provide same with a mechanical pre-stress causing a defined curvature which compensates for the warping of the circuit board to be expected during burn-in.

The present invention relates to a method of pretreating steel-hybrid printed circuit boards, particularly those which are intended to be provided with surface mounted electronic components, before coatings that are to be burnt in or fired are applied.
It is known to produce steel-hybrid circuit boards of this type in that a carrier plate in the form of a steel-hybrid base plate is covered with various electrically conductive and electrically insulating coatings, respectively, which after their respective application are fired in a conventional kiln.
One problem encountered in the production of such circuit boards is that at the customary firing temperatures in the kiln, the differences in coefficients of thermal expansion of the carrier material (here the steel-hybrid or substrate) and of the respective coating produce different thermal stresses. As the person skilled in the art is aware, in the past this has always resulted in warping of the fired circuit board.
In the past, and as a remedy and solution of the above-described problem, a very thin coating has been applied to a rather thick steel-hybrid carrier. Thin coatings, however, exhibit adhesion problems and frequently result in undue electrical breakdown voltages. Moreover, thick steel-hybrid carrier plates have an undesirably high weight, frequently increase the time required for the entire manufacturing process, and are expensive. Thus, to obtain a circuit board that is not noticeably warped it has been necessary to revert, for example, to a carrier plate thickness of about 4-6 mm for a coating thickness of 150 .mu.m.
Because of the problems described above, so-called multi-layer steel-hybrid circuit boards having planar conductor paths in different layers have not yet been able to be produced.

Method for the treatment of steel-hybrid printed circuit boards