The present invention provides methods and compositions for conferring selective death on cells expressing a specific target precursor messenger RNA (selective target pre-mRNA). The compositions of the invention include pre-trans-splicing molecules (PTMs) designed to interact with a target precursor messenger RNA molecule (target pre-mRNA) expressed within a cell and mediate a trans-splicing reaction resulting in the generation of a novel chimeric mRNA molecule (chimeric mRNA) capable of encoding a light producing protein or enzyme. Cell death is further mediated by the presence of a photosensitizer which upon photoactivation produces cytotoxicity.

DNA sequences in the chromosome are transcribed into pre-mRNAs which contain coding regions (exons) and generally also contain intervening non-coding regions (introns). Introns are removed from pre-mRNAs in a precise process referred to as splicing. In most cases, the splicing reaction occurs within the same pre-mRNA molecule, which is termed cis-splicing. Splicing between two independently transcribed pre-mRNAs is termed trans-splicing. Trans-splicing was first discovered in trypanosomes (Sutton & Boothroyd, 1986, Cell 47:527; Murphy et al., 1986, Cell 47:517) and subsequently in nematodes (Krause & Hirsh, 1987, Cell 49:753); flatworms (Rajkovic et al., 1990, Proc. Nat'l. Acad. Sci. USA, 87:8879; Davis et al., 1995, J. Biol. Chem. 270:21813) and in plant mitochondria (Malek et al., 1997, Proc. Nat'l. Acad. Sci. USA 94:553). In the parasite Trypanosoma brucei, all mRNAs acquire a splice leader (SL) RNA at their 5′ termini by trans-splicing. A 5′ leader sequence is also trans-spliced onto some genes in Caenorhabditis elegans. This mechanism is appropriate for adding a single common sequence to many different transcripts.
The mechanism of spliced leader trans-splicing, which is nearly identical to that of conventional cis-splicing, proceeds via two phosphoryl transfer reactions. The first causes the formation of a 2′-5′ phosphodiester bond producing a 'Y' shaped branched intermediate, equivalent to the lariat intermediate in cis-splicing. The second reaction, exon ligation, proceeds as in conventional cis-splicing. In addition, sequences at the 3′ splice site and some of the snRNPs which catalyze the trans-splicing reaction, closely resemble their counterparts involved in cis-splicing.
Trans-splicing may also refer to a different process, where an intron of one pre-mRNA interacts with an intron of a second pre-mRNA, enhancing the recombination of splice sites between two conventional pre-mRNAs. This type of trans-splicing was postulated to account for transcripts encoding a human immunoglobulin variable region sequence linked to the endogenous constant region in a transgenic mouse (Shimizu et al., 1989, Proc. Nat'l. Acad. Sci. USA 86:8020). In addition, trans-splicing of c-myb pre-RNA has been demonstrated (Vellard, M. et al. Proc. Nat'l. Acad. Sci., 1992 89:2511-2515), trans-spliced RNA transcripts from SV40 have been detected in cultured cells and nuclear extracts (Eul et al., 1995, EMBO. J. 14:3226) and more recently, the transcript from the p450 gene in human liver has been shown to be trans-spliced (Finta et al., 2002, J. Biol Chem 22:5882-5890). However, in general, naturally occurring trans-splicing of mammalian pre-mRNAs is thought to be an exceedingly rare event.
In vitro trans-splicing has been used as a model system to examine the mechanism of splicing by several groups (Konarska & Sharp, 1985, Cell 46:165-171 Solnick, 1985, Cell 42:157; Chiara & Reed, 1995, Nature 375:510). Reasonably efficient trans-splicing (30% of cis-spliced analog) was achieved between RNAs capable of base pairing to each other, splicing of RNAs not tethered by base pairing was further diminished by a factor of 10. Other in vitro trans-splicing reactions not requiring obvious RNA-RNA interactions among the substrates were observed by Chiara & Reed (1995, Nature 375:510), Bruzik J. P. & Maniatis, T. (1992, Nature 360:692) and Bruzik J. P. and Maniatis, T., (1995, Proc. Nat'l. Acad. Sci. USA 92:7056-7059). These reactions occur at relatively low frequencies and require specialized elements, such as a downstream 5′ splice site or exonic splicing enhancers.
U.S. Pat. Nos. 6,083,702, 6,013,487 and 6,280,978 describe the use of PTMs to mediate a trans-splicing reaction by contacting a target precursor mRNA to generate novel chimeric mRNAs. The resulting RNA can encode any gene product including a protein of therapeutic value to the cell or host organism, a toxin, such as Diptheria toxin subunit A, which causes killing of the specific cells or a novel protein not normally present in cells. The PTMs can also be engineered for the production of chimeric proteins including those encoding reporter molecules useful to image gene expression in vivo in real time or to add peptide affinity purification tags which can be used to purify and identify proteins expressed in a specific cell type.
Photodynamic therapy (PDT) of cancer uses light excitation of a photosensitive substance to produce oxygen-related cytotoxic intermediates, such as singlet oxygen or free radicals (Dougherty et al., 1993, Photochem. Photobiol. 58:895-900; Hopper et al., 2000, Lancet Oncol. 1:212-219; Ochsner et al., 1997, J. Photochem. Photobiol. B. Biol 39:1-18, Fuchs et al., 1998, Biol. Med. 24:835-847). For example, the use of CL4 for the excitation of the photosensitizer hypercin has been used for the in vitro inactivation of the equine infectious anemia virus (Carpenter, S. et al. 1994, Proc. Natl. Acad. Sci. USA 91:12273-12277). Additionally, Theodossis et al., described the in vitro photodynamic effect of rose bengal activated by intracellular generation of light generated by the oxidation of the chemiluminescent substrate luciferin, in luciferase-transfected NIH 3T3 murine fibroblasts (Theodossis et al., 2003, Cancer Research 63:1818-1821).
PDT involves the use of two individual components that combine to induce cytotoxicity in an oxygen dependent manner. The first component of PDT is a photosensitizer molecule that usually enters cells and/or tissues non-specifically. The second component involves the localized administration of light of a specific wavelength that is capable of activating the photosensitizer. Once activated the photosensitizer transfers energy from the light to molecular oxygen, thereby generating reactive oxygen species (ROS), such as singlet oxygen and free radicals. Such ROS mediate cellular toxicity. Photosensitizers may also undergo photochemical reactions that do not use oxygen as an intermediate, such as compounds that result in photoaddition to DNA. As used herein, the term photosensitizer includes, but is not limited to, other chemicals that are activated upon exposure to light. Such photosensitizers are known to those skilled in the art and the examples set forth herein are non-limiting.
Although photodynamic therapy use is desirable because of its limited side effects, its main disadvantages are the poor accessibility of light to certain tissues and the problem of restricting the delivery of light primarily to the target cells. The present invention provides methods and compositions for targeted expression of light producing enzymes in the desired cell types and in cells that otherwise are inaccessible to light, thereby providing a method for use of photodynamic therapy for the specific destruction of targeted cells. Specifically, the invention provides PTM molecules that are designed to interact with one or more cell selective target pre-mRNA species and mediate trans-splicing reactions resulting in the generation of chimeric mRNA molecules capable of encoding light producing enzyme or protein. The expression of the light producing enzyme or protein permits activation of a co-localized photosensitizer leading to death of the selected cell. The present invention provides a system for targeting cancer cell destruction. In addition, the invention provides a system for targeting selective cell death to cells infected with pathogenic microorganisms, or, cell death in instances where the activity of a particular cell type leads to disease.

Trans-splicing mediated photodynamic therapy


The present invention provides an apparatus and method for monitoring the read/write reliability of data storage devices contained within a data cartridge library system. The data cartridge library system includes multiple player/recorder devices. In accordance with one aspect of the invention, the data cartridge library computer queries a player/recorder device after it has been involved in a read/write operation. In one embodiment, the information queried is the Write and/or Read ECC Error Rates. In another embodiment, the Write and/or Read ECC Error Rates are assessed to determine whether the subject player/recorder device is experiencing read/write problems and whether remedial action is warranted. In another embodiment, the subject player/recorder device is tested using a certified test cartridge and a known data pattern. In another aspect of the invention, preventative maintenance of the data cartridge library system includes one of the player/recorder devices writing a known data pattern to a certified test and the same device, as well as the remaining player/recorder devices, reading the known data pattern from the certified cartridge. Preferably, these steps are repeated for all player/recorders in the data cartridge library system and the respective Write and Read ECC Error Rates are displayed in a matrix format to facilitate diagnosing whether any of the player/recorders are experiencing misalignment or data interchange problems.

The general purpose of data cartridge library systems is to store large amounts of data provided by a host computer system and to transfer stored data back to the host computer system when needed.
The components of a typical data cartridge library system include a storage array for holding a number of data cartridges that each contain a recording media, typically tape or disk; one or more player/recorder for writing data from the host computer onto the recording media and reading data previously recorded on the recording media and providing this data to the host computer system; and a picker for moving data cartridges between the storage array and the player/recorders. One commonly used player/recorder is known as a helical scan tape player, which records narrow strips of data diagonally across a tape. Another type of player/recorder is known as a digital linear tape drive.
The typical data cartridge library system also includes an operator interface that permits an operator to interact with the system. Generally, the interface is comprised of an output device, such as a CRT, and an input device, such as a keyboard.
Further included in the typical data cartridge library system is a controller that processes requests from the host computer system and operator inputs. For example, the controller would respond to a request from the host computer to write data onto recording media in a data cartridge by causing the picker to retrieve the subject cartridge from the storage array and load the cartridge into the appropriate player/recorder so that data from the host computer can be recorded.
One problem with present data cartridge library systems is that occasionally such systems are either unable to store/retrieve data on a recording media in a data cartridge or the storing/retrieval requires a substantial amount of time and/or effort. Presently, one source if the read/write problem has been identified as the use of "old cartridges." More specifically, when magnetic media within a data cartridge has been subjected to a number of read/write operations in a recorder/player, the magnetic media becomes worn out, thereby making storage/retrieval of the data difficult. To address this problem, many library systems periodically replace "old cartridges" with "new cartridges" that contain the data previously recorded on the old cartridge.
Even with the periodic replacement of data cartridges, the noted read/write problem persists. Consequently, there is a need for an apparatus and method which further provides the ability to reliably read/write data.

Apparatus and method for monitoring read/write reliability of data storage device


A semiconductor device is disclosed which includes a data memory which stores data and a code memory which stores an ECC code corresponding to the data. The semiconductor device includes an ECC unit which outputs, to the data memory as the data, a test pattern required to test the data memory, and which generates, from the test pattern, code information having an error checking function, and outputs the code information to the code memory as the ECC code.

1. Field of the Invention
The present invention generally relates to a semiconductor device, and in particular, to a semiconductor device with memories and a method for memory tests which tests the memory.
2. Description of the Related Art
In general, semiconductor storage devices include a built-in ECC circuit type storage device. "ECC" stands for "error correcting code" in some cases. In the present specification, "ECC" is used to mean "error checking and correcting." Both a data memory for storing data and a code memory for storing ECC codes are incorporated in the built-in ECC circuit type semiconductor storage device (refer to, for example, U.S. Pat. No. 6,295,617).
For such a semiconductor storage device, a method for memory tests is available which tests the memories utilizing a built-in test circuit and the ECC circuit (refer to, for example, Japanese Patent No. 2001-351398).
With the method for memory tests described in this prior art document, when a memory read speed is tested, a 1-bit inversion circuit is used to invert a predetermined bit in write data and in an ECC code. Then, the data containing the error bits is written in memory cells. Test conditions are set so that during a read, the ECC circuit checks and corrects the errors in the data.
With the conventional method for memory tests, both the data memory and the code memory must be tested. Thus, compared to tests on a single memory which are executed only on the data memory of the same capacity, the conventional method requires a longer time for the test process. Furthermore, test circuits are required which deal with the data memory and code memory, respectively. This increases test costs.

Semiconductor device with memory and method for memory test


In some embodiments a connector is to couple a peripheral, and a detector coupled to the connector is to detect if the peripheral is disconnected from the connector in response to a first reserved pin and a second reserved pin.

Theft of computer peripherals such as keyboards, mice, etc. is becoming a problem, particularly in some locations and in some types of use (for example, internet cafes). Some mechanical solutions exist to prevent keyboards from being stolen. However, such solutions do not include any alert signal to be sent to a console so that a supervisor is aware of the attempted theft. Further, if a thief cuts a mechanical cable the mechanical solutions are rendered useless and the theft is successful. No current electrical solutions exist to detect a state of connection and/or disconnection of a keyboard, particularly when the system is in an S5 power state.
Current solutions for theft prevention of a mouse include a mechanical solution and a smart contactless detection mechanism. The cost of both of these options is high, and neither allow for any alert to be sent or remote management to be implemented.

Detection of connection and disconnection of computer peripheral


Various examples are directed to systems and methods for network virtualization for web applications. For example, a WAN controller may receive from a backend query processor, a first tenant user query table that describes a first set of query types for a first user. The first set of query types may comprises a first query type having a first computational weight and a second query type having a second computational weight less than the first computational weight. The WAN controller may determine that a first network path to a web application data center is less congested that a second network path to the web application data center. The WAN controller may send a first flow entry to a first network appliance on the first network path instructing the first network appliance on the first network path to send packets associated with queries of the first set of query types to a second network appliance on the first network path.

Network virtualization is used to increase the configurability of network appliances, such as routers, switches, etc., that make up a computing network. Control plane components, often implemented in software, provide instructions to data plane components, such as hardware network appliances. The instructions provide the network appliances with rules for treating incoming packets.

Network virtualization for web application queries


A watering and transport device for plants, with a rectangular base platform, at each of the four corner regions of which is disposed, perpendicularly thereto, a support socket, in each of which is received a frame strut in a vertical position and provided with a longitudinal slot and insertion recesses, wherein the frame struts can be received in the support sockets either in a transport position or in a storage position, which is rotated by comparison thereto, and wherein a number of storage platforms are stacked one on top of the other the base platform, said storage platforms each having, in corner regions, a mounting member which has an insertion end portion ending freely, and wherein an upper rim portion of each support socket is located at such a height above the base platform that there is a vertical space between it and the insertion end portions of a bottom storage platform, so that the latter do not rest on the support sockets bearing a load.

Watering and transport devices for plants of the kind which are used, for example, for delivering and storing potted and garden plants in garden centers and similar sales outlets are known from, for example, DE 20213719. When devices of this kind are being transported (back) empty, the problem regularly arises as to how the numerous storage platforms on which the plants had been standing during shipment can now be housed in as compact and space-saving an arrangement as possible on the base platform or on the frame struts so that the best possible use is made of the available cargo space in the delivery vehicles used for this purpose, and so that this process can be conducted in as short a time as possible.
Conventionally, the method adopted for this is that the individual storage platforms are hung one on top of the other in the frame struts in as densely packed an arrangement as possible, i.e. so that a storage platform is hung in the insertion recesses of each individual level. This is very time-consuming and does not make the best possible use of the space which would actually be available in the vertical direction.
It is known per se from DE 28 00 575 C2 to insert the frame struts into the support sockets in a transport position, in which their longitudinal slots are facing each other, or inwards, i.e. in a position which is rotated by 180° compared to the storage position. In this position, a number of storage platforms can be stacked one after the other on the base platform from above, and it is no longer necessary to hang the insertion end portions in the insertion recesses, since they instead extend into/through the longitudinal slots and are received in a hollow space inside the frame struts. This leads to a saving of labor time both in creating the transport position (storage platforms are stacked on the base platform) and in the reverse procedure, in which the individual storage platforms have to be removed and are again hung in frame struts mounted on a base platform, which have of course previously been inserted the other way round or are located in the storage position. Nevertheless, this stacking method has never been used in practice, because the mounting members on the bottom storage platform in each case had to bear the entire weight of all the stacked storage platforms and could not take the load.
The invention is based on the object of making an improvement here and providing a watering and transport device for plants in which the storage platforms can be arranged for transport purposes more quickly and more closely packed than hitherto, and without the risk of damage.

Watering and transport device for plants


A method of forming a metal pattern includes disposing a gate metal layer on a substrate; disposing a photoresist layer on the gate metal layer; etching portions of the photoresist layer to form a first photo pattern; etching portions of the gate metal layer to form a gate pattern including a gate electrode, in which the gate metal layer is patterned using the first photo pattern as a mask; ashing an end portion of the first photo pattern to form a second photo pattern; disposing a first gate insulating layer over the substrate and the second photo pattern; removing the second photo pattern and a portion of the first gate insulating layer disposed over the second photo pattern; and disposing a second insulating layer over the gate pattern and the remaining portions of the first gate insulating layer.

1. Field
The following disclosure relates to a method of forming a metal pattern and a method of manufacturing a display substrate.
2. Discussion of the Background
Generally, a display substrate used in a display device includes a thin-film transistor ("TFT") as a switching element for driving a pixel region, a signal line connected to the TFT, and a pixel electrode. The signal line includes a gate line transmitting a gate driving signal and a data line crossing the gate line and transmitting a data driving signal.
As size of the display device is increased and customer demand for higher resolution is increased, a width of a gate pattern or a data pattern is decreased so that an electric resistance is increased. Thus, a resistance-capacitance ("RC") signal delay may occur, and the gate pattern or the data pattern may be formed from a metal having a relatively low resistance, and a thickness of the gate pattern or the data pattern may be increased in order to prevent the RC signal delay.
When a thickness of the gate pattern increases, a taper angle of the gate pattern may be increased. Thus, a crack of an insulating layer adjacent to the gate pattern may occur so that a quality of the display apparatus is poor.

Method of forming a metal pattern and method of manufacturing a display substrate


A mechanism for confining a flat flexible cable of an image scanner in position is provided. The flat flexible cable is electrically connected between a circuit board and a carriage and bends differentially with the movement of the carriage relative to the circuit board under a scanning platform. The mechanism includes a confining member disposed between a first portion of the flat flexible cable and the scanning platform for isolating the flat flexible cable from the scanning platform. The confining member changes states and bends differentially with the movement of the carriage relative to the circuit board under the scanning platform, and has a bending resistance greater than that of the flat flexible cable. Accordingly, the confining member is kept at least a certain clearance from the scanning platform while confining the first portion of the flat flexible cable thereunder.

The present invention relates to an anti-abrasive mechanism for use in a flatbed image scanner, and more particularly to a mechanism for avoiding abrasion by confining the flat flexible cable in position in the flatbed image scanner.
A flat flexible cable is a common connecting wire between electric devices. It is advantageous to be easily and reversibly bent and stretched in a narrow and crowded space. For example, in a flatbed image scanner, the moving-around carriage containing therein optical and photoelectric devices is connected with the circuit board through a flat flexible cable. Please refer to FIGS. 1(a) and 1(b) which are a top and a cross-sectional side views, respectively, schematically showing the arrangement of a flat flexible cable in a flatbed image scanner. The flatbed scanner includes an upper cover (not shown) and a lower housing 10. In the lower housing, a carriage 11 containing therein optical and photoelectric devices, a driving device 12 consisting of a motor and gear set 121 and a rail set 122, a circuit board 13 for processing electric signals received from the carriage 11, and a flat flexible cable 14 connecting the carriage 11 with the circuit board 13 are covered with a transparent scanning platform 15 for placing thereon the object to be scanned. The carriage 11 is moved by the motor and gear set 121 along the rail set 122 to pass by the scanned object, e.g. a document, film or picture, so as to realize the image data of the document or picture.
Please refer to FIG. 2(a), which is a schematic cross-sectional diagram showing the structure of a conventional flat flexible cable. The flat flexible cable 14 includes a flexible copper foil 141, an insulating wrapper 142 made of a flexible plastic, and a strengthening plate 143 made of a rigid plastic. The insulating wrapper 142 surrounds the copper foil 141 with two ends of the copper foil 141 exposed for electric contact with the carriage 11 and the circuit board 13, respectively. The strengthening plate 143 is mounted onto the end portion of the flat flexible cable 14 to facilitate the insertion of the exposed copper foil into the connecting slot (not shown) of the carriage 11 or the circuit board 13.
The configuration of the flat flexible cable 14 changes with the movement of the carriage 11 along a scanning direction. Before a scanning operation begins, the carriage 11 stands beside the circuit board 13 so that the flat flexible cable 14 is bent at around the middle point thereof. With the movement of the carriage 11 away from the circuit board 13, the bent point also advances. As is known to those skilled in the art, the flat flexible cable is made of light and flexible material such as plastic or rubber so that the bent portion ascends relative to the unbent portion due to the flexible property thereof. The bent portion may undesirably rise up to the inner surface of the platform 15 that is made of glass so as to be subject to abrasion. As shown in FIG. 2(b), abrasion is likely to occur in the bent portion due to the contact of the flat flexible cable 14 with the transparent platform 15. Especially for an image scanner having reduced thickness or using a contact image sensor (CIS) as an image pickup device which requires close contact with the document placed on the platform 15, the flat flexible cable 14 has great chance to keep in contact with the inner surface of the platform 15. The dropped chips resulting from the abrasion may smear the platform 15 and adversely affect the scanning quality.

This patent is subject to a terminal disclaimer.

Anti-abrasive mechanism confining flat flexible cable in position in flatbed image scanner


A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird's beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird's beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness.

1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices and methods of producing the same, and more particularly to a semiconductor integrated circuit device including a nonvolatile semiconductor storage device and using a plurality of supply voltages, and a method of producing such a semiconductor integrated circuit device.
A flash memory device is a nonvolatile semiconductor storage device that stores information in the form of electric charges in floating gate electrodes. The flash memory device, which has a simple device configuration, is suitable for forming a large-scale integrated circuit device.
In the flash memory device, information is written or erased by injecting hot carriers into and extracting hot carriers by the Fowler-Nordheim-type tunnel effect from the floating gate electrodes through a tunnel insulating film. Since a high voltage is required to generate such hot carriers, the flash memory device has a voltage rise control circuit that raises a supply voltage provided in its peripheral circuits cooperating with memory cells. Therefore, transistors used in such peripheral circuits have to operate at a high voltage.
On the other hand, it has been practiced of late to form such a flash memory device and a high-speed logic circuit on a common semiconductor substrate as a semiconductor integrated circuit device. In such a high-speed logic circuit, a transistor employed therein is required to operate at a low voltage. Therefore, such a semiconductor integrated circuit device is required to use a plurality of supply voltages.
2. Description of the Related Art
FIGS. 1A through 1Q are diagrams showing a production process of the conventional semiconductor integrated circuit device including such a flash memory and using a plurality of supply voltages.
In FIG. 1A, a flash memory cell region A, a low-voltage operation transistor region B, and a high-voltage operation transistor region C are formed in partitions on a silicon (Si) substrate 11 on which a field oxide film or an isolation structure (not shown in the drawing) such as a shallow trench isolation (STI) structure is formed. In the step of FIG. 1A, a tunnel oxide film 12A of a thickness of 8 to 10 nm is formed on the above-described regions A through C by performing thermal oxidation on the surface of the Si substrate 11 at temperatures ranging from 800 to 1100° C. In the step of FIG. 1B, an amorphous silicon film 13 doped with phosphorous (P) and having a thickness of 80 to 120 nm and an insulating film 14 having a so-called oxide-nitride-oxide (ONO) structure are successively deposited on the tunnel oxide film 12A. The ONO insulating film 14 is formed of a silicon dioxide (SiO2) film 14c of a thickness of 5 to 10 nm deposited by chemical vapor deposition (CVD) on the amorphous silicon film 13, a silicon nitride (SiN) film 14b of a thickness of 5 to 10 nm deposited by CVD on the SiO2 film 14c, and a thermal oxide film 14a of a thickness of 3 to 10 nm formed on the surface of the SiN film 14b. The ONO insulating film 14 has a good leakage-current characteristic.
Next, in the step of FIG. 1C, a resist pattern 15A is formed on the flash memory cell region A, and the ONO insulating film 14, the amorphous silicon film 13, and the tunnel oxide film 12A are removed from the low-voltage operation transistor region B and the high-voltage operation transistor region C on the Si substrate 11 by using the resist pattern 15A as a mask so that the surface of the Si substrate 11 is exposed in the regions B and C. In removing the tunnel oxide film 12A, wet etching using hydrofluoric acid (HF) is performed so that the surface of the Si substrate 11 is exposed to the HF in the regions B and C.
In the step of FIG. 1D, the resist pattern 15A is removed, and a thermal oxide film 12C of a thickness of 10 to 50 nm is formed in the regions B and C to cover the Si substrate 11 by performing thermal oxidation at temperatures ranging from 800 to 1100° C. The thermal oxide film 12C may be replaced by a thermal nitride oxide film.
In the step of FIG. 1E, another resist pattern 15B is formed in the flash memory cell region A to cover the ONO insulating film 14 and in the high-voltage operation transistor region C to cover the thermal oxide film 12C, and the thermal oxide film 12C is removed from the low-voltage operation transistor region B by HF processing by using the resist pattern 15B as a mask so that the surface of the Si substrate 11 is exposed in the region B. By the step of FIG. 1E, the surface of the Si substrate 11 is subjected to the second HF processing in the region B.
In the step of FIG. 1F, the resist pattern 15B is removed, and a thermal oxide film 12B of a thickness of 3 to 10 nm is formed on the exposed Si substrate 11 in the region B by performing thermal oxidation at temperatures ranging from 800 to 1100° C. The thermal oxide film 12B may be replaced by a thermal nitride oxide film. Further, in the step of FIG. 1F, as a result of the thermal oxidation for forming the thermal oxide film 12B, the thickness of the thermal oxide film 12C formed in the high-voltage operation transistor region C increases.
Next, in the step of FIG. 1G, an amorphous silicon film 16 doped with P and having a thickness of 100 to 250 nm is deposited on the structure of FIG. 1F by plasma CVD. The amorphous silicon film 16 may be replaced by a polysilicon film. Further, the amorphous silicon film 16 may be doped with P in a later step. In the step of FIG. 1H, a resist pattern 17A is formed on the amorphous silicon film 16, and by using the resist pattern 17A as a mask, patterning is performed successively on the amorphous silicon film 16, the ONO insulating film 14, and the amorphous silicon film 13 in the flash memory cell region A so that a multilayer gate electrode structure 16F of the flash memory which structure is formed of an amorphous silicon pattern 13A, an ONO pattern 14A, and an amorphous silicon pattern 16A and includes the amorphous silicon pattern 13A as a floating gate electrode is formed in the region A. In the step of FIG. 1G, it is possible to form a silicide film of, for instance, tungsten silicide (WSi) or cobalt silicide (CoSi) on the amorphous silicon film 16 as required. Further, it is also possible to form a non-doped polysilicon film and then form an n-type gate electrode of P or arsenic (As) or a p-type gate electrode of boron (B) or difluoroboron (BF2) in a later step of ion implantation.
Next, in the step of FIG. 1I, the resist pattern 17A is removed, and a new resist pattern 17B is formed to cover the flash memory cell region A. By using the resist pattern 17B as a mask, patterning is performed on the amorphous silicon film 16 in the low-voltage operation transistor region B and the high-voltage operation transistor region C so that a gate electrode 16B of a low-voltage operation transistor and a gate electrode 16C of a high-voltage operation transistor are formed in the regions B and C, respectively.
Next, in the step of FIG. 1J, the resist pattern 17B is removed, and a protection oxide film (also referred to as a protection insulating film or a thermal oxide film) 18 is formed, by performing thermal oxidation at temperatures ranging from 800 to 900° C., to cover each of the multilayer gate electrode structure 16F in the flash memory cell region A, the gate electrode 16B in the low-voltage operation transistor region B, and the gate electrode 16C in the high-voltage operation transistor region C.
Next, in the step of FIG. 1K, a resist pattern 19A is formed on the structure of FIG. 1J so as to cover the low-voltage operation transistor region B, the high-voltage operation transistor region C, and a part of the flash memory cell region A. By using the resist pattern 19A and the multilayer gate electrode structure 16F as masks, ion implantation of P+ is performed typically with a dose of 1×1014 to 3×1014 cm−2 at accelerating voltages ranging from 30 to 80 keV so that an n-type diffusion region 11a is formed next to the multilayer gate electrode structure 16F in the Si substrate 11. P+ may be replaced by As+.
In the step of FIG. 1K, by using the resist pattern 19A as a mask, ion implantation of As+ is performed typically with a dose of 1×1015 to 6×1015 cm−2 at accelerating voltages ranging from 30 to 50 keV so that another n-type diffusion region 11b is formed inside the n-type diffusion region 11a. In the step of FIG. 1K, no ion implantation is performed in the low-voltage operation transistor region B and the high-voltage operation transistor region C since the regions B and C are covered with the resist pattern 19A.
Next, in the step of FIG. 1L, the resist pattern 19A is removed, and a new resist pattern 19B is formed to cover the regions B and C and leave the region A exposed. Further, in the step of FIG. 1L, by using the resist pattern 19B as a mask, ion implantation of As+ is performed with a dose of 5×1014 to 5×1015 cm−2 at accelerating voltages ranging from 30 to 50 keV. As may be replaced by P+. As a result, an impurity concentration is increased in the n-type diffusion region 11b and at the same time, a yet another n-type diffusion region 11c is formed in the flash memory cell region A by using the multilayer gate electrode structure 16F as a self-alignment mask. At this point, the step of FIG. 1K may be deleted.
Next, in the step of FIG. 1M, the resist pattern 19B is removed, and a resist pattern 19C is formed on the Si substrate 11 so as to leave only the low-voltage operation transistor region B exposed. Further, in the step of FIG. 1M, ion implantation of a p-type or n-type impurity is performed by using the resist pattern 19C as a mask so that a pair of lightly doped drain (LDD) diffusion regions 11d are formed on both sides of the gate electrode 16B in the Si substrate 11 in the region B with the gate electrode 16B serving as a self-alignment mask.
Next, in the step of FIG. 1N, the resist pattern 19C is removed, and a resist pattern 19D is formed on the Si substrate 11 so as to leave only the high-voltage operation transistor region C exposed. Further, in the step of FIG. 1N, ion implantation of a p-type or n-type impurity element is performed by using the resist pattern 19D as a mask so that a pair of LDD diffusion regions 11e are formed on both sides of the gate electrode 16C in the Si substrate 11 in the region C. The diffusion regions 11d and 11e may be formed in the same step.
Further, in the step of FIG. 1O, sidewall insulating films 16s are formed on both sides of each of the multilayer gate electrode structure 16F, the gate electrode 16B, and the gate electrode 16C by depositing and performing etchback on a CVD oxide film. In the step of FIG. 1P, a resist pattern 19E is formed to cover the flash memory cell region A and leave the low-voltage operation transistor region B and the high-voltage operation transistor region C exposed. Further, by performing ion implantation of a p-type or n-type impurity element with the resist pattern 19E and the gate electrodes B and C serving as a mask, p-type or n-type diffusion regions 11f are formed on both sides of the gate electrode 16B in the Si substrate 11 in the region B, and similarly, p-type or n-type diffusion regions 11g are formed on both sides of the gate electrode 16C in the Si substrate 11 in the region C. A low-resistance silicide film of, for instance, WSi or CoSi may be formed as required on the surface of each of the diffusion regions 11f and 11g by silicide processing.
In the step of FIG. 1Q, an interlayer insulating film 20 is formed on the Si substrate 11 so as to continuously cover the regions A through C. Further, in the region A, contact holes are formed in the interlayer insulating film 20 so that the diffusion regions 11b and 11c are exposed, and W plugs 20A are formed in the contact holes. Likewise, in the region B, contact holes are formed in the interlayer insulating film 20 so that the diffusion regions 11f are exposed, and W plugs 20B are formed in the contact holes. In the region C, contact holes are formed in the interlayer insulating film 20 so that the diffusion regions 11g are exposed, and W plugs 20C are formed in the contact holes.
In the production process of the semiconductor integrated circuit device including the flash memory device having the multilayer gate electrode structure 16F, in the step of FIG. 1J, the protection oxide film 18 of a thickness of 5 to 10 nm is formed on the sidewall faces of the multilayer gate electrode structure 16F by thermal oxidation performed at temperatures ranging from 800 to 900° C. As a result of the thermal oxidation, the protection oxide film 18 is formed not only on the multilayer gate electrode structure 16F but also on the sidewall faces of each of the gate electrode 16B formed in the low-voltage operation transistor region B and the gate electrode 16C formed in the high-voltage operation transistor region C as shown in FIGS. 2A and 2B.
At this point, the protection oxide film 18 forms bird's beaks that penetrate under the gate electrode 16B in the region B as shown circled by broken lines in FIG. 2B. Therefore, especially in a low-voltage operation transistor whose gate length is short, that is, whose gate oxide film 12B is thin, a substantial change in the thickness of the gate oxide film 12B is effected right under the gate electrode 16B, thus causing a problem that a threshold characteristic shifts from a desired value.
Indeed, such a problem is prevented from occurring if the protection oxide film 18 is not formed. However, without formation of the protection oxide film 18, electrons retained in the amorphous silicon pattern 13A (hereinafter, also referred to as a floating gate electrode pattern 13A) are dissipated to the sidewall insulating films 16s formed by CVD and etchback in the step of FIG. 1O as shown in FIG. 3B so that information stored in the flash memory device is lost in a short period of time. On the other hand, with the protection oxide film 18 that is a high-quality thermal oxide film hardly allowing a leakage current being formed on the sidewalls of the floating gate electrode pattern 13A, the electrons injected into the floating gate electrode pattern 13A are stably retained therein as shown in FIG. 3A.
Therefore, it is essential to form the protection oxide film 18 in the semiconductor integrated circuit device including the flash memory device. However, formation of such a protection oxide film inevitably causes the problem of a change in the threshold characteristic of a MOS transistor forming a peripheral or logic circuit. Such a problem of a change in the threshold characteristic of the MOS transistor is noticeable when the MOS transistor is a high-speed transistor having a short gate length.
FIG. 4 is a plan view of a configuration of a flash memory cell (flash memory device) having a single-layer gate electrode structure by related art. In FIG. 4, the same element as those of the previous drawings are referred to by the same numerals, and a description thereof will be omitted.
According to FIG. 4, a device region 11A is formed on the Si substrate 11 by a field oxide film 11F. One end of the above-described floating gate electrode pattern 13A is formed on the Si substrate 11 to cross the device region 11A. In the device region 11A, by using the floating gate electrode pattern 13A as a self-alignment mask, the n−-type source region 11a and the n+-type source line region 11b are formed on one side, and the n+-type drain region 11c is formed on the other side.
On the Si substrate 11, another device region 11B is formed next to the device region 11A. An n+-type diffusion region 11C is formed in the device region 11B. The other end of the floating gate electrode pattern 13A is formed as a coupling part 13Ac covering the diffusion region 11C.
FIG. 5A is a sectional view of the flash memory cell of FIG. 4 taken along the line X-X′.
According to FIG. 5A, the tunnel oxide film 12A is formed between the source line region 11b and the drain region 11c on the Si substrate 11, and the floating gate electrode pattern 13A is formed on the tunnel oxide film 12A. Further, the n−-type source region 11a is formed outside the n+-type source line region 11b in the Si substrate 11. The sidewall insulating films 16s are formed on the sidewalls of the floating gate electrode pattern 13A.
FIG. 5B is a sectional view of the flash memory cell of FIG. 4 taken along the line Y-Y′.
According to FIG. 5B, the floating gate electrode pattern 13A continuously extends from the device region 11A to the adjacent device region 11B on the field oxide film 11F formed on the Si substrate 11. The coupling part 13Ac of the floating gate electrode pattern 13A is capacitive-coupled via an oxide film 12Ac to the high-density diffusion region 11C.
At the time of a write (program) operation, by providing the source line region 11b, applying a drain voltage of +5 V to the drain region 11c, and applying a write voltage of +10 V to the high-density diffusion region 11C as shown in FIGS. 6A and 6B, the potential of the floating gate electrode pattern 13A rises so that hot electrons are injected into the floating gate electrode pattern 13A via the tunnel oxide film 12A in the device region 11A.
On the other hand, at the time of an erase operation, an erase voltage of +15 V is applied to the source line region 11b with the drain region 11c and the high-density diffusion region 11C being grounded as shown in FIGS. 6C and 6D. As a result, the electrons in the floating gate electrode pattern 13A tunnel through the tunnel oxide film 12A to the source region 11a to be absorbed into a source power supply through the source line region 11b.
Thus, in the flash memory cell of FIG. 4, the high-density diffusion region 11C serves as a control gate electrode, and unlike the conventional flash memory cell of a multilayer gate structure, it is unnecessary to form the above-described ONO insulating film 14 between the polysilicon floating gate electrode and the polysilicon control gate electrode. In the flash memory cell of FIGS. 5A and 5B, the oxide film 12Ac serves as the ONO insulating film 14. Since the oxide film 12Ac is formed on the Si substrate 11 by thermal oxidation, the oxide film 12Ac has high quality.
FIGS. 7A through 7M are diagrams showing a production process of a semiconductor integrated circuit device including the flash memory cell of FIG. 4 in addition to the low-voltage operation transistor B and the high-voltage operation transistor C. In the drawings, the same elements as those previously described are referred to by the same numerals, and a description thereof will be omitted.
According to FIG. 7A, the thermal oxide film 12C of a thickness of 5 to 50 nm is formed on the Si substrate 11 by performing thermal oxidation at temperatures ranging from 800 to 1100° C. in each of the flash memory cell region A, the low-voltage operation transistor region B, and the high-voltage operation transistor region C. In the step of FIG. 15B, the thermal oxide film 12C is removed from the flash memory cell region A by a patterning process using a resist pattern 151.
Next, in the step of FIG. 7C, the resist pattern 151 is removed, and the tunnel oxide film 12A of a thickness of 5 to 15 nm is formed on the surface of the Si substrate 11 in the region A by performing thermal oxidation at temperatures ranging from 800 to 1100° C. In the step of FIG. 7C, as a result of the thermal oxidation for forming the tunnel oxide film 12A, the thermal oxide film 12C is developed in each of the regions B and C.
Next, in the step of FIG. 7D, the thermal oxide film 12C is removed from the low-voltage operation transistor region B by a patterning process using a resist pattern 152. Then, in the step of FIG. 7E, after the resist pattern 152 is removed, the thermal oxide film 12B of a thickness of 3 to 10 nm is formed on the exposed Si substrate 11 in the region B by performing thermal oxidation at temperatures ranging from 800 to 1100° C. In the step of FIG. 7E, as a result of the thermal oxidation for forming the thermal oxide film 12B, the tunnel oxide film 12A is developed in the region A and the thermal oxide film 12C is developed in the region C.
Next, in the step of FIG. 7F, the amorphous silicon film 13 uniformly doped with P and having a thickness of 150 to 200 nm is formed on the Si substrate 11. In the step of FIG. 7G, patterning is performed on the amorphous silicon film 13 with a resist pattern 171 serving as a mask, so that the floating gate electrode pattern 13A is formed in the flash memory cell region A, a gate electrode pattern 13B is formed in the low-voltage operation transistor region B, and a gate electrode pattern 13C is formed in the high-voltage operation transistor region C.
Next, in the step of FIG. 7H, the surfaces of the floating gate electrode pattern 13A and the gate electrode patterns 13B and 13C are covered with the protection oxide film 18 of a thickness of 5 to 10 nm by thermal oxidation at temperatures ranging from 800 to 900° C. Then, in the step of FIG. 7I, with a resist pattern 172 serving as a mask, the source region 11a is formed by performing ion implantation of P+ or As+ with a dose of 1×1014 to 5×1014 cm−2 at accelerating voltages ranging from 30 to 80 keV.
Further, in the step of FIG. 7J, with the regions B and C being covered with a resist pattern 173, ion implantation of As+ is performed with a dose of 5×1014 to 3×1015 cm−2 at accelerating voltages ranging from 30 to 50 keV in the region A by using the floating gate electrode pattern 13A as a self-alignment mask. Thereby, the n+-type source line region 11b is formed inside the source region 11a and the n+-type drain region 11c is formed on the opposite side of a channel region from the source region 11a.
Next, in the step of FIG. 7K, a resist pattern 173 covering the flash memory cell region A is formed, and the LDD regions 11d and 11e are formed in the regions B and C, respectively, by ion implantation of a p-type or n-type impurity element.
Further, in the step of FIG. 7L, the sidewall oxide films 16s are formed on both sidewalls of each of the floating gate electrode pattern 13A and the gate electrode patterns 13B and 13C. In the step of FIG. 7M, with the flash memory region A being covered with a resist pattern 174, the diffusion regions 11f and 11g are formed in the regions B and C, respectively, by ion implantation of a p-type or n-type impurity element.
Also in the production of the semiconductor integrated circuit device including the flash memory device of such a single-layer gate structure, when the thermal oxide film 18 is formed as a protection insulating film to cover the single-layer gate electrode structure (the floating gate electrode pattern) 13A in the flash memory cell region A as shown in detail in FIG. 8A in the step of FIG. 7H, the same thermal oxide film 18 is also formed in the low-voltage transistor region B so as to cover the gate electrode 13B as shown in FIG. 8B. As a result, bird's beaks that penetrate right under the gate electrode 13B are formed as shown circled in FIG. 8B. Therefore, the low-voltage operation transistor formed in the region B is prevented from having a desired threshold characteristic.

Semiconductor integrated circuit device and method of producing the same


A rotor core has a plurality of magnetic steel sheets laminated in an axial direction. Cooling passages extending in an axial direction are formed by aligning openings of the plurality of magnetic steel sheets. The cooling passages have axial direction passages that communicate at one end. A coolant inlet is then formed in one passage, and coolant outlets are formed in the other passages.

A rotation electrical machine, such as an electric motor or a generator, comprises a stator and a rotor, with power being output as a result of rotation of the rotor by supply of electrical power from outside, and generated electrical power being output by causing rotation of the rotor with power that is supplied from outside. With a permanent magnet motor, a plurality of permanent magnets are arranged on the rotor, a plurality of poles are formed, and the rotor is made to rotate by creating a rotating magnetic field by supplying electrical power to the stator.
Also, a rotor core is often constructed by laminating a plurality of magnetic steel sheets (also called electromagnetic steel sheets or electric steel sheets), and with a permanent magnet motor an opening is provided in each of the magnetic steel sheets, and by laminating so as to align position of the openings in the plurality of magnetic steel sheets that are being laminated a permanent magnet insertion hole is formed extending in the axial direction.
Further, a motor generates heat when it is driven. With a drive motor for an electric vehicle or hybrid vehicle or the like, the amount of that heat generation is significant, and the stator and rotor are cooled by circulating oil, for example, as a coolant.
In patent document 1, oil is supplied to a cooling passage that is provided inside a rotor core, via a cooling passage inside a drive shaft of a rotor. In patent document 1, it is disclosed to provide a cooling passage that passes from one end surface of a rotor core comprising laminated magnetic steel sheets to the other end surface, in an axial direction of the rotor core. It is possible to cool the whole of the rotor core by distributing oil in this type of cooling passage.


A cylinder with a speed control mechanism wherein in a transfer stroke, a piston is smoothly accelerated or smoothly decelerated at an initiation or termination end of the stroke by controlling the speed of the piston, whereas in a return stroke, the speed of the piston is not controlled, thereby reducing the time required for the return stroke. A bypass passage bypassing longitudinal grooves for flow control provided on a cushion ring (74) is formed in a passage which provides communication between the outside and a main passage or a cylinder chamber (71, 72). A check valve (78A, 78B) is disposed in the bypass passage to allow a fluid to flow through the bypass passage only during the return stroke of the piston (6).

The present invention relates to cylinders, for example, rodless cylinders, which are used to operate various machines. More particularly, the present invention relates to a cylinder with a speed control mechanism in which a piston is accelerated smoothly at an initiation end of a stroke thereof, or in which the piston is smoothly decelerated at a termination end of a stroke thereof.
Japanese Patent Application Unexamined Publication (KOKAI) No. 7-158614 discloses a rodless cylinder with a speed control mechanism. In the rodless cylinder, a piston is slidably fitted in a cylinder tube, and a head cover is secured to an end of the cylinder tube. A hollow cushion ring is disposed at the end of the cylinder tube such that the cushion ring can be inserted into a hollow portion of the piston. Sinusoidal grooves are formed on the outer surface of the cushion ring. The sinusoidal grooves are formed such that the depth thereof changes sinusoidally with respect to the longitudinal direction of the cushion ring. The sinusoidal grooves are deepest at the cushion approach side of the cushion ring. The rodless cylinder is arranged such that all of the fluid flowing between the inside and outside of the cylinder tube flows through an internal passage in the hollow cushion ring. The conventional rodless cylinder has the function of smoothly accelerating the piston at an initiation end of a stroke thereof, or the function of smoothly decelerating the piston at a termination end of a stroke thereof.


This disclosure describes systems and methods for a graphical interface including a graphical representation of medical data. The graphical interface platform may receive medical data and provide medical safety reporting capabilities including reporting of history data and real-time visual monitoring data. The graphical interface platform may be configured to identify potential problems and corrections to medical devices in operation while a reporting cycle is underway through visual representation of performance metrics.

Individual medical decision support platforms generally function independently without relying on performance optimizations derived from population specific data that is routinely collected. For example, decision support platforms may aggregate information into databases, but generally do not integrate the information or leverage knowledge gained to adapt and optimize therapy management rule sets and parameters to produce enhanced patient safety and patient outcomes.
A dashboard or user interface that adapts to user needs and provides information for treating patients in the presence of comparative analysis data with population performance under similar therapy rule sets and conditions may provide information useful to set alarms on outliers, and to flag outliers to staff for further investigation of inadequate response to therapy, for example.
Thus, an object of the present invention is the provision of a graphical user interface or dashboard system and methods that are useful to users or clinicians at various different levels in one or more healthcare facilities to monitor, manage and improve patient therapy conducted with electronic medical equipment.
This and other objects of the present invention will be apparent from the figures and the description that follows.

Systems and methods for a graphical interface including a graphical representation of medical data


Highly purified rare gas (helium, neon, argon, krypton, xenon, etc.) is obtained by removing impurities contained therein, such as nitrogen, hydrocarbon, carbon monoxide, carbon dioxide, oxygen, hydrogen and water, at relatively low temperatures by the use of a getter. This getter is a two-component alloy of zirconium and vanadium, or a multi-component alloy containing, as well as zirconium and vanadium, at least one of chromium, nickel and cobalt.

1. Field of the Invention
The present invention relates to a process for purification of rare gas. More particularly the present invention relates to a process for efficiently removing impurities contained in rare gases, such as helium, neon, argon, krypton and xenon, by the use of a getter metal to thereby purify the rare gas.
2. Description of Related Arts
Rare gases are usually purified by the use of a getter because they have similar chemical properties. Among rare gases, helium and argon are widely used in the semiconductor fabrication industry which has been greatly developing in recent years, and a higher gas purity is required. Moreover, neon, krypton and xenon are essential for production of special lamps, and they are often recycled after being used once, for reuse thereof, because they are very expensive. In this case, it is required that the recycled gas is highly purified by removing the impurities contained therein. Thus, it is desired that nitrogen, hydrocarbon, carbon monoxide, carbon dioxide, oxygen, hydrogen, water, etc., present in the ppm order in the rare gas be removed to the ppb order.
Among rare gases, argon is used in an extremely large amount and, therefore, purification of argon has been mainly under investigation. It is well known that technical information obtained by investigation of the purification of argon is also applicable to purification of other rare gases. There are two types of getters: a vaporization type in which barium, for example, is used, and a non-vaporization type in which titanium, zirconium or the like is used. For the purification of rare gas, the non-vaporization type of getter is usually employed.
Heretofore, as a purification method using the nonvaporization type of getter, there has been employed a method in which nitrogen, hydrocarbon, carbon monoxide, carbon dioxide, oxygen, hydrogen, water, etc., are removed by the use of titanium or a titanium-base alloy. In this method, since it is necessary to maintain the getter at a temperature as high as about 1,000.degree. C., materials for use in, for example, a purification cylinder are substantially limited to quartz, from a viewpoint of thermal resistance. Moreover, when the purification cylinder is used under pressure, there is the danger of it breaking; that is, there is a safety problem. For this reason, the number of purification apparatuses using titanium or a titanium alloy is decreasing, and attempts to develop a purification apparatus using zirconium or its alloy as the getter have been made. Use of zirconium or its alloy as the getter enables lowering the operating temperature of the purification apparatus to 400.degree. to 700.degree. C., and employing stainless steel, etc., for production of the purification apparatus, thereby producing the advantages that the danger of operation under pressure is eliminated and at the same time, an ability to remove hydrogen, which is barely removed at high temperatures, is increased
Japanese Patent Application Laid-Open No. 3008/1987 for example, discloses a Zr-V-Fe three-component alloy as a getter, and a purification apparatus using the threecomponent getter, which permits purification at lowered temperatures. However, since the three-component getter is relatively poor in its ability to remove impurities, specifically nitrogen and hydrocarbon, it has disadvantages in that the apparatus must be increased in size, a large space is needed for setting up the apparatus, and production costs of the apparatus are increased.
Japanese Patent Application Laid-Open No. 118045/1990 discloses a Zr-Al-V three-component alloy getter, and British Patent 1,370,208 discloses a Zr-Ti-Ni three-component alloy getter. These getters have a relatively high ability of removing hydrogen, but have a low ability of removing nitrogen.
Journal of the Less-Common Metals, Vol. 53, pp. 117-131 (1977) describes reversible hydrogen absorption characteristics of three component alloys represented by Zr(Co.sub.x, V.sub.1-x).sub.2 and Zr(Fe.sub.x, V.sub.1-x).sub.2, but there cannot be found any description about the getter action on other gases.
Moreover, as a two component-alloy getter, a Zr-Ti alloy is disclosed in U.S. Pat. No. 2,926,981. In the vicinity of 400.degree. C., the alloy has a higher rate of oxygen absorption than Zr or Ti alone, but it has a disadvantage of being low in absorption rate of other gases.
U.S. Pat. No. 4,071,335 proposes the use of a Zr-Ni alloy. Although the Zr-Ni alloy is excellent in the ability to remove hydrogen and water, its nitrogen removing ability is poor.
U.S. Pat. No. 4,306,887 describes Zr-Fe, which has a markedly poor ability to remove nitrogen.


A display apparatus including first and second light sources, gaze-tracking means, and processor(s) configured to: process gaze-tracking data to determine gaze direction; identify gaze region; determine first and second portions of gaze region; send, to rendering server, resolution information indicative of at least one of: gaze direction, gaze region, first and second portions of gaze region, different required resolutions of at least two input images; receive said input images comprising first input image(s) and second input image(s), from rendering server; process first input image(s) to generate first region of first output image and second region of second output image; process second input image(s) to generate remaining regions of first and second output images; and display first and second output images via first and second light sources.

In recent times, immersive technologies such as virtual-reality, augmented-reality, mixed-reality (collectively referred to as extended-reality (XR) technology) are being employed in various fields such as entertainment, real-estate, combat training, medical imaging operations, simulators, navigation, and the like. Notably, immersive technologies are employed in display apparatuses to provide immersive XR environments to a user. The display apparatus may include a head-mounted device (HMD) at which images corresponding to the XR environment are displayed, wherein the HMD receives rendering images constituting the XR environment from a rendering server.
Typically, there exist multiple display apparatuses for displaying XR environments. In a first instance, the display apparatus may employ a single-resolution display. In such instance, the XR environment provided by single-resolution images fails to provide an immersive experience to the user when the single-resolution images are displayed via the single-resolution display. In a second instance, multiple displays or projectors (per eye of the user) having a same resolution may be employed in the display apparatus to display images constituting the XR environment. However, the XR environment provided by the images displayed via the multiple displays or projectors is sub-optimal, as projections of the images are not properly optically combined and provide a disjointed visual scene of the XR environment. In a third instance, the display apparatus may employ fixed foveated displaying, such as at a multiresolution display or using projector(s) of the display apparatus. In such instance, a gaze direction of the user is assumed to be directed towards a central portion of a viewport of the display apparatus, wherein an image corresponding to the central portion of the viewport is rendered at a higher resolution than an image corresponding to a remaining portion of the viewport. Such display apparatus always present XR environments having high resolution in the central portion of the viewport and low resolution in the remaining portion of the viewport, which may not always be consistent with a manner in which the user's gaze can freely move around an entirety of the viewport. Such XR environment have limited realism.
Furthermore, rendering images constituting complex and realistic XR environments is computationally intensive and time-consuming. This causes excessive processing burden on the rendering server, especially when the images are required to be displayed at high frame rates and varying resolutions for providing a visually pleasing foveated XR environments to the user. Overburdening of the rendering server leads to an increase in rendering time and effort, which is detrimental to usability of both the rendering server and the display apparatus, and adversely impacts immersiveness and realism within the XR environment.
Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with existing display apparatuses for presenting XR environments to users.

Display apparatuses and methods incorporating foveated rendering


A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the memory hub. The controller communicates with the memory hubs by coupling optical signals to and from the memory hubs using an optical communication path, such as one or more optical waveguides. In one example of the invention, the memory modules transmit and receive optical signals having different wavelengths. In another example of the invention, the memory modules receive optical signals corresponding to memory command and address signals at different wavelengths, but they transmit and receive optical signals corresponding to memory commands at the same wavelength.

Memory modules are in common use in computer systems in the form of double in-line memory modules ("DIMMs"). An example of a conventional DIMM-type memory module 10 is shown in FIG. 1. The memory module 10 includes a circuit board substrate 14 on which several memory devices 20, typically dynamic random access memories ("DRAMs"), are mounted. In the DIMM-type memory module 10 shown in FIG. 1, 8 memory devices 20 are mounted on each side of the substrate 14. Terminals 24 are formed along an edge of the substrate 14, which mate with slotted connectors (not shown ) typically mounted on a computer system mother-board. The terminals 24 are electrically coupled to the power and signal terminals on the memory devices 20. The terminals 24 in the DIMM-type memory module 10 shown in FIG. 1 are on each side of the substrate 14. Also mounted on the substrate 14 may be a register 26 that stores command and address signals applied to the memory module 10 through the terminals 24 responsive to a clock signal that is also applied to the memory module 10 through the terminals 24. The register 26 then applies the command and address signals to the memory devices 20. Memory modules having a register 26 operating in this manner are known as "registered DRAM modules." However, it should be understood that memory modules often do not include the register 26, and they may include components in addition to those shown in FIG. 1.
As the speed of computer systems continues to increase, the operating speed of memory devices has increased in a corresponding manner. A portion of a computer system 30 shown in FIG. 2 includes three memory modules 10a,b,c coupled to a system controller 32 though a common data bus 34, address bus 36 and command bus 38. The system controller 32 initiates a memory operation by coupling a memory request in the form of a memory command and a memory address (generally in the form of a row address and a column address) to all of the memory modules 10 through the command bus 38 and the address bus 36, respectively. If the memory operation is a write operation, the system controller 32 will also couple write data to the memory modules 10 through the data bus 34. To prevent all of the memory modules 10 from responding to the memory request, the system controller 32 also generally applies a unique chip select or similar select signal to each of the memory modules 10. A unique select signal is thus applied to each of the memory modules 10 so that only the memory module 10 receiving the select signal responds to the memory request.
The bandwidth of data between the system controller 32 and the memory modules 10 could be increased by simultaneously accessing all of the 16 memory devices 20 (FIG. 1) in each of the modules 10. For example, if the 16 memory devices 20 included in the memory module 10 could be divided into 2 sets or "ranks" of 8 memory devices and both of the ranks could be accessed at the same time, data could be read from the ranks at a rate that is 2 times faster than the rate at which data can be read from each rank of the memory devices 20. Unfortunately, data can be accessed in conventional memory modules 10 only one rank of 6 memory devices 20 at a time. As the operating speed of memory devices continue to increase, the bandwidth of data coupled from the memory modules 10 threatens to be limited by the bandwidth of the data bus 34 coupled between the system controller 32 and the memory modules 10.
Another factor that limits the operating speed of computer systems using the system controller 32 coupled to the memory modules 10 through the buses 34–38 is the need to allow for a settling time between writing data to a memory module 10 and reading data from a memory module 10. When the system controller 32 outputs data to the memory modules, the data signals are reflected from various locations, such as the junction between the data bus 34 and terminals 24 (FIG. 1) on the substrates 14 of the modules 10. Therefore, signal induced noise is present on the data bus for a considerable period after data have been written to the memory modules 10. Signal induced noise is generated on the data bus for the same reason in a read operation when one of the memory modules 10 couples data onto the data bus 34 for transfer to the system controller 32. This noise must be allowed to settle before data are subsequently written to or read from the memory modules 10 or else the noise may be mistakenly interpreted as read or write data. The need to provide for a settling time can markedly reduce the effective memory bandwidth of computer systems and other devices using memory modules.
There is therefore a need for a computer system architecture and memory module that permits a higher bandwidth of data transfer to and from memory modules and that does not require settling times between a memory accesses.

Wavelength division multiplexed memory module, memory system and method


Variable speed drive to be connected to a rotating driving shaft (5) and to a rotating driven shaft (6) includes at least two angled bearings (7, 7'), controller for controlling the orientation of the axis (13, 13') of each angled bearing (7, 7') adapted so that the axes are offset from one another, and transmission (9,9', 11, 11') adapted so that in each phase of the movement at least one of the angled bearings (7, 7') engages and at least one of the bearings (7, 7') does not engage. The controller is adapted to alter the slant of all the angled bearings (7, 7') on the basis of a signal for controlling the variation in the variable speed drive ratio.

The invention relates to a variable speed drive to be connected between a rotating driving shaft and a rotating driven shaft and allowing a continuous variation of the transmission ratio between these two shafts.
Different implementations of variable speed drives have already been described, comprising intermediate alternating movements of variable amplitude which determine the transmission ratio.
FR-A-1.133.080 describes a variable drive comprising connecting rod/crank systems having torsion bar and freewheel. FR-A-2.125.083 describes a variable speed drive comprising a series of peripheral assemblies which oscillate by action of a cam and are coupled by freewheels to a driven shaft. The transmission ratio depends on the amplitude of the cyclic movement of the peripheral assemblies which themselves depend upon the eccentricity of the cam. Also, FR-A-2.200.933 describes a variable drive having variable ratio straight gears functioning as a square wave generator, the variation of the amplitudes of the square waves causing the variation in the transmission ratio.
Moreover, drives are known which comprise an angled bearing allowing the generation of intermediate alternating movements transmitted onto a driven shaft by a freewheels mechanism (see, for example, FR-A-2.538.532).
Nevertheless, and in spite of the age of these documents, the different devices that they describe have not been usable, in practice, because of their low performance. Indeed, in addition to the large losses caused by the many moving elements, their design theory has the consequence that the engendered alternating movements do not have the shape of continuous successive square signals. It is, therefore, necessary to associate a hydraulic coupling and/or a flywheel to the variable drive, which causes the assembly to be oversized. Moreover, the movements of the variable drive generate strong vibrations. Moreover, with these known variable drives, the transmission of an engine brake is not possible.
Also, the movements carried out at high frequency engender fatigue and vibration problems which are not taken into account in known variable drives. Also, the mechanical play of the moving elements accumulate, further reducing performances, functioning precision, and the behavior over time of these variable drives, notably for the variable drive described in FR-A-2.200.330.
Equally, the control of the functioning and in load of the variation in amplitude inducing the variation of the transmission ratio and, more generally, the control of the various functioning modes of the conventional variable drives, present problems which are not fully resolved. Indeed, these controls must be carried out with hydraulic control units which are expensive, complex, bulky and which consume a large amount of energy.

Variable speed drive having intermediate alternating movements


A nitride semiconductor laser device has a semiconductor multi-layer structure that includes a lower clad layer of a first conductive type, an active layer, and an upper clad layer of a second conductive type stacked in this order on a substrate, wherein a layer under the active layer includes a stripe-like trench; the semiconductor multi-layer structure includes a stripe-like optical cavity arranged along the stripe-like trench; the stripe-like trench has a narrower width in its both end regions compared to its central main region; and the active layer is formed of a nitride semiconductor containing In.

1. Field of the Invention
The present invention relates to a high-power-output semiconductor laser device, and particularly to a high-power-output nitride semiconductor laser device that is unlikely to cause catastrophic optical damage (COD) in both end mirror parts of its optical cavity and a method of producing the same.
2. Description of the Background Art
A semiconductor laser device operating at high power output has a limited lifetime until it causes a malfunction. The most common malfunction in the high-power-output semiconductor laser device is catastrophic optical damage (COD) in both end mirror parts of the optical cavity.
A mirror part of an optical cavity of a semiconductor laser device includes a high density of non-radiative recombination centers which act as non-radiative recombination sites for carriers. Non-radiative recombination current generates heat. Besides, a relatively low density of carriers near the mirror part cause absorption of laser light. Heat generated by both the non-radiative recombination current and light absorption causes a temperature rise of the mirror part. When the semiconductor temperature rises, its energy band gap decreases. The band gap reduction acts to promote further light absorption. Such increased light absorption may cause a runaway process damaging the mirror part of the laser device under high-power-output operation, which may result in a malfunction of the laser device.
In order to alleviate such an output power limitation, various kinds of laser structures have been proposed. One example is known as a NAM (non-absorbing mirror) structure. In order to achieve this structure, the energy band gap of the active layer in a laser device is made larger in a region near the mirror than in other regions by utilizing diffusion of impurities, ion implantation of impurities, or epitaxial re-growth. A laser device having this NAM structure is able to operate at an output power that is greater by about one order of magnitude compared to conventional laser devices.
However, there are various limitations in such methods of producing the NAM structure as described in published documents. For example, both of the methods disclosed in U.S. Pat. Nos. 4,983,541 and U.S. Pat. No. 5,113,405 are inconvenient methods, each of which needs two-step epitaxial growth. While U.S. Pat. No. 5,395,793 discloses a method of utilizing low energy ion implantation so as to cause a distribution of defects inside a layer above a quantum well layer, it is necessary that part of the defects is diffused downward and mixed with the quantum well by heating subsequent to the ion implantation.

Nitride semiconductor laser device and method of producing the same


Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. During programming, a temporary lockout mode is provided for memory cells which pass a verify test. During a checkpoint program-verify iteration, all memory cells of a target data state are subject to the verify test. The memory cells in the temporary lockout mode are therefore subject to the verify test a second time. Memory cells that fail the verify test in the checkpoint program-verify iteration are programmed further. A normal or slow programming mode is used for a memory cell depending on whether it had reached the temporary lockout mode. Threshold voltage distributions are narrowed by reprogramming some of the memory cells.

The present technology relates to techniques for programming memory cells.
Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory structure sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from a stack of alternating conductive and dielectric layers. A memory hole is formed in the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory hole with materials including a charge-trapping layer. A straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a bottom back gate. Control gates of the memory cells are provided by the conductive layers. However, various challenges are presented in operating such memory devices.

Efficient reprogramming method for tightening a threshold voltage distribution in a memory device


The invention is an agitator configuration for a floor care appliance such as an upright vacuum cleaner. The floor care appliance is provided with at least two agitator chambers each having at least one rotary agitator member disposed therein. In the preferred embodiment of the present invention, a vacuum cleaner suction nozzle is provided with symmetric left and right agitator disposed adjacent one another. A front agitator assembly comprised of a left and right agitator half-section is disposed in the left and right agitator chambers, respectively. A rear agitator is located rearward of the front agitator assembly and is also comprised of a left and right agitator half-section disposed in the left and right agitator chambers, respectively. A plurality of brush members extend from each agitator half-section arranged in a helical pattern around the circumference of each of the agitator-half-sections. The left and right agitator half-sections of the front agitator assembly have opposite helical patterns so that a “chevron” pattern is formed from the front agitator assembly. The “chevron” brush pattern sweeps dirt particles from the center of the suction nozzle along the front of the cleaner toward the suction nozzle's outer edges. Similarly, the left and right agitator half-sections of the rear agitator assembly have opposite helical patterns so that a “chevron” pattern is formed from the rear agitator assembly. The “chevron” brush pattern sweeps dirt particles from the center of the suction nozzle along the rear edge of the suction nozzle toward the suction nozzle's outer edges.

1. Field of the Invention
This invention relates to an agitator configuration for a vacuum cleaner and, more specifically, to a vacuum cleaner having at least two agitator chambers each having at least one rotary agitator member disposed therein.
2. Summary of the Prior Art
Upright vacuum cleaners are well known in the art. Typically, these upright vacuum cleaners include a vacuum cleaner housing pivotally mounted to a vacuum cleaner foot. The foot is formed with a nozzle opening and may include an agitator mounted therein for loosening dirt and debris from a floor surface. A motor may be mounted to either the foot or the housing for producing suction at the nozzle opening. The suction at the nozzle opening picks up the loosened dirt and debris and produces a stream of dirt-laden air which is ducted to the vacuum cleaner housing.
It is known in U.S. Pat. No. 5,513,418, owned by a common assignee, to provide forward and rearwardly disposed suction ducts that extend along the front and back sides of a suction nozzle to lead suction air to a rearwardly extending fan communicating duct. It is also known from this patent to make an outer covering piece of a communicating duct portion extending between the front and back sides of the suction nozzle removable. It is also known from this patent to make the agitator tunnel an inner structure in its nozzle. It is also generally known to provide a hood structure which either sits on its underbody or obviously overlaps it.
However, while the foregoing suction nozzle arrangement in the '418 patent has produced satisfactory results and has been commercially successful, consumer demand has forced floor care appliance and vacuum cleaner designers to design floor care appliances and vacuum cleaners with additional features and/or performance. The present invention fulfills this need by providing a vacuum cleaner having an improved suction nozzle configuration comprised of front and rear rotary agitators, twin agitator chambers, separate air paths extending from the agitator chambers, and suction ducts disposed along the front or rear edges, or both, of the agitator chambers.
Accordingly, it is an object of the invention to provide an improved agitator configuration for a floor care appliance.
It is another object of the invention to provide an improved agitator configuration for a floor care appliance having at least two agitator chambers and at least one rotary agitator member disposed therein.
It is yet another object of the invention to provide an improved agitator configuration for a floor care appliance having at least two agitator chambers and at least one rotary agitator member disposed therein wherein the rotary agitator member is removable.


A surge chamber assembly (70) for use in a wellbore includes a housing (80) having one or more openings (112), a surge chamber (100) and a combustion chamber (98). The openings (112) provide fluid communication between the exterior (82) of the housing (80) and the surge chamber (100). A sleeve (114) is slidably positioned within the housing (80) and has a first position wherein fluid communication through the openings (112) is prevented and a second position wherein fluid communication through the openings (112) is allowed. A combustible element (124) is positioned in the combustion chamber (98) such that combusting the combustible element (124) generates pressure in the combustion chamber (98) that actuates the sleeve (114) from the first position to the second position.

Without limiting the scope of the present invention, its background will be described with reference to perforating a subterranean formation using shaped charge perforating guns, as an example.
After drilling the various sections of a subterranean wellbore that traverses a formation, individual lengths of relatively large diameter metal tubulars are typically secured together to form a casing string that is positioned within the wellbore. This casing string increases the integrity of the wellbore and provides a path for producing fluids from the producing intervals to the surface. Conventionally, the casing string is cemented within the wellbore. To produce fluids into the casing string, hydraulic openings or perforations must be made through the casing string, the cement and a short distance into the formation.
Typically, these perforations are created by detonating a series of shaped charges that are disposed within the casing string and are positioned adjacent to the formation. Specifically, one or more charge carriers or perforating guns are loaded with shaped charges that are connected with a detonator via a detonating cord. The charge carriers are then connected within a tool string that is lowered into the cased wellbore at the end of a tubing string, wireline, slick line, coil tubing or other conveyance. Once the charge carriers are properly positioned in the wellbore such that the shaped charges are adjacent to the formation to be perforated, the shaped charges may be fired. If more than one downhole zone is to be perforated, a select fire perforating gun assembly may be used such that once the first zone is perforated, subsequent zones may be perforated by repositioning and firing the previously unfired shaped charges without tripping out of the well.
The perforating operation may be conducted in an overbalanced pressure condition, wherein the pressure in the wellbore is greater than the pressure in the formation or in an underbalanced pressure condition, wherein the pressure in the wellbore is less than the pressure in the formation. When perforating occurs in an underbalanced pressure condition, formation fluids flow into the wellbore immediately after the casing is perforated. This inflow is beneficial as perforating generates debris from the perforating guns, the casing and the cement that may otherwise remain in the perforation tunnels and impair the productivity of the formation. As clean perforations are essential to a good perforating job, perforating underbalanced condition is preferred. It has been found, however, that due to safety concerns, maintaining an overbalanced pressure condition during most well completion operations is preferred. For example, if the perforating guns were to malfunction and prematurely initiate creating communication paths to a formation, the overbalanced pressure condition will help to prevent any uncontrolled fluid flow to the surface.
A need has therefore arisen for an apparatus and method for perforating a cased wellbore that create effective perforation tunnels. A need has also arisen for such and apparatus and method that provide for safe installation and operation procedures. Further, a need has arisen for such an apparatus and method that provide for the reuse of certain of the perforating string components.

Surge chamber assembly and method for perforating in dynamic underbalanced conditions


A network device of an optical network terminal (ONT) includes an optical communication interface, an input interface, a memory and a processor. Wherein the optical communication interface transmits optical signals with adjusted transmission power; the input interface is used to input a distance; the memory stores a plurality of distances, and a plurality of databases respectively correspond to the distances; the processor electrically connects to the optical communication interface, input interface and the memory, and is used to access the database in the memory corresponding to the inputted distance, and then adjust the transmission power of the optical communication interface according to the content in the database. In addition, a method of adjusting the power of optical signals is further provided in this invention.

1. Field of the Invention
The present invention relates generally to optical network devices, and more particularly to a network device of an optical network terminal (ONT) and a method of adjusting power of optical signals.
2. Description of the Related Art
For the development of transmission technology through network, optical transmission is replacing the traditional electrical transmission. Gigabits passive optical network (GPON) has been widely applied in network structures to provide high speed transmission and to broaden the bandwidth.
The GPON system includes an optical line terminal (OLT) at the service provider's central office (CO) and a plurality of optical network terminals (ONTs) near end users. OLT transmits downstream and upstream signals between CO and ONTs.
However, the distance between each ONT and the OLT depends, and ONT always transmits optical signals with fixed transmission power. Therefore, for those ONTs set at far, the transmission power may be insufficient, so that the transmission may be incomplete or erroneous. On the contrary, for the transmission between the OLT and those ONTs set near, the transmission power may be too high to cause waste of energy, shorter lifespan of transmission units, and higher cost for maintenance.
The drawbacks described above are unavoidable, as long as the distances between the ONTs and the OLT are different.

Network device of optical network terminal and method of adjusting power of optical signals


A grounding mechanism for an electrical appliance is provided. The electrical appliance includes an electrical plug configured for connection to an electrical ground, a chassis, an electrical component, and the grounding mechanism. The chassis is connected to the electrical plug to ground the chassis when the electrical plug is connected to the electrical ground. The grounding mechanism includes a conducting plate mounted to the chassis, a non-conducting fastener, and a grounding element. The conducting plate is in electrical contact with the electrical component to provide a ground to the electrical component. The non-conducting fastener mounts the conducting plate to the chassis such that the conducting plate is not in electrical contact with the chassis. The grounding element is mounted to the chassis from an exterior of the chassis to place the conducting plate in electrical contact with the chassis to provide the electrical ground to the electrical component.

As with many consumer products electrical appliances are subject to rules, regulations, and laws which attempt to ensure product quality and user safety. For example, UL 858 is a set of safety standards which apply to electrically operated household cooking appliances such as cooktops, ovens, stoves, ranges, etc. According to UL 858, a household cooking appliance must pass a high potential voltage test prior to being sold to a consumer. The high potential voltage test has to be conducted after the household cooking appliance is fully assembled. Unfortunately, implementing the high potential test can be problematic because many cooking appliances include electrical components which are designed to prevent voltages which fall in the range of the test.
For example, many modern cooking appliances include one or more metal oxide varistors (MOVs) on their power supplies to suppress high voltage transients which can occur during power surges, lightning storms, etc. To protect the cooking appliance and its user, the MOVs prevent high input voltages such as those in the range of the required high potential test. Cooking appliance manufacturers address this problem by disconnecting the MOVs from a constant earth ground to which the rest of the cooking appliance is connected. Without the constant earth ground, the MOVs are able to float such that an apparent voltage differential caused by the high potential input is minimal. In traditional cooking appliances, connecting and/or disconnecting the MOVs to the electrical ground requires that the cooking appliance be disassembled.
Thus, implementing a simple high potential test can require that the cooking appliance be assembled and disassembled multiple times. For example, the cooking appliance manufacturer has to fully assemble the cooking appliance with the MOV(s) disconnected perform the high potential test by sending a voltage through the electrical appliance, disassemble the cooking appliance, manually connect the MOV(s) to the electrical ground connected to the rest of the cooking appliance, and reassemble the cooking appliance, all prior to packaging the cooking appliance. This process is laborious and time consuming and results in lost revenue for the cooking appliance manufacturer,
Thus, there is a need for an electrical appliance which includes an external grounding mechanism such that an MOV or other electrical component can be connected to and/or disconnected from an electrical ground without disassembling the electrical appliance.

External ground connection for an electrical appliance