A multi-layer type semiconductor device is disclosed, in which a plurality of semiconductor layers are formed in vertically opposite directions. The multi-layer type semiconductor device is obtained by forming a first semiconductor layer, an insulating layer and a second semiconductor layer in the mentioned order on a main surface of a first substrate, forming a semiconductor device by using the second semiconductor layer as a base, with an exposed surface thereof directed upward, forming an insulating film on the semiconductor device, attaching a second substrate to the insulating film, thinning the first substrate to expose the first semiconductor layer, and forming a further semiconductor device by using the first semiconductor layer as a base, with an exposed surface of the first semiconductor layer directed upward. A single-chip type image forming system or sensing system may be provided by employing, as the semiconductor devices, a sensing device such as a photosensor, a pressure sensor or the like, a processing circuit for processing a signal received from the sensor, and a display device for displaying results of the processing. A large number of pads may be provided by arranging the pads on opposite surfaces of a chip.

1. Field of the Invention
This invention relates to multi-layer type semiconductor devices, and more particularly to multi-layer type semiconductor devices having semiconductor element layers stacked in opposite directions. This invention relates also to methods of manufacturing such multi-layer type semiconductor devices. The invention has particular application in the field of image processing system fabricated on a single common multiple layer integrated circuit.
2. Description of the Background Art
An ordinary integrated circuit is formed on a surface of a wafer and has, so to speak, a two-dimensional structure. As distinct from this, an integrated circuit including a plurality of semiconductor layers having semiconductor elements and stacked one upon another is called a three-dimensional integrated circuit. Because of the multi-layer structure, the three-dimensional integrated circuit has the advantage of realizing a very high degree of integration and greatly improved functions.
Generally, the three-dimensional integrated circuit includes semiconductor layers and insulating layers stacked alternately, with each semiconductor layer having active elements formed therein. With the integrated circuit having active elements formed in the respective semiconductor layers formed on the insulating layers, the elements have only a small excess capacity, and hence a further advantage of enabling high speed operation of these elements.
The technique of forming semiconductor layers, particularly silicon layers, on insulating layers will be described next.
The technique of providing a structure in which silicon layers are formed on insulating layers is known as SOI (Silicon On Insulator) technique. A silicon layer formed on an insulating layer is called an SOI layer, and a structure having silicon layers formed on insulating layers an SOI structure. Such a technique is described, for example, in an article titled "Silicon-on-Insulator; Its Technology and Applications" edited by S. Furukawa and published by KTK Scientific Publishes in 1985.
As SOI techniques, methods are known which utilize epitaxy. These methods include a liquid phase epitaxy method such as a melting recrystallization method in which a polycrystalline or amorphous semiconductor layer formed on an insulating layer is exposed to and melted by energy light such as a laser beam, an electron beam or the like, and is thereafter allowed to solidify, a solid phase epitaxy method which causes an amorphous semiconductor layer to grow in solid phase, and a vapor phase epitaxy method which utilizes graphoepitaxy or bridging epitaxy. However, since these methods cause silicon crystals to grow on an insulating layer, it is difficult to obtain a single-crystal layer over a large area and to control film thickness compared with the case of causing silicon crystals to grow epitaxially on a single-crystal layer.
As a technique of obtaining the SOI structure, SIMOX (Separation by Implanted Oxygen) is known. SIMOX is a method of obtaining a structure having mutually separated semiconductor layers, in which ions such as of oxygen are injected in high concentration into a semiconductor layer to form a buried insulating layer. With this method, however, it is difficult to obtain a multi-layer structure, which makes this method hardly applicable for manufacture of a three-dimensional integrated circuit.
As another technique of obtaining the SOI structure, a wafer direct bonding method is known. Such a method is presented, for example, in "APPLICATIONS OF THE SILICON WAFER DIRECT-BONDING TECHNIQUE TO ELECTRON DEVICES" by K. Furukawa et al. in 1989 Applied Surface Science 41/42 at pp. 627-632. In the wafer direct bonding method, a wafer having an insulating layer formed on a surface thereof is superposed by a single-crystal wafer or a wafer having a single-crystal layer, and the two wafers are heat-treated (annealed) in an atmosphere of 600.degree. to 1,000.degree. C. The heat treatment induces an interatomic junction over containing surfaces, thereby bonding the wafers together. Then the upper wafer is thinned, to complete a semiconductor layer formed on the insulating layer. The semiconductor layer obtained on the insulating layer by the wafer direct bonding method is, by origin, a product of epitaxy formed on a single-crystal silicon substrate. Thus, this semiconductor layer has an excellent crystalline property and a uniform film thickness, to be suitable for manufacture of a three-dimensional integrated circuit.
A multi-layer type semiconductor device manufactured by the above wafer direct bonding method and forming the background of this invention will be described next.
FIGS. 24A through 24K are sectional views showing a process of manufacturing the multi-layer type semiconductor device forming the background of this invention.
Referring to FIG. 24A, a first silicon wafer 101a having a thickness of 500 to 600 .mu.m includes an insulating layer 102 formed 1,000 to 10,000.ANG. thick on a surface region thereof. A second silicon wafer 101b having a thickness corresponding to that of the first silicon wafer 101a includes, formed on a surface region thereof, a boron-injected layer 103a with boron injected thereinto in a high concentration on the order of 1.times.10.sup.20 /cm.sup.3 and a low concentration epitaxial layer 104a having a thickness of about 5,000.ANG.. Boron-injected layer 103 is used as etchant stopper for a subsequent process. The epitaxial layer 104a is obtained by causing silicon crystals to grow epitaxially on the single-crystal substrate 101b.
Referring to FIG. 24B, the two wafers 101a and 101b are placed in superposition with the insulating layer 102 and epitaxial layer 104a opposed so each other, and are heat-treated in an atmosphere of about 800.degree. C. This heat treatment is called annealing. The annealing induces an interatomic junction over contacting surfaces, which bonds the two wafers 101a and 101b together. Next, an upper surface of one of the wafers 101b is coarsely polished until its thickness is reduced to 100 .mu.m. Thereafter the wafer 101b is finely etched with a mixed liquid of hydrofluoric acid and nitric acid until its thickness is reduced to 10 .mu.m.
Next, the wafer 101b is etched with an aqueous solution of ethylenediamine and pyrocatechol. The etching step using this aqueous solution is carried out at a rate of 1 .mu.m/min. for semiconductor regions having a low concentration of boron, whereas the etching processes at a rate of 20.ANG./min. for regions the higher boron concentration. Consequently, the etching action stops at the high concentration boron-injected layer 103a. Thus, as shown in FIG. 24C, the water 101b is removed except the high concentration boron-injected layer 103a and epitaxial layer 104a. Next, to form semiconductor elements, the boron-injected layer 103a is etched away, and a surface thereby exposed is oxidized which is followed by a step of etching away an oxide film. This leaves a thin SOI layer 104a having a thickness on the order of 1,000.ANG..
Referring to FIG. 24D next, the field oxide layers 105a are formed by LOCOS (Local Oxidation of Silicon) in regions of the SOI layer 104a which are to serve as isolation regions.
Referring to FIG. 24E next, a gate insulating film 107a is formed by oxidation of the SOI layer 104, and a polysilicon layer is formed on the gate insulator film 107a. This polysilicon layer is patterned into a shape of a gate electrode 106a. Next, impurities are applied by ion implantation using the gate electrode 106a as a mask to form source and drain regions 108a.
Referring to FIG. 24F next, an interlayer insulating film 109a is formed over the entire surface, and contact holes 110 are formed through the interlayer insulating film 109a.
Referring to FIG. 24G next, refractory metal interconnections 111 a reformed as electrically connected to the source and drain regions 108a and extending onto the interlayer insulating films 109a. The gate electrode 106a, gate insulator film 107a and source and drain regions 108a constitute a transistor. Next, an insulating layer 112 is formed over the interlayer insulating film 109a and refractory metal interconnections 111.
Referring to FIG. 24H next, the insulating layer 112 is flattened for the purpose of superposition. Thereafter the flattened insulating layer 112 is superposed by a third silicon wafer 101c including a high concentration boron-injected layer 103b and an epitaxial layer 104b as does the second silicon wafer 101b. The two wafers are annealed in an atmosphere of about 800.degree. C., whereby the wafers are bonded together through surfaces of the insulating layer 112 and epitaxial layer 104b as shown in FIG. 24I.
Next, as described hereinbefore, the wafer 101c is thinned by polishing and by etching with the mixed liquid of hydrofluoric acid and nitric acid. Further, the wafer 101c is etched with the aqueous solution of ethylenediamine and pyrocatechol. Consequently, as shown in FIG. 24J, the wafer 101c is removed except the high concentration boron-injected layer 103b and epitaxial layer 104b. The epitaxial layer 104b of the third silicon wafer 101c is used as a second SOI layer. Subsequently, to form semiconductor elements, the boron-injected layer 103a is etched away.
Referring to FIG. 24K next, field oxide layers 105b, a gate insulator film 107b, a gate electrode 106b, source and drain regions 108b, an interlayer insulating film 109b, and metal interconnections 113 comprising aluminum or an aluminum alloy are formed by using the second SOI layer 104b as a base, as described with reference to FIGS. 24D and 24E. The gate electrode 106b, gate insulator film 107b and source and drain regions 108b constitute a transistor. In this way, a first active layer L1 is formed on the semiconductor substrate 101a through the insulating layer 102, and a second active layer L2 on the first active layer L1 through the insulating layer 112. The transistor of the first active layer L1 and that of the second active layer L2 are electrically interconnected, as necessary, by conductors mounted in through holes 114.
The multi-layer type semiconductor device manufactured by the above method employs a refractory metal, instead of aluminum, for the metal interconnections of the first active layer. This is because the metal interconnections are exposed to the high temperature when the two wafers are bonded by annealing as shown in FIG. 24I. Thus, if a third active layer is formed on the second active layer, the aluminum interconnections of the second active layer L2 are replaced with the refractory metal interconnections.
In the foregoing multi-layer type semiconductor device, the active layers are stacked in a fixed directions on the basis of a surface of the semiconductor substrate. If a large number of layers are stacked, a distortion due to the fixed stacking direction becomes apparent, giving rise to the problems of fluctuating a threshold voltage and increasing leakage.
Further, since the active layers are stacked on only one surface of the substrate, the active layer close to the substrate is heated more frequently than the active layer or layers farther away from the substrate and, therefore, is required to have a better heat-resisting property.
An image process system employing the multi-layer type semiconductor device manufactured by the foregoing method will be described next. This image processing system includes a photodetecting portion for receiving light from an object, and a display portion for displaying a received optical signal as an image.
In such an image processing system, generally, the photodetecting portion and display portion are formed separately for the following reason. It is necessary for photodetecting elements to receive light from outside, and for display elements to be visible from outside. The two types of elements must, therefore, be formed in or adjacent outwardly exposed positions. If the multi-layer semiconductor device 10 shown in FIG. 24K is applied to the image processing system, since the display elements and photodetecting elements are formed on one side of the substrate, the substrate must be transparent and the display elements are formed closest to the substrate and the photodetecting elements remotest therefrom, or, conversely, the photodetecting elements are formed closest to the substrate and the display elements remotest therefrom. Since the previously formed active layers are heated every time a new active layer is formed, the active layer close to the substrate is heated more frequently than the active layer or layers farther away from the substrate. Thus, a material having a poor heat-resisting property cannot be used for the layer close to the substrate.
If, for example, a sensor comprising an amorphous material were formed in the layer close to the substrate, this sensor would be inoperable since the amorphous material would become crystallized as a result of the long heat treatment. If a sensor comprising a pn junction were formed in the layer close to the substrate, the position of junction in the pn junction would shift or would extend deep into the semiconductor layer as a result of the long heat treatment, thereby lowering the light absorption efficiency of the sensor. Further, a liquid crystal display formed adjacent the substrate would have the liquid crystal destroyed by the heat.
In order to avoid the above setbacks, a possible consideration is that, for example, an active layer including display elements is formed on one surface of the substrate, and an active layer including sensor elements is formed on the other surface thereof. However, this construction would require through holes to be formed in the thick substrate in order to electrically interconnect the active layers formed on the opposite surfaces of the substrate. Since it is difficult to form a plurality of through holes in the substrate, this method cannot be applied to the above system which requires a high degree of integration. Thus, it is very difficult to apply the multi-layer type semiconductor device with the SOI layers stacked only on one surface of the substrate to an image processing system having a photodetecting portion and a display portion formed on a single chip. Generally, therefore, as shown in FIG. 25, a photodetecting portion 20 and a display portion 30 are fabricated separately and are electrically interconnected through leads 15.
In FIG. 25, the photodetecting portion 20 includes a substrate 201, an insulating layer 202 formed on the substrate 201 for forming an SOI layer, a three-dimensional integrated circuit 215 formed on the insulating layer 202 and having a processing circuit for processing an electric signal based on the light received by the photodetecting portion 20 and a memory circuit for storing data for comparison with the electric signal, a photoelectric sensor 216 having a photodiodes arranged in matrix form, and an output circuit 217 having output pads. The three-dimensional integrated circuit 215 includes active layers L1, L2 . . . Ln forming, individually or in combination, circuits having independent functions, and signals are communicated among the layers via through holes. The display portion 30 includes a substrate 301, a switching circuit 318 having electrodes for driving a liquid crystal display, an input circuit 317 having input pads, a liquid crystal 319, a resin member 320 for sealing the liquid crystal, and a window 321.
In the image processing system shown in FIG. 25, the photoelectric sensor 216 of the photodetecting portion 20 receives light traveling in the direction of arrow A from an object, and converts it into an electric signal. This electric signal is electrically processed by the three-dimensional integrated circuit 215 for contour extraction and highlighting, pattern recognition and the like. This electric signal is transferred from the output pads 217 of the output circuit such as a shift register through the leads 15 to the input pads 317 of the display portion 30. In the display portion 30, the liquid crystal 319 is driven in response to the signal transferred, to display a figure such as of contour lines. The displayed figure is visible through the window 321 in the direction of arrow B.
A method of manufacturing the photodetecting portion and display portion of the image processing system shown in FIG. 25 will be described in outline next.
Referring to FIG. 26A, the photodetecting portion is manufactured by forming the three-dimensional integrated circuit 215, which carries out image processing, on the insulating layer 202 superposed on the silicon substrate 201 in the same way as described with reference to FIGS. 24A through 24K. Referring next to FIG. 26B, the photoelectric sensor 216 and the output circuit 217 having the output pads are formed on the three-dimensional integrated circuit 215.
Referring to FIGS. 26C and 26D, the display portion is manufactured by forming, on the substrate 301, the switching circuit 318 having the electrodes for driving the liquid crystal display, and the input circuit 317 having the input pads. Then the resin member 320 for sealing the liquid crystal is mounted in position, and the transparent window 321 is attached to the resin member 320. Subsequently, pressure in a gap between the switching circuit 318 and window 321 is reduced to introduce the liquid crystal 319 therein.
A sensing system employing the foregoing multi-layer type semiconductor device having the three-dimensional integrated circuit will be described next. This sensing system includes a sensor provided at an input side for detecting light, pressure, temperature or radiation, and light emitting elements such as light emitting diodes at an output side for displaying sensing results. Such a sensing system is shown in FIG. 27.
In FIG. 27, a sensor portion 40 includes a substrate 401, an insulating an SOI layer, a three-dimensional integrated circuit 415 formed of a plurality of active layers L1, L2 . . . Ln and having a processing circuit for processing information detected by the sensor portion 40, and an output circuit 417 having output pads. An output portion 50 includes a substrate 501, display elements 522 which are red, green and blue light emitting diodes arranged in matrix form, and an input circuit 517 having input pads.
This sensing system is manufactured by the following method. As shown in FIG. 28A, the insulating layer 402 is formed on the substrate 401, and the three-dimensional integrated circuit 415 is formed on the insulating layer 402. Then, as shown in FIG. 28B, the sensor 416 and the output circuit 417 having the output pads formed.
As shown in FIGS. 28C and 28D, the display elements 522 which are the light emitting diodes arranged in matrix form, and the input circuit 517 having the input pads are formed on the substrate 501. Next, the output pads 417 and input pads 517 are interconnected by leads 15. This completes the sensing system having a sensing function and a displaying function.
The foregoing image processing system or sensing system may be classified broadly into two types by a difference in displaying mode.
The first type, as shown in FIG. 29, has a photodetecting portion 20 and a display portion 30 formed of materials penetrable to light, and a transmitted image of an object 25 to be detected and an image based on results of processing are superimposed when seen by the naked eye 35. The transmitted image herein refers to an image of the object 25 visible through the photodetecting portion 20 and display portion 30, and the image based on results of processing refers to an image displayed on a liquid crystal 319. With this type of system, a precise positional adjustment between the photodetecting portion 20 and display portion 30 is necessary for the transmitted image and the image based on results of processing to be seen in perfect register.
In the second type, as shown in FIGS. 30 and 31, only the image displayed on the display portion 30 or 50 can be seen by the naked eye 35. This type of system provides no transmitted image of the object 25.
FIG. 30 shows a system employing the liquid crystal 319 as the display device, while FIG. 31 shows a system employing the light emitting element 522. Particularly where the signal processing function of the three-dimensional integrated circuit 215 or 415 is jeopardized by external light or light from the object 25, a light shielding film 224 or 424 is inserted between the sensor 216 or 416 and three-dimensional integrated circuit 215 or 415.
The second type of system using a liquid crystal as the display device may be further classified into the reflection type and the transmission type. As shown in FIG. 30, the reflection type includes a reflecting film provided on a rear surface of the liquid crystal 319 to give a display by light reflected from the reflecting film on the rear surface of the liquid crystal 319. As shown in FIG. 32, the transmission type includes a light source 323 disposed behind the liquid crystal 319 to give a display by transmitted light passing through the liquid crystal 319. The reflection type shown in FIG. 30 employs a material having high reflectance, such as a silicon substrate, as the substrate 301a of the display portion 30.
The transmission type shown in FIG. 32 employs a transparent substrate as the substrate 301b of the display portion 30, and includes a light emitter 323 outwardly of the transparent substrate 301b. However, in this case too, the light from the light emitter 323 will enter the three-dimensional integrated circuit 215 to jeopardize its signal processing function if a substrate 201b and an insulating layer 202b are penetrable to light. In order to avoid such trouble, it is necessary to provide a light shielding plate 324 between the light emitter 323 and photodetecting portion 20 as shown in FIG. 33, or to employ a light shielding material as the substrate 201c of the photodetecting portion 20.
Where the signal processing function of the three-dimensional integrated circuit 215 is jeopardized by external light or light from the object 25, a light shielding film 224 or 424 must be inserted between the sensor layer 216 and three-dimensional integrated circuit 215 as in the systems shown in FIGS. 30 and 31.
Further, where the foregoing liquid crystal display device is employed, there is a disadvantage of enlarging the system configuration since it is necessary to incorporate a light emitter.
The image processing system or sensing system employing the multi-layer type semiconductor device with active layers stacked only on one surface of a semiconductor substrate, as described above, has the sensor portion and display portion fabricated on separate chips, which results in the following disadvantage. There are a serial transmission system and a parallel transmission system for transferring signals between the two chips. A transfer of the signals in serial transmission is time-consuming and makes real-time processing impossible. A parallel transfer of the signals necessitates numerous input and output pads to be provided on each chip, which inevitably leads to an increased chip area.
The manner in which the input and output pads of the multi-layer type semiconductor device forming the background of this invention are arranged will be described next.
FIG. 34A is a plan view of the multi-layer type semiconductor device, FIG. 34B is a bottom view thereof, and FIG. 34C is a section taken on line 34C-34C of FIG. 34A. As shown in FIG. 34A through 34C, pads 617a and 617b are provided only on one side of the multi-layer type semiconductor device 60, with no pads provided on the other side.
As shown in FIG. 34C, a first active layer 615a is formed on a substrate 601a, and a second active layer 615b is formed on the first active layer 615a through an insulating layer 612. The first active layer 615a and second active layer 615b include electric circuits serving the purpose for which the semiconductor device 60 is intended. The electric circuit in the first active layer 615a and the electric circuit in the second active layer 615b are electrically interconnected by conductors mounted in through holes 614b. Refractory metal interconnections 611 are led out of the electric circuit formed in the first active layer 615a. Pads 617a are formed on the insulating layer 612, and aluminum interconnections 613a extend from the pads 617a. These interconnections 613a are electrically connected to the refractory metal interconnections 611 by conductors mounted in through holes 614a. Aluminum interconnections 613b are led out of the electric circuit formed in the second active layer 615b. These aluminum interconnections 613b are electrically connected to pads 617b formed on the insulating layer 612.
Of the pads arranged around the electric circuit 615b shown in FIG. 34A, the outer pads 617a correspond to the first active layer 615a and the inner pads 617b to the second active layer 615b. Pads 617b are used, for example, as input pads while pads 617a are used, for example, as output pads. In this case, signals input through the pads 617b are processed by the two-layer electric circuits 615b and 615a and output through pads 617a.
FIGS. 35A through 35E are sectional views illustrating a method of manufacturing the multi-layer type semiconductor device 60 shown in FIGS. 34A and 34C. The method of manufacturing the multi-layer type semiconductor device will be described next with reference to FIGS. 35A through 35E.
Referring to FIGS. 35A and 35B, the first active layer 615a is formed on the substrate 601a by the method shown in FIGS. 24A through 24G. The substrate comprises a semiconductor substrate or quartz. Next, an electric circuit comprising semiconductor elements if formed in the active layer 615a, and the refractory metal interconnections 611 are formed as electrically connected to the electric circuit.
Referring to FIG. 35C next, the insulating layer 612 is formed over an entire surface of the substrate 601a, which is then flattened.
Referring to FIG. 35D next, a substrate 601b having an epitaxial layer 604 formed on one side thereof is superposed on the insulating layer 612, and the substrate 601a and 601b are bonded together by annealing in an atmosphere of about 800.degree. C. Thereafter, the substrate 601b is thinned down to expose the epitaxial layer 604 by the same method as described with reference to FIG. 24I.
Referring to FIG. 35E next, the second active layer 615b is formed on the epitaxial layer 604 acting as the base, an electric circuit comprising semiconductor elements if formed on the active layer 615b, and the electric circuits of the first and second active layers are interconnected via through holes 614b formed in the insulating layer 612. On the insulating layer 612 are formed the aluminum interconnections 613b electrically connected to the electric circuit of the second active layer, and the pads 617b electrically connected to the aluminum interconnections 613b. Further, on the insulating layer 612 are formed the pads 617a, and aluminum interconnections 613a electrically connected to the pads 617a and electrically connected via the through holes 614a to the interconnections 611.
As described above, the multi-layer type semiconductor device forming the background of this invention has the pads formed only on one surface of a chip. Thus, there is a problem of having to enlarge the chip area when providing a large number of pads.
The multi-layer type semiconductor device forming the background of this invention, because the SOI layers or active layers are stacked in a fixed direction, has various disadvantages as follows:
(1) Where a large number of layers are stacked, a distortion due to the stacking in a fixed direction, that is, stacking from only one side of the substrate becomes apparent, which results in fluctuations of a threshold voltage and an increase in leakage.
(2) A possible consideration is that, where necessary, SOI layers stacked in a fixed direction are formed on one surface of a substrate, and an active layer or layers are formed on the other surface thereof, the latter being electrically connected to the elements formed in the SOI layers. However, it is difficult to form a plurality of through holes in the thick substrate.
(3) In a system comprising a photodetecting portion or sensor portion and a display portion, the stacked SOI layers must include a sensor layer and a display layer located closest to and remotest from the substrate. It is, therefore, difficult to realize an image processing system or a sensing system formed on a single chip.
(4) That the sensor portion and display portion must be formed on separate chips entails the following disadvantages. It is difficult to transfer a large amount of data at high speed. A positional adjustment must be effected in order to place an object detected and an image displayed in register, Furthermore, the device per se has a large configuration.
(5) Since the input and output pads are formed only on one surface of the substrate, an increase in the number of input and output pads results in a large chip configuration.

Method of forming a multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions


A high frequency surgery generator having an output circuit and a power oscillator for generating an HF output voltage. The power oscillator is designed to excite the output circuit at a first excitation frequency, which corresponds to a resonant frequency of the output circuit, in a first operating mode and to excite the output circuit at a second excitation frequency which differs from the first excitation frequency, which does not correspond to the resonant frequency of the output circuit, in a second operating mode.

These days, electrosurgery is used in many medical fields. In the process, a relatively high voltage, which is applied to a monopolar or bipolar electrode, is used to damage or cut biological tissue in a targeted manner. In order to produce these voltages, use is usually made of an electrosurgical generator (RF surgical generator).
Different types of modulation are used for cutting and/or coagulating the biological tissue. To this end, e.g. bursts must have a quick beginning and end.
EP 1 776 929 A1 describes an electrosurgical generator in which the output voltage of the RF surgical generator can quickly be reduced. In the process, if a threshold is exceeded, the output voltage of the RF surgical generator is quickly reduced by virtue of converting the energy from the power supply unit into heat by connecting an additional load component. A disadvantage of this is that the generated heat needs to be dissipated and that the RF surgical generator is technically complex and has poor cutting properties.
DE 102 18 895 A1 describes a further electrosurgical generator, wherein the output voltage of the electrosurgical generator can quickly be reduced. Here, the output voltage of the power supply unit is reduced by virtue of feeding the output capacitor energy back to the DC voltage supply. As a result, the energy stores on the output side of the DC voltage supply and in the power oscillator are quickly discharged. As a result of this, the output voltage of the electrosurgical generator is quickly reduced. A disadvantage of this is that the electrosurgical generator offers poor cutting properties and the circuit is complicated and technically complex.
US 2004/0193148 A1 describes an electrosurgical generator in which surges in the output voltage of the RF surgical generator can quickly be regulated down. In this case, the resonant frequency of the oscillator is modified by the addition of further components as soon as the output voltage of the RF surgical generator lies above a limit voltage. As a result, the unchanging excitation frequency no longer corresponds to the resonant frequency of the oscillator, as a result of which the output voltage of the RF surgical generator is reduced below the limit voltage, i.e. to the level of a normal output voltage, and sparking is prevented. It is disadvantageous in this case that the circuit is technically complex and sparking, which is advantageous for cutting, is prevented and hence the RF surgical generator offers poor cutting properties.


A method for post lithographic critical dimension shrinking of a patterned semiconductor feature includes forming an overcoat layer over a patterned photoresist layer, and removing portions of the overcoat layer initially formed over top surfaces of the patterned photoresist layer. The remaining portions of the overcoat layer on sidewalls of said patterned photoresist layer are reacted so as to chemically bind the remaining portions of the overcoat layer on the sidewalls.

The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a method for post lithographic critical dimension shrinking including post overcoat planarization.
The fabrication of integrated circuits on a semiconductor substrate typically includes multiple photolithography steps. A photolithography process begins by applying a thin layer of a photoresist material to the substrate surface. The photoresist is then exposed through a photolithography exposure tool to a radiation source that changes the solubility of the photoresist at areas exposed to the radiation. The photolithography exposure tool typically includes transparent regions that do not interact with the exposing radiation and a patterned material or materials that do interact with the exposing radiation, either to block it or to shift its phase.
As each successive generation of integrated circuits crowds more circuit elements onto the semiconductor substrate, it becomes necessary to reduce the size of the features, i.e., the lines and spaces that make up the circuit elements. The minimum feature size that can be accurately produced on a substrate is limited by the ability of the fabrication process to form an undistorted optical image of the mask pattern onto the substrate, by the chemical and physical interaction of the photoresist with the developer, and by the uniformity of the subsequent process (e.g., etching or diffusion) that uses the patterned photoresist.
Advanced lithography for formation of structures such as contact holes has become increasingly reliant on "shrink" methods in which a contact hole is imaged at a critical dimension (CD) larger than the target dimension, and is thereafter reduced to the target dimension through some post-lithography process. Many different processes are under development/exploration by resist vendors, as well as device manufacturers, using a wide range of techniques including reflow, etch tapering in intermediate layers, and overcoats that bind to the existing pattern with finite thickness. Although no clear front-runner has emerged in this relatively immature technology field, overcoat-based techniques offer certain fundamental advantages among litho-based techniques. More specifically, they offer the least opportunity for uncontrolled distortion of the lithographic image during the shrink (as compared to purely thermal reflow processes, for example) and have the best potential to offer consistent CD shrinks within the contact, regardless of pattern density.
Overcoat based chemical shrinks typically rely on an interaction with the already imaged resist material, wherein a new film is spin cast such that both materials fill in and overcoat the previously imaged material with a finite thickness. For example, in some common schemes, residual acid in the resist is used to catalyze a reaction with the overcoat material that crosslinks a controlled thickness of the overcoat both within the contact hole and on top of the resist surface. However, while this effect works relatively well along a straight edge, the diffusion behavior is much less ideal around a sharp corner of the feature. It is well known that degradation around top corners of lithographically imaged features contributes to uncontrolled variation in subsequent etch processing. Accordingly, it would be desirable to be able to improve this type of shrink process for corner features.

Method for post lithographic critical dimension shrinking using post overcoat planarization

International Business Machines Corporation


A micro-tip is manufactured by forming a recess portion on a first substrate consisting of monocrystalline silicon for forming a tip. A peeling layer is formed on the recess portion, and contact layer is formed on at least a portion other than the peeling layer on the substrate. A tip material layer is formed on the peeling layer and the contact layer. The tip material layer on the peeling layer is transferred onto a second substrate.

1. Field of the Invention
The present invention relates to a method of manufacturing a micro-tip used in a scanning tunneling microscope, an atomic force microscope for detecting a very weak force, or the like and a female mold substrate used in the manufacture of the micro-tip, and a method of manufacturing a probe having the micro-tip and the probe and, more particularly, to a method of manufacturing a micro-tip, that allows mass production of a tip, which has a small curvature at its distal end, exhibits excellent characteristics in the above-mentioned application, and can realize a multi-tip structure.
2. Related Background Art
In recent years, a scanning tunneling microscope (to be abbreviated as an "STM" hereinafter) that allows direct observation of the electron structures of atoms on conductor surfaces has been developed (G. Binnig et al., Phys. Rev. Lett., 49, 57 (1983)), and a real space image can be measured at a high resolution independently of single-crystal or amorphous materials. Such STM utilizes a tunneling current that flows across a metal tip and a conductive material when a voltage is applied across them and the tip is brought close to a distance of about 1 nm to the conductive material.
This current is very sensitive to a change in distance between the tip and the conductive material, and changes exponentially. Hence, by scanning the tip to maintain a constant tunneling current, the surface structure of a real space can be observed at a resolution on the atomic order.
Objects that can be analyzed using the STM are limited to conductive materials. However, recently, the STM is often applied to structural analysis of a thin insulating layer formed on the surface of a conductive material.
Furthermore, the above-mentioned device and means allow observation of a medium with low electric power without damaging it since they use a method of detecting a very weak current.
Since the STM can operate in air, extensive studies have been made for its applications to various fields such as observation/evaluation and micropatterning of semiconductors or polymers on the atomic or molecular order (E. E. Ehrichs, Proceedings of 4th International Conference on Scanning Tunneling Microscopy/Spectroscopy, "89, S13-3), an information recording/reproduction apparatus, and the like, using the STM technique.
For example, upon applying the STM to an information recording/reproduction apparatus, the distal end portion of a tip of the STM preferably has a small radius of curvature to attain a high recording density.
At the same time, in view of improvement in function, especially an increase in speed of the recording/reproduction system, it is proposed to simultaneously drive a large number of probes (multi-tip structure). For this purpose, however, tips having uniform characteristics must be manufactured on a single substrate.
An atomic force microscope (to be abbreviated as an "AFM" hereinafter) can measure a three-dimensional pattern image on the specimen surface independently of conductors or insulators since it can detect a repulsive force or attractive force acting on the surface of a substance.
The AFM uses a micro-tip formed on the free end of a thin-film cantilever. As in the STM, in order to increase the resolution of the AFM, the distal end portion of the tip is required to have a small radius of curvature.
As a conventional method of forming the above-mentioned micro-tip, a micro-tip formed by anisotropic etching of monocrystalline silicon using a semiconductor manufacturing process is known (U.S. Pat. No. 5,221,415). In the method of forming a micro-tip, as shown in FIG. 1, a pit 518 is formed by anisotropic etching on a silicon wafer 514 coated with silicon dioxide masks 510 and 512, and is used as a female mold of a tip. After the silicon dioxide masks 510 and 512 are removed, the two surfaces of the wafer 514 are coated with silicon nitride layers 520 and 521 to form a pyramid-shaped pit 522 which is to serve as a cantilever and a micro-tip. After the pit 522 is patterned into a cantilever shape, the silicon nitride layer 521 on the rear surface is removed. Then, a glass plate 530 with a SAW-cut 534 and a Cr layer 532 is joined to the silicon nitride layer 520. Thereafter, the silicon wafer 514 is removed by etching, thus manufacturing a probe which is transferred to a mounting block 540 and is constituted by the silicon nitride tip and the cantilever.
Finally, a metal film 542 serving as a reflection film for an optical lever type AFM is formed.
Also, the following methods are available. That is, in another manufacturing method, as shown in (a) in FIG. 2, a thin film layer on a silicon substrate 611 is patterned into a circular shape, the silicon is etched using the patterned thin film layer as a mask 612, and a tip 613 is formed by utilizing side etching (O. Wolter, et al., "Micromachined silicon sensors for scanning force microscopy", J. Vac. Sci. Technol. B9(2), Mar/Apr, 1991, pp. 1353-1357). In still another manufacturing method, as shown in (b) in FIG. 2, a conductive material 625 is obliquely deposited onto a substrate 621 via a reverse-tapered resist aperture portion 624 of a resist film 622 while rotating the substrate 621, and is lifted off (C. A. Spindt, et al., "Physical properties of thin film field emission cathode with molybdenum cones", J. Appl. Phys., 47, 1976, pp 5248-5263).
However, the conventional micro-tip manufacturing method suffers the following problems.
For example, the conventional micro-tip manufacturing method shown in FIG. 1 suffers the following problems.
(1) Since the silicon substrate used as a female mold of a tip is removed by etching in a later process, it cannot be re-used, resulting in low productivity and high manufacturing cost.
(2) Since the silicon substrate used as a female mold of a tip is etched, deterioration of the tip material and the tip shape on the probe surface due to an etchant, and contamination from the etchant occur.
(3) When a tip for the STM is manufactured by coating the tip surface with a conductive material, since the tip is formed to have a sharp distal end, it is not easy to form a coating of the conductive material. When the tip surface is coated with the conductive material, grain clots of the conductive film appear, and it is difficult to control the grain clots with high reproducibility. In the STM that processes a very weak current, i.e., a tunneling current, it is difficult to obtain stable characteristics.
(4) Furthermore, when a micro-tip is formed on a thin-film cantilever, a reflection film is formed on the entire rear surface of a probe in an AFM, and the cantilever warps due to the film stress of the reflection film.
The conventional micro-tip manufacturing method shown in FIG. 2 suffers the following problem.
(5) Strict process management is required to make constant the etching condition for silicon upon forming a tip, the patterning condition for a resist, the deposition condition of a conductive material, and it is difficult to maintain accurate shapes such as the heights, the radii of curvature of distal ends, and the like of a plurality of micro-tips to be formed.

Method of manufacturing micro-tip and female mold substrate therefor, and method of manufacturing probe with micro-tip and the probe


An apparatus and process for increasing the concentric bearing load capabilities of the length of liner is disclosed. Overlapping ends of vertically aligned pipe lengths are joined by a coupling which provides aligned throughholes through the respective pipe ends. A cylindrical liner having a length substantially equal to co-lengths of an individual pipe member is positioned such that a series of throughholes passing through an approximate mid-length portion of the liner are positioned opposite to and aligned with the pipe coupling throughholes. Fasteners are then used to secure the two vertically aligned overlapping pipe ends to the interior liner pipe.

This invention relates generally to foundation support brackets. Buildings often experience foundation settling attributable to loose or sandy soil present around the foundation, overly moist soil, and/or improper construction of the foundation.
It is known in the art to use embedded earth anchors and brackets as a means of supporting foundations. Typically, a screw anchor is positioned beneath a foundation using a torque drive. Respective anchors are positioned at a depth sufficient to support the load of the building structure so as to avoid further settlement of either the screw anchors or the foundation.
The number of screw anchors and foundation supports attached thereto generally correlate to the amount of force needed to support the foundation. Underpinning a foundation using foundation anchors and support brackets is costly in terms of the time and materials needed to install the requisite number of anchors and attached foundation brackets. Any ability to increase the load capabilities of the foundation support apparatus can result in substantial savings of materials and labor by reducing the number of foundation supports needed to shore the foundation. Heretofore, screw anchors were driven by a torque into below ground positions using lengths of square tubing or cylindrical pipe as connectors. As the helical screw is driven further into the foundation subsoil, lengths of tubing or pipe are attached via overlapping ends until the desired depth is obtained. The concentric load bearing capabilities of the tubing or pipe are often the determining factor in the amount of load bearing capability for any single helical anchor and attached bracket. Accordingly, there remains room for improvement and variation within the art in terms of an apparatus and process for increasing the concentric load bearing capabilities of a foundation anchoring system.

Concentric load bearing piping with liner for foundation anchor


The present invention is a method and apparatus for overdriving signals received by a sense amplifier circuit. To this end, an overdrive circuit comprising an n-channel common source switch drives the signal to be sensed for a period of time to a voltage level greater than a normal level. The period of time the signal is overdriven corresponds to the operating voltage of the sense amplifier circuit. Upon completion of the overdriving, a normalization circuit drives the signal to be sensed for a second period of time to the normal level, thereby preparing it for the next memory cycle so that the signals can be once again set to the desired precharge level.

The invention relates generally to semiconductor circuit design and, more particularly, to a method and apparatus for a memory sensing circuit with a constant delay-time.
Digital logic requires input and output signals to meet defined voltage levels to be interpreted as either "high" or "low." However, typical integrated circuits, or "chips," utilizing digital logic also include signals at many voltage levels. As a result, sense amplifying circuits are utilized to interpret, or "separate," the signals, driving them to either a high or low voltage level, thereby producing the correct voltage level for other digital circuits on the chip. For example, a capacitor-type memory cell for a dynamic random access memory ("DRAM") device utilizes very small bit signals. Sense amplifier circuits residing on the DRAM device separate the bit signals by comparing them to a precharge level, which is defined as a level between the high and low levels of the memory cell. If the level of the bit signal is above the precharge level, then the sense amplifier circuit interprets the signal as a high, or logic 1, signal. If the level of the bit signal is below the precharge level, then the sense amplifier circuit interprets the signal as a low, or logic 0, signal.
As technology progresses, the speed and accuracy of the signal separation performed by sense amplifier circuits becomes more critical. For this reason, chip designers have tried various methods to speed up the signal separation. For example, U.S. Pat. No. 5,257,232 to Dhong et al., teaches a method of overdriving sense amplifier circuits to speed up the signal separation. Although this method succeeds in separating the signals quickly, it has drawbacks. One such drawback is that the overdriving is inaccurate because when the sensing is complete, the signals do not return to their desired precharge level. Instead, the signals return to a level that is offset due to the overshot voltage during the sensing. As a result, the precharge level becomes altered, and the sense amplifier circuits do not interpret the next bit signal incorrectly.
This problem is exacerbated by the fact that modem integrated circuits utilize an external power supply ("VDD") that may be set to different voltage levels. For example, a single chip may operate at an external power supply level between 4.0 V and 2.4 V. Therefore, components used by sense amplifier circuits, as well as a length of time in which a signal is overdriven, must support a wide variance in power supply levels. For example, conventional chips utilize a large p-channel common source switch to control the length of time a signal is overdrawn. This is due to the ability of a p-channel device to pull to a very high voltage and to do so quickly at high power supply levels. However, the operational characteristics of p-channel devices vary dramatically with changes in operating voltages, making a fast and accurate design even more difficult to achieve. Furthermore, p-channel devices vary greatly with changes in operating voltages, being very slow at low operating voltages. Further still, p-channel devices require significantly large amounts of layout space on the chip.
Therefore, what is needed is a method and apparatus for overdriving signals to achieve fast signal separation, while maintaining the accuracy of the sense amplifier operation.
Furthermore, what is needed is a method and apparatus for overdriving signals in chips operating at different power supply levels.

Semiconductor integrated circuit device having a constant delay-time circuit for different operating voltages


Regenerative intensifier systems that can receive fluids from landfills, anaerobic digesters, wastewater treatment plants, animal waste lagoons, swamp gas, decaying permafrost, and oceanic clathrate decomposition interchangeably with natural gas and other available fuels and substances and provide suitably conditioned fuel for operation of an engine, fuel cell, or other industrial and/or chemical processes. Alternatively, gases collected from landfills, waste digesters, bakeries, breweries, ethanol plants, calciners, power plant stacks, electrolyzers, and/or natural gas that may be delivered at relatively low pressures can be converted to high pressure and/or high purity constituents to enable efficient utilization as a transportation fuel and/or industrial feedstock or chemical plant reactant.

Vast amounts of biomass waste could be converted into methane, carbon and other valuable substances and more efficient technology is needed to separate and pressurize these products for storage, conveyance, to market and/or for many chemical reactions. Similarly many commercial and industrial customers have access to pipeline deliveries of relatively low pressure natural gas that may contain considerable amounts of impurities such as water vapor, nitrogen, H2S, silanes, and heavier hydrocarbons. It may not be economically feasible to provide suitable pressurization and appropriate separation processes to remove impurities by conventional methods and operations because of prohibitive capital expenses for a prime mover, compressor, and various filters that may be used for separation and/or the maintenance costs for suitably efficient operation. Embodiments of the present system provide new multifunctional operations, and processes, and outcomes to overcome these problems.

Regenerative intensifier and associated systems and methods


This invention relates generally to olefin metathesis, and more particularly relates to the ring-opening, ring insertion cross-metathesis of cyclic olefins with internal olefins such as seed oils and the like. In one embodiment, a method is provided for carrying out a catalytic ring-opening cross-metathesis reaction, comprising contacting at least one olefinic substrate with at least one cyclic olefin as a cross metathesis partner, in the presence of a ruthenium alkylidene olefin metathesis catalyst under conditions effective to allow ring insertion cross metathesis whereby the cyclic olefin is simultaneously opened and inserted into the olefinic substrate. The invention has utility in the fields of catalysis, organic synthesis, and industrial chemistry.

In the past 15 years, ruthenium olefin metathesis catalysts have firmly established olefin metathesis as a versatile and reliable synthetic technique for organic syntheses. The exceptionally wide scope of substrates and functional group tolerance makes olefin metathesis a valuable technique. In this application, the use of olefin cross metathesis to produce alpha-olefins is another example of the usefulness and the robustness of olefin metathesis technology. Compared to traditional synthetic organic techniques, olefin metathesis efficiently produces compounds that are otherwise hard to synthesize. Numerous man hours of research have resulted in the elucidation of many olefin metathesis reactions catalyzed by various transition metal complexes. In particular, certain ruthenium and osmium carbene compounds, known as "Grubbs' catalysts," have been identified as effective catalysts for olefin metathesis reactions such as, for example, cross-metathesis (CM), ring-closing metathesis (RCM), ring-opening metathesis (ROM), ring opening cross metathesis (ROCM), ring-opening metathesis polymerization (ROMP) or acyclic diene metathesis (ADMET) polymerization.
ROCM is a version of cross metathesis and historically has been underutilized mainly due the difficulty of controlling selectively. ROCM is an intermolecular exchange of a cyclic olefin and an acyclic olefin. In these instances, release of ring strain is the driving force for the reaction to proceed. A review of ROCM is provided by Schrader and Snapper in Handbook of Metathesis, Volume 2: Applications in Organic Synthesis (R. H. Grubbs Ed.), Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim, 2003, pp 205-237.
Early ROCM examples were low yielding reactions with poor selectivities. Even with these shortcomings, ROCM has become an important fixture in metathesis history because ROCM was the key reaction used by Yves Chauvin to propose the currently accepted metathesis mechanism that bears his name, i.e. the Chauvin mechanism. Chauvin proposed the interchange of metal carbenes via a metallocyclobutane ring as an alternative mechanism to the then-accepted pair-wise mechanism for olefin cross metathesis. The metallocyclobutane mechanism was proposed based on the ROCM of cyclopentene with 2-pentene, shown in Scheme 1, which resulted in a statistical product distribution (1:2:1 of compounds 1, 2, and 3 respectively). In the pair-wise mechanism only compound 2 would be expected to form, at low conversions. Chauvin was rewarded for his insight and contributions to metathesis by sharing the 2005 Nobel Prize in Chemistry with Dr. Robert Grubbs and Dr. Richard Schrock.

ROCM reactions using cyclododecene and methyl oleate or oleyl acetate have been reported. The reactions employed an ill-defined tungsten catalyst system to produce the ring inserted product, as shown in Scheme 2.

There is an ongoing need in the art for methods and systems that would allow ring insertion cross metathesis of cyclic olefins into internal olefins, e.g., seed oils and the like. This type of reaction would be useful in the preparation of various useful products, including, by way of example, chain-extended trialkylglycerides (TAGs) and chain-extended fatty acid methyl esters (FAMEs). An ideal such reaction could be implemented in the preparation of metathesis products useful as binders in urethane foams, latex pains, printing inks, and high melting point waxes.

Ring opening cross-metathesis reaction of cyclic olefins with seed oils and the like


The distributed reflector includes a substrate and at least one optical waveguide formed on the substrate and having a refractive index larger than the substrate and at least one optical confinement layer having a refractive index smaller than the optical waveguide layer. A diffractive grating is formed in at least one layer constituting the optical waveguide. The diffractive grating has a structure of which at least one parameter defining optical reflectivity varies depending on its position, and is formed continuously for at least two periods, the period being approximately defined by the length of repeating unit region. The parameter may be pitch, coupling coefficient, bandgap composition, phase shift, etc. The semiconductor laser includes the distributed reflector which may be of a distributed reflector type or distributed feed back type and has distributed reflector regions and a phase adjustment region. Application of current or voltage to the refractive index of the active region or inactive region in which a diffractive grating is present or absent adjusts the refractive index thereof and enables coarse and fine adjustment of lasing wavelength.

1. Field of the Invention
The present invention relates to a distributed reflector and a semiconductor laser with such a distributed reflector useful in optical transmission field, and more particularly to a wavelength-tunable semiconductor laser with a distributed reflector which is suitable as a light source for transmission, a tunable light source for synchronous rectification, and a light source for photometry in optical wavelength (frequency) multiplexing communication systems.
2. Description of the Prior Art
As a wavelength-tunable light source, distributed reflector type semiconductor lasers have been studied widely. FIG. 1A is a schematic cross-sectional view showing a basic structure of a first conventional example of a wavelength-tunable distributed reflector type semiconductor laser. (e.g., Y. Tohmori et al., Electronics Letters, Vol. 19, p. 656 (1983)). In FIG. 1A, 2 is an active waveguide layer, 3 an inactive waveguide layer, 20 a diffractive grating, 101 an active region, 102 a front side distributed reflection region, 103 a rear side distributed reflection region, and 104 a phase adjustment region. In such a type of laser, the distributed reflectors on the both front and rear sides have identical peak wavelengths and can lase stably at a low threshold value when their respective reflectivities are high.
However, in the first conventional example, the distributed reflector regions 102 and 103 each may be deemed to have a uniform pitch .LAMBDA., and a uniform equivalent refractive index, n.sub.eq, as illustrated in FIG. 1B. Hence, Bragg wavelength, .lambda..sub.B, at which a high reflectivity is obtained will be observed as a single line as illustrated in FIG. 1C. Tunable range of a lasing wavelength is an amount of variation .DELTA..lambda. (=2.LAMBDA..multidot..DELTA.n.sub.eq) from the Bragg wavelength, .lambda..sub.B, and depends on the amount of variation .DELTA.n.sub.eq of the equivalent refractive index, n.sub.eq, caused by current injected into the distributed reflector region. Incidentally, a maximum relative equivalent refractive index variation, .DELTA.n.sub.eq /n.sub.eq, is 1% or less, and various workers on experiments on wavelength tunability with the above-mentioned conventional distributed reflector type semiconductor lasers (cf., e.g., Y. Kotaki, et al., Electronics Letters, Vol. 23, p. 327 (1987)) remained to report wavelength tunable ranges on the order of 10 nm, which is insufficient for providing a light source for optical wavelength multiplexing communication systems.
Recently, a distributed reflector as shown in FIG. 2A has been proposed which enables wavelength tuning within the range on the order of above 10 nm, which is referred to herein as reflector according to a second conventional example. In FIG. 2A, broken line indicates portions whose depiction has been omitted. In this case, the waveguide has a diffractive grating of a pitch of .LAMBDA., formed partially and periodically, thereby giving a plurality of reflection peaks in the vicinity of Bragg wavelength, .lambda..sub.B, which depends on the pitch, .LAMBDA., as illustrated in FIG. 2B. In a laser structure, one of the reflection peaks is selected electrically (i.e., rough adjustment of wavelength), and wavelength tuning is performed in the vicinity of the selected reflection peak (i.e., fine adjustment of wavelength) (cf. U.S. Pat. No. 4,896,325 to L. A., Coldren et al.; and V. Jayaraman et al., LEOS, "91, paper SDL15.5, 1991). There is a report on wavelength tuning which says only on an experimental basis, rough adjustment on the order of 50 nm was made (V. Jayaraman et al., IEEE, 13th International Conference on Semiconductor Lasers, Post Deadline Papers PD-11).
In the second conventional reflector, as will be understood from FIG. 2B, reflectivities decrease considerably as the wavelengths depart from Bragg wavelength, .lambda..sub.B. There has been no report on continuous operation of a wavelength-tunable semiconductor laser having the above-mentioned reflector according to the second conventional example while only pulse operation was made to confirm its action.
With view to complying to expected rapid and great increase in the amount of communication and information in future, various investigations have been made on optical wavelength (frequency) multiplexing communication systems and there is a keen desire on the development of a light source with a wavelength tunability over a wide range as a light source for transmission, and synchronous rectification. Also, it is desired to realize a wavelength-tunable light source which can cover a wide band useful in the field of photometry.

Distributed reflector and wavelength-tunable semiconductor laser

Nippon Telegraph and Telephone Corporation