An electrode substrate includes a substrate and an electrode layer of a noble metal crystal formed on the substrate, the noble metal crystal exhibiting a substantially linear domain boundary and a plane orientation dispersion angle in X-ray analysis of 1.degree. or less. An information recording medium includes an electrode substrate as described above and a recording layer provided on the electrode layer. An information processing apparatus includes: an information recording medium as described above; a probe electrode arranged in close proximity to this medium; and a voltage applying circuit for applying a pulse/bias voltage between the medium and the probe electrode, information being written/read onto/from the medium by the application of the pulse/bias voltage. An information processing method includes the steps of: preparing an information recording medium as described above; arranging a probe electrode in close proximity to the medium; and applying a pulse/bias voltage between the medium and the probe electrode so as to write/read information onto/from the medium.

1. Field of the Invention
The present invention relates to an information processing apparatus utilizing the principle of a scanning tunneling microscope (hereinafter abbreviated as "STM"), and an electrode substrate and an information recording medium used in the apparatus.
2. Description of the Related Art
Nowadays, memory materials are being used in computers and apparatuses related thereto, video discs, digital audio discs, etc., equipment constituting the nucleus of the electronics industry. The development of new materials in this field is being very actively promoted. The characteristics required of memory material vary in accordance with the use for which it is intended. The following are characteristics generally required of memory material:
1 High density and large recording capacity;
2 High response speed in recording and reproduction;
3 Low power consumption; and
4 High productivity and low price.
Conventionally, semiconductor memories and magnetic memories made of semiconductors and magnetic substances have been the mainstream of memories for information processing. However, as a result of recent developments in laser technology, inexpensive high-density recording mediums have appeared which consist of optical memories using films of organic dyes, photopolymers, or the like.
Apart from this, an STM (a scanning tunneling microscope) has recently been developed which makes it possible to directly observe the electronic structure of a surface atom of a conductor (G. Binning et al., Phys. Rev. Let., 49,57 (1982)). With this microscope, it is possible to perform high-resolution measurement on a real image in space, whether it is monocrystalline or amorphous. Further, it has an advantage that it allows the specimen to be observed with low power without being damaged by electric current. Moreover, it can operate even in ambient atmosphere so that it can be used with respect to various types of materials. Thus, a wide range of applications are expected from the STM.
The STM utilizes the fact that a tunnel current flows when a metal probe (a probe electrode) is brought near a conductive substance, up to a distance of approximately 1 nm, while applying a voltage between them. This current is very sensitive to changes in the distance between the metal probe and the conductive substance, and even allows for the reading of a variety of information regarding the entire electron cloud in an actual space by performing scanning with the probe in such a way as to maintain the tunnel current constant. In that case, the resolution in the in-plane dimension is approximately 0.1 nm.
Thus, by utilizing the principle of the STM, there is a good possibility that a high-density recording/reproduction of the atom order (sub-nanometer) can be performed. For example, in the information processing apparatus disclosed in Japanese Patent Laid-Open Publication No. 61-80536, an electron beam or the like is used to write data onto a recording medium by removing atom particles adhering to the medium surface, and reproducing the data by means of an STM. According to the disclosure in the specification of U.S. Pat. No. 4,575,822, the tunnel current flowing between the recording medium surface and the probe electrode is used to effect recording by injecting electric charges into a dielectric layer formed on the medium surface. There has also been a method proposed in which a laser beam, electron beam, corpuscular beam or the like is used to perform recording by utilizing physical or magnetic disruption of the medium surface.
According to another proposed method, a material having a memory effect with respect to voltage/current switching characteristics, for example, a thin-film layer of a .pi.-electron-type organic compound, chalcogen compound or the like, is used as the recording layer to perform recording and reproduction with an STM (Japanese Patent Laid-Open Publication Nos. 63-161552 and 63-161553). Assuming that the recording bit size is 10 nm, this method makes it possible to perform recording and reproduction by as much as 10.sup.12 bit/cm.sup.2.
FIG. 8 shows a sectional view of a conventional recording medium together with the tip of a probe electrode 202.
Numeral 101 indicates a substrate; numeral 102, an electrode layer; numeral 103, a recording layer; numeral 104, a track; numeral 202, the probe electrode; numeral 401, a data bit recorded on the recording layer 103; and numeral 402, crystal grains generated during the formation of the electrode layer 102. Assuming that the electrode layer 102 is formed by a usual method, such as vacuum evaporation or sputtering, the size of the crystal grains 402 ranges from approximately 30 to 50 nm.
The distance between the probe electrode 202 and the recording layer 103 can be kept constant through a conventionally well-known circuit construction. That is, a tunnel current flowing between the probe electrode and the recording layer is detected, and its value is transmitted through a logarithmic compressor 302 and a low-pass filter 303 and then compared with a reference voltage. A Z-axis actuator 204 supporting the probe electrode is controlled in such a way that this comparison value approaches zero, thereby maintaining a constant distance between the probe electrode and the recording layer.
Further, by driving an XY-stage 201, the surface of the recording medium is traced by the probe electrode 202, and the high frequency component of a signal at an arbitrary point P is separated, thereby making it possible to detect the data of the recording layer 103. FIG. 9 shows a signal strength spectrum with respect to the signal frequency at point P at this time.
Any signals of a frequency component not higher than f.sub.0 are due to a gentle rise and fall of the substrate 101 caused by warp, distortion or the like. The signals around f.sub.1 are due to surface irregularities of the electrode layer 103, caused mainly by the crystal grains 402 generated during the formation of the material into an electrode. Symbol f.sub.2 indicates a recording data carrier component, and numeral 403 indicates a data signal band as shown in FIG. 6. Symbol f.sub.3 indicates a signal component generated from the atomic/molecular arrangement of the recording layer 103. Symbol f.sub.T indicates a tracking signal, which enables the probe electrode 202 to trace data arrays. It can be realized by forming a groove on the medium or writing thereto a signal which enables detection whenever an off-track condition occurs.
Use of a conventional recording medium based on an electrode substrate as described above entails the following problems:
1 To make use of the high resolution, which features the STM, and perform high-density recording, the data frequency component 403 must be between f.sub.1 and f.sub.3. For this purpose, a high-pass filter of a cut-off frequency of f.sub.c is used for data component separation. However, as shown in FIG. 9, a foot portion of the f.sub.1 signal component overlaps the data band 403. This is attributable to the fact that the f.sub.1 signal component is due to the crystal grains 402 of the electrode layer 102, with the recording size and bit interval of the data being in the range of 1 to 10 nm, which is close to the crystal grain size of 30 to 50 nm. As a result, the S/N ratio in data reproduction is deteriorated, thereby increasing the incidence of error.
2 The tracking signal f.sub.T can only be placed in the vicinity of f.sub.0. As a result, the frequency of the tracking signal is considerably low as compared with the data frequency, resulting in poor data tracing accuracy in tracking. This causes the incidence of error in data reading to be increased, thereby deteriorating the reliability of the information processing apparatus.
3 Further, a track groove corresponding to such a low tracking frequency is considerably large as compared to the data bit size, with the result that the data recording density is significantly low, thereby making it impossible to fully make use of the high resolution featuring the STM.

Information processing apparatus, and electrode substrate and information recording medium used in the apparatus


Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.

Time interleaving is a technique used to increase the overall sampling rate of a system by using multiple sampling elements in parallel. For example, multiple slicers/samplers may be used in parallel in a serializer/deserializer application, or multiple sub-analog-to-digital converters may be used in parallel in a digital signal processing based receiver. By using time interleaving, higher bit rates may be achieved while keeping the clock frequency lower than if time interleaving was not used. This may result in lower power dissipation in the system compared to not using time interleaving.
In an N-way time interleaved receiver, an overall sampling rate fs, may be obtained by using N sampling elements, with each of the sampling elements sampling at a different, equally spaced, phase of a clock that has a clock rate of fs/N.
Implementing time interleaving may involve precise multi-phase clock generation, such as the creation of N clocks, with each one of the N clocks sampling at substantially exactly one sampling period 1/fs from each other.

System and method for adjusting clock phases in a time-interleaved receiver


A MOSFET (Metal Oxide Semiconductor Field Effect Transistors) cell array formed on a semiconductor substrate includes a major surface formed with a plurality of MOSFET cells. Each semiconductor cell in the cell array is geometrically configured with a base portion and a plurality of protruding portions extending from the base portion. The base and protruding portions define a closed cell boundary enclosing each semiconductor cell. The closed cell boundary of each semiconductor cell is disposed on the major surface proximal to and in geometrical accord with the corresponding cell boundaries of other adjacent semiconductor cells in the cell array. As arranged, the cell boundary and thus the channel width of each cell is extended without any concomitant reduction in cell area.

1. Field of the Invention
The present invention relates generally to microelectronic circuits, and more particularly, to power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) circuits having high packing densities.
2. Description of the Related Art
Power semiconductor devices have long been used as replacement for mechanical relays in various applications. Development in semiconductor technology enables these power devices to operate with high reliability and performance. FIG. 1 shows a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) array arranged on a planar configuration. The MOSFET array is generally signified by the reference numeral 2. The array 2 comprises a substrate 4 which is deposited with various diffusion or implant regions. For example, there are source regions 6 which are heavily doped with N-type material. Similarly, there are body regions 8 which are doped with P-type material. The drain 9 comprises an epitaxial layer 10 deposited in contact with a heavily doped drain contact layer 12 formed of N-type material. A plurality of polysilicon gates 14 is also disposed above the substrate 4 spaced by gate oxide layers 16. The polysilicon gates 14 are electrically connected together via bridging traces not shown in FIG. 1. Similarly, the sources 6 are electrically tied together via a source metal layer 17.
During normal operations, the sources 6 are connected to the ground potential via the source metal layer 17. At the same time, a positive potential is applied across the drain 9 and the source regions 6. A drain-to-source voltage V.sub.DS is established. In a similar fashion, a gate-to-source voltage V.sub.GS is also applied across the gates 14 and the source regions 6. The V.sub.GS voltage capacitively induces N-type channels 18 underneath the gate oxide layers 16. The channel 18 allows the V.sub.DS voltage to drive a drain-to-source current I.sub.DS from the drain 9 to the source regions 6. The MOSFET 2 is said to be at the power-on state.
The current path where the drain-to-source current I.sub.DS flows is predominantly resistive and the resistance value is called the drain-to-source R.sub.DS of the MOSFET. In a power MOSFET device, there is a plurality of individual MOSFETs 19 fabricated together to form the MOSFET array 2. The aggregate resistance values of the drain-to-source resistance R.sub.DS during the power-on state is called the power-on resistance R.sub.ON of the MOSFET array 2.
It has been a constant design goal to make MOSFET arrays with low power-on resistance R.sub.ON. Lower power-on resistance R.sub.ON not only curtails power consumption and thus cuts down the wasteful heat dissipation of the MOSFET array 2, it also prevents the MOSFET array 2 from robing away any intended driving voltage V.sub.CC to any circuits that the MOSFET array 2 drives. Specifically, lower Ohmic drop passing through the MOSFET array 2 during normal operations avails any circuits driven by the MOSFET 2 with a less distorted driving voltage V.sub.CC.
The advent of high resolution photolithography allows semiconductor components to be formed on a semiconductor substrate with ultra fine geometries. Accordingly, to reduce the power-on resistance R.sub.ON of any MOSFET arrays, one conventional approach is to densely integrate the MOSFETs 19 on the semiconductor substrate 4. The rationale behind this approach is that the higher the number of MOSFETs 19 operating in parallel, the lower the overall power-on resistance R.sub.ON results in the MOSFET array 2. However, theoretical feasible as it appears, there are various technical complications associated with densely integrating a planar MOSFET array 2.
Reference is now directed back to FIG. 1 which shows the countervailing factors commonly frustrating the attempts of densely integrating a planar MOSFET device. As mentioned before, advanced development in high definition photolithography allows denser device integration. As integration density increases, cell-to-cell separations decrease. As shown in FIG. 1, the drain-to-source resistance R.sub.DS of each cell during the power-on state can be approximated by the following algebraic equation: EQU R.sub.DS =R.sub.cs +R.sub.S +R.sub.ch +R.sub.j +R.sub.d1 +R.sub.d2(1)
where R.sub.CS is the contact resistance of the source metal 17 to the source region 6; R.sub.s is the source resistance; R.sub.ch is the channel resistance; R.sub.j is the junction resistance; R.sub.d1 is the drain resistance at the epitaxial region 10; and R.sub.d2 is the drain resistance at the drain contact region 12 in ohms. The dominant components are the junction resistance R.sub.j and the drain resistance R.sub.d1 at the epitaxial region 10. First, the epitaxial layer 10 is lightly doped and consequently assumes a high resistivity. Furthermore, the epitaxial region 10 is also a relatively thick layer and therefore extends a longer resistive path. As integration density increases, the diffusion regions, such as the source diffusion regions 6 and the body diffusion regions 18 among the MOSFET cells 2 encroach closer and closer toward each other as illustrated by the directions 20 shown in FIG. 1. Consequently, during the power-on state, the drain-to-source current I.sub.DS of each cell only has a limited resistive area to pass through. As shown in FIG. 1, basically, the region signified by the reference numeral 22 has to be shared by two MOSFET cells 19. As is known in the art, the smaller the area of the resistive path, the higher is the resistance value. Equally as detrimental is the current crowding effect in the confined region 22 which also plays a dominant role in increasing the values of the resistances R.sub.j and R.sub.d1. Accordingly, the advantage gained in pursuing higher density integration can be totally negated by the increase in drain and junction resistances R.sub.d1 and R.sub.j as explained above.
To avoid the aforementioned problems associated with dense integration, MOSFET structures with trenched gates have been devised. FIG. 2 shows a typical arrangement of trenched MOSFET array signified by the reference numeral 24 which includes a substrate 26. There is a plurality of trenches 28 filled with conducting material 30 which is electrically separated from the substrate 26 by a thin insulting layer 32. Each MOSFET cell 34 can be a N-channel device comprising a source layer 36 made of N-type material; a body layer 38 formed of P-type material; an epitaxial layer 40 composed of a lightly doped N-type material; and a drain contact layer 42 based on a heavily doped N-type material. Atop the trenches 28 are insulating layers 42 insulating the conductive material 30 from a source contact metal layer 17. There is also a drain metal contact layer 46 attached to the drain contact region 42 of the MOSFET 24. The conductive materials 30 in the trenched gates 28 are electrically connected together but are not shown in FIG. 2.
There are also cell contact regions 52 diffused in the substrate 26. The implementation of the cell contact regions 52 is to prevent triggering the parasitic NPN transistors 54 into action, which NPN transistors 54 are surreptitiously embedded in each MOSFET cell 34. As shown in FIG. 2, the source region 36 is of N-type which corresponds to the emitter E of the NPN transistor 54. Similarly, the body region 38 is of P-type conductivity which acts as the base B of the NPN transistor 24. The N-type drain 42 is the common collector of all the transistors 54 (only one is shown in FIG. 2). The body regions 38 are lightly doped regions and assume high resistivity. In accordance with Ohm's law, current passing through any resistive body region 38 generates a potential voltage difference. With the body regions 38 built in with a high resistivity, small amount of stray current passing through the regions 38 will suffice to generate a voltage of sufficient magnitude to turn on the base-to-emitter voltages V.sub.BE of the NPN transistors 54. Once the parasitic transistors 54 are turned on, they enter into the active conduction mode and sustain huge collector-to-emitter current I.sub.CE and cause irreparable damages to the MOSFET cells 34.
The presence of the cell contact regions 52 is to decrease the base-to-emitter resistivity of the NPN transistors 54 such that they can tolerate a reasonably high base-to-emitter current without exceeding the typical base-to-emitter voltage V.sub.BE which is about a potential difference drop of a diode of approximately 0.7 Volts.
As with the planar MOSFET array 2 shown in FIG. 1, the current path where the drain-to-source current I.sub.DS flows is resistive and its resistance is called the drain-to-source R.sub.DS of the MOSFET cell 34. The aggregate resistance values of the drain-to-source resistance R.sub.DS during the power-on state is called the power-on resistance R.sub.ON of the MOSFET array 24. Since the channels 48 are arranged in a vertical manner, the lateral current paths are basically eliminated. The problem of cell-to-cell encroachment competing for current flow is no longer an issue. That is, as different from the MOSFET array 2 with the planer configuration, the junction resistance R.sub.j of the drain-to-source resistance R.sub.DS is essentially removed, as shown in FIG. 2. Moreover, the drain resistance R.sub.d1 in the epitaxial region 40 also has a relatively larger cross-sectional area for current to pass through due to the more spaced-apart relationship between the cells 34. The consequential benefit is that a higher degree of integration on a semiconductor substrate can be realized, which in turn provides lower power-on R.sub.ON resistance. Lower power-on resistance R.sub.ON curtails ohmic loss during the power-on state and further alleviates heat dissipation.
Advantageous as it appears, densely integrating the cells 34 necessitates packing more cells 34 per unit area on a semiconductor surface. As a consequence, each cell 34 is laid out with a smaller physical area having smaller contact surfaces for the source regions 36 and for the cell contact regions 52. Accordingly, cross-sectional areas for current flow through the regions 36 and 52 are also diminished resulting in increase in contact resistivity. Differently put, with reference to FIG. 2, the source contact resistance R.sub.CS and the cell contact resistance R.sub.CC of each cell 34 are increased due to the corresponding decrease in the individual geometrical areas of the source region 36 and the cell contact region 52 because of the overall reduction in area of each cell 34. As a consequence, the cell contact regions 52 are less effective in suppressing the parasitic transistors 54 during normal operations. Equally as undesirable is that the source contact resistance R.sub.CS, and to a lesser extent, the source resistance R.sub.s in the source regions 36, emerge as the dominant components in the drain-to-source resistance R.sub.DS of the MOSFET 24 during the power-on state.
Thus, scaling down the geometrical areas of the cells in a MOSFET array does not appear to be a viable solution to reduce the power-on resistance R.sub.ON of the MOSFET array fabricated via high density integration. There is a minimum limit in cell area that each cell 34 must maintain. Beyond such a limit, the dominant effects of the source contact resistance R.sub.CS and the cell contact resistance R.sub.CC would negate any advantages of fabricating MOSFET arrays by way of high density integration.
Prior to any further analysis, the configurations of the conventional MOSFET arrays need first be identified. FIG. 3 is a perspective view, partially cut away, showing the typical cell-to-cell arrangement of the MOSFET array 24. FIG. 4 is the top plan view taken along the line 4--4 of FIG. 3. FIGS. 3 and 4 are shown with the insulating and passivation layers removed exposing the relevant layers of the MOSFET array 24. The cell-to-cell arrangement of the array shown in FIGS. 3 and 4 are called the "brick wall" pattern in which the cells of any cell row are shifted by half a cell length with respect to the cells of the adjacent cell rows. Alternatively, the cells can be arranged in another pattern called the "waffle" pattern in which the cell rows and columns are geometrically aligned as shown in FIG. 5.
As another alternative, cells can be arranged in a "honey comb" pattern as disclosed in U.S. Pat. No. 5,072,266, Bulucea et al., entitled "Trench DMOS Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry", issued Dec. 10, 1991. The "honey comb" pattern is illustrated in FIG. 6.
To alleviate the aforementioned problems of shrinkage in contact areas for the source regions 36 and the cell contact regions 52 (FIG. 2) due to dense integration, it is desirable that the power-on resistance R.sub.ON resistance decreases without any accompanying reduction in the source contact and cell contact areas associated with the regions 36 and 52. Phrased differently, with reference to FIGS. 1 and 2, in the fabrication of a high density MOSFET array with the state-of-the art high resolution photolithography, the ideal objective is to reduce the drain-to-source resistance R.sub.DS of each cell 19 or 34 without any concomitant increase in the source contact resistance R.sub.CS and the cell contact resistance R.sub.CC.
The semiconductor array of the invention accomplishes the above-mentioned objective by extracting a longer cell boundary out of a fixed cell area. A longer cell boundary results in a longer channel width W for each cell 34 which in turn provides lower drain-to-source resistance R.sub.DS.
As is known in the art, the power-on resistance R.sub.ON assumes the following algebraic relationship: ##EQU1## where L is the channel length in .mu.m; and W is the channel width in .mu.m. With reference again to FIGS. 2-5, for a trenched MOSFET with a square cell configuration, the channel length L is the linear dimension extending from source region 36 to the epitaxial region 40 (FIG. 3). The channel width W is the length of the boundary enclosing each active cell 34. Each side of the square cell 34 is one quarter of the channel width W and is labelled W/4 in FIGS. 3-5.
Assuming the channel length L is a fixed parameter, and further assuming that the geometrical area for each cell 34 is also fixed such that there is no diminution in the area L sizes of the source regions 36 and the cell contact regions 52, a MOSFET cell with a lower power-on resistance R.sub.ON would result if a longer channel W can be designed to encompass each cell 34. The MOSFET array of the invention provides such a longer channel width W for each cell without any sacrifice or trade-offs with other parameters.
Instruments are now built with ever increasing complexity and decreasing physical sizes. To fully reap the advantages of high resolution photolithography, factors that hamper high density integration must be overcome. Specifically, semiconductor power devices, even fabricated with fine line geometry at high packing density, need to exhibit ruggedness in performance and with low power-on resistance. At the same time, production yield is not compromised with the improvement in performance. There has been a long-felt need to provide power devices meeting the aforementioned criteria.

Semiconductor cell array with high packing density


A flatware sorting machine including a feed bin for holding unsorted flatware, a sorting system for sorting the flatware, and a flatware pick-up and transport system for retrieving the flatware from the feed bin and transporting them to the sorting system.

Manually sorting flatware according to type and orientation is a time consuming and tedious labor intensive task at restaurants and cafeterias such as cafeterias at major universities where thousands of pieces of flatware are used and must be washed each day.
At such facilities, dirty flatware is normally dumped unsorted into a tray for washing in an automatic dishwasher. After washing, the individual pieces of flatware are then manually sorted according to type and placed handle down in individual knife, fork, teaspoon, and soup spoon bins for a sanitizing cycle in the dishwasher. The reason the flatware is placed handle down is so that the sanitizing solution drips off the head of the flatware during the sanitizing cycle.
After sanitization, the flatware is then manually transferred to serving trays or bins, usually handle end up.
The need for automatic flatware sorting machines was recognized in U.S. Pat. No. 4,954,250. Unfortunately, the apparatus disclosed therein was excessively large, did not always sort the flatware properly according to type, and, in any case, did not automatically orient the flatware for the sanitizing cycle. Thus, this apparatus still required a fair amount of manual labor.
Other attempts at manufacturing a fully automatic flatware sorting machine have also failed. As discussed in the '250 patent, complex image recognition systems have been developed in an attempt to sort flatware both according to type and orientation but such systems exhibit high failure rates, low reliability, and are not robust enough to withstand the harsh kitchen environment where they are used.
Thus, there is a need for a fairly compact, robust, highly reliable, and fully automatic flatware sorting machine which sorts flatware not only according to type but also according to orientation to eliminate the tedious manual labor associated with sorting operations in restaurants and cafeterias.

c/o East Coast Industries, Inc. 2532 Main St.


Aspects of the present disclosure describe distributed optical fiber sensing systems, methods, and structures that advantageously employ point sensors that send sensory data/information over an attached, distributed optical fiber sensor without using a separate network or communications facility.

Distributed optical fiber sensing systems have shown great utility in a number of unique sensing applications due to their intrinsic advantages over conventional techniques. They can be integrated into normally inaccessible areas and can function in harsh environments. They are immune to radio frequency interference and electromagnetic interference and can provide continuous, real-time measurements along an entire length of a fiber optic cable.
Similarly, point sensors—i.e., sensors that perform a specific measurement, have shown great utility in a variety of sensing applications also. Despite their utility—particularly when coupled with dedicated communications networks—point sensors have not been employed in DOFS systems.

Distributed optical fiber sensing using point sensors


A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.

1. Field of the Invention
The invention relates in general to a semiconductor package and a manufacturing method thereof, and more particularly to a semiconductor package with an antenna and a manufacturing method thereof.
2. Description of the Related Art
Wireless communication devices, such as cell phones, require antennas for transmitting and receiving radio frequency (RF) signals. Conventionally, a wireless communication device includes therein an antenna and a communication module (e.g., a semiconductor package with RF communication capability), each disposed on different parts of a circuit board. Under the conventional approach, the antenna and the communication module are separately manufactured and electrically connected after being placed on the circuit board. Accordingly, higher manufacturing costs are incurred and a compact product design as well as reduced device size are difficult to achieve. In addition, a RF signal transmission path between the antenna and the communication module is long, and the quality of a signal transmitted between the antenna and the communication module is reduced.

Semiconductor package having an antenna and manufacturing method thereof

Advanced Semiconductor Engineering, Inc.


A touch sensitive apparatus includes a touch plate to which several pickup sensors and at least one excitation transducer are coupled. Each of the sensors is configured to sense bending waves in the touch plate, and the excitation transducer is configured to induce bending waves in the touch plate. The apparatus may further include active buffer circuits, wherein each of the active buffer circuits is coupled to one of the sensors. A controller is coupled to the sensors via the active buffer circuits and to the excitation transducer via a non-actively buffered connection. The controller is configured to compute a location of a contact on the touch plate responsive to sense signals received from the sensors. The apparatus may be used to perform a variety of calibrations, including touch plate and sensor calibrations. Changes in touch sensing apparatus calibration and performance may be detected and tracked over time.

Interactive visual displays often include some form of touch sensitive screen. Integrating touch sensitive panels with visual displays is becoming more common with the emergence of next generation portable multimedia devices. One popular touch detection technology, referred to as Surface Acoustic Wave (SAW), uses high frequency waves propagating on the surface of a glass screen. Attenuation of the waves resulting from contact of a finger with the glass screen surface is used to detect touch location. SAW employs a "time-of-flight" technique, where the time for the disturbance to reach the pickup sensors is used to detect the touch location. Such an approach is possible when the medium behaves in a non-dispersive manner, such that the velocity of the waves does not vary significantly over the frequency range of interest.

Touch sensitive device employing bending wave vibration sensing and excitation transducers


A stand for a Christmas tree or the like is adapted to cooperate with a base portion of a pole such as a tree trunk to provide a stable support for the pole with its base spaced above a support surface such as a floor. The stand comprises a plurality of support members each having a proximal end spaced above the support surface. The proximal ends of the support members cooperate to form a clamp for receiving the base portion of the pole. The clamp is arranged such that, when the base portion of the pole is received in the clamp, one or more of the support members pivots at its proximal end about the clamp to thereby cause the clamp to close and grip the base portion of the pole. The weight of the pole may be sufficient to cause the clamp of the stand to automatically grip the pole.

Stands for supporting both natural Christmas trees and artificial Christmas trees are known. In most known stands, the stands include means adapted to loosely receive a base portion of the tree pole or trunk. In order to then stably support the Christmas tree, the stands includes means for fixedly securing the tree pole to the stand. Such means often comprise one or more manually operated screws or the like provided at or adjacent to the means for receiving the lower portion of the tree pole where the screws must be driven into the material of the tree pole to fix it to the stand.
There are a number of disadvantages with known tree stands. One such problem is that the stands are often not easily collapsible for transport or storage purposes. Or, where they are collapsible, it often requires that they are disassembled into multiple separate parts for storage with the danger that one or more of such parts becomes mislaid. Another problem is that the fixture means such as screws for fixedly securing the tree pole to the stand may damage the material of the pole. This is not an issue in the case of cut natural Christmas trees which are normally disposed of after use, but it can become a problem with artificial trees which may be used time and time again.

Stand for supporting a pole within a base


A hand belt sander has a housing, a drive roller and a deflecting roller both rotatably supported in the housing, the deflecting roller being arranged at a distance from the drive roller movable between a substantially axes-parallel arrangement and out of the axes-parallel arrangement with the drive roller, an endless sanding belt guided along the rollers, a guide plate located in the housing and carrying a control plate with an end for receiving the deflecting roller and being displaceable together with the control plate, a lever arm sensing a position of the sanding belt by a stop part and acting on the position of the sanding belt, a swivel arm around which the lever arm is swivelable and which extends perpendicular relative to the guide plate. The swivel arm sits in the guide plate. The control plate is swivelable around the swivel axle together with the ends and extends toward the guide roller so as to form the swivel arm in a one-piece element, and also carries the stop part.

The present invention is directed to a hand belt sander. More particularly, it relates to a hand belt sander which has a housing for receiving a motor, a drive roller and a deflecting roller, an endless sanding belt guided along the deflecting roller and over a sanding plate, and a guide plate which has a control plate with a fork-shaped end for receiving the deflecting roller and arranged to be displaceable with the latter.
A hand belt sander of the generic type comprising drive and deflecting rollers and an automatic belt running centering means is described in EP-PS 7172. A feeler with a lever system for swiveling the deflecting roller is supported at the housing of the known hand belt sander. The support is located near the deflecting roller.
Hand belt sanders have the peculiarity that the circulating sanding belt wanders laterally, depending on the force and direction of application. The belt running centering means is provided in order to ensure that the center of the sanding belt accurately conforms to the center of the drive or deflecting roller running surface. As soon as the sanding belt moves transversely relative to the running direction, one of its edges strikes the feeler which is situated a short distance therefrom. The feeler acts on the deflecting roller via the lever system. The deflecting roller is moved out of the position in which it is parallel to the axis of the drive roller in such a way that the belt is steered again into the center of the roller circumference.
Disadvantages of the known belt running centering means consist in its costly construction which comprises a plurality of articulations and is susceptible to disturbances from vibration and dirt, as well as the high wear on the lever system for the belt running centering means and on the sanding belt to be centered. A further disadvantage consists in the necessary adjustment of the known belt running centering means depending, for example, on elongation of the sanding belt caused by wear or as a result of the differences in length between different sanding belts when exchanging the latter.


An inspection device includes a movable portion, and a substantially fixed portion. The movable portion includes a plurality of bins as well as beam directors positioned between the bins. The fixed portion includes light detectors and light emitters. The light detectors are arranged to allow multiplexing of the light detectors.

In some commercial and retail settings, there is a need to sort multiple print jobs. For example, a retail photo printer will need to place different customer print jobs in different bins to keep them separated. In another example, a shared resource, such as a copying machine or work group printer, will need to place different print jobs in one of a number of different empty bins, trays or slots. In each instance it is necessary to determine whether a bin, tray or slot is empty before placing a set of prints or a print job into the bin, tray or slot. This assures that the prints or the print job in the slot is for one customer or user and will prevent someone from getting someone else's prints or print job. Furthermore, for order management, it is necessary to know which bins contain jobs, when the job is removed, and if any prints were left behind, as well as which bins are empty and available to receive a new print job. It is also necessary to determine when the bin is empty so that another print job can be placed in the bin. In addition, if the print job is finished, an operator or picker can be prompted to empty a bin. The same will happen if a bin is not totally empty.
In addition to print sorters, there may also be other sorters for copy jobs and the like. Sometimes mechanical sensors or electromechanical sensors are used to detect when a bins if a bin contains materials. Mechanical sensors or electromechanical sensors are less than totally reliable. If the mechanical sensor or electromechanical sensor is required to move with a bin, slot or tray, the mechanical or electromechanical sensor is more prone to failure and, therefore, less reliable. Contacts associated with wires may fail, wires may fail, and moving mechanical devices are prone to failure. If the mechanical sensor is powered by an electrical source, consistently powering a sensor that requires power while moving one or more of a set of bins also can be a challenge.
The description set out herein illustrates the various embodiments of the invention and such description is not intended to be construed as limiting in any manner.

Multiplexed optical sensor system and method

Hewlett-Packard Development Company, L.P.


A method for continuous data protection in a storage system, including receiving a first write command to write first data to a partition of a logical volume and then generating a first partition descriptor record (PDR) having a first timestamp. The method further includes storing the first data at a first location, associating the first PDR with the first location, and receiving a second write command, subsequent to the first command, to update the first data with second data. Responsively to the second command, a second PDR having a second timestamp is generated. The second data is stored at a second location, and the second PDR is associated with the second location. The method includes generating a pointer between the first PDR and the second PDR, and accessing the first PDR using the pointer in response to a read command indicating a time prior to the second timestamp.

Data storage systems generally store data on physical media in a manner that is transparent to host computers. From the perspective of a host computer, data is stored at logical addresses located on file systems, or logical volumes, of the storage system. The file systems or logical volumes are typically configured to store the data required for a specific data processing application. To function, data storage systems map the logical addresses to addressable physical locations on storage media, such as direct access hard disks. In a typical configuration, physical locations comprise tracks on a hard disk, and a track can typically store many blocks of data.
Continuous Data Protection (CDP) is a term used to indicate techniques for restoring data sets, such as logical volumes, to a situation existing at a prior instant of time. When a system utilizes CDP, a system administrator does not have to initiate the process of copying logical volumes so as to be able to recover the status at a prior time. Rather, the system creates copies automatically, and the administrator may access the copies by specifying the desired prior time for data restoration.
U.S. Patent Application Publications 2005/0076262, 2005/0076261, 2005/0066222, 2005/0065962, and 2005/0063374 to Rowan, et al., whose disclosures are incorporated herein by reference, describe "a method, apparatus, and system for accessing units of storage that depends at least in part on an address of the unit of storage and the time that data was written to the unit of storage." A data store is provided that identifies the location of data at a requested address in response to a time specification and a data request. In one embodiment, "the location is chosen from a time store associated with a data store and a current store associated with the data store, or some combination. The identifying step can include determining whether the data at the requested address at the specified time was changed after the specified time. If data at the requested address was changed after the specified time, the identified location is the time store. If the data was not changed, the identified location is the current store."

International Business Machines Corporation


A method of making an adhesive for an ice protection assembly includes transferring Z-CNTs from a substrate carrier into the adhesive. De-bonding of the adhesive for ice protection assembly inspection or repair or repositioning at initial installation includes heating the Z-CNTs in the adhesive to soften the adhesive and allow for easy removal.

This application relates generally to ice protection assemblies, and specifically to ice protection assembly adhesives.
An aircraft moving through the air is often subjected to ice formation, and anti-icing or de-icing devices must be used to remove or prevent ice from accumulating on exterior surfaces of the aircraft. Ice protection assemblies, such as pneumatic and electrothermal elastomeric ice protection devices, are often attached to wing leading edges or other aircraft components with adhesive.
Both pneumatic and electrothermal elastomeric ice protection devices may be removed and re-applied during the lifetime of the part on which they prevent ice formation or repositioned if initial application on the surfaces is not aligned properly. Typically, ice protection devices are attached to aircraft component with chemical adhesives that require extensive preparation, application, and drying time. De-bonding these chemical adhesives, or pressure sensitive adhesives used to secure ice protection devices to aircraft components for reapplying or repositioning ice protection assembly, is time consuming and can damage the ice protection device. Additionally, traditional "fast application" or "quick removal" adhesives lack the strength necessary to secure an ice protection device to an aircraft component surface.

This patent is subject to a terminal disclaimer.

Z-CNT filled meltable adhesives for bonding of deicers