A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

1. Field of the Invention
The present invention relates generally to nonvolatile semiconductor memory devices and, more particularly, to a nonvolatile semiconductor memory device in which data can electrically be written and erased.
2. Description of the Background Art
There are two types of semiconductor memory devices: the one is a volatile memory such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory) and the like, and the other is a nonvolatile memory. Storage data of a volatile memory are all erased when a power supply is OFF. Storage data of a nonvolatile memory are, however, not erased even if the power supply is OFF. As a representative of nonvolatile semiconductor memory devices, there is a PROM (programmable read only memory). The PROM is a semiconductor memory device in which information is written by a user. As one type of the PROM, there is an EEPROM (electrically erasable and programmable ROM) in which written information can electrically be erased so that information can be rewritten any times. An EEPROM in which storage data of all memory cells can be erased in block is called a flash EEPROM.
FIG. 21 is a schematic block diagram showing a fundamental structure of a conventional flash EEPROM. With reference to FIG. 21, the flash EEPROM includes a memory array 1, a row decoder 4, a Y gate 2 and a column decoder 5.
Memory array 1 includes a plurality of memory cells MC arranged in matrix in the directions of rows and columns. Each of memory cells MC is connected to a corresponding bit line 30 and a corresponding word line 50 in memory array 1. A FAMOS (floating-gate avalanche injection MOS) transistor capable of storing charges in a floating gate is employed in each memory cell MC.
FIG. 22 is a cross-sectional view showing structure of a FAMOS transistor. With reference to FIG. 22, the FAMOS transistor includes a control gate 200, a floating gate 210, N type regions 220 and 230 formed on a P type substrate 240, and an insulator layer 250. Floating gate 210 is formed on P type substrate 240 to bridge N type regions 220 and 230, with insulator layer 250 interposed therebetween. Control gate 200 is formed on floating gate 210 with insulator layer 250 interposed therebetween. Control gate 200 and floating gate 210 are both formed of polysilicon. Insulator layer 250 is formed of an oxide film such as SiO.sub.2 or the like. Oxide film 250 formed between P type substrate 240 and floating gate 210 has such a small thickness as of normally approximately 100 .ANG.. Control gate 200 is connected to a corresponding word line 50 in FIG. 21. The one N type region 220 of the two N type regions is connected as a drain of this MOS transistor to a corresponding bit line 30 in FIG. 21. The other N type region 230 is connected as a source of the MOS transistor to a source line 80 which is common to all memory cells MC in FIG. 21. P type substrate 240 is grounded.
In data writing, high voltage pulses of 12 V or less are applied to control gate 200 and drain 220 via word line 50 and bit line 30, respectively. Source 230 is grounded via source line 80. When the high voltage pulses are applied to drain 220, and source 230 is grounded, avalanche breakdown is caused, so that hot electrons are generated in the vicinity of the interface between drain 220 and P type substrate 240. Accordingly, an electric current flows in drain 220. Since the high voltage pulses are also applied to control gate 200, the hot electrons .crclbar. are accelerated by an electric field from control gate 200 and then injected into floating gate 210 through thin oxide film 250 formed between floating gate 210 and P type substrate 240.
The electrons injected into floating gate 220 cannot escape therefrom because floating gate 210 is electrically insulated by oxide film 250. Thus, the electrons once injected into floating gate 210 do not leak out from floating gate 210 but stored therein for a long time even after a power supply is cut off. The state where the electrons are stored in floating gate 210 corresponds to data "0", and the state where no electrons are stored in floating gate 210 corresponds to data "1". Therefore, storage data of memory cells MC are held even after the power supply is cut off. If the electrons are stored in floating gate 210, a threshold voltage of the MOS transistor is raised due to the electric field from the stored electrons. That is, no inversion layer is produced in a channel region unless control gate 200 is supplied with a higher voltage than the voltage enabling an inversion layer to be formed in the channel region when no electrons are stored in floating gate 210.
In erasing of the storage data, a high voltage is applied to source 230 via source line 80, and control gate 200 is grounded via word line 50. This causes a high electric field having a higher potential on source 230 to be applied to a portion between floating gate 210 and source 230. As a result, a tunnel phenomenon occurs in oxide film 250 insulating floating gate 210 and source 230 from each other, so that a current (tunnel current) flows between floating gate 210 and source 230. That is, the electrons leak out from floating gate 210 to source 230 through oxide film 250. Accordingly, the electrons stored in floating gate 210 are removed, so that the threshold voltage of the MOS transistor is lowered. Since source line 80 is commonly connected to respective sources of memory cells MC, as shown in FIG. 21, the storage data of all memory cells MC in memory array 1 are erased in block.
In data reading, control gate 200 and drain 220 are supplied with a supply voltage (normally 5 V) and a voltage relatively close to the supply voltage via corresponding word line 50 and bit line 30, respectively. Source 230 is grounded via source line 80. If no electrons are stored in floating gate 210 (i.e., if storage data is "1"), the threshold voltage of the MOS transistor is low, so that a channel is produced between source 230 and drain 220 in response to the supply voltage applied to control gate 200. If the electrons are stored in floating gate 210 (i.e., if storage data is "0"), however, the threshold voltage of the MOS transistor is high, so that no channel occurs between source 230 and drain 220 even if the supply voltage is applied to control gate 200. Accordingly, the MOS transistor constituting the memory cell, in which the storage data is "1", is turned on in data reading, so that a current flows from corresponding bit line 30 to source line 80. Since the MOS transistor constituting the memory cell, in which the storage data is "0", is in an OFF state even in data reading, no current flows from corresponding bit line 30 to source line 80. Thus, in data reading, a sense amplifier detects whether or not the current flows through a bit line corresponding to the memory cell, from which data is to be read. A determination is made as to whether the storage data is "1" or "0", based on a result of this detection.
If a potential to be applied to bit line 30 in data reading is too high, a high electric field is applied to oxide film 250 formed between floating gate 210 and drain 220, and hence the electrons stored in floating gate 210 are drawn to the drain 220 side. Thus, the potential to be applied to bit line 30 is approximately 1-2 V. Therefore, a small current flows through the memory cell, in which the storage data is "1" in data reading. Thus, a current sense amplifier is employed to detect this small current.
With reference to FIG. 21 again, address input terminals A0-AK receive an externally applied address signal. This address signal serves to instruct which one of memory cells MC in memory array 1 data is to be read from or written in. An address buffer 6 buffers an applied address signal to apply the buffered address signal to a row decoder 4 and a column decoder 5.
An input/output buffer 9 is connected to input/output terminals I/O.sub.0 -I/O.sub.N for receiving input data and output data. Input/output buffer 9 applies write data which is externally applied to input/output terminals I/O.sub.0 -I/O.sub.N to a write circuit 7. Further, input/output buffer 9 provides data supplied from a sense amplifier 8 to input/output terminals I/O.sub.0 -I/O.sub.N as read data.
Write circuit 7 supplies a voltage corresponding to the write data applied from input/output buffer 9 to a Y gate 2. Sense amplifier 8 detects an output of Y gate 2 and, in response to a result of the detection, supplies a signal voltage corresponding to data "0" or "1" as read data to input/output buffer 9.
Row decoder 4 responds to the address signal from address buffer 6 to select one of word lines 50 in memory array 1. Column decoder 5 responds to the address signal from address buffer 6 to select one of bit lines 30 in memory array 1.
A control circuit 140 controls Y gate 2, column decoder 5, write circuit 7, address buffer 6, input/output buffer 9 and sense amplifier 8 so that they can perform an operation corresponding to each mode.
A terminal T.sub.PP is supplied with an external high voltage V.sub.PP. A terminal T.sub.CC is supplied with an external supply voltage V.sub.CC of a normal level. A switch circuit 400 selectively outputs to predetermined circuitry one of the high voltage V.sub.PP and supply voltage V.sub.CC applied respectively to terminals T.sub.PP and T.sub.CC.
Switch circuit 400 is controlled by control circuit 140 to supply the high voltage V.sub.PP from terminal T.sub.PP to row decoder 4 in data writing. Further, switch circuit 400 is controlled by control circuit 140 to apply the supply voltage V.sub.CC to row decoder 4 in data reading. Switch circuit 400 is further controlled by control circuit 140 to supply the high voltage V.sub.PP to a source line switch 3 in data erasing.
In data writing, Y gate 2 supplies the voltage applied from write circuit 7 to a bit line selected by column decoder 5. Specifically, if write data is "0", Y gate 2 supplies the high voltage V,, to the selected bit line. If the write data is "1", Y gate 2 holds a potential on the selected bit line at a ground potential. In data writing, row decoder 4 supplies the high voltage V.sub.PP from high voltage switch circuit 400 to a selected word line. In data writing, source line switch 3 applies the ground potential to source line 80. Therefore, if the write data is "0", the electrons generated by avalanche breakdown are injected only into floating gate 210 of a memory transistor (a selected memory transistor) located at the cross-over point between the word line selected by row decoder 4 and the bit line selected by column decoder 5. If the write data is "1", however, no electrons are injected into floating gate 210 since the voltage of control gate 200 is not boosted in the selected memory transistor.
In data reading, row decoder 4 supplies a supply voltage V.sub.CC applied from switch circuit 400, which is lower than the above-described high voltage V.sub.PP, to the selected word line. In data writing, Y gate 2 supplies a low voltage of 1-2 V to the bit line selected by column decoder 5. In data reading, source line switch 3 applies a ground potential to source line 80 like the case in data writing. Accordingly, if storage data of the selected memory transistor is "1", a current flows from the selected bit line through drain 220, the channel region and source 230 of the selected memory cell to source line 80. If the storage data of the selected memory transistor is "0", the selected memory transistor is not turned on in response to a gate voltage of approximately 5 V, so that no current flows through the selected bit line. Y gate 2 supplies a supply voltage to the selected bit line and also electrically connects only the selected bit line to sense amplifier 8. This enables sense amplifier 8 to detect whether the current flowing through the selected bit line exists or not.
In data erasing, Y gate 2 maintains all bit lines 30 in memory array 1 at a lower potential (ground potential). Row decoder 4 supplies the ground potential to all word lines 50 in memory array 1, in data erasing. Source line switch 3 converts the high voltage V.sub.PP applied from switch circuit 400 into a pulse signal, to apply the pulse signal to source line 80. Therefore, in data erasing, a tunnel phenomenon occurs in each of all memory cells MC in memory array 1, so that the electrons stored in floating gate 210 of the memory transistor, in which the storage data is "0", are removed from floating gate 210. Accordingly, when the data erasing is completed, the storage data of all memory cells MC in memory array 1 are "1".
It is assumed in the following description that the supply potential and the ground potential correspond to a logic high level (or the H level) and a logic low level (or the L level), respectively.
As described in the foregoing, in the EEPROM, data erasing is carried out by forcing the bending of an energy band between floating gate 210 and source 230 so as to make electrons to tunnel from floating gate 210 to source 230, with a high voltage applied between control gate 200 and source 230 of the memory transistor in data erasing. Thus, the amount of electrons drawn out from floating gate 210 varies depending on the magnitude of a high voltage to be applied to source line 80, the time period in which the high voltage is applied (i.e., the pulse width of high voltage pulses), the thickness of oxide film 250 existing between floating gate 210 and source 230, the thickness of oxide film 250 existing between floating gate 210 and control gate 200, and the like.
There are irregularities in manufacture of memory transistors constituting memory array 1. Because of the irregularities, the thickness of oxide film 250, the form of control gate 200 and floating gate 210, the length of the channel region, and the like are not completely uniformed in all memory transistors. It is actually difficult to simultaneously set the storage data of all memory cells MC in memory array 1 to "1" by the above-described collective erasing, due to the irregularities on manufacture of the memory transistors and other various factors such as some causes in actual circuit configurations. More specifically, in some of the memory transistors, in which the storage data is "0", only the stored electrons are completely removed from floating gate 210 in response to a high voltage applied in collective erasing, whereas in the other memory transistors, a larger amount of electrons than those stored in data writing are drawn out from floating gate 210 in response to the high voltage applied in collective erasing. The phenomenon of the latter case, in which the electrons are excessively drawn out from the floating gate, is called an excess erase.
When an excess erase occurs, floating gate 210 is charged to plus, so that an inversion layer is produced between source 230 and drain 220. This means that this memory transistor is in an ON state even if any potential of 0 V or more is applied to control gate 200. As a result, in data reading, a current flows through a bit line corresponding to this memory transistor despite the fact that the transistor is in a non-selection state. Thus, if a memory cell connected to the bit line corresponding to the memory transistor subjected to the excess erase is selected, read data is "1" even in case where storage data of the selected memory transistor is "0". In data writing, if data "0" is intended to be written in the excess-erased memory cell or the memory cell connected to the same bit line as that of the excess-erased memory cell, a current flows not only through the selected memory cell but also the excess-erased memory cell, so that sufficient avalanche breakdown is not generated in the selected memory cell. Thus, electrons are not sufficiently injected into floating gate 210 of the selected memory cell. Accordingly, if the excessively erased memory cell exists, writing characteristics in data writing deteriorate, and further, data writing is disabled. As described above, the excess erase causes troubles in data reading and data writing.
In order to prevent such an excess erase, the following method is adopted at present. That is, the pulse width of a high voltage pulse (hereinafter referred to as erase pulse) to be applied to source line 80 for data erasing is made smaller. Every time this erase pulse having the shorter pulse width is applied to source 80 once, the storage data of all the memory cells in memory array 1 are read, so as to check whether or not all the storage data of memory cells MC in memory array 1 are "1". If there is even one memory cell in which the storage data is not "1", the erase pulse of the shorter pulse width is again applied to source line 80. The confirmation as to whether or not the storage data of the memory cells are "1" after the erase pulse is applied to source line 80, i.e., whether or not the storage data of the memory cells are completely erased, is called erase verifying. Such erase verification and such application of the erase pulse to source line 80 are repeated until the data erasing is completed with respect to all memory cells MC in memory array 1. FIG. 23 is a block diagram showing configuration of a flash EEPROM in which an excess erase is prevented by such a method. This flash EEPROM is stated in ISSCC Digest of Technical Papers (1990), pp. 60-61 and Electronic Information Communication Society Technical Research Papers (May 21, 1990), pp. 73-77.
With reference to FIG. 23, this flash EEPROM includes an erase control circuit 11 for performing erase verification. Erase control circuit 11 is connected to a source line switch 3, a row decoder 4, a column decoder 5, an address buffer 6, a sense amplifier 8 and a mode control circuit 10. An internal configuration of erase control circuit 11 is shown in detail in FIG. 24. FIG. 25 is a circuit diagram showing the structure of a memory array 1 and Y gate 2 and the connecting relation between memory array 1 and Y gate 2 and peripheral circuits in case where memory array 1 includes 9 memory transistors arranged in matrix of 3 rows and 3 columns by way of example. FIG. 26 is a timing chart showing an operation of this flash EEPROM in data erasing. A description will now be made of the structure and operation of the flash EEPROM mainly in data erasing, with reference to FIGS. 24-26.
With reference to FIG. 24, erase control circuit 26 includes a command signal latch circuit 112, a sequence control circuit 113, a verify voltage generator 114 and a voltage switch 115. Command signal latch circuit 112 receives only a status polling command signal of control signals to be applied from mode control circuit 10, the signal indicating that this flash EEPROM enters in an erase mode. Sequence control circuit 113 is circuitry for controlling the generation of erase pulses and a circuit operation for erase verifying. Verify voltage generator 114 supplies a voltage of 3.4 V lower than a normal supply voltage of 5 V to voltage switch 115. In data writing, voltage switch 115 changes a high voltage V.sub.PP (=12 V; FIG. 1(b)) to be supplied to a selected word line and a selected bit line, normal supply voltage V.sub.CC (=5 V; FIG. 26(a)) and the voltage of 3.4 V to be supplied from verify voltage generator 114, in data writing, normal data reading and erase verifying, so as to output those changed voltages as outputs. The outputs of voltage switch 115 are applied to row decoder 4, column decoder 5 and sense amplifier 8.
Sequence control circuit 113 includes an address counter 116, an erase/erase verifying control circuit 117, a decoder control circuit 119 and an erase pulse generator 118. Address counter 116 is controlled by command signal latch circuit 112 and erase/erase verifying control circuit 117 so as to output address signals, sequentially designating the memory cells in memory array 1 in the order of address, to address buffer 6 in a data erase mode. Erase/erase verifying control circuit 117 is controlled by command signal latch circuit 112 so as to control verify voltage generator 114, address counter 116, decoder control circuit 119 and erase pulse generator 118 in response to read data applied from sense amplifier 8. Erase pulse generator 118 is controlled by erase/erase verifying control circuit 117 so as to supply, if necessary, erase pulses having a pulse width 10 msec to source line switch 3. Decoder control circuit 119 is controlled by mode control circuit 10 and erase/erase verifying control circuit 117, to instruct row decoder 4 to output a voltage of a logic low level only during the period when erase pulses are generated from erase pulse generator 118.
Mode control circuit 10 performs a mode setting of this flash EEPROM in response to external control signals such as an erase enable signal EE, a chip enable signal CE, an output enable signal OE, a program signal PGM and the like. Erase enable signal EE is a control signal for enabling/disabling an erasing operation of the flash EEPROM. Chip enable signal CE is a control signal for enabling/disabling an operation of this flash EEPROM chip. Output enable signal OE is a control signal for enabling/disabling a data output operation of the flash EEPROM. Program signal PGM is a control signal for enabling/disabling a data writing operation of the flash EEPROM. All of these erase enable signal EE, chip enable signal CE, output enable signal OE and program signal PGM are low active signals. More specifically, erase enable signal EE designates the enabling of an erasing operation when it is at a logic low level. Conversely, this signal designates the disabling of the erasing operation when it is at a logic high level. Chip enable signal CE also designates the enabling of a chip operation only when it is at a logic low level. Output enable signal OE also designates the enabling of a signal output operation only when it is at a logic low level. Program signal PGM also designates the enabling of a writing operation only when it is at a logic low level.
With reference to FIG. 26, when chip enable signal CE (FIG. 26(d)) is at a logic low level and thus this flash EEPROM chip is enabled, the flash EEPROM enters in the erase mode if erase enable signal EE (FIG. 26(g)) is held at a logic low level for a definite time period t.sub.EW (=50 nsec). At this time, output enable signal OE (FIG. 26(e)) and program signal PGM (FIG. 26(f)) both attain a logic high level so that externally applied data may not be written in memory array 1, and storage data of memory array 1 may not be read out to the outside. Mode control circuit 25 detects that erase enable signal EE attains a logic low level for the definite period t.sub.EW when output enable signal OE and program signal PGM are both at a logic high level and chip enable signal CE is at a logic low level. In response to this detection, mode control circuit 10 outputs a signal designating the erase mode to command signal latch circuit 112 and decoder control circuit 119.
In the erase mode, data "0" is first written in all the memory cells in memory array 1. A circuit operation for this writing will now be described.
When the erase mode is designated by mode control circuit 10, command signal latch circuit 112 latches an erase mode designating output of mode control circuit 10 and also applies this output to address counter 116 and erase/erase verifying control circuit 117. Address counter 116 responds to the erase mode designating output to start a counting operation to generate an address signal (FIG. 26(c)). Address counter 116 outputs an address signal indicating a subsequent address to the address indicated by the address signal that has been output so far, every time a count value thereof is incremented by one. Thus, the address signal is output from address counter 116 while being incremented each definite time. In the erase mode, address buffer 6 accepts the address signal generated from address counter 116 to apply the same to row decoder 4 and column decoder 5. Erase/erase verifying control circuit 117 responds to the applied erase mode designating output to control row decoder 4, column decoder 5 and write circuit 7. Row decoder 4 is controlled by erase/erase verifying control circuit 117 so as to select a single word line in memory array 1 in response to the address signal accepted by address buffer 6. Column decoder 5 is controlled by erase/erase verifying control circuit 117 so as to select a single bit line in memory array 1 in response to the address signal accepted by address buffer 6.
A description will now be made on the internal structure of memory array 1 and Y gate 2. With reference to FIG. 25, memory transistors MC are each provided in the corresponding cross-over points between word lines WL1-WL3 connected to row decoder 4 and bit lines BL1-BL3 connected to Y gate 2. Each of memory transistors MC has the structure shown in FIG. 22. Respective sources of all memory transistors MC are commonly connected to source line 80 connected with source line switch 3. Y gate 2 includes an I/O line 27 connected to write circuit 7 and sense amplifier 8, and N channel MOS transistors TR1-TR3 provided as transfer gates between I/O line 27 and bit lines BL1-BL3, respectively. Respective gates of transistors TR1-TR3 are connected via different connecting lines Y1-Y3 to column decoder 5. As described above, connecting lines Y1-Y3 each correspond to bit lines BL1-BL3 in the correspondence of one to one.
Row decoder 4 responds to an applied address signal to selectively output a high voltage V.sub.PP to any one of word lines WL1-WL3 in memory array 1. Column decoder 5 responds to an applied address signal to selectively apply a voltage of a logic high level to only one of connecting lines Y1-Y3 in Y gate 2. Accordingly, only one of transfer gates TR1-TR3, which is provided corresponding to the selected connecting line, is turned on, so that only one of bit lines BL1-BL3 corresponding to the selected connecting line is electrically connected to I/O line 27.
Write circuit 22 is controlled by erase/erase verifying control circuit 117 so as to apply a high voltage V.sub.PP to I/O line 27. I/O line 27 is electrically connected only to the bit line selected by column decoder 5. Thus, the high voltage V.sub.PP applied to I/O line 27 is applied only to the selected bit line (one of bit lines BL1-BL3). Source line switch 3 supplies a ground potential to source line 80.
As the result of such a circuit operation, electrons caused by avalanche breakdown are injected into the floating gate only in one memory transistor of memory transistors MC in memory array 1, corresponding to the address signal generated by address counter 116. The address signal applied to address buffer 6 is kept incremented by the counting operation of address counter 11 until all memory transistors MC in memory array 1 are selected. Thus, a selecting operation of row decoder 4 and column decoder 5 brings memory transistors MC in memory array 1 sequentially into a selection state in the order of address, so that the electrons are injected into the floating gate of each memory transistor. As a result, data "0" is written in all memory cells 30 in memory array 1. If the address signal supplied as an output from address counter 116 is incremented up to a final value, the data writing into memory array 1 is completed. With the data writing completed, a circuit operation for data erasing starts. A description will now be made on the circuit operation for data erasing.
First, erase/erase verifying control circuit 117 instructs erase pulse generator 118 to generate erase pulses. In response to this instruction, erase pulse generator 118 applies high voltage pulses having a predetermined pulse width of 10 msec as erase pulses to source line switch 3. Source line switch 3 applies the applied erase pulses to source line 80 of FIG. 25.
At the same time, erase/erase verifying control circuit 117 applies a signal instructing decoder control circuit 119 to start an erasing operation. In response to the applied signal, decoder control circuit 119 supplies as an output a control signal for forcing all outputs of row decoder 4 to attain a logic low level during the period when the decoder control circuit is receiving the erase pulses from erase pulse generator 118. Accordingly, word lines WL1-WL3 of FIG. 25 are supplied with a potential of a logic low level during the period when source line 80 is supplied with high voltage pulses. As a result, the tunnel phenomenon, in which the electrons injected into the floating gate in data writing are drawn out through the insulator layer to the source region, occurs in each of memory transistors MC in memory array 1.
When the application of the high voltage pulses to source line 80 is completed, a verification is made as to whether or not data "0" of all memory cells MC in memory array 1 are erased, according to the application of the high voltage pulses. That is, an erase verifying is carried out. A description will now be given of a circuit operation in erase verifying.
When the generation of the high voltage pulses from erase pulse generator 118 is completed, erase/erase verifying control circuit 117 instructs address counter 116 to start a counting operation and also instructs decoder control circuit 119 to start an erase verifying operation. Further, erase/erase verifying control circuit 117 instructs verify voltage generator 114 to generate/output a voltage of 3.4 V. Address counter 116 generates an address signal in response to the instruction from erase/erase verifying control circuit 117. Decoder control circuit 119 responds to the instruction from erase/erase verifying control circuit 117 to output a control signal for operating row decoder 4 and column decoder 5 in the same manner as in normal data reading. Verify voltage generator 114 responds to the instruction from erase/erase verifying control circuit 117 to supply the voltage of 3.4 V to voltage switch 115.
The address signal generated from address counter 116 is accepted by address buffer 6, to be applied to row decoder 4 and column decoder 5. Voltage switch 115 supplies the voltage of 3.4 V applied from verify voltage generator 114 to row decoder 4 and sense amplifier 8.
Row decoder 4 is controlled by decoder control circuit 119 to supply the voltage of 3.4 V applied from voltage switch 115 to only a single word line of word lines WL1-WL3 in memory array 1, corresponding to the address signal applied from address buffer 6, and hold potentials on the other word lines at a logic low level. Accordingly, the voltage of 3.4 V is applied to the respective control gates of all the memory transistors connected to the selected word line in memory array 1. Column decoder 5 is controlled by decoder control circuit 119 to supply a voltage of a logic high level to only one of connecting lines Y1-Y3 in Y gate 2, corresponding to the address signal applied from address buffer 6, and hold potentials on the other connecting lines at a logic low level. Thus, only one of transfer gates TR1-TR3, corresponding to the selected connecting line, is turned on in Y gate 2. As a result, only the selected bit line of bit lines BL1-BL3 is electrically connected to I/O line 27. Sense amplifier 8 is driven at the voltage of 3.4 V applied from voltage switch 115 to detect a current flowing through I/O line 27. Source line switch 3 grounds source line 80 when no erase pulses are applied from erase pulse generator 118. Thus, in erase verifying, the respective voltages of 3.4 V and 0 V are applied to the control gate and the source of the selected memory transistor in memory array 1.
If no electrons are stored in the floating gate of the selected memory transistor, i.e., if the threshold voltage of the selected memory transistor is lower than a predetermined value, the selected memory transistor is rendered conductive in response to the voltage of 3.4 V applied from row decoder 4. Thus, a current flows from I/O 27 via the selected transfer gate and the selected bit line to source line 80. The predetermined value is set for an average threshold voltage of the memory transistors, in which no data is written. Therefore, if the electrons stored in the floating gate of the selected memory transistor in data writing are completely removed in response to the foregoing erase pulses, the current flows through the selected bit line. If the electrons remain in the floating gate of the selected memory transistor, however, the threshold value of the selected transistor does not fall down to the predetermined value. Thus, the selected memory transistor is not rendered conductive in response to a gate voltage of 3.4 V applied from row decoder 4, so that no current flows through the selected bit line. Thus, if storage data of the selected memory cell is completely erased, a current flows through I/O line 27. Conversely, if the storage data of the memory cell is not completely erased, no current flows through I/O line 27.
Sense amplifier 8 operates in the same manner as in normal data reading, so as to make a determination, based on the presence/absence of the current flowing through I/O line 27, as to whether or not a current flows through the selected bit line. If no current flows through the selected bit line, then sense amplifier 8 applies a signal corresponding to data "0" as read data to erase/erase verifying control circuit 117. Conversely, if a current flows through the selected bit line, sense amplifier 8 applies a signal corresponding to data "0" as read data to erase/erase verifying control circuit 117. Erase/erase verifying control circuit 117 responds to the data applied from sense amplifier 8 being "1" to instruct address counter 116 to increment an address signal. Also, this erase/erase verifying control circuit 117 successively controls verify voltage generator 114 and decoder control circuit 119 in the same manner as so far. Further, this control circuit 117 responds to the data read by sense amplifier 8 being "0" to control erase pulse generator 118 and decoder control circuit 119 like in the previous erase pulse application so that all word lines WL1-WL3 in memory array 1 may be grounded by row decoder 4 and high voltage pulses may be applied to source line 80.
Therefore, if the storage data of the selected memory cell is "1", i.e., if the electrons are completely removed from the floating gate of the selected memory transistor, the address signal generated from address counter 116 is incremented. Then, the storage data of the memory cell corresponding to the incremented address signal is read by sense amplifier 8. Conversely, if the storage data of the selected memory cell is "0", i.e., if the electrons are not completely removed from the floating gate thereof, erase pulses are again applied to all memory transistors MC in memory array 1. As described above, erase/erase verifying control circuit 117 selectively performs, in the erase mode, a control operation for reading data from a new memory cell or a control operation for applying erase pulses again to memory array 1, in response to each of read data applied from sense amplifier 8 after data writing. More specifically, erase/erase verifying control circuit 117 detects the memory cell, in which no data is erased, based on an output of sense amplifier 8 and, in response to this detection, circuit 117 again generates the erase pulses.
Specifically, if the first erase pulse is applied to memory array 1, erase/erase verifying control circuit 117 does not instruct the re-generation of another erase pulse so far as read data applied from sense amplifier 8 is not "0". Thus, data is read in the order of address from memory array 1 after the first erase pulse application until the data read by sense amplifier 8 is "0". Then, when the read data is "0", the second erase pulse is applied to memory array 1 by the control operation of erase/erase verifying control circuit 117. Data is again read from memory array 1 after the second erase pulse application. At this time, since an address signal generated from address counter 116 is not incremented, the data, which is first read after the second erase pulse application, is storage data of the previous memory cell, in which the read data is "0" after the first erase pulse application. If the storage data of this memory cell attains "1" in response to the second erase pulse, erase/erase verifying control circuit 117 increments the address signal, so that data is read from the next address 1. If the data of this memory cell is still "0" even after the second erase pulse application, however, the third erase pulse is applied to memory array 1 by the control operation of erase/erase verifying control circuit 117.
As in the foregoing manner, after the first erase pulse is applied to memory array 1, the storage data of the memory cell is sequentially read in the order of address, and the data reading is interrupted at the time when the memory cell, in which the data is not completely erased in response to the first erase pulse, is detected. Then, erase pulses are repetitively applied to memory array 1 until the storage data of this detected memory cell is "1". As a result, when the storage data of the detected memory cell is completely erased, the data reading restarts with an address next to the address of the detected memory cell. Then, such a circuit operation is repeated every time the data to be read is "0" so that the memory cell, in which the data is not completely erased, is detected. Thus, such a process that the address generated from address counter 116 is incremented to a maximal value, so that the reading of data from all memory cells MC in memory array 1 is completed means that the storage data of all memory cells MC in memory array 1 are completely erased.
If the data reading from all memory cells MC is completed, erase/erase verifying control circuit 117 resets latch data of command signal latch circuit 112. The signal latched in command signal latch circuit 112 is output as a status signal. Accordingly, it can be recognized based on a potential of input/output terminal I/O 7 whether or not a circuit operation for data erasing (the application of erase pulses and the erase verifying operation) continues. Specifically, with reference to FIG. 26, after erase enable signal EE attains a logic low level for a definite period t.sub.EW to enter in the erase mode, chip enable signal CE attains a logic low level so as to enable the operation in response to an external signal of this flash EEPROM. Further, output enable signal OE attains a logic low level so as to enable the output operation of a signal from input/output terminals I/O 0-I/O 7 of the flash EEPROM, and erase enable signal EE attains a logic low level. In response to this, the flash EEPROM enters in a status polling mode in which a signal of a logic low level or a logic high level appears on input/output terminal I/O 7 in accordance with an internal circuit operation. In the status polling mode, the signal appearing on input/output terminal I/O 7 attains a logic low level when the circuit operation for data erase continues, and conversely, it attains a logic high level when the circuit operation for data erase is completed, as shown in FIG. 26(h). In this flash EEPROM, the time required for a series of operations for data erasing including the data writing into all memory cells MC in memory array 1 (erase time) is typically approximately 1 sec, which is the time period t.sub.ET from the time when erase enable signal EE attains a logic low level for definite period t.sub.EW to the time when the signal appearing on input/output terminal I/O 7 attains a logic high level in the status polling mode.
In order to ensure an operation margin in data reading, the voltage to be applied to the control gate and the drain of the memory transistor for data reading should be the voltage of 3.4 V lower than a normal supply voltage of 5 V, in erase verifying. That is, if the data reading in erase verifying is carried out by application of such a high inherent supply voltage as of approximately 5 V to the control gate of the memory transistor, the following disadvantage might occur.
More specifically, in a memory transistor which is not rendered conductive unless a gate voltage is boosted up to approximately 5 V of the inherent supply voltage, data "1" is read in erase verifying, whereas data "0" is read if the supply voltage becomes lower than the inherent level of 5 V in normal data reading. Even if this memory transistor is rendered conductive with its control gate supplied with a voltage lower than the inherent supply voltage, the transistor is not completely turned on, so that only a small amount of current flow through the bit line. This causes an increase in the time period when the data to be read by the sense amplifier becomes correct data "1" corresponding to the storage data of the transistor. That is, the access time in reading is delayed. Thus, the data reading is carried out by application of the voltage lower than the inherent supply voltage to a selected word line so that a determination is made that only a memory transistor, the threshold voltage of which is sufficiently low, is the memory transistor in which data erase is completed, in erase verifying.
Since this flash EEPROM automatically repeats the erase pulse application and the erase verifying operation in the erase mode, it requires no external control signal.
In normal data reading, address buffer 6 accepts externally applied address signals at its address terminals A0-A16 and then applies the same to row decoder 4 and column decoder 5.
As has been described heretofore, the conventional flash EEPROM repeats the cycle in which the erase pulse having a short pulse width is first applied to the memory array, and then the erase verifying is carried out, in order to prevent an excess erase. Thus, if the memory cell, in which data is not completely erased, is detected by the erase verifying operation, the erase pulse is again applied to all the memory cells in the memory array. Accordingly, the erase pulses applied again to the memory array serve to remove the electrons stored in the floating gate in data writing in the memory transistor, in which data is not yet completely erased. Conversely, the applied erase pulses serve to draw out the electrons originally existing in the floating gate therefrom in the memory transistor, in which data is already completely erased. Consequently, when the data erasing is completed with respect to memory cells in which data is less easily erased, an excess erase occurs in memory cells in which data is easily erased.
Larger the differences in easiness of data erasing between the memory cells constituting the memory array are, larger the differences in the number of erase pulses required for a complete erase of data between the memory cells constituting memory array 1 are. There is a case where the erase pulses, which are again applied so as to completely erase the data of the memory cell detected by erase verifying, cannot perform a complete data erase with respect to the memory cell, in which data is less easily erased than the detected memory cell. In this case, the erase pulses are again applied to all the memory cells in the memory array at the time when the memory cell, in which data is less easily erased, is detected by the next erase verifying operation. Therefore, as there are larger differences in easiness of data erasing between the memory cells constituting the memory array, the number of the erase pulses applied to the memory array before the data erasing is completed with respect to the memory cell, in which data is least easily erased (i.e., before the data of all the memory cells in the memory array are completely erased) increases. Thus, it is highly possible that an excess erase occurs in many memory cells when the erasing operation is completed.
The differences in easiness of data erasing between the memory cells constituting one memory array are due to various factors in the manufacture and the circuit configuration of the device, as described above. Such differences increase with an increase in the number of memory cells constituting one memory array. Therefore, a recent increase in the capacity of semiconductor memory devices, i.e., an increase in the number of bits makes the foregoing disadvantage more significant.
Incidentally, when a gate voltage is 0 V in an N channel MOS transistor, an inter-band tunneling phenomenon occurs in an overlapping region of a gate and a drain diffusion region. This phenomenon also occurs in an overlapping region of the gate and a source diffusion region when a source potential is high. The inter-band tunneling occurs When the surface of N type drain and source diffusion regions is in a deep depletion state since the gate voltage is 0 V. If the surface of these N type diffusion regions is in the deep depletion state, then an energy band at the boundary between a substrate and an oxide film beneath the gate curves sharply. Thus, electrons of a valence electron band tunnel to a conduction band in the N type diffusion regions. Holes generated at this time flow into the grounded substrate, while the electrons that have tunneled to the conduction band are focused into the N type diffusion regions. A current generated by the flow of the holes into the substrate becomes a leakage current of this N channel MOS transistor. In data erasing, since a high voltage is applied to source 230 of the memory transistor and control gate 200 is thus grounded, such an inter-band tunneling phenomenon occurs.
Referring again to FIG. 27, it is known that the inter-band tunneling phenomenon occurs at a portion 260 in the vicinity of source 230 at an interface between substrate 240 and oxide film 250, in data erasing. Since substrate 240 is grounded, the holes generated by this phenomenon flow as a leakage current to the substrate 240 side, and the electrons that have tunneled to the conduction band flow to the source 230 side together with the electrons drawn out from floating gate 210. The inter-band tunneling phenomenon in the flash EEPROM is described in the article entitled "Subbreakdown Drain Leakage Current in MOSFET", IEEE Electron Device lett., vol. EDL-8, 1987, pp. 515-517 by J. Chen et al., and the article entitled "A FLASH-ERASE EEPROM CELL WITH AN ASYMMETRIC SOURCE AND DRAIN STRUCTURE", IEEE Tech. Dig. of IEDM 1987, 25. 8, pp. 560-563 by H. Kume et al. According to these documents, a leakage current generated by the inter-band tunneling phenomenon is approximately 10.sup.-8 A for one memory transistor when the potential of source 230 is approximately 10 V. Accordingly, in the case of a 1M bit flash EEPROM, if high voltage pulses of 10 V are applied to source 230 for data erasing, then a leakage current generated in data erasing is 10 mA. This leakage current causes such various problems as heat generation of chips due to an increase in power consumption, and a decrease in supply voltage. In general, the tolerance of such a leakage current is several 10 mA or less. However, with the capacity of semiconductor apparatus having been increased in recent years, the number of memory transistors of a flash EEPROM has been increased, and the capacity of the flash EEPROM has also been increased up to approximately 16M bit at present. In the case of a 16M bit flash EEPROM, for example, if data erasing is carried out in response to high voltage pulses of 10V, then a leakage current developed in data erasing is 10 mA.times.16, i.e., 160 mA, the value largely exceeding the tolerance. Since a voltage to be applied to source 230 for data erasing is 12 V in practice, the actual magnitude of the leakage current is further larger than that value. In such a circumstance, the leakage current generated in data erasing should be reduced as much as possible.
Even if data erasing utilizing the tunnel phenomenon is carried out without the generation of the leakage current due to the inter-band tunneling phenomenon, a current generated by the drawing of electrons from floating gate 210 to source 230 becomes significantly large in each erase pulse application when a large number of memory cells are data-erased simultaneously. Therefore, from the view point of power consumption, it is desirable that the total amount of the current generated by such electron drawing in each erase pulse application is small.
As described above, with the number of memory cells constituting one memory array increasing, a problem of the increase in power consumption in data erasing becomes remarkable.

Nonvolatile semiconductor memory device and data erasing method thereof


An apparatus including a fixing assembly for fixing an image onto a medium as the medium travels in a path through the assembly, the fixing assembly having a wide nip along the path of travel of the medium formed by a pair of nip forming rollers, at least one of which rollers contains a hydraulic fluid and maybe heated. The hydraulic roller has an aluminum core encased in a sealed stainless steel flexible hydraulic sleeve. In the space between the core and sleeve of each roller is a pressurized fluid. The apparatus also has a hydraulic piston for pressurizing the fluid.

The instant invention relates to an apparatus and process for fixing toners or other materials on a medium. Subsequent to development of an image, the developed image is transferred to a receiving medium. After the transfer to the receiving medium, pressure and/or heat are applied to the receiving medium as the receiving medium and the developed image pass through a nip formed by a pair of rollers. By pressure and/or heat being applied, at the nip, to the receiving medium, the developed image is permanently fixed to the receiving medium.
As in any apparatus for fixing toners or other materials, the feeding and contact parameters, as the receiving medium passes through the nip, are critical. Without the proper feeding and contact parameters various problems, in and about the nip, result such as:
1. Defects in the fixed image caused by localized stresses in the nip mechanics during the fixing process. PA1 2. Inefficient thermal conductivity for internally heated rollers causing an increase in the time needed for the fixing roller to reach operational temperatures. PA1 3. Nip width directly related to the fixing pressure. PA1 4. Excessive drive torque that creates paper grab and deformation. PA1 5. Velocity changes in the nip causing image distortion. PA1 6. Static charge in the nip causing image distortion. PA1 7. Excessive roller wear. PA1 8. Artifacts such as rivers and lakes or toner smear caused by local stress in the nip. PA1 9. An arched nip resulting in paper curl or loss of paper stiffness. PA1 10. The need for large rollers to create wide flat nips. PA1 1. Minimal defects in the fixed image caused by localized stresses in the nip mechanics during the fixing process. PA1 2. Efficient thermal conductivity for internally heated rollers, thereby reducing the time needed for the heated roller to reach operational temperatures. PA1 3. A nip width minimally related to the fixing pressure. PA1 4. Reduced nip drive torque with minimal paper grab and deformation. PA1 5. Virtually no velocity change in the nip. PA1 6. Virtually no static charge in the nip. PA1 7. Virtually no roller wear. PA1 8. Virtually no artifacts such as rivers and lakes or toner smear. PA1 9. A symmetrical flat nip to prevent paper curl or lost of paper stiffness. PA1 10. A compact unit, using small rollers, capable of having a wide flat nip width.
In the past, to avoid feeding and contact problems, such as above stated, and to prevent the movement of the toner particles and the localized stress that caused defects or distortion of a image, one would change the compliancy of one or more of the rollers in the fixing assembly to lessen the effect of such process-related defects. Attempts made to increase the compliancy and to thereby lessen the fixing related image defects included making the elastomeric layers thicker and using an elastomeric foam material such as disclosed in U.S. Pat. No. 4,814,819. However, since fixing rollers are usually heated internally, it was difficult to obtain an elastomeric material that was sufficiently compliant while having a heat conductivity that efficiently provided the necessary heat to fix the toner images. Therefore, these attempted solutions proved unsatisfactory.


An interactive type numerical control apparatus having an interactive type data input function for controlling the operation of a machine tool by creating a machining program based on input data. A composite tool (3) able to carry out a plurality of different machining operations is selected and an NC sentence is created based on data input designating the tool path of the composite tool (3). With this arrangement, a plurality of different numerically controlled NC machining operations can be effectively executed by the composite tool (3).

An interactive type numerical control apparatus designates a tool in accordance with a created machining program, and outputs a command to a machine tool for sequentially machining a raw material. When this machining program is created, different machining operations, such as bar machining, trace machining, fillet machining, face machining, screw machining, groove machining and the like, are selected and the tools and cutting conditions are automatically determined based on input data.
Accordingly, tools and cutting conditions optimum for the different machining operations for the raw material are designated, to thereby shorten a machining cycle time and obtain a more effective operation of the machine tool.
Recently, a tool capable of performing a plurality of different machining operations has been developed, and an effective operation of such a machine tool further shortens the machining cycle time. For example, a Cut-Grip (Trade Mark) tool having a composite function with cutting blades at both the front and side, for arbitrarily effecting a cutting operation in any direction, can perform an outside diameter machining, face machining, trick machining and inside diameter machining, without changing the tool.
When a cutting operation and groove machining operation are performed by using a tool having such composite functions, without changing the tool, a time necessary for changing the tool is further reduced and the programming therefore can be simplified.
Further, in general, when a machining program including an outside diameter cutting operation and a groove machining operation is created by an interactive type numerical control apparatus, configuration data for each of the two operations is input in accordance with a different set screen.
Nevertheless, when data is input through a different set screen each time a type of machining is changed in the creation of a program effected by using an interactive type numerical control apparatus, the program cannot be effectively created. Further, unless a machine tool is operated in accordance with a machining program that makes the best use of the features of the tool having a composite function, a cycle time cannot be always shortened.
Also, preferably when a composite tool is not fitted as the machine tool, the same machining can be realized by using conventional tools with a single cutting blade.

Interactive type numerical control apparatus and method thereof


Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; amounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory.

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including solder balls, for example.
The specification of U.S. Pat. No. 7,009,115 (FIG. 5B) discloses a BGA (Ball Grid Array) type semiconductor device. The BGA type semiconductor device includes solder balls arranged in an array. In the semiconductor device, lines are formed on a mounting board so as to pass through a space between the solder balls. Specifically, the lines are formed in the space between the solder balls in such a manner that a line connected to a certain solder ball is not connected to another solder ball.
Along with the enhanced functonality, speed-up, and miniaturization of semiconductor devices, there is a demand for increasing the number of balls (signal lines) and narrowing a pitch. In the BGA having a narrow pitch, the number of lines passing through the space between balls is reduced. In the specification of U.S. Pat. No. 7,009,115 (FIG. 5B), some of the solder balls are removed to allow lines to pass through the space between the balls. This results in a reduction in the number of balls, that is, the number of signals.
Other problems to be solved and novel features will be apparent from the description of the specification and the accompanying drawings.


A portable electronic device includes a host module, a display module, a pivoting mechanism and a moving component. The pivoting mechanism is connected to the host module and the display module and for pivoting the host module relative to the display module. The pivoting mechanism includes a base and a pivoting unit. The pivoting unit includes a lower pivoting component and an upper pivoting component. The lower pivoting component is installed on the base. The upper pivoting component is pivotally connected to the lower pivoting component in a first pivoting direction and installed on the display module, so that the display module rotates relative to the host module in the first pivoting direction. The moving component contacts an upper surface of the host module and moves relative to the upper surface as the display module rotates relative to the host module in the first pivoting direction.

1. Field of the Invention
The present invention relates to a portable electronic device, and more especially, to a portable electronic device capable of pivoting stably.
2. Description of the Prior Art
There are two using modes of a rotatable notebook computer in the market presently. It can be used as a general notebook computer or as a tablet computer, so that users are able to choose from the two modes according to different requirements of situations. However, compared with the normal notebook computer, the pivoting mechanism of the rotatable notebook computer is designed to be in a center of a display module thereof. The display module might sway easily as the display module pivots relative to a host module. It results in a bottom of the display module colliding with an upper surface of the host module and a keyboard thereon, so as to scratch the host module and the keyboard. In consideration of it, it is a significant issue to design a pivoting mechanism capable of pivoting the display module relative to the host module stably nowadays.

Portable electronic device capable of pivoting


The invention relates to lubricating greases based on alkali metal soaps and/or earth-alkali metal soaps and metal complex soaps based on (R)-10-hydroxyoctadecanoic acid and to the use thereof.

For many technical applications or tribosystems, it is important to use lubricants to reduce friction and wear on the contact surfaces of moving parts. Depending on the application, lubricants of different consistencies can be used. Lubricating oils have a liquid and flowable consistency, while lubricating greases have a semi-solid to solid—often gel-like—consistency. A lubricating grease is characterised in that a liquid oil component is taken up and held by a thickener component. The pasty nature of a lubricating grease and its property of being spreadable and easily plastically deformable, together with the property of being adhesive, ensures that the lubricating grease wets the lubricating point and that the lubricating effect unfolds on the tribologically stressed surfaces.
Lubricating greases contain a thickening agent that is homogeneously distributed in a base oil. Additional additives, such as emulsifiers, are often used to ensure that the thickening agent disperses stably in the base oil. A wide variety of substances are known as base oils. Organic and inorganic compounds are used as thickening agents. Moreover, additives are often added to the lubricating grease to improve wear protection, friction behaviour, ageing stability and corrosion protection, among other things.
The most important viscoelastic properties of a lubricating grease include the flow point and the shear viscosity. Both have a great influence on the efficiency of grease-lubricated drives or bearing arrangements, especially when elastohydrodynamic lubrication (EHL) is present at high sliding speeds or rotational speeds. Particularly at low application temperatures, flow point and shear viscosity have a great influence on the so-called breakaway torque and running torque of grease-lubricated components and aggregates.
Greases are widely used for lubrication purposes in the automotive and aerospace industries. Compared to oils, they have numerous advantages in terms of design and maintenance. Therefore, they are used to lubricate a large number of moving parts in passenger cars and aircraft where oil lubrication fails.
The viscoelastic behaviour of lubricating greases also has disadvantages, which can be seen in particular when operating lubricated components at very low temperatures. When starting up a largely cooled vehicle (winter, arctic regions), the "breakaway torque" is particularly noticeable when grease-lubricated vehicle components such as steering systems, sunroofs, window lifters, side mirror adjusters or door locks have to be operated manually or are operated with low servo-electric drive power. In the automotive industry, lubricating greases must therefore usually function reliably down to a temperature of at least −40° C. In aviation, lubricating greases must work reliably at temperatures as low as −54° C., in some cases even as low as −73° C. The lubricating grease in the landing gear wheel bearings must not fail during landing, even if the aircraft has been at high altitude for a long time and the landing gear has been exposed to very low temperatures. The "breakaway torque" of aircraft lubricating greases must not exceed a certain value.
Often, the design of maximum torques of grease-lubricated components such as gears, plain or roller bearings and all other types of tribological pairings depends on the quality of the lubricating grease used for lubrication. Low flow point and shear viscosity at low temperatures lead to reduced breakaway and running torques and allow designers to select aggregates with comparatively low drive power. This plays a particularly important role in vehicles in which electric drives are used, e.g., in hybrid vehicles or fully electric vehicles. By using lubricating greases with particularly low adhesion and sliding friction at lower application temperatures, for example −40° C., reduced starting and running torques lead to a lower demand for electrical drive power and electricity, which on the one hand extends the range of battery-driven vehicles and on the other hand makes it possible to use power cables with a smaller cross-sectional area and thus save weight in the on-board supply system.
A high degree of practical experience is required to create a lubricating grease of high utility value depending on the lubrication and equipment requirements.
Hydroxyoctadecanoic acid, in particular 12-hydroxyoctadecanoic acid (12-hydroxystearic acid), is a fatty acid that has been used for some time for the production of metal soap greases, especially lithium soap greases and lithium complex soap greases. The starting product for 12-hydroxyoctadecanoic acid or its esters or triglycerides is ricinoleic acid ((9Z,12R)-12-hydroxy-9-octadecenoic acid) and its triglyceride, the so-called castor oil, which is mainly obtained from the castor plant. For this purpose, the unsaturated hydroxy fatty acid ricinoleic acid or its triglyceride is converted into a saturated hydroxy fatty acid by hydrogenation to make it storage-stable and increase its thermal stability. To date, other hydroxyoctadecanoic fatty acids such as 10-hydroxyoctadecanoic acid have hardly any technical significance, even though they are repeatedly cited in passing in intellectual property rights or in the literature, such as in U.S. Pat. No. 4,802,999 A, EP 3461901 A1 or Matthias Engleder et al. "Structure-Based Mechanism of Oleate Hydratase from Elizabethkingia meningoseptica", Chem. Bio-Chem., 16 (2015), pages 1730-1734, without that the R-form has been specifically mentioned or actually has been used as a component of the thickener.

Lubricating grease comprising metal soaps and metal complex soaps based on R-10-hydroxyoctadecanoic acid


An offshore wind turbine foundation comprising a platform carrying a support for the wind turbine tower in its central region, and a plurality of leg guides in its peripheral region; and a plurality of legs, each of which may be movable between a raised position for transport and lowered positions for resting on the seabed. Each leg is capable of freely sliding in its guide.

The document US-7 163 355 B2 describes a foundation of this type, in which each leg and its guide are equipped with a device for relative movement with multiple cylinders and racks.
When the foundation, or complete wind turbine reaches its site of operation, these movement devices make it possible to move each leg down until it makes contact with the seabed, and then raise the platform to the desired height above sea level.
This design therefore requires legs with complex structures and numerous cylinders, which are only used during installation on site and then left in place.

Offshore wind turbine foundation, corresponding offshore wind turbine and method for their installation on site


In a steering device having a steering lock device and a telescopic clamp device, the strength of a column in a key-locked state and the force of telescopic clamping are secured. A flange section and ribs are formed between a through hole which a lock pin comes in and leaves and a slit for reducing the inner circumferential diameter of an outer column so as to increase the strength of the outer column. Hence, both the strength of the outer column against the bending moment applied to the lock pin in a key-locked state and the strength of the outer column against telescopic clamping effected by reducing the inner peripheral diameter of the outer column can be secured.

In a steering device having a steering lock device, when an ignition key is turned into a lock position and pulled out from the key hole, a lock pin projects toward the axis of the steering shaft. As a result, an end portion of the lock pin engages a key lock hole formed in a key lock collar press-fitted to the outer periphery of the steering shaft so as to fix the steering shaft to the outer column not to allow the steering shaft to rotate.
Existing steering devices having a steering lock device have a separate housing for the steering lock device bolted to a flange section of an outer column after the housing is positioned by fitting an engaging convex part of the housing in a through hole formed in the outer column.
There have also been steering devices having a steering lock device in which an outer column has a slit used to contract the diameter of the outer column so as to telescopically clamp the outer column to an inner column.
In cases where, in a steering device having both a steering lock device and a telescopic clamp device as described above, a through hole and a slit are closely positioned on an outer column, the outer column strength reduces. Therefore, when, in such cases, the steering wheel is subjected to a large rotating torque in a key-locked state (a lock pin is engaged with a key lock hole), the bending moment applied to the lock pin causes a large stress to be applied to the outer column possibly causing the outer column to be cracked.
In the steering device disclosed in Japanese Unexamined Patent Application Publication No. 2002-337663, a flange section made of thick steel plate is welded to a column made of a steel pipe enhancing the mounting rigidity between the column and the housing for a steering lock device. Also, in the steering device, an engaging convex part of the steering lock device is tightly fitted in a through hole formed in the column, and the bending moment applied to the lock pin in a key-locked state is born by both the flange section and the through hole. The column used in the steering device disclosed in Japanese Unexamined Patent Application Publication No. 2002-337663, is, however, made of steel, and no measure for enhancing the strength of a column made of an aluminum alloy and having both a through hole and a slit is disclosed.
In the steering device disclosed in International Publication WO2006/011378, to secure the strength of a portion peripheral to a slit formed in a column which is made of an aluminum alloy and which has both a through hole and the slot, a rib is formed along the peripheral edge of the closed end of the slit. International Publication WO2006/011378, however, includes no description of a flange section used to attach a housing for a steering lock device to the column.


A semiconductor device having a photosensitive thermosetting resin layer 64 provided on top of a protective film 13 for a semiconductor chip 10. A lead frame 11 is affixed to the surface of this photosensitive thermosetting resin layer 64 only at support pin sections 60, 61, and this lead frame 11 is electrically connected to the surface of semiconductor chip 10. Breakage of the wiring and chip cracking are prevented after the pressure-bonding mounting of the lead frame. Because package cracking and package warping are better controlled in thermal processes such as such as IR reflow and resin sealing, a lower cost semiconductor device and manufacturing method are enabled.

One conventional way to seal an IC chip in a package is to provide an LOC construction wherein a lead frame is affixed on the circuit-forming surface of the IC chip, for example as shown in FIGS. 28 and 29.
In FIGS. 28 and 29, a package for a LOC construction of, for example, a DRAM (dynamic RAM) is shown, with a large number of bonding pads 1 being arranged on a straight line in the center of the semiconductor integrated circuit (IC) chip 10. The power supply lines 42, 43, which are called bus bars, and a large number of signal lines 44, 45, are respectively arranged on both sides of this pad line, forming the lead frame 11 used for the LOC. This lead frame is formed from an iron-nickel alloy, a copper alloy, copper, or the like.
The bus bars 42, 43 are connected to the power supply Vss or Vcc, and the signal lines 44, 45 are used for the various signals such as the addresses A0 to A10, CAS, and RAS.
The connections between each bonding pad 1 and each wire is accomplished by means of the respective wire bonding by means of bonding wires 6, 7 on one side of the bonding pad line, and by bonding wires 8, 9 on the other side. In this case, the wires 7, 9 that connect the signal lines 44, 45 (specifically, the inner lead section) straddles on top of the bus bars 42, 43. Also, the entire body is sealed by means of a molding resin 18 (in FIG. 28, shown by the virtual line) consisting of an epoxy resin or the like, with the outer lead section 45a being led to the outside of this molding resin.
In the package for the IC chip 10 made in this manner, the lead frame 11 is affixed on top of the IC chip 10 (specifically, on top of the circuit forming surface) by means of the LOC construction; details are explained with FIG. 29.
First, with regard to the IC chip 10, for example, a passivation film (protective film) 13 comprising a laminated film of SiO.sub.2 and Si.sub.3 N.sub.4, for example, SiO.sub.2 and Si.sub.3 N.sub.4 is provided on one main face of the silicon substrate 12, bonding pads 1 are formed in the window sections of this passivation film and connected to the internal circuits of the IC chip 10, then a thermosetting polyimide protective film 14 is adhered on the entire surface, except for this bonding pad region.
A filler is contained in the molding resin 18 (for example, additional SiO.sub.2 for the purpose of reducing the thermal expansion coefficient), but because a filler made in this manner contains radioactive elements such as uranium and thorium, which radiate .alpha.-rays, the so-called soft errors are easily generated wherein the .alpha.-rays from these radioactive elements are irradiated on the IC chip 10 and the circuit operates erroneously. The polyimide protective film 14 in particular prevents the invasion of the .alpha.-rays generated in that manner, and is provided to prevent defects due to soft errors.
The process that forms the polyimide protective film 14 on top of the passivation film 13, which consists of the laminated film of Si.sub.3 N.sub.4 film 13A and SiO.sub.2 film 13B, is shown summarized in FIGS. 30-33.
First, after the passivation film 13 is selectively etched (FIG. 30) to expose the bonding pads 1, a noncured thermosetting polyimide resin 14A is coated on the entire surface (FIG. 31.
Next, an etching mask 20 is formed in the prescribed pattern by ultraviolet radiation and a developing process (FIG. 32). Using this mask 20, the polyimide resin 14A is wet etched, the bonding pads 1 are exposed (FIG. 33) and, after the removal of the mask 20, curing is performed, producing the polyimide protective film 14.
As shown in FIG. 29, frame 11 is adhered on top of the polyimide protective film 14 by means of the double-faced adhesive type of insulating tape 15 (but, in FIG. 28, the insulating tape 15 is omitted from the illustration). This insulating tape 15 is a tape wherein adhesives (for example, thermoplastic adhesives) 17, 19 are respectively painted on both faces of the insulating film substrate 16, lead frame 11 is adhered to the substrate 16 under heat and pressure by means of one of the adhesives 17, and the substrate 16 is adhered on top of the polyimide protective film 14 for the IC chip 10 under heat and pressure by means of the other adhesive 19. In this manner, the lead frame 11 is mounted and pressure bonded on top of the IC chip 10 by means of the insulating tape 15.
However, because the lead frame 11 is affixed on top of the IC chip 10 by means of the insulating tape 15, in addition to the thickness of the insulating film substrate 16 being, for example, 50 .mu.m, the thickness of the adhesives 17, 19 on both of its faces is, for example 12.5 .mu.m, respectively. Therefore, because the combined thickness of the insulating tape 15 becomes as much as 75 .mu.m (depending on the circumstances, 75 to 175 .mu.m), the fact is clear that the various defects (a) to (d) presented below are mainly generated.
(a) Breaks are generated in the metal wiring during the mounting pressure and temperature cycles.
During pressure mounting for the lead frame 11, the stress that is shown by the following formula is generated: ##EQU1## where Tm: temperature (.degree.C.) during mounting
-65.degree.: minimum temperature (.degree.C.) during the thermal cycle PA0 E: modulus of elasticity of the insulating tape including the adhesives PA0 .alpha..sub.2 : thermal expansion coefficient of the insulating tape including the adhesives PA0 .alpha..sub.1 : thermal expansion coefficient of the silicon substrate of the IC chip PA0 h: thickness (.mu.m) of the insulating tape including the adhesives PA0 W: width (.mu.m) of the insulating tape including the adhesives PA0 IR Reflow Test PA0 Thermal Cycle Test (-65-150.degree. C.) PA0 Soft Error PA0 Parasitic Capacitance PA0 t: polyimide thickness PA0 .epsilon.: polyimide dielectric rate (3.3) PA0 .epsilon..sub.0 : dielectric rate of vacuum PA0 C: capacitance PA0 Package Warpage PA0 X: warpage of wafer PA0 a: length of the arc of the warped wafer PA0 D: wafer thickness (280 .mu.m) PA0 E: Si (wafer) modulus of elasticity (16200 kg/mm.sup.2) PA0 t: polyimide resin film thickness PA0 v: Poisson ratio (0.3) PA0 Tensile Stress PA0 Adhesive Strength PA0 Curing conditions: temperature 350.degree. C. (2 h), 390.degree. C. (1 h) PA0 Atmosphere: N.sub.2 gas, air flow PA0 Plasma etching conditions: CHF.sub.3 /CF.sub.4, CF.sub.4, none PA0 Thermal-pressure bonding temperatures: 280, 310, 330, 370, 400.degree. C. PA0 Thermal-pressure bonding pressures: 3.0 kg/cm.sup.2, 6.0 kg/cm.sup.2 PA0 Thermal-pressure bonding times: 3 sec, 6 sec PA0 Glass Transition Point, Surface Roughness, & Surface Chemical Composition of Photosensitive Thermosetting Polyimide Resin PA0 Electrical Characteristics PA0 Thermosetting epoxy resin PA0 Photosensitive thermosetting polyimide resin
According to this equation for stress, if the thickness and the thermal expansion coefficient of the insulating tape 15 including the adhesives are large, the stress during the mounting pressure of the lead frame easily becomes large. In the case of the mounting pressure of the lead frame 11, because the insulating tape 15 is used, due to the thickness and thermal expansion coefficient of this insulating tape 15, as is shown in FIG. 34, cracks 23 are generated in the IC chip 10, particularly from the outer edge to the inner portion of the insulating tape 15, and there are instances in which the metal wiring 24 breaks.
(b) The generation of package cracks originating in the expansion of the insulating tape, which are generated during IR reflow.
At the time of affixing the completed IC package on top of the printed circuit wiring board 26, for example, as shown in FIG. 37, as a method of bonding the outer lead section 45a or 44a to the circuit pattern 27 by means of solder, there is the IR reflow method that conducts bonding by means of infrared ray (IR) heating. At the time of IR reflow, the IC package is heated to about 245.degree. C. at its peak.
Currently, the glass transition point (Tg) of the insulating tape is designed to be 210.degree. C. In order to prevent the oxidation of the lead frame 11, it is preferable that the temperature at which the lead frame 11 is glued to the chip 10 be made less than 400.degree. C., but it is necessary that this gluing temperature be above the glass transition temperature of the thermosetting adhesives 17, 19 of the insulating tape 15 +150.degree. C. It is for this reason that the glass transition point of the insulating tape 15 is designed to be 210.degree. C.
However, as for this glass transition point (210.degree. C.), since it is lower than the IR reflow temperature (245.degree. C.), as shown in FIG. 35, the adhesive makes the transition to a near liquid rubber condition during IR reflow, and its adhesive function is remarkably decreased. Due to this, during IR reflow, package cracks are easily generated.
On the other hand, because the combined thickness (75 .mu.m) of the insulating tape 15 is large, the percentage of moisture absorption of the tape itself (below 85.degree. C., 85% humidity) becomes as high as 2 to 2.5%. If the package is left to set for a long time in the air, the tape absorbs moisture, and as shown in FIG. 36, swelling is easily generated in the adhesives 17 and 19. This causes crack 25 to be generated in sealing resin 18 during IR reflow, and generates package cracks even more easily. It was confirmed that package cracks appeared in 16 out of 120 samples.
(c) Generation of package warpage.
As for the size of each section shown by A', B', C', D', B', F', H', I', and J' in FIG. 29, specifically, these are as shown in the following Table I. Here, these are shown for both a TSOP (Thin Small Outline Package) with a total thickness of about 1 mm (1000 .mu.m) and an SOJ (Single Outline J-Lead Package) with a total thickness of about 2.7 mm (2700 .mu.m).
TABLE I ______________________________________ 1 mm TSOP 2.7 mm SOJ ______________________________________ A' 0.195 mm (195 .mu.m) 0.810 mm (810 .mu.m) B' 0.125 mm (125 .mu.m) 0.200 mm (200 .mu.m) C' 0.075 mm (75 .mu.m) 0.075 mm (75 .mu.m) D' 0.010 mm (10 .mu.m) 0.010 mm (10 .mu.m) E' 0.280 mm (280 .mu.m) 0.280 mm (280 .mu.m) F' 0.325 mm (325 .mu.m) 1.335 mm (1335 .mu.m) H' 0.395 mm (395 .mu.m) 1.085 mm (1085 .mu.m) I' 0.325 mm (325 .mu.m) 1.335 mm (1335 .mu.m) J' 15.240 mm (15,240 .mu.m) 15.240 mm (15,240 .mu.m) ______________________________________
Because the thickness (C'=75 .mu.m) of insulating tape 15 is large, it is difficult to adopt a construction balance in the package. In particular, in the case of a TSOP package or the like with a 1 mm thickness, the bowing referred to as package warpage originating in the tape thickness (greater than 75 .mu.m) is easily generated.
In the 1-mm TSOP package used until now, it is difficult to make the resin thickness (A') on top of the lead frame less than 195 .mu.m, but this is because of the capabilities of the wire bonder and to prevent the protrusion of the wire loop outside the package. Because of this, when the IC chip thickness (B') is made 280 .mu.m, the resin thickness on top of the chip becomes H'=395 .mu.m and the resin thickness beneath the chip becomes I'=325 .mu.m. This unbalanced thickness relationship is naturally generated due to the insulating tape thickness being C'=75 .mu.m, and brings about the problem of package warpage.
Due to the generation of this type of package warpage, shown in exaggerated form in FIG. 37, the package is warped 30-60 .mu.m, the outer lead sections 45a or 44a on both edges in particular rise up in relation to the circuit pattern 27 on top of the printed wiring board 26, and there are instances when these do not connect.
(d) Cost increases.
Insulating tape 15 that adheres the lead frame 11 has a high value of above several tens of yen per single unit, the cost of packages using this rises, and there are limitations to its cost reduction.
Thus, the present applicants, to eliminate the types of defects, in Japanese Patent Application No. Hei 6[1994]-27367, proposed a semiconductor device and its manufacturing method (hereinafter, referred to as the invention of the previous application) for a package construction that can prevent the chip cracking and breakage of the wiring during the pressure bonded mounting and thermal cycles for the lead frame, that can control the package cracking and package warpage in processes such as IR reflow, and that can be manufactured at a low cost.
In other words, the invention of the previous application relates to a semiconductor device wherein a second protective film (in particular, a second protective film that alleviates the influence of the .alpha.-rays due to the filler of the molding resin) is provided on top of the protective film for the semiconductor chip, the lead frame is affixed on top of this second protective film, and this lead frame is electrically connected to the surface of the semiconductor chip, with the main components of the lead frame being affixed on top of the second protective film with a thermoplastic resin layer interposed and forming at least one portion of the second protective film.
In the semiconductor device of the invention of the previous application, the second protective film can be formed by means of a laminated body of a thermosetting polyimide resin layer, which becomes the bottom layer, and a thermoplastic polyimide resin layer, which becomes the upper layer.
In this case, in the laminated body, in the region wherein the lead frame is adhered, the thermoplastic polyimide resin layer and the thermosetting polyimide resin layer are formed in almost the same pattern. The thickness of the thermoplastic polyimide resin layer is 15-35 .mu.m, the thickness of the thermosetting polyimide resin layer is 10 to 30 .mu.m, and in the region where the lead frame is not adhered, the thickness of the thermosetting polyimide resin layer can be 5-15 .mu.m.
Also, in the laminated body, the thermoplastic polyimide resin layer can also be provided on top of the thermosetting polyimide resin layer in the regions where the lead frame is not adhered. The thickness of the thermoplastic polyimide resin layer can be 15-35 .mu.m, and the thickness of the thermosetting polyimide resin layer can be 10-30 .mu.m.
In either case, the total thickness of the laminated body within the lead frame adhesion regions can be 35 to 65 .mu.m.
In the semiconductor device of the invention of the previous application, the second protective layer can be made of only the thermoplastic polyimide resin layer.
In this case, the thickness of the thermoplastic polyimide resin layer can be 30-50 .mu.m. Also, it is preferable that the thermoplastic polyimide resin layer also be provided on top of regions where the lead frame is not adhered.
In the semiconductor device of the invention of the previous application, it is also permissible if the edges of the thermoplastic polyimide resin layer within the lead frame adhesion regions protrude 0.1 to 0.15 mm more than the edge of the lead frame (specifically, the width of the thermoplastic polyimide resin layer is made 0.1 to 0.15 mm larger on each side in relation to the width of the lead frame).
Also, the spacing between the cell section of the semiconductor chip and the edge of the thermoplastic resin layer can be 100 to 500 .mu.m on the side of the bonding pad for the semiconductor chip.
Also, the thermoplastic resin layer and/or the thermosetting resin layer can be present in the regions of the bonding pad.
As for the semiconductor device of the invention of the previous application, in actuality, the bonding pad and the lead frame are wire bonded, and the entire body can be sealed with a molding resin. Also, the lead frame can comprise the lead frame section used for the signal lines and the lead frame section used for the power-supply lines.
In the manufacture of the semiconductor device of the invention of the previous application, at least a thermoplastic resin is coated on top of the protective film for the semiconductor chip. This coated resin is patterned, and it is preferable that the lead frame be adhered on top of the thermoplastic resin layer after the curing is accomplished.
In this case, in practice, after the lead frame is adhered, the bonding pads of the semiconductor chip with the lead frame are wire bonded, then the entire body can be sealed with a molding resin.
Next, a concrete example of the invention of the previous application is explained based on FIGS. 38-46. This example is a device wherein the invention of the previous application was applied, for example, to a package for a DRAM, the same keys are applied to the components that are the same as in the prior example shown in FIGS. 28-37, so their explanations are omitted.
First, to explain the construction of the package of an LOC construction based on this example in FIGS. 38 and 39, the distinctive feature of this package is the fact that the thermoplastic polyimide resin layer 54 is laminated on top of the passivation film 13 of the IC chip 10. Using that thermoplasticity, the bus bars 42, 43 and the signal lines 44, 45 (inner lead section) of the lead frame 11 on top of this are bonded by thermal pressure (pressure-bonding mounted).
In other words, the thermoplastic polyimide resin layer 54 provided on top of the IC chip, along with functioning as a second protective film in the same manner as the previously mentioned polyimide protective film 14, is used as an adhesive for the lead frame 11, and the point at which the insulating tape 15 like that previously mentioned is not used is a fact that should be noted.
According to this example, as shown in FIGS. 38 and 39, the second protective layer is formed by means of only the thermoplastic polyimide resin layer 54. This resin layer 54 is provided across almost the entire region of the memory cell section of the IC, as shown by the diagonal lines in FIG. 39.
Also, it is preferable for the thickness (b) of the polyimide resin layer 54 to be 20-45 .mu.m. The glass transition point of the thermoplastic polyimide resin layer 54 should be 210.degree. C. The reason for this is that, in the same manner as presented above, the temperature at the time of thermal pressure bonding of the lead frame on the IC chip surface is less than 400.degree. C., with the wire bonding temperature being 200.degree. C.
Also, when looked at in regard to the entire body of the package, specifically, the size of each component can be designed as shown in the following Table II.
TABLE II ______________________________________ 1 mm TSOP 2.7 mm SOJ ______________________________________ A 0.195 mm (195 .mu.m) 0.810 mm (810 .mu.m) B 0.125 mm (125 .mu.m) 0.200 mm (200 .mu.m) b 0.030 mm (30 .mu.m) 0.030 mm (30 .mu.m) E 0.280 mm (280 .mu.m) 0.280 mm (280 .mu.m) F 0.370 mm (370 .mu.m) 1.380 mm (1380 .mu.m) H 0.350 mm (350 .mu.m) 1.040 mm (1040 .mu.m) I 0.370 mm (370 .mu.m) 1.380 mm (1380 .mu.m) J 15.240 mm (15,240 .mu.m) 15.240 mm (15,240 .mu.m) ______________________________________
As for the package based on this example, because it is a construction wherein the lead frame 11 is directly pressure-bonding-mounted on top of the thermoplastic polyimide resin layer 54 used as the protective film, the following effects (A)-(E) can be obtained.
(A) The metal wiring breaks that are generated after the pressure-bonded mounting and during the thermal cycles can be prevented.
Because the insulating tape used in the conventional mounting was a thickness of 75 to 175 .mu.m, the thermal stress was large, but because the thickness of the polyimide resin layer 54 is as little as 30-50 .mu.m, the tension stress can be lowered as much as 30% compared to the conventional type.
Specifically, in the package internal section, the maximum stress is concentrated in the chip surface region directly beneath the corner section (P) of the bus bar shown in FIG. 39. Due to this, the tensile stress exerts a harmful influence on the device characteristics. When the tensile stress on top of the chip surface was found during a thermal cycle of 150.degree. C. to -65.degree. C., in the structure of FIG. 38, a tensile stress of 2.90 kg/mm.sup.2 was shown. It can be seen that it decreased about 30%, compared to a tensile stress of 4.20 kg/mm.sup.2 in the construction of FIG. 29 based on the conventional example.
(B) The package cracks that tend to be generated during IR reflow can be prevented.
Accompanying the capability to reduce the volume of the adhesive layer (polyimide resin layer), since the percentage of water absorption is reduced, the generation of package cracks during IR reflow can be remarkably reduced or prevented. In this case, there were absolutely no package cracks for a sampling of 120 units.
(C) Package warpage can be prevented.
Specifically, in a 1-mm TSOP or the like, a balance of the resin thickness above and below the chip within the package is easily obtained due to the equilibrium between the thicknesses (H) and (I), and the package warpage can be made less than 20 .mu.m or sufficiently prevented.
(D) A cost reduction can be realized.
Compared to the cost of the insulating tape (attached to the lead frame) used until now, in the mounting construction based on this example, the [cost] per unit can be reduced to less than about 1/7 to 1/33.
(E) Soft errors can be effectively prevented.
By providing the thermoplastic polyimide resin layer 54 at a thickness of above 30 .mu.m across the entire region of the cell section, the cell section is physically shielded from the previously mentioned .alpha.-rays. Therefore, the .alpha.-rays radiated from the lead frame and the filler (SiO.sub.2 and the like) within the molding resin 18 are effectively shielded, and soft errors of the memory cell section can be prevented.
The thermoplastic polyimide resin 54 used here has the following physical values, and can be of the construction shown in FIG. 40.
Tensile strength 10 kg/mm.sup.2 (room temperature)
Tensile modulus of elasticity 280 kg/mm.sup.2 (room temperature)
Tensile coefficient of elongation 10% (room temperature)
Volume resistivity 6.3.times.10.sup.16 .OMEGA.-cm
Leakage current value 1.61.times.10.sup.-11 (A) (room temperature) 1.07.times.10.sup.-11 (A) (PCT after 500 h)
(The PCT (Pressure Coupler Test) test is one stress testing method wherein the body to be tested is placed at a pressure of 1 atm and at 121.degree. C., and the changes in various characteristics before and after that are observed.)
Pyrolysis temperature 520.degree. C.
Thermal expansion coefficient 4.3.times.10.sup.-5 (1/.degree.C.) (30-100.degree. C.)
Glass transition point 240.degree. C. (In the sample evaluation, those with the points of 160-300.degree. C. were also used.)
Moisture absorption rate 0.91% 22.degree. C., 60% RH)
Next, to explain the main processes of the manufacturing method for the package shown in FIG. 38, first, after the passivation film 13 is selectively etched to expose the bonding pads (FIG. 41), a noncured thermoplastic polyimide resin 54A is painted on the entire face (FIG. 42).
Next, an etching mask 20 of a photoresist is formed in the prescribed pattern by ultraviolet radiation and developing processes (FIG. 43). Using this mask 20, the polyimide resin 54A is wet etched and the bonding pads 1 are exposed (FIG. 44). After removal of the mask 20, the curing is performed, producing the polyimide protective film 54.
The package that is manufactured in this manner has the superior advantages, but it can be seen that there are still problems that must be alleviated. As for these problems, they are mainly generated in the etching process of the polyimide resin 54A shown in FIGS. 43 and 44, which are explained in detail in FIG. 44.
Namely, because the thermoplastic polyimide resin 54A is a non-photosensitive type (even though exposed, it is not made photosensitive), it would be ideal for the etching to be done at the same window size as mask 20 shown by the broken line in FIG. 45(A), but because it depends on wet etching, in actuality, overetching occurs as in FIG. 45(B). Due to this, there are instances wherein the polyimide resin 54 between adjacent bonding pads 1--1 is completely eliminated.
In the event that the thickness of the polyimide resin 54 is 20 .mu.m before curing 10 .mu.m thickness after curing) and the size of the bonding pad 1 is 100 .mu.m.times.100 .mu.m, the amount of overetching becomes as high as 20-30 .mu.m, the polyimide resin 54 between adjacent bonding pads 1--1 is easily removed by the etching, and the passivation film 13 is exposed.
As a result, when sealing is done by means of molding resin 18 as shown in FIG. 38, this molding resin (for example, a multipurpose type of epoxy resin) 18 comes in direct contact with the passivation film 13, but because the molding resin 18 has poor adhesion characteristics with the Si.sub.3 N.sub.4 film 13A of the passivation film 13, fissures are generated in the Si.sub.3 N.sub.4 film 13A by the stress due to heat, and become a cause of package cracking. The problems due to the overetching in this manner are also generated in the same manner even in the etching of the thermosetting polyimide resin 14A shown in FIGS. 32 and 33, and the same types of defects as the are created.
This invention should eliminate defects such as the, and its purpose is to offer a semiconductor device and its manufacturing method for a package construction that can prevent chip cracking and wiring breakage after the pressure-bonded mounting of the lead frame and during the thermal cycles, that controls the package cracking and package warpage in processes such as IR reflow and resin sealing, and that can be done at a low cost.

Semiconductor device having a tapeless mounting