An adjusting apparatus for a comfort element swingable in relation to a support structure, in particular for an armrest of a vehicle, includes a latching device actuatable by adjusting the comfort element and having a latching arm connected to the comfort element and a latching lever interacting with the latching arm. A swing position of the comfort element is locked by providing a locking lever which is swingably articulated to the latching arm and has an engagement portion which locks the swing position by a spring force, when the engagement portion assumes an engagement position with a locking portion of a locking element that is fixed to the support structure, and the swing position of the comfort element is unlocked by an actuator by which the locking lever is disengageable from the engagement position with the locking element.

The invention relates to an adjusting apparatus for a comfort element which is swingable in relation to a support structure, in particular for an armrest of a vehicle.
A generic adjusting apparatus for adjustment of a swingable armrest or arm support is known, for example, from DE 10 2006 048 107 A1. This apparatus includes a latching device which includes a first latching element connected to a swingable armrest and having a toothing, and a second latching element which also has a toothing. The second latching element is held swingably under the influence of a spring force in an engagement position with the toothing of the first latching element. The profiles of both toothings are hereby configured to permit the armrest to swing open in the manner of a ratchet, while a swinging back is, however, supported by the toothings.
Such armrests may also be configured for longitudinal adjustment, as known e.g. from DE 199 15 469 A1 and additionally equipped with a storage space underneath the pivotable armrest.
In order to meet the motor vehicle safety standard (FMVSS 201) of the National Highway Traffic Safety Administration (NHTSA) in terms of height-adjustable and length-adjustable armrests, the latter must be additionally locked when cantilevered or in the presence of a subjacent storage option.
The afore-mentioned known adjusting apparatuses for armrests of a motor vehicle fail to meet this condition, i.e. the armrest may carry out an uncontrolled pivoting motion, when accelerated accordingly in the event of an accident, so that objects, stowed in a storage space underneath the armrest may fly around in the interior of the vehicle and therefore pose a significant risk of injury to vehicle occupants.
Object of the invention is therefore to refine an adjusting apparatus of the afore-mentioned type such that an uncontrolled upward swinging of a comfort element, in particular an armrest of a vehicle, is reliably prevented and the armrest has a simple structure.

Adjusting apparatus for a pivotable comfort element, in particular for an armrest of a vehicle


A light source module includes a base, a supporter, and a light source fixed by the supporter. The base includes a top surface, a first side surface connected with the top surface, a second side surface connected with the top surface, a protrusion projecting from the first side surface, and a recess defined in the second side surface. The protrusion is for inserting into a recess of another light source module. The recess is configured for coupling with a protrusion of still another light source module. The supporter is mounted on the top surface of the base.

1. Technical Field
The present disclosure relates to a light source module and a light source module array having the light source module.
2. Description of Related Art
Light source modules, such as incandescence lamps, fluorescent lamps and halogen lamps, generally have a limited illumination area. However, it is not adequate to use these light source modules in certain areas, such as stadiums and stages, where a large-area illumination is needed.
In order to illuminate a large area, a plurality of light source modules can be used simultaneously, each of which works independently. However, since the light source modules are arranged independently, it can be difficult and troublesome to install.
Therefore, a new light source module and a new light source module array are desired to overcome the above mentioned problems.

Light source module and light source module array having same


Disclosed are a method for manufacturing an array substrate, an array substrate and a display device. The method includes the following operations: sequentially forming a gate, a gate insulation layer, an active layer, an ohmic contact layer and a metal layer on a base substrate; forming a photolithography mask on the metal layer, a thickness of the photolithography mask being between 1.7 μm and 1.8 μm; exposing the photolithography mask through a mask plate to make a uniformity of the photolithography mask in a half-exposed area of the mask plate reach a preset uniformity; and manufacturing the array substrate based on the exposed photolithography mask.

Nowadays, during the process of manufacturing the thin film transistor array substrate through 4-mask process (4-Mask), a photolithography mask needs to be formed on the metal layer before forming the channel region of the array substrate by etching. A thickness of the photolithography mask in the region corresponding to the channel region (this region corresponds to the half-exposed region of the mask plate) is smaller than the rest.
During the production process, the thickness of the photolithography mask in the channel region is not easy to be controlled. If the thickness is too thin, the ohmic contact layer residue will be formed when the metal layer and the ohmic contact layer are sequentially etched after the photolithography mask is removed. If the thickness is too thick, a photolithography mask residue will be formed when the photolithography mask is subsequently removed, resulting in abnormal dimensions of each layer in the channel region and excessive deviation of critical dimensions (the corresponding metal layer, ohmic contact layer, and active layer cannot be completely etched, resulting in a series of metal layer residues, ohmic contact layer residues and active layer residues). In severe cases, the channel region cannot even be formed, which seriously affects the display performance of the array substrate.

Method for manufacturing array substrate, array substrate and display device

BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.


The invention relates to a dialyzer comprised of two modules that are realized in one basic unit. The first module has a bundle of membrane capillaries and one inlet and one outlet each for the fluid to be treated and one inlet and one outlet for the dialysate. The second module likewise comprises a bundle of membrane capillaries used to sterilize substituate by filtration and one inlet for the substituate. In addition, the dialyzer has a chamber, in which the purified substituate is able to be combined with the fluid to be treated.

Hemodiafiltration is a combined process in which hemodialysis and hemofiltration are carried out simultaneously. This process unites the advantages associated with convective mass transfer in hemofiltration and those of the dialytic diffusion process. To implement volumetric fluid balancing in known on-line hemodiafiltration processes, balancing chambers are utilized to directly measure a replacement fluid (substituate). Thus, a patient's fluid intake and output is centrally controlled by means of the balancing chambers, while all added and withdrawn fluids are observed. Also in an on-line process, no additional reservoir is needed for the substituate, because it is produced concurrently. In the known process, the substituate is sterilized by filtration using an especially provided on-line hemodiafiltration filter, which is present in addition to the actual hemodiafiltration filter. The additionally provided on-line hemodiafiltration filter is not replaced with every treatment. For that reason a separate contamination-prevention chamber is provided to reduce the risk of cross-contamination. In spite of this measure, there is still a residual risk of cross-contamination.


A side-impact airbag system includes an inner airbag that is supplied with gas and inflates and deploys in an inner side in a vehicle width direction for a seating occupant on a driver's seat, and an ECU that instructs an inner inflator to supply gas to the inner airbag. The ECU activates the inner inflator of the driver's seat to supply gas to the inner airbag at a first timing in the event of the side impact collision on a passenger seat side and at second timing that is set to be later than the first timing in the event of the side impact collision on a driver's seat side.

1. Field of the Invention
The present invention relates to an occupant protection device.
2. Description of Related Art
A vehicle seat is well-known in which a side-impact airbag is installed in each of an inner and an outer protrusions that are provided in an upper section of a seat back (for example, see Japanese Patent Application Publication No. 7-267037 (JP 7-267037 A)). In the vehicle seat described above, in the event of the side impact collision, the side-impact airbag in the outer protrusion inflates first, and then the side-impact airbag (side airbag) in the inner protrusion inflates.
In the vehicle seat described above, the difference in the direction of the side impact collision is not taken into account.


An improved bumped chip carrier (BCC) package according to the present invention includes a resin-molded lead frame encapsulating an attached semiconductor integrated circuit (IC) and a plurality of interconnecting wire bonds attaching a plurality of contact pads on the IC to an associated plurality of solder-covered external contact terminals that are integrated in the lead frame. By integrally processing the external contact terminals, bonding wires may be affixed using a single wire bonding process. A method for manufacturing the BCC package preferably includes a dual photoresist patterning process accompanied by a dual wet etching process to create a plurality of highly reliable external contact terminals having improved bonding between the contact terminals and the encapsulating resin mold.

1. Field of the Invention
The present invention relates to a semiconductor package and a met hod for manufacturing the same. More particularly, the present invention relates to a bumped chip carrier package using a lead frame and a method for manufacturing the same.
2. Description of the Related Art
In an effort to reduce the size and weight of multi-function electronic devices while simultaneously increasing speed and performance, high-density integrated circuits (ICs) are being mounted in high-density packages. One such high-density package is a chip scale package (CSP), wherein ICs are mounted directly on a substrate. Although such CSPs have been manufactured in sizes as small as a single IC, a CSP may provide for the mounting of multiple ICs on a common substrate or carrier, such as a printed circuit board (PCB), a tape circuit board, or a lead frame. One such conventional CSP is a bumped chip carrier (BCC) package, which uses a lead frame as shown in FIG. 1 through 3, wherein FIG. 2 illustrates a cross-sectional view taken along line 2—2 in FIG. 1.
Referring to the two views of the BCC package shown in FIGS. 1 and 2, a semiconductor chip 20 is attached to a chip mounting area 12 of a lead frame 10, and a plurality of contact grooves 14 are formed around the periphery of the chip mounting area 12. Each one of a plurality of bonding pads 24 on semiconductor chip 20 are electrically connected to an associated contact groove 14 by a bonding wire 30. The semiconductor chip 20, the plurality of bonding wires 30, and the plurality of contact grooves 14 on lead frame 10 are then encapsulated with a molding resin to form a resin mold 40.
Each contact groove 14 typically includes a depression having an overlaying plating layer 16, which is formed by successive deposition and/or etching of metal layers using metals, such as stannum (Sn), palladium (Pd), and aurum (Au). Since it is difficult to attach a bonding wire 30 directly to the concave plating layer 16, a conventional procedure for connecting the bonding wire 30 to the plating layer 16 is typically a two-step process.
In a first step, a first plurality of ball solder bumps 32 are formed on each one of the contact locations on plating layer 16 using a ball bonding technique. A second plurality of ball solder bumps are then formed on each one of the bonding pads 24 of semiconductor chip 20. A stitch bonding operation is then performed to connect each end of the bonding wires 30 to the associated ball solder bumps.
An alternate variation on this conventional CSP might feature the elimination of lead frame 10 under the resin mold 40 by using a selective etching, such as that shown by the conventional bumped chip carrier package 50 of FIG. 3. In bumped chip carrier package 50, an external contact terminal 18 has a structure in which plating layer 16 is filled with a molding resin.
Because the height of the external contact terminals 18 in the bumped chip carrier package 50 may be adjustably controlled during the manufacturing process of the lead frame, the bumped chip carrier package 50 has a significant advantage over conventional semiconductor chip mounting techniques using conventional solder balls as an external contact terminal.
Disadvantageously, however, since a conventional external contact terminal structure features a plating layer 16 being filled with a molding resin, plating layer 16 may exhibit cracking due to a difference in thermal expansion coefficients between the plating layer 16 and the molding resin during conventional manufacturing tests of bumped chip carrier package 50, for example, during a temperature cycling (T/C) test. Another significant disadvantage of conventional CSPs is that the aforementioned two-step ball bonding operation is typically required in the wire bonding process.

Bumped chip carrier package using lead frame and method for manufacturing the same


Provided is a pressure-strain sensor including a graphene structure having a three-dimensional porous structure, planar sheets provided on a surface of the graphene structure, and a polymer layer configured to cover the graphene structure and the planar sheets, wherein each of the planar sheets contains a transition metal chalcogenide compound.

The present disclosure herein relates to a pressure-strain sensor and a manufacturing method thereof, and more particularly, to a pressure-strain sensor including planar sheets and a manufacturing method thereof.
When a specific object externally receives a vertical direction pressure, a tensile force, or a compressive force, a strain in length occurs. A pressure-strain sensor of a piezo resistive type is a sensor configured to sense a resistance change occurring according to a strain in length of the object and measure the pressure, the tensile force, or the compressive force of the object. When the length of the object is elongated and the cross-sectional area is reduced, the resistance of the object increases, and when the length of the object is reduced and the cross-sectional area is extended, the resistance of the object is reduced. A pressure-strain sensor using the above-described piezo resistive effect is referred to as a piezo resistive sensor.

Pressure-strain sensor including a graphene structure

Electronics and Telecommunications Research Institute


The invention relates to the preparation of chiral compounds, in particular to the preparation of chiral compounds which may be used as intermediates for the preparation of anti-diabetic agents, preferably sitagliptin.

Type II diabetes mellitus (T2DM) is a global epidemic. Therefore, the research is oriented in the development of selective inhibitors of the enzyme DPP-IV as a promising new treatment for the type II diabetes.
Sitagliptin (CAS Registry Number 486460-32-6. IUPAC Name: (R)-4-oxo-4-[3-(trifluoromethyl)-5,6-dihydro[1,2,4]triazolo[4,3-a]pyrazin-7(8H)-yl]-1-(2,4,5-trifluorophenyl)butan-2-amin) is an anti-diabetic agent and a potent inhibitor of the DPP-IV. It is represented by the structure:

There is a constant search for improved synthetic protocols for key intermediates, in particular β-amino acid intermediates of the formula I,
and β-hydroxy intermediates of the formula IV
for the synthesis of sitagliptin.
WO 03/004498 disclose a method for producing the carboxylic acid of the β-amino acid intermediate of the formula I, which is performed through a 2,3,5-trifluorobenzylbromide intermediate, where enantioselectivity was induced by the use of unusual dihydropyrazine chiral auxiliaries. In the last steps, diazomethane, which is an explosive reagent, and stoichoimetric amounts of silver salts are included in the synthetic protocol which are very expensive and therefore unsuitable reagents for industrial synthesis.
Other synthetic approaches include asymmetric hydrogenation of β-enamino acid intermediates. The asymmetric hydrogenation reactions are conducted in the presence of expensive metal catalysts like rhodium in combination with chiral phosphine/diphosphine ligands (WO 03/004498, Kubryl, M.; et. al. Tetrahedron Asymmetry 2006, 17, 205). In some cases also expensive ruthenium metal catalysts are used (WO 09/064476, WO 04/085378, WO 05/097733, WO 06/081151, Hsiao, Y.; et. al. J. Am. Chem. Soc., 2004, 126, 9918). Hydrogenation with cheaper achiral catalysts involving a chiral derivatization of enamines is also known (WO 04/085661).
Also known are synthetic strategies, which are based on the chemocatalytic selective reduction of β-keto esters in the presence of ruthenium or rhodium diphosphine chiral catalysts (WO 04/087650, US 2009/0192326; US 2006/0052382; Hansen, K. B.; et. al. J. Am. Chem. Soc. 2009, 131, 8798.; Hansen K. B.; et. al. Org. Process Res. Dev. 2005, 9, 634-639).
WO 09/045507 discloses a biocatalytic approach to sitagliptin where an enantioselective step was performed using an appropriate enzymes (ketoreductase) for the asymmetric reduction of the β-carbonyl part of the molecule to form than the β-hydroxy intermediates of the formula IV. The transformation of the obtained chiral hydroxyl intermediates to the final sitagliptin precursors was performed via azetidinone intermediates. It is well known that this step is very difficult to establish. Disadvantages of these protocols are also: reactions at high pressures (250 psi), the use of very expensive metal chiral catalysts (Rh or Ru), low stereoselectivity and product contamination with rhodium and consequently hard purification protocols of final compound.
WO 09/045507 discloses difficult protocols for the synthesis of the β-hydroxy intermediate of the formula IV and the β-amino acid intermediate of the formula I.
It has been also shown that rhodium or ruthenium asymmetric catalytic hydrogenation of β-keto esters through enamines can be replaced by an efficient biocatalytic process using special enzymes transaminases, which improve the efficiency of sitagliptin manufacturing up to 99.95% enantiomeric excess (Savile, C. K.; et. al. Science 2010, 329, 305 and references cited therein). This enzymatic route features direct amination of the prositagliptin ketone to provide the enantiopure sitagliptin, followed by phosphate salt formation to provide the final sitagliptin phosphate. It is well known that enzymatic reactions offer an environmentally friendly approach to the synthesis of final molecules but on the other hand the availability and especially price of special enzymes (isolation protocols etc.) represent an inconsiderable disadvantage of a biocatalytic process.
There is also disclosed an intermediate of the formula II
with R3 being methyl, but no experimental procedure, no evidence and any other signs are devoted to this intermediate. All synthetic strategies disclosed in WO 2010/122578 are experimentally complicated, involve relatively many synthetic steps and some of them are conducted under extreme reaction conditions (temperature up to −50° C.; dry conditions etc.). The efficiency and especially the selectivity of some individual synthetic steps are modest and consequently influence the lower overall yields of the process.
Liu et al. discloses an asymmetric synthesis of sitagliptin over 9-10 steps, with the overall 31% yield and 99.5% enantiomeric excess (Liu, F.; et. al. J. Chem. Res. 2010, 34, 230-232.) The synthetic strategy involving also an intermediate of formula II, presents synthetic approach to sitagliptin but on the other hand offers also a lot of disadvantages. One of these disadvantages is the long and complicated process to obtain the intermediate of the formula II.
Therefore, it was an object of the present invention to provide an improved process for the preparation of an intermediate of formula I.
It was another object of the present invention to provide an improved process for the preparation of an intermediate of formula I starting from of the intermediate of the formula II.
It was a further object of the present invention to provide an improved process for the preparation of an intermediate of formula IV.
It was another object of the present invention to provide an improved process for the preparation of an intermediate of formula IV starting from the intermediate of the formula II.
It was yet another object of the present invention to provide an improved and simple process for the preparation of an intermediate of the formula II. In particular, the object was to provide an improved and simple one-pot process for the preparation of an intermediate of the formula II using environment friendly reagents.
It was yet another object of the present invention to provide new intermediates for the preparation of anti-diabetic agents, preferably sitagliptin.

Preparation of sitagliptin intermediates


A data card may comprise a chip and a card body having a first face and a second face. The chip may be mounted in the card body between the first face and the second face at least one of the first face and the second face has a cut indicator.

A data card such as a credit card, debit card or smart card may store information in a variety of ways. Some data cards store information in magnetic stripes and some store information in a chip. When a data card has expired or is no longer needed, a cardholder may destroy the data card to prevent further use of the card. For example, a credit card issuing bank may instruct cardholders to destroy a magnetic stripe credit card when the card is replaced or has expired.
Because a magnetic stripe is visible on the face of a card it is easy for a cardholder to destroy. Newer cards have chips formed inside a body of the card. The chips are not visible to cardholders. It is difficult for cardholders to properly destroy such cards so that they are rendered unusable.


A power transfer system includes four relays for switching power from a primary power supply to an auxiliary power supply having a starter motor and a kill switch. A first relay couples the primary power supply to the load. A second relay is responsive to the failure of the primary power supply and activates the starter motor and deactivates the kill switch. A third relay is responsive to power supplied by the auxiliary power supply and couples the auxiliary power supply to the load. A fourth relay is responsive to power supplied by the auxiliary power supply and decouples the primary power supply from the load and deactivates the starter. An optional time delay relay is provided for delaying the activation of the starter motor upon the loss of power supplied by the primary power supply.

1. Field of the Invention
The present invention relates to systems for providing backup power to a primary power supply and more particularly pertains to a new Power Transfer System for cost effectively providing backup power which is easily installable.
2. Description of the Prior Art
The use of systems for providing backup power to a primary power supply is known in the prior art. More specifically, prior art systems for providing backup power to a primary power supply heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art systems for providing backup power to a primary power supply include U.S. Pat. No. 4,879,624; U.S. Pat. No. 4,675,539; U.S. Pat. No. 5,191,229; U.S. Pat. No. 5,268,850; U.S. Pat. No. 4,703,191 and U.S. Pat. No. 4,044,268.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new Power Transfer System. The inventive device includes four switching means for switching power from the primary power supply to an auxiliary power supply having a start means and a stop means. A first switching means couples the primary power supply to the load. A second switching means is responsive to the failure of the primary power supply and activates the start means and deactivates the stop means. A third switching means is responsive to power supplied by the auxiliary power supply and couples the auxiliary power supply to the load. A fourth switching means is responsive to power supplied by the auxiliary power supply and decouples the primary power supply from the load and deactivates the start means.
In these respects, the Power Transfer System according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of cost effectively providing backup power which is easily installable.


A BMC firmware security system includes a BMC coupled to a programmable circuit device and a first storage subsystem. In response to BMC initialization, the BMC uses a system identifier to verify that a license in the first storage subsystem authorizes the BMC to use BMC firmware in the BMC, uses branding identity information in the BMC to verify that the BMC is branded for the BMC firmware, determines that the programmable circuit device identifies the BMC firmware and, in response, the performs BMC initialization operations using the BMC firmware. A BIOS is coupled to the programmable circuit device and a second storage system. In response to BIOS initialization, the BIOS uses the branding identity information in the second storage subsystem to identify the BMC firmware, determines that the programmable circuit device identifies the BMC firmware and, in response, performs BIOS initialization operations.

The present disclosure relates generally to information handling systems, and more particularly to providing for the secure use of Baseboard Management Controller (BMC) firmware in BMC devices included in information handling systems.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems such as, for example, server devices and/or other computing devices known in the art, are sometimes provided with Baseboard Management Controller devices (BMC devices) that operate to manage an interface between system management software and platform hardware, monitor server device parameters (e.g., temperature, fan speeds, power information, operating system status, and/or other parameters known in the art), send alerts based on the monitored server device parameters, enable remote management of the server device, and/or perform a variety of other BMC functionality known in the art. Furthermore, BMC devices may be configured using different BMC firmware in order to enable different BMC functionality, and server device manufacturers may configure BMC devices in particular server devices with particular BMC firmware in order to provide particular BMC functionality and security.
For example, in server devices that are part of the POWEREDGE® server platform available from DELL® Inc. of Round Rock, Tex., United States, BMC devices may be configured (by default) with integrated Remote Access Controller (iDRAC®) firmware to provide the BMC device as an "iDRAC" that includes particular BMC functionality and security, and most users utilize their server devices/BMC devices with the default configuration. However, some users may wish to provide modified or custom BMC firmware on the BMC devices in their server devices, and doing so will change the BMC functionality and security of that BMC device/server device. As such, server device/BMC device vendors are presented with the issue of how to provide secure server devices/BMC devices that a majority of their users can trust, while also allowing some users to configure their server devices/BMC devices in a custom manner (e.g., that may limit the BMC functionality and security) without negatively effecting the reputation of the corresponding server platform.
Accordingly, it would be desirable to provide a BMC firmware security system that addresses the issues discussed above.

Baseboard management controller firmware security system


There is described a one-piece friction body having a support and at least one friction pad disposed thereon, based on friction materials containing reinforcing fibers, thermoset binders and customary additives, in which the at least one friction pad is joined to the support integrally and positive-locking by means of reinforcing fibers penetrating the boundary layer between the support and the friction pad. There is further described a method of manufacturing this friction body, comprising the steps of bonding together the friction materials containing reinforcing fibers, thermosetting binders and customary additives for the support and the at least one friction pad in the desired shape and arrangement, needling the reinforcing fibers contained in the friction materials of the composite in such manner that at least the reinforcing fibers of the friction material of the at least one friction pad penetrate at least in part the friction material of the support and of the other friction pad, respectively, and curing the needled intermediate under heat and pressure in a pressing mold corresponding to the friction body to be manufactured.

Friction bodies which contain reinforcing fibers, lubricants, abrasives, inorganic materials and fillers in a binder matrix cured under the action of heat and pressure are widely used in various technical fields, in particular as brake pads, clutch pads, or friction pads. These friction bodies generally comprise a support, or a support plate, made of metal or synthetic material and at least one friction pad disposed thereon. The joining of the friction pad and the support is usually accomplished by riveting or bonding. The metallic support may be present in the form of a plate or hub with inner or outer teeth, or, however, also in the form of a brake block support.
The friction pad normally is produced by molding the corresponding friction materials under heat and stamping or cutting. The so produced friction pad is then bonded with the use of an adhesive, or riveted, onto the support which may consist of metal or an injection-molded synthetic material. The adhesives employed for this purpose contain solvents and are cured in the oven at elevated temperatures, thereby releasing solvents. The also employed two-component adhesives do not possess the heat resistance required in the use of the friction bodies.
Joining the friction pads to the support by riveting is laborious and expensive and only offers a pointwise fixing of the friction pad, so that the latter may bulge between the "rivets". Another large drawback lies in the high cost of manufacture of the metal supports, especially when these supports have inner or outer teeth which must have a very high fitting accuracy. Last, problems arise from the different thermal expansion of the metallic support and the friction pad due to distortion of the friction pads and their becoming detached from the support.
DE 21 09 907 A, for instance, discloses a pad for vehicle brakes, in particular a brake block consisting of a plurality of parts having different qualities, which parts are integrally joined, in particular by bonding with an adhesive. The joining of these individual parts to one another, and to the required support consisting, for example, of steel, not only is expensive due to providing this metallic support and the required adhesive but also cannot be satisfactory in view of the requisite joining of the parts of the friction body to one another and to the support.
From DE 39 05 627 C2 there is known a method of manufacturing a brake body for a disc brake comprising a flat back plate and as a friction pad a lining on the back plate, with at least two lining portions with different friction properties. The method resides in charging the granular material which corresponds to the different lining portions and which may contain different portions of polishing material depending on the respective lining portions into a molding frame comprising a partitioning unit separating the individual lining portions and at the same time forming all of the lining portions on the back plate by a pressing treatment and subjecting the lining portions on the back plate to a heating treatment under pressure.
EP 0 859 164 A1 discloses a friction element, in particular for an automobile brake or a friction clutch, wherein the friction element has a pad support and a friction pad mounted thereon, said friction pad having a variable friction value μ depending on the degree of wear so as to prevent in this manner the occurrence of undesired noises during operation.
The friction bodies known from this state of the art which comprise a support and at least one friction pad disposed thereon cannot be satisfactory in so far as the friction pad and the support are manufactured separately and in a manner involving high cost and must subsequently be joined, for example by bonding with an adhesive or by riveting, which methods of attachment often do not offer the strength that is required in practice, so that there may occur deformation, or possibly even detachment, of the friction pad disposed on the support.

One-piece friction body with a support and a friction pad disposed thereon and method of its manufacture

Rex Industrie-Produkte Grafe Von Rex GmbH


An electrical circuit arrangement for detecting the switching conditions of individual switching devices includes a direct voltage source having a positive terminal and a negative terminal. Switching groups each having switching devices are connected in parallel between a respective input (e1, e2) and a respective output (a1, a2). Resistors are connected in series to a respective switching device between the respective inputs (e1, e2) and the respective outputs (a1, a2). Each one of the resistors has a preselected resistance value for providing a voltage encoded signal output across the respective inputs (e1, e2) and the respective outputs (a1, a2) when the corresponding switching device is switched on. Evaluation electronics alternately connect at predetermined time intervals the inputs (e1, e2) and outputs (a1, a2) of each of the first and second switching groups to the positive terminal and negative terminal of the direct voltage power supply to measure the voltage encoded signal for determining which switching devices are switched on.

A circuit arrangement of this type--connected to a direct voltage supply--is provided in order, by means of switching devices appertaining thereto to switch electrical consumers cooperating therewith on and off in a power-free manner. Only one signal current is directed via the switching devices by means of which power drivers, for example, relays or power semi-conductors, allocated to the electrical consumers can be actuated. In order, in the case of a plurality of switching devices allocated to a circuit arrangement, to avoid connecting each switching device to its power driver by means of its own electric line it is known to provide them with a respective resistor. The resistors differ in their resistance value so that control signals are imparted to evaluation electronics allocated to the power drivers of the electrical consumers and these control signals move to a different level in the manner of a voltage encoding.
A problem in this principle of operation which is in itself very reliable is that in the case of a multiplicity of switching devices the voltage level appertaining to the switching devices or the currents resulting therefrom no longer differ from each other in their gradation in such a way that, in particular, in the case of a plurality of switching devices operating simultaneously, a reliable detection and allocation of these switching devices or of an individual switching device is ensured by the evaluation electronics.


A silver halide photographic material comprises a silver halide emulsion layer and a non-light-sensitive hydrophilic colloidal layer provided on a support. The silver halide emulsion layer or the hydrophilic colloidal layer contains a selenium compound represented by the formula (I), (II) or (III): ##STR1## in which R.sup.11 is an aliphatic, aromatic or heterocyclic group, --OR.sup.13 or --NR.sup.14 R.sup.15 ; each of R.sup.13, R.sup.14 and R.sup.15 is hydrogen or an aliphatic or aromatic group; Ch is S, Se or Te; R.sup.12 is an aliphatic, aromatic or heterocyclic group or --COR.sup.16 ; each of R.sup.16, R.sup.21 and R.sup.31 has the same meaning as that of R.sup.11 ; M.sup.1 is Ge, Sn or Pb; M.sup.2 is Ni, Pd or Pt; each of R.sup.22 and R.sup.32 is an aliphatic or aromatic group; and each of n and m is 1 or 2.

A silver halide emulsion used for a silver halide photographic material is usually chemically sensitized with various chemical sensitizers to obtain a desired sensitivity or gradation. Examples of the chemical sensitizers include a sulfur sensitizer, a selenium sensitizer, a tellurium sensitizer, a noble metal (such as gold) sensitizer, a reduction sensitizer and a combination thereof.
An improvement of the silver halide photographic material has increasingly been demanded for several years. The recent photographic material requires very high sensitivity. Further, an improvement of the graininess and the sharpness has been required with respect to the formed image. A rapid image forming process such as a quick development process is also required. The sensitization and the sensitizers have been improved to meet these requirements.
Sulfur sensitization has most frequently been used in the silver halide photography. Numerous sulfur sensitizers have been known and used in silver halide photographic materials.
On the other hand, the sensitizing effect of selenium sensitization is higher than the effect of the sulfur sensitization. Accordingly, various selenium sensitizers have been proposed in place of the sulfur sensitizers. However, the proposed selenium sensitizers have a tendency that fogs easily occur in the image and gradation of the image is softened. Therefore, the selenium sensitizers should be further improved to be used in place of the conventional sulfur sensitizers. U.S. Pat. No. 3,297,447 discloses selenourea derivatives (e.g., dimethylselenourea) as improved selenium sensitizers. However, the improvement is still insufficient, and a rather dense fog is observed in the image (cf., Tables 1-5 in Examples of the present specification).
The sulfur sensitization and the selenium sensitization are usually used in combination with a gold sensitization. The combinations of the sensitizations remarkably improve the sensitivity of the photographic material. However, the combinations also increase the degree of fog in the image. The fog in the gold-selenium sensitization is more remarkable than that in the gold-sulfur sensitization. Accordingly, the fog caused by a selenium sensitizer should be reduced particularly in the case that the selenium sensitizer is used in combination with a gold sensitizer.
Further, the selenium sensitizers are usually not stable compounds. The sensitivity of a silver halide photographic material sensitized with a selenium sensitizer is sometime changed while the material is preserved. Therefore, a stable selenium sensitizer has also been required.

Silver halide photographic material containing selenium compound


A first phase setting circuit generates a first phase setting signal. A first synchronous signal generator generates a first synchronous clock signal having a phase set by the first phase setting signal from a multi-phase local clock signal. By removing a phase fluctuation component representing phase fluctuation of the reception data signal from a first signal including a frequency component representing a frequency offset between a multi-phase local clock signal and a reception data signal and the phase fluctuation component, a second generation unit generates a second signal including the frequency component. The first phase setting circuit updates the first phase setting signal according to the second signal.

1. Field of the Invention
The present invention relates to a reception device.
2. Description of the Background Art
Japanese Patent Application Laid-Open No. 2007-201842 discloses a passive optical network (PON) system including a station-side terminating device (OLT: optical line terminal) and a line terminating device (ONU: optical network unit). In the PON system disclosed in Japanese Patent Application Laid-Open No. 2007-201842, the OLT generates a transmission signal synchronized with a clock signal which has a predetermined frequency and is synchronized with a reference clock signal for synchronization generated by a station-side reference clock source. Accordingly, the ONU reproduces a clock signal from the transmission signal from the OLT, converts a frequency of the clock signal into a predetermined frequency, and generates a reference clock signal for use in Ethernet (registered trademark) equipment.
Japanese Patent Application Laid-Open No. 2011-9984 discloses a gigabit Ethernet-passive optical network (GEPON) system including a station-side device and a terminal-side device. In the GEPON system disclosed in Japanese Patent Application Laid-Open No. 2011-9984, a station-side device uses a device clock generated from a network reference clock as an operation clock, generates transmission data by adding time stamp information to input data, generates correlation information representing a correlation between the network reference clock and the time stamp information, and multiplexes the generated correlation information into downlink data. The terminal-side device reproduces the network reference clock based on the time stamp information and the correlation information included in the transmission data transmitted from the station-side device.
Japanese Patent Application Laid-Open No. 2003-283332 discloses a synchronization circuit including a clock selector, a phase control unit, a phase information storage unit, and a frequency offset control unit. The clock selector outputs a selected clock having a desired phase from a multi-phase clock. The phase control unit outputs a phase control signal based on a comparison result of phases of input data and the selected clock. The phase information storage unit stores phase information from the phase control unit, and controls the clock selector. The frequency offset control unit outputs an offset control signal according to the number of phase control signal outputs, and outputs an offset control signal according to a cumulative number when the cumulative number of the phase control signal exceeds an activation threshold value.
Japanese Patent Application Laid-Open No. 2007-43460 discloses a bit synchronization circuit having an initial phase determination unit. The initial phase determination unit detects a variation point of a reception signal using a multi-phase clock during a preamble reception period of burst data, and outputs initial phase information including a phase number of a clock synchronized with the variation point.
U.S. Pat. No. 7,692,499 discloses a system including a phase-frequency comparator, a storage unit, an adaptive filter, and a digital control oscillator. The phase/frequency comparator detects an error between a reference clock and a feedback clock. The storage unit stores a model which predicts frequency fluctuation of a temperature-compensated crystal oscillator. The adaptive filter includes a loop filter and an algorithm for predicting frequency fluctuation based on a model, and generates a selected output signal based on filter data and prediction data. The digital control oscillator sets a phase of an output clock signal according to an output signal of the adaptive filter. The adaptive filter receives an error signal and outputs filter data in a normal time in which a reference clock is valid, and outputs prediction data in a holdover time in which a reference clock is invalid.
As disclosed in Japanese Patent Application Laid-Open Nos. 2007-201842 and 2011-9984, a reference clock (synchronous clock) can be generated using a clock reproduction unit provided in the ONU.
However, a reception data signal received by the ONU from the OLT is affected by fluctuation within the OLT or noise in a transmission process. In a data reproduction clock signal reproduced based on the reception data signal, frequency fluctuation is large (a cutoff frequency of jitter transfer characteristics from the reception data signal to the clock signal for reproducing data is too high). Therefore, the above-described reproduction clock signal cannot be used as a synchronous clock signal.
In addition, it is also necessary to use a clock signal (transmission clock signal) synchronized with an OLT-side clock signal in generation of a transmission signal to be transmitted to the OLT. The clock signal for reproducing data also cannot be used as a transmission clock signal because frequency fluctuation is too large.
In addition, as in U.S. Pat. No. 7,692,499, technology for supplying a synchronous clock signal for a holdover time based on data stored for a normal time is well known. However, in particular, as in Japanese Patent Application Laid-Open No. 2003-283332, when a clock signal of a desired phase is generated as a synchronous clock signal by performing selection from a multi-phase clock or mixing a multi-phase clock signal, data to be stored is not particularly obvious.


Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively small parts of the user's logic as synthesized for the FPGA technology is resynthesized for the structured ASIC implementation. The resynthesis may handle different kinds of parts of the logic differently. For example, for a part for which an ASIC synthesis is already known and available in a library, the known ASIC synthesis may be retrieved from the library. More extensive resynthesis (including, for example, logic minimization and function packing) may be performed on other parts of the logic for which library syntheses are not available.

This invention relates to methods for producing application-specific integrated circuit ("ASIC") equivalents of programmable logic devices such as field-programmable gate arrays ("FPGAs").
The ASICs referred to herein are structured ASICs in the sense that they have a basic organization, structure, or architecture that is predetermined or fixed. Only certain features of the ASIC are customizable to meet each user's particular design. For example, many of the device-fabrication masks that are needed to make the ASIC are always at least substantially the same. Only some of the masks in the set are customized to implement a particular user's design. Examples of features that are always at least substantially the same may include the masks that produce the operational elements of the ASIC. Examples of features that may be customized include certain aspects of the circuitry that interconnects various operational elements. Use of ASICs that are basically structured in this way, and that therefore require only some masks to be customized, greatly simplifies and speeds up the process of producing ASIC equivalents of FPGAs. This approach also has numerous other advantages such as lower cost, lower risk of error, etc.
Chua et al. U.S. patent application Ser. No. 10/884,460, filed Jul. 2, 2004, ("the Chua reference") discusses some examples of when it may be desirable to provide an ASIC equivalent of an FPGA. The Chua reference (which is hereby incorporated by reference in its entirety) shows ASIC architectures that are structured to facilitate providing FPGA equivalents. The Chua reference also shows methods for equivalently implementing a user's logic design in either an FPGA or a structured ASIC. Improvements, refinements, and enhancements in this general type of technology are always being sought, and the present invention provides various such improvements, refinements, and enhancements.

Methods of producing application-specific integrated circuit equivalents of programmable logic


A computer-implemented method, program product and system for planning execution of a plurality of tasks according to a plurality of dependencies includes receiving an indication of a task type and execution time, ordering the tasks into a task list according to a primary ordering criterion, receiving an indication of a dependency type for the task type and an indication of a dependency time for the execution time of a predecessor one of the tasks, ordering the dependencies into a dependency list according to the primary ordering criterion, scanning the dependency list for resolving each current one of the dependencies, identifying the predecessor task as a current one of the tasks having the task type meeting the dependency type and the execution time meeting the dependency time, and planning the execution of the tasks according to the resolved dependencies.

Planning execution of different tasks (i.e., the control of their flow over time in order to achieve a desired object) is a commonplace activity in a number of applications. A typical example is a workload scheduler, or simply scheduler, which is used in a data-processing system to control the execution of large quantities of data-processing jobs, or simply jobs (i.e., any work unit suitable to be executed thereon).
For this purpose, the scheduler creates a workload plan, or simply a plan (establishing the flow of execution of the jobs); particularly, the plan is created by arranging the jobs in succession according to a desired execution time thereof.
The execution of some jobs may also be constrained by one or more dependencies on other jobs (for example, when the jobs process the results of the other jobs). Generally, each dependency indicates a job (referred to as predecessor job), whose execution enables the execution of another job (referred to as successor job). Moreover, the dependency may also indicate a dependency time (for example, a dependency timeframe), which further requires that the execution time of the predecessor job meets the dependency timeframe to enable the execution of the successor job (for example, when the execution time of the predecessor job falls within the dependency timeframe); the dependency timeframe may be specified either in absolute terms (for example, a fixed time interval) or in relative terms with respect to the execution time of the successor job (for example, a time interval around it).
The plan may comprise the execution of multiple instances of some jobs of the same type. Therefore, each dependency is to be resolved by identifying the actual predecessor job to be linked to the successor job, by selecting it among all the eligible jobs of the required type having the execution time within the dependency timeframe. The selection of the predecessor job is performed according to pre-defined rules. For example, the predecessor job may be selected so as to have the execution time that is closest to the execution time of the successor job before it (comprised when they are the same); if this is not possible, the predecessor job is selected so as to have the execution time that is closest to the execution time of the successor job after it.
The resolution of each dependency then involves the searching of the corresponding predecessor job throughout all the jobs (for example, in the plan when a new job is to be added thereto). However, this requires several scanning of the jobs backwards and forwards. Therefore, the resolution of the dependencies may become quite long, especially when a very high number of jobs are to be executed (for example, several thousands in complex production environments), with a corresponding increase of the time required for creating the plan. All of the above has a detrimental effect on the performance of the scheduler, and then of the whole data-processing system.
Several techniques have been proposed in the art for improving the performance of a scheduler, for example, as disclosed in the following documents (the entire disclosures of which are herein incorporated by reference).
Particularly, U.S. Pat. No. 8,392,397 discloses a selection of provenance dependency function, US-A-2011/0246998 discloses a reorganization of tasks to achieve optimization of resources, US-A-2009/0241117 discloses an integration of flow orchestration and scheduling, US-A-2012/0084789 discloses an aggregation topology for optimizing task graphs, U.S. Pat. No. 7,661,090 discloses an optimization of operation sequence to allow manual operations to be combined when feasible, US-A-2009/0013322 discloses a scheduler allowing task overruns, US-A-2005/0149927 discloses a determination of executability of tasks based on required resource amount, U.S. Pat. No. 8,296,170 discloses a management of deadlines for completing activities, and "Optimizing Grid-Based Workflow Execution by Gurmeet Singh, Carl Kesselman and Ewa Deelman, Journal of Grid Computing (2006)" discloses an application of abstraction refinement to large-scale static scheduling problem.
However, the planning techniques known in the art are not completely satisfactory, especially with respect to the resolution of the dependencies.

Planning execution of tasks with dependency resolution

International Business Machines Corporation


A method and apparatus to analyze noise in a pulse logic digital circuit comprising identifying a channel connected component (CCC) in the pulse logic digital circuit design, said CCC comprising a pulse generator. Modifying the pulse logic digital circuit by disconnecting the pulse generator form an input of the CCC in the pulse logic digital circuit design. Turning on the pulse logic digital circuit, inputting a noise signal to the CCC and monitoring an output of the pulse logic digital circuit during the time the pulse logic digital circuit is turn on.

1. Field of the Invention
The present invention is related to the field of circuit design. In particular, the present invention is related to method and apparatus to analyze noise in a pulse logic digital circuit design.
2. Description of the Related Art
Static signal integrity analysis is typically used during the design verification stages of an electronic circuit to ensure the functionality of the silicon comprising the circuit for various electrical noise conditions. A noise problem in the design verification state of the electronic circuit may cause functional errors or may impact the frequency performance of the electronic circuit.
FIG. 1 illustrates an example of a conventional pulse logic digital circuit. Pulse logic circuits are circuits used to maximize the performance of digital circuits and work using a pull-up/pull down network. As illustrated in FIG. 1, the example pulse logic digital circuit 100 comprises a PMOS transistor 105 coupled to NMOS transistors 110-125 as illustrated. The signal value at node N1 is maintained by a keeper circuit comprising back to back inverters 130 and 135 as illustrated. The clock signal CLK is inverted by inverter 140 to form the NCLK signal. The CLK signal and the NCLK signal is input into the gates of transistors 110 and 120 respectively. When CLK is 0 the PMOS transistor 105 is on and precharges node N1 to a logical 1. At this time NMOS 110 is off and therefore, the voltage value at N1 is maintained at 1. Assuming a logical 1 at inputs A and B of NMOS transistors 115 and 125 respectively, during the transition of CLK from 0 to 1, NMOS transistor 110 is turned on and NMOS transistor 120 is turns off after an inverter delay. Thus, during the inverter delay all NMOS transistors 110-125 are turned on, discharging node N1 to a logical 0, and this results in a logical 1 at the output of the keeper. Thus, for the circuit of FIG. 1, only when both transistors 115 and 125 have a 1 bat their inputs the output of the pulse logic digital circuit is a 1.
Conventional verification tools are incapable of accurately analyzing pulse logic digital circuits because the conventional verification tools either simplify the circuit to an equivalent circuit or are unable to generate a steady state stimuli condition which tests the node N1 under evaluation conditions. For example, the conventional verification tools may simplify FIG. 1 to an AND gate coupled to a latch and apply steady state signals to inputs of the equivalent circuit to analyze noise effects. Simplifying and/or analyzing pulse logic digital circuits using steady state signals is inaccurate, because during normal operation, the pulse logic digital circuits latch the signals at node N1 during the inverter delay i.e., during a transition of the CLK signal as illustrated with respect to FIG. 1. Thus, conventional verification tools fail to indicate problems such as noise related failures in pulse logic digital circuits.

Method and apparatus to analyze noise in a pulse logic digital circuit design


A plasma welding method for a golf club head includes the steps of: preparing a club head body and a striking plate, and mounting the striking plate to the club head body; moving a plasma nozzle to aim to a connection line formed between the club head body and the striking plate before the plasma welding; tilting the plasma nozzle a predetermined inclined angle with respect to a vertical direction of the combination of the club head body and the striking plate for the plasma welding; and controlling the tilted plasma nozzle to weld the striking plate to the club head body so as to constitute the golf club head.

1. Field of the Invention
The present invention relates to a plasma welding method for a golf club head. Particularly, the present invention relates to the plasma welding method of tilting a plasma nozzle a predetermined angle with respect to the golf club head for avoiding obstruction of a neck portion or a hosel of the golf club head. More particularly, the present invention relates to the plasma welding method for welding on a connection line, within a predetermined section, between a striking plate and a club head body.
2. Description of the Related Art
Referring now to FIGS. 1 and 2, a conventional golf club head includes a club head body 91 and a striking plate 92 mounted to the club head body 91, as disclosed in TWN Patent Pub. No. 585,792, entitled "golf club head and manufacturing method therefor (II)," TWN Patent Pub. No. I225,421, entitled "golf club head structure," TWN Patent Pub. No. I226,251, entitled "connecting structure for a striking plate with a golf club head," and U.S. Pat. No. 6,099,414, entitled "golf club head and method for producing the same" etc. A connection line 93 exists between the club head body 91 and the striking plate 92 which are welded by a suitable welding method. In welding operation, a variety of welding methods, such as tungsten inert gas (TIG) welding, laser welding, plasma welding or other suitable welding methods, may be selectively used.
The above plasma welding may be selected to weld the club head body 91 and the striking plate 92, which carries out advantages of high-energy, high-accuracy, high-speed and high-quality welding, and further minimizes or attenuates a heat affected zone of material in a welding process.
In plasma welding operation, a movable plasma nozzle 94 is disposed on a slide track (not shown) and aligned with the connection line 93 existing between the club head body 91 and the striking plate 92. Subsequently, the plasma nozzle 94 is moved downward to an operating level above the connection line 93, and welded along the connection line 93 by an automatic welding process. The club head body 91 has a neck portion 91 and a hosel 912 connected thereto. It should be noted that the neck portion 911, however, is located between the hosel 912 and the club head body 91 and extended upward from a level of the striking plate 92. The neck portion 911 may unavoidably obstruct or interfere in a runway of the plasma nozzle 94 in the plasma welding since the neck portion 911, to a certain extent, is too close to the connection line 93. Consequently, the plasma nozzle 94 running at the operating level cannot pass through above a section of the connection line 93 adjacent to the neck portion 911 of the club head body 91 due to interference with the neck portion 911.
As explained above, the automatic plasma welding process is only suitable for welding the other section of the connection line 93 away from the neck portion 911 of the club head body 91. Meanwhile, other suitable welding methods, a TIG welding method for example, may be used to manually weld the section of the connection line 93 adjacent to the neck portion 911 of the club head body 91. Such welding method may cause poor quality, increased deformation and low efficiency of welding on the connection line 93 adjacent to the neck portion 911 of the club head body 91. Accordingly, such practice, however, may limit the welding process to carry out to be a complete automatic welding process. Hence, there is a need for improving the plasma welding process for the golf club head.
The present invention intends to provide the plasma welding method of tilting a plasma nozzle a predetermined angle with respect to a golf club head for avoiding obstruction of a neck portion or a hosel of the golf club head in such a way to mitigate and overcome the above problem. This permits the plasma nozzle passing through a connection line adjacent to the neck portion of the golf club head in the plasma welding process. Accordingly, the plasma welding method carries out a complete automatic plasma welding process so as to improve the welding efficiency and quality.

Plasma welding method for a golf club head


An image processing device is capable of inhibiting the moire and the false color from occurring in the case of performing color display using four colors of sub-pixels. The image processing device has filter processing sections. The filter processing sections limit frequency bands of signals R, G, B, and W in an X direction and a Y direction in accordance with a positional relationship between the sub-pixels corresponding to each of the colors and the other sub-pixels. Further, the filter processing sections control a frequency response of image signals of the respective colors in accordance with an amplitude of a high frequency component of the image signal corresponding to each of the other colors.

1. Technical Field
The present invention relates to image processing performed in the case of performing color display using four colors of sub-pixels.
2. Related Art
As an arrangement of pixels in a display device using three primary colors, there can be cited a stripe arrangement and a delta arrangement (see, e.g., JP-A-07-006703 (Document 1)). In such a display device, each pixel is composed of three sub-pixels. Besides these arrangements, there is known the Bayer arrangement. In the Bayer arrangement, one pixel is composed of totally four sub-pixels arranged 2×2 including two G (green) sub-pixels, one R (red) sub-pixel, and one B (blue) sub-pixel.
In the display device using the Bayer arrangement, color display is generally performed using image data with the number of pixels a quarter of the number of pixels of image data input thereto. In this case, the resolution of the image data used actually is lower than the resolution of the image data input thereto. Therefore, in order to suppress the moire caused by folding noise, a filter process for limiting a frequency band of an image signal is performed. For example, in the case of R and B image signals, in order for preventing moire caused by a high-frequency component, it is necessary to limit the frequency band of both of the vertical and lateral directions to a half (i.e., ½) thereof. It should be noted that since a G image signal has twice as many sub-pixels as the R or B image signal, the limitation range of the band can be smaller than those of the R and B image signals.
There is a case in which the color display is performed using four primary colors (or more primary colors) for the purpose of improvement of color reproducibility and brightness. For example, JP-A-2006-267541 (Document 2) discloses an image display device having either one of the G sub-pixels in the Bayer arrangement replaced with a white (W) or a cyan (C) sub-pixel to thereby perform the color display with four colors of sub-pixels. Further, JP-A-2000-338950 (Document 3) discloses a technology for calculating color image signals of the respective colors in the case of having a color display section of four or more primary colors. It should be noted that the "primary color" mentioned here denotes the color forming a base of the color mixture (an additive process), and is not limited to the light's three primary colors.
In the case of performing the color display using the four colors of sub-pixels, if the band of the image signal is limited independently color by color, moire or false color may occur in some cases.

Image processing device, display device, and image processing method


Embodiments of the invention relate to reading at least one locked, encrypted computer file encrypted by an encryption filter driver running on an operating system of a computer system, with an added kernel driver, while the operating system is running and reading at least one locked, unencrypted computer file in a computer system with an operating system with an added kernel driver while the operating system is running. An exemplary embodiment includes getting the handle of the locked, encrypted computer file, causing encryption key information associated with the locked, encrypted computer file to be processed, and reading data from the locked, encrypted computer file by using the added kernel driver.

Encrypting Computer Files
A computer system may include an encryption filter driver which runs on an operating system of the computer system. For example, MICROSOFT has an encryption filter driver that is part of MICROSOFT'S New Technology File System (hereinafter "NTFS") Encrypting File System (hereinafter "EFS") that runs on MICROSOFT'S WINDOWS operating system of a computer system. In addition, the kernel of an operating system of a computer system and processes and programs running on the computer system can encrypt computer files on the computer system via the encryption filter driver. For example, the WINDOWS kernel and WINDOWS processes and programs accessing computer files on the NTFS EFS have the ability to encrypt computer files to prevent their contents from being interpreted by another user via the NTFS EFS filter driver which is encapsulated in NTFS.
Locking Computer Files
In addition, the kernel of an operating system of a computer system and processes and programs running on the computer system can lock (i.e. protect) computer files on the computer system.
Locking at File-Open Time
One type of locking is locking at file-open time. For example, the WINDOWS kernel and WINDOWS processes and programs have the ability to lock computer files from being opened and read by other processes by locking (i.e. protecting) the computer files on a computer system running the WINDOWS operating system. This is done by the kernel or a process opening a computer file and not granting specific permissions (such as read) to other processes, thereby locking the computer file. As long as the kernel or the process holds the computer file open, other processes are subject to the permissions granted by the kernel or the process. If another process attempts to open such a locked computer file, (1) WINDOWS "sharing violation" would occur and the data in the locked computer file could not be read by that other process.
Byte-Range Locking
Another type of locking is byte-range locking. Byte-range locking gives a process the ability to lock at least one portion of at least one computer file from being read by another process. Although another process may be able to open such a byte-range locked file, if that other process attempts to read a portion of the computer file which is byte-range locked, a WINDOWS "locking violation" would occur and the data in the byte-range locked computer file could not be read by that other process.
In some circumstances, a computer file can be encrypted and locked at the same time.
Need for Accessing Locked Computer Files
The data in locked computer files can be extremely important to various computer applications that access computer files, such as computer file backup applications, virus scanning applications, and indexer applications. It is important (1) for such computer applications to be able to read and open every computer file on a computer system and (2) for computer file backup applications to maintain the encrypted status of these computer files throughout the backup of the computer system, such that even in the backup image, these computer files remain encrypted and inaccessible until they are restored to the correct user.
Prior Art Systems
Currently, prior art computer file access systems (such as a computer file backup systems) fail to address this need.
Sector-Wise Copy
In a first prior art approach, as shown in prior art FIG. 1A, a first prior art computer file access system (1) performs a sector-wise copy of data on a storage device (e.g. a hard disk) of a computer system and (2) generates an entire image of the storage device. Unfortunately, this first prior art computer file backup system produces an image of the storage device that is a monolithic copy of the storage device with individual files in the monolithic copy being unreadable without a great deal of effort. In other words, data in this format is difficult to associate with computer files and, therefore, are of little use to many computer applications, such as indexer applications. Therefore, this first prior art computer file backup system makes performing a "single file restore" from the image of the storage device very difficult to do.
Shutdown & Preboot
In a second prior art approach, as shown in prior art FIG. 1B, a second prior art computer file backup system (1) shuts down a computer system, (2) restarts the computer system in a "preboot" environment, and copies a computer file copy in the "preboot" environment. In the "preboot" environment, the computer file would not be locked. Thus, with this second prior art computer file backup system, the computer system is either rebooted again or finishes booting to the operating system of the computer system. This second prior art computer file backup system is poor because it requires a reboot to be able to copy computer files. Therefore, this second prior art computer file backup system cannot perform a computer file backup on a computer system while the computer system is running, such that the user of the computer system could not continue to run other computer applications on the computer system.
Combination
In a third prior art approach, as shown in prior art FIG. 1C, a third prior art computer file backup system uses the methods and systems described in commonly owned, pending U.S. patent application Ser. No. 10/737,581 (entitled "Method and System of Accessing at Least One Target File in a Computer System with an Operating System with File Locking Implemented at a File-Open Time", filed Dec. 15, 2003) and/or the methods and systems described in commonly owned, pending U.S. patent application Ser. No. 10/736,825 (entitled "Method and System of Accessing at Least One Target File in a Computer System with an Operating System with File Locking Implemented with Byte-Range Locking", filed Dec. 15, 2003), which allow computer applications to access locked computer file data from either the filesystem or the cache manager of a computer system while the computer system is running. Unfortunately, using this third prior art computer file backup system on a locked, encrypted computer file either (1) produces an unencrypted version of the computer file or (2) produces a useless, encrypted version of the computer file, because the third prior art computer file backup system fails to get encryption key information associated with the locked, encrypted computer file. In a computer system running the WINDOWS operating system, the encryption key information is the EFS key information associated with a locked, encrypted computer file.
Volume Shadow Copy
In a fourth prior art approach, as shown in prior art FIG. 1D, a fourth prior art computer file backup system, for WINDOWS XP and higher, uses a Volume Shadow Copy service to backup computer files if the Volume Shadow Copy service is enabled. In particular, the fourth prior art computer file backup system (1) creates a Shadow Copy of the storage device (i.e. hard disk) of the computer system, using a Window operating system facility and (2) performs a backup from this Shadow Copy, which remains unmodified by other processes running on the computer system. Unfortunately, this fourth prior art computer file backup system is only supported by MICROSOFT'S WINDOWS XP operating system (hereinafter "XP") and later editions of the Windows operating system. Further, this fourth prior art computer file backup system may potentially cause the computer system to run out of storage space sufficient to maintain the Shadow Copy.
Therefore, a method and system of reading at least one locked, encrypted computer file encrypted by an encryption filter driver running on an operating system of a computer system, with an added kernel driver, while the operating system is running and reading at least one locked, unencrypted computer file in a computer system with an operating system with an added kernel driver while the operating system is running is needed.

Reading a locked windows NFTS EFS encrypted computer file


Apparatuses, methods, and non-transitory computer readable medium that evaluate a source code scanner are described. In one implementation, the method comprises obtaining source code. One or more good code snippets and one or more bad code snippets are inserted into the source code to obtain a modified source code. An issue list generated by the source code scanner upon scanning the modified source code is obtained. The issue list comprises code segments having security defects identified by the source code scanner, reasons for the security defects, and locations of the security defects in the modified source code. The code segments present in the issue list are compared with the one or more good code snippets and the one or more bad code snippets. A plurality of metrics, indicating quality of the source code scanner, are generated based on the comparison.

Generally, most of audit standards, such as Payment Card Industry-Data Security Standards (PCI-DSS), Health Insurance Portability and Accountability Act (HIPPA), and Gramm-Leach-Bliley Act (GLBA) ask for source code auditing. A source code audit is typically carried out using a source code scanner to identify irregularities or security defects in source codes. In industry, the source code scanners are also referred to as source code analyzers or source code scanning tools. A code segment in a source code may be functionally correct, yet it may be written in a way that the code easily allows security attackers to break-in. Therefore, code authors have a combined responsibility to both write functionally correct code and code that is relatively harder, if not impossible, to break-in by a malicious attacker. While the issue of functional correctness of the code has been much addressed in software testing industry, the issue of secure coding correctness is relatively new
The source code scanning tools scan the source code and identify irregularities present in the source code. In an example, the source code scanners may look for the irregularities such as, misuse of code constructs that easily allows the code to break or fail, design flaws within the source code, absence of logical organization in the source code, missing generics, errors in conditional logic, and issues that come up during execution of the source code. A wide variety of security code defects are known in industry, and standards bodies have reported top-10 or top-35 types of defects list. Source code scanners benchmark themselves by being able to detect known or well-documented source code security breaches. Nowadays, a wide range of the source code scanners are available in market. Therefore, organizations may find it difficult to select a source code scanner that meet requirements of their project, and identify irregularities in the source code accurately.

Systems and methods for evaluating a source code scanner


A stretcher with a dedicated multi-functional removable floating patient support platform is described. The stretcher has a lower frame assembly and an upper frame assembly is vertically displaceable thereover in an adjustable manner. The patient support platform is a rigid rectangular platform having a substantial portion thereof constructed of radiolucent material. The patient support platform is supported on bearings and retained captive on a platform support structure, whereby to slide axially thereof. Restraining hingeable side frames are provided and permit the patient support platform to be displaced laterally on the bearings to permit the patient support platform to be transferred from the platform support structure laterally thereof, in an effortless support manner.

There are a multitude of different stretcher structures and some of these comprise a base structure having a patient carrier which is removable from the base structure whereby to transport a patient to another location or a bed. U.S. Pat. No. 4,037,871 describes such a structure. However, the carrier portion of the stretcher is not suitable for multi-purpose use such as to support a patient under diagnostic equipment or for surgical procedures. In other words, the patient must be removed from such carrier. Furthermore, the carrier is not constructed for use with other support structures, other than the ambulance cot as described in that patent. U.S. Pat. No. 4,977,630 also shows a patient-mover device which is strappable on a stretcher. Again, the device is so constructed that it does not have multi-functional uses, and the patient must be removed therefrom, and transferred to other support structures for diagnostic or surgical procedures. Many hospital beds or stretcher structures are known whereby to tilt a patient to a Trendelenberg position. The use of extendible cylinders to effect such displacement of the patient support structure is also known as can be seen from U.S. Pat. No. 4,912,787. This patent also teaches that the top or the patient-support portion of the stretcher can be used for x-ray examination. A patient-support platform for x-ray diagnostic purposes is known for example, from U.S. Pat. Nos. 3,947,686 and 4,145,612.
It is pointed out that known stretcher construction or hospital bed structures provide various features, but during the transport of a patient, it becomes necessary to transfer the patient from the stretcher structure in order to transfer the patient to diagnostic devices or for surgical procedures, and such displacement and transfer can be harmful to the patient. Accordingly, there is a need to provide a stretcher wherein the patient can be supported on a dedicated multi-functional support platform and undergo examinations, or interventional radiology, or surgical procedures until it becomes safe to transfer the patient onto a hospital bed.

Stretcher with dedicated multi-functional removable floating patient support platform


A gesture recognition apparatus, a gesture recognition method, a computer device and a storage medium are disclosed. The gesture recognition apparatus includes a controller, a first distance sensor and a second distance sensor, wherein a first measurement area of the first distance sensor partially overlaps a second measurement area of the second distance sensor; and the controller is configured to recognize a gesture to be measured according to a first trajectory and a second trajectory as well as a position relationship between the first distance sensor and the second distance sensor.

As one of distance measurement principles, the optical time-of-flight (TOF) distance measurement principle is mainly implemented by continuously sending an optical pulse to a measured target, receiving the optical pulse returned from the measured target by a sensor, and detecting a flight (round trip) time of the optical pulse to obtain a distance to the measured target.

Gesture recognition apparatus, gesture recognition method, computer device and storage medium


Systems and methods that use cloud-hosted control system back-up processing to replace the functionality of a failed control panel are provided. Systems can include a remote monitoring station, a remote control panel device, and a local control system installed in a region, the local control system including a local control panel and at least one device. When operating in a normal mode, the at least one device can communicate with the local control panel, the local control panel can communicate with the remote monitoring station, and the remote control panel device can be inactive. When operating in a back-up mode, the remote control panel device can be active, the at least one device can communicate with the remote control panel device, the remote control panel device can communicate with the remote monitoring station, and the local control panel can be inactive.

Known control systems can include, for example, alarm security systems, access control systems, fire control systems, and the like. These types of control systems are often dependent on a local control panel to operate. For example, when a control system is installed in a building, sensors and/or output devices can be installed throughout the building, and each of the sensors and/or output devices can communicate and rely on a control panel that is also located in the building.
Because of the dependent nature of known control systems, the hardware and/or software failure of the control panel is problematic. For example, failed hardware and/or software must be replaced before the control system can continue operation. But it is not always possible to replace the hardware or software in a timely manner.
There is thus a continuing, ongoing need for systems and methods to protect against the failure of local control panels.

System and method to protect against local control failure using cloud-hosted control system back-up processing


A memory cell structure and control of the memory operation are simplified, and the cost of production is decreased, by way of a semiconductor nonvolatile memory having a transistor including a gate electrode provided on a p-type semiconductor substrate via a gate insulating film, and a source region and a drain region, which are a pair of n-type impurity diffusion regions in the surface layer region of the semiconductor substrate at positions sandwiching the gate electrodes therebetween. A first resistance-varying portion and a second resistance-varying portion are sandwiched by the source region, drain region and channel-forming region. The n-type impurity concentration in the resistance-varying portions is lower than in the source and drain regions.

1. Field of the Invention
This invention relates to a semiconductor nonvolatile memory, to a method of recording data into the semiconductor nonvolatile memory (writing method and erasing method) and to a method of reading data from the semiconductor nonvolatile memory.
2. Description of the Related Art
Owing to its capability of holding stored data without requiring electric power, the semiconductor nonvolatile memory has been utilized as a memory in low-power-consumption equipment such as portable equipment.
In recent years, there has been proposed, as a semiconductor nonvolatile memory, a structure equipped with a memory cell of the MONOS (metal oxide nitride oxide) type having at least two gate electrodes (see, for example, U.S. Pat. No. 5,408,115 and U.S. Pat. No. 6,399,441).
The memory cells of the MONOS type are of the constitution including a transistor having a general gate-insulating film and a transistor having a gate-insulating film comprising an ONO laminated insulating film capable of accumulating an electric charge, which are formed on the channel-forming regions.
In the semiconductor nonvolatile memories disclosed in the above U.S. Pat. No. 5,408,115 and U.S. Pat. No. 6,399,441, however, the channel concentrations must be separately optimized in the channel-forming regions that are formed under the ONO laminated insulating film and under the gate-insulating film. This, however, involves complex operation when it is attempted to operate the memory and, besides, makes it difficult to easily and efficiently inject the electric charge into the ONO laminated insulating film.
Further, the memory cell structure becomes complex since it has at least two gate electrodes as well as a gate-insulating film that includes the ONO laminated insulating film, and the cost of production increases.
In order to decrease the area occupied by the memory cell, therefore, there has been proposed a structure in which the gate electrode on the ONO laminated insulating film is formed in the side wall type. When a voltage is applied, however, the electrode of the side wall type exhibits an increased resistance bringing about such a hindrance that the speed for reading out the data becomes low.

Semiconductor nonvolatile memory, method of recording data in the semiconductor nonvolatile memory and method of reading data from the semiconductor nonvolatile memory


An Internet infrastructure with network devices and end point devices containing service module manager and service modules, that supports packet routing and vectoring based on payload comparison with spatially related templates. The network device that supports packet content analysis on arriving packet, consists of a plurality of packet switched interface circuitries, user interface circuitry, local storage comprising the service module manager software and a plurality of local service modules, and processing circuitry communicatively coupled to each of the packet switched interfaces, local storage and user interface circuit. The processing circuitry executes service module manager and thus analyzes the packet content and applies one or more selected local service module processing using the packet. The service module manager contains, for comparisons, header templates, spatially related payload trigger templates and spatially related payload supplemental templates. The spatially related templates attempt to identify a target data with certainty. The processing circuitry takes one or more actions on the packet of a target data, by applying selected service modules.

1. Field of the Invention
This invention generally relates to communication systems.
2. Related Art
Internet has rapidly become widespread among population because of its ability to traffic audio, video, data packets at increased speeds. Internet infrastructure typically includes network devices such as routers, switches, packet switched exchanges, access points and Internet service provider's networks (ISPN), Internet communication pathways and end point devices. The end point devices include personal or laptop computers, servers, set top boxes, handheld data/communication devices and other client devices, for example. All these end point devices residing in remote locations exchange audio, video, and data packets using any available Internet communication pathway.
Various remote and local services relating to communicated data are available to conventional end-point devices. Typically, an end-point device analyzes received data to determine if such services are warranted. Before performing such analysis on packetized, received data, the end-point device first reconstructs the packets (desegments) and stores the reconstructed data locally. If analysis of the reconstructed data so indicates, the end-point device will deliver the reconstructed data to the local or remote service—a process that often requires resegmentation and retransmission (for a remote service). This process often results in wasted communication, local storage, local processing and routing infrastructure resources. Moreover, even if the end-point device should perform such analysis and delivery, it need not do so to thwart a highly desired service. This applies to both source and destination end-point devices, which may be, for example, client devices and servers.
Typically, the exchange of audio, video and data packets via the Internet happens without any internal control over the packets, other than the network devices routing the packets from a source end point device to one or more destination end point devices. In other words, typical packet flow in an Internet infrastructure is unrestrained. Though such free flow of packets is usually beneficial, some packets, inadvertently or deliberately, may contain disruptive content (e.g., virus, worms or other malware), unauthorized content (e.g., pirated copies of video, audio, text or program code), unwanted content (e.g., pornography or adult themes), or unsuitable content (e.g., content unlikely to benefit a particular region because of customs, regional constraints, or language limitations). Conventional end point devices have the burden of restraining presentation or execution of such disruptive, unauthorized, unwanted and unsuitable content. Often, however, such end point devices are incapable of doing so. For example, even with malware protection software active, end point devices are often infected. With blocking software installed, pornography is still displayed to children. Other types of filters blocking such types of content also fail with undesirable results.
A target data, from a packet of any of the above mentioned target data or files is not easily identified by analyzing payload portions of the segmented packet because of arbitrary lengths of the packets.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention.

Packet routing and vectoring based on payload comparison with spatially related templates