An electrostatic discharge protection device has a substrate, a P-well, a N-well, and an isolation portion. The P-well and N-well formed in the substrate are neighboring to each other. Along a specific direction, the P-well has a first N-type, a first P-type, a second N-type, a second P-type, and a third N-type high doping regions sequentially located thereon, and the N-well has a third P-type, a fourth N-type, a fourth P-type, a fifth N-type, and a fifth P-type high doping regions sequentially located thereon. The first N-type, the third N-type, the first P-type, and the second P-type high doping regions are coupled to a ground end, the third P-type, the fifth P-type, the fourth N-type, and the fifth N-type high doping regions are coupled to a voltage supply end, and the second N-type and the fourth P type high doping regions are coupled to an input/output end.

1. Technical Field
The present disclosure relates to an electrostatic discharge protection device, in particular, to an electrostatic discharge protection device with embedded silicon controlled rectifier (SCR) and an electronic device thereof.
2. Description of Related Art
To protect electronic elements (e.g. integrated circuit) from encountering electrostatic discharge and being damaged during the design, production, and use processes. Thus, there is usually an electrostatic discharge protection circuit set on the path connected to the bonding wire in the electronic device to protect the inner circuit of the electronic device.
Please refer to FIG. 1, FIG. 1 is a circuit diagram of an electronic device with a traditional electrostatic discharge protection device. As shown in FIG. 1, the electronic device comprises an input/output end 2′, a supply voltage end VDD, a ground end GND, and an electrostatic protection device and chip 6′, wherein the electrostatic protection device consists of the diode 3′, 4′ and an plug-in clamp circuit 5′ (consisted of a plurality of transistors and a resistor for instance).
An anode of the diode 3′ and a cathode of the diode 4′ are connected to the input/output end 2′. A cathode of the diode 3′ is connected to the supply voltage end VDD and an anode of the diode 4′ is connected to the ground end GND. The clamping circuit 5′ is connected between the supply voltage end VDD and the ground end GND. The chip 6′ is connected to the supply voltage end VDD, the input/output end 2′ and the ground end GND. The chip 6′ is equivalent to the combination of multiple transistors; for instance, one of the transistors 7′ is connected to the input/output end 2′ and the ground end GND. The ground end GND is connected to a ground voltage, and the supply voltage end VDD is connected to a supply voltage, wherein the supply voltage is larger than the ground voltage.
When the input/output end 2′ encounters the electrostatic discharge (positive voltage), there will be electrostatic discharge conducting path, path1, and more details will be explained in the following. In the electrostatic discharge conducting path, path1, the electrostatic discharge current will pass through the forward diode 2′ to the voltage supply end VDD. Then, the electrostatic discharge current passes through the triggered clamping circuit 5′ to the ground end GND. At that moment, the voltage of the input/output end 2′ is Vth+Ipath1(RVDD+RCLAMP), wherein Vth is the forward conducting voltage of the diode 3′, Ipath1 is the electrostatic discharge current of the electrostatic discharge conducting path, path1. Furthermore, RVDD and RCLAMP are respectively the resistor of the wire connected to the voltage supply end and the resistor of the clamping circuit 5′. Thus, if the length of the wire connected to the voltage supply end is too long (i.e. RVDD is too large), the voltage of the input/output end 2′ may be large, so that the chip 6′ will be damaged; for instance, the transistor 7′ will breakdown and be damaged.

Electrostatic discharge protection device and electronic apparatus thereof


A circuit for receiving and decoding Manchester-encoded communication signals such as those used in an Ethernet network. The circuit uses a single local reference clock signal to clock a shift register that temporarily stores samples of the incoming signal. A window pointer selects a particular bit of the shift register as the current output bit; the value of the window pointer is maintained by a feedback loop which tracks any phase error in the incoming signal, that the output data remains in phase with the incoming signal. The combined functions of a Manchester-decoder and retiming circuit are thus provided in a simple circuit.

Peer-to-peer communication environments such as local area networks (LANs) have lately become the technique of choice for interconnecting different types of computer equipment, primarily because of their minimal expense and ease of use.
In a network using the well-known Ethernet signaling technique, the network devices, such as stations, repeaters, bridges, and the like, must include a circuit for receiving and decoding an incoming Ethernet signal. Ethernet signals are self-clocking, Manchester-encoded signals having a finite packet length. Such signals are self-clocking in the sense that they contain both data and clock information, thereby eliminating the need to transmit a separate clock signal. This is accomplished by insuring that a level transition, from zero to one or one to zero, occurs in the middle of every transmitted bit. The time duration of an Ethernet signal is limited by the maximum packet length of 1518 bytes.
Certain known techniques are especially adapted for detecting self-clocking signals. For example, U.S. Pat. No. 4,745,626, issued to Wells, describes a Manchester-encoded signal receiver in which transitions in an incoming signal are detected and then clocked into a shift register. The shift register is clocked by a local clock signal having a frequency which is a multiple of the fundamental data rate of the incoming signal. A logic circuit connected to the shift register determines when phase shifts in the incoming signal occur, so that the incoming data may be decoded without the need for a feedback circuit such as a phase locked loop.
Unfortunately, the lack of feedback in such a circuit means that when the incoming signal drifts more than a slight amount from the local clock, synchronization is easily lost.
Another technique is disclosed in U.S. Pat. No. 4,450,572, issued to Stewart et al., and assigned to Digital Equipment Corporation, the assignee of this application. In Stewart, et al. circuit, a flip-flop, exclusive-OR gate, and delay line separate the data and clock signals. The data signal is fed to a serial shift register clocked by the clock signal; an internal synchronizing circuit re-synchronizes the output of the shift register to an independent clock source.
While this technique works well for its intended purpose, it does have certain shortcomings. In particular, it is asynchronous, in the sense that certain components switch in phase with the clock signal embedded in the incoming signal, and certain other components switch in phase with a local reference signal having a phase and/or frequency which differs from the embedded clock signal. In other words, a first clock signal is extracted from the Manchester-encoded incoming signal, and then use the first clock signal to sample the incoming signal to recover the input data. Once the data is recovered, the input data is re-timed by sampling it again with a second clock signal, which is a locally generated signal asynchronous to the first clock signal.
The greater the number of asynchronous clock signals in a circuit, the more complicated and expensive it becomes. A particularly vexatious problem in such a circuit is to resolve metastable conditions, which may occur when a flip-flop is clocked before its input signals reach a stable state. This condition is more likely to occur in a circuit where input signals to a flip-flop may change asynchronous to the clock signal driving the flip-flop.
Thus, it would be desirable to minimize the number of asynchronous clock signals in circuits such as an Ethernet signal decoder. In fact, it is preferable for all components of such a circuit to operate in phase with a single local oscillator, which would then minimize the cost and complexity of such a device, while improving its reliability.

Synchronous decoder for self-clocking signals


The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.

A thin film transistor (hereinafter, referred to as a "TFT") having an oxide semiconductor layer of indium gallium zinc oxide (hereinafter, referred to as "IGZO") or the like as a channel layer has a characteristic in that the TFT has a fast operating speed as compared with a TFT having an amorphous silicon layer as a channel layer and that the TFT requires no crystallization process as compared with a TFT having a polycrystalline silicon layer as a channel layer. Therefore, in recent years, development of TFTs having an oxide semiconductor layer as a channel layer is being actively progressed.
However, the TFT having an oxide semiconductor layer as a channel layer has a problem in that an off-current (the current flowing between a source electrode and a drain electrode in the off state) becomes large. To reduce such an off-current, Patent Document 1 discloses a method for causing a microcrystalline layer to be not easily formed at a backchannel side of the oxide semiconductor layer, by increasing an oxygen concentration at the backchannel side in the TFT having the oxide semiconductor layer as a channel layer. In this way, by causing a microcrystalline layer to be not easily formed at the backchannel side, the backchannel side is made amorphous, and therefore, the off-current of the TFT is reduced.


The stretching of bitmap images in a computer system is accomplished by stretching each row of a source bitmap and storing the pixel information associated with the stretched row in a buffer, typically in main memory. The pixel information is transferred multiple times to the memory location associated with the destination bitmap, these memory locations generally reside in either main memory or in the frame buffer. Each time the buffer is written to the destination bitmap, an error term is adjusted by a predetermined amount. When the value of the error term meets a predefined criteria, the next row of the source bitmap is stretched and stored in the buffer and the process is repeated.

The speed at which a personal computer operates is dependent upon a number of factors. Naturally, the speed of the microprocessor has a significant influence on the speed of operation of the overall computer system. Next to processor speed, in many cases, the video graphics subsystem has the most influence on the performance of the overall computer system. This is particularly true when a graphical user interface, such as MICROSOFT WINDOWS (by Microsoft Corporation of Redmond, Wash.) is used. In order to boost performance, most modern day personal computers use either a local video bus (which has a higher data bandwidth than the main peripheral bus) and an accelerated video card which increases the speed of certain operations. An accelerated video card allows the video card to perform selected video operations at high speed, rather than using the CPU to perform the operation. This accelerates the operation of the computer system in two ways: (1) the CPU no longer needs to perform low-level operations handled by the video card and (2) the data bandwidth for certain operations is greatly reduced resulting in less bus traffic.
In order for acceleration to increase the responsiveness of the system, the operating environment, such as WINDOWS, must know the capabilities of the accelerated video subsystem. When the operating environment is loaded, it initiates the loading of a video driver, which is a program which acts as an intermediary between the operating environment and accelerated video subsystem. The driver passes parameters to the operating environment which specify its capabilities. Thereafter, when the operating environment needs to perform a video operation which could benefit from one of the accelerated capabilities, it passes the necessary data to the driver. The driver interprets the information from the operating environment, processes the information and passes data via the bus to the video subsystem. The video subsystem then performs the video operation by writing data to its frame buffer. As the market for accelerated video subsystems has matured, it has become apparent that the speed of the video subsystem is in large part dependent upon the operation of the video driver.
One video operation which can have a significant effect on the responsiveness of the computer system is a bitmap stretch. In a bit-mapped image (or "bitmap"), the color information for each pixel in the bitmap is represented in a corresponding portion of memory. In a bitmap stretch, the destination bitmap is sized to dimensions greater than the source bitmap. Because of the complications of resizing a bitmap, most display device drivers only support bitmap stretching when the size of the destination bitmap is an integer stretch of the source bitmap. This technique is shown in FIGS. 1a-c. In FIG. 1a, the original bitmap 10 consists of nine pixels 12 arranged in a 3.times.3 array. For illustration purposes, each pixel has an associated index (1-9) which indicates the color of the pixel. The resulting destination bitmap 14 after performing a 2:1 stretch of the source bitmap 10 is shown in FIG. 1b. In FIG. 1b, each pixel 12 has been replicated twice in both the vertical and horizontal directions, resulting in a 6.times.6 array. As can be seen, each pixel from the bitmap of FIG. 1a is now a 2.times.2 array in FIG. 1b.
Similarly, in FIG. 1c, a destination bitmap 16 resulting from a 3:1 stretch of the source bitmap 10 of FIG. 1a is illustrated. In FIG. 1c, each pixel 12 of bitmap 10 of FIG. 1a is replicated in FIG. 1c as a 3.times.3 array. The resulting bitmap 16 is therefore a 9.times.9 array.
With an integer-multiple stretch of a bitmap array, the video operations are very simple, since each pixel is replicated by the integer multiple in both the "x" and "y" directions. However, with non-integer multiples, stretching becomes much more complex. For example, stretching the 3.times.3 bitmap of FIG. 1a to a 7.times.8 bitmap requires that decisions are made as to the number of times to replicate each pixel. Because of the complication of providing a non-integer multiple, most display device drivers only support integer stretching.
Therefore, a need has arisen in the industry for a video driver capable of supporting high-speed non-integer stretching of bitmapped images.

Method and apparatus for stretching bitmaps to non-integer multiples


Middleware is validated using a two layered modeling strategy for the generation of test suites. A high level model of the syntax of the programming language used to program the middleware generates a series of high level abstract programs. These high level abstract programs then undergo two separate translations. First they are translated directly into actual test programs, which are expressed in the programming language of the middleware. Second, they are translated into second models of the high level abstract programs. Running the model based test generator again on the second models produces a set of suites of test cases, each test case consisting of data inputs and predicted results for one of the actual test programs. The actual test programs are run repetitively using the middleware execution engine. The results are compared with the predicted results, using a generic validation engine.

1. Field of the Invention
This invention relates to software testing. More particularly this invention relates to model based automatic generation of test programs for the validation of middleware.
2. Description of the Related Art
Middleware is software that functions as a conversion or translation layer between applications or between an application and the operating system. Middleware solutions have been developed in order to enable applications to communicate with other applications. The applications may execute on different platforms, be produced by different vendors or both. Today, there is a diverse group of products that offer packaged middleware solutions. One of the characteristics of middleware is that its software is "programmable". In other words, the user can program the middleware to behave in a number of different ways.
Traditional software testing involves study of the software system by the tester, who then writes and executes individual test scenarios that exercise the software being tested. In the case of middleware, testing typically requires validation of many functional levels, which increases the complexity of the task. Test software for a middleware system is itself an application which needs to be tested.
More recent model-based approaches to test generation have common problems that this invention builds upon. In each case, the number of unique paths, or generated test programs is an exponential function of the number of modeled states and transitions. Thus, as the scope of the modeled behavior grows, the time to exhaustively generate test cases, and more significantly, the time needed to execute the generated test cases grows exponentially. This growth places a practical limit on the complexity of the program behavior to which automated model-based test generation can be applied. The invention focuses and therefore reduces the number of tests to a practical level. In so doing, the invention raises the practical limit on the complexity of the software program to which automated model-based test generation may be applied.
Conventional testing of established types of middleware involves the use of benchmark sets of input programs. These programs are seldom run with real input data. Instead, the output of the middleware, for example a compiler, is compared with the results of other compilers for the same input code. This testing methodology is inappropriate for new products, for which there are no benchmarks, and for which there is no comparable middleware to evaluate the test.
Typical of conventional approaches for generating test programs from a model is U.S. Pat. No. 5,394,347 to Kita et al. which discloses a method of modeling a specification as an extended finite state machine, then performing a depth-first traversal of the resulting state diagram to generate a path file as a basis for a test program.
In U.S. Pat. No. 5,918,037 to Tremblay et al., it is proposed to employ a test generator that automatically produces test programs based on a finite state machine model of the software. Limiting the number of test programs is achieved by controlling loop execution, and by appropriately setting the coverage level for the model, known as "transition cover testing". This approach seeks to specify during the test program generation process that each transition within the finite state machine model be exercised once. The generator is capable of specifying different coverage levels for selected portions of the program under test, so that critical portions might be exhaustively tested, while other portions receive less comprehensive testing.
During the past decade, model-based random test program generators have become popular in processor architectural design verification and software testing. An example of such a random test generators include the IBM tool, "Genesys", which is disclosed in the document Model-Based Test Generation for Process Design Verification, Y. Lichtenstein et al., Sixth Innovative Applications of Artificial Intelligence Conference, August 1994, pp. 83–94.
Another conventional test generator, AVPGEN, is disclosed in the document AVPGEN—A Generator for Architecture Verification Test Cases, A. Chandra, et al. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 3, No. 2, 188–200 (June 1995).
None of the techniques disclosed in the above noted documents is well suited for solving the particular issues presented by middleware.

Recursive use of model based test generation for middleware validation

International Business Machines Corporation


An electrooptic device includes a first substrate and a second substrate. The first substrate includes an electrooptic element in which an electrooptic substance is interposed between a first electrode and a second electrode, the electrooptic element being disposed on a surface of the first substrate that opposes the second substrate; an electronic element for driving the electrooptic element; and a power supply wire for supplying power to at least one of the electrooptic element and the electronic element. The second substrate includes a second auxiliary wire for supplying auxiliary power to at least one of the electrooptic element and the electronic element, the second auxiliary wire being disposed on a surface of the second substrate that opposes the first substrate, the second auxiliary wire having a planar shape that corresponds with a non-opening region of the electrooptic element.

1. Technical Field
The present invention relates to the technical fields of electrooptic devices, such as organic electroluminescent (EL) devices, production methods therefor, and various electronic apparatuses including the electrooptic devices.
2. Related Art
In electrooptic devices, such as organic EL devices and silicon light-emitting devices, that include solid thin films and are driven and controlled by active elements such as TFTs, the electrodes and power supply wires of the electrooptic devices are composed of thin films. Even when these electrodes and power supply wires are composed of low-resistance metal materials, the resistance of the electrode and power supply wire causes the power voltage to decrease with the increase in size and output (brightness) of the electrooptic devices. This also affects the operation properties of the electrooptic devices. When the electrooptic devices is a display device of an active drive type in which power is supplied to a plurality of pixels arranged in a matrix over the entire image display region including the end portions, the voltage drop is particularly large at a location far from the power terminal. As a result, unevenness in brightness in the image display region readily occurs.
FIG. 6 shows the rate of decrease in brightness in the entire display during the full white display according to the structure of a related art, and FIG. 7 shows an example of unevenness in brightness. The difference in brightness between the display center and display end portions is preferably up to 3-2% in realizing a high quality display by increasing the size of a high-definition, light-emitting display device, such as a high definition television (HDTV). Even when the current of the light-emitting device of each pixel is 15 μA or lower, the power current in a display device having a diagonal size of 40 inches or more is on the ampere order. Thus, the resistance of the power supply wire for supplying power to each column of the pixels must be 11Ω or less and the power voltage drop must be 0.2 V or less. Moreover, as shown in FIG. 7, when a white square is displayed at the center of the red back ground over the entire image display region, bright red regions appear at the left and right of the white square and dark red regions appear above and below the white square because of the unevenness in brightness described above.
Consequently, in attempting to apply the device to a thin-film light-emitting device of an active drive type, such as an organic EL display device, by increasing the size, the thickness of the wiring (power supply wire) cannot be simply increased. The feasible thickness is about 200 to 300 nm from the standpoint of economically planarizing the step differences. Furthermore, in order to form a full color display, the width of the power supply wire for each pixel column must be one third of the width of the pixel or less. Accordingly, in an active light-emitting devices in the related art, the difference in brightness between high-brightness pattern and display patterns around the high-brightness pattern shown in FIG. 7 is at least 5% to 10% due to the limitations in thickness and width of the power supply wire and the resistance of the wiring materials. Thus, the display quality is significantly degraded, and increasing the size, the resolution, and/or the brightness of the device is difficult.
In view of the above, various techniques for decreasing the resistance of the power supply wire have been proposed (refer to Japanese Unexamined Patent Application Publication Nos. 11-329743, 5-307997, 2002-40961, and 2004-178839.

Electrooptic device, method for producing the same, and elecronic apparatus


Systems and methods for transitioning an aircraft between helicopter and fixed wing flight modes are provided. In one embodiment, an aircraft comprises a plurality of wings each having a spar and a flap; a flap actuator configured to move the flap with respect to the spar; and a center section rotatably coupled to each spar. The center section includes at least one spar actuator configured to rotate at least one of the wings about a rotational axis of the spar when the aircraft transitions between helicopter and fixed wing flight modes.

1. Field of the Invention
The invention relates generally to unmanned aircraft designs, and, more particularly, to aircraft designs that combine the features of helicopter and fixed wing aircraft.
2. Description of the Related Art
Some unmanned aircraft designs attempt to combine the vertical takeoff and landing (VTOL) and hover capabilities of a helicopter and the increased speed and range capabilities of fixed wing airplanes. Stop rotor "nose sitter" configurations, so named because the aircraft takes off and lands from a nose-down orientation, may offer good hover efficiency and aerodynamic design but can require complex mechanical systems. These designs can also suffer a significant loss in altitude during transition from helicopter to airplane mode, and involve uneven weight distributions, rendering the aircraft "top heavy" and unwieldy during takeoff and landing. Further, the counter-rotating fuselage and tail of some "nose sitter" designs are less practical than aircraft designs with a conventional fuselage orientation and tail rotor. "Tilt rotor" configurations with tiltable rotating propellers also involve mechanically complex systems and decreased hover efficiency due to higher disk loading. "Tail-sitter" designs, so named because the aircraft takes off and lands from a tail-down orientation, are associated with poor hover efficiency due to high disk loading and an awkward 90 degree attitude change between hover and forward flight modes.
The compound helicopter has a rotor system driven by an engine for takeoff, hovering, and landing and an additional propulsion system and supplemental wing independent of the rotor system. At higher speeds, the rotor system does not drive the aircraft and is substantially unloaded by the lift of the wing. Compound designs also have disadvantages: they are heavy due to additional systems and can suffer a significant download penalty when hovering due to the presence of the wing in the rotor downwash. The canard rotor wing configuration contemplates a rotor that stops in flight and acts as a fixed wing, but it too suffers drawbacks. The shape of its airfoil compromises between forward and reverse airflow directions, leading to reduced performance in both flight modes. Similarly, tilt duct designs, whose propellers are shrouded in ducts and rotate between flight modes, suffer from poor hover efficiency and high drag in forward flight mode. Thus, combining a helicopter's vertical takeoff and landing capability and efficient hover with a fixed wing aircraft's high speed and long range into one aircraft design while reducing or eliminating performance tradeoffs remains a significant aspect in aeronautical engineering.

The United States of America as represented by the Secretary of the Navy


The object of the invention is a ratchet wheel pipette having a body and in it a cylinder (3) and a piston (12) and a filling and dispensing arrangement to draw liquid into the cylinder and to dispense it in smaller portions with the aid of the piston. The pipette has a push rod (11) as an extension of the piston, a transmission wheel (6) in mesh with the push rod, a ratchet wheel (5) having a larger diameter than the transmission wheel and rotating with it and having a peripheral engaging surface, such as gears, and, journaled on the same shaft as the ratchet wheel, a dispensing lever (9) which is movable between an upper position and a lower position and with an attached pawl (10) engaging the engaging surface of the ratchet wheel, so that when the dispensing lever moves downwards, beginning at a certain point of the movement, the pawl engages the engaging surface of the ratchet wheel and forces the ratchet wheel and thus also the transmission wheel to rotate, and so that when the dispensing lever moves upwards the pawl does not rotate the ratchet wheel. The pipette can be used in laboratories, for instance to dispense samples or reagents.

Such pipettes are known as comprise a piston movable in a cylinder, a longitudinal pinion rack on the piston shaft, and a pawl engaging the pinion rack due to the force of a spring. The pawl is connected to an operating member with which the pawl is forced to move the upwards pulled pinion rack and thus also the piston downwards in steps with a desired length. The length of the step can also be adjusted by a cover plate movable on or on the side of the pinion rack or by a pawl lifter, which determines the position where the downwards moving pawl engages the pinion rack. Such pipettes are presented for instance in the publications DE-A-2926691, FI-A-844096 and FI-A-931650.
On the market there has also been a stepping pipette (Socorex Stepper 411) having a ratchet wheel and a co-operating pawl journaled on a separate shaft, and a gearwheel rotating with the ratchet wheel and moving the piston of the pipette.


A house for parking bicycles so that bicycles can be placed separately in a circular storage area. The bicycles are positioned radially with the rear ends of the bicycles being directed toward the center axis of the house. The storage area of the house is provided with fixed walls and a door thus providing a closed room with at least one door. The floor of the area is sloped toward the center axis and is shaped as a double floor of which the inner floor is rotatable. The storage area is divided into stalls for placing the bicycle.

The invention concerns a house for parking bicycles of the type which is indicated in the introduction to claim 1.
Throughout the years the bicycle has been a popular means of transport, having been employed, e.g., as a means of conveyance to the starting point for further transport by tram or train, or people have cycled all the way to their destination.
In this connection there has been a problem with parking bicycles at such locations, the theft of bicycles being a frequent occurrence, even though they have been locked according to the book.
A need therefore exists for the development of a system for more secure parking facilities for bicycles.
It has been possible to solve this problem by fencing in areas which are guarded and where a fee is paid for installing the bicycle. Such solutions are expensive, however, due to the security and also occupy a relatively large amount of space.
Bicycle parking houses have also been developed previously, and examples thereof are described in WO-A-92/22718, WO-A-89/08578 and DE-C-44 03 859.
In the first of these publications there is described a bicycle parking arrangement which consists of a frame in which the bicycles are parked and where the frame can be rotated about a central axis. In order to park or retrieve the bicycle the frame is rotated to a vacant position or until the bicycle in question reaches a door. On the frame there are mounted holders for the bicycle, and the bicycle is locked in these holders. When removing the bicycle the holder device is pulled out and the bicycle can be unlocked from the holder and removed. This bicycle parking arrangement has a relatively complicated frame and holder design and it will be possible for unauthorized persons to enter the parking area, e.g. by paying for parking a bicycle, whereupon acts of vandalism can be carried out or parts can be removed from other bicycles.
In WO-A-89/08578 a bicycle parking arrangement is described where the bicycles are placed in separate, triangular stalls, where the bicycle is firmly wedged in the stall. Each stall is designed with its own door and a key system in order to ensure that no one else can gain access to the stall. Such stalls can be arranged in twos in rectangular units or also assembled to form a circular unit. The arrangement requires a relatively large amount of space, since it must be possible to reach it from all sides, each space having its own opening.
Furthermore, in DE-C-44 03 859 there is described a bicycle parking arrangement in which, in a similar fashion to the aforementioned system, the bicycles are placed in separate stalls in the form of triangles, which can be placed in a circle. The special feature of this arrangement is that entry ramps have also been provided for parking on two storeys for better utilization of space. This arrangement, however, has the same basic construction as the aforementioned unit, each stall having its own door opening.


A device for automatic image segmentation according to the invention comprises a data processor associated with a network of automata organized in three levels; the inputs of each of the automata are weighted by adjustable coefficients; the number of automata of the first level is equal to the number of characteristic values computed from observation windows taken firstly in a set of examples of image zones having different textures. Learning by the network permits adjustment of the weighting coefficients of the automata of the network until all the examples of the same texture lead to the same configuration.

1. Field of the Invention
The invention relates to the field of automatic computer analysis of images and in particular to a method, and to the corresponding device for automatic segmentation of images through analysis of their texture.
Texture is an important characteristic for the analysis, segmentation and classification of images, in particular when the latter are of low contrast. Perception of textures is closely related to the visual system: this surface property perceived by the observer is considered to be homogeneous and therefore translation invariant for a zone of the same type. Observation of a texture leaves the same visual impression whatever the portion of the texture observed.
The problem to be resolved when analysing the textures in an image is to mark out the modifications of texture on the basis of an observation window moved over image.
2. Discussion of the Background
Numerous methods have been proposed for analysing textures. These methods can be grouped into four distinct families depending on the parameters analysed:
methods proceeding by analysis of spatial characteristics determine the period of repetition of an elementary motif; PA1 methods proceeding by analysis of the frequency characteristics use Fourier transform computations to search for characteristic frequencies; PA1 methods operating by analysis following coevent matrices using a more complicated formalism, performing, around each point and for all the possible directions, statistical analyses on the grey level repetitions; PA1 methods operating by structuralist analysis, implementing artificial intelligence. PA1 A. GAGALOWICZ "Towards a model of textures" PhD Thesis in mathematical sciences, University of Paris IV-1983. PA1 S. RABOISSON "Numerical image processing by characterisation of textures. Application to the segmentation of echograph images" MSc Thesis in information processing - University of Rennes I-1985. PA1 in an initial phase, a file of several examples of each of several textures is created from sets of characteristic values, each set being representative of a sample of a given texture, PA1 then, in a learning phase, these sets of values are used to adjust by successive approximations, weighting coefficients of a network of automata, until the outputs of this network are as close as possible to a configuration characteristic of a given texture, for all the examples of this texture, each of the textures being associated with a characteristic configuration, PA1 then, in a classification phase, the images are processed by computing sets of characteristic values of zones delimited by an observation window moved in the image, each set of characteristic values of a zone, which set is applied to the input of the network of automata, leading to an output configuration of this network, from which configuration are determined one texture from those learned in the learning phase, and an associated confidence value which is a function of a disparity between the output configuration obtained and that associated with this determined texture.
These methods are described in detail in the following documents:
The existing methods therefore necessitate a modelling of the concept of texture by statistical or structuralist models and these methods fail when the textures present in the image to be analysed are not describable by the model and therefore cannot be marked out.

Method and device for automatic image segmentation by textural analysis


A feeding reservoir 11 for intermittently or continuously feeding granular raw material into a pulling apparatus 1, a chamber 13 connected to the feeding reservoir 11 through a gate valve 12, a granular raw material supply section 15 by which the granular raw material is supplied to the chamber 13 through a gate valve 14 and a pressure adjustment means 20 which adjusts the inner pressure of the chamber 13 is provided, and the granular raw material is fed to the feeding reservoir 11 while maintaining the inner pressure of the feeding reservoir 11 as the same as the inner pressure of the single crystal pulling apparatus 1. This feeding method and structure makes it possible to feed an additional amount of granular raw material even during the continuous charging process and or the recharging process without interrupting the process and also to pull a heavy single crystal rod with a large diameter without increasing the capacity of the feeding reservoir.

1. Field of the Invention
This invention relates in general to a method and an apparatus for growing a single crystal according to the Czochralski method, and more particularly to a method and an apparatus for feeding the granular raw material.
2. The prior Art
When manufacturing a silicon single crystal according to the Czochralski method, the granular raw material, i.e. silicon poylcrystals, which is the raw material for the single crystal is put into a crucible and heated above the melting point of silicon to obtain a melt. A seed crystal is then dipped in the melt, and then pulled upwardly to grow a single crystal rod. The amount of the melt in the crucible decreases as the pulling process progresses, so that it is required to make up for the decrease of the melt by feeding the granular raw material to the crucible. An apparatus which have a granular raw material feeding pipe is used for feeding the granular raw material.
One of these methods for feeding the granular raw material using such an apparatus is so-called continuous charging method in which the granular raw material is continuously feeded onto the surface of the melt in the crucible while the single crystal is grown. FIG. 4 shows an example of the configuration of the single crystal pulling apparatus and the granular raw material feeder used for growing a single crystal according to the continuous charging method. In FIG. 4, the single crystal pulling apparatus 21 has a crucible which is not shown, and the granular raw material is fed into the crucible from the granular raw material feeder 30, whose configuration is enclosed by dotted lines.
The granular raw material feeder 30 comprises a feeding reservoir 32 which is connected to the single crystal pulling apparatus 21 through a gate valve 31, a gas feeding section 35 which is interconnected to the feeding reservoir 32 through a valve 34 and supplies argon and such, and a vacuum pump 36 which is interconnected to the feeding reservoir 32 through a valve 33. The feeding reservoir 32 has a granular raw material supplying section 38 by which the granular raw material is supplied through a valve (or an opening which can be sealed) 37. The pressure in the feeding reservoir 32 is always kept at the same pressure as the inner pressure of the single crystal pulling apparatus 21 (typically 10-1,000 hPa) and it is possible to feed the granular raw material into the single crystal pulling apparatus 21 through the gate valve 31 while the single crystal is being pulled. The valves 33, 34 and 37, or all valves except the gate valve 31, are closed during feeding.
For supplying the granular raw material to the feeding reservoir 32 when the inner pressure of the single crystal pulling apparatus 21 is reduced, the gate valve 31 is closed firstly, then the valve 37 is then opened to restore the inner pressure of the feeding reservoir 32 back to the atmospheric pressure. Then the feeding reservoir 32 is removed, and the granular raw material is directly supplied to the feeding reservoir 32 through the granular raw material supplying section (loading port) 38. An alternative method involves setting up a drum can containing the raw material or an intermediate feeding reservoir on top of the feeding reservoir 32, connecting it to the granular raw material supplying section 38 and then pouring the granular raw material through the valve 37.
After supplying the granular raw material, the feeding reservoir 32 is replaced if it has been removed, the valves 34 and 37 are closed, then the valve 33 is opened with the vacuum pump 36 running to establish a vacuum in the feeding reservoir 32, and then the valve 33 is closed. Then the valve 34 is opened to supply argon from the gas feeding section 35 into the feeding reservoir 32 so that the inside of the feeding reservoir 32 is filled with argon gas whose pressure is the same as the pressure in the single crystal pulling apparatus 21. Then the valve 34 and the gate valve 31 are closed one by one. By the processes shown above, it is possible to feed the granular raw material into the single crystal pulling apparatus 21.
The continuous charging method as described above makes it possible to grow a longer single crystal rod limited by the capacity of the feeding reservoir, and therefore allows a substantial improvement in the manufacturing yield and a drastic reduction of the manufacturing cost.
In addition to the continuous charging method described above, the multiple-pulling method, a version of the conventional batch process, is also known as a method of reducing the manufacturing cost (refer to Semiconductor Silicon Crystal Technology, Fumino Shimura, pp178-179, 1989). In this method, after pulling a single crystal with a dopant concentration in the range which satisfies prescribed resistivity standards, additional charging (hereafter referred to as recharging) of the granular raw material in the amount equal to the weight of the grown single crystal rod is carried out by the batch process, and another rod of single crystal is pulled again. By this way, a plurality of single crystal rods can be manufactured from the melt once loaded. Therefore this method makes it possible to improve the manufacturing yield and reduce cost for the crucible. In this multiple-pulling method, the granular raw material is also fed from the feeding reservoir while recharging is being carried out.
In the conventional method for feeding granular raw material as described above, continuous charging and recharging of the granular raw material is impossible while feeding the granular raw material into the feeding reservoir during the pulling process, in which the gate valve between the feeding reservoir and the single crystal pulling apparatus is closed, as described before, and the inner pressure of the feeding reservoir is restored to the atmospheric pressure before feeding the granular raw material. Therefore it results in poor efficiency.

Method for feeding a granular raw material and feeding apparatus


A vehicle lighting unit is provided with: a projection lens arranged on a lens center axis extending in a longitudinal direction of a vehicle; a light source arranged on a rear side of a rear focal point of the projection lens; a reflector for reflecting forward a light from the light source toward the lens center axis; and a shade. An upper end edge of the shade passes in a vicinity of the rear focal point of the projection lens to shield a part of a reflected light from the reflector. An optical axis of the reflector is shifted from the lens center axis that is set to pass through an upper end edge of the shade so that the optical axis of the reflector is apart from the upper end edge.

1. Field of the Invention
The present invention relates to a vehicle lighting unit and, more particularly, a projector-type vehicle lighting unit used as a passing-beam (lower beam) headlight.
2. Background Art
Nowadays a projector-type headlight is often employed as the vehicle lighting unit. This projector-type headlight is equipped with a projection lens arranged on a lens center axis extending in the longitudinal direction of the vehicle, a light source arranged on the rear side of the rear focal point of this projection lens, and a reflector for reflecting forward a light from this light source to go toward the lens center axis.
When this projector-type headlight is used as the passing-beam headlight, a shade for shielding a part of the reflected light from the reflector to remove an upward illumination light is provided between the projection lens and the reflector. Accordingly, a passing-beam light distribution pattern having a light-shade boundary line is formed (see JP-A-2004-095481, for example).
A basic light distribution pattern for the passing-beam light distribution pattern is a light distribution pattern having a light-shade boundary line that is formed by projecting a shape of an upper end edge of the shade. In the light-shade boundary line, an opposite lane side is constructed by a horizontal cut-off line and an own lane side is constructed by an oblique cut-off line that rises leftward from the horizontal cut-off line at an angle of 15°. Also, in this basic light distribution pattern, a hot zone (high luminous intensity area) is formed under and near the right end portion of the oblique cut-off line of the light-shade boundary line.
However, in the above projector-type headlight in the background art, normally a focal position of the projection lens is set to the upper end edge of the shade during the passing-beam light distribution. Therefore, an almost half of the upward illumination light is removed by the shade, and particularly a part of the hot zone is cut by the oblique cut-off line of the light-shade boundary line. As a result, such a problem existed that a utility factor of the light is low. Also, there are some shades to which a mirror process has not been applied. In this case, a loss due to a reflection not a little occurs.

This patent is subject to a terminal disclaimer.


Disclosed is a PLL circuit including a phase frequency detector (PFD) for comparing phase and frequency between an input signal and an output signal, a charge pump circuit for charging a capacitor when an up-signal from the PFD is activated, discharging the capacitor when a down-signal is activated, and for outputting the terminal voltage of the capacitor as a control voltage, and a VCO for outputting an output signal of a frequency in accordance with the control voltage. An output of the VCO is fed back as an output signal to the PFD as input. The PFD includes a delay adjustment circuit for exercising control for resetting the up-signal and the down-signal with a preset delay as from a time point both up-signal and the down-signal have been activated. There is also provided a comparator amplifier circuit for comparing a reference voltage, corresponding to a control voltage when both up-signal and down-signal are activated, to supply first and second control signals to the delay adjustment circuit. The pulse widths of up and down-signals are adjusted depending on current offset characteristics of the charge pump circuit.

Recently, with the increase of operating speed (operating clock frequency) of CMOS LSI products, larger numbers of LSI products, each having a PLL (phase-locked loop) circuit, are manufactured and sold. The degree of accuracy demanded of the PLL circuit nowadays has become increasingly higher.
In the conventional charge-pump type PLL circuit, phase offset persists, so that variations in for example, temperature, power supply voltage, or fabrication process, significantly affect the circuit characteristic of the PLL circuit. Hence, the improvement of this situation in the charge-pump type PLL circuit is required.
FIG. 10 is a diagram illustrating an example of the configuration of a conventional charge-pump type PLL circuit (see Non-Patent Document 1). Referring to FIG. 10, the conventional charge-pump type PLL circuit includes a phase frequency detector (PFD) 10′, a charge pump circuit 20, and a voltage-controlled oscillator (VCO) 30. An output Vout of the VCO 30 is fed back as an input to the phase frequency detector 10′. The phase frequency detector (PFD) 10′ compares the phase of an output signal Vout with that of an input signal Vin, and outputs an UP signal UP, its complementary signal UPb, a DOWN signal DN and its complementary signal DNb. Of these, the signals UPb and DN are supplied to the charge pump circuit 20. The phase frequency detector (PFD) 10′ includes a D-type flip-flop with reset 11, a D-type flip-flop with reset 12, and AND circuit 13. The D-type flip-flop 11 has a data input terminal D connected to a power supply VDD, has a clock input terminal CK supplied with Vin, and samples a signal (HIGH LEVEL) at the data input terminal D responsive to the rising edge of Vin to output UP at a high level and UPb at a low level from a non-inverting output terminal Q and from an inverting output terminal QB, respectively. The D-type flip-flop 12 has a data input terminal D connected to the power supply VDD, has a clock input terminal CK supplied with Vout, and samples a signal at the data input terminal D responsive to the rising edge of Vout to output DN at a high level and DNb at a low level from the non-inverting output terminal Q and at the inverting output terminal QB, respectively. The AND circuit 13 receives UP and DN as inputs. An output signal (reset) of the AND circuit 13 is supplied to reset terminals R of the D-type flip-flops 11 and 12. When UP and DN are high, the output signal (reset) from the AND circuit 13 becomes high and the D-type flip-flops 11 and 12, which receive the high level reset signal from the AND circuit 13 at respective reset terminals R, are reset, as a result of which outputs UP and DN are reset to a low level, while respective complementary signals UPb and DNb are reset to a high level.
The charge pump circuit 20 includes pMOS transistors Pa1 and Pa2, nMOS transistors Na1 and Na2, and a capacitor 21. The pMOS transistor Pa1 has a source and a gate connected to the power supply VDD and to Vb2 (bias voltage), respectively. The pMOS transistor Pa2 has a source connected to the drain of the pMOS transistor Pa1 and has a gate supplied with Upb. The nMOS transistor Na2 has a drain connected to the drain of the pMOS transistor Pa2 and has a gate supplied with DN. The nMOS transistor Na1 has a drain connected to the source of the nMOS transistor Na2, has a gate supplied with Vb1 and has a source connected to the ground (GND). With this charge pump circuit 20, when UP is high and UPb is low, the pMOS transistor Pa2 is turned on to charge the capacitor 21 by the source current Isource supplied from the pMOS transistor Pa1 constituting a current source. Conversely, when DN is high, the nMOS transistor Na2 is turned on to discharge the capacitor 21 by the sink current Isink supplied from the nMOS transistor Na1 constituting a current source. The pMOS transistor Pa1 and the nMOS transistor Na1 receive at gates thereof bias voltages Vb2 and Vb1, respectively, such that the source current Isource and the sink current Isink will be as approximately equal to each other as possible. The respective timings at which the source current Isource and the sink current Isink flow are adjusted by the on time of the transistors Pa2 and Na2, which are on/off controlled by the signals UPb and DN, respectively. The terminal voltage of the capacitor 21 is supplied as the control voltage Vcont to the VCO 30.
The Patent Document 1 shows, a charge pump circuit comprising a current correcting circuit as shown in FIG. 12 is disclosed. This charge pump circuit operates as follows. When charging/discharging the capacitor in an LPF (loop filter), using UP and DN pulses output from a phase comparator, the difference between the charging current and the discharge current, resulting from the offset between output impedances of a pMOS transistor P12 and an nMOS transistor N12, is extracted and corrected so as to make the charging current and the discharge current equal to each other by a sense amplifier (AMP) 5. An output of the sense amplifier (AMP) 5 is fed back to pMOS transistors P12 and P14 to render the control voltage Vcont constant or to make Vcont to be kept in a preset voltage width. P13 and P11 are pMOS transistors, N11 and N13-N16 are nMOS transistors and I11 is a current source.
The Patent Document 2 discloses a PLL circuit including a pulse adjustment unit between a phase comparator and a charge pump and a pulse width adjustment unit for controlling the pulse width of UP and DOWN pulse signals output from the phase comparator to the charge pump to enable the lock in time to be reduced.
The Patent Document 3 discloses a PLL circuit including a feedback loop, comprised of a phase comparator for comparing the phase of a reference clock with that of a feedback clock, a charge pump, a loop filter and an oscillator, a pulse generator supplied with the reference clock and the feedback clock, and a pulse width decision circuit, and configured for adjusting the amount of phase correction consistent with the ratio of the delay in the feedback loop and the interval of the phase comparision.
The Patent Document 4 discloses a PLL circuit in which a reset signal of a phase comparator is delayed for decreasing a phase insensitive zone in a phase comparator.
The Patent Document 5 discloses the configuration of a PLL circuit in which two current source circuits are provided in a circuit for generating the current or the voltage consistent with the phase difference detected by a phase comparator, the operating current in the circuit is increased to cause a high gain operation of the circuit in effecting frequency pull-in, and in which the operating current in the circuit is decreased to cause high gain operation of the circuit in effecting phase matching.
The Patent Document 6 discloses, as the configuration for preventing a PLL circuit from being locked with a phase shift being remained, the configuration of a charge pump including a PNP transistor for current setting, an NPN transistor for current adjustment, and a feedback amplifier, in which no offset current flows through a filter even in case the output terminal voltage is varied, such as to maintain the balance of the charging current and the discharge current for a filter.
The Patent Document 7 is a diagram illustrating the configuration in which there are provided a steady-state phase error detection unit for detecting the phase difference between a reference clock and a VCO output clock signal, means for outputting a control signal for detecting the steady-state phase error only when the PLL circuit is in a pull-in state to control a steady-state phase error detection unit, and a load circuit means for adding a load to a reference clock line and to a feedback line from the VCO responsive to the steady-state phase error.
[Non-Patent Document 1]
Bahzad Razavi, translated by Tadahiro Kuroda, 'Designing of Analog CMOS Integrated Circuits, Application', published by MARUZEN, Mar. 30, 2003, pages 667-691
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2003-87115A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2000-349626A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2002-141798A
[Patent Document 4]
Japanese Patent Kokai Publication No. JP-P2004-64742A
[Patent Document 5]
Japanese Patent Kokai Publication No. JP-A-11-205133
[Patent Document 6]
Japanese Patent Kokai Publication No. JP-A-11-298261
[Patent Document 7]
Japanese Patent No. 3425909


A dirt conveying duct arrangement is formed between a nozzle and motor-fan of a vacuum cleaner and includes front and rear duct sections. The front duct section is open at the bottom thereof and covered by a removable bottom plate. The rear duct section is open at the top thereof and is covered by a removable top duct cover. The two-section dirt conveying duct arrangement allows clogs to be removed along the entire length thereof. The corner formed between the rear duct section and the motor-fan inlet may be molded with a radius to improve airflow into the motor-fan and limit losses in suction pressure.

1. Technical Field
The invention relates to vacuum cleaners. Particularly, the invention relates to a dirt conveying duct arrangement for vacuum cleaners. More particularly, the invention relates to a dirt conveying duct having a front duct section open at the bottom thereof and covered by a removable bottom plate, and a rear duct section open at the top thereof and covered by a removable top duct cover.
2. Background Information
Dirt clogging of vacuum cleaners has long been a problem in the floor care art. Dirt-laden air is loosened from the floor by a cylindrical agitator and is drawn into a dirt conveying duct by a suction force produced by a motor-fan. The dirt-laden air travels through the dirt conveying duct into a motor-fan inlet of the motor-fan and is blown into a filter bag which filters the small dirt particles from the airflow. The exhaust air from the filter bag is emitted into the atmosphere. Although a clog may occur anywhere between the suction nozzle mouth and to and within the bag itself, typically these clogs occur in the dirt conveying duct between the agitator chamber and the motor-fan inlet.
Conventional vacuum cleaners include dirt conveying ducts formed with an open bottom. The open bottom is covered by the removable bottom plate which also covers the agitator chamber and belt compartment. One problem with the dirt conveying ducts of conventional vacuum cleaners is that the duct extends transversely along the foot of the vacuum cleaner while the motor-fan and agitator chamber extend longitudinally across the foot of the vacuum cleaner. Thus, the dirt-laden air drawn into the nozzle and dirt conveying duct must turn at a 90 degree angle into the motor-fan inlet where it is then blown into the filter bag. It is well known in the art of airflow that a 90 degree corner causes losses in the suction pressure and reduces the airflow velocity, thus reducing the efficiency of the vacuum cleaner.
By forming the rear of the duct with an open top, the corner between the dirt conveying duct and the motor-fan inlet may be radiused or curved to improve airflow between the duct and the motor-fan, thus increasing the suction pressure, airflow velocity and overall efficiency of the vacuum cleaner. A front duct section is open at the bottom thereof allowing for easy removal of clogs in the front of the dirt conveying duct arrangement. By forming the front of the duct with an open bottom, clogs which may occur in the front duct section may be easily accessed by removal of the bottom plate preventing time consuming disassembly of the hood and top duct cover. Further, the open front duct section provides visibility to the rear duct section allowing the user to check the rear duct section for clogs before disassembling the hood and top duct cover to gain access to the rear duct section.
Several vacuum cleaners mold the base in such a manner that corner of the duct adjacent the motor fan inlet may be radiused. For example, U.S. Pat. No. 5,383,252 discloses a suction channel molded in the nozzle and formed by integral bottom and side walls. The suction channel has an open top end which allows the motor-fan inlet to be formed with a radiused edge. A top panel is permanently attached to the upper surface of the side walls by ultrasonic welding or other equivalent process. However, after the top panel has been ultrasonically welded over the top of the duct, the user cannot easily access clogs which may occur at the rear of the dirt conveying duct.
U.S. Pat. No. 4,384,385 discloses a duct having an open top portion along the entire length of the duct and covered by a duct cap which is removably secured over the open top. A circular opening is formed in the side walls of the duct opposite the motor-fan inlet and provides access to the duct for removal of the dirt or debris retained therein. A removable stopper cap covers the dirt removal opening of the duct during operation of the vacuum cleaner.
Several other patents disclose dirt conveying ducts which allow provide for easy removal clogs. For example, U.S. Pat. No. 4,219,900 discloses a pivoting nozzle duct which is pivotally connected to the motor-fan inlet. The duct is a generally L-shaped tubular member which provides fluid communication between the agitator chamber and the motor-fan. The duct pivots out of the housing providing access thereto for de-clogging and cleaning thereof.
U.K. Patent Application GB 2043432-A discloses an air duct formed with a neck having an open front end which communicates with the agitator chamber, an enlarged rear chamber which provides communication between the neck and the motor-fan inlet and a bottom well. The bottom well is formed below the enlarged rear chamber and allows heavier objects which are picked up by the vacuum cleaner to fall therein, preventing these heavier objects from being sucked into the motor-fan inlet possibly damaging the fan blade. A hole is formed in the bottom wall of the cleaner foot for removing the heavy objects contained within the well.
Although these devices are adequate for the purposes for which they are intended, they do not disclose a two section dirt conveying duct which allows the corner between the rear duct section and the motor fan inlet to be radiused and which provides an open bottom for easy removal of clogs therefrom while providing visibility to the rear duct section allowing for the inspection of clogs therein.
Therefore, the need exists for a dirt conveying duct arrangement which has a front duct section open at the bottom thereof which allows for removal of clogs therein and which provides visibility to the rear duct section, and in which the rear duct section is open at the top thereof which allows a radiused corner to be formed between the duct and the motor-fan.


The use of callback functions when executing intermediate instructions in a virtual machine is described. The virtual machine receives and evaluates intermediate instructions. The virtual machine evaluates the instructions based on a function table referencing definitions of the functions. A callback is loaded into the virtual machine platform, and a callback loader modifies the function table to cause a function in the table to point to the callback instead of the standard definition. Thus, when the intermediate code is evaluated, it is evaluated based on the modified functionality of the callback rather than the standard definition.

Many programming languages allow development of programs or applications that will be implemented in a virtual machine. The virtual machine is designed to allow "platform-independent" development. The basic principle of a virtual machine environment is that the executable code exists as "intermediate state," or intermediate form, code, or code in a state that still will be evaluated or interpreted by a virtual machine layer to essentially translate the program code into instructions executable on a hardware and operating system environment of the computing device on which the virtual machine executes. JAVA (of SUN MICROSYSTEMS of Sunnyvale, Calif.) is a well-known example. PERL (of the PERL FOUNDATION) is an example of a programming language that uses an intermediate state of code. Note that all trademarks used herein are used solely for purposes of identification of a source of a product. All trademarks are the property of their respective owners.
Programming languages that do not use a virtual machine layer or intermediate state code are implemented with a compiler that converts human-readable code written in the programming language into machine-executable code made up of instructions within an instruction set supported by a particular hardware and operating system environment, also referred to as a platform. Accordingly, such programming languages require, for each platform on which a program written in the program language is to be executed, separate compilers and separate compiling of human-readable code.
Virtual machines allow development of what is frequently referred to as "portable" code, or a "platform-independent" implementation. Platform-independent implementations allow human-readable code to be converted into a single format for execution on multiple platforms with a single compiler. The single compiler converts the human-readable code into an intermediate form, rather than into machine-executable instructions. The intermediate form is made up of a platform-independent instruction set, which instruction set is supported by the virtual machine. The virtual machine is effectively a virtual platform or architecture supporting the instruction set that makes up the intermediate form.
The virtual machine in turn is implemented on various platforms, where each implementation of the virtual machine is capable of executing the intermediate code. In this way, the intermediate code is platform independent, and execution of the intermediate code on a computing system is limited only by the existence of a virtual machine environment for a given platform. Thus, when a virtual machine is implemented for a given platform, that platform becomes automatically capable of executing all programs compiled into the intermediate form, without having to re-compile the human-readable, or source, code.
An example of a programming language that uses a virtual machine layer is JAVA. FIG. 1 illustrates an exemplary implementation of known virtual machines. Human-readable code, or source code 102 is processed by compiler 104, which converts source code 102 into an intermediate form, as shown by byte code 106. The compiling of source code 102 into byte code 106 is understood to take place at "design time," referring to some time before execution of the program.
At runtime, or a time or times when byte code 106 is executed by virtual machine 110, the individual instructions making up byte code 106 are evaluated within virtual machine 110 by reference to function table 120. Function table 120 stores, for each function, a reference to machine-executable function definition, such as 116. Thus, intermediate instruction 112 is evaluated as reference 114 to entry 122 in function table 120. Entry 122 in turn is evaluated as reference 124 to function definition 116.
While a virtual machine layer in the implementation of a programming language creates a great deal of flexibility, it does not provide all the flexibility that developers might desire. When a platform introduces new capabilities, a developer must wait until the virtual machine implementation for the platform is updated to use those capabilities if he wishes to gain their benefit. For example, if a given platform adds new instructions to support 64-bit arithmetic, but the virtual machine implementation of that platform remains limited to instructions for 32-bit arithmetic, a developer cannot use the new 64-bit instructions on that implementation. Also, there exists a great deal of "legacy" code for legacy programs that may have been developed in the past. While the executable or intermediate form of the code for the legacy programs may exist, sometimes the source code is not available. Thus, for legacy programs, it may not be possible in traditional systems to change the program in the virtual machine.


Systems and methods are disclosed for detecting node outages in a mesh network. A tracking node in the mesh network detects a set of signals originating from a tracked node in the mesh network. The set of signals includes beacons and communication messages transmitted by the tracked node. The tracking node determines that a threshold number of the alive beacon intervals have passed since receiving a most recent signal from the tracked node. The tracking node then outputs a ping to the tracked node requesting a response to the ping. When the response to the ping is not received from the tracked node, the tracking node transmits an outage alarm message to a next topologically higher layer of the mesh network, the outage alarm message comprising an identification of the tracked node.

Networked systems, such as networks of smart power, gas, and water meters and other smart devices (i.e., devices capable of connecting to and communicating with other devices or networks), are capable of interconnecting with each other for interdevice communication. Further, one or more of the smart devices within the networked systems may be capable of interconnecting with the internet or other networks. For example, a networked system provides the smart devices with a mechanism to communicatively couple with one another and exchange data. The networked system may include one or more nodes that connect to a network (e.g., the internet or an intranet) either directly or indirectly through additional layers of parent and root nodes or collectors. The networked system may also include nodes that link with the parent nodes or other child nodes to exchange data across the networked system.
Certain issues arise with node reliability and node outage detection and reporting for nodes within the networked system. For example, the nodes may rely on a supercapacitor to provide sufficient energy for the node to transmit an outage indication after the node stops receiving power from a primary power source of the node. Over time, liquid (e.g., an electrolyte mixture) stored within the supercapacitor may leak, and the leaking liquid may short electrical components and result in a premature breakdown of the node. Additionally, outage indications transmitted by the node powered by the supercapacitor may not always be detected by other nodes in the networked system due to a lossy nature of communication across the networked system. Accordingly, the outage indication may never be received by other nodes in the networked system and reported to a head-end system. Thus, outage events of nodes in the networked system may not be adequately or consistently detected and reported to the head-end system for further remediating action.

Managing outage detections and reporting


A magnetic field detector includes: a magnet; a detecting magnetic resistance element having a layer structure containing a ferromagnetic layer, the resistance being changed when a direction of magnetization of the ferromagnetic layer is changed; and a reference magnetic resistance element having substantially the same layer structure as that of the detecting magnetic resistance element. A magnetic field, the magnetic intensity of which is higher than the saturation magnetic field, is impressed by the magnet in a direction which is sensed by the ferromagnetic layer of the reference magnetic resistance element.

1. Field of the Invention
The present invention relates to a magnetic field detector in which a magnetic resistance element is used and a method of manufacturing the magnetic field detector.
2. Description of the Related Art
Hall element is conventionally used for the magnetic field detector. It is possible to enhance the accuracy of the magnetic field detector by increasing a ratio of a detection signal to a noise. Therefore, in order to detect the magnetic field with high accuracy, it is desirable to obtain a higher intensity of signal, that is, it is desirable to increase a resistance change ratio that is changed by the magnetic field. From the above viewpoints, the magnetic resistance element, in which Giant Magneto-resistance (GMR) or Tunnel Magneto-resistance (TMR) is used, has been developed.
This magnetic resistance element detects a change in the outside magnetic field as a change in the resistance. However, the resistance of the magnetic resistance element is also changed by the temperature. Therefore, in an environment in which the outside temperature is greatly changed, it is difficult to use the magnetic resistance element as a magnetic sensor. JP-A-2001-345498 discloses a magnetic detector to solve the above problems. The magnetic detector disclosed in JP-A-2001-345498 is composed in such a manner that a tunnel magnetic resistance element, which is magnetically shielded, and a tunnel magnetic resistance element, which is not magnetically shielded, are connected to each other by the bridge connection so that an influence made by the change in the resistance when the temperature is changed can be reduced. The magnetic resistance element, which is not magnetically shielded, is used as a magnetic resistance element for detection, the resistance of which is changed by the outside magnetic field. The tunnel magnetic resistance element, which is magnetically shielded, is used as a magnetic resistance element for reference, the resistance of which is not changed by the outside magnetic field. In this case, the performance of the magnetic resistance element, which is magnetically shielded, and the performance of the magnetic resistance element, which is not magnetically shielded, are the same.

Magnetic field detector and manufacturing method thereof


An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND, the parameter ND satisfying R×R−1−N×ND=1 for an integer N and a radix R that is coprime to and greater than N, with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.

1. Field of the Invention
The present invention relates to an arithmetic device containing multiplier-accumulator circuitry. More particularly, the present invention relates to an arithmetic device that calculates effective lower bits of a parameter ND for Montgomery modular multiplication, where ND satisfies a mathematical condition R×R−1−N×ND=1 for an integer N and a radix R that is coprime to and greater than N.
2. Description of the Related Art
Recent years have seen a rapid growth of online trade market, also known as electronic commerce (e-commerce), where commercial transactions involving money transfers take place over a network. People are exchanging personal information such as their credit card numbers over a network more frequently than ever before. Such important personal information has to be protected from eavesdropping and tampering attacks by a malicious third party. The use of cryptographic techniques is thus mandatory to ensure the security of information transfer.
Public-key systems, one of the modern cryptographic algorithms, use a pair of cryptographic keys called public and private keys. The sender encrypts his/her message with the receiver's public key, and the receiver decrypts the received message with his/her secret private key. Suppose, for example, that a person is purchasing a product at an online store. The online store sends their public key to the purchaser, allowing him/her to send his/her credit card number and other information in encrypted form. The store can decode the received information by using their private key. The advantage of public-key systems is that the public key is made available to the public. That is; public-key cryptosystems permit one to achieve secure communication with anyone who have publicized their encryption keys.
One example of a public-key algorithm is RSA, named after its three creators: Ron Rivest, Adi Shamir, and Leonard Adleman. The RSA cryptosystem uses a modular multiplication process to ensure the secrecy of ciphertext, relying on the difficulty of prime factorization of a large integer. That is, when a certain number x and an integer n are given, it is relatively easy for a computer to calculate a power of x modulo n (remainder of division by n). But, because of the difficulty of prime factorization, it is very hard to accomplish the reverse process when n is large, meaning that the original number x cannot be reproduced easily. RSA is grounded on this nature of modular arithmetic.
RSA, however, requires a larger amount of computation for modular multiplication than symmetric cryptosystems such as the Data Encryption Standard (DES), and this fact leads to demands for a faster algorithm. Montgomery modular multiplication method is one of the solutions for reducing computational burden. When a radix R coprime to an integer N is selected such that R>N, the Montgomery algorithm computes T×R−1 mod N (i.e., remainder of division of T×R−1 by integer N) from an input value T satisfying O≦T≦R×N, where modulus N is represented as an irreducible polynomial of degree N. This algorithm is suitable for "modulo N" computation particularly when the integer N is very large. For details, see: P. L. Montgomery, "Modular Multiplication without Trial Division," Mathematics of Computation, Vol. 44, No. 170, pp. 519-521, 1985.
To implement the Montgomery algorithm, it is necessary to obtain a parameter ND that satisfies the condition of R×R−1−N×ND=1, where R−1 denotes the multiplicative inverse element of radix R, modulo N. It is known that ND can be obtained by applying the Euclidean algorithm to radix R and integer N, where the process of repeating divisions yields all digits of an ND value. While ND is a multiple-precision data word, we know that Montgomery modular multiplication requires not all bits of ND as its input parameter, but only a limited number of lower bits of ND. In this description, we use the term "effective lower bits" to refer to this limited range of lower bits of ND that are relevant to Montgomery modular multiplication.
Some algorithms for calculating ND take advantage of the fact that the effective lower bits of N×ND are all ones (e.g., 0xffffffff when lower 32 bits are used in modular multiplication). See, for example, . K. Koç, "High-Speed RSA Implementation," Technical Report TR 201, RSA Laboratories, Version 2.0, November, 1994, pp. 48-49. The following section will describe how this type of algorithm works.
FIG. 7 shows a conventional algorithm for calculating ND. The algorithm is represented in the form of a program code, where s (lowercase letter) denotes the number of lower bits of ND that are relevant to the calculation, and the number or symbol in square brackets following each variable S, N, or ND represents a particular bit position. The bit position is counted in the direction from the least significant bit (LSB) to the most significant bit (MSB). For example, S[0] means the LSB of variable S, and ND[i] means the (i+1)th bit of ND, counted from its LSB.
The algorithm starts with initialization of variable S and then repeats the following process for i=0 to s−1. Specifically, ND[i] will be set to one (ND[i]:=1) and N is added to S, if S[0] is zero. (Note that the addition takes effect only on the effective lower bits, and this holds true in the rest of this section.) The resulting sum is then shifted to the right by one bit, as indicated by the operator ">>1" in FIG. 7, before it is put in place of S. If S[0] is one, ND[i] is set to zero, and S is shifted right by one bit.
FIG. 8 shows the structure of a conventional arithmetic circuit for calculating ND. As an implementation of the algorithm described in FIG. 7, the illustrated arithmetic circuit 800 is composed of the following elements: a multiplexer 801, a two-input adder 802, a sum register 803, an inverter 804, and an ND register 805. The multiplexer 801 selects either N or zero (i.e., determines whether to add N to S), depending on the current value of S. The two-input adder 802 performs addition of the selected value and variable S. The sum register 803 stores the resulting sum S, while the ND register 805 stores ND.
Suppose that the sum register 803 has been initialized to zero. The multiplexer 801 determines whether to add N to S, depending on S[0], the current LSB of variable S. When S[0]==0, meaning that addition should take place, the multiplexer 801 selects and supplies N to the two-input adder 802. Otherwise, it selects and supplies zero to the two-input adder 802. The two-input adder 802 adds the selected value to the variable S read out of the sum register 803, shifts the result to the right by one bit, and stores it back into the sum register 803. The inverter 804 supplies the ND register 805 with an inverted version of the current S[0] as the bit of ND. The ND register 805 is a shift register designed to shift the data rightward each time a new bit arrives at its MSB end. The ND register 805 will thus yield a complete ND value when the predetermined number(s) of iterations are completed.
Carry delay time of the two-input adder 802 can be a critical factor in performance when ND has a large number of effective lower bits. For high-speed applications, carry-save adders (CSA) are thus preferred. Specifically, the carry output is saved in a carry register, aside from the sum output. A carry-save adder sums up three input values (N, S, carry) to yield ND.

Encryption/decryption system for calculating effective lower bits of a parameter for Montgomery modular multiplication


Methods, systems, and computer-readable media are provided for efficiently evaluation Boolean expressions. According to the method, the Boolean expression is expressed using pre-fix notation. Each element in the pre-fix expression is then parsed. For each first operand for a Boolean operation, the value of the operand is determined. This may include evaluating a GUID. When an operator and a second operand are encountered, a decision is made as to whether the second operand should be evaluated. The determination as to whether the second operand should be evaluated is made based upon the value of the first operand and the type of operator. If the second operand need not be evaluated, no evaluation is performed thereby saving time and memory space. The evaluation of the Boolean expression continues in this manner until the entire expression has been evaluated. If the Boolean expression is evaluated as true, the program module associated with the Boolean expression may be loaded. Otherwise, the program module will not be loaded.

In most computing systems, low level instruction code is used as an intermediary between the hardware components of the computing system and the operating software and other high level software executing on the computing system. In some computer systems, this low level instruction code is known as the Basic Input and Output System ("BIOS"). The BIOS provides a set of software routines that allow high level software to interact with the hardware components of the computing system using standard calls.
Because of limitations of the BIOS in many PC-compatible computers, a new specification for creating the firmware that is responsible for booting the computer and for intermediating the communication between the operating system and the hardware has been proposed. The new specification is called the Extensible Firmware Interface ("EFI") specification and is available from INTEL CORPORATION.
The EFI specification describes an interface between the operating system and the system firmware. In particular, the EFI specification defines the interface that platform firmware must implement and the interface that the operating system may use in booting. How the firmware implements the interface is left up to the manufacturer of the firmware. The EFI specification provides protocols for EFI drivers to communicate with each other, and the EFI core provides functions such as allocation of memory, creating events, setting the clock, and many others. This is accomplished through a formal and complete abstract specification of the software-visible interface presented to the operating system by the platform and the firmware.
The EFI is capable of providing services to other applications. Services are implemented by modules that may be loaded by a boot loader when the EFI is started. Because certain services are dependent upon other services for their operation, some modules must be loaded before other modules. In order to ensure that the various modules are loaded in the proper order, each module may provide a list of conditions that must be satisfied before the module can be loaded and executed. The list of conditions is specified as a dependency expression. A dependency expression is a Boolean expression that can be evaluated to a true or false state (the terms '0'/'zero'/'false' are used interchangeably herein, as are the terms '1'/'one'/'true'). If the dependency expression is evaluated as true, the module may be loaded immediately. If the Boolean expression is evaluated as false, the module may be loaded at a later time when the Boolean expression can be evaluated to true. If the Boolean expression cannot be evaluated as true, the module will not be loaded. In this manner, a proper order for loading each of the modules may be determined that takes into account all of the dependencies that a module may have.
Dependency expressions may include the standard Boolean operators AND, OR, and NOT, may include Boolean constants, such as '0' or '1', and may include Boolean variables. Boolean variables are variables that may be evaluated as true or false. One type of Boolean variable is the Globally Unique Identifier ("GUID"). Each service is assigned a GUID that uniquely identifies the service. If a GUID is specified in a dependent expression, it is necessary to evaluate the GUID by determining whether the service that the GUID refers to is currently available. If the service is available, the GUID is evaluated as true. If the service is unavailable, the GUID is evaluated as false.
Evaluation of a GUID specified within a Boolean expression can be a time consuming and memory consuming process. However, memory is very limited during certain phases of firmware initialization. There is also a desire to have each of the EFI services launched as quickly as possible. Therefore, there is a need for a method and system for efficiently evaluating a dependent expression that may include GUIDs within an EFI environment that can reduce the amount of time and memory required to evaluate the expression.

Method, system, and apparatus for efficient evaluation of boolean expressions


As disclosed herein, novel compositions including steroid hormones, such as trimegestone (TMG) and progesterone (P4), provide treatments for term and preterm labor with significant effects on the delay of delivery. Delay and block of delivery occurs when both P4 and TMG are administered late in gestation in pregnant rat and guinea pig animal models. TMG exhibits remarkable drug efficacy, achieving the same inhibition as P4, but at much lower doses. These hereto unknown effects of TMG on the processes of cervical ripening and uterine contraction provide a novel approach for extending pregnancy term, including reducing a likelihood of preterm and/or term labor, along with improved methods of administration. Other diseases and/or conditions may be treated with TMG, such as dysmenorrhea or luteal insufficiency for sustaining pregnancy.

All publications herein are incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. The following description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Preterm birth (less than 37 completed weeks of gestation) is one of the major problems and challenges in obstetrics. The frequency of preterm births is about 12-13% in the USA and 5-9% in many other developed countries.1,2 Despite all efforts to reduce the number of preterm births the problem is continuing to escalate. Since 1990 the percentage of births delivered preterm has risen more than 20 percent and is 36 percent higher since the early 1980s in the USA.3 Preterm birth is not only a major determinant of neonatal and infant morbidity, including neurodevelopmental handicaps, chronic respiratory problems, intraventricular hemorrhage, infection, retrolental fibroplasia, and necrotizing enterocolitis, but it is also the single most important cause of perinatal mortality in North America, Europe and particularly in undeveloped countries.4 Additionally, the neonatal and long-term health care costs of preterm infants impose a considerable economic strain both on individual families and on healthcare costs (>$26.2 billion in 2005 in the USA).5,53 There is a need in the art for novel and effective treatments for preterm delivery.
Both uterine and cervical functions play important roles in the onset and progression of term and preterm labor and delivery. Ripening of the cervix is an inflammatory-like reaction with infiltration of leukocytes, increase of cytokines (interleukin (IL)-1 and IL-8) and an increase in metalloproteinases (MMPs), with MMPs playing a key role in ECM remodeling.8,9,10 Following cervical ripening, uterine contraction and cervical dilation results in delivery of the fetus. Uterine contraction results from the biomechanical coupling of actin and myosin, which depends on the phosphorylation of myosin by myosin light-chain kinase (MLCK). The activation of MLCK by various uterotonins, including oxytocin and prostaglandins, fosters actin-myosin coupling, leading to synchronous high-amplitude activity in cell-cell connections that generate contractions in the uterus.
Both processes of cervical ripening and uterine contractility are regulated by steroid hormones (in particular progesterone (P4) and estrogen) and progesterone has been known to be used for recurrent or high risk preterm labor (PTL).17-26,32 However, P4 used to treat preterm labor and uterine contractile disorders is often delivered through inconvenient and less effective routes of vaginal, oral or intramuscular delivery. Further, P4 exhibits some measure of non-specificity for non-progesterone receptors, leading to potentially undesirable side effects.
Trimegestone (TMG), a 19-norpregnane derivative progestin, has been used in clinical trials as a proposed treatment for hormone replacement therapy, as well as for oral contraception.57-62 To date, the efficacy of compounds such as TMG has not been shown in treatments for pre-term pregnancy. As a "next generation" progestin (i.e., synthetic or exogenous progestogen), TMG exhibits a 6-fold higher affinity for progesterone receptor (PR) than P4, with much greater potency.11,12 This activity is coupled with higher selectivity for the PR compared to other steroid hormone receptors. For example, TMG binds with low affinity to the androgen, glucocorticoid and mineralocorticoid receptor and has no measurable affinity for the estrogen receptor.12,14,64,65 These pharmacological differences may result in notably different biological effects. For example, TMG also exhibits a differential effect on MMP expression in cultured stromal cells when compared to P4 administration.13 TMG also exhibits antiestrogenic activity in processes related to rat uterine decidualization and ovulation assays, and possesses the highest level of estrogenic activity antagonism in the uterine endometrium among reference progestins.67 Together, these results suggest TMG may be a potent compound for inhibiting cervical ripening and uterine contractility, with further opportunities to apply TMG in new therapeutic avenues, such as dysmenorrhea.68
These features of TMG present intriguing questions of how TMG application for preterm pregnancy treatment compares to P4 administration, and if higher PR specificity coupled with different mechanisms of action may lead to improved methods of treatment and/or administration.11

Trimegestone (TMG) for treatment of preterm birth


The present invention relates to a positioning marker intended to be inserted in tissue. The marker is an elongated object with a longitudinal axis A and with a diameter perpendicular to said longitudinal axis, wherein the diameter is at the most 1.2 mm. The marker further has a predetermined total length LTOT. The marker comprises a plurality of first segments 1 and a plurality of second segments 2, wherein the first and the second segments are arranged alternately after each others. The marker comprises a first material with a density of at least 10 g/cm3, and this material constitute at least 90% by volume of the marker, and a second material that is magnetic and that constitute at the most 10% by volume of the marker.

When treating cancer tumors the doctor is preparing the treatment e.g. by planning how large the dose of the medicine shall be or how much the radiation therapy shall comprise. Basis for the planning of the radiation therapy is done e.g. by using computer tomography images. These images are nowadays more and more frequently combined with images from other media such as magnetic camera images (a magnetic camera is normally referred to as MRI=magnetic resonance imaging) and images from a PET camera (PET=Positron Emission Tomography) in order with more certainty to determine the tumor/-s extension in all directions.
In order to minimize the side effects on normal healthy tissue repeatedly radiation doses normally are given. At these times of treatment it is important to carefully reposition the body and the tumor area according to predetermined parameters so the tumor area not will be missed.
Electronic image giving plates have been used for many years in order to control the position of the skeleton when using high energetic therapy beams on 4-20 megavolts (MV), which normally are used. In recent years the beam accelerators that give rise to the radiation doses have been equipped with complementary equipment resulting in x-ray beams in the kilovolt area (kV). These beams in the kV area have properties differentiated from the high energetic MV beam. The beams in the kV area are decelerated not only by the mass coming in its way, but also by a decelerating force in relation to the density of the material that the beams are passing by and the decelerating force is increasing almost exponentially with higher density.
Positioning markers are used in order to show the location of a tumor in a human or an animal tissue. These markers are decelerating the x-ray beams so much that the marker becomes visible on monitors where the results from different media are shown. Gold has a high density of 19.3 g/cm3, which makes it advantageously to be used as decelerating substance for the beams. Pure gold is also soft and possible to shape and is tolerated by the body since it is an inert material. The volume of gold may be limited so the substance becomes a thin wire, which also means that the marker may be inserted into the body be means of thin needles. Thereby the risk of bleedings and infections is minimized. Such a marker of gold is known by e.g. WO2006/004542 A1.
X-ray beams passing a body with a diameter of up until 60 cm give an image on the monitor by means of the beams having been decelerated to a varying extent in different parts of the tissue. If a small positioning marker of ca 0.25-1.2 mm in the tissue shall be able to influence the image the x-ray beams hitting on the marker must decelerate the x-ray beams to such extent that contrasting differences are giving in the image.
Markers that are put into tissue of human or animal will rest mainly in the same place the entire life. Thus, it is extremely important that the markers not cause mechanical damage or give rise to allergies or other state of ill-health. The marker must have sufficient size and have an appropriate density in order for the marker to be clearly depicted at MR examination.
The inventor has identified a need when using positioning markers of gold, which is related to the difficulty to make them visible on monitors from all media that are used in order to determine the extension of the tumor. In order to facilitate such that the images from the computer tomography and the magnetic camera may be superposed in the appropriate way it would be desirable that the positioning marker also is visible when using a magnetic camera. As an example small positioning markers of gold are not visible on magnetic camera images.
The purpose with the present invention is thus, to achieve a positioning marker that is visible on monitors for the majority of media being used in order to optimize the beam treatment planning. Further the marker shall satisfy the demands to be tolerated of the body and not to cause mechanical damage in the body of the person in which the marker is inserted.