A modular solid-state radar transmitter apparatus for producing waveforms whose amplitude may be varied over time. The transmitter achieves pulse modulation on either an intrapulse or pulse to pulse basis, while at the same time reducing stress on individual solid-state modules. Intrapulse modulation and pulse to pulse modulation can be produced with the disclosed modular solid-state transmitter because the number of modules and the sequence in which they are activated is selectable. These selections provide the various desired levels of transmitted power and thus effectively achieve modulation. In order to achieve this intrapulse modulation, a variable combiner is introduced whose coupling factor is coordinated with the module activations. In one embodiment, variable combining is accomplished by the use of RF switching logic for combining pairs of signals in parallel. In this case, RF switches are programmed to act as a conventional combiner when all modules are active. When a module is deactivated, the switches are set so that the active modules are connected to the output or the next stage of combining. Another embodiment uses a series approach to accomplish such variable combining. Here, when all modules are active RF switches and phase shifters are programmed for performance as in a conventional combiner. When a module is deactivated, the phase of the signals within each coupler section is adjusted by means of RF amplifier programming and phase shifters to avoid loss in the termination.

Radar is used to detect and locate remote objects by the reflection of radio waves. This is accomplished by transmitting a signal of a known waveform and observing the nature of the received echo. Traditionally, the radar waveform has usually been a repetitive train of short-duration pulses all of a constant amplitude. There are certain applications for radar, however, where the production of a pulse train or waveform having varying degrees of amplitudes is advantageous. For example, tracking of objects can be improved through the use of a radar system which is capable of producing variable waveforms. This is because such systems are less susceptible to jamming and other types of Electronic Counter Measures (ECMs).
The desirability of varying a waveform's shape, also known as pulse shaping, is discussed in Chapter 27 of RADAR TECHNOLOGY by Brookner entitled "EFFICIENT SPECTRUM CONTROL FOR PULSED RADAR TRANSMITTERS". Here, waveform control or spectrum control is discussed in the context of meeting Electro-Magnetic Compatibility (EMC) requirements which are now commonly specified on radar equipment, e.g., MIL-STD-469. Techniques are considered to improve the efficiency on shaped pulses for the Traveling Wave Tube (TWT) and Klystron Tube Transmitters. With these techniques, a reasonable efficiency can be achieved, however, the complexity in the design of the power supplies for the tubes is greatly increased. This translates into a significant cost increase which has prohibited widespread implementation.
Without the help of complex and expensive power supplies, tube transmitters have significant problems when they are run in any state other than saturation. As such, they are seldom operated except in that manner. Thus, with only this single mode of operation, tube transmitters have little capability to vary the power transmissions of the pulses. One way of varying the power is to form a series or sequence of transmitter tubes called a transmitter chain. Again, such a method is prohibitive because of its cost.
The amplitudes of pulses from tube transmitters may also be controlled at IF and microwave frequencies by using a PIN diode as an attenuator or switch. For example, a PIN diode can be configured in shunt to an output RF signal so that when the diode is zero biased the signal will be transmitted with no effect; when the diode is forward biased the RF resistance decreases, shunting some of the signal to ground and thus attenuating the output signal. This is the basic reflective attenuator. The disadvantage of such a circuit is that some of the input signal will be reflected back to the input port, resulting in reduced efficiency and a poor Voltage Standing Wave Ratio (VSWR) that increases as the current is increased. In addition, the attenuation range is limited. Other methods of amplitude control for tube-type transmitters are described in MODERN RADAR TECHNIQUES edited by Scanlan, Macmillan Publishing Co. 1987, at pages 63-69, however, each has limitations similar to those methods previously described.
Because of the above-mentioned drawbacks, there has been little interest in modulating the power in a transmit pulse from a tube transmitter, either as a function of pulses in a group or on an intrapulse basis, i.e., where various amplitudes are present in a single pulse envelope. Consequently, waveform designers have concentrated on the design of coded pulses of constant amplitude and placing these constant amplitude pulses in groups which are weighted upon their receipt at the receiver. This technique can be used to control the time or spectrum sidelobes of the transmitted wave.
Because tube transmitters are seldom operated except in saturation, it has also been impossible to match the transmitted pulse waveform to that of a rectangular pulse which would provide for optimum detection; that is because a rectangular transmitted pulse requires an unrealizable rectangular filter. This unmatched condition leads to losses in the system design, since essentially some of the transmitted power is being discarded. Also, because the tube transmitters have very fast risetimes, they are vulnerable to electronic countermeasures (ECM) or jamming.
Another type of transmitter which is gaining popularity and which is replacing tube transmitters in certain applications is the solid-state transmitter. In a tube transmitter, a single thermionic device or high power microwave valve provides the final amplification for the system. Having a single power device to provide system-wide power can be disadvantageous because such devices have a limited life and failure results in complete radar system failure. With solid-state transmitters, the available architectures are significantly more diverse. They range from a set of modules which are centrally located and which emulates a tube transmitter, to a fully distributed architecture which places transmit/receive modules in an array on the antenna. Such architectures allow for the use of smaller, less stressed and less costly mass produced microwave semiconductor power devices. The very long operating life of semiconductor devices not only allows a decrease in overall radar failure rate, but provides a gradual degradation in radar performance as the semiconductor devices fail.
With the advent of solid-state transmitters, system designers have new opportunities. A typical new opportunity is more flexibility in the transmitted waveform. Additional flexibility in waveform design is available, because with modular solid-state transmitters, the number of modules which are active at a given time is selectable. This selectability is useful in order to vary the power and amplitude of the transmitted pulses.
It is, therefore, an object of the present invention to provide an apparatus and method for utilizing the added flexibility of solid-state radar transmitters to produce advanced waveforms having varying degrees of amplitude, while at the same time reducing prime power usage. The apparatus achieves significant performance advantages, such as a reduction in prime power usage. As mentioned, radar systems capable of transmitting variable waveforms provide better detection because they are less susceptible to interference from jamming and other ECMS. This invention overcomes the difficulties associated with tube transmitters through the use of a variable combiner able to achieve modulation on a pulse-to-pulse basis or an intrapulse basis. The combiner increases efficiency by controlling losses in output power when individual modules of a solid-state transmitter are activated and deactivated. Intrapulse modulation and pulse to pulse modulation can be produced with the disclosed modular solid-state transmitter because the number of modules and the sequence in which they are activated is selectable. These selections provide the various desired levels of transntitted power and thus effectively achieve modulation.
In order to achieve this intrapulse modulation, a variable combiner is introduced whose coupling factor is coordinated with the module activations. In one embodiment, variable combining is accomplished by the use of RF switching logic for combining pairs of signals in parallel. In this case, RF switches are programmed to act as a conventional combiner when all modules are active. When a module is deactivated, the switches are set so that the active modules are connected to the output or the next stage of combining. Another embodiment uses a series approach to accomplish such variable combining. Here, when all modules are active RF switches and phase shifters are programmed for performance as in a conventional combiner. When a module is deactivated, the phase of the signals within each coupler section is adjusted by means of RF amplifier programming and phase shifters to avoid loss in the termination resistors.
Finally, since the solid-state transmitter is modular, different modules can be activated during the beginning and end portions of a waveform to accomplish the intrapulse modulation. This decreases the stress on any one individual module, achieving the same result as if identical modules were activated at both the start and finish of the modulated pulse.

Modular solid-state radar transmitter apparatus and method for producing variable waveforms


A waste collection device (10) comprising a receptacle (12) having an opening (24) in an upper end and a tubular member (28) mounted for sliding movement within the opening (24). A pump is provided for pumping water outwardly from within the receptacle (12) and a basket is provided within the tubular member (28). The tubular member (28) comprises a cylindrical inner wall (32) and a cylindrical outer wall (33) connected at upper and lower ends thereof to define an annular chamber (36) to provide buoyancy to the tubular member (28).

The amount of waste which finds its way into lakes, rivers and the oceans has become a significant environmental problem. The present invention relates to a device to be deployed within such bodies of water in order to collect floating waste for proper disposal.
The device proposed in the applicant's earlier Spanish Patent number 201330495 comprises a garbage collection device designed to be located adjacent the surface of a body of water. This device acts to draw water into the top of the receptacle, which is captured in an internal basket. Water is pumped out of the receptacle by an internal pump, thereby lowering the water level and causing the basket to fall, allowing inflow of water. As the water level rises, the basket moves again upwardly. While the device described operates reasonably effectively, the present invention aims to provide a garbage collection device having improved performance. The present invention relates to a waste collection device having features aimed providing improvements with regard to maintaining a more constant flow of water through the device and also coping with heavy loads within the basket.


An insecticidal barrier (1) having an upper net part (2) with a mesh size preventing insects, for example mosquitoes, to transverse the barrier, the upper net part (2) having a first content of insecticide. In addition, the insecticidal barrier (1) has a lower part (3) with an insecticidal fabric, tarpaulin, foil, woven or knitted fabrics or non-woven, or net with a net material having a higher tear strength than the net of the upper part (2) in order to make the lower part (3) of the net more durable.

Use of mosquito nets is one of the most important means for protection against vector born diseases. Accordingly, there is an ongoing effort for improving the efficiency and durability of nets, especially of nets to be used in rural areas, where supply of new nets is limited and there is a tendency to use acquired nets for a long time.
One means to improve the durability of nets is a border or skirt at the lower edge of the nets protecting the nets against wear. Such border is made of a stronger material, for example a fabric. The height of the border, typically, varies between 10 cm and 25 cm. In addition, the WHO has adopted the requirement that a Long Lasting Insecticidal Net should last for at least 20 washes and still show sufficient insecticidal activity. However, as has turned out, often, not the wash resistance is the limiting factor but the general long term use of the nets, where the insecticidal effect is reduced with time. Thus, there is a general need for improvement in the art.
Often such improvements are performed in countries other than the countries where the nets are used. For the developer, this is a challenging task, because the way of living in the countries of the developers may be substantially different from the way of living in the countries, where the nets, finally, are used. Often, this implies that the product is not optimised for the customers, and only close study of the behaviour of the customers can reveal the required optimal aspects of a product. In connection with the invention, as explained in the following, such close, behavioural studies have been performed in order to improve insecticidal products, primarily mosquito nets.

Insecticidal barrier with a durable lower part


Embodiments of the present invention relate to a method and system for automatic event analysis. In particular, according to embodiments of the present invention, there is disclosed a method for automatic event analysis, comprising: collecting information on events of a predetermined type occurring at, within a period of time, at least one location in a space; determining a predictability of the events of the predetermined type with respect to the at least one location based on the collected information and a predetermined condition(s) related to the events of the predetermined type; and determining the stability of predictable events with respect to the at least one location within the period of time. Further, there is disclosed a corresponding system. According to embodiments of the present invention, it is possible to classify an event associated with a service and analyze the service demands in a more efficient way.

For lots of services in information, data, telecommunications and/or traditional non-information fields, the accurate estimation and analysis of service demands are of vital importance. In particular, many services are spatially distributed, such as mobile communication services, network services, etc. For such services, how to accurately analyze and predict service demands at different locations and/or different moments plays a significant role in the allocation and planning of service resources, for example.
Consider mobile communication services as an example. In a wireless communication network formed by cells, the service capacity (e.g., coverage scope, the number of mobile terminals that can be processed, etc.) of each local access point (AP) is typically limited. It depends on the service demand prediction to a great extent regarding how and what access points are disposed at various locations of the wireless network and how these access points are activated or deactivated at different periods of time. Specifically, if it is possible to determine by analysis that a service demanded at a certain location is obviously higher than those at other locations, then it is possible to accordingly adjust the number of deployed APs, the type thereof, and/or the service capacity, etc.
Known service demand analysis includes statistics of service situation at various locations in a space where services are distributed. Based on the statistical information, it is possible to analyze the service demand situation at each location. However, according to the prior art, an event triggering a service is always assumed to be predictable in the demand analysis of spatially distributed services. Hence, different characteristics and different aspects of such events are not fully considered in the service analysis and subsequent optimization. Besides, spatial heterogeneity in the worst case scenarios is difficult to estimate according to known demand analysis schemes. Sharing of flexible resources (e.g., temporal resources) is also difficult. Moreover, known demand event analysis schemes fail to integrate the fact that demands vary with the location and time. Therefore, the location-based demand statistics and analysis will not be efficiently updated or changed with time.

International Business Machines Corporation


A seating device can include a seat and a base connected to the seat to support the seat. A tilt mechanism can be connected to at least one of the base and the seat. The tilt mechanism can include at least one of (a) at least one seat connecting member connecting the seat to an upper portion of the base, (b) a plurality of resilient fingers that are attached to the base to engage a floor and flex in response to a user providing a force while sitting or leaning on the seat, and (c) an elastomeric floor engagement member that is attached to the base and has a bottom peripheral portion that contacts a floor and is flexible in response to a user providing the force. In some embodiments, the tilt mechanism may include all of elements (a)-(c).

Chairs often include a base that supports a seat and/or a backrest. Examples of chairs, stools, and other types of seating devices may be appreciated from U.S. Pat. Nos. 8,764,117, 8,663,514, 8,646,841, 8,480,171, 8,220,872, 8,216,416, 8,167,373, 8,157,329, 8,136,876, 8,029,060, 7,887,131, 7,478,878, 7,198,329, 6,997,511, 6,834,916, 6,824,218, 6,817,667, 5,683,139, 5,112,103, 4,738,487, 4,130,263, 3,312,437, and D664,779 and U.S. Pat. App. Pub. Nos. 2003/0168901, 2006/0006715, and 2008/0290712.
Chairs may be configured to include a tilt mechanism for use in controlling tilting of a seat or backrest. Examples of chair tilt mechanism can be seen from U.S. Pat. Nos. 8,668,265, 7,922,248, 7,798,573, 6,957,863, 6,880,886, 5,775,774, 5,203,853, 5,997,087, and 4,652,050. Such tilt mechanisms often require use of one or more springs that are stored internally within a housing that is used to connect a pedestal base so that the base of the chair can support the seat backrest, and armrests of the chair. Such tilt mechanisms can often be expensive to manufacture.


A generalized zigzag code is described where the code segments (each including one parity bit and information bits) of a block are not necessarily of uniform length. For coding rates in which the average code segment length is not an integer, all code segment lengths may be identical. The number of code segments depends on the coding rate and number of information bits in a block. At the encoder, parity bits are added to each string of information bits in a block to yield the code segments. For a punctured code, concatenated or not, the encoder may remove or not generate the punctured parity bits. At a decoder that operates at a rate different from the code rate of a received block, null parity bits are inserted. The received block has a number of code segments. The decoder increases the number of code segments by the addition of null parity bits, thereby reducing the coding rate to the rate of the decoder. Methods and apparatuses are detailed.

Turbo codes, introduced in early 1990s, can achieve performance very close to the Shannon limit. These codes are now used in various cellular standards, e.g., WCDMA and 1×EV-DV. However, a turbo-decoder based on the a posterior probability APP algorithm is highly complex. Concatenated single-parity check codes are an alternative that offer much reduced decoding complexity, but at the cost of high error floors and sub-optimal performance at low data rates.
It is believed that zigzag codes and concatenated zigzag codes were first introduced in a paper by L. Ping, X. Huang, and N. Phamdo, entitled ZIGZAG CODES AND CONCATENATED ZIGZAG CODES, IEEE Transactions on Information Theory, Vol. 47, No. 2, February 2001, pp. 800-807. The performance of zigzag codes has been asserted as very close to that of Turbo codes (only about 0.5 dB worse, according to the above paper), while the decoding complexity of zigzag codes is significantly lower than that of Turbo codes. By increasing the coding rate one can increase the data rate at the cost of degraded link performance and increased mega-instructions-per-second MIPS requirement (due to larger size of the data block to be decoded). For high data rate systems that use high coding rates, it is desirable to have lower complexity decoding schemes with performance as close to the Turbo codes (and thus the Shannon limit) as possible. Concatenated zigzag codes appear to provide an attractive alternative to Turbo codes in this respect.
Following is an abbreviated description of zigzag codes, as generally presented in the above paper by Li Ping et al. FIG. 1 is a prior art schematic view of information bits and parity bits in a zigzag code. The information bits to be encoded are represented by {d(i,j)}, i=1,2,3, . . . I, j=1,2,3, . . . J. The parity bits are represented by {p(i)}, i=1,2, . . . I. Further, a segment is defined as [p(i−1),d(i,1),d(i,2), . . . d(i,J),p(i)], and is illustrated in FIG. 1 as the bits along one straight line. The parity bits are chosen such that each segment contains even numbers of ones. The code rate is thus J/(J+1).
At the transmitter, the parity bits are computed as follows:
                                          p                                      (              1              )                                =                                    ∑                              j                =                1                            J                                                                  d                                                  (                                      1                    ,                    j                                    )                                                                                mod                                                                                2                                                                                p                                            (                i                )                                      =                                          [                                                                            ∑                                              j                        =                        1                                            J                                                                                d                                                                    (                                                  i                          ,                          j                                                )                                                                              +                                      p                                                              (                                              i                        -                        1                                            )                                                                      ]                                                                                mod                                                                                2                                ,                                                                              for                                                                                i                        =            2                    ,          3          ,          ⋯                                                    ,                      I            .                                              [        1        ]
Defining a weighting formula for parameters a1, a2, . . . an
            as                                              W                          (                                    a              1                        ,            ⋯                                                              ,                          a              n                                )                      =                  [                              ∏                          i              =              1                        n                                                                                sgn                                      (                              a                i                            )                                      ]                                    min                      1            ≤            i            ≤            n                                                                  a            i                                          ,yields the following equations to calculate the MLA's of the parity and information bits, where F[*] is the forward MLA for the bracketed parity bit, B[*] is the backward MLA for the bracketed parity bit, and L[*] is the MLA for the bracketed information bit:F[p(0)]=+∞F[p(i)]={tilde over (p)}(i)+W(F[p(i−1)],{tilde over (d)}(i,1), . . . ,{tilde over (d)}(i,J)), for i=1, . . . ,I  [2]B[p(I)]={tilde over (p)}(I),B[p(i)]={tilde over (p)}(i)+W({tilde over (d)}(i+1,1), . . . ,{tilde over (d)}(i+1,J),B[p(i+1)]), for i=I−1, . . . ,1  [3]L[d(i,j)]={tilde over (d)}(i,j)+W(F[p(i−1)],{tilde over (d)}(i,1), . . . , {tilde over (d)}(i,j−1),{tilde over (d)}(i,J+1), . . . ,{tilde over (d)}(i,J),B[p(i)])   [4]
The prior art zigzag code of FIG. 1 is shown in tabular form at FIGS. 2A-2B, with an additional set of parity codes to show how zigzag codes might be concatenated. FIG. 2A is an I*J size matrix of information bits d(i,j), where I=5 and J=3. FIG. 2B is a column matrix of I rows showing parity bits p(i). Redefining a code sequence as a string (of at least one) information bit d(i,j) terminating with a parity bit p(i), each of the code segments according to the paper by L. Ping et al. are then the rows of the matrix of FIG. 2A followed by the associated parity bit for the relevant value for i. Each code segment is necessarily the same length as all other code segments, which in this example is three information bits and one parity bit, because j=1, 2, 3, . . . J for each code segment.
A concatenated zigzag code is defined by (I,J,K) where K represents the number of encoders used in concatenation, each encoder multiplying the information bit matrix (FIG. 2A) by a separate parity bit matrix (FIG. 2B). The information data block of FIG. 2A (matrix of I rows and J columns, I*J) to be encoded is first passed through a random interleaver. The parity bits, p(i), of this block of data are calculated using equation [1] above, and represented by FIG. 2B. The original information data block of FIG. 2A is now passed through a second random interleaver and a different set of parity bits are computed and interleaved. This concatenation continues for the number of encoders (K) used. Thus a total of K columns of parity bits (each having length I as shown in FIG. 2B) are computed and are transmitted along with the original information data block of FIG. 2A. The number of total transmitted bits is I*(J+K) (I*J is the number of the information bits and I*K is the number of the parity bits). The code rate of a concatenated zigzag code is therefore J/(J+K). Because each of J and K must be non-zero integers, the coding rate for the above described zigzag codes cannot be arbitrarily set in a transmitter with a finite number of encoders. Each code segment is still the same length as all other code segments.
Practical communication systems are usually required to support several different data rates depending on the channel conditions and user preferences. This requires flexible code rates and puncturing schemes along with appropriate decoding algorithms to provide the desired data rates at an acceptable error rate performance. In a paper by K. S. Chan, L. Ping and S. Chan, entitled ADAPTIVE TYPE II HYBRID ARQ SCHEME USING ZIGZAG CODES, Electronics Letters, Vol. 35, No. 24, November 1999, pp. 2102-2104, a method of puncturing concatenated zigzag codes has been proposed which can be used in hybrid automatic repeat-request ARQ systems as well. However, it appears that the approach in the paper by K. S. Chan et al. does not enable an arbitrary rate code. The inventors view the set of available rates by that approach as not sufficiently broad to serve the needs of current telecommunications systems, as the only available rates are J/(J+1), J/(J+2), . . . , J/(J+K).
What is needed in the art is a coding scheme that enables high data rates but that is less computationally expensive than turbo codes. For practical deployment in existing communication infrastructure, such a coding rate should be compatible with various wireless standards already in use around the world.

Flexible rate and punctured zigzag codes


The present disclosure generally relates to a method for controlling a medical device. The method may comprise tracking movement of a foot with a hands-free device and processing movement of the foot to move a cursor, wherein the cursor is disposed on a display screen of the medical device. The method may further comprise receiving a selection of at least one icon with the cursor through the hands-free device. A system for controlling a medical device may comprise a console and a display screen coupled to the console and may be configured to display a cursor. The system may further comprise a hands-free device. The hands-free device may be communicatively coupled to the console and may be operable to track movement within a tracking area and generate an output. The system may further comprise a medical device connected to the console and a processor configured to execute instructions.

Surgical operations often require many different and specialized tools. The tools may include a complex machine, designed to function and/or operate in a specific manner. Furthermore, tools may have individual controls that do not communicate and/or work with other controls. Specifically, controls may be in the form of foot pedals, which may allow a surgeon to operate and control a tool with their feet. This presents many challenges in the operating room during a surgical operation.
For example, a medical device, controlled by a foot pedal, may include more functions and/or operations than switches and/or buttons on the foot pedal. To operate and/or function a medical device in a manner not attached to the foot pedal may be performed by an operator utilizing a touch screen to select such operations and/or functions. This may not be possible as the operator may have both hands operating other medical devices, which may be disposed in a patient. Current techniques for controlling the function and/or operation of medical devices during a surgical operation are both rudimentary and onerous and may lead to costly mistakes that a patient may bear.


The present invention concerns the field of processed cheese compositions, and, more particularly, relates to reduced salt processed cheese compositions. The present invention derives from the surprising finding that potassium lactate can be used in the manufacture of processed cheese compositions with reduced sodium content, without detrimental consequences on the taste of the final product. A processed cheese composition according to the invention imparts to the final product an improved flavour perception, as well as strengthening salty, savoury and cheesy taste. An additional surprising finding of the method of the invention is that the use of potassium lactate according to the invention has beneficial consequences on the safety and shelf life of the final product. The use of potassium lactate, in particular potassium lactate in the form of a fermentation product in accordance with the invention, also obviates the need to incorporate artificial flavorings and flavor enhancers, which results in a product with an improved label.

Processed cheese is broadly defined as a blend of one or more natural cheeses of different ages, emulsifying agents, water, and other dairy and nondairy ingredients. The mixture undergoes heating and continuous agitation to produce a pasteurized product that is homogeneous and has an extended shelf life. Processed cheeses are dairy products with relatively high sodium content. This is partly caused by salt present in cheese (accounting for approximately 28% to 37% of the final sodium content), partly by sodium-based emulsifying salts that are used in processing to get the required product characteristics (approximately 44% to 48%), and finally by the further addition of salt (approximately 15% to 28%).
Excessive intake of sodium is known to be a risk factor for many diseases including hypertension, and nowadays a large number of health guidelines recommend to limit the intake of sodium chloride. To decrease the sodium content in processed cheeses the emulsifying salts can be replaced by non-sodium salts (such as potassium-based salts) and added sodium chloride can be reduced or removed.
However, the salt plays an important role in the food safety of cheese because the amount of salt in the moisture phase of the cheese controls the growth of microorganisms. Indeed, to date, the body of evidence for the safety of processed cheese relies heavily on high amounts of sodium chloride in the product. Models developed to ensure the microbiological safety of processed cheese are based on the inhibitory effects of sodium phosphate-based emulsifying salts in combination with pH, water activity, and sodium chloride. As a matter of fact, processed cheese falls into the category of low-acid canned foods due to its chemical composition and pH. Therefore, anaerobic spore-forming organisms such as Clostridium spp. are one of the major concerns in processed cheese.
In addition, reducing sodium has a very negative impact on the taste of the product. Despite a number of attempts to compensate salt reduction with flavor enhancers, there is currently no satisfactory solution to manufacture a processed cheese composition with a low sodium content and a taste acceptable for consumers.
It is thus the objective of the present invention to provide a processed cheese composition with reduced levels of sodium, with improved organoleptic properties and/or microbial stability.
Furthermore, there also has been an increased desire to provide foods that contain an increased amount of natural ingredients or ingredients perceived as natural by the consumer.

Salt reduction in processed cheese compositions, processed cheese composition and use


A system and method for automatically establishing TV channels, based on time/date/geographic location/location of the TV within the home either entered manually or using a locater system such as GPS.

1. Field of the Invention
The present invention relates generally to television systems.
2. Description of the Related Art
Televisions and computers have become ubiquitous, and since both usually entail a visual display, efforts have been made to integrate both functions into a single system. In this way, a consumer need not purchase and operate two separate systems, which can burden some consumers who, while familiar with operating a television and its remote control, might not be familiar with operating, e.g., an Internet computer.
To the extent that attempts have been made to combine television with Internet features, it has generally been with the focus of producing what might be thought of as a "lean forward" system. That is, hybrid TV/computers have typically been more oriented toward productivity, generally thought of as a computer system characteristic, and less toward entertainment ("lean back"), generally regarded as a television system characteristic. It is not just the dichotomy between productivity and entertainment that distinguishes a "lean forward" experience from a "lean back" experience, however. As contemplated herein, "lean forward" activities often are experienced by only a single person, while "lean back" activities are often group experiences. Moreover, "lean back" activities can extend to purchasing products that are advertised on TV, as opposed to, e.g., making products for sale. In any case, with the above-mentioned critical observation of the present invention in mind, it can readily be appreciated that the differences between a system designed for "lean forward" experiences and a system designed for "lean back" experiences can be both subtle and profound.
An example of a "lean forward" system is the system known as "WebTV", in which preselected Internet pages are loaded once into a television during manufacture and never subsequently updated, with the preselected pages being accessible through the television using a computer keyboard with its attendant complexity. To access the pages, the consumer must access a central site by means of the keyboard, and then be redirected to a desired Web page. In terms of currently expected speeds of Internet access, this consumes an undue amount of time. Furthermore, it requires browser or browser-like operations that must be executed by a consumer. All of these features—use of a keyboard, knowledgeable use of a browser, and wait time for Web page access—are not per se unacceptable for a lean forward experience, but would severely detract from a lean back experience.
For instance, in the context of lean back, entertainment- and group-oriented experiences, consumers are accustomed to using a much simpler input device than a computer keyboard, namely, a remote control. Moreover, a user interface that is simpler than a Web browser, e.g., an electronic program guide (EPG), is preferred. Also, waiting for entertainment to load or otherwise be prepared for playing is distracting in a lean-back, group-oriented experience. But as exemplified above by the WebTV system, current systems that attempt to integrate television and computers essentially do so by grafting a TV onto what is essentially an underlying, lean forward computer system, and consequently provide less than optimum lean back experiences. As an example, a large number of potential TV settings are available, and unlike a computer user who might expect to alter computer settings frequently based on the task at hand, a TV viewer might not want to laboriously establish each one every time viewing circumstances change. The object of the present invention is to provide a TV system that accommodates lean back experiences better than existing systems.

System and method for establishing TV channel


Provided are a method, apparatus, system, and article of manufacture, wherein in certain embodiments a network adapter having an offload protocol stack receives a query. The offload protocol stack of the network adapter is configured to provide a programmable identity for the offload protocol stack of the network adapter. A response is generated to the query by processing the query in the configured offload protocol stack, wherein the response is based on the programmable identity. The generated response is sent by the network adapter.

1. Field
The disclosure relates to a method, apparatus, system, and article of manufacture for generating a response in an offload adapter.
2. Background
A network adapter may be coupled to a host system to provide communications. Some network adapters may provide hardware support for the processing of data related to the Transmission Control Protocol/Internet Protocol (TCP/IP) or other protocols that may be used for communications. Such network adapters may be referred to as offload adapters, and if the provided hardware support is for the TCP/IP protocol then the offload adapter may be referred to as a TCP/IP offload engine (TOE) adapter. Further details of the TCP/IP protocol are described in the publication entitled "Transmission Control Protocol: DARPA Internet Program Protocol Specification," prepared for the Defense Advanced Projects Research Agency (RFC 793, published September 1981). TOE adapters may perform all or major parts of the TCP/IP protocol processing, including processing send requests, i.e., requests to send packets from a host system to a computational device.
A protocol stack may be implemented in the TOE adapter, wherein some of the functions of protocol processing may be offloaded from a host system to the protocol stack, and wherein the TOE adapter is coupled to the host system and provides communications for the host system. The protocol stack for the TOE adapter may be implemented in hardware, software, firmware, microcode or any combination thereof.
Certain applications may be used for network exploration or security auditing. Such applications may transmit raw packets and attempt to determine what hosts are available in a network, what services the hosts provide, what versions of operating systems the hosts run, what type of packet filters or firewalls are in use in the hosts, and other characteristics associated with the hosts and the network. Certain applications perform such network exploration or security auditing for exploiting vulnerabilities in the hosts and the network.

Method, apparatus, system, and article of manufacture for generating a response in an offload adapter


A power transfer system includes DC-DC power conversion circuitry that has a first switch and a second switch on either side of a transformer with a first capacitor and a second capacitor cross-connected across the transformer. A direction of power transfer is determined, and primary and secondary sides of the DC-DC power conversion circuitry are aligned based on the direction of power transfer. A quantity of power transfer through the DC-DC power conversion circuitry is determined based on power and voltage characteristics of electrical components. A duty cycle and a switching frequency for the first switch or second switch is determined based on the quantity of power to be transferred. The primary and secondary switches are controlled using switching.

A DC-DC converter can employ magnetic and capacitive isolation to conduct bi-directional power transfer. U.S. Patent Application Publication No. 2013/0300210 A1 entitled "Power Transfer System" by Hosotani describes a power transfer system that performs DC-DC power conversion through soft switching and supports bi-directional power transfer through symmetrical full bridge switching circuits.

DC-DC power conversion circuit with magnetic and capacitive isolation

Toyota Motor Engineering & Manufacturing North America, Inc.


An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock trees are used to synchronize the buffering and conditioning of input/output signals before sending such signals to a pad or core. The clock trees are implemented via custom layouts to allow tight control of clock/strobe parameters (e.g., skew, duty cycle, rise/fall times). Two of the clock trees are local to the I/O interface and trigger a plurality of output latches configured on-the-fly to buffer output data signals from the core in asynchronous or synchronous mode. In the synchronous mode, a clock/strobe could be either edge-centered or window-strobe with respect to the data. The third clock tree distributes clock/strobes from an external source and is used to trigger a plurality of input latches configured on-the-fly to buffer input data from the pad in either a window-strobe mode or an edge-centered mode. The I/O interface also includes conditioning circuits that condition the I/O signals to be compliant with AGP/DDR protocols, as well as, full swing, reduced swing (SSTL), and TTL signal specifications.

Since the advent of integrated circuits, I/O interfaces have been used for the purpose of interfacing internal (i.e., on-chip) circuits to external (i.e., off-chip) circuits. I/O interfaces typically are designed using asynchronous circuits which operate without a clock. As the frequency of signals through the interface increases, however, it becomes more difficult to capture and transmit signals using asynchronous circuits. In an asynchronous circuit, signals ripple through the system, set and reset flip-flops, and produce an output at some unpredictable future time dependent on system propagation delays. Because signals can happen at any time, asynchronous circuits are prone to being upset by noise in the system. For example, a noise burst on a signal line between clock pulses could cause a number of flip-flops to change state and cause a system malfunction.
In contrast, synchronous circuits, such as edge-triggered "D" flip-flops, can be used to reliably capture and transmit signals on either the positive-edge or the negative-edge of a clock pulse or strobe. A noise burst on a signal line between clock pulses does not typically upset a synchronous circuit. While synchronous circuits have been included in I/O interfaces for testing purposes (e.g., scan testing), they are not typically used to capture data signals communicated between core logic and pads in an integrated circuit chip. To reliably capture such data signals, synchronous circuits must have clocks that abide by a variety of constraints including skew, duty cycle, and setup/hold times. If these clock parameters are violated, the synchronous circuits could malfunction (e.g., clock race, latch-up) resulting in erroneous data signals being captured and transmitted. To reduce the probability of synchronous circuits malfunctioning, such circuits can be designed using custom physical layouts.
Custom physical layouts place physical placement control and constraints on the components of the I/O interface so as to restrict the variability of critical parameters, thereby ensuring reliable high frequency operation. By designing components to have a tight relationship to each other, any uncertainty in the operation and/or compensation of such components can be minimized. For example, clock and data paths can be accurately matched as well as designed to compensate for simultaneous switching push-out.
In addition to reliability concerns, it is also desirable that I/O interfaces be configurable on-the-fly to comply with multiple protocols and signal specifications including: Accelerated Graphics Port (AGP), Double Data Rate (DDR), Peripheral Component Interconnect (PCI), Stob Serial Terminated Logic (SSTL), and Transistor-to-Transistor Logic (TTL). Such I/O interfaces provide additional flexibility to system designers.
Accordingly, there is a need for reliable and flexible I/O interfaces for buffering and conditioning data signals between core logic and pads in integrated circuit chips. It is desirable that these I/O interfaces be configurable on-the-fly to comply with multiple protocols and signal specifications. Such I/O interfaces should have custom physical layouts of circuitry, power, and clock bussing to eliminate problems associated with, for example, uneven layout traces.

AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip


A bias circuit includes a resistor in parallel with a voltage-drive bias circuit including a GaAs-HBT transistor. This configuration ensures that a current can be supplied from a reference voltage input terminal to the base terminal of a first transistor via the resistor in an idling state in which a voltage applied to the base terminal is lower than a voltage at which a second transistor operates, thereby enabling a desired amplifying operation while maintaining the idling current generally constant in a temperature range, even when the reference voltage is reduced to a value lower than twice the barrier voltage of the GaAs HBT.

1. Field of the Invention
The present invention relates to a bias circuit for a power amplifier and, more particularly, to a bias circuit including an emitter follower integrally formed on one GaAs chip for a power amplifier and capable of operating by a low external reference voltage.
2. Background Art
GaAs-heterojunction bipolar transistors (GaAs-HBTs) have recently come into wide use in power amplifiers for portable telephones including those in code division multiple access (CDMA) systems and power amplifiers for wireless LANs.
In Japanese Unexamined Patent Publication No. 2004-343244, a circuit formed as a conventional GaAs-HBT power amplifier module is disclosed.
FIGS. 7A and 7B show an example of a conventional GaAs-HBT power amplifier module. A portion of the module shown within the area surrounded by the broken line in FIG. 7A is formed on a GaAs chip. Portions other than the portion within the broken-line area are formed by chip parts and lines on the module circuit board.
The circuit shown in FIG. 7A has an RF signal input terminal (IN) and an RF signal output terminal (OUT). Tr1 and Tr2 denote an initial-stage heterojunction bipolar transistor (HBT) and a final-stage HBT, respectively. Vc1 and Vc2 denote collector power supply terminals for the transistors Tr1 and Tr2, respectively. Vcb denotes a power supply terminal of a bias circuit of Tr1 and Tr2. Vref denotes a reference voltage input terminal of the bias circuit. Rb1, Rb2, Rb12 and Rb22 denote resistors. C1 to C4, C21 to C23, Cd1, Cd2 and Cdb denote capacitors. L1 and L2 denote inductors. L11 and L21 to L23 denote lines having particular electrical lengths and functioning as inductors.
FIG. 7B shows a concrete example of a circuit configuration of the final-stage transistor Tr2 and a circuit portion for biasing the transistor Tr2. (The initial-stage transistor Tr1 and a circuit portion for biasing the transistor Tr1 have substantially the same circuit configuration.) Trb1 to Trb5 denote HBTs. Rbb1 to Rbb6 denote resistors. Vrefb denotes a reference voltage input terminal (a terminal to which a reference voltage is externally applied) of the bias circuit. Vcb denotes a collector power supply terminal for the bias circuit. Vbo denotes an output terminal of the bias circuit. This bias circuit operates so as to constantly maintain the idling current through Tr1 and Tr2 for the power amplifier (bias current when no RF signal input is supplied) under varying temperature.
For the normal operation of the bias circuit for the power amplifier shown in FIGS. 7A and 7B, a reference voltage Vref higher than twice the barrier voltage of the HBTs, typified by that in the two-stage cascaded section formed of Trb4 and Trb5 in a diode connection Tr or that in the two-stage cascaded section formed of the final-stage Tr2 and the Trb1, is required. That is, in a case where GaAs HBTs are used, a Vref of about 2.7 to 2.9 V is required from consideration of a barrier voltage of about 1.25 to 1.30 V and a voltage drop of about 0.2 to 0.3 V across the resistor Rbb1.
FIG. 8A shows an example of input/output characteristics of the power amplifier shown in FIGS. 7A and 7B. FIG. 8B shows an example of temperature dependence of idling current Icq2 through the final-stage Tr2 (operating current when no RF signal input is supplied). In a power amplifier for a portable telephone in which an idling current flows at all times like in CDMA use, the magnitude of the idling current largely influences the maximum talk time of the portable telephone. Therefore, circuit constants are designed so that the desired output power (about 26 to 28 dBm) is obtained at a low idling current value. The Trb1 forming the emitter follower is a device having the function of absorbing the difference between the low base current of the Tr2 when the idling current is low and the high base current of the Tr2 during high-output operation.
A concrete example of variation in Icq2 with respect to temperature in use of the bias circuit shown in FIG. 7B will be described. If Icq2 is about 25 mA at ordinary temperature, it is about 20 mA at a temperature in the range from a low temperature to 25° C., and is about 28 mA at a high temperature of 85° C. Thus, the circuit shown in FIG. 7B is capable of effectively limiting variation in Icq2 with respect to temperature and it is considered that there is no problem with the circuit in practice if Vref of about 2.8 to 2.9 is applied.
In the bias circuit shown in FIG. 7B, however, no idling current flows even at ordinary temperature when Vref is reduced to a value lower than about twice the barrier voltage of the HBTs, i.e., about 2.5 V. For this reason, the bias circuit shown in FIG. 7B cannot be used in practice without being modified. This tendency of the idling current to stop becomes stronger as the temperature decreases because the barrier voltage determined by device materials is increased as the temperature decreases. The temperature dependence of the barrier voltage ordinarily has a gradient of about −1 to −2 mV/° C.
With the conventional bias circuit for a GaAs-HBT power amplifier, there has been a problem that the idling current does not flow at ordinary or low temperature when the reference voltage Vref is reduced to a value lower than about twice the barrier voltage of the HBTs, as described above.

Bias circuit for power amplifier operated by a low external reference voltage


In a network having a first node and a second node, a method of verifying a lane routing between the first node and the second node. The first node and the second node operate according to a protocol in which: (1) a character is converted to code groups, (2) each code group has a corresponding lane, and (3) the code groups are communicated across the lanes in a parallel manner. A first set of code groups is transmitted from the first node. Preferably, the first set of code groups is different from a set of code groups predefined by the protocol. A second set of code groups is received at the second node. The second set of code groups corresponds to the first set of code groups. A determination is made whether the second set of code groups matches the first set of code groups. An identity of the first set of code groups can be preprogrammed within the second node. Preferably, the first set of code groups has a different code group in each lane. Optionally, the lane routing between the first node and the second node is corrected if the second set of code groups mismatches the first set of code groups.

1. Field of the Invention
The present invention relates in general to local area networks, and specifically to verification and correction of a 10GBASE-X lane routing between nodes.
2. Background Art
Ethernet protocol is a popular technology used to implement Local Area Networks (LANs), and was originally developed in the late 1970s. In 1985, Ethernet was adopted by the Standards Board of the Institute of Electrical and Electronics Engineers Standards Association (IEEE-SA) as IEEE Std 802.3® The IEEE-SA has approved an amendment for "Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation" to IEEE Std 802.3. The amended standard is designated IEEE Std 802.3ae™. The technology it supports is commonly referred to as "10 Gigabit Ethernet". IEEE Std 802.3ae introduces Clause 48 entitled "Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) Sublayer, Type 10GBASE-X." 10GBASE-X refers to a family of 10 Gb/s Physical Layer implementations.
To facilitate the use of high speed serial busses, 10GBASE-X expands upon the configuration set forth in Clause 36 of IEEE Std 802.3 entitled "Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) Sublayer, Type 1000BASE-X." 1000BASE-X refers to a family of 1000 Mb/s Physical Layer implementations. When transmitting from the Reconciliation Sublayer (RS), 1000BASE-X uses an 8B/10B Encoder in the PCS to map eight-bit Gigabit Media Independent Interface (GMII) characters to ten-bit code groups. Likewise, 10GBASE-X maps 10 Gigabit Media Independent Interface (XGMII) (or comparably formatted) characters to code groups. However, while GMII characters are eight bits in length, XGMII characters include 32 data bits, four control bits, and a clock. Therefore, whereas 1000BASE-X encodes GMII within a single lane configured to transmit at a rate of up to 125 million code groups per second, 10GBASE-X encodes XGMII to four lanes, each configured to transmit at a rate of up to 312.5 million code groups per second. 10GBASE-X designates its lanes as follows: lane 0, lane 1, lane 2, and lane 3.
Because a lane is coupled between an input port and an output port, the use of multiple lanes entails the use of multiple input ports and multiple output ports. This invites the possibility that lanes will be misrouted between ports. The possibility of lanes being misrouted diminishes the reliability of the IEEE Std 802.3ae protocol. What is needed is a method for verifying a 10GBASE-X lane routing between nodes. Preferably, such a method would also be capable of correcting the effects of misrouted lanes on communications between nodes.

Verification and correction of 10GBASE-X lane routing between nodes


A logical channel scheduling method including receiving, by the terminal device, control information sent by a network device, where the control information includes the logical channel scheduling indication information, and the logical channel scheduling indication information is at least one of an indication that a resource is used by a logical channel separately, an update indication of a prioritized bit rate (PBR) scheduled for the logical channel, and an update indication of a logical channel priority (LCP) scheduled for the logical channel; and obtaining, by the terminal device according to the logical channel scheduling indication information, an uplink scheduling resource used for sending logical channel data.

With rapid development of the fifth generation mobile communications technology (5G), mobile communications exerts great impact on people's life and work. Application scenarios of 5G usually include enhanced mobile broadband (eMBB), massive machine-type communications (mMTC), and ultra-reliable and low latency communications (URLLC). Because a URLLC service has a relatively high requirement on a service latency and service reliability, how to ensure a service requirement of another logical channel while ensuring a requirement of the URLLC service becomes a problem to be resolved urgently.
Before sending uplink data to a network device, an existing terminal device first needs to receive an uplink scheduling resource sent by the network device. Because a total quantity of uplink scheduling resources is determined, the terminal device needs to determine, according to a specific rule, a quantity of uplink scheduling resources that can be allocated to each logical channel. Usually, the terminal device determines, based on a logical channel configuration, the quantity of uplink scheduling resources that can be allocated to each logical channel. The logical channel configuration is a prioritized bit rate (PBR) or a logical channel priority (LCP) scheduled for a logical channel. After the terminal device allocates an uplink scheduling resource to each logical channel, if an uplink scheduling resource allocated to a specific logical channel cannot satisfy a requirement for scheduling a buffer on the logical channel, the terminal device needs to modify a logical channel configuration of the logical channel in a Radio Resource Control (RRC) configuration.
However, a process in which the terminal device modifies the logical channel configuration of the logical channel in the RRC configuration (this process is also referred to as an RRC reconfiguration process) is relatively complex, and is likely to cause overstocking to the buffer on the logical channel. In addition, modifying the logical channel configuration of the logical channel in the RRC reconfiguration process generates a relatively large amount of RRC signaling, affecting performance of the terminal device.

Logical channel scheduling method and system, and apparatus


An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

Typically, an SRAM cell includes a pair of inverters with the outputs of the inverters cross-coupled to form a flip-flop. The typical SRAM cell includes four transistors for storing data and two transistors for selection of a particular cell. Unlike dynamic random access memory (DRAM) cells, because of the flip-flop feedback effect, SRAM cells typically enable storage of static data even without refresh operations.
FIG. 1 is a circuit diagram of a conventional SRAM cell. Referring to FIG. 1, an SRAM cell includes a pair of access transistors AT1 and AT2, a pair of pull-up transistors PT1 and PT2, and a pair of driver transistors DT1 and DT2. The transistors PT1 and DT1 constitute a first inverter, and the transistors PT2 and DT2 constitute a second inverter. The first and second inverters are cross-coupled at nodes N1 and N2.
Source regions of the transistors DT1 and DT2 are coupled to a ground line Vss, and source regions of the transistors PT1 and PT2 are coupled to a power line Vdd. A drain region of the transistor AT1 is coupled to a first bit line BL1, and a drain region of the transistor AT2 is coupled to a second bit line BL2. Source regions of the transistors AT1 and AT2 are coupled to nodes N1 and N2, respectively. Gate electrodes of the transistors AT1 and AT2 are coupled to a common word line WL.
FIG. 2 is a top plan view of a conventional SRAM cell. As seen in FIG. 2, a field region 210 is formed at a substrate to define first and second active regions 200a and 200b. An N+ n-type active region is formed by heavily doping n-type impurities into a region denoted by "A", and a P+ p-type active region is formed by heavily doping p-type impurities into a region denoted by "B".
The word line 220 crosses over the active region 200a to form gates of the transistors AT1 and AT2. A first gate electrode 230a is disposed at right angles to the word line 220, and crosses over the active regions 200a and 200b to form gates of the transistors DT1 and PT1 and to connect the gates. A second gate electrode 230b is disposed in parallel with the first gate electrode 230a, that form gates of the transistors DT2 and PT2, and connects the gates.
The n-type impurity region N+ disposed between the transistors AT1 and DT1 becomes the node N1. The node N1 is coupled to a local interconnection line (not shown) through a contact CT2a. The local interconnection line is coupled to a drain of the transistor PT1 through a contact CT5a, and coupled to the gates of the transistors DT2 and PT2.
The n-type impurity region N+ disposed between the transistors AT2 and DT2 becomes the node N2. The node N2 is coupled to the local interconnection line (not shown) through a contact CT2b. The local interconnection line is coupled to a drain of the transistor PT2 through a contact CT5b, and coupled to the gates of the transistors DT1 and PT1.
The contacts CT1a and CT1b connect the drains of the transistors AT1 and AT2 to the separate bit lines (not shown), respectively. The contact CT4 connects the source of the transistors PT1 and PT2 to the power line Vdd (not shown), and the contact CT6 connects the source of the transistors DT1 and DT2 to a ground line Vss (not shown).
As semiconductor integrated circuits have become more highly integrated and operate at higher speed with lower power, extensive techniques for forming SOI devices have been investigated. SOI typically includes forming a single crystal silicon layer on an insulation layer to enable integration of devices disposed on the silicon layer.
FIG. 3 is a cross-sectional view of a conventional transistor formed on a SOI substrate. Referring to FIG. 3, a buried insulation layer 305 is formed on a base substrate 300 and a p-type lightly doped semiconductor layer is formed on the buried insulation layer 305. A field region 310 is formed at the semiconductor layer to define an active region. Source and drain regions 315 are provided in the semiconductor layer. A body 320 is provided between the source and drain regions 315. A gate electrode 330 is formed on the body 320, and a gate insulation layer 325 is provided between the gate electrode 330 and the body 320. Gate spacers 335 are formed on sidewalls of the gate electrode 330.
As compared with semiconductor devices fabricated using conventional bulk wafers, SOI devices fabricated using SOI wafers may have advantages for high-speed operations due to a low junction capacitance, reduction in soft errors caused by a α-particle in memory devices, and the like.
However, conventional SOI devices may suffer from floating body effects. Floating body effect may arise when the body of the device is not connected to a fixed electric potential, the body of the device has an electric potential based on its history. For example, when both source and drain regions of the transistor are at a high logic level, the body region is charged with equivalent voltages. Thereafter, when the source (or the drain) of the transistor changes quickly to a low logic level, the junction between the source (or the drain) and the body region is positively biased. As a result, a parasitic bipolar transistor may be formed that can lead to the generation of a leakage current.
FIGS. 4A and 4B illustrate that a bipolar transistor may operate to generate a leakage current in a MOS transistor.
Referring to FIG. 4A, even if an access transistor is in the off-state, a leakage current may be generated due to floating body effect. For example, when a high signal is stored in a node, the bit line voltage may be applied at the high level for a time of approximately 1 μs to 100 ms. Thereafter, the bit line voltage is changed to a low level for a short time of approximately 1 to 10 ns. In this case, a leakage current is generated at the node toward the bit line.
Referring to FIG. 4B, a graph represents leakage current as a function of operating voltage of the bit line utilizing a length of the gate electrode of 0.11 μm, an operating voltage of the bit line was applied at a high level for a time of approximately 10 ms. Thereafter, the operating voltage of the bit line was applied at a low level for a time of 5 ns. As a result, a leakage current was generated.

Methods for fabricating reduced floating body effect static random access memory cells


Methods and systems are provided for applying metering and rate-limiting in a virtual router environment and supporting a hierarchy of metering/rate-limiting contexts per packet flow. According to one embodiment, multiple first level metering options and multiple second level metering options associated with a hierarchy of metering levels are provided. A virtual routing engine receives packets associated with a first packet flow and packets associated with a second packet flow. The virtual routing engine performs a first type of metering of the first level metering options on the packets associated with the first packet flow using a first metering control block (MCB) and performs a second type of metering of the second level metering options on the packets associated with the first packet flow and the packets associated with the second flow using a second MCB.

1. Field
Embodiments of the present invention generally relate to data communications, and in particular, packet metering and rate limiting in a network processor environment, computer security, and in particular to computer network security.
2. Description of the Related Art
In a multi-client network, many subscribers and groups of subscribers are required to share a limited bandwidth of communication channels. Switches within the multi-client network must balance these shared bandwidth resources among multiple subscribers in a fair manner. Conventional routers attempt to solve this problem by performing packet metering/rate limiting on each physical interface of a routing or forwarding instance. Packet metering is conventionally used to limit the rate at which packets are placed on a network for transmission.
In the case of a multi-client network, for example, it may be desirable to meter and/or identify customers, or certain groups of customers, that are oversubscribing (e.g., using more than their allocated bandwidth). This may not be possible with conventional packet metering because metering is performed at a single physical interface. Another limitation of these conventional metering approaches is that they are not able to support packets that are associated with a variety of virtual interfaces, which may be employed by a virtual router.
Thus, there is a general need for an improved system and method for performing metering in a virtual router based network switch. There is also a general need for a system and method for performing metering in a multi-client network that distinguishes between clients and groups of clients. There is also a need for a system and method that supports a fair sharing of communication resources.

This patent is subject to a terminal disclaimer.

Hierarchical metering in a virtual router-based network switch


An integrated fail-silence and fail-operational control system includes a primary controller controlling features of devices while operating under non-fault operating conditions. A secondary controller includes a fail detector/decider module monitoring faults in the primary controller. The fail detector/decider module determines whether the fault in the primary controller is associated with a fail-silence requirement or a fail-operational requirement. If the fail detector/decider module determines the fault is a fail-silence requirement, then the fail detector/decider module actuates a shutdown command to the primary controller to shut down a feature affected by the fault where the feature becomes non-operational. If the fail detector/decider module determines that the feature associated with the fault is a fail-operational requirement, then the fail detector/decider module signals the primary controller to relinquish controls of the feature to the secondary controller. The secondary controller functions as a high assurance system for controlling the feature in a fail-operational mode.

An embodiment relates to fault tolerant control systems.
Systems which provide safety functions typically utilize redundant controllers to ensure safety by shutting down functions that have experienced a fault or failure. Such systems are known as fail-silent systems. If a fault is detected, controls are shut down for the feature and the feature will no longer be operable in the system.
Some systems try to implement control systems utilizing a fail-operational system where additional controllers are used to ensure that a safe operation can be continued for a duration of time, such as dual duplex controllers. If a first controller fails and falls silent, a second controller will be activated and all actuators will switch over to rely on requests from the second controller. The issue with duplex designs is that due to fact that the controllers are essentially identical, they carry the same defects, particularly software defects. Since the software is identical, both controllers will inherently have the same issues if a software related defect occurs. As a result, in a system that uses symmetrical implementation of controllers, which are essentially exact copies of each function, such systems provide little assistance with respect to software faults.
Other types of systems that utilize non-symmetrical implementation of controllers may avoid duplicative hardware and software faults; however, utilizing a second non-symmetric controller that includes the necessary software and hardware for controlling all features controlled by the first non-symmetrical controller is costly.

Architecture for scalable fault tolerance in integrated fail-silent and fail-operational systems


The present disclosure relates to a novel dyeing composition for dyeing human keratinous fibers, such as hair, comprising at least one dicationic diazo dye of formula (I):[W1—N═N—W2—W3—(W4—W5)p-]2-L   Formula (I)as well as the process for dyeing hair using same. Certain compounds of formula (I) are also disclosed herein.

It is known practice to dye keratin fibers, and in particular human hair, with dye compositions containing oxidation dye precursors, which are generally known as oxidation bases, such as ortho- or para-phenylenediamines, ortho- or para-aminophenols and heterocyclic compounds. These oxidation bases are colorless or weakly colored compounds, which, when combined with oxidizing products, give rise to colored compounds by a process of oxidative condensation.
It is also known that the shades obtained with these oxidation bases may be varied by combining them with couplers or coloration modifiers, the latter agents being chosen especially from aromatic meta-diamines, meta-aminophenols, meta-diphenols and certain heterocyclic compounds such as indole compounds.
The variety of molecules used as oxidation bases and couplers allows a wide range of colors to be obtained.
This process of oxidation dyeing consists in applying to the keratin fibers oxidation bases or a mixture of oxidation bases and of couplers with an oxidizing agent, for example aqueous hydrogen peroxide solution, leaving the application on the fibers, and then rinsing the fibers. The colorations resulting therefrom are permanent, strong and fast with respect to external agents, especially light, bad weather, washing, perspiration and rubbing. Generally applied at basic pH, dyeing and simultaneous lightening of the fiber may be obtained, which is reflected in practice by the possibility of obtaining a final coloration that is lighter than the original color. In addition, lightening of the fiber may have the advantageous effect of producing a unified color in the case of gray hair, and, in the case of naturally pigmented hair, of bringing out the color, i.e. of making it more visible.
It is also known practice to dye keratin fibers by direct dyeing. The process conventionally used in direct dyeing consists in applying to the keratin fibers direct dyes, which are colored and coloring molecules that have affinity for the fibers, leaving the dyes on the fibers, and then rinsing the fibers.
It is known practice, for example, to use direct dyes belonging to the nitrobenzene, anthraquinone, nitropyridine, azo, indoamine, azine or triarylmethane class.
The colorations resulting therefrom are particularly chromatic colorations, that are temporary or semi-permanent since the nature of the interactions binding the direct dyes to the keratin fiber, and their desorption from the surface and/or the core of the fiber are responsible for their poor dyeing power and their poor resistance to washing or to perspiration. These direct dyes are also generally light-sensitive due to the poor resistance of the chromophore with respect to photochemical attack, leading over time to fading of the coloration of the hair. In addition, their light sensitivity is dependent on their uniform distribution or distribution as aggregates in the keratin fiber.
It is known practice to use direct dyes in combination with oxidizing agents. However, direct dyes are generally sensitive to the action of oxidizing agents such as aqueous hydrogen peroxide solution, and reducing agents such as sodium bisulfite, which makes it generally difficult to use them in compositions for lightening direct dyeing based on aqueous hydrogen peroxide solution and based on a basifying agent or in oxidation dye compositions in combination with precursors such as oxidation bases or couplers.
For example, it has been proposed in patent applications FR-1 584 965 and JP-062 711 435 to dye the hair with dye compositions based on nitro direct dyes and/or dispersed azo dyes and on ammoniacal aqueous hydrogen peroxide solution, by applying to the hair a mixture of said dyes and of said oxidizing agent, prepared just before use. However, the colorations obtained are found to have insufficient resistance and disappear on shampooing, making the lightening of the hair fiber show through. Such a coloration becomes unattractive by changing over time.
It has also been proposed in patent applications JP-53 95693 and JP-55 022 638 to dye the hair with compositions based on cationic direct dyes of oxazine type and on ammoniacal aqueous hydrogen peroxide solution, by applying to the hair ammoniacal aqueous hydrogen peroxide solution in a first step, followed by a composition based on the oxazine direct dye in a second step. This coloration is unsatisfactory because it requires a process that is made too slow by the leave-in times of the two successive steps. If, besides that, an extemporaneous mixture of the oxazine direct dye with ammoniacal aqueous hydrogen peroxide solution is applied to the hair, the hair fiber is not colored or at most, a virtually nonexistent coloration is obtained.
More recently, patent application FR 2 741 798 has disclosed dye compositions containing direct dyes comprising at least one quaternized nitrogen atom of the azo or azomethine type, said compositions being for extemporaneous mixing at basic pH with an oxidizing composition. These compositions make it possible to obtain uniform, resistant and bright colorations with glints. However, they do not allow keratin fibers to be dyed as strongly as with oxidation dye compositions.
There is thus a real need to find chromatic direct dyes that allow keratin fibers to be dyed as strongly as with oxidation dyes, which are just as stable as oxidation dyes to light, which are also fast with respect to bad weather, washing and perspiration, and which are also stable enough in the presence of oxidizing and reducing agents to be able simultaneously to obtain lightening of the fiber either by using lightening direct compositions containing them, or by using oxidation dye compositions containing them. There is also a real need to find direct dyes that allow keratin fibers to be dyed to obtain a very wide range of colors, in particular very chromatic colors, not forgetting the "fundamental" shades, for instance, blacks and browns.

Dyeing composition for keratinous fibers comprising a dicationic diazo dye


A method for improving real-time video communications using a Foveation-based unequal error protection scheme (UEP) and error resilience. In a preferred embodiment of the present invention, a real time processing module partitions a video image into at least two data bit stream signals based on a directional pointing device or a pattern filter definition of “areas of importance.” These different data bit stream signals are then processed via different algorithms based on the importance of correcting errors in the data signals. The data is then transmitted. After reception at a receiving device, the data signals are regenerated and corrected to their original form.

Video data communications can have high data error rates, particularly in mobile applications where carrier signals tend to randomly fade for several seconds due to transmitter/receiver motion acting in conjunction with signal path physical obstructions. During periods of such high data error rates, video quality can be severely degraded due to a reduction in data throughput over a finite transmission time period. Such throughput reduction results when normal data transmission time is consumed by error-correction processing activities, such as repeatedly re-transmitting a damaged data packet or processing data with time-consuming error-correction algorithms at both the transmitter and receiver ends of a communications system.
To alleviate time lost to such error-correction, various data compression techniques can be employed to reduce the size of transmitted data packets. Such techniques take advantage of the fact that smaller data packets result in smaller transmission time slots being required for re-transmission of damaged data blocks and/or enable the use of less sophisticated, and thus less time consuming, error-correction algorithms. One such data reduction technique that has particular application to video images relies on the fact that the human eye is foveated. Foveation is characterized by exponentially decreasing image resolution away from the focal point of the eye resulting in being able to see the fine details only in the area of focus.
Thus, due to this non-uniform resolution processing of the human eye, high frequency data components can be removed from areas of lesser importance without a corresponding loss of visual quality. This high frequency elimination provides an attendant reduction in the quantity of data needed for the transmission of a quality video image. Such foveated video data compression techniques have been successfully used at very low bit rates for such data communications. See S. Lee et al, "Foveated Video Quality Assessment", IEEE Trans. Multimedia and S. Lee, et al, "Foveated video compression with optimal rate control", IEEE Trans. Image Processing, both submitted, but not yet published.
In another application using foveation, U.S. Pat. No. 4,692,806 to Anderson, et al, teaches that data transmissions of a "busy" video image can be improved by performing successive processing passes over an image. A first pass captures a data block for an overall general image area, and then successive passes capture a finer area of detail or selective images of importance. Control of the "selected area" is accomplished by pointing/aiming a video camera to the points of importance based on feedback from a remote viewing screen. As is known in the art, there are many techniques for such camera manipulation to a targeted area of an image, such as using eye-tracking devices, a computer mouse, and/or a joystick. Once a targeted area is selected, detailed data processing is made only on the selected area.
However, a significant disadvantage of this technique is that it does not correct for a data transmission exhibiting a high bit error rate, such as those characteristic of the mobile applications cited above. Although such high data error rates will negatively impact both the selected area and the background area equally, the lack of extra error correction/resilience for the important "selected area" leads to significant perceptual degradation in the received video image.

Foveation-based error resilience algorithm


The present invention provides a method for producing double-card anti-counterfeit marks with interlock protection based on the technique which combines nuclear technology with computer-generated hologram (CGH) technology and inspecting apparatus for the mark. The invention relates to the technical field of optical information processing in physics. The technical feature of the invention is to insert potential images R,T and matched potential images R',T' in the anti-counterfeit identification marks and in the inspecting identification marks respectively by means of charged particle track image in sampling coincidence with CGH. When R coincides with R', a certain message of genuineness for an identification mark will be shown, and when T coincides with T', different specific information in thousands of ways appears to prove the genuineness of the protected objects. Because of the microscopic characteristics of nuclear tracks and the distribution characteristics of the phase hologram on the frequency spectrum plane, the potential images R,T,R',T', as the information carriers, can't be duplicated and must be coincided respectively, so as to prevent the genuine anti-counterfeit marks from the illegal imitation.

A lot of anti-counterfeit technologies such as techniques based on temperature alternation, fluorescence and phosphorescence, implicit metal, laser hologram and etc. have been developed for checking bank-note, paper money, bill and trademarks. On Oct. 16, 1991, a Chinese patent for invention (application No.90105079.2) was disclosed, in which a method for producing a potential image in document was introduced. The potential image is inserted on a certain place of bank note or document, in case of necessity the potential image can be observed for identifying the genuineness. A method for producing a special kind of anti-counterfeit paper is disclosed in another Chinese patent published on Sep. 25, 1991 with application No.91102676. Color fabric thread is dispersed and processed first and then added into the paper pulp-making system for producing paper material contained color fabric thread. Through a paper machine, a kind of paper with uniform-distributed color fabric thread on its surface is manufactured. The feature of presenting clear and uniform color fabric thread differs from that of ordinary printing paper. The anti-counterfeit purpose can be achieved by using such kind of paper.
In recent years a kind of laser holographic method for anti-counterfeit identification mark has been developed in trademark protection. The technical processes for photography, plate making, printing are described in the book "Practical Hologram Photography" published by the Publishing House of Beijing Institute of Posts and Telecommunications. A Chinese patent published on Sep. 27, 1989 with application No.87205319 has also described a laser hologram method for anti-counterfeit identification. The feature is at the first step an embossed white light reconstructed hologram is taken by using photoresist plate as a recording medium and then the embossed image is transferred from the photoresist plate to a metallic plate by electric casting. Finally, a moulded master mask is obtained. The embossed hologram is duplicated on a piece of thermoplastic paper with aluminium film by die pressing for manufacturing the laser hologram anti-counterfeit identification mark. For its multicoloured diffraction effects, three-dimensional feeling, and difficulty to be copied, the rainbow hologram used to be in vogue for a time and considered as the most effective way for anti-counterfeit identification. However, infringers succeeded in imitating the above-mentioned laser hologram anti-counterfeit identification marks and used them as real certificate of their false products, causing heavy losses to manufacturees of famous trademark products and consumers. In a Chinese patent application No. 87205139 published on Nov. 16, 1988, and in a Canadian patent application with publication date Nov. 9, 1984 and filing No. 86132651 entitled "An apparatus for identifying real product by using optic interference and its production method", furthermore, in a German patent application No. 93168673 published on Feb. 29, 1992 entitled "Safe original document of credit card and ID card", technical methods have been introduced by which a secured bar code mark or a difficult-to-copy safety layer is added to the anti-counterfeit identification marks for proving the authenticity of bank notes, tickets, documents and trademarks. In spite of the complexily of the techniques, the counterfeiters spare no expense to acquire and master them. Although the counterfeiters are not able to make the fake identification marks exactly as the real ones, the consumers can not distinguish the authentics from the false for the unspecified information as fringes, fluorescent, magnetic granule and etc. because of their limited identifying ability. In order to achieve the exact anticounterfeit goal, identification marks should possess the following features: 1. The self-protecting function, e.g. to prove the authenticity of themselves before testifying the protected objects; 2. The impossibility to be copied; 3. The identifying capability under their various changeable circumstances; 4. The simple and definite method for checking their authenticity; 5. The one-off feasibility and reasonable cost for mass production.
The object of the invention is to provide a method for producing a double-card track laser hologram anti-counterfeit identification mark and its inspecting apparatus. By using nuclear track, laser speckles and optical information processing technique, the double-card, double-protection technical scheme for anti-counterfeit identification mark is carried out, namely one card for proving the reality of the mark itself and the other one for proving the reality of the object to be protected by the mark, so as to get rid of the fake disturbance from imitators.

Method for producing laser hologram anti-counterfeit mark with identifying card and inspecting card and inspecting apparatus for the mark


An asymmetrical network is disclosed for coupling customer-premises Internet hosts such as personal computers to the Internet. The head end of a CATV system has a high-bandwidth connection to the Internet. The CATV system supports a plurality of concurrent channels to which an RF modem is capable of tuning. The RE modem is capable of receiving information from the head end that specifies the channel to which the RF modem should tune. Once tuned to the specified channel, the RF modem is capable of utilizing the CATV system for carrying high-speed data traffic. The high-speed data traffic can support Internet access using the Internet Protocol (IP).

1. Field of the Invention
The invention concerns data networks generally and more particularly concerns data networks that employ protocols belonging to the TCP/IP protocol suite and data networks that are asymmetric, that is, data networks in which there is more capacity to move data in one direction than there is in the reverse direction.
2. Description of the Prior Art
In the not-too-distant past, images could be processed and displayed only by large, special-purpose computer systems. Owners of lower-cost and less-powerful computers such as personal computers had to content themselves with character-based displays. The cost of memory has dropped so quickly and the power of microprocessors has increased so greatly in recent years, however, that modem personal computers are completely capable of processing and displaying images. Indeed, modern graphical user interfaces depend to a large extent on this capability.
Frustratingly enough for users of personal computers, the old problems with images have returned in another area, namely network computing. In network computing, the personal computer or work station is connected to a network and is able to use the network to fetch the data it is processing from remote locations. The most recent development in network computing is the Internet, a world-wide logical network which permits anyone who has access to the Internet to interactively fetch data including images from just about anywhere in the world. For example, using the Internet, it is possible to fetch pictures of the latest restoration projects in Florence, Italy from that city's home page on the World Wide Web.
The main drawback to interactively fetching data on the Internet is the length of time it takes to retrieve and display images. The problem is so serious that many people set up the program they use to access the Internet so that it does not fetch images. Doing this restricts the user to character data, but greatly decreases the time it takes to access information. The bottleneck in retrieving images from the Internet is not the personal computer, but rather the lack of capacity or bandwidth of the networks over which the images must be fetched. One part of the network where bandwidth is particularly restricted is the analog telephone line that connects most PC users to the Internet. It has been known for years that the bandwidth of the telephone system can be increased by replacing the analog system with a digital system, but all of the known techniques for doing this require extensive modification of the telephone system.
A great many homes do in fact have a high bandwidth connection, namely that provided by cable television. The problem with this connection is that it is one way. A PC may receive data via a home's CATV cable, but it cannot use the cable to send data. Again, ways of making the CATV system bidirectional have been known for years. For example, in the early 1980s, Scientific-Atlanta, Inc. introduced and marketed a product known as the Model 6404 Broadband Data Modem for use with bidirectional CATV systems. Scientific-Atlanta, Inc. has also filed several patents, which describe bidirectional CATV systems including: U.S. Pat. No. 5,790,806 filed on Apr. 3, 1996, entitled Cable Data Network Architecture; U.S. Pat. No. 5,966,163 filed on Oct. 16, 1996, entitled Providing Constant Bit Rate Upstream Data Transport in a Two-Way Cable System by Scheduling Preemptive Grants for Upstream Data Slots Using Selected Fields of a Plurality of Grant Fields; a continuation-in-part of U.S. Pat. Nos. 5,790,806 and 5,966,163 filed on Mar. 14, 1997 that issued as U.S. Pat. No. 6,230,203, entitled System and Method for Providing Statistics for Flexible Billing in a Cable Environment; and a continuation of U.S. Pat. No. 5,966,163 filed on Apr. 19, 1999 that issued as U.S. Pat. No. 6,467,091, entitled Constant Bit Rate Transport in a Contention Based Medium Access Control. As with the telephone systems, the problem here is not the technology, but the fact that its introduction requires extensive modification of most existing CATV systems.
Given that many homes have a CATV cable and virtually all homes have an analog telephone line, systems have been proposed in which the CATV cable is used to send data from the Internet to the PC and the telephone line used to return data from the PC to the Internet. These systems take advantage of the fact that by far the most common pattern of interaction between users and networks is for the user to retrieve a large amount of data over the network, for example an image of a restored art work from Florence, examine the image, and then send a few keystrokes over the network. With this kind of interaction, far less bandwidth is needed in the channel that is used to return the keystrokes than in the channel that is used to fetch the image.
An example of such a system is the one disclosed in Moura et al., Asymmetric Hybrid Access System and Method, U.S. Pat. No. 5,586,121, issued Dec. 17, 1996, and in Moura et al., Remote Link Adapter for use in TV Broadcast Data Transmission System, U.S. Pat. No. 5,347,304, issued Sep. 13, 1994. In this system, the head end of a cable system has high bandwidth access to the Internet or to other networks and access via CATV cables and the telephone system to households or businesses with PCs. Data received from these networks is sent to PCs connected to the cable system's cables and responses from the PCs are collected via the telephone system and sent to the network. In the home or business, the PC is connected either directly or via a local area network to a device which includes both a radio frequency modem and a standard analog telephone modem. The radio frequency modem is connected to the CATV cable. It receives and decodes the data sent on the CATV cable and provides it to the PC. The telephone modem is connected to a standard telephone line. It receives data from the PC and sends it to the CATV head end, which in turn forwards it to the Internet or other networks.
While systems such as the one disclosed in the Moura references do provide a solution to the bandwidth problem, they have a number of deficiencies, particularly when used in the context of the Internet. Among the deficiencies are the following:
The system of Moura wastes Internet Protocol (IP) addresses for the computers attached to the modem. IP addresses are in short supply. In the system of Moura, however, IP addresses are statically assigned to the PCs and are consequently not available for reuse when a PC is idle or not engaged in an activity which involves network access.
From the point of view of the Internet, the system of Moura is a link level system, that is, the components of the system of Moura do not themselves have IP addresses and cannot themselves execute IP protocols. In particular, IP routing is not used within the system of Moura. One difficulty arising from this situation is that IP routing is centralized in the IP router that connects the head end to the Internet; another is that the modem in the system of Moura cannot function as an IP router.
In Moura, the telephone connection to the modem is used solely to transfer data from the PC and modem to the head end. All data received by the PC and modem is sent via the CATV cable. Consequently, when the CATV system fails, the PC is left without a connection by which it can receive data. This situation is made even less desirable by the fact that CATV systems are far more likely to fail than the telephone system.
The CATV channel to which the modem of Moura responds is statically assigned to a given modem, thereby rendering the channel unavailable for use by other modems when the PC connected to the given modem is idle or is not engaged in an activity which involves network access.
It is an object of the system disclosed herein to overcome the preceding and other deficiencies of systems like that of Moura.

Router for use with a link that has a set of concurrent channels