An acquiring unit configured to acquire association information that indicates a relationship between a profile, which is a setting information group containing a plurality of pieces of setting information, and dewarp information on a fisheye image, and a associating unit configured to associate a video source configuration, a video encoder configuration, and a PTZ configuration to the profile based on the association information acquired by the acquiring unit are provided.

Hitherto, in a surveillance camera that sends a captured image to a client apparatus, a command group for instructing the surveillance camera to change settings from an external apparatus or to start distributing images from an external apparatus is installed. As an example of such a command group, a command group defined by the standard developed by open network video interface forum (ONVIF) is known.
In ONVIF, the following items are set as the settings (configurations) of the surveillance camera. In other words, a video source setting (video source configuration) is defined. The video source setting (video source configuration) contains dewarp information and a resolution. The dewarp information determines the presence or absence and type of image distortion correction and image clipping range. The resolution is that a sensor is able to output. A video encoder setting (video encoder configuration) is defined. The video encoder setting (video encoder configuration) contains an encode type for encoding an image, a resolution, and the like. A PTZ setting (PTZ configuration) is defined. The PTZ setting (PTZ configuration) contains, for example, whether pan, tilt, or zoom is supported or not.
These configurations are mapped to (associated with) a profile to be designated for control over the surveillance camera, and the surveillance camera provides video distribution, PTZ control, or the like, with the details of the configurations mapped to the profile. A profile is a collection of the above-described settings and is used, for example, when a client apparatus receives a video stream from a surveillance camera. For example, a client apparatus designates the settings contained in the profile and instructs the surveillance camera to send a video stream based on the settings. FIG. 1 is a view that illustrates an example in which configurations are mapped to a profile in compliance with ONVIF. In this way, one of each is selected from among one or more video source configurations, video encoder configurations, and PTZ configurations and is mapped to a profile.
There are a method in which a surveillance camera prepares a profile to which configurations have been already mapped and a method in which a client apparatus acquires configurations from a surveillance camera and maps the configurations to a profile. When a client apparatus maps configurations to a profile, the client apparatus maps the configurations in consideration of dependency among the configurations.
For example, in the case of a camera that is an omnidirectional camera capable of generating a plurality of images, such as a fisheye image, a panoramic image, and an image partially clipped from a fisheye image, the dewarp information of an image is designated in a video source configuration.
When a fisheye image is distributed from a surveillance camera, a video source configuration compatible with the fisheye image is mapped to a profile. At this time, a video encoder configuration having a resolution that can be set for a fisheye image is set.
When PTZ of a fisheye image cannot be performed, a PTZ configuration cannot be mapped to a profile.
In this way, depending on the dewarp information of an image to be distributed, a video source configuration, a video encoder configuration, and a PTZ configuration, compatible with the dewarp information, are, for example, mapped to a profile, and a surveillance camera is not able to provide video distribution or PTZ control unless those settings are mapped properly.
Japanese Patent Laid-Open No. 2014-107590 describes an image capturing apparatus that adjusts setting values between a video source configuration and a video encoder configuration.

Image capturing apparatus, control method, and storage medium


A phase adjustment circuit includes: a local frequency band phase shifter that adjusts a phase of a signal in a local signal frequency band and that outputs the adjusted signal; a frequency-converting mixer that receives the adjusted signal and another signal different from the adjusted signal, and that mixes the adjusted signal with the other signal; and a buffer amplifier that is provided between the local frequency band phase shifter and the frequency-converting mixer, and that is capable of amplifying an input power that is to be input to the frequency-converting mixer so that the input power is up to be in an input power range in which an input-output characteristic of power of the frequency-converting mixer is out of a linear region.

With the sudden increase in mobile traffic in recent years, there is a desire for higher precision of beam control in array antenna devices on which many antenna elements are mounted, in order to realize millimeter-band communication with strong directionality for the purpose of high-capacity communication. In order to realize such high-precision beam control, it is important to adjust, with high precision, the amplitudes and phases of signals transmitted from the respective antenna elements.
Patent Document 1 describes technology of adjusting the phase differences between local signals.

Phase adjustment circuit and array antenna device


A continuously operable portable icemaker charged with an ammonia solution and pressured to about 450 pounds per square inch with hydrogen and powered with a source of heat to cause percolation of the ammonia solution acts to freeze water charged into a removable refillable cylindrical vessel.

Improvements over the original patent include:
use of higher pressure to minimize exchanger size: PA1 use of aluminum with a corrosion inhibitor to minimize weight; PA1 formation of ice in an easily removable cylindrical shape around a central evaporator tube or freezing component; PA1 simplification of the icemaker components; and in a preferred embodiment PA1 arrangement of the icemaker components to make maximum use of the chimney effect to maximize air flow to improve heat transfer.
This patent covers both a free standing unit and a unit made with suitable hooks to allow the unit to be transported and held in the proper upright position by hooking to a side of a normal insulated cooler chest.
The ice is formed from water poured into a container with an inner central cylindrical opening that fits closer than one sixteenth of an inch around the cylindrical evaporator tube or evaporator.


A method, apparatus, and system for providing a standard, generic contract between an application server and a message provider which allows the message provider to deliver messages to message endpoints (each of which is associated with a corresponding message application) residing in the application server is disclosed. By generic, it is meant that the contract is independent of the specific messaging style, messaging semantics and messaging infrastructure used to deliver messages. In this way, the contract also serves as the standard message provider pluggability contract that allows any message provider to be plugged into any application server via an associated resource adapter.

1. Field of Invention
The invention relates generally to computer systems. More particularly, methods and apparatus for providing a generic contract between an application server and a message provider which allows the message provider to deliver messages to message endpoints (MDBs) residing in the application server independent of the specific messaging style, messaging semantics and messaging infrastructure used to deliver messages. Such a contract also serves as the standard message provider pluggability contract that allows any message provider to be plugged into any application server via a resource adapter.
2. Description of Relevant Art
In modern Enterprise Information Systems (EIS) is formed to include a number of EIS resources. An EIS resource provides EIS-specific functionality to its clients examples of which include a record or set of records in a database system, a business object in an ERP system, and a transaction program in a transaction processing system. Generally, an EIS is formed of a number of interconnected personal computers, workstations, mainframes, and the like along with other devices such as large mass storage subsystems, network interfaces, as well as interfaces to the public telephony systems are interconnected providing an integrated environment in which information may be shared among the various users. Typically, users may be performing a variety of operations, including order receipt, manufacturing, shipping, billing, inventory control, and other operations in which sharing of data on a real time basis provides a significant advantage over, for example, maintaining separate records and attempting to reconcile them later.
The Java 2 Platform, Enterprise Edition (J2EE) provides containers for client applications, web components (based on servlets, Java Server Pages) and Enterprise JavaBeans components. These containers provide deployment and runtime support for application components as well as an integrated view of the services provided by underlying application server for the associated application components. Containers can run on existing systems such as, for example, web servers (for the web containers) application servers, TP monitors, and database systems for EJB containers enabling EISs to leverage both the advantages of their existing systems and those of J2EE. For example, EISs can write (or rewrite) new applications using J2EE capabilities and can also encapsulate parts of existing applications in Enterprise Java Beans (EJB), Message Driven Beans (MDB), Java Server Pages (JSP) or Servlets. IN addition, EIS applications access functions and data associated with applications running on Enterprise Information Systems (EIS).
The J2EE Connector architecture defines standard contracts which allows bi-directional connectivity between enterprise applications and EISs. An architecture for integration of J2EE servers with EISs is referred to as a connector architecture. There are two parts to the connector architecture: an EIS vendor-provided resource adapter and an application server that allows this resource adapter to plug in. The contracts support bi-directional communication between the application server and the resource adapter. (It is well to note that a resource adapter is a system-level software driver that is used by a Java application to connect to an EIS. The resource adapter plugs into an application server and provides connectivity between the EIS, the application server, and the enterprise application. The J2EE Connector architecture defines a standard architecture for connecting the Java 2 Platform, Enterprise Edition (J2EE) platform to heterogeneous EISs.)
Accordingly, the connector architecture defines a set of scalable, secure, and transactional mechanisms (i.e., a set of contracts) such as transactions, security, connection management, that a resource adapter has to support to plug in to an application server that enable the integration of EISs with application servers and enterprise applications. The connector architecture also defines a Common Client Interface (CCI) for EIS access. The CCI defines a client API for interacting with heterogeneous EISs. The connector architecture enables an EIS vendor to provide a standard resource adapter for its EIS. In this way, an application server vendor extends its system once to support the connector architecture and is then assured of a seamless connectivity to multiple EISs. Likewise, an EIS vendor provides one standard resource adapter and it has the capability to plug in to any application server that supports the connector architecture.
Asynchronous message delivery or event notification is a widely used application communication paradigm. Some of the characteristics of asynchronous message-based communication paradigm include a message producer is not directly aware of message consumers (there could be one or more consumers interested in the message). Message delivery is solicited, that is, a message consumer has to express interest in receiving messages. Message producer is not directly aware of message consumers and consequently it produces messages of a constant type Messaging infrastructure stores and routes messages reliably (depending on QoS) to interested messsage consumers. Inherently, the interaction is loosely coupled. The message producer and the consumer do not share any execution context. The message producer generally is not interested in the outcome of message processing by consumers. The message delivery always involves a message routing infrastructure, which offers varying QoS for storing (persistence) and routing messages reliably.
J2EE applications could use two different approaches to interact with a message provider. One approach relies upon the direct use specific messaging APIs to send and synchronously receive messages. Alternatively, any message provider could provide a connector resource adapter which supplies connection objects for use by applications to send and synchronously receive messages using the specific messaging API without requiring any additional contracts (it could use MDBs to asynchronously receive messages via a message provider).
While the above approaches allow a J2EE application to send and receive messages, there is no standard system-level contract to plug-in message providers to an application server, and to deliver messages to message endpoints (MDBs) residing in the application server. Without a standard pluggability contract, an application server (of which there may be m) would have to use special contracts to interact with various message providers (of which there may be n), and a message provider has to do the same to interact with different application servers representing an mxn type problem.
Therefore, there is a need for a standard, generic contract between an application server and a message provider which allows the message provider to deliver messages to message endpoints (MDBs) residing in the application server independent of the specific messaging style, messaging semantics and messaging infrastructure used to deliver messages. Such a contract also serves as the standard message provider pluggability contract which allows any message provider to be plugged into any application server via a resource adapter.

Architecture for plugging messaging systems into an application server


A memory driving apparatus comprises instruction means and which instruction means instructs whether a reference voltage generating portion should be activated at all times or it should be activated only when data is read out.

1. Field of the Invention
The present invention relates to a memory driving apparatus for driving a memory such as a ROM.
2. Description of the Prior Art
FIG. 2 is a block diagram showing an example of structure of a prior art memory driving apparatus. Referring to FIG. 2, S1 denotes a signal for bus controlling output from the central portion constituted of a central processing unit (CPU) and the like, not shown, of the memory driving apparatus; 1 denotes a signal generating portion for generating a chip select signal CS and a pre-charge signal PR for controlling operations of the memory driving apparatus; 7 denotes a reference voltage generating portion for generating reference voltages VP and VN for reading out a signal retained in a read only memory (ROM) 10; 8 denotes a sense amplifier for outputting a signal corresponding to the logical level written in each ROM cell of the ROM 10; 9 denotes a selector for selecting a bit line among bit lines B0-B3 of the ROM 10; 10 denotes the ROM as the object out of which the present memory driving apparatus reads data; CS denotes a chip select signal output from the signal generating portion 1; PR denotes a pre-charge signal output from the signal generating portion 1; VP and VN denote reference voltages output from the reference voltage generating portion 7; N2 denotes a node as the output terminal of the sense amplifier 8; S denotes a node as the junction point between the sense amplifier 8 and the selector 9; A0 and A1 denote address signals for selecting a bit line among the bit lines B0-B3; A2 and A3 denote address signals for selecting a word line among word lines of the ROM 10; B0-B3 denote the bit lines of the ROM 10.
FIG. 3 is a circuit diagram showing concrete configurations of the reference voltage generating portion 7, the sense amplifier 8, the selector 9, and the ROM 10 of the memory driving apparatus shown in FIG. 2.
First, the concrete configuration of the reference voltage generating portion 7 will be described. Reference numeral 6 denotes a source voltage input terminal to which a source voltage of 5V is applied; T5 and T9 denote a P-channel transistor, respectively, for generating the reference voltage VP; T6, T7, and T8 denote an N-channel transistor, respectively, for similarly generating the reference voltage VP; N4 denotes a node as the point where the drain and the gate of the transistor T5, the drain of the transistor T9, and the drain of the transistor T6 join; T10 denotes a P-channel transistor for generating the reference voltage VN; 16 denotes an inverter for inverting the chip select signal CS and supplying it to the gate of the transistor T10; T11-T16 denote an N-channel transistor, respectively, for generating the reference voltage VN. The transistor T11 has the same channel length and four times as large channel width as the transistor T6 has, while the transistor T12 has the same channel length and four times as large channel width as the transistor T7 has. Reference character N3 denotes a node as the point where the drain of the transistor T10, the drain and the gate of the transistor T11, and the gate of the transistor T6 join. The transistors T10-T16 function as the voltage source for supplying the gate voltage of the transistor T6.
Now, the concrete configuration of the sense amplifier 8 will be described.
Reference character T1 denotes a P-channel transistor, which functions as the current source for supplying current to the node N1; T3 denotes an N-channel transistor, which acts as a grounded-gate amplifier and has the same channel length and the same channel width as the transistor T6 has. Reference character T4 denotes a P-channel transistor for supplying current to the bit lines B0-B3; I4 denotes an inverter for inverting the pre-charge signal PR and supplying it to the gate of the transistor T4; I5 denotes an inverter functioning as a buffer amplifier at the output stage; N1 denotes a node as the point where the drain of the transistor T1, the drain of the transistor T3, the drain of the transistor T4, and the input terminal of the inverter 15 join.
Next, the concrete configuration of the selector 9 will be described.
Reference character I10 denotes an inverter for inverting the address signal A1; I11 denotes an inverter for inverting the address signal A0; G1-G4 denote a NAND gate, respectively, which functions as an address decoder in the aggregate; I6, I7, I8, and I9 denote an inverter, respectively, for inverting the output signals of the NAND gates G1, G2, G3, and G4, respectively, and supplying the inverted signals to the gates of the transistors T17, T18, T19, and T20, respectively; T17, T18, T19, and T20 denote an N-channel transistor, respectively, for breaking and making the connections of the bit lines B0, B1, B2, and B3 with the node S; respectively; T21, T22, T23, and T24 denote an N-channel transistor, respectively, for grounding the bit lines B0, B1, B2, and B3, respectively. The transistors T17-T20 have an equal channel length and a channel width, respectively, to each other, and the channel length and the channel width are same as those of the transistor T7 of the reference voltage generating portion 7. The transistors T21-T24 also have an equal channel length and a channel width, respectively, to each other.
Now, the concrete configuration of the ROM 10 will be described.
Reference character I12 denotes an inverter for inverting the address signal A3; I13 denotes an inverter for inverting the address signal A2; G5-G8 denote an AND gate, respectively, which functions as an address decoder in the aggregate; W3, W2, W1, and W0 denote a word line, respectively, which is connected to the output terminals of the AND gates G5, G6, G7, and G8, respectively; R1 denotes a ROM cell whose address is designated by the word line W3 and the bit line B0; R2 denotes a ROM cell whose address is designated by the word line W2 and the bit line B0; R3 denotes a ROM cell whose address is designated by the word line W0 and the bit line B0; R4 denotes a ROM cell whose address is designated by the word line W1 and the bit line B1; R5 denotes a ROM cell whose address is designated by the word line W0 and the bit line B1; R6 denotes a ROM cell whose address is designated by the word line W3 and the bit line B2; R7 denotes a ROM cell whose address is designated by the word line W1 and the bit line B2; R8 denotes a ROM cell whose address is designated by the word line W3 and the bit line B3; R9 denotes a ROM cell whose address is designated by the word line W1 and the bit line B3; R10 denotes a ROM cell whose address is designated by the word line W0 and the bit line B3; R11 denotes a ROM cell whose address is designated by the word line W1 and the bit line B0; R12 denotes a ROM cell whose address is designated by the word line W3 and the bit line B1; R13 denotes a ROM cell whose address is designated by the word line W2 and the bit line B1; R14 denotes a ROM cell whose address is designated by the word line W2 and the bit line B2; R15 denotes a ROM cell whose address is designated by the word line W0 and the bit line B2; R16 denotes a ROM cell whose address is designated by the word line W2 and the bit line B3. The ROM cells R1-R16 are an N-channel transistor, respectively, all of which have a same channel length and a channel width, respectively. The channel length and the channel width of them are the same as those of the transistor T8 and the transistors T13-T16 of the reference generating portion 7. The ROM cells R11-R16 have been channel-cut, and the threshold voltage of them is set to be 5V or higher. Namely, writing in the ROM cells R11-R16 has been made so that, even if a voltage of 0-5V is applied to the gate of them, no drain current flows in them. The ROM 10 as a whole has a NOR type memory block configuration.
Now, operations will be described also referring to the timing chart of FIG. 4.
In the reference voltage generating portion 7, when the source voltage is applied to the source voltage input terminal 6, the transistors T7, T8, and T12-T16 are held ON at all times. In this state, while the chip select signal CS is at the L level, the transistor T9 is ON and the transistor T10 is OFF. Accordingly, the transistor T11 is in its OFF state and the potential of the node N3, i.e., the reference voltage VN, is at the L level. Hence, the transistor T6 is in its OFF state and the source voltage is supplied to the node N4 through the transistor T9 to bring the reference voltage VP to the H level.
When a signal S1 for bus controlling is input from the central portion of the memory driving apparatus to the signal generating portion 1, the signal generating portion 1 raises the chip select signal CS and the pre-charge signal PR to the H level.
When the chip select signal CS rises to the H level, the transistor T9 is turned OFF and, hence, the transistor T5 is turned ON. On the other hand, the output level of the inverter I6 is brought to the L level and the transistor T10 is turned ON, and thereby, the transistor T11 is turned ON. Since the transistors T12-T16 are ON, current flows, via the transistor T10 and T11, into the transistors T10-T16 and, thus, the transistors T10-T16 act as the voltage source for supplying the gate voltage of the transistor T6. Since the transistor T6 is thereby turned ON and the transistors T7 and T8 are held ON, the reference voltage VP is pulled to a potential (L level) determined by the ratio between the resistance values of the transistor T5 and the transistors T6-T8. On the other hand, the reference voltage VN is raised to a potential (about 1.5V in the present example) determined by the ratio between the resistance values of the transistor T10 and the transistors T11-T16. Incidentally, the transistor T10 supplies a current of about 400 .mu.A to the transistors T11-T16.
In the sense amplifier 8, while the pre-charge signal PR is at the L level, the reference voltage VP is at the H level, and the reference voltage VN is at the L level, the transistor T1 is in its OFF state, and the transistor T3 is also in its OFF state, and then the transistor T4 is in an OFF state. Hence, the potential of the node N1 is at the L level and, accordingly, the output voltage as the potential of the node N2 is at the H level.
Here, we consider the case where the address signals A3, A2, A1, and A0 are at the L, H, L, and L levels, respectively. At this time, in the selector 9, the output level of the NAND gate G1 is brought to the L level and, hence, the transistor T17 is turned ON and the transistor T21 is turned OFF. Thereby, the bit line B0 is connected to the node S. The potential of the other bit lines B1-B3 is fixed to 0V because the transistors T22-T24 are turned ON. At this time, in the ROM 10, the output level of the AND gate G7 goes to the H level, and the word line W1 goes to the H level. Thereby, linked together with the above-described selection of the bit line B0, the ROM cell R11 of the ROM 10 is selected.
Concerning the transistors of the reference voltage generating portion 7, as described above, the transistor T6 has the same channel length and the channel width as the transistor T3 of the sense amplifier 8 has, the transistor T11 has the same channel length and four times as large channel width as the transistor T6 has. The transistor T7 has the same channel length and the channel width as each of the transistors T17-T20 of the selector 9 has, and the transistor T12 has the same channel length and four times as large channel width as the transistor T7 has. Further, the transistor T8 and T13-T16 each have the same channel length and the channel width as the ROM cells R1-R16 of the ROM 10 each have. Hence, the bit line corresponding to the address of the specified ROM cell is pre-charged when the chip select signal CS is at the H level, so that about one fourth of the current of 400 .mu.A flowing through the transistor T10 of the reference voltage generating portion 7, i.e., a current of about 100 .mu.A, may flow, via the transistors T1 and T3 of the sense amplifier 8, into the pertinent ROM cell, when the gate voltage of the ROM cell is the source voltage of 5V, by the current mirror effect.
When the pre-charge signal PR goes to the H level, the transistor T4 of the sense amplifier 8 is turned ON and the node N1 is charged to approach the source voltage of 5V. At the same time, the node S and the bit line B0 are charged through the transistor T3. The transistor T3 causes the potential of the node N1 to change according as the amount of the current drawn from the node S. Incidentally, since, in this prior art example, the reference voltage VN is about 1.5V, the bit line B0 is charged only up to 0.7V or so. Although the ROM cell R11 is selected by the connection of the bit line B0 with the node S by the selector 9 and the rise of the word line W1 to the H level, the current supplied to the bit line B0, as it is, keeps on being charged to the bit line B0 because the ROM cell R11 has been written in so as not to draw current from the bit line B0 even if the word line W1 is at the H level.
As the result of the node N1 getting charged, the node N2 as the output terminal of the inverter I5 is reversed to the L level. And, when the potential of the bit line B0 has become a substantially fixed value, the pre-charge signal PR falls to the L level. The pre-charge period is up to this point of time.
The pre-charge period is over when a predetermined period of time has elapsed after the chip select signal CS and the pre-charge signal PR were both raised to H levels. Then, the pre-charge signal PR falls to the L level, the transistor T4 is turned OFF, and the current which has been supplied from the power source through the transistor T4 is stopped. Thereby, the potential of the node N1, node S, and the bit line B0 slightly falls but the fall in the potential is of such a degree that gives no effect to the output level of the inverter I5. Thereafter, the potential of the node N1, node S, and the bit line B0 is gradually raised by the current supplied from the power source through the transistor T1 and, hence, the potential of the node N2 is maintained at the L level. This means that the L level, i.e., a logical value 0, is read out of the ROM cell R11.
Now, the case where the address signals A3, A2, A1, and A0 are all L will be considered. At this time, in the selector 9, only the output signal of the NAND gate G1 goes to the L level and the output signals of the other NAND gates G2-G4 go to the H level. Thereby, the bit line B0 is connected to the node S, while the other bit lines B1-B3 are not connected to the node S and held at the potential of 0V. Further, in the ROM 10, only the output level of the AND gate G8 goes to the H level, and the output levels of the other AND gates G5-G7 go to the L level. Accordingly, the word line W0 goes to the H level and thus the ROM cell R3 is selected.
In this case, as with the above described case, the node N1, when the chip select signal CS and the pre-charge signal PR are raised to the H level, is supplied with current from the power source through the transistor T4 to obtain a potential approaching the source voltage of 5V. Since the ROM cell R3 is selected in the ROM 10 in this case, the ROM cell R3 draws current from the bit line B0. However, since the current supplied to the node N1 through the transistor T4 is much greater than the current drawn from the bit line B0 by the ROM cell R3, the potential of the node N1 keeps on rising. On the other hand, while the bit line B0 is charged through the transistor T3 and the node S, since the current is drawn by the ROM cell R3, the potential is kept below that in the above described case where the ROM cell R11 was selected, i.e., at around 0.4V.
When the pre-charge signal PR falls to the L level, the transistor T4 is turned OFF. Since the current flowing through the transistor T1 is about 1/4 of the current drawn by the ROM cell R3, the potential of the node N1 in this state gradually falls. Although the potential of the node S and the bit line B0 also falls, the fall in the potential of them is small because the bit line capacitance is great compared to the capacitance of the node N1. When the potential of the node N1 falls below a certain value, the output potential of the inverter I5 is reversed to the H level. This means that the H level, i.e., the logical value 1, is read out of the ROM cell R3.
While the case where the sense amplifier 8 reads out a one-bit signal was described in the foregoing, several to several tens of sense amplifiers 8 are required in an actual real memory driving apparatus. Namely, the operation shown in FIG. 4 must be performed as many times as the number of the sense amplifiers 8. An actual circuit has a configuration for example as shown in FIG. 5. That is, referring to FIG. 5, reference numerals 8a, 8b, 8c, and 8d each denote a sense amplifier outputting a read-out signal of one bit; 10a, 10b, 10c, and 10d denote a ROM, respectively, as the objects out of which the sense amplifiers 8a, 8b, 8c, and 8d read out data written therein, respectively; 9a, 9b, 9c, and 9d denote a selector, respectively, selecting a bit line among the bit lines B0-B3 of the ROMs 10a, 10b, 10c, and 10d, respectively; 11 denotes the wiring capacitance of the signal line supplying a reference voltage VP; 12 denotes the wiring capacitance of the signal line supplying a reference voltage VN. Other constituents are the same as those in the prior art example shown in FIG. 2. Further, operations of each of the pluralities of sense amplifiers 8a, 8b, 8c, and 8d, selectors 9a, 9b, 9c, and 9d, and the ROMs 10a, 10b, 10c, and 10d are the same as in the above described case where one each of the sense amplifier 8, the selector 9, and the ROM 10 are provided.
According to the actual memory driving apparatus of the prior art shown in FIG. 5, there are multiple sense amplifiers 8a, 8b, 8c, and 8d, selectors 9a, 9b, 9c, and 9d, and ROMs 10a, 10b, 10c, and 10d arranged in parallel and connected to one set of the signal generating portion 1 and the reference voltage generating portion 7. Namely, one signal generating portion 1 and one reference voltage generating portion 7 are provided to each of the sense amplifiers 8a, 8b, 8c and 8d. Therefore, one reference voltage generating portion 7 must drive the transistors T1 and T3 same in number as the sense amplifiers 8a, 8b, 8c, and 8d, which transistors T1 and T3 are provided with each sense amplifier 8a, 8b, 8c and 8d by one, respectively.
According as the chip select signal CS and the pre-charge signal PR become faster, the parasitic capacitance constituted of the wiring capacitance 11 and 12 due to wiring arrangement of the signal lines for supplying the reference voltages VP and VN and the gate capacitance of the transistors T1 and T3 becomes non-negligible. Although the reference voltage VP fell and the reference voltage VN rose during the pre-charge period in the operation of the prior art example shown in FIG. 4, it sometimes becomes impossible, according as the signals become faster, for the reference voltage VP to fall and for the reference voltage VN to rise during the pre-charge period. This means that reading out of the memory becomes impossible in the fast operation.
As a measure to deal adequately with the faster pre-charge signal PR, there is a method to hold the chip select signal CS, for example, at the H level at all times. According to this method, the reference voltages VP and VN can be constantly kept at predetermined values and, hence, making the faster operation becomes possible. However, since the reference voltage generating portion 7 is activated at all times, it keeps on outputting the reference voltages VP and VN which constantly take on fixed DC values and, therefore, the consumption current becomes increased when the apparatus is operated slowly, for example, with the pre-charge signal PR at a frequency of 32 kHz or so or when the values in the RAM, not shown, are held retained while the memory driving apparatus is not making any operation, namely, in the stop mode in which read out of the ROM 10 is not performed.
As another measure to achieve a fast operation, there is a way in which the reference voltage generating portions 7 of the same number as the number of the sense amplifiers 8a, 8b, 8c, and 8d are provided, but, in this case, the area required for arranging the reference voltage generating portions 7 therein becomes greater. Further, there is a way in which the output impedance of the reference voltage generating portion 7 is lowered, but even if this method is used, there still is a defect of an increase in the current consumption by the reference voltage generating portion 7.
Since prior art memory driving apparatuses are configured as described above, there have been such problems that the rise of the reference voltages is retarded by the parasitic capacitance constituted of the wiring capacitance, gate capacitance, and the like, and thereby fast read out of the memory is made impossible, that the current consumption increases when such a method for achieving the fast reading is used as to keep the chip select signal at the H level at all times or to lower the output impedance of the reference voltage generating portion, and that, in such a method as to provide the reference voltage generating portions of the same number as that of the sense amplifiers, the area for arranging the reference voltage generating portions therein is increased.


The user assistance system provides a system and method for capturing images of a document and interaction of a primary user with the document in an interaction session. Briefly described, one embodiment comprises an image capture means adapted to capture an initial image of the document and at least one subsequent, additional image of the document during an interaction session, the image being mapped to a known co-ordinate system, interaction capture means for capturing the interaction of a user with the document whereby to determine at least one co-ordinate of a pointer used for the interaction relative to the same co-ordinate system defined for the initial captured image, and processing means for determining an appropriate transform that maps the additional image onto the original image.

It is known to provide apparatus which captures images of a primary user at one location interacting with a document or other object. The captured information can subsequently be displayed at a remote site as an image of the document/object and the interaction of the primary user with the document. To be truly useful such apparatus should provide real time images (or almost real time) of the interaction and the document, although the images may be recorded for subsequent transmission to the remote user.
For document sharing with interaction specialist electronic sharing tools have been developed which support the sharing of electronic documents between users across a network. Each user is provided with a computer which is connected to the network and includes a display upon which an image of the document can be presented. It is useful to enable a user to interact with the document and in many applications (such as Netmeeting® by Microsoft Corporation of Redmond Drive, Seattle, Wash., USA) the user can interact with the images by moving a cursor around the screen. The movement of the cursor is then displayed on every users screen at the same time.
The ability to interact with an electronic document through the use of a pointer such as a mouse is difficult and some users do not find it a natural way to interact with a document. The interaction can be very stilted and it does not offer the range of interactions possible when co-present. Working with a hard copy or an original of a document is also easier for many users than interacting with an image on a screen.
Video conferencing, as a genuine alternative, allows a user at a remote site to see how a primary user interacts with an object. A user can then interact with the document and the interaction will also be caught on camera provided it is in the field of view of the camera. The stream of images are then sent across a network to the remote user where the images are reproduced on a screen. The remote user can then see the areas of the document that the user is pointing to. In an even simpler system, the output of a video camera is recorded to a tape which can be played back at a later data by a remote user.

Method and apparatus for capturing images of a document with interaction

Hewlett-Packard Development Company, L.P.


A method and a system for restricting access to automotive data in a regulated automotive data distribution network are provided herein. The method may include the following steps: receiving a plurality of automotive data sharing rules from automotive data sharing regulations; receiving data sharing restrictions applicable to at least some of the automotive data; generating a data sharing policy based on the automotive data sharing rules and the data sharing restrictions; and applying the data sharing policy to the automotive data to restrict one or more data consumers from accessing all or portions of the automotive data. The system may implement the steps of the aforementioned method using a regulated data distribution server such as a neutral server for automotive data.

Car makers usually provide data in one feed containing data from different models and years. Currently, there are "standard" policies for authorization of sharing data between the car makers and data consumers.
The car maker may define white lists, blacklists, and/or sets of rules to approve data consumers. The car maker may request each data consumer is individually approved. These restrictions are typically applied to a full data feed from the particular car maker. The aforementioned process can be performed prior to enabling a particular data consumer to get a particular data feed.
In Europe, as part of the Neutral Server regulation, car makers are currently required to share their data with Tier1 suppliers and/or automotive subsystem manufactures. Similar regulations are being contemplated in the United States. Such data can include performance information, detected error codes, sub-system failure information, and/or additional data as defined in the regulations. Usually car makers have more than one Tier1 supplier of the same sub system, thus resulting in a car maker typically having to share data with multiple entities.
The data collected from vehicles can be business sensitive. Different car models can have different Tier1 suppliers, in some scenarios, even for the same car part. Tier1 suppliers can compete with each other, which can result in the data collected from the vehicles being highly business sensitive. Therefore, the Neutral Server regulation regime can require a data feed access authorization solution that is can account for data sharing among multiple businesses and competitors. This can be enhanced in comparison to the types of solutions that are currently in use.

Method and system for restricting access to automotive data in a regulated automotive data distribution network


An ornament assembly includes an attachment clip, an elongated shaft, and an ornament. The attachment clip includes a first jaw and a second jaw. The first jaw includes a first spine and a first finger extending from the first spine. The second jaw includes a second spine and a second finger extending from the second spine toward the first finger. The elongated shaft includes a first end and a second end. The second end of the elongated shaft is coupled to each of the first spine and the second spine such that at least one of the first jaw and the second jaw rotates about the elongated shaft to move the attachment clip between an open position and a closed position. The ornament is coupled to the first end of the elongated shaft such that the ornament is spaced from the attachment clip via a length of the elongated shaft.

Seasonal decorating has long been a tradition across many cultures. Decorating efforts are often at their peak during the holiday seasons, for example, when Christmas trees become the center of many homes. Ornaments and decorations of a plurality of types are placed to adorn the trees. A feature ornament, such as a star or angel, is typically placed on the highest branch as a tree top decoration. Placement of the feature ornament at the top of the tree is a rather challenging undertaking as it can often be difficult to balance an ornament in a desired upright manner in a desired position above the tree while simultaneously coupling the ornament to the tree. Similar issues apply to the selective coupling of ornaments and decorations throughout homes, businesses, or other suitable environments.


A retract clamp (20) utilizes three clamp arm retraction enhancement mechanisms (26, 28, 63) to increase clamp arm (24) retraction consistency. The first retraction enhancement mechanism (26) is a bifurcated piston having a first piston member (68) and a second piston member (70). If the first piston member (68) becomes tilted and caught, the second piston member (70) continues to move allowing the first piston member (68) to right itself. The second retraction enhancement mechanism (28) comprises a clamp arm guide mechanism having a base (82), a pusher (84), and a plurality of resilient members (110-124) interposed between the base (82) and the pusher (84) to bias the pusher (84) against the clamp arm (24) and align the clamp arm (24) with a clamp arm receiving area (40) defined in a clamp arm holder (22). The third clamp arm retraction enhancement mechanism comprises a lift surface (63) on the clamp arm (24). The lift surface 63 is oriented substantially perpendicular to the axis of the clamp arm (24) for upward retraction of the clamp arm outer end 54 substantially prior to axial retraction of the clamp arm (24).

To speed production of work pieces, such as parts for assembling machines, it is efficient to use a retract clamp to hold the parts down while some forming operation is performed on the parts by a fixture such as a mill or drill press. One such retract clamp is shown in U.S. Pat. No. 5,752,693, (currently application No. 08/705,957) which is hereby fuilly incorporated herein by reference.
One problem encountered with retract clamps in general is inconsistent retraction. Not infrequently, the clamp arm will fail to retract frilly. This is generally caused by the arm or some component of the retract clamp becoming caught in the body of the clamp. When the clamp arm fails to fully retract, it can interfere with the proper removal and placement of work pieces. It can also interfere with the proper operation of the fixture. In either case, the production operation is halted, the work piece likely ruined, and the fixture can be damaged in some significant way.
Another problem encountered with retract clamps is seal failure. In a hydraulic retract clamp, a piston member is provided with a seal to contain hydraulic fluid in a hydraulic chamber. During normal operation, the piston member can tilt. When the piston member tilts, it pinches the seal. Over time the seal fails allowing hydraulic fluid to leak out of the hydraulic chamber eventually rendering the clamp inoperable.
The retract direction of the clamp arm in retract clamps is also generally problematic. If the retract clamp pulls the clamp arm rearwardly before the clamp arm moves upwardly and disengages the work piece, the clamp arm drags across the work piece which can leave marks on the work piece. Further, the clamp arm can move the work piece as it retracts. This moves the work piece out of position which can require that the production operation be halted.


A variable delay circuit for a semiconductor memory device includes an input buffer for converting a digital input signal to an analog signal and buffering the resultant analog signal, an analog delay unit for delaying the analog signal outputted from the input buffer unit for a certain time, and an output buffer unit for converting the delayed analog signal to a digital signal and buffering the resultant digital signal. The analog delay unit is composed of a CMOS inverter, a plurality of operational transconductance amplifier-capacitor delay elements, and an output inverter, to form a second-order Bessel filter. An O.T.A and an inverter may be additionally provided between the plurality of O.T.A.'s for thereby decreasing a parasitic effect of the capacitors connected to the outputs of each of the plurality of O.T.A.'s in the analog delay unit. The delay circuit serves to obtain a desired delay time by varying a control voltage irrespective of unstable time delay values of components caused by the fabrication process.

1. Field of the Invention
The present invention relates to a variable delay circuit, and more particularly to a variable delay circuit suitable for integration into a semiconductor memory device and capable of variably delaying an input signal by means of an OTA-C (operational transconductance amplifier-capacitor filter), when there occurs a change in a fabrication process or an input voltage.
2. Description of the Prior Art
Typically, as shown in FIG. 1, a conventional delay circuit in a conventional semiconductor memory device is composed of a plurality N of delay units (1-N) in series.
As shown in FIG. 2, each of the delay units includes: an inverter 10 for inverting an input signal IN1; an NMOS transistor 20 to the drain of which the output from the inverter 10 is applied through a resistance 15, to the gate of which the input signal IN1 is applied, and the source of which is connected to a ground voltage Vss potential; a PMOS transistor 25 configured as a capacitor and to the gate of which the drain of the NMOS transistor 20 is connected, and to the drain and source of which a supply voltage Vcc is applied; a NAND gate 30 for NANDing the output from the drain of the NMOS transistor 20 and a reset signal RST for thereby generating an output signal OT1; and a switch SW1 for switching a parallel shunt connection line also carrying the input signal IN1 and generating the output signal OT1.
With reference to FIGS. 3A and 3B, the operation of the thusly composed conventional delay circuit will now be described.
First, as shown in FIG. 3A, with switch SW1 opened (turned off) when the input signal IN1 transits from low to high, the inverter 10 inverts the transited high level signal to a low level. At the same time, the NMOS transistor 20, to the gate of which the input signal IN1 is applied, is turned on by the transited high signal IN1 and also discharges through the NMOS transistor 20 the supply voltage Vcc charged on the PMOS transistor capacitor 25 from the node N1, to ground Vss. As a result, the NAND gate 30 outputs a high level signal in accordance with the level at node N1 and the signal from the reset terminal RST.
Therefore, as shown in FIG. 3B, during the rising edge of the input signal IN1, the discharging of the PMOS transistor capacitor 25 is hurried through the NMOS transistor 20, thereby causing a certain time delay D1 with respect to the rising of output signal OT1. Conversely, during a falling edge of the input signal IN1, the NMOS transistor 20 is turned off according to the transited signal, and the inverter 10 inverts the low level input signal IN1 to a high level signal.
During the transition of the input signal IN1, the PMOS transistor 25 capacitor is discharged until the voltage at the node N1 reaches a high level, and the NAND gate 30 NANDs the high level signal at the node N1 and a high signal from the reset terminal RST, thereby outputting a low level output signal OT1.
So, during a rising edge of the input signal IN1, because the output signal OT1 depends on the RC time constant of the resistance 15 and the PMOS transistor capacitor 25 and thus requires a longer time to rise, the time delay D2 during a falling edge of the input signal IN1 remains longer than the time delay D1 during a rising edge of the input signal N1.
When a time delay is not required, the switch SW1 connected to the output of the NAND gate 30 is respectively closed (turned on), whereby the input signal is directly outputted without passing through the delay circuit.
However, the conventional delay circuit of the semiconductor memory device delays the input signal by using the resistance 15 and the PMOS transistor capacitor 25 which are respectively sensitive to the fabrication process and the supply voltage Vcc, thereby causing an instability in the delay time.
Particularly, for obtaining a longer delay time than 5 ns, more delay circuits had to be serially connected to each other, thereby causing difficulties in application to a highly integrated circuit.


The inventors have devised novel approaches for the preparation of flavanolignan compositions of enhanced solubility and substantially free of toxic contaminants. Such novel approaches are based on spray drying or lyophilizing to dry a diluted preparation of flavanolignan. These approaches avoid the use of toxic excipients and or carriers commonly used to precipitate flavanolignan concentrates and thus address the drawbacks of existing methods and compositions.

1. Field of the Invention
The invention relates to compositions and a process for the manufacture of a flavanolignan-containing substance from milk thistle displaying enhanced aqueous solubility relative to pure flavanolignan preparations. The substance of the method according to the invention is useful for the manufacture of solid medicinal products and dietary supplements with desired improved dissolution characteristics.
2. Summary of the Related Art
Fruits of milk thistle (Silybum marianum (L.) Gaertn.) contain several isomeric compounds of flavanol-lignane type of the general formula C25H22O11-silybinin A, silybinin B, isosilybinin A, isosilybinin B, silydianin and silychristin—collectively called flavanolignans of milk thistle or silymarin. Silymarin (generally available as the dry extract of milk thistle) has been reported to have numerous pharmacological activities such as for example, antioxidant effect, stabilization of cell membranes, and stimulation of biosynthesis of proteins to mention a few. Silybin (a mixture of silybinin A and silybinin B) has been found to be particularly suited as an hepatoprotective agent. Silymalin is effective in the treatment and prophylaxis of liver disease including acute and chronic intoxication of the liver caused by toxins, (including drugs and various alcohols, e.g., carbon tetrachloride, galactosamine, paracetamol, ethanol, phalloidin and α-amanitin). Silymarin is an active component of pharmaceutical products, (e.g., LEGALON®, Madus AG, Koln, Germany; Hepamarin, Pharmasan GmbH, Freiburg, Germany; HEPADURAN®, Zwinkscher GmbH, Karlsruhe, Germany; or SILYHEXAL®, Hexal Pharma AG, Wien, Austria) used to treat and prevent hepatic diseases. More information about silymarin and its use can be found in Morazzoni et al., Fitoterapia, LXVI, 3-42, (1995); Sailer et al., Drugs, 61: 2035-2063, (2001); Wellington et al., BioDrugs, 15(7): 465-489, (2001).
The silymarin preparation used for manufacture of pharmaceutical preparations or food supplements is thus a purified extract standardized to include specific flavanolignans. Pharm. Forum 28: 418-420, (2002) provides that silymarin contains not less than 90% and not more than 110% of silymarin, calculated as silybin on the dried basis; consisting of not less than 20.0% and not more than 45.0% of the sum of silydianin and silycristin; not less than 40% and not more than 65% for the sum of silibin A and silibin B; and not less 10.0% and not more than 20% for the sum of isosilybin A and isosilybin B; contains from about 40 up to 80% flavanolignans consisting of from about 40 up to 65% of the sum of silybinin A and B; from about 20 up to 45% of the sum of silychristin and silydianin and from about 10 up to 20% of the sum of isosilybinin A and B.
However, the use of milk thistle flavanolignans in general and that of silymarin and its components in the preparation of pharmaceutical products is greatly impaired by the low solubility in both hydrophilic and lipophilic environments of these compounds which greatly reduces their bioavailability and resorbability in mammals. Given the tremendous therapeutic potential, it is not surprising that several investigators have sought a variety of approaches to address the solubility/bioavailability problems as attested by the large body of literature on point including several patents discussed hereinafter.
One approach lies in the preparation of silybin esters (mixture of silybinins A and B, possibly also isosilybinins A and B) with dicarboxylic acid. For example U.S. Pat. Nos. 4,895,839 and 5,196,448 describe a di-sodium salt of bis-hemisuccinate of silybin. This preparation is presently incorporated in in LEGALON® SIL inj., a pharmaceutical product for the treatment of serious poisoning by Amanita mushrooms or other hepatotoxic compounds, marketed by Madaus &Co.
Another approach has been the preparation of silybin glycosides as set forth for example in CZ Patent No. 287 657. The described silybin glycosides are more soluble in water than silybin and they show similar effects as silymarin. Complex compounds of silymarin or silybin with phospholipides are also described by U.S. Pat. Nos. 4,764,508 and 4,895,839. These complexes are prepared by dissolution of components (1 mol of silymarin or silybin and 0.3 up to 2.0 mol of phosphatidyl choline, phosphatidyl serine or phosphatidyl ethanolamine) in aprotic solvent (dioxane or acetone) and by precipitation of the complex by addition of aliphatic hydrocarbon or lyophilization or spray drying. The described complex compounds are the basis of the substance called SILIPED™ or SILYPHOS™, (manufactured by Indena) currently under clinical trials (Comoglio A., et al., Biochem. Pharmacol., 50:(8):1313-1316 (1995).
Yet another approach has been formulation in cyclodextrin complexes notorious for their role in solubilizing a variety of compounds. Inclusion complexes of silybinin with cyclodextrines are described in the U.S. Pat. No. 5,198,430. Complexes of silybinin are described with α-, β- and γ-cyclodextrine and their derivatives in molecular ratio of 1 mol of silybinin with 1 up to 4 mol of the corresponding cyclodextrine. Complexes are prepared by dissolution of both components in aqueous ammonia and by removal of the ammonia either by evaporation or neutralization with hydrochloric acid and by subsequent drying or lyophilization.
Solutions of silymarin in polyethylene glycol alone or in polyethylene glycol and some co-solvents and/or surfactants are described in WO 99/18985. The gelatin capsules filled with such solutions show higher solubility in dissolution tests than silymarin alone.
Another patented procedure for increasing the biological availability of silymarin consists in the preparation of coprecipitates of flavanolignans with carriers and detergents (see for example, U.S. Pat. No. 5,906,991 and EP 722719). Suitable carriers according to these methods include water soluble saccharides, derivatives of cellulose and polyvinylpyrrolidone whereas polysorbates of fatty acids are used as detergent. These coprecipitates are said to have higher solubility properties as compared to untreated silymarin. However, some of these obligatory carriers and excipients according to these patents coprecipitate as contaminants with the flavanolignans. Unfortunately, some of these contaminants are known toxic compounds and thus may produce adverse reactions in a patient further exacerbating an already existing condition.
Thus, the currently available approaches for the preparation of flavanolignan compositions suffer from a number of drawbacks. In general, conventional methodologies fail to produce a sufficiently soluble preparation. Moreover, because of the low solubility, such preparations are not sufficiently bioavailable. A further disadvantage of the formulations in presently the art is that often the flavanolignan is bound to a chemical compound which can physiologically act as a foreign substance in the body thereby bringing about undesired side reactions or impair the effectiveness of the flavanolignan. Therefore, there remains a need to identify and develop improved methodologies and compositions. Such methodologies and compositions should overcome the shortcomings of the traditional methods in the literature. It is an object of the present invention to provide flavanolignan preparations which reduce the binding of the flavanolignans to foreign compounds and possess high rate of liberation wherein the liberation is accomplished physically by means of destruction of its crystalline lattice (amorphous substance). These flavanoligaans preparations should maintain their efficacy while limiting their binding to foreign compounds.

Increased solubility flavanolignan preparations


An apparatus for implementing a minimum toggle rate guarantee may comprise first, second, and third circuitries. The first circuitry may calculate a sequence of values for an internal bus inversion signal based upon a sequence of values for a plurality of internal Input/Output (IO) signals. The second circuitry may establish a sequence of values for an external bus inversion signal by selecting between the sequence of values for the internal bus inversion signal and a sequence of substantially random values. The third circuitry may set the values for a plurality of external IO signals to inverted values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a first value, and to values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a second value.

Modern chip-to-chip parallel interfaces may comprise relatively wide Input/Output (IO) buses with clock frequencies over 1 gigahertz (GHz). Wide IO busses may raise various Signal Integrity (SI) issues, such as effects related to Simultaneous Switching Noise (SSN). When multiple IO output drivers switch simultaneously, they may induce a voltage drop in a chip power distribution, or package power distribution, and may momentarily raise a ground voltage within the device relative to a system ground. SSN may be related to an inductance that may be present between the device ground and the system ground, a Simultaneous Switching Output (SSO) count of the interface, and a slew rate of output drivers, for example.
A feature of chip-to-chip interfaces that may reduce SSN is a Bus Inversion (BI) signal, which indicates whether data currently being transmitted on an interface is inverted or not. Using a BI signal, a choice may be made to send either non-inverted data or inverted data, depending on which would have a lower SSO count. One example implementation of BI logic may be to count a total number of bits in a covered bus having a first value (e.g., a value of "1"). If the total number is larger than half of a width of the covered bus, the BI bit may be set to a predetermined value (e.g., a value of "1") and inverted data may be sent on the interface. Doing so may facilitate keeping an SSO count on the covered bus continuously at or below half of the width of the covered bus, and may therefore bound a level of SSN corresponding with the covered bus.
For synchronous chip-to-chip interfaces, an associated clock IO signal may be constantly toggling, while other non-clock IO signals may toggle far less frequently. At high IO clock frequencies, a timing margin for interface IOs to act synchronously as a group may become so tight that once-negligible timing factors, like transistor aging, may become significant. Meanwhile, the use of BI signals may reduce a rate of IO toggling, which may impact various aspects of transistor aging, and may in turn impact timing margins for interface IOs.

Minimum input/output toggling rate for interfaces


A combination mouse/trackball input device for an electronic computer functions as either a mouse or a trackball, depending on which of two operating modes the user selects. The user selects the desired mode by moving a selector handle to one of two positions, which causes a tracking ball to be raised to trackball mode or lowered to mouse mode. In mouse mode, the tracking ball makes contact with the mouse pad or other flat surface on which the device rests so that the ball rotates when the device is moved. This mode is suitable for general purpose use. In trackball mode, the tracking ball is elevated so that it does not make contact with the mouse pad, but it projects through an aperture in the top face of the enclosure. In this mode, which is preferred for applications requiring fine control over the cursor position, the user rotates the ball directly with his or her fingers. The device permits easy switching between the two modes with minimal interruption of the user's work. In both modes, rollers sense the rotation of the tracking ball along two axes and a photo detector mechanism converts this rotation into electrical pulses which are sent to the attached computer. The computer uses the pulses to calculate the movement of the tracking ball along two axes and to move an on-screen cursor accordingly.

1. Field of the Invention
This invention relates to input devices for electronic computers and, more particularly, to a device which functions as either a mouse or a trackball, depending on the user's selection.
2. Description of the Related Art
Many computers, particularly those which utilize a graphical user interface, can be controlled by causing a pointer, or cursor, to move on the computer screen. This cursor is used to select commands, manipulate data, activate menus and windows, and so on. Typically, one or more function buttons are available to send activation signals to the computer when the buttons are pressed, or "clicked". Thus, for example, a user can choose a command from an on-screen menu by moving the cursor to a position atop the desired command and clicking a function button to activate the command.
The user must employ some form of input device to generate the signals required by the computer to move the cursor on the screen. The most effective types of input devices for this purpose are those which permit an intuitive correspondence, or mapping, between the user's physical manipulation of the input device and the movement of the on-screen cursor.
Several such devices are well known. Two of the most common are:
a) The mouse, wherein a tracking ball protrudes through an aperture in the bottom face of the device, so that the ball rotates when the device is moved along a flat surface. The cursor moves in accordance with the movement of the device.
b) The trackball, wherein a tracking ball protrudes through an aperture in the top face of the device. The user rotates the ball with his or her fingers, and the cursor moves in accordance with this rotation.
Each of these devices has advantages and disadvantages. Ordinarily, the mouse is the preferred device for general use. It is favored over the trackball, especially for applications where the control button must be held down while the on-screen cursor is moved. In such situations, it is relatively easy for the user to keep his or her finger on the button as he or she moves the device on the pad.
The mouse, however, is not ideally suited for finely detailed work, such as drawings, where the user requires precise control over the cursor. For such uses, the trackball is superior, since the user has more direct control over the tacking ball. Also, with a trackball the user can press the function buttons without any danger of inadvertently moving the cursor, as can happen with the mouse.
For many users, who alternate between general use and finely detailed work, neither the mouse nor the trackball is an ideal solution by itself. Such users would benefit from a combination of the two devices, one that is easily switchable between the two modes of operation.

Combination mouse/trackball input device


A sealing arrangement is provided for sealing an orifice between an interior and an exterior surface of an electronic module. An air-permeable, water-impermeable membrane is disposed in the orifice. A portion of the exterior surface is provided with at least one surface channel which extends between the orifice and a distant point. A protective cover is attached to the exterior surface and arranged to overlie the membrane disposed about the orifice but not to overlie the distant point, thereby providing an air path to the interior surface of the module, via the surface channel and the membrane.

This invention relates to sealing arrangements for electronic circuit modules, and particularly but not exclusively to sealing arrangements for electronic circuit modules for use in automotive applications.
In the automotive industry, electronic circuits are used in many applications within vehicles. For example, electronic circuits are now used in the field of engine management control, where a microprocessor is programmed to receive inputs from sensors and then provides instructions to various transducers for optimising variable engine parameters.
In such an application, and referring to FIG. 1, there is shown a module 5, which is often located in close proximity to the engine (not shown). Electronic circuitry 10 of the module 5 is typically housed in a casing 20, to protect delicate components of the circuitry 10 from oil, grease, water and extremes of temperature.
A problem with this arrangement is that the casing should be watertight, but in order to prevent an air pressure differential from building up the casing should also be air-permeable.
It is known to provide a breather device, such as a dedicated vent 25 as shown in FIG. 2. A typical vent may comprise a hole 30 formed in the casing 20 with a carrier piece 40 disposed in the hole 30 and containing an air-permeable membrane 50. An o-ring seal 70 is provided to seal the space between the carrier piece 40 and the casing 20. An intricate covering piece 60 overlies the membrane (in order to protect against clogging of the membrane by oil and grease) but at the same time has a network of small channels 65 which facilitate movement of air through the covering piece 60, so as to provide the vent.
However the manufacture of the above vent 25, including the provision of a breather hole 30 in the casing 20, the carrier piece 40 for the membrane which is disposed in the hole (with the seal 70), the complex protective covering piece 60 (with the channels 65) which must be secured to the encapsulating piece, adds further expense, time and complexity to the overall manufacture of the module 20.
This invention seeks to provide a sealing arrangement for an electronic circuit module which mitigates the above mentioned disadvantages.
According to a first aspect of the present invention there is provided a sealing arrangement for an electronic circuit module as claimed in claim 1.
In this way a seal is provided using an air-permeable, water-impermeable membrane in a simple and inexpensive arrangement, which protects the membrane from damage.

Sealing arrangement for an electronic circuit module


A line head includes pixel circuits each of which has a plurality of light-emitting elements and circuit elements arranged in a line, and that make the light-emitting elements emit light selectively, based on selecting signals and data signals; selecting circuits that generate the selecting signals based on clock signals input through clock signal lines; data lines that supply data signals to the pixel circuits; and a conductive line having low impedance, arranged in the vicinity of the clock signal line.

The present invention relates to a line head and to an image forming apparatus.
A line head is known as a device for forming (exposing) an electrostatic latent image on a surface of a photoconductor incorporated into an image forming apparatus of an electrophotographic system, such as a copy machine, a printer, or the like. The line head is provided with a plurality of light-emitting elements one-dimensionally arrayed on a substrate, and the respective light-emitting elements are driven through wiring lines patterned on the substrate. Light-emitting diodes (LEDs) and organic EL elements are utilized as the light-emitting elements of the line head. A light-emitting element array corresponding to this line head and an image forming apparatus are disclosed in, for example, Japanese Unexamined Patent Application Publication No. 11-274569.
In general, data lines and control signal lines are arranged according to the arrangement of light-emitting elements, in an organic EL panel used for the line head. Therefore, the length of the wiring lines reaches several tens of centimeters, which is likely to cause a build-up of static electricity and electrostatic breakdown to occur in circuits other than an input buffer. In particular, among the control signal lines, clock signal lines for sequentially selecting a plurality of light-emitting elements are disposed to be separated from other wiring lines, in order to reduce parasitic capacitance, so that static electricity is likely to build-up. Accordingly, electrostatic breakdown is more likely to occur in a circuit connected to the clock signal line than other wiring lines.


Examples herein relate to wavelength division multiplexing optical interconnects. In particular, implementations herein relate to an optical interconnect that include a wavelength translator. The optical interconnect includes a first transmitter configured to modulate, combine, and transmit multi-wavelength optical signals, the modulated optical signals having a first number of optical channels, a first data rate per wavelength, and a first wavelength spacing between neighboring modulated optical signals. The optical interconnect includes a wavelength translator configured to convert the modulated optical signals such that the converted modulated optical signals have at least one or more of: a second number of optical channels different from the first number of optical channels, a second data rate per wavelength different from the first data rate per wavelength, or a second wavelength spacing different from the first wavelength spacing.

Optoelectronic communication (e.g., using optical signals to transmit electronic data) is becoming more prevalent as a potential solution, at least in part, to the ever increasing demand for high bandwidth, high quality, and low power consumption data transfer in applications such as high performance computing systems, large capacity data storage servers, and network devices. Wavelength division multiplexing (WDM) is useful for increasing communication bandwidth by combining and sending multiple different data channels or wavelengths from one or more optical sources over an optical fiber. However, there are several competing or different standards of optical wavelength grids in the optical communication space. Therefore, there remains a need for improved optical interconnects with the ability to enable optical wavelength translation between different standards or optical wavelength grids.

Wavelength division multiplexing wavelength translator

Hewlett Packard Enterprise Development LP


In a semiconductor acceleration sensor, a weight and thin beam parts adjacent to the weight are formed on a substrate, a moving electrode is formed on the weight, and a fixed electrode is formed at a position of the other substrate opposed to the moving electrode. Both the electrodes come in contact with each other and conduct as a result of acceleration on the weight, whereby the semiconductor acceleration sensor operates. The fixed electrode or the moving electrode is formed with a projection toward the opposed electrode and the projection and the electrode come in contact with each other and conduct by action of acceleration with a predetermined spacing held between both the electrodes for preventing occurrence of chattering caused by the electrostatic attraction force between both the electrodes.

The present invention relates to an acceleration sensor and in particular to an acceleration sensor having a switching mechanism using a semiconductor microworking technology.
In recent years, acceleration sensors have been used as means for indirectly detecting an action force of impact, etc., without coming in direct contact with an object. The acceleration sensors cover various applications; it is desired that the acceleration sensor is compact and lightweight, does not require a mounting space on an object, and operates precisely and reliably.
As a predetermined acceleration detection sensor, a sensor using a conductive sphere displaced according to acceleration and connecting two contacts by the conductive sphere is disclosed in Japanese Utility Model Laid-Open Nos. Hei. 4-136575 and 4-127574.
However, the mechanical acceleration switch connecting two contacts by a conductive sphere becomes large in the outside shape because of its structure, so it is poor in responsiveness and it has an accuracy problem. If such a mechanical acceleration switch is miniaturized, batch processing cannot be performed in the manufacturing process and the mechanical acceleration switch becomes expensive.
Further, such a mechanical acceleration switch uses a movement of a sphere caused by acceleration, thus chattering occurs at the operation time.


In sash windows where the sashes are supported on window units which run in channels in a window frame, and the window units are suspended from spring balances, the shoes have easily accessible mechanisms for adjusting the tension in the spring balances, without demounting the sashes and without separating the spring balances from the shoes. Adjustment is done by rotating an element in the shoes, at the bottom of the sash, with the sash pivoted out of the plane of the window. A tool is inserted in a socket to turn an element of the shoe exposed by the tilting of the sash, and the rotation of this element is transferred through 90° to vary the tension in the respective balance.

Spring balances are often used in sash windows, to support or counterbalance the weight of each window sash. A balance is fitted on either side of each sash. The balances work by winding up a helical spring which then produces a frictional engagement between two parts, one connected directly or indirectly to the frame and the other connected directly or indirectly to the sash. The friction is such that the sash will stay put in any position to which it is moved, but can be overcome, so that the sash can be moved, when pushed up or down by an external force. The tension in the springs in the balances have to be set in accordance with the weight of the particular sash being supported. The tension is adjusted by rotating a component of the balance which is to be connected to the sash, while that component is momentarily disengaged from the sash.
This rotation is difficult to do, because access to the relevant component is restricted by the adjacent parts of the window frame. Also it is difficult to adjust the balances on both sides of a window so that they are under equal tension. Still further, readjustment may be necessary after the window has been in use for a period of time.
Sash windows are known where the sashes are supported on slide shoes which slide in channels in vertical window frame members. The sashes are pivotally mounted in these shoes so that the sash can be pivoted out of the plane of the window frame. Such sashes are also provided with secondary fastenings to normally hold the sashes in the window plane, but those secondary fastenings can be released when the window is to be pivoted.
The invention seeks to provide a mechanism which overcomes or reduces the difficulty of spring balance adjustment when slide shoes are used.


Embodiments of the invention are directed to obstacles for used in yard games, a set of obstacles, and a method of playing games using the obstacles. Example obstacles include a ramp, a helical loop, a banked curve, and an inclined pipe. Although preferably these obstacles are used in croquet, some or all of them can be used in other yard games, such as yard bowling (bocce), rolling hoops, etc., or variations thereof.

Yard games, such as croquet, are well known. The game of croquet has been played for decades. Early croquet games typically included wooden mallets, wooden balls, metal-wire wickets, and wooden stakes. Newer games have some of the pieces made out of plastic.
In a standard croquet game, wickets are set within a playing field in a standard configuration. A player progresses his or her ball through all the wickets (typically 6, 7, or 9), toward a turning stake, which is located at the far side of the field. A player gets an extra turn for causing their croquet ball to pass through a wicket. After striking the turning stake with the ball, the player returns through the wickets to the finishing stake. The first to strike the finishing stake is the winner.
If a first player's ball strikes another player's ball during the first player's turn (a croquet), the first player is allowed to knock the other player's ball by resting their ball next to the other player's ball, holding their own ball under their foot, and striking their ball so as to send the second player's ball rolling far away.
Although the game of croquet is highly entertaining, playing the same game, even with variation, can get repetitive and cause players to become disinterested.
Embodiments of the invention address these and other limitations in the prior art.


Disclosed herein is a diffractive waveguide-spatial optical modulator. The diffractive waveguide-spatial optical modulator includes a substrate member, a plurality of reflecting members, and an actuation means. The reflecting members are each formed in a plate shape, are arranged on the substrate member at regular intervals to form a grating array, are configured to form openings therebetween, and are provided with reflecting surfaces formed on the opposite vertical surfaces of the reflecting members and the bottoms of the openings. The actuation means varies the interval between the reflecting members by actuating the reflecting members. The openings between the reflecting members act as wave guides when light is incident on the open sides thereof, and shift the phase of the incident light and then reflect the incident light, so that the reflected light can form diffracted light, when the interval is varied by the reflecting members.

1. Field of the Invention
The present invention relates generally to an optical modulator and, more particularly, to a diffractive waveguide-spatial optical modulator that shifts the phase of incident light by varying the interval between the opposite vertical surfaces of a plurality of reflecting members forming a grating array, thereby forming diffracted light.
2. Description of the Related Art
In the conventional manufacture of optical modulation devices, a device using an acousto-optic effect is referred to as an ultrasonic wave optical modulator. This optical modulator generally uses an ultrasonic wave medium having a uniform optical refractive index, and is operated in such a way as to propagate ultrasonic waves having a uniform period of condensation and rarefaction through the ultrasonic wave medium in a specific direction, introduce laser light into the ultrasonic wave medium at an appropriate incident angle with respect to the direction of propagation of the ultrasonic waves, so that the introduced laser light is reflected by the surface of the ultrasonic waves within the medium and is modulated into diffracted light, and change the output of the ultrasonic waves, so that the state of the condensation and rarefaction of the ultrasonic waves propagating through the medium is changed, thereby changing the intensity of the diffracted light reflected by the surface of the ultrasonic waves and then modulating the laser light.
In the conventional optical modulator, in order to introduce laser light onto the surface of the ultrasonic waves in the medium at the specific incident angle θ, a light source must be installed at a specific inclined angle with respect to the side surface of the ultrasonic wave medium, therefore it is difficult to design and manufacture the system. Furthermore, since a light reflecting surface formed within the ultrasonic wave medium is formed through the aggregation of the ultrasonic waves, the light reflecting surface cannot act as a desirable reflecting surface. In particular, there is a problem in that the output of ultrasonic waves is reduced due to the dispersion of ultrasonic waves that occur within the ultrasonic wave medium. Moreover, there is a disadvantage in that a light absorbing element must be installed outside the ultrasonic wave medium to absorb non-modulated light. Furthermore, when the laser light is incident on the ultrasonic wave medium, the loss of light due to the reflection of light by the surface of the medium cannot be avoided. Moreover, when high-power laser light, such as Ar+laser light or Kr−laser light, is employed, heat generated within the ultrasonic wave medium influences the ultrasonic waves, therefore the modulation of light intensity becomes unstable.
Meanwhile, the conventional optical modulator has problems in that the width of a light beam is restricted in the direction of propagation of the ultrasonic waves and the switching rate is restricted due to time delay at the relatively low propagation speed of the ultrasonic waves.

Diffractive waveguide-spatial optical modulator


An emergency fire evacuation kit comprising a package having one substantially transparent side, a carrying means, a blanket or poncho of a fire-resistant material, the material producing no noxious fumes or odors when burned, a flashlight and indicia.

1. Field of the Invention
This invention relates to an emergency kit, and more particularly, to a fire emergency kit to aid individuals in evacuating a building due to a threat of fire.
2. Brief Description of the Prior Art
Emergencies can arise in many situations, such as in the home, the automobile and the workplace. Over the years, emergency kits have been developed that address many of these situations. For example, U.S. Pat. No. 752,463 to Morris discloses an emergency case having a hinged box containing medical supplies and a first-aid book. U.S. Pat. No. 2,982,392 to Bossone discloses a safety kit for motor vehicles having a box-like container for an emergency supply of gasoline. This safety kit also may include other items necessary for motor cars, such as: a tire gauge, an anti-fog cloth, road reflectors, an ice scraper, safety tape, yellow light filters, a trough light and a tire cutter. U.S. Pat. Nos. 1,857,824 to Scholz et al. entitled "Emergency Kit for Automobiles" and 1,625,547 to Kessler entitled "Emergency Kit" are similar in nature to the Bossone and Morris patents.
U.S. Pat. No. 3,935,944 to Wilson et al. discloses a diagnostic display package having a transparent cover and small receptacles within. The package is useful for conveniently storing and displaying medical diagnostic tests. U.S. Pat. No. 4,726,365 to Jablonski discloses an air filtering apparatus for use in aircraft emergencies. The apparatus includes a pouch containing an air filtration mask. The pouch is affixed to other commonly found aircraft emergency apparatus, such as an airsickness bag or a card explaining emergency procedures. The apparatus also includes a transparent cover whereby a passenger may visualize the air filter mask within and instructions for using the filter mask, the instructions being visible when the pouch is in an unopened state.
Fire emergencies pose particular challenges to persons dwelling in large multi-unit facilities, such as personal care homes, dormitories and hotels. Aged or infirm residents or residents unfamiliar with their surroundings can become confused during emergencies or fire drills. This stems in part from the amount of material each resident must remember during the emergency. Furthermore, many facilities do not provide the basic necessities needed for escape from fire emergencies, including fire-resistant blankets, flashlights and instructions on how to escape from a given room in the structure.
Generally, multi-unit facilities provide instructions to aid individuals in identifying a proper escape route. Some multi-unit facilities provide flashlights and blankets to protect the residents as they attempt to escape from their apartments or dwelling rooms. Some facilities also provide fire-safety devices that attach to the doors of the apartments. These devices indicate that the apartments have been evacuated. However, in emergency situations many residents of multi-unit facilities panic and cannot and do not locate these various items, which can result in an unnecessary loss of life.
Therefore, it is an object of my invention to improve the safety of persons living in multi-unit facilities. There is a need for an accessible, compact, portable kit providing necessities for escape from a fire or other emergencies, particularly in multi-unit facilities.


A self-aligning socket for an integrated circuit package includes an outer frame and an array of contacts configured for alignment with corresponding conductive pads on the bottom of the integrated circuit package. The outer frame further includes a first plurality of alignment ball bearings configured thereon, the ball bearings mounted on cantilevered spring rods.

The present invention relates generally to integrated circuit device mounting assemblies and, more particularly, to an apparatus for implementing a self-centering land grid array (LGA) socket.
Area array socket connectors are an evolving technology in which an electrical interconnection between mating surfaces is provided through a conductive interposer. One significant application of this technology is the socketing of land grid array (LGA) modules directly to a printed wiring board, in which the electrical connection is achieved by aligning the contact array of the two mating surfaces and the interposer, then mechanically compressing the interposer. LGA socket assemblies are prevalent today in the electronics industry, and are commonly used to attach both single chip modules (SCMs) and multi-chip modules (MCMs) to printed wiring boards.
Integrated circuits, such as those mounted in LGA assemblies for example, are commonly tested before installation. Accordingly, test sockets are primarily used to determine whether the integrated circuit functions properly, and can make the required electrical connections to pads or leads on the integrated circuit package. In a test system, the test socket is typically mounted on a test circuit board coupled to a control unit. The test circuit board typically includes electronic interconnects (e.g., thin, narrow conductive strips) for coupling electronic signals between the test socket and a control unit. The control unit, in turn, includes a processor that communicates with a device under test (e.g., a packaged electronic circuit mounted on the test socket) by transmitting electronic signals to the packaged electronic circuit and receiving electronic signals from the packaged electronic circuit.
With such testing, there is a need for repeated, accurate centering of LGA substrates within test sockets. Moreover, the test socket should be able to accommodate variations of ±8 mils or more in substrate size, and must also be easy to load and unload in a manufacturing environment. Currently, conventional sockets (including test sockets) incorporate plastic spring fingers in the support frame thereof. Unfortunately, however, there are several disadvantages associated with the present spring finger design. For example, even where a substrate is properly seated in the socket, there is typically poor tactile feedback for indicating a proper insertion. Furthermore, the insertion of a substrate within a socket can generate plastic debris that contaminates the socket.
Still another consideration is the difficulty associated with loading and unloading substrates; if a substrate is misloaded, one or more spring fingers may easily be sheared off, thereby destroying the socket (since spring fingers cannot be repaired or replaced). Even if not destroyed, the spring fingers are still subject to conditions such as wearing, shaving, and thermal fatigue/stress (due to operating temperatures at about 100° C.). In any case, it is also difficult to balance and adjust the spring rates of machined or molded plastic fingers, which are further subject to spring rate variations caused by material anisotropy. Due to the high friction of spring fingers against a substrate edge, a poor centering capability also results.
In view of the above, it would be desirable to overcome the above described shortcomings by configuring a self-centering LGA socket that (among other aspects) provides ease with respect to loading and unloading substrates (i.e., has low friction), as well as good tactile feedback when the substrate is properly seated therein.

Apparatus for implementing a self-centering land grid array socket

International Business Machines Corporation


Ionomers based on ethylene/unsaturated carboxylic acid copolymers are modified with from 0.5 to 15 weight percent adipic acid. The modified-ionomers have improved melt flow and melt processing behavior over unmodified ionomers having a comparable level of neutralization of acid groups present. Certain mechanical properties are improved, particularly stiffness, abrasion resistance and low temperature izod impact. The ionomers modified with adipic acid are in particular suitable for balata ball replacement when formulated as golf ball cover compositions and covers.

1. Field of the Invention
This invention relates to adipic acid-modified-ionomers. The modified-ionomers have improved processability as well as certain improved properties and to golf balls and golf ball covers containing these modified ionomers.
2. Background of the Invention
Copolymers which are dipolymers of ethylene and the unsaturated carboxylic acids methacrylic or acrylic acid, are well known. Commercially such dipolymers typically contain at least about 75 weight percent, and up to about 96 weight percent, ethylene. They are used for molding, packaging and some adhesive applications. Examples of such ethylene/acid-copolymers include those sold under the trade name, Nucrel.RTM., which are produced by E. I. du Pont de Nemours and Company. Such ethylene/acid-copolymers are disclosed in U.S. Pat. No. 4,351,931 (Armitage), the parent disclosure of which was filed in 1961.
Acid-copolymers of this type are also used to prepare `ionomers`, wherein the carboxylic acid units of the copolymers are partially neutralized with metal ions. Such ionomers are sold by E. I. du Pont de Nemours and Company under the trade name Surlyn.RTM.. These resins are thermoplastic in the melt. Partial neutralization is used because fully neutralized acid-copolymers are known to, and are disclosed as having, intractable melts. Ionomers have separate utility and significantly different properties from the non-neutralized ethylene/acid-copolymer `precursors`. Ionomers were first disclosed in U.S. Pat. No. 3,264,272 (Rees). The ions form a sort of `ionic crosslink` bond at low temperatures, but the ions in these ionic crosslink bonds are sufficiently labile at melt temperatures, provided there remain some non-neutralized acid groups, that they allow thermoplastic melt processability. Nevertheless, ionomers are considerably more viscous than their acid-copolymer precursors.
Typically, ionomers are made from acid-copolymer precursor copolymers having a melt index of from about 20 to 300 grams/10 minutes. Neutralization results in an increase in viscosity, or a decrease in melt flow, commonly measured as melt index (MI). Useful ionomers can have a level of neutralization of between 10 and 90 percent, preferably 25 and 75 percent, and their MI falls between 0.1 and about 20 grams/10 minutes, but preferably lower than about 3 grams/10 minutes. The higher the acid-copolymer precursor MI, the higher the MI of the ionomer for a given level of neutralization percent of acid groups neutralized). Higher MI generally allows more ready processing. Nevertheless, many of the attractive properties associated with ionomers compared with acid-copolymers depend on higher levels of neutralization, and hence poorer flow. In addition, lower MI of the acid-copolymer precursor is often more desirable because this relates to the underlying polymeric chain length, which ionic crosslinking does not change significantly. The reality is that neutralization to an MI of 3.0 or less is highly desirable and ionomers with MIs of less than 1.0 have particularly good properties. At these MI levels however, processability is considerably reduced compared with higher MI ionomers.
U.S. Pat. No. 4,104,216 (Clampitt) describes ionomers modified with 5-50 weight percent of a 19-11C long chain (un)saturated fatty acid as `plasticizer`. The product has higher MI, but lower glass transition temperature, and lower stiffness.
Japanese patent application No. 48/70757 discloses ionomers modified with a high level of a low molecular weight saturated or unsaturated carboxylic acid or salt or anhydride, specifically 10 to 500 parts per 100 parts by weight of ionomer. The carboxylic acid may have 1 to 100 hydrocarbon carbon chain units. Stearic, citric, oleic and glutamic acid and/or salts are exemplified. The acid compounds specifically disclosed include 38 carboxylic acids or metal salts, but do not include adipic acid. The useful additives are likened to plasticizers, comparison being made with plasticization of poly(vinyl chloride) having `appropriate flexibility` and improved processability at high temperatures.
There is a need for ionomers which have improved processability and other properties, but which are not plasticized in the sense of reduced modulus and stiffness, and which do not have deficiencies in other properties.
In addition, Synthetic balata is used as a soft cover material for golf balls to provide a soft feel, high spin and good ball control characteristics. It is high cost, requires crosslinking and is deficient in cut resistance, tear strength, yield behavior and scuff resistance. Current ionomer technology using such brands as SURLYN.RTM. by E.I. DuPont de Nemours and Company allows or provides balls with covers having good toughness properties, cut resistance and yield behavior but does not provide the soft feel of balata. There is a need therefore to develop golf ball resins or formulations having all the beneficial properties of ionomer resins currently sold as used for this purpose but which also have the soft "feel" of the balata covered balls. The present invention meets this need by providing a formulation comprising an ethylene acid ionomer which provides good toughness properties, cut resistance and yield behavior and an adipic acid which diminishes the resilience of the composition to provide golf ball covers which mimic the soft "feel" of balata covered golf balls wherein the golf balls do not have any of the disadvantages of the balata covered ball.

Modified-ionomers having improved properties and processability