A liquid crystal display panel including a thin film transistor array substrate structure including, a substrate, a gate line and a data line disposed on the substrate and insulated from each other by a gate insulating pattern, a thin film transistor provided at intersection of the gate and data lines, a protective film disposed to protect the thin film transistor, and a pad structure connected to a respective one of the gate line and data line, the pad structure including a transparent conductive film and a data metal layer; and a color filter array substrate structure joined with the thin film transistor array substrate structure, wherein the protective film is disposed within an area where the color filter array substrate structure overlaps with the thin film transistor array substrate structure, and exposing either the data metal layer or the transparent conductive film along a side portion of the substrate.

1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly, to a liquid crystal display panel and a fabricating method thereof for reducing the number of mask processes as well as preventing a corrosion of a shorting line.
2. Description of the Related Art
In general, a liquid crystal display (LCD) drives a liquid crystal by an electric field formed between a pixel electrode and a common electrode arranged opposite from each other on upper and lower substrates. The LCD controls the application of the electric field across a liquid crystal, and accordingly light transmittance of the liquid crystal, thereby displaying a desired picture.
The LCD includes a thin film transistor array substrate structure and a color filter array substrate that are joined opposite from each other, a spacer for constantly keeping a cell gap between the two substrates, and a liquid crystal filled in the cell gap. The thin film transistor substrate structure comprises of a plurality of signal wirings and thin film transistors, and an alignment film coated thereon for the aligning the liquid crystal. The color filter array substrate structure is comprised of a color filter for implementing a color, a black matrix for preventing a light leakage, and an alignment film coated thereon for alignment of the liquid crystal.
In such a LCD, the thin film transistor substrate structure has a complicated fabrication process involving a semiconductor process that requires a plurality of mask processes. These processes lead to a significantly increased in the manufacturing cost of the liquid crystal display panel. To solve this, a thin film transistor array substrate structure has been developed with a reduced number of mask processes. Since one mask process can accommodate several processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection processes, etc., the total number of mask processes can be reduced. Recently, a four-round mask process, one less mask process from the existent five-round mask process is becoming a standard mask process of the thin film transistor.
FIG. 1 is a plan view illustrating a related art lower transistor array substrate adopting a four-round mask process, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate structure taken along line II–II′ of FIG. 1. Referring to FIGS. 1 and 2, the thin film transistor array substrate structure includes a gate line 2 and a data line 4 provided on a lower substrate 1 intersecting each other and having a gate insulating pattern 12 therebetween. The gate line 2 is provided to apply a gate signal and the data line 4 is provided to a data signal at an intersection structure to define a pixel area 5. Furthermore, the thin film transistor array substrate includes a thin film transistor 30 provided at each intersection, a pixel electrode 22 provided at a cell area defined by an intersection, a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4.
The thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. The thin film transistor 30 allows a pixel signal on the data line 4 to be charged and maintained at the pixel electrode 22 in response to a gate signal from the gate line 2. Further, the thin film transistor 30 includes an active layer 14 overlapping the gate electrode 6 having a gate insulating pattern 12 therebetween to define a channel between the source electrode 8 and the drain electrode 10.
The active layer 14 also overlaps the data line 4 and a lower data pad electrode 62. On the active layer 14, an ohmic contract layer 16 is provided for making a contact with the data line 4, the source electrode 8, with the drain electrode 10 and the lower data pad electrode 62. The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 via a first contact hole 20 passing through a protective film 18 and is provided at a pixel area 5.
Thus, an electric field is formed between the pixel electrode 22 to which a pixel signal is supplied via the thin film transistor 30 and a common electrode (not shown) supplied with a reference voltage. Liquid crystal molecules between the thin film transistor array substrate structure and the color filter array substrate structure rotates due to a dielectric anisotropy induced by such an electric field. Transmittance of a light onto the pixel area 5 is varied depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.
The gate pad 50 is connected to a gate driver (not shown) to apply a gate signal to the gate line 2. The gate pad 50 consists of a lower gate pad electrode 52 extended from the gate line 2, and an upper gate pad electrode 54 connected to the lower gate pad electrode 52 via a second contact hole 56 passing through the gate insulating pattern 12 and the protective film 18.
The data pad 60 is connected to a data driver (not shown) to apply a data signal to the data line 4. The data pad 60 comprises a lower data pad electrode 62 extended from the data line 4, and an upper data pad electrode 64 connected to an upper data pad electrode 64 connected to the lower data pad electrode 62 via a third contact hole 66 passing through the protective film 18.
Hereinafter, a method of fabricating the thin film transistor array substrate structure having the above-mentioned structure adopting the four-round mask process will be described in detail with reference to FIG. 3A to FIG. 3D. Referring to FIG. 3A, a first conductive pattern group including the gate line 2, the gate electrode 6, and the lower gate pad electrode 52 are provided on the lower substrate 1 by the first mask process. More specifically, a gate metal film is formed on the lower substrate 1 by a deposition technique such as sputtering. Then, the gate metal film is patterned by photolithography and etching process using a first mask to form the first conductive pattern group including the gate line 2, the gate electrode 6, and the lower gate pad electrode 52. The gate metal film is made from an aluminum group metal, and the like.
Referring to FIG. 3B, the gate insulating pattern 12 is coated over the lower substrate 1 provided with the first conductive pattern group. Further, semiconductor pattern including the active layer 14 and the ohmic contact layer 16; and a second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, and the lower data pad electrode 62 are formed on the gate insulating pattern 12 by the second mask process.
More specifically, a plurality of layers are sequentially provided on the lower substrate 1. The gate insulating pattern 12, an amorphous silicon layer, a n+ amorphous silicon layer, and a data metal layer are sequentially disposed on the lower substrate 1 provided with the first conductive pattern group formed by the deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc. Herein, the gate insulating pattern 12 is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The data metal layer is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the data metal layer by photolithography using a second mask process. In this process, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion. Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to provide the second conductive pattern group including the data line 4, the source electrode 8, and the drain electrode 10 which is integral to the source electrode 8.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned simultaneously by a dry etching process using the same photo-resist pattern to provide the ohmic contact layer 16 and the active layer 14. The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source/drain metal layer and the ohmic contact layer 16 of the channel portion are etched by the dry etching process. The active layer 14 of the channel portion is exposed to disconnect the source electrode 8 from the drain electrode 10. Then, the photo-resist pattern left on the second conductive pattern group is removed by the stripping process.
Referring to FIG. 3C, the protective film 18 including the first to third contact holes 20, 56 and 66 are formed on the gate insulating pattern 12 provided with the second conductive pattern group. The protective film 18 is entirely formed on the gate insulating pattern 12 by a deposition technique such as the plasma enhanced chemical vapor deposition (PECVD). Then, the protective film 18 is patterned by the photolithography and the etching process using a third mask to define the first to third contact holes 20, 56 and 66. The first contact hole 20 passes through the protective film 18 to expose the drain electrode 10, whereas the second contact hole 56 passes through the protective film 18 and the gate insulating pattern 12 to expose the lower gate pad electrode 52. The third contact hole 66 passes through the protective film 18 to expose the lower gate pad electrode 52. Herein, when a metal having a large dry etching ratio, such as molybdenum (Mo), is used as the data metal layer, the first and third contact holes 20 and 66 pass through the drain electrode 10 and the lower data pad electrode 62, respectively, to expose the side surfaces thereof. The protective film 18 is made from an inorganic insulating material identical to the gate insulating pattern 12, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, the third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 54, and the upper data pad electrode 64 are provided on the protective film 18 by the fourth mask process. More specifically, a transparent conductive film is coated onto the protective film 18 by a deposition technique such as the sputtering, etc. Then, the transparent conductive film is patterned by the photolithography and the etching process using a fourth mask to provide the third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 54, and the upper data pad electrode 64. The pixel electrode 22 is electrically connected to the drain electrode 10 via the first contact hole 20. The upper gate pad electrode 54 is electrically connected to the lower gate pad electrode 52 via the second contact hole 56. The upper data pad electrode 64 is electrically connected to the lower data pad electrode 62, via the third contact hole 66. The transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO) or indium-zinc-oxide (IZO).
As described above, the related art thin film transistor array substrate structure and the fabricating method thereof adopts the four-round mask process, thereby reducing the total number of fabricating processes and hence reducing a manufacturing cost proportional to the fabrication with the five-round mask process. However, since the four-round mask process still has a complicate fabricating process to limit the cost reduction, there has been required a scheme capable of more simplifying the fabricating process to further reduce the manufacturing cost.
Furthermore, as shown in FIG. 4A, the thin film transistor array substrate structure of the related art liquid crystal display panel includes a gate shorting bar 80 connected to the gate pad 50 via a gate shorting line 82, and a data shorting bar 90 connected to the data pad 60 via a data shorting line 92. This feature is included to conduct a quality check to inspect a short and a breakage of the signal line after it was provided by the four-round mask process. As shown in FIG. 4B, when the lower substrate 1 is taken along the scribing line SCL (line crossing through the gate shorting line 82 and the data shorting line 92) after a poor performance of the liquid crystal display panel was detected by the shorting bars 80 and 90, then the gate shorting line 82 and the data shorting line 92 would have been exposed along the side surface of the lower substrate 1. In this case, a metal possessing a poor corrosion resistance, for example, the gate shorting line 82 formed from aluminum or copper, etc. becomes liable for a metal corrosion at a high temperature and in a humid environment. In addition, application of an electric field for driving of the TFT can cause the metal corrosion. These corrosion phenomenon can cause further problems such that the metal corrosion can extend into the gate pad 50 and the data pad 60 as well as the gate line 2 and the data line 4 when given sufficient time.

Liquid crystal display panel and fabricating method thereof


A general framework for cross-validation of any supervised learning algorithm on a distributed database comprises a multi-layer software architecture that implements training, prediction and metric functions in a C++ layer and iterates processing of different subsets of a data set with a plurality of different models in a Python layer. The best model is determined to be the one with the smallest average prediction error across all database segments.

This application relates generally to analyzing data using machine learning algorithms to develop prediction models for generalization, and more particularly to cross validation of machine learning algorithms on distributed database systems.
Companies and other enterprises acquire and store large amounts of data and other information relevant to their operations, generally in large distributed databases. Successful companies may acquire, explore, analyze and manipulate the data in order to search for facts and insights that characterize the data and lead to new business opportunities and leverage for their strategies. Analyzing large amounts of data to gain insight into the data so it may be used for generalization and prediction is a complex task.
One approach to characterizing data is to use supervised learning. Supervised learning is a machine-implemented approach to analyzing a set of representative training data to produce an inferred function or model from the data that can be used with a prediction function for generalization or prediction on another set of similar data. The training data is generally a subset of the data set comprising training samples that are analyzed using a computer executing a supervised learning algorithm to produce the inferred function or model. Different models may be used with the training and prediction functions, and a metric function is used to measure the differences between the values predicted by the prediction function using the models and the actual values. The metric function measures the performance of the models. The supervised learning algorithm creates the models for the data using the training samples. The objective is to produce a model that results in the smallest difference between the predicted values and the real values. However, a supervised learning model typically has parameters that cannot be fitted using the training data through this process, and other methods are needed to fix the values of these parameters.
Cross-validation is an approach for assessing how the results of a statistical analysis will generalize to an independent data set. It is useful in prediction applications to estimate how accurately a predictive model will perform in practice. Cross-validation comprises partitioning a sample of data into complementary subsets, performing an analysis on one subset (called the training set), and validating the analysis on the other subset (called the validation set). To reduce variability, multiple rounds of cross-validation may be performed using different partitions, and the validation results of the multiple rounds averaged.
Supervised learning and cross-validation require processes such as executing training, prediction and metric functions that query languages such as Structural Query Language (SQL) and the like generally cannot perform, and these processes normally cannot run directly within a database. It is desirable to provide systems and methods that afford a framework that operates within a database to execute such functions directly on stored data and produce measurements of model performance for multiple sets of values and for one or more sets of model parameters. It is to these ends that the present invention is directed.

General framework for cross-validation of machine learning algorithms using SQL on distributed systems


A method of batching multiple sets of responses on a server and sending the responses to a client in a single batch (i.e., a “chained” or “packed” batch). The sets of responses may be each be obfuscated and/or compressed. Once the batch is received by the client, each set is processed individually. The client may be configured to communicate the size of an uncompressed set of responses that it can handle. The server may use this information to create sets of responses that are the correct size, and may or may not compress the sets of responses. The server may chain the sets of responses and may continue to chain sets, compressed or not, until the server's buffer is full or close to full. The chained set of responses may then be sent to the client, and may process each of the sets of responses individually.

Email has become an important method for communicating. Email systems typically include a server component (e.g., Microsoft Exchange Server) and a client component (e.g., Microsoft Outlook or Microsoft Outlook Express). These components are typically software applications that are configured to execute on computing devices (e.g., servers, PCs, laptops, and PDAs).
Some types of email servers are configured to allow email to be accessed via an Internet browser client (e.g., Microsoft Internet Explorer) rather than a dedicated email client. In these systems, the browser interacts with the email server, and any functions required to be performed on the client system are performed through the browser (e.g., by downloading Javascript) or through the use of Active Server Pages.
Since clients and servers are often connected by networks that have low bandwidth and high latency (e.g., slow dial-up connections), many email clients and servers are configured to store pending instructions and then send several instructions together. For example, instead of sending an open folder command and sending an open calendar command, a client may store the first instruction and combine it with second instruction and then send the two instructions together. This store, combine, and send scheme tends to allow a more efficient use of network and server resources, since there is some overhead associated with each transmission.
Some prior art systems have relied on a single buffer allocated at each of the client and at the server to act as a data store area for instructions and/or data that are waiting to be sent together. In one example of such a system, the client uses a buffer to store instructions and data that are to be sent to the server. Once the buffer is full or close to being full, the client sends the contents of the buffer to the server. The server stores the received contents into a buffer and begins parsing and executing the instructions. A pointer may be used to designate the next request to be serviced.
The server assembles its responses in its buffer, and ensures that the contents of its buffer do not exceed the size of a client buffer. If the server is unable to complete any requests in its buffer (e.g., because there is not enough room in the buffer), the server writes the uncompleted requests into the buffer and sends them back to the client with the completed responses.
In some systems, the client may be configured to specify how much memory the client is willing to allocate to its buffer. For example, the client may indicate to the server that only 32 KB will be devoted to its buffer. In response, the server will ensure that it does not send the client more than 32 KB at one time.
Given the low bandwidth and high latency nature of the connections used between many email clients and servers, a system and method for improving performance is needed.

System and method for using packed compressed buffers for improved client server communications


A hospital bed has two mechanical drive mechanisms connected between each end of a bed support frame and a base, each of which has a respective actuator. Selective operation of each of the drive mechanisms with the actuators permits either end of the bed support frame to be inclined to the Trendelenburg and reverse Trendelenburg positions at any height of the hospital bed. The drive mechanisms transfer forces for raising and lowering the bed support frame but do not transfer force when the bed is lowered onto an obstacle. When an obstacle is encountered, a switch interrupts operation of its respective actuator.

1. Field of the Invention
The present invention relates to a hospital bed and more particularly to dual drive mechanisms with respective actuators for selectively raising and lowering either end of a hospital bed.
2. Background of the Invention
Many activities and therapies require that a hospital bed be adjustable to different heights, and/or its ends be inclined relative to a horizontal plane so that either the foot of the bed is elevated above the head of the bed, i.e. the Trendelenburg position, or the head of the bed is elevated above the foot of the bed, i.e. the reverse Trendelenburg position. It is further desirable that the Trendelenburg or reverse Trendelenburg positions be achieved at any height of the bed.
U.S. Pat. No. 4,494,259 discloses one apparatus for controlling the height and inclination of either end of a hospital bed. In that disclosure an actuator drives one or two screw and nut drives which may be connected by a clutch. Engaging the clutch couples the screws causing both screws to rotate in unison. The bed is raised or lowered via a linkage mechanism connected between the bedframe and the nuts. Disengagement of the clutch decouples the screws, and one screw and nut drive is operative to raise or to lower a foot end of the bedframe. Consequently, the Trendelenburg position may be achieved by engaging the clutch, fully lowering the bed, disengaging the clutch and raising the foot end of the bed. The reverse Trendelenburg position is achieved by engaging the clutch, raising the bed, disengaging the clutch and lowering the foot end of the bed. Consequently, to move from the Trendelenburg position to the reverse Trendelenburg position or vice versa, it is often necessary to change the height of the bed before its inclination may be changed.
In view of the fact that hospital bed motion must be very slow to accommodate the sensitivities of a patient, this dual motion is inefficient and requires additional personnel time.


An object is to provide a high-frequency plasma generating apparatus and process which can further advance uniformity of the thickness of a film on a substrate with a large area in comparison with conventional apparatuses. In a reaction chamber (1), a ground electrode (3) is disposed, and a discharge electrode (2) is disposed opposite to the ground electrode (3). A substrate (4) as a processing object is placed in close contact with the ground electrode (3). A high-frequency voltage is applied to the discharge electrode (2) so as to generate plasma between the ground electrode and the discharge electrode. An RF electric power supply (15) generates a first high-frequency voltage, and outputs the generated voltage on feeding points (9) disposed on a lateral portion of the discharge electrode (2). An RF electric power supply (16) generates a second high-frequency voltage, and outputs the generated voltage on feeding points (9) disposed on another lateral portion of the discharge electrode (2). Here, the second high-frequency voltage has the same frequency as that of the first high-frequency voltage and has a phase which varies with a low-frequency signal, which is modulated by a predetermined modulation signal.

FIG. 5 shows an example of a conventional high-frequency plasma generating apparatus. FIG. 6 is a cross-sectional view showing a reaction chamber 1 of the same apparatus. The high-frequency plasma generating apparatus shown in these figures can be used for production of a thin film of amorphous silicon semiconductor for solar cells.
The inside of the reaction chamber 1 shown in FIG. 5 and FIG. 6 is equipped with a ladder-shaped electrode 2 as a discharge electrode and a ground electrode 3. The reaction chamber 1 is made gastight, to which a gas supply pipe and an exhaust pipe (both of which are not shown in the drawings) are open at appropriate positions respectively. Through the gas supply pipe, which communicates with a gas supply source, a gas for film formation is introduced into the reaction chamber 1. The exhaust pipe communicates with the suction side of a vacuum pump. The reaction chamber 1 can be evacuated to an internal pressure of about 1 ×10−6 Torr using this vacuum pump.
The ground electrode 3 and the ladder-shaped electrode 2 are disposed opposite to each other at a predetermined distance (for example, a distance of 20 mm). The ground electrode 3 is equipped with a mechanism for holding a glass substrate 4 as a processing object and has a heater built in so as to heat the glass substrate 4. The ladder-shaped electrode 2 needs to be larger than the glass substrate 4 and is a rectangle with the dimensions 1.25 m by 1.55 m when the glass substrate 4 is a rectangle with the dimensions 1.1 m by 1.4 m.
A gas diffusion port of the gas supply pipe is open desirably behind the ladder-shaped electrode 2 (i.e., on the opposite side to the glass substrate 4). Gas is supplied preferably in parallel from several positions.
As shown in FIG. 5, the ladder-shaped electrode 2 is formed by assembling a plurality of parallel longitudinal electrode rods 6 and a pair of transverse electrode rods 7 and 8 into the form of a lattice, and the ladder-shaped electrode 2 is disposed in parallel with and opposite to the glass substrate 4, which is held by the ground electrode 3. Each of transverse electrode rods 7 and 8 of the ladder-shaped electrode 2 is provided with eight feeding points 9. Feeding points 9 of the transverse electrode rod 7 are individually connected to an electric power divider 11, and feeding points 9 of the transverse electrode rod 8 are individually connected to an electric power divider 12. The electric power dividers 11 and 12 are connected to impedance matchers 13 and 14, respectively, by coaxial cables. The impedance matchers 13 and 14 are connected to RF (high-frequency) electric power supplies 15 and 16, respectively. The RF electric power supply 15 is connected to an output portion of an oscillator 17. The RF electric power supply 16 is connected via a phase modulator 21 to the output portion of the oscillator 17. The phase modulator 21 is a circuit which modulates the phase of an output signal S from the oscillator 17 according to output from a sine wave (or triangle wave) oscillator 18, and outputs the modulated signal to the RF electric power supply 16. Here, the output amplitude of the oscillator 18 is constant, and therefore, the phase shift Δθ of modulation by the phase modulator 21 is constant.
With the above structure, the glass substrate 4 on which an a-Si thin film is to be formed is placed on the ground electrode 3 which is set at a temperature of 200° C., for example, then SiH4 gas is introduced at a flow rate of 2 slm, for example, from the gas supply pipe, and the exhaust rate of the vacuum pump system which is connected to the vacuum exhaust pipe is regulated, so as to adjust the pressure inside the reaction chamber 1 to, for example, 40 Pa (300 mTorr). Then, a high-frequency signal of 60 MHz generated by the oscillator 17 is amplified using the RF electric power supplies 15 and 16, and is applied to the transverse electrode rods 7 and 8 of the ladder-shaped electrode 2 through the impedance matchers 13 and 14 and the electric power dividers 11 and 12. This operation generates plasma between the glass substrate 4 and the ladder-shaped electrode 2. At this point, the impedance matchers 13 and 14 are adjusted so that the high-frequency electric power can be efficiently supplied to the plasma generating part. In the plasma, SiH4 is decomposed, and an a-Si film is formed on the surface of the glass substrate 4. An a-Si film with a required thickness can be formed by continuing this film forming operation in this condition for, for example, about 5 to 10 minutes.
However, there is a drawback to the above-described conventional high-frequency plasma generating apparatus in that it is difficult to uniformly form a large area film. This is because a standing wave is generated mainly due to a reflected wave which occurs at an end of an electrode or the like, since the wavelength of the high-frequency wave is about on the same order as the sizes of the electrodes 2 and 3. For example, the wavelength for 60 MHz on the ladder-shaped electrode would be about 3 m. Although the wavelength for 60 MHz in a vacuum is 5 m, the wavelength in plasma is shortened due to increase in capacitance. This wavelength of 3 m gives a ¼ wavelength of about 0.75 m as opposed to the electrode length of 1.25 m, creating maximum and minimum voltage points on the electrode. Therefore, plasma becomes nonuniform following the voltage distribution on the electrode, causing as a result a problem in that a film is formed nonuniformly.
In order to solve such a problem, there are apparatuses as in Japanese Patent Application No. 2001-133830, and there are apparatuses as disclosed in Japanese Patent Application, First Publication (Kokai), No. 2001-274099.
Since an apparatus according to Japanese Patent Application No. 2001-133830 employs a method of high-speed switching between a single-frequency plasma and a double-frequency plasma, plasma changes discontinuously, and a strong plasma is formed in the vicinity of feeding points. Accordingly, there is a limit to obtaining uniformity in the distribution of film thickness, and when a strong plasma exists, the possibility arises that generation of nanoclusters degrades the quality of the film.
On the other hand, an apparatus as disclosed in Japanese Patent Application, First Publication (Kokai), No. 2001-274099 is an apparatus as shown in FIG. 5 with which the phase of the high-frequency applied to the transverse electrode rods 7 and 8 is periodically varied. That is, the phase of output from the RF electric power supply 16 is periodically varied with respect to the phase of output from the RF electric power supply 15 (see FIG. 4 and paragraphs 0091 to 0096 of that publication).

High frequency plasma generator and high frequency plasma generating method


An on-screen calibration system for disc drives and the operating method thereof. The calibration system includes an autocollimator detecting the inclined angle of the stage of a disc drive. A control module is connected to the on-screen display module and a bar code scanner to receive the bar code of the pick-up module and compute a predetermined position data. A monitor displays a moving point according to the inclined angle and a target point according to the predetermined position data through an on-screen display module. The tilt-adjusting mechanism supporting the pick-up module is adjusted to shift the moving point overlapping the target point.

1. Field of the Invention
The present invention relates to a calibration system for disc drives, and in particular to a calibration system using an on-screen display module to calibrate the inclined angle of the pick-up module in disc drives.
2. Description of the Related Art
Pick-up modules are one of the key components in conventional disc drives, such as DVD-ROMs or CD-ROMs. However, when assembling a disc drive, the optical axis of the pick-up module must be parallel, or have a predetermined included angle, relative to the normal angle of an inserted disc, ensuring that the pick-up module can function properly. Thus, conventional disc drives usually have tilt-adjusting mechanisms to calibrate the optical axis of pick-up modules.
FIG. 1 is a perspective view of a conventional disc drive. In FIG. 1, the disc drive has a pick-up module 11 driven by a sliding mechanism 12, a stage 13 driven by a spindle motor and a control PCB 14. The sliding mechanism 12 includes two lead screws 15 arranged in parallel, forming a surface on which the pick-up module 11 moves. The height of one end of a major lead screw can be adjusted, and the other end is fixed. Furthermore, the height of both ends of the other lead screw can be adjusted, such that the sliding surface of the pick-up module 11 can be modified. When a disc is loaded, it is possible that the disc and the sliding surface are not parallel because of the inaccuracy of the spindle motor, or the improper assembly of the lead screws 15. It can cause jitters of 10 μm˜1 mm during disc rotation. Thus, the data received by the pick-up module 11 may have errors.
A conventional calibration method includes two steps. First, the inclined angle and vibration of the disc supported by the stage is adjusted through an autocollimator. Next, the jitter value of RF signals emitted by the pick-up module is tuned through a jitter meter. The jitter value must be lower than a predetermined value to ensure the accuracy of output data. Unqualified disc drives with a jitter value higher than the predetermined value will again be adjusted.
Jitter meters used in the conventional calibration method are easily jammed by external noise. They cannot directly determine the optimum jitter value of each pick-up module, and each pick-up module must be checked several times to ensure product quality.
Moreover, because the reading light paths for CDs and DVDs are different, the jitter values with respect to CDs or DVDs of the same pick-up module are different. Thus, the conventional calibration method individually calibrates the jitter value of CDs and DVDs, thus complicating fabrication. Additionally, the inclined angle of the sliding surface and the jitter value cannot be simultaneously calibrated. Hence, there is a need for a better calibration system, which addresses this problem, and simplifies the conventional calibration method.

On-screen calibration system and operating method thereof


A gesture detecting apparatus prepares time series data of coordinates of specific part of object gesturing, calculates velocity vector of the specific part from the time series data of coordinates, to obtain time-series velocity vectors, detects dynamic periods when displacement per unit time of the specific part is larger than predetermined value, based on the time-series velocity vectors, acquires each representative velocity vector from velocity vectors in each dynamic period, stores the each representative velocity vector corresponding to the each dynamic period in memory, calculates first intersection angle of two representative velocity vectors stored in the memory, the two representative velocity vectors corresponding to two successive dynamic periods, and detects that the motion of the specific part is reciprocating motion when the first intersection angle is larger than first threshold value.

1. Field of the Invention
The present invention relates to a gesture detecting method and apparatus.
2. Description of the Related Art
If human gestures can be automatically recognized, it will be possible to broadly utilize gesture recognition in various fields. Such recognition is applicable to fields such as a household electric appliance which is remotely operated without depending on a remote controller, a user interface of a console terminal, an input interface replacing a keyboard or a mouse, recognition of sign language, an input interface of a game apparatus, and apparatus operation support for a driver.
In a conventional gesture detecting method described in Jpn. Pat. Appln. KOKAI Publication No. 6-12493 (see page 13, FIG. 1), a standard pattern of a gesture to be detected is prepared and stored beforehand, and the stored standard pattern is matched with that of the input gesture to detect the gesture.
A database of the standard pattern has to be prepared, for example, for each user with respect to any gesture to be detected in order to detect the gesture with good precision. Therefore, there has been a problem that great effort is required for the preparation of the standard pattern.
Moreover, even as to the same gesture, if the velocity of a motion is high, pattern matching has to be performed between the standard pattern and the input gesture in consideration of time contraction. Therefore, there has also been a problem that the pattern matching requires a large calculation amount.
Furthermore, there has been a problem that mismatch occurs between the standard pattern and the input gesture by the influence of unexpected noise superimposed upon moving picture data, and erroneous detection of the gesture occurs, even when the standard pattern is prepared with great effort in a case where the motion of a moving specific part is calculated from photographed moving picture data to detect the gesture based on the calculation.
In Jpn. Pat. Appln. KOKAI Publication No. 2000-163196 (see page 10, FIG. 6), a gesture detecting method is described in which no standard pattern is used. In this method, a moving person is regarded as an object, a vertical moving amount of a head is detected, the moving amount is compared with a predetermined threshold value, and it is detected that a nod has been performed in a case where the moving amount exceeds the threshold value.
In this method, even in a case where the object person's head moves as if a V-shaped track were drawn (this cannot be said to be a nod), when the moving amount exceeds a predetermined value in the head's vertical motion, this motion is detected as a nod.
The present invention has been developed in order to solve the above-described problem, and an object is to provide a gesture detecting method and apparatus capable of detecting a gesture from the relationship between velocity vectors of a specific part of an object to robustly detect the gesture with speed and precision.

Gesture detecting method, gesture detecting apparatus, and recording medium


A FAIMS cell has an elongated inner electrode with a longitudinal axis extending along a first direction. The inner electrode has a curved outer surface that defines a circle when viewed in a cross section that is taken in a plane normal to the longitudinal axis, which itself passes through the center of the circle so defined. An outer electrode having an inner surface is disposed in a spaced-apart facing relationship relative to the outer surface of the inner electrode so as to define an analytical gap therebetween. A first ion inlet orifice is defined through a first portion of the outer electrode, and an ion outlet orifice is defined through a second portion of the outer electrode. In particular, the first ion inlet orifice has a first ion injection axis that does not pass through the center of the circle. Furthermore, the second electrode does not have defined through any portion thereof an ion inlet orifice having an ion injection axis that passes through the center of the circle.

High Field Asymmetric Waveform Ion Mobility Spectrometry (FAIMS) is a technology that is capable of separating gas-phase ions at atmospheric pressure. In FAIMS, the ions are introduced into an analytical gap across which a radio frequency (rf) waveform, the magnitude of which is referred to as dispersion voltage (DV), is applied such that the ions are alternately subjected to high and low electric fields. The waveform is asymmetric; the high field is applied for one time unit followed by an opposite-polarity low field of half the high field component that is applied for twice as long. The field-dependent change in the mobility of the ions causes the ions to drift toward the walls of the analytical gap. Since the dependence of ion mobility on electric field strength is compound specific, this leads to a separation of the different types of ions one from the other, and is referred to as the FAIMS separation or the FAIMS mechanism. In order to transmit an ion of interest through FAIMS, an appropriate direct current compensation voltage (CV) is applied to compensate for the drift of the ion of interest toward the analyzer wall. By varying the CV, different ions are selectably transmitted through the FAIMS device.
Different FAIMS electrode geometries are known in the art. One specific type of electrode geometry, which is referred to as the "side-to-side" FAIMS geometry, includes typically a set of overlapping inner and outer electrodes. In particular, the inner electrode often is provided in the form of a circularly cylindrical rod-shaped electrode, whilst the outer electrode has a similarly curved inner surface that is spaced-apart from and facing the inner electrode. The annular space between the inner electrode and outer electrode defines an analytical gap for separating different types of ions one from another, according to the above-mentioned FAIMS mechanism. Ions are produced at an ionization source, such as for instance an electrospray ionization (ESI) source, and are introduced into the analytical gap via one or more ion inlet orifices. Once inside the analytical gap, the ions travel circumferentially in both directions around the inner electrode toward an ion outlet orifice. Some types of ions do not have stable trajectories under the selected combination of CV and DV and are lost due to collisions with an electrode surface, whilst other types of ions are carried to the ion outlet orifice and then out of the analytical gap for subsequent analysis or collection.
A feature that is common to all current side-to-side FAIMS devices, as well as FAIMS devices that are based on some other common electrode geometries, is that at least one ion inlet orifice is defined through the outer electrode in such a way that ion introduction is opposed directly by the electrical field within the analytical gap during one portion of the asymmetric waveform cycle. In fact, the electrical field extends into the ion inlet orifice and accordingly the electrical field begins to influence ion motion even before the ions actually enter the analytical gap. The result is that within the ion inlet orifice, and immediately after the ions enter the analytical gap, the ion trajectories oscillate first directly toward the inner electrode during application of one portion of the asymmetric waveform and then directly away from the inner electrode during application of another portion of the asymmetric waveform. Thus, the ions tend to "jitter" in and out of the analytical gap during introduction, although the net motion is still toward the inner electrode since the ions are also entrained in a flow of a carrier gas. Once inside the analytical gap, the carrier gas flow splits and carries the ions in both directions around the inner electrode. The electrical field continues to induce the same oscillations in the ion trajectories, and only those ions for which the oscillations are compensated by the compensation voltage actually reach the ion outlet orifice.
The above-mentioned "jitter" motion that occurs during ion introduction has a tendency to increase the width of the ion injection window as well as to decrease the ion introduction efficiency. Since one of the advantages of the side-to-side FAIMS device is the short ion flow path length around the inner electrode, and consequently a relatively short ion transit time through the analytical gap, it will be apparent that a longer ion injection window has an adverse effect on the performance of a side-to-side FAIMS device. Accordingly ion inlet configurations, such as those described previously by Guevremont et al. in U.S. Pat. No. 6,753,522 and including three or more separate ion inlet orifices that are arranged in rows or other geometrical arrangements, tend not to result in optimal performance. In particular, each ion inlet configuration disclosed by Guevremont et al. includes at least one ion inlet orifice that is defined through the outer electrode in such a way that ion introduction is opposed directly by the electrical field within the analytical gap during one portion of the asymmetric waveform cycle. This is particularly problematic when the side-to-side FAIMS device is being used to separate or analyze ions on a very short time scale. One such example involves analysis of ions that are generated from samples that are eluting from a high-performance liquid chromatography (HPLC) apparatus, or from another similar chromatographic apparatus.
Of course, the same "jitter" motion also occurs when ions are introduced into FAIMS devices that are based on other electrode geometries. Of particular note is the so-called domed-FAIMS (d-FAIMS) electrode geometry. In a d-FAIMS device, ions enter into an analytical gap between two concentric cylindrical electrodes and spread out in a ring-shaped cloud of finite thickness at a particular radial distance between the two electrodes. The ions travel along the length of the device and are directed radially inward around a domed surface terminus of the inner electrode prior to being extracted via an ion outlet orifice. Since the ions are introduced via an ion inlet in such a way that ion introduction is opposed directly by the electrical field within the analytical gap during one portion of the asymmetric waveform cycle, the d-FAIMS device is expected to show behavior similar to that which has been described above.
Accordingly, there exists a need for a FAIMS cell that overcomes at least some of the above-mentioned limitations.

FAIMS cell having an offset ion inlet orifice


An information processing device includes a housing part; a heating part arranged in the housing part; a cooling unit configured to cool the heating part; an airflow supplying member configured to supply an airflow to the cooling unit; and an airflow limitation member configured to limit the airflow supplied by the airflow supplying member. A part of the cooling unit, the airflow limitation member, and the airflow supplying member are arranged in series. An air intake part is provided in one surface of the housing part so as to intake air into the airflow limitation member. An air discharge part is provided in another surface of the housing part so as to discharge air cooling the part of the cooling unit. An air discharge unit is provided at an air discharge opening provided at one side surface of the airflow limitation member.

1. Field of the Invention
The present invention generally relates to information processing devices and manufacturing methods of the information processing devices, and more particularly, an information processing device having a cooling mechanism for a heating part such as a CPU (Central Processing Unit) and a manufacturing method of the information processing device.
2. Description of the Related Art
Accompanying the spread of the Internet and improvement in CPUs (Central Processing Unit) and the like, a process such as image processing or motion picture processing is frequently performed by using a personal computer or a computer made exclusively for the process. Such a process places a heavy workload on the CPU.
Although performance of the CPU is being improved day by day, if the process for placing the heavy workload on the CPU is continuously performed, the CPU is heated so as to have a high temperature. This causes degradation of the performance of the CPU.
In addition, as the performance of the CPU is improved and the CPU works at a low voltage, consumption of electrical current in the CPU is increased. This causes an increase of temperature of a power control element for supplying electric power to the CPU.
In order to solve the above-discussed problem, Japanese Laid-Open Patent Application Publication No. 2003-108269 discloses the following structure for cooling of electronic parts. That is, a high temperature area contains a CPU, a chip set, a memory, and a graphic board. A low temperature area contains a power supply and drives for driving an external storage medium. The temperature areas are separated by a partition wall. The high temperature area is cooled by a CPU cooling fan, a heat sink and an additional fan, and the low temperature area is cooled by a power supply fan. The partition wall is formed by a riser board and a riser bracket.
However, in the technique disclosed in Japanese Laid-Open Patent Application Publication No. 2003-108269, there is limitation of lay-out when an electronic component is mounted on an SMT (Surface Mount Technology) board. Hence, design freedom of a surface mount design is lost. In addition, Japanese Laid-Open Patent Application Publication No. 2003-108269 does not discuss how hot air dispersed by a CPU cooling fan is discharged to the outside of the computer.
Furthermore, the power control element requires controlling a large amount of electric current. For example, approximately 100 A may be required for the operation of recent CPUs. Such a power control element may be required to be arranged in the vicinity of the CPU so that there is little influence of impedance of a wiring pattern. Effective heat transfer from these elements may be required.

Information processing device and manufacturing method of the information processing device


In an embodiment, a rotorcraft includes an airframe; a main rotor transmission; one or more brackets mounting the main rotor transmission to the airframe, longitudinal axes of the one or more brackets being substantially parallel with a longitudinal axis of the rotorcraft; and one or more restraints mounting the main rotor transmission to the airframe, the one or more restraints being mounted at an angle non-orthogonal to the longitudinal axis of the rotorcraft and a lateral axis of the rotorcraft.

A rotorcraft may include one or more rotor systems including one or more main rotor systems. The main rotor system generates aerodynamic lift to support the weight of the rotorcraft in flight and thrust to move the rotorcraft in forward flight. The main rotor system may generate noise, vibration, and energy, which may result in discomfort for passengers, wear to components of the rotorcraft, and the like. For smooth, quiet flight and increased longevity of rotorcraft components, a pylon restraint system may isolate the main rotor system from an airframe of the rotorcraft SUMMARY
In accordance with an embodiment, a rotorcraft includes an airframe; a main rotor transmission; one or more brackets mounting the main rotor transmission to the airframe, longitudinal axes of the one or more brackets being substantially parallel with a longitudinal axis of the rotorcraft; and one or more restraints mounting the main rotor transmission to the airframe, the one or more restraints being mounted at an angle non-orthogonal to the longitudinal axis of the rotorcraft and a lateral axis of the rotorcraft. In an embodiment, the one or more restraints are mounted to the airframe at an angle from 32° to 40° to the lateral axis of the rotorcraft. In an embodiment, the one or more restraints have a stiffness from 6552 lbs/in to 8008 lbs/in. In an embodiment, each of the one or more brackets is attached to the airframe through a spherical bearing. In an embodiment, the one or more restraints have a total travel from ½ inch to 1 inch. In an embodiment, a height between a central axis of the one or more restraints and a bottom surface of the main rotor transmission is from 0.69 inches to 0.85 inches. In an embodiment, the one or more restraints provide a stiffness in a roll plane less than a stiffness in a pitch plane. In an embodiment, the one or more restraints include two restraints, and the one or more restraints provide stiffness in a roll plane and a pitch plane.
In accordance with another embodiment, a system includes a rotor hub; a plurality of rotor blades attached to the rotor hub; a transmission coupled to the rotor hub; and a transmission mounting assembly for mounting the transmission to an airframe, the transmission mounting assembly including one or more brackets; and one or more restraints, the one or more restraints being mounted to the transmission and the airframe at an angle between 0° and 90° with a lateral axis of the airframe. In an embodiment, the one or more restraints include one or more elastomeric restraints. In an embodiment, each restraint of the one or more restraints has a travel from ¼ inch to ½ inch in a direction parallel to a longitudinal axis of the airframe and a travel from ¼ inch to ½ inch in a direction parallel to the lateral axis of the airframe. In an embodiment, the angle is from 32° to 40°. In an embodiment, the transmission mounting assembly includes four brackets and two restraints. In an embodiment, a longitudinal axis of a first bracket and a longitudinal axis of a second bracket of the one or more brackets meet at a virtual focal point, and a first restraint of the one or more restraints is mounted to the transmission at a point from 10.2 inches to 12.5 inches below the virtual focal point.
In accordance with yet another embodiment, a method for determining parameters for a transmission restraint in a rotorcraft includes determining a plurality of inputs for a main rotor system, the main rotor system including a rotorcraft fuselage, a rotorcraft transmission, and a rotorcraft hub; solving equations of motion for the main rotor system to determine a spring rate for a restraint used to attach the rotorcraft transmission to the rotorcraft fuselage; calculating a distance between an attachment point of the restraint on the rotorcraft transmission and a virtual focal point of two brackets used to attach the rotorcraft transmission to the rotorcraft fuselage based on the spring rate; and calculating an angle of restraint between the restraint and the rotorcraft fuselage based on the spring rate and the distance, the angle of restraint being between 0° and 90°. In an embodiment, the spring rate is from 6552 lbs/in to 8008 lbs/in. In an embodiment, the distance is from 10.2 inches to 12.5 inches. In an embodiment, the angle of restraint is from 32° to 40°. In an embodiment, the plurality of inputs include a distance from a center of gravity of the hub to a center of gravity of the pylon, a distance from the center of gravity of the pylon to a center of gravity of the fuselage, a weight of the hub, a weight of the pylon, and a weight of the fuselage. In an embodiment, the restraint has a stiffness in a roll plane of the rotorcraft from 5367 lbs/in to 6559 lbs/in and a stiffness in a pitch plane of the rotorcraft from 3758 lbs/in to 4594 lbs/in.


The present invention provides a gas diffusion layer for a fuel cell which has proper rigidity, is easy to handle and contributes to the improvement of the productivity of fuel cells. A method for producing a gas diffusion layer for a fuel cell including a first step of: impregnating a conductive porous substrate made of a conductive carbon fiber cloth or conductive carbon fiber felt with a first dispersion containing a first fluorocarbon resin having thermoplasticity; and baking the first conductive porous substrate at a first baking temperature of not less than the melting point of the first fluorocarbon resin and less than the decomposition temperature of the first fluorocarbon resin to enhance the rigidity of the conductive porous substrate.

The present invention relates to methods for producing a gas diffusion layer, an electrode and a membrane electrode assembly for a polymer electrolyte fuel cell, and to a gas diffusion layer, an electrode and a membrane electrode assembly produced by the aforesaid methods.
Conventional polymer electrolyte fuel cells using a cation (hydrogen ion) conductive polymer electrolyte membrane simultaneously generate electricity and heat by electrochemically reacting a fuel gas containing hydrogen and an oxidant gas containing oxygen such as air.
FIG. 17 is a schematic cross sectional view illustrating a basic structure of a unit cell designed to be mounted in a conventional polymer electrolyte fuel cell. FIG. 18 is a schematic cross sectional view illustrating a basic structure of a membrane electrode assembly designed to be mounted in the unit cell 100 shown in FIG. 17. As shown in FIG. 18, in a membrane electrode assembly 101, on each surface of a polymer electrolyte membrane 111 capable of selectively transporting hydrogen ions is formed a catalyst layer 112, which is composed of carbon powder carrying an electrode catalyst such as a platinum metal catalyst thereon and a hydrogen ion conductive polymer electrolyte.
As the polymer electrolyte membrane 111, polymer electrolyte membranes made of perfluorocarbonsulfonic acid such as Nafion (trade name) manufactured by E.I. Du Pont de Nemours & Co. Inc., USA are currently widely used. On the outer surface of the catalyst layer 112 is formed a gas diffusion layer 113 made of a conductive porous substrate such as carbon paper, carbon cloth or carbon felt, which has been previously treated for water repellency. The combination of the catalyst layer 112 and the gas diffusion layer 113 forms an electrode 114 (fuel electrode or oxidant electrode).
A conventional unit cell 100 is composed of a membrane electrode assembly 101, gaskets 115 and a pair of separator plates 116. The gaskets 115 are placed on the outer periphery of the electrodes with the polymer electrolyte membrane sandwiched therebetween so as to prevent the supplied fuel gas and the supplied oxidant gas from leaking out and to prevent them from mixing with each other. The gaskets are usually integrated in advance with the electrodes and the polymer electrolyte membrane, and the whole is sometimes called "membrane electrode assembly".
On the outer surfaces of the membrane electrode assembly 101 are placed a pair of separator plates 116 for mechanically fixing the membrane electrode assembly 101. On the surface of the separator plate 116 in contact with the membrane electrode assembly 101 are formed gas channels 117 for supplying a reaction gas (fuel gas or oxidant gas) to the electrode and removing a gas containing an electrode reaction product and unreacted reaction gas from the reaction site to the outside of the electrodes. Although the gas channels 117 may be formed independently of the separator plate 116, they are usually formed by providing grooves on the surface of the separator plate as shown in FIG. 17.
As described above, the unit cell is formed by fixing the membrane electrode assembly 101 with the pair of separator plates 116. By supplying the fuel gas to the gas channels of one of the separator plates and the oxidant gas to those of the other of the separator plates, the unit cell can produce an electromotive force of about 0.7 to 0.8 V at a practical current density of several tens to several hundreds mA/cm2. Polymer electrolyte fuel cells, when used as power sources, are usually required to produce a voltage of several to several hundreds volts. For this reason, in practice, the necessary number of the unit cells are connected in series and clamped to give a stack for use. In the production thereof, in order to prevent gas leakage, etc, the stack of unit cells is clamped by applying a certain clamping pressure to the stack.
The gas diffusion layer 113 constituting the electrode 114 for a conventional polymer electrolyte fuel cell as described above mainly has the following three functions: (1) to diffuse a reaction gas such as a fuel gas or an oxidant gas so as to uniformly supply the reaction gas from the gas channels 117 formed outside the gas diffusion layer 113 to the catalyst in the catalyst layer 112; (2) to rapidly carry away water produced by the reaction in the catalyst layer 112 to the gas channels 117 to prevent water clogging (flooding); and (3) to transfer the electrons necessary for the reaction and the produced electrons. As such, the gas diffusion layer 113 is required to have high reaction gas permeability, high water permeability and high electron conductivity.
In order to meet such demand, in a conventional technique, gas permeability is imparted by allowing the gas diffusion layer to have a porous structure. Water permeability is imparted by dispersing a water repellent polymer as typified by fluorocarbon resin in the gas diffusion layer. Electron conductivity is imparted by using an electron conductive material such as carbon fiber, metal fiber or carbon fine powder to make the gas diffusion layer.
In view of the above, a typical gas diffusion layer is formed by coating carbon paper serving as a conductive porous substrate with fluorocarbon resin and forming a conductive water repellent layer on the catalyst-layer-side surface of the carbon paper as described in, for example, Japanese Laid-Open Patent Publication No. Hei 2-295065. The fluorocarbon resin coating is carried out to ensure water repellency for a long period of time. The conductive water repellent layer is formed to prevent an ink for forming a catalyst layer from filling and clogging the pores when a catalyst layer is formed.
In stead of carbon paper, there is a method using carbon cloth or carbon felt as the conductive porous substrate for gas diffusion layer in order to improve the properties and to achieve low cost production, as described in Japanese Laid-Open Patent Publication No. 2002-56851. In this method, a conductive porous substrate is treated for water repellency by immersing the conductive porous substrate in a water repellent agent containing a surfactant, and then drying the conductive porous substrate at a temperature at which the surfactant is not removed. A conductive water repellent layer is then formed on the aforesaid conductive porous substrate, followed by baking.
As previously mentioned, in the production of the stack, a certain clamping pressure is applied to the stack of unit cells to prevent gas leakage. When carbon paper is used as the conductive porous substrate as described above, the above-described carbon paper hardly changes in shape during the production of the stack because the carbon paper is rigid enough. Accordingly, no problem occurs during the operation of the fuel cell to be obtained.
The carbon paper, however, is excessively rigid, so the handling thereof itself is troublesome. For example, the mass productivity and the cost efficiency might be reduced when the handling of the carbon paper during the production process is difficult. Moreover, the carbon fibers constituting the carbon paper are two-dimensionally oriented, that is, oriented in the surface direction of the carbon paper. To be more specific, they are oriented in the same direction as the flowing direction of the reaction gas in the gas channels 117 of the separator plate 116. For this reason, the flow of water moving in the thickness direction of the gas diffusion layer 113, that is, the water flow from the catalyst layer 112 to the gas channels 117 of the separator plate 116, does not go smoothly, causing water to stay and collect, which makes it likely to cause flooding.
In some cases, carbon cloth or carbon felt is used as the conductive porous substrate for constituting the gas diffusion layer 113 for purposes of optimal water repellency, low cost production, process rationalization and the improvement of productivity.
Carbon cloth and carbon felt, however, have the drawback that the carbon fibers thereof are three-dimensionally oriented and therefore micro short-circuiting is likely to occur. Moreover, when the gas diffusion layer 113 is formed using carbon cloth or carbon felt, the gas diffusion layer 113 hangs down into the gas channels 117 of the separator plate 116 since carbon cloth and carbon felt are highly flexible and not rigid enough. The hanging down of the gas diffusion layer 113 causes a greater variation in pressure loss in the gas channels 117, which makes it likely to cause flooding.
There is also a problem when forming a conductive water repellent layer on the surface of the conductive porous substrate constituting the gas diffusion layer 113. The problem is that the ink for forming a conductive water repellent layer is impregnated into the conductive porous substrate, which might inhibit the gas diffusibility of the produced gas diffusion layer 113.
Moreover, it is generally considered that, in order to improve water repellency of the water repellent layer, heat treatment, i.e., baking at a temperature exceeding the melting point of the water repellent material contained in the ink for forming a water repellent layer is desirable. But when polytetrafluoroethylene (PTFE) of high molecular weight is used as the water repellent material, the problem also arises that the baking at a temperature exceeding the melting point of PTFE reduces the adhesive strength, the ease of handling and the mass productivity, and that the conductive water repellent layer is peeled and separated from the electrode, which makes it likely to cause flooding.

Gas diffusion layer, electrode and membrane electrode assembly for fuel cell, and production methods thereof

Matsushita Electric Industrial Co., Ltd.


An endoscope includes: an objective optical section including a first barrel; an image pickup optical section including a solid image pickup device, an optical member forming an optical image through the objective optical section on an image pickup surface of the solid image pickup device, and a second barrel housing the optical member and the solid image pickup device, the second barrel fixed to the first barrel after positional adjustment in an axial direction relative to the first barrel; a holding member formed of material having a linear expansion coefficient lower than linear expansion coefficients of the first and second barrels, and fixed to outer surfaces of the first and second barrels; a first adhesive that bonds the first barrel and the second barrel; and a second adhesive having a bonding strength higher than that of the first adhesive, which bonds the holding member to the first and second barrels.

1. Field of the Invention
The present invention relates to an endoscope that includes a first barrel and a second barrel in an image pickup optical system.
2. Description of the Related Art
Conventionally, endoscopes are used in, e.g., an industrial field and a medical field. With an endoscope, observation is performed by inserting an elongated insertion portion into, e.g., a structure or a living body. In general, in a distal end portion included in an insertion portion, an illumination optical system and an image pickup optical system included in an observation optical section are incorporated. The illumination optical system illuminates an inside of the structure or an inside of the living body. The image pickup optical system shoots an image of the inside of the structure or the inside of the living body illuminated by the illumination optical system.
The image pickup optical system includes, for example, an objective optical section and an image pickup optical section, and after focusing adjustment, the objective optical section and the image pickup optical section are integrally fixed. More specifically, the objective optical section includes a plurality of optical lenses and a first barrel, which is a lens barrel.
In the first barrel, the plurality of optical lenses is housed and fixed. The image pickup optical section includes a solid image pickup device, such as a CCD or a C-MOS sensor, and a second barrel, which is a device barrel. In the second barrel, the solid image pickup device is housed and fixed. Then, the lens barrel in the objective optical section and the device barrel in the image pickup optical section are fitted together. Then, focusing is performed by adjusting positions in an axial direction of the lens barrel and the device barrel. After completion of the focusing, the lens barrel and the device barrel are integrally fixed to form the image pickup optical system.
For example, Japanese Patent Application Laid-Open Publication No. 2006-267166 discloses an objective section of an endoscope. In the objective section of the endoscope, two objective barrels that incorporate objective members for forming an optical image of an object (corresponding to barrels in the present invention) can be bonded and adhered to each other in an air-tight manner without a decrease in optical performance. In Japanese Patent Application Laid-Open Publication No. 2006-267166, a covering that covers the entire outer circumferential faces of boundary portions of the two objective barrels with no space is provided in such a manner that the covering extends across both of the outer circumferential faces of the two objective barrels, and then, the two objective barrels and the covering are adhered to each other in an air-tight manner via brazing, soldering or welding.

Endoscope having adhesives with different bonding strengths


A method of fabricating a semiconductor device includes an exposing process in which a lower pattern is formed by a first exposing process and an upper pattern is formed thereon by a second exposing process, wherein the exposure process includes the steps of obtaining a first correction value representing a difference of first and second alignment error correction parameter preset values respectively used at the time of a first exposing process of exposing the lower patterns in a current lot and in a just-before lot, obtaining, as a second correction value, an optimum correction amount of a third alignment error correction parameter preset value needed for proper alignment of the upper pattern in the second exposing process of the just-before lot, the third alignment error correction parameter has been used in the second exposing process of the just-before lot for exposing the upper pattern, and obtaining an optimum correction parameter prediction value to be used for exposing the upper pattern in the second exposing process of the current lot, from the first correction value and the second correction value.

The present invention generally relates to fabrication of semiconductor devices and more particularly to the technology of alignment of exposure apparatus.
With increasing speed and functional diversity of semiconductor devices, extremely miniaturized patterns are formed nowadays on the surface of semiconductor wafers. Associated with this, there exists an increasing demand for more accurate alignment in the photolithographic process, particularly in the exposure step of semiconductor wafers conducted by using an exposure apparatus.
In the fabrication process of semiconductor devices, it has been practiced to achieve alignment of semiconductor patterns with regard to an underlying semiconductor pattern at the time of exposure process by measuring the coordinate of alignment marks formed in each of the chip regions arranged in rows and columns on a semiconductor wafer.

Fabrication method of semiconductor device


A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a semiconductor including an element isolating region and a method for manufacturing such a semiconductor device.
In a semiconductor device of the prior art, an element such as a bipolar transistor is formed by performing an element isolation process. Such a bipolar transistor is formed on a substrate with an embedment layer having a high impurity concentration. Known element isolation processes include isolation of elements with a field oxidation film, which is formed by performing local oxidation of silicon (LOCOS), and formation of a deep trench to isolate a high concentration impurity layer in a substrate. When a field oxidation film is formed by performing LOCOS, in addition to the flatness of the surface of an element isolating region decreasing, the area of the element isolating region is increased due to a "bird's beak" that occurs during the formation of the field oxidation film. This makes it difficult to further miniaturize such a semiconductor device.
Accordingly, Japanese Patent No. 3382063 proposes shallow trench isolation (STI) that enables the formation of a flat and miniaturized element isolating region.
FIG. 14 is a cross-sectional view showing a semiconductor device including an element isolating region formed by performing STI in the prior art. In FIG. 14, an N+ embedment layer 102 and an N-type epitaxial silicon layer 103 are formed on a silicon substrate 101. An STI trench is formed in the N-type epitaxial silicon layer 103. An insulative film 104 is formed on the inner surface of the STI trench. The STI trench is filled with an embedment film 105. A deep trench formed in the STI trench has a depth reaching the silicon substrate 101. An insulative film 106 is formed on the inner surface of the STI trench. The deep trench is further filled with an embedment film 107.
In the STI technique of the prior art, each corner in the STI trench and the deep trench (opening edge 200a of the STI trench, bottom edge 200b of the STI trench, boundary edge 200c between the STI trench and the deep trench, and bottom edge 200d of the deep trench) is rounded. Further, the insulative films 104 and 106 have about the same thicknesses.
The rounded corners (200a, 200b, 200c, and 200d) of the STI trench and the deep trench prevent the concentration of stress, which results from the shape of the element isolation structure, from causing defects. However, when forming a further miniaturized semiconductor device, heat treatment, which is performed when forming an insulative film on the inner surface of the STI trench or deep trench, may diffuse impurities from the N+ embedment layer 102 to positions close to the surface. This would deteriorate the transistor characteristics.
When the N+ embedment layer 102 is exposed from the deep trench, the impurities of the N+ embedment layer 102 is diffused outwards through the deep trench. This would lower the concentration of the impurities in the N+ embedment layer 102 and increase the collector resistance. Thus, when forming an insulative layer on the inner surface of the STI trench and on the inner surface of the deep trench, the prevention of defects resulting from the corners in the STI and deep trenches and the prevention of impurity diffusion from the N+ embedment layer 102 must both be performed at the same time.
In the element isolation structure of the prior art STI technique, the thicknesses of the insulative film on the inner surfaces of the STI trench and the deep trench are about the same. Thus, when preventing the occurrence of defects near the STI trench while rounding the corners of the deep trench, the heat treatment for forming the insulative layer on the inner surface of the deep trench increases the diffusion of impurities from the N+ embedment layer 102. When preventing the diffusion of impurities from the N+ embedment layer 102 during the formation of the insulative film on the inner surface of the deep trench, the corners, especially, those of the STI trench, cannot be sufficiently rounded. Thus, the occurrence of defects cannot be prevented. The corners of the STI trench are covered by the insulative film during the formation of an insulative film on the inner surface of the deep trench. Thus, it would be difficult for stress to be released from such corners. In such a case, stress is accumulated at the corners when forming the insulative film on the inner surface of the deep trench. This would increase the tendency of a defect occurring at a corner of the STI trench.

Semiconductor device and method for manufacturing semiconductor device


The present invention relates to methods and arrangements of controlling an uplink data rate between a user equipment and a communication network node, which are communicating with each other on uplink and downlink data channels over a radio interface. A scheduler is arranged to distribute available scheduling headroom, provided by an uplink load control unit, between user equipments which are to be scheduled. A scheduling grant signalling is sent from the communication network node to the user equipment, based on which the user equipment is able to select a transport format combination (E-TFC).

Load control and scheduling are two key functions to manage the radio resources in wideband code division multiple access (WCDMA) systems. The scheduler distributes the radio resource among user equipments (UEs) while the load control estimates the available scheduling headroom that the scheduler may use. This is illustrated in FIG. 2, which shows the prior art procedure of scheduling. The uplink load control provides the Enhanced uplink (EUL) scheduler with the total scheduling headroom for a cell. The scheduler selects the user equipment(s) to be scheduled and distributes the available scheduling headroom among the selected user equipment(s) (step 20). The scheduler then maps the scheduling headroom to power offset or enhanced transport format combination (E-TFC) for each UE to be scheduled (step 21). The scheduler then signals the scheduling grants in terms of maximum E-TFC or power offset to the UEs via a scheduling grant signalling (step 22). The UEs select a suitable E-TFC below the granted E-TFC (step 23). The radio base station (RBS) measures the cell rise over thermal (ROT) and carrier-to-interference ratio (CIR) and inputs the measurements to the uplink load control, which adjusts the maximum scheduling headroom based on the received measurements (step 24) and provides the scheduler with this adjusted scheduling headroom, and so on.
In the uplink, the common radio resource shared among the user terminals is the total amount of tolerable interference, which is defined as the average interference over all the antennae. A relative measure of total interference is rise over thermal (ROT), i.e. the total interference relative to thermal noise.
Load factor represents the portion of uplink interference that a certain channel of a certain user terminal generates, which is defined as the interference due to the channel of that user terminal divided by the total interference. The total load factor of different channels equals to the sum of load factors due to different channels.
The uplink load control estimates the resource utilization in terms of cell load generated by different type of traffic and channels of each cell based on measurements, such as, rise over thermal and CIR; the load control also regulates the maximum available scheduling headroom that the scheduler can use to schedule user equipments for transmitting data in the cell.
The scheduler distributes the available scheduling headroom among the user equipments which have data to transmit, either one at a time, time division multiplexing (TDM) scheme, or several at a time, code division multiplexing (CDM) scheme. The scheduler determines when a certain user equipment is allowed to transmit and at what maximum data rate. In the existing scheduling framework, two scheduling grants, absolute grants and relative grants are used to control data transmission limit of each user equipment. The data transmission limit is expressed in terms of the maximum E-TFC. The E-TFC for different data rate is formulated by power offset between the enhanced dedicated physical data channel (E-DPDCH) and dedicated physical control channel (DPCCH), as shown in equation (1):pwroffgrant—estk=f(loadavik,loadDPCCH—estk,loadsched—estk)  (1)wherein:                pwroffgrant—estk is the (estimated) maximum power offset that can be granted for user k;        loadavik is the available scheduling headroom for user k;        loadDPCCH—estk is the (estimated) DPCCH load from user k; and,        loadsched—estk is the (estimated) load from the channel(s) that are already scheduled for user k.
The scheduler signals the scheduled user equipment with the maximum E-TFC or the maximum power offset via scheduling grant. To determine the scheduling grants, the uplink load generated by each scheduled user equipment needs to be estimated.
The uplink load may be estimated based on carrier-to-interference ratio (CIR) measurements. Suppose user k has N uplink channels, the load generated by the user equipment can be calculated by equation (2):
                              Load          i_est          k                =                                            CIR                              1                                _meas                            k                        ·                          pwroff              i_est              k                                                          loadpar              1                        +                                          loadpar                2                            ·                              CIR                                  1                                    _meas                                k                            ·                              (                                  1                  +                                                            ∑                                              i                        =                        2                                            N                                                                                pwroff                      i_est                      k                                                                      )                                                                        (        2        )            wherein:                CIR1—meask is the (measured) CIR of the 1st channel from user k;        pwroffi—estk is the (estimated) power offset between the ith channel and the first channel of user k;        loadpar1 is the first load estimation parameter; and,        loadpar2 is the second load estimation parameter.
The load parameters are system parameters selected by the radio network controller (RNC).
In the existing solution the scheduler controls the user equipment data rate by limiting the maximum E-TFC. To estimate the maximum E-TFC for a user equipment, the load generated by each user equipment in the cell needs to be estimated. There are several problems for EUL scheduler to estimate the load in the previously known systems:                Due to the inner-loop power control, the DPCCH power used by a user equipment may vary quite a lot from the time when the EUL scheduler estimates the load to the time when the grant is used by the user equipment;        The load generated by the granted E-TFC can be completely different from the load that was estimated at EUL scheduler;        Another difficulty for EUL scheduler is to take into account individual receiver type of EUL user equipments when the load of a granted E-TFC is estimated, since the impact of self-interference is not negligible.
The inaccuracy in the load estimation causes large oscillations in the actual cell load or rise over thermal; To ensure stability of the system, a large load margin is introduced to prevent the instability. However, it is difficult to configure the load margin for all different scenarios. A conservative large load margin may result in inefficiently utilization of resource while a small load margin may cause large oscillations in rise over thermal, both have negative impact on the system throughput.
The addressed problems may be mitigated by:                Dynamically adapting the load parameters according to the temporary radio environment.        Power based load estimation (according to the original definition of load factor), where the load factor due to the ist channel of user k is estimated as:
                              Load          i_est          k                =                              pwr            i_meas            k                                Itot            meas                                              (        3        )                            The variation in radio environment, etc. is automatically reflected in the wide band received power. This is because the uplink (inner loop) power control always tries to adjust the user equipment power so that the perceived CIR at the base station is close to the CIR target. The level of received power will however, depend on the receiver scheme, data rate and radio environment.        Introducing another inner power control loop to control the total received power. This inherently avoids oscillation in rise over thermal even with fixed load parameters.
However, for all the schemes a precondition to achieve evident performance gain (both increased throughput and decreased rise over thermal oscillation) is that system delay is small and scheduling as well as load estimation are performed sufficiently frequently (especially when with high target rise over thermal). This is because with large system delay the load may vary a lot from the time when the EUL scheduler determines the power offset (E-TFC) that can be granted to the time when the granted E-TFC is used by the user equipment. This may lead to distinct load estimation error at the time the grant is used by the user equipment, even though the load is accurately estimated at the time the EUL scheduler issues the grants. Thus, the benefits of these schemes are decreased.
On the other hand, decreasing system delay is not an easy task when signaling procedure is involved, and more frequent execution of scheduling implies higher signaling overhead, especially for the third alternative addressed above, where two power control loops are needed.

Methods and arrangements in a communication network system


A lifting device comprises three or more links hingedly joined end-to-end such that the lifting device is able to hingedly move in a first direction from a linear arrangement to a bent arrangement but is not able to hingedly move from the linear arrangement to a bent arrangement in a second direction opposite the first direction.

Conventional pallet movement and loading is accomplished using forklift trucks or similar forked machines. These machines must pick up and deposit pallets on flat surfaces, as even the slightest vertical obstruction can prevent its use. This limitation presents problems when a palletized load needs to be loaded onto a vehicle or trailer that has side walls, even if the side walls are relatively short.
In large scale operations (e.g., ship yards, train yards, warehouses, distribution hubs, etc.), craning and other overhead solution are available because space and lifting capacity are much greater. However, in small scale operations (e.g., big box home improvement stores, retail or wholesale building supply stores, retail or wholesale landscaping material (e.g., stone) suppliers, etc.), employees must find a way to load palletized products onto customers' vehicles or trailers without damaging the vehicle or the load.
It is known to try to overcome this limitation by the use of simple slings, straps, or ropes affixed to the pallet and to the forks of the forked machine. However, slings, straps, and ropes can damage the pallets and destabilize the loads, making the use of these items dangerous. For small quantity pallet loading (e.g., 1-3 pallets), palletized loads are often hand loaded from the pallet onto the vehicle/trailer due to the forked machines' limitations. Such hand loading subjects people to injuries to hands, feet, backs, shoulders, etc., and exposes the palletized materials to damage. It is also known that employees may ignore the limitations of the forked machines and simply try to load the pallet directly onto the receiving vehicles (e.g., customers' vehicles/trailers), thereby risking damage to the receiving vehicles.


A method and system for capturing and reporting debug information regarding data transport failures in a multi-level secure operating environment. A process available only to a trusted system administrator is activated causing probe activation. The data transport command is repeated. The process probes the locations where the data packets move across environment boundaries of the secure network. When the data stops being transported, the process captures the relevant information on the type of failure, its cause, the address where it occurred and the possible consequence. The captured information can then be displayed to an appropriately credentialed administrator through a password-protected command for debug. The probes are then deactivated.

1. Field of the Invention
The present invention relates to the field of multi-level secure operating environments. Specifically, an embodiment of the present invention relates to a method and a system for diagnosing data transport failures in a multi-level secure operating environment.
2. Related Art
Over the past few decades, computer systems have become corporate-wide resources, essential for day-to-day operations. A wide range of information on new products, engineering data, employee compensation, health records, marketing and sales plans, and other sensitive data is often stored on these systems. Considerable cost, damage, and loss can be caused by hostile or unauthorized access and use of this sensitive information.
In order to control external access, firewalls and other systems are often used as gatekeepers. One method available for providing extensive internal protection against intruders and misuse is the multi-level secure operating environment. This environment allows system administrators to limit access to system and data resources by setting controls on all potential interactions with programs, file access, and utilities on a user-by-user basis.
Since information can have many levels of sensitivity, it is assigned a classification based on its sensitivity level. Within the multi-level secure operating environment, there exist controls that track information, which is assigned a classification to assure that the information, reaches only those destinations that are cleared for the same classification. There are various access controls used throughout the population of multi-level secure operating environments. One example of a multi-level secure operating environment control is a label-based access control that is automatically enforced by the system. In the case of label-based access controls, each data packet contains a label carrying information about the classification of the data in the packet and also the credentials or privileges of the process that generated the data.
There are some locations, e.g., users, within a distributed environment that have clearance to see information with a particular classification and some that are not. This is dependent upon the level of trust that has been assigned by a system administrator to each location within the environment. Therefore, there are instances in which a data packet never reaches its destination, not because of a hardware connectivity problem, but due to a security requirement that the data carries and for which the destination is not cleared. In a case of such a data transport failure, there is no "error" and, therefore, no error message generated. The system is not allowed to return a message regarding the data sensitivity issue that halted the data transport because such a message in itself constitutes sensitive information (e.g., a lower classified level can send information to a higher level, but cannot receive information back from the higher classified level). This creates a very difficult problem for the system administrator to diagnose. The troubleshooting paths, which a system administrator typically follows, will reveal no problem if the issue is not one of connectivity. Therefore there is no apparent way to determine what went wrong with the data packet.

Diagnosability enhancements for multi-level secure operating environments