A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing-rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation. The multi-branch chemical dispensing unit provides a flexible, modular building block for constructing various equipment configurations that use multiple chemical treatments and/or pH neutralization steps.

Technical Field
The present disclosure relates to wet cleaning processes and equipment and, in particular, to wet cleaning of integrated circuit wafers in the semiconductor industry following chemical-mechanical polishing (CMP).
Description of the Related Art
Wet chemical processing and wet cleaning are frequently executed steps used to fabricate integrated circuits on semiconductor wafers. In particular, various types of wet chemical processes typically are used to etch wafers, to clean wafers following etching, to polish wafers, and to clean wafers following polishing. Wet processing equipment used in all four of these operations generally is designed to include multiple processing modules such as one or more chemical processing modules, one or more water rinse modules, and a wafer dryer. The processes and equipment needed for such wet processing operations are similar in some respects and quite different in other respects.
Some conventional wet chemical wafer cleaning operations entail immersing wafers in a tank, wet chemical processing for etching and associated post-etch cleaning. Typically, batches of wafers or single wafers are held upright in a vertical orientation within immersion tanks during wet processing. Chemical immersion tanks are typically made from non-reactive materials such as, for example, polytetrafluoroethylene (PTFE, known as "teflon"), or stainless steel. Following chemical treatment, wafers can be moved to a separate rinse module such as a water rinse tank, to receive a treatment that arrests chemical reactions occurring on the wafer surface. Water rinse tanks are also used to achieve pH neutralization following exposure of wafers to acidic or basic chemicals during processing in the chemical immersion tanks. Thus, the water tanks are exposed to chemicals used in the steps that precede the pH neutralization step, which means the water tank materials must also be resistant to such chemicals. Spray processing modules are one alternative to immersion tanks for chemical and/or water processing. Spray processing typically entails spraying individual wafers that are held in a horizontal position.
Some chemical immersion tanks and/or water rinse tanks are equipped with a sonic vibration system to assist in removing particles from wafer surfaces by vibrating the water while the wafer is submerged. Once particles are dislodged by the sonic vibrations, the particles can float away from the wafer surface. When the sonic vibration system operates at a vibration frequency in the MHz range, the process is referred to as a "megasonic" clean.
Wafer dryers can use, for example, nitrogen gas and/or a solvent such as isopropyl alcohol (IPA) to evaporate rinse water from the wafers. Additionally or alternatively, a high-speed spinning machine can drive water from the wafers by the action of a centrifugal force.
Single wafers or groups of wafers are typically transported between processing modules by one or more automated transport devices such as industrial manufacturing robots. Such robots can be designed to function in an aqueous environment and/or which may be chemically resistant. Such robots can be single axis, dual axis, or triple axis robots.
Some chemical immersion tanks and/or water rinse tanks are equipped with brushes that assist in removing particles from the wafer surfaces. Brushes are especially useful for removing slurry particles that may remain on the wafer surface after completing a CMP process. Brush cleaning typically entails scrubbing the front side of each individual wafer to remove particulates from at least partially formed integrated circuits.
Typically, neither etching nor post-etch cleaning involves scrubbing wafers with slurry or brushes. On the other hand, existing post-polish wafer cleaning equipment typically uses slurry and brushes combined with water or dilute acidic detergents, as opposed to concentrated chemicals and/or complex sequences of chemicals to clean the wafer. The design of wet cleaning equipment depends in large part on what chemicals are used. For example, the type of chemical to be used in the cleaning system determines the materials allowed for the tanks, delivery lines, hardware, filters, and even soldering methods used to plumb the delivery lines. Furthermore, different types of chemicals can require different safety features that impact equipment design. The design of post-polish cleaning equipment is therefore different from that of post-etch cleaning equipment in that the handling, delivery, and disposal of water and detergents containing particulate slurries will differ significantly from those needed for concentrated corrosive chemicals such as sulfuric acid, ethylene glycol, and the like that are typically used in post-etch cleaning.

Post-CMP hybrid wafer cleaning technique


There are provided a step of acquiring a main point cloud data on a predetermined measurement range by a laser scanner, a step of detecting a range with no data acquired, a step of acquiring a supplementary image data of the range with no data acquired by an auxiliary image pickup device, a step of preparing a stereoscopic image based on the supplementary image data obtained by the auxiliary image pickup device, a step of acquiring supplementary point cloud data from the stereoscopic image, and a step of supplementing the range with no data acquired of the main point cloud data by matching of the main point cloud data and the supplementary point cloud data.

The present invention relates to a surveying method, a surveying system, and a surveying data processing program for acquiring three-dimensional data of a predetermined area.
In recent years, three-dimensional surveying on three-dimensional object has been more frequently performed, and there are now growing demands on an image with three-dimensional data to be used for an electronic map. Because of such circumstances or the like, the amount of the data required for surveying purpose has extensively increased.
A laser scanner is known as a surveying system for measuring a large amount of three-dimensional data in detail and within short time.
A laser scanner is a surveying system for projecting a pulsed laser beam to a predetermined measurement area, for receiving a reflected light of the pulsed laser beam to measure three-dimensional position data at a projecting point of the pulsed laser beam for each pulse, and for acquiring point cloud data of the measurement area.
The laser scanner can obtain a large amount of point cloud data within short time. However, when obstacle(s) such as a vehicle, a tree, etc. are present in the measurement area, shadow (occlusion) occurs, and this causes a portion where the data is lacking. Also, because a distance is measured by the reflection of a pulsed laser beam, if reflectivity at the projecting point is low, e.g. if the laser beam used is in green color when the reflection point is in black color or in complementary color (i.e. in red color), the reflected light cannot be obtained. This causes a data-lacking portion to occur, too.
Further, when the measurement area is scanned from a horizontal direction, point cloud data cannot be obtained on the upper surface of a building or a structure, for instance.
For the purpose of obtaining point cloud data of the portion in occlusion, it has been practiced to move the laser scanner and to acquire the data of the portion in occlusion. Also, in order to obtain the point cloud data on the upper surface of a building or a structure, the laser scanner is moved to a position where the upper surface can be projected by the laser beam from the laser scanner to acquire the point cloud data on the upper surface.
For this purpose, every time the occlusion portion occurs, the laser scanner had to be moved. Or, large-scale equipment or tools such as a scaffold or an elevator or the like had to be installed to move the laser scanner to higher position. This means that tremendous efforts and long time are required for the surveying operation.
Also, when reflectivity is low at the point to be measured, such inconveniences often arise that the point cloud data cannot be obtained.

Surveying method, surveying system and surveying data processing program


A unique latch circuitry having both a latching and margin testing capability is provided. Every antifuse in a memory circuit is connected to a respective latch circuit. The latch circuits utilize a global input signal to configure a reference impedance with either a normal operational mode impedance or a test mode impedance. Once configured, and without any other additional circuitry, the latch circuits are capable of performing the latching or testing capability based upon comparisons to the reference impedance. When configured for the normal operational mode, the latch circuits read and output the status of their respective antifuses responsive to a control signal. When configured for the testing mode, the latch circuits test the impedance margin of their respective antifuses responsive to the same control signal. The configuration of the unique latch circuit, and the use of the same control signal for normal and test modes, allows for the global testing of all of the antifuses in a memory circuit while reducing the circuitry required to perform the testing. In addition, it is also possible to have different reference impedances for the normal and test modes.

1. Field of the Invention
This invention relates generally to integrated circuits and, in particular, to a method and apparatus for global testing the impedance of a programmable element within a memory circuit.
2. Description of the Related Art
Typical memory circuits include arrays of memory cells arranged in rows and columns. These memory circuits will also include several redundant rows and columns that are used as substitutes for defective locations in the memory array. When a defective memory array location is identified, rather than treating the entire array as defective, a redundant row or column is substituted for the defective row or column. This substitution is performed by assigning the address of the defective row or column to the redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make the substitution of the redundant row or column substantially transparent to a system including the memory circuit, the memory circuit utilizes an address detection circuit. The address detection circuit monitors row and column addresses and enables redundant rows or columns if the address of a defective row or column is detected. FIG. 1 illustrates the typical memory circuit 10 including an address detection circuit 100, control and address circuitry 12, an array of memory cells 14 and row and columns of redundant memory cells 16.
One type of address detection circuit 100 is a fuse-bank address detection circuit. A fuse-bank address detection circuit utilizes several fuse-bank circuits to control the redundant rows and columns. Each fuse-bank circuit corresponds to one of the redundant rows or columns. If there are eight redundant rows and eight redundant columns, for example, then the address detection circuit 100 will include sixteen fuse-bank circuits. Each fuse-bank circuit includes a bank of sense lines, each sense line connected to a respective fuse. Each sense line corresponds to one bit of a memory address since each fuse-bank will be programmed with an address of a defective memory array location. If an address comprises eight bits, then each fuse-bank circuit includes eight sense lines, each with corresponding fuses.
The sense lines are "programmed" by blowing fuses in a pattern corresponding to the address word of the defective row or column (hereinafter referred to as the programmed addresses). The programmed addresses are then detected by initially applying a test voltage across the bank of sense lines. Then, bits of an external address are applied to the sense lines. If the pattern of blown fuses corresponds exactly to the pattern of the external address bits, the sense lines block current and the voltage across the bank remains latched high. Otherwise, at least one sense line conducts and the voltage falls. Therefore, a high voltage indicates that the programmed address matches the external address while a low address does not. A matched address indicates that the redundant row or column should be used.
Recently, to save the costs and labor required to blow the conventional fuse, antifuses have replaced fuses in the address detection circuit 100. Antifuses are capacitive-type structures which, in their unblown states, form open circuits. Antifuses are "blown" by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, blown antifuses conduct while unblown anitifuses do not.
FIG. 2a illustrates an antifuse circuit 110 used in an antifuse-bank circuit. The circuit 110 corresponds to one bit of a programmed address. As previously stated, if an address consisted of eight bits, then each antifuse-bank circuit would include eight antifuse circuits 110. An antifuse 112, illustrated in its unblown state, is connected to a switchable signal CGND and a latch circuit 114. During normal operation, the switchable signal CGND is a ground potential to provide a reference for the antifuse 112. To blow or "program" the antifuse 112, the switchable signal CGND is supplied with a high voltage sufficient enough to cause the capacitive-type structure of the antifuse 112 to break down. Generally, the high voltage used to blow the antifuse is referred to as a programming voltage. Once blown, the antifuse 112 has a known impedance, plus or minus a predetermined margin, which is detected by the latch circuit 114. FIG. 2b illustrates the antifuse circuit 110 of FIG. 2a where the blown antifuse 112 is represented by its known impedance R.sub.112. When strobed by logic in the address detection circuit 100, the latch circuit 114 detects the impedance R.sub.112 of the antifuse 112 and outputs an output signal that is either a logical "1" if the antifuse is blown or a logical "0" if the antifuse is not blown. This output signal when combined with the output signals of the remaining antifuse circuits 110 of the antifuse-bank circuit forms an address of a defective memory location (i.e., a programmed address). The operation of antifuse in an address detection circuit 100 is described, for example, in U.S. Pat. No. 5,374,617 (Zheng), U.S. Pat. No. 5,742,555 (Marr et al.), and U.S. Pat. No. 5,706,238 (Cutter et al.), all assigned to Micron Technology Inc. and incorporated by reference herein.
One known problem with antifuses 112 is that they may not always have their expected or desired impedance R.sub.112 after being programmed. As stated above, an external address is received by the address detection circuit 100 which is compared to the antifuse-bank programmed addresses. The anitfuses 112 of each antifuse-bank, corresponding to an address of a defective row or column, must be read and latched by the latch circuits 114 and then compared to the external address. There must be an exact match before a redundant row or column can be used. If the impedance R.sub.112 of the antifuse 112 is not low enough, the latch circuit 114 will not detect that the antifuse 112 is blown and therefore, the correct status (i.e., blown antifuse 112) of the antifuse 112 will not be latched; this leads to a programmed address that does not match the defective address. Since the external address does not match any of the programmed addresses, the address detection circuit 100 will not substitute a redundant row or column for a defective row or column. In fact, the programmed address may match an external address of a non-defective memory array location. Accordingly, the redundant memory may substitute for good memory.
FIG. 3 illustrates a mechanism of testing the impedances R.sub.112 of antifuses 112. Four antifuse circuits 110 are illustrated, each having a respective antifuse 112 and associated latch 114. It must be noted, however, that there would be an antifuse circuit 110 for every bit in a programmed address and that four circuits 110 are illustrated for convenience purposes only. A test circuit for testing the impedance value of the antifuse 112 is also shown as test latch circuit 106 and multiplexer 104. The outputs of the circuits 110 are connected to a multiplexer 104. The multiplexer 104 is connected to a test latch circuit 106. The test latch circuit 106 is configured in the same manner as the latch circuits 114 included in the antifuse circuits 110. That is, the test latch circuit 106 will detect whether an antifuse 112 has been blown by measuring its impedance R.sub.112.
When testing the impedances of the antifuses 112, the multiplexer 104 sequentially connects the antifuses 112 to the test latch circuit 106. The test latch circuit 106 compares the impedance R.sub.112 of the antifuse 112 being tested to a reference impedance R.sub.REF (i.e., the expected impedance plus a margin). If the impedance R.sub.112 is greater than the reference impedance R.sub.REF and the antifuse 112 has been blown, then the antifuse 112 impedance R.sub.112 would lead to an erroneous programmed address when sensed by the latch circuit 114. Repairs or replacements would be required in order to use the antifuse circuit 110. If the impedance R.sub.112 is less than the reference impedance R.sub.REF, then the antifuse 112 would not lead to an erroneous programmed address and the antifuse circuit 110 will be used. Each antifuse circuit 110 is tested one at a time by the test latch circuit 106 during sequential operation of the multiplexer 104.
Although the above mechanism can properly detect when a blown antifuse 112 has an impedance R.sub.112 that is too high and would lead to incorrect programmed addresses, it still has some shortcomings. For example, the mechanism illustrated in FIG. 3 requires the use of a multilplexer 104 and a test latch circuit 106 and the numerous respective connections to the antifuse circuits 110. This additional circuitry adds costs and uses up valuable space on the semiconductor die. In addition, the antifuses 112 are tested one at a time in a sequential manner. This leads to slower testing of the antifuses 112, particularly if numerous redundant rows and columns were to be used.
Therefore, there is a need and desire to provide a method and apparatus for global testing the impedance of an antifuse while reducing the circuitry required to perform the testing.
In addition, manufacturers may require a blown antifuse 112 to have a smaller impedance margin during in-house testing than is actually required by users once the product is out in the field. To do so, however, a test latch circuit 106 that is not configured the same as the latch circuits 114 would be required. This adds additional steps in the manufacturing process of the memory circuit 10 and again consumes more circuit area. Therefore, there is a need and desire to provide a method and apparatus for testing the antifuse for different impedance values, but without requiring test circuitry that differs from the circuitry required to latch the status of the antifuse.

Method and apparatus for global testing the impedance of a programmable element


Sport footwear assembly, especially an in-line roller skate boot, of the type including two elements, of which one, internal, is a boot, and the other, external, is a boot support coming from the skate. According to the invention, these distinct elements have closure and linkage mechanisms constituted by a single lace which carries out the simultaneous tightening of the two elements, in order to ensure their tightening on the foot.

1. Field of the Invention
The present invention relates to a sport footwear assembly, especially a boot for a roller skate or in-line roller skate. This assembly is of the type including two elements one of which, "internal", i.e., a liner or a boot, is in direct contact with the foot and envelope the latter, and the other, external, i.e., a boot shell or a boot support coming from the skate, respectively, is adapted to receive and maintain the internal element. In such an assembly, at least the external element includes means for closing and linking the assembly, which means are constituted by hooks or a lace or cable connecting therebetween, along a predetermined alternating path, a series of return hooks or eyelets arranged on the edges of an internal quarter and of an external quarter of the external element demarcating an opening for introducing the user's foot to constitute a lacing zone. In this manner, during a traction on the strands of the lace, the latter tightens the quarters to bring them closer to one another and maintain them in a tightening position on the foot.
2. Background and Material Information
In known assemblies of this type, whether it is a sport boot provided with a liner, or a boot adapted to be affixed to a chassis, it is always tedious for the user to have to perform a first lacing of the internal element, which is in fact the liner in an in-line roller skate, then the lacing of the external element, which is in fact the shell.


A rack for flanged articles comprises a pair of front and rear opposed parallel transverse support members, and a pair of longitudinal members extending between the front and rear support members. Each of longitudinal member is formed of a wire strip and comprises a straight portion and an upturned forward end portion. The straight portions of the longitudinal members extend forward from the rear support member to positions below the front support member. The straight portions are disposed to form a pair of spaced parallel rails for receiving therebetween a row of articles such that the articles are slidably engaged at the undersides of their flanges with the rails, and thereby the articles are suspended by their flanges for movement along the rails. The upturned forward end portions of the longitudinal members extend upward to the front support member and secured to the same to form a brace for interconnecting the rails and the front support member. The upturned forward end portions are divergent toward the front support member so that an exit for the articles is defined between the upturned forward end portions.

The present invention relates generally to racks for flanged articles such as stemware and flanged bottles, and, more particularly, to a suspension-type display rack having an elongate track for slidably supporting flanged articles in pendant position.
Suspension-type display racks have been used in the merchandising of soft drink bottles such as PET bottles having outwardly projecting annular neck flanges. These racks have article-supporting tracks arranged side by side in a parallel relationship. Each track has a pair of spaced parallel rails extending along that track. The necks of flanged bottles are received between the rails of each track so that the bottles are engaged at their neck flanges with the rails and thus suspended from the respective track. The bottles received in each track are automatically arranged in a tidy row along that track and presented for removal by customers through the front end of the track.
Typically, each track is manufactured separately as a part or parts of a rack, and several separate tracks are assembled together into a shelf-like unit. Then, one or more of such units are mounted on suitable vertical support means such as a four-post framework to complete a rack. Examples of these conventional bottle racks are disclosed in U.S. Pat. Nos. 4,318,485; 4,367,818; and 4,401,221 which are owned by the assignee of the present invention. These bottle racks, on one hand, have certain adjustability in size and number of tracks. On the other hand, however, their manufacturing cost is high and their assembly is time-consuming.
Suspension-type wire racks are well known in the field of storage of stemware such as wine glasses, goblets or the like. Stemware glasses are engaged at their foot flanges with the track rails and thus suspended upside-down from the tracks. An example of conventional wire racks for stemware is disclosed in U.S. Pat. No. 3,214,031. Wire racks are inexpensive and easy to manufacture as compared to those bottle racks formed of sheet metal or plastic. Specifically, they do not require much assembly at the points of installation. However, when applying known wire arrangement to bottle racks, it is essential to take account of structural strength or rigidity of such bottle racks because of the significant difference in weight between empty stemware and filled bottles.
What is needed, therefore, is a suspension-type rack for flanged articles which is inexpensive, easy to manufacture and ready to use without substantial assembly. Such racks should have simple and sturdy arrangement for supporting the front ends of the tracks.


Disclosed is to enable high speed reading from a storage node when a read is executed. A main cell array is constituted from main cell division units 20a. Each main cell division unit 20a includes select gates SG that extend in a vertical direction, common sources CS that extend in a horizontal direction below the select gates SG outside a cell region, word lines W0 to W15 that extend above the select gates SG in the horizontal direction within the cell region, a plurality of storage nodes disposed in the vicinity of intersecting portions between the word lines W0 to W15 and the select gates SG, respectively, below the word lines W0 to W15, and a bit line MGB for transmitting to a sense amplifier 11 information on one of the storage nodes through a selection switch 21. In the main cell division unit 20a, an inversion layer is formed below each of the select gates SG within the cell region by applying a positive voltage to each of the select gates SG. A reference cell array is constituted from a reference cell division unit 30a having a same configuration as the main cell division unit 20a.

Among conventional non-volatile semiconductor memory devices, a non-volatile semiconductor memory device as shown in FIGS. 10 to 11 (conventional art 1) is known. The non-volatile semiconductor memory device in the conventional art 1 includes first diffusion regions 107, select gates 103, second diffusion regions (indicated by reference numeral 121 in FIG. 10), floating gates 106, and control gates 111 (refer to FIGS. 10 and 11).
The first diffusion regions 107 are extended in (below) a surface of a substrate 101, and are provided together, being separated to one another. The first diffusion regions 107 are used as local bit lines. The select gates 103 are disposed in regions between the mutually adjacent first diffusion regions 107 above the substrate 101 via an insulating film 102, and extend in the direction in which the first diffusion regions 107 extend. The second diffusion regions (indicated by reference numeral 121 in FIG. 10) are disposed on the surface of the substrate 101 below the select gates 103 outside cell regions, and extend in a direction that crosses the select gates 103 on both sides outside the cell regions. The second diffusion regions (indicated by reference numeral 121 in FIG. 10) are employed as common sources. The floating gates 106 are storage nodes, and are disposed between the first diffusion regions 107 and the select gates 103, respectively via the insulating film 102. The floating gates 106 are arranged in the form of islands as seen from a direction normal to the plane. The control gates 111 are disposed above the floating gates 106 and the select gates 103 through an insulating film 108, and are disposed together, being separated to one another. The control gates 111 extend in the direction that crosses the select gates 103. The control gates 111 are employed as word lines.
One of the first diffusion regions 107 on both sides of a select gate 103, a floating gate 106, a control gate 111, and the select gate 103 constitute a first unit cell. The other of the first diffusion regions 107 on both sides of the select gate 103, a floating gate 106, the control gate 111, and the select gate 103 constitute a second unit cell. In this non-volatile semiconductor memory device, by applying a positive voltage to the select gate 103, an inversion layer 120 is formed on the surface of the substrate 101 below the select gate 103 in the cell regions.
An operation of the non-volatile semiconductor memory device according to the conventional art 1 will be described with reference to drawings. FIG. 12 is a schematic diagram for explaining about a read operation (read operation when electrons are not stored in a floating gate) from the semiconductor memory device according to the conventional art 1. FIG. 13 is a schematic diagram for explaining about a write operation onto the semiconductor memory device according to the conventional art 1. FIG. 14 is a schematic diagram for explaining about an erase operation from the semiconductor memory device according to the conventional art 1.
Referring to FIG. 12, for a read operation, first, in a state where electrons are not stored in the floating gate 106 (or an erased state; with a low threshold voltage), by applying positive voltages to the control gate 111, select gate 103, and the second diffusion region (indicated by reference numeral 121 in FIG. 10), respectively, electrons e move from the first diffusion region 107 through a channel immediately below the floating gate 106, moves through an inversion layer 120 formed below the select gate 103, and moves to the second diffusion region (indicated by reference numeral 121). On the other hand, in a state where the electrons are stored in the floating gate 106 (or a written state; with a higher threshold voltage), even if the positive voltages are applied to the control gate 111, select gate 103, and second diffusion region (indicated by reference numeral 121 in FIG. 10), respectively, the electrons e do not flow because there is no channel below the floating gate 106 (not shown). Reading is performed by making a judgment on data (whether it has a value of 0 or 1) to see whether the electrons e flow or not.
Referring to FIG. 13, for a write operation, positive high voltages are applied to the control gate 111 and the first diffusion region 107, and a positive low voltage of an extent that causes an electric current flow of 1 μA through a memory cell is applied to the select gate 103. The electrons e thereby move from the second diffusion region (indicated by reference numeral 121 in FIG. 10) to the first diffusion region 107 via the inversion layer 120 formed below the select gate 103. On that occasion, part of the electrons e attain high energy due to an electric field at a boundary between the select gate 103 and the floating gate 106, and thus this part of the electrons e are injected into the floating gate 106 across an insulating film 105 (tunnel oxide film) disposed beneath the floating gate 106.
Referring to FIG. 14, for an erase operation, a negative high voltage is applied to the control gate 111, and a positive high voltage is applied to the substrate 101. The electrons e are thereby drawn from the floating gate 106 to the substrate 101 through the insulating film 105 (tunnel oxide film) disposed beneath the floating gate 106.
Next, an internal circuit of the non-volatile semiconductor memory device according to the conventional art 1 will be described using drawings. FIG. 15 is a circuit diagram schematically showing the internal circuit of the non-volatile semiconductor memory device according to the conventional art 1.
The non-volatile semiconductor memory device includes a main cell region 130, a reference cell region 131, a sensor amplifier 132, a main cell decoder 135, and a reference cell decoder 136.
In the main cell region 130, memory cells shown in FIG. 11 (pairs of first and second memory cells) are arranged in the form of a matrix constituted from m rows (on an X coordinate)×n columns (on a Y coordinate). The first diffusion region (indicated by reference numeral 107 in FIG. 1) in a main cell is electrically connected to the sense amplifier 132 through a main cell local bit line MLB, a main cell block selection switch 133, and a main cell global bit line MGB. The control gates (indicated by reference numeral 111 in FIG. 11) in the main cell region 130 are electrically connected to the main cell decoder 135 via corresponding word lines (data lines) W0 to W15. Incidentally, referring to FIG. 15, reference symbol SG indicates the select gate, while reference symbol CS indicates a common source corresponding to each of the second diffusion regions 121 in FIG. 10.
In the reference cell region 131, one memory cell (one pair of the first and second unit cells) shown in FIG. 11 is arranged. The first diffusion region in a reference cell (indicated by reference numeral 107 in FIG. 11) is electrically connected to the sense amplifier 132 via a reference cell block selection switch 134 and a reference cell global bit line RGB. The control gate (indicated by reference numeral 111 in FIG. 11) in the reference cell region 131 is electrically connected to the reference cell decoder 136 through a corresponding reference cell word line RW.
The sense amplifier 132 amplifies a potential difference between the memory cell global bit line MGB and the reference cell global bit line RGB. The sense amplifier 132 is provided for each main cell global bit line MGB. The main cell decoder 135 applies a voltage to one of word lines W0 to W15 specified by an address signal. The reference cell decoder 136 applies a voltage to the word line RW.
A description will be directed to a case where the address signal indicative of "14" is sent to the main cell decoder 135 and the reference cell decoder 136. When a read operation is performed, in a state where electrons are not stored in floating gates of cells surrounded by a heavy dot-dashed line (i.e. the erased state; with the low threshold voltage) in the main cell region 130, positive voltages are applied to the select gate SG, common sources CS, and word line W14, respectively, and the main cell block selection switch 133 is turned ON. Then, currents from the common sources CS are thereby input to the sense amplifier 132 via paths indicated by heavy dotted lines. On the other hand, in the reference cell region 131, regardless of whether the address signal indicates which address, positive voltages are applied to the select gate SG, common sources CS, and reference cell word line RW, respectively, and the reference cell block selection switch 134 is turned ON. Current from the common source CS is thereby input to the sense amplifier 132 via a path indicated by a heavy dotted line. In the sense amplifier 132, a potential difference between the main cell global bit line MGB and the reference cell global bit line RGB is amplified. The 0/1 judgment is thereby performed based on data output from the sense amplifier 132.
There is also provided other conventional non-volatile semiconductor memory device that includes a first column tree, a second column tree, and a differential amplifier (of conventional art 2; refer to Patent Document 1). The first column tree includes a wiring group to which information on a first memory cell is transmitted. The second column tree includes a wiring group to which information on a second memory cell is transmitted. The differential amplifier amplifies a potential difference between a potential at a data line and a potential at a reference data line. The non-volatile semiconductor memory device further includes a column switching gate. The column switching gate couples the first column tree to the data line and also couples the second column tree to the reference data line when the first memory cell is selected. When the second memory cell is selected, the column switching gate couples the second column tree to the data line and also couples the first column tree to the reference data line. According to conventional art 2, a non-volatile semiconductor memory device having strong noise immunity, in which a capacitance of a main body side can be more accurately adjusted to a capacitance of a reference side, while suppressing an increase in the area of the device, can be obtained.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2002-8386A (FIG. 1)

Non-volatile semiconductor memory device


An electric power cable line is arranged in which the insulating layer is increased to a greater thickness at two end portions of each cable than a thickness at the other or center portion of the same. Since the insulating layer is increased in thickness at the end portions of the cable, thus an electrical stress exerted on the overall layer construction of the end portions is lowered. Hence, the dielectric strength of the end portions of the cable becomes high and the power cable line will thus be increased in the operational reliability.

1. Field of the Invention
The present invention relates to an electric power cable line.
2. Description of the Related Art
One of known electric power cable lines which are commonly in use is illustrated in FIG. 1. Shown are power cables 10, straight joints 28 for jointing two cables to each other, terminal ends 29, straight joint constructions 30, and terminal end constructions 31.
FIG. 2 is a longitudinal cross sectional view of the cable 10, in which there are provided a center conductor 12, an inner semiconductive layer 14, a cable insulating layer 16, an outer semiconductive layer 18, a shield layer 20, and a sheath 22. FIG. 2 illustrates an upper half of the cable 10 for simplicity because two, upper and lower, halves of the cable 10 are symmetrical about the axis. FIG. 3 is a schematic view of the straight joint construction 30 showing a joint box 31, an epoxy unit 32, a premolded stress relief cone 34, a retainer 36, and a conductive connector 38.
It is essential for the electric power cable line to withstand a high voltage in long-time service. It is common for the dielectric strength of the straight joints and terminal ends in a long-time supply of high voltage to be as low as about 60% of that of the cable. To increasing the operational reliability of the cable lines, improved straight joints and terminal ends are much desired.

Electric power cable line and a method of fabricating the same


A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices including, but not limited to, non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a "three-dimensional (3D) memory array") architectures. A conventional vertical memory array includes vertical memory strings extending through openings in one or more decks (e.g., stack structures) including tiers of conductive structures and dielectric materials. Each vertical memory string may include at least one select device coupled in series to a serial combination of vertically stacked memory cells. Such a configuration permits a greater number of switching devices (e.g., transistors) to be located in a unit of die area (i.e., length and width of active surface consumed) by building the array upwards (e.g., vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Control logic devices within a base control logic structure underlying a memory array of a memory device (e.g., a non-volatile memory device) have been used to control operations (e.g., access operations, read operations, write operations) of the memory cells of the memory device. An assembly of the control logic devices may be provided in electrical communication with the memory cells of the memory array by way of routing and interconnect structures. However, processing conditions (e.g., temperatures, pressures, materials) for the formation of the memory array over the base control logic structure can limit the configurations and performance of the control logic devices within the base control logic structure. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size (e.g., horizontal footprint) of the memory device, and/or improvements in the performance (e.g., faster memory cell ON/OFF speed, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption) of the memory device. Furthermore, as the density and complexity of the memory array have increased, so has the complexity of the control logic devices. In some instances, the control logic devices consume more real estate than the memory devices, reducing the memory density of the memory device.

Microelectronic devices, related electronic systems, and methods of forming microelectronic devices


A floor structure includes a plurality of structural metal components that each have: a plate-shaped supporting portion that is laid either perpendicular or oblique to an installation surface; a plate-shaped top flange that extends from a top end portion of the supporting portion in parallel with the installation surface; a plate-shaped bottom flange that extends from a bottom end portion of the supporting portion in parallel with the installation surface and in the opposite direction from the top flange, wherein the structural metal components are laid on a flat surface in parallel with each other such that the top flange of one of the mutually adjacent structural metal components covers the bottom flange of the other of the mutually adjacent structural metal material.

When the structural framework of an erected construction such as a building or house is constructed using a steel structure (S structure), a steel reinforced concrete structure (RC structure), or a steel framed reinforced concrete structure (SRC structure), normally, the floor structure of the erected construction is formed by a concrete floor structure or by a composite structure which combines steel deck plates and an RC structure (referred to below as an RC floor structure), however, building a steel-construction floor that is formed solely from steel is also possible with current construction technology.
Prior art relating to the aforementioned floor structures is disclosed, for example, in Patent documents 1 to 5 shown below. Specifically, a floor structure that uses folded plate-shaped steel floor panels is described in Patent documents 1 and 2. A method of constructing a floor using deck plates is described in Patent document 3. This construction method is a technology for an RC floor structure in which a plurality of beam materials are assembled as a base, and after this assembled unit has been put in position, concrete is laid over the deck plates. A floor structure in which a plurality of box-shaped steel materials are arranged in parallel is described in Patent document 4. Technology for an RC floor structure in which a plurality of folded deck plates are arranged in parallel and concrete is then laid over the deck plates is described in Patent document 5.
Patent document 1: Japanese Unexamined Patent Application, First Publication No. 2003-119946
Patent document 2: Japanese Patent No. 3781674
Patent document 3: Japanese Unexamined Patent Application, First Publication No. H11-293834
Patent document 4: Japanese Unexamined Patent Application, First Publication No. 2003-293017
Patent document 5: Japanese Unexamined Patent Application, First Publication No. 2005-320722

This patent is subject to a terminal disclaimer.

Floor structure including plate-shaped supporting portion


The present invention discloses an electronic cigarette, comprising a main body and a heating device, wherein the main body is provided with a first locking member and a mounting chamber with an opening, the heating device is provided with a second locking member, the heating device is mounted to the mounting chamber along the opening, the second locking member is engaged with the first locking member to lock the heating device to the main body to form a locked state; one of the main body and the heating device is further provided with a driving member, and the main body is further provided with an through hole through which the external detaching device is inserted to extrude the driving member, so that the driving member drives the second locking member to be separated from the first locking member.

Studies have shown the use of "heating non-burning". Related studies have shown that nicotine and some tobacco flavor components can be transferred to smoke in a manner of only heating but not burning tobacco at a lower temperature below 500° C. Compared to traditional burning cigarettes, low temperature cigarettes can significantly reduce the release of tar and harmful components as a whole. At the same time, there is basically no sidestream smoke, which is of little harm to others and the environment.
The existing low-temperature flue-cured tobacco is usually provided with a heating chamber for the user to add tobacco products, and then the tobacco products in the heating chamber are heated by providing a heating device. However, the substance produced by the tobacco products during heating tends to adhere to the surface of the heating chamber and the heating device, and the heating chamber cannot be detached from the electronic cigarette. When cleaning, the cleaning device needs to extend into the heating chamber to clean the chamber wall of the heating chamber and the surface of the heating device, so that it is more difficult to clean and the degree of cleaning is lower.
However, the existing structure for detaching the heating device from the main body usually snap-fits the heating device with the main body, and then the heating device is controlled to be separated from the main body by an elastic lock button. There is also a deficiency that the elastic lock button is exposed to the outside of the main body and is easily extruded when being placed in a pocket to result in false triggering.


Systems and methods for securely transferring authentication information between a user and an electronic resource are disclosed herein. The methods include providing an authentication image to a user interface. The authentication image is associated with a resource-side coordinate system and the providing includes encoding the resource-side coordinate system to generate a user-side coordinate system that is different from the resource-side coordinate system and transmitting the authentication image and the user-side coordinate system to the user interface. The methods further include receiving an encoded coordinate set, which uniquely identifies an authentication location in the user-side coordinate set and that is user-selected from the authentication image, from the user interface and decoding the encoded coordinate set to generate a decoded coordinate set that uniquely identifies the authentication location in the resource-side coordinate set. The systems include systems that perform the methods.

Traditional alphanumeric passwords suffer from a variety of limitations. One limitation relates to a user's ability to remember a strong password that is not easily guessed using automated and/or manual attack methodologies. For example, a long, random sequence of numbers, letters, and/or characters may be utilized to generate a strong password that is not easily guessed or otherwise ascertained. However, most users have difficulty remembering such a strong password and will either write it down (producing the possibility of the password being physically stolen or otherwise visually observed) or will choose a simpler (weak) password that is based upon information that is familiar to the user (such as significant dates, names, and/or dictionary words) or uses fewer and/or repetitive characters. While these weak passwords may be readily remembered, they also may be readily guessed, thereby increasing the likelihood that the weak password may be compromised.
These issues are compounded by the fact that most users have a large number of electronic accounts (such as personal email, personal network, work email, work network, bank accounts, brokerage accounts, credit card accounts, retail accounts, etc.) and that each of these electronic accounts may have its own respective password for access thereto. Thus, a user is presented with a dilemma. In the interest of being able to remember the respective passwords, the user might select the same password for several, or even all, electronic accounts. However, if this password is stolen or otherwise compromised, all of the electronic accounts that utilize this password may be compromised. Alternatively, the user might choose a different password for each electronic account (whether weak or strong); however, the user then must remember different passwords for all of these accounts.
In addition, and regardless of the strength of a selected password, malicious software exists that may be utilized to steal a password from a targeted user. For example, keystroke logging software may capture a sequence of keys that is entered by the user while logging in to an electronic resource, and an unauthorized individual may utilize these logged keystrokes to log into the electronic resource without the user's permission. Alternatively, and even if the password is entered securely by the user, it may be intercepted during transmission from the user to the electronic resource. For example, many selected passwords, regardless of their individual strength, are vulnerable to being compromised (i.e., stored, copied, or otherwise identified) during transmission from the user (client/user side) to the corresponding remote site (server/resource side).
Graphical, or graphic-based, passwords have been utilized to generate strong passwords that may be more readily remembered by the user. Illustrative, non-exclusive examples of graphical passwords, including methods for generating and/or utilizing such passwords, are disclosed in U.S. Pat. No. 8,181,029 and U.S. Patent Application Publication Nos. 2011/0040946 and 2011/0055585, the complete disclosures of which are hereby incorporated by reference. However, these graphic-based passwords still suffer from inherent limitations and/or still may be compromised and/or intercepted during transmission. Thus, there exists a need for improved systems and methods for secure electronic authentication.


A semi-trailer landing gear assembly can include a set of legs actuable to raise and lower a semi-trailer. Each leg can include a foot abutting the ground and a support abutting the semi-trailer. A rotatable shaft couples to the set of legs where rotation of the rotatable shaft raises and lowers the legs. A crank can operably couple to the rotatable shaft to rotate the rotatable shaft. At least two air drivers operably couple to the crank to rotate the crank in an opposing manner such that at least one air driver is always offset from the direction of rotation to provide continuous torque.

The invention relates to mechanisms that drive rotational movement, and more particularly to an improvement in an actuator that is driven by air drivers such as that used in a landing gear of a semi-trailer.
One environment to which the invention may be applicable is found in FIG. 1 where a conventional landing gear 10 for a semi-trailer is shown. The landing gear 10 is used to support a semi-trailer when the semi-trailer is disconnected from a tractor. The landing gear 10 is designed to expand and contract vertically. In expansion, the landing gear 10 lifts the front of a semi-trailer so that it can be disconnected from the tractor, and thereafter supports the front of the semi-trailer when the tractor departs. In contraction, the landing gear 10 lowers the front of the semi-trailer to enable connection to a tractor, and, once connected, to further gain ground clearance so the semi-trailer can be pulled by the tractor free of interference.
The landing gear 10 comprises a pair of spaced legs 12, each having a mounting bracket 14 for securing the landing gear to a frame of a semi-trailer (not shown). Each leg 12 comprises a hollow tube 16 within which is the leg 12 that is geared to extend from and retract into the hollow tube 16. Each leg 12 has a foot pad 18 that supports the landing gear 10 on the ground. A gearbox 20 mounted to one of the legs controls the extension and retraction of both legs by way of a cross drive shaft 22 extending between the legs 12. The gearbox 20 is manually driven by a crank handle 24. It can require substantial torque via the gearbox 20 to raise a loaded semi-trailer, on the order of less than or equal to 100 foot pounds when the trailer is loaded and the foot pad 18 is in contact with the ground.


A circuit includes a plurality of first MuGFET devices supported by a substrate and having a first performance level. A plurality of second MuGFET devices is supported by the substrate and have a second performance level. The first and second devices in one embodiment are arranged in separate areas that facilitate different processing of the first and second devices to tailor their performance characteristics. In one embodiment, the circuit is an SRAM having pull down transistors with higher performance.

For dense array style circuit layouts, such as static random access memories (SRAMs), a small cell is desired. In a read operation, a bit line and complementary bit line are pre-charged to a supply voltage. An externally received read address signal is decoded, and according to the decoding result, a word line signal for the read operation is enabled. Next, cell access transistors are turned on, and the data stored in the cell is read through the bit line and the complementary bit line. Similarly, in the write operation, a write address signal is received and is decoded, and according to the decoding result, a word line signal for a write operation is enabled, and the access transistors are then turned on, and the data loaded on the bit line and the complementary bit line is stored in the cell.
To avoid over writing data in the cell and thus to increase read stability, an access transistor is usually made weaker than the corresponding pull down devices. In conventional bulk complementary metal oxide semiconductor (CMOS) layouts, the access transistor is designed with a smaller transistor width. In multi gate field effect transistor (MuGFET) technologies, a core cell area is constrained by the distance between two fins (fin pitch) and the number of fins used per device. Thus, fins are placed close together, and are similar in current driving characteristics. One of the characteristics that differentiate MuGFET layouts from convention bulk complementary metal oxide semiconductor (CMOS) layouts is the fixed pitch in which transistor fins must be placed.
One known skinny SRAM cell layout that consumes little area has a length of four fin pitches. pFET (p-type field effect transistor) devices are located in the middle of the layout, with nFET (n-type field effect transistor) devices, including pull down devices located on the sides. The electrical characteristics of this prior SRAM cell are sub-optimal. All the transistors share the same fin height, which is equivalent to the gate width in bulk CMOS. This is not optimal to achieve sufficient cell stability, especially during read and write access.

Circuit layout for different performance and method


An elevator door interlock includes a position indicator mounted at each landing, an elongate vane pivotally mounted in a fixed position with respect to the car door for movement between a first position, preferably several degrees rotated from perpendicular, and a second position, preferably generally perpendicular to the door surface, a swing latch including a latch arm secured at one end to the vane, preferably extending generally perpendicular to the vane, a contact plate secured to the end of the swing latch opposite the vane end, and a stop plate mounted in a fixed position with respect to the elevator car. The vane is preferably mounted on a spring-biased hinge, and is normally biased towards the first position such that the contact plate extends into the plane of the stop plate and contacts the stop plate to prevent further opening of the elevator door more than a limited distance when the door is opened unless the elevator car door is moved into a safe landing position within the hoistway.

An ongoing concern in the elevator industry is the situation where an elevator car stops between floors due to a power failure, equipment breakdown, or for some other unforeseen circumstance. Existing codes require that either the elevator car doors or hoistway doors cannot be opened more than four inches from inside the car whenever the car is outside the landing zone. These standard codes also require that when the car door is arranged so that it cannot be opened, the car door shall be openable from outside the car without the use of special tools.
Elevators typically employ door coupling mechanisms which mechanically couple the car doors to access doors located at the passenger landings, so that both the car door and the access door can be simultaneously and jointly controlled to open or close to allow for entry and exit of passengers. One such existing door coupling mechanism is the blade-and-roller-type mechanism employed on elevators manufactured by Otis Elevator Company. This coupling mechanism is illustrated in FIGS. 1 and 2.
Various mechanical car door locking systems have been developed which are integrated with the car door coupling mechanism. One example, shown in U.S. Pat. No. 1,326,440, entitled "Apparatus for Operating an Interlocking Landing in Cage Gates of Elevators," issued to Shaudoir, shows an elevator/hoistway door coupling mechanism employing a mechanical interlock which prevents the elevator door and/or hoistway door from opening unless the elevator car is in the desired position at a hoistway landing.
Another example, U.S. Pat. No. 4,313,525, entitled "Car Door Safety Interlock," issued to McDonald, discloses a power operating sliding door of an elevator car which is provided with a mechanical safety interlock which restrains the elevator car door from opening unless disengaged through a mechanical interconnection responsive to the motion of a door coupling vane contacting a pair of hatch door rollers.
U.S. Pat. No. 4,423,799, entitled "Vehicle Door Lock for Limiting Door Opening to Specified Vehicle Positions," issued to Glaser, et al., similarly discloses a variety of locking mechanisms which restrain elevator car doors from opening unless disengaged as an indirect result of the engagement of the elevator car door/hoistway door coupling mechanism.
These and other existing mechanical interlock systems, however, typically utilize several interconnected moving parts and are difficult or impossible to retrofit on existing elevator systems.
One object of the present invention is, therefore, to provide a mechanical car door interlock which employs few moving parts.
Another object of the present invention is to provide a mechanical car door restraint which is integrated with a conventional blade-and-roller type door coupling mechanism so that the elevator door coupling vane serves the additional functions of position sensor and actuator for the elevator car door interlock.
It is yet another object of the present invention to provide a mechanical door interlock which is simple in design and operation, to facilitate easy installation, service, and retrofitting of the device onto existing elevator systems.
It is yet another object of the present invention to provide a mechanical door interlock which may be quickly and easily disengaged from outside the elevator car.


A method involves a headless IoT device wirelessly communicating a MAC address to a client device in response to a scan by the client device, and receiving from the client device a vendor action frame comprising access credentials for communicating via a Wi-Fi access point. The IoT device applies the credentials to authenticate to the Wi-Fi access point, forms an application layer for communicating over the Wi-Fi access point network, and communicates with the client device via the application layer.

Wi-Fi is a wireless communication technology that allows mobile devices such as cellphones and tablets to wirelessly connect to the Internet or other computer data networks. Many devices include a display and a keyboard for the user interface. A typical procedure for provisioning a Wi-Fi connection on such devices involves presenting on the display a list of available Wi-Fi networks to the user. After choosing the network, the user is prompted for a password. If the password is correct, the connection is successfully established.
The process of establishing a secure Wi-Fi connection becomes more challenging for certain Internet of Things (IoT) devices that do not include a display and a keyboard. These so-called "headless" devices require alternate methods to obtain the network name and password from the user.
One conventional method for establishing secure Wi-Fi connections for headless IoT devices utilizes the Software Access Point (Soft AP) process. Using Soft AP, a client device, such as a tablet, phone, etc., first executes a two-step process: 1) the client device disconnects from the Wi-Fi network to connect to the IoT device to share Wi-Fi credentials (SSID and Password), and 2) the client device connects back to the Wi-Fi network and waits for the target IoT device to connect to the Wi-Fi network.
In another conventional method, the un-provisioned IoT device wakes-up initially as a Wi-Fi access point, with an SSID defined by the equipment manufacturer. Before trying to connect to the external Wi-Fi network for the first time, the un-provisioned device creates a Wi-Fi network of its own, allowing a PC or a smart phone (for example) to connect to it directly to facilitate its initial configuration. Often the un-provisioned device executes an embedded web server. After the smartphone, PC, etc. connects to the un-provisioned device's Wi-Fi access point, it opens the smart phone's web browser and browses into the device's web site via a pre-defined local URL or IP address. In the embedded web site, the user chooses (or types in) the external Wi-Fi network name and password. The un-provisioned device stores the network credentials in nonvolatile memory and then switches modes in order to connect to the external Wi-Fi network using the stored network credentials.
SmartConfig™ technology is a proprietary provisioning method of Texas Instruments® that uses a mobile app to broadcast the network credentials from a client device to an unprovisioned headless Wi-Fi device. When triggered by a configuration signal from the client device the un-provisioned device enters a special scan mode, waiting to pick up the network information that is being broadcasted by the client device. The client device needs to be connected to the Wi-Fi network to be able to transmit the configuration signal to the un-provisioned device. The SSID that the client device is connected to is displayed automatically by an application on the client device. The user of the client device then adds the network password and activates a control on the client device to begin the process of provisioning the un-provisioned device on the external Wi-Fi network. After the network credentials are picked up by the unprovisioned device, it connects automatically to the external Wi-Fi network and sends out a service discovery message back to the client device. The application on the client device detects the service discovery message and presents a notification to the user that the previously un-provisioned device was provisioned on the external Wi-Fi network successfully.
These conventional methods are inefficient and utilize more steps than needed. A need therefore exists for method of establishing Wi-Fi connections for headless IoT devices that reduces the number of steps and avoids temporary disconnection of the Wi-Fi connection between the client device and the Wi-Fi network while configuring the IoT device.

Connectionless fast method for configuring Wi-Fi on displayless Wi-Fi IoT device


The present invention concerns an amplifying device arranged to receive an input signal having a certain duty cycle. The amplifying device comprise a first switching unit having an input terminal adapted to receive a first half of the input signal, and an output terminal adapted to be connected to a first signal output where a first half of an output signal is provided. The amplifying device comprise a second switching unit having an input terminal adapted to receive a second half of the input signal and an output terminal adapted to be connected to a second signal output where a second half of the output signal is provided. Also, the first switching unit and the second switching units are adapted to receive an input signal, wherein the first half of said input signal has the same duty cycle as the second half of the input signal but shifted in phase. The present invention also concerns a wireless transceiver and a radio transmission device.

The rapid development of the telecommunications industry have made wireless handheld devices like cell phones, pagers, two-way messaging devices, etc. massively popular, creating a need for new electronic components and circuits in both mobile and base station systems as competition drives the introduction of expanded capabilities.
Radio frequency power amplifiers contribute to the power consumption in the communications systems. To extend battery life in mobile units, and to reduce operating costs of base stations, there is a need to develop new amplifiers to replace the traditionally inefficient, power wasting, elderly designs currently in use.
Many contemporary base station amplifiers employ complex techniques to realize amplifiers with a high degree of linearity over a broad frequency range. Unfortunately those solutions have a low efficiency.
Handset power amplifiers also suffer from efficiency problems, often more critical than those for base stations as the power supply for mobile user equipment is strictly limited. Today's smaller, faster and more effective portable electronics demand high power with only little losses.
For many decades, linear power amplifiers of the Class A and/or Class AB type have been employed as radio frequency power amplifiers for cellular base station systems. These amplifiers are based on the operation of a transistor in its linear mode. As such, they are however limited in their ability to efficiently amplify radio frequency signals.
The Doherty amplifier is another common method to increase the efficiency in the context of power amplification. However, the Doherty method is often demanding to implement. In practical cases a Doherty amplifier seldom reaches an efficiency level above 50%.
Switching mode amplifiers have been used for quite some time in various electronic systems including audio power amplifiers and switching power supply circuits. In switching mode amplifiers, the transistor is operated as a switch. Switching mode amplifiers suffer however from the existence of some fundamental limits, such as large parasitic capacitance, which may prevent many transistors from working well at high power and frequency.
The Class-D amplifier architecture has often been used in low frequency and audio frequency applications. The traditional Class D amplifier, or Voltage Mode Class D amplifier, is defined as a switching circuit that results in the generation of a half-sinusoidal current waveform and a square voltage waveform. Voltage Mode Class D amplifiers are however afflicted with a number of problems that make them awkward to realize. Firstly, the availability of suitable devices for the upper switch is limited. Secondly, device parasitics such as drain-source capacitance and lead inductance result in losses in each cycle.
The Current Mode Class D amplifiers that has emerged, has proven to be feasible to implement also at high frequencies and have output levels with good bandwidth and peak drain efficiency. However, it is very important to optimize the harmonic terminations in the output filter to get the square current wave form and the half wave sinusoidal voltage waveform to minimize overlaps. Nearly ideal waveforms are critical to maximizing efficiency, as an overlap of the current and voltage waveforms correspond to power dissipated in the switch and cause rapid efficiency degradation.
Thus there is a problem to develop a Current Mode Class D amplifier with harmonic terminations in the output filter to get the square current wave form and the half wave sinusoidal voltage waveform to minimize overlaps, in order to reach a high degree of efficiency.
Amplitude modulation is a technique used in electronic communication, most commonly for transmitting information via a radio carrier wave. Amplitude modulation works by varying the strength of the transmitted signal in relation to the information being sent. For example, changes in the signal strength can be used to reflect the sounds to be reproduced by a speaker. Unfortunately, Current Mode Class D amplifiers loose efficiency when working in back off i.e. working below full effect, why they at present are unsuitable to be used for amplitude modulation of a radio signal. Thus there is a problem with efficiency in back off.
Another problem with Current Mode Class D amplifiers is that they occasionally may suffer from the occurrence of large voltage spikes when symmetrically pulse width modulated. This prevents practical usage since the switching units can break because of the large voltage spikes.


Previous systems and methods for personalizing web content presented to a user has been achieved in a decentralized manner by storing personal data relating to the user repeatedly by different content providing servers. Consequently, the consistency of the data stored can be inconsistent and, in some cases, incomplete. Additionally, the user does not have any control over the dissemination of the content. The present invention provides a system, apparatus and method whereby web related data is modified in communications between user equipment units and content providing servers. The modification to the web related data is carried out by a proxy server (20) having access to centrally stored personal data in a data store (22). Consequently, data provided to content providing servers is consistent, complete and the information provided by the content providing servers to the user has a higher degree of relevance to the user.

Using the Internet, it is known for a user of a personal computer to download web content, for example a web page from a web server. Personalisation of the web content is increasingly being required. Personalisation of web content enables providers of the web content to tailor the web content to preferences of the user as well as personal circumstances of the user. It is envisaged that personalisation of the web content will add value to services provided over the Internet, especially e-commerce. Of course, personalisation of the web content can only be achieved with information about the user. Furthermore, the web content is, of course, provided by different respective content providers.
A number of approaches exist to personalising the web content. Consequently, each of the content providers can typically employ different approaches having different strategies and using different software tools for personalising the web content. Additionally, the content providers can repeatedly request information about the user, resulting in inconsistent information about the user being stored by the content providers. In some cases, the content providers do not possess a sufficient amount of information about the user, resulting in further scope existing to better personalise the web content and hence to deliver the web content in a form that is more in accordance with needs and/or personal circumstances of the user.
Mechanisms, for example Cookies, provided by web browser software (hereinafter referred to as a "web browser") have been known to be used to personalise the web content to a limited extent. Cookies are small pieces of information sent by the web server to the web browser, for example, to track origins of requests for web content. However, Cookies only permit, a limited amount of data to be stored locally by the web browser. Also, Cookies are not secure and many users distrust and/or refuse to accept Cookies.
Additionally, in the cases of a number of known approaches to personalising the web content, once submitted, the user has little or no control over the information. Therefore, a risk exists that any of the information about the user submitted to content providers can be disseminated without of the user knowing of such dissemination.

System, apparatus and method for personalising web content


The power source contains a plurality of batteries stacked in more than three tiers within a battery case divided into a first sub holder case and second sub holder case, and the first sub holder case contains the batteries in a larger number of tiers than the second sub holder case. An intermediary duct is provided between the two sub holder cases, and a first outer duct and a second outer duct are respectively provided outside each of the two sub holder cases. The batteries in the holder case are cooled by the cooling air which flows from the intermediary duct through the holder case into the outer duct for exhaustion. Further, the second outer duct is designed to experience a larger pressure loss than the first outer duct.

1. Field of the Invention
The present invention relates generally to an electric power source which contains a plurality of batteries in its battery case and pertains specifically to a power source which is used to supply a power to a motor mainly for driving a vehicle.
2. Description of the Related Art
An electric motor vehicle, such as an electric car and a hybrid car which is designed to travel optionally with an internal combustion engine or with an electric motor, uses an electric power source, having a multitude of batteries interconnected, as a power unit for supplying electric power to a drive motor.
An electric power source used for this kind of application is designed to provide a high output voltage so that a large amount electricity may be supplied to a motor which requires a high power. In order to satisfy such a design need, a multitude of batteries, interconnected in series, are contained in a holder case. For example, a currently commercially available power source mounted to a hybrid car has hundreds of batteries interconnected in series to generate a high output voltage to an extent of several hundreds. Such power source is designed to have five or six pieces of batteries interconnected in series to form a battery module, and further a multitude of such battery modules are interconnected in series within a holder case.
In the electric power source mounted to an electric motor vehicle such as a hybrid car, when the vehicle needs a burst of speed, a large current is discharged to accelerate the motor, and when the vehicle is slowed down or when the vehicle travels down on a slope, a large current is charged by means of a regenerative brake. Such a discharging and charging cycle may often cause the battery to be heated up to a considerably high temperature. In addition, when the battery is used in the surroundings at higher temperatures like in a summer season, the battery temperature tends to be elevated to even higher degrees. In view of these factors, when a power source contains a multitude of batteries in its holder case, it is vital to cool each of contained batteries both effectively and uniformly. This is because various disadvantages are likely to occur when a temperature difference exists among those many batteries being cooled. For example, a battery having undergone a high temperature tends to be degraded and thus results in a reduced amount of real charge capacity for reaching a full charge. When a battery with a reduced amount of real charge capacity is interconnected in series to be charged and discharged with the same current, the battery is very likely to be overcharged or overdischarged. This happens when a full charge capacity and a full discharge capacity have become smaller. A remarkable decrease is caused to a battery in its property or performance through an overcharge and overdischarge, so that a battery with a reduced, real amount of charge capacity is accelerated into degradation. Especially when the battery temperature is elevated to higher degrees, the battery is even more likely to be degraded that much. For these reasons, when an electric power source contains a multitude of batteries in its holder case, it is important to uniformly cool all the batteries so that a temperature irregularity may be prevented.
There have been developed a variety of battery structures to overcome such drawbacks resulting from the temperature irregularity. Refer to Japanese Laid-Open Patent Publication Nos. 2001-313090, 2002-50412 and 1999-329518.


A method and apparatus for facilitating availability of object data types at runtime are described. In one embodiment, the method may include parsing debug information generated by a compiler for a software program, identifying in the debug information desired data types and objects associated with the desired data types, and creating for each desired data type an object list including references to associated objects. The method may further include adding resulting object lists to a set of object files generated by the compiler for the software program. The set of object files with the added object lists may then be used by a linker when creating an executable file for the software program.

When creating source code of a program, a programmer typically declares variables using names and data types, and specifies functions that perform operations on the variables. In addition, the programmer may need to provide memory allocation for the variables. Because it is a manual process, a reference specified by the programmer may not be valid (e.g., may refer to a non-existent memory location, a variable being referenced may not be initialized, the memory location might have been freed, etc.). In some programming languages, it is possible to mismatch the types of the reference and the referenced object.
During runtime, when a function passes a reference to an object, the program may terminate abnormally if the reference was specified by the programmer incorrectly. In addition, the program may terminate abnormally if the object being referenced has a data type that is inconsistent with an operation that needs to be performed on the object by the function.
In some programming languages (e.g., C), debugging a problem caused by an invalid reference is not a trivial task because data type information is not available at runtime for certain variables. In particular, the data type information is only available in a few situations such as if local variables are initialized by explicit function calls. As to global and initialized automatic variables, they are initialized by the compiler and their data type information is not expressly stated in the object file created by the compiler.
The most common solution for the above problem uses heuristics to determine whether a reference passed by a function is for an object initialized by the compiler. If so, an error message is returned indicating that the reference is invalid. However, this solution leads to false positives because it does not account for references to objects initialized by the compiler that have a proper data type. Furthermore, the above solution cannot track references to objects that do not have a proper data type even though they were not initialized by the compiler.

Facilitating availability of object data types at runtime


The present invention provides a single shell-pass shell-and-tube heat exchanger with helical baffles, where within a single pitch, the helical baffles are separated into inner and outer parts along the radial direction of the shell. In the central portion of the inner space of the shell, an inner non-continuous helical form is employed; in other portion outside the central portion, doughnut shaped helical baffles with continuous curved surfaces are arranged to form an outer continuous helical baffle, and the outer helical baffles are arranged to surround the inner helical baffles. Furthermore, the present invention relates to a multiple shell-pass shell-and-tube heat exchanger with helical baffles, in which complete continuous helical baffles are provided in shell-sides other than the inner shell-pass, while non-continuous helical baffles or other flow guide means are employed in the inner shell-pass. The present invention makes flow patterns of fluids on the shell side more desirable, leading to a reduced flow pressure drop, and mitigate fouling, thus the heat transfer rate is improved and the service life of the heat exchanger is increased. The present invention also provides two methods for manufacture of continuous helical baffles, which ensure the concentricity of the tube bundle holes on each continuous helical baffle so as to facilitate installation of heat exchange tube bundles.

Among others, heat exchangers are important apparatuses that are widely used in petrochemical industry, energy power industry, metallurgical industry, refrigeration engineering and seawater desalination. Among heat exchange equipments, the shell-and-tube heat exchangers are predominant, accounting for about 55-70%. This type of heat exchanger has a simple structure that mainly contains two parts, i.e., heat exchange tube bundles and shells. When one kind of fluid flows inside the tubes, and the other kind of fluid flows outside the tubes against the shell side, the two fluids indirectly exchange heat through the tube wall.
In a shell-and-tube heat exchanger, a more important function of the baffles, besides supporting the tube bundles, is to change the flow direction of fluid in the shell-sides so as to enhance heat transfer rate.
There exist many problems in the conventional segmental baffles, e.g., (1) a high pressure drop occurs since the segmental baffles make fluid perpendicularly impact the shell wall and the tubes, leading to an increased power load; (2) the fluid with high speed crosses the heat exchange bundles laterally, inducing vibrations of heat exchange tubes and thus a reduced service life; (3) the heat transfer rates decrease due to a flow stagnation region generated at the joint of baffles and shell walls, where fouling tends to accumulate as well; and (4) the mass flow rate laterally crossing tube bundles is efficiently decreased due to the bypass flows and leaking flows which exist between baffles and shell walls and between heat exchange tubes and baffles, resulting in a reduced heat transfer rate on the shell side.
Aimed at the above problems, some new kinds of shell-and-tube heat exchangers with helical baffles are developed in recent years. In these newly developed heat exchangers, baffles are arranged in helix to make the fluid on the shell side of the heat exchanger flow along a helical path, resulting in an affirmative reduction in flow pressure drop on the shell side and an enhancement in heat transfer rate. Heat exchangers with helical baffles in the prior art may be classified into two categories, one being heat exchangers with non-continuous helical baffles employing non-continuous helical baffles formed of a plurality of fan or oval shaped flat plates, with the non-continuous helical baffles in a continuously overlap form (see CN Patent Application No. 99241930.1 and U.S. Pat. No. 6,827,138 B1,) or in a staggered helical form (see CN Patent Application No. 200320106763.1); the other being heat exchangers with continuous helical baffles employing continuous helix (see CN Patent Application No. 200510043033.5). As compared with non-continuous helical baffles, the continuous helical baffles make the flow assume a helical pattern, which further reduces pressure drop and leakage. However its manufacture is more complicated than in the case of non-continuous helical baffles. This is especially the case when the pitch is large, that is, the helical surface becomes relatively steep in portions close to the central axis, which makes it more difficult, or even impossible to manufacture curved surfaces and to position and form holes on these surfaces. Currently, in order to make it easier for fluid on the shell side to accomplish helical flow patterns, most of shell-and-tube heat exchangers with continuous helical baffles are additionally installed with a central tube of a certain diameter along the centre axis. This somehow mitigates the difficulty in the manufacture of continuous helical baffles, however, it relatively decreases the efficient heat exchange area of heat exchangers since no fluid passes through the central tube, and the diameter of the central tube increases with the increase of baffle pitch.
Moreover, some researches show that, given same tube-side arrangements and same shell-side flow rate, the current single shell-pass heat exchanger with helical baffles has higher heat exchange capacity under the same shell-side pressure drop. While its pressure loss is lower than that of a traditional heat exchanger with segmental baffles, however, its heat exchange capacity is also lower, simultaneously which can hardly meet users' requirement. To enhance shell side heat transfer rate, a multiple shell-pass shell-and-tube heat exchanger with continuous helical baffles was proposed (see CN Patent Application No. 200610041949.1). Given same number of tube-side and same flow rate, the velocity of fluid in a shell-side in a multiple shell-pass shell-and-tube heat exchanger is higher than that in a single shell-pass shell-and-tube heat exchanger. Therefore the heat exchange coefficient becomes higher, that is, a higher heat transfer rate is achieved.
A non-continuous helical baffle is formed by splicing a plurality of fan shaped or oval shaped flat plates. This has an advantage that manufacture is easy. Generally, a central pole is employed for positioning the center and the volume occupied by the central pole is small. However, there is a relatively large leakage, which affects heat exchange. Continuous helical baffles are formed by splicing complete continuous helical baffles of many cycles, each cycle being a continuous helical curved plate, such that the flow behavior approximates to a helical pattern. This has an advantage that pressure drop and leakage are reduced and heat transfer coefficient is higher, however, when the pitch is large, the helical surface becomes relatively steep at portions close to the central axis, where it is difficult to manufacture the continuous helical surfaces. Generally, a central tube is employed to fit the helical structure inside of the helix. However, as heat exchange tubes can not be arranged at the location of the central tube, the effective heat exchange area of the heat exchanger is relatively decreased, and part of the heat exchanger volume is occupied, thus leading to a decreased compactness. Currently, there is no heat exchanger with helical baffles having the advantages of both continuous helical baffles and non-continuous helical baffles.
Further, the shell-and-tube heat exchangers used in industries are generally in form of a horizontal type. The continuous helical baffles may reduce leakage, however when the fluid on the shell side is such a medium that tends to foul, fouling can accumulate at the bottom of the horizontally arranged shell-and-tube heat exchanger due to a low flow rate. Especially when the helical angle is small, a large amount of fouling will deposit and cleanup becomes difficult, thus resulting in a decreased heat transfer rates.

Single shell-pass or multiple shell-pass shell-and-tube heat exchanger with helical baffles


A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.

Data prefetching, or early fetching of data into a cache, is a feature implemented in a processor to augment a probability of having requested data in a timely manner and thereby maintain a high processing efficiency. When the data is available at a first cache level, a number of cycles where the processor stalls may be reduced. For example, a processor may stall when waiting for data to come back from more distant (with respect to the processor) cache levels or memory.
Currently, many data prefetchers in modern state-of-the art processors work within page boundaries. Every prefetch request that crosses a page boundary is dropped by the data prefetcher. This is because every time the processor crosses the page boundary, it should guarantee it can obtain a translation from virtual to physical addresses. The translation lookaside buffer (TLB) may not always have the address translation and the data prefetcher cannot access the TLB to obtain the address translation. As a result, a data prefetcher may be very aggressive in making data requests in advance of next addresses, but if it crosses a page boundary, it cannot generate that request because it does not have the physical translation. As the accuracy of data prefetchers increases, this inability to move beyond page boundaries can result in processor latency and performance setbacks.

Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset


A stress test apparatus and method for a semiconductor memory device with a plurality of memory cell arrays. The stress test apparatus comprises a plurality of plate terminals connected to one another, each of the plate terminals being connected to a plurality of storage capacitors, first and second switching elements connected in common to the plate terminals, a plate voltage generator connected to the first switching element, a stress signal generator connected to the second switching element, and a switching control signal generator for generating a switching control signal to control the first and second switching elements. According to the present invention, a cell plate voltage is applied and varied to stress the storage capacitors without driving word lines. Therefore, the storage capacitor stressing operation is simply performed, the stress test time is reduced and the cost is cut down.

1. Field of the Invention
The present invention relates in general to a stress test apparatus and method for a semiconductor memory device, and more particularly to a stress test apparatus and method in which a cell plate voltage of a dynamic random access memory (referred to hereinafter as DRAM) is applied and varied to stress storage capacitors at the same time and within a short time.
2. Description of the Prior Art
Generally, a stress test operation is for previously removing a chip with a potential fault to prevent an error from occurring when a semiconductor memory device is in use.
In a conventional storage capacitor stressing method, a stress test operation is enabled by fixing a cell plate voltage to half a supply voltage (referred to hereinafter as "half voltage") Vcc/2 and driving a word line. In more detail, in a standby mode, a bit line is precharged with the half voltage Vcc/2, a supply voltage Vcc or a ground voltage Gnd is stored at a storage node, and the half voltage Vcc/2 is applied to a cell plate terminal. If the word line is driven under the above condition, a voltage Vcc/2+.DELTA.V or Vcc/2-.DELTA.V is generated on the bit line and storage node by the charge distribution through a turned-on cell transistor. At this time, the cell plate terminal remains still at the half voltage Vcc/2.
When a sense amplifier is operated, the voltage on the bit line and storage node is changed to the supply voltage Vcc or the ground voltage Gnd, and the cell plate terminal remains still at the half voltage Vcc/2. As a result, in the conventional stressing method, a voltage across a storage capacitor is not more than the half voltage Vcc/2 even though the supply voltage Vcc is raised. Also, the word line must be disabled after being enabled for the stress test operation. In this connection, to stress all cells in the chip, the word line enable/disable operations must be repeated with complexity and inefficiency. Further, in the case where the stress operation is performed with respect to 10 to 100 word lines at a time, a high voltage must be applied to drive the word lines. However, the application of such a high voltage results in a severe damage in cell transistors and storage capacitors. For this reason, it is impossible to make the word line drive voltage high. To the contrary, in the case where a low voltage is applied to drive the word lines, it is impossible to perform the stress test operation through the word lines.
As mentioned above, in the conventional stress test method, much time is required in performing the stress test operation with respect to all the cells in the chip. Also, because the voltage across the storage capacitor has such a small value of Vcc/2 at most, a long stress time is required in removing a fault in the storage capacitor. Further, there is a limitation in increasing the voltage across the storage capacitor.

Stress test apparatus and method for semiconductor memory device

Hyundai Electronics Industries Co., Ltd.