A method of executing a tennis stroke includes covering a knee of a tennis player with a knee pad during tennis play. The covered knee of the player is placed on a tennis court surface with the knee pad positioned between the knee and the surface. The tennis racket is swung toward a tennis ball so as to hit the tennis ball with the racket either while the covered knee is on the tennis court surface, or just prior to the knee contacting the tennis court surface.

1. Field of the Invention
The present invention relates to the field of playing tennis.
2. Description of the Background Art
Tennis is a well known game which is played on a tennis court having a surface centrally divided by a vertical net. Each player has a racket and generally plays bare-legged, with men players typically wearing short pants and women players often wearing skirts or short pants.
During the game of tennis, players hit the ball over the net with the racket. One object of the game is to hit the ball over the net so that the ball lands in-bounds in the opponent's court, but at a location out of effective stroking reach of the opponent, whereby the opponent cannot successfully execute a stroke to return the ball in-bounds.
There remains a need in the art for improved methods of executing tennis strokes in difficult ball-return situations.


Contact holes through a dielectric are formed by forming a layer of polysilicon having a thickness between 0.02 um and 0.15 um inclusive on the dielectric, forming a layer of resist having a thickness between 0.4 um and 0.6 um inclusive on the layer of polysilicon, making a mask of the layer of resist, using it to form a mask in the layer of polysilicon and etching contact holes in the dielectric by exposing it to etching gasses through the apertures in the polysilicon mask. When the dielectric includes a layer of oxide adjacent the polysilicon mask and a layer of nitride between it and elements of the device, the resist mask is removed prior to etching the contact hole and a gas mixture of: C.sub.4 F.sub.8 ; one of Ar, H, F; CO; CF.sub.4 or C.sub.2 F.sub.6 is used. Contact holes are made through a dielectric to conductors in a substrate by the same method, and desired cross sections are obtained by using a second resist mask and a selective etch for the polysilicon followed by a selective etch for the dielectric. These structures can be stacked and suitable interconnections made by the described method. Contact holes to gate electrodes can be etched using the basic process.

Elements of solid state devices are generally formed near the surface of a silicon substrate and covered with a layer of dielectric. Electrical connections to the elements are made by filling contact holes etched through the layer of dielectric with metal. Etching the contact holes by exposing the dielectric to appropriate gasses in a plasma through openings in a resist mask is sometimes uncontrollable because the carbon liberated from the resist mask forms a polymer in the contact holes that terminates the etching process before the contact holes reach a desired element.
In order to overcome this problem, a layer of polysilicon has been formed on the dielectric layer and made into a mask having apertures therein by exposing it to etching gasses through openings in a resist mask that is formed on top of it. The resist mask is removed and the contact holes are etched into the dielectric by exposing it to suitable ionized gasses through the apertures in the polysilicon mask. Because the resist mask is not present during the latter process, less carbon is produced and less polymer formed. Examples of this process are described in: U.S. Pat. No. 5,028,550 issued on Jul. 2, 1991 and entitled "Method of Manufacturing Semiconductor Device; U.S. Pat. No. 4,473,435 issued on Sep. 25, 1984 entitled "Plasma Etchant Mixture" and U.S. Pat. No. 5,279,989 issued on Jan. 18, 1994 and entitled "Method For Forming Miniature Contacts of Highly Integrated Semiconductor Devices."
As the dimensions of devices in a direction parallel to the substrate decrease, there is a need for the diameter of contact holes to be reduced. As noted in the U.S. Pat. No. 5,279,989, there is a limit to the minimum diameter of contact hole that can be attained using the resist masking process because the minimum diameter of the apertures formed in the polysilicon mask is too large. Although not stated in the patent, this diameter is 0.6 um when standard techniques are used. In order to effectively reduce the diameter of the apertures in the polysilicon mask in accordance with this patent, the resist mask used to form the apertures is removed and the new exposed polysilicon mask is coated with silicon dioxide. The silicon dioxide layer is then entirely removed except for the portion of it in contact with the inner edges of the apertures, which is referred to as a spacer, by a blanket etching process, but the polysilicon layer is not affected. Access holes are then etched in the dielectric by exposing it to etching gasses through the spacers that have a smaller diameter than the apertures in the polysilicon mask.

Etching high aspect contact holes in solid state devices

International Business Machines Corporation


A helmet carrying and hanger assembly is provided including. an elongated rod having a pair of ends. A plurality of helmet coupling mechanisms are provided for mounting the helmets to the elongated rod. A handle is coupled to the rod for carrying purposes. Finally, a mounting assembly is included for mounting the elongated rod to a fence.

1. Field of the Invention
The present invention relates to a helmet carrying and hanger assembly and more particularly pertains to maintaining a plurality of helmets in an easily carried and organized orientation.
2. Description of the Prior Art
The use of helmet hangers is known in the prior art. More specifically, helmet hangers heretofore devised and utilized for the purpose of organizing helmets are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
By way of example, the prior art includes U.S. Pat. No. 4,193,495; U.S. Pat. No. 5,294,005; U.S. Pat. No. Des. 357,777; U.S. Pat. No. 4,629,065; and U.S. Pat. No. 4,793,532.
In this respect, the helmet carrying and hanger assembly according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of maintaining a plurality of helmets in an easily carried and organized orientation.
Therefore, it can be appreciated that there exists a continuing need for a new and improved helmet carrying and hanger assembly which can be used for maintaining a plurality of helmets in an easily carried and organized orientation. In this regard, the present invention substantially fulfills this need.


A solid-state imaging device includes: a sensor unit; a vertical scanning unit and a horizontal scanning unit; column amplifier units provided at respective vertical signal lines corresponding to columns in the sensor unit and amplifying signal charges read out to the vertical signal lines; a bias current adjustment unit controlling current flowing in the vertical signal lines by changing bias current of the column amplifier units; a signal processing unit processing signal charges read out to the vertical signal lines and amplified at the column amplifier units into image signals to be outputted; an output unit to which signals outputted from the signal processing unit are supplied; a drive signal generation unit supplying drive signals to the vertical scanning unit, the horizontal scanning unit, the signal processing unit and the output unit; and an input unit supplying plural drive mode signals to the drive signal generation unit.

1. Field of the Invention
The invention relates to a solid-state imaging device applied to, for example, an image input system, and an imaging apparatus using the same.
2. Description of the Related Art
As an imaging apparatus using a solid-state imaging device, a digital camera, a PC camera, an optical mouse, a portable TV telephone and the like are developed in recent years. These apparatuses require low voltage and low power consumption from the point of increasing the battery operating time or miniaturization, in addition to from the point of image quality. Since a CCD sensor has difficulties in the above points, a MOS-type solid-state imaging device is often applied. The MOS-type solid-state imaging device has characteristics such as single power supply, lower power consumption, system-on-chip, and further has large degree of freedom in reading out. For example, it is possible to output only part of an image (cutting operation) or output image information discontinuously (thinning-out operation).
A MOS-type solid-state imaging device in related arts will be explained with reference to FIG. 6.
In FIG. 6, a MOS-type solid-state imaging device 1 includes a sensor unit 2 in which many unit pixels including photo diodes performing photoelectric conversion and MOS switches are arranged in a matrix state, a vertical scanning circuit 3 and a horizontal scanning circuit 4 driving the sensor unit 2, a CDS (Correlated Double Sampling)/signal holding circuit 5 receiving signals of a row of pixels in the sensor unit 2, an output amplifier 6, a timing generator circuit 7 generating pulses for operating respective units of the vertical scanning circuit 3, the horizontal scanning circuit 4, the CDS/signal holding circuit 5 and the output amplifier 6 and a serial interface 8 (refer to JP-A-2002-209149 (Patent Document 1)).
Vertical scanning lines 10 from the vertical scanning circuit 3 are commonly connected to pixels of respective rows in the sensor unit 2, and vertical scanning pulses φV [φV1, φV2, . . . φVn] are simultaneously supplied from the vertical scanning circuit 3 to pixels of respective rows through the vertical scanning lines 10. Vertical signal lines 11 are commonly connected to pixels of respective columns in the sensor unit 2, and the respective vertical signal lines 11 are connected to a horizontal signal line 12 through the CDS/signal holding circuit 5. The horizontal signal line 12 is connected to the input side of the output amplifier 6. The horizontal scanning circuit 4 supplies horizontal scanning pulses φH[φH1, φH2, . . . φHn] for selecting pixel signals from the CDS/signal holding circuit 5 and outputting them to the horizontal signal line 12 to horizontal switches of the CDS/signal holding circuit 5. Serial data is supplied to the serial interface 8 from the outside. A synchronizing signal and a clock signal are supplied to the serial interface 8 and the timing generator circuit 7 from the outside.
In the above CMOS-type solid-state imaging device 1, the serial interface 8 receives data from the outside, controlling the operation of the timing generator circuit 7 according to the data. The timing generator circuit 7 generates drive pulses for operating the vertical scanning circuit 3, the horizontal scanning circuit 4, the CDS/signal holding circuit 5 and the output amplifier 6 according to data, supplying them to respective units. The sensor unit 2 is scanned by the vertical scanning circuit 3, that is to say, rows of pixels are sequentially selected by the vertical selection pulses φV [φV1, φV2, . . . φVn] from the vertical scanning circuit 3, and pixel signals in the selected (scanned) row are outputted to the CDS/signal holding circuit 5 through the vertical signal lines 11. The CDS/signal holding circuit 5 receives the signals of a row and holds the signals whose offset components peculiar to respective pixels (correspond to fixed-pattern noise components) are subtracted. Then, the horizontal switches are sequentially turned on by the horizontal scanning pulses φH [φH1, φH2, . . . φHn] from the horizontal scanning circuit 4 and pixel signals of a row held in the CDS/signal holding circuit 5 are sequentially read out to the output amplifier 6 through the horizontal signal line 12. The signals are amplified in the output amplifier 6 to be outputted to an output terminal "t out" as analog signals.

Solid-state imaging device and imaging apparatus utilizing a dynamic bias current for reduced power consumption


A profile control method for controlling a profile in the width direction of a sheet by using a plurality of actuators, includes calculating an envelope profile connecting local peaks of the profile; and calculating a manipulated value of each actuator with the objective of optimizing 2σ of the profile and the envelope profile.

1. Field of the Invention
The present invention relates to a profile control method for a sheet-manufacturing process of paper, films, and the like (hereinafter, collectively referred to as sheet) and the system thereof.
Priority is claimed on Japanese Patent Application No. 2006-092756, filed Mar. 30, 2006, the content of which is incorporated herein by reference.
2. Description of the Related Art
In a sheet manufacturing process of paper, films, and the like, to make the quality of sheets in the width direction uniform is the most important factor in characterizing the product quality. For example, T. Sasaki, M. Matsuda, S. Yamamoto, and I. Hashimoto, "Optimizing Control of Basis Weight Profile in Paper Machines based on Virtual Slice-bolt Position," KAGAKU KOGAKU RONBUNSHU, Vol. 25, No. 6, 1999, pp. 947-954, and Japanese Published Unexamined Patent Application, First Publication No. (JP-A) H2-139488 have disclosed a technology, in which in sheet-making paper by using a paper machine, paper is measured for the basis weight (the weight of paper in grams per square meter: g/m2), while the paper is scanned in the width direction, thereby optimizing the variation (2σ) of deviations with respect to the mean value of basis weight to make the basis weight uniform in the width direction of the paper. Hereinafter, a specific description will be given for the technology.
In this instance, a plurality of basis weight data (t pieces) between one-way scans in the width direction of paper is given as RV(i) (i=1, 2, . . . , t), and a set of data based on deviations between the mean value RVAV of the basis weight data concerned RV(i) and each of the basis weight data RV(i) are called basis weight raw profile. Where the basis weight raw profile is given as R(i), it is expressed as R(i)=RV(i)−RVAV (i=1, 2, . . . , t). Further, of a plurality of actuators (N units), the above basis weight raw profile changes on operation of the kth actuator. In this instance, the number of basis weight data RV(i) corresponding to the center of a change in profile is called a kth actuator position correspondence, which is given as SPT(k). In other words, SPT(k) is an integer value from 1 to t.
Further, virtual actuators (the total number N−1 unit) are defined at an intermediate position of adjacent actuators, and the number of basis weight data RV(i) corresponding to the center of the change in profile due to operation of the virtual actuator is called a virtual actuator position correspondence, which is given as SP(i) (i=1, 2, . . . , 2N−1). In this instance, basis weight raw profiles are averaged with respect to the position of an actually available actuator and that of a virtually defined actuator, thereby defining a virtual actuator corresponding profile P(i) which is expressed by the formula (1) given below.
                                          P                                      (              i              )                                =                                    1              MPT                                                                  ∑                                  j                  =                                      -                    h                                                                    +                  h                                                                                R                                                        (                                                                  SP                                                                          (                          i                          )                                                                    +                      j                                        )                                                                                (                                                            i                      =                      1                                        ,                    …                                                                                ,                                                                  2                        *                        N                                            -                      1                                                        )                                                                                where          ,                      MPT            =                          a                                                                                first                                                                                odd                                                                                number                                                                                of                                                                                no                                                                                less                                                                                than                                                                                t                                                      2                                        N                                    -                  1                                                                                h          =                                    MPT              -              1                        2                                              (        1        )
In the above formula (1), the virtual actuator position correspondence SP(i) is expressed by the following formulae (2) and (3). In other words, an odd-numbered virtual actuator position correspondence is equal to a kth actuator position correspondence, whereas an even-numbered virtual actuator position correspondence is obtained by rounding the mean value of the kth actuator position correspondence of an adjacent actuator to obtain an integer number.SP(2k−1)=SPT(k)   (2)
                              SP                                (                          2                            k                        )                          =                  int          (                                                    SPT                                                  (                  k                  )                                            +                              SPT                                                  (                                      k                    +                    1                                    )                                                      2                    )                                    (        3        )                            k=1, . . . , and N (N: the number of actuators)
As shown in the above formula (1), the virtual actuator corresponding profile P(i) is a profile consisting of points which is two times the total number of actuators (N) minus 1 (i.e., N×2−1), which is obtained by averaging basis weight raw profiles with respect to the position of an actually available actuator and that of a virtually defined actuator. Each of the actuators is controlled, with the objective of optimizing mountain/valley portions of the above-described virtual actuator corresponding profile P(i), that is, variation (2σ) of deviations with respect to mean values, thereby making it possible to make the basis weight uniform in the width direction of paper.
In this instance, the manipulated value of each of the actuators is given as X(j) (j=1, 2, . . . , N). In general, where each of the actuators arranged in the width direction is operated, a profile is changed not only at a position corresponding to the thus operated actuator but also in the vicinity thereof. This phenomenon is called a width-direction process interference. Where a variation of an ith virtual actuator corresponding profile P(i) with respect to the above-described manipulated value X(j) is given as W(i,j) and a matrix expressing the width-direction process interference (process interference matrix) is defined as W={W(i,j)}, a matrix P of the virtual actuator corresponding profile is expressed by the formula (4) shown below.P=X·tW+P0 (tW is a transposed matrix of W)   (4)where,
P=(P(1),P(2), . . . , P(2·N−1)): Virtual actuator corresponding profile
P0=(P0(1), P0(2), . . . , P0(2·N−1)): Initial value of the virtual actuator corresponding profile
X=(X(1),X(2), . . . ,X(N)): Manipulated value
  W  =            [                                                                  W                                                  (                                      1                    ,                    1                                    )                                                                                W                                                  (                                      1                    ,                    2                                    )                                                                                …                                                                                W                                                  (                                      1                    ,                    N                                    )                                                                                W                                            (                                  2                  ,                  1                                )                                                                                W                                                  (                                                                                2                        ·                        N                                            -                      1                                        ,                    1                                    )                                                                                …                                                                                W                                                  (                                                                                2                        ·                        N                                            -                      1                                        ,                    N                                    )                                                                        ]                  :      Process interference matrix
Further, the virtual actuator corresponding profile P(i) expresses at all times a deviation with respect to a mean value. Thus, assuming that the mean value of the virtual actuator corresponding profile P(i) is zero, an evaluation function E(X) indicating a variation of the deviation with respect to the above mean value is expressed by the formula (5) given below. Further, a gradient ∇E(X) of the evaluation function E(X) is expressed by the formula (6) given below.
                                                                        E                                                  (                  X                  )                                            =                                                ∑                                      i                    =                    1                                                                              2                      ·                      N                                        -                    1                                                                                P                                                              (                      i                      )                                                        2                                                                                =                              P                ·                                                                           t                                                      P                                                                                =                                                (                                                                                X                        t                                                                  W                                        +                                          P                      0                                                        )                                ·                                                                           t                                                                          (                                                                                X                          t                                                                        W                                            +                                              P                        0                                                              )                                                                                =                                                                    X                    t                                                                          W                    ·                                          W                      t                                                                          X                                +                                                      P                    0                                                                          W                    t                                                      X                                +                                                      X                    t                                                                          W                    t                                                                          P                    0                                                  +                                                      P                    0                                                                          P                    0                                                                                t                                                                                (        5        )            Assuming
            ∇              E                          (          X          )                      =          (                                    ∂                          E                                            (                X                )                                                          ∂                          X                                            (                1                )                                                    ,                              ∂                          E                                            (                X                )                                                          ∂                          X                                            (                2                )                                                    ,        …                                          ,                              ∂                          E                                            (                X                )                                                          ∂                          X                                            (                N                )                                                        )        ,The following is obtained.
                                                                        ∇                                  E                                                        (                    X                    )                                                              =                                                2                                                        X                    t                                                                          W                    ·                    W                                                  +                                  2                                                        P                    0                                                      W                                                                                =                                                2                                                                              (                                              P                        -                                                  P                          0                                                                    )                                        ·                    W                                                  +                                  2                                                        P                    0                                                      W                                                                                =                              2                                                  P                  ·                  W                                                                                (        6        )
In this instance, the changed manipulated value ΔX for making the evaluation function E(X) small most rapidly (in other words, minimizing the variation of deviations in the virtual actuator corresponding profile) is expressed based on the steepest descent method by using a sufficiently small positive value E to give the formula (7), which is also expressed in a scalar form as the formula (8) shown below.
                              Δ                                                              X                =                                            -                              ɛ                2                                      ·                          ∇                              E                                                  (                  X                  )                                                              =                                    -              ɛ                        ·            P            ·            W                                              (        7        )                                          Δ                                                                          X                                      (              j              )                                      =                              -            ɛ                    ·                                    ∑                              l                =                1                                                              2                  ·                  N                                -                1                                                                                P                                                        (                    i                    )                                                  ·                                  W                                                        (                                          i                      ,                      j                                        )                                                                                (                                                      j                    =                    1                                    ,                  …                                                                                ,                  N                                )                                                                        (        8        )
In other words, based on a plurality of basis weight data between one-way scans, a virtual actuator corresponding profile P(i) is calculated from the above formula (1), and the changed manipulated value ΔX of each actuator is also calculated from the above formula (8), thereby the changed manipulated value ΔX is used to control each of the actuators. It is, therefore, possible to make the basis weight uniform in the width direction of paper. Further, the technology disclosed in Sasaki et al. and JP-A 02-139488 is applicable as a profile control not only to paper but also to other sheets such as films in the manufacturing process.
Further, Japanese Published Unexamined Patent Application, First Publication No. (JP-A) 2005-186377 has disclosed a film-thickness control method for providing a preferable film winding shape by uniformizing local projections made on a thickness profile in the width direction of film in manufacturing processes. According to this film-thickness control method, first, a film pushed out from a slit-shaped film discharge port mounted on a T die is measured for thickness, while the film is scanned in the width direction, thereby obtaining a thickness profile indicating the variation of deviations with respect to the mean value of the thickness. Then, a first correction control value is determined so that the variation of the thickness profile will fall within a permissible range of use, and a second correction control value is determined so that projections of the thickness profile will fall within the permissible range of use. On the basis of the first correction control value and the second correction control value, the clearance of the film discharge port on the T die is controlled. More specifically, a plurality of adjusting bolts having the same function as the actuator in the above-described paper machine are arranged along a lip portion of the film discharge port. Each of the adjusting bolts is controlled for a vertical movement based on the first correction control value and the second correction control value, by which load applied to the lip portion is adjusted to control the clearance of the film discharge port and uniformize the film thickness.
Incidentally, according to the technology disclosed in the above Sasaki et al. and JP-A 02-139488, it is possible to uniformize a profile for the width direction of sheets by defining a virtual actuator corresponding profile P(i) and controlling each actuator with the objective of optimizing the variation (2σ) mainly based on the mean value of the profile concerned. However, the following problems exist regarding the quality of an entire roll finally wound up.
In processes of manufacturing a plastic film, in particular, a greater importance is placed on a preferable film winding shape after being wound up to a roll, rather than on the variation of thickness profiles in the width direction of the film. For example, where there are at all times projections greater than those in the vicinity at the same place of a thickness profile, the projections come to the surface as lumps on winding up the film to the roll, thus resulting in the deteriorated quality of the film winding shape in the roll. According to the technology disclosed in Sasaki et al. and JP-A 02-139488, there are some cases where the above-described projections which are greater than those in the vicinity may remain on the film.
On the other hand, according to the technology disclosed in JP-A 2005-186377, after a first correction control value is determined, a thickness profile variation is estimated by referring to a model, and a second correction control value is also determined for making the projections uniform in height. This method requires a greater calculation amount to result in an increased processing load on a calculating unit, which is problematic.
Further, where there is an unexpectedly great difference between the thickness profile variation calculated by referring to the model and an actual thickness profile variation due to disturbance, another problem is posed that a sufficient control performance is not maintained.

Profile control method and system therefor


This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased. The normally on and normally off JFET transistors are configured to achieve low voltage drop, low on resistance, high current density and high frequency operations.

1. Field of the Invention
This invention relates generally to the structure and fabrication process for manufacturing the junction field effect transistors (JFET). More particularly, this invention relates to a novel device structure and fabrication process for manufacturing normally on or normally off JFET transistors with low on-resistance for low voltage and high current density applications.
2. Description of the Prior Art
The semiconductor industry now faces a difficult challenge to satisfy the ever increased needs for providing transistors suitable for power management with voltage under three-volts. As the feature sizes of the integrated circuits (ICs) are becoming ever smaller and electronic devices are continuously being miniaturized, the voltages from AC or DC power sources for providing power to these devices are further dropped. Dropping the voltage from five volts to three volts results in a 25:9 reduction in power if the current density is maintained unchanged. At 1.8 volts, the power drops another 60%. However, the transient current loads can be very high. Under such operation conditions, the normal forward voltage drop for a p-n junction typically employed in a rectifier is about 0.9 volts. Most of the power will be consumed in the rectifying process. Power supply systems built with such types of p-n junctions would no longer be suitable for the low voltage applications. Even the Schottky barrier diodes with a forward voltage drop below 0.5 volts would not be a suitable solution to provide rectifiers or power switching devices for operation under the low voltage conditions.
The concept of junction filed effect transistors (JFETs) has been disclosed after the invention of the bipolar transistors. JFET transistor can be operated at very high frequency with high switching speed because the JFET transistors are operated with majority carriers. The JFET transistor are well known and employed commonly in a naturally on state when the gate bias is zero. Because of the naturally on state, the JFET transistor are not as widely used in the semiconductor industry as the MOSFET, i.e., the metal oxide semiconductor field effect transistors. In order to make the JFET transistors to operate in a naturally off state, the distance between the gates has to be reduced for the depletion regions from the gate to shut off the current conducting paths. Such naturally off JFET transistors are however not very useful in their conventional configurations due to the longer current channel thus limiting the current capacity with a high on-resistance. S. M. Sze in xe2x80x9cPhysics of Semiconductor Devicesxe2x80x9d disclosed one example of such configuration (John Wiley and Son, 1981 Second Edition, page 322). The normally off JFET transistors discussed by Sze are for high speed low power applications. The long current channel and high-on resistance limit the usefulness of JFET transistors particularly the high on-resistance prevents such transistors for application in modern electronic devices operated with extreme low voltages.
In U.S. Pat. No. 4,523,111 entitled xe2x80x9cNormally-Off Gate-Controlled Electric Circuit with Low On-Resistancexe2x80x9d, Baliga disclosed a JFET serially connected to an IGFET. The gate of IGFET is operated as the gate for the serially connected circuit. The gate of IGFET is applied to block the current to flow through a normally on JFET until the IGFET is turned on with a positively biased voltage above an IGFET threshold voltage. The on-resistance is the sum of the JFET resistance and the IGFET resistance. The on-resistance would not be adequate for extreme-low voltage applications required by modern electronic devices as discussed above. A similar invention is disclosed in U.S. Pat. No. 4,645,957 that is entitled xe2x80x9cNormally Off Semiconductor Device with Low On-Resistance and Circuit Analoguexe2x80x9d by Baliga. The JFET transistor is serially connected to a bipolar transistor to achieve the normally off state. Again, the on-resistance is the sum of the bipolar resistance and the JFET resistance and becomes too high for modern application to modern devices operated with extremely low voltages.
In U.S. Pat. No. 5,321,283 entitled xe2x80x9cHigh Frequency JFETxe2x80x9d Cogan et al. disclose a JFET for radio frequency (RF) operation at high frequency. The normally-on JFET transistors disclosed in this patent are operated with high voltage and not suitable to satisfy the requirements of modern portable electronic devices that require extremely low voltage and relatively high current capacity. Similarly, in U.S. Pat. No. 5,618,688 entitled xe2x80x9cMethod of Forming a Monolithic Semiconductor Integrated Circuit having an N-Channel JFETxe2x80x9d, Ruess et al disclose a normally on JFET transistor manufactured with BiCMOS processes. The JFET transistors disclosed in this patent are not suitable for low voltage and high current applications.
Therefore, a need still exits in the art of design and manufacture of transistor for low voltage power supply to provide a novel structural configuration and fabrication process that would resolve these difficulties. More specifically, it is preferably that the transistor for low voltage power supply has low on-resistance and high switching speed. It is further desirable to employ a simplified manufacture process to fabricate the power transistors such that highly reliable power transistors can be made available at a reasonably low production cost.
It is therefore an object of the present invention to provide new device structures and manufacture methods. The conventional JFET transistors, which are normally on with negatively biased off, are now provided with unconventional device structures such that the new JFET transistors are operated with low on-resistance and high current capacity that can be either normally on or normally off by arranging the distance between the gates. The unconventional JFET transistors of this invention provide special advantages for low-voltage low-resistance applications such that aforementioned limitations and difficulties as encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a new device structure and manufacture method to provide an unconventional JFET transistor with flexibly on-off adjustment. When the distance between the gates is sufficiently large, the JFET transistors are normally on with zero gate bias. As the distance between the gates is sufficiently small, the depletion regions from the gates fills the conduction paths between the gates thus the conduction paths are shut off and the JFET transistors are normally off with a zero gate bias and turned on with positive gate bias voltage. A positive or negative bias voltage applied to the gate causes the depletion regions surrounding the gate to shrink and open up the channel for current to pass through. Very low resistance current path is provided. Low voltage and high current density can be achieved by applying to the normally-off-positively-biased-on or normally-on-negatively-biased-off JFET transistors.
Another object of the present invention is to a new device structure and manufacture method for providing JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. The JFET transistors configured with unconventional structures are formed with low on-resistance, high current capacity and high switching speed. In a preferred embodiment, a horizontal JFET device is manufactured with standard CMOS processes with top and bottom gates controlling the drain to source current.
Another object of the present invention is to provide a new device structure and manufacture method for providing JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. In a preferred embodiment, a Schottky barrier is used as the top gate to achieve high switching speed. The barrier height is adjusted by controlling the implant dopant concentration or using different metal silicon or silicide/silicon systems.
Another object of the present invention is to provide a new device structure and manufacture method for JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. In a preferred embodiment, a deep implanted gate is formed in a multiple resistivity layers to provide gate control channel and to reduce the resistance of the drain/source ohmic contacts.
Another object of the present invention is to provide a new device structure and manufacture method for providing JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. In a preferred embodiment, a vertical gate pillar is used for a horizontal JFET transistor. The gate pillars can control the current flowed between deeper source and drain regions. Greater current density can be controlled without requiring greater silicon areas thus reducing the semiconductor real estate requirement for power transistor used for large current applications.
This invention is based on Applicant""s disclosures filed in the United States Patent and Trademark Office under the Disclosure Document Program. The disclosures filed are: 1) xe2x80x9cLow On Resistance Transistors and the Method of Makingxe2x80x9d #444899 filed on Sep. 24, 1998 and 2) xe2x80x9cNovel Structure of JFETs for Low Voltage Applicationsxe2x80x9d #444,874 filed on Sep. 17, 1998. This invention provides the advantages of low forward voltage drops between the source and drain. The voltage drops can be reduced to 0.1 volts or less and a current over 100 amperes for large size chips can also be achieved.
Briefly, in a preferred embodiment, the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. For a normally on JFET transistor, the depletion regions respond to a negative bias applied to the gate to turn off the current path. For a normally off JFET transistor, the depletion region responds to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased. Special configurations are disclosed for normally on and normally off JFET transistors to shorten the current channels and to achieve low on-resistance, high current density and high switching speed.
The present invention also discloses a method for manufacturing a junction field effect transistor (JFET) device. The method includes the steps of a) forming a plurality of gates separated by a distance W wherein a depletion region surrounds each gate. And, b) adjusting a threshold voltage for the JFET transistor by gradually increasing a channel doping concentration near the depletion regions surrounding the gates for gradually decreasing the threshold voltage for the JFET transistor. In a preferred embodiment, the step of gradually increasing a channel doping concentration near the depletion regions surrounding the gates for gradually decreasing the threshold voltage is a step of making the JFET transistor with a threshold voltage greater than zero for providing a normally on JFET transistor. In a different preferred embodiment, the step of gradually increasing a channel doping concentration near the depletion regions surrounding the gates for gradually decreasing the threshold voltage is a step of making the JFET transistor with a threshold voltage equal or less than zero for providing a normally on JFET transistor. The distance, W, between gates can be determined by lithography, etch, and/or thermal process and can be reduced by RTA thermal process for threshold voltage adjustment prior to metalization.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.

JFET structure and manufacture method for low on-resistance and low voltage application


A refrigerator door alarm system that includes a message circuit having a playback function that is triggered by a trigger circuit that detects movement of the magnetic gasket of the refrigerator door. The refrigerator door alarm system includes an alarm housing and an alarm circuit including a trigger circuit, a timer circuit responsive to the trigger circuit, a message circuit responsive to the trigger circuit, and a buzzer responsive to the timer circuit. The alarm housing includes an outwardly extended magnetic attachment side strip secured to an attachment strip support, a speaker grate, a buzzer grate, a message record button opening, a message play button opening, a battery compartment, and a magnetically actuated reed switch assembly member; the trigger circuit including a magnetically actuated reed switch that is activatable by the magnetic field oat a magnetic refrigerator door gasket. The refrigerator door alarm system audibly outputs the recorded message on the speaker each time the trigger circuit is triggered. The refrigerator door alarm system generates an audible buzzer output when the timer circuit runs past a predetermined door open time. The door open time is measured from the triggering of the trigger circuit.

Loss of the contents of a freezer or refrigerator compartment of a refrigerator unit can often result from leaving the door ajar. Although the user is conscientious in trying to maintain the door in the closed position, it could be helpful to have an alarm that provided an audible output to attract the attention of the user to close the refrigerator door once a predetermined time period had elapsed. Because it is often difficult to install alarms and the like, it would be a benefit to have an alarm system that was enclosed in one housing and that could be installed simply by positioning the housing onto a surface of the refrigerator unit adjacent to the door to be monitored. In addition, because the refrigerator unit is often visited it would be a further benefit to have a refrigerator door alarm system that included a message playing mechanism for passing along message to occupants of the home by playing a user recordable audible message each time the monitored refrigerator door is opened.


A bulk bag for the storage and transport of bulk materials, comprises: a bottom panel; a plurality of side panels; a pair of substantially parallel collapsible tubular guide members, each tubular guide member having a first end and a second end and being secured on or adjacent to the top of a side panel; and a plurality of lifting straps; each end of each tubular guide member supporting a lifting strap and the tubular members being connected together by a first spacer; wherein the first spacer comprises at least one axially stiff elongate member and is provided with a pair of jaws at each end, each pair of jaws comprising a first jaw member and a second jaw member and being adjustable between an open position and a closed position and biased to the open position by spring means; each pair of jaws being connected to a tubular member at or adjacent to the first end thereof in a manner whereby when the jaws are in the closed position they will cause at least the first end of each tubular member to lie substantially flat and when the jaws are in the open position they will cause or permit at least the first end of each of the tubular members to adopt a shape which is suitable for receiving a tine of a fork-lift. Other aspects of the invention provide a support device for modifying a conventional bulk bag, and a spacer for use in the bag or support device.

1. Field of the Invention
The present invention relates to bulk bags for the storage and transport of bulk materials, and to support devices for making such bulk bags.
2. Description of the Prior Art
Bags for storage and transport of bulk materials, for example half-tonne, one-tonne, or two-tonne capacity bags, are typically of generally cuboid shape, formed from a fabric material such as polypropylene. Typically, the weight of fabric material will be from about 180 g/m2 to 400 g/m2 depending on the intended load and operating conditions. The fabric may be reinforced for extra strength.
The bags have a top which is either permanently fully open or which can be opened, for loading. The bottoms of the bags are typically provided with a discharge spout through which the contents of the bag can be emptied when the spout is opened. Alternatively, the base of the bag may be cut to discharge the contents if the bag is not to be re-used.
To enable such bags to be lifted and manoeuvred by a fork-lift truck, each bag is typically provided with a lifting strap at each corner. Such bags are often called Flexible Intermediate Bulk Containers (FIBC), or bulk bags. The term "bulk bags" will be used herein to denote such bags.
To lift a filled bulk bag, a fork-lift operator brings the tines of the fork close to the top of one edge of the filled bag so that each tine is adjacent to a lifting strap. An assistant lifts up each lifting strap to enable a tine to pass through the strap while the operator moves the tines forward over the bag. The fork-lift operator moves the tines further over the top of the bag until the tines are adjacent the rear pair of lifting straps, and the process is repeated so that the tines are disposed through the rear lifting straps. The bulk bag can then be lifted and moved.
A problem with this procedure is that there is a danger of injury to the assistant when the tines or the fork are moved. This is a particular problem when filled bulk bags are stacked high, on top of each other. The fork-lift operator is unable to see the rear pair of lifting straps when the stack is too high, and the assistant may be injured by a tine or pushed off a ladder. It is also costly to employ two men to secure the bulk bag on the fork.
If no assistant is present, the fork-lift operator must move the truck so that the tines of the fork are positioned near the front straps. He must then get out of the cab of the truck, hook the front straps over the tines, and get back in the cab. He must then drive the truck forward as far as he thinks necessary, get out again, hook the rear straps onto the tines (if he has judged the forward distance correctly), get back in the cab, drive further forward to pick up the bulk bag. The procedure is slow and can be dangerous.
To facilitate lifting of a bulk bag, it has been proposed in EP 0 259 230 to provide a rigid tubular cruciform structure to be secured in the straps of a bag so that pairs of tubes can receive the tines of a fork. In FR 2 721 304 it has been proposed to provide a similar disposable structure made of cardboard. To reduce the load to which lifting straps are subjected it has been proposed to provide bags with integral lifting slings along opposite top edges so that the load is spread out along those edges; see for example GB 1 549 448, GB 2 050 298, GB 2 092 990, and WO 97/37908. However, the use of such slings does not remove the need for a fork-lift operator either to leave the cab of his truck or to use an assistant to hook the tines of the fork-lift in the slings.
In WO 99/35058 it has been proposed to provide a bulk bag with a pair of parallel tubular guide members along the tops of opposed edges of the bulk bag. The tubular members are resilient and connected together by rigid spacing means at or adjacent to their ends. The lifting straps are supported upright by the tubular members, which function as guides for the tines of a fork-lift. This enables a fork-lift operator to insert the tines of the fork-lift through all four lifting straps in one movement and without leaving his cab. The tubular members may be formed from rubber or reinforced with a helically-wound wire of metal or a plastics material so that they lie flat when under load but revert to a predetermined sectional shape when the load is removed. The resilience of the tubular members allows stacking of filled bulk bags without significant wasted space. Bulk bags with self-raising straps are also described in U.S. Pat. No. 4,300,608. A problem we have found with such devices is that, if a heavy load is applied for a long time, the strap straps or tubular members may not recover, or not fully recover, their initial shape so that insertion of a fork-lift's tines may be difficult or impossible without manual intervention.


A control method for generating a manipulated variable for controlling a hydraulic drive. In this case, account is taken of at least a desired value for the speed of the hydraulic drive, a first parameter, which simulates the response characteristic of the hydraulic drive, and a second parameter, which simulates the internal resistance which the technical process, opposes to the hydraulic drive. It is advantageous that nonlinear dependencies of the hydraulic drive can be taken into account for generating the manipulated variable driving the hydraulic drive. A technically complicated sensor system may be dispensed with. The control method may serve, in particular, the nonlinear control of a plastics injection molding machine.

In hydraulic drives which serve to operate a technical process, the hydraulic drive may have have a specific velocity profile. The hydraulic drive acts on the technical process in a stipulated desired drive speed.
On the one hand, it is possible, in particular, to control the hydraulic drive with reference to its operating speed by means of a closed-loop control circuit. The disadvantage of such closed-loop control circuits consists in that the control requires a precise, quick and therefore technically complicated sensor technology and control engineering. The sensor technology serves to detect specific measured values, required as input variables of the closed-loop control circuit, of the hydraulic drive, such as, for example, specific pressures, valve strokes and drive speeds.
Three different closed-loop concepts, specifically state control, adaptive control and structurally variable model follower control are described in Kxc3x6ckemann, A, Konertz, J, Lausch, H. xe2x80x9cRegelung elektrohydraulischer Antriebe unter Berxc3xccksichtigung industrieller Rand-bedingungenxe2x80x9d xe2x80x9cClosed-loop control of electrohydraulic drives taking account of industrial boundary conditionsxe2x80x9d; at xe2x80x94Automatisierungstechnik, 1991, No. 6, pages 187 to 196. Furthermore, a digital closed-loop control of plastics injection molding machines is described in Pritschow, G Dalacker, M, Treffler, V.: xe2x80x9cHochdynamische digitale Regelung von Kunststoffspritzgiexcex2maschinenxe2x80x9d, xe2x80x9cHighly dynamic digital closed-loop control of plastics injection molding machinesxe2x80x9d; O+P xe2x80x9cxc3x96lhydraulik und Pneumatikxe2x80x9d, 1993, No. 6, pages 528 to 531 . In these closed-loop control circuits, the closed-loop control likewise requires a corresponding sensor technology and control engineering.
German Patent No. DE 43 15 626 describes an open-loop control for a hydraulic drive, in which a desired value for moving the drive is calculated from a prescribed desired value. In this case, the calculation is based in each case at least on a measured state variable of the drive at the instant of the calculation.
It is an object of the present invention to provide a control method for a hydraulic drive which permits nonlinearities to be taken into account.
The object is achieved with the aid of the control method according to the present invention, and with the aid of the plastics injection molding machine according to the present invention, having an open-loop control circuit for carrying out the control method, and with the aid of the use of the control method for controlling a plastics injection molding machine.
The control method according to the present invention has the advantage that it is possible to take account of nonlinear dependencies of the hydraulic drive acting on the technical process in order to generate the manipulated variable driving the hydraulic drive. In this case, it is advantageously possible to dispense with a technically complicated sensor technology for measured-value acquisition.
It is particularly advantageous that in the control method according to the present invention account is taken both of properties of the hydraulic drive and of properties of the technical process, particularly internal resistance for which the technical process opposes to the hydraulic drive.
In an advantageous embodiment of the control method according to the present invention, the parameter simulating the internal resistance is cyclically updated. It is thereby advantageously possible for the control method to be switched over adaptively, in particular automatically, to changing, technical processes which are operated by the hydraulic drive.
It is therefore advantageously possible by using the control method according to the present invention in plastics injection molding machines, for example, to eliminate a troublesome heating and cooling phase before using a new plastics injection molding machine, since the cyclically performed updating can automatically take account of the changes in the technical process.
A further advantage is that the control method according to the present invention can be carried out by using a precontrol circuit in a closed-loop control circuit. An appropriate precontrol circuit can be used, for example, as support for a closed-loop control circuit. Whereas the control method according to the present invention takes over the coarse presetting of the hydraulic drive, the closed-loop control circuit serves the purpose of further, additional fine tuning. It is thereby possible for the accuracy and speed of the hydraulic drive to be improved.

Control method for a hydraulic mechanism of a technical process


The present invention provides improved work schedulers for computer systems and communication processors. A preferred embodiment of the present invention includes systems with buffer memory for storing one or more communication packets or work requests arranged on a plurality of scheduling queues and information for controlling the scheduling of the queues, with output processors for outputting packets from the buffer memory; and with control processors for performing the scheduling methods of this invention. The scheduling methods repetitively initialize each queue's service credits, repetitively process each queue in a round-robin order by granting each queue with remaining service credits no more than one quantum of service and updating that queue's service credits to reflect the service actually used and the service available for use but not actually used.

Round-robin ("RR") is a work-scheduling technique that has been used in many types of computer systems. Standard RR scans work queues, on which pending work is stored, repetitively and in a fixed order. Each queue is allocated a fixed amount of time. When a queue with pending work is found, some or all of these pending requests are processed within the fixed amount of time. The request is a data packet in communication networks. In a typical implementation of RR, the RR scheduler scans work queues on which pending work is stored, repetitively and in a fixed order, and when a queue with pending work is found, a single request is processed. However, the request service may vary in duration. Standard RR is computationally very efficient, but it lacks controllability and is prone in both cases to undesirable "burstiness", and "unfairness". Generally, scheduling "fairness" is understood to mean providing service to queues in a fair manner, such as by providing each queue equal service on average. Other implementation of RR, referred to as Weighted Round Robin (WRR), attempt to allocate each queue a number of requests that are eligible for service in a round. In this case, the RR scheduler scans work queues on which pending work is stored, repetitively and in a fixed order, and when a queue with pending work is found, up to the assigned number of requests eligible for service in a round are processed from that queue. WRR still faces the same issues of burstiness and unfairness (in the presence of service requests that take variable time) as RR.
Thus standard WRR has been modified in various ways to overcome such drawbacks. See, e.g., Shreedhar et al., 1996, IEEE/ACM Trans. on Networking 4(3), pp. 375-385. An example of a variant WRR scheduling technique now believed to be used in communication switches with variable packet sizes repetitively performs the steps of assigning each queue a service weight and then servicing each queue with backlogged data until the assigned service weight is exhausted. However the service weight is measured, entire packets must be transmitted in their entirety in order to avoid packet corruption due to the interleaving of different packets on output links. Although this variant RR technique does grant all work queues on average their assigned service even if one or more of the queues are continuously backlogged, it can often cause undesirable short-term variance in packet throughput (jitter) as well as burstiness.
Similarly, other known variant RR techniques that improve one aspect of scheduling service often do so at the cost of unintended consequences for other aspects of scheduling service. Accordingly, what is needed in the scheduling arts are schedulers controllable to achieve determined service goals (also referred to as quality-of-service (QOS) goals) while retaining the computational efficiency. Computational efficiency is particularly key in modern communication switches and routers that need to service packet queues on modern high-throughput communication links (often at speeds excess of 100, or 200, or 500, or more megabits/sec).
Citation or identification of any reference in this section or any section of this application shall not be construed that such reference is available as prior art to the present invention.

Systems and methods for smooth and efficient round-robin scheduling


A power-on reset circuit initiates a reset signal when the circuit's power supply voltage is low, and terminates the signal in response to the supply voltage exceeding a reset termination threshold that is based upon the greater of the threshold voltages for p-channel and n-channel FETs employed in the circuit. The reset termination threshold is preferably the sum of the greater FET threshold plus a safety margin, with the termination delayed by a predetermined period to ensure an adequate reset period, and a hysteresis feature added to ensure a stable reset termination.

1. Field of the Invention
This invention is related to the provision of a power-on reset signal for electronic circuits.
2. Description of the Related Art
Power is often supplied to electronic systems in a gradual fashion for a number of reasons, e. g., the need to limit in-rush currents, limits on power availability, etc. During the time that power gradually "ramps up", i.e., the power supply voltage increases to its final value, circuitry may toggle somewhat randomly, leaving an entire system in an unknown state when power has been fully supplied to a system. Furthermore, the rate at which power is supplied varies from system to system, as does the final value of the power supply voltage.
Power-on reset signals are used to ensure that an electronic circuit does not begin operation until the power supply voltage reaches a level that permits proper operation. Digital circuitry, from the lowest level of integration, such as the "glue" logic required to provide an interface between complex digital systems, to the highest levels of integration exemplified by the most complex microprocessors available, requires an "all clear" signal that indicates to the circuitry when operation may safely commence. Without such a signal the somewhat random toggling of digital circuitry that occurs during the time that power is gradually applied to the system could be interpreted as meaningful data or instructions, with possibly catastrophic consequences. A power-on reset signal may be employed to place registers and other circuits in a predetermined state, providing a baseline from which to operate and, possibly, suppressing undesirable output signals.
FIG. 1 illustrates a conventional approach to creating a power-on reset signal. A delay circuit 2 includes a resistor 3 and a capacitor 6 connected in series between a positive voltage supply terminal V.sub.dd and a negative voltage supply terminal nominally designated as ground (gnd), with the resistor/capacitor (RC)'s tap connected to the input of an inverter 4. The capacitor 6 is connected between the inverter input and ground. As the power supply voltage (between Vdd and ground) increases, the tap voltage of the RC follows it. Once the RC tap voltage reaches the input HIGH threshold voltage of the inverter, the inverter output POR goes low, thus providing an active low power-on reset signal which, ostensibly, indicates that the power supply voltage has reached a level which is acceptable for normal circuit operation.
In fact, this circuit provides the power-on reset signal only indirectly. The voltage at the input of the inverter 4 does not directly track the power supply voltage. That is, the voltage at the inverter input is not a fixed ratio of the power supply voltage; rather it is a delayed version of it. The voltage at the inverter input depends upon the RC time constant, not directly upon the input voltage. Some RC time constant after V.sub.dd passes the inverter's input threshold, the delayed version of the power supply voltage at the inverter input reaches the inverter's input HIGH threshold voltage. If the capacitor 6 is too small, the input voltage could reach the inverter's threshold before the power supply voltage has reached an adequate level. Because it is important to be sure that the power supply voltage has reached its minimum acceptable level before commencing operation, the capacitor 6 is often chosen to be quite large. Consequently, the resistor 3 and capacitor 6 are typically large, discrete components.
One problem with using a large capacitor is that the power-on reset circuitry must respond to disturbances to the power supply that, although brief, may be of sufficient magnitude to upset and invalidate the logic states of the circuitry. To accommodate these limited-duration power supply disturbances, often referred to as "brown outs", a diode 7 is connected across the resistor 3 so that it is reverse-biased during normal operation but rapidly drains the capacitor 6 when the power supply voltage falls more than a diode drop below the voltage across the capacitor.
Even with the addition of the diode, however, the capacitor's selection presents a compromise between a capacitor that is large enough to assure a valid POR signal for the initial application of power, whether rapid or gradual, and one that permits a response to relatively brief power disturbances. Because it is impractical to produce large capacitors within integrated circuits (ICs) and because the rate at which power is applied to a system varies widely from application to application, this conventional circuit requires the use of external components, i.e.,components not located within the IC, with all their attendant cost and reliability problems.
A complicating factor is that, in complementary metal-oxide-semiconductor (CMOS) circuits employing p-channel and n-channel field effect transistors (FETs), the threshold voltages for operation of the p-channel and n-channel devices are generally independent of each other, and can vary widely within a range of approximately 0.6-1.2 volts due to processing variations. This makes it very difficult to predict an accurate level for the termination of a power-on reset signal. If the signal is terminated at a voltage below the level at which all of the FETs are operative, the circuit may not function properly. If it is terminated significantly above the threshold levels, any circuit operation at all is sacrificed until the reset termination level is reached.
For the forgoing reasons, there is a need for a power-on reset indicator that eliminates external components, improves reliability, reduces cost and ensures, regardless of the rapidity with which power is supplied to the circuit, that the power supply voltage has reached a safe operating level before indicating to other circuitry that operation may commence.

Power-on reset circuit based upon FET threshold level


Anti-anal leakage agents are used in combination with vitamin-fortified liquid fatty acid polyester compositions to provide pharmaceutical and food compositions for treating and/or preventing hypercholesterolemia while avoiding undesired anal leakage of the polyesters.

The present invention relates to certain edible, but non-absorbable and non-digestible, liquid polyesters which can be used as low calorie fat substitutes in foods and as pharmaceutical compositions. The polyesters herein interfere with the body's absorption of cholesterol and thereby provide a means for treating hypercholesterolemia. The polyesters can undesirably interfere with the body'source of fat-soluble vitamins, but this problem is overcome by fortification with vitamins. It has now been determined that the liquid polyesters herein can also cause an undesired anal leakage effect. By the present invention, certain agents are added to the polyester/vitamin compositions to avoid this undesired effect. Highly preferred compositions for treating hypercholesterolemia and/or hyperlipidemia comprising the polyesters, anti-anal leakage agent, and one or more fat-soluble vitamins are provided.
High blood cholesterol (hypercholesterolemia) is recognized as being a risk factor in cardiovascular disease which comprises a major health care problem today. Epidemiological studies have demonstrated that, with few exceptions, populations consuming large quantities of saturated fat and cholesterol have a relatively high concentration of serum cholesterol and a high mortality rate from coronary heart disease. While it is recognized that other factors can also contribute to the development of cardiovascular disease, there appears to be a casual relationship between the concentration of serum cholesterol, in which hypercholesterolemia results in the accumulation of undesirable amounts of cholesterol in various parts of the circulatory system (atherosclerosis) or in soft tissues (xanthomatosis), and coronary disease and coronary mortality rates.
A variety of dietary and drug regimens have been suggested for alleviating or preventing hypercholesterolemia.
By providing a fat substitute which is non-absorbable and non-digestible, the total content of cholesterol in the body can be lowered. Mineral oil is a well-known laxative and has been suggested for use as a fat substitute and as a kind of "intestinal solvent" to dissolve cholesterol and cause its removal in body wastes. However, mineral oil has never been accepted for these uses. Moreover, mineral oil is partially absorbed by the body and undesirably deposits in the liver.
In the present invention, liquid, non-absorbable, non-disgestible polyesters of sugars (or sugar alcohols) are used as fat substitutes in foods and, conveniently, in unit dose forms as therapaeutic composition. The polyesters herein are fat-like in their physical properties and are excellent fat substitutes for use in low calorie foods and diets. Moreover, the polyesters herein efficiently inhibit absorption of cholesterol by the body and, in contrast with mineral oil, are not absorbed and/or deposited in the liver during usage in a treatment/prevention regimen in persons having or likely to develop hypercholesterolemia.
The polyesters herein are used in combination with fat-soluble vitamins so as to supply the body's requirement therefor.
The anal leakage effect of the liquid polyesters of the type disclosed herein can be overcome by adding an anti-anal leakage agent of the type disclosed hereinafter to the vitamin-fortified, liquid polyesters herein, or to foods containing same.
The following references are relevant to the present invention.
The copending application of Mattson, Ser. No. 628,265, filed Nov. 3, 1975, entitled COMPOSITIONS FOR INHIBITING ABSORPTION OF CHOLESTEROL, discloses vitamin-fortified liquid and solid polyesters of the general type employed herein, their use as anti-hypercholesterolemic and anti-hyperlipidemic agents, and their stool-softening laxative effect.
The concurrently-filed application of Jandacek, Ser. No. 657,528, filed Feb. 12, 1976, P&G Attorney's Docket No. 2308, entitled COMPOSITIONS FOR TREATING HYPERCHOLESTEROLEMIA, discloses binary compositions comprising a source of fatty acids and a liquid polyester of the type employed herein.
U.S. Pat. No. 3,600,186 (1971) to Mattson and Volpenheim discloses low calorie food compositions containing polyol polyesters of the general type employed herein, and their use in combination with hardstocks which are fatty acid sources. The anti-anal leakage effect of fatty acids is not noted. In a fat balance experiment, the diet fed to animals contained water-soluble vitamins, but there is no mention of fat-soluble vitamins in the polyester component of this diet.
The copending application of Mattson and Volpenhein, entitled PHARMACEUTICAL COMPOSITIONS FOR INHIBITING ASORPTION OF CHOLESTEROL, Ser. No. 425,010, filed Dec. 14, 1973, now U.S. Pat. No. 3,954,976 discloses and claims sugar polyesters of the general type employed herein for the treatment and/or prevention of hypercholesterolemia. A variety of optional carriers are mentioned, including the fatty acid, stearic acid. The anti-anal leakage effect of stearic acid is not mentioned. The use of the disclosed polyesters in combination both with fat-soluble vitamins and fatty acids is not disclosed.
U.S. Pat. No. 1,656,474 (1928) to Dubin discloses edible fat compositions consisting of ethyl and glycerol esters of odd chain fatty acids in combination with fat-soluble vitamins.
Mattson and Nolen, The Journal of Nutrition Vol. 102, No. 9. Sept. 1972, at pages 1171-1175, report on the lack of absorability of sugar polyesters of the general type employed herein in rats. The rats were fed water-soluble vitamins in the diet and given one drop of fat-soluble vitamins per week.
Fallet, Glueck, Mattson and Lutmer, Clinical Research XXIII No. 3, page 319A (1975) report the lowering of both serum cholesterol and vitamin A and E levels in subjects receiving sugar polyesters of the present type.
U.S. Pat. No. 2,962,419 (1960) to Minich relates to neopentyl fatty esters, their use as fat substitutes, and their use with "vitamins", among other things. Fat-soluble vitamins do not appear to be specifically contemplated in the Minich disclosure.
U.S. Pat. No. 3,160,565 (1964) to H. E. Duell relates to sugar mono-, di- and tri-esters and their use as carriers for various orally-administered medicinals, including the B vitamins.
U.S. Pat. No. 3,849,554 (1974) to Winitz discloses means for reducing blood serum cholesterol by ingesting diets comprising a fatty acid source, said diets being low in sucrose.
U.S. Pat. No. 2,893,900 (1959) to Hass, et al., discloses fatty acid mono- and di-esters of sucrose which aid in the absorption of fat from the digestive tract.
U.S. Pat. No. 3,158,490 (1964) to Baur and Lutton discloses non-cloudy salad oils containing esters of disaccharides in which there are not more than five unesterified hydroxy groups . See also U.S. Pat. Nos. 3,059,009 (1962) and 3,059,010 (1962) to Schmid and Baur.
U.S. Pat. No. 2,997,492 (1961) to Martin is directed to a method of making partial fatty acid esters of hexitols. U.S. Pat. No. 2,997,491 (1961) to Huber is directed to the synthesis of partial fatty esters of inositol. The general methods of synthesis disclosed in these patents can be used to prepare the liquid polyesters herein. Preferred methods of synthesis are fully disclosed hereinafter.
In addition to the foregoing, there are other patents directed to the use of fat-soluble vitamins in a variety of naturally-occurring oils not contemplated by the present invention. See, for example, U.S. Pat. No. 2,685,517, issued Aug. 3, 1954, to Nutrition Products, Inc.

Vitaminized compositions for treating hypercholesterolemia


A fiber optic relay for an individual light guide according to the present invention includes a first light guide from a remote source of illumination, which is coupled to second light guide in series by a relay having a light shut-off means including an electro-magnetic solenoid. In a preferred embodiment the light is fully off when the solenoid is de-energized and has the solenoid plunger disposed between the first and second light guides, blocking light transmission from the first light guide to the second light guide. When the solenoid is energized from a remote source of electrical power the solenoid plunger is withdrawn from between the first and second light guides, allowing light from the first light guide to pass into the second light guide with low attenuation and high efficiency.

This invention applies to the field of fiber optic lighting, and in particular to programmable lighting requiring switched or moving light patterns. This also includes the field in interactive lighting, whereby a person is able to select an object or area to be illuminated, or in which a recorded program can sequentially illuminate different portions of a display.


A control system for one or more power stacks in a power converter is disclosed, each power stack comprising a plurality of electronic switches, said control system comprising one or more controllers, wherein a distributed clock signal from a real-time communication system is used as synchronization means for the switches in the power stacks. One or more controllers controlling the switching times of the switches in one or more power stacks may be connected directly to one or more real-time communication buses of the real-time communication system, using the distributed clock signal for synchronization of pulses when using the one or more power stacks for pulse-width modulation of a desired AC output voltage. Furthermore, a power converter comprising such a control system and a wind turbine comprising such a power converter are disclosed.

When using power converters with a plurality of power stacks, for instance for pulse-width modulation of a desired AC output signal, it is crucial that the switching times of the electronic switches in the power stacks are well synchronized in order to achieve a proper current sharing between the paralleled power stacks.
Power converters known in the art are forced to derate the power output due to reduced control of current sharing.

Control system for power stacks in a power converter, power converter with such control system and wind turbine with such power converter


To provide a confocal microscope for obtaining an extended image by easily determining the capturing range of an observation image without being aware of the shape of a sample to be observed, the confocal microscope comprises confocal image generating unit for generating a confocal image, first counting unit for counting a first number of pixels having a predetermined brightness level or lower among the brightness levels of the pixels of the confocal image, second counting unit for counting a second number of pixels obtained by extracting only a pixel that matches a predetermined condition for the confocal image, and boundary determining unit for detecting a boundary by determining whether or not the observation surface is within the image capturing range based on the first and the second numbers of pixels.

1. Field of the Invention
The present invention relates to a confocal microscope with which a confocal image of a sample to be observed can be obtained.
2. Description of the Related Art
Conventionally, there are microscopes having a confocal optics system (hereinafter referred to as a confocal microscope) that illuminates a sample to be observed with a pointlike light source in a pointlike shape, forms the pointlike image of the light reflected from the illuminated sample, and obtains the density information of the image with a detector via a pinhole.
FIG. 1 is a schematic diagram showing the outline of the configuration of the confocal optics system. As shown in this figure, light irradiated from a pointlike light source 701 gathers at one point of a sample to be observed 704 with an objective lens 703 the aberration of which is properly corrected, and illuminates the sample 704.
The light reflected from the sample 704 is formed as a pointlike image on a pinhole 705 via a half mirror 702, and the light formed as the pointlike image is detected by a light detector 706 via the pinhole 705. By two-dimensionally scanning the sample 704, for example, similar to the raster scanning of a television, a two-dimensional image (hereinafter referred to as a confocal image) is obtained.
Here, reflected light in a position "a" displaced from the light-gathering position of the objective lens 703 is not gathered on the pinhole 705. Therefore, the reflected light does not pass through the pinhole 705 and is not detected by the light detector 706. Accordingly, with the optics system shown in FIG. 1, the image only in the light-gathering position, namely, the focusing position of the objective lens 703 can be obtained.
The focal depth of the above described confocal optics system is shallow. Therefore, there are no problems if an observation surface of the sample 704 is a flat surface. However, if the sample has non-flat observation surfaces where there are projections and depressions of different lengths as shown in FIG. 2, the image of a surface of the sample away from the focusing position cannot be obtained.
FIG. 2 shows an example of the sample having the non-flat observation surfaces. The sample 800 shown in this figure is a sample having non-flat observation surfaces A, B, and C of different heights a, b, and c (b>a>c). Z is the irradiation direction of light. For example, when the observation surface A is focused, observation images of the observation surfaces B and C cannot be obtained.
Accordingly, it is impossible to observe all the observation surfaces A, B, and C by performing an observation operation only once. To observe all the observation surfaces A, B and C, observation images obtained by individually focusing the observation surfaces A, B and C must be synthesized.
However, an observer must determine the focusing position of each of, for example, the observation surfaces A, B and C while viewing an observation image. Therefore, the observer must determine focusing positions for all of observation surfaces whenever he or she observes a sample like that 800 shown in FIG. 2, leading to a heady load on the observer.
As a solution to this problem, Patent Document 1 discloses a scanning-type optical microscope that can obtain an observation image of a sample without determining focusing positions for all of observation surfaces by automatically setting an image capturing range for a sample having the observation surfaces of different heights, and can reduce a load on an observer.
With the scanning-type optical microscope disclosed by Patent Document 1, a confocal image is captured while the microscope moves between first and second stages, and a focused image (herein after referred to as an extended image) in an entire measurement region can be obtained even if a user does not set the image capturing range.
However, according to Patent Document 1, the image capturing range is determined depending on whether or not the number of pixels of a predetermined brightness level or lower is equal to or larger than a preset number of pixels in a confocal image obtained in an arbitrary stage position. Accordingly, for a sample having a plurality of level differences (for example, the sample 800 shown in FIG. 2), the image capturing range is erroneously determined to end at the initial level difference.
As a solution to this problem, Patent Document 2 discloses a scanning-type microscope that can automatically sets an image capturing range without fail even for a sample having observation surfaces of different heights.
The scanning-type microscope disclosed by Patent Document 2 uses the numbers of observation surfaces (the numbers of flat surfaces) of a sample to be observed. Namely, the number of flat surfaces Nup in an upper limit direction of an initial focusing position, and the number of flat surfaces Ndown in a lower limit direction are used. Assuming that the initial focusing position exists between A and C in the sample shown in FIG. 2, the numbers of flat surfaces Nup and Ndown are 2 and 1 respectively.
Then, the number of pixels of brightness equal to or lower than a predetermined level in an obtained confocal image is counted while the stage on which the sample is put is being moved in one direction, and a flat surface is determined depending on whether or not the counted number of pixels is equal to or larger than a predetermined number of pixels. Then, the number of flat surfaces is counted each time a flat surface is detected.
A position where the number of flat surfaces reaches a set value (for example, Nup=2) is stored as a first stage position. Similarly, the number of pixels of brightness equal to or lower than a predetermined level in an observation image is counted while the stage on which the sample is put is being moved in the reverse direction, and a flat surface is determined depending on whether or not the counted number of pixels is equal to or larger than a predetermined number of pixels. Then, the number of flat surfaces is counted, and a position where the number of flat surfaces reaches a preset value (for example, Ndown=1) is stored as a second stage position.
With the above described process, the first and the second stage positions are detected and the confocal image between the first and the second stage positions can be obtained even for a sample having observation surfaces with a plurality of level differences. As a result, an extended image can be obtained.    [Patent Document 1] Japanese Published Unexamined Application No. H06-308393    [Patent Document 2] Japanese Published Unexamined Application No. H08-278450