In a linear sensor, a charge transfer part is disposed between a one-dimensional array of photodetectors and an overflow drain and includes a CCD having four or more transfer gates for each photodetector for transferring signal charges from the photodetector array in a direction of the photodetector array, transfer gates controlling charge transfer from the photodetectors to the CCD, and shutter gates for controlling charge transfer from the charge transfer part to the overflow drain. Each transfer gate is disposed between each photodetector and a prescribed one of the four or more transfer gates, and each shutter gate is disposed between the prescribed transfer gate and the overflow drain. The four or more CCD transfer gates are controlled by four or more phase driving clocks. Therefore, during charge transfer, at least three adjacent CCD transfer gates are all closed so that signal charges are drained from the photodetector into the overflow drain through the transfer gate in the middle of the three transfer gates without mixing the drained signal charges with the signal charges transferred. The charge drain operation is carried out during the charge transfer operation in the charge transfer part whereby the timing of opening the shutter gate can be set at an arbitrary time in the charge read cycle.

With the progress in silicon LSI technology in recent years, a linear image sensor, in which a one-dimensional array of photodetectors and a charge coupled device (hereinafter referred to as CCD) transferring signal charges generated in the photodetectors are combined on a semiconductor substrate, has been put to practical use. Photodiodes utilizing p-n junction or Schottky barrier diodes are used as the photodetectors. The linear image sensor is called a visible image sensor or an infrared image sensor, depending on a wavelength detected by the image sensor. Some of these image sensors are provided with an electron shutter mechanism for preventing saturation of signal charges in the photodetectors.
FIGS. 15(a) and 15(b) illustrate a prior art infrared linear image sensor with such an electron shutter mechanism, in which FIG. 15(a) is a plan view schematically showing a layout of elements constituting the sensor and FIG. 15(b) is a sectional view taken along a line XVb--XVb of FIG. 15(a).
In FIG. 15(a), an infrared linear image sensor 200 includes a p type silicon substrate 9, a one-dimensional array of infrared detectors 1, a CCD 12, and an overflow drain 13. The CCD 12 and the over-flow drain 13 are parallel to each other with the array of the infrared detectors 1 between. Each infrared detector 1 is connected to the CCD 12 through a transfer gate 4 which controls transfer of charges from the infrared detector 1 to the CCD 12. In addition, each infrared detector 1 is connected to the overflow drain 13 through a shutter gate 15 which controls transfer of charges from the infrared detector 1 to the overflow drain 13. Gates of transistors constituting the transfer gates 4 and the shutter gates 15 are connected to input terminals It and Is, respectively, and controlled by clock signals from the input terminals It and Is.
In this structure, the CCD 12 constitutes a charge transfer circuit which transfers signal charges generated in the infrared detectors 1 in a direction of the array of infrared detectors, and an output amplifier 8 is connected to an output end of the charge transfer circuit. The overflow drain 13 is biased with positive external voltage and signal charges generated in the detectors 1 are drawn into the overflow drain 13.
A description is given of a sectional structure of the linear image sensor 200 with reference to FIG. 15(b). In FIG. 15(b), reference numeral 10 designates a PtSi/Si Schottky barrier diode as the above-described infrared detector 1, which comprises a platinum silicide layer 1a selectively disposed on the p type silicon substrate 9 and a p type silicon region 9a contacting the platinum silicide layer 1a to produce a Schottky junction. In addition, a guard ring 11 is disposed around the p type silicon region 9a, so that leakage current from the infrared detector 1 is reduced. The guard ring 11 and the platinum silicide layer 1a serve as a charge storage region of the infrared detector 1.
An n type impurity diffused region 12d as a CCD channel and an n type impurity diffused region as the overflow drain 13 are disposed at opposite sides of the p type silicon region 9a of the infrared detector 1 with prescribed intervals from the p type silicon region 9a. In addition, a CCD transfer gate 12a comprising polysilicon is disposed on the n type impurity region 12d through a gate insulating film 10a. The CCD transfer gate 12a is connected to an input terminal Ic through which a transfer clock signal is supplied to the CCD 12.
A p type impurity region 4b having a prescribed concentration is disposed between the guard ring 11 and the CCD channel 12d and a p type impurity region 15b having a prescribed concentration is disposed between the guard ring 11 and the n type impurity region of the overflow drain 13. Gate electrodes 4a and 15a comprising polysilicon are disposed on the p type impurity region 4b and the p type impurity region 15b, respectively, through gate insulating films 10a. Thus, transistors as the transfer gate 4 and the shutter gate 15 are constituted. Characteristics of the transistors, i.e., potential levels in their ON and OFF states, are varied by varying the concentrations of the n type impurity regions 4b and 15b. Therefore, the concentrations are set so that the potential levels of the transistors as the transfer gate and the shutter gate are equal to each other.
FIG. 16 is a schematic diagram for explaining operation of the transfer gate and the shutter gate in a charge read cycle Xr of the image sensor of FIGS. 15(a) and 15(b). FIGS. 17(a)-17(f) are schematic diagrams illustrating potential profiles during the charge read operation in a cross-section taken along a line XVb-XVb of FIG. 15(a). The charge read operation will be described using FIGS. 16 and 17(a)-17(f).
When a driving clock CLt of the transfer gate 4 rises at time Ta0, the transfer gate 4 opens, that is, the potential level of the transfer gate 4 falls to an ON level Et.sub.on from an OFF level Et.sub.off as shown in FIG. 17(f), and signal charges Cs.sub.2 stored in the photodetector 10 until then are transferred to the CCD channel 12d through the n type impurity region 4b. When the driving clock CLt falls at time Ta1, the potential level of the transfer gate 4 returns to the level Et.sub.off, and the transfer gate 4 closes. At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Et.sub.on (energy level .phi.t) of the transfer gate 4.
More specifically, when the transfer gate 4 opens, the platinum silicide layer la in its floating state is connected to the CCD channel 12d whose potential level is lower than the potential level of the platinum silicide layer 1a, whereby the signal charges Cs2 are transferred toward the CCD channel 12a through the platinum silicide layer 1a and the gate 4. When the transfer gate 4 is closed, the platinum silicide layer 1a is disconnected from the CCD channel 12d and returns to the floating state, so that the platinum silicide layer 1a is charged in accordance with the quantity of transferred charges. In addition, the transfer of signal charges is carried out until the potential level of the infrared detector 1 becomes equal to the lowered potential level Et.sub.on of the transfer gate 4.
Meanwhile, in the infrared detector 1, signal charges Cs1 are stored in accordance with the amount of incident infrared light during a period of Ta1<t<ta2, until the shutter gate 5 opens, as shown in FIG. 17(b). When the driving clock Cls of the shutter gate 5 rises at time Ta2, the shutter gate 5 opens, that is, potential level of the shutter gate 5 drops to an ON level Es.sub.on from an OFF level Es.sub.off as shown in FIG. 17(c), and the signal charges Cs1 stored in the photodetector 10 until then are drawn into the n type impurity region of the overflow drain 13 through the n type impurity region 15b. When the driving clock CLs falls at time Ta3, the potential level of the shutter gate 5 returns to the level Es.sub.off and the shutter gate 5 closes as shown in FIG. 17(d). At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Es.sub.on of the shutter gate 5 (energy level .phi.s) like the above-described opening and closing operations of the transfer gate 4. This reset level .phi.s of the shutter gate 5 is equal to the reset level .phi.t of the transfer gate 4.
Thereafter, in the infrared detector 1, signal charges Cs2 are stored in accordance with the amount of incident infrared light as shown in FIG. 17(e) during a period of Ta3<t<ta4 until the transfer gate 5 opens, i.e., during a shutter period Xs. The signal charges Cs2 stored during the shutter period Xs are transferred to the CCD channel 12 within a pulse period of the driving clock Clt of the transfer gate 4, i.e., a period of Ta4.ltoreq.t<Ta5 (FIG. 17(f)). Thereafter, the charge read operation from the infrared detector 1 to the CCD 12 is carried out in the charge read cycle Xr as described with respect to FIGS. 17(a) to 17(f).
In the charge read cycle Xr, the CCD 12 transfers signal charges from the infrared detector 1. Hereinafter, the charge transfer operation will be described with reference to FIGS. 18 to 20.
FIG. 18 is a plan view illustrating the structure of CCD transfer gates of the linear image sensor 200 and connections between the CCD transfer gates and driving clocks therefor. FIG. 19 is a schematic diagram illustrating waveforms of three phase driving clocks .phi.1 to .phi.3 for the CCD 12 in addition to the driving clocks CLt and CLs of FIG. 16. FIG. 20 is a schematic diagram for explaining transfer of signal charges in an infrared detector to a position corresponding to the next infrared detector in the CCD 12.
As shown in FIG. 18, the CCD 12 is a three-phase driving CCD which includes three transfer gates 12a to 12c for one infrared detector 1. In this structure, a transfer gate 4 is disposed between each infrared detector 1 and each transfer gate 12a, and signal charges generated in the infrared detector 1 are transferred to a region directly under the transfer gate 12a of the CCD channel 12d. In addition, a shutter gate 15 is disposed between each infrared detector 1 and the overflow drain 13.
As shown in FIG. 20, when a pulse of the driving clock CLt is applied to the transfer gate input I.sub.t in the period of Ta0.ltoreq.t<Ta1 in which potential wells are formed directly under the transfer gates 12a, signal charges A to D are sent to the potential wells under the first transfer gates 12a from the respective infrared detectors 1. When the driving clock CLt falls down at time Ta1, the charge transfer operation begins.
More specifically, phases of the CCD driving signals .phi.1 to .phi.3 are different by 120 degrees from each other. Therefore, the potential wells are formed beneath the first and second transfer gates 12a and 12b during the first transfer period of Ta1.ltoreq.t<t1, directly beneath the second transfer gates 12b during the second transfer period of t1.ltoreq.t<t2 and beneath the second and third transfer gates 12b and 12c during the third transfer period of t2.ltoreq.t<t3. When the fourth transfer period of t3.ltoreq.t<t4 and the fifth transfer period of t4.ltoreq.t<t5 have passed away, signal charges A to D are present in the potential wells beneath the next transfer gates 12a. That is, during the above-described period of Ta0.ltoreq.t<t6, the Signal charges A to D move a distance corresponding to one infrared detector. The CCD 12 repeats the transfer operation until the next rise of the driving clock CLt of the transfer gate 4 to finish the transfer operation.
In the linear image sensor 200 having the electron shutter mechanism, however, if the potential level .phi.t of the infrared detector 1 which is reset at the time of the opening and closing operations of the transfer gate 4 is different from the potential level .phi.s of the infrared detector 1 which is reset at the time of the opening and closing operations of the shutter gate 15 even to a small degree, an accurate amount of the infrared light cannot be detected. That is, the detector reset level .phi.t at the time of reading charges depends on characteristics of the transfer gate transistor and the detector reset level .phi.s at the time of sweeping charges depends on characteristics of the shutter gate transistor. Therefore, if there is a difference, even a slight difference, in characteristics between the transfer gate transistor and the shutter gate transistor due to variations in manufacturing, the reset level of the infrared detector at the time of transferring charges from the infrared detector to the CCD is unfavorably different from the reset level of the infrared detector at the time of sweeping charges into the overflow drain 13, whereby some signal charges remain in the infrared detector without being transferred to the CCD or excessive charge is transferred to the CCD.
This problem will be described in more detail. FIGS. 21(a)-21(f) and FIGS. 22(a)-22(f) illustrate potential profiles each corresponding to the potential profile of FIGS. 17(a)-17(f). FIGS. 21(a)-21(f) show a case where the potential level .phi.s of the infrared detector 1 which is reset at the time of sweeping charges is lower than the potential level .phi.t of the infrared detector 1 which is reset at the time of transferring charges. In this case, when the shutter gate 5 operates, charges C0 are excessively drawn into the overflow drain in addition to the stored charges Cs1 as shown in FIG. 21(c). Thereafter, during the charge read operation, signal charges Cs3 at a storage level lower than the difference between the level Et.sub.on at the ON time of the transfer gate 4 and the level Es.sub.on at the ON time of the shutter gate 5, i.e., an energy difference of .phi.t-.phi.s, unfavorably remain in the infrared detector 1.
On the other hand, FIGS. 22(a)-22(f) show a case where the potential level .phi.s of the infrared detector 1 which is reset at the time of sweeping charges is higher than the potential level .phi.t of the infrared detector 1 which is reset at the time of transferring charges. In this case, when the shutter gate 5 operates, a part of the stored charges Csl, i.e., charges Cs5, are only drawn into the overflow drain leaving charges Cs4 as shown in FIG. 22(c). Thereafter, during the charge read operation, charges Cs4 in a quantity equivalent to the difference between the level Et.sub.on at the ON time of the transfer gate 4 and the level Es.sub.on at the ON time of the shutter gate 5, i.e., an energy difference of .phi.t-.phi.s, are excessively sent to the CCD in addition to the signal charges Cs2. As the result, signal contrast is lowered.
In order to solve these problems, an improved linear image sensor has been developed by the inventor of the present invention.
FIGS. 23(a) and 23(b) are diagrams illustrating the improved linear image sensor, in which FIG. 23(a) is a plan view schematically showing a layout of elements constituting the sensor and FIG. 23(b) is a sectional view taken along a line XXIIIb--XXIIIb of FIG. 23(a). In these figures, reference numeral 300 designates the improved linear image sensor. In the sensor 300, an overflow drain 3 and a CCD 12 are disposed on one side of an array of infrared detectors 1 and the CCD 12 is disposed between the overflow drain 3 and the infrared detector array. Shutter gates 5 are disposed between the CCD 12 and the overflow drain 3, so that signal charges generated in the infrared detector array are drawn into the overflow drain 3 through the CCD 12. In addition, a p type impurity region 5b is disposed between a transfer channel 12b of the CCD 12 and an n type impurity region of the overflow drain 3, and a polysilicon gate 5a is disposed on the p type impurity region 5b through a gate insulating film 10a. The p type region 5b and the polysilicon gate 5a constitute a shutter gate transistor. Other structures are the same as those of the linear image sensor shown in FIG. 15.
FIG. 24 is a plan view illustrating a structure of CCD transfer gates of the linear image sensor 300 and connections between the CCD transfer gates and driving clocks therefor. FIGS. 25(a)-25(g) are schematic diagrams illustrating potential profiles during a charge read operation of the linear image sensor 300 in a cross-section taken along the line XXIIIb--XXIIIb of FIG. 23(a). FIG. 26 is a schematic diagram illustrating waveforms of signals applied to the respective gates of the linear image sensor 300. The charge read operation will be described using these figures.
First of all, when the driving clock CLt of the transfer gate 4 rises at time Ta0, the transfer gate 4 opens, that is, the potential level of the gate 4 falls to an ON level Et.sub.on from an OFF level Et.sub.off, and signal charges Cs stored in the infrared detector 1 until then are transferred to the CCD channel 12d through the n type impurity region 4b (FIG. 25(f)). When the driving clock CLt falls at time Ta1, the potential level of the gate 4 returns to the level Et.sub.off and the gate 4 closes. At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Et.sub.on of the transfer gate 4 (an energy level .phi.t) for the same reason as in the case of the sensor 200 shown in FIG. 15.
At the same time, charge transfer operation begins in the CCD 12. Thereafter, during the period of Tal.ltoreq.t<Tb2 of FIG. 25(a), i.e., the transfer period Xt of FIG. 26, signal charges are successively stored in the infrared detector 1 as shown in FIG. 25(a) while the charge transfer operation is carried on in the CCD 12. Thereafter, during the period of Tb2.ltoreq.t<Tb3, i.e., the period until the shutter gate 5 opens, signal charges Ce are stored in the infrared detector 1 in accordance with the amount of incident infrared light as shown in FIG. 25(b). When the driving clock CLs of the shutter gate 5 and the driving clock CLt of the transfer gate 4 rise at time Tb3, these gates 5 and 4 open, that is, the potential levels of the gates 5 and 4 fall to the ON levels Es.sub.on and Et.sub.on from the OFF levels Es.sub.off and Et.sub.off, respectively, whereby signal charges Ce stored in the infrared detector 1 are drawn into the n type impurity region of the overflow drain 3 through the channel 12b of the CCD 12.
When the driving clocks CLs and CLt rise at time Tb4, the potential levels of the gates 5 and 4 return to the levels of Es.sub.off and Et.sub.off, respectively, and the gates 5 and 4 close (FIG. 25(d)). At this time, the potential level Eid of the infrared detector 1 is reset to the ON level Et.sub.on (.phi.t) of the transfer gate 4, regardless of the ON level Es.sub.on of the shutter gate 5, as in the case of the opening and closing operations of the transfer gate 4, so that the potential level of the infrared detector 1 in the charge read operation is not different from that in the charge drain operation.
Thereafter, in the infrared detector 1, signal charges Cs are stored in accordance with the amount of incident infrared light until the transfer gate 4 opens, during the shutter period Xs, i.e., the period of Tb4<t<Tb5 (FIG. 25(e)). Charges Cs stored during this period are transferred to the CCD channel 12 within the pulse period of the driving clock CLt of the transfer gate 4, i.e., the period of Tb5.ltoreq.t<Tb6 (FIG. 25(f) ). When the driving clock CLt rises at time Tb6, the CCD 12 begins the charge transfer operation. Thereafter, charges are successively transferred from the infrared detector 1 to the CCD 12 in the charge read cycle Xr as shown in FIGS. 25(a) to 25(g).
In order to achieve the above-described operation, it is necessary to set the potential levels to be increasingly deep in the order of the transfer gate (Et.sub.on), the CCD channel (E.sub.cc), the shutter gate (Es.sub.on) and the overflow drain (Eod). This is easily achieved by controlling impurity concentrations of the p type and n type impurity regions of the respective elements.
In the above-described linear image sensor 300, unnecessary charges generated in the infrared detector are drawn into the charge exhaust part like the overflow drain through the charge transfer part. This idea is also disclosed in Japanese Published Patent Applications 62-200761 and 60-120555. More specifically, Japanese Published Patent Application 62-200761 discloses a solid-state imaging element in which a charge transfer part is disposed between a one-dimensional array of infrared detectors and an overflow drain, and charges flowing into the charge transfer part due to excess light incident on the infrared detector are drawn into the overflow drain. However, this device has no electron shutter mechanism. In addition, Japanese Published Patent Application 60-120555 discloses a solid-state imaging device in which two CCD registers are disposed on opposite sides of a one-dimensional array of infrared detectors and two dummy shift registers are disposed on the outer sides of the CCD registers and charges remaining in the infrared detectors are drained into the dummy shift registers through the CCD shift registers.
In the above-described linear image sensor 300, since the signal charges Ce stored in the infrared detector 1 are drawn into the overflow drain 3 through the CCD 12, during charge drain operation, the charge transfer operation of the CCD 12, transferred signal charges are sometimes mixed with the drawn charges. In this case, the shutter gate 5 cannot be turned ON during the transfer operation of the CCD 12. In order to avoid this, the CCD transfer period and the charge drain period are set in different periods of time. However, the shutter period Xs is limited to a short period after the charge transfer period Xt in the charge read cycle Xr, so that signal charges are not sufficiently stored especially when the amount of incident infrared light is small.

Linear image sensor with shutter gates for draining excess charge


A system and method are provided for dispersing storage of a plurality of related and unrelated data items on a plurality of removable recordable media instances (RMIs). A first storage device is provided for storing a data item on a qualifying related RMI, the qualifying related RMI having one or more related data items stored on it and having sufficient actual storage space remaining for storing the data. A multiplier device is connected to the first storage device for multiplying the actual size of a data item, which is not stored by the first storage device because there is no qualifying related RMI, by a factor greater than one, to produce reserved storage space data which characterizes any other RMI that actually stores the data item. A second storage device, which is responsive to the multiplier device is provided for storing a data item on a qualifying unrelated RMI, the qualifying unrelated RMI having one or more unrelated data items stored on it and having sufficient actual and unreserved storage space remaining to store the data item and, if there is no qualifying unrelated RMI, then storing the data item on a new RMI the new RMI having no data stored on it. This arrangement provides for shared logical space reservation so that physical proximity of related data items is optimized with respect to a set of RMIs.

1. Field of the Invention
The present invention relates to a system for storing related and unrelated data items on a plurality of removable recordable media instances (RMIs), and more particularly to a system which will reserve RMI storage space so that related data items are grouped together even though they are stored at different times.
2. Discussion of the Related Art
The grouping of information by subject matter is basic to any library. For instance, in a library for books, the librarian typically reserves shelf space for a subject book, particularly when the subject matter is an active one. While this is relatively easy for a book library, it is much more difficult to arrange subject matter on electronic media in electronic storage devices. With electronic media, one deals with data items instead of books. A data item can be a word, a sentence, a normal book, larger than a normal book, or any size of drawing. When a number of electronic media producers or processors, such as personal computer workstations, store data items, it is more efficient to store these data items at a central location rather than on individual memories of the personal computers. For example, if a large number of people were working at various personal computer workstations to develop and process data items which are required for a large project, such as building a missile, it would be desirable that each one of these data items be classified by subject matter and stored at a remote location for retrieval by any one of the workstation users. In order to make the retrieval of this information efficient, it is necessary that related subject matter be grouped into a common location within the remote storage device so that the accessing device does not have to access related data items from one end of the storage device to the other.
A prior art data file storage management system, available from the assignee of this application, eliminates the need for individual workstation users or groups of users to perform data storage space management on their limited storage devices. The system is a distributed file storage management system and is sold under the trademark "DFSMS", which is owned by the IBM corporation. With this system, space management is handled by a storage administrator who can cause data storage space requests from distributed workstation sites to be allocated based upon particular parameters dictated by the enterprise being served. The DFSMS system is primarily focused on permanently mounted storage media of the direct access storage device (DASD) type. This focus did not address the methodologies for effective utilization and optimization of storage and retrieval of data residing on media which is not permanently mounted.
The object access method (OAM), a component of a data facility product (DFP)/multiple virtual storage (MVS) available from the IBM Corporation stores data on "write-once-read-many" (WORM) optical media in a form that is permanent, as opposed to storage of erasable data on magnetic media. The advantage of optical media is that it can contain very large quantities of data and it can be demounted to allow other media to be used on the same optical read/write device. These optical read/write devices are placed in an optical library that can store many optical media volumes and mount/demount these volumes in one or more available optical read/write devices.
Currently, OAM stores data on any eligible optical media that is already mounted using the storage group constraints of the DFSMS product. The problem is that this can result in data being scattered across multiple instances of optical media in an optical library. This creates a retrieval problem in that two or possibly many more optical media must be mounted before all of the data needed by an application is made available.
The need is for a system for storing logically related data on the same or as few as possible removable recordable media instances (RMIs), such as optical disks or magnetic tape cartridges, so that this related data can be quickly accessed when the user desires to retrieve information on any particular subject. This system has to work regardless of time constraints. For instance, a piece of data may be stored today, then many months may pass before another piece of data, related to the first stored data, is stored. Accordingly, the system has to reserve storage space on the RMI on behalf of a system external to the RMI so that when the related data item arrives many months later it will be stored in proximity to the first stored data item. With such an arrangement, removable recordable media, such as optical disks and magnetic tape cartridges, can be efficiently utilized to store a large group of related data items which may be submitted for storage in multiple, separate transactions.

Storage dispersal system based on related, shared data storage space reservation

International Business Machines Corporation

by Sandra I. Vomaska, legal representative


A mechanism is provided for identifying a wire-pull test location on a wire of a microelectronic package. A first distance between a first terminating location of the wire on the microelectronic package and a second terminating location of the wire on the microelectronic package is determined. Based on the first distance, a second distance from either the first terminating location or the second terminating location is determined as the wire-pull test location for testing a strength of a connection of the wire to at least one of the first terminating location or the second terminating location. An adjustment is performed such that a visual guide is oriented on the wire at the wire-pull test location.

The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for identifying a wire-pull test location on a wire of a microelectronic package.
Wire-pull is a long established technique for testing the integrity of wire-bond interconnects within microelectronic packages. The principle behind basic wire-bond testing is positioning of a hook underneath the wire and pulling in a Z-axis either until the bond breaks (destructive testing) or a predefined force is reached (non-destructive testing). Wire bond testing is covered by the external standard MIL-STD-883 (Methods 2011.7 for destructive testing and 2023.5 for non-destructive).

This patent is subject to a terminal disclaimer.

Wire-pull test location identification on a wire of a microelectronic package

International Business Machines Corporation


Provided is a sling for coupling a weapon to a user of the weapon. The sling includes a strap, and a weapon connector that cooperates with a fastening feature provided to the weapon to releasably couple the weapon to the strap. A first connector is coupled to the strap, as is a second connector, which is coupled to a different portion of the strap. The second connector is separated from the first connector along the sling by at least a portion of the strap. The first and second connectors cooperate to establish a connection and form a loop that extends about a portion of the user of the weapon. The sling also includes a rapid sizing adjuster coupled to the strap. The rapid sizing adjuster is adjustable by the user of the weapon to quickly establish a desired length of the sling in a single motion while the sling is coupling the weapon to the user.

1. Field of the Invention
This application relates generally to a sling for coupling a weapon to a person and, more specifically, to a tactical sling that couples a firearm to a person and is adjustable between a single-point configuration and a multiple-point configuration.
2. Description of Related Art
Traditionally, slings for coupling a weapon such as a firearm to a person have been configured as either a two-point sling or a single-point sling. Traditional two-point slings have commonly included a length of material extending between a pair of fasteners. A first fastener at one end of the material cooperates with a forward portion of the firearm, adjacent to a barrel of the firearm for example. A second fastener at the other end of the material, opposite the end with the first fastener, includes a second fastener that cooperates with a rearward portion of the firearm, such as the stock. With the two fasteners at opposite ends of the material cooperating with the firearm, the length of material could be draped over the person's shoulder, neck, or other body part to suspend the firearm from that person.
Traditional two-point slings allow the firearm suspended from the person to be quickly removed, and allow for a wide range of movement of the firearm on the person. Two-point slings also maintain the firearm at an elevation above the person's legs, allowing the person wearing the sling to walk or even run without kicking the firearm. However, two-point slings also typically suspend the firearm only in a substantially-horizontal orientation, which may be undesirable for certain tactical situations requiring the person to navigate narrow spaces with a long firearm.
As the name suggests, traditional single-point slings have commonly included only a single fastener that connects the firearm to the sling at a single location on the firearm at any given time. The length of material attached to the single fastener of a single-point sling typically forms a loop that extends around the upper torso (usually over one shoulder and under the other) of a person wearing the sling. Since the single-point sling is attached to the firearm at only a single location, the firearm is allowed to dangle in a substantially-vertical orientation from the person wearing the sling. This vertical orientation of the firearm allows the person to navigate narrow walkways and positions the firearm out of the way of the person wearing the sling. However, it may be cumbersome to walk with the firearm in the vertical orientation since the firearm will often extend down significantly along the person's legs.
Thus, there are times when a two-point sling is convenient and other times when a single-point sling is convenient. However, in tactical applications the person who is to wear the sling is often required to walk long distances, or repel from or climb up vertical obstacles carrying various tactical gear. Under such circumstances it is desirable for the person to travel light, making it impractical to carry both slings. But even if the person is carrying both the two-point and single-point slings, tactical operations often require the person wearing the sling to react quickly to a potential threat or a change in environment. Under such circumstances there will probably be an insufficient amount of time available for the person to change to the sling most appropriate for the given environment.
But regardless of whether a sling is a two-point or a single-point sling, conventional slings have traditionally included limited adjustment options for adjusting a length of the sling to fit people of various sizes. One such adjustment feature has typically included a strap doubled over onto itself through a slide lock adjuster. Adjusting the length of the sling using such an adjustment feature requires the person wearing the sling to remove it and manually feed a length of the material through the adjuster, followed by the second step of pulling the other portion of the material doubled over onto the newly-fed material through the adjuster. Such an adjustment is time consuming and tedious, requiring a high degree of dexterity in the person's hands. For tactical applications, a rapid adjustment may be required in less time than required for manual adjustment of a conventional slide lock adjuster through which the sling material extends and is doubled back on itself for another pass through the slide lock.


The invention covers a procedure for measuring hydrostatic pressure, especially that of ground water, with the particularity that air is bubbled into the ground water, the pressure in the measuring pipe is fed to an absolute pressure cell and atmospheric pressure is then applied to the same measurement cell.

A very important aspect of hydrological measurement practice is continuous monitoring of the water table, since this is needed for resolving environmental problems caused by manmade developments.
Water occurs naturally in the form of surface water and ground water. In the surface water category are rivers, streams, lakes and oceans. The water level of surface water is normally easily accessible which makes installation of equipment for measuring and recording this level relatively easy.
By contrast boreholes have to be sunk in order to monitor ground water feeds, and these are normally constructed using 2" to 6" pipes. These pipes are normally capped to prevent unauthorised access.
The requirements of a ground water measuring system are very exacting because of local environmental conditions and specifications imposed by measurement network operators. Some of these requirements are listed below.
Total installation inside 2" to 6" pipes PA1 Operating temperature -20.degree. C. to .+-.60.degree. C. PA1 Resistance to water condensate PA1 Stable long-term measurement accuracy of +1 cm over 10 m measurement run PA1 Independent power supply for at least 1 year PA1 Low acquisition costs PA1 Low operating costs PA1 the principle of the introduction of air bubbles can be applied; PA1 a two inch pipe can be used to house the equipment; PA1 reliable operation is assured at outside temperatures of -20.degree. C. to +60.degree. C.; PA1 resistance to water condensate is assured; PA1 stable long-term measurement accuracy is guaranteed of +/-1 cm over 10 m; PA1 a self-contained power supply is provided for at least 1 year, something which has been inconceivable for other existing systems; PA1 compared with other existing systems, the procurement cost of this equipment is up to 50% lower, and operating costs are low.
Nowadays a large number of measurement systems are available for measuring water levels. But in the light of the overall requirements outlined above not all measurement procedures are suitable for measuring ground water in conjunction with electronic data collectors.
Measurement procedures so far invented can basically be placed in two categories, those measuring length and those measuring pressure. Those measuring length include all measurement systems operated by means of floats with angle encoders, acoustical and optical procedures and measurement using conductivity levels. Those measuring pressure include all systems such as pneumatic pressure recording (introduction of air bubbles) and electronic pressure measurement (piezo resistant, capacitative etc.)
For the purposes of ground water measurement the only systems to have proven themselves in practice are measurement of length by means of floats with angle encoders and electronic pressure measurement. There is a DVWK paper, Issue 107: Ground Water Measurement Devices, Bonn, 1994 which provides a current overview of the use of ground water measurement systems.

Method and measuring device for measuring hydrostatic pressure, in particular that of ground water


A switching power control circuit includes an analog-to-digital converter (ADC) configured to convert an analog direct current (DC) voltage into a digital voltage; a digital compensator configured to set a gain and phase characteristics of the digital voltage output from the ADC and output a digital compensation value; and a pulse generating circuit configured to generate at least one driving signal based on the digital compensation value, wherein the pulse generating circuit is switched by an ON/OFF signal for turning on or off an output of the driving signal from the pulse generating circuit and a control scheme selection signal for selecting a predetermined driving signal from the driving signal.

Recently, two-way switching power control circuits are installed in electric vehicles, hybrid vehicles, and the like in order to charge electric power generated by photovoltaic power generation and supply charged electric power to households, or the like as needed.
There exists a switching power supply device for performing a two-way power interchange. In the switching power supply device, a full bridge circuit is connected to a primary side of a transformer while a push-pull circuit is connected to a secondary side thereof. The full bridge circuit may perform a switching operation using a phase shift signal.
Further, an isolated DC/DC converter is used. The isolated DC/DC converter is configured such that an operation (or control) of a switching element is switched between a full bridge and a half bridge by a microcomputer. Also, the switching element constituting the full bridge and the half bridge is connected to a primary winding side of a transformer. Thus, switching of the full bridge and the half bridge may be performed by the primary winding side of the transformer. That is to say, in the isolated DC/DC converter, a driving scheme of a secondary winding side of the transformer may not be switched.
In addition, a compact, highly efficient DC/DC converter is also used. In such a converter, a plurality of control schemes such as a full bridge two-way isolated DC/DC converter, a flyback converter, a series converter using a polarity reversing chopper, and a one-way isolated DC/DC converter may be available.


An image sensor includes a pixel array, and a correlated double sample circuit coupled to one of the pixels in the pixel array. The correlated double sample circuit includes first and second inputs, and first and second sample capacitors respectively coupled to the first and second inputs. The first input is for receiving an analog signal from a pixel, and the second input is for receiving a time varying reference signal. The analog signal varies during a pixel readout period, and has a first level during a first reset period and a second-level during a second read period. A comparator circuit compares the time varying reference signal and the analog signal. The analog signal and the time varying reference signal are constantly read onto one of the first and second sample capacitors during both the first reset period and the second read period.

CMOS image sensors have become increasingly prevalent in various devices, and in particular, mobile cellular telephones. A major demand within the mobile phone market is for small, thin, pocket sized devices that are still packed with various additional features, such as cameras incorporating CMOS image sensors. As a result, image sensor manufacturers are continually required to produce sensors with either a greater resolution for the same physical size, or a smaller physical size with at least the same resolution.
Resolution is determined in the first instance by the number of pixels within an image sensor, and secondly, by the resolutions of the analog to digital converters within the image sensor. That is, resolution is determined by the number of pixels available to represent the image being taken, and the number of bits required to represent the signal from each pixel, respectively.
U.S. Pat. No. 6,943,719 discloses an analog to digital converter (ADC) for a power saving image sensor. The ADC comprises a correlated double sampling (CDS) circuit and an output circuit. The CDS circuit includes an input for a voltage ramp, and an input for a signal from a pixel. Each input includes a switch to isolate the input signal from the CDS. The CDS circuit also includes first and second capacitors that are in series with the respective switches. An output of the CDS is connected to both the first and second capacitors, and is connected to the output circuit.
The output circuit comprises, in series, an inverter circuit having a bypass controlled by a switch, a capacitor, and an inverter also having a bypass controlled by a switch and a latch. The power consumption of the ADC is controlled by selectively enabling the inverter circuit, and selectively allowing the pixel signal onto one of the capacitors in the CDS circuit. The inverter is switched off when not required, and the pixel is switched off when not required. This helps to minimize or reduce power consumption of the circuit.
Prior art ADCs for image sensors have a number of drawbacks when attempting to increase resolution while also minimizing the size of the image sensor package. In particular, during correlated double sampling, kT/C noise or reset noise is cancelled by sampling the kT/C noise during reset before sampling the pixel signal onto the capacitors. The size of capacitors is determined by the kT/C noise. As the ADC circuit is required for every column in the pixel array, an increase in capacitor size can severely effect the size of the overall image sensor.

STMicroelectronics (Research & Development) Limited


An object of the present invention is to provide an epitaxial growth apparatus and an epitaxial growth method that can suppress variation in in-face temperature of a semiconductor wafer caused by deflection of a susceptor and manufacture an epitaxial wafers of high quality. Specifically, the present invention provides an epitaxial growth apparatus for forming an epitaxial film on a semiconductor wafer placed in a chamber having a supply port and an exhaust port for a treatment gas, the apparatus comprising: a susceptor for placing the semiconductor wafer thereon within the chamber; and a susceptor support shaft for supporting the susceptor at an underneath portion of the susceptor, wherein the susceptor support shaft has a support column located substantially coaxial with the center of the susceptor, and at least four support arms extending radially from the top end of the support column with equal intervals therebetween.

1. Field of the Invention
The present invention relates to an epitaxial growth apparatus and an epitaxial growth method and, in particular, to improvement of a support shaft of a susceptor for supporting a semiconductor wafer during growth of an epitaxial film on the semiconductor wafer.
2. Description of the Related Art
In the field of semiconductor electronics in which products are increasingly required to exhibit high performances and high functionality, quality of an epitaxial wafer significantly influences quality of a resulting product device. An epitaxial wafer is a semiconductor wafer having an epitaxial film formed on a surface thereof by vapor phase epitaxy. A high quality epitaxial film having aligned crystal axes is formed on a surface of a semiconductor wafer in accordance with the regular sequence of atoms thereat.
There has conventionally been used in production of an epitaxial wafer a batch-process-type epitaxial growth apparatus capable of effecting epitaxial growth on plural semiconductor wafers simultaneously. However, such a batch-process-type epitaxial growth apparatus as described above cannot easily adapt to production of large-diameter semiconductor wafers. For this reason, in recent years, it is increasingly common to use a single-wafer epitaxial growth apparatus in which epitaxial growth is effected for a single semiconductor wafer individually. Recently, there has been developed a single-wafer epitaxial growth apparatus for a large-diameter semiconductor wafer, capable of handling a semiconductor wafer having a diameter of 450 mm or more.
FIG. 1 is a schematic sectional view of a conventional single-wafer epitaxial growth apparatus 200. This epitaxial growth apparatus 200 includes a chamber 201, a susceptor 202 for supporting a wafer W placed within the chamber 201, and a susceptor support shaft 203 for supporting the susceptor 202. A supply port 204 for a treatment gas is formed at a side portion of the chamber 201, and an exhaust port 205 is formed at a position of the chamber opposite to the supply port 204. Further, plural halogen lamps 206 as heating sources are radially disposed in each of an upper side region and a lower side region of the chamber 201.
FIG. 2 is a schematic exploded perspective view showing details of the susceptor 202 and the susceptor support shaft 203 described above. The susceptor support shaft 203 includes a support column 207 and support arms 208, and a protrusion 209 and a protrusion 210 for supporting the susceptor 202 are provided on the support column 207 and each support arm 208, respectively. Further, there are formed on the rear surface of the susceptor 202 a recessed portion 211 and a recessed portion 212 at positions corresponding to the protrusion 209 and the protrusion 210, respectively. In this structure, the positioning of the susceptor 202 is effected by aligning the recessed portion 211 formed at a center of the susceptor 202 with the protrusion 209 provided at the support column 207. Yet further, the recessed portions 212 are engaged with the corresponding protrusions 210, respectively, thereby preventing the susceptor 202 from making relative movement around the protrusion 209 in the rotational direction.
By using the epitaxial growth apparatus 200, the semiconductor wafer W is placed on the susceptor 202; the halogen lamps 206 are lit to heat the semiconductor wafer W; and a treatment gas including a carrier gas, a growth source gas, a dopant gas and the like are introduced from the supply port 204 while being exhausted from the exhaust port 205 simultaneously, such that the treatment gas flows in a laminar flow state along a surface of the semiconductor wafer W which has been heated to a predetermined temperature. As a result, an epitaxial film can be grown on the semiconductor wafer W.
However, in the case where the aforementioned epitaxial growth apparatus 200 is used, there arises a problem that an epitaxial film having sufficient thickness is not formed at the center portion of the semiconductor wafer W. In general, the thickness of an epitaxial film formed by epitaxial growth is affected by a temperature of the semiconductor wafer W therebelow. As described above, although the semiconductor wafer W is heated by the halogen lamps 206, heat from the halogen lamps 206 located at the lower portion of the chamber 201 cannot be transferred in a satisfactory manner because, as is obvious from FIG. 1, the rear surface of the semiconductor wafer W is heated through the susceptor 202 and there exist the support column 207 of the susceptor support shaft 203 and the protrusion 209 provided at the top end of the support column 207 at the center portion of the susceptor 202 (i.e. the center portion of the semiconductor wafer W).
In view of the facts described above, JP 2000-124141 Laid-Open discloses a technique in which the protrusion 209 is not provided at the top end of the support column 207 and the positioning of the susceptor 202 is effected by alignment of respective three pairs of the protrusions 210 and the recessed portions 212, so that the heat from the halogen lamps 206 located at the lower portion is not blocked and can reach the center portion of the semiconductor wafer W.
The temperature in the chamber 201 of the epitaxial growth apparatus 200 becomes more than 1000° C. during the epitaxial growth process, and the susceptor 202 and the susceptor support shaft 203 are exposed to such a high-temperature environment. JP 2009-135258 Laid-Open discloses a technique in which a reinforcing member (not shown) is provided to each support arm 208 of the susceptor support shaft 203, among the susceptor 202 and the susceptor support shaft 203, in order to prevent the support arm 208 from being deformed and thus supporting the susceptor 202 in a slanted manner.
JP 2000-103696 Laid-Open discloses a technique in which provision of the protrusion 209 at the top end of the support column 207 is omitted as in JP 2000-124141 and further a position at which the support arm 208 is in contact with the rear surface of the susceptor 202 is shifted toward the inner or the outer side in the radial direction than in JP 2000-124141 for the purpose of uniformly heating the susceptor 202 by the halogen lamps 206 located at the lower portion of the chamber 201.
According to the inventions of JP 2000-124141, JP 2009-135258, and JP 2000-103696 described above, the susceptor 202 can be uniformly heated and an effect of making epitaxial film thickness even is achieved to some extent. However, the effect of making epitaxial film thickness even is not yet sufficient and variation in resistivity distribution within an epitaxial film is still quite large.
As a result of a keen study to make thickness and resistivity distribution of an epitaxial film uniform, the present inventors discovered that, even in a case where the susceptor 202 is uniformly heated, the outer peripheral portion of the susceptor 202 is deflected (in the circumferential direction) due to exposure of the susceptor 202 itself to the high-temperature environment and that a magnitude of such deflection of the susceptor 202 as described is especially large at a portion which is not supported by the susceptor support shaft 203.
In a case where the epitaxial growth process is carried out in a state where the susceptor 202 has partially been deflected at the outer peripheral portion thereof, a space is created between the deflected portion of the susceptor 202 and a semiconductor wafer W placed thereon, whereby the semiconductor wafer W is partially cooled by a carrier gas or the like entering into the space and the temperature of the semiconductor wafer W varies in the circumferential direction thereof. When epitaxial growth is performed at such a surface of the semiconductor wafer W where the temperature varies as described above, the thickness of an epitaxial film grown on the wafer surface and the amount of dopant taken into the epitaxial layer also vary within the wafer surface. In short, deflection of a susceptor significantly affects the thickness distribution and the resistivity distribution of a silicon epitaxial film of an epitaxial wafer. This problem of uneven distribution of resistivity cannot be ignored, in particular, in an epitaxial wafer to which the resistivity standards must be strictly applied.

Epitaxial growth apparatus and epitaxial growth method


A wheel with a pneumatic tire, with the tire cavity divided into two fluid-filled reservoirs connected with a passageway (orifice, capillary, or porous material) having a required degree of flow restriction in order to generate a desired damping action when the tire is subjected to a vibratory exertion. The flow in the passageway is maintained at a laminar regime.

Most modern transportation vehicles, agricultural tractors and implements, aircraft while performing surface conveyance (takeoff and landing), etc., are equipped with wheels having pneumatic tires inflated by a compressed fluid. Most frequently, the tires are inflated by compressed air, although some other media are used, such as water, in some agricultural applications.
Besides the main task - to insure reliable grip with the road surface - pneumatic tires also create a resilient connection between the vehicle and the road surface in which the resilience depends mainly on the pressure of air in the tire. The damping effect of this resilient connection is usually very small and is determined mainly by the damping characteristics of the tire material. As a result, when disturbances from the road have frequencies sufficiently higher than the natural frequency of the vehicle/tire system ("hop frequency"), the tires behave as vibration isolators, but for vibration frequencies close to the hop frequency, tires tend to worsen the vibration effect on the vehicle. If the vehicle has a suspension system, the harmful increases of the vibration effects on the vehicle when the frequency is near the hop frequency are alleviated, because the natural frequency of the suspension system is usually much lower than the hop frequency. However, even a limited increase of the vibration level at the tire's natural frequency is very unpleasant and in many cases can force the designer to lower the natural frequency of the suspension system. Especially bad consequences for the strength of the vehicle and its component units, passenger comfort, cargo conditions, etc., are encountered in cases when the tires are the sole resilient element, such as in wheeled tractors or bicycles. In such cases, the maximum speed of the vehicle while on a given road surface may be limited by the resonant amplitudes of vibration of the vehicle on tires. Increasing damping of the tires would reduce these resonant amplitudes and thus would alleviate the negative effects listed above as well as allow higher effective maximum speed.
This can be accomplished by providing a means by which a part of vibrational energy is dissipated (transformed to heat), thereby damping road-induced shocks and vibrations but which does not cause energy losses resulting from the rolling motion of the tire. Such means, proposed in U.S. Pat. No. 4,289,187 to E. Rivin (author of this invention), comprises a damping fluid chamber supported on the wheel and connected with the tire cavity by an energy-dissipating passage having a specified flow resistance. The system described in U.S. Pat. No. 4,289,187 was successfully tested as described in: B. Bachrach, E. Rivin, "Pneumatic Damping of Vehicle Tires to Improve Ride Quality", Proceedings of the Fifth International Conference on Vehicular Structural Mechanics, vol. P-144, SAE, 1984. While the positive effect of the system was demonstrated, its limitation was found to be a very small change of volume (and pressure) in the tire cavity when the wheel is subjected to vibratory loads. Only a 3% fraction of the tire reaction to its vibratory displacement caused by the road unevenness was found to be accommodated by the pressure change in the tire cavity. The bulk of the reaction is due to structural stiffness of the inflated tire and due to changes in the tire footprint area. Thus, while the system per U.S. Pat. No. 4,289,187 was proven to be useful, its performance capacity is rather limited. The performance capacity is also a function of volume ratio between the damping chamber and the tire cavity, thus the chamber has to be large to enhance the performance characteristics. Attachment of a large chamber to the wheel structure would require its expensive changes and is undesirable because of weight and packaging constraints.
While the role of vehicle tires in providing protection for passengers and cargo from the road-induced excitations is important, tires themselves may become sources of vibrations due to high-frequency acoustic resonance of their internal cavities. These resonant vibrations can be responsible for annoying components of noise in the vehicle passenger compartment. The frequency range of these annoying sound components is about 100-200 Hz, which is difficult to adequately isolate. An example of special means to reduce this noise is represented by U. S. Pat. No. 4,896,921 granted to C. Sato, et al. This patent teaches several chambers ("resonators") attached to the wheel and connected to the tire cavity though calibrated passages (similar to design of U.S. Pat. No. 4,289,187). Such design requires special and expensive wheel modifications. Other known designs, such as U.S. Pat. No. 4,909,295 granted to T. Nirei, et al, involve modifications to the tire structures, also rather expensive.


Method and apparatus are used to reshape isochronous Constant Bit Rate (CBR) and Variable Bit Rate (VBR) data at a receiving point (such as a multimedia workstation) using precise universal real time clocks that are provided by Global Position System (GPS) satellites.

This invention relates to data communication networks, and in particular, to ATM networks for transmitting and receiving isochronous data.
In the data communications process, a sending station can transfer isochronous audio and video data into an ATM network on frame-by-frame basis at a constant rate. Each frame can contain many ATM cells. In transit through the ATM network, the data at a receiving station will be skewed, clumped, and jittered, due to cable propagation delays through the network and ATM cell queueing (ATM cell transfer delays) and through many ATM switches in the network. Thus, the received data have to be reshaped at the receiving station to become a constant data stream as originally arranged.
One conventional method to reshape the data at the receiving station into the original constant rate stream is to transmit timing information to the ATM network along with each frame of the data.
Unfortunately, this method has following disadvantages:
(1) The data transmission is dependent on ATM network clock; PA1 (2) The same network clock must be available at both sending and receiving ends; and PA1 (3) The implementation is complicated. PA1 (1) Data queue size is dependent on cell delay variation; PA1 (2) If cells are lost in transit, null cells must be added to keep the local Phase Locked Loop (PLL) clock stable, thus this method may not be feasible for bursty LAN traffic; and PA1 (3) Network jitter can affect playback of the bit stream (Playback refers to replaying the video and audio data (at a constant rate) to the user (i.e. video screen and sound speakers). PA1 at least one sending terminal, connected to said network system, for sending a data stream containing a plurality of data segments being represented as: data segment (1), data segment (2), . . . , and data segment (n), data segment (i) (i=1, 2, . . . ,n) being sent at a time T.sub.send (i) (i=1, 2, . . . , n); PA1 at least one receiving terminal, connected to said network system, for receiving said data stream including data segment (1), segment (2), . . . , data segment (n), said data segment (i) (i=1, 2, . . . , n) being received at time T.sub.destination (i); PA1 means, at the endpoint of said receiving terminal, for measuring the time delay T.sub.delay (i) between T.sub.send (i) and T.sub.destination (i), (i=1, 2, . . . , n); PA1 means for generating a constant offset bias, said constant offset bias being greater than T.sub.delay (i) (i=1, 2, . . . , n); and PA1 means for outputting said data segment (i) (i=1, 2, . . . , n) at the time of T.sub.send (i) plus said constant offset bias. PA1 at transmitting end of a sending terminal connected to said network system, sending a data stream containing a plurality of data segments being represented as: data segment (1), data segment (2), . . . , and data segment (n), data segment (i) (i=1, 2, . . . ,n) being sent at time T.sub.send (i) (i=1, 2, . . . , n); PA1 at receiving end of a receiving terminal, connected to said network system, receiving said data stream including data segment (1), segment (2), . . . , data segment (n), said data segment (i) (i=1, 2, . . . , n) being received at time T.sub.destination (i); PA1 at the endpoint of said receiving terminal, measuring the time delay T.sub.delay (i) between T.sub.send (i) and T.sub.destination (i), (i=1, 2, . . . ,n); PA1 generating a constant offset bias, said constant offset bias being greater than T.sub.delay (i) (i=1, 2, . . . , n); and PA1 outputting said data segment (i) (i=1, 2, . . . , n) at the time of T.sub.send (i) plus said constant offset bias.
Another conventional method to reshape the data at the receiving station into the original constant rate stream is to store the data received into a data queue. The receiving station then reads the queue with a local clock. The fill level of the queue is used to control the frequency of the local clock. The control is performed by continuously measuring the fill level around the queues midway point. By measuring the fill level a phase-locked loop can reconstruct the local clock. It the queue starts to fill up, the local clock reading the queue speeds up. If the queue starts to empty, the local clock slows down. If the ATM cell is lost in transit through the network, the receiver should detect the loss and put a null cell into the queue, Otherwise, the phase-locked loop reading the queue will become unstable.
While data transmission is independent from ATM network clock, this method has the following disadvantages:
Therefore, it is desirable to provide improved apparatus and method to reshape the data at receiving station into a constant rate stream.

Method and apparatus using GPS to reshape isochronous data at the receiving ends of an ATM network


There is disclosed herein a bulk container valve for use with a bulk container having a tubular spout. The valve comprises a one piece plastic housing having an interior chamber connecting a front port to a rear port. The housing includes a rear fitting about the rear port for connection to the spout, in use, and a front fitting about the front port. A one piece plastic cylindrical valve element is rotationally supported in the interior chamber of the housing for movement between a valve open position and a valve closed position. The valve element includes a handle for selective rotation of the valve element. A collar secures the valve element to the housing to maintain the valve in assembled condition.

This invention relates to intermediate bulk storage containers and, more particularly, to an improved bulk container valve for use therewith.
For shipment of goods, a storage system known as intermediate bulk container (IBC) has found wide acceptance. The IBC comprises a 275 gallon container mounted to a skid or pallet. A wire mesh cage is also mounted to the skid and surrounds the container on all four sides. The top of the container is generally exposed. Additional pallets or IBC""s may then be stacked for shipping and storage.
The IBC is filled at its top by removing a cover providing access to an opening. A bottom spout acts as an outlet for goods stored in the container. A bulk container valve is typically removably secured to the IBC to control removal of goods from the container. Typically the valve is threaded onto the spout. A hose can then be connected to the valve with a cam lever coupling to empty the contents of the IBC.
A typical cylindrical IBC valve comprises a plastic housing with a cylindrical valve element contained within the housing. A handle attaches to the cylindrical valve element. Typically, the handle is secured to the valve element with an external bolt. However, such a bolt can be easily removed, causing the handle to fall off. As is apparent, without the handle the valve would be extremely difficult to operate.
To maintain the valve element within the plastic housing, an arc shaped metal clip engages the shoulder of the housing and a top surface of the valve element. Therefore, the valve consists of three elements, the valve element, a handle, and a clip. This can increase assembly time of the valve.
Typically, a seal is disposed between the valve element and valve housing to prevent fluid leakage. More specifically, an O-ring seal is disposed between the valve element sidewall and the interior wall of the chamber. During service, the valve may be deformed, such as when a laborer inadvertently steps on the valve handle while accessing adjacent containers. This deformation may lead to the escape of fluid past the O-ring seal and out of the valve.
The present invention is directed to solving one or more of the problems discussed above in a novel and simple manner.
In accordance with the invention there is provided a bulk container valve in which the valve element and handle are formed of one piece.
Broadly, there is disclosed herein a bulk container valve adapted for use with a bulk container having a tubular spout. The valve comprises a one piece plastic housing having an interior chamber connecting a front port to a rear port. The housing includes a rear fitting about the rear port for connection to the spout, in use, and a front fitting about the front port. A one piece cylindrical valve element is rotationally supported in the interior chamber for movement between a valve open position and a valve closed position. The valve element includes a handle for selective rotation of the valve element. Securing means for securing the valve element to the housing to maintain the valve in assembled condition are provided.
It is a feature of the invention that the valve includes a sealing plug insertable into the valve element to prevent fluid leakage from within the valve element.
It is another feature of the invention that the securing means comprises a collar having a radially inwardly directed flange.
It is yet another feature of the invention that the valve further comprises a stop on the valve element extending radially outwardly and abutting an arc shaped guide formed within the housing for limiting rotational movement of the handle.
It is a further feature of the invention that the valve comprises a tamper evident pin insertable through rotationally aligned openings formed within each of the housing and the valve element and that the pin is aligned along the radial direction of the cylindrical valve element.
In accordance with another aspect of the invention there is disclosed a bulk container valve comprising a one piece plastic housing having a cylindrical sidewall, a closed bottom end and an open top end forming an interior chamber, the sidewall including a front port and an opposed rear port, the front port having a front fitting and the rear port having a rear fitting for connection to the spout, in use. A generally cylindrical one piece plastic valve element having a proximal and distal end, the distal end being insertable through the open top end of the housing and rotationally supported in the interior chamber, the proximal end including a handle for selective rotation of the valve element between a valve open position and a valve closed position is included. Securing mean for securing the valve element within the interior chamber of the housing is included.
It is a feature of the invention that the securing means comprises a collar having a radially inwardly directed flange, the collar being threadably securable to the housing.
It is another feature of the invention that the valve comprises an O-ring sealing means disposed between adjacent annular surfaces of the housing and the valve element such that radial expansion and contraction of the valve housing and valve element during ovalization does not interrupt the sealing means.
In accordance with yet another aspect of the invention there is disclosed a bulk container valve comprising a one piece plastic housing having an interior chamber connecting a front port to a rear port, the housing including a rear fitting about the rear port for connection to the spout, in use, and a front fitting about the front port. A plastic cylindrical valve element is rotationally supported in the interior chamber of the housing for movement between a valve open position and a valve closed position, the valve element having a handle attached thereto for selective rotation of the valve element is included. Securing means for securing the valve element to the housing comprises a collar threadably attached to the housing. The collar includes a radially inwardly extending flange having a face abutting a surface of the valve element to maintain the valve in an assembled condition.
It is a feature of the invention that the valve element and handle are one piece.
It is another feature of the invention that the collar has an annular surface including regularly spaced protrusions, the surface being engageable with a corresponding surface of the housing during assembly of the valve.
It is another feature of the invention that the valve further comprises a stop on the valve element extending radially outwardly and abutting an arc shaped guide formed within the housing for limiting rotational movement of the handle.
It is yet another feature of the invention that the valve further comprises an O-ring sealing means disposed between adjacent annular surfaces of the housing and the valve element such that radial expansion and contraction of the valve element during ovalization does not interrupt the sealing means.
It is yet a further feature of the invention that the plastic housing is made of propylene.
Further features and advantages of the invention will be readily apparent from the specification and from the drawing.


An apparatus and method are provided for managing a cache hierarchy. The apparatus has processing circuitry for executing instructions, and a cache hierarchy for storing content for access by the processing circuitry when executing those instructions. The cache hierarchy has a plurality of levels of cache including a highest level of cache that is accessed prior to the other levels of cache in response to a request from the processing circuitry. Eviction control circuitry is provided in association with each level of cache, and the eviction control circuitry associated with a chosen level of cache in arranged to implement a most recently read eviction policy that causes content most recently read from the chosen level of cache to be selected for eviction from that chosen level of cache. It has been found that such an approach can significantly increase the effective cache capacity within the cache hierarchy, without the complexities often associated with other schemes.

The present technique relates to an apparatus and method for managing a cache hierarchy.
In a data processing apparatus, it is known to provide a cache hierarchy between the processing circuitry used to execute instructions and main memory, the cache hierarchy being used to store content for access by the processing circuitry when executing the instructions, with the aim of providing quicker access to that content than would be the case if the content had to be accessed in main memory. The content stored in the cache hierarchy may comprise instructions to be executed by the processing circuitry and/or data values to be operated on when executing those instructions.
The individual caches within the cache hierarchy can be organised with respect to each other in a variety of ways. It is typically the case that the caches closer to the processing circuitry (i.e. the ones that are accessed first when an access request is issued by the processing circuitry) have a smaller capacity than the caches further away from the processing circuitry. Accesses to a cache will typically be quicker when the cache is of a smaller size, and accordingly such an arrangement enables faster access to the content when it is in one of the caches closer to the processing circuitry.
It is also often desirable to seek to increase the effective capacity of cache storage within the cache hierarchy so as to increase the amount of content that can be retained within the cache hierarchy at any point in time. One known way to seek to increase the effective capacity between two adjacent levels of cache is to arrange for those caches to operate as exclusive caches. In accordance with an exclusive cache arrangement, any item of content will only be cached in one of the caches at any particular point in time. However, operating caches in a fully exclusive arrangement requires significant overhead in terms of the complexity of the control circuitry required to maintain the exclusive arrangement between the caches.
Accordingly, it would be desirable to provide alternative techniques for increasing the effective cache capacity.

Apparatus and method for managing a cache hierarchy


A data array system, and inter-controller-link messaging method, for controlling redundant access to a storage device and providing inter-controller communication without a dedicated controller link. The host has a host bus, such as a PCI bus, and the system includes an active and a standby controller that are linked to the host bus and use the host bus for an inter-controller-link. A messaging mechanism transmits messages and data over the host bus from the active to the standby controller. The standby controller includes message and data buffers for storing the messages and data written and a message queue in which the active controller writes a signal identifier indicating that a new message has been written and defining the message for processing by the standby controller (such as a message-only transfer, a partial or all data transfer, or as a data-only transfer).

1. Field of the Invention
The present invention relates, in general, to data storage networking technology, and more particularly, to a system and method for communicatively-linking redundant data array controllers using the host bus, and more particularly, the host PCI bus, as the inter-controller-link and for controlling redundant messaging or communications at the array controllers rather than at the host.
2. Relevant Background
Modern mass storage subsystems are continuing to provide increasing storage capacities to fulfill user demands from host computer system applications. This reliance on large capacity mass storage has led to increased demands for enhanced reliability. Various storage device configurations are used to meet the demands for higher storage capacity while maintaining or enhancing reliability of the mass storage subsystems.
One solution to these mass storage demands for increased capacity and reliability is the use of multiple smaller storage modules configured in geometries that permit redundancy of stored data to assure data integrity in case of various failures. In many such redundant subsystems, recovery from many common failures can be automated within the storage subsystem itself due to the use of data redundancy, error correction codes, and the like. These subsystems are typically referred to as redundant arrays of inexpensive (or independent) disks (or more commonly by the acronym RAID). There are five "levels" of standard geometries defined for RAID. The simplest array, a RAID level 1 system, comprises one or more disks for storing data and an equal number of additional "mirror" disks for storing copies of the information written to the data disks. The remaining RAID levels, identified as RAID level 2, 3, 4 and 5 systems, segment the data into portions for storage across several data disks. One or more additional disks are utilized to store error check or parity information.
RAID storage subsystems typically utilize a control module or array controller that at least partially shields the user or host system or server from the details of managing the redundant array. The array controller makes the subsystem appear to the host computer as a set of highly reliable, high capacity disk drives independent of the physical drive size and characteristics. In fact, the array controller may distribute the host-supplied data across a plurality of the small independent drives with redundancy and error checking information so as to improve subsystem reliability. Frequently RAID subsystems provide large cache memory structures to further improve the performance of the RAID subsystem. The cache memory is associated with the control array such that the storage blocks on the disk array are mapped to blocks in the cache. This mapping is also transparent to the host. The host system simply requests blocks of data to be read or written and the RAID controller manipulates the disk array and cache memory as required.
To further improve reliability, redundant array controllers are sometimes provided to reduce the failure rate of the subsystem due to control electronics failures. In some redundant architectures, pairs of control modules are configured such that they control the same physical array of disk drives. A cache memory module is associated with each of the redundant pair of control modules. When one of the redundant pair of control modules fails, the other stands ready to assume control to carry on operations on behalf of I/O requests. Typically, one controller, often referred to as a master or the active controller, essentially processes all I/O requests for the RAID subsystem. The other redundant controller, often referred to as a slave or passive controller, is simply operable to maintain a consistent mirrored status by communicating with the active controller. The caches are mirrored on each controller, and it is desirable that writes posted to the active controller are mirrored on the standby or passive controller. In the case of dual active controller arrangements, the passive controller may manipulate data on separate logical units and this may occur even on the same drive set. For any particular RAID logical unit (a group of disk drives configured to be managed as a RAID array), there is a single active controller responsible for processing of all I/O requests directed thereto. The passive controller does not concurrently manipulate data on the same RAID logical unit.
The data storage industry continues to struggle how most efficiently to facilitate controller redundancy. A key design issue arises because the redundant control modules must communicate with one another to assure that the cache modules are synchronized and to provide proper redundancy. It is common in the art to require host intervention to coordinate failover operations among the controllers and to facilitate communications, i.e., to provide a host-driven redundancy scheme. Host interaction and control over communications may be undesirable because it reduces host processing efficiency as processing time is used to control and monitor controller communications and limits host interoperability as each array controller platform may vary significantly. Further, host interaction and control for redundancy is not readily available and is often expensive. Host involvement to maintain mirrored caches requires data movement from the host (e.g., the host processor, host memory, host North Bridge, and Peripheral Component Interconnect (PCI) bus) twice, once to each controller, and therefore, is undesirable because it reduces available bandwidth by half.
A number of arrangements currently exist for allowing the active and passive controller to communicate. In one arrangement, the host system needs to provide two special and dedicated extended bus slots (such as PCI extended slots) for host to controller communications and using a channel on the controller (such as a Small Computer System Interface (SCSI) channel) and a shared bus for the link between the controllers. The provision of extended bus slots is not common in host devices such as servers, and this arrangement requires the host to include controller control software and uses up a communication channel on each controller. Similarly, some arrangements call for a separate bus (such as a SCSI bus) or storage communications network (such as Fibre Channel (FC), Gigabit Ethernet, and the like) that provides a communication path between the host and each of the redundant controllers. Again, this requires controller command or communication mechanisms to be run by the host or in peripheral host devices and often requires additional hardware, such as host bus adapters (HBAs) to provide a link between the host bus and the communication link to the controllers. Further, the controllers still require a dedicated or shared bus and communication channel to provide inter-controller communications.
Hence, there remains a need for an improved system and method for providing array controller redundancy and communicatively linking the pair of redundant array controllers. Preferably, such a system and method would reduce processing demands on host devices, reduce the need for dedicated or specialized communication busses and communication ports, and increase interchangeability of hosts.

Data array having redundancy messaging between array controllers over the host bus

Hewlett-Packard Development Company, L.P.


The invention provides an improved air chiller unit mounted on an aircraft for sending cooled air to service carts used for serving meals. A compressor 20 of a refrigerant equipped in an air chiller unit has a motor 210 and a rotary compressor 220 disposed in a cylindrical housing 200. An oil separator unit 240 attached to the top portion of a drive shaft 214 of the motor has two disks 241 and 242 which define two labyrinth portions G1 and G2 for effectively separating lubricating oil from the refrigerant traveling toward a refrigerant exit 203.

1. Field of the Invention
The present invention relates to an air chiller unit (air cooling device) equipped within a body of an aircraft, for supplying cooled air to foods or the like.
2. Description of the Related Art
Passenger aircrafts that travel long distances, such as international flights, are equipped with service carts storing meals etc. to be served to passengers, and galleys (kitchen areas) storing the service carts for preparing beverages and carrying out easy food preparation.
The meals are cooked in advance in service facilities on the ground, placed on trays to be stored in service carts, and brought on board.
Of the meals placed on the trays, warm dishes are heated by a heater etc., and cold dishes such as salads are maintained at low temperature by cooled air fed into the service carts.
Patent document 1, U.S. Pat. No. 5,491,979, discloses an example of a device for cooling service carts.
The air chiller unit is disposed in a space provided on the ceiling or under the floor of the galley in the aircraft. The air chiller unit is equipped with a refrigeration cycle unit, cooling air by an evaporator disposed with in a cooling air chamber and supplying the cooled air via a duct to the galley or the like.
Since the air chiller unit is equipped in an aircraft, the unit is required to be light weight and small sized, and since it is located near the passenger seats, the noise generated by the unit must be reduced.


A premixed combustion burner for a gas turbine can efficiently premix fuel and air to produce fuel gas having a uniform concentration, while reliably achieving prevention of flash back by making the flow rate of fuel gas substantially uniform. The premixed combustion burner for a gas turbine has a fuel nozzle, a burner cylinder arranged so as to surround the fuel nozzle and form an air passageway between itself and the fuel nozzle, and swirler vanes that are arranged along an axial direction of the fuel nozzle in a plurality of positions around the circumferential direction of an outer circumference surface of the fuel nozzle. The swirler vanes gradually curve from an upstream side to a downstream side to spin the air traveling within the air passageway from the upstream side to the downstream side. A cutaway section is provided in a rear edge section on an inner circumference side of the swirler vanes.

1. Field of the Invention
The present invention relates to a premixed combustion burner for a gas turbine. The present invention is devised so that fuel and air can be efficiently premixed to produce fuel gas having a uniform concentration, while achieving reliable prevention of flash back (back fire) by making the flow rate of fuel gas substantially uniform.
2. Description of Related Art
As a premixed combustion burner for a gas turbine, for example, the premixed combustion burner disclosed in Japanese Translation of a PCT International Application, Publication No. 2006-500544 is commonly known.
The invention disclosed in the above patent document is to prevent flash back by lowering the fuel concentration on an inner circumference side (radial direction inner side) of an air passageway.
However, since a total amount of fuel injected into the air passageway per unit time does not change, the fuel concentration in another area (for example, the area on the outer circumference side of the air passageway) increases inversely to the reduction made in the fuel concentration on the inner circumference side of the air passageway, and flame temperature rises on the downstream side, resulting in a possible increase in NOx.

Premixed combustion burner for gas turbine


An apparatus, system and method for verifying the achievement of a desired sterility assurance level (SAL) for components manipulated within a low-energy electron beam sterilization chamber. The components are preferably pre-sterilized and connected together in an assembly fashion which creates and maintains the sterility of the connection by subjecting the components to low-energy (less than 300 KeV) electron beam radiation. The verification is completed by measuring the sterilization dose delivered to a sensor, also known as a dosimeter, positioned within the sterilization process to simulate the components.

In general, the sterilization of medical products depends upon the ability of the process to kill pathogenic microorganisms. The application of radiation to sterilize medical products is widely used throughout the world and recognized as a safe, effective form of sterilization. The first commercial application of electron beam sterilization processing for medical devices was developed by Ethicon Inc., a subsidiary of Johnson and Johnson in 1956. In the early 1960s the use of gamma rays from Cobalt-60 for the sterilization of disposable medical devices was being developed in the United Kingdom. Because of the poor reliability of the early electron beam systems, the radiation sterilization of medical products was dominated by Cobalt-60 (gamma) irradiators, which had no similar reliability issues.
With the advent of national laboratories devoted to high-energy physics research, a major effort was put into improving the reliability and performance of critical accelerator components. By the 1970s, industry's involvement in developing radiographic and oncology machines further enhanced the durability and reliability of electron accelerators. This improvement of component performance—along with the integration of computerized controls—encouraged reevaluation of the commercial possibilities of the technology. Soon thereafter, interest in high-energy (>300 keV) E-beam based sterilization was rapidly growing.
Perhaps the largest industrial application of radiation is the modification of polymers. Radiation is used to polymerize and cure monomers into polymers, to cross-link polymers, and to graft different types of monomers onto polymer molecules to form new materials with special properties. Radiation is also used for the intentional degradation of polymers and for tailoring of molecular weight distributions to serve special industrial and commercial purposes. This industrial application of radiation is dominated by low energy (<300 keV) electron beam systems.
In 1999, use of a low-energy (<300 KeV) E-beam system in sterilization of medical devices was described in U.S. patent application Ser. No. 09/294,964, filed Apr. 20, 1999, now U.S. Pat. No. 7,264,771, assigned to the assignee of the present application, Baxter International, the relevant disclosure of which is hereby incorporated by reference. E-beam sterilization unit size and cost were two big factors feeding the move toward low-energy sterilization systems. Depth of the sterilizing radiation penetration became the tradeoff. Where high-energy systems may achieve penetration depths of over a meter, low-energy beams are limited to penetration depths of as low as only a few microns.
The significantly reduced radiation penetration of low-energy electron beams used for medical device sterilization raised the issue of sterility validation as a processing concern. The FDA requires that "all processes used to produce medical devices be validated" (21 C.F.R. §820.752), including E-beam sterilization. The goal of such validation is to determine the minimum exposure dose that can be used to meet a desired sterility assurance level and allow "dosimetric release," which is the determination that a product is sterile based on physical irradiation process data rather than actual sterility testing.
Therefore, validation must begin with the selection of a sterility assurance level (SAL), a measure of the probability that one unit in a batch will remain non-sterile after being exposed to a specific sterilant. For example, an SAL of 10-3 means that one device in a thousand may be non-sterile. Selecting the proper SAL occurs during a dose-setting phase of radiation sterilization validation. In many cases, the intended use of the device will dictate the need for a particular SAL. The commonly accepted SAL for invasive medical devices is 10-6. However, some European countries only recognize 10-6 SAL for a claim of "sterile." In such cases, the country of intended use will dictate the SAL as much as the device's intended use.
Although both gamma and ethylene oxide-gas sterilization are validated, effective and readily available technologies, the increased focus on E-beam can be ascribed to its having the shortest process cycle of any currently recognized sterilization method. In both high- and low-energy E-beam processing, the products are scanned for seconds, with the bulk of the processing time devoted to transporting the products into and out of a shielded booth. With the use of established and recognized dosimetric release procedures, a product under going high-energy E-beam sterilization can be released from quarantine as sterile within 30 minutes. The prior art, however, has not sufficiently developed a method for validation and routine monitoring of low-energy E-beam sterilization.
As a solution to this problem, the present invention has been developed which provides an apparatus for use in the validation of low-energy electron beam sterilization systems. Furthermore, the invention provides a method that cost-effectively and reliably provides for the routine dosimetric monitoring of the sterilization process for low-energy electron beam sterilization systems.

Method and apparatus for validation of sterilization


The present application discloses various embodiments of a hemostatic device with improved comfort features over the known prior art, including hemostatic devices having attachment straps with non-linear edges and/or non-planar skin-facing edges.

The present invention relates to a hemostasis band that is adapted to act as a compression device to promote hemostasis at a surgical access site, and more particularly to a hemostasis band having an improved edge design for increased user comfort.
After a surgical procedure involving arterial or venous access, it may be desirable or necessary to apply pressure to the access site to promote hemostasis. Some existing hemostasis bands may be uncomfortable to users. Accordingly, there is a need for a hemostasis band that addresses this and other drawbacks of the prior art.

Hemostasis band with improved edge design


A trajectory generation device which generates a trajectory of a robot includes: a trajectory exploration graph generation unit which is configured to generate a trajectory exploration graph composed of a plurality of nodes for generating the trajectory; an acceleration upper limit value acquisition unit which is configured to acquire a first acceleration upper limit value based on orientations and an acceleration direction of the robot at a current node; a velocity and acceleration setting unit which is configured to set a first velocity representing a velocity when moving from the current node to a next node adjacent to the current node based on the acquired first acceleration upper limit value, and an acceleration; and a node cost calculation unit which is configured to calculate a moving time by using the set first velocity and the acceleration as cost from the current node to the next node.

Patent Literature 1 discloses "a control device for an articulated robot that includes a rotation arm having a plurality of rotation axes driven by a motor and operates according to a program taught in advance, and the control device for the articulated robot is provided with an unit that calculates an allowable maximum acceleration at a current position and a target position of the rotation axis by an inertia term of the arm around the corresponding rotation axis calculated from rotational position information of the current position and the target position of the motor and a gravity term calculated in consideration of direction information which accelerates the arm".

Trajectory generation device, trajectory generation method, and robot system


A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at one side of the buried gate, a landing pad on the metal contact, a capacitor on the landing pad and electrically connected to the active region, and a metal oxide layer between the metal contact and the active region.

1. Field of the Invention
The present inventive concept relates to semiconductor devices and methods of forming semiconductor devices.
2. Description of the Related Art
As feature sizes of semiconductor memory devices are reduced, short channel effects have become more and more problematic. To overcome short channel effects, a buried channel array transistor (BCAT) structure, including a gate electrode buried in a trench, has been proposed. However, various characteristics of BCAT devices, including, for example, gate induced drain leakage (GIDL), current amount, etc., may vary depending on how much the gate electrode is buried in the trench.

Semiconductor devices including buried channels