Exemplary embodiments of the present invention relate to a backlight assembly and a display device, including a backlight unit including a light emitting diode (LED) light source of and a light guide, and a bottom chassis disposed at a rear surface of the backlight unit, wherein the bottom chassis includes a bottom chassis main body, an inner supporting member disposed at an inner surface of the bottom chassis main body, an outer supporting member disposed at an outer surface of the bottom chassis main body, and a fastener to fasten at least two of the bottom chassis main body, the inner supporting member, and the outer supporting member.

1. Field
Exemplary embodiments of the present invention relate to a backlight assembly and a display device.
2. Discussion of the Background
Various flat panel displays, such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) display, an electrowetting display (EWD), an electrophoretic display (EPD), an embedded microcavity display (EMD), and a nanocrystal display (NCD), have been developed.
A liquid crystal display (LCD) has advantages of a reduced size and weight compared to conventional cathode ray tube (CRT) display devices, and may have low power consumption. As a result, the liquid crystal display (LCD) is used in numerous information processing devices requiring a display. Conventionally, a liquid crystal display is a display device in which a differential voltage is applied to two electrodes in the LCD to generate an electric field, a liquid crystal material is injected between an upper substrate on which a common electrode, a color filter is formed, and a lower substrate on which a thin film transistor and pixel electrode are formed. By applying different potential voltages to the pixel electrode and the common electrode, an arrangement of liquid crystal molecules in the liquid crystal layer may be changed and/or controlled. Transmittance of light is adjusted through the change of the arrangement of the liquid crystal molecules to display an image on the display screen.
A liquid crystal display panel, in a liquid crystal display is a light receiving element which may not, by itself, emit light. Accordingly, the liquid crystal display may include a backlight unit for providing light to the liquid crystal display panel under the liquid crystal display panel.
The backlight unit is classified into an edge type of backlight unit, and a direct type of backlight unit according to a position of a light source of the backlight unit. The edge type of backlight unit, in which a light source is positioned in a side surface, transmits light provided from the light source to a display panel in an upper side by using a reflection sheet.
The liquid crystal display, including the backlight unit, is fixed and supported by a top chassis and a bottom chassis. The bottom chassis is positioned at a rear surface of the backlight unit and must have a predetermined angle to support and protect the liquid crystal display and not be bent. To support the LCD structure, the bottom chassis may have a protruding structure through a forming process.
However, the protruding structure may be difficult to manufacture according to the forming process. As the size of a display device increases, more support and strength is required to support the LCD structure. The strength of the LCD structure may decrease if the bottom chassis is twisted.
To reduce weight of the large sized display device, the bottom chassis is formed of a light metal such as aluminum. However, a strength of the LCD is not determined by only the forming process. Another problem is that the liquid crystal display and the backlight unit may not be adequately protected in the forming process.
The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.


The present application provides a chip package structure and an electronic device, which could reduce a chip package thickness and implement ultra-thinning of chip package. The chip package structure includes a chip, a substrate, a lead and a lead protection adhesive; the lead is configured to electrically connect the chip and the substrate; the lead protection adhesive is configured to support the lead, where a highest point of the lead protection adhesive is not higher than a highest point of an upper edge of the lead.

At present, in a process of packaging an electronic chip, two manners are generally adopted for packaging a lead: molding package and dispensing package. A common dispensing package method is to completely wrap a first solder joint, a second solder joint of a lead and the lead with a protection adhesive, so as to play a protective role. Therefore, in this dispensing package method, a height of the protection adhesive needs to be higher than a height of the lead thereby occupying entire thickness space of a packaged product, which is not conducive to development of ultra-thinning of a product.

Chip package structure, electronic device and method for preparing a chip package structure


A leak detection device includes a high vacuum pump implemented as a friction vacuum pump with two further vacuum pumps operating against atmospheric pressure. The further vacuum pumps are dry-sealing pumps in order to avoid hydrocarbon contaminations in a region of a test sample or a test chamber.

The invention relates to a leak detection device with a high-vacuum pump implemented as a friction vacuum pump and two further vacuum pumps working against atmospheric pressure. The invention, furthermore, relates to a process for operating such leak detection device.
A leak detector of this type is disclosed in EU-A-283543. It operates according to the principle of counterflow (with helium as the test gas) and permits the detection of the impermeability of a test sample, respectively its permeability, and specifically gross impermeability to extremely small leaks (leakage rates up to 10.sup.-10 mbars l/s). In the helium leak detection with a device of the prior known type, the danger exists of hydrocarbon contamination occurring in the region of the test sample and/or the test chamber. These are caused by molecules which originate in the suction chambers of the oil-sealed vacuum pumps operating against atmospheric pressure and which diffuse back into the high-vacuum region against the delivery direction of the vacuum pump.

Leak detector with vacuum pumps and operating process for same


A methodology for allowing component models to be developed independently and allowing a user to select and connect a set of models into a desired multi-component configuration at run-time. The component models are built free from inter-model dependencies, thereby enhancing flexibility and reuse. The component models conform to a standard interface for initialization (prior to simulation run) and inter-model communication (prior to and during a simulation run).

1. Technical Field
The present invention relates generally to software tools used to model the behavior of complex systems.
2. Description of the Related Art
Complex systems are typically built from many discrete components. In a given field of interest, different systems often utilize many of the same components. Computer systems are a classic example. Such systems are designed and built from many discrete system components including, without limitation, processors, caches, memories, buses, bridges, adapters and peripherals. Building and analyzing models of such complex systems provides insight into the behavior of such systems.
In the prior art, it is known to build models of a small number of components of a given computer domain (e.g., a network) and then to use such component models for the purpose of analyzing or predicting the effects of individual components on system performance. Such schemes, however, are limited in their applicability to the particular domain for which the component models are designed. These known techniques do not afford a methodology or the tools necessary to enable complete "end-to-end" system modeling wherein a model may represent any complex system from a small subsystem up to an entire multiprocessor/multicomputer network. Another prior art approach is to model from a "system-centric" or top-down approach, whereby particular components of a system configuration are modeled with system-wide dependencies. In the latter approach, individual system components are not "isolated" from each other in the system model and thus are interdependent. Individual component models are rarely reusable to any significant extent in other system models. Therefore, the usefulness of the overall system model is limited to a specific subset of configurations.
There has been a long-felt need in the art to provide fully "end-to-end" system models using individual system component models or modules that are truly independent and that may be seamlessly connected in a building block fashion. This invention is directed to solving this important problem.

Method for flexible simulation modeling of multi-component systems

International Business Machines Corporation


The present invention relates to mercury amalgams in discharge lamps for use at elevated operating temperatures.

Discharge lamps with a mercury fraction in the discharge medium have long been known and are the subject of intensive development work. It is known in particular to introduce mercury into the lamp in the form of an amalgam addition. On account of its relatively high vapor pressure at the temperatures which are encountered and on account of the efficiency with which UV is generated in discharge media with a mercury fraction, mercury is especially suitable for these applications and is therefore in widespread use. If mercury is introduced in the form of amalgams, a range of technical criteria need to be taken into account and complied with, in particular the stability and mechanical handling properties and/or consistency of the amalgam, as well as the vapor pressures in the temperature range in question.

Mercury amalgams for elevated temperatures in discharge lamps


A relay device includes a security information reception unit, a security information processing unit, and a security information transmission unit. The security information reception unit receives, from a terminal device, first security information containing a user ID and user authentication information of a user of the terminal device. The security information processing unit adds a relay device ID and relay device authentication information to the first security information to generate second security information. The security information transmission unit transmits the second security information to an authentication server.

1. Field of the Invention
The present invention relates to a relay device, an authentication server, and an authentication method.
2. Description of the Related Art
Conventionally, when a relay device is controlled by a provider, an authentication server has notified security information necessary for keeping data secret, securing data integrity, or the like to the relay device controlled by the provider (referred to as "provider-controlled relay device", hereinafter). Accordingly, data has been kept secret and data integrity has been secured between a terminal device and the provider-controlled device. FIG. 1 shows that a secure communication path is established between a terminal device 100 and a provider-controlled relay device 200a.
Additionally, it can be imagined that not only the provider-controlled relay device but also a relay device not controlled by the provider (referred to as "provider-uncontrolled relay device", hereinafter) will have to be accommodated (e.g., H. Yumida, et al, "IP-Based IMT Network Platform", IEEE Personal Communication Magazine, October 2001, pp. 18 to 23). As the provider-uncontrolled relay device, for example, an access point set at user's home or office may be cited. Thus, in the case of accommodating such a provider-uncontrolled relay device, data must be kept secret and data integrity must be secured between the terminal device and the authentication server. FIG. 1 shows that a secure communication path is established among the terminal device 100, a provider-uncontrolled relay device 200b, and an authentication server 300.
However, the provider-uncontrolled relay device may disguise itself as a provider-controlled relay device by using an ID of the provider-controlled relay device to bug or falsify data, creating a danger of invading user's privacy. FIG. 2 shows that the provider-uncontrolled relay device 200b disguises itself as the provider-controlled relay device 200a by using an ID (ID#1) thereof.
The present invention has been developed with the foregoing problem in mind, and objects of the invention are to provide a relay device capable of preventing a danger that a provider-uncontrolled relay device will disguise itself as a provider-controlled relay device to bug or falsify data, thereby invading user's privacy, an authentication server, and an authentication method.

This patent is subject to a terminal disclaimer.

Relay device, authentication server, and authentication method


A mask having a removable respirator, a viewing glass and flexible fastening straps on the rear side thereof is provided. The respirator and the viewing glass are fixed by respective fixing rings to suitable positions in front of the mask. The fixing rings are tightened by a screw having a turning grip formed on the top thereof, so that it makes possible simple disassembly without the use of tools. The screw is also provided with a flange adapted for convenient attachment of a speech microphone thereto.

The present invention relates to a mask of a novel design, more specifically it relates to such a design of mask which permits the respirator and the viewing glass, both being components thereof, to be simply and promptly removed, without recourse to any other tools, so as to facilitate cleanup services. Further, it permits ready and reliable attachment of a speech microphone to a given side thereof, thus achieving its novelty and advantageous features.
Conventionally, various models of masks, either for anti-gas, or for anti-smoke purposes, owe their structure to the mounting of the respirator and of the viewing glass to the front-piece, by such fixing parts as the frame, screws and nuts. The front-piece being complete with fastening straps.
With models of such conventional design, apart from the necessity for a secured interconnection between the respirator and the viewing glass, consideration must also be given to the interfacing anti-leak requirements, so in the assembling process tools are indispensable, like a screwdriver and similar items, to lock the respirator, viewing glass and the front-piece in a tightly sealed state. Similarly, the same tooling is needed when the user wants to remove these components to undertake cleanup or maintenance services, such service being preconditioned by unscrewing, and disassembling efforts.
Disassembling a mask by means of necessary tools, in the exercise of regular servicing procedures, is quite all right. It can indeed prove a very big problem under unexpected situations, for instance in pre-mission examinations, when a poor seal is identified in the wake of permeating smoke at the scene of a fire, or when the frame loosens so as to leak, due to collisions. All of these situations prescribe that a suitable and workable tooling be readily available.
All of the aforementioned drawbacks and inconveniences can only be eliminated, and the efficiency of conventional masks enhanced, by the design of a device which permits easy adjustment of the locking means, assembling, and disassembling of the mask proper, just as does certain models of pistols which can be readily disassembled without any tooling for facilitating cleanup services. However, such a design has heretofore not been available.


A method is provided in one example embodiment and includes receiving at a first network element a packet from a second network element; processing the packet at the first network element to obtain information regarding an identity of a virtual machine (“VM”) hosted by the second network element contained within the packet; and storing at the first network element the identifying information. The identifying information stored at the first network element is accessible by at least one third network element. In some embodiments, the first network element comprises a physical switch and the second network element comprises a virtual switch.

Currently, for virtualized data centers, visibility of orchestration engines, such as vCloud Director, Openstack, and Cloupedia, to name a few, is limited to the hypervisors and virtual switch managers. Such orchestration engines provision virtual machines ("VMs") and their resources, both on the hypervisor and on the virtual switches. All of these VMs talk to the other VMs or to the infrastructure outside the data center via the data center network fabric. The network fabric comprises a collection of Top of Rack ("ToR") switches, referred to as leaf switches, that in turn are connected by a set of spine stitches. The orchestration engines do not have visibility into the fabric; similarly, the switches in the fabric have no visibility into the server and their hypervisor infrastructure. Hence, the switches cannot relay to the network or server administrators information regarding where a particular VM is physically attached to the network.
A crude way of tracking this information would be to dump the Address Resolution Protocol ("ARP") and Media Access Control ("MAC") tables and then attempt to correlate the information to form a table of directly attached local hosts. This is not only unwieldy but would make it very difficult for the administrators to correlate the information across various databases; moreover, the information would be provided on a per-interface or per-virtual Network Interface Card ("vNIC") basis, rather than a per end host/VM basis.

Enabling scalable virtual machine tracking in a data center fabric


An automatic transmission with an anti-creep control apparatus includes a torque converter connected to the engine, first and second friction elements, and a control unit. The first friction element is operated when the automatic transmission is put in a drive range. The second friction element performs to prevent a reverse rotation of an output shaft of the automatic transmission. The control unit executes an anti-creep control controls, controlling the second friction element to prevent a reverse rotation of an output shaft of the automatic transmission when the anti-creep control is executed, holds the engagement of the second friction element during a time period from the time when the anti-creep control is cancelled to the time when the first friction element is fully engaged, and disengages the second friction element thereafter.

The present invention relates to improvements in an automatic transmission with an anti-creep control apparatus for a vehicle.
Japanese Patent Provisional Publication No. 63-106449 discloses an apparatus that executes an anti-creep control for preventing a transmitting of engine power to driven wheels during an idling condition and a hill-hold control for preventing the backward movement of a staying vehicle on an uphill road. The shift change control can be executed by selectively operating friction elements, as shown by a time chart in FIG. 10: (a) starting the anti-creep control at the moment T1, (b) starting the hill-hold control at the moment T3 so as to engage a brake for shifting (second coast brake), (c) starting a starting operation of the vehicle at the moment T3, and (d) canceling the anti-creep control by the execution of the starting operation. The apparatus executes a control for starting the engagement of the forward clutch and for promptly disengaging a shifting brake of the automatic transmission at the moment T5 when the hydraulic pressure of a forward clutch (C1) reaches a predetermined value P.sub.sset. During this period, by applying a signal pressure Ps to a servo hydraulic pressure control of the forward clutch and a servo hydraulic pressure control of a brake for shifting, the hydraulic pressure of the both servos are relationally controlled.
However, an actual clutch hydraulic pressure and an actual brake hydraulic pressure are not applied to the servo control of the forward clutch and the shifting brake although the signal hydraulic pressure Ps is used to relationally control the forward clutch and the shifting brake. Therefore, if the responsibility of the actual clutch hydraulic pressure and the actual brake hydraulic pressure are deviated, various problems are generated by this apparatus. For example, in order to start the engagement of the forward clutch (C1) and to simultaneously cancel the anti-creep control at the moment T5 after the acceleration ON at the moment T4 shown in FIG. 10, it is necessary to raise the forward clutch hydraulic pressure to a value that is greater than the hydraulic pressure value Px since the input torque of the automatic transmission is increased. In order to prevent the engagement shock, the hydraulic pressure is once increased to the shelf pressure and then to the maximum pressure. Herein, if the forward clutch hydraulic pressure is radically (such as steppingly) increased to the shelf pressure Px to execute the engagement of the forward clutch, the shifting brake (B1) is fully engaged at the moment T5 and the reduction speed ratio is set at the first speed since the hydraulic pressure of the shifting brake is promptly decreased. As a result, the shock due to the engagement of the forward clutch (C1) is amplified by the first speed and performs as an output shaft torque. Therefore, a drive feels large engagement shock.
Further, when it is intended to radically increase the forward clutch hydraulic pressure, the hydraulic pressure responsibility is largely degraded if entrained air exists in the hydraulic passage of the control hydraulic system for the forward clutch and the shifting brake or if it is cold. When the responsibility of the forward clutch hydraulic pressure is degraded by the entrained air in the hydraulic passage and that no air is mixed in the hydraulic passage of the control hydraulic system of the shifting brake (B1), the hydraulic pressure of the shifting brake (B1) is promptly decreased and the shifting brake (B1) is fully disengaged. Therefore, the hill-hold function becomes inoperative. If the vehicle is put in this situation, during a time period from the moment T4 to the moment T5, the forward clutch hydraulic pressure is not sufficiently increased and the output torque is still small. Therefore, the automatic transmission is temporarily set in the neutral position. This invites a problem that the vehicle is moved backward on an uphill road.

Automatic transmission with anti-creep control apparatus


A wireless communications system that allows a mobile phone, tablet or personal computer user the ability to initiate the sending of a text message or email whereby the sender is able to include photographs, graphs, pie charts and the like within the flow of the actual word by word texting or email writing process, without depending on the traditional necessary step to “attach” the photograph.

In a traditional texting or messaging environment, in order to insert media data other than text, a user must go through a cumbersome process of attaching the media data, select the media data through a series of menus, or otherwise go through similar cumbersome processes of attaching the media data. Further, such inserted data is typically generic and impersonal to the users.
Therefore, there is a need for a messaging system that optimizes the information power of the communication process between users and further adds a personal feeling and experience, which in turn, substantially increases the amount of information per message.

Media messaging methods, systems, and devices


A tissue cutting instrument includes an outer member, an inner member received within the outer member, and a cutter coupled to the inner and the outer members such that rotation of the inner member about an axis causes off-axis movement of the cutter. A method of cutting tissue includes positioning an outer member such that the outer member is adjacent tissue, engaging the tissue with a cutter coupled to the outer member, and moving the cutter to end-on cut the tissue. The extended portion of the cutter extends distally beyond a terminal end of the outer member.

A conventional tissue cutting blade typically includes two coaxial tubes or members, where one tube rotates or reciprocates within the other. Each tube has geometry cut therein to form the cutting edges. For soft tissue cutting blades, the tubes are matched with minimal clearances to provide a shearing action between them. Bone cutters typically use a burr-type inner member, which does not depend on the outer member for shearing. With both of these designs, the cutting action of the blade is reduced close to the rotational axis of the blade. This is due in part to the surface speed of the blade approaching zero close to the blade axis.


A piezoelectric vibrator unit comprises: at least one piezoelectric vibrator including: common internal electrode layers and segment internal electrode layers arranged alternately; piezoelectric layers, each interposed between adjacent pair of the common and segment internal electrode layers; and external electrodes formed on an exterior of the piezoelectric vibrator and electrically connected respectively to the common internal electrode layers and the segment internal electrode layers; and a fixing member to which a surface of the piezoelectric vibrator is fixed. The piezoelectric vibrator is displaceable in a direction perpendicular to a lamination direction in which the internal electrode layers and piezoelectric layers are laminated. The magnitude of electric fields applied to the piezoelectric layers is non-uniform.

The present invention relates to a piezoelectric vibrator unit preferably used to eject ink droplets, and an ink-jet recording head that employs the piezoelectric vibrator unit. In particular, the present invention relates to a piezoelectric vibrator unit and an ink-jet recording head that can suppress bending during the operation of the piezoelectric vibrator.
An ink-jet recording head (hereinafter referred to as a recording head) used for an image recording apparatus, such as an ink-jet printer or plotter, comprises: a flow passage unit, which includes pressure chambers and a reservoir; and a piezoelectric vibrator unit, which is located at the rear of the flow passage unit and which includes a plurality of piezoelectric vibrators for changing the volumes of the associated pressure chambers.
The following procedures, for example, are employed to fabricate the piezoelectric vibrator unit. First, common internal electrodes and segment internal electrodes are alternately laminated with piezoelectric material interposed between the adjacent internal electrodes to thereby form a plate-like laminated member. A common external electrode and a segment external electrode are formed on a surface of the laminated member to be electrically connected to the common internal electrodes and the segment internal electrodes, respectively. Then, one side face of the base end portion of the laminated member having the external electrodes is secured to a fixing plate, and thereafter, the leading end portion of the laminated member is cut into a plurality of extremely narrow piezoelectric vibrators using the a wire saw or a dicing saw.
The piezoelectric vibrator of this type is affected by a constraining force exerted at a joint portion thereof because one side face of the base end portion of the laminated member is secured to the fixing plate. That is, when voltage is applied to the external electrode to cause the piezoelectric vibrator to contract, the piezoelectric material in the opposite side (i.e. the side opposite in the lamination direction from the side where the piezoelectric vibrator is fixed to the fixing plate) tends to contract slightly more than the piezoelectric material in the fixing plate side.
Therefore, as shown in FIG. 9, bending occurs, i.e., the piezoelectric vibrator 200 is bent in the lamination direction away from the fixing plate 204 (upward in FIG. 9).
Due to such bending of the piezoelectric vibrator 200, a pressure wave as denoted by α in FIG. 10 is generated within the pressure chamber 203 of a recording head 202, which repeatedly reflects and reciprocates within the pressure chamber 203 as if the pressure chamber 203 was an acoustic tube. The pressure wave adversely affects ink ejection by generating a mist or a satellite, or by curving the flight path of an ink droplet.
Since no damper element for positively attenuating the pressure wave is present in the pressure chamber 203, it takes a time until the pressure wave is satisfactorily attenuated. Consequently, a required time interval to a next ink droplet ejection is long, hindering the high frequency driving of the piezoelectric vibrator.


An ultra-high pressure mercury lamp in which the tungsten comprising the electrodes is prevented from spraying during starting and operation, and blackening on the inside wall of the arc tube is prevented is achieved in that at least one of the electrodes has an axial part which is made essentially of tungsten and a starting part which is made essentially of tungsten, at least one of the axial part and of the starting part containing an electron emission material with a smaller work function than tungsten such that the value of S/A in mm2/% by weight is in the range 1≦S/A≦1×104, S in mm2 designating the surface area of the part of the electrode projecting into the arc tube containing the electron emission material and A in % by weight indicating the concentration of the electron emission material in this part.

1. Field of the Invention
The invention relates to a discharge lamp which is used for a liquid crystal display device and for a projector device, such as a DLP (digital light processor) or the like using a DMD (digital micro-mirror device). The invention relates especially to an ultra-high pressure mercury lamp in which the arc tube is filled with at least 0.15 mg/mm3 of mercury and in which the mercury vapor pressure during operation is at least 150 atm.
2. Description of the Prior Art
In a projector device of the projection type which includes a liquid crystal projector, DLP or the like using a DMD, there is a need for uniform illumination of images onto a rectangular screen, moreover with adequate color rendering. Therefore, the light source is a metal halide lamp filled with mercury and a metal halide. Recently, these metal halide lamps have been becoming smaller and smaller, and more and more often point light sources are being produced. In practice, they are used with extremely small distances between the electrodes.
Against this background, lamps with an extremely high mercury vapor pressure in operation, for example, with at least 150 atm, have recently been suggested instead of metal halide lamps. This increase of the mercury vapor pressure is designed to reduce broadening of the arc (the arc is compressed), and at the same time, to greatly increase the light intensity. Such an ultra-high pressure mercury lamp is disclosed, for example, in Japanese patent application publication JP-A-HEI 2-148561 which corresponds to U.S. Pat. No. 5,109,181 and in Japanese patent application JP-A-HEI 6-52830 which corresponds to U.S. Pat. No. 5,497,049.
Such an ultra-high pressure mercury lamp often has the disadvantage that blackening of the inside wall of the arc tube reduces the light transmittance. This is a result of the high operating temperature of the electrodes and frequent spraying of the tungsten electrode material during operation causing tungsten to be deposited on the inside wall of the bulb.
Therefore, the above described publications describe that the arc tube, which has a spherical light emitting part in its middle area, is filled with a given amount of halogen gas, and that blackening in the arc tube is prevented by carrying out the halogen cycle.
On the other hand, in the above described ultra-high pressure mercury lamp, there are also many cases in which the tungsten comprising the electrodes sprays during start-up. It can be imagined that this is caused by the following.
Normal operation of the ultra-high pressure mercury lamp takes place such that, at the start of operation, a glow discharge is formed in which the cathode constitutes the starting point, that the discharge starting point passes to the cathode tip when a high temperature state of the electrodes is reached by a glow discharge, and that it passes into rated operation due to the hot arc discharge.
However, since in this glow discharge the starting voltage (the voltage necessary for starting) is high, the tungsten sprays easily due to the fact that vigorous ion sputtering and thermal shocks are applied to the electrodes. This spraying of the tungsten leads directly to blackening of the arc tube, since the halogen cycle is inactive during starting. Therefore, spraying of the tungsten is regarded as more disadvantageous in start-up than in operation.


A developing device is provided. The developing device includes a developer carrier, a regulator, a first developer storing chamber, a plurality of conveyers disposed within the first developer storing chamber, a second developer storing chamber in communication with the first developer storing chamber, and a supply member disposed within the second developer storing chamber. The developer carrier carries developer on its surface and supplies developer to a latent image carrier carrying a latent image. The regulator regulates the thickness of developer on the surface of the developer carrier. The first developer storing chamber stores developer separated from the developer carrier by the regulator and is to be supplied with fresh developer. Each of the plurality of conveyers coveys developer in a different conveyance direction. The second developer storing chamber is to be supplied with developer from the first developer storing chamber. The supply member supplies developer to the developer carrier.

1. Technical Field
The present disclosure relates to a developing device for use in image forming apparatuses such as copier, printer, and facsimile machine; and a process cartridge and an image forming apparatus using the developing device.
2. Description of the Related Art
Image forming apparatus, such as copier, printer, facsimile machine, and combined machine thereof, generally includes a developing device that supplies developer to a latent image carrier such as photosensitive drum. The developing device generally includes a developer carrier, such as developing roller, that supplies developer to the latent image carrier by contact therewith; a supply member, such as supply roller, that supplies developer to the developer carrier; and a regulator, such as regulating blade or regulating roller, that regulates the thickness of the developer deposited on the surface of the developer carrier. As the supply member and the developer carrier supply the developer stored in the developing device to the latent image carrier, a latent image on the latent image carrier is developed.

Developing device, process cartridge, and image forming apparatus


Apparatus for inspecting containers that includes an inspection head positioned for rotation about a fixed axis adjacent to a container under inspection. A light source and a camera are carried by the head for directing illumination energy onto the container and receiving energy from the container after interaction with the container. The camera is connected to interface electronics for controlling camera operation and receiving data signals from the camera. The light source, camera and interface electronics are mounted on the head and rotate continuously, with the light source and interface electronics being connected by optical commutation to external control devices.

Conventional technology for mass production of glass or plastic containers involves forming the containers in a multiplicity of molds. Various types of faults or checks, termed "variations" in the art, may occur. Variations that may affect commercial acceptability of the containers are called "commercial variations." It has heretofore been proposed to employ optical scanning techniques for inspecting such containers for variations that affect optical transmission characteristics of the containers. In U.S. Pat. Nos. 4,378,493, 4,378,494 and 4,378,495, all assigned to the assignee hereof, there are disclosed methods and apparatus in which glass containers are conveyed through a plurality of stations where they are physically and optically inspected. At one inspection station, a glass container is held in vertical orientation and rotated about its vertical axis. An illumination source directs diffused light energy through the container sidewall. A camera, which includes a plurality of light sensitive elements or pixels oriented in a linear array parallel to the vertical axis of rotation, is positioned to view light transmitted through a vertical strip of the container sidewall. The output of each pixel is sampled at increments of container rotation, and event signals are generated when adjacent pixel signals differ by more than a preselected threshold level. An appropriate reject signal is produced and the rejected container is sorted from the conveyor line.
U.S. Pat. No. 4,701,612, assigned to the assignee hereof, discloses a method and apparatus for inspecting the finish of transparent containers, particularly glass containers, that include facility for directing diffused light energy laterally through the container finish as the container is rotated about its central axis. A camera includes a plurality of light sensitive elements or pixels disposed in a linear array angulated with respect to the container axis and coplanar therewith to view the external and internal finish wall surfaces, the latter through the open container mouth. Individual elements of the camera linear array are sampled by an information processor at increments of container rotation, and corresponding data indicative of light intensity at each element is stored in an array memory as a combined function of element number and scan increment. Such data is compared, following completion of container rotation, to standard data indicative of an acceptable container finish, and a reject signal is generated if such comparison exceeds an operator-adjustable threshold.
U.S. Pat. No. 4,945,228, assigned to the assignee hereof, discloses a system for inspecting the finish of a container by directing light energy downwardly onto the container finish as the container is rotated, and receiving reflections from the container finish as a function of its structural characteristics and variations. A light source is positioned to direct light energy onto the container sealing surface as the container is held in stationary position and rotated about its central axis. A camera includes an array of light sensitive elements positioned and oriented with respect to the container axis of rotation to receive light energy reflected by the sealing surface. The camera array is scanned at increments of container rotation to develop information indicative of light intensity at each array element as a function of such increments, and commercial variations at the container sealing surface are detected as a function of such information.
U.S. Pat. No. 4,958,223, also assigned to the assignee hereof, discloses apparatus for inspecting the finish of a container as the container is rotated about its central axis. A light source is positioned to direct diffused light energy onto the container finish, and a camera is positioned across the axis of the container from the light source. The camera comprises multiple arrays of light sensitive elements positioned with respect to the camera focusing elements on a common optical plane opposed to the light source to receive non-overlapping images of the container finish spaced from each other laterally of the container axis. Information processing electronics are coupled to the camera arrays for indicating optical characteristics of the container finish as differing functions of light intensity incident on the elements of each array.
Systems of the type disclosed in the noted patents have enjoyed substantial commercial success in conjunction with cylindrical containers that are symmetrical about their axes, but are not as well adapted for use in conjunction with non-circular containers such as salad dressing bottles. A general object of the present invention is to provide an apparatus and method for inspecting containers that are adapted to operate in conjunction with containers of any shape, including both round and non-round containers, and containers of any size or geometry. Another object of the present invention is to provide an apparatus and method of the described character that are adapted for inspecting any portion of a container--i.e., either the container body, the container finish or both.

Apparatus for inspecting containers having a dual optical transmission means, a dual light sensing means and a rotating head


This invention locally controls the pitch of speech and audio signals. The invention is based on a seamless time scale modification (S-TSM) scheme connected to a synchronized sampling rate converter that switches between different time scale factors in a seamless manner and controls pitch during playback in a nearly continuous way.

The prior art includes a variety of techniques and algorithms for improving the quality of digitally recorded and transmitted audio data. These techniques include altering audio pitch.
One prior art technique achieves pitch shifting by seamless time-scale modification (TSM) and restoration of the original time scale through sampling rate conversion. Pitch shifters embedded in karaoke systems use this principle permitting adjustment of the key of a song accompaniment to the singer's voice. Previous approaches to pitch conversion generally employ either: constant pitch shift of the entire signal as seen in common key-shifting algorithms; or complex algorithms that rely on manually labeled databases, speech production models and/or frequency domain processing.

Local pitch control based on seamless time scale modification and synchronized sampling rate conversion


This disclosure describes techniques and mechanisms for providing hybrid cloud services for enterprise fabric. The techniques include enhancing an on-demand protocol (e.g., such as LISP) and allowing simplified security and/or firewall service insertion for datacenter servers providing those services. Accordingly, the techniques described herein provide hybrid cloud services that work in disaggregated, distributed, and consistent way, while avoiding complex datacenter network devices (e.g., such running overlay on TOR), replacing and moving the functionality to on demand protocol enabled servers, which intelligently receive the required mappings as well as registers and publishes the service information to intelligently interact with the network.

Computer networks are generally a group of computers or other devices that are communicatively connected and use one or more communication protocols to exchange data, such as by using packet switching. For instance, computer networking can refer to connected computing devices (such as laptops, desktops, servers, smartphones, and tablets) as well as an ever-expanding array of Internet-of-Things (IoT) devices (such as cameras, door locks, doorbells, refrigerators, audio/visual systems, thermostats, and various sensors) that communicate with one another. Modern-day networks deliver various types of network architectures, such as Local-Area Networks (LANs) that are in one physical location such as a building, Wide-Area Networks (WANs) that extend over a large geographic area to connect individual users or LANs, Enterprise Networks that are built for a large organization, Internet Service Provider (ISP) Networks that operate WANs to provide connectivity to individual users or enterprises, software-defined networks (SDNs), wireless networks, core networks, cloud networks, and so forth.
These networks often include specialized network devices to communicate packets representing various data from device-to-device, such as switches, routers, servers, access points, and so forth. Each of these devices is designed and configured to perform different networking functions. For instance, switches act as controllers that allow devices in a network to communicate with each other. Routers connect multiple networks together, and also connect computers on those networks to the Internet, by acting as a dispatcher in networks by analyzing data being sent across a network and choosing an optimal route for the data to travel. Access points act like amplifiers for a network and serve to extend the bandwidth provided by routers so that the network can support many devices located further distances from each other.
In recent years, enterprise services have increasingly moved to the cloud. Further, growing numbers of enterprise devices connect using overlay based new software defined access (SDA) or software defined network (SDN) architecture need a uniform way of accessing hybrid cloud services (from both private cloud as well as public cloud at the same time). Traditionally, datacenter (DC) servers providing enterprise services usually use a Top-Of-Rack, leaf (TOR) switch to connect to aggregation switches (e.g., spine). Though TOR architecture reduces the cabling requirement and provide faster access, its increases the rack space, cooling requirements and cost/complexity due to the increased switching devices. While datacenter End-Of-Row (EOR) architecture does not require access switches, it increases the wiring requirements and reduces access efficiency. Accordingly, there exists a need to simplify services and server's connectivity without losing access efficiency to apply hybrid cloud services in consistent manner.

Hybrid cloud services for enterprise fabric


A method and a system for measuring a distance from a reference point to an object are provided. The method comprises the following steps. At least one image of an object is captured through a lens comprising a phase mask composed of a parallel plate and a wedge prism. At least two corresponding regions of interest (ROI) are obtained from the images. The regions of interest correspond to identical portions of the object. The relative coordinates between corresponding locations within the corresponding regions of interest is measured. The distance is calculated according to the relative coordinates.

Accompanying advancements in technologies, various distance measuring devices and methods have been invented. A simple method for measuring a distance from a reference point to an object may be to roll a wheel from the reference point to the object and calculate the number of rotating times of the wheel times the perimeter of the wheel.
Or, a measuring device may emit an infrared ray toward an object and receive the reflected infrared ray for evaluating the distance by recording the time lap between the emitting and the receiving of the infrared ray. Alternatively, the phase of a modulated light beam can be measured to provide the distance information. Such devices use a technology called "Time Of Flight". They suffer from noise created by strong reflecting objects and many can't be used in natural daylight. Those measuring devices and methods are limited to be used in some particular environments. Other devices based on stereo matching can be used under natural light and outdoors but require intensive computations. There is a need for a new device and method for measuring distances both in and outdoors, and with less intensive computations.

Method and system for measuring distance

INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE


The present invention includes forming a pad oxide layer on a substrate. A silicon nitride layer is deposited on the pad oxide. Then, an etching process is used to etch the silicon nitride layer, pad oxide. Subsequently, a silicon oxynitride layer is formed on the substrate. An undoped polysilicon layer is deposited on the silicon nitride layer and silicon oxynitride layer. Subsequently, polysilicon side wall spacers are formed. Then, the silicon nitride layer is removed to expose the pad oxide. Then, a blanket ion implantation is carried out to implant dopant into the side wall spacers, and through the pad oxide or the silicon oxynitride layer into the substrate. An oxide layer is deposited on the polysilicon side wall spacers. Then, a chemical mechanical polishing (CMP) is performed for planarization. A further silicon oxynitride layer is grown at the top of the polysilicon side wall spacers. Next, a doped polysilicon layer is formed on the oxide, polysilicon side wall spacers as word line.

The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs. Different types of devices have been developed for specific applications requirements in each of these segments. These parts have been developed with a focus on the high endurance and high speed requirements.
The basic technologies used to manufacture electrically programmable ROMs all utilize to some extent Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-silicon dioxide interface and into the oxide conduction band. The thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide to silicon nitride interface and remain trapped there since the materials are high quality insulators.
Take the EEPROM as an example, in programming mode, a negative voltage is applied to the source and drain while the substrate and gate are grounded. The potential at the central portion of the channel became almost the same as that of the drain and source so that tunneling electrons move from the silicon to the nitride through the thin oxide layer and the electrons are trapped in the nitride. In the mode of erasing, electrons are emitted from the traps in the nitride by applying a negative voltage to the gate electrode while the source and the drain are grounded.
Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistor are used for the bit lines. Cross point array technology has been disclosed. The self-aligned source and drain will allow this device to be optimized even further for programming speed. See "A New Self-Aligned Planar Cell for Ultra High Density EPROMs, A. T. Mitchellx, IEDM, Tech. pp. 548-553, 1987". Bergemont proposed another cell array for high density flash EEPROM, which can be seen in "NOR Virtual Ground (NVG)- A New Scaling Concept for Very High Density FLASH EEPROM and its Implemntation in a 0.5 .mu.m Process, A Bergemont, IEEE, pp. 15-18, 1993". This cell structure is introduced for scaling down the size of the devices to fabricate high density EEPROMs. In the flash array schematic, one metal bit line is shared between two columns of cells. The NVG array uses select devices at the top and bottom of each array block. The metal bit lines are connected through contacts to every other diffusion bit line. Another prior art that relates to the field is the article "A 0.67 um2 Self-Aligned Shallow Trench Isolation Cell (SA-STI CELL) for 3V-only 256 Mbit EEPROMs, S. Aritome, IEEE, pp. 61-64, 1994". Aritome proposed a NAND structure EEPROM that reduces the cell size without scaling of the device dimension.
Typically, the high density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Further, it can be used to replace magnetic disk memory. However, it is difficult to make the sub-0.1 .mu.m nonvolatile memory by using the current lithography technology.

Method to form high density NAND structure nonvolatile memories


For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.

The present invention is directed, in general, to processors and, more particularly, to rounding denormalized numbers in a pipelined floating point unit (FPU) without pipeline stalls.
The ever-growing requirement for high performance computers demands that computer hardware architectures maximize software performance. Conventional computer architectures are made up of three primary components: (1) a processor, (2) a system memory and (3) one or more input/output devices. The processor controls the system memory and the input/output (xe2x80x9cI/Oxe2x80x9d) devices. The system memory stores not only data, but also instructions that the processor is capable of retrieving and executing to cause the computer to perform one or more desired processes or functions. The I/O devices are operative to interact with a user through a graphical user interface (xe2x80x9cGUIxe2x80x9d) (such as provided by Microsoft Windows(trademark) or IBM OS/2(trademark)), a network portal device, a printer, a mouse or other conventional device for facilitating interaction between the user and the computer.
Over the years, the quest for ever-increasing processing speeds has followed different directions. One approach to improve computer performance is to increase the rate of the clock that drives the processor. As the clock rate increases, however, the processor""s power consumption and temperature also increase. Increased power consumption is expensive and high circuit temperatures may damage the processor. Further, the processor clock rate may not increase beyond a threshold physical speed at which signals may traverse the processor. Simply stated, there is a practical maximum to the clock rate that is acceptable to conventional processors.
An alternate approach to improve computer performance is to increase the number of instructions executed per clock cycle by the processor (xe2x80x9cprocessor throughputxe2x80x9d). One technique for increasing processor throughput is pipelining, which calls for the processor to be divided into separate processing stages (collectively termed a xe2x80x9cpipelinexe2x80x9d). Instructions are processed in an xe2x80x9cassembly linexe2x80x9d fashion in the processing stages. Each processing stage is optimized to perform a particular processing function, thereby causing the processor as a whole to become faster.
xe2x80x9cSuperpipeliningxe2x80x9d extends the pipelining concept further by allowing the simultaneous processing of multiple instructions in the pipeline. Consider, as an example, a processor in which each instruction executes in six stages, each stage requiring a single clock cycle to perform its function. Six separate instructions can therefore be processed concurrently in the pipeline; i.e., the processing of one instruction is completed during each clock cycle. The instruction throughput of an n-stage pipelined architecture is therefore, in theory, n times greater than the throughput of a non-pipelined architecture capable of completing only one instruction every n clock cycles.
Another technique for increasing overall processor speed is xe2x80x9csuperscalarxe2x80x9d processing. Superscalar processing calls for multiple instructions to be processed per clock cycle. Assuming that instructions are independent of one another (the execution of each instruction does not depend upon the execution of any other instruction), processor throughput is increased in proportion to the number of instructions processed per clock cycle (xe2x80x9cdegree of scalabilityxe2x80x9d). If, for example, a particular processor architecture is superscalar to degree three (i.e., three instructions are processed during each clock cycle), the instruction throughput of the processor is theoretically tripled.
These techniques are not mutually exclusive; processors may be both superpipelined and superscalar. However, operation of such processors in practice is often far from ideal, as instructions tend to depend upon one another and are also often not executed efficiently within the pipeline stages. In actual operation, instructions often require varying amounts of processor resources, creating interruptions (xe2x80x9cbubblesxe2x80x9d or xe2x80x9cstallsxe2x80x9d) in the flow of instructions through the pipeline. Consequently, while superpipelining and superscalar techniques do increase throughput, the actual throughput of the processor ultimately depends upon the particular instructions processed during a given period of time and the particular implementation of the processor""s architecture.
The speed at which a processor can perform a desired task is also a function of the number of instructions required to code the task. A processor may require one or many clock cycles to execute a particular instruction. Thus, in order to enhance the speed at which a processor can perform a desired task, both the number of instructions used to code the task as well as the number of clock cycles required to execute each instruction should be minimized.
Statistically, certain instructions are executed more frequently than others are. If the design of a processor is optimized to rapidly process the instructions which occur most frequently, then the overall throughput of the processor can be increased. Unfortunately, the optimization of a processor for certain frequent instructions is usually obtained only at the expense of other less frequent instructions, or requires additional circuitry, which increases the size of the processor.
As computer programs have become increasingly more graphic-oriented, processors have had to deal more and more with the operations on numbers in floating point notation. Thus, to enhance the throughput of a processor that must generate, for example, data necessary to represent graphical images, it is desirable to optimize the processor to efficiently process numbers in floating point notation.
One aspect of operations involving numbers in floating point notation is xe2x80x9croundingxe2x80x9d, which is basically the increasing or decreasing of the least significant bit of a floating point operand to conform the operand to a desired degree of precision; the IEEE Standard 754 defines the formats for various levels of precision. In an FPU, rounding operations may be required in combination with a floating-point adder unit (xe2x80x9cFAUxe2x80x9d), a floating-point multiplication unit (xe2x80x9cFMUxe2x80x9d), and a store unit. To simplify the design and fabrication of the FPU, it is desirable to employ a rounding unit that is xe2x80x9cmodularizedxe2x80x9d, i.e., which can be universally employed, without modification, in combination with a FAU, FMU, or floating-point store unit.
Implementation of the IEEE 754 standard for rounding has always posed a challenge for FPU designers. The rounding process is complicated by the fact that the Intel x87 architecture supports denormal numbers and gradual underflow. Rounding for numbers in the subnormal range is a function of the method by which the numbers are stored in the machine; storing denormal numbers in the normal format helps to eliminate a normalization step that would otherwise be required when such numbers are operated upon, but poses a problem in the rounding step due to the variable location of the decimal point.
Therefore, what is needed in the art is a system and method for rounding denormalized numbers and a processor employing the same. Preferably, the system or method is embodied in a modular circuit that is suitably operative in combination with a FAU, a FMU, and a floating-point store unit.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide rounding logic capable of handling denormalized numbers and a processor employing the same.
In the attainment of the above primary object, the present invention provides, for use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.
The present invention therefore introduces the broad concept of rounding logic capable of dealing with denormalized numbers. This can be accomplished by creating a mask that takes into account each number""s denormalization and employs the mask in logical operations to determine the L, R and S bits necessary to determine rounding.
The present invention can preferably be embodied as a pipelined process, resulting in relatively fast operation. Further, an embodiment to be illustrated and described contains logic sufficient to render a rounder that may be generically employed with an adder, a multiplier or a load unit. In this sense, the present invention can provide a modular, xe2x80x9cuniversalxe2x80x9d rounder, perhaps for use in multiple locations in a single processor.
For purposes of the present invention, xe2x80x9can extent to which the denormalized number is denormalxe2x80x9d is defined as the degree to which (or, synonymously, quantity of bits by which) the denormalized number is misaligned. In one embodiment of the present invention, the extent may be determined with reference to the denormalized number""s exponent. Knowing the extent of denormalization allows an appropriate bit mask to be created that defines the dividing line between (1) the fraction portion of the denormalized number and (2) bits that are too insignificant to be contained in the fraction portion. While the latter bits fall outside of the fraction portion, they nonetheless play a significant role in rounding according to the IEEE 754 standard, as will be set forth in detail below.
In one embodiment of the present invention, the combinatorial logic generates the L bit by: (1) initially bitwise ANDing the bit mask and an inverted, 1-bit left-shifted version of the bit mask to yield a first intermediate bit pattern, (2) next bitwise ANDing the fraction portion and the first intermediate bit pattern to yield a second intermediate bit pattern and (3) next ORing bits in the second intermediate bit pattern to yield the L bit.
In one embodiment of the present invention, the combinatorial logic generates the R bit by: (1) initially bitwise ANDing an inverted version of the bit mask and a 1-bit right-shifted version of the bit mask to yield a first intermediate bit pattern, (2) next bitwise ANDing the fraction portion and the first intermediate bit pattern to yield a second intermediate bit pattern and (3) next ORing bits in the second intermediate bit pattern to yield the R bit.
In one embodiment of the present invention, the combinatorial logic generates the S bit by: (1) initially bitwise ANDing the fraction portion and an inverted, 1-bit right-shifted version of the bit mask to yield an intermediate bit pattern and (2) next ORing bits in the intermediate bit pattern to yield the S bit.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls


Methods, systems, and apparatus, including computer-readable media, for verified boot and key rotation. In some implementations, a device extracts a public key from a secure data storage area of the device. The device extracts a first certificate for an intermediate key and a second certificate for a signing key, the first certificate and the second certificate being extracted from a system image. The device verifies a signature of the first certificate using the public key. After verifying the signature of the first certificate, the device verifies the second certificate using a public key in the first certificate. In response to verifying the second certificate, the device loads the system image during a boot process of the device.

The present specification relates to security for electronic devices, including verified boot and key rotation.
Computing devices are generally initialized during a boot process that loads an operating system and other software modules. If insecure or malicious software is loaded during the boot process, a user's device and data may be at risk. Accordingly, techniques to verify the integrity of software during boot are needed.


A method to construct a transaction serialization order based on parallel or distributed database log files that connects the log files into a network and merges the network into a sequence. Only vote symbols and commit symbols are considered in the construction and a protocol of a transaction's vote appearing before a transaction's commit is enforced. The log files are connected by making links between commit symbols of the same transactions in different log files. The method identifies ambiguities in the orders of the individual log files, called commit symbol cycles, and resolves them by breaking an unsupported segment of the cycle and sliding the segment's forwardmost commit symbol backward to a position immediately prior to the first commit symbol on that segment. By doing so, the serialization implication of an individual log file may be changed, but the overall serialization implication of the database remains intact. Using an iterative process, this method can order the log files in one pass-through.

1. Field of the Invention
This invention is related to computers and computer systems, and in particular to database management systems (DBMS).
2. Description of the Related Art
A database management system keeps track of changes made to a database during its lifetime. These changes are called "transactions" and each transaction is made up of operations such as insert, update, and delete. The operations are recorded in a "log file" in the order in which the operations are performed in the system. This log file may contain entries of operations performed from the time the database was created or from the time the database was last backed up until the present.
With the increasing emphasis in the database community on historical data, data warehousing, and updating remote or warehouse copies of a database, there is a need to develop a global log file that, when applied to a copy of a database, recreates the results of changes to the original database. As part of that task, it is necessary to first reconstruct the original order of transactions. For serial database systems, the transaction order can easily be inferred by examining the log files for each transaction; creating a global log file in that case is trivial. However, in parallel or distributed database systems, which consist of nodes each of which performs a part of a transaction, creating a global log file is much more complex. In such systems, after all the nodes have finished processing their parts of the transaction, the results are put together to complete the transaction. Each node has its own log file associated with it, often called a "local log file," in which all of the operations performed by the node are recorded in the order completed. On a "share-nothing" model of a parallel or distributed database system, each node operates on a partition of the database; the problem of constructing a global transaction order is especially complex in this case because any data item in the database belongs to exactly one partition and thus to exactly one node. FIG. 1 depicts the architecture of a share-nothing parallel database system in which the network 9 is made up of processing nodes 1,2,3,4 each respectively associated with partitions 5,6,7,8.
In order to better regulate the management of data, parallel or distributed database systems often operate under two protocols. The first is a "two-phase commit protocol," involving a transaction coordinator on some node and transaction participants on that node and others, in which each participant signals to the coordinator when the participant has completed its part of the transaction (first phase), and the coordinator signals to the participants whether the transaction should be executed or not (second phase). Specifically, the coordinator decides on which nodes lie the data items needed to complete the transaction and assigns a participant on each node to complete the operations necessary for each node. When each participant completes its part of the transaction, it sends a "vote" to the coordinator telling the coordinator that it has completed its work and requesting the coordinator to decide whether it should commit to the work it has done. After the coordinator receives a vote from all of the participants, it sends either a "commit" or an "abort" to each participant. The participants then commit to or abort their part of the transaction accordingly. For any transaction i, V.sub.i denotes its vote operation and C.sub.i denotes its commit operation. For these types of database systems, the local log files record the votes, commits, and aborts as well as the inserts, updates, and deletes. Thus, the two-phase commit protocol requires that in any node, the vote for a transaction will necessarily precede that transaction's commit or abort.
The second protocol under which these database systems operate is a "strict two-phase locking protocol" which controls and locks resources needed to complete database transactions. In general, a locking protocol requires the DBMS to lock resources needed to complete a transaction so that only that transaction can access the resources at any one time. A "two-phase locking protocol," consisting of a "locking phase" and a "releasing phase," restricts the acquisition and release of locks in such a way that all the locks must first be acquired for the transaction before any lock is released, and, once a lock is released, no other locks can be acquired for that transaction. A more stringent requirement results in the "strict two-phase locking protocol" where all the locks must first be acquired for the transaction and no locks are released until the commit or abort is processed for that transaction. In a sharenothing model of a parallel or distributed database system, each node independently abides by the strict two-phase locking protocol and thus requires that when two transactions i and j need to access the same resources on that node, the transaction that acquires the locks first will be committed to or aborted before the other transaction. Thus, if transaction i acquires the locks first, in the log file for that node the commit or the abort of i will precede the commit or abort of j.
In constructing a global transaction order, a set of transactions can be arranged into a "serialization order" which can either be a total order (a sequence relating any two transactions in the set) or a partial order (a sequence in which some transactions may be related to others but not necessarily). The term "serialization order" can also be used to describe the order in which two transactions i and j appear in the total or partial order. Related to "serialization order" is a "serialization requirement" which takes effect when a DBMS performs its operations so that it is only meaningful to view one transaction as preceding another. This requirement is related to the strict two-phase locking protocol described above in that if two transactions need to access a common data item, the database system will grant the lock to the data item first to one transaction and then to the other. In such a case there is a "serialization requirement" between the two transactions that "requires" the transaction that acquired the lock first to be ordered before the other transaction. Finally, each log file has a "serialization implication" which is made up of information regarding the serialization requirement carried by the system. This information includes the records of the sequence and type of operations performed on its associated node, together with the semantics of the system in which the operations are executed.
The combination of all the local log files in the system reflects the history of the entire database. In constructing a global order at some later time, only the local log files exist. The most obvious solutions to this delayed ordering problem are to examine either the timestamp information for each transaction or the data items accessed by each transaction, information that may be recorded in the local log files. However, in practice these methods do not work very well because global timestamps are not always available in every DBMS and examining data items accessed by each transaction involves too many log entries and a complex analysis.
In situations such as these when timestamp information or information relating to each data item is not available, one method used to construct a global order is to examine the order of commit entries in the local log files. However, the commit entries alone do not provide enough information for constructing a global transaction order. In a parallel or distributed database system, a database node records its commit entries in its log file in the order it processes them, not in the order imposed by the system serialization requirement. Thus, for two transactions i and j whose commit entries are recorded in the same local log file, it is possible that (1) i must be serialized before j; (2) j must be serialized before i; or (3) no serialization requirement exists between i and j. In addition, the commit entries of two transactions have several properties that may lead to an ambiguous ordering. First, the order of two commit entries in the log file does not necessarily imply their serialization requirement because the commit entry of one transaction may precede that of another in some log file simply because it is processed earlier than the other, and the two transactions may not access any common data item at all. Second, two different log files may record the commit entries of the same two transactions in different orders. Thus, examining the positions of commit entries in the log files alone does not provide enough information to construct a global serialization order.
This lack of information creates local log files that are often ambiguous, and it is difficult to infer a global order merely by examining the order of the individual commit operations in each local log file. Up to now there been no method to construct a global order from local log files where the construction is performed some time after the log files have been created and can be completed on the full log file in one pass-through.

Constructing a transaction serialization order based on parallel or distributed database log files


A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least one master device to use the bus system to access a slave device are received, and the priority values of all requesting master devices are compared. If a sole requesting master device has the highest priority value access to the respective slave device is granted to that master device. If a plurality of requesting master devices have the same highest priority value access is successively granted to the requesting master devices having the same highest priority value on the basis of the address allocation of the master devices.

The bus system connects the various units in a computer system (memory, CPU, peripheral units) to one another and conveys the data interchange between them. The components of the electronic data processing system use a common transport path, the bus system(s), to which they are connected in parallel.
The coordination of the transmission, i.e. the selection of sender and receiver, the respective access and also the time synchronization are controlled by means of control signals. In the simplest case, bus control is performed by a sole bus master.
Basic execution of a data transfer on the respective bus system with a sole master which controls the access occurs essentially in three steps.
First, the master device provides an address for selecting a communication partner on the address bus in the bus system. The selected partner identifies this and goes into standby. By activating a control signal, for example for a read or write access operation, the master device determines the direction of transmission. The sender or slave device determined in this manner places the data onto the data bus. The master device performs the data transfer and signals that data transfer has concluded by deactivating the read or write signal. This returns the bus system to the initial state and means that it is ready for a subsequent transfer.
In "multimaster bus systems", a plurality of master devices are authorized, in principle independently of one another, to use the bus system to address slave devices. To avoid collisions and disturbances during access via the bus system, a bus access rights controller needs to be provided in multimaster bus systems. A bus access rights controller normally uses a selection method (arbitration) to grant combinations of master devices and slave devices the respective access via the bus system.
Particularly in whole systems today which are integrated on a single semiconductor chip, "systems on a chip", with multiple masters, it is desirable for the arbitration to be as flexible as possible. Only in this way is it possible to use the appropriate selection method which best matches a target application, for example an engine controller, an antilocking system, a signal processor in mobile radio applications etc.
On the basis of the prior art, two particular selection methods for bus access rights control are in use. On the basis of the priority selection method, all master devices are allocated a priority value. In the event of simultaneous access requests from various master devices, the arbitration controller or bus access rights controller always selects the requesting master device which has the highest priority for access to the bus system. Priority-controlled bus access allocation guarantees that urgent tasks, that is to say combinations of master and slave devices, are handled with priority. However, this may result in processes which have low priority never being executed. This is called starvation of a process.
On the basis of the second important access rights allocation method, the round robin method, all processes or bus access requests from master devices are executed in a fixed order. The round robin method therefore ensures that all active processes or requests from master devices to access slave devices via the bus system are assigned a guaranteed bus access time. In the case of the round robin method, however, all bus access operations, or requests to use the bus system for access, also have the same very long waiting time, which results from the maximum latencies of all the simultaneously active master devices. This means that bus system access which is more frequent or more important in a respective application is disadvantaged and the speed of the whole system on the semiconductor chip with an on-chip bus system and multiple masters is slowed.
Stipulating a single arbitration method or method for allocating bus access rights in multimaster bus systems has the fundamental drawback that the arbitration chosen in this manner cannot be optimum for all applications or target applications for the respective system on a chip.

Method and apparatus for allocating bus access rights in multimaster bus systems


A magnet coil for magnetic Czochralski single crystal growth includes: a first coil, a second coil, and an auxiliary coil arranged between the first coil and the second coil. A distance between the first coil and a first edge of the auxiliary coil close to the first coil is equal to a distance between the second coil and a second edge of the auxiliary coil close to the second coil. The auxiliary coil, the first coil and the second coil have a common central axis. When being energized, a direction of a current in the first coil is opposite to a direction of a current in the second coil, and a magnetic field generated by a current in the auxiliary coil is used for enhancing a cusp magnetic field between the first coil and the second coil.

With the rapid development of the manufacturing technology of semiconductor microelectronic devices, large-scale integrated circuits and other devices, the requirement for preparing semiconductor material including single crystal silicon is higher and higher. Undesired impurities and their non-uniformity in single crystal silicon are one of the main factors which restrict the improvement of the quality of single crystal silicon. Therefore, in the single crystal silicon growth, it is important to reduce defects and impurity content of the single crystal silicon and improve the distribution uniformity of dopants and impurities such as oxygen, carbon and the like in the crystal.
The single crystal silicon growth method includes a Czochralski method and a floating zone method. Currently, single crystal silicon is typically prepared by using the Czochralski method. In the Czochralski method, a single crystal rod is pulled from a melt in a single crystal growth furnace. In the Czochralski single crystal growth, the impurities are not uniform in both macroscopic and microscopic due to the thermal convection of the melt, thereby affecting physical and chemical properties of the crystals. Therefore, suppressing the thermal convection of the melt is one of the important ways to improve the quality of the single crystal silicon.
In order to solve the above problems, the magnetic Czochralski single crystal growth technology is gradually developed. On the basis of the Czochralski method, a strong magnetic field is provided outside the single crystal growth furnace to suppress the heat convection of the melt, reduce the impurity content of the crystal and improve the longitudinal and radial impurity distribution uniformity, so that high-quality single crystal silicon is obtained.
A permanent magnetic material and a conventional electromagnet is generally used in the magnetic field generating apparatus of the traditional magnetic Czochralski single crystal growth method. This magnetic Czochralski single crystal growth method is limited by the saturation magnetization of the permanent magnetic material and the power of the conventional electromagnet, so that the generated magnetic field strength is usually not high, and the suppression effect on the thermal convection of the melt does not met the expectation. With the development of superconducting magnet technologies, more and more superconducting magnets replace conventional electromagnets. The superconducting magnet can generate a stronger magnetic field, has a more evident thermal convection suppression effect on the melt, and can be used for preparing single crystal silicon with larger size or higher quality with the Czochralski process.
The magnetic field generated by the superconducting magnet in the magnetic Czochralski single crystal growth method generally includes a cusp magnetic field, a transverse magnetic field and a longitudinal magnetic field. The suppression effect of the longitudinal magnetic field on the thermal convection of the melt is not evident and is replaced by the cusp magnetic field and the transverse magnetic field.
Since the magnetic flux of the longitudinal magnetic field and the magnetic flux of the transverse magnetic field are each in a single direction, the longitudinal magnetic field and the transverse magnetic field only have a suppression effect on the part of thermal convection perpendicular to their respective magnetic fluxes, but have no suppression effect on the thermal convection parallel to their respective magnetic fluxes, and the impurity content and uniformity of the single crystal silicon are affected.
In order to further improve the quality of the single crystal, a cusp magnetic field is proposed. The cusp magnetic field includes a divergent magnetic field with radial and longitudinal components, and can effectively suppress thermal convection and forced convection generated by relative rotation of the single crystal and the crucible, thereby further improving the quality of the crystalline silicon. As the size of single crystal silicon increases, the demand for magnetic field strength increases, so that the weight and cost of the traditional magnet for generating the cusp magnetic field increase.

Magnet coil for magnetic czochralski single crystal growth and magnetic czochralski single crystal growth method

Suzhou Bama Superconductive Technology Co., Ltd.


A whistle designed particularly for outdoor use, such as in hiking or camping, wherein opposite sidewalls of the whistle are provided with openings having inwardly directed flanges so that closure devices may be press fitted therein and wherein the closure devices preferably comprise a compass, a thermometer or a molded disk, but can also comprise other environmental instruments.

There are many uses of a whistle when people are using the outdoors for various reasons, such as hiking or camping. The whistle can be used by one group to indicate its position to another group. In case of emergency, the whistle can be used to signify a need for assistance. In some instances, a compass is desired to follow a direction to reach a desired location. Another environmental instrument desired for use in hiking and camping is a thermometer to indicate conditions that may require certain precautions. While all these environmental instruments are well known and generally available, they are generally carried as separate environmental instruments and can be misplaced or lost.

Combined whistle and environmental instruments

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The invention relates to a shock absorber for a landing gear leg, the shock absorber being of the type comprising a cylinder and a sliding rod, and including a disk that delimits a lower hydraulic fluid chamber which communicates via a diaphragm with an upper hydraulic fluid chamber adjacent to a pressurized gas chamber formed in the top portion of the cylinder. According to the invention, the sliding rod 102 is implemented in telescopic form, having an outer rod 131 and an inner rod 132 which bears directly against an intermediate partition 112 constituting the above-mentioned disk when the shock absorber is relaxed or under static load. The shock absorber also includes a linear actuator 150.1 received in the inner rod 132, and which, when triggered, serves to extend the landing gear providing the airplane is stationary or is moving slowly on the ground. Two scissors linkages 124 and 127 are also provided for conveying structural twisting forces.

It is known that a shock absorber for an airplane landing gear leg can be implemented in the form of a cylinder and a rod that slides inside said cylinder, said rod including a bottom that delimits a lower hydraulic fluid chamber which communicates via a diaphragm with an upper hydraulic fluid chamber adjacent to a chamber containing gas under pressure and formed in the top portion of the cylinder.
In certain situations, when the airplane is stationary or moving slowly over the ground, it is desirable to be able to modify the attitude of the airplane, i.e. the inclination of its longitudinal axis.
One possible approach then consists in attempting to change the length of its nose landing gear without altering its main landing gear: if the nose landing gear can be lengthened, then the attitude desired for an airplane which is stationary or which is moving slowly on the ground can be achieved.
Under such circumstances, it is advantageous to have nose landing gear capable of being lengthened.
Nevertheless, it is necessary to avoid confusing lengthening the landing gear while the airplane is stationary or moving slowly on the ground, and lengthening the landing gear so as to enable it to run over rough ground and even to pass over obstacles that are large in size. In the latter circumstance, the idea is to change the isothermal response curve of the shock absorber (variation in shock absorber force as a function of retraction stroke), e.g. by providing a structure such that the shock absorber has a single chamber on landing, and two chambers when taxiing (after the landing gear has been lengthened), as described in the document FR-A-2 601 097.
The shock absorber described in that document thus includes a moving disk that delimits the top of a high-pressure gas chamber whose bottom is delimited by a piston whose rod passes through the moving disk, and a bottom hydraulic fluid chamber which is delimited by said piston and by the end of the sliding rod, and which is fed from a controllable source connected to the hydraulic power generator of the airplane. The structure of that shock absorber provides the desired objective, i.e. it passes freely over bumps, and as a result, such a shock absorber is unsuitable for the sole purpose of statically lengthening the landing gear when the airplane is stationary or moving slowly on the ground.
Static lengthening of the landing gear for an airplane that is stationary or that is moving slowly on the ground, consists merely in generating a force equivalent to the static load on the landing gear so as to raise the cylinder of the shock absorber relative to its sliding rod (which rod is stationary, such that lengthening the shock absorber by moving out its sliding rod causes the cylinder or cylinder portion of said shock absorber to be raised).

Shock absorber for an aircraft landing gear leg


Methods and apparatus compress data, comprising an In-phase (I) component and a Quadrature (Q) component. Statistical characteristics of the data are utilized to convert the data into a form that requires fewer bits in accordance with the statistical characteristics. The data may be further compressed by transforming the data and by modifying the transformed data in accordance with a quantization conversion table that is associated with the processed data. Additionally, redundancy may be removed from the processed data with an encoder. Subsequent processing of the compressed data may decompress the compressed data in order to approximate the original data by reversing the process for compressing the data with corresponding inverse operations. Interleaved I and Q components can be processed rather than separating the components before processing the data. The processed data type may be determined by providing metadata to retrieve the appropriate quantization table from a knowledge database.

Compression of Synthetic Aperture Radar (SAR) data may require that both magnitude and phase information be preserved. FIG. 1 shows data processing of synthetic aperture radar data according to prior art. Synthetic aperture radar data 102 are typically collected in analog-format by an antenna 101 and is converted to digital format through an Analog-to-Digital (A/D) converter 103. The raw, unprocessed data are referred to as Video Phase History (VPH) data 104, and comprise two components: In-phase (I) and Quadrature (Q). Video phase history data 104 having multiple components, such as I and Q, are typically referred as complex SAR data. Complex SAR data are essential for the generation of complex SAR applications products such as interferograms, polarimetry, and coherent change detection, in which a plurality of such images must be processed and compared.
Video phase history data 104 are then passed through a Phase History Processor (PHP) 105 where data 104 are focused in both range (corresponding to a range focusing apparatus 107) and azimuth (corresponding to an azimuth focusing apparatus 109). The output of phase history processor 105 is referred to as Single Look Complex (SLC) data 110. A detection function 111 processes SLC data 110 to form a detected image 112.
Existing complex SAR sensors collect increasingly large amounts of data. Processing the complex data information and generating resultant imagery products may utilize four to eight times the memory storage and bandwidth that is required for the detected data (I&Q). In fact, some studies suggest exponential growth in associated data throughput over the next decade. However, sensors are typically associated with on-board processors that have limited processing and storage capabilities. Moreover, collected data are often transmitted to ground stations over a radio channel having a limited frequency bandwidth. Consequently, collected data may require compression in order to store or transmit collected data within resource capabilities of data collecting apparatus. Also, a SAR compression algorithm should be robust enough to compress both VPH data 104 and SLC SAR data 110, should produce visually near-lossless magnitude image, and should cause minimal degradation in resultant products 112.
Several compression algorithms have been proposed to compress SAR data. However, while such compression algorithms generally work quite well for magnitude imagery, the compression algorithms may not efficiently compress phase information. Moreover, the phase component may be more important in carrying information about a SAR signal than the magnitude component. With SAR data 102, compression algorithms typically do not achieve compression ratios of more than ten to one without significant degradation of the phase information. Because many of the compression algorithms are typically designed for Electro/Optical (EO) imagery, the compression algorithms rely on high local data correlation to achieve good compression results and typically discard phase data prior to compression. Table 1 lists several compression algorithms discussed in the literature and provide a brief description of each.
TABLE 1Popular Alternative SAR Data Compression AlgorithmsCompression AlgorithmDescriptionBlock AdaptiveChoice of onboard dataQuantization (BAQ)compression methods dueto simplicity in codingand decoding hardware.Low compression ratiosachieved (<4:1).Vector Quantization (VQ)Codebook createdassigning a numberfor a sequence of pixels.Awkward implementationsince considerablecomplexity required incodebook formulation.Block Adaptive VectorConsists of first compressingQuantization (BAVQ)data with BAQ and thenfollowing up with VQ.Similar to BAQ.Karhunen-LoeveStatistically optimalTransform (KLT)transform for providinguncorrelated coefficients;however, computationalcost is large.Fast Fourier Transform2-D Fast Fourier TransformBAQ (FFT-BAQ)(FFT) performed on rawSAR data. Before rawdata is transformed,dynamic range for eachblock is decreasedusing a BAQ.Uniform SampledEmphasizes phaseQuantization (USQ)accuracy of selectedpoints.Flexible BAQ (FBAQ)Based on minimizingmean square error betweenoriginal and reconstructed data.Trellis-Coded Quantization (TCQ)Unique quantizer optimizationdesign. Techniques providesuperior signal to noise ratio(SNR) performance to BAQand VQ for SAR.Block Adaptive ScalarBSAQ's adaptive techniqueQuantization (BSAQ)provides some performanceimprovement.
Existing optical algorithms are inadequate for compressing complex multi-dimensional data, such as SAR data compression. For example with optical imagery, because of a human eyesight's natural high frequency roll-off, the high frequencies play a less important role than low frequencies. Also, optical imagery has high local correlation and the magnitude component is typically more important than the phase component. However, such characteristics may not be applicable to complex multi-dimensional data. Consequently, a method and apparatus that provides a large degree of compression without a significant degradation of the processed signal are beneficial in advancing the art in storing and transmitting complex multi-dimensional data. Furthermore, the quality of the processed complex multi-dimensional data is not typically visually assessable. Thus, a means for evaluating the effects of compression on the resulting processed signal is beneficial to adjusting and to evaluating the compression process.

Measurement and signature intelligence analysis and reduction technique

Science Applications International Corporation